RAA223021_V01 RENESAS | Alldatasheet
Document overview
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- PDF pages: 24
Technical content
Datasheet sections
- 1.1 Block Diagram
- 2.1 Pin Assignments
- 2.2 Pin Descriptions
- 3.1 Absolute Maximum Ratings
- 3.2 Thermal Information
- 3.3 Recommended Operating Conditions
- 3.4 Electrical Specifications
- 5.1 Constant Off-Time Mode
- 5.2 PFM Mode
- 5.3 Output Voltage Sampling
- 5.4 Soft Start-Up
- 5.5 Overload Protection
- 5.6 Short-Circuit Protection
- 7.1 Feedback Resistor Selection
- 7.2 Output Inductor Selection
- 7.3 Feedback Capacitor (CFB1) Selection
- 7.4 Output Capacitor Selection
- 7.5 Bias Capacitor Selection
- 7.6 Dummy Resistor Selection
- 7.7 Power Capability
- 7.8 PCB Layout Guidance
Features
▪ Ultra-low standby power (<20mW) ▪ No audible noise ▪ Low quiescent current (<80µA) ▪ Output voltage as low as 3.3V ▪ Low EMI with frequency dithering ▪ 7 Ld SOIC package ▪ Programmable PFM allows optimization of COUT for various standby power requirements ▪ Protection features: Short-Circuit Protection (SCP), Overload Protection (OLP), Overvoltage Protection (OVP), open feedback protection, and Over-Temperature Protection (OTP).
Applications
▪ Home appliances ▪ Home automation, IoT, and sensors ▪ Metering and Industry control ▪ Bias power Figure 1. Typical RAA223021 Buck Application Circuit
Table 1. Maximum Output Current (Maximum Ambient 85°C)
1.1 Block Diagram
Figure 2. Block Diagram of RAA223021
R16DS0074EU0102 Rev.1.02 Page 5 Dec 7, 2022 RAA223021 Datasheet 2. Pin Information
2.1 Pin Assignments
2.2 Pin Descriptions
7 Ld SOIC
Pin Number Pin Name Description
1 VCC IC supply voltage
2 FB Feedback pin
4 DRAIN Internal power MOSFET drain
5-8 SOURCE Internal power MOSFET source SOURCE SOURCE VCC FB DRAIN SOURCE SOURCE
R16DS0074EU0102 Rev.1.02 Page 6 Dec 7, 2022 RAA223021 Datasheet 3. Specifications
3.1 Absolute Maximum Ratings
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product reliability and result in failures not covered by warranty.
3.2 Thermal Information
3.3 Recommended Op erating Conditions
Parameter Minimum Maximum Unit VCC -0.3 +6.5 V VFB -0.3 +6.5 V DRAIN (to SOURCE) - 0.3 700V V Continuous Power Dissipation (TA = +25°C) 1 W ESD Rating Value Unit Human Body Model (Tested per JS-001-2017) 1.2 kV Charged Device Model (Tested per JS-002-2014) 1 kV Latch-Up (Tested per JESD78E; Class 2, Level A) 100 mA Thermal Resistance (Typical) θ JA (°C/W)[1] 1. θJA is measured in free air with the component mounted on a 1-layer test board with thermal copper 555mm2 in size and 1oz Cu (35µm) thickness. θJC (°C/W)[2] 2. For θJC, the case temperature location is taken at the package top center.
7 Ld SOIC 50 23
Parameter Minimum Maximum Unit Maximum Junction Temperature +150 °C Maximum Storage Temperature Range -60 +150 °C Pb-Free Reflow Profile See TB493 Parameter Minimum Maximum Unit Supply Voltage, V DRAIN 375 V Ambient Temperature -40 +85 °C Output Voltage 3.3 V
R16DS0074EU0102 Rev.1.02 Page 7 Dec 7, 2022 RAA223021 Datasheet
3.4 Electrical Specifications
Typical operating conditions at 25°C, VDRAIN = 100V, VCC = 5.6V, TJ = -40 to +125°C, unless otherwise specified. Parameter Symbol Test Conditions Min [1] Typ Max [1] Unit Startup and Power FET Internal VCC Startup Current I VCC_START VCC = 4V 2.5 mA Drain Leakage Current I D_LEAK VCC = 0V, VDRAIN = 325V, VFB = 2.6V 1 µA IDRAIN Bias I D_BIAS VDRAIN = 375V 10 µA Power FET Breakdown Voltage V DS(BR) TJ = 25°C 700 V Power FET On-Resistance r DS(ON) TJ = 25°C, IDS = 30mA, VCC = 5.8V 4 5.5 Ω TJ = 125°C 7 8.5 Ω VCC Supply VCC Start (Rising) V CC_START 5.6 6 6.4 V VCC when Internal Regulator Off V CC_OFF 5.6 6 6.4 V VCC (Falling) Regulator On at Startup VCC_ON 5.45 5.9 6.25 V Internal VCC On/Off Hysteresis V CC_HYS 0.10 0.15 V VCC (Fallng) Regulator On after Startup VCC_ON_SS 4.3 4.5 4.9 V VCC Undervoltage Threshold (Falling) VCC_UVLO IC stop switching 3.8 4 4.4 V VCC Shunt Regulator On (Rise) V CC_SON External VCC supply, internal shunt on 6.2 6.5 V VCC Shunt Regulator Off (Fall) V CC_SOFF External VCC supply, internal shunt off 6.1 6.45 V VCC Quiescent Current I VCC_Q VFB > 2.5V, no switching 80 125 µA VCC Current During Switching I VCC VFB < 2.5V, switching frequency = 43kHz, D = 0.15, VCC = VCC_ON + 0.1V 225 325 µA VCC Discharging Current Hiccup Timing IQVCC3 VCC discharge timing for fault hiccup delay 20 33 µA Current Sense Peak Current Limit I PK di/dt = 600mA/µs, TJ = 25°C, VCC = 5.8V 875 1100 1325 mA SCP Threshold[2] ISC_TH 1.73 A Minimum Peak Current I PKMIN VIN = 85VAC, IOUT = 0, VCC = 5.8V 158 mA Leading Edge Blank Time t LEB TJ =25°C, VCC = 5.8V 200 250 ns Feedback Feedback Voltage V FB TJ =25°C, VCC = 5.8V 2.4 2.5 2.64 V Transconductance GM I PK GM, VCC = 5.8V 22 S Feedback Undervoltage Threshold VFBUV VCC = 5.7V 1.6 1.7 1.8 V Feedback Threshold for Increased Off-Time VFB_TOFFMIN VCC = 5.0V 0.88 V Feedback Overvoltage V FBOV 2.8 3 3.35 V Timing Minimum Off-Time t OFF_MIN VCC = 5.0V 18 23 32 µs
R16DS0074EU0102 Rev.1.02 Page 8 Dec 7, 2022 RAA223021 Datasheet Maximum On-Time t ON_MAX VCC = 5.0V 11 14 18 µs Minimum Off-Time in Short-Circuit t OFFMIN_SC VCC = 5.0V 150 µs Hiccup Restart Delay t HICC CVCC = 1µF 90 ms OLP Timer t OLP fSW = 43kHz, VFB < 1.7V, VCC = 5.0V 1032 cycle Thermal Over-Temperature Threshold OTP TH 150 °C Over-Temperature Hysteresis OTP HYS 45 °C 1. Compliance to datasheet limits is as sured by one or more methods: production test, characterization, and/or design. 2. Compliance to limits is established by design. Typical operating conditions at 25°C, VDRAIN = 100V, VCC = 5.6V, TJ = -40 to +125°C, unless otherwise specified. Parameter Symbol Test Conditions Min [1] Typ Max [1] Unit
compared with the internal reference through an error amplifier that controls the peak current accordingly.
5.1 Constant Off-Time Mode
peak current becomes lower while still switching around 43kHz until it hits the minimum peak current limit. Because the switching frequency is always kept around 43kHz in the operation, no audible noises can be heard.
5.2 PFM Mode
(PFM) operation as Figure 21 shows; therefore, losses are reduced because of switching frequency reduction. Figure 21. PFM Operation in Light Load Figure 22. Switching Frequency vs IOUT Figure 23. Peak Current vs Switching Frequency
5.3 Output Voltage Sampling
The RC sampling network samples the output voltage through a forward-biased D3 when D2 is free-wheeling. Feedback Capacitor (CFB1) Selection.
5.4 Soft Start-Up
reaches up to 6V, the IC begins switching, the internal HV current source is turned off, and a start-up timer begins. consumption for high-efficiency and low-standby power, as Figure 24 shows. Figure 25 shows the start-up diagram. Figure 24. RAA223021 Low Standby Power Buck Regulator Figure 25. RAA223021 Start-Up Diagram
5.5 Overload Protection
without switching is the hiccup time). The overload protection time sequence is shown in Figure 26.
5.6 Short-Circuit Protection
When the output is shorted, VOUT = 0, VFB drops to zero because of the feedback network, introducing a delay. to 6V where the IC resumes switching. removed. When the short is removed, VOUT returns to normal. This procedure is shown in Figure 27. Figure 26. RAA223021 Overload Protection Diagram
Figure 27. RAA223021 Short-Circuit Protection Diagram
To simplify the analysis, the following design guidelines are based on the circuit shown in Figure 1.
7.1 Feedback Resistor Selection
calculate the resistor values of RFB1 and RFB2. A series resistor with D3 can help decrease the mismatch affect.
7.2 Output Inductor Selection
7.3 Feedback Capacitor (CFB1) Selection
current is shown in Figure 32. The average output current can be written as Equation 3. Figure 32. The Inductor Current at No Load Operation
where ƞ is the light-load efficiency. Replacing IOUT_MIN with Equation 4 gives you Equation 6. where ∆VOUT is the output voltage increase above the nominal VOUT at no load. in mode transition. Therefore, choose ∆VOUT properly according to the highest VOUT allowed in the applications. When ∆VOUT is picked, CFB1 is calculated by using Equation 8.
7.4 Output Capacitor Selection
VOUT discharging by Equation 9. Figure 33. Output Capacitor Discharging at Step Load
R16DS0074EU0102 Rev.1.02 Page 19 Dec 7, 2022 RAA223021 Datasheet However, the output capacitor should also be large enough to provide sufficient transient voltage support to load step (if any), as with the pulses being separated with a big time interval at no load the controller most likely cannot detect the voltage change and take action promptly. where 7% voltage drop is used in this example.
7.5 Bias Capacitor Selection
7.5.1 V CC Hold Up Capacitor C3 Selection
The C3 capacitor holds up the VCC voltage during PFM mode. In PFM mode, this capacitor provides hold up energy from output to the IC during off-time. This can achieve better light-load efficiency instead of taking energy from the input side. Renesas recommends setting the output ripple voltage smaller than 1V at no load condition with maximum input voltage, which is the worst case with the output capacitor keeping the no-load output voltage from getting too high. Its value is calculated from Equation 11.
7.5.2 V CC Capacitor CVCC Selection
The CVCC capacitor filters the VCC voltage and sets the hiccup time when OLP is triggered. After OLP is triggered, the VCC capacitor is discharged by a discharge current, IQVCC3. When the voltage of CVCC drops to 4.5V, the IC restarts, and CVCC is charged by IVCC_START to VCC_OFF again. Therefore, choose CVCC based Equation 12. However, CVCC also protects the VCC voltage from overshoot from C3 when the chip is shut down. Therefore, for design consideration, the CVCC capacitance should be at least doubled to C3.
7.5.3 Input Capacitor Selection
Typically, the input capacitance affects the inrush current, and therefore the input fuse and bridge selection. When using a bridge rectifier, the input capacitor is chosen as 1.5 ~ 2μF/W for the universal input condition (Equation 13). where ƞ = 0.75 (EQ. 9) (EQ. 10) (EQ. 11) (EQ. 12) (EQ. 13) COUT CFB1 IOUT RFB1 RFB2+ VOUT COUT IOUT T 0.07VOUT PIN_STBY T2 VOUT
2 VOUT 1– 2–
thiccup CVCC 2 1 IQVCC3 IVCC START– = CIN VOUT IOUT 1.5F/W =
7.6 Dummy Resistor Selection
7.7 Power Capability
7.8 PCB Layout Guidance
operation for various operating environments. Pay attention to the following layout recommendations. ▪ Leave proper spacing (minimum 1.4mm) between high voltage (max 400V) traces and low voltage traces. unshielded switching inductor is used. layout example is shown in Figure 34. Figure 34. Example PCB Layout
R16DS0074EU0102 Rev.1.02 Page 22 Dec 7, 2022 RAA223021 Datasheet 9. Package Outline Drawing For the most recent package outline drawing, see M7.15A. M7.15A
7 Lead Narrow Body Small Outline Plastic Package (SOIC)
Rev 1,12/20
- These Pb-free plastic packaged products empl oy special Pb-free material sets, molding compounds/die attach materials, and 100%
- For Moisture Sensitivity Level (MSL), see the RAA223021 device page. For more information about MSL, see TB363.
- See TB347 for details about reel specifications.
Table 2. Key Differences between Family of Parts 1.02 Dec 7, 2022 Updated the output power listed on page 1 from 8W to 12W. Updated revision numbers to the correct Renesas format. 1.01 May 12, 2021 Updated Table 1: added 24V output setting. 1.00 Feb 12, 2021 Initial release.
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