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Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 26
Technical content
Datasheet sections
- 1.1 Block Diagram
- 2.1 Pin Assignments
- 2.2 Pin Descriptions
- 3.1 Absolute Maximum Ratings
- 3.2 Thermal Information
- 3.3 Recommended Operating Conditions
- 3.4 Electrical Specifications
- 5.1 Constant Off-Time Mode
- 5.2 PFM Mode
- 5.3 Output Voltage Sampling
- 5.4 Soft Start-Up
- 5.5 Overload Protection
- 5.6 Short-Circuit Protection
- 5.7 Input Brownout Protection
- 7.1 Feedback Resistor Selection
- 7.2 Output Inductor Selection
- 7.3 Feedback Capacitor (C FB1) Selection
- 7.4 Output Capacitor Selection
- 7.5 Dummy Resistor Selection
- 7.6 Power Capability
- 7.7 PCB Layout Guidance
Features
▪ Ultra-low standby power (<10mW) ▪ No audible noise ▪ Low quiescent current (<100µA) ▪ Output voltage as low as 3.3V ▪ Low EMI with frequency dithering ▪ 5 Ld TSOT23, 7 Ld SOIC, and 8 Ld SOIC package options ▪ Programmable PFM allows optimization of COUT for various standby power requirements ▪ Protection features: Short-Circuit Protection (SCP), Overload Protection (OLP), open feedback protection, and Over-Temperature Protection (OTP).
Applications
▪ Home appliances ▪ Home automation, IoT, and sensors ▪ Metering and Industry control ▪ Bias power Table 1. Maximum Output Current (85°C Ambient 8Ld Figure 1. Typical RAA223011 Buck Application Circuit
1.1 Block Diagram
Figure 2. Block Diagram of RAA223011
R16DS0040EU0302 Rev.3.02 Page 4 Mar 3, 2022 RAA223011 Datasheet 2. Pin Information
2.1 Pin Assignments
2.2 Pin Descriptions
5 Ld TSOT23
8 Ld SOIC
7 Ld SOIC
Pin Name Description5 Ld TSOT23 8 Ld SOIC 7 Ld SOIC 1 1 1 VCC IC supply voltage 2 2 2 FB Feedback pin 3 3 - GND IC ground, externally connect to the SOURCE 4 4 5, 6, 7, 8 SOURCE Source of integrated MOSFET 5 7 4 DRAIN Drain of integrated MOSFET - 5, 6, 8 - N/C Not connected FB GND VCC DRAIN SOURCE FB SOURCE VCC DRAIN GND N/C N/C N/C FB DRAIN VCC SOURCE SOURCE SOURCE SOURCE
R16DS0040EU0302 Rev.3.02 Page 5 Mar 3, 2022 RAA223011 Datasheet 3. Specifications
3.1 Absolute Maximum Ratings
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product reliability and result in failures not covered by warranty.
3.2 Thermal Information
3.3 Recommended Op erating Conditions
Parameter Minimum Maximum Unit VCC -0.3 +6.5 V VFB -0.3 +6.5 V DRAIN (to SOURCE) -0.3 700 V Continuous Power Dissipation (TA = +25°C) 1 W ESD Rating Value Unit Human Body Model (Tested per JS-001-2017) 1.2 kV Charged Device Model (Tested per JS-002-2014) 1 kV Latch-Up (Tested per JESD78E; Class 2, Level A) 100 mA Thermal Resistance (Typical) θ JA (°C/W)[1] 1. θJA is measured on single layer 1oz evaluation PCB with 218mm2 thermal copper connected to source and drain pin, in free air. θJC (°C/W)[2] 2. For θJC, the case temperature location is taken at the package top center.
5 Ld TSOT23 80 71
8 Ld SOIC 86 57
7 Ld SOIC 60 28
Parameter Minimum Maximum Unit Maximum Junction Temperature +150 °C Maximum Storage Temperature Range -60 +150 °C Pb-Free Reflow Profile See TB493 Parameter Minimum Maximum Unit Supply Voltage, V DRAIN 375 V Ambient Temperature -40 +85 °C Output Voltage 3.3 V
R16DS0040EU0302 Rev.3.02 Page 6 Mar 3, 2022 RAA223011 Datasheet
3.4 Electrical Specifications
Typical operating conditions at 25°C, VDRAIN = 100V, VCC = 5.6V, TJ = -40 to +125°C, unless otherwise specified. Parameter Symbol Test Conditions Min [1] Typ Max [1] Unit Startup and Power FET Internal VCC Startup Current I VCC_START VCC = 4V 1.6 mA Drain Leakage Current I D_LEAK VCC = 0V, VDRAIN = 375V, VFB = 2.65V 1 µA IDRAIN Bias I D_BIAS VCC = 5.9V, VDRAIN = 375V 5 µA Power FET Breakdown Voltage V DS(BR) TJ = 25°C 700 V Power FET On-Resistance r DS(ON) TJ = 25°C, VCC = 5.8V, IDS = 200mA 14.5 17 Ω TJ = 125°C 25 30 Ω VCC Supply VCC Start (Rising) V CC_START 5.5 5.9 6.3 V VCC when Internal Regulator Off V CC_OFF 5.5 5.9 6.3 V VCC (Falling) Regulator On at Startup VCC_ON 5.2 5.55 5.9 V Internal VCC On/Off Hysteresis V CC_HYS 0.3 0.35 0.45 V VCC (Falling) Regulator On after Startup VCC_ON_SS 4.25 4.55 4.8 V VCC Undervoltage Threshold (Falling) VCC_UVLO IC stop switching 3.15 3.4 3.55 V VCC Shunt Regulator On (Rise) V CC_SON External VCC supply, internal shunt on 6.15 6.5 V VCC Shunt Regulator Off (Fall) V CC_SOFF 6.1 6.4 V VCC Quiescent Current I VCC_Q VFB > 2.5V, no switching, VCC = 5.6V 70 103 µA VCC Current During Switching I VCC VFB < 2.5V, switching frequency = 30kHz, D = 0.15, VCC = VCC_ON + 0.1V 130 200 µA VCC Discharging Current Hiccup Timing IQVCC3 VCC discharge current for timing of fault hiccup delay 19 30 µA Current Sense Peak Current Limit I PK VFB<2.5V, di/dt = 0.5A/µs, VCC = 5.8V 445 520 660 mA SCP Threshold I SC_TH 750 mA Minimum Peak Current I PKMIN di/dt = 0.5A/µs, VCC = 5.8V 150 mA Leading Edge Blank Time t LEB 217 300 ns Feedback Feedback Voltage V FB 2.4 2.5 2.63 V Transconductance GM I PK GM, VCC = 5.8V 9 S Feedback Undervoltage Threshold V FBUV VCC = 5.7V 1.6 1.7 1.8 V Feedback Threshold for Increased Off-Time VFB_TOFFMIN VCC = 5.0V 0.67 0.84 0.98 V Feedback Overvoltage V FBOV 2.8 3 3.3 V Timing Minimum Off-Time t OFF_MIN VCC = 5.0V 24 32 37 µs
R16DS0040EU0302 Rev.3.02 Page 7 Mar 3, 2022 RAA223011 Datasheet Maximum On-Time t ON_MAX VCC = 5.0V 13 17 19 µs Minimum Off-Time in Short-Circuit t OFFMIN_SC VCC = 5.0V 200 µs Hiccup Restart Delay t HICC CVCC = 1µF 100 ms Startup Blanking Time, OLP Time t ST/OLP fSW =3 0 k H z , VFB < 1.7V, VCC = 5.0V 1024 cycle Thermal Over-Temperature Threshold OTP TH 150 °C Over-Temperature Hysteresis OTP HYS 30 °C 1. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design. Typical operating conditions at 25°C, VDRAIN = 100V, VCC = 5.6V, TJ = -40 to +125°C, unless otherwise specified. (Cont.) Parameter Symbol Test Conditions Min [1] Typ Max [1] Unit
compared with the internal reference through an error amplifier that controls the peak current accordingly.
5.1 Constant Off-Time Mode
peak current becomes lower while still switching around 33kHz until it hits the minimum peak current limit. Because the switching frequency is always kept around 33kHz in the operation, no audible noises can be heard.
5.2 PFM Mode
operation is illustrated in Figure 22 and Figure 23. Figure 21. PFM Operation in Light Load Figure 22. Switching Frequency vs IOUT Figure 23. Peak Current vs Switching Current
5.3 Output Voltage Sampling
The RC sampling network samples the output voltage through a forward biased D3 when D2 is free-wheeling. Feedback Capacitor (CFB1) Selection.
5.4 Soft Start-Up
consumption for high efficiency and low standby power, see Figure 24. Figure 25 shows the start-up diagram. Figure 24. RAA223011 Low Standby Power Buck Regulator Figure 25. RAA223011 Start-Up Diagram
5.5 Overload Protection
(the interval without switching is the hiccup time). The overload protection time sequence is shown in Figure 26.
5.6 Short-Circuit Protection
When the output is shorted, VOUT = 0, VFB drops to zero because of the feedback network, introducing a delay. back to 5.9V where the IC resumes switching. CCM with the inductor peak current being limited at IPK, with an average current around 400mA during the short. Figure 26. RAA223011 Overload Protection Diagram
The part remains in hiccup mode until the short is removed. When the short is removed, VOUT returns to normal. This procedure is shown in Figure 27.
5.7 Input Browno ut Protection
and IC from overheating. If input voltage returns to normal levels, normal switching and power delivery resumes. See Figure 17 for waveform example of brownout protection. Figure 27. RAA223011 Short-Circuit Protection Diagram
7.1 Feedback Resistor Selection
calculate the resistor values of RFB1 and RFB2.
7.2 Output Inductor Selection
L is chosen with a fixed value 1000µH.
7.3 Feedback Capacitor (C FB1) Selection
current is shown in Figure 32. The average output current can be written as Equation 3. Figure 32. The Inductor Current at No Load Operation
R16DS0040EU0302 Rev.3.02 Page 17 Mar 3, 2022 RAA223011 Datasheet Therefore: To have the required input standby power, PIN_STBY, the power delivered to the output should satisfy Equation 5: where ƞ is the light-load efficiency. Replacing IOUTMIN with Equation 4 gives you Equation 6. The required time interval T is calculated using Equation 7: Because the time interval Tstb is primarily determined by the sampling network discharging time, it is related to CFB1 in Equation 8: where ∆VOUT is the output voltage increase above the nominal VOUT at no load. From Equation 8, it can be seen that a bigger sampling capacitor leads to a smaller ∆VOUT, but CFB1 can not be too big as it calls for a huge COUT. A small ∆VOUT can cause erratic logic function of the internal PFM comparator in mode transition. Therefore, choose ∆VOUT properly according to the highest VOUT allowed in the applications. When ∆VOUT is picked, CFB1 is calculated using Equation 8. (EQ. 4) (EQ. 5) (EQ. 6) (EQ. 7) (EQ. 8) IOUT_MIN LI PK_MIN 2 2VOUT Tstb VOUT IOUT_MIN PIN_STBY= VOUT LI PK_MIN 2 2VOUT Tstb P IN_STBY= Tstb LI PK_MIN 2 CFB1 VOUT Tstb
7.4 Output Capacitor Selection
calculated according to VOUT discharging by Equation 9. where 7% voltage drop is used in this example.
7.5 Dummy Resistor Selection
7.6 Power Capability
up to 85C. This table should be used as a reference and may vary because of actual PCB thermal design. Figure 33. Output Capacitor Discharging at Step Load
7.7 PCB Layout Guidance
- Leave proper spacing between high voltage (max 400V) traces and low voltage traces (minimum1.4mm).
- Keep a small loop from the input filter capacitor to the IC, switching inductor, output capacitor, and to the ground of the input capacitor. Also, a small loop consisting of a switching inductor, output capacitor, and freewheeling diode.
- Keep sufficient copper area on the IC drain and/or source pin (not less than 220mm2 for 3-4W output power) for better thermal performance.
- Keep the switching inductor away from the input EMI inductor to avoid noise coupling, especially when an unshielded switching inductor is used.
- Place the VCC decoupling capacitor and the FB pin decoupling capacitor close to the pins. A PCB layout example is shown in Figure 34. 8. EMI Performance Conducted and Radiated EMI compliance for EN55022/CISPR22 (12V/260mA output).
Figure 34. Example PCB Layout Figure 35. Line, 120VAC Figure 36. Line, 230VAC
R16DS0040EU0302 Rev.3.02 Page 21 Mar 3, 2022 RAA223011 Datasheet 9. Package Outline Drawings For the most recent package outline drawing, see P5.064B. P5.064B
5 Lead Thin Small Outline Transistor (TSOT) Plastic Package
Rev 3, 2/2022
R16DS0040EU0302 Rev.3.02 Page 22 Mar 3, 2022 RAA223011 Datasheet For the most recent package outline drawing, see M7.15A. M7.15A
7 Lead Narrow Body Small Outline Plastic Package (SOIC)
Rev 1,12/20
R16DS0040EU0302 Rev.3.02 Page 23 Mar 3, 2022 RAA223011 Datasheet For the most recent package outline drawing, see M8.15. M8.15
8 Lead Narrow Body Small Outline Plastic Package
Rev 5, 4/2021
- These Pb-free plastic packaged products empl oy special Pb-free material sets, molding compounds/die attach materials, and 100%
- For Moisture Sensitivity Level (MSL), see the RAA223011 device page. For more information about MSL, see TB363.
- See TB347 for details about reel specifications.
- The part marking is located on the bottom of the part.
Table 2. Key Differences between Family of Parts
R16DS0040EU0302 Rev.3.02 Page 25 Mar 3, 2022 RAA223011 Datasheet 11. Revision History Rev. Date Description 3.02 Mar 3, 2022 Updated Input Brownout Protection section. Updated POD P5.064B to the latest revision, changes are as follows: ▪ In the End View, widened the lead thickness range to 0.08-0.2mm and removed Note 6. 3.01 Jan 13, 2022 Updated Figures 17 and 18. Added Input Brownout Protection section. Updated POD P5.064B to the latest version, changes are as follows: ▪ Corrected pin numbering to align with datasheet and actual unit. 3.00 Sep 2, 2021 Changed the Theta JC thermal value for the SOT23-5 package from 80 to 71. 2.00 May 27, 2021 Applied new template. Changed SOIC Theta JA numbers from 89 to 86 and from 50 to 60. Changed TSOT23 Theta JC from 60 to 80. Updated Table 2. Updated POD M8.15 to latest revision: ▪ Added the coplanarity specification. 1.02 Feb 25, 2021 Updated Figure 31. 1.01 Feb 18, 2021 Corrected Pin numbers for the 7 Ld SOIC package in the Pin Configurations section.
1.00 Dec 16, 2020 Initial release
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