RAA211605_V01 RENESAS | Alldatasheet
Document overview
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- PDF pages: 17
Technical content
Datasheet sections
- 1.1 Block Diagram
- 2.1 Pin Assignments
- 2.2 Pin Descriptions
- 3.1 Absolute Maximum Ratin gs
- 3.2 Recommended Operating Con ditions
- 3.3 Thermal Information
- 3.4 Electrical Specifications
- 5.1 Soft-Start
- 5.2 Undervoltage Lockout
- 5.3 Current Limit
- 5.4 Output Undervoltage Protection
- 5.5 Thermal Shutdown
- 6.1 Output Voltage Feedback Re sistor Divider
- 6.2 Input Undervoltage Lockout
- 6.3 Inductor Selection
- 6.4 Input Capacitor Selection
- 6.5 Output Capacitor Select ion
- 6.6 Diode Selection
- 6.7 BST Refresh
- 6.8 Boot Capacitor Selection
- 6.9 Thermal Considerations
Features
▪ Wide input voltage range: 4.5V to 60V ▪ Adjustable output voltage ▪ Up to 0.5A output current ▪ Internal compensation ▪ Internal soft start ▪ 600mΩ internal MOSFET ▪ 450kHz nominal switching frequency ▪ Pulse skipping mode under light load condition ▪ Cycle-by-cycle current limit ▪ Input voltage UVLO and output voltage undervoltage protection ▪ Thermal shutdown ▪ Available in the TSOT23-6 package
Applications
▪ Power meters ▪ Battery powered devices ▪ Distributed power systems ▪ Handheld power tools Figure 1. Typical Application Schematic
1.1 Block Diagram
Figure 2. RAA211605 Block Diagram
R16DS0175EU0106 Rev.1.06 Page 4 Mar 24, 2023 RAA211605 Datasheet 2. Pin Information
2.1 Pin Assignments
2.2 Pin Descriptions
Pin Number Pin Name Description 1 BST The bootstrap circuit supply pin. Connect this pin to SW wi th a capacitor to provide bias voltage for the integrated MOSFET gate driver.
2 GND Ground connection pin
3 FB The FB pin connects to the inverting input of the feedback e rror amplifier and should be
connected to a properly selected resistor divider from VOUT to ground to set the output voltage. 4 EN The enable pin. It is high voltage tolerant and therefore, c an be directly connected to VIN. 5 VIN Te VIN pin is connected to the drain of the integrated MOSF ET. This pin is also connected to the input of internal linear regulator that provide bias for the IC. Connect this pin to the input rail.
6 SW This pin is the phase node of the regulator and is connected to the source of the integrated
MOSFET. Connect this pin to the inductor, diode, and boot capacitor. BST GND FB SW VIN EN
R16DS0175EU0106 Rev.1.06 Page 5 Mar 24, 2023 RAA211605 Datasheet 3. Specifications
3.1 Absolute Maximum Ratings
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product reliability and result in failures not covered by warranty.
3.2 Recommended Op erating Conditions
3.3 Thermal Information
Parameter[1] 1. All voltages referenced to VSS unless otherwise specified. Min Max Unit VIN -0.3 65 V EN -0.3 65 V SW -0.7 V IN + 0.3 V BST SW + 4 V BST to SW -0.3 4 V All other pins -0.3 4 V Operating junction temperature –40 150 °C Storage temperature range –65 150 °C ESD Ratings Value Unit Human Body Model (tested per JS-001-2017) 2 kV Charged Device Model (Tested per JS-002-2018) 750 V Latch-Up (tested per JESD78E; Class 2, Level A) 100 mA Parameter Min Max Unit Input Voltage, V IN 4.5 60 V Output Voltage, VOUT 0.8 V IN × DMAX[1] 1. D MAX is 89% to 91%. Also, see the BST Refresh section for refresh considerations. V Output Current, IOUT 00 . 5 A Junction Temperature, TJ -40 125 °C Thermal Resistance (Typical) θ JA (°C/W)[1] 1. θ JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with direct attach features. See TB379. θJC (°C/W)[2] 2. For θ JC, the case temperature location is on the top side of the package.
6 Ld TSOT23 114 42
R16DS0175EU0106 Rev.1.06 Page 6 Mar 24, 2023 RAA211605 Datasheet
3.4 Electrical Specifications
Typical Values are at TA = +25°C, VIN = 24V, VOUT = 3.3V, COUT = 10µF, unless otherwise noted. Min and Max values apply across the junction temperature range, -40°C to +125°C, unless otherwise noted. Parameter Symbol Test Conditions Min [1] 1. Compliance to datasheet limit s is established by one or more methods: production test, characterization, and/or design. Typ Max [1] Unit VIN Supply Input Voltage Range V IN 4.5 60 V Shutdown Current I SHDN 2.75 µA Quiescent Current I Q EN = 2V, VFB = 0.825V, No Switching 300 425 µA Line Regulation ∆V OUT/∆VIN VIN = 5V to 60V 0.25 µV/V VIN UVLO/EN VIN UVLO Rising Threshold 4.05 4.25 4.45 V VIN UVLO Falling Hysteresis 250 mV EN Rising Threshold 1.15 1.275 1.45 V EN Falling Hysteresis 125 mV Feedback Voltage Reference Feedback Voltage Reference V FB 25 °C 0.788 0.8 0.812 V -40 °C to 125 °C 0.776 0.8 0.824 V Integrated MOSFET High-side FET On-Resistance RDS_onh 600 mΩ Soft-Start Internal Soft-Start Time t SS 1m s Oscillator/PWM Comparator Switching Frequency f SW VFB = 0.8 V 409.5 450 500.5 kHz Minimum On-Time t ON_MIN 96 ns Minimum Off-Time t OFF_MIN 212 ns Overcurrent Protection (OCP)/VOUT Undervoltage Protection (UVP) Peak Current Limit Threshold I HSOC Duty ratio = 0.9, 25 °C 0.7 0.9 A VFB Undervoltage Threshold 0.24 V Foldback Frequency V FB = 0V 100 kHz Hiccup Time t HICCUP 23 ms Thermal Shutdown (OTP) Thermal Shutdown Threshold 155 °C Thermal Shutdown Recovery Hysteresis 20 °C
CCM, it operates at a fixed switching frequency of 450kHz.
5.1 Soft-Start
error amplifier ramps from 0V to its nominal value of 0.8V in approximately 1ms.
5.2 Undervoltage Lockout
5.3 Current Limit
foldback function kicks in. When VFB is 0, the foldback frequency is around 100kHz.
5.4 Output Undervoltage Protection
is above 30% of the nominal setpoint, the controller returns to normal voltage regulation.
5.5 Thermal Shutdown
temperature drops to approximately 135°C (typical). The recommended component selections for typical applications are listed in Table 1. Table 1. Recommended Components Selection for Typical Applications
R16DS0175EU0106 Rev.1.06 Page 11 Mar 24, 2023 RAA211605 Datasheet
6.1 Output Voltage Feedback Resistor Divider
The output voltage can be programmed down to 0.8V with a resistor divider from VOUT to FB pin to GND based on Equation 1. The recommended RFB2 (see Figure 1) resistance is 20kΩ. Table 1 can be referenced for RFB1 and RFB2 for typical VOUT applications.
6.2 Input Undervoltage Lockout
The input undervoltage lockout level can be set with a resistor divider from VIN to EN pin to GND based on Equation 2 (see Figure 1). where VINR is the minimum input voltage for the part to turn on. The resulting input voltage VINF for the part to be turned off is calculated based on Equation 3 (see Figure 1).
6.3 Inductor Selection
The inductor of the buck converter determines its current ripple and factors such as inductance, saturation current, DC resistance should be considered when selecting it. Choosing the inductance requires the choice of inductor current ripple. Larger inductance results in less inductor current ripple and therefore less output voltage ripple. However, it may increase the response time and output voltage variance during a load transient. A reasonable starting point for inductor current ripple is 30% to 60% of the maximum output current. Considering the wide operating input voltage range of the part, Renesas recommends calculating required inductance L based on Equation 4. Table 1 can be referenced for selecting the inductance for typical VOUT applications. where VOUT is the output voltage in V and the inductance L is in µH. In addition, the saturation current rating of the inductor should be higher than the peak current under overload conditions. For lower loss and smaller output voltage ripple, the inductor with smallest possible DC resistance should be selected provided its mechanical dimensions meet application requirements. The RMS current rating of the inductor needs to meet the maximum load and the recommended rating of the saturation current is 1A or higher.
6.4 Input Capacitor Selection
The input capacitor is used in the Buck converter to maintain the input voltage by suppressing the voltage ripple induced by discontinuous switching current. The required RMS current rating IIN(RMS) of the input capacitor is calculated using Equation 5. where IOUT(MAX) is the maximum average load current and D is the duty ratio. When D equals 0.5, IIN(RMS) has the maximum value which is IOUT(MAX)/2. (EQ. 1) (EQ. 2) (EQ. 3) (EQ. 4) (EQ. 5) RFB1 RFB2 VOUT 0.8– RIN1 RIN2 VINR 1.275– VINF 1.15 RIN1 RIN2+ RIN2 L1 0 V OUT•= IIN(RMS) IOUT MAX() D1 D –()••=
R16DS0175EU0106 Rev.1.06 Page 12 Mar 24, 2023 RAA211605 Datasheet The voltage rating of the input capacitor should be higher than the maximum input voltage. The required capacitance CIN of the input capacitor to ensure the expected peak-to-peak input voltage ripple ΔVIN is calculated using Equation 6: where fSW is the switching frequency. The required capacitance also has the maximum value when D equals 0.5. Renesas recommends using ceramic capacitors as an input capacitor, which has low ESR and low ESL. When selecting the ceramic capacitor, consider that the effective capacitance reduces with DC bias voltage across it. Also, Renesas recommends using X7R ceramic capacitors because of their small temperature coefficient. If the part is connected to the power source through a high impedance path, Renesas recommends adding an electrolytic capacitor in addition to the ceramic capacitor to damp the input voltage oscillation.
6.5 Output Capacitor Selection
The output capacitor determines both steady-state performance and transient performance of the Buck converter. Factors such as output voltage ripple, output voltage variation during transients, and control loop stability should be considered when selecting the output capacitor. For this part, Renesas recommends using X7R ceramic capacitors as the output capacitor. When selecting the ceramic capacitor, consider that the effective capacitance reduces with DC bias voltage across it. For the ceramic capacitor, its capacitance is dominating the voltage ripple. Therefore, the required capacitance COUT(RIPPLE) for the expected peak-to-peak output voltage ripple ΔVOUT(RIPPLE) is calculated using Equation 7. where ΔIL is the inductor the inductor peak-to-peak current ripple and fSW is the switching frequency. To meet the output voltage variation requirements during load step-up and load step-down transients, the required capacitance COUT(STEPUP) is calculated using Equation 8 and COUT(STEPDOWN) is calculated using Equation 9. where ISTEP is the transient load step and ΔVOUT is the expected voltage variation during the transient. For the control loop to be stable with gain and phase margin in addition to sufficient bandwidth, the required capacitance COUT(LOOP) is derived using Equation 10. where COUT(LOOP) is in µF and VOUT is in V. Select the output capacitors such that aforementioned requirements are met, which means the total output capacitance should be higher than the maximum value of the above calculated capacitance. For convenience, Table 1 can be referenced when selecting output capacitors for typical VOUT applications. (EQ. 6) (EQ. 7) (EQ. 8) (EQ. 9) (EQ. 10) CIN IOUT MAX() D1 D –()• COUT RIPPLE() ΔIL COUT STEPUP() LI STEP ΔIL 2 COUT STEPDOWN() LI STEP ΔIL 2 COUT LOOP() VOUT
6.6 Diode Selection
recommended for this application.
6.7 BST Refresh
switching, which keeps BST refreshed.
6.8 Boot Capacitor Selection
6.9 Thermal Considerations
temperature at different loads (VOUT = 3.3V) allowed for the IC mounted on the aforementioned PCB. Figure 21. Maximum Ambient Temperature vs Output Current
R16DS0175EU0106 Rev.1.06 Page 14 Mar 24, 2023 RAA211605 Datasheet 7. Layout Suggestions ▪ Place the input ceramic capacit or(s) as close as possible to the IC VIN pin and the diode. Keep the power loop (input ceramic capacitor, IC VIN pin, and diode) as small as possible to minimize phase node voltage ringing induced by trace parasitic inductance. This also results in better EMI performance. ▪ If an aluminum electrolytic cap acitor is used, place it as close as possible to the IC VIN pin. ▪ Keep the phase node copper area small for less parasitic capacitance but large enough to handle the load current. ▪ Place the output capacitor(s) c lose to the inductor and freewheel diode. ▪ Connect the power ground (CIN, diode, and COUT ground) to the analog ground plane, which connects to the GND pin. Use a single point connection. ▪ Place feedback resistors close t o the FB and GND pins, and away from phase node. ▪ Use a large etch metal area and ground plane on the PCB. Place ground vias underneath the IC and around the ground node of the input and output capacitors in addition to the output diode, facilitating better heat dissipation.
R16DS0175EU0106 Rev.1.06 Page 15 Mar 24, 2023 RAA211605 Datasheet 8. Package Outline Drawing For the most recent package outline drawing, see P6.064C. P6.064C
6 Lead Thin Small Outline Transistor (TSOT) Plastic Package
Rev 2, 12/20
R16DS0175EU0106 Rev.1.06 Page 16 Mar 24, 2023 RAA211605 Datasheet 9. Ordering Information 10. Revision History Part Number[1][2] 1. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J-STD-020. 2. For Moisture Sensitivity Level (MSL), see the RAA211605 device page. For more information about MSL, see TB363. Part Marking[3] 3. Part marking is located on the bottom of the part. Package Description (RoHS Compliant) Pkg. Dwg. # Carrier Type [4] 4. See TB347 for details about reel specifications. Junction Temp Range RAA2116054GP3#JA0 605 TSOT23-6 P6.064C Reel, 3k -40 to 125°C RTKA211605DR0000BU RAA211605 Demonstration Board RTKA211605DR0010BU RAA211605 DC/D C step-down regulator small form factor demonstration board Revision Date Description 1.06 Mar 24, 2023 Updated Max for Output Voltage, VOUT in Recomme nded Operating Conditions. 1.05 Oct 13, 2021 Corrected Typo in EC table changed unit for Lin e Regulation from mV/V to µV/V.
1.04 Oct 4, 2021 Updated Features bullet
1.03 Sep 21, 2021 Updated Ordering Information table. 1.02 Sep 10, 2021 Corrected typo in the paragraph under Equation 10 on page 12. 1.01 Jul 29, 2021 Updated Functional Description section. Added BST Refresh section. 1.00 Jul 14, 2021 Initial release.
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