RA6T1

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www.renesas.com Renesas RA6T1 Group Datasheet 32-Bit MCU Renesas Advanced (RA) Family Renesas RA6 Series May 2020Rev.1.00 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp. website (http://www.renesas.com). Cover

R01DS0375EU0100 Rev.1.00 Page 2 of 69 May 29, 2020 ■ Arm Cortex-M4 Core with Floating Point Unit (FPU)  Armv7E-M architecture with DSP instruction set  Maximum operating frequency: 120 MHz  Support for 4-GB address space  On-chip debugging system: JTAG, SWD, and ETM  Boundary scan and Arm Memory Protection Unit (Arm MPU) ■ Memory  Up to 512-KB code flash memory (40 MHz zero wait states)  8-KB data flash memory (125,000 erase/write cycles)  64-KB SRAM  Flash Cache (FCACHE)  Memory Protection Units (MPU)  Memory Mirror Function (MMF)  128-bit unique ID ■ Connectivity  Serial Communications Interface (SCI) with FIFO × 7  Serial Peripheral Interface (SPI) × 2  I2C bus interface (IIC) × 2  CAN module (CAN) × 1  IrDA interface ■ Analog  12-bit A/D Converter (ADC12) with 3 sample-and-hold circuits each × 2  12-bit D/A Converter (DAC12) × 2  High-Speed Analog Comparator (ACMPHS) × 6  Programmable Gain Amplifier (PGA) × 6  Temperature Sensor (TSN) ■ Timers  General PWM Timer 32-bit Enhanced High Resolution (GPT32EH) × 4  General PWM Timer 32-bit Enhanced (GPT32E) × 4  General PWM Timer 32-bit (GPT32) × 5  Asynchronous General-Purpose Timer (AGT) × 2  Watchdog Timer (WDT) ■ Safety  SRAM parity error check  Flash area protection  ADC self-diagnosis function  Clock Frequency Accuracy Measurement Circuit (CAC)  Cyclic Redundancy Check (CRC) calculator  Data Operation Circuit (DOC)  Port Output Enable for GPT (POEG)  Independent Watchdog Timer (IWDT)  GPIO readback level detection  Register write protection  Main oscillator stop detection  Illegal memory access ■ System and Power Management  Low power modes  Event Link Controller (ELC)  DMA Controller (DMAC) × 8  Data Transfer Controller (DTC)  Key Interrupt Function (KINT)  Power-on reset  Low Voltage Detection (LVD) with voltage settings ■ Security and Encryption  AES128/192/256  3DES/ARC4  SHA1/SHA224/SHA256/MD5  GHASH  RSA/DSA/ECC  True Random Number Generator (TRNG) ■ Multiple Clock Sources  Main clock oscillator (MOSC) (8 to 24 MHz)  Sub-clock oscillator (SOSC) (32.768 kHz)  High-speed on-chip oscillator (HOCO) (16/18/20 MHz)  Middle-speed on-chip oscillator (MOCO) (8 MHz)  Low-speed on-chip oscillator (LOCO) (32.768 kHz)  IWDT-dedicated on-chip oscillator (15 kHz)  Clock trim function for HOCO/MOCO/LOCO  Clock out support ■ General-Purpose I/O Ports  Up to 76 input/output pins - Up to 9 CMOS input - Up to 67 CMOS input/output - Up to 14 input/output 5 V tolerant - Up to 13 high current (20 mA) ■ Operating Voltage  VCC: 2.7 to 3.6 V ■ Operating Temperature and Packages  Ta = -40°C to +105°C - 100-pin LQFP (14 mm × 14 mm, 0.5 mm pitch) - 64-pin LQFP (10 mm × 10 mm, 0.5 mm pitch) RA6T1 Group Datasheet Leading performance 120-MHz Arm® Cortex®-M4 core, up to 512 KB of code flash memory, 64-KB SRAM, security and safety features, and advanced analog.

Features

R01DS0375EU0100 Rev.1.00 Page 3 of 69 May 29, 2020 RA6T1 Datasheet 1. Overview 1. Overview The MCU integrates multiple series of software- and pin-compatible Arm®-based 32-bit cores that share a common set of Renesas peripherals to facilitate design scalability and efficient platform-based product development. The MCU in this series incorporates a high-performance Arm Cortex®-M4 core running up to 120 MHz with the following features:  Up to 512-KB code flash memory  64-KB SRAM  Security and safety features  12-bit A/D Converter (ADC12)  12-bit D/A Converter (DAC12)  Analog peripherals.

1.1 Function Outline

Table 1.1 Arm core Feature Functional description Arm Cortex-M4 core  Maximum operating frequency: up to 120 MHz  Arm Cortex-M4 core: - Revision: r0p1-01rel0 - Armv7E-M architecture profile - Single precision floating-point unit compliant with the ANSI/IEEE Std 754-2008.  Arm Memory Protection Unit (Arm MPU): - Armv7 Protected Memory System Architecture - 8 protect regions.  SysTick timer: - Driven by SYSTICCLK (LOCO) or ICLK. Table 1.2 Memory Feature Functional description Code flash memory Up to 512-KB code flash memory. See section 41, Flash Memory in User’s Manual. Data flash memory 8-KB data flash memory. See section 41, Flash Memory in User’s Manual. Memory Mirror Function (MMF) The Memory Mirror Function (MMF) can be configured to mirror the target application image load address in code flash memory to the application image link address in the 23-bit unused memory space (memory mirror space addresses). Your application code is developed and linked to run from this MMF destination address. Your application code does not need to know the load location where it is stored in code flash memory. See section 5, Memory Mirror Function (MMF) in User’s Manual. Option-setting memory The option-setting memory determines t he state of the MCU after a reset. See section 7, Option-Setting Memory in User’s Manual. SRAM On-chip high-speed SRAM. See section 40, SRAM in User’s Manual. Table 1.3 System (1 of 3) Feature Functional description Operating modes Two operating modes:  Single-chip mode  SCI boot mode. See section 3, Operating Modes in User’s Manual.

R01DS0375EU0100 Rev.1.00 Page 4 of 69 May 29, 2020 RA6T1 Datasheet 1. Overview Resets 14 resets:  RES pin reset  Power-on reset  Voltage monitor 0 reset  Voltage monitor 1 reset  Voltage monitor 2 reset  Independent watchdog timer reset  Watchdog timer reset  Deep Software Standby reset  SRAM parity error reset  Bus master MPU error reset  Bus slave MPU error reset  Stack pointer error reset  Software reset. See section 6, Resets in User’s Manual. Low Voltage Detection (LVD) The Low Voltage Detection (LVD) fu nction monitors the voltage level input to the VCC pin, and the detection level can be selected using a software program. See section 8, Low Voltage Detection (LVD) in User’s Manual. Clocks  Main clock oscillator (MOSC)  Sub-clock oscillator (SOSC)  High-speed on-chip oscillator (HOCO)  Middle-speed on-chip oscillator (MOCO)  Low-speed on-chip oscillator (LOCO)  PLL frequency synthesizer  IDWT-dedicated on-chip oscillator  Clock out support. See section 9, Clock Generation Circuit in User’s Manual. Clock Frequency Accuracy Measurement Circuit (CAC) The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to be measured (measurement target clock) within the time generated by the clock to be used as a measurement reference (measurement reference clock), and determines the accuracy depending on whether the number of pulses is within the allowable range. When measurement is complete or the number of pulses within the time generated by the measurement reference clock is not within the allowable range, an interrupt request is generated. See section 10, Clock Frequency Accuracy Measurement Circuit (CAC) in User’s Manual. Interrupt Controller Unit (ICU) The Interrupt Controller Unit (ICU) controls which event signals are linked to the NVIC/DTC module and DMAC module. The ICU also controls NMI interrupts. See section 13, Interrupt Controller Unit (ICU) in User’s Manual. Key Interrupt Function (KINT) A key interrupt can be generated by setting the Key Return Mode Register (KRM) and inputting a rising or falling edge to the key interrupt input pins. See section 20, Key Interrupt Function (KINT) in User’s Manual. Low power modes Power consumption can be reduced in mu ltiple ways, such as by setting clock dividers, stopping modules, selecting power control mode in normal operation, and transitioning to low power modes. See section 11, Low Power Modes in User’s Manual. Register write protection The register write protection function protects important registers from being overwritten because of software errors. See section 12, Register Write Protection in User’s Manual. Memory Protection Unit (MPU) Four Memory Protection Units (M PUs) and a CPU stack pointer monitor function are provided for memory protection. See section 15, Memory Protection Unit (MPU) in User’s Manual. Watchdog Timer (WDT) The Watchdog Timer (WDT) is a 14-bit dow n-counter that can be used to reset the MCU when the counter underflows because the system has run out of control and is unable to refresh the WDT. In addition, a non-maskable interrupt or interrupt can be generated by an underflow. A refresh-permitted period can be set to refresh the counter and used as the condition for detecting when the system runs out of control. See section 25, Watchdog Timer (WDT) in User’s Manual. Table 1.3 System (2 of 3) Feature Functional description

R01DS0375EU0100 Rev.1.00 Page 5 of 69 May 29, 2020 RA6T1 Datasheet 1. Overview Independent Watchdog Timer (IWDT) The Independent Watchdog Timer (IWDT) consists of a 14-bit down-counter that must be serviced periodically to prevent counter underflow. The IWDT provides functionality to reset the MCU or to generate a non-maskable interrupt or interrupt for a timer underflow. Because the timer operates with an independent, dedicated clock source, it is particularly useful in returning the MCU to a known state as a fail-safe mechanism when the system runs out of control. The IWDT can be triggered automatically on a reset, underflow, or refresh error, or by a refresh of the count value in the registers. See section 26, Independent Watchdog Timer (IWDT) in User’s Manual. Table 1.4 Event link Feature Functional description Event Link Controller (ELC) The Event Link Controller (ELC ) uses the interrupt requests generated by various peripheral modules as event signals to connect them to different modules, enabling direct interaction between the modules without CPU intervention. See section 18, Event Link Controller (ELC) in User’s Manual. Table 1.5 Direct memory access Feature Functional description Data Transfer Controller (DTC) A Data Transfer Controller (D TC) module is provided for transferring data when activated by an interrupt request. See section 17, Data Transfer Controller (DTC) in User’s Manual. DMA Controller (DMAC) An 8-channel DMA Controller (DMA C) module is provided for transferring data without the CPU. When a DMA transfer request is generated, the DMAC transfers data stored at the transfer source address to the transfer destination address. See section 16, DMA Controller (DMAC) in User’s Manual. Table 1.6 Timers Feature Functional description General PWM Timer (GPT) The General PWM Timer (GPT) is a 32-bit timer with 13 channels. PWM waveforms can be generated by controlling the up-counter, down-counter, or up- and down-counter. In addition, PWM waveforms can be generated for controlling brushless DC motors. The GPT can also be used as a general-purpose timer. See section 22, General PWM Timer (GPT) in User’s Manual. Port Output Enable for GPT (POEG) Use the Port Output Enable for GPT (POEG) function to place the General PWM Timer (GPT) output pins in the output disable state. See section 21, Port Output Enable for GPT (POEG) in User’s Manual. Low Power Asynchronous General- Purpose Timer (AGT) The Low Power Asynchronous General-Purpose Timer (AGT) is a 16-bit timer that can be used for pulse output, external pulse width or period measurement, and counting of external events. This 16-bit timer consists of a reload register and a down-counter. The reload register and the down-counter are allocated to the same address, and can be accessed with the AGT register. See section 24, Low Power Asynchronous General-Purpose Timer (AGT) in User’s Manual. Table 1.3 System (3 of 3) Feature Functional description

R01DS0375EU0100 Rev.1.00 Page 6 of 69 May 29, 2020 RA6T1 Datasheet 1. Overview Table 1.7 Communication interfaces Feature Functional description Serial Communications Interface (SCI) The Serial Communications Interface (SCI) is configurable to five asynchronous and synchronous serial interfaces:  Asynchronous interfaces (UART and Asynchronous Communications Interface Adapter (ACIA))  8-bit clock synchronous interface  Simple IIC (master-only)  Simple SPI  Smart card interface. The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and transmission protocol. Each SCI has FIFO buffers to enable continuous and full-duplex communication, and the data transfer speed can be configured independently using an on-chip baud rate generator. See section 27, Serial Communications Interface (SCI) in User’s Manual. IrDA Interface (IrDA) The IrDA interface sends and rece ives IrDA data communication waveforms in cooperation with the SCI1 based on the IrDA (Infrared Data Association) standard 1.0. See section 28, IrDA Interface in User’s Manual. I 2C bus interface (IIC) The 2-channel I 2C bus interface (IIC) conforms with and provides a subset of the NXP I2C (Inter-Integrated Circuit) bus interface functions. See section 29, I2C Bus Interface (IIC) in User’s Manual. Serial Peripheral Interface (SPI) Two independent Serial Periph eral Interface (SPI) channels are capable of high-speed, full- duplex synchronous serial communications with multiple processors and peripheral devices. See section 31, Serial Peripheral Interface (SPI) in User’s Manual. Controller Area Network (CAN) module The Controller Area Network (CAN) module provides functionality to receive and transmit data using a message-based protocol between multiple slaves and masters in electromagnetically- noisy applications. The CAN module complies with the ISO 11898-1 (CAN 2.0A/CAN 2.0B) standard and supports up to 32 mailboxes, which can be configured for transmission or reception in normal mailbox and FIFO modes. Both standard (11-bit) and extended (29-bit) messaging formats are supported. See section 30, Controller Area Network (CAN) Module in User’s Manual. Table 1.8 Analog Feature Functional description 12-bit A/D Converter (ADC12) Up to two successive approximatio n 12-bit A/D Converters (ADC12) are provided. In unit 0, up to 11 analog input channels are selectable. In unit 1, up to eight analog input channels, the temperature sensor output, and an internal reference voltage are selectable for conversion. The A/D conversion accuracy is selectable from 12-bit, 10-bit, and 8-bit conversion, making it possible to optimize the tradeoff between speed and resolution in generating a digital value. See section 35, 12-Bit A/D Converter (ADC12) in User’s Manual. 12-bit D/A Converter (DAC12) A 12-bit D/A Converter (DAC12) converts data and includes an output amplifier. See section 36, 12-Bit D/A Converter (DAC12) in User’s Manual. Temperature Sensor (TSN) The on-chip Temperature Sensor (TSN) can determine and monitor the die temperature for reliable operation of the device. The sensor outputs a voltage directly proportional to the die temperature, and the relationship between the die temperature and the output voltage is linear. The output voltage is provided to the ADC12 for conversion and can also be used by the end application. See section 37, Temperature Sensor (TSN) in User’s Manual. High-Speed Analog Comparator (ACMPHS) The High-Speed Analog Comparator (ACMPHS) compares a test voltage with a reference voltage and provides a digital output based on the conversion result. Both the test and reference voltages can be provided to the comparator from internal sources such as the DAC12 output and internal reference voltage, and an external source with or without an internal PGA. Such flexibility is useful in applications that require go/no-go comparisons to be performed between analog signals without necessarily requiring A/D conversion. See section 38, High- Speed Analog Comparator (ACMPHS) in User’s Manual.

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1.2 Block Diagram

Figure 1.1 shows a block diagram of the MCU superset, some individual devices within the group have a subset of the features. Table 1.9 Data processing Feature Functional description Cyclic Redundancy Check (CRC) calculator The Cyclic Redundancy Check (CRC) calculator generates CRC codes to detect errors in the data. The bit order of CRC calculation results can be switched for LSB-first or MSB-first communication. Additionally, various CRC-generating polynomials are available. The snoop function allows monitoring reads from and writes to specific addresses. This function is useful in applications that require CRC code to be generated automatically in certain events, such as monitoring writes to the serial transmit buffer and reads from the serial receive buffer. See section 32, Cyclic Redundancy Check (CRC) Calculator in User’s Manual. Data Operation Circuit (DOC) The Data Op eration Circuit (DOC) compares, adds, and subtracts 16-bit data. See section 39, Data Operation Circuit (DOC) in User’s Manual. Table 1.10 Security Feature Functional description Secure Crypto Engine 7 (SCE7)  Security algorithms: - Symmetric algorithms: AES, 3DES, and ARC4 - Asymmetric algorithms: RSA, DSA, and ECC.  Other support features: - TRNG (True Random Number Generator) - Hash-value generation: SHA1, SHA224, SHA256, GHASH, and MD5 - 128-bit unique ID.

R01DS0375EU0100 Rev.1.00 Page 8 of 69 May 29, 2020 RA6T1 Datasheet 1. Overview Figure 1.1 Block diagram Memory Up to 512 KB code flash

8 KB data flash

64 KB SRAM

DMAC × 8 System Mode control Power control Register write protection MOSC/SOSC Clocks (H/M/L) OCO PLL Arm Cortex-M4 DSP FPU MPU NVIC System timer Test and DBG interface DTC CAC POR/LVD Reset Bus MPU KINT ICU GPT32EH x 4 GPT32E x 4 GPT32 x 5 Timers AGT × 2 WDT/IWDT Communication interfaces IIC × 2 SPI × 2 CAN × 1 SCI × 7 IrDA × 1 ELC Event link SCE7 Security Analog CRC Data processing DOC TSN DAC12 ACMPHS × 6 ADC12 with PGA × 2

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1.3 Part Numbering

Figure 1.2 shows the product part number information, including memory capacity and package type. Table 1.11 shows a list of products. Figure 1.2 Part numbering scheme Table 1.11 Product list Product part number Orderable part number Package code Code flash Data flash SRAM Operating temperature R7FA6T1AD3CFP R7FA6T1AD3CFP#AA0 PLQP0100KB-B 512 KB 8 KB 64 KB -40 to +105°C R7FA6T1AB3CFP R7FA6T1AB3CFP#AA0 PLQP0100KB-B 256 KB -40 to +105°C R7FA6T1AD3CFM R7FA6T1AD3CFM#AA0 PLQP0064KB-C 512 KB -40 to +105°C R7FA6T1AB3CFM R7FA6T1AB3CFM#AA0 PLQP0064KB-C 256 KB -40 to +105°C # A A 0R 7 F A 6 T 1 A D 3 C F P Package type FP: LQFP 100 pins FM: LQFP 64 pins Quality Grade Operating temperature 3: -40 °C to 105°C Code flash memory size D: 512 KB, B: 256KB Feature set Group number Series name RA family Flash memory Renesas microcontroller Packaging, Terminal material (Pb -free) #AA: Tray/Sn (Tin) only #AC: Tray/others Production identification code

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1.4 Function Comparison

Table 1.12 Functional comparison Function Part numbers R7FA6T1AD3CFP R7FA6T1AB3CFP R7FA6T1AD3CFM R7FA6T1AB3CFM Pin count 100 64 Package LQFP LQFP Code flash memory 256 KB/512 KB Data flash memory 8 KB SRAM 64 KB Parity 64 KB System CPU clock 120 MHz Backup registers

512 Bytes

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1.5 Pin Functions

Table 1.13 Pin functions (1 of 3) Function Signal I/O Description Power supply VCC Input Power supply pi n. This is used as the digital power supply for the respective modules and internal voltage regulator, and used to monitor the voltage of the POR/LVD. Connect this pin to the system power supply. Connect it to VSS by a 0.1-μF capacitor. Place the capacitor close to the pin. VCL0 Input Connect this pin to VSS through a 0.1- μF smoothing capacitor used to stabilize the internal power supply. Place the capacitor close to the pin.VCL Input VSS Input Ground pin. Connect to the system power supply (0 V). Clock XTAL Output Pins for a crystal resonator. An external clock signal can be input through the EXTAL pin.EXTAL Input XCIN Input Input/output pins for the sub-clo ck oscillator. Connect a crystal resonator between XCOUT and XCIN.XCOUT Output CLKOUT Output Clock output pin Operating mode control MD Input Pin for setting the operating mode. The signal level on this pin must not be changed during operation mode transition on release from the reset state. System control RES Input Reset signal input pin. The MCU enters the reset state when this signal goes low. CAC CACREF Input Measurement reference clock input pin Interrupt NMI Input Non-maskable interrupt request pin IRQ0 to IRQ13 Input Maskable interrupt request pins KINT KR00 to KR07 Input A key interrupt can be generated by inputting a falling edge to the key interrupt input pins On-chip emulator TMS I/O On-chip emulator or boundary scan pins TDI Input TCK Input TDO Output TCLK Output This pin outputs the clock fo r synchronization with the trace data TDATA0 to TDATA3 Output Trace data output SWDIO I/O Serial wire debug data input/output pin SWCLK Input Serial wire clock pin SWO Output Serial wire trace output pin GPT GTETRGA, GTETRGB, GTETRGC, GTETRGD Input External trigger input pins GTIOC0A to GTIOC12A, GTIOC0B to GTIOC12B I/O Input capture, output compare, or PWM output pins GTIU Input Hall sensor input pin U GTIV Input Hall sensor input pin V GTIW Input Hall sensor input pin W GTOUUP Output 3-phase PWM output for BLDC motor control (positive U phase) GTOULO Output 3-phase PWM output for BLDC motor control (negative U phase) GTOVUP Output 3-phase PWM output for BLDC motor control (positive V phase) GTOVLO Output 3-phase PWM output for BLDC motor control (negative V phase) GTOWUP Output 3-phase PWM output for BLDC motor control (positive W phase) GTOWLO Output 3-phase PWM output for BLDC motor control (negative W phase) AGT AGTEE0, AGTEE1 Input External event input enable signals AGTIO0, AGTIO1 I/O External event input and pulse output pins AGTO0, AGTO1 Output Pulse output pins AGTOA0, AGTOA1 Output Output compare match A output pins AGTOB0, AGTOB1 Output Output compare match B output pins

R01DS0375EU0100 Rev.1.00 Page 12 of 69 May 29, 2020 RA6T1 Datasheet 1. Overview SCI SCK0 to SCK4, SCK8, SCK9 I/O Input/output pins for the clock (clock synchronous mode) RXD0 to RXD4, RXD8, RXD9 Input Input pins for received data (asynchronous mode/clock synchronous mode) TXD0 to TXD4, TXD8, TXD9 Output Output pins for transmitted data (asynchronous mode/clock synchronous mode) CTS0_RTS0 to CTS4_RTS4, CTS8_RTS8, CTS9_RTS9 I/O Input/output pins for controlling t he start of transmission and reception (asynchronous mode/clock synchronous mode), active-low SCL0 to SCL4, SCL8, SCL9 I/O Input/output pins for the IIC clock (simple IIC mode) SDA0 to SDA4, SDA8, SDA9 I/O Input/output pins for the IIC data (simple IIC mode) SCK0 to SCK4, SCK8, SCK9 I/O Input/output pins for the clock (simple SPI mode) MISO0 to MISO4, MISO8, MISO9 I/O Input/output pins for slave transmission of data (simple SPI mode) MOSI0 to MOSI4, MOSI8, MOSI9 I/O Input/output pins for master trans mission of data (simple SPI mode) SS0 to SS4, SS8, SS9 Input Chip-select input pins (s imple SPI mode), active-low IIC SCL0, SCL1 I/O Input/output pins for the clock SDA0, SDA1 I/O Input/output pins for data SPI RSPCKA, RSPCKB I/O Clock input/output pin MOSIA, MOSIB I/O Input or output pins for data output from the master MISOA, MISOB I/O Input or output pins for data output from the slave SSLA0, SSLB0 I/O Input or output pin for slave selection SSLA1 to SSLA3, SSLB1 to SSLB3 Output Output pins for slave selection CAN CRX0 Input Receive data CTX0 Output Transmit data Analog power supply AVCC0 Input Analog voltage supply pin. This is used as the analog power supply for the respective modules. Supply this pin with the same voltage as the VCC pin. AVSS0 Input Analog ground pin. This is used as the analog ground for the respective modules. Supply this pin with the same voltage as the VSS pin. VREFH0 Input Analog reference voltage supply pi n for the ADC12 (unit 0). Connect this pin to VCC when not using the ADC12 (unit 0) and sample-and-hold circuit for AN000 to AN002. VREFL0 Input Analog reference ground pin for the ADC12. Connect this pin to VSS when not using the ADC12 (unit 0) and sample-and-hold circuit for AN000 to AN002 VREFH Input Analog reference voltage supply pin for the ADC12 (unit 1) and D/A Converter. Connect this pin to VCC when not using the ADC12 (unit 1), sample-and-hold circuit for AN100 to AN102, and D/A Converter. VREFL Input Analog reference ground pin for the ADC12 and D/A Converter. Connect this pin to VSS when not using the ADC12 (unit 1), sample-and-hold circuit for AN100 to AN102, and D/A Converter. ADC12 AN000 to AN003, AN005 to AN007, AN016 to AN018, AN020 Input Input pins for the analog signals to be processed by the ADC12 AN100 to AN102, AN105 to AN107, AN116, AN117 Input ADTRG0 Input Input pins for the external trig ger signals that start the A/D conversion ADTRG1 Input PGAVSS000, PGAVSS100 Input Pseudo-differential input pins Table 1.13 Pin functions (2 of 3) Function Signal I/O Description

R01DS0375EU0100 Rev.1.00 Page 13 of 69 May 29, 2020 RA6T1 Datasheet 1. Overview DAC12 DA0, DA1 Output Output pins for the anal og signals processed by the D/A converter ACMPHS VCOUT Output Comparator output pin IVREF0 to IVREF3 Input Reference voltage input pins for comparator IVCMP0 to IVCMP3 Input Analog voltage input pins for comparator I/O ports P000 to P007 Input General-purpose input pins P008, P014, P015 I/O General-purpose input/output pins P100 to P115 I/O General-purpose input/output pins P200 Input General-purpose input pin P201, P205 to P214 I/O General-purpose input/output pins P300 to P307 I/O General-purpose input/output pins P400 to P415 I/O General-purpose input/output pins P500 to P504, P508 I/O General-purpose input/output pins P600 to P602, P608 to P610 I/O General-purpose input/output pins P708 I/O General-purpose input/output pin Table 1.13 Pin functions (3 of 3) Function Signal I/O Description

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1.6 Pin Assignments

Figure 1.3 and Figure 1.4 show the pin assignments. Figure 1.3 Pin assignment fo r 100-pin LQFP (top view) Note 1. This pin should be left floating. R7FA6T1AD3CFP/ R7FA6T1AB3CFP

R01DS0375EU0100 Rev.1.00 Page 15 of 69 May 29, 2020 RA6T1 Datasheet 1. Overview Figure 1.4 Pin assignment for 64-pin LQFP (top view) Note 1. This pin should be left floating. P501 VCC VSS P015 VREFL VREFH AVCC0 AVSS0 VREFL0 VREFH0 P003 P002 P001 P014 P300/TCK/SWCLK P301 P302 VCC VSS P201/MD RES P210 P205 P206 P207 VCC VSS P200 P100 P102 P103 P104 P105 P106 P107 VCL VSS VCC P112 P111 P110/TDI P108/TMS/SWDIO P101 P109/TDO P400 P402 VCC VCL0 XCIN XCOUT VSS P213/XTAL P212/EXTAL VCC P411 P410 P408 P407 P401 P409 P000 R7FA6T1AD3CFM/ R7FA6T1AB3CFM P500 NC NC*1

R01DS0375EU0100 Rev.1.00 Page 16 of 69 May 29, 2020 RA6T1 Datasheet 1. Overview

1.7 Pin Lists

Power, System, Clock, Debug, CAC Interrupt I/O port Timers Communication interfaces Analog LQFP100 LQFP64 AGT GPT GPT CAN SCI0,2,4,8 (30 MHz) SCI1,3,9 (30 MHz) IIC SPI ADC12 DAC12, ACMPHS 1 1 - IRQ0 P400 AGTIO1 - GTIOC6A - SCK4 - SCL0_A - ADTRG1 - 2 2 - IRQ5-DS P401 - GTETRGA GTIOC6B CTX0 CTS4_RTS4/S -S D A 0 _ A - - - 3 3 CACREF IRQ4-DS P402 AGTIO0/AGTI 4 - - - P403 AGTIO0/AGTI 13 9 XTAL IRQ2 P213 - GTETRGC GTIOC0A - - TXD1/MOSI1/S DA1 -- A D T R G 1 - 14 10 EXTAL IRQ3 P212 AGTEE1 GTETRGD GTIOC0B - - RXD1/MISO1/S CL1 -- - - 16 - CACREF IRQ11 P708 - - - - - RXD1/MISO1/S CL1 -S S L A 3 _ B - - 17 - - IRQ8 P415 - - GTIOC0A - - - - SSLA2_B - - 18 - - IRQ9 P414 - - GTIOC0B - - - - SSLA1_B - - 19 - - - P413 - GTOUUP - - CTS0_RTS0/S -- S S L A 0 _ B - - 2 0 - - -P 4 1 2 A G T E E 1 G T O U L O - -S C K 0 - -R S P C K A _ B - - 21 12 - IRQ4 P411 AGTOA1 GTOVUP GTIOC9A - TXD0/MOSI0/S DA0 CTS3_RTS3/S -M O S I A _ B - - 22 13 - IRQ5 P410 AGTOB1 GTOVLO GTIOC9B - RXD0/MISO0/S CL0 SCK3 - MISOA_B - - 23 14 - IRQ6 P409 - GTOWUP GTIOC10A - - TXD3/MOSI3/S DA3 -- - - 24 15 - IRQ7 P408 - GTOWLO GTIOC10B - - RXD3/MISO3/S CL3 SCL0_B - - - 25 16 - - P407 AGTIO0 - - - CTS4_RTS4/S -S D A 0 _ B - A D T R G 0 - 31 22 - IRQ0-DS P206 - GTIU - - RXD4/MISO4/S CL4 -S D A 1 _ A - - - 32 23 CLKOUT IRQ1-DS P205 AGTO1 GTIV GTIOC4A - TXD4/MOSI4/S DA4 CTS9_RTS9/S SCL1_A - - - 33 - TRCLK - P214 - GTIU - - - - - - - - 34 - TRDATA0 - P211 - GTIV - - - - - - - - 35 24 TRDATA1 - P210 - GTIW - - - - - - - - 36 - TRDATA2 - P209 - GTOVUP - - - - - - - - 37 - TRDATA3 - P208 - GTOVLO - - - - - - - - 44 - - IRQ9 P304 - GTOWLO GTIOC7A - - - - - - - 48 30 - IRQ5 P302 - GTOUUP GTIOC4A - TXD2/MOSI2/S DA2 -- S S L B 3 _ B - - 49 31 - IRQ6 P301 AGTIO0 GTOULO GTIOC4B - RXD2/MISO2/S CL2 CTS9_RTS9/S -S S L B 2 _ B - - 50 32 TCK/SWCLK - P300 - GTOUUP GTIOC0A_A - - - - SSLB1_B - - 51 33 TMS/SWDIO - P108 - GTOULO GTIOC0B_A - - CTS9_RTS9/S -S S L B 0 _ B - - 52 34 CLKOUT/TDO/ SWO - P109 - GTOVUP GTIOC1A_A - - TXD9/MOSI9/S DA9 -M O S I B _ B - - 53 35 TDI IRQ3 P110 - GTOVLO GTIOC1B_A - CTS2_RTS2/S RXD9/MISO9/S CL9 - MISOB_B - VCOUT 54 36 - IRQ4 P111 - - GTIOC3A_A - SCK2 SCK9 - RSPCKB_B - - 55 37 - - P112 - - GTIOC3B_A - TXD2/MOSI2/S DA2 SCK1 - SSLB0_B - - 56 - - - P113 - - GTIOC2A - RXD2/MISO2/S CL2 -- - - -

R01DS0375EU0100 Rev.1.00 Page 17 of 69 May 29, 2020 RA6T1 Datasheet 1. Overview Note: Some pin names have the added suffix of _A and _B. When as signing the GPT, IIC, and SPI functionality, select the functional pins with the same suffix. 6 5 - - -P 6 0 2 - - G T I O C 7 B -- T X D 9 -- - - 6 6 - - -P 6 0 1 - - G T I O C 6 A -- R X D 9 -- - - 67 - CLKOUT/CAC REF -P 6 0 0 - - G T I O C 6 B -- S C K 9 -- - - 68 41 - KR07 P107 AGTOA0 - GTIOC8A - CTS8_RTS8/S -- - - - 69 42 - KR06 P106 AGTOB0 - GTIOC8B - SCK8 - - SSLA3_A - - 70 43 - IRQ0/KR05 P105 - GTETRGA GTIOC1A - TXD8/MOSI8/S DA8 -- S S L A 2 _ A - - 71 44 - IRQ1/KR04 P104 - GTETRGB GTIOC1B - RXD8/MISO8/S CL8 -- S S L A 1 _ A - - 72 45 - KR03 P103 - GTOWUP GTIOC2A_A CTX0 CTS0_RTS0/S -- S S L A 0 _ A - - 73 46 - KR02 P102 AGTO0 GTOWLO GTIOC2B_A CRX0 SCK0 - - RSPCKA_A ADTRG0 - 74 47 - IRQ1/KR01 P101 AGTEE0 GTETRGB GTIOC5A - TXD0/MOSI0/S DA0 CTS1_RTS1/S SDA1_B MOSIA_A - - 75 48 - IRQ2/KR00 P100 AGTIO0 GTETRGA GTIOC5B - RXD0/MISO0/S CL0 SCK1 SCL1_B MISOA_A - - 76 49 - - P500 AGTOA0 GTIU GTIOC11A - - - - - AN016 IVREF0 77 50 - IRQ11 P501 AGTOB0 GTIV GTIOC11B - - - - - AN116 IVREF1 78 - - IRQ12 P502 - GTIW GTIOC12A - - - - - AN017 IVCMP0 79 - - - P503 - GTETRGC GTIOC12B - - - - - AN117 - 8 0 - - -P 5 0 4 - G T E T R G D - -- - -- A N 0 1 8 - 84 53 - IRQ13 P015 - - - - - - - - AN006/AN106 DA1/ IVCMP1 IVREF3 AN107 94 - - IRQ11-DS P006 - - - - - - - - AN102 IVCMP2 95 - - IRQ10-DS P005 - - - - - - - - AN101 IVCMP2 96 - - IRQ9-DS P004 - - - - - - - - AN100 IVCMP2 AN007 98 62 - IRQ8-DS P002 - - - - - - - - AN002 IVCMP2 99 63 - IRQ7-DS P001 - - - - - - - - AN001 IVCMP2 100 64 - IRQ6-DS P000 - - - - - - - - AN000 IVCMP2 Pin number Power, System, Clock, Debug, CAC Interrupt I/O port Timers Communication interfaces Analog LQFP100 LQFP64 AGT GPT GPT CAN SCI0,2,4,8 (30 MHz) SCI1,3,9 (30 MHz) IIC SPI ADC12 DAC12, ACMPHS

R01DS0375EU0100 Rev.1.00 Page 18 of 69 May 29, 2020 RA6T1 Datasheet 2. Electr ical Characteristics 2. Electrical Characteristics Unless otherwise specified, the electrical characteristics of the MCU are defined under the following conditions:  VCC = AVCC0 = 2.7 to 3.6 V  2.7 ≤ VREFH0/VREFH ≤ AVCC0  VSS = AVSS0 = VREFL0/VREFL= 0 V  Ta = Topr. Figure 2.1 shows the timing conditions. Figure 2.1 Input or output timing measurement conditions The measurement conditions for the timing specification of each peripheral are recommended for the best peripheral operation. However, make sure to adjust the driving abilities of each pin to meet the conditions of your system. Each function pin used for the same function must select the same drive ability. If the I/O drive ability of each function pin is mixed, the A/C specification of each function is not guaranteed.

2.1 Absolute Maximum Ratings

Caution: Permanent damage to the MCU might result if absolute maximum ratings are exceeded. Note 1. Ports P205, P206, P400, P401, P407 to P415, and P708 are 5 V tolerant. Note 2. Connect AVCC0 to VCC. Table 2.1 Absolute maximum ratings Parameter Symbol Value Unit Power supply voltage VCC -0.3 to +4.0 V Input voltage (except for 5 V-tolerant ports*1)V in -0.3 to VCC + 0.3 V Input voltage (5 V-tolerant ports*1)V in -0.3 to + VCC + 4.0 (max. 5.8) V Reference power supply voltage VREFH/VREFH0 -0.3 to AVCC0 + 0.3 V Analog power supply voltage AVCC0 * 2 -0.3 to +4.0 V Analog input voltage (except for P000 to P007) V AN -0.3 to AVCC0 + 0.3 V Analog input voltage (P000 to P007) when PGA pseudo- differential input is disabled VAN -0.3 to AVCC0 + 0.3 V Analog input voltage (P000 to P002, P004 to P006) when PGA pseudo-differential input is enabled VAN -1.3 to AVCC0 + 0.3 V Analog input voltage (P003, P007) when PGA pseudo- differential input is enabled VAN -0.8 to AVCC0 + 0.3 V Operating temperature*3, *4 Topr -40 to +105 °C Storage temperature T stg -55 to +125 °C For example P100 C VOH = VCC × 0.7, VOL = VCC × 0.3 VIH = VCC × 0.7, VIL = VCC × 0.3 Load capacitance C = 30 pF

R01DS0375EU0100 Rev.1.00 Page 19 of 69 May 29, 2020 RA6T1 Datasheet 2. Electr ical Characteristics Note 3. See section 2.2.1, Tj/Ta Definition. Note 4. Contact Renesas Electronics sales office for informati on on derating operation when Ta = +85°C to +105°C. Derating is the systematic reduction of load for improved reliability. Note 1. Connect AVCC0 to VCC. When the A/D converter, the D/A c onverter, or the comparator are not in use, do not leave the AVCC0, VREFH/VREFH0, AVSS0, and VREFL/VREFL0 pins open. Connect the AVCC0 and VREFH/VREFH0 pins to VCC, and the AVSS0 and VREFL/VREFL0 pins to VSS, respectively.

2.2 DC Characteristics

2.2.1 T j/Ta Definition

Note: Make sure that T j = Ta + θja × total power consumption (W), where total power consumption = (VCC - VOH) × ΣIOH + VOL × ΣIOL + ICCmax × VCC.

2.2.2 I/O V IH, VIL

Table 2.2 Recommended operating conditions Parameter Symbol Min Typ Max Unit Power supply voltages VCC 2.7 - 3.6 V VSS - 0 - V Analog power supply voltages AVCC0* 1 -V C C -V AVSS0 - 0 - V Table 2.3 DC characteristics Conditions: Products with operating temperature (Ta) -40 to +105°C. Parameter Symbol Typ Max Unit Test conditions Permissible junction temperature 100-pin LQFP 64-pin LQFP Tj - 125 °C High-speed mode Low-speed mode Subosc-speed mode. Table 2.4 I/O V IH, VIL (1 of 2) Parameter Symbo l Min Typ Max Unit Input voltage (except for Schmitt trigger input pins) Peripheral function pin EXTAL(external clock input), SPI (except RSPCK) V IH VCC × 0.8 - - V VIL - - VCC × 0.2 IIC (SMBus)*1 VIH 2.1 - - VIL -- 0 . 8 IIC (SMBus)*2 VIH 2.1 - VCC + 3.6 (max 5.8) VIL -- 0 . 8 Schmitt trigger input voltage IIC (except for SMBus)*1 VIH VCC × 0.7 - - VIL - - VCC × 0.3 ΔVT VCC × 0.05 - - IIC (except for SMBus)*2 VIH VCC × 0.7 - VCC + 3.6 (max 5.8) VIL - - VCC × 0.3 ΔVT VCC × 0.05 - - 5 V-tolerant ports*3, *7 VIH VCC × 0.8 - VCC + 3.6 (max 5.8) VIL - - VCC × 0.2 ΔVT VCC × 0.05 - -

R01DS0375EU0100 Rev.1.00 Page 20 of 69 May 29, 2020 RA6T1 Datasheet 2. Electr ical Characteristics Note 1. SCL1_B, SDA1_B (total 2 pins). Note 2. SCL0_A, SDA0_A, SCL0_B, SDA0_B, SCL1_A, SDA1_A (total 6 pins). Note 3. RES and peripheral function pins associated with P205, P206, P400, P401, P407 to P415, P708 (total 15 pins). Note 4. All input pins except for the peripheral function pins already described in the table. Note 5. P205, P206, P400, P401, P407 to P415, P708 (total 14 pins). Note 6. All input pins except for t he ports already described in the table. Note 7. When VCC is less than 2.7 V, the input voltage of 5 V-to lerant ports should be less than 3.6 V, otherwise breakdown may occur because 5 V-tolerant ports are electrically controlled so as not to violate the breakdown voltage.

2.2.3 I/O I OH, IOL

P402/AGTIO0,1 P403/AGTIO0,1 V IH VCC × 0.8 - VCC + 0.3 V VIL - - VCC × 0.2 ΔVT VCC × 0.05 - - Other input pins*4 VIH VCC × 0.8 - - VIL - - VCC × 0.2 ΔVT VCC × 0.05 - - Ports 5 V-tolerant ports* 5, *7 VIH VCC × 0.8 - VCC + 3.6 (max 5.8) VIL - - VCC × 0.2 Other input pins*6 VIH VCC × 0.8 - - VIL - - VCC × 0.2 Table 2.5 I/O I OH, IOL (1 of 2) Parameter Symbol Min Typ Max Unit Permissible output current (average value per pin) Ports P008, P201 - I OH --- 2 . 0 m A IOL --2 . 0 m A Ports P014, P015 - I OH --- 4 . 0 m A IOL --4 . 0 m A Ports P205, P206, P407 to P415, P602, P708 (total 13 pins) Low drive*1 IOH --- 2 . 0 m A IOL --2 . 0 m A Middle drive*2 IOH --- 4 . 0 m A IOL --4 . 0 m A High drive*3 IOH --- 2 0 m A IOL --2 0m A Other output pins*4 Low drive*1 IOH --- 2 . 0 m A IOL --2 . 0 m A Middle drive*2 IOH --- 4 . 0 m A IOL --4 . 0 m A High drive*3 IOH --- 1 6 m A IOL --1 6m A Table 2.4 I/O V IH, VIL (2 of 2) Parameter Symbo l Min Typ Max Unit

R01DS0375EU0100 Rev.1.00 Page 21 of 69 May 29, 2020 RA6T1 Datasheet 2. Electr ical Characteristics Caution: To protect the reliability of the MCU, the output cu rrent values should not exceed the values in this table. The average output current indicates the average value of current measured during 100 μs. Note 1. This is the value when low driving abi lity is selected in the Port Drive Capability bit in the PmnPFS register. The selected driving ability is retained in Deep Software Standby mode. Note 2. This is the value when middle drivi ng ability is selected in the Port Drive Capability bit in the PmnPFS register. The selected driving ability is retained in Deep Software Standby mode. Note 3. This is the value when high driving ability is selected in the Port Drive Capability bit in the PmnPFS register. The selected driving ability is retained in Deep Software Standby mode. Note 4. Except for P000 to P007, P200, which are input ports.

2.2.4 I/O V OH, VOL, and Other Characteristics

Permissible output current (max value per pin) Ports P008, P201 - I OH --- 4 . 0 m A IOL --4 . 0 m A Ports P014, P015 - I OH --- 8 . 0 m A IOL --8 . 0 m A Ports P205, P206, P407 to P415, P602, P708 (total 13 pins) Low drive*1 IOH --- 4 . 0 m A IOL --4 . 0 m A Middle drive*2 IOH --- 8 . 0 m A IOL --8 . 0 m A High drive*3 IOH --- 4 0 m A IOL --4 0m A Other output pins*4 Low drive*1 IOH --- 4 . 0 m A IOL --4 . 0 m A Middle drive*2 IOH --- 8 . 0 m A IOL --8 . 0 m A High drive*3 IOH --- 3 2 m A IOL --3 2m A Permissible output current (max value of total of all pins) Maximum of all output pins ΣIOH (max) --- 8 0 m A ΣIOL (max) --8 0m A Table 2.6 I/O V OH, VOL, and other characteristics (1 of 2) Parameter Symbol Min Typ Max Unit Test conditions Output voltage IIC V OL -- 0 . 4 V I OL = 3.0 mA VOL -- 0 . 6 I OL = 6.0 mA IIC*1 VOL -- 0 . 4 I OL = 15.0 mA (ICFER.FMPE = 1) VOL -0 . 4 - I OL = 20.0 mA (ICFER.FMPE = 1) Ports P205, P206, P407 to P415, P602, P708 (total of 13 pins)*2 VOH VCC - 1.0 - - I OH = -20 mA VCC = 3.3 V VOL -- 1 . 0 I OL = 20 mA VCC = 3.3 V Other output pins V OH VCC - 0.5 - - I OH = -1.0 mA VOL -- 0 . 5 I OL = 1.0 mA Input leakage current RES |I in|- - 5 . 0 μAV in = 0 V Vin = 5.5 V Ports P000 to P002, P004 to P006, P200 -- 1 . 0 V in = 0 V Vin = VCC Ports P003, P007 Before initialization*3 -- 4 5 . 0 V in = 0 V Vin = VCC After initialization*4 -- 1 . 0 V in = 0 V Vin = VCC Table 2.5 I/O I OH, IOL (2 of 2) Parameter Symbol Min Typ Max Unit

R01DS0375EU0100 Rev.1.00 Page 22 of 69 May 29, 2020 RA6T1 Datasheet 2. Electr ical Characteristics Note 1. SCL0_A, SDA0_A (total 2 pins). Note 2. This is the value when high drivi ng ability is selected in the Port Drive Capability bit in the PmnPFS register. The selected driving ability is retained in Deep Software Standby mode. Note 3. P0nPFS.ASEL(n = 3 or 7) = 1 Note 4. P0nPFS.ASEL(n = 3 or 7) = 0

2.2.5 Operating and Standby Current

current (off state) 5 V-tolerant ports |I TSI|- - 5 . 0 μAV in = 0 V Vin = 5.5 V Other ports (except for ports P000 to P007, P200) -- 1 . 0 V in = 0 V Vin = VCC Input pull-up MOS current Ports P0 to P7 (except for ports P000 to P007) Ip -300 - -10 μA VCC = 2.7 to 3.6 V Vin = 0 V Input capacitance Ports P003, P007, P014, P015, P400, P401 Cin - - 16 pF Vbias = 0 V Vamp = 20 mV f = 1 MHz T a = 25°COther input pins - - 8 Table 2.7 Operating and standby current (1 of 2) Parameter Symbol Min Typ Max Unit Test conditions Supply current*1 High-speed mode Maximum*2 ICC*3 - - 87 mA ICLK = 120 MHz PCLKA = 120 MHz PCLKB = 60 MHz PCLKC = 60 MHz PCLKD = 120 MHz FCLK = 60 MHz CoreMark ®*5 -1 7 - Normal mode All peripheral clocks enabled, while (1) code executing from flash* -2 4 - All peripheral clocks disabled, while (1) code executing from flash*5, *6 -1 2 - Sleep mode*5, *6 - 9 33.5 Increase during BGO operation Data flash P/E - 6 - Code flash P/E - 8 - Low-speed mode*5 -1 . 2 - I C L K = 1 M H z Subosc-speed mode*5 - 1.0 - ICLK = 32.768 kHz Software Standby mode - 1.3 13 Ta ≤ 85°C -1 . 3 2 1 T a ≤ 105°C Deep Software Standby mode DPSBYCR.DEEPCUT[1:0] = 00b*8 -2 8 6 5 μAT a ≤ 85°C -2 8 9 3 T a ≤ 105°C DPSBYCR.DEEPCUT[1:0] = 01b*8 - 11.6 28 Ta ≤ 85°C - 11.6 32 Ta ≤ 105°C DPSBYCR.DEEPCUT[1:0] = 11b*8 -4 . 9 2 1 T a ≤ 85°C -4 . 9 2 6 T a ≤ 105°C Increase when the AGT is operating When the low-speed on-chip oscillator (LOCO) is in use -4 . 4 - - When a crystal oscillator for low clock loads is in use -1 . 0 - - When a crystal oscillator for standard clock loads is in use -1 . 4 - - Analog power supply current During 12-bit A/D conversion AI CC -0 . 8 1 . 1 m A - During 12-bit A/D conversion with S/H amp - 2.3 3.3 mA - PGA (1ch) - 1 3 mA - ACMPHS (1 unit) - 100 150 µA - Temperature sensor - 0.1 0.2 mA - During D/A conversion (per unit) Without AMP output - 0.1 0.2 mA - With AMP output - 0.6 1.1 mA - Waiting for A/D, D/A conversion (all units) - 0.9 1.6 mA - ADC12, DAC12 in standby modes (all units)* 7 -2 8 µ A - Table 2.6 I/O V OH, VOL, and other characteristics (2 of 2) Parameter Symbol Min Typ Max Unit Test conditions

R01DS0375EU0100 Rev.1.00 Page 23 of 69 May 29, 2020 RA6T1 Datasheet 2. Electr ical Characteristics Note 1. Supply current values are with all output pins unloaded and all input pull-up MOS transistors in the off state. Note 2. Measured with clocks supplied to the peripheral functions. This does not include the BGO operation. Note 3. I CC depends on f (ICLK) as follows. (ICLK:PCLKA:PCLKB:PCLKC:PCLKD = 2:2:1:1:2) ICC Max. = 0.53 x f + 23 (maximum operation in High-speed mode) ICC Typ. = 0.08 x f + 2.4 (normal operation in High-speed mode) ICC Typ. = 0.1 x f + 1.1 (Low-speed mode) ICC Max. = 0.09 x f + 23 (Sleep mode). Note 4. This does not include the BGO operation. Note 5. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation. Note 6. FCLK, PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (3.75 MHz). Note 7. When the MCU is in Software Standby mode or the MS TPCRD.MSTPD16 (12-bit A/D Converter 0 Module Stop bit) and MSTPCRD.MSTPD15 (12-bit A/D Converter 1 Module Stop bit) are in the module-stop state. See section 35.6.8, Available functions and register settings of AN000 to AN002, AN007, AN100 to AN102, and AN107 in User’s Manual. Note 8. For more information on the DBSBYCR register, see sect ion 11.2.11, Deep Software Standby Control Register (DPSBYCR) in User’s Manual. Figure 2.2 Temperature dependency in Software Standby mode (reference data) Reference power supply current (VREFH0) During 12-bit A/D conversion (unit 0) AIREFH0 - 70 120 μA- Waiting for 12-bit A/D conversion (unit 0) - 0.07 0.5 μA- ADC12 in standby modes (unit 0) - 0.07 0.5 µA - Reference power supply current (VREFH) During 12-bit A/D conversion (unit 1) AIREFH - 70 120 µA - During D/A conversion (per unit) Without AMP output - 0.1 0.4 mA - With AMP ouput - 0.1 0.4 mA - Waiting for 12-bit A/D (unit 1), D/A (all units) conversion - 0.07 0.8 µA - ADC12 unit 1 in standby modes - 0.07 0.8 µA - Table 2.7 Operating and standby current (2 of 2) Parameter Symbol Min Typ Max Unit Test conditions

R01DS0375EU0100 Rev.1.00 Page 25 of 69 May 29, 2020 RA6T1 Datasheet 2. Electr ical Characteristics

2.2.6 VCC Rise and Fall Gr adient and Ripple Frequency

Note 1. At boot mode, the reset from voltage monitor 0 is disabled regardless of the value of the OFS1.LVDAS bit. Figure 2.5 Ripple waveform

2.3 AC Characteristics

2.3.1 Frequency

Note 1. FCLK must run at a frequency of at least 4 MHz when programming or erasing the flash memory. Note 2. See section 9, Clock Generation Ci rcuit in User’s Manual for the relationship between the ICLK, PCLKA, PCLKB, PCLKC, PCLKD, and FCLK frequencies. Note 3. When the ADC12 is used, the PCLKC frequency must be at least 1 MHz. Table 2.8 Rising gradie nt characteristics Parameter Symbol Min Typ Max Unit Test conditions VCC rising gradient Voltage monitor 0 reset disabled at startup SrVCC 0.0084 - 20 ms/V - Voltage monitor 0 reset enabled at startup 0.0084 - - - SCI boot mode*1 0.0084 - 20 - Table 2.9 Rise and fall gradient and ripple frequency characteristics The ripple voltage must meet the allowable ripple frequency fr(VCC) within the range between the VCC upper limit (3.6 V) and lower limit (2.7 V). When the VCC change exceeds VCC ±10%, the allowable voltage change rising and falling gradient dt/dVCC must be met. Parameter Symbol Min Typ Max Unit Test conditions Allowable ripple frequency f r (VCC) --1 0 k H z Figure 2.5 Vr (VCC) ≤ VCC × 0.2 --1 M H z Figure 2.5 Vr (VCC) ≤ VCC × 0.08 --1 0 M H z Figure 2.5 Vr (VCC) ≤ VCC × 0.06 Allowable voltage change rising and falling gradient dt/dVCC 1.0 - - ms/V When VCC change exceeds VCC ±10% Table 2.10 Operation frequency value in high-speed mode Parameter Symbol Min Typ Max Unit Operation frequency Sy stem clock (ICLK*2) f - - 120 MHz Peripheral module clock (PCLKA)*2 - - 120 Peripheral module clock (PCLKB)*2 --6 0 Peripheral module clock (PCLKC)*2 -*3 -6 0 Peripheral module clock (PCLKD)*2 - - 120 Flash interface clock (FCLK)*2 -*1 -6 0 Vr( VCC)VCC 1/fr(VCC)

R01DS0375EU0100 Rev.1.00 Page 26 of 69 May 29, 2020 RA6T1 Datasheet 2. Electr ical Characteristics Note 1. Programming or erasing the flas h memory is disabled in Low-speed mode. Note 2. See section 9, Clock Generation Ci rcuit in User’s Manual for the relationship between the ICLK, PCLKA, PCLKB, PCLKC, PCLKD, and FCLK frequencies. Note 3. When the ADC12 is used, the PCLKC frequency must be set to at least 1 MHz. Note 1. Programming or erasing the flash memory is disabled in Subosc-speed mode. Note 2. See section 9, Clock Generation Ci rcuit in User’s Manual for the relationship between the ICLK, PCLKA, PCLKB, PCLKC, PCLKD, and FCLK frequencies. Note 3. The ADC12 cannot be used.

2.3.2 Clock Timing

Table 2.11 Operation frequency value in low-speed mode Parameter Symbol Min Typ Max Unit Operation frequency Syst em clock (ICLK)*2 f--1 M H z Peripheral module clock (PCLKA)*2 --1 Peripheral module clock (PCLKB)*2 --1 Peripheral module clock (PCLKC)*2,*3 -*3 -1 Peripheral module clock (PCLKD)*2 --1 Flash interface clock (FCLK)*1, *2 --1 Table 2.12 Operation frequency value in Subosc-speed mode Parameter Symbol Min Typ Max Unit Operation frequency Syst em clock (ICLK)* 2 f 29.4 - 36.1 kHz Peripheral module clock (PCLKA)*2 - - 36.1 Peripheral module clock (PCLKB)*2 - - 36.1 Peripheral module clock (PCLKC)*2,*3 - - 36.1 Peripheral module clock (PCLKD)*2 - - 36.1 Flash interface clock (FCLK)*1, *2 29.4 - 36.1 Table 2.13 Clock timing except for sub-clock oscillator (1 of 2) Parameter Symbol Min Typ Max Unit Test conditions EXTAL external clock input cycle time t EXcyc 41.66 - - ns Figure 2.6 EXTAL external clock input high pulse width t EXH 15.83 - - ns EXTAL external clock input low pulse width t EXL 15.83 - - ns EXTAL external clock rise time t EXr -- 5 . 0 n s EXTAL external clock fall time t EXf -- 5 . 0 n s Main clock oscillator frequency f MAIN 8- 2 4 M H z - Main clock oscillation stabilization wait time (crystal) *1 tMAINOSCWT -- - * 1 ms Figure 2.7 LOCO clock oscillation frequency f LOCO 29.4912 32.768 36.0448 kHz - LOCO clock oscillation stabilization wait time t LOCOWT - - 60.4 μs Figure 2.8 ILOCO clock oscillation frequency f ILOCO 13.5 15 16.5 kHz - MOCO clock oscillation frequency F MOCO 6.8 8 9.2 MHz - MOCO clock oscillation stabilization wait time t MOCOWT - - 15.0 μs-

R01DS0375EU0100 Rev.1.00 Page 27 of 69 May 29, 2020 RA6T1 Datasheet 2. Electr ical Characteristics Note 1. When setting up the main clock oscill ator, ask the oscillator manufacturer for an oscillation evaluation, and use the results as the recommended oscillation stabilization time. Set the MOSCWTCR register to a value equal to or greater than the recommended value. After changing the setting in the MOSCCR.MOSTP bit to start main clock operation, read the OSCSF.MOSCSF flag to confirm that it is 1, and then start using the main clock oscillator. Note 2. This is the time from release from reset state until the HOCO oscillation frequency (fHOCO) reaches the range for guaranteed operation. Note 1. When setting up the sub-clock oscill ator, ask the oscillator manufacturer for an oscillation evaluation and use the results as the recommended oscillation stabilization time. After changing the setting in the SOSCCR.SOSTP bit to start sub-clock operation, only start using the sub-clock oscillator after the sub-clock oscillation stabilization time elapses with an adequate margin. A value that is two times the value shown is recommended. Figure 2.6 EXTAL external clock input timing HOCO clock oscillator oscillation frequency Without FLL f HOCO16 15.78 16 16.22 MHz -20 ≤ Ta ≤ 105°C fHOCO18 17.75 18 18.25 fHOCO20 19.72 20 20.28 fHOCO16 15.71 16 16.29 -40 ≤ Ta ≤ -20°C fHOCO18 17.68 18 18.32 fHOCO20 19.64 20 20.36 With FLL f HOCO16 15.955 16 16.045 -40 ≤ Ta ≤ 105°C Sub-clock frequency accuracy is ±50 ppm. f HOCO18 17.949 18 18.051 fHOCO20 19.944 20 20.056 HOCO clock oscillation stabilization wait time*2 tHOCOWT - - 64.7 μs- FLL stabilization wait time t FLLWT -- 1 . 8 m s - PLL clock frequency f PLL 120 - 240 MHz - PLL clock oscillation stabilization wait time t PLLWT - - 174.9 μs Figure 2.9 Table 2.14 Clock timing fo r the sub-clock oscillator Parameter Symbol Min Typ Max Unit Test conditions Sub-clock frequency f SUB - 32.768 - kHz - Sub-clock oscillation stabilization wait time t SUBOSCWT --- * 1 s Figure 2.10 Table 2.13 Clock timing except for sub-clock oscillator (2 of 2) Parameter Symbol Min Typ Max Unit Test conditions tEXH tEXcyc EXTAL external clock input VCC × 0.5 tEXL tEXr tEXf

R01DS0375EU0100 Rev.1.00 Page 29 of 69 May 29, 2020 RA6T1 Datasheet 2. Electr ical Characteristics

2.3.3 Reset Timing

Figure 2.11 Power-on reset timing Figure 2.12 Reset input timing Table 2.15 Reset timing Parameter Symbol Min Typ Max Unit Test conditions RES pulse width Power-on t RESWP 1- - m s Figure 2.11 Deep Software Standby mode t RESWD 0.6 - - ms Figure 2.12 Software Standby mode, Subosc-speed mode tRESWS 0.3 - - ms All other t RESW 200 - - μs Wait time after RES cancellation t RESWT -2 9 3 2 μs Figure 2.11 Wait time after internal reset cancellation (IWDT reset, WDT reset, software reset, SRAM parity error reset, bus master MPU error reset, bus slave MPU error reset, stack pointer error reset) tRESW2 - 320 390 μs- VCC RES Internal reset signal (active-low) tRESWP tRESWT RES Internal reset signal (active-low) tRESWD, tRESWS, tRESW tRESWT

R01DS0375EU0100 Rev.1.00 Page 30 of 69 May 29, 2020 RA6T1 Datasheet 2. Electr ical Characteristics

2.3.4 Wakeup Timing

Note 1. The recovery time is determined by the system clock source. When multiple oscillators are active, the recovery time can be determined with the following equation: Total recovery time = recovery time for an oscillator as the system clock source + the longest oscillation stabilization time of any oscillators requiring longer stabilization times than the system clock source + 2 LOCO cycles (when LOCO is operating) + 3 SOSC cycles (when Subosc is oscillating and MSTPC0 = 0 (CAC module stop)). Note 2. When the frequency of the crystal is 24 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h). For other settings (MOSCWTCR is set to Xh), the recovery time can be determined with the following equation: tSBYMC (MOSCWTCR = Xh) = tSBYMC (MOSCWTCR = 05h) + (tMAINOSCWT (MOSCWTCR = Xh) - tMAINOSCWT (MOSCWTCR = 05h)) Note 3. When the frequency of PLL is 240 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h). For other settings (MOSCWTCR is set to Xh), the recovery time can be determined with the following equation: tSBYMC (MOSCWTCR = Xh) = tSBYMC (MOSCWTCR = 05h) + (tMAINOSCWT (MOSCWTCR = Xh) - tMAINOSCWT (MOSCWTCR = 05h)) Note 4. When the frequency of the external cloc k is 24 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h). For other settings (MOSCWTCR is set to Xh), the recovery time can be determined with the following equation: tSBYMC (MOSCWTCR = Xh) = tSBYMC (MOSCWTCR = 00h) + (tMAINOSCWT (MOSCWTCR = Xh) - tMAINOSCWT (MOSCWTCR = 00h)) Note 5. When the frequency of PLL is 240 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h). For other settings (MOSCWTCR is set to Xh), the recovery time can be determined with the following equation: tSBYMC (MOSCWTCR = Xh) = tSBYMC (MOSCWTCR = 00h) + (tMAINOSCWT (MOSCWTCR = Xh) - tMAINOSCWT (MOSCWTCR = 00h)) Note 6. The HOCO frequency is 20 MHz. Note 7. The MOCO frequency is 8 MHz. Note 8. In Subosc-speed mode, the sub-clock oscillator or LOCO continues oscillating in Software Standby mode. Note 9. When the SNZCR.RXDREQEN bit is set to 0, the fo llowing time is added as the power supply recovery time: STCONR.STCON[1:0] = 00b:16 µs (typical), 34 µs (maximum) STCONR.STCON[1:0] = 11b:16 µs (typical), 104 µs (maximum). Note 10. When the SNZCR.RXDREQEN bit is set to 0, 16 μs (typical) or 18 μs (maximum) is added as the HOCO wait time. Table 2.16 Timing of recovery from low power modes Parameter Symbol Min Typ Max Unit Test conditions Recovery time from Software Standby mode*1 Crystal resonator connected to main clock oscillator System clock source is main clock oscillator* tSBYMC - 2 . 4 * 9 2.8*9 ms Figure 2.13 The division ratio of all oscillators is 1.System clock source is PLL with main clock oscillator*3 tSBYPC - 2 . 7 * 9 3.2*9 ms External clock input to main clock oscillator System clock source is main clock oscillator* tSBYEX - 230* 9 280*9 μs System clock source is PLL with main clock oscillator*5 tSBYPE - 570* 9 700*9 μs System clock source is sub-clock oscillator*8 tSBYSC -1 . 2 * 9 1.3*9 ms System clock source is LOCO*8 tSBYLO -1 . 2 * 9 1.4*9 ms System clock source is HOCO*6 tSBYHO - 240* 9, *10 300 *9, *10 µs System clock source is MOCO*7 tSBYMO - 220* 9 300*9 µs Recovery time from Deep Software Standby mode t DSBY - 0.65 1.0 ms Figure 2.14 Wait time after cancellation of Deep Software Standby mode t DSBYWT 34 - 35 t cyc Recovery time from Software Standby mode to Snooze mode High-speed mode when system clock source is HOCO (20 MHz) t SNZ - 3 5 * 9, *10 70 *9, *10 μs Figure 2.15 High-speed mode when system clock source is MOCO (8 MHz) tSNZ -1 1 * 9 14*9 μs

R01DS0375EU0100 Rev.1.00 Page 32 of 69 May 29, 2020 RA6T1 Datasheet 2. Electr ical Characteristics Figure 2.15 Recovery timing from Software Standby mode to Snooze mode

2.3.5 NMI and IRQ Noise Filter

Note: 200 ns minimum in Software Standby mode. Note: If the clock source is switched, add 4 clock cycles of the switched source. Note 1. t Pcyc indicates the PCLKB cycle. Note 2. t NMICK indicates the cycle of the NMI digital filter sampling clock. Note 3. t IRQCK indicates the cycle of the IRQi digital filter sampling clock. Figure 2.16 NMI interrupt input timing Figure 2.17 IRQ interrupt input timing Table 2.17 NMI and IRQ noise filter Parameter Symbol Min Typ Max Unit Test conditions NMI pulse width t NMIW 200 - - ns NMI digital filter disabled t Pcyc × 2 ≤ 200 ns tPcyc × 2*1 -- t Pcyc × 2 > 200 ns 200 - - NMI digital filter enabled t NMICK × 3 ≤ 200 ns tNMICK × 3.5*2 -- t NMICK × 3 > 200 ns IRQ pulse width t IRQW 200 - - ns IRQ digital filter disabled t Pcyc × 2 ≤ 200 ns tPcyc × 2*1 -- t Pcyc × 2 > 200 ns 200 - - IRQ digital filter enabled t IRQCK × 3 ≤ 200 ns tIRQCK × 3.5*3 -- t IRQCK × 3 > 200 ns tSNZ IRQ ICLK(to DTC, SRAM)*1 PCLK ICLK(except DTC, SRAM) Oscillator Software Standby mode Snooze mode Note 1. When SNZCR.SNZDTCEN is set to 1, ICLK is supplied to DTC and SRAM. tNMIW NMI tIRQW IRQ

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2.3.6 I/O Ports, POEG, GPT32, AGT, KINT, and ADC12 Trigger Timing

Note: t Pcyc: PCLKB cycle, tPDcyc: PCLKD cycle. Note 1. This skew applies when the same driver I/O is used. If the I/O of the middle and high drivers is mixed, operation is not guaranteed. Note 2. The load is 30 pF. Note 3. Constraints on input cycle: When not switching the source clock: tPcyc × 2 < tACYC should be satisfied. When switching the source clock: tPcyc × 6 < tACYC should be satisfied. Figure 2.18 I/O ports input timing Figure 2.19 POEG in put trigger timing Table 2.18 I/O ports, POEG, GPT32, AGT, KINT, and ADC12 trigger timing GPT32 conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register. AGT conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register. Parameter Symbol Min Max Unit Test conditions I/O ports Input data pulse width t PRW 1.5 - t Pcyc Figure 2.18 POEG POEG input trigger pulse width t POEW 3- t Pcyc Figure 2.19 GPT32 Input capture pulse width Single edge t GTICW 1.5 - t PDcyc Figure 2.20 Dual edge 2.5 - GTIOCxY output skew (x = 0 to 7, Y= A or B) Middle drive buffer t GTISK*1 -4 n s Figure 2.21 High drive buffer - 4 GTIOCxY output skew (x = 8 to 12, Y = A or B) Middle drive buffer - 4 High drive buffer - 4 GTIOCxY output skew (x = 0 to 12, Y = A or B) Middle drive buffer - 6 High drive buffer - 6 OPS output skew GTOUUP, GTOULO, GTOVUP , GTOVLO, GTOWUP , GTOWLO tGTOSK -5 n s Figure 2.22 GPT (PWM Delay Generation Circuit) GTIOCxY_Z output skew (x = 0 to 3, Y = A or B, Z = A) t HRSK*2 -2 . 0 n s Figure 2.23 AGT AGTIO, AGTEE input cycle t ACYC*3 100 - ns Figure 2.24 AGTIO, AGTEE input high width, low width t ACKWH, tACKWL 40 - ns AGTIO, AGTO, AGTOA, AGTOB output cycle t ACYC2 62.5 - ns ADC12 ADC12 trigger input pulse width t TRGW 1.5 - t Pcyc Figure 2.25 KINT KRn(n = 00 to 07) pulse width t KR 250 - ns Figure 2.26 Port tPRW POEG input trigger tPOEW

R01DS0375EU0100 Rev.1.00 Page 35 of 69 May 29, 2020 RA6T1 Datasheet 2. Electr ical Characteristics Figure 2.24 AGT input/output timing Figure 2.25 ADC12 trigger input timing Figure 2.26 Key inte rrupt input timing

2.3.7 PWM Delay Generation Circuit Timing

Note 1. This value normaliz es the differences between lines in 1-LSB resolution.

2.3.8 CAC Timing

Table 2.19 PWM Delay Gene ration Circuit timing Parameter Min Typ Max Unit Test conditions Operation frequency 80 - 120 MHz - Resolution - 260 - ps PCLKD = 120 MHz DNL*1 - ±2.0 - LSB - Table 2.20 CAC timing Parameter Symbol Min Typ Max Unit Test conditions CAC CACREF input pulse width t PBcyc ≤ tcac*2 tCACREF 4.5 × tcac + 3 × tPBcyc --n s - tPBcyc > tcac*2 5 × tcac + 6.5 × tPBcyc --n s tACYC2 AGTIO, AGTEE (input) tACYC tACKWL tACKWH AGTIO, AGTO, AGTOA, AGTOB (output) ADTRG0, ADTRG1 tTRGW KR00 to KR07 tKR

R01DS0375EU0100 Rev.1.00 Page 36 of 69 May 29, 2020 RA6T1 Datasheet 2. Electr ical Characteristics Note 1. t PBcyc: PCLKB cycle. Note 2. t cac: CAC count clock source cycle.

2.3.9 SCI Timing

Note 1. t Pcyc: PCLKA cycle. Figure 2.27 SCK clock input/output timing Table 2.21 SCI timing (1) Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins: SCK0 to SCK4, SCK8, SCK9. For other pins, middle drive output is selected in the Port Drive Capability bit in the PmnPFS register. Parameter Symbol Min Max Unit *1 Test conditions SCI Input clock cycle Asynchronous t Scyc 4 - t Pcyc Figure 2.27 Clock synchronous Input clock pulse width t SCKW 0.4 0.6 t Scyc Input clock rise time t SCKr -5 n s Input clock fall time t SCKf -5 n s Output clock cycle Asynchronous t Scyc 6-t Pcyc Clock synchronous Output clock pulse width t SCKW 0.4 0.6 t Scyc Output clock rise time t SCKr -5 n s Output clock fall time t SCKf -5 n s Transmit data delay Clock synchronous tTXD -2 5 n s Figure 2.28 Receive data setup time Clock synchronous tRXS 15 - ns Receive data hold time Clock synchronous tRXH 5-n s tSCKW tSCKr tSCKf tScyc SCKn (n = 0 to 4, 8, 9)

R01DS0375EU0100 Rev.1.00 Page 40 of 69 May 29, 2020 RA6T1 Datasheet 2. Electr ical Characteristics Note: t IICcyc: IIC internal reference clock (IICφ) cycle. Note 1. Cb indicates the to tal capacity of the bus line. Figure 2.34 SCI simple IIC mode timing Simple IIC (Fast mode) SDA input rise time t Sr - 300 ns Figure 2.34 SDA input fall time t Sf - 300 ns SDA input spike pulse removal time t SP 04 × t IICcyc ns Data input setup time t SDAS 100 - ns Data input hold time t SDAH 0- n s SCL, SDA capacitive load C b*1 - 400 pF Table 2.23 SCI timing (3) (2 of 2) Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register. Parameter Symbol Min Max Unit Test conditions SDAn SCLn VIH VIL P*1 S*1 tSftSr tSDAH tSDAS tSP P*1 Test conditions: VIH = VCC × 0.7, VIL = VCC × 0.3 VOL = 0.6 V, IOL = 6 mA Sr*1 Note 1. S, P, and Sr indicate the following: S: Start condition P: Stop condition Sr: Restart condition (n = 0 to 4, 8, 9)

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2.3.10 SPI Timing

Note 1. t Pcyc: PCLKA cycle. Table 2.24 SPI timing Conditions: For RSPCKA and RSPCKB pins, high drive output is selected with the Port Drive Capability bit in the PmnPFS register. For other pins, middle drive output is selected in the Port Drive Capability bit in the PmnPFS register. Parameter Symbol Min Max Unit* 1 Test conditions*2 SPI RSPCK clock cycle Master t SPcyc 2 (PCLKA  60 MHz) 4 (PCLKA > 60 MHz) 4096 t Pcyc Figure 2.35 C = 30 pF Slave 4 4096 RSPCK clock high pulse width Master t SPCKWH (tSPcyc - tSPCKr - tSPCKf) / 2 - 3 -n s Slave 2 × t Pcyc - RSPCK clock low pulse width Master t SPCKWL (tSPcyc - tSPCKr - tSPCKf) / 2 - 3 -n s Slave 2 × t Pcyc - RSPCK clock rise and fall time Master t SPCKr, tSPCKf -5 n s Slave - 1 µs Data input setup time Master t SU 4- n s Figure 2.36 to Figure 2.41 C = 30 pFSlave 5 - Data input hold time Master (PCLKA division ratio set to 1/2) tHF 0- n s Master (PCLKA division ratio set to a value other than 1/2) t H tPcyc - Slave t H 20 - SSL setup time Master t LEAD N × tSPcyc - 10*3 N × tSPcyc + 100*3 ns Slave 6 x t Pcyc -n s SSL hold time Master t LAG N × tSPcyc - 10 *4 N × tSPcyc + 100*4 ns Slave 6 x t Pcyc -n s Data output delay Master t OD -6 . 3 n s Slave - 20 Data output hold time Master t OH 0- n s Slave 0 - Successive transmission delay Master t TD tSPcyc + 2 × tPcyc 8 × tSPcyc + 2 × tPcyc ns Slave 6 × t Pcyc MOSI and MISO rise and fall time Output t Dr, tDf -5 n s Input - 1 μs SSL rise and fall time Output t SSLr, tSSLf -5 n s Input - 1 μs Slave access time t SA -2 x t Pcyc + 28 ns Figure 2.40 and Figure 2.41 C = 30PFSlave output release time t REL -2 x t Pcyc + 28

R01DS0375EU0100 Rev.1.00 Page 45 of 69 May 29, 2020 RA6T1 Datasheet 2. Electr ical Characteristics Figure 2.41 SPI timing for slave when CPHA = 1

2.3.11 IIC Timing

Table 2.25 IIC timi ng (1) (1 of 2) (1) Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins: SDA0_B, SCL0_B, SDA1_A, SCL1_A, SDA1_B, SCL1_B. (2) The following pins do not require setting: SCL0_A, SDA0_A. (3) Use pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group membership. For the IIC interface, the AC portion of the electrical characteristics is measured for each group. Parameter Symbol Min* 1 Max Unit Test conditions*3 IIC (Standard mode, SMBus) ICFER.FMPE = 0 SCL input cycle time t SCL 6 (12) × tIICcyc + 1300 - ns Figure 2.42 SCL input high pulse width t SCLH 3 (6) × tIICcyc + 300 - ns SCL input low pulse width t SCLL 3 (6) × tIICcyc + 300 - ns SCL, SDA input rise time t Sr - 1000 ns SCL, SDA input fall time t Sf - 300 ns SCL, SDA input spike pulse removal time tSP 0 1 (4) × t IICcyc ns SDA input bus free time when wakeup function is disabled tBUF 3 (6) × tIICcyc + 300 - ns SDA input bus free time when wakeup function is enabled tBUF 3 (6) × tIICcyc + 4 × tPcyc + 300 -n s START condition input hold time when wakeup function is disabled tSTAH tIICcyc + 300 - ns START condition input hold time when wakeup function is enabled tSTAH 1 (5) × tIICcyc + tPcyc + 300 -n s Repeated START condition input setup time tSTAS 1000 - ns STOP condition input setup time t STOS 1000 - ns Data input setup time t SDAS tIICcyc + 50 - ns Data input hold time t SDAH 0- n s SCL, SDA capacitive load C b - 400 pF SSLAn input RSPCKn CPOL = 0 input RSPCKn CPOL = 1 input MISOn output MOSIn input t Dr, tDf tSA tOH tLEAD tTD tLAG tH LSB OUT (last data) DATA MSB OUT MSB IN DATA LSB IN MSB IN LSB OUT tSU tOD tREL MSB OUT SPI n = A or B

R01DS0375EU0100 Rev.1.00 Page 46 of 69 May 29, 2020 RA6T1 Datasheet 2. Electr ical Characteristics Note: t IICcyc: IIC internal reference clock (IICφ) cycle, tPcyc: PCLKB cycle. Note 1. Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1. Note 2. Only supported for SCL0_A, SDA0_A. Note 3. Must use pins that have a letter appended to their name, fo r instance “_A”, “_B”, to indicate group membership. For the IIC interface, the AC portion of the electrical characteristics is measured for each group. IIC (Fast mode) SCL input cycle time t SCL 6 (12) × tIICcyc + 600 - ns Figure 2.42 SCL input high pulse width t SCLH 3 (6) × tIICcyc + 300 - ns SCL input low pulse width t SCLL 3 (6) × tIICcyc + 300 - ns SCL, SDA input rise time t Sr 20 × (external pullup voltage/5.5V)*2 300 ns SCL, SDA input fall time t Sf 20 × (external pullup voltage/5.5V)*2 300 ns SCL, SDA input spike pulse removal time tSP 0 1 (4) × t IICcyc ns SDA input bus free time when wakeup function is disabled tBUF 3 (6) × tIICcyc + 300 - ns SDA input bus free time when wakeup function is enabled tBUF 3 (6) × tIICcyc + 4 × tPcyc + 300 -n s START condition input hold time when wakeup function is disabled tSTAH tIICcyc + 300 - ns START condition input hold time when wakeup function is enabled tSTAH 1 (5) × tIICcyc + tPcyc + 300 -n s Repeated START condition input setup time tSTAS 300 - ns STOP condition input setup time t STOS 300 - ns Data input setup time t SDAS tIICcyc + 50 - ns Data input hold time t SDAH 0- n s SCL, SDA capacitive load C b - 400 pF Table 2.25 IIC timi ng (1) (2 of 2) (1) Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins: SDA0_B, SCL0_B, SDA1_A, SCL1_A, SDA1_B, SCL1_B. (2) The following pins do not require setting: SCL0_A, SDA0_A. (3) Use pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group membership. For the IIC interface, the AC portion of the electrical characteristics is measured for each group. Parameter Symbol Min* 1 Max Unit Test conditions*3

R01DS0375EU0100 Rev.1.00 Page 47 of 69 May 29, 2020 RA6T1 Datasheet 2. Electr ical Characteristics Note: t IICcyc: IIC internal reference clock (IICφ) cycle, tPcyc: PCLKB cycle. Note 1. Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1. Note 2. Cb indicates the to tal capacity of the bus line. Figure 2.42 I 2C bus interface input/output timing Table 2.26 IIC timing (2) Setting of the SCL0_A, SDA0_A pins is not required with the Port Drive Capability bit in the PmnPFS register. Parameter Symbol Min* 1,*2 Max Unit Test conditions IIC (Fast mode+) ICFER.FMPE = 1 SCL input cycle time t SCL 6 (12) × tIICcyc + 240 - ns Figure 2.42 SCL input high pulse width t SCLH 3 (6) × tIICcyc + 120 - ns SCL input low pulse width t SCLL 3 (6) × tIICcyc + 120 - ns SCL, SDA input rise time t Sr - 120 ns SCL, SDA input fall time t Sf - 120 ns SCL, SDA input spike pulse removal time tSP 0 1 (4) × t IICcyc ns SDA input bus free time when wakeup function is disabled tBUF 3 (6) × tIICcyc + 120 - ns SDA input bus free time when wakeup function is enabled tBUF 3 (6) × tIICcyc + 4 × tPcyc + 120 -n s Start condition input hold time when wakeup function is disabled tSTAH tIICcyc + 120 - ns START condition input hold time when wakeup function is enabled tSTAH 1 (5) × tIICcyc + tPcyc + 120 -n s Restart condition input setup time t STAS 120 - ns Stop condition input setup time t STOS 120 - ns Data input setup time t SDAS tIICcyc + 30 - ns Data input hold time t SDAH 0- n s SCL, SDA capacitive load C b - 550 pF SDA0, SDA1 SCL0, SCL1 VIH VIL tSTAH tSCLH tSCLL P*1 S*1 tSf tSr tSCL tSDAH tSDAS tSTAS tSP tSTOS P*1 tBUF Test conditions: VIH = VCC × 0.7, VIL = VCC × 0.3 VOL = 0.6 V, IOL = 6 mA (ICFER.FMPE = 0) VOL = 0.4 V, IOL = 15 mA (ICFER.FMPE = 1) Sr*1 Note 1. S, P, and Sr indicate the following: S: Start condition P: Stop condition Sr: Restart condition

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2.4 ADC12 Characteristics

Table 2.27 A/D conversion characteristics for unit 0 (1 of 2) Conditions: PCLKC = 1 to 60 MHz Parameter Min Typ Max Unit Test conditions Frequency 1 - 60 MHz - Analog input capacitance - - 30 pF - Quantization error - ±0.5 - LSB - Resolution - - 12 Bits - Channel-dedicated sample-and-hold circuits in use* (AN000 to AN002) Conversion time*1 (operation at PCLKC = 60 MHz) Permissible signal source impedance Max. = 1 kΩ 1.06 (0.4 + 0.25)* -- μs  Sampling of channel- dedicated sample-and-hold circuits in 24 states  Sampling in 15 states Offset error - ±1.5 ±3.5 LSB AN000 to AN002 = 0.25 V Full-scale error - ±1.5 ±3.5 LSB AN000 to AN002 = VREFH0- 0.25 V Absolute accuracy - ±2.5 ±5.5 LSB - DNL pseudo-differential nonlinearity error - ±1.0 ±2.0 LSB - INL integral nonlinearity error - ±1.5 ±3.0 LSB - Holding characteristics of sample-and hold circuits -- 2 0 μs- Dynamic range 0.25 - VREFH0 - 0.25 Channel-dedicated sample-and-hold circuits not in use (AN000 to AN002) Conversion time*1 (operation at PCLKC = 60 MHz) Permissible signal source impedance Max. = 1 kΩ 0.48 (0.267)*2 -- μs Sampling in 16 states Offset error - ±1.0 ±2.5 LSB - Full-scale error - ±1.0 ±2.5 LSB - Absolute accuracy - ±2.0 ±4.5 LSB - DNL pseudo-differential nonlinearity error - ±0.5 ±1.5 LSB - INL integral nonlinearity error - ±1.0 ±2.5 LSB - High-precision channels (AN003, AN005, AN006) Conversion time* (operation at PCLKC = 60 MHz) Permissible signal source impedance Max. = 1 kΩ 0.48 (0.267)*2 -- μs Sampling in 16 states Max. = 400 Ω 0.40 (0.183)*2 -- μs Sampling in 11 states VCC = AVCC0 = 3.0 to 3.6 V

3.0 V ≤ VREFH0 ≤ AVCC0

Offset error - ±1.0 ±2.5 LSB - Full-scale error - ±1.0 ±2.5 LSB - Absolute accuracy - ±2.0 ±4.5 LSB - DNL pseudo-differential nonlinearity error - ±0.5 ±1.5 LSB - INL integral nonlinearity error - ±1.0 ±2.5 LSB - High-precision channels (AN007) Conversion time* (operation at PCLKC = 60 MHz) Permissible signal source impedance Max. = 1 kΩ 0.75 (0.533)*2 -- μs Sampling in 32 states Offset error - ±1.0 ±2.5 LSB - Full-scale error - ±1.0 ±2.5 LSB - Absolute accuracy - ±2.0 ±4.5 LSB - DNL pseudo-differential nonlinearity error - ±0.5 ±1.5 LSB - INL integral nonlinearity error - ±1.0 ±2.5 LSB -

R01DS0375EU0100 Rev.1.00 Page 49 of 69 May 29, 2020 RA6T1 Datasheet 2. Electr ical Characteristics Note: These specification values apply when there is no access to the external bus during A/D conversion. If access occurs during A/D conversion, the values might not fall within the indicated ranges. The use of ports 0 as digital outputs is not allowed when the 12-bit A/D converter is used. The characteristics apply when AVCC0, AVSS0, VREFH0, VREFH, VREFL0, VREFL, and 12-bit A/D converter input voltage are stable. Note 1. The conversion time includes the sampling and comparison times. The number of sampling states is indicated for the test conditions. Note 2. Values in parentheses indicate the sampling time. Note 3. When simultaneously using c hannel-dedicated sample-and-hold circuits in unit 0 and unit 1, see Table 2.29. Normal-precision channels (AN016 to AN018, AN020) Conversion time* (Operation at PCLKC = 60 MHz) Permissible signal source impedance Max. = 1 kΩ 0.88 (0.667)*2 -- μs Sampling in 40 states Offset error - ±1.0 ±5.5 LSB - Full-scale error - ±1.0 ±5.5 LSB - Absolute accuracy - ±2.0 ±7.5 LSB - DNL pseudo-differential nonlinearity error - ±0.5 ±4.5 LSB - INL integral nonlinearity error - ±1.0 ±5.5 LSB - Table 2.28 A/D conversion characteristics for unit 1 (1 of 2) Conditions: PCLKC = 1 to 60 MHz Parameter Min Typ Max Unit Test conditions Frequency 1 - 60 MHz - Analog input capacitance - - 30 pF - Quantization error - ±0.5 - LSB - Resolution - - 12 Bits - Channel-dedicated sample-and-hold circuits in use* (AN100 to AN102) Conversion time*1 (operation at PCLKC = 60 MHz) Permissible signal source impedance Max. = 1 kΩ 1.06 (0.4 + 0.25)*2 -- μs  Sampling of channel- dedicated sample-and-hold circuits in 24 states  Sampling in 15 states Offset error - ±1.5 ±3.5 LSB AN100 to AN102 = 0.25 V Full-scale error - ±1.5 ±3.5 LSB AN100 to AN102 = VREFH - 0.25 V Absolute accuracy - ±2.5 ±5.5 LSB - DNL pseudo-differential nonlinearity error - ±1.0 ±2.0 LSB - INL integral nonlinearity error - ±1.5 ±3.0 LSB - Holding characteristics of sample-and hold circuits -- 2 0 μs- Dynamic range 0.25 - VREFH - 0.25 V - Channel-dedicated sample-and-hold circuits not in use (AN100 to AN102) Conversion time* (Operation at PCLKC = 60 MHz) Permissible signal source impedance Max. = 1 kΩ 0.48 (0.267)* -- μs Sampling in 16 states Offset error - ±1.0 ±2.5 LSB - Full-scale error - ±1.0 ±2.5 LSB - Absolute accuracy - ±2.0 ±4.5 LSB - DNL pseudo-differential nonlinearity error - ±0.5 ±1.5 LSB - INL integral nonlinearity error - ±1.0 ±2.5 LSB - Table 2.27 A/D conversion characteristics for unit 0 (2 of 2) Conditions: PCLKC = 1 to 60 MHz Parameter Min Typ Max Unit Test conditions

R01DS0375EU0100 Rev.1.00 Page 50 of 69 May 29, 2020 RA6T1 Datasheet 2. Electr ical Characteristics Note: These specification values apply when there is no access to the external bus during A/D conversion. If access occurs during A/D conversion, the values might not fall within the indicated ranges. The use of ports 0 as digital outputs is not allowed when the 12-bit A/D converter is used. The characteristics apply when AVCC0, AVSS0, VREFH0, VREFH, VREFL0, VREFL, and 12-bit A/D converter input voltage are stable. Note 1. The conversion time includes the sampling and comparison times. The number of sampling states is indicated for the test conditions. Note 2. Values in parentheses indicate the sampling time. Note 3. When simultaneously using c hannel-dedicated sample-and-hold circuits in unit 0 and unit 1, see Table 2.29. High-precision channels (AN105, AN106) Conversion time*1 (Operation at PCLKC = 60 MHz) Permissible signal source impedance Max. = 1 kΩ 0.48 (0.267)*2 -- μs Sampling in 16 states Max. = 400 Ω 0.40 (0.183)*2 -- μs Sampling in 11 states VCC = AVCC0 = 3.0 to 3.6 V

3.0 V ≤ VREFH ≤ AVCC0

Offset error - ±1.0 ±2.5 LSB - Full-scale error - ±1.0 ±2.5 LSB - Absolute accuracy - ±2.0 ±4.5 LSB - DNL pseudo-differential nonlinearity error - ±0.5 ±1.5 LSB - INL integral nonlinearity error - ±1.0 ±2.5 LSB - High-precision channels (AN107) Conversion time* (Operation at PCLKC = 60 MHz) Permissible signal source impedance Max. = 1 kΩ 0.75 (0.533)*2 -- μs Sampling in 32 states Offset error - ±1.0 ±2.5 LSB - Full-scale error - ±1.0 ±2.5 LSB - Absolute accuracy - ±2.0 ±4.5 LSB - DNL pseudo-differential nonlinearity error - ±0.5 ±1.5 LSB - INL integral nonlinearity error - ±1.0 ±2.5 LSB - Normal-precision channels (AN116, AN117) Conversion time* (Operation at PCLKC = 60 MHz) Permissible signal source impedance Max. = 1 kΩ 0.88 (0.667)* -- μs Sampling in 40 states Offset error - ±1.0 ±5.5 LSB - Full-scale error - ±1.0 ±5.5 LSB - Absolute accuracy - ±2.0 ±7.5 LSB - DNL pseudo-differential nonlinearity error - ±0.5 ±4.5 LSB - INL integral nonlinearity error - ±1.0 ±5.5 LSB - Table 2.29 A/D conversion characteristics for simult aneous use of channel-dedicated sample-and-hold circuits in unit 0 and unit 1 Conditions: PCLKC = 30/60 MHz Parameter Min Typ Max Test conditions Channel-dedicated sample-and-hold circuits in use with continious sampling function enabled (AN000 to AN002) Offset error - ±1.5 ±5.0  PCLKC = 60 MHz  Sampling in 15 statesFull-scale error - ±2.5 ±5.0 Absolute accuracy - ±4.0 ±8.0 Channel-dedicated sample-and-hold circuits in use with continious sampling function enabled (AN100 to AN102) Offset error - ±1.5 ±5.0 Full-scale error - ±2.5 ±5.0 Absolute accuracy - ±4.0 ±8.0 Channel-dedicated sample-and-hold circuits in use with continious sampling function enabled (AN000 to AN002) Offset error - ±1.5 ±3.5  PCLKC = 30 MHz  Sampling in 7 statesFull-scale error - ±1.5 ±3.5 Absolute accuracy - ±3.0 +4.5/-6.5 Channel-dedicated sample-and-hold circuits in use with continious sampling function enabled (AN100 to AN102) Offset error - ±1.5 ±3.5 Full-scale error - ±1.5 ±3.5 Absolute accuracy - ±3.0 +4.5/-6.5 Table 2.28 A/D conversion characteristics for unit 1 (2 of 2) Conditions: PCLKC = 1 to 60 MHz Parameter Min Typ Max Unit Test conditions

R01DS0375EU0100 Rev.1.00 Page 51 of 69 May 29, 2020 RA6T1 Datasheet 2. Electr ical Characteristics Note: When simultaneously using c hannel-dedicated sample-and-hold circuits in unit 0 and unit 1, setting the ADSHMSR.SHMD bit to 1 is recommended. Figure 2.43 Illustration of ADC12 characteristic terms Absolute accuracy Absolute accuracy is the difference between output code based on the theoretical A/D conversion characteristics, and the actual A/D conversion result. When measuring absolute accuracy, the voltage at the midpoint of the width of the analog input voltage (1-LSB width), which can meet the expectation of outputting an equal code based on the theoretical A/D conversion characteristics, is used as the analog input voltage. For example, if 12-bit resolution is used and the reference voltage VREFH0 is 3.072 V , then the 1-LSB width becomes 0.75 mV , and 0 mV , 0.75 mV , and 1.5 mV are used as the analog input voltages. If the analog input voltage is 6 mV , an absolute accuracy of ±5 LSB means that the actual A/D conversion result is in the range of 003h to 00Dh, though an output code of 008h can be expected from the theoretical A/D conversion characteristics. Integral nonlinearity error (INL) Integral nonlinearity error is the maximum deviation between the ideal line when the measured offset and full-scale errors are zeroed, and the actual output code. Pseudo-differential nonlinearity error (DNL) Pseudo-differential nonlinearity error is the difference between the 1-LSB width based on the ideal A/D conversion characteristics and the width of the actual output code. Offset error Offset error is the difference between the transition point of the ideal first output code and the actual first output code. Table 2.30 A/D internal reference voltage characteristics Parameter Min Typ Max Unit Test conditions A/D internal reference voltage 1.13 1.18 1.23 V - Sampling time 4.15 - - μs- Integral nonlinearity error (INL) Actual A/D conversion characteristic Ideal A/D conversion characteristic Analog input voltage Offset error Absolute accuracy Pseudo-differential nonlinearity error (DNL) Full-scale error FFFh 000h Ideal line of actual A/D conversion characteristic 1-LSB width for ideal A/D conversion characteristic Pseudo-differential nonlinearity error (DNL) 1-LSB width for ideal A/D conversion characteristic VREFH0 (full-scale) A/D converter output code

R01DS0375EU0100 Rev.1.00 Page 52 of 69 May 29, 2020 RA6T1 Datasheet 2. Electr ical Characteristics Full-scale error Full-scale error is the difference between the transition point of the ideal last output code and the actual last output code.

2.5 DAC12 Characteristics

2.6 TSN Characteristics

2.7 OSC Stop Detect Characteristics

Table 2.31 D/A conversion characteristics Parameter Min Typ Max Unit Test conditions Resolution - - 12 Bits - Without output amplifier Absolute accuracy - - ±24 LSB Resistive load 2 M Ω INL - ±2.0 ±8.0 LSB Resistive load 2 M Ω DNL - ±1.0 ±2.0 LSB - Output impedance - 8.5 - k Ω - Conversion time - - 3.0 μs Resistive load 2 M Ω, Capacitive load 20 pF Output voltage range 0 - VREFH V - With output amplifier INL - ±2.0 ±4.0 LSB - DNL - ±1.0 ±2.0 LSB - Conversion time - - 4.0 μs- Resistive load 5 - - k Ω - Capacitive load - - 50 pF - Output voltage range 0.2 - VREFH - 0.2 V - Table 2.32 TSN characteristics Parameter Symbol Min Typ Max Unit Test conditions Relative accuracy - - ±1.0 - °C - Temperature slope - - 4.0 - mV/°C - Output voltage (at 25°C) - - 1.24 - V - Temperature sensor start time t START --3 0 μs- Sampling time - 4.15 - - μs- Table 2.33 Oscillation stop detection circuit characteristics Parameter Symbol Min Typ Max Unit Test conditions Detection time t dr --1 m s Figure 2.44

R01DS0375EU0100 Rev.1.00 Page 53 of 69 May 29, 2020 RA6T1 Datasheet 2. Electr ical Characteristics Figure 2.44 Oscillation stop detection timing

2.8 POR and LVD Characteristics

Note 1. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR, Vdet1, and Vdet2 for POR and LVD. Table 2.34 Power-on reset circuit and voltage detection circuit characteristics Parameter Symbol Min Typ Max Unit Test conditions Voltage detection level Power-on reset (POR) DPSBYCR.DEEPCUT[1:0] = 00b or 01b VPOR 2.5 2.6 2.7 V Figure 2.45 DPSBYCR.DEEPCUT[1:0] = 11b 1.8 2.25 2.7 Voltage detection circuit (LVD0) V det0_1 2.84 2.94 3.04 Figure 2.46 Vdet0_2 2.77 2.87 2.97 Vdet0_3 2.70 2.80 2.90 Voltage detection circuit (LVD1) V det1_1 2.89 2.99 3.09 Figure 2.47 Vdet1_2 2.82 2.92 3.02 Vdet1_3 2.75 2.85 2.95 Voltage detection circuit (LVD2) V det2_1 2.89 2.99 3.09 Figure 2.48 Vdet2_2 2.82 2.92 3.02 Vdet2_3 2.75 2.85 2.95 Internal reset time Power-on reset time t POR -4 . 5 -m s Figure 2.45 LVD0 reset time t LVD0 -0 . 5 1 - Figure 2.46 LVD1 reset time t LVD1 -0 . 3 8 - Figure 2.47 LVD2 reset time t LVD2 -0 . 3 8 - Figure 2.48 Minimum VCC down time*1 tVOFF 200 - - μs Figure 2.45, Figure 2.46 Response delay t det - - 200 μs Figure 2.45 to Figure 2.48 LVD operation stabilization time (after LVD is enabled) t d(E-A) --1 0 μs Figure 2.47, Figure 2.48Hysteresis width (LVD1 and LVD2) V LVH -7 0 -m V tdr Main clock OSTDSR.OSTDF MOCO clock ICLK

R01DS0375EU0100 Rev.1.00 Page 56 of 69 May 29, 2020 RA6T1 Datasheet 2. Electr ical Characteristics

2.9 ACMPHS Characteristics

Note 1. This value is the internal propagation delay.

2.10 PGA Characteristics

Table 2.35 ACMPHS characteristics Parameter Symbol Min Typ Max Unit Test conditions Reference voltage range VREF 0 - AVCC0 V - Input voltage range VI 0 - AVCC0 V - Output delay*1 Td - 50 100 ns VI = VREF ± 100 mV Internal reference voltage Vref 1.13 1.18 1.23 V - Table 2.36 PGA characteristics in single mode Parameter Symbol Min Typ Max Unit PGAVSS input voltage range PGAVSS 0 - 0 V AIN0 (G = 2.000) 0.050 × AVCC0 - 0.45 × AVCC0 V AIN1 (G = 2.500) 0.047 × AVCC0 - 0.360 × AVCC0 V AIN2 (G = 2.667) 0.046 × AVCC0 - 0.337 × AVCC0 V AIN3 (G = 2.857) 0.046 × AVCC0 - 0.32 × AVCC0 V AIN4 (G = 3.077) 0.045 × AVCC0 - 0.292 × AVCC0 V AIN5 (G = 3.333) 0.044 × AVCC0 - 0.265 × AVCC0 V AIN6 (G = 3.636) 0.042 × AVCC0 - 0.247 × AVCC0 V AIN7 (G = 4.000) 0.040 × AVCC0 - 0.212 × AVCC0 V AIN8 (G = 4.444) 0.036 × AVCC0 - 0.191 × AVCC0 V AIN9 (G = 5.000) 0.033 × AVCC0 - 0.17 × AVCC0 V AIN10 (G = 5.714) 0.031 × AVCC0 - 0.148 × AVCC0 V AIN11 (G = 6.667) 0.029 × AVCC0 - 0.127 × AVCC0 V AIN12 (G = 8.000) 0.027 × AVCC0 - 0.09 × AVCC0 V AIN13 (G = 10.000) 0.025 × AVCC0 - 0.08 × AVCC0 V AIN14 (G = 13.333) 0.023 × AVCC0 - 0.06 × AVCC0 V Gain error Gerr0 (G = 2.000) -1.0 - 1.0 % Offset error Voff -8 - 8 mV

R01DS0375EU0100 Rev.1.00 Page 57 of 69 May 29, 2020 RA6T1 Datasheet 2. Electr ical Characteristics

2.11 Flash Memory Characteristics

2.11.1 Code Flash Memory Characteristics

Note 1. This is the minimum number of times to guarantee all t he characteristics after reprogramming. The guaranteed range is from 1 to the minimum value. Note 2. This indicates the minimum value of the characterist ic when reprogramming is performed within the specified range. Note 3. This result is obtained from reliability testing. Note 4. The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times (n = 10000), erasing can be performed n times for each block. For example, when 128-byte programming is performed 64 times for different addresses in 8-KB blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However, programming the same address several times as one erasure is not enabled. Overwriting is prohibited. Table 2.37 PGA characteristics in pseudo-differential mode Parameter Symbol Min Typ Max Unit PGAVSS input voltage range PGAVSS -0.5 - 0.3 V Pseudo-differential input voltage range G = 1.500 AIN-PGAVSS -0.5 - 0.5 V G = 5.667 -0.15 - 0.15 V Gain error G = 1.500 Gerr -1.0 - 1.0 % Table 2.38 Code flash memory characteristics Conditions: Program or erase: FCLK = 4 to 60 MHz Read: FCLK ≤ 60 MHz Parameter Symbol FCLK = 4 MHz 20 MHz ≤ FCLK ≤ 60 MHz Unit Test conditionsMin Typ Max Min Typ Max Programming time NPEC  100 times 128-byte t P128 - 0.75 13.2 - 0.34 6.0 ms 8-KB t P8K -4 9 1 7 6 -2 2 8 0 m s 32-KB t P32K - 194 704 - 88 320 ms Programming time NPEC > 100 times 128-byte t P128 - 0.91 15.8 - 0.41 7.2 ms 8-KB t P8K -6 0 2 1 2 -2 7 9 6 m s 32-KB t P32K - 234 848 - 106 384 ms Erasure time NPEC  100 times 8-KB t E8K - 78 216 - 43 120 ms 32-KB t E32K - 283 864 - 157 480 ms Erasure time NPEC > 100 times 8-KB t E8K - 94 260 - 52 144 ms 32-KB t E32K - 341 1040 - 189 576 ms Reprogramming/erasure cycle*4 NPEC 10000*1 - - 10000* 1 --T i m e s Suspend delay during programming t SPD - - 264 - - 120 μs First suspend delay during erasure in suspend priority mode tSESD1 - - 216 - - 120 μs Second suspend delay during erasure in suspend priority mode tSESD2 -- 1 . 7 --1 . 7 m s Suspend delay during erasure in erasure priority mode tSEED -- 1 . 7 --1 . 7 m s Forced stop command t FD -- 3 2 --2 0 μs Data hold time*2 tDRP 10*2, *3 --1 0 * 2, *3 - - Years

R01DS0375EU0100 Rev.1.00 Page 58 of 69 May 29, 2020 RA6T1 Datasheet 2. Electr ical Characteristics Figure 2.49 Suspension and forced stop timing for flash memory programming and erasure FCU command FSTATR0.FRDY Programming pulse

• Suspension during programming FCU command FSTATR0.FRDY Erasure pulse
• Suspension during erasure in suspend priority mode FCU command FSTATR0.FRDY Erasure pulse
• Suspension during erasure in erasure priority mode Program Suspend Ready Not Ready Ready Programming tSPD Erase Suspend Ready Not Ready Ready tSEED Erasing Erase Suspend Resume Suspend Ready Not Ready Ready Not Ready tSESD1 tSESD2 Erasing Erasing tFD
• Forced Stop FACI command FSTATR.FRDY Forced Stop Not Ready Ready

R01DS0375EU0100 Rev.1.00 Page 59 of 69 May 29, 2020 RA6T1 Datasheet 2. Electr ical Characteristics

2.11.2 Data Flash Memory Characteristics

Note 1. The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times (n = 12500 0), erasing can be performed n times for each block. For example, when 4-byte programming is performed 16 times for different addresses in 64-byte blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However, programming the same address several times as one erasure is not enabled. Overwriting is prohibited. Note 2. This is the minimum number of times to guarantee all t he characteristics after reprogramming. The guaranteed range is from 1 to the minimum value. Note 3. This indicates the minimum value of the characterist ic when reprogramming is performed within the specified range. Note 4. This result is obtained from reliability testing.

2.12 Boundary Scan

Table 2.39 Data flash memory characteristics Conditions: Program or erase: FCLK = 4 to 60 MHz Read: FCLK ≤ 60 MHz Parameter Symbol FCLK = 4 MHz 20 MHz ≤ FCLK ≤ 60 MHz Unit Test conditionsMin Typ Max Min Typ Max Programming time 4-byte t DP4 - 0.36 3.8 - 0.16 1.7 ms 8-byte t DP8 - 0.38 4.0 - 0.17 1.8 16-byte t DP16 - 0.42 4.5 - 0.19 2.0 Erasure time 64-byte t DE64 - 3.1 18 - 1.7 10 ms 128-byte t DE128 - 4.7 27 - 2.6 15 256-byte t DE256 - 8.9 50 - 4.9 28 Blank check time 4-byte t DBC4 -- 8 4 - - 3 0 μs Reprogramming/erasure cycle*1 NDPEC 125000*2 - - 125000 *2 --- Suspend delay during programming 4-byte t DSPD - - 264 - - 120 μs 8-byte - - 264 - - 120 16-byte - - 264 - - 120 First suspend delay during erasure in suspend priority mode 64-byte t DSESD1 - - 216 - - 120 μs 128-byte - - 216 - - 120 256-byte - - 216 - - 120 Second suspend delay during erasure in suspend priority mode 64-byte t DSESD2 - - 300 - - 300 μs 128-byte - - 390 - - 390 256-byte - - 570 - - 570 Suspend delay during erasing in erasure priority mode 64-byte t DSEED - - 300 - - 300 μs 128-byte - - 390 - - 390 256-byte - - 570 - - 570 Forced stop command t FD -- 3 2 - - 2 0 μs Data hold time*3 tDRP 10*3,*4 - - 10* 3,*4 - - Year Table 2.40 Boundary scan characteristics (1 of 2) Parameter Symbol Min Typ Max Unit Test conditions TCK clock cycle time t TCKcyc 100 - - ns Figure 2.50 TCK clock high pulse width t TCKH 45 - - ns TCK clock low pulse width t TCKL 45 - - ns TCK clock rise time t TCKr --5 n s TCK clock fall time t TCKf --5 n s

R01DS0375EU0100 Rev.1.00 Page 61 of 69 May 29, 2020 RA6T1 Datasheet 2. Electr ical Characteristics

2.13 Joint Test Action Group (JTAG)

Figure 2.53 JTAG TCK timing Figure 2.54 JTAG input/output timing Table 2.41 JTAG Parameter Symbol Min Typ Max Unit Test conditions TCK clock cycle time t TCKcyc 40 - - ns Figure 2.50 TCK clock high pulse width t TCKH 15 - - ns TCK clock low pulse width t TCKL 15 - - ns TCK clock rise time t TCKr --5 n s TCK clock fall time t TCKf --5 n s TMS setup time t TMSS 8- - n s Figure 2.51 TMS hold time t TMSH 8- - n s TDI setup time t TDIS 8- - n s TDI hold time t TDIH 8- - n s TDO data delay time t TDOD --2 0 n s TCK tTCKH tTCKcyc tTCKL tTCKf tTCKr TCK TMS tTMSS tTMSH TDI tTDIS tTDIH TDO tTDOD

R01DS0375EU0100 Rev.1.00 Page 62 of 69 May 29, 2020 RA6T1 Datasheet 2. Electr ical Characteristics

2.14 Serial Wire Debug (SWD)

Figure 2.55 SWD SWCLK timing Figure 2.56 SWD input/output timing Table 2.42 SWD Parameter Symbol Min Typ Max Unit Test conditions SWCLK clock cycle time t SWCKcyc 40 - - ns Figure 2.55 SWCLK clock high pulse width t SWCKH 15 - - ns SWCLK clock low pulse width t SWCKL 15 - - ns SWCLK clock rise time t SWCKr --5 n s SWCLK clock fall time t SWCKf --5 n s SWDIO setup time t SWDS 8- - n s Figure 2.56 SWDIO hold time t SWDH 8- - n s SWDIO data delay time t SWDD 2 - 28 ns SWCLK tSWCKH tSWCKcyc tSWCKL SWCLK SWDIO (input) tSWDS tSWDH SWDIO (output) tSWDD SWDIO (output) tSWDD SWDIO (output) tSWDD

R01DS0375EU0100 Rev.1.00 Page 63 of 69 May 29, 2020 RA6T1 Datasheet 2. Electr ical Characteristics

2.15 Embedded Trace Macr o Interface (ETM)

Figure 2.57 ETM TCLK timing Figure 2.58 ETM output timing Table 2.43 ETM Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register. Parameter Symbol Min Typ Max Unit Test conditions TCLK clock cycle time t TCLKcyc 33.3 - - ns Figure 2.57 TCLK clock high pulse width t TCLKH 13.6 - - ns TCLK clock low pulse width t TCLKL 13.6 - - ns TCLK clock rise time t TCLKr --3 n s TCLK clock fall time t TCLKf --3 n s TDATA[3:0] output setup time t TRDS 3.5 - - ns Figure 2.58 TDATA[3:0] output hold time t TRDH 2.5 - - ns TCLK tTCLKH tTCLKcyc tTCLKL tTCLKf tTCLKr TDATA[3:0] TCLK tTRDS tTRDStTRDH tTRDH

R01DS0375EU0100 Rev.1.00 Page 64 of 69 May 29, 2020 RA6T1 Datasheet Appendix 1. Package Dimensions Appendix 1.Package Dimensions Information on the latest version of the package dimensions or mountings is shown in “Packages” on the Renesas Electronics Corporation website. Figure 1.1 100-pin LQFP MASS (Typ) [g] 0.6 Unit: mm Previous CodeRENESAS Code PLQP0100KB-B — P-LFQFP100-14x14-0.50 © 2015 Renesas Electronics Corporation. All rights reserved. D E HD HE A bp c T e x y L p 13.9 13.9 15.8 15.8 0.05 0.15 0.09 0.45 Min Nom Dimensions in millimetersReference Symbol Max 14.0 14.0 1.4 16.0 16.0 0.20 3.5q 0.5 0.6 1.0 14.1 14.1 16.2 16.2 1.7 0.15 0.27 0.20 0.08 0.08 0.75 NOTE) 1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH. 2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET. 3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE LOCATED WITHIN THE HATCHED AREA. 4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY. T HD A2A1 Lp Detail F A c 0.25 D 100 26 251 F NOTE 4 NOTE 3 Index area HE E*2 *3 bpe yS S M

R01DS0375EU0100 Rev.1.00 Page 65 of 69 May 29, 2020 RA6T1 Datasheet Appendix 1. Package Dimensions Figure 1.2 64-pin LQFP MASS (Typ) [g] 0.3 Unit: mm Previous CodeRENESAS Code PLQP0064KB-C — P-LFQFP64-10x10-0.50 © 2015 Renesas Electronics Corporation. All rights reserved. D E HD HE A bp c T e x y L p 9.9 9.9 11.8 11.8 0.05 0.15 0.09 0.45 Min Nom Dimensions in millimetersReference Symbol Max 10.0 10.0 1.4 12.0 12.0 0.20 3.5q 0.5 0.6 1.0 10.1 10.1 12.2 12.2 1.7 0.15 0.27 0.20 0.08 0.08 0.75 NOTE) 1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH. 2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET. 3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE LOCATED WITHIN THE HATCHED AREA. 4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY. HD A2A1 Lp Detail F A c 0.25 D 48 33 3249 161 F NOTE 4 NOTE 3 Index area HE E*2 bpe yS S M T

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1.00 May 29, 2020 First release

Revision History

Publication Date: Rev.1.00 May 29, 2020 Published by: Renesas Electronics Corporation Colophon

1. Precaution against Electro static Discharge (ESD) A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices. 2. Processing at power-on The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the level at which resetting is specified. 3. Input of signal during power-off state Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Follow the guideline for input signal during power- off state as described in your product documentation. 4. Handling of unused pins Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. 5. Clock signals After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable. 6. V oltage application waveform at input pin Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V IL (Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.). 7. Prohibition of access to reserved addresses Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these addresses as the correct operation of the LSI is not guaranteed. 8. Differences between products Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system-evaluation test for the given product. http://www.renesas.com Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics Corporation TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan Renesas Electronics America Inc. 1001 Murphy Ranch Road, Milpitas, CA 95035, U.S.A. Renesas Electronics Canada Limited

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