RA6E2

RA6E2 RENESAS | Alldatasheet

Document overview

• Manufacturer or author: Renesas Electronics Corporation
• PDF pages: 92

Technical content

Features

Rev.1.10 Feb 28, 2023 ■ Arm® Cortex®-M33 Core

• Armv8-M architecture with the main extension
• Maximum operating frequency: 200 MHz
• Arm Memory Protection Unit (Arm MPU) – Protected Memory System Architecture (PMSAv8) – Secure MPU (MPU_S): 8 regions – Non-secure MPU (MPU_NS): 8 regions
• SysTick timer – Embeds two Systick timers: Secure and Non-secure instance – Driven by LOCO or system clock
• CoreSight™ ETM-M33 ■ Memory
• Up to 256-KB code flash memory
• 4-KB data flash memory (100,000 program/erase (P/E) cycles)
• 40-KB SRAM ■ Connectivity
• Serial Communications Interface (SCI) × 2 – Asynchronous interfaces – 8-bit clock synchronous interface – Smart card interface – Simple IIC – Simple SPI – Manchester coding
• I3C bus interface (I3C)
• Serial Peripheral Interface (SPI) × 2
• Quad Serial Peripheral Interface (QSPI)
• USB 2.0 Full-Speed Module (USBFS)
• CAN with Flexible Data-rate (CANFD)
• Serial Sound Interface Enhanced (SSIE)
• Consumer Electronics Control (CEC) ■ Analog
• 12-bit A/D Converter (ADC12)
• 12-bit D/A Converter (DAC12) × 2
• Temperature Sensor (TSN) ■ Timers
• General PWM Timer 16-bit Enhanced (GPT16E) × 6
• Low Power Asynchronous General Purpose Timer (AGT) × 2 ■ Security
• Arm® TrustZone® – Up to three regions for the code flash – Up to two regions for the data flash – Up to three regions for the SRAM – Individual secure or non-secure security attribution for each peripheral
• 128-bit unique ID
• True Random Number Generator (TRNG)
• Pin function – Secure pin multiplexing ■ System and Power Management
• Low power modes
• RealTime Clock (RTC) with calendar
• Event Link Controller (ELC)
• Data Transfer Controller (DTC)
• DMA Controller (DMAC) × 8
• Power-on reset
• Low V oltage Detection (LVD) with voltage settings
• Watchdog Timer (WDT)
• Independent Watchdog Timer (IWDT) ■ Multiple Clock Sources
• Main clock oscillator (MOSC) (8 to 24 MHz)
• Sub-clock oscillator (SOSC) (32.768 kHz)
• High-speed on-chip oscillator (HOCO) (16/18/20 MHz)
• Middle-speed on-chip oscillator (MOCO) (8 MHz)
• Low-speed on-chip oscillator (LOCO) (32.768 kHz)
• IWDT-dedicated on-chip oscillator (15 kHz)
• Clock trim function for HOCO/MOCO/LOCO
• PLL
• Clock out support ■ General-Purpose I/O Ports
• 5-V tolerance, open drain, input pull-up, switchable driving ability ■ Operating Voltage
• VCC: 2.7 to 3.6 V ■ Operating Temperature and Packages – 64-pin LQFP (10 mm × 10 mm, 0.5 mm pitch) – 48-pin QFN (7 mm × 7 mm, 0.5 mm pitch) – 32-pin QFN (5 mm × 5 mm, 0.5 mm pitch) – 64-pin BGA (5 mm × 5 mm, 0.5 mm pitch) – 36-pin BGA (4 mm × 4 mm, 0.5 mm pitch) Datasheet R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 1 of 92

1. Overview The MCU integrates multiple series of software- and pin-compatible Arm®-based 32-bit cores that share a common set of Renesas peripherals to facilitate design scalability and efficient platform-based product development. The MCU in this series incorporates a high-performance Arm Cortex®-M33 core running up to 200 MHz with the following features:

• Up to 256 KB code flash memory
• 40 KB SRAM
• Quad Serial Peripheral Interface (QSPI)
• USBFS
• Analog peripherals
• Security and safety features

1.1 Function Outline

Table 1.1 Arm core Feature Functional description Arm Cortex-M33 core ● Maximum operating frequency: up to 200 MHz

• Arm Cortex-M33 core: – Armv8-M architecture with security extension – Revision: r0p4-00rel0
• Arm Memory Protection Unit (Arm MPU) – Protected Memory System Architecture (PMSAv8) – Secure MPU (MPU_S): 8 regions – Non-secure MPU (MPU_NS): 8 regions
• SysTick timer – Embeds two Systick timers: Secure and Non-secure instance – Driven by SysTick timer clock (SYSTICCLK) or system clock (ICLK)
• CoreSight ™ ETM-M33 Table 1.2 Memory Feature Functional description Code flash memory Maximum 256 KB of code flash memory. Data flash memory 4 KB of data flash memory. Option-setting memory The option-setting memory determines the state of the MCU after a reset. SRAM On-chip high-speed SRAM with either parity bit or Error Correction Code (ECC). Standby SRAM On-chip SRAM that can retain data in Deep Software Standby mode. See section x, Standby SRAM. Table 1.3 System (1 of 2) Feature Functional description Operating modes Two operating modes:
• Single-chip mode
• SCI/USB/SWD boot mode Resets The MCU provides 14 resets. Low Voltage Detection (LVD) The Low Voltage Detection (LVD) module monitors the voltage level input to the VCC pin. The detection level can be selected by register settings. The LVD module consists of three separate voltage level detectors (LVD0, LVD1, LVD2). LVD0, LVD1, and LVD2 measure the voltage level input to the VCC pin. LVD registers allow your application to configure detection of VCC changes at various voltage thresholds. RA6E2 Datasheet 1. Overview R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 2 of 92

Table 1.3 System (2 of 2) Feature Functional description Clocks ● Main clock oscillator (MOSC)

• Sub-clock oscillator (SOSC)
• High-speed on-chip oscillator (HOCO)
• Middle-speed on-chip oscillator (MOCO)
• Low-speed on-chip oscillator (LOCO)
• IWDT-dedicated on-chip oscillator
• PLL
• Clock out support Clock Frequency Accuracy Measurement Circuit (CAC) The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to be measured (measurement target clock) within the time generated by the clock selected as the measurement reference (measurement reference clock), and determines the accuracy depending on whether the number of pulses is within the allowable range. When measurement is complete or the number of pulses within the time generated by the measurement reference clock is not within the allowable range, an interrupt request is generated. Interrupt Controller Unit (ICU) The Interrupt Controller Unit (ICU) controls which event signals are linked to the Nested Vector Interrupt Controller (NVIC), the DMA Controller (DMAC), and the Data Transfer Controller (DTC) modules. The ICU also controls non-maskable interrupts. Low power modes Power consumption can be reduced in multiple ways, including setting clock dividers, stopping modules, selecting power control mode in normal operation, and transitioning to low power modes. Register write protection The register write protection function protects important registers from being overwritten due to software errors. The registers to be protected are set with the Protect Register (PRCR). Memory Protection Unit (MPU) The MCU has one Memory Protection Unit (MPU). Table 1.4 Event link Feature Functional description Event Link Controller (ELC) The Event Link Controller (ELC) uses the event requests generated by various peripheral modules as source signals to connect them to different modules, allowing direct link between the modules without CPU intervention. Table 1.5 Direct memory access Feature Functional description Data Transfer Controller (DTC) A Data Transfer Controller (DTC) module is provided for transferring data when activated by an interrupt request. DMA Controller (DMAC) The MCU includes an 8-channel direct memory access controller (DMAC) that can transfer data without intervention from the CPU. When a DMA transfer request is generated, the DMAC transfers data stored at the transfer source address to the transfer destination address. Table 1.6 External bus interface Feature Functional description External buses ● QSPI area (EQBIU): Connected to the QSPI (external device interface) Table 1.7 Timers (1 of 2) Feature Functional description General PWM Timer (GPT) The General PWM Timer (GPT) is a 16-bit timer with GPT16E × 6 channels. PWM waveforms can be generated by controlling the up-counter, down-counter, or the up- and down-counter. In addition, PWM waveforms can be generated for controlling brushless DC motors. The GPT can also be used as a general-purpose timer. Port Output Enable for GPT (POEG) The Port Output Enable (POEG) function can place the General PWM Timer (GPT) output pins in the output disable state Low Power Asynchronous General Purpose Timer (AGT) The low power Asynchronous General Purpose Timer (AGT) is a 32-bit timer that can be used for pulse output, external pulse width or period measurement, and counting external events. This timer consists of a reload register and a down counter. The reload register and the down counter are allocated to the same address, and can be accessed with the AGT register. RA6E2 Datasheet 1. Overview R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 3 of 92

Table 1.7 Timers (2 of 2) Feature Functional description Realtime Clock (RTC) The realtime clock (RTC) has two counting modes, calendar count mode and binary count mode, that are used by switching register settings. For calendar count mode, the RTC has a 100-year calendar from 2000 to 2099 and automatically adjusts dates for leap years. For binary count mode, the RTC counts seconds and retains the information as a serial value. Binary count mode can be used for calendars other than the Gregorian (Western) calendar. Watchdog Timer (WDT) The Watchdog Timer (WDT) is a 14-bit down counter that can be used to reset the MCU when the counter underflows because the system has run out of control and is unable to refresh the WDT. In addition, the WDT can be used to generate a non-maskable interrupt or an underflow interrupt. Independent Watchdog Timer (IWDT) The Independent Watchdog Timer (IWDT) consists of a 14-bit down counter that must be serviced periodically to prevent counter underflow. The IWDT provides functionality to reset the MCU or to generate a non-maskable interrupt or an underflow interrupt. Because the timer operates with an independent, dedicated clock source, it is particularly useful in returning the MCU to a known state as a fail-safe mechanism when the system runs out of control. The IWDT can be triggered automatically by a reset, underflow, refresh error, or a refresh of the count value in the registers. Table 1.8 Communication interfaces Feature Functional description Serial Communications Interface (SCI) The Serial Communications Interface (SCI) × 2 channels have asynchronous and synchronous serial interfaces:

• Asynchronous interfaces (UART and Asynchronous Communications Interface Adapter (ACIA))
• 8-bit clock synchronous interface
• Simple IIC (master-only)
• Simple SPI
• Smart card interface
• Manchester interface The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and transmission protocol. SCIn (n = 0, 9) has FIFO buffers to enable continuous and full-duplex communication, and the data transfer speed can be configured independently using an on-chip baud rate generator. I3C bus interface (I3C) The I3C bus interface (I3C) has one channel. The I3C module conforms with and provides a subset of the NXP I2C (Inter-Integrated Circuit) bus interface functions and a subset of the MIPI I3C. Serial Peripheral Interface (SPI) The Serial Peripheral Interface (SPI) has 2 channels. The SPI provides high-speed full-duplex synchronous serial communications with multiple processors and peripheral devices. Control Area Network with Flexible Data-Rate Module (CANFD) The CAN with Flexible Data-Rate (CANFD) module can handle classical CAN frames and CANFD frames complied with ISO 11898-1 standard. The module supports 4 transmit buffers and 32 receive buffers. USB 2.0 Full-Speed module (USBFS) The USB 2.0 Full-Speed module (USBFS) can operate as a device controller. The module supports full-speed transfer as defined in Universal Serial Bus Specification 2.0. The module has an internal USB transceiver and supports all of the transfer types defined in Universal Serial Bus Specification 2.0. The USB has buffer memory for data transfer, providing a maximum of 5 pipes. Pipe 0 and pipe 4 to pipe 7 can be assigned any endpoint number based on the peripheral devices used for communication or based on your system. Quad Serial Peripheral Interface (QSPI) The Quad Serial Peripheral Interface (QSPI) is a memory controller for connecting a serial ROM (nonvolatile memory such as a serial flash memory, serial EEPROM, or serial FeRAM) that has an SPI-compatible interface. Serial Sound Interface Enhanced (SSIE) The Serial Sound Interface Enhanced (SSIE) peripheral provides functionality to interface with digital audio devices for transmitting I2S/Monaural/TDM audio data over a serial bus. The SSIE supports an audio clock frequency of up to 50 MHz, and can be operated as a slave or master receiver, transmitter, or transceiver to suit various applications. The SSIE includes 32-stage FIFO buffers in the receiver and transmitter, and supports interrupts and DMA-driven data reception and transmission. Consumer Electronics Control module (CEC) The CEC transmission/reception module can generate and receive CEC signals complied with the High-Definition Multimedia Interface (HDMI) Version 1.4b. The module can also automatically detect communication states. RA6E2 Datasheet 1. Overview R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 4 of 92

Table 1.9 Analog Feature Functional description 12-bit A/D Converter (ADC12) A 12-bit successive approximation A/D converter (ADC12) is provided. Up to 12 analog input channels are selectable. Temperature sensor output and internal reference voltage are selectable for conversion. 12-bit D/A Converter (DAC12) A 12-bit D/A converter (DAC12) is provided. Temperature Sensor (TSN) The on-chip Temperature Sensor (TSN) determines and monitors the die temperature for reliable operation of the device. The sensor outputs a voltage directly proportional to the die temperature, and the relationship between the die temperature and the output voltage is fairly linear. The output voltage is provided to the ADC12 for conversion and can be further used by the end application. Table 1.10 Data processing Feature Functional description Cyclic Redundancy Check (CRC) calculator The Cyclic Redundancy Check (CRC) generates CRC codes to detect errors in the data. The bit order of CRC calculation results can be switched for LSB-first or MSB-first communication. Additionally, various CRC-generation polynomials are available. Data Operation Circuit (DOC) The Data Operation Circuit (DOC) compares, adds, and subtracts 16-bit data. When a selected condition applies, 16-bit data is compared and an interrupt can be generated. Table 1.11 I/O ports Feature Functional description Programmable I/O ports ● I/O ports for the 64-pin LQFP – I/O pins: 45 – Input pins: 5 – Pull-up resistors: 46 – N-ch open-drain outputs: 45 – 5-V tolerance: 11

• I/O ports for the 48-pin QFN – I/O pins: 29 – Input pins: 5 – Pull-up resistors: 30 – N-ch open-drain outputs: 29 – 5-V tolerance: 6
• I/O ports for the 32-pin QFN – I/O pins: 16 – Input pins: 5 – Pull-up resistors: 17 – N-ch open-drain outputs: 16 – 5-V tolerance: 4
• I/O ports for the 64-pin BGA – I/O pins: 45 – Input pins: 5 – Pull-up resistors: 46 – N-ch open-drain outputs: 45 – 5-V tolerance: 11
• I/O ports for the 36-pin BGA – I/O pins: 20 – Input pins: 4 – Pull-up resistors: 21 – N-ch open-drain outputs: 20 – 5-V tolerance: 5 RA6E2 Datasheet 1. Overview R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 5 of 92

1.2 Block Diagram

Figure 1.1 shows a block diagram of the MCU superset. Some individual devices within the group have a subset of the features. Memory

256 KB code flash

4 KB data flash

40 KB SRAM

DMAC × 8 System Mode control Power control Register write protection MOSC/SOSC Clocks (H/M/L) OCO PLL GPT16E x 6 Timers AGT × 2 RTC Arm Cortex-M33 DTC CAC POR/LVD Reset ELC Event link TRNG Security Analog CRC Data processing DOC Communication interfaces QSPI I3C SPI × 2 CANFD USBFS SCI × 2 TSN DAC12 × 2 ADC12

1 KB Standby

Note: Not available on all parts Figure 1.1 Block diagram

1.3 Part Numbering

Figure 1.2 shows the product part number information, including memory capacity and package type. Table 1.12 shows a list of products. RA6E2 Datasheet 1. Overview R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 6 of 92

# A A 0R 7 F A 6 E 2 B B 3 C F M Package type FM: LQFP 64 pins NE: QFN 48 pins NH: QFN 32 pins BB: BGA 36 pins BC: BGA 32 pins Quality Grade Operating temperature 2: -40 C to 85 C 3: -40 C to 105 C Code flash memory size 9: 128 KB B: 256 KB Feature set Group name Series name RA family Flash memory Renesas microcontroller Terminal material (Pb-free) A: Sn (Tin) only C: Others Production identification code Packing A: Tray B: Tray (Full carton) Note: Check the order screen for each product on the Renesas website for valid symbols after the #. Figure 1.2 Part numbering scheme Table 1.12 Product list Product part number Package code Code flash Data flash SRAM Operating temperature R7FA6E2BB3CFM PLQP0064KB-C 256 KB 4 KB 40 KB -40 to +105°C R7FA6E2BB3CNE PWQN0048KC-A R7FA6E2BB3CNH PWQN0032KE-A R7FA6E2BB2CBB PLBG0064KB-A -40 to +85°C R7FA6E2BB2CBC PLBG0036KA-A R7FA6E2B93CFM PLQP0064KB-C 128 KB 4 KB 40 KB -40 to +105°C R7FA6E2B93CNE PWQN0048KC-A R7FA6E2B93CNH PWQN0032KE-A R7FA6E2B92CBB PLBG0064KB-A -40 to +85°C R7FA6E2B92CBC PLBG0036KA-A RA6E2 Datasheet 1. Overview R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 7 of 92

1.4 Function Comparison

Table 1.13 Function Comparison Part numbers R7FA6E2BB3CFM/ R7FA6E2BB2CBB R7FA6E2B93CFM/ R7FA6E2B92CBB R7FA6E2BB3CNE R7FA6E2B93CNE R7FA6E2BB2CBC R7FA6E2B92CBC R7FA6E2BB3CNH R7FA6E2B93CNH Pin count 64 48 36 32 Package LQFP/BGA QFN BGA QFN Code flash memory 256 KB, 128 KB Data flash memory 4 KB SRAM 40 KB Parity 32 KB ECC 8 KB Standby SRAM 1 KB DMA DTC Yes DMAC 8 System CPU clock 200 MHz (max.) CPU clock sources MOSC, SOSC, HOCO, MOCO, LOCO, PLL CAC Yes WDT/IWDT Yes Communication SCI 2 I3C 1 SPI 2 CANFD 1 USBFS Yes No QSPI Yes SSIE Yes CEC Yes Timers GPT16E*1 6 5 4 AGT*1 2 RTC*1 Yes Analog ADC12 12 8 4 5 DAC12 2 1 TSN Yes Data processing CRC Yes DOC Yes Event control ELC Yes Security TrustZone I/O ports I/O pins 45 29 20 16 Input pins 5 5 4 5 Pull-up resistors 46 30 21 17 N-ch open-drain outputs 45 29 20 16 5-V tolerance 11 6 5 4 Note 1. Available pins depend on the pin count, see section 1.7. Pin Lists for details. RA6E2 Datasheet 1. Overview R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 8 of 92

1.5 Pin Functions

Table 1.14 Pin functions (1 of 3) Function Signal I/O Description Power supply VCC Input Power supply pin. Connect it to the system power supply. Connect this pin to VSS by a 0.1-µF capacitor. The capacitor should be placed close to the pin. VCL I/O Connect this pin to the VSS pin by the smoothing capacitor used to stabilize the internal power supply. Place the capacitor close to the pin. VSS Input Ground pin. Connect it to the system power supply (0 V). Clock XTAL Output Pins for a crystal resonator. An external clock signal can be input through the EXTAL pin.EXTAL Input XCIN Input Input/output pins for the sub-clock oscillator. Connect a crystal resonator between XCOUT and XCIN.XCOUT Output CLKOUT Output Clock output pin Operating mode control MD Input Pin for setting the operating mode. The signal level on this pin must not be changed during operation mode transition on release from the reset state. System control RES Input Reset signal input pin. The MCU enters the reset state when this signal goes low. CAC CACREF Input Measurement reference clock input pin On-chip emulator SWDIO I/O Serial wire debug data input/output pin SWCLK Input Serial wire clock pin Interrupt NMI Input Non-maskable interrupt request pin IRQn Input Maskable interrupt request pins IRQn-DS Input Maskable interrupt request pins that can also be used in Deep Software Standby mode GPT GTETRGA, GTETRGB, GTETRGC, GTETRGD Input External trigger input pins GTIOCnA, GTIOCnB I/O Input capture, output compare, or PWM output pins GTADSM0, GTADSM1 Output A/D conversion start request monitoring output pins GTIU Input Hall sensor input pin U GTIV Input Hall sensor input pin V GTIW Input Hall sensor input pin W GTOUUP Output 3-phase PWM output for BLDC motor control (positive U phase) GTOULO Output 3-phase PWM output for BLDC motor control (negative U phase) GTOVUP Output 3-phase PWM output for BLDC motor control (positive V phase) GTOVLO Output 3-phase PWM output for BLDC motor control (negative V phase) GTOWUP Output 3-phase PWM output for BLDC motor control (positive W phase) GTOWLO Output 3-phase PWM output for BLDC motor control (negative W phase) AGT AGTEEn Input External event input enable signals AGTIOn I/O External event input and pulse output pins AGTOn Output Pulse output pins AGTOAn Output Output compare match A output pins AGTOBn Output Output compare match B output pins RA6E2 Datasheet 1. Overview R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 9 of 92

Table 1.14 Pin functions (2 of 3) Function Signal I/O Description RTC RTCOUT Output Output pin for 1-Hz or 64-Hz clock RTCICn Input Time capture event input pins SCI SCKn I/O Input/output pins for the clock (clock synchronous mode) RXDn Input Input pins for received data (asynchronous mode/clock synchronous mode) TXDn Output Output pins for transmitted data (asynchronous mode/clock synchronous mode) CTSn_RTSn I/O Input/output pins for controlling the start of transmission and reception (asynchronous mode/clock synchronous mode), active- low. CTSn Input Input for the start of transmission. SCLn I/O Input/output pins for the IIC clock (simple IIC mode) SDAn I/O Input/output pins for the IIC data (simple IIC mode) SCKn I/O Input/output pins for the clock (simple SPI mode) MISOn I/O Input/output pins for slave transmission of data (simple SPI mode) MOSIn I/O Input/output pins for master transmission of data (simple SPI mode) SSn Input Chip-select input pins (simple SPI mode), active-low I3C I3C_SCL I/O Input/output pins for the I3C clock I3C_SDA I/O Input/output pins for the I3C data SCL0 I/O Input/output pins for the I2C clock SDA0 I/O Input/output pins for the I2C data SPI RSPCKA, RSPCKB I/O Clock input/output pin MOSIA, MOSIB I/O Input or output pins for data output from the master MISOA, MISOB I/O Input or output pins for data output from the slave SSLA0, SSLB0 I/O Input or output pin for slave selection SSLA1 to SSLA3, SSLB1 to SSLB3 Output Output pins for slave selection CANFD CRX0 Input Receive data CTX0 Output Transmit data USBFS VCC_USB Input Power supply pin VSS_USB Input Ground pin USB_DP I/O D+ pin of the USB on-chip transceiver. Connect this pin to the D+ pin of the USB bus. USB_DM I/O D- pin of the USB on-chip transceiver. Connect this pin to the D- pin of the USB bus. USB_VBUS Input USB cable connection monitor pin. Connect this pin to VBUS of the USB bus. The VBUS pin status (connected or disconnected) can be detected when the USB module is operating as a function controller. QSPI QSPCLK Output QSPI clock output pin QSSL Output QSPI slave output pin QIO0 to QIO3 I/O Data0 to Data3 RA6E2 Datasheet 1. Overview R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 10 of 92

Table 1.14 Pin functions (3 of 3) Function Signal I/O Description SSIE SSIBCK0 I/O SSIE serial bit clock pins SSILRCK0/SSIFS0 I/O LR clock/frame synchronization pins SSITXD0 Output Serial data output pin SSIRXD0 Input Serial data input pin SSIDATA0 I/O Serial data input/output pins AUDIO_CLK Input External clock pin for audio (input oversampling clock) CEC CECIO I/O CEC data communication Analog power supply AVCC0 Input Analog voltage supply pin. This is used as the analog power supply for the respective modules. Supply this pin with the same voltage as the VCC pin. AVSS0 Input Analog ground pin. This is used as the analog ground for the respective modules. Supply this pin with the same voltage as the VSS pin. VREFH Input Analog reference voltage supply pin for the D/A Converter. VREFL Input Analog reference ground pin for the D/A Converter. VREFH0 Input Analog reference voltage supply pin for the ADC12. Connect this pin to AVCC0 when not using the ADC12. VREFL0 Input Analog reference ground pin for the ADC12. Connect this pin to AVSS0 when not using the ADC12. ADC12 AN0n Input Input pins for the analog signals to be processed by the A/D converter. (n: pin number) ADTRG0 Input Input pins for the external trigger signals that start the A/D conversion, active-low. DAC12 DAn Output Output pins for the analog signals processed by the D/A converter. I/O ports Pmn I/O General-purpose input/output pins (m: port number, n: pin number) P200 Input General-purpose input pin RA6E2 Datasheet 1. Overview R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 11 of 92

1.6 Pin Assignments

The following figures show the pin assignments from the top view. 1 0 1 1 1 2 1 3 1 4 1 5 1 6 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 P008 P006 P015 P014 P003 V R E F H /A VCC0 V R E F L /A VSS0 VREFL0 VREFH0 P 00 5 P 00 4 P 002 P 001 P013 P 300/SWCLK P301 P302 P303 P304 P201/MD RES P20 8 P 205 P 206 P207 VCC_USB P814/USB_DP P815/USB_DM VSS_USB P200 P100 P102 P103 P104 P105 P106 P107 VSS VCC P 113 P 112 P 111 P 110 P108 /SWDIO P101 P10 9 P400 P402 P403 VCL XCIN XCOUT VSS P 2 1 3 /X TAL P 2 1 2 /E X TAL VCC P 4 11 P410 P408 P407 P401 P409 P 000 P500 Figure 1.3 Pin assignment for LQFP 64-pin P109 G H D E FA B C G H D E FA B C P013 P014 P006 P500 VREFH0 P015 P008 P100 VREFH/ AVCC0 P103 P102 P101 VCC P106 P105 P104 P000 P001 P005 P003 P400 P002 P004 VREFL0 VCL P401 P402 VREFL/ AVSS0 XCIN VSS P403 VSS XCOUT VCC P411 VSS_USB VCC_USB P107 P113 P112 P213/ XTAL P409 P410 P208 RES P302 P111 P110 P212/ EXTAL P408 P207 P206 P201/ MD P303 P301 P407 P815/ USB_DM P814/ USB_DP P205 P200 P304 P300/ SWCLK P108/ SWDIO Figure 1.4 Pin assignment for BGA 64-pin RA6E2 Datasheet 1. Overview R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 12 of 92

1.7 Pin Lists

Table 1.15 Pin list (1 of 2) LQFP64 BGA64 QFN48 BGA36 QFN32 Power, System, Clock, Debug, CAC I/O ports Ex. Interrupt SCI/I3C/SPI/ CANFD/USBFS/ QSPI/SSIE/CEC GPT/AGT/RTC ADC12/DAC12

1 G8 — — — — P400 IRQ0 SCL0_A AGTIO1 —

2 F7 — — — — P401 IRQ5-DS SDA0_A/CTX0 GTETRGA —

3 F6 1 — — CACREF P402 IRQ4-DS CRX0/AUDIO_CLK AGTIO0/AGTIO1/

4 E6 2 — — — P403 IRQ14-DS — GTIOC3A/AGTIO0/

5 F8 3 E5 2 VCL — — — — —

8 E7 6 D4 4 VSS — — — — —

9 C8 7 C6 5 XTAL P213 IRQ2 TXD0/MOSI0/SDA0/

AUDIO_CLK GTIOC0A/ GTETRGC

10 B8 8 B6 6 EXTAL P212 IRQ3 RXD0/MISO0/SCL0 GTIOC0B/

11 D7 9 D3 7 VCC — — — — —

12 D6 — — — — P411 IRQ4 TXD0/MOSI0/SDA0 GTOVUP —

13 C6 — — — — P410 IRQ5 RXD0/MISO0/SCL0 GTOVLO —

14 C7 10 — — — P409 IRQ6 — GTIOC1A/GTOWUP/

15 B7 11 B5 — — P408 IRQ7 SCL0_B/

AUDIO_CLK GTIOC1B/GTIW/ AGTOB1

16 A8 12 A6 8 — P407 — SDA0_B/

SSIBCK0_A/ USB_VBUS GTIV/AGTIO0/ RTCOUT/GTADSM0 ADTRG0

18 A7 14 A5 — USB_DM P815 — — GTIOC0A/

19 A6 15 A4 — USB_DP P814 — — GTIOC0B/GTETRGB —

21 B6 17 C5 9 CACREF P207 — SCK9/MOSIA_A/

QSSL/SSILRCK0_A/ SSIFS0_A GTIOC5A/GTIW/ AGTIO1

22 B5 18 B4 10 — P206 IRQ0-DS CTS9/SDA0_C/

MISOA_A/ SSIDATA0_A/CECIO GTIOC5B/GTIU —

23 A5 — — — CLKOUT P205 IRQ1-DS CTS_RTS9/SS9/

SCL0_C/SSLA3_A GTIOC4A/GTIV/ AGTO1

24 C5 — — — — P208 — — GTOVLO ADTRG0

25 C4 19 B3 11 RES — — — — —

26 B4 20 D5 12 MD P201 — — — —

27 A4 21 A3 13 — P200 NMI — — —

28 A3 — — — — P304 IRQ9 — GTOWLO —

30 C3 22 C2 14 — P302 IRQ5 CTS0/SCK9/

RSPCKA_A/ SSITXD0_A GTIOC4A/GTOUUP/ RTCOUT

31 B2 23 B2 15 — P301 IRQ6 CTS_RTS9/SS9/

SSLA0_A/ SSIRXD0_A GTIOC4B/GTOULO/ AGTIO0

32 A2 24 A2 16 SWCLK P300 — SSLA1_B GTIOC0A/GTOUUP —

33 A1 25 A1 17 SWDIO P108 — CTS_RTS9/SS9/

SSLA0_B GTIOC0B/GTOULO —

34 B1 26 B1 18 CLKOUT P109 — TXD9/MOSI9/SDA9/

MOSIA_B/CTX0/ SSITXD0_B GTIOC1A/GTOVUP/ AGTOA0

35 C1 27 C1 19 — P110 IRQ3 RXD9/MISO9/SCL9/

MISOA_B/CRX0/ SSIRXD0_B GTIOC1B/GTOVLO/ AGTOB0 RA6E2 Datasheet 1. Overview R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 14 of 92

Table 1.15 Pin list (2 of 2) LQFP64 BGA64 QFN48 BGA36 QFN32 Power, System, Clock, Debug, CAC I/O ports Ex. Interrupt SCI/I3C/SPI/ CANFD/USBFS/ QSPI/SSIE/CEC GPT/AGT/RTC ADC12/DAC12

36 C2 28 — — — P111 IRQ4 SCK9/RSPCKA_B/

SSIDATA0_B GTIOC3A —

37 D1 29 — — — P112 — SSLA0_B/QSSL GTIOC3B/

39 E4 30 C3 20 VCC — — — — —

40 E5 31 C4 21 VSS — — — — —

41 D3 — — — — P107 — SSLA2_B AGTOA0 —

42 E3 — — — — P106 — SSLB3 AGTOB0 —

43 E2 — — — — P105 IRQ0 SSLB2 GTIOC1A/GTETRGA —

44 E1 32 — — — P104 IRQ1 SSLB1/QIO2 GTIOC1B/

45 F3 33 D2 — — P103 — CTS_RTS0/SS0/

SSILRCK0_B/ SSIFS0_B GTIOC2A/GTOWUP —

46 F2 34 D1 22 — P102 — SCK0/RSPCKB/

SSIBCK0_B GTIOC2B/GTOWLO/ AGTO0 ADTRG0

47 F1 35 E1 23 — P101 IRQ1 TXD0/MOSI0/SDA0/

I3C_SDA/SDA0_D/ MOSIB/QIO1 GTIOC5A/ GTETRGB/AGTEE0

48 G1 36 F1 24 — P100 IRQ2 RXD0/MISO0/SCL0/

I3C_SCL/SCL0_D/ MISOB/QSPCLK/ AUDIO_CLK GTIOC5B/ GTETRGA/AGTIO0

49 H1 37 — — CACREF P500 — QSPCLK GTIU/AGTOA0 AN016

50 G2 — — — — P008 IRQ12-DS — — AN008

51 H2 — — — — P006 IRQ11-DS — — AN006

52 G3 38 — — — P015 IRQ13 — — AN013/DA1

53 H3 39 E2 25 — P014 — — — AN012/DA0

54 H4 40 — — — P013 — — — AN011

55 H5 41 F2 26 — P003 — — — AN007

56 F4 42 E3 27 VREFH/AVCC0 — — — — —

57 F5 43 E4 28 VREFL/AVSS0 — — — — —

58 G5 44 F4 29 VREFL0 — — — — —

59 G4 45 F3 30 VREFH0 — — — — —

60 H6 — — — — P005 IRQ10-DS — — AN005

61 G6 — — — — P004 IRQ9-DS — — AN004

62 G7 46 — 31 — P002 IRQ8-DS — — AN002

63 H7 47 F5 32 — P001 IRQ7-DS — — AN001

64 H8 48 F6 1 — P000 IRQ6-DS — — AN000

Note: Several pin names have the added suffix of _A, _B, _C, and _D. The suffix can be ignored when assigning functionality. Note 1. XCIN cannot be used in QFN32. XCIN must be connected to VSS through a resistor (pull down). RA6E2 Datasheet 1. Overview R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 15 of 92

1. Electrical Characteristics Supported peripheral functions and pins differ from one product name to another. Unless otherwise specified, the electrical characteristics of the MCU are defined under the following conditions:

• VCC = A VCC0 = VCC_USB = 2.7 to 3.6
• 2.7 ≤ VREFH0/VREFH ≤ A VCC0
• VSS = A VSS0 = VREFL0/VREFL = VSS_USB = 0 V
• Ta = Topr Figure 2.1 shows the timing conditions. For example, P100 C V OH = VCC × 0.7, V OL = VCC × 0.3 V IH = VCC × 0.7, V IL = VCC × 0.3 Load capacitance C = 30 pF Figure 2.1 Input or output timing measurement conditions The recommended measurement conditions for the timing specification of each peripheral provided are for the best peripheral operation. Make sure to adjust the driving abilities of each pin to meet your conditions.

2.1 Absolute Maximum Ratings

Table 2.1 Absolute maximum ratings Parameter Symbol Value Unit Power supply voltage VCC, VCC_USB*2 –0.3 to +4.0 V Input voltage (except for 5 V-tolerant ports*1) Vin –0.3 to VCC + 0.3 V Input voltage (5 V-tolerant ports*1) Vin –0.3 to + VCC + 4.0 (max. 5.8) V Reference power supply voltage VREFH/VREFH0 –0.3 to VCC + 0.3 V Analog power supply voltage AVCC0*2 –0.3 to +4.0 V Analog input voltage VAN –0.3 to AVCC0 + 0.3 V Operating temperature*3 *4 *5 Topr –40 to +105 °C Storage temperature Tstg –55 to +125 °C Note 1. Ports P100, P101, P205, P206, P400, P401 and P407 to P411 are 5 V tolerant. Note 2. Connect AVCC0 and VCC_USB to VCC. Note 4. Contact a Renesas Electronics sales office for information on derating operation when Ta = +85°C to +105°C. Derating is the systematic reduction of load for improved reliability. Note 5. The upper limit of operating temperature is +85°C or +105°C, depending on the product. For details, see section x.x. Part Numbering. RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 16 of 92

Caution: Permanent damage to the MCU might result if absolute maximum ratings are exceeded. Table 2.2 Recommended operating conditions Parameter Symbol Value Min Typ Max Unit Power supply voltages VCC When USB is not used 2.7 — 3.6 V When USB is used 3.0 — 3.6 V VSS — 0 — V USB power supply voltages VCC_USB — VCC — V VSS_USB — 0 — V Analog power supply voltages AVCC0*1 — VCC — V AVSS0 — 0 — V Note 1. Connect AVCC0 to VCC. When the A/D converter and the D/A converter are not in use, do not leave the AVCC0, VREFH/VREFH0, AVSS0, and VREFL/VREFL0 pins open. Connect the AVCC0 and VREFH/VREFH0 pins to VCC, and the AVSS0 and VREFL/ VREFL0 pins to VSS, respectively.

2.2 DC Characteristics

2.2.1 Tj/Ta Definition

Table 2.3 DC characteristics Parameter Symbol Typ Max Unit Test conditions Permissible junction temperature Tj — 125 °C High-speed mode Low-speed mode Subosc-speed mode105*1 Note: Make sure that T j = Ta + θja × total power consumption (W), where total power consumption = (VCC - VOH) × ΣIOH + VOL × ΣIOL + ICCmax × VCC. Note 1. The upper limit of operating temperature is 85°C or 105°C, depending on the product. If the part number shows the operation temperature to 85°C, then Tj max is 105°C, otherwise, 125°C.

2.2.2 I/O VIH, VIL

Table 2.4 I/O VIH, VIL (1 of 2) Parameter Symbol Min Typ Max Unit Input voltage (except for Schmitt trigger input pins) Peripheral function pin EXTAL (external clock input), SPI (except RSPCK) VIH VCC × 0.8 — — V VIL — — VCC × 0.2 I3C (SMBus) VIH 2.1 — VCC + 3.6 (max 5.8) VIL — — 0.8 RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 17 of 92

Table 2.4 I/O VIH, VIL (2 of 2) Parameter Symbol Min Typ Max Unit Schmitt trigger input voltage Peripheral function pin I3C (except for SMBus) VIH VCC × 0.7 — VCC + 3.6 (max 5.8) V VIL — — VCC × 0.3 ΔVT VCC × 0.05 — — 5 V-tolerant ports*1 *5 VIH VCC × 0.8 — VCC + 3.6 (max 5.8) VIL — — VCC × 0.2 ΔVT VCC × 0.05 — — Other input pins*2 VIH VCC × 0.8 — — VIL — — VCC × 0.2 ΔVT VCC × 0.05 — — Ports 5 V-tolerant ports*3 *5 VIH VCC × 0.8 — VCC + 3.6 (max 5.8) V VIL — — VCC × 0.2 Other input pins*4 VIH VCC × 0.8 — — VIL — — VCC × 0.2 Note 1. RES and peripheral function pins associated with P100, P101, P205, P206, P400, P401, P407 to P411 (total 12 pins). Note 2. All input pins except for the peripheral function pins already described in the table. Note 3. P100, P101, P205, P206, P400, P401, P407 to P411 (total 11pins). Note 4. All input pins except for the ports already described in the table. Note 5. When VCC is less than 2.7 V, the input voltage of 5 V-tolerant ports should be less than 3.6 V, otherwise breakdown may occur because 5 V-tolerant ports are electrically controlled so as not to violate the break down voltage. RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 18 of 92

2.2.3 I/O IOH, IOL

Table 2.5 I/O IOH, IOL (1 of 2) Parameter Symbol Min Typ Max Unit Permissible output current (average value per pin) I3C pins IIC Standard mode*4 IOL — — 3.0 mA IIC Fast mode*4 IOL — — 6.0 mA IIC Fast mode plus*4 IOL — — 20 mA IIC High speed mode*4 IOL — — 3.0 mA Ports P004 to P006, P008, P013 to P015, P201 — IOH — — –2.0 mA IOL — — 2.0 mA Ports P205, P206, P407 to P411 (total 7 pins) Low drive*1 IOH — — –2.0 mA IOL — — 2.0 mA Middle drive*2 IOH — — –4.0 mA IOL — — 4.0 mA High drive*3 IOH — — –20 mA IOL — — 20 mA Other output pins*5 Low drive*1 IOH — — –2.0 mA IOL — — 2.0 mA Middle drive*2 IOH — — –4.0 mA IOL — — 4.0 mA High drive*3 IOH — — –16 mA IOL — — 16 mA Permissible output current (max value per pin) I3C pins IIC Standard mode*4 IOL — — 3.0 mA IIC Fast mode*4 IOL — — 6.0 mA IIC Fast mode plus*4 IOL — — 20 mA IIC High speed mode*4 IOL — — 3.0 mA Ports P004 to P006, P008, P013 to P015, P201 — IOH — — –4.0 mA IOL — — 4.0 mA Ports P205, P206, P407 to P411 (total 7 pins) Low drive*1 IOH — — –4.0 mA IOL — — 4.0 mA Middle drive*2 IOH — — –8.0 mA IOL — — 8.0 mA High drive*3 IOH — — –40 mA IOL — — 40 mA Other output pins*5 Low drive*1 IOH — — –4.0 mA IOL — — 4.0 mA Middle drive*2 IOH — — –8.0 mA IOL — — 8.0 mA High drive*3 IOH — — –32 mA IOL — — 32 mA RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 19 of 92

Table 2.5 I/O IOH, IOL (2 of 2) Parameter Symbol Min Typ Max Unit Permissible output current (maxvalue of total of all pins) Maximum of all output pins ΣIOH (max) — — –80 mA ΣIOL (max) — — 80 mA Note 1. This is the value when low driving ability is selected in the Port Drive Capability bit in the PmnPFS register. The selected driving ability is retained in Deep Software Standby mode. Note 2. This is the value when middle driving ability is selected in the Port Drive Capability bit in the PmnPFS register. The selected driving ability is retained in Deep Software Standby mode. Note 3. This is the value when high driving ability is selected in the Port Drive Capability bit in the PmnPFS register. The selected driving ability is retained in Deep Software Standby mode. Note 4. SCL0_D, SDA0_D (total 2 pins). This is the value when IIC function is selected. Note 5. Except for P000 to P003, P200, which is an input port. Caution: To protect the reliability of the MCU, the output current values should not exceed the values in this table. The average output current indicates the average value of current measured during 100 µs.

2.2.4 I/O VOH, VOL, and Other Characteristics

Table 2.6 I/O VOH, VOL, and other characteristics (1 of 2) Parameter Symbol Min Typ Max Unit Test conditions Output voltage I3C*1 VOL — — 0.4 V IOL = 3.0 mA VOL — — 0.6 IOL = 6.0 mA I3C*2 VOH VCC - 0.27 — — IOH = 3.0 mA (PRTS.PRTMD = 0) VOL — — 0.4 IOL = 15.0 mA (PRTS.PRTMD = 1, BFCTL.FMPE = 1) VOL — 0.4 — IOL = 20.0 mA (PRTS.PRTMD = 1, BFCTL.FMPE = 1) VOL — — 0.4 IOL = 3.0 mA (PRTS.PRTMD = 1, BFCTL.HSME = 1) VOL — — 0.27 IOL = 3.0 mA (PRTS.PRTMD = 0) Ports P205, P206, P407 to P411(total 7 pins)*3 VOH VCC - 1.0 — — IOH = –20 mA VCC = 3.3 V VOL — — 1.0 IOL = 20 mA VCC = 3.3 V Other output pins VOH VCC - 0.5 — — IOH = –1.0 mA VOL — — 0.5 IOL = 1.0 mA Input leakage current RES |Iin| — — 5.0 µA Vin = 0 V Vin = 5.5 V Port P000 to P003, P200 — — 1.0 Vin = 0 V Vin = VCC Three-state leakage current (off state)

5 V-tolerant ports

(except for port P100, P101) |ITSI| — — 5.0 µA Vin = 0 V Vin = 5.5 V (P100, P101) — — 10.0 Vin = 0 V Vin = 5.5 V Other ports (except for port P000 to P003, P200) — — 1.0 Vin = 0 V Vin = VCC Input pull-up MOS current Ports P0 to P5, P8 (except for ports P000 to P003) Ip –300 — –10 µA VCC = 2.7 to 3.6 V Vin = 0 V RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 20 of 92

Table 2.6 I/O VOH, VOL, and other characteristics (2 of 2) Parameter Symbol Min Typ Max Unit Test conditions Pull-up current serving as the SCL current source I3C*4 ICS 3 — 12 mA VCC = 3.0 to 3.6 V Vin = 0.3 × VCC to 0.7 × VCC Input capacitance Ports P003, P014, P015,P814, P815 Cin — — 16 pF Vbias = 0 V Vamp = 20 mV f = 1 MHz Ta = 25°COther input pins — — 8 Note 1. SCL0_A, SCL0_B, SCL0_C, SDA0_A, SDA0_B, and SDA0_C (total 6 pins). Note 2. I3C_SCL/SCL0_D, I3C_SDA/SDA0_D (total 2 pins). Note 3. This is the value when high driving ability is selected in the Port Drive Capability bit in the PmnPFS register. The selected driving ability is retained in Deep Software Standby mode. Note 4. I3C_SCL/SCL0_D (1 pin). This is the value when IIC high speed mode is selected.

2.2.5 Operating and Standby Current

Table 2.7 Operating and standby current (1 of 2) Parameter Symbol Min Typ Max Unit Test conditions Supply current*1 High-speed mode Maximum*2 ICC*3 — — 65 mA ICLK = 200 MHz PCLKA = 100 MHz PCLKB = 50 MHz PCLKC = 50 MHz PCLKD = 100 MHz FCLK = 50 MHz Normal mode All peripheral clocks enabled, while (1) code executing from flash*4 — 18.6 — All peripheral clocks disabled, while (1) code executing from flash*5 *6 — 14.7 — Sleep mode*5 *6 — 7.5 43 Increase during BGO operation Data flash P/E — 6 — Code flash P/E — 8 — Low-speed mode*5 *9 — 1.8 — ICLK = 1 MHz Subosc-speed mode*5 *10 — 1.6 — ICLK = 32.768 kHz Software Standby mode SNZCR.RXDREQEN = 1 — — 35 — SNZCR.RXDREQEN = 0 — 1.4 — — Deep Software Standby mode Power supplied to Standby SRAM and USB resume detecting unit — 16 96 µA — Power not supplied to SRAM or USB resume detecting unit Power-on reset circuit low power function disabled — 11 25.6 — Power-on reset circuit low power function enabled — 4.2 20.4 — Increase when the RTC and AGT are operating When the low-speed on-chip oscillator (LOCO) is in use — 4.5 — — When a crystal oscillator for low clock loads is in use — 1.0 — — When a crystal oscillator for standard clock loads is in use — 1.4 — — Inrush current on returning from deep software standby mode Inrush current*7 IRUSH — 160 — mA — Energy of inrush current*7 ERUSH — 1.0 — µC — RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 21 of 92

Table 2.7 Operating and standby current (2 of 2) Parameter Symbol Min Typ Max Unit Test conditions Analog power supply current During 12-bit A/D conversion AICC, AIREFH — 0.8 1.2 mA — Temperature sensor — 0.1 0.2 mA — During D/A conversion (per unit) Without AMP output — 0.2 0.6 mA — With AMP output — 0.7 1.5 mA — Waiting for A/D, D/A conversion (all units) — 0.5 1.0 mA — ADC12, DAC12 in standby modes (all units)*8 — 0.4 6 µA — Reference power supply current (VREFH0) During 12-bit A/D conversion (unit 0) AIREFH0 — 70 120 µA — Waiting for 12-bit A/D conversion (unit 0) — 0.07 0.5 µA — ADC12 in standby modes (unit 0) — 0.07 0.5 µA — USB operating current Full speed USB ICCUSBFS — 4.0 10.0 mA VCC_USB Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state. Note 2. Measured with clocks supplied to the peripheral functions. This does not include the BGO operation. Note 3. ICC depends on f (ICLK) as follows. ICC Max. = 0.14 × f + 37 (max. operation in high-speed mode) ICC Typ. = 0.06 × f + 2.75 (normal operation in high-speed mode, all peripheral clocks disabled) ICC Typ. = 0.1× f + 1.71 (low-speed mode) ICC Max. = 0.03 × f + 37 (sleep mode) Note 4. This does not include the BGO operation. Note 5. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation. Note 6. FCLK, PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (3.125 MHz). Note 7. Reference value Note 8. When the MCU is in Software Standby mode or the MSTPCRD.MSTPD16 (12-Bit A/D Converter 0 Module Stop bit) is in the module-stop state. Note 9. FCLK, PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (15.6 kHz). Note 10. PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (512 Hz). FCLK is the same frequency as that of ICLK. Table 2.8 Coremark and normal mode current Parameter Symbol Typ Unit Test conditions Supply Current*1 Coremark*2 ICC 80 µA/MHz ICLK = 200 MHz PCLKA = PCLKB = PCLKC = PCLKD = FCLK =

3.125 MHz

Normal mode All peripheral clocks disabled, cache on, while (1) code executing from flash*2 All peripheral clocks disabled, cache off, while (1) code executing from flash*2 Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state. Note 2. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation. RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 22 of 92

2.2.6 VCC Rise and Fall Gradient and Ripple Frequency

Table 2.9 Rise and fall gradient characteristics Parameter Symbol Min Typ Max Unit Test conditions VCC rising gradient Voltage monitor 0 reset disabled at startup SrVCC 0.0084 — 20 ms/V — Voltage monitor 0 reset enabled at startup 0.0084 — — — SCI/USB boot mode*1 0.0084 — 20 — VCC falling gradient SfVCC 0.0084 — — ms/V — Note 1. At boot mode, the reset from voltage monitor 0 is disabled regardless of the value of the OFS1.LVDAS bit. Table 2.10 Rising and falling gradient and ripple frequency characteristics The ripple voltage must meet the allowable ripple frequency fr(VCC) within the range between the VCC upper limit (3.6 V) and lower limit (2.7 V). When the VCC change exceeds VCC ±10%, the allowable voltage change rising and falling gradient dt/dVCC must be met. Parameter Symbol Min Typ Max Unit Test conditions Allowable ripple frequency fr (VCC) — — 10 kHz Figure 2.6 Vr (VCC) ≤ VCC × 0.2 — — 1 MHz Figure 2.6 Vr (VCC) ≤ VCC × 0.08 — — 10 MHz Figure 2.6 Vr (VCC) ≤ VCC × 0.06 Allowable voltage change rising and falling gradient dt/dVCC 1.0 — — ms/V When VCC change exceeds VCC ±10% V r(VCC)VCC 1 / f r(VCC) Figure 2.6 Ripple waveform

2.2.7 Thermal Characteristics

Maximum value of junction temperature (Tj) must not exceed the value of “section 2.2.1. Tj/Ta Definition”. Tj is calculated by either of the following equations.

• Tj = Ta + θja × Total power consumption
• Tj = Tt + Ψjt × Total power consumption – Tj : Junction Temperature (°C) – Ta : Ambient Temperature (°C) – Tt : Top Center Case Temperature (°C) – θja : Thermal Resistance of “Junction”-to-“Ambient” (°C/W) – Ψjt : Thermal Resistance of “Junction”-to-“Top Center Case” (°C/W)
• Total power consumption = V oltage × (Leakage current + Dynamic current) RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 25 of 92

• Leakage current of IO = Σ (IOL × VOL) /V oltage + Σ (|IOH| × |VCC – VOH|) /V oltage
• Dynamic current of IO = Σ IO (Cin + Cload) × IO switching frequency × V oltage – Cin: Input capacitance – Cload: Output capacitance Regarding θja and Ψjt, refer to Table 2.11. Table 2.11 Thermal Resistance Parameter Package Symbol Value*1 Unit Test conditions Thermal Resistance 32-pin QFN (PWQN0032KE-A) θja 36.8 °C/W JESD 51-2 and 51-7 compliant48-pin QFN (PWQN0048KC-A) 29.7 64-pin LQFP (PLQP0064KB-C) 41.3 36-pin BGA (PLBG0036KA-A) 53.7 64-pin BGA (PLBG0064KB-A) 51.6 32-pin QFN (PWQN0032KE-A) Ψjt 0.36 °C/W JESD 51-2 and 51-7 compliant48-pin QFN (PWQN0048KC-A) 0.27 64-pin LQFP (PLQP0064KB-C) 1.39 36-pin BGA (PLBG0036KA-A) 1.70 64-pin BGA (PLBG0064KB-A) 1.70 Note 1. The values are reference values when the 4-layer board is used. Thermal resistance depends on the number of layers or size of the board. For details, refer to the JEDEC standards.

2.2.7.1 Calculation guide of ICCmax

Table 2.12 shows the power consumption of each unit. Table 2.12 Power consumption of each unit (1 of 2) Dynamic current/ Leakage current MCU Domain Category Item Frequency [MHz] Current [uA/MHz] Current*1 [mA] Leakage current Analog LDO and Leak*2 Ta = 75 °C*3 — — 25.10 RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 26 of 92

Table 2.12 Power consumption of each unit (2 of 2) Dynamic current/ Leakage current MCU Domain Category Item Frequency [MHz] Current [uA/MHz] Current*1 [mA] Dynamic current CPU Operation with Flash and SRAM Coremark 200 56.885 11.38 Peripheral Unit Timer GPT16 (6ch)*4 100 8.480 0.85 POEG (4 Groups)*4 50 1.171 0.06 AGT (2ch)*4 50 3.967 0.20 RTC 50 2.711 0.27 WDT 50 0.635 0.03 IWDT 50 0.261 0.01 Communication interfaces USBFS 50 4.969 0.25 SCI (2 ch)*4 100 5.607 0.56 I3C 100 8.483 0.85 CANFD 50 2.680 0.27 CEC 100 0.213 0.01 SPI (2ch)*4 100 5.739 0.57 QSPI 100 2.379 0.24 SSIE 50 2.831 0.14 Analog ADC12 100 2.229 0.22 DAC12 (2ch)*4 100 0.602 0.06 TSN 50 0.277 0.01 Event link ELC 50 0.562 0.06 Security TRNG 100 0.013 1.27 Data processing CRC 100 0.363 0.04 DOC 100 0.133 0.01 System CAC 50 0.777 0.04 DMA DMAC 200 4.450 0.89 DTC 200 4.382 0.88 Note 1. The values are guaranteed by design. Note 2. LDO and Leak are internal voltage regulator’s current and MCU’s leakage current. It is selected according to the temperature of Ta. Note 3. Δ(Tj-Ta) = 20 °C is considered to measure the current. Note 4. To determine the current consumption per channel or unit, divide Current [mA] by the number of channels, groups or units. Table 2.13 shows the outline of operation for each unit. Table 2.13 Outline of operation for each unit (1 of 2) Peripheral Outline of operation GPT Operating modes is set to saw-wave PWM mode. GPT is operating with PCLKD. POEG Only clear module stop bit. AGT AGT is operating with PCLKB. RTC RTC is operating with LOCO. WDT WDT is operating with PCLKB. IWDT IWDT is operating with IWDTCLK. RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 27 of 92

Table 2.13 Outline of operation for each unit (2 of 2) Peripheral Outline of operation USBFS Transfer types is set to bulk transfer. USBFS is operating using Full-speed transfer (12 Mbps). SCI SCI is transmitting data in clock synchronous mode. I3C Communication format is set to I3C-bus format. I3C is transmitting data in master mode. CANFD CANFD is transmitting and receiving data in self-test mode 1. SPI SPI mode is set to SPI operation (4-wire method). SPI master/slave mode is set to master mode. SPI is transmitting 8-bit width data. QSPI QSPI is issuing Fast Read Quad I/O Instruction. SSIE Communication mode is set to Master. System word length is set to 32 bits. Data word length is set to 20 bits. SSIE is transmitting data using I2S format. CEC CEC operation clock is set to CECCLK. CEC is transmitting and receiving header block and data block. ADC12 Resolution is set to 12-bit accuracy. Data registers is set to A/D-converted value addition mode. ADC12 is converting the analog input in continuous scan mode. DAC12 DAC12 is outputting the conversion result while updating the value of data register. TSN TSN is operating. ELC Only clear module stop bit. TRNG TRNG is executing built-in self test. CRC CRC is generating CRC code using 32-bit CRC32-C polynomial. DOC DOC is operating in data addition mode. CAC Measurement target clocks is set to PCLKB. Measurement reference clocks is set to PCLKB. CAC is measuring the clock frequency accuracy. DMAC Bit length of transfer data is set to 32 bits. Transfer mode is set to block transfer mode. DMAC is transferring data from SRAM0 to SRAM0. DTC Bit length of transfer data is set to 32 bits. Transfer mode is set to block transfer mode. DTC is transferring data from SRAM0 to SRAM0.

2.2.7.2 Example of Tj calculation

Assumption :

• Package 64-pin LQFP : θja = 41.3 °C/W
• Ta = 100 °C
• ICCmax = 40 mA
• VCC = 3.5 V (VCC = A VCC0 = VCC_USB)
• IOH = 1 mA, VOH = VCC – 0.5 V , 8 Outputs
• IOL = 20 mA, VOL = 1.0 V , 6 Outputs
• IOL = 1 mA, VOL = 0.5 V , 8 Outputs
• Cin = 8 pF, 8 pins, Input frequency = 10 MHz
• Cload = 30 pF, 8 pins, Output frequency = 10 MHz RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 28 of 92

Leakage current of IO = Σ (VOL × IOL) / Voltage + Σ ((VCC - VOH) × IOH) / Voltage = 34.29 mA + 1.14 mA + 1.14 mA = 36.6 mA Dynamic current of IO = Σ IO (Cin + Cload) × IO switching frequency × Voltage = 10.6 mA Total power consumption = Voltage × (Leakage current + Dynamic current) = 305 mW (0.305 W) Tj = Ta + θja × Total power consumption = 112.6 °C

2.3 AC Characteristics

2.3.1 Frequency

Table 2.14 Operation frequency value in high-speed mode Parameter Symbol Min Typ Max Unit Operation frequency System clock (ICLK) f — — 200 MHz Peripheral module clock (PCLKA) — — 100 Peripheral module clock (PCLKB) — — 50 Peripheral module clock (PCLKC) —*2 — 50 Peripheral module clock (PCLKD) — — 100 Flash interface clock (FCLK) —*1 — 50 Note 1. FCLK must run at a frequency of at least 4 MHz when programming or erasing the flash memory. Note 2. When the ADC12 is used, the PCLKC frequency must be at least 1 MHz. Table 2.15 Operation frequency value in low-speed mode Parameter Symbol Min Typ Max Unit Operation frequency System clock (ICLK) f — — 1 MHz Peripheral module clock (PCLKA) — — 1 Peripheral module clock (PCLKB) — — 1 Peripheral module clock (PCLKC) *2 —*2 — 1 Peripheral module clock (PCLKD) — — 1 Flash interface clock (FCLK)*1 — — 1 Note 1. Programming or erasing the flash memory is disabled in low-speed mode. Note 2. When the ADC12 is used, the PCLKC frequency must be set to at least 1 MHz. RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 29 of 92

Table 2.16 Operation frequency value in Subosc-speed mode Parameter Symbol Min Typ Max Unit Operation frequency System clock (ICLK) f 29.4 — 36.1 kHz Peripheral module clock (PCLKA) — — 36.1 Peripheral module clock (PCLKB) — — 36.1 Peripheral module clock (PCLKC) *2 — — 36.1 Peripheral module clock (PCLKD) — — 36.1 Flash interface clock (FCLK)*1 29.4 — 36.1 Note 1. Programming or erasing the flash memory is disabled in Subosc-speed mode. Note 2. The ADC12 cannot be used.

2.3.2 Clock Timing

Table 2.17 Clock timing except for sub-clock oscillator Parameter Symbol Min Typ Max Unit Test conditions EXTAL external clock input cycle time tEXcyc 41.66 — — ns Figure 2.7 EXTAL external clock input high pulse width tEXH 15.83 — — ns EXTAL external clock input low pulse width tEXL 15.83 — — ns EXTAL external clock rise time tEXr — — 5.0 ns EXTAL external clock fall time tEXf — — 5.0 ns Main clock oscillator frequency fMAIN 8 — 24 MHz — Main clock oscillation stabilization wait time (crystal)*1 tMAINOSCWT — — —*1 ms Figure 2.8 LOCO clock oscillation frequency fLOCO 29.4912 32.768 36.0448 kHz — LOCO clock oscillation stabilization wait time tLOCOWT — — 60.4 µs Figure 2.9 ILOCO clock oscillation frequency fILOCO 13.5 15 16.5 kHz — MOCO clock oscillation frequency FMOCO 6.8 8 9.2 MHz — MOCO clock oscillation stabilization wait time tMOCOWT — — 15.0 µs — HOCO clock oscillator oscillation frequency Without FLL fHOCO16 15.78 16 16.22 MHz –20 ≤ Ta ≤ 105°C fHOCO18 17.75 18 18.25 fHOCO20 19.72 20 20.28 fHOCO16 15.71 16 16.29 –40 ≤ Ta ≤ –20°C fHOCO18 17.68 18 18.32 fHOCO20 19.64 20 20.36 With FLL fHOCO16 15.960 16 16.040 –40 ≤ Ta ≤ 105°C Sub-clock frequency accuracy is ±50 ppm.fHOCO18 17.955 18 18.045 fHOCO20 19.950 20 20.050 HOCO clock oscillation stabilization wait time*2 tHOCOWT — — 64.7 µs — HOCO period jitter — — ±85 — ps — FLL stabilization wait time tFLLWT — — 1.8 ms — PLL clock frequency fPLL 120 — 240 MHz — PLL clock oscillation stabilization wait time tPLLWT — — 174.9 µs Figure 2.10 PLL period jitter fPLL — — ±100 — ps — PLL long term jitter — — ±300 — ps Term: 1µs, 10µs RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 30 of 92

PLLCR.PLLSTP OSCSF.PLLSF PLL clock t PLLWT PLL circuit output Figure 2.10 PLL clock oscillation start timing Sub-clock oscillator output SOSCCR.SOSTP Sub-clock tSUBOSCWT Figure 2.11 Sub-clock oscillation start timing

2.3.3 Reset Timing

Table 2.19 Reset timing Parameter Symbol Min Typ Max Unit Test conditions RES pulse width Power-on tRESWP 0.7 — — ms Figure 2.12 Deep Software Standby mode tRESWD 0.6 — — ms Figure 2.13 Software Standby mode, Subosc-speed mode tRESWS 0.3 — — ms All other tRESW 200 — — µs Wait time after RES cancellation tRESWT — 37.3 41.2 µs Figure 2.12 Wait time after internal reset cancellation (IWDT reset, WDT reset, software reset, SRAM parity error reset, SRAM ECC error reset, bus master MPU error reset, TrustZone error reset, Cache parity error reset) tRESW2 — 324 397.7 µs — RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 32 of 92

(low is valid) t RESWP t RESWT VCCmin Figure 2.12 RES pin input timing under the condition that VCC exceeds VPOR voltage threshold RES Internal reset signal (low is valid) t RESWD , t RESWS , t RESW t RESWT Figure 2.13 Reset input timing

2.3.4 Wakeup Timing

Table 2.20 Timing of recovery from low power modes (1 of 2) Parameter Symbol Min Typ Max Unit Test conditions Recovery time from Software Standby mode*1 Crystal resonator connected to main clock oscillator System clock source is main clock oscillator*2 tSBYMC*13 — 2.1 2.4 ms Figure 2.14 The division ratio of all oscillators is 1. System clock source is PLL with main clock oscillator*3 tSBYPC*13 — 2.2 2.6 ms External clock input to main clock oscillator System clock source is main clock oscillator*4 tSBYEX*13 — 45 125 μs System clock source is PLL with main clock oscillator*5 tSBYPE*13 — 170 255 μs System clock source is sub-clock oscillator*6 *11 tSBYSC*13 — 0.7 0.8 ms System clock source is LOCO*7 *11 tSBYLO*13 — 0.7 0.9 ms System clock source is HOCO clock oscillator*8 tSBYHO*13 — 55 130 µs System clock source is PLL with HOCO*9 tSBYPH*13 — 175 265 µs System clock source is MOCO clock oscillator*10 tSBYMO*13 — 35 65 µs Recovery time from Deep Software Standby mode DPSBYCR.DEEPCUT[1] = 0 and DPSWCR.WTSTS[5:0] = 0x0E tDSBY — 0.38 0.54 ms Figure 2.15 DPSBYCR.DEEPCUT[1] = 1 and DPSWCR.WTSTS[5:0] = 0x19 tDSBY — 0.55 0.73 ms Wait time after cancellation of Deep Software Standby mode tDSBYWT 56 — 57 tcyc RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 33 of 92

Table 2.20 Timing of recovery from low power modes (2 of 2) Parameter Symbol Min Typ Max Unit Test conditions Recovery time from Software Standby mode to Snooze mode High-speed mode when system clock source is HOCO (20 MHz) tSNZ — 35*12 70*12 μs Figure 2.16 High-speed mode when system clock source is MOCO (8 MHz) tSNZ — 11*12 14*12 μs Note 1. The recovery time is determined by the system clock source. When multiple oscillators are active, the recovery time can be determined with the following equation: Total recovery time = recovery time for an oscillator as the system clock source + the longest tSBYOSCWT in the active oscillators - tSBYOSCWT for the system clock + 2 LOCO cycles (when LOCO is operating) + Subosc is oscillating and MSTPC0 = 0 (CAC module stop)) Note 2. When the frequency of the crystal is 24 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x05) and the greatest value of the internal clock division setting is 1. Note 3. When the frequency of PLL is 200 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x05) and the greatest value of the internal clock division setting is 4. Note 4. When the frequency of the external clock is 24 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x00) and the greatest value of the internal clock division setting is 1. Note 5. When the frequency of PLL is 200 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x00) and the greatest value of the internal clock division setting is 4. Note 6. The Sub-clock oscillator frequency is 32.768 KHz and the greatest value of the internal clock division setting is 1. Note 7. The LOCO frequency is 32.768 kHz and the greatest value of the internal clock division setting is 1. Note 8. The HOCO frequency is 20 MHz and the greatest value of the internal clock division setting is 1. Note 9. The PLL frequency is 200 MHz and the greatest value of the internal clock division setting is 4. Note 10. The MOCO frequency is 8 MHz and the greatest value of the internal clock division setting is 1. Note 11. In Subosc-speed mode, the sub-clock oscillator or LOCO continues oscillating in Software Standby mode. Note 12. When the SNZCR.RXDREQEN bit is set to 0, the following time is added as the power supply recovery time: 16 µs (typical), 48 µs (maximum). Note 13. The recovery time can be calculated with the equation of tSBYOSCWT + tSBYSEQ. And they can be determined with the following value and equation. For n, the greatest value is selected from among the internal clock division settings. Wakeup time TYP MAX Unit tSBYOSCWT tSBYSEQ tSBYOSCWT tSBYSEQ tSBYMC (MSTS[7:0]*32 + 3) / 0.262 35 + 18 / fICLK + 4n / fMAIN (MSTS[7:0]*32 + 14 / 0.236 62 + 18 / fICLK + 4n / fMAIN µs tSBYPC (MSTS[7:0]*32 + 34) / 0.262 35 + 18 / fICLK + 4n / fPLL (MSTS[7:0]*32 + 45) / 0.236 62 + 18 / fICLK + 4n / fPLL µs tSBYEX 10 35 + 18 / fICLK + 4n / fEXMAIN 62 62 + 18 / fICLK + 4n / fEXMAIN µs tSBYPE 135 35 + 18 / fICLK + 4n / fPLL 192 62 + 18 / fICLK + 4n / fPLL µs tSBYSC 0 35 + 18 / fICLK + 4n / fSUB 0 62 + 18 / fICLK + 4n / fSUB µs tSBYLO 0 35 + 18 / fICLK + 4n / fLOCO 0 62 + 18 / fICLK + 4n / fLOCO µs tSBYHO 20 35 + 18 / fICLK + 4n / fHOCO 67 62 + 18 / fICLK + 4n / fHOCO µs tSBYPH 140 35 + 18 / fICLK + 4n / fPLL 202 62 + 18 / fICLK + 4n / fPLL µs tSBYMO 0 35 + 18 / fICLK + 4n / fMOCO 0 62 + 18 / fICLK + 4n / fMOCO µs RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 34 of 92

(system clock) ICLK IRQ Software Standby mode t SBYMC, t SBYEX, t SBYPC, t SBYPE, t SBYPH, t SBYSC, t SBYHO, t SBYLO Oscillator (not the system clock) t SBYOSCWT t SBYSEQ Oscillator (system clock) ICLK IRQ Software Standby mode t SBYMC, t SBYEX, t SBYPC, t SBYPE, t SBYPH, t SBYSC, t SBYHO, t SBYLO t SBYOSCWT t SBYOSCWT When stabilization of the system clock oscillator is slower t SBYSEQ Oscillator (not the system clock) When stabilization of an oscillator other than the system clock is slower Figure 2.14 Software Standby mode cancellation timing RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 35 of 92

(low is valid) Reset exception handling start Deep Software Standby mode Deep Software Standby reset (low is valid) t DSBY t DSBYWT Figure 2.15 Deep Software Standby mode cancellation timing t SNZ IRQ ICLK (to DTC, SRAM) PCLK ICLK (except DTC, SRAM) Oscillator Software Standby mode Snooze mode Note 1. When SNZCR.SNZDTCEN bit is set to 1, ICLK is supplied to DTC and SRAM. Figure 2.16 Recovery timing from Software Standby mode to Snooze mode

2.3.5 NMI and IRQ Noise Filter

Table 2.21 NMI and IRQ noise filter Parameter Symbol Min Typ Max Unit Test conditions NMI pulse width tNMIW 200 — — ns NMI digital filter disabled tPcyc × 2 ≤ 200 ns tPcyc × 2*1 — — tPcyc × 2 > 200 ns 200 — — NMI digital filter enabled tNMICK × 3 ≤ 200 ns tNMICK × 3.5*2 — — tNMICK × 3 > 200 ns IRQ pulse width tIRQW 200 — — ns IRQ digital filter disabled tPcyc × 2 ≤ 200 ns tPcyc × 2*1 — — tPcyc × 2 > 200 ns 200 — — IRQ digital filter enabled tIRQCK × 3 ≤ 200 ns tIRQCK × 3.5*3 — — tIRQCK × 3 > 200 ns RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 36 of 92

Note: 200 ns minimum in Software Standby mode. Note: If the clock source is switched, add 4 clock cycles of the switched source. Note 1. tPcyc indicates the PCLKB cycle. Note 2. tNMICK indicates the cycle of the NMI digital filter sampling clock. Note 3. tIRQCK indicates the cycle of the IRQi digital filter sampling clock. t NMIW NMI Figure 2.17 NMI interrupt input timing t IRQW IRQ Figure 2.18 IRQ interrupt input timing

2.3.6 I/O Ports, POEG, GPT, AGT, and ADC12 Trigger Timing

Table 2.22 I/O ports, POEG, GPT, AGT, and ADC12 trigger timing GPT16E Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register. AGT Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register. Parameter Symbol Min Max Unit Test conditions I/O ports Input data pulse width tPRW 1.5 — tPcyc Figure 2.19 POEG POEG input trigger pulse width tPOEW 3 — tPcyc Figure 2.20 GPT Input capture pulse width Single edge tGTICW 1.5 — tPDcyc Figure 2.21 Dual edge 2.5 — GTIOCxY output skew (x = 0 to 3, Y = A or B) Middle drive buffer tGTISK*1 — 4 ns Figure 2.22 High drive buffer — 4 GTIOCxY output skew (x = 4, 5, Y = A or B) Middle drive buffer — 4 High drive buffer — 4 GTIOCxY output skew (x = 0 to 5, Y = A or B) Middle drive buffer — 6 High drive buffer — 6 OPS output skew GTOUUP, GTOULO, GTOVUP, GTOVLO, GTOWUP, GTOWLO tGTOSK — 5 ns Figure 2.23 AGT AGTIO, AGTEE input cycle tACYC*2 100 — ns Figure 2.24 AGTIO, AGTEE input high width, low width tACKWH, tACKWL 40 — ns AGTIO, AGTO, AGTOA, AGTOB output cycle tACYC2 62.5 — ns ADC12 ADC12 trigger input pulse width tTRGW 1.5 — tPcyc Figure 2.25 Note: t Pcyc: PCLKB cycle, tPDcyc: PCLKD cycle. Note 1. This skew applies when the same driver I/O is used. If the I/O of the middle and high drivers is mixed, operation is not guaranteed. Note 2. Constraints on input cycle: When not switching the source clock: tPcyc × 2 < tACYC should be satisfied. RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 37 of 92

Figure 2.23 GPT output delay skew for OPS t ACYC2 AGTIO, AGTEE (input) t ACYC t ACKWL t ACKWH AGTIO, AGTO, AGTOA, AGTOB (output) Figure 2.24 AGT input/output timing ADTRG0 t TRGW Figure 2.25 ADC12 trigger input timing

2.3.7 CAC Timing

Table 2.23 CAC timing Parameter Symbol Min Typ Max Unit Test conditions CAC CACREF input pulse width tPBcyc ≤ tcac*1 tCACREF 4.5 × tcac + 3 × tPBcyc — — ns — tPBcyc > tcac*1 5 × tcac + 6.5 × tPBcyc — — ns RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 39 of 92

Note: t PBcyc: PCLKB cycle. Note 1. tcac: CAC count clock source cycle.

2.3.8 SCI Timing

Table 2.24 SCI timing (1) Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register. Parameter Symbol Min Max Unit Test conditions SCI Input clock cycle Asynchronous tScyc 4 — tPcyc Figure 2.26 Clock synchronous 6 — Input clock pulse width tSCKW 0.4 0.6 tScyc Input clock rise time tSCKr — 5 ns Input clock fall time tSCKf — 5 ns Output clock cycle Asynchronous tScyc 6 — tPcyc Clock synchronous 4 — Output clock pulse width tSCKW 0.4 0.6 tScyc Output clock rise time tSCKr — 5 ns Output clock fall time tSCKf — 5 ns Transmit data delay Clock synchronous master mode (internal clock) tTXD — 5 ns Figure 2.27 Clock synchronous slave mode (external clock) tTXD — 25 ns Receive data setup time Clock synchronous master mode (internal clock) tRXS 15 — ns Clock synchronous slave mode (external clock) tRXS 5 — ns Receive data hold time Clock synchronous tRXH 5 — ns Note: t Pcyc: PCLKA cycle. t SCKW t SCKr t SCKf t Scyc SCKn Note: n = 0, 9 Figure 2.26 SCK clock input/output timing RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 40 of 92

Note: n = 0, 9 Figure 2.27 SCI input/output timing in clock synchronous mode Table 2.25 SCI timing (2) Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register. Parameter Symbol Min Max Unit Test conditions Simple SPI SCK clock cycle output (master) tSPcyc 4 65536 tPcyc Figure 2.28 SCK clock cycle input (slave) 6 65536 SCK clock high pulse width tSPCKWH 0.4 0.6 tSPcyc SCK clock low pulse width tSPCKWL 0.4 0.6 tSPcyc SCK clock rise and fall time tSPCKr, tSPCKf — 5 ns Data input setup time master tSU 15 — ns Figure 2.29 to Figure 2.32slave 5 — ns Data input hold time tH 5 — ns SS input setup time tLEAD 1 — tSPcyc SS input hold time tLAG 1 — tSPcyc Data output delay master tOD — 5 ns slave — 25 ns Data output hold time tOH -5 — ns Data rise and fall time tDr, tDf — 5 ns SS input rise and fall time tSSLr, tSSLf — 5 ns Slave access time tSA — 3 × tPcyc + 25 ns Figure 2.32 Slave output release time tREL — 3 × tPcyc + 25 ns Note: t Pcyc: PCLKA cycle. RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 41 of 92

t Dr, t Df t SA t OH t LEAD t TD t LAG t H LSB OUT (Last data) DATA MSB OUT MSB IN DATA LSB IN MSB IN LSB OUT t SU t OD t REL MSB OUT SSn input SCKn CKPOL = 1 input SCKn CKPOL = 0 input MISOn output MOSIn input Note: n = 0, 9 Figure 2.32 SCI simple SPI mode timing for slave when CKPH = 0 Table 2.26 SCI timing (3) Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register. Parameter Symbol Min Max Unit Test conditions Simple IIC (Standard mode) SDA input rise time tSr — 1000 ns Figure 2.33 SDA input fall time tSf — 300 ns SDA input spike pulse removal time tSP 0 4 × tIICcyc ns Data input setup time tSDAS 250 — ns Data input hold time tSDAH 0 — ns SCL, SDA capacitive load Cb*1 — 400 pF Simple IIC (Fast mode) SDA input rise time tSr — 300 ns Figure 2.33 SDA input fall time tSf — 300 ns SDA input spike pulse removal time tSP 0 4 × tIICcyc ns Data input setup time tSDAS 100 — ns Data input hold time tSDAH 0 — ns SCL, SDA capacitive load Cb*1 — 400 pF Note: t IICcyc: IIC internal reference clock (IICφ) cycle. Note 1. Cb indicates the total capacity of the bus line. RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 44 of 92

Test conditions: V IH = VCC × 0.7, V IL = VCC × 0.3 V OL = 0.6 V, I OL = 6 mA Sr* Note: n = 0, 9 Note 1. S, P, and Sr indicate the following conditions: S: Start condition P: Stop condition Sr: Restart condition Figure 2.33 SCI simple IIC mode timing RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 45 of 92

2.3.9 SPI Timing

Table 2.27 SPI timing Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register. Parameter Symbol Min Max Unit Test conditions SPI RSPCK clock cycle Master tSPcyc 2 4096 tPcyc Figure 2.34 Slave 4 4096 RSPCK clock high pulse width Master tSPCKWH (tSPcyc – tSPCKr – tSPCKf) / 2 – 3 — ns Slave 0.4 0.6 tSPcyc RSPCK clock low pulse width Master tSPCKWL (tSPcyc – tSPCKr – tSPCKf) / 2 – 3 — ns Slave 0.4 0.6 tSPcyc RSPCK clock rise and fall time Master tSPCKr, tSPCKf — 5 ns Slave — 1 µs Data input setup time Master tSU 4 — ns Figure 2.35 to Figure 2.40Slave 5 — Data input hold time Master (PCLKA division ratio set to 1/2) tHF 0 — ns Master (PCLKA division ratio set to a value other than 1/2) tH tPcyc — Slave tH 20 — SSL setup time Master tLEAD N × tSPcyc - 10*1 N × tSPcyc + 100*1 ns Slave 4 × tPcyc — ns SSL hold time Master tLAG N × tSPcyc - 10*2 N × tSPcyc + 100*2 ns Slave 4 × tPcyc — ns Data output delay Master tOD1 — 6.3 ns tOD2 6.3 Slave tOD — 20 Data output hold time Master tOH 0 — ns Slave 0 — Successive transmission delay Master tTD tSPcyc + 2 × tPcyc 8 × tSPcyc + 2 × tPcyc ns Slave 4 × tPcyc MOSI and MISO rise and fall time Output tDr, tDf — 5 ns Input — 1 µs SSL rise and fall time Output tSSLr, tSSLf — 5 ns Input — 1 µs Slave access time tSA — 25 ns Figure 2.39 and Figure 2.40 Slave output release time tREL — 25 Note: t Pcyc: PCLKA cycle. RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 46 of 92

CPOL = 0 input RSPCKn CPOL = 1 input MISOn output MOSIn input t Dr, t Df t SA t OH t LEAD t TD t LAG t H LSB OUT (Last data) DATA MSB OUT MSB IN DATA LSB IN MSB IN LSB OUT t SU t OD t REL MSB OUT Note: n = A or B Figure 2.40 SPI timing for slave when CPHA = 1

2.3.10 QSPI Timing

Table 2.28 QSPI timing Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register. Parameter Symbol Min Max Unit Test conditions QSPI QSPCK clock cycle tQScyc 2 48 tPcyc Figure 2.41 QSPCK clock high pulse width tQSWH tQScyc × 0.4 — ns QSPCK clock low pulse width tQSWL tQScyc × 0.4 — ns Data input setup time tSu 10 — ns Figure 2.42 Data input hold time tIH 0 — ns QSSL setup time tLEAD (N + 0.5) × tQscyc - 5*1 (N + 0.5) × tQscyc + 100*1 ns QSSL hold time tLAG (N + 0.5) × tQscyc - 5*2 (N + 0.5) × tQscyc + 100*2 ns Data output delay tOD — 4 ns Data output hold time tOH –3.3 — ns Successive transmission delay tTD 1 16 tQScyc Note: t Pcyc: PCLKA cycle. Note 1. N is set to 0 or 1 in SFMSLD. Note 2. N is set to 0 or 1 in SFMSHD. RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 50 of 92

2.3.11 I3C Timing

Table 2.29 IIC timing(1)-1 1. Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins: SDA0_A, SCL0_A, SDA0_B, SCL0_B, SDA0_C, SCL0_C. 2. The following pins do not require setting: SDA0_D, SCL0_D. 3. Use pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group membership. For the IIC interface, the AC portion of the electrical characteristics is measured for each group. Parameter Symbol Min Max Unit IIC (Standard mode, SMBus) BFCTL.FMPE = 0 SCL input cycle time tSCL 10(18) × tI3Ccyc + 1300 — ns SCL input high pulse width tSCLH 5(9) × tI3Ccyc + 300 — ns SCL input low pulse width tSCLL 5(9) × tI3Ccyc + 300 — ns SCL, SDA rise time tSr — 1000 ns SCL, SDA fall time tSf — 300 ns SCL, SDA input spike pulse removal time tSP 0 1(4) × tI3Ccyc ns SDA input bus free time when wakeup function is disabled tBUF 5(9) × tI3Ccyc + 300 — ns SDA input bus free time when wakeup function is enabled tBUF 5(9) × tI3Ccyc + 4 × tTcyc + 300 — ns START condition input hold time when wakeup function is disabled tSTAH tI3Ccyc + 300 — ns START condition input hold time when wakeup function is enabled tSTAH 1(5) × tI3Ccyc + tTcyc + 300 — ns Repeated START condition input setup time tSTAS 1000 — ns STOP condition input setup time tSTOS 1000 — ns Data input setup time tSDAS tI3Ccyc + 50 — ns Data input hold time tSDAH 0 — ns SCL, SDA capacitive load Cb*1 — 400 pF Note: t I3Ccyc: I3C internal reference clock (I3Cφ) cycle, tTcyc: I3CCLK cycle. Note: Values in parentheses apply when INCTL.DNFS[3:0] is set to 0x3 while the digital filter is enabled with INCTL.DNFE set to 1. Note: Must use pins that have a letter appended to their name, for instance “_A”, “_B”, to indicate group membership. For the IIC interface, the AC portion of the electrical characteristics is measured for each group. Note 1. Cb indicates the total capacity of the bus line. RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 52 of 92

Table 2.30 IIC timing(1)-2 1. Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins: SDA0_A, SCL0_A, SDA0_B, SCL0_B, SDA0_C, SCL0_C. 2. The following pins do not require setting: SDA0_D, SCL0_D. 3. Use pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group membership. For the IIC interface, the AC portion of the electrical characteristics is measured for each group. Parameter Symbol Min Max Unit IIC (Fast-mode) SCL input cycle time tSCL 10(18) × tI3Ccyc + 600 — ns SCL input high pulse width tSCLH 5(9) × tI3Ccyc + 300 — ns SCL input low pulse width tSCLL 5(9) × tI3Ccyc + 300 — ns SCL, SDA rise time tSr 20 × (external pullup voltage/5.5 V)*1 300 ns SCL, SDA fall time tSf 20 × (external pullup voltage/5.5 V)*1 300 ns SCL, SDA input spike pulse removal time tSP 0 1(4) × tI3Ccyc ns SDA input bus free time when wakeup function is disabled tBUF 5(9) × tI3Ccyc + 300 — ns SDA input bus free time when wakeup function is enabled tBUF 5(9) × tI3Ccyc + 4 × tTcyc + 300 — ns START condition input hold time when wakeup function is disabled tSTAH tI3Ccyc + 300 — ns START condition input hold time when wakeup function is enabled tSTAH 1(5) × tI3Ccyc + tTcyc + 300 — ns Repeated START condition input setup time tSTAS 300 — ns STOP condition input setup time tSTOS 300 — ns Data input setup time tSDAS tI3Ccyc + 50 — ns Data input hold time tSDAH 0 — ns SCL, SDA capacitive load Cb*2 — 400 pF Note: t I3Ccyc: I3C internal reference clock (I3Cφ) cycle, tTcyc: I3CCLK cycle. Note: Values in parentheses apply when INCTL.DNFS[3:0] is set to 0x3 while the digital filter is enabled with INCTL.DNFE set to 1. Note: Must use pins that have a letter appended to their name, for instance “_A”, “_B”, to indicate group membership. For the IIC interface, the AC portion of the electrical characteristics is measured for each group. Note 1. Only supported for SDA0_D, SCL0_D. Note 2. Cb indicates the total capacity of the bus line. RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 53 of 92

Table 2.31 IIC timing(1)-3 Setting of the SDA0_D, SCL0_D pins is not required with the Port Drive Capability bit in the PmnPFS register. Parameter Symbol Min Max Unit IIC (Fast-mode+) BFCTL.FMPE = 1 SCL input cycle time tSCL 10(18) × tI3Ccyc + 240 — ns SCL input high pulse width tSCLH 5(9) × tI3Ccyc + 120 — ns SCL input low pulse width tSCLL 5(9) × tI3Ccyc + 120 — ns SCL, SDA rise time tSr — 120 ns SCL, SDA fall time tSf 20 × (external pullup voltage/5.5 120 ns SCL, SDA input spike pulse removal time tSP 0 1(4) × tI3Ccyc ns SDA input bus free time when wakeup function is disabled tBUF 5(9) × tI3Ccyc + 120 — ns SDA input bus free time when wakeup function is enabled tBUF 5(9) × tI3Ccyc + 4 × tTcyc + 120 — ns START condition input hold time when wakeup function is disabled tSTAH tI3Ccyc + 120 — ns START condition input hold time when wakeup function is enabled tSTAH 1(5) × tI3Ccyc + tTcyc + 120 — ns Restart condition input setup time tSTAS 120 — ns Stop condition input setup time tSTOS 120 — ns Data input setup time tSDAS tI3Ccyc + 30 — ns Data input hold time tSDAH 0 — ns SCL, SDA capacitive load Cb*1 — 550 pF Note: t I3Ccyc: I3C internal reference clock (I3Cφ) cycle, tTcyc: I3CCLK cycle. Note: Values in parentheses apply when INCTL.DNFS[3:0] is set to 0x3 while the digital filter is enabled with INCTL.DNFE set to 1. Note 1. Cb indicates the total capacity of the bus line. SDAn SCLn V IH V IL t STAH t SCLH t SCLL t Sf t Sr t SCL t SDAH t SDAS t STAS t SP t STOS t BUF Sr* Note 1. S, P, and Sr indicate the following conditions: S: Start condition P: Stop condition Sr: Restart condition Figure 2.43 I2C bus interface input/output timing RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 54 of 92

Table 2.32 IIC timing(2) Conditions: VCC = 3.00 to 3.60 V Setting of the SDA0_D, SCL0_D pins is not required with the Port Drive Capability bit in the PmnPFS register. Parameter Symbol Min Max Unit IIC (Hs-mode) BFCTL.HSME = 1 SCL input cycle time tSCL 55(57) × tI3Ccyc — ns SCL input high pulse width Cb = 400 pF tSCLH 43(44) × tI3Ccyc — ns Cb = 100 pF 23(24) × tI3Ccyc — SCL input low pulse width Cb = 400 pF tSCLL 64(65) × tI3Ccyc — ns Cb = 100 pF 32(33) × tI3Ccyc — SCL rise time Cb = 400 pF tSrCL — 80 ns Cb = 100 pF — 40 SDA rise time Cb = 400 pF tSrDA — 160 ns Cb = 100 pF — 80 SCL fall time Cb = 400 pF tSfCL — 80 ns Cb = 100 pF — 40 SDA fall time Cb = 400 pF tSfDA — 160 ns Cb = 100 pF — 80 SCL, SDA input spike pulse removal time tSP 0 1(1) × tI3Ccyc ns Repeated START condition input setup time tSTAS 40 — ns STOP condition input setup time tSTOS 40 — ns Data input setup time tSDAS 10 — ns Data input hold time Cb = 400 pF tSDAH 0 150 ns Cb = 100 pF 0 70 SCL, SDA capacitive load Cb*1 — 400 pF Note: t I3Ccyc: I3C internal reference clock (I3Cφ) cycle. Note: Values in parentheses apply when INCTL.DNFS[3:0] is set to 0x3 while the digital filter is enabled with INCTL.DNFE set to 1. Note 1. Cb indicates the total capacity of the bus line. I3C_SDA0 I3C_SCL0 S r tSfDA tSrDA tSTAS tSDAH tSDAS tSTOS tSfCL tSCLH tSCLHtSCLLtSCLL tSrCL 0.3 × VCC = MCS current source pull-up = Rp resistor pull-up S r P 0.7 × VCC 0.3 × VCC 0.7 × VCC Figure 2.44 I2C bus interface input/output timing (Hs-mode) RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 55 of 92

Table 2.33 I3C timing (open drain timing parameters) Conditions: VCC = 3.00 to 3.60 V Setting of the I3C_SDA, I3C_SCL pins is not required with the Port Drive Capability bit in the PmnPFS register. Parameter Symbol Min Max Unit Test conditions I3C Open Drain Timing Parameters SCL Clock Low Period tLOW_OD *1 *2 200 — ns Figure 2.47 tDIG_OD_L tLOW_ODmin + tfDA_ODmin — ns Figure 2.47 SCL Clock High Period tHIGH*3 *4 — 41 ns Figure 2.45 tDIG_H — tHIGH + tCF ns Figure 2.45 SDA Signal Fall Time tfDA_OD tCF 12 ns Figure 2.47 SDA Data Setup Time Open Drain Mode tSU_OD*1 17 — ns Figure 2.46 Clock After START (S) Condition tCAS*5 *6 38.4 nano For ENAS0: 1 µ seconds Figure 2.47 For ENAS1: 100 µ For ENAS2: 2 milli For ENAS3: 50 milli Clock Before STOP (P) Condition tCBP tCASmin / 2 — seconds Figure 2.48 Current Master to Secondary Master Overlap time during handoff tMMOverla p tDIG_OD_Lmin — ns Figure 2.53 Bus Available Condition tAVAL*7 1 — µs — Bus Idle Condition tIDLE 1 — ms — Time Internal Where New Master Not Driving SDA Low tMMLock tAVALmin — µs Figure 2.53 Note 1. This is approximately equal to tLOWmin + tDS_ODmin + trDA_ODtyp + tSU_Odmin. Note 2. The Master may use a shorter Low period if it knows that this is safe, i.e., that SDA is already above VIH Note 3. Based on tSPIKE, rise and fall times, and interconnect Note 4. This maximum High period may be exceeded when the signals can be safely seen by Legacy I2C Devices, and/or in consideration of the interconnect (e.g., a short Bus). As a product specification, if this Max value cannot be guaranteed, change this Max value and specify that it cannot be used in the Mixed Bus. Note 5. On a legacy bus where I2C devices need to see Start Note 6. Slaves that do not support the optional ENTASx CCCs shall use the tCAS Max value shown for ENTAS3 Note 7. On a mixed bus with Fm Legacy I2C Devices, tAVAL is 300 ns shorter than the Fm Bus Free Condition time (tBUF) RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 56 of 92

Table 2.34 I3C timing (push-pull timing parameters for SDR mode) Conditions: VCC = 3.00 to 3.60 V Setting of the I3C_SDA, I3C_SCL pins is not required with the Port Drive Capability bit in the PmnPFS register. Parameter Symbol Min Max Unit Test conditions I3C Push-Pull Timing Parameters for SDR Mode SCL Clock Frequency fSCL*1 0.01 12.5 MHz — SCL Clock Low Period tLOW 24 — ns Figure 2.45 tDIG_L*2 *4 40 — ns Figure 2.45 SCL Clock High Period for Mixed Bus tHIGH_MIXED 24 — ns Figure 2.45 tDIG_H_MIXED*2 40 45 ns Figure 2.45 SCL Clock High Period tHIGH 24 — ns Figure 2.45 tDIG_H*2 40 — ns Figure 2.45 Clock in to Data Out for Slave tSCO — 12 ns Figure 2.50 SCL Clock Rise Time tCR — 150 × 1 /fSCL (capped at 60) ns Figure 2.45 SCL Clock Fall Time tCF — 150 × 1 /fSCL (capped at 60) µs Figure 2.45 SDA Signal Data Hold in Push-Pull Mode Master tHD_PP*4 tCR + 3 and tCF + 3 — — Figure 2.49 Slave tHD_PP 0 — — Figure 2.49 SDA Signal Data Setup in Push-Pull Mode tSU_PP 17 N/A ns Figure 2.51 Clock After Repeated START (Sr) tCASr tCASmin N/A ns Figure 2.52 Clock Before Repeated START (Sr) tCBSr tCASmin / 2 N/A ns Figure 2.52 Capacitive Load per Bus Line (SDA/SCL) Cb — 50 pF — Note 1. fSCL = 1 / (tDIG_L + tDIG_H) Note 2. tDIG_L and tDIG_H are the clock Low and High periods as seen at the receiver end of the I3C Bus using VIL and VIH. Note 3. When communicating with an I3C Device on a mixed Bus, the tDIG_H_MIXED period must be constrained in order to make sure that I2C Devices do not interpret I3C signaling as valid I2C signaling. Note 4. As both edges are used, the hold time needs to be satisfied for the respective edges; i.e., tCF + 3 for falling edge clocks, and tCR + 3 for rising edge clocks. RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 57 of 92

0.7 × V DD 0.3 × V DD 0.7 × V DD 0.3 × V DD t CF t CR t HD_PP t SU_PP Figure 2.49 I3C master out timing RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 60 of 92

T C9C8C1 D7 D6 D1 Repeated START(Sr) STOP(P) = High Speed Active Push-Pull Drive STOP(P) Repeated START(Sr) SDA MST-SDA SLV-SDA SCL 0.3 × VDD 0.7 × VDD 0.3 × VDD 0.7 × VDD 0.3 × VDD 0.7 × VDD 0.3 × VDD 0.7 × VDD 0.3 × VDD 0.7 × VDD 0.3 × VDD 0.7 × VDD tCBSr TCASr tSCOtSCO SDA SCL = Active Drive by Master or Slave = Open-Drain class Pull-Up by master = High-Z by Master = High-Z by Slave Figure 2.52 T-bit when master ends read with repeated START and STOP RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 62 of 92

0.3 × VDD 0.7 × VDD = Active Drive by Master NM_SDA CM_SDA NM_SCL CM_SCL SCL A6 A5 C1 C2 tSU_STO tMMlock tMMoverlap tCAStSCO 0.3 × VDD 0.7 × VDD 0.3 × VDD 0.7 × VDD 0.3 × VDD 0.7 × VDD 0.3 × VDD 0.7 × VDD 0.3 × VDD 0.7 × VDD OD or PP Open-Drain OD or PPOpen-Drain = Open-Drain class Pull-Up by master = High-Z by Master Figure 2.53 I3C timing (open drain timing parameters)

2.3.12 SSIE Timing

Table 2.35 SSIE timing (1 of 2) (1) High drive output is selected with the Port Drive Capability bit in the PmnPFS register. (2) Use pins that have a letter appended to their names, for instance “_A” , “_B” or “_C” to indicate group membership. For the SSIE interface, the AC portion of the electrical characteristics is measured for each group. Parameter Symbol Target specification Unit CommentsMin. Max. SSIBCK0 Cycle Master tO 80 — ns Figure 2.54 Slave tI 80 — ns High level/ low level Master tHC/tLC 0.35 — tO Slave 0.35 — tI Rising time/ falling time Master tRC/tFC — 0.15 tO / tI Slave — 0.15 tO / tI RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 63 of 92

SSILRCK0/SSIFS0 (input) SSITXD0, SSIDATA0 (output) MSB bit output delay after SSILRCK0/SSIFS0 change for slave transmitter when DEL = 1, SDTA = 0 or DEL = 1, SDTA = 1, SWL[2:0] = DWL[2:0] in SSICR. Figure 2.58 SSIE data output delay after SSILRCK0/SSIFS0 change

2.3.13 CANFD Timing

Table 2.36 CANFD interface timing Parameter Symbol CAN-FD Unit Test conditionsMin Max Internal delay time tnode — 75 ns Figure 2.59 Transmission rate — 5 Mbps Note: t node = toutput + tinput CTX0 CRX0 CANFD interface Internal transmission delay time (toutput) Internal reception delay time (tinput) Figure 2.59 CANFD interface condition RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 66 of 92

2.4 USB Characteristics

2.4.1 USBFS Timing

Table 2.37 USBFS full-speed characteristics (USB_DP and USB_DM pin characteristics) Conditions: VCC = AVCC0 = VCC_USB = 3.0 to 3.6 V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, USBCLK = 48 MHz Parameter Symbol Min Typ Max Unit Test conditions Input characteristics Input high voltage VIH 2.0 — — V — Input low voltage VIL — — 0.8 V — Differential input sensitivity VDI 0.2 — — V | USB_DP - USB_DM | Differential common-mode range VCM 0.8 — 2.5 V — Output characteristics Output high voltage VOH 2.8 — 3.6 V IOH = –200 µA Output low voltage VOL 0.0 — 0.3 V IOL = 2 mA Cross-over voltage VCRS 1.3 — 2.0 V Figure 2.60 Rise time tLR 4 — 20 ns Fall time tLF 4 — 20 ns Rise/fall time ratio tLR / tLF 90 — 111.11 % tFR/ tFF Output resistance ZDRV 28 — 44 Ω USBFS: Rs = 27 Ω included Pull-up and pull-down characteristics DM pull-up resistance in device controller mode Rpu 0.900 — 1.575 kΩ During idle state 1.425 — 3.090 kΩ During transmission and reception USB_DP, USB_DM t FFt FR 90% 10%10% 90%V CRS Figure 2.60 USB_DP and USB_DM output timing in full-speed mode Observation point 50 pF 50 pF USB_DP USB_DM 27  Figure 2.61 Test circuit in full-speed mode RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 67 of 92

2.5 ADC12 Characteristics

Table 2.38 A/D conversion characteristics for unit 0 Conditions: PCLKC = 1 to 50 MHz Parameter Min Typ Max Unit Test conditions Frequency 1 — 50 MHz — Analog input capacitance — — 30 pF — Quantization error — ±0.5 — LSB — Resolution — — 12 Bits — High-precision high-speed channels (AN000 to AN002, AN007) Conversion time*1 (operation at PCLKC =

50 MHz)

source impedance Max. = 1 kΩ 0.52 (0.26)*2 — — μs Sampling in 13 states Offset error — ±1.0 ±2.5 LSB — Full-scale error — ±1.0 ±2.5 LSB — Absolute accuracy — ±2.0 ±4.5 LSB — DNL differential nonlinearity error — ±0.5 ±1.5 LSB — INL integral nonlinearity error — ±1.0 ±2.5 LSB — High-precision normal-speed channels (AN004 to AN006, AN008, AN011 to AN013) Conversion time*1 (Operation at PCLKC = source impedance Max. = 1 kΩ 0.92 (0.66)*2 — — μs Sampling in 33 states Offset error — ±1.0 ±2.5 LSB — Full-scale error — ±1.0 ±2.5 LSB — Absolute accuracy — ±2.0 ±4.5 LSB — DNL differential nonlinearity error — ±0.5 ±1.5 LSB — INL integral nonlinearity error — ±1.0 ±2.5 LSB — Normal-precision normal-speed channels (AN016) Conversion time*1 (Operation at PCLKC = source impedance Max. = 1 kΩ 0.92 (0.66)*2 — — μs Sampling in 33 states Offset error — ±1.0 ±5.5 LSB — Full-scale error — ±1.0 ±5.5 LSB — Absolute accuracy — ±2.0 ±7.5 LSB — DNL differential nonlinearity error — ±0.5 ±4.5 LSB — INL integral nonlinearity error — ±1.0 ±5.5 LSB — Note: These specification values apply when there is no access to the external bus during A/D conversion. If access occurs during A/D conversion, values might not fall within the indicated ranges. The use of PORT0 as digital outputs is not allowed when the 12-Bit A/D converter is used. The characteristics apply when AVCC0, AVSS0, VREFH0, VREFL0, and 12-bit A/D converter input voltage are stable. Note 1. The conversion time includes the sampling and comparison times. The number of sampling states is indicated for the test conditions. Note 2. Values in parentheses indicate the sampling time. Table 2.39 A/D internal reference voltage characteristics Parameter Min Typ Max Unit Test conditions A/D internal reference voltage 1.13 1.18 1.23 V — Sampling time 4.15 — — µs — RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 68 of 92

error (INL) Actual A/D conversion characteristic Ideal A/D conversion characteristic Analog input voltage Offset error Absolute accuracy Differential nonlinearity error (DNL) Full-scale error 0xFFF 0x000 Ideal line of actual A/D conversion characteristic 1-LSB width for ideal A/D conversion characteristic Differential nonlinearity error (DNL) 1-LSB width for ideal A/D conversion characteristic VREFH0 (full-scale) A/D converter output code Figure 2.62 Illustration of ADC12 characteristic terms Absolute accuracy Absolute accuracy is the difference between output code based on the theoretical A/D conversion characteristics, and the actual A/D conversion result. When measuring absolute accuracy, the voltage at the midpoint of the width of the analog input voltage (1-LSB width), which can meet the expectation of outputting an equal code based on the theoretical A/D conversion characteristics, is used as an analog input voltage. For example, if 12-bit resolution is used and the reference voltage VREFH0 = 3.072 V , then the 1-LSB width becomes 0.75 mV , and 0 mV , 0.75 mV , and 1.5 mV are used as the analog input voltages. If the analog input voltage is 6 mV , an absolute accuracy of ±5 LSB means that the actual A/D conversion result is in the range of 0x003 to 0x00D, though an output code of 0x008 can be expected from the theoretical A/D conversion characteristics. Integral nonlinearity error (INL) Integral nonlinearity error is the maximum deviation between the ideal line when the measured offset and full-scale errors are zeroed, and the actual output code. Differential nonlinearity error (DNL) Differential nonlinearity error is the difference between the 1-LSB width based on the ideal A/D conversion characteristics and the width of the actual output code. Offset error Offset error is the difference between the transition point of the ideal first output code and the actual first output code. RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 69 of 92

Full-scale error is the difference between the transition point of the ideal last output code and the actual last output code.

2.6 DAC12 Characteristics

Table 2.40 D/A conversion characteristics Parameter Min Typ Max Unit Test conditions Resolution — — 12 Bits — Without output amplifier Absolute accuracy — — ±24 LSB Resistive load 2 MΩ INL — ±2.0 ±8.0 LSB Resistive load 2 MΩ DNL — ±1.0 ±2.0 LSB — Output impedance — 8.5 — kΩ — Conversion time — — 3 µs Resistive load 2 MΩ, Capacitive load 20 pF Output voltage range 0 — VREFH V — With output amplifier INL — ±2.0 ±4.0 LSB — DNL — ±1.0 ±2.0 LSB — Conversion time — — 4.0 µs — Resistive load 5 — — kΩ — Capacitive load — — 50 pF — Output voltage range 0.2 — VREFH – 0.2 V —

2.7 TSN Characteristics

Table 2.41 TSN characteristics Parameter Symbol Min Typ Max Unit Test conditions Relative accuracy — — ± 1.0 — °C — Temperature slope — — 4.0 — mV/°C — Output voltage (at 25 °C) — — 1.24 — V — Temperature sensor start time tSTART — — 30 µs — Sampling time — 4.15 — — µs —

2.8 OSC Stop Detect Characteristics

Table 2.42 Oscillation stop detection circuit characteristics Parameter Symbol Min Typ Max Unit Test conditions Detection time tdr — — 1 ms Figure 2.63 RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 70 of 92

OSTDSR.OSTDF MOCO clock ICLK Figure 2.63 Oscillation stop detection timing

2.9 POR and LVD Characteristics

Table 2.43 Power-on reset circuit and voltage detection circuit characteristics (1) Parameter Symbol Min Typ Max Un it Test conditions Voltage detection level Power-on reset (POR) DPSBYCR.DEEPCUT[1:0] = 00b or 01b. VPOR 2.5 2.6 2.7 V Figure 2.64 Voltage detection circuit (LVD0) Vdet0_1 2.84 2.94 3.04 Figure 2.65 Vdet0_2 2.77 2.87 2.97 Vdet0_3 2.70 2.80 2.90 Voltage detection circuit (LVD1) Vdet1_1 2.89 2.99 3.09 Figure 2.66 Vdet1_2 2.82 2.92 3.02 Vdet1_3 2.75 2.85 2.95 Voltage detection circuit (LVD2) Vdet2_1 2.89 2.99 3.09 Figure 2.67 Vdet2_2 2.82 2.92 3.02 Vdet2_3 2.75 2.85 2.95 Internal reset time Power-on reset time tPOR — 4.5 — ms Figure 2.64 LVD0 reset time tLVD0 — 0.51 — Figure 2.65 LVD1 reset time tLVD1 — 0.38 — Figure 2.66 LVD2 reset time tLVD2 — 0.38 — Figure 2.67 Minimum VCC down time*1 tVOFF 200 — — µs Figure 2.64, Figure 2.65 Response delay tdet — — 200 µs Figure 2.65 to Figure 2.67 LVD operation stabilization time (after LVD is enabled) td(E-A) — — 10 µs Figure 2.66, Figure 2.67 Hysteresis width (LVD1 and LVD2) VLVH — 70 — m V Note 1. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR, Vdet0, Vdet1, and Vdet2 for POR and LVD. RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 71 of 92

T d(E-A) LVCMPCR.LVD1E LVD1 Comparator output LVD1CR0.CMPE LVD1SR.MON Internal reset signal (active-low) When LVD1CR0.RN = 0 When LVD1CR0.RN = 1 V LVH t LVD1 Figure 2.66 Voltage detection circuit timing (Vdet1) RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 73 of 92

T d(E-A) LVCMPCR.LVD2E LVD2 Comparator output LVD2CR0.CMPE LVD2SR.MON Internal reset signal (active-low) When LVD2CR0.RN = 0 When LVD2CR0.RN = 1 V LVH t LVD2 Figure 2.67 Voltage detection circuit timing (Vdet2)

2.10 Flash Memory Characteristics

2.10.1 Code Flash Memory Characteristics

Table 2.44 Code flash memory characteristics (1 of 2) Conditions: Program or erase: FCLK = 4 to 50 MHz Read: FCLK ≤ 50 MHz Parameter Symbol FCLK = 4 MHz 20 MHz ≤ FCLK ≤ 50 MHz Unit Test conditionsMin Typ*6 Max Min Typ*6 Max Programming time NPEC ≤ 100 times 128-byte tP128 — 0.75 13.2 — 0.34 6.0 ms 8-KB tP8K — 49 176 — 22 80 ms 32-KB tP32K — 194 704 — 88 320 ms Programming time NPEC > 100 times 128-byte tP128 — 0.91 15.8 — 0.41 7.2 ms 8-KB tP8K — 60 212 — 27 96 ms 32-KB tP32K — 234 848 — 106 384 ms Erasure time NPEC ≤ 100 times 8-KB tE8K — 78 216 — 43 120 ms 32-KB tE32K — 283 864 — 157 480 ms Erasure time NPEC > 100 times 8-KB tE8K — 94 260 — 52 144 ms 32-KB tE32K — 341 1040 — 189 576 ms Reprogramming/erasure cycle*4 NPEC 10000*1 — — 10000*1 — — Times RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 74 of 92

Table 2.44 Code flash memory characteristics (2 of 2) Conditions: Program or erase: FCLK = 4 to 50 MHz Read: FCLK ≤ 50 MHz Parameter Symbol FCLK = 4 MHz 20 MHz ≤ FCLK ≤ 50 MHz Unit Test conditionsMin Typ*6 Max Min Typ*6 Max Suspend delay during programming tSPD — — 264 — — 120 µs Programming resume time tPRT — — 110 — — 50 µs First suspend delay during erasure in suspend priority mode tSESD1 — — 216 — — 120 µs Second suspend delay during erasure in suspend priority mode tSESD2 — — 1.7 — — 1.7 ms Suspend delay during erasure in erasure priority mode tSEED — — 1.7 — — 1.7 ms First erasing resume time during erasure in suspend priority mode*5 tREST1 — — 1.7 — — 1.7 ms Second erasing resume time during erasure in suspend priority mode tREST2 — — 144 — — 80 µs Erasing resume time during erasure in erasure priority mode tREET — — 144 — — 80 µs Forced stop command tFD — — 32 — — 20 µs Data hold time*2 tDRP 10*2 *3 — — 10*2 *3 — — Years Note 1. This is the minimum number of times to guarantee all the characteristics after reprogramming. The guaranteed range is from 1 to the minimum value. Note 2. This indicates the minimum value of the characteristic when reprogramming is performed within the specified range. Note 3. This result is obtained from reliability testing. Note 4. The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times (n = 10,000), erasing can be performed n times for each block. For example, when 128-byte programming is performed 64 times for different addresses in 8-KB blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However, programming the same address several times as one erasure is not enabled. Overwriting is prohibited. Note 5. Time for resumption includes time for reapplying the erasing pulse (up to one full pulse) that was cut off at the time of suspension. Note 6. The reference value at VCC = 3.3V and room temperature. RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 75 of 92

FSTATR.FRDY Programming pulse

• Suspension during programming FACI command FSTATR.FRDY Erasure pulse
• Suspension during erasure in suspend priority mode FACI command FSTATR.FRDY Erasure pulse
• Suspension during erasure in erasure priority mode Program Suspend Ready Not Ready Ready Programming tSPD Erase Suspend Ready Not Ready Ready tSEED Erasing Erase Suspend Resume Suspend Ready Not Ready Ready Not Ready tSESD1 tSESD2 Erasing Erasing tFD
• Forced Stop FACI command FSTATR.FRDY Forced Stop Not Ready Ready Resume tPRT Programming Resume tREST1 Ready Not Ready tREST2 Erasing Resume Not Ready tREET Erasing Figure 2.68 Suspension and forced stop timing for flash memory programming and erasure

2.10.2 Data Flash Memory Characteristics

Table 2.45 Data flash memory characteristics (1 of 2) Conditions: Program or erase: FCLK = 4 to 50 MHz Read: FCLK ≤ 50 MHz Parameter Symbol FCLK = 4 MHz 20 MHz ≤ FCLK ≤ 50 MHz Unit Test conditionsMin Typ*6 Max Min Typ*6 Max Programming time 4-byte tDP4 — 0.36 3.8 — 0.16 1.7 ms 8-byte tDP8 — 0.38 4.0 — 0.17 1.8 16-byte tDP16 — 0.42 4.5 — 0.19 2.0 Erasure time 64-byte tDE64 — 3.1 18 — 1.7 10 ms 128-byte tDE128 — 4.7 27 — 2.6 15 256-byte tDE256 — 8.9 50 — 4.9 28 Blank check time 4-byte tDBC4 — — 84 — — 30 µs Reprogramming/erasure cycle*1 NDPEC 125000*2 — — 125000*2 — — — Suspend delay during programming 4-byte tDSPD — — 264 — — 120 µs 8-byte — — 264 — — 120 16-byte — — 264 — — 120 Programming resume time tDPRT — — 110 — — 50 µs First suspend delay during erasure in suspend priority mode 64-byte tDSESD1 — — 216 — — 120 µs 128-byte — — 216 — — 120 256-byte — — 216 — — 120 RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 76 of 92

Table 2.45 Data flash memory characteristics (2 of 2) Conditions: Program or erase: FCLK = 4 to 50 MHz Read: FCLK ≤ 50 MHz Parameter Symbol FCLK = 4 MHz 20 MHz ≤ FCLK ≤ 50 MHz Unit Test conditionsMin Typ*6 Max Min Typ*6 Max Second suspend delay during erasure in suspend priority mode 64-byte tDSESD2 — — 300 — — 300 µs 128-byte — — 390 — — 390 256-byte — — 570 — — 570 Suspend delay during erasing in erasure priority mode 64-byte tDSEED — — 300 — — 300 µs 128-byte — — 390 — — 390 256-byte — — 570 — — 570 First erasing resume time during erasure in suspend priority mode*5 tDREST1 — — 300 — — 300 µs Second erasing resume time during erasure in suspend priority modeFirst erasing resume time during erasure in suspend priority mode tDREST2 — — 126 — — 70 µs Erasing resume time during erasure in erasure priority mode tDREET — — 126 — — 70 µs Forced stop command tFD — — 32 — — 20 µs Data hold time*3 tDRP 10*3 *4 — — 10*3 *4 — — Year Note 1. The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times (n = 125,000), erasing can be performed n times for each block. For example, when 4-byte programming is performed 16 times for different addresses in 64-byte blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However, programming the same address several times as one erasure is not enabled. Overwriting is prohibited. Note 2. This is the minimum number of times to guarantee all the characteristics after reprogramming. The guaranteed range is from 1 to the minimum value. Note 3. This indicates the minimum value of the characteristic when reprogramming is performed within the specified range. Note 4. This result is obtained from reliability testing. Note 5. Time for resumption includes time for reapplying the erasing pulse (up to one full pulse) that was cut off at the time of suspension. Note 6. The reference value at VCC = 3.3 V and room temperature.

2.10.3 Option Setting Memory Characteristics

Table 2.46 Option setting memory characteristics Conditions: Program: FCLK = 4 to 50 MHz Read: FCLK ≤ 50 MHz Parameter Symbol FCLK = 4 MHz 20 MHz ≤ FCLK ≤ 50 MHz Unit Test conditionsMin Typ*4 Max Min Typ*4 Max Programming time NOPC ≤ 100 times tOP — 83 309 — 45 162 ms Programming time NOPC > 100 times tOP — 100 371 — 55 195 ms Reprogramming cycle NOPC 20000*1 — — 20000*1 — — Times Data hold time*2 tDRP 10*2 *3 — — 10*2 *3 — — Years Note 1. This is the minimum number of times to guarantee all the characteristics after reprogramming. The guaranteed range is from 1 to the minimum value. Note 2. This indicates the minimum value of the characteristic when reprogramming is performed within the specified range. Note 3. This result is obtained from reliability testing. Note 4. The reference value at VCC = 3.3 V and room temperature. RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 77 of 92

2.11 Serial Wire Debug (SWD)

Table 2.47 SWD Parameter Symbol Min Typ Max Unit Test conditions SWCLK clock cycle time tSWCKcyc 40 — — ns Figure 2.69 SWCLK clock high pulse width tSWCKH 15 — — ns SWCLK clock low pulse width tSWCKL 15 — — ns SWCLK clock rise time tSWCKr — — 5 ns SWCLK clock fall time tSWCKf — — 5 ns SWDIO setup time tSWDS 8 — — ns Figure 2.70 SWDIO hold time tSWDH 8 — — ns SWDIO data delay time tSWDD 2 — 28 ns SWCLK t SWCKH t SWCKcyc t SWCKL Figure 2.69 SWD SWCLK timing RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 78 of 92

(Input) t SWDD SWDIO (Output) t SWDD SWDIO (Output) t SWDD SWDIO (Output) Figure 2.70 SWD input/output timing RA6E2 Datasheet 2. Electrical Characteristics R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 79 of 92

Appendix 1. Port States in Each Processing Mode Function Pin function Reset Software Standby mode Deep Software Standby mode After Deep Software Standby mode is canceled (return to startup mode) IOKEEP = 0 IOKEEP = 1*1 Mode MD Pull-up Keep-O Keep Hi-Z Keep IRQ IRQx Hi-Z Keep-O*2 Keep Hi-Z Keep IRQx-DS Hi-Z Keep-O*2 Keep*3 Hi-Z Keep AGT AGTIOn Hi-Z Keep-O*2 Keep Hi-Z Keep AGTIOn (n = 1) Hi-Z Keep-O*2 Keep*3 Hi-Z Keep SCI RXD0 Hi-Z Keep-O*2 Keep Hi-Z Keep I3C I3C_SCL/I3C_SDA SCLn/SDAn Hi-Z Keep-O*2 Keep Hi-Z Keep USBFS USB_VBUS Hi-Z Keep-O*2 Keep*3 Hi-Z Keep USB_DP/USB_DM Hi-Z Keep-O*4 Keep*3 Hi-Z Keep RTC RTCICx Hi-Z Keep-O*2 Keep*3 Hi-Z Keep RTCOUT Hi-Z [RTCOUT selected] RTCOUT output Keep Hi-Z Keep CLKOUT CLKOUT Hi-Z [CLKOUT selected] CLKOUT output Keep Hi-Z Keep DAC DAn Hi-Z [DAn output (DAOE = 1)] D/A output retained Keep Hi-Z Keep Others — Hi-Z Keep-O Keep Hi-Z Keep Note: H: High-level L: Low-level Hi-Z: High-impedance Keep-O: Output pins retain their previous values. Input pins go to high-impedance. Keep: Pin states are retained during periods in Software Standby mode. Note 1. Retains the I/O port state until the DPSBYCR.IOKEEP bit is cleared to 0. Note 2. Input is enabled if the pin is specified as the Software Standby canceling source while it is used as an external interrupt pin. Note 3. Input is enabled if the pin is specified as the Deep Software Standby canceling source. Note 4. Input is enabled while the pin is used as an input pin. RA6E2 Datasheet Appendix 1. Port States in Each Processing Mode R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 80 of 92

Appendix 2. Package Dimensions Information on the latest version of the package dimensions or mountings is displayed in “Packages” on the Renesas Electronics Corporation website. MASS (Typ) [g] 0.3 Unit: mm Previous CodeRENESAS Code PLQP0064KB-C — P-LFQFP64-10x10-0.50 © 2015 Renesas Electronics Corporation. All rights reserved. D E HD HE A bp c e x y Lp 9.9 9.9 11.8 11.8 0.05 0.15 0.09 0.45 Min Nom Dimensions in millimetersReference Symbol Max 10.0 10.0 1.4 12.0 12.0 0.20 3.5 0.5 0.6 1.0 10.1 10.1 12.2 12.2 1.7 0.15 0.27 0.20 0.08 0.08 0.75 NOTE) 1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH. 2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET. 3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE LOCATED WITHIN THE HATCHED AREA. 4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY. HD A2A1 Lp Detail F A c 0.25 D 48 33 3249 161 F NOTE 4 NOTE 3 Index area HE E*2 bpe yS S M Figure 2.1 LQFP 64-pin RA6E2 Datasheet Appendix 2. Package Dimensions R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 81 of 92

(D/2 X E/2) D SEATING PLANE ccc C bbb C A B ddd C e b(48X) L(48X) K(48X) C aaa C B aaa C (A3) A1A eee C fff C A B fff C A B A EXPOSED DIE PAD 1 12 2536 E 48X 36 25 121 37 24 Reference Symbol Dimension in Millimeters Min. Nom. Max. A － － 0.80 A1 0.00 0.02 0.05 A3 0.203 REF. b 0.20 0.25 0.30 D 7.00 BSC E 7.00 BSC e 0.50 BSC L 0.30 0.40 0.50 K 0.20 － － D2 5.25 5.30 5.35 E2 5.25 5.30 5.35 aaa 0.15 bbb 0.10 ccc 0.10 ddd 0.05 eee 0.08 fff 0.10 P-HWQFN048-7x7-0.50 PWQN0048KC-A 0.13 g Figure 2.2 QFN 48-pin RA6E2 Datasheet Appendix 2. Package Dimensions R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 82 of 92

INDEX AREA(D/2 X E/2)D E SEATING PLANEcccC32X bbbCABdddC eb(32X) 321 89 161724 L(32X)K(32X) C aaaC B2XaaaC (A3)A1AeeeC fffCABfffCAB A32 2524 1716 981 外形図 Outline drawingRenesasコード PWQN0032KE-Aルネサスエレクトロニクス株式会社Renesas Electronics CorporationRDK-G-0014451/1 Figure 2.3 QFN 32-pin RA6E2 Datasheet Appendix 2. Package Dimensions R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 83 of 92

外形図 Outline drawingRenesasコード PLBG0064KB-Aルネサスエレクトロニクス株式会社Renesas Electronics CorporationRDK-G-001***1/1 D A aaaCcccC AA1dddCE1 D1e φeeeCABφfffCn X φb B C INDEX AREA Figure 2.4 BGA 64-pin RA6E2 Datasheet Appendix 2. Package Dimensions R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 84 of 92

外形図 Outline drawingRenesasコード PLBG0036KA-Aルネサスエレクトロニクス株式会社Renesas Electronics CorporationRDK-G-001***1/1 E D A aaaCcccC AA1dddCE1 D1e φeeeCABφfffCn X φb B C INDEX AREA Figure 2.5 BGA 36-pin RA6E2 Datasheet Appendix 2. Package Dimensions R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 85 of 92

Appendix 3. I/O Registers This appendix describes I/O register address and access cycles by function.

3.1 Peripheral Base Addresses

This section provides the base addresses for peripherals described in this manual. Table 3.1 shows the name, description, and the base address of each peripheral. Table 3.1 Peripheral base address (1 of 2) Name Description Base address RMPU Renesas Memory Protection Unit 0x4000_0000 TZF TrustZone Filter 0x4000_0E00 SRAM SRAM Control 0x4000_2000 BUS BUS Control 0x4000_3000 DMAC0 Direct memory access controller 0 0x4000_5000 DMAC1 Direct memory access controller 1 0x4000_5040 DMAC2 Direct memory access controller 2 0x4000_5080 DMAC3 Direct memory access controller 3 0x4000_50C0 DMAC4 Direct memory access controller 4 0x4000_5100 DMAC5 Direct memory access controller 5 0x4000_5140 DMAC6 Direct memory access controller 6 0x4000_5180 DMAC7 Direct memory access controller 7 0x4000_51C0 DMA DMAC Module Activation 0x4000_5200 DTC Data Transfer Controller 0x4000_5400 ICU Interrupt Controller 0x4000_6000 CACHE CACHE 0x4000_7000 CPSCU CPU System Security Control Unit 0x4000_8000 DBG Debug Function 0x400_1B000 FCACHE Flash Cache 0x400_1C100 SYSC System Control 0x4001_E000 PORT0 Port 0 Control Registers 0x4008_0000 PORT1 Port 1 Control Registers 0x4008_0020 PORT2 Port 2 Control Registers 0x4008_0040 PORT3 Port 3 Control Registers 0x4008_0060 PORT4 Port 4 Control Registers 0x4008_0080 PORT5 Port 5 Control Registers 0x4008_00A0 PORT8 Port 8 Control Registers 0x4008_0100 PFS Pmn Pin Function Control Register 0x4008_0800 ELC Event Link Controller 0x4008_2000 RTC Realtime Clock 0x4008_3000 IWDT Independent Watchdog Timer 0x4008_3200 WDT Watchdog Timer 0x4008_3400 CAC Clock Frequency Accuracy Measurement Circuit 0x4008_3600 MSTP Module Stop Control A, B, C, D 0x4008_4000 POEG Port Output Enable Module for GPT 0x4008_A000 RA6E2 Datasheet Appendix 3. I/O Registers R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 86 of 92

Table 3.1 Peripheral base address (2 of 2) Name Description Base address USBFS USB 2.0 FS Module 0x4009_0000 SSIE0 Serial Sound Interface Enhanced (SSIE) 0x4009_D000 CEC Consumer Electronics Control 0x400A_C000 CANFD CANFD Module Control 0x400B_0000 PSCU Peripheral Security Control Unit 0x400E_0000 AGT0 Low Power Asynchronous General purpose Timer 0 0x400E_8000 AGT1 Low Power Asynchronous General purpose Timer 1 0x400E_8100 TSN Temperature Sensor 0x400F_3000 CRC CRC Calculator 0x4010_8000 DOC Data Operation Circuit 0x4010_9000 SCI0 Serial Communication Interface 0 0x4011_8000 SCI9 Serial Communication Interface 9 0x4011_8900 SPI0 Serial Peripheral Interface 0 0x4011_A000 SPI1 Serial Peripheral Interface 1 0x4011_A100 I3C I3C Bus Interface 0x4011_F000 CANFD ECC CANFD ECC 0x4012_F000 GPT16E0 General PWM 16-Bit Timer 0 (16-bit Enhanced High Resolution) 0x4016_9000 GPT16E1 General PWM 16-Bit Timer 1 (16-bit Enhanced High Resolution) 0x4016_9100 GPT16E2 General PWM 16-Bit Timer 2 (16-bit Enhanced High Resolution) 0x4016_9200 GPT16E3 General PWM 16-Bit Timer 3 (16-bit Enhanced High Resolution) 0x4016_9300 GPT16E4 General PWM 16-Bit Timer 4 (16-bit Enhanced High Resolution) 0x4016_9400 GPT16E5 General PWM 16-Bit Timer 5 (16-bit Enhanced High Resolution) 0x4016_9500 GPT_OPS Output Phase Switching Controller 0x4016_9A00 ADC120 12bit A/D Converter 0 0x4017_0000 DAC12 12-bit D/A converter 0x4017_1000 FLAD Data Flash 0x407F_C000 FACI Flash Application Command Interface 0x407F_E000 QSPI Quad-SPI 0x6400_0000 Note: Name = Peripheral name Description = Peripheral functionality Base address = Lowest reserved address or address used by the peripheral

3.2 Access Cycles

This section provides access cycle information for the I/O registers described in this manual.

• Registers are grouped by associated module.
• The number of access cycles indicates the number of cycles based on the specified reference clock.
• In the internal I/O area, reserved addresses that are not allocated to registers must not be accessed, otherwise operations cannot be guaranteed.
• The number of I/O access cycles depends on bus cycles of the internal peripheral bus, divided clock synchronization cycles, and wait cycles of each module. Divided clock synchronization cycles differ depending on the frequency ratio between ICLK and PCLK.
• When the frequency of ICLK is equal to that of PCLK, the number of divided clock synchronization cycles is always constant. RA6E2 Datasheet Appendix 3. I/O Registers R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 87 of 92

• When the frequency of ICLK is greater than that of PCLK, at least 1 PCLK cycle is added to the number of divided clock synchronization cycles.
• The number of write access cycles indicates the number of cycles obtained by non-bufferable write access. Note: This applies to the number of cycles when access from the CPU does not conflict with the instruction fetching to the external memory or bus access from other bus masters such as DTC or DMAC. Table 3.2 Access cycles (1 of 3) Peripherals Address Number of access cycles ICLK = PCLK ICLK > PCLK*1 Cycle Unit Related functionFrom To Read Write Read Write RMPU, TZF, SRAM, BUS, DMACn, DMA, DTC, ICU 0x4000_0000 0x4000_6FFF 4 3 4 3 ICLK Renesas Memory Protection Unit, TrustZone Filter, SRAM Control, BUS Control, Direct memory access controller n, DMAC Module Activation, DTC Control Register, Interrupt Controller CACHE 0x4000_7000 0x4000_7FFF 3 5 3 5 ICLK CACHE CPSCU, DBG, FCACHE 0x4000_8000 0x4001_CFFF 4 3 4 3 ICLK CPU System Security Control Unit, Debug Function, Flash Cache SYSC 0x4001_E000 0x4001_E3FF 5 4 5 4 ICLK System Control SYSC 0x4001_E400 0x4001_E5FF 9 8 5 to 8 5 to 8 PCLKB System Control PORTn, PFS 0x4008_0000 0x4008_0FFF 5 4 2 to 5 2 to 4 PCLKB Port n Control Registers, Pmn Pin Function Control Register ELC, RTC, IWDT, WDT, CAC 0x4008_2000 0x4008_3FFF 5 4 3 to 5 2 to 4 PCLKB Event Link Controller, Realtime Clock, Independent Watchdog Timer, Watchdog Timer, Clock Frequency Accuracy Measurement Circuit MSTP 0x4008_4000 0x4008_4FFF 5 4 2 to 5 2 to 4 PCLKB Module Stop Control POEG 0x4008_A000 0x4008_AFFF 5 4 3 to 5 2 to 4 PCLKB Port Output Enable Module for GPT USBFS 0x4009_0000 0x4009_03FF 6 5 3 to 6 3 to 5 PCLKB USB 2.0 FS Module USBFS 0x4009_0400 0x4009_04FF 4 3 1 to 4 1 to 3 PCLKB USB 2.0 FS Module SSIE0 0x4009_2000 0x4009_FFFF 5 4 2 to 5 2 to 4 PCLKB SD Host Interface 0, Serial Sound Interface Enhanced, Inter- Integrated Circuit n, Inter-Integrated Circuit

0 Wake-up Unit

CEC 0x400A_C000 0x400A_CFFF 4 3 1 to 3 1 to 3 PCLKB Consumer Electronics Control CANFD 0x400B_0000 0x400C_FFFF 5 4 2 to 5 2 to 4 PCLKB CANFD Module PSCU 0x400E_0000 0x400E_0FFF 5 4 2 to 5 2 to 4 PCLKB Peripheral Security Control Unit AGTn 0x400E_8000 0x400E_8FFF 7 4 5 to 7 2 to 4 PCLKB Low Power Asynchronous General purpose Timer n TSN 0x400F_3000 0x400F_3FFF 5 4 2 to 5 2 to 4 PCLKB Temperature Sensor CRC, DOC 0x4010_8000 0x4010_9FFF 5 4 2 to 5 2 to 4 PCLKA CRC Calculator, Data Operation Circuit RA6E2 Datasheet Appendix 3. I/O Registers R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 88 of 92

Table 3.2 Access cycles (2 of 3) Peripherals Address Number of access cycles ICLK = PCLK ICLK > PCLK*1 Cycle Unit Related functionFrom To Read Write Read Write SCIn 0x4011_8000 0x4011_8FFF 5*2 4*2 2 to 5*2 2 to 4*2 PCLKA Serial Communication Interface n SPIn 0x4011_A000 0x4011_AFFF 5*3 4*3 2 to 5*3 2 to 4*3 PCLKA Serial Peripheral Interface n I3C 0x4011_F000 0x4011_FFFF 5 4 2 to 4 2 to 4 PCLKA I3C Bus Interface CANFD ECC 0x4012_F000 0x4012_FFFF 5 4 2 to 4 2 to 4 PCLKA CANFD ECC Module GPT16En, GPT_OPS 0x4016_9000 0x4016_9FFF 7 4 4 to 7 2 to 4 PCLKA General PWM 16-Bit Timer n, Output Phase Switching Controller ADC12n, DAC12 0x4017_0000 0x4017_2FFF 5 4 2 to 5 2 to 4 PCLKA 12bit A/D Converter n, 12-bit D/A converter QSPI 0x6400_0010 0x6400_0013 25 to *4 6 to *4 25 to *4 5 to *4 PCLKA Quad-SPI QSPI 0x6400_0014 0x6400_0037 5 14 to *4 2 to 5 14 to *4 PCLKA Quad-SPI QSPI 0x6400_0804 0x6400_0807 4 3 1 to 4 1 to 3 PCLKA Quad-SPI Table 3.2 Access cycles (3 of 3) Peripherals Address Number of access cycles ICLK = FCLK ICLK > FCLK*1 Cycle Unit Related functionFrom To Read Write Read Write FLAD, FACI 0x407F_C000 0x407F_EFFF 5 4 2 to 5 2 to 4 FCLK Data Flash, Flash Application Command Interface Note 1. If the number of PCLK or FCLK cycles is non-integer (for example 1.5), the minimum value is without the decimal point, and the maximum value is rounded up to the decimal point. For example, 1.5 to 2. 5 is 1 to 3. Note 2. When accessing a 16-bit register (FTDRHL, FRDRHL, FCR, FDR, LSR, and CDR), access is 2 cycles more than the value shown in Table 3.2. When accessing an 8-bit register (including FTDRH, FTDRL, FRDRH, and FRDRL), the access cycles are as shown in Table 3.2. Note 3. When accessing the 32-bit register (SPDR), access is 2 cycles more than the value in Table 3.2. When accessing an 8-bit or 16-bit register (SPDR_HA), the access cycles are as shown in Table 3.2. Note 4. The access cycles depend on the QSPI bus cycles. RA6E2 Datasheet Appendix 3. I/O Registers R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 89 of 92

Revision History

Revision 1.00 — September 26, 2022 Initial release Revision 1.10 — February 28, 2023 Features:

• Updated the title of Security. 1. Overview:
• Updated Figure 1.1 Block diagram.
• Updated Table 1.11 I/O ports.
• Updated Figure 1.2 Part numbering scheme.
• Updated Table 1.13 Function Comparison.
• Updated Table 1.14 Pin functions.
• Updated Figure 1.4 Pin assignment for BGA 64-pin.
• Updated Figure 1.6 Pin assignment for BGA 36-pin 2. Electrical Characteristics:
• Updated Table 2.5 I/O I OH, IOL.
• Updated Table 2.6 I/O VOH, VOL, and other characteristics.
• Updated Table 2.34 I3C timing (push-pull timing parameters for SDR mode).
• Updated Table 2.37 USBFS full-speed characteristics (USB_DP and USB_DM pin characteristics). Appendix 3. I/O Registers:
• Updated Table 3.2 Access cycles. RA6E2 Datasheet Revision History R01DS0410EJ0110 Rev.1.10 Feb 28, 2023 Page 90 of 92

General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1. Precaution against Electrostatic Discharge (ESD) A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices. 2. Processing at power-on The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the level at which resetting is specified. 3. Input of signal during power-off state Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Follow the guideline for input signal during power-off state as described in your product documentation. 4. Handling of unused pins Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. 5. Clock signals After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable. 6. Voltage application waveform at input pin Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.). 7. Prohibition of access to reserved addresses Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these addresses as the correct operation of the LSI is not guaranteed. 8. Differences between products Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system- evaluation test for the given product.

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