RA4W1

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www.renesas.com Renesas RA4W1 Group Datasheet 32-Bit MCU Renesas Advanced (RA) Family Renesas RA4 Series Mar 2020Rev.1.00 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp. website (http://www.renesas.com). Cover

R01DS0359EJ0100 Rev.1.00 Page 2 of 105 Mar 31, 2020

Features

■ Arm Cortex-M4 Core with Floating Point Unit (FPU)  Armv7E-M architecture with DSP instruction set  Maximum operating frequency: 48 MHz  Support for 4-GB address space  Arm Memory Protection Unit (Arm MPU) with 8 regions  Debug and Trace: ITM, DWT, FPB, TPIU, and ETB  CoreSight™ debug port: JTAG-DP and SW-DP ■ Memory  512-KB code flash memory  8-KB data flash memory (100,000 erase/write cycles)  96-KB SRAM  Flash Cache (FCACHE)  Memory Protection Units  Memory Mirror Function (MMF)  128-bit unique ID ■ Connectivity  Bluetooth Low Energy - Bluetooth 5.0 core specification compliant BLE transceiver and link layer - Supporting LE 1M, 2M and Coded PHY, and LE Advertising extension - Dedicated AES-CCM (128-bit blocks) encryption circuit  USB 2.0 Full-Speed (USBFS) module - On-chip transceiver - Compliant with USB Battery Charging Specification 1.2  Serial Communications Interface (SCI) × 4 - UART - Simple IIC - Simple SPI  Serial Peripheral Interface (SPI) × 2  I 2C bus interface (IIC) × 2  Controller Area Network (CAN) module ■ Analog  14-bit A/D Converter (ADC14)  12-bit D/A Converter (DAC12)  8-bit D/A Converter (DAC8) ×2 (for ACMPLP)  Low Power Analog Comparator (ACMPLP) × 2  Operational Amplifier (OPAMP) × 1  Temperature Sensor (TSN) ■ Timers  General PWM Timer 32-bit (GPT32) × 4  General PWM Timer 16-bit (GPT16) × 3  Asynchronous General-Purpose Timer (AGT) × 2  Watchdog Timer (WDT) ■ Safety  Error Correction Code (ECC) in SRAM  SRAM parity error check  Flash area protection  ADC self-diagnosis function  Clock Frequency Accuracy Measurement Circuit (CAC)  Cyclic Redundancy Check (CRC) calculator  Data Operation Circuit (DOC)  Port Output Enable for GPT (POEG)  Independent Watchdog Timer (IWDT)  GPIO readback level detection  Register write protection  Main oscillator stop detection  Illegal memory access ■ System and Power Management  Low power modes  Realtime Clock (RTC) with calendar and Battery Backup support  Event Link Controller (ELC)  DMA Controller (DMAC) × 4  Data Transfer Controller (DTC)  Key Interrupt Function (KINT)  Power-on reset  Low Voltage Detection (LVD) with voltage settings ■ Security and Encryption  AES128/256  GHASH  True Random Number Generator (TRNG) ■ Human Machine Interface (HMI)  Segment LCD Controller (SLCDC) - Up to 9 segments × 4 commons - Capacitive Touch Sensing Unit (CTSU) ■ Multiple Clock Sources  Main clock oscillator (MOSC) (1 to 20 MHz when VCC = 2.4 to 3.6 V) (1 to 8 MHz when VCC = 1.8 to 2.4 V)  Sub-clock oscillator (SOSC) (32.768 kHz)  High-speed on-chip oscillator (HOCO) (24, 32, 48, 64 MHz when VCC = 2.4 to 3.6 V) (24, 32, 48 MHz when VCC = 1.8 to 3.6 V)  Middle-speed on-chip oscillator (MOCO) (8 MHz)  Low-speed on-chip oscillator (LOCO) (32.768 kHz)  IWDT-dedicated on-chip oscillator (15 kHz)  Clock trim function for HOCO/MOCO/LOCO  Clock out support ■ General Purpose I/O Ports  Up to 35 input/output pins - Up to 3 CMOS input - Up to 32 CMOS input/output - Up to 4 input/output 5 V tolerant - Up to 1 high current (20 mA) ■ Operating Voltage  VCC: 1.8 to 3.6 V ■ Operating Temperature and Packages  Ta = –40°C to +85°C - 56-pin QFN (7 mm × 7 mm, 0.4 mm pitch) High efficiency 48-MHz Arm® Cortex®-M4 core, 512-KB code flash memory, 96-KB SRAM, Segment LCD Controller, Capacitive Touch Sensing Unit, Bluetooth Low Energy, USB 2.0 Full-Speed, 14-Bit A/D Converter, 12-Bit D/A Converter, security and safety features. RA4W1 Group Datasheet

R01DS0359EJ0100 Rev.1.00 Page 3 of 105 Mar 31, 2020 RA4W1 Datasheet 1. Overview 1. Overview The MCU integrates multiple series of software- and pin-compatible Arm®-based 32-bit cores that share a common set of Renesas peripherals to facilitate design scalability and efficient platform-based product development. The MCU in this series incorporates a low-power and high-performance Arm Cortex®-M4 32-bit core running up to

48 MHz, with the following features:

 512-KB code flash memory  96-KB SRAM  Bluetooth Low Energy (BLE)  Segment LCD Controller (SLCDC)  Capacitive Touch Sensing Unit (CTSU)  USB 2.0 Full-Speed Module (USBFS)  14-bit A/D Converter (ADC14)  12-bit D/A Converter (DAC12)  Security features.

1.1 Function Outline

Table 1.1 Arm core Feature Functional description Arm Cortex-M4 core  Maximum operating frequency: up to 48 MHz  Arm Cortex-M4 core: - Revision: r0p1-01rel0 - Armv7E-M architecture profile - Single precision floating-point unit compliant with the ANSI/IEEE Std 754-2008.  Arm Memory Protection Unit (Arm MPU): - Armv7 Protected Memory System Architecture - 8 protect regions  SysTick timer: - Driven by SYSTICCLK (LOCO) or ICLK. Table 1.2 Memory Feature Functional description Code flash memory Maximum 512 KB of code flash memory . See section 43, Flash Memory in User’s Manual. Data flash memory 8 KB of data flash memory. S ee section 43, Flash Memory in User’s Manual. Option-setting memory The option-setting memory determines t he state of the MCU after a reset. See section 7, Option-Setting Memory in User’s Manual. Memory Mirror Function (MMF) The Memory Mirror Function (MMF) can be configured to mirror the desired application image load address in code flash memory to the application image link address in the 23-bit unused memory space (memory mirror space addresses). Your application code is developed and linked to run from this MMF destination address. The application code does not need to know the load location where it is stored in code flash memory. See section 5, Memory Mirror Function (MMF) in User’s Manual. SRAM On-chip high-speed SRAM with either parity bit or Error Correction Code (ECC). An area in SRAM0 provides error correction capability using ECC. See section 42, SRAM in User’s Manual.

R01DS0359EJ0100 Rev.1.00 Page 4 of 105 Mar 31, 2020 RA4W1 Datasheet 1. Overview Table 1.3 System (1 of 2) Feature Functional description Operating modes Two operating modes:  Single-chip mode  SCI/USB boot mode. See section 3, Operating Modes in User’s Manual. Resets 14 resets:  RES pin reset  Power-on reset  VBATT-selected voltage power-on reset  Independent watchdog timer reset  Watchdog timer reset  Voltage monitor 0 reset  Voltage monitor 1 reset  SRAM parity error reset  SRAM ECC error reset  Bus master MPU error reset  Bus slave MPU error reset  Stack pointer error reset  Software reset. See section 6, Resets in User’s Manual. Low Voltage Detection (LVD) The Low Voltage Detection (LVD) monitors the voltage level input to the VCC pin, and the detection level can be selected using a software program. See section 8, Low Voltage Detection (LVD) in User’s Manual. Clocks  Main clock oscillator (MOSC)  Sub-clock oscillator (SOSC)  High-speed on-chip oscillator (HOCO)  Middle-speed on-chip oscillator (MOCO)  Low-speed on-chip oscillator (LOCO)  PLL frequency synthesizer  IWDT-dedicated on-chip oscillator  Bluetooth-dedicated clock oscillator  Bluetooth-dedicated low-speed on-chip oscillator  Clock out support. See section 9, Clock Generation Circuit in User’s Manual. Clock Frequency Accuracy Measurement Circuit (CAC) The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to be measured (measurement target clock) within the time generated by the clock to be used as a measurement reference (measurement reference clock), and determines the accuracy depending on whether the number of pulses is within the allowable range. When measurement is complete or the number of pulses within the time generated by the measurement reference clock is not within the allowable range, an interrupt request is generated. See section 10, Clock Frequency Accuracy Measurement Circuit (CAC) in User’s Manual. Interrupt Controller Unit (ICU) The Interrupt Controller Unit (ICU) controls which event signals are linked to the NVIC/DTC module and DMAC module. The ICU also controls NMI interrupts. See section 14, Interrupt Controller Unit (ICU) in User’s Manual. Key Interrupt Function (KINT) A key interrupt can be generated by setting the Key Return Mode Register (KRM) and inputting a rising or falling edge to the key interrupt input pins. See section 21, Key Interrupt Function (KINT) in User’s Manual. Low Power Mode Power consumption can be reduced in mu ltiple ways, such as by setting clock dividers, stopping modules, selecting power control mode in normal operation, and transitioning to low power modes. See section 11, Low Power Modes in User’s Manual. Battery backup function A battery backup function is provided for partial powering by a battery. The battery powered area includes RTC, SOSC, LOCO, wakeup control, backup memory, VBATT_R low voltage detection, and switch between VCC and VBATT. During normal operation, the battery powered area is powered by the main power supply, which is the VCC pin. When a VCC voltage fall is detected, the power source is switched to the dedicated battery backup power pin, the VBATT pin. When the voltage rises again, the power source is switched from the VBATT pin to the VCC pin. See section 12, Battery Backup Function in User’s Manual. Register write protection The register write protection func tion protects important registers from being overwritten because of software errors. See section 13, Register Write Protection in User’s Manual.

R01DS0359EJ0100 Rev.1.00 Page 5 of 105 Mar 31, 2020 RA4W1 Datasheet 1. Overview Memory Protection Unit (MPU) Four Memory Protection Units (M PUs) and a CPU stack pointer monitor function are provided for memory protection. See section 16, Memory Protection Unit (MPU) in User’s Manual. Watchdog Timer (WDT) The Watchdog Timer (WDT) is a 14-bit dow n-counter that can be used to reset the MCU when the counter underflows because the system has run out of control and is unable to refresh the WDT. In addition, a non-maskable interrupt or interrupt can be generated by an underflow. The refresh-permitted period can be set to refresh the counter and used as the condition for detecting when the system runs out of control. See section 26, Watchdog Timer (WDT) in User’s Manual. Independent Watchdog Timer (IWDT) The Independent Watchdog Timer (IWDT) consists of a 14-bit down-counter that must be serviced periodically to prevent counter underflow. It can be used to reset the MCU or to generate a non-maskable interrupt/interrupt for a timer underflow. Because the timer operates with an independent, dedicated clock source, it is particularly useful in returning the MCU to a known state as a fail-safe mechanism when the system runs out of control. The IWDT can be triggered automatically on a reset, underflow, refresh error, or by a refresh of the count value in the registers. See section 27, Independent Watchdog Timer (IWDT) in User’s Manual. Table 1.4 Event link Feature Functional description Event Link Controller (ELC) The Event Link Controller (ELC) uses the interrupt requests generated by various peripheral modules as event signals to connect them to different modules, enabling direct interaction between the modules without CPU intervention. See section 19, Event Link Controller (ELC) in User’s Manual. Table 1.5 Direct memory access Feature Functional description Data Transfer Controller (DTC) A Data Transfer Controller (D TC) module is provided for transferring data when activated by an interrupt request. See section 18, Data Transfer Controller (DTC) in User’s Manual. DMA Controller (DMAC) A 4-channel DMA Controller (DMAC) m odule is provided for transferring data without the CPU. When a DMA transfer request is generated, the DMAC transfers data stored at the transfer source address to the transfer destination address. See section 17, DMA Controller (DMAC) in User’s Manual. Table 1.3 System (2 of 2) Feature Functional description

R01DS0359EJ0100 Rev.1.00 Page 6 of 105 Mar 31, 2020 RA4W1 Datasheet 1. Overview Table 1.6 Timers Feature Functional description General PWM Timer (GPT) The General PWM Timer (GPT) is a 32-bit timer with 4 channels and a 16-bit timer with 3 channels. PWM waveforms can be generated by controlling the up-counter, down-counter, or the up- and down-counter. In addition, PWM waveforms can be generated for controlling brushless DC motors. The GPT can also be used as a general-purpose timer. See section 23, General PWM Timer (GPT) in User’s Manual. Port Output Enable for GPT (POEG) Use the Port Output Enable for GPT (POEG) function to place the General PWM Timer (GPT) output pins in the output disable state. See section 22, Port Output Enable for GPT (POEG) in User’s Manual. Asynchronous General Purpose Timer (AGT) The Asynchronous General Purpose Timer (AGT) is a 16-bit timer that can be used for pulse output, external pulse width or period measurement, and counting of external events. This 16-bit timer consists of a reload register and a down-counter. The reload register and the down-counter are allocated to the same address, and they can be accessed with the AGT register. See section 24, Asynchronous General Purpose Timer (AGT) in User’s Manual. Realtime Clock (RTC) The Realtime Clock (RTC) has two counting modes, calendar count mode and binary count mode, that are controlled by the register settings. For calendar count mode, the RTC has a 100-year calendar from 2000 to 2099 and automatically adjusts dates for leap years. For binary count mode, the RTC counts seconds and retains the information as a serial value. Binary count mode can be used for calendars other than the Gregorian (Western) calendar. See section 25, Realtime Clock (RTC) in User’s Manual. Table 1.7 Communication interfaces (1 of 2) Feature Functional description Serial Communications Interface (SCI) The Serial Communication Interface (SCI) is configurable to five asynchronous and synchronous serial interfaces:  Asynchronous interfaces (UART and asynchronous communications interface adapter (ACIA))  8-bit clock synchronous interface  Simple IIC (master-only)  Simple SPI  Smart card interface. The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and transmission protocol. SCI0 and SCI1 have FIFO buffers to enable continuous and full-duplex communication, and the data transfer speed can be configured independently using an on-chip baud rate generator. See section 29, Serial Communications Interface (SCI) in User’s Manual. I 2C bus interface (IIC) The 2-channel I2C bus interface (IIC) conforms with and provides a subset of the NXP I2C (Inter-Integrated Circuit) bus interface functions. See section 30, I2C Bus Interface (IIC) in User’s Manual. Serial Peripheral Interface (SPI) Two independent Serial Periph eral Interface (SPI) channels are capable of high-speed, full- duplex synchronous serial communications with multiple processors and peripheral devices. See section 32, Serial Peripheral Interface (SPI) in User’s Manual. Controller Area Network (CAN) module The Controller Area Network (CAN) module provides functionality to receive and transmit data using a message-based protocol between multiple slaves and masters in electromagnetically noisy applications. The CAN module complies with the ISO 11898-1 (CAN 2.0A/CAN 2.0B) standard and supports up to 32 mailboxes, which can be configured for transmission or reception in normal mailbox and FIFO modes. Both standard (11-bit) and extended (29-bit) messaging formats are supported. See section 31, Controller Area Network (CAN) Module in User’s Manual. USB 2.0 Full-Speed (USBFS) module The USB 2.0 Full-Speed (USBFS) m odule can operate as a host controller or device controller. The module supports full-speed and low-speed (only for the host controller) transfer as defined in the Universal Serial Bus Specification 2.0. The module has an internal USB transceiver and supports all of the transfer types defined in the Universal Serial Bus Specification 2.0. The USB has buffer memory for data transfer, providing a maximum of 10 pipes. Pipes 1 to 9 can be assigned any endpoint number based on the peripheral devices used for communication or based on the user system. The MCU supports revision 1.2 of the Battery Charging Specification. See section 28, USB 2.0 Full-Speed Module (USBFS) in User’s Manual.

R01DS0359EJ0100 Rev.1.00 Page 7 of 105 Mar 31, 2020 RA4W1 Datasheet 1. Overview Bluetooth low energy(BLE)  On-chip RF transceiver and link layer compliant with the Bluetooth 5.0 Low Energy specification  Bit rates: 1 Mbps, 2 Mbps, 500 kbps, and 125 kbps  LE Advertising extension support  Includes an RF transceiver power supply (selectable as a DC-to-DC converter or linear regulator)  On-chip matching circuit to help reduce the number of external parts  Transmission power: +4 dBm support Table 1.8 Analog Feature Functional description 14-bit A/D Converter (ADC14) A 14-bit succ essive approximation A/D converter is provided. Up to 8 analog input channels are selectable. Temperature sensor output and internal reference voltage are selectable for conversion. The A/D conversion accuracy is selectable from 12-bit and 14-bit conversion making it possible to optimize the tradeoff between speed and resolution in generating a digital value. See section 34, 14-Bit A/D Converter (ADC14) in User’s Manual. 12-bit D/A Converter (DAC12) The 12-bit D/A Converter (DAC12) converts data and includes an output amplifier. See section 35, 12-Bit D/A Converter (DAC12) in User’s Manual. 8-bit D/A Converter (DAC8) for ACMPLP The 8-bit D/A Converter (DAC8) converts data and does not include an output amplifier. The DAC8 is used only as the reference voltage for ACMPLP. See section 39, 8-Bit D/A Converter (DAC8) in User’s Manual. Temperature Sensor (TSN) The on-chip temperature sensor determines and monitors the die temperature for reliable operation of the device. The sensor outputs a voltage directly proportional to the die temperature, and the relationship between the die temperature and the output voltage is linear. The output voltage is provided to the ADC14 for conversion and can be further used by the end application. See section 36, Temperature Sensor (TSN) in User’s Manual. Low-Power Analog Comparator (ACMPLP) The Low-Power Analog Comparator (ACMPLP) compares a reference input voltage and analog input voltage. The comparison result can be read by software and also be output externally. The reference voltage can be selected from an input to the CMPREFi(i = 0,1) pin, an internal 8-bit D/A converter output, or the internal reference voltage (Vref) generated internally in the MCU. The ACMPLP response speed can be set before starting an operation. Setting the high-speed mode decreases the response delay time, but increases current consumption. Setting the low- speed mode increases the response delay time, but decreases current consumption. See section 38, Low Power Analog Comparator (ACMPLP) in User’s Manual. Operational Amplifier (OPAMP) The Operat ional Amplifier (OPAMP) can be used to amplify small analog input voltages and output the amplified voltages. A differential operational amplifier unit with two input pins and one output pin are provided. See section 37, Operational Amplifier (OPAMP) in User’s Manual. Table 1.9 Human machine interfaces Feature Functional description Segment LCD Controller (SLCDC) The SLC DC provides the following functions:  Waveform A or B selectable  The LCD driver voltage generator uses an external resistance division method  Automatic output of segment and common signals based on automatic display data register read  The LCD can be made to blink. See section 44, Segment LCD Controller (SLCDC) in User’s Manual. Capacitive Touch Sensing Unit (CTSU) The Capacitive Touch Sensing Unit (CTSU) measures the electrostatic capacitance of the touch sensor. Changes in the electrostatic capacitance are determined by software, which enables the CTSU to detect whether a finger is in contact with the touch sensor. The electrode surface of the touch sensor is usually enclosed with an electrical insulator so that a finger does not come into direct contact with the electrode. See section 40, Capacitive Touch Sensing Unit (CTSU) in User’s Manual. Table 1.7 Communication interfaces (2 of 2) Feature Functional description

R01DS0359EJ0100 Rev.1.00 Page 8 of 105 Mar 31, 2020 RA4W1 Datasheet 1. Overview Table 1.10 Data processing Feature Functional description Cyclic Redundancy Check (CRC) calculator The Cyclic Redundancy Check (CRC) calculator generates CRC codes to detect errors in the data. The bit order of CRC calculation results can be switched for LSB-first or MSB-first communication. Additionally, various CRC generation polynomials are available. The snoop function allows monitoring reads from and writes to specific addresses. This function is useful in applications that require CRC code to be generated automatically in certain events, such as monitoring writes to the serial transmit buffer and reads from the serial receive buffer. See section 33, Cyclic Redundancy Check (CRC) Calculator in User’s Manual. Data Operation Circuit (DOC) The Data Op eration Circuit (DOC) compares, adds, and subtracts 16-bit data. See section 41, Data Operation Circuit (DOC) in User’s Manual. Table 1.11 Security Feature Functional description Secure Crypto Engine 5 (SCE5)  Security algorithm: - Symmetric algorithm: AES  Other support features: - TRNG (True Random Number Generator) - Hash-value generation: GHASH.

R01DS0359EJ0100 Rev.1.00 Page 9 of 105 Mar 31, 2020 RA4W1 Datasheet 1. Overview

1.2 Block Diagram

Figure 1.1 shows a block diagram of the MCU superset. Some individual devices within the group may have a subset of the features. Figure 1.1 Block diagram

1.3 Part Numbering

Figure 1.2 shows how to read the product part number information, including memory capacity, and package type. Table 1.13 shows a product list. Memory

512 KB code flash

8 KB data flash

96 KB SRAM

DMAC × 4 System Mode control Power control ICU MOSC/SOSC Clocks (H/M/L) OCO PLL Battery backup GPT32 × 4 Timers AGT × 2 RTC CTSU Arm Cortex-M4 DSP FPU MPU NVIC System timer Test and DBG I/F Bus MPU DTC CSC External WDT/IWDT CAC POR/LVD Reset Human machine interfaces SLCDC ELC Event link SCE5 Security Analog CRC Data processing DOC Communication interfaces BLE IIC × 2 SPI × 2 CAN × 1 USBFS with Battery Charging revision 1.2 SCI × 4 TSN DAC12 ACMPLP × 2 ADC14 OPAMP × 1 GPT16 × 3 DAC8 KINT Register write protection

R01DS0359EJ0100 Rev.1.00 Page 10 of 105 Mar 31, 2020 RA4W1 Datasheet 1. Overview Figure 1.2 Part numbering scheme Table 1.12 Product list Product part number Orderable part number Code flash Data flash SRAM Operating temperature R7FA4W1AD2CNG R7FA4W1AD2CNG#AA0 512 KB 8 KB 96 KB -40 to +85°C D 2 C N G #AA 0R 7 F A 4 W 1 A Package type NG: QFN 56 pins Quality ID Operating temperature 2: -40 C to 85 C Code flash memory size D: 512 KB Feature set A: Security Series name 4: Up to 100MHz Renesas RA family Flash memory Renesas microcontroller Renesas Production identification code Packing, Terminal material (Pb-free) #AA: Tray/Sn(Tin) only #AC: Tray/others Group name W1: Wireless Communication 1

R01DS0359EJ0100 Rev.1.00 Page 11 of 105 Mar 31, 2020 RA4W1 Datasheet 1. Overview

1.4 Function Comparison

Table 1.13 Function comparison Part numbers R7FA4W1AD2CNG Pin count 56 Package QFN Code flash memory 512 KB Data flash memory 8 KB SRAM 96 KB Parity 80 KB ECC 16 KB System CPU clock 48 MHz Backup registers 512 bytes ICU Yes KINT 8 Event control ELC Yes DMA DTC Yes DMAC 4 Timers GPT32 4 GPT16 3 AGT 2 RTC Yes WDT/IWDT Yes Communication SCI 6 IIC 2 SPI 2 CAN 1 USBFS Yes BLE An RF transceiver and link layer compliant with Bluetooth 5.0 low energy specification Analog ADC14 8 DAC12 1 DAC8 2 ACMPLP 2 OPAMP 1 TSN Yes HMI SLCDC 4 com × 9 seg CTSU 11 Data processing CRC Yes DOC Yes Security SCE5

R01DS0359EJ0100 Rev.1.00 Page 12 of 105 Mar 31, 2020 RA4W1 Datasheet 1. Overview

1.5 Pin Functions

Function Signal I/O Description Power supply VCC Input Power supply pin. Connect it to the system power supply. Connect this pin to VSS by a 0.1-μF capacitor. The capacitor should be placed close to the pin. VCL Input Connect this pin to the VSS pin by t he smoothing capacitor used to stabilize the internal power supply. Place the capacitor close to the pin. VSS Input Ground pin. Connect it to the system power supply (0 V). VBATT Input Backup power pin Clock XTAL Output Pins for a crystal resonator. An external clock signal can be input through the EXTAL pin.EXTAL Input XCIN Input Input/output pins for the sub-cloc k oscillator. Connect a crystal resonator between XCOUT and XCIN.XCOUT Output CLKOUT_RF Output Bluetooth-dedicated clock output pin for output of a 1-, 2-, or 4-MHz signal XTAL1_RF Input Pins for connecting the Bluetoot h-dedicated clock oscillator. Connect a 32- MHz oscillator to these pins.XTAL2_RF Output CLKOUT Output Clock output pin Operating mode control MD Input Pins for setting the operating mode. The signal levels on these pins must not be changed during operation mode transition at the time of release from the reset state. System control RES Input Reset signal input pin. The MCU enters the reset state when this signal goes low. CAC CACREF Input Measurement reference clock input pin Interrupt NMI Input Non-maskable interrupt request pin IRQ0 to IRQ4, IRQ6, IRQ7, IRQ9, IRQ11, IRQ14, IRQ15 Input Maskable interrupt request pins KINT KR00 to KR07 Input A key interrupt can be generated by inputting a falling edge to the key interrupt input pins On-chip debug TMS I/O On-chip emulator pins TDI Input TCK Input TDO Output SWDIO I/O Serial Wire debug Data Input/Output pin SWCLK Input Serial Wire Clock pin SWO Output Serial Wire trace Output pin Battery backup VBATWIO0 I/O Output wakeup signal for the VBATT wakeup control function. External event input for the VBATT wakeup control function. GPT GTETRGA, GTETRGB Input External trigger input pin GTIO0A to GTIOA5A,GTIO8A, GTIO0B to GTIOA5B,GTIO8B I/O Input capture, Output capture, or PWM output pin GTIU Input Hall sensor input pin U GTIV Input Hall sensor input pin V GTIW Input Hall sensor input pin W GTOUUP Output 3-phase PWM output for BLDC motor control (positive U phase) GTOULO Output 3-phase PWM output for BLDC motor control (negative U phase) GTOVUP Output 3-phase PWM output for BLDC motor control (positive V phase) GTOVLO Output 3-phase PWM output for BLDC motor control (negative V phase) GTOWUP Output 3-phase PWM output for BLDC motor control (positive W phase) GTOWLO Output 3-phase PWM output for BLDC motor control (negative W phase) AGT AGTEE0, AGTEE1 Input External event input enable AGTIO0, AGTIO1 I/O External event input and pulse output AGTO0, AGTO1 Output Pulse output AGTOB0 Output Output compare match B output

R01DS0359EJ0100 Rev.1.00 Page 13 of 105 Mar 31, 2020 RA4W1 Datasheet 1. Overview RTC RTCOUT Output Output pin for 1-Hz/64-Hz clock RTCIC0, RTCIC2 Input Time capture event input pins SCI SCK0,SCK1,SCK4, SCK9 I/O Input/output pins for the clock (clock synchronous mode) RXD0, RXD1, RXD4, RXD9 Input Input pins for received data (async hronous mode/clock synchronous mode) TXD0, TXD1, TXD4, TXD9 Output Output pins for transmitted data (asynchronous mode/clock synchronous mode) CTS0_RTS0, CTS1_RTS1, CTS4_RTS4, CTS9_RTS9 I/O Input/Output pins for controlling t he start of transmission and reception (asynchronous mode/clock synchronous mode), active-low SCL0, SCL1, SCL4, SCL9 I/O Input/output pins for the IIC clock (simple IIC) SDA0, SDA1, SDA4, SDA9 I/O Input/output pins for the IIC data (simple IIC) SCK0, SCK1, SCK4, SCK9 I/O Input/output pins for the clock (simple SPI) MISO0, MISO1, MISO4, MISO9 I/O Input/output pins for slave tr ansmission of data (simple SPI) MOSI0, MOSI1, MOSI4, MOSI9 I/O Input/output pins for master transmission of data (simple SPI) SS0, SS1,SS4,SS9 Input Slave-select i nput pins (simple SPI), active-low IIC SCL0 to SCL1 I/O Input/output pins for clock SDA0 to SDA1 I/O Input/output pins for data SPI RSPCKA, RSPCKB I/O Clock input/output pin MOSIA, MOSIB I/O Inputs or outputs data output from the master MISOA, MISOB I/O Inputs or outputs data output from the slave SSLA0, SSLB0 I/O Input or output pin for slave selection SSLA1, SSLA2, SSLA3, SSLB1, SSLB3 Output Output pin for slave selection CAN CRX0 Input Receive data CTX0 Output Transmit data USBFS VSS_USB Input Ground pins VCC_USB_LDO Input Power supply pin for USB transceiver. Apply the same voltage as VCC_USB. VCC_USB I/O Input: Power supply pin for USB transceiver. USB_DP I/O D+ I/O pin of the USB on-chip tr ansceiver. This pin should be connected to the D+ pin of the USB bus. USB_DM I/O D– I/O pin of the USB on-chip tr ansceiver. This pin should be connected to the D– pin of the USB bus. USB_VBUS Input USB cable connection monitor pin. This pin should be connected to VBUS of the USB bus. The VBUS pin status (connected or disconnected) can be detected when the USB module is operating as a device controller. USB_VBUSEN Output VBUS (5 V) supply enable signal for external power supply chip USB_OVRCURA, USB_OVRCURB Input External overcurrent detection si gnals should be connected to these pins. Analog power supply AVCC0 Input Analog block power supply pin AVSS0 Input Analog block power supply ground pin VREFH0 Input Reference power supply pin VREFL0 Input Reference power supply ground pin ADC14 AN004 to AN006, AN009, AN010, AN017, AN019, AN020 Input Input pins for the analog signals to be processed by the A/D converter ADTRG0 Input Input pins for the external tri gger signals that start the A/D conversion, active-low DAC12 DA0 Output Output pins for the analog si gnals to be processed by the D/A converter Function Signal I/O Description

R01DS0359EJ0100 Rev.1.00 Page 14 of 105 Mar 31, 2020 RA4W1 Datasheet 1. Overview Comparator output VCOUT Output Comparator output pin ACMPLP CMPREF0, CMPREF1 Input Reference voltage input pins CMPIN0, CMPIN1 Input Analog voltage input pins OPAMP AMP2+ Input Analog voltage input pins AMP2- Input Analog voltage input pins AMP2O Output Analog voltage output pins CTSU TS00, TS01, TS03, TS10, TS12, TS13, TS18, TS28, TS30, TS31, TS34 Input Capacitive touch det ection pins (touch pins) TSCAP — Secondary power supply pin for the touch driver I/O ports P004, P010, P011, P014, P015 I/O General-purpose input/output pins P100 to P111 I/O General-purpose input/output pins P200 Input General-purpose input pin P201, P204 to P206, P212, P213 I/O General-purpose input/output pins P214, P215 Input General-purpose input pins P300 I/O General-purpose input/output pins P402, P404, P407, P409, P414 I/O General-purpose input/output pins P501 I/O General-purpose input/output pins P914, P915 I/O General-purpose input/output pins SLCDC VL1, VL2, VL4 I/O Voltage pin for driving the LCD COM0 to COM3 Output Common signal output pins for the LCD controller/driver SEG6, SEG9, SEG11, SEG12, SEG20, SEG23, SEG49, SEG52, SEG53 Output Segment signal output pins for the LCD controller/driver BLE (Bluetooth Low Energy) ANT I/O RF single I/O pin for the RF transceiver Set the impedance of the signal line to 50 Ω. DCLOUT Output RF transceiver power-supply output pin DCLIN_A Input RF transceiver power-supply output connection pin DCLIN_D Input RF transceiver power-supply output connection pin VCC_RF Input RF transceiver power supply pin AVCC_RF Input RF transceiver power supply pin VSS_RF Input RF transceiver ground pin Function Signal I/O Description

R01DS0359EJ0100 Rev.1.00 Page 15 of 105 Mar 31, 2020 RA4W1 Datasheet 1. Overview

1.6 Pin Assignments

Figure 1.3 shows the pin assignments. Figure 1.3 Pin assignment for QFN 56-pin (top view) VSS_RF P100 P101 P103 P104 P105 P106 P107 VSS VCC P111 P110/TDI P109/TDO/SWO P102 VCC_RF P004 AVCC_RF P010/VREFH0 P011/VREFL0 AVSS0 AVCC0 XTAL1_RF XTAL2_RF P014 P015 ANT P501 DCLOUT P915/USB_DM P914/USB_DP VCC_USB VCC_USB_LDO P206 P205 P204 RES P201/MD P200 P300/TCK/SWCLK P407 VSS_USB P108/TMS/SWDIO R7FA4W1AD2CNG 43DCLIN_D P402 DCLIN_A VBATT VCL P215/XCIN P214/XCOUT VSS P213/XTAL P212/EXTAL VCC P414/CLKOUT_RF P409 P404 Note: VSS_RF is assigned as the exposed die pad. For details, refer to Appendix 2, Package Dimensions.

R01DS0359EJ0100 Rev.1.00 Page 16 of 105 Mar 31, 2020 RA4W1 Datasheet 1. Overview

1.7 Pin Lists

Pin number Timers Communication interfaces Analogs HMI QFN56 Power, System, Clock, Debug, CAC, VBATT Interrupt I/O Ports AGT GPT_OPS, POEG GPT RTC USBFS, CAN SCI IIC SPI RF ADC14 DAC12, OPAMP ACMPLP SLCDC CTSU

1 P407 AGTIO0 RTCOUT USB_VBUS CTS4_RTS4

/SS4 SDA0 SSLB3 ADTRG0 SEG11 TS3

2 VSS_USB

3 P915 USB_DM

4 P914 USB_DP

5 VCC_USB

6 VCC_USB

_LDO

7 IRQ0 P206 GTIU USB_VBUS

8 CLKOUT IRQ1 P205 AGTO1 GTIV GTIOC4A USB_OVRC

CTS9_RTS9 /SS9 SCL1 SSLB0 SEG20 TSCAP

9 CACREF P204 AGTO1 GTIW GTIOC4B USB_OVRC

SCK4/SCK9 SCL0 RSPCKB SEG23 TS0

10 RES

11 MD P201

12 NMI P200

13 TCK/

14 TMS/

P108 GTOULO GTIOC0B CTS9_RTS9 /SS9 SSLB0

15 TDO/

P109 GTOVUP GTIOC1A CTX0 SCK1/ TXD9/ MOSI9/ SDA9 MOSIB SEG52 TS10

16 TDI IRQ3 P110 GTOVLO GTIOC1B CRX0 RXD9/

17 IRQ4 P111 GTIOC3A SCK9 RSPCKB TS12

18 VCC

19 VSS

20 KR07 P107 GTIOC8A COM3

21 KR06 P106 GTIOC8B SSLA3 COM2

22 KR05/

P105 GTETRGA GTIOC1A SSLA2 COM1 TS34

23 KR04/

P104 GTETRGB GTIOC1B RXD0/ MISO0/SCL0 SSLA1 COM0 TS13

24 KR03 P103 GTOWUP GTIOC2A CTX0 CTS0_RTS0

/SS0 SSLA0 AN019 CMPREF1 VL4

25 KR02 P102 AGTO0 GTOWLO GTIOC2B CRX0 SCK0 RSPCKA AN020/

26 KR01/

P101 AGTEE0 GTETRGB GTIOC5A TXD0/ MOSI0/ SDA0/ CTS1_RTS1 /SS1 SDA1 MOSIA CMPREF0 VL2

R01DS0359EJ0100 Rev.1.00 Page 17 of 105 Mar 31, 2020 RA4W1 Datasheet 1. Overview

27 KR00/

P100 AGTIO0 GTETRGA GTIOC5B RXD0/ MISO0/ SCL0/ SCK1 SCL1 MISOA CMPIN0 VL1

28 VSS_RF

29 IRQ11 P501 AGTOB0 GTIV GTIOC2B USB_OVRC

30 ANT

31 IRQ7 P015 AN010 TS28

32 P014 AN009 DA0

33 XTAL2_RF

34 XTAL1_RF

35 AVCC0

36 AVSS0

37 VREFL0 IRQ15 P011 AN006 AMP2+ TS31

38 VREFH0 IRQ14 P010 AN005 AMP2- TS30

39 AVCC_RF

40 IRQ3 P004 AN004 AMP2O

41 DCLOUT

42 VCC_RF

43 DCLIN_D

44 VBATWIO

45 DCLIN_A

46 P404 GTIOC3B RTCIC2

47 VBATT

48 VCL

Pin number Timers Communication interfaces Analogs HMI QFN56 Power, System, Clock, Debug, CAC, VBATT Interrupt I/O Ports AGT GPT_OPS, POEG GPT RTC USBFS, CAN SCI IIC SPI RF ADC14 DAC12, OPAMP ACMPLP SLCDC CTSU

R01DS0359EJ0100 Rev.1.00 Page 18 of 105 Mar 31, 2020 RA4W1 Datasheet 1. Overview

49 XCIN P215

50 XCOUT P214

51 VSS

52 XTAL IRQ2 P213 GTETRGA GTIOC0A TXD1/

53 EXTAL IRQ3 P212 AGTEE1 GTETRGB GTIOC0B RXD1/

54 VCC

55 IRQ9 P414 GTIOC0B SSLA1 CLKOUT_

56 IRQ6 P409 GTOWUP GTIOC5A USB_EXICE

N SEG9 Pin number Timers Communication interfaces Analogs HMI QFN56 Power, System, Clock, Debug, CAC, VBATT Interrupt I/O Ports AGT GPT_OPS, POEG GPT RTC USBFS, CAN SCI IIC SPI RF ADC14 DAC12, OPAMP ACMPLP SLCDC CTSU

R01DS0359EJ0100 Rev.1.00 Page 20 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics

2.1 Absolute Maximum Ratings

Note 1. Ports P205, P206, P402, P407 are 5V-tolerant. Note 2. See section 2.2.1, Tj/Ta Definition. Caution: Permanent damage to the MCU may result if absolute maximum ratings are exceeded. To preclude any malfunctions due to noise interference, insert capacitors of high frequency characteristics between the VCC and VSS pins, between the AVCC0 and AVSS0 pins, between VCC_RF and VSS_RF pins, between the AVDD_RF and VSS_RF pins, between the VCC_USB and VSS_USB pins, between the VREFH0 and VREFL0 pins. Place capacitors with values of about 2.2 μF in the case of the VCC_RF pin and about 0.1 μF otherwise as close as possible to every power supply pin, and use the shortest and thickest possible traces for the connections. Also, connect capacitors as stabilization capacitance. Connect the VCL pin to a VSS pin by a 4.7 µF capacitor. The capacitor must be placed close to the pin. Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up might cause malfunction and the abnormal current that passes in the device at this time might cause degradation of internal elements. Table 2.1 Absolute maximum ratings Parameter Symbol Value Unit Power supply voltage VCC –0.5 to +4.0 V Input voltage 5V-tolerant ports* 1 Vin –0.3 to +6.5 V P004, P010, P011, P014, P015 Vin –0.3 to AVCC0 + 0.3 V ANT V in –1.0 to +1.4 V XTAL1_RF, XTAL2_RF V in –0.3 to +1.4 V DCLIN_A, DCLIN_D V in –0.3 to +2.2 V Others V in –0.3 to VCC + 0.3 V Reference power supply voltage VREFH0 –0.3 to +4.0 V VBATT power supply voltage VBATT –0.5 to +4.0 V Analog power supply voltage AVCC0 –0.5 to +4.0 V VCC_RF –0.3 to +4.0 V AVCC_RF –0.3 to +4.0 V USB power supply voltage VCC_USB –0.5 to +4.0 V VCC_USB_LDO –0.5 to +4.0 V Analog input voltage When AN004 to AN006, AN009, AN010 are used V AN –0.3 to AVCC0 + 0.3 V When AN017, AN019, AN020 are used –0.3 to VCC + 0.3 V LCD voltage VL1 voltage V L1 –0.3 to +2.8 V VL2 voltage V L2 –0.3 to +4.0 V VL4 voltage V L4 –0.3 to +4.0 V Operating temperature*2 Topr –40 to +85 °C Storage temperature T stg –55 to +125 °C

R01DS0359EJ0100 Rev.1.00 Page 21 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics Note: Bluetooth power supply voltage VCC_RF *3 1.8 - 3.6 V Note: AVCC_RF * 3 1.8 - 3.6 V Note: VCC_RF - 0 - V Note 1. Use AVCC0 and VCC under the following conditions: AVCC0 and VCC can be set individually within the operating range when VCC ≥ 2.2 V and AVCC0 ≥ 2.2 V AVCC0 = VCC when VCC < 2.2 V or AVCC0 < 2.2 V Note 2. When powering on the VCC and AVCC0 pins, power them on at the same time or the VCC pin first and then the AVCC0 pin. Note 3. Use VCC = VCC_RF = AVCC_RF Table 2.2 Recommended operating conditions Parameter Symbol Value Min Typ Max Unit Power supply voltages VCC *1, *2 When USBFS is not used 1.8 - 3.6 V When USBFS is used USB Regulator Disable VCC_USB - 3.6 V V S S -0 -V USB power supply voltages VCC_USB When USBFS is not used -V C C -V When USBFS is used USB Regulator Disable (Input) 3.0 3.3 3.6 V VCC_USB_LDO When USBFS is not used -V C C -V When USBFS is used - VCC - V VSS_USB - 0 - V VBATT power supply voltage VBATT When the battery backup function is not used -V C C -V When the battery backup function is used 1.8 - 3.6 V Analog power supply voltages AVCC0 *1, *2 1.8 - 3.6 V AVSS0 - 0 - V VREFH0 When used as ADC14 Reference 1.8 - AVCC0 V VREFL0 - 0 - V BLE power supply voltages VCC_RF *3 1.8 - 3.6 V AVCC_RF*3 1.8 - 3.6 VSS_RF - 0 -

R01DS0359EJ0100 Rev.1.00 Page 22 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics

2.2 DC Characteristics

2.2.1 Tj/Ta Definition

Note: Make sure that Tj = T a + θja × total power consumption (W), where total power consumption = (VCC – VOH) × ΣIOH + VOL × ΣIOL + ICCmax × VCC. Note 1. The upper limit of operating te mperature is 85°C. For details, see section 1.3, Part Numbering. If the part number shows the operation temperature at 85°C, then the maximum value of Tj is 105°C.

2.2.2 I/O V IH, VIL

Note 1. P205, P206, P407 (total 3 pins). Note 2. P205, P206, P402, P407 (total 4 pins). Table 2.3 DC characteristics Conditions: Products with operating temperature (Ta) –40 to +85°C Parameter Symbol Typ Max Unit Test conditions Permissible junction temperature Tj - 105* 1 °C High-speed mode Middle-speed mode Low-voltage mode Low-speed mode Subosc-speed mode Table 2.4 I/O V IH, VIL (1) Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LDO = 2.7 to 3.6V, VBATT = 1.8 to 3.6 V, VSS = AVSS0 = 0 V Parameter Symbol Min Typ Max Unit Test conditions Schmitt trigger input voltage IIC*1 VIH VCC × 0.7 - 5.8 V - VIL -- V C C × 0 . 3 ΔVT VCC × 0.05 - - RES, NMI Other peripheral input pins excluding IIC VIH VCC × 0.8 - - VIL - - VCC × 0.2 ΔVT VCC × 0.1 - - Input voltage (except for Schmitt trigger input pin) 5V-tolerant ports* 2 VIH VCC × 0.8 - 5.8 VIL - - VCC × 0.2 P914, P915 V IH VCC_USB × 0.8 - VCC_USB + 0.3 VIL - - VCC_USB × 0.2 P004, P010 V IH AVCC0 × 0.8 - - VIL -- A V C C 0 × 0 . 2 EXTAL Input ports pins except for P004, P010, P914, P915 VIH VCC × 0.8 - - VIL - - VCC × 0.2 When VBATT power supply is selected P402 V IH VBATT × 0.8 - V BATT + 0.3 VIL -- V BATT × 0.2 ΔVT VBATT × 0.05 - -

R01DS0359EJ0100 Rev.1.00 Page 23 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics Note 1. P205, P206, P402, P407 (total 4 pins). Table 2.5 I/O V IH, VIL (2) Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LDO = 1.8 to 2.7 V, VBATT = 1.8 to 3.6 V, VSS = AVSS0 = 0 V Parameter Symbol Min Typ Max Unit Test conditions Schmitt trigger input voltage RES, NMI Peripheral input pins VIH VCC × 0.8 - - V - VIL - - VCC × 0.2 ΔVT VCC × 0.01 - - Input voltage (except for Schmitt trigger input pin) 5V-tolerant ports* 1 VIH VCC × 0.8 - 5.8 VIL - - VCC × 0.2 P914, P915 V IH VCC_USB × 0.8 - VCC_USB + 0.3 VIL - - VCC_USB × 0.2 P004, P010 V IH AVCC0 × 0.8 - - VIL - - AVCC0 × 0.2 EXTAL Input ports pins except for P004, P010 VIH VCC × 0.8 - - VIL - - VCC × 0.2 When VBATT power supply is selected P402, P404 V IH VBATT × 0.8 - V BATT + 0.3 VIL -- V BATT × 0.2 ΔVT VBATT × 0.01 - -

R01DS0359EJ0100 Rev.1.00 Page 24 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics

2.2.3 I/O I OH, IOL

Caution: To protect the reliability of the MCU, the output cu rrent values should not exceed the values in this table. The average output current indicates the average value of current measured during 100 μs. Table 2.6 I/O I OH, IOL Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LDO = 1.8 to 3.6 V Parameter Symbol Min Typ Max Unit Permissible output current (average value per pin) Ports P212, P213 - IOH --– 4 . 0 m A IOL --4 . 0 m A Port P409 Low drive *1 IOH --– 4 . 0 m A IOL --4 . 0 m A Middle drive*2 VCC = 2.7 to 3.0 V IOH --– 8 . 0 m A IOL --8 . 0 m A Middle drive*2 VCC = 3.0 to 3.6 V IOH --– 2 0 . 0 m A IOL --2 0 . 0 m A Ports P100 to P111, P201, P204, P300, P501 (total 16 pins) Low drive*1 IOH --– 4 . 0 m A IOL --4 . 0 m A Middle drive*2 IOH --– 4 . 0 m A IOL --8 . 0 m A Ports P914, P915 - IOH - - –4.0 mA IOL --4 . 0 m A Other output pin*3 Low drive*1 IOH --– 4 . 0 m A IOL --4 . 0 m A Middle drive*2 IOH --– 8 . 0 m A IOL --8 . 0 m A Permissible output current (Max value per pin) Ports P212, P213 - IOH --– 4 . 0 m A IOL --4 . 0 m A Port P409 Low drive *1 IOH --– 4 . 0 m A IOL --4 . 0 m A Middle drive*2 VCC = 2.7 to 3.0 V IOH --– 8 . 0 m A IOL --8 . 0 m A Middle drive*2 VCC = 3.0 to 3.6 V IOH --– 2 0 . 0 m A IOL --2 0 . 0 m A Ports P100 to P111, P201, P204, P300, P501 (total 16 pins) Low drive*1 IOH --– 4 . 0 m A IOL --4 . 0 m A Middle drive*2 IOH --– 4 . 0 m A IOL --8 . 0 m A Ports P914, P915 - IOH - - –4.0 mA IOL --4 . 0 m A Other output pin*3 Low drive*1 IOH --– 4 . 0 m A IOL --4 . 0 m A Middle drive*2 IOH --– 8 . 0 m A IOL --8 . 0 m A Permissible output current (max value total pins) Total of ports P004, P010 ΣIOH (max) --– 3 0 m A ΣIOL (max) --3 0m A Ports P914, P915 ΣIOH (max) - - –4.0 mA ΣIOL (min) --4 . 0 m A Total of all output pin*5 ΣIOH (max) --– 6 0 m A ΣIOL (max) --6 0m A

R01DS0359EJ0100 Rev.1.00 Page 25 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics Note 1. This is the value when low drivi ng ability is selected with the Port Drive Capability bit in PmnPFS register. Note 2. This is the value when middle driv ing ability is selected with the Port Drive Capability bit in PmnPFS register. Note 3. Except for ports P200, P214, P215, which are input ports. Note 4. This is the value when middle driv ing ability for IIC Fast-mode is selected with the Port Drive Capability bit in PmnPFS register. Note 5. For details on the permissible output current used with CTSU, see section 2.11, CTSU Characteristics.

2.2.4 I/O V OH, VOL, and Other Characteristics

Note 1. P100, P101, P204, P205, P206, P407 (total 6 pins). Note 2. This is the value when middle driv ing ability is selected with the Port Drive Capability bit in PmnPFS register. Note 3. Based on characterization data, not tested in production. Note 4. Except for ports P200, P214, P215, which are input ports. Note 5. Except for P212, P213. Note 6. This excludes the CLKOUT_RF pin. Note 1. Except for ports P200, P214, P215, which are input ports. Note 2. Except for P212, P213. Note 3. This excludes the CLKOUT_RF pin. Table 2.7 I/O V OH, VOL (1) Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LDO = 2.7 to 3.6 V Parameter Symbol Min Typ Max Unit Test conditions Output voltage IIC* 1 VOL -- 0 . 4 V I OL = 3.0 mA VOL*2,*5 -- 0 . 6 I OL = 6.0 mA Ports P409*2, *3 VOH VCC – 1.0 - - I OH = –20 mA VCC = 3.3 V VOL -- 1 . 0 I OL = 20 mA VCC = 3.3 V Ports P004, P010 Low drive V OH AVCC0 – 0.5 - - I OH = –1.0 mA VOL -- 0 . 5 I OL = 1.0 mA Middle drive V OH AVCC0 – 0.5 - - I OH = –2.0 mA VOL -- 0 . 5 I OL = 2.0 mA Ports P914, P915 V OH VCC_USB – 0.5 - - I OH = –1.0 mA VOL -- 0 . 5 I OL = 1.0 mA Other output pins *4, *6 Low drive V OH VCC – 0.5 - - I OH = –1.0 mA VOL -- 0 . 5 I OL = 1.0 mA Middle drive*5 VOH VCC – 0.5 - - I OH = –2.0 mA VOL -- 0 . 5 I OL = 2.0 mA Table 2.8 I/O V OH, VOL (2) Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LDO = 1.8 to 2.7 V Parameter Symbol Min Typ Max Unit Test conditions Output voltage Ports P004, P010 Low drive V OH AVCC0 – 0.3 - - V I OH = –0.5 mA VOL -- 0 . 3 I OL = 0.5 mA Middle drive V OH AVCC0 – 0.3 - - I OH = –1.0 mA VOL -- 0 . 3 I OL = 1.0 mA Ports P914, P915 V OH VCC_USB – 0.3 - - I OH = –0.5 mA VOL -- 0 . 3 I OL = 0.5 mA Other output pins *1, *3 Low drive V OH VCC – 0.3 - - I OH = –0.5 mA VOL -- 0 . 3 I OL = 0.5 mA Middle drive*2 VOH VCC – 0.3 - - I OH = –1.0 mA VOL -- 0 . 3 I OL = 1.0 mA

R01DS0359EJ0100 Rev.1.00 Page 26 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics

2.2.5 I/O Pin Output Characte ristics of Low Drive Capacity

Figure 2.2 V OH/VOL and IOH/IOL voltage characteristics at Ta = 25°C when low drive output is selected (reference data) Table 2.9 I/O V OH, VOL (3) Conditions: 3.0V ≤ VCC = AVCC0 = VCC_USB = VCC_USB_LDO = VCC_RF = AVCC_RF ≤ 3.6 V Parameter Symbol Min Max Unit Test conditions Output low CLKOUT_RF V OL -0 . 3 V I OL = 0.5 mA Output high CLKOUT_RF V OH VCC_RF – 0.3 - V I OH = –0.5 mA Table 2.10 I/O other characteristics Conditions: VCC = AVCC0 = 1.8 to 3.6 V Parameter Symbol Min Typ Max Unit Test conditions Input leakage current RES, P200, P214, P215 | I in | - - 1.0 μAV in = 0 V Vin = VCC Three-state leakage current (off state) 5V-tolerant ports | I TSI | - - 1.0 μAV in = 0 V Vin = 5.8 V Other ports (except for ports P200, P214, P215 and 5 V tolerant) -- 1 . 0 V in = 0 V Vin = VCC Input pull-up resistor All ports (except for ports P200, P214, P215, P914, P915) R U 10 20 50 k Ω Vin = 0 V Input capacitance P914, P915, P100 to P103, P111, P200 Cin - - 30 pF V in = 0 V f = 1 MHz Ta = 25°COther input pins - - 15 ‐30 ‐20 ‐10 00 . 511 . 522 . 533 . 54 IOH/IOL[mA] VOH/VOL [V] IOH/IOL vs VOH/VOL VCC = 3.6V VCC = 2.7V VCC = 1.8V VCC = 1.8V VCC = 2.7V VCC = 3.6V

R01DS0359EJ0100 Rev.1.00 Page 28 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics Figure 2.5 V OH/VOL and IOH/IOL temperature characteristics at VCC = 3.6 V when low drive output is selected (reference data)

2.2.6 I/O Pin Output Characteri stics of Middle Drive Capacity

Figure 2.6 V OH/VOL and IOH/IOL voltage characteristics at Ta = 25°C when middle drive output is selected (reference data) ‐30 ‐20 ‐10 00 . 511 . 522 . 533 . 54 IOH/IOL[mA] VOH/VOL [V] IOH/IOL vs VOH/VOL Ta = -40 Ta = 85 Ta = 25 Ta = 85 Ta = -40 Ta = 25 ‐60 ‐40 ‐20 00 . 511 . 522 . 533 . 54 IOH/IOL[mA] VOH/VOL [V] IOH/IOL vs VOH/VOL VCC = 3.6V VCC = 2.7V VCC = 1.8V VCC = 1.8V VCC = 2.7V VCC = 3.6V

R01DS0359EJ0100 Rev.1.00 Page 30 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics Figure 2.9 V OH/VOL and IOH/IOL temperature characteristics at VCC = 3.6 V when middle drive output is selected (reference data)

2.2.7 P409 I/O Pin Output Characte ristics of Middle Drive Capacity

Figure 2.10 V OH/VOL and IOH/IOL voltage characteristics at Ta = 25°C when middle drive output is selected (reference data) ‐80 ‐60 ‐40 ‐20 00 . 511 . 522 . 533 . 54 IOH/IOL[mA] VOH/VOL [V] IOH/IOL vs VOH/VOL Ta = -40 Ta = 85 Ta = 25 Ta = 85 Ta = -40 Ta = 25 ‐100 ‐80 ‐60 ‐40 ‐20 100 0 0.5 1 1.5 2 2.5 3 3.5 4 IOH/IOL[mA] VOH/VOL [V] IOH/IOL vs VOH/VOL VCC = 3.6V VCC = 2.7V VCC = 2.7V VCC = 3.6V

R01DS0359EJ0100 Rev.1.00 Page 32 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics

2.2.8 IIC I/O Pin Out put Characteristics

Figure 2.13 V OH/VOL and IOH/IOL voltage characteristics at Ta = 25°C 100 110 120 0123456 IOL[mA] VOL [V] IOL vs VOL VCC = 2.7V (Low drive) VCC = 3.6V (Low drive) VCC = 3.6V (Middle drive) VCC = 2.7V (Middle drive)

R01DS0359EJ0100 Rev.1.00 Page 33 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics

2.2.9 Operating and Standby Current

Table 2.11 Operating and standby current (1) (1 of 2) Conditions: VCC = AVCC0 = 1.8 to 3.6 V Parameter Symbol Typ* 10 Max Unit Test conditions Supply current*1 High-speed mode Normal mode All peripheral clock disabled, while (1) code executing from flash*5 ICLK = 48 MHz I CC 8.4 - mA *7 ICLK = 32 MHz 5.9 - ICLK = 16 MHz 3.5 - ICLK = 8 MHz 2.3 - All peripheral clock disabled, CoreMark code executing from flash*5 ICLK = 48 MHz 17.9 - ICLK = 32 MHz 12.4 - ICLK = 16 MHz 7.0 - ICLK = 8 MHz 4.3 - All peripheral clock enabled, while (1) code executing from flash ICLK = 48 MHz 21.2 - *9 ICLK = 32 MHz 16.0 - *8 ICLK = 16 MHz 8.8 - ICLK = 8 MHz 5.1 - All peripheral clock enabled, code executing from SRAM ICLK = 48 MHz - 56.0 *9 Sleep mode All peripheral clock disabled*5 ICLK = 48 MHz 3.7 - *7 ICLK = 32 MHz 2.7 - ICLK = 16 MHz 2.0 - ICLK = 8 MHz 1.5 - All peripheral clock enabled*5 ICLK = 48 MHz 16.4 - *9 ICLK = 32 MHz 12.7 - *8 ICLK = 16 MHz 7.2 - ICLK = 8 MHz 4.3 - Increase during BGO operation*6 2.5 - - Middle-speed mode*2 Normal mode All peripheral clock disabled, while (1) code executing from flash ICLK = 12 MHz I CC 2.5 - mA *7 ICLK = 8 MHz 2.1 - ICLK = 1 MHz 1.0 - All peripheral clock disabled, CoreMark code executing from flash ICLK = 12 MHz 5.2 - ICLK = 8 MHz 4.0 - ICLK = 1 MHz 1.3 - All peripheral clock enabled, while (1) code executing from flash ICLK = 12 MHz 6.5 - *8 ICLK = 8 MHz 4.8 - ICLK = 1 MHz 1.6 - All peripheral clock enabled, code executing from SRAM ICLK = 12 MHz - 23.0 Sleep mode All peripheral clock disabled*5 ICLK = 12 MHz 1.4 - *7 ICLK = 8 MHz 1.3 - ICLK = 1 MHz 0.9 - All peripheral clock enabled*5 ICLK = 12 MHz 5.3 - *8 ICLK = 8 MHz 4.0 - ICLK = 1 MHz 1.5 - Increase during BGO operation*6 2.5 - -

R01DS0359EJ0100 Rev.1.00 Page 34 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics Note 1. Supply current values do not incl ude output charge/discharge current from all pins. The values apply when internal pull-up MOSs are in the off state. Note 2. The clock source is HOCO. Note 3. The clock source is MOCO. Note 4. The clock source is the sub-clock oscillator. Note 5. This does not include BGO operation. Note 6. This is the increase for programming or erasure of the flash memory for data storage during program execution. Note 7. FCLK, PCLKA, PCLKB, PCLKC and PCLKD are set to divided by 64. Note 8. FCLK, PCLKA, PCLKB, PCLKC and PCLKD are the same frequency as that of ICLK. Note 9. FCLK and PCLKB are set to divided by 2 and PCLKA, PCLKC and PCLKD are the same frequency as that of ICLK. Note 10. VCC = 3.3 V. Supply current*1 Low-speed mode Normal mode All peripheral clock disabled, while (1) code executing from flash*5 ICLK = 1 MHz I CC 0.4 - mA *7 All peripheral clock disabled, CoreMark code executing from flash*5 ICLK = 1 MHz 0.6 - All peripheral clock enabled, while (1) code executing from flash*5 ICLK = 1 MHz 1.1 - *8 All peripheral clock enabled, code executing from SRAM*5 ICLK = 1 MHz - 2.5 Sleep mode All peripheral clock disabled*5 ICLK = 1 MHz 0.3 - *7 All peripheral clock enabled*5 ICLK = 1 MHz 1.0 - *8 Low-voltage mode Normal mode All peripheral clock disabled, while (1) code executing from flash ICLK = 4 MHz I CC 1.8 - mA *7 All peripheral clock disabled, CoreMark code executing from flash ICLK = 4 MHz 3.0 - All peripheral clock enabled, while (1) code executing from flash ICLK = 4 MHz 3.3 - *8 All peripheral clock enabled, code executing from SRAM ICLK = 4 MHz - 9.0 Sleep mode All peripheral clock disabled*5 ICLK = 4 MHz 1.4 - *7 All peripheral clock enabled ICLK = 4 MHz 2.9 - *8 Subosc- speed mode*4 Normal mode All peripheral clock disabled, while (1) code executing from flash*5 ICLK = 32.768 kHz I CC 9.3 - μA *8 All peripheral clock enabled, while (1) code executing from flash*5 ICLK = 32.768 kHz 17.2 - All peripheral clock enabled, code executing from SRAM*5 ICLK = 32.768 kHz - 106.0 Sleep mode All peripheral clock disabled*5 ICLK = 32.768 kHz 6.0 - All peripheral clock enabled*5 ICLK = 32.768 kHz 14.0 - Table 2.11 Operating and standby current (1) (2 of 2) Conditions: VCC = AVCC0 = 1.8 to 3.6 V Parameter Symbol Typ* 10 Max Unit Test conditions

R01DS0359EJ0100 Rev.1.00 Page 37 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics Figure 2.18 Voltage dependency in subosc-speed mode (reference data) Note 1. Supply current values do not incl ude output charge/discharge current from all pins. The values apply when internal pull-up MOSs are in the off state. Note 2. The IWDT and LVD are not operating. Note 3. Includes the current of sub-oscillat ion circuit or low-speed on-chip oscillator. Note 4. VCC = 3.3 V. Table 2.12 Operating and standby current (2) Conditions: VCC = AVCC0 = 1.8 to 3.6 V Parameter Symbol Typ* 4 Max Unit Test conditions Supply current* Software Standby mode* Ta = 25°C I CC 0.9 5.0 μA PSMCR.PSMC[1:0] = 01b (48-KB SRAM on)Ta = 55°C 1.5 8.1 Ta = 85°C 3.6 22.1 Ta = 25°C 1.0 5.6 PSMCR.PSMC[1:0] = 00b (All SRAM on)Ta = 55°C 1.6 8.4 Ta = 85°C 4.3 26.7 Increment for RTC operation with low-speed on-chip oscillator*3 0.5 -- Increment for RTC operation with sub-clock oscillator*3 0.4 - SOMCR.SODRV[1:0] are 11b (Low power mode 3) 1.2 - SOMCR.SODRV[1:0] are 00b (Normal mode) Note 1. All peripheral operations except any BGO operati on are operating normally. This is the average of the actual measurements of the sample cores during product evaluation. Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the average of the actual measurements for the upper-limit samples during product evaluation. 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 ICC(—A) VCC (V) Ta = 25Ԩ, ICLK = 32kHz *1 Ta = 85Ԩ, ICLK = 32kHz *2 Ta = 85Ԩ, ICLK = 32kHz*2 Ta = 25Ԩ, ICLK = 32kHz*1

R01DS0359EJ0100 Rev.1.00 Page 39 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics Note 1. Supply current values do not incl ude output charge/discharge current from all pins. The values apply when internal pull-up MOSs are in the off state. Figure 2.21 Temperature dependency of RTC operation with VCC off (reference data) Table 2.13 Operating and standby current (3) Conditions: VCC = AVCC0 = 0V, VBATT = 1.8 to 3.6 V, VSS = AVSS0 = 0V Parameter Symbol Typ Max Unit Test conditions Supply current*1 RTC operation when VCC is off T a = 25°C I CC 0.8 - μA VBATT = 2.0 V SOMCR.SORDRV[1:0] = 11b (Low power mode 3)Ta = 55°C 0.9 - Ta = 85°C 1.1 - Ta = 25°C 0.9 - VBATT = 3.3 V SOMCR.SORDRV[1:0] = 11b (Low power mode 3)Ta = 55°C 1.0 - Ta = 85°C 1.2 - Ta = 25°C 1.6 - VBATT = 2.0 V SOMCR.SORDRV[1:0] = 00b (Normal mode)Ta = 55°C 1.8 - Ta = 85°C 2.1 - Ta = 25°C 1.7 - VBATT = 3.3 V SOMCR.SORDRV[1:0] = 00b (Normal mode)Ta = 55°C 1.9 - Ta = 85°C 2.2 - Note 1. Average value of the tested middle sample during product evaluation. Low drive capacity*1 Normal drive capacity*1 -40 -20 0 20 40 60 80 100 120 ICC(—A) Ta (Ԩ) Low drive capacity*1 Normal drive capacity*1

R01DS0359EJ0100 Rev.1.00 Page 40 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics Note 1. The reference power supply current is included in the power supply current value for D/A conversion. Note 2. Current consumed only by the USBFS. Note 3. Includes the current supplied from the pull-up resistor of the USB_DP pin to the pull-down resistor of the host device, in addition to the current consumed by the MCU during the suspended state. Note 4. When VCC = VCC_USB = 3.3 V. Note 5. Current flowing only to the LCD controller. No t including the current that flows through the LCD panel. Note 6. When the MCU is in Software Standby mode or the MSTPCRD.MSTPD16 (ADC140 Module Stop bit) is in the module-stop state. Table 2.14 Operating and standby current (4) Conditions: VCC = AVCC0 = 1.8 to 3.6 V, VREFH0 = 2.7 V to AVCC0 Parameter Symbol Min Typ Max Unit Test conditions Analog power supply current During A/D conversion (at high-speed conversion) I AVCC -- 3 . 0 m A - During A/D conversion (at low power conversion) - - 1.0 mA - During D/A conversion (per channel)* 1 -0 . 4 0 . 8 m A - Waiting for A/D and D/A conversion (all units)*6 -- 1 . 0 μA- Reference power supply current During A/D conversion I REFH0 -- 1 5 0 μA- Waiting for A/D conversion (all units) - - 60 nA - During D/A conversion I REFH -5 0 1 0 0 μA- Waiting for D/A conversion (all units) - - 100 μA- Temperature sensor I TNS -7 5 - μA- Low-Power Analog Comparator operating current Window mode I CMPLP -1 5 - μA- Comparator High-speed mode - 10 - μA- Comparator Low-speed mode - 2 - μA- Comparator Low-speed mode using DAC8 - 820 - μA- Operational Amplifier operating current Low power mode 1 unit operating I AMP -2 . 5 4 . 0 μA- High speed mode 1 unit operating - 140 220 μA- LCD operating current External resistance division method fLCD = fSUB = 128 Hz, 1/3 bias, and 4-time slice ILCD1*5 -0 . 3 4 - μA- USB operating current During USB communication operation under the following settings and conditions:  Host controller operation is set to full-speed mode Bulk OUT transfer (64 bytes) × 1, bulk IN transfer (64 bytes) × 1  Connect peripheral devices via a 1-meter USB cable from the USB port. I USBH*2 - 4.3 (VCC) 0.9 (VCC_USB)*4 -m A - During USB communication operation under the following settings and conditions:  Device controller operation is set to full-speed mode Bulk OUT transfer (64 bytes) × 1, bulk IN transfer (64 bytes) × 1  Connect the host device via a 1-meter USB cable from the USB port. I USBF*2 - 3.6 (VCC) 1.1 (VCC_USB)*4 -m A - During suspended state under the following setting and conditions:  Device controller operation is set to full-speed mode (pull up the USB_DP pin)  Software standby mode  Connect the host device via a 1-meter USB cable from the USB port. I SUSP*3 - 0.35 (VCC) 170 (VCC_USB)*4 - μA-

R01DS0359EJ0100 Rev.1.00 Page 41 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics Table 2.15 Operating and standby current (5) Conditions: VCC = VCC_RF = AVCC_RF = 3.3 V, VSS = VSS_RF = 0 V, Ta = +25°C Parameter Symbol Min Typ Max Unit Test conditions Transmit output power 0 dBm 4 dBm BLE operating current (When DC-DC converter is selected) Transmit mode, 2 Mbps Idd_tx - 4.5 8.7 - mA - Transmit mode, 1 Mbps - - mA - Transmit mode, 500 kbps - - mA - Transmit mode, 125 kbps - - mA - Receive mode, 2 Mbps Prf = -67 dBm Idd_rx - 3.3 3.5 - mA - Receive mode, 1 Mbps Prf = -67 dBm -- m A - Receive mode, 500 kbps Prf = -72 dBm -- m A - Receive mode, 125 kbps Prf = -79 dBm -- m A - Idle mode Idd_idle - 0.5 - mA - Deep sleep mode Idd_slp - 1.5 - μA- Power down mode Idd_down - 0.1 - μA- BLE operating current (When linear regulator is selected) Transmit mode, 2 Mbps Idd_tx - 10.2 18.1 - mA - Transmit mode, 1 Mbps - - mA - Transmit mode, 500 kbps - - mA - Transmit mode, 125 kbps - - mA - Receive mode, 2M bps Prf = -67 dBm Idd_rx - 6.9 - mA - Receive mode, 1 Mbps Prf = -67 dBm -6 . 9 - m A - Receive mode, 500 kbps Prf = -72 dBm -6 . 9 - m A - Receive mode, 125 kbps Prf = -79 dBm -7 . 1 - m A - Idd_idle Idd_idle - 0.7 - mA - Idd_slp Idd_slp - 1.5 - μA- Idd_down Idd_down - 0.1 - μA-

R01DS0359EJ0100 Rev.1.00 Page 42 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics

2.2.10 VCC Rise and Fall Gr adient and Ripple Frequency

Note 1. When OFS1.LVDAS = 0. Note 2. At boot mode, the reset from voltage monitor 0 is disabled regardless of the value of the OFS1.LVDAS bit. Figure 2.22 Ripple waveform Table 2.16 Rise and fall gradient characteristics Conditions: VCC = AVCC0 = 0 to 3.6 V Parameter Symbol Min Typ Max Unit Test conditions Power-on VCC rising gradient Voltage monitor 0 reset disabled at startup (normal startup) SrVCC 0.02 - 2 ms/V - Voltage monitor 0 reset enabled at startup*1 0.02 - - SCI/USB Boot mode*2 0.02 - 2 Table 2.17 Rising and falling gradient and ripple frequency characteristics Conditions: VCC = AVCC0 = VCC_USB = 1.8 to 3.6 V The ripple voltage must meet the allowable ripple frequency fr(VCC) within the range between the VCC upper limit (3.6 V) and lower limit (1.8 V). When VCC change exceeds VCC ±10%, the allowable voltage change rising/falling gradient dt/dVCC must be met. Parameter Symbol Min Typ Max Unit Test conditions Allowable ripple frequency f r (VCC) --1 0 k H z Figure 2.22 Vr (VCC) ≤ VCC × 0.2 --1 M H z Figure 2.22 Vr (VCC) ≤ VCC × 0.08 --1 0 M H z Figure 2.22 Vr (VCC) ≤ VCC × 0.06 Allowable voltage change rising and falling gradient dt/dVCC 1.0 - - ms/V When VCC change exceeds VCC ±10% Vr(VCC)VCC 1/fr(VCC)

R01DS0359EJ0100 Rev.1.00 Page 43 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics

2.3 AC Characteristics

2.3.1 Frequency

Note 1. The lower-limit frequency of FCLK is 1 MHz while pr ogramming or erasing the flash memory. When using FCLK for programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. Note 2. The frequency accuracy of FCLK must be ±3.5% while pr ogramming or erasing the flash memory. Confirm the frequency accuracy of the clock source. Note 3. The lower-limit frequency of PCLKC is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-bit A/D converter is in use. Note 4. See section 9, Clock Generation Ci rcuit in User’s Manual for the relationship of frequencies between ICLK, PCLKA, PCLKB, PCLKC, PCLKD, and FCLK. Note 5. The maximum value of operation frequency does not include the internal oscillator errors. The operation can be guaranteed with the errors of the internal oscillator. For details on the range for guaranteed operation, see Table 2.23, Clock timing. Table 2.18 Operation frequency value in high-speed operating mode Conditions: VCC = AVCC0 = 2.4 to 3.6 V Parameter Symbol Min Typ Max* 5 Unit Operation frequency System clock (ICLK)*4 2.7 to 3.6 V f 0.032768 - 48 MHz 2.4 to 2.7 V 0.032768 - 16 FlashIF clock (FCLK)*1, *2, *4 2.7 to 3.6 V 0.032768 - 32 2.4 to 2.7 V 0.032768 - 16 Peripheral module clock (PCLKA)* 4 2.7 to 3.6 V - - 48 2.4 to 2.7 V - - 16 Peripheral module clock (PCLKB)* 4 2.7 to 3.6 V - - 32 2.4 to 2.7 V - - 16 Peripheral module clock (PCLKC)* 3, *4 2.7 to 3.6 V - - 64 2.4 to 2.7 V - - 16 Peripheral module clock (PCLKD)* 4 2.7 to 3.6 V - - 64 2.4 to 2.7 V - - 16 Table 2.19 Operation frequency value in Middle-speed mode Conditions: VCC = AVCC0 = 1.8 to 3.6 V Parameter Symbol Min Typ Max* 5 Unit Operation frequency System clock (ICLK)*4 2.7 to 3.6 V f 0.032768 - 12 MHz 2.4 to 2.7 V 0.032768 - 12 1.8 to 2.4 V 0.032768 - 8 FlashIF clock (FCLK)* 1, *2, *4 2.7 to 3.6 V 0.032768 - 12 2.4 to 2.7 V 0.032768 - 12 1.8 to 2.4 V 0.032768 - 8 Peripheral module clock (PCLKA)* 4 2.7 to 3.6 V - - 12 2.4 to 2.7 V - - 12 1.8 to 2.4 V - - 8 Peripheral module clock (PCLKB)* 4 2.7 to 3.6 V - - 12 2.4 to 2.7 V - - 12 1.8 to 2.4 V - - 8 Peripheral module clock (PCLKC)* 3, *4 2.7 to 3.6 V - - 12 2.4 to 2.7 V - - 12 1.8 to 2.4 V - - 8 Peripheral module clock (PCLKD)* 4 2.7 to 3.6 V - - 12 2.4 to 2.7 V - - 12 1.8 to 2.4 V - - 8

R01DS0359EJ0100 Rev.1.00 Page 44 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics Note 1. The lower-limit frequency of FCLK is 1 MHz while pr ogramming or erasing the flash memory. When using FCLK for programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. Note 2. The frequency accuracy of FCLK must be ±3.5% while pr ogramming or erasing the flash memory. Confirm the frequency accuracy of the clock source. Note 3. The lower-limit frequency of PCLKC is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-bit A/D converter is in use. Note 4. See section 9, Clock Generation Ci rcuit in User’s Manual for the relationship of frequencies between ICLK, PCLKA, PCLKB, PCLKC, PCLKD, and FCLK. Note 5. The maximum value of operation frequency does not include errors of the internal oscillator. The operation can be guaranteed with the errors of the internal oscillator. For details on the range for guaranteed operation, see Table 2.23, Clock timing. Note 1. The lower-limit frequency of FCLK is 1 MHz while programming or erasing the flash memory. Note 2. The lower-limit frequency of PCLKC is 1 MHz when the A/D converter is in use. Note 3. See section 9, Clock Generation Ci rcuit in User’s Manual for the relationship of frequencies between ICLK, PCLKA, PCLKB, PCLKC, PCLKD, and FCLK. Note 4. The maximum value of operation frequency does not include the internal oscillator errors. The operation can be guaranteed with the errors of the internal oscillator. For details on the range for guaranteed operation, see Table 2.23, Clock timing. Note 1. The lower-limit frequency of FCLK is 1 MHz while pr ogramming or erasing the flash memory. When using FCLK for programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. Note 2. The frequency accuracy of FCLK must be ±3.5% while pr ogramming or erasing the flash memory. Confirm the frequency accuracy of the clock source. Note 3. The lower-limit frequency of PCLKC is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-bit A/D converter is in use. Note 4. See section 9, Clock Generation Ci rcuit in User’s Manual for the relationship of frequencies between ICLK, PCLKA, PCLKB, PCLKC, PCLKD, and FCLK. Note 5. The maximum value of operation frequency does not include errors of the internal oscillator. The operation can be guaranteed with the errors of the internal oscillator. For details on the range for guaranteed operation, see Table 2.23, Clock timing. Table 2.20 Operation frequency value in Low-speed mode Conditions: VCC = AVCC0 = 1.8 to 3.6 V Parameter Symbol Min Typ Max* 4 Unit Operation frequency System clock (ICLK)*3 1.8 to 3.6 V f 0.032768 - 1 MHz FlashIF clock (FCLK)*1, *3 1.8 to 3.6 V 0.032768 - 1 Peripheral module clock (PCLKA)*3 1.8 to 3.6 V - - 1 Peripheral module clock (PCLKB)*3 1.8 to 3.6 V - - 1 Peripheral module clock (PCLKC)*2, *3 1.8 to 3.6 V - - 1 Peripheral module clock (PCLKD)*3 1.8 to 3.6 V - - 1 Table 2.21 Operation frequency value in low-voltage mode Conditions: VCC = AVCC0 = 1.8 to 3.6 V Parameter Symbol Min Typ Max* 5 Unit Operation frequency System clock (ICLK)*4 1.8 to 3.6 V f 0.032768 - 4 MHz FlashIF clock (FCLK)*1, *2, *4 1.8 to 3.6 V 0.032768 - 4 Peripheral module clock (PCLKA)*4 1.8 to 3.6 V - - 4 Peripheral module clock (PCLKB)*4 1.8 to 3.6 V - - 4 Peripheral module clock (PCLKC)*3, *4 1.8 to 3.6 V - - 4 Peripheral module clock (PCLKD)*4 1.8 to 3.6 V - - 4

R01DS0359EJ0100 Rev.1.00 Page 45 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics Note 1. Programming and erasing the flash memory is not possible. Note 2. The 14-bit A/D converter cannot be used. Note 3. See section 9, Clock Generation Ci rcuit in User’s Manual for the relationship of frequencies between ICLK, PCLKA, PCLKB, PCLKC, PCLKD, FCLK, and BCLK.

2.3.2 Clock Timing

Table 2.22 Operation frequency value in Subosc-speed mode Conditions: VCC = AVCC0 = 1.8 to 3.6 V Parameter Symbol Min Typ Max Unit Operation frequency Peripheral module clock (PCLKA)*3 1.8 to 3.6 V - - 37.6832 Peripheral module clock (PCLKB)*3 1.8 to 3.6 V - - 37.6832 Peripheral module clock (PCLKC)*2, *3 1.8 to 3.6 V - - 37.6832 Peripheral module clock (PCLKD)*3 1.8 to 3.6 V - - 37.6832 Table 2.23 Clock timing (1 of 2) Parameter Symbol Min Typ Max Unit Test conditions EXTAL external clock input cycle time t Xcyc 50 - - ns Figure 2.23 EXTAL external clock input high pulse width t XH 20 - - ns EXTAL external clock input low pulse width t XL 20 - - ns EXTAL external clock rising time t Xr --5 n s EXTAL external clock falling time t Xf --5 n s EXTAL external clock input wait time*1 tEXWT 0.3 - - μs- EXTAL external clock input frequency f EXTAL --2 0 M H z 2 . 4 ≤ VCC ≤ 3.6 Main clock oscillator oscillation frequency f MAIN 1- 2 0 M H z 2 . 4 ≤ VCC ≤ 3.6 1- 8 1 . 8 ≤ VCC < 2.4 Main clock oscillation stabilization wait time (crystal)*9 tMAINOSCWT --- * 9 ms LOCO clock oscillation frequency f LOCO 27.8528 32.768 37.6832 kHz - LOCO clock oscillation stabilization time t LOCO --1 0 0 μs Figure 2.24 IWDT-dedicated clock oscillation frequency f ILOCO 12.75 15 17.25 kHz - Bluetooth-dedicated clock oscillation frequency f BLECK -3 2 -M H z Bluetooth-dedicated low-speed on-chip oscillator oscillation frequency fBLELOCO - 32.768 - kHz MOCO clock oscillation frequency f MOCO 6 . 88 9 . 2M H z - MOCO clock oscillation stabilization time t MOCO --1 μs- HOCO clock oscillation frequency f HOCO24 23.64 24 24.36 MHz Ta = –40 to –20°C 1.8 ≤ VCC ≤ 3.6 23.76 24 24.24 Ta = –20 to 85°C 1.8 ≤ VCC ≤ 3.6 fHOCO32 31.52 32 32.48 Ta = –40 to -20°C 1.8 ≤ VCC ≤ 3.6 31.68 32 32.32 Ta = –20 to 85°C 1.8 ≤ VCC ≤ 3.6 fHOCO48*4 47.28 48 48.72 Ta = –40 to –20°C 1.8 ≤ VCC ≤ 3.6 47.52 48 48.48 Ta = –20 to 85°C 1.8 ≤ VCC ≤ 3.6 fHOCO64*5 63.04 64 64.96 Ta = –40 to –20°C 2.4 ≤ VCC ≤ 3.6 63.36 64 64.64 Ta = –20 to 85°C 2.4 ≤ VCC ≤ 3.6

R01DS0359EJ0100 Rev.1.00 Page 48 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics

2.3.3 Reset Timing

Note 1. When OFS1.LVDAS = 0. Note 2. When OFS1.LVDAS = 1. Figure 2.30 Reset input timing at power-on Figure 2.31 Reset input timing (1) Table 2.24 Reset timing Parameter Symbol Min Typ Max Unit Test conditions RES pulse width At power-on t RESWP 3 - - ms Figure 2.30 Other than above t RESW 30 - - μs Figure 2.31 Wait time after RES cancellation (at power-on) LVD0: enable*1 tRESWT - 0.7 -m s Figure 2.30 LVD0: disable*2 - 0.3 - Wait time after RES cancellation (during powered-on state) LVD0: enable*1 tRESWT2 - 0.5 -m s Figure 2.31 LVD0: disable*2 - 0.05 - Internal reset cancellation time (Watchdog timer reset, SRAM parity error reset, SRAM ECC error reset, Bus master MPU error reset, Bus slave MPU error reset, Stack pointer error reset, Software reset) LVD0: enable* 1 tRESWT3 - 0.6 -m s LVD0: disable*2 - 0.15 - VCC RES tRESWP Internal reset tRESWT RES Internal reset tRESWT2 tRESW

R01DS0359EJ0100 Rev.1.00 Page 49 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics

2.3.4 Wakeup Time

Note 1. The division ratio of ICK, BCK, FCK, and PCKx is t he minimum division ratio within the allowable frequency range. The recovery time is determined by the system clock source. Note 2. The Main Clock Oscillator Wait C ontrol Register (MOSCWTCR) is set to 05h. Note 3. The Main Clock Oscillator Wait C ontrol Register (MOSCWTCR) is set to 00h. Note 4. The HOCO Clock Wait Control Register (HOCOWTCR) is set to 05h. Note 5. The HOCO Clock Wait Control Register (HOCOWTCR) is set to 06h. Note 1. The division ratio of ICK, BCK, FCK, and PCKx is t he minimum division ratio within the allowable frequency range. The recovery time is determined by the system clock source. Note 2. The Main Clock Oscillator Wait C ontrol Register (MOSCWTCR) is set to 05h. Note 3. The Main Clock Oscillator Wait C ontrol Register (MOSCWTCR) is set to 00h. Table 2.25 Timing of recovery from low power modes (1) Parameter Symbol Min Typ Max Unit Test conditions Recovery time from Software Standby mode*1 High-speed mode Crystal resonator connected to main clock oscillator System clock source is main clock oscillator (20 MHz) tSBYMC -2 3m s Figure 2.32 System clock source is PLL (48 MHz) with Main clock oscillator*2 tSBYPC -2 3m s External clock input to main clock oscillator System clock source is main clock oscillator (20 MHz) tSBYEX -1 4 2 5 μs System clock source is PLL (48 MHz) with Main clock oscillator tSBYPE -5 3 7 6 μs System clock source is HOCO*4 (HOCO clock is 32 MHz) tSBYHO -4 3 5 2 μs System clock source is HOCO*4 (HOCO clock is 48 MHz) tSBYHO -4 4 5 2 μs System clock source is HOCO*5 (HOCO clock is 64 MHz) tSBYHO -8 2 1 1 0 μs System clock source is MOCO t SBYMO -1 6 2 5 μs Table 2.26 Timing of recovery from low power modes (2) Parameter Symbol Min Typ Max Unit Test conditions Recovery time from Software Standby mode*1 Middle-speed mode Crystal resonator connected to main clock oscillator System clock source is main clock oscillator (12 MHz) tSBYMC -2 3m s Figure 2.32 System clock source is PLL (24 MHz) with main clock oscillator*2 tSBYPC -2 3m s External clock input to main clock oscillator System clock source is main clock oscillator (12 MHz) tSBYEX -2 . 9 1 0 μs System clock source is PLL (24 MHz) with main clock oscillator*3 tSBYPE -4 9 7 6 μs System clock source is HOCO (24 MHz) t SBYHO -3 8 5 0 μs System clock source is MOCO t SBYMO -3 . 5 5 . 5 μs

R01DS0359EJ0100 Rev.1.00 Page 50 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics Note 1. The division ratio of ICK, BCK, FCK, and PCKx is t he minimum division ratio within the allowable frequency range. The recovery time is determined by the system clock source. Note 2. The Main Clock Oscillator Wait C ontrol Register (MOSCWTCR) is set to 05h. Note 3. The Main Clock Oscillator Wait C ontrol Register (MOSCWTCR) is set to 00h. Note 1. The division ratio of ICK, BCK, FCK, and PCKx is t he minimum division ratio within the allowable frequency range. The recovery time is determined by the system clock source. When multiple oscillators are active, the recovery time can be determined by the following expression. Note 2. The Main Clock Oscillator Wait C ontrol Register (MOSCWTCR) is set to 05h. Note 3. The Main Clock Oscillator Wait C ontrol Register (MOSCWTCR) is set to 00h. Note 1. The sub-clock oscillator or LOCO itself continues to oscillate in Software Standby mode during Subosc-speed mode. Table 2.27 Timing of recovery from low power modes (3) Parameter Symbol Min Typ Max Unit Test conditions Recovery time from Software Standby mode*1 Low-speed mode Crystal resonator connected to main clock oscillator System clock source is main clock oscillator (1 MHz) tSBYMC -2 3 m s Figure 2.32 External clock input to main clock oscillator System clock source is main clock oscillator (1 MHz)*3 tSBYEX -2 8 5 0 μs System clock source is MOCO t SBYMO -2 5 3 5 μs Table 2.28 Timing of recovery from low power modes (4) Parameter Symbol Min Typ Max Unit Test conditions Recovery time from Software Standby mode Low-voltage mode Crystal resonator connected to main clock oscillator System clock source is main clock oscillator (4 MHz)*2 tSBYMC -2 3m s Figure 2.32 External clock input to main clock oscillator System clock source is main clock oscillator (4 MHz)*3 tSBYEX - 108 130 μs System clock source is HOCO tSBYHO - 108 130 μs Table 2.29 Timing of recovery from low power modes (5) Parameter Symbol Min Typ Max Unit Test conditions Recovery time from Software Standby mode* Subosc-speed mode System clock source is sub-clock oscillator (32.768 kHz) tSBYSC -0 . 8 5 1m s Figure 2.32 System clock source is LOCO (32.768 kHz) tSBYLO - 0.85 1.2 ms

R01DS0359EJ0100 Rev.1.00 Page 51 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics Figure 2.32 Software Standby mode cancellation timing Table 2.30 Timing of recovery from low power modes (6) Parameter Symbol Min Typ Max Unit Test conditions Recovery time from Software Standby mode to Snooze mode High-speed mode System clock source is HOCO tSNZ -3 6 4 5 μs Figure 2.33 Middle-speed mode System clock source is MOCO tSNZ -1 . 3 3 . 6 μs Low-speed mode System clock source is MOCO tSNZ -1 0 1 3 μs Low-voltage mode System clock source is HOCO tSNZ -8 7 1 1 0 μs Oscillator ICLK IRQ Software Standby mode tSBYSC, tSBYLO Oscillator ICLK IRQ Software Standby mode tSBYMC, tSBYPC, tSBYEX, tSBYPE, tSBYMO, tSBYHO

R01DS0359EJ0100 Rev.1.00 Page 52 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics Figure 2.33 Recovery timing from Software Standby mode to Snooze mode Note 1. W hen SNZCR.SNZDTCEN is set to 1, ICLK is supplied to DTC and SRAM. tSNZ IRQ ICLK (to DTC, SRAM)*1 PCLK ICLK (except DTC, SRAM) Oscillator Software Standby mode Snooze mode

R01DS0359EJ0100 Rev.1.00 Page 53 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics

2.3.5 NMI and IRQ Noise Filter

Note: 200 ns minimum in Software Standby mode. Note: If the clock source is switched, add 4 clock cycles of the switched source. Note 1. t Pcyc indicates the cycle of PCLKB. Note 2. t NMICK indicates the cycle of the NMI digital filter sampling clock. Note 3. t IRQCK indicates the cycle of the IRQi digital filter sampling clock (i = 0 to 15). Figure 2.34 NMI interrupt input timing Figure 2.35 IRQ interrupt input timing Table 2.31 NMI and IRQ noise filter Parameter Symbol Min Typ Max Unit Test conditions NMI pulse width t NMIW 200 -- ns NMI digital filter disabled t Pcyc × 2 ≤ 200 ns tPcyc × 2*1 -- tPcyc × 2 > 200 ns 200 -- NMI digital filter enabled t NMICK × 3 ≤ 200 ns tNMICK × 3.5*2 -- tNMICK × 3 > 200 ns IRQ pulse width t IRQW 200 -- ns IRQ digital filter disabled t Pcyc × 2 ≤ 200 ns tPcyc × 2*1 -- tPcyc × 2 > 200 ns 200 -- IRQ digital filter enabled t IRQCK × 3 ≤ 200 ns tIRQCK × 3.5*3 -- tIRQCK × 3 > 200 ns tNMIW NMI tIRQW IRQ

R01DS0359EJ0100 Rev.1.00 Page 54 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics

2.3.6 I/O Ports, POEG , GPT, AGT, KINT, and ADC14 Trigger Timing

Note 1. Constraints on input cycle: When not switching the source clock: tPcyc × 2 < tACYC should be satisfied. When switching the source clock: tPcyc × 6 < tACYC should be satisfied. Note: t Pcyc: PCLKB cycle, tPDcyc: PCLKD cycle Figure 2.36 I/O ports input timing Figure 2.37 POEG in put trigger timing Figure 2.38 GPT input capture timing Table 2.32 I/O Ports, PO EG, GPT, AGT, KINT, and ADC14 trigger timing Parameter Symbol Min Max Unit Test conditions I/O ports Input data pulse width t PRW 1.5 - t Pcyc Figure 2.36 Input/output data cycle (P004) t POcyc 10 - us POEG POEG input trigger pulse width t POEW 3- t Pcyc Figure 2.37 GPT Input capture pulse width Single edge t GTICW 1.5 - t PDcyc Figure 2.38 Dual edge 2.5 - AGT AGTIO, AGTEE input cycle 2.7 V ≤ VCC ≤ 3.6 V t ACYC*1 250 - ns Figure 2.39 2.4 V ≤ VCC < 2.7 V 500 - ns 1.8 V ≤ VCC < 2.4 V 1000 - ns AGTIO, AGTEE input high level width, low-level width 2.7 V ≤ VCC ≤ 3.6 V t ACKWH, tACKWL 100 - ns 2.4 V ≤ VCC < 2.7 V 200 - ns 1.8 V ≤ VCC < 2.4 V 400 - ns AGTIO, AGTO, AGTOB output cycle 2.7 V ≤ VCC ≤ 3.6 V t ACYC2 62.5 - ns Figure 2.39 2.4 V ≤ VCC < 2.7 V 125 - ns 1.8 V ≤ VCC < 2.4 V 250 - ns ADC14 14-bit A/D converter trigger input pulse width t TRGW 1.5 - t Pcyc Figure 2.40 KINT KRn (n = 00 to 07) pulse width t KR 250 - ns Figure 2.41 Port tPRW POEG input trigger tPOEW Input capture tGTICW

R01DS0359EJ0100 Rev.1.00 Page 55 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics Figure 2.39 AGT I/O timing Figure 2.40 ADC14 trigger input timing Figure 2.41 Key inte rrupt input timing

2.3.7 CAC Timing

Note 1. t PBcyc: PCLKB cycle. Note 2. t cac: CAC count clock source cycle. Table 2.33 CAC timing Parameter Symbol Min Typ Max Unit Test conditions CAC CACREF input pulse width t PBcyc*1 ≤ tcac*2 tCACREF 4.5 × tcac + 3 × tPBcyc*1 --n s - tPBcyc*1 > tcac*2 5 × tcac + 6.5 × tPBcyc*1 --n s tACYC2 AGTIO, AGTEE (input) tACYC tACKWL tACKWH AGTIO, AGTO, AGTOB (output) ADTRG0 tTRGW KR00 to KR07 tKR

R01DS0359EJ0100 Rev.1.00 Page 56 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics

2.3.8 SCI Timing

Note 1. t Pcyc: PCLKA cycle. Figure 2.42 SCK clock input timing Table 2.34 SCI timing (1) Parameter Symbol Min Max Unit *1 Test conditions SCI Input clock cycle Asynchronous t Scyc 4- t Pcyc Figure 2.42 Clock synchronous 6 - Input clock pulse width t SCKW 0.4 0.6 t Scyc Input clock rise time t SCKr -2 0 n s Input clock fall time t SCKf -2 0 n s Output clock cycle Asynchronous t Scyc 6- t Pcyc Clock synchronous 4 - Output clock pulse width t SCKW 0.4 0.6 t Scyc Output clock rise time 1.8 V or above t SCKr -2 0 n s Output clock fall time 1.8 V or above t SCKf -2 0 n s Transmit data delay (master) Clock synchronous 1.8 V or above t TXD -4 0 n s Figure 2.43 Transmit data delay (slave) Clock synchronous

2.7 V or above - 55 ns

2.4 V or above - 60

1.8 V or above - 100

time (master) Clock synchronous

2.7 V or above t

2.4 V or above 55 -

1.8 V or above 90 -

time (slave) Clock synchronous

2.7 V or above 40 - ns

1.8 V or above 45 -

time (master) Clock synchronous t RXH 5- n s Receive data hold time (slave) Clock synchronous t RXH 40 - ns tSCKW tSCKr tSCKf tScyc SCKn (n = 0, 1, 4, 9)

R01DS0359EJ0100 Rev.1.00 Page 57 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics Figure 2.43 SCI input/output timing in clock synchronous mode Table 2.35 SCI timing (2) Parameter Symbol Min Max Unit Test conditions Simple SPI SCK clock cycle output (master) t SPcyc 4 65536 t Pcyc Figure 2.44 SCK clock cycle input (slave) 6 65536 SCK clock high pulse width t SPCKWH 0.4 0.6 t SPcyc SCK clock low pulse width t SPCKWL 0.4 0.6 t SPcyc SCK clock rise and fall time 1.8 V or above t SPCKr, tSPCKf -2 0 n s Data input setup time Master 2.7 V or above t SU 45 - ns Figure 2.45 to Figure 2.482.4 V or above 55 -

1.8 V or above 80 -

Slave 2.7 V or above 40 - Data input hold time Master t H 33.3 - ns Slave 40 - SS input setup time t LEAD 1- t SPcyc SS input hold time t LAG 1- t SPcyc Data output delay Master 1.8 V or above t OD -4 0 n s Slave 2.4 V or above - 65 Master 2.7 V or above t OH –10 - ns

2.4 V or above –20 -

1.8 V or above –30 -

Slave –10 - Data rise and fall time Master 1.8 V or above t Dr, tDf -2 0 n s Slave 1.8 V or above - 20 Slave access time t SA - 10 (PCLKA >

32 MHz),

6 (PCLKA ≤

32 MHz)

tPcyc Figure 2.47 and Figure 2.48 Slave output release time t REL - 10 (PCLKA > 6 (PCLKA ≤ n = 0, 1, 4, 9

R01DS0359EJ0100 Rev.1.00 Page 60 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics Figure 2.48 SCI simple SPI mode timing (slave, CKPH = 0) Note 1. t IICcyc: Clock cycle selected by the SMR.CKS[1:0] bits. Note 2. Cb indicates the to tal capacity of the bus line. Table 2.36 SCI timing (3) Conditions: VCC = 2.7 to 3.6 V Parameter Symbol Min Max Unit Test conditions Simple IIC (Standard mode) SDA input rise time t Sr - 1000 ns Figure 2.49 SDA input fall time t Sf - 300 ns SDA input spike pulse removal time t SP 04 × t IICcyc*1 ns Data input setup time t SDAS 250 - ns Data input hold time t SDAH 0- n s SCL, SDA capacitive load C b*2 - 400 pF Simple IIC (Fast mode) SDA input rise time t Sr - 300 ns Figure 2.49 For all ports use PmnPFS.DSCR of middle drive. SDA input fall time t Sf - 300 ns SDA input spike pulse removal time t SP 04 × t IICcyc*1 ns Data input setup time t SDAS 100 - ns Data input hold time t SDAH 0- n s SCL, SDA capacitive load C b*2 - 400 pF tDr, tDf tSA tOH tLEAD tTD tLAG tH LSB OUT (Last data) DATA MSB OUT MSB IN DATA LSB IN MSB IN LSB OUT tSU tOD tREL MSB OUT SSn input SCKn CKPOL = 1 input SCKn CKPOL = 0 input MISOn output MOSIn input (n = 0, 1, 4, 9)

R01DS0359EJ0100 Rev.1.00 Page 61 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics Figure 2.49 SCI simple IIC mode timing SDAn SCLn VIH VIL P* 1 S* 1 tSftSr tSDAH tSDAS tSP P* 1 Test conditions: VIH = VCC × 0.7, V IL = VCC × 0.3 VOL = 0.6 V, I OL = 6 mA Sr* 1 (n = 0, 1, 4, 9) Note 1. S, P, and Sr indica te the following conditions: S: Start condition P: Stop condition Sr: Restart condition.

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2.3.9 SPI Timing

Table 2.37 SPI timing (1 of 2) Conditions: Middle drive output is selected in the Port Drive Capability in PmnPFS register Parameter Symbol Min Max Unit *1 Test conditions SPI RSPCK clock cycle Master t SPcyc 2*4 4096 t Pcyc Figure 2.50 Slave 6 4096 RSPCK clock high pulse width Master t SPCKWH (tSPcyc – tSPCKr – tSPCKf) / 2 – 3 -n s Slave 3 × t Pcyc - RSPCK clock low pulse width Master t SPCKWL (tSPcyc – tSPCKr – tSPCKf) / 2 – 3 -n s Slave 3 × t Pcyc - RSPCK clock rise and fall time Output 2.7 V or above t SPCKr, tSPCKf -1 0 n s

2.4 V or above - 15

1.8 V or above - 20

Input - 1 µs Data input setup time Master t SU 10 - ns Figure 2.51 to Figure 2.56Slave 2.4 V or above 10 -

1.8 V or above 15 -

Data input hold time Master (RSPCK is PCLKA/2) tHF 0- n s Master (RSPCK is other than above.) tH tPcyc - Slave t H 20 - SSL setup time Master 1.8 V or above t LEAD -30 + N × tSpcyc*2 -n s Slave 6 × t Pcyc - SSL hold time Master t LAG -30 + N × tSpcyc*3 - Slave 6 × t Pcyc - Data output delay Master 2.7 V or above t OD -1 4 n s Figure 2.51 to Figure 2.56 2.4 V or above - 20

1.8 V or above - 25

Slave 2.7 V or above - 50

1.8 V or above - 85

Master t TD tSPcyc + 2 × tPcyc 8 × tSPcyc + 2 × tPcyc ns Slave 6 × t Pcyc - MOSI and MISO rise and fall time Output 2.7 V or above t Dr, tDf -1 0 n s Input - 1 µs

R01DS0359EJ0100 Rev.1.00 Page 63 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics Note 1. t Pcyc: PCLKA cycle. Note 2. N is set as an integer from 1 to 8 by the SPCKD register. Note 3. N is set as an integer from 1 to 8 by the SSLND register. Note 4. The upper limit of RSPCK is 16 MHz. Figure 2.50 SPI clock timing SPI SSL rise and fall time Output 2.7 V or above t SSLr, tSSLf -1 0 n s Figure 2.51 to Figure 2.56 2.4 V or above - 15 Input - 1 µs Slave access time 2.4 V or above t SA -2 × t Pcyc + 100 ns Figure 2.55 and Figure 2.561.8 V or above - 2 × t Pcyc + 140 Slave output release time 2.4 V or above t REL -2 × t Pcyc + 100 ns

1.8 V or above - 2 × t Pcyc + 140

Table 2.37 SPI timing (2 of 2) Conditions: Middle drive output is selected in the Port Drive Capability in PmnPFS register Parameter Symbol Min Max Unit *1 Test conditions RSPCKn master select output RSPCKn slave select input tSPCKWH VOH VOH VOL VOL VOH VOH tSPCKWL tSPCKr tSPCKf VOL tSPcyc tSPCKWH VIH VIH VIL VIL VIH VIH tSPCKWL tSPCKr tSPCKf VIL tSPcyc VOH = 0.7 × VCC, V OL = 0.3 × VCC, V IH = 0.7 × VCC, V IL = 0.3 × VCC n = A or B

R01DS0359EJ0100 Rev.1.00 Page 67 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics

2.3.10 IIC Timing

Note: t IICcyc: IIC internal reference clock (IICφ) cycle, tPcyc: PCLKB cycle Note 1. The value in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1. Table 2.38 IIC timing Conditions: VCC = 2.7 to 3.6 V Parameter Symbol Min* 1 Max Unit Test conditions IIC (standard mode, SMBus) SCL input cycle time t SCL 6 (12) × tIICcyc + 1300 - ns Figure 2.57 SCL input high pulse width t SCLH 3 (6) × tIICcyc + 300 - ns SCL input low pulse width t SCLL 3 (6) × tIICcyc + 300 - ns SCL, SDA input rise time t Sr - 1000 ns SCL, SDA input fall time t Sf - 300 ns SCL, SDA input spike pulse removal time tSP 0 1 (4) × t IICcyc ns SDA input bus free time (When wakeup function is disabled) tBUF 3 (6) × tIICcyc + 300 - ns SDA input bus free time (When wakeup function is enabled) tBUF 3 (6) × tIICcyc + 4 × tPcyc + 300 -n s START condition input hold time (When wakeup function is disabled) tSTAH tIICcyc + 300 - ns START condition input hold time (When wakeup function is enabled) tSTAH 1 (5) × tIICcyc + tPcyc + 300 -n s Repeated START condition input setup time tSTAS 1000 - ns STOP condition input setup time t STOS 1000 - ns Data input setup time t SDAS tIICcyc + 50 - ns Data input hold time t SDAH 0- n s SCL, SDA capacitive load C b - 400 pF IIC (Fast mode) SCL input cycle time t SCL 6 (12) × tIICcyc + 600 - ns Figure 2.57 For all ports, use PmnPFS.DS CR of middle drive. SCL input high pulse width t SCLH 3 (6) × tIICcyc + 300 - ns SCL input low pulse width t SCLL 3 (6) × tIICcyc + 300 - ns SCL, SDA input rise time t Sr - 300 ns SCL, SDA input fall time t Sf - 300 ns SCL, SDA input spike pulse removal time tSP 0 1 (4) × t IICcyc ns SDA input bus free time (When wakeup function is disabled) tBUF 3 (6) × tIICcyc + 300 - ns SDA input bus free time (When wakeup function is enabled) tBUF 3 (6) × tIICcyc + 4 × tPcyc + 300 -n s START condition input hold time (When wakeup function is disabled) tSTAH tIICcyc + 300 - ns START condition input hold time (When wakeup function is enabled) tSTAH 1(5) × tIICcyc + tPcyc + 300 -n s Repeated START condition input setup time tSTAS 300 - ns STOP condition input setup time t STOS 300 - ns Data input setup time t SDAS tIICcyc + 50 - ns Data input hold time t SDAH 0- n s SCL, SDA capacitive load C b - 400 pF

R01DS0359EJ0100 Rev.1.00 Page 68 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics Figure 2.57 I 2C bus interface input/output timing

2.3.11 CLKOUT Timing

Note 1. When the EXTAL external clock input or an oscillator is used with division by 1 (the CKOCR.CKOSEL[2:0] bits are 011b and the CKOCR.CKODIV[2:0] bits are 000b) to output from CLKOUT, the above should be satisfied with an input duty cycle of 45 to 55%. Note 2. When the MOCO is selected as the clock output source (t he CKOCR.CKOSEL[2:0] bits are 001b), set the clock output division ratio selection to be divided by 2 (the CKOCR.CKODIV[2:0] bits are 001b). Note 3. The voltage for VCC_RF when CLKOUT_RF pin is to be used is between 3.0 V and 3.6 V. Table 2.39 CLKOUT timing Parameter Symbol Min Max Unit* 1 Test conditions CLKOUT CLKOUT pin output cycle* 1 VCC = 2.7 V or above t Ccyc 62.5 - ns Figure 2.58 VCC = 1.8 V or above 125 - CLKOUT pin high pulse width*2 VCC = 2.7 V or above t CH 15 - ns VCC = 1.8 V or above 30 - CLKOUT pin low pulse width*2 VCC = 2.7 V or above t CL 15 - ns VCC = 1.8 V or above 30 - CLKOUT pin output rise time VCC = 2.7 V or above t Cr -1 2 n s VCC = 1.8 V or above - 25 CLKOUT pin output fall time VCC = 2.7 V or above t Cf -1 2 n s VCC = 1.8 V or above - 25 CLKOUT_RF*3 CLKOUT_RF pin output cycle t CRFcyc 250 - ns Figure 2.59 CLKOUT_RF pin high pulse width t CRFH 100 - ns CLKOUT_RF pin low pulse width t CRFL 100 - ns CLKOUT_RF pin output rise time t CRFr -5n s CLKOUT_RF pin output fall time t CRFf -5n s SDA0, SDA1 SCL0, SCL1 VIH VIL tSTAH tSCLH tSCLL P*1 S*1 tSf tSr tSCL tSDAH tSDAS tSTAS tSP tSTOS P*1 tBUF Sr*1 Note 1. S, P, and Sr indica te the following conditions. S: Start condition P: Stop condition Sr: Restart condition

R01DS0359EJ0100 Rev.1.00 Page 70 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics

2.4 USB Characteristics

2.4.1 USBFS Timing

Figure 2.60 USB_DP and USB_DM output timing Table 2.40 USB characteristics Conditions: VCC = VCC_USB = 3.0 to 3.6 V, Ta = -20 to +85°C (USBCLKSEL = 1) Parameter Symbol Min Max Unit Test conditions Input characteristics Input high level voltage V IH 2.0 - V - Input low level voltage V IL -0 . 8 V - Differential input sensitivity V DI 0.2 - V | USB_DP - USB_DM | Differential common mode range VCM 0.8 2.5 V - Output characteristics Output high level voltage V OH 2.8 VCC_USB V I OH = –200 μA Output low level voltage V OL 0.0 0.3 V I OL = 2 mA Cross-over voltage V CRS 1.3 2.0 V Figure 2.60, Figure 2.61, Figure 2.62Rise time FS t r 42 0 n s LS 75 300 Fall time FS t f 42 0 n s LS 75 300 Rise/fall time ratio FS t r/tf 90 111.11 % LS 80 125 Output resistance Z DRV 28 44 Ω (Adjusting the resistance of external elements is not required.) VBUS characteristics VBUS input voltage V IH VCC × 0.8 - V - VIL -V C C × 0 . 2 V - Pull-up, pull-down Pull-down resistor R PD 14.25 24.80 k Ω - Pull-up resistor R PUI 0.9 1.575 k Ω During idle state RPUA 1.425 3.09 k Ω During reception Battery Charging Specification Ver 1.2 D + sink current I DP_SINK 25 175 μA- D – sink current I DM_SINK 25 175 μA- DCD source current I DP_SRC 71 3 μA- Data detection voltage V DAT_REF 0.25 0.4 V - D + source voltage V DP_SRC 0.5 0.7 V Output current = 250 μA D – source voltage V DM_SRC 0.5 0.7 V Output current = 250 μA USB_DP, USB_DM tftr 90% 10%10% 90%VCRS

R01DS0359EJ0100 Rev.1.00 Page 72 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics

2.5 ADC14 Characteristics

Figure 2.63 AVCC0 to VREFH0 voltage range Table 2.41 A/D conversion characteristics (1) in high-speed A/D conversion mode (1 of 2) Conditions: VCC = AVCC0 = 2.7 to 3.6 V, VREFH0 = 2.7 to 3.6 V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions Frequency 1 - 48 MHz - Analog input capacitance*2 Cs - - 8 (reference data) pF High-precision channel - - 9 (reference data) pF Normal-precision channel Analog input resistance Rs - - 2.5 (reference data) k Ω High-precision channel - - 6.7 (reference data) k Ω Normal-precision channel Analog input voltage range Ain 0 - VREFH0 V - 12-bit mode Resolution - - 12 Bit - Conversion time* (Operation at PCLKC = 48 MHz) Permissible signal source impedance Max. = 0.3 kΩ 0.94 - - μs High-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 0Dh 1.50 - - μs Normal-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 28h Offset error - ±0.5 ±4.5 LSB High-precision channel ±6.0 LSB Other than above Full-scale error - ±0.75 ±4.5 LSB High-precision channel ±6.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±1.25 ±5.0 LSB High-precision channel ±8.0 LSB Other than above DNL differential nonlinearity error - ±1.0 - LSB - INL integral nonlinearity error - ±1.0 ±3.0 LSB - 14-bit mode Resolution - - 14 Bit - VREFH0 4.0 3.5 3.0 2.5 2.0 A/D Conversion Characteristics (1) ADCSR.ADHSC = 0 3.6 2.7 2.4 2.4 2.7 3.6 AVCC0 VREFH0 4.0 3.5 3.0 2.5 2.0 ADCSR.ADHSC = 1 3.6 2.7 2.4 2.4 2.7 3.6 AVCC0 1.8 1.8 A/D Conversion Characteristics (2) A/D Conversion Characteristics (3) A/D Conversion Characteristics (4) A/D Conversion Characteristics (5)

R01DS0359EJ0100 Rev.1.00 Page 73 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics Note: The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Note 2. Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics. Conversion time*1 (Operation at PCLKC = 48 MHz) Permissible signal source impedance Max. = 0.3 kΩ 1.06 - - μs High-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 0Dh 1.63 - - μs Normal-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 28h Offset error - ±2.0 ±18 LSB High-precision channel ±24.0 LSB Other than above Full-scale error - ±3.0 ±18 LSB High-precision channel ±24.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±5.0 ±20 LSB High-precision channel ±32.0 LSB Other than above DNL differential nonlinearity error - ±4.0 - LSB - INL integral nonlinearity error - ±4.0 ±12.0 LSB - Table 2.42 A/D conversion characteristics (2) in high-speed A/D conversion mode (1 of 2) Conditions: VCC = AVCC0 = 2.4 to 3.6 V, VREFH0 = 2.4 to 3.6 V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions Frequency 1 - 32 MHz - Analog input capacitance*2 Cs - - 8 (reference data) pF High-precision channel - - 9 (reference data) pF Normal-precision channel Analog input resistance Rs - - 2.5 (reference data) k Ω High-precision channel - - 6.7 (reference data) k Ω Normal-precision channel Analog input voltage range Ain 0 - VREFH0 V - 12-bit mode R e s o l u t i o n --1 2 B i t - Conversion time* (Operation at PCLKC = 32 MHz) Permissible signal source impedance Max. = 1.3 kΩ 1.41 - - μs High-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 0Dh 2.25 - - μs Normal-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 28h Offset error - ±0.5 ±4.5 LSB High-precision channel ±6.0 LSB Other than above Full-scale error - ±0.75 ±4.5 LSB High-precision channel ±6.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±1.25 ±5.0 LSB High-precision channel ±8.0 LSB Other than above DNL differential nonlinearity error - ±1.0 - LSB - INL integral nonlinearity error - ±1.0 ±3.0 LSB - 14-bit mode Table 2.41 A/D conversion characteristics (1) in high-speed A/D conversion mode (2 of 2) Conditions: VCC = AVCC0 = 2.7 to 3.6 V, VREFH0 = 2.7 to 3.6 V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions

R01DS0359EJ0100 Rev.1.00 Page 74 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics Note: The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Note 2. Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics. R e s o l u t i o n --1 4 B i t - Conversion time*1 (Operation at PCLKC = 32 MHz) Permissible signal source impedance Max. = 1.3 kΩ 1.59 - - μs High-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 0Dh 2.44 - - μs Normal-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 28h Offset error - ±2.0 ±18 LSB High-precision channel ±24.0 LSB Other than above Full-scale error - ±3.0 ±18 LSB High-precision channel ±24.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±5.0 ±20 LSB High-precision channel ±32.0 LSB Other than above DNL differential nonlinearity error - ±4.0 - LSB - INL integral nonlinearity error - ±4.0 ±12.0 LSB - Table 2.43 A/D conversion characteristics (3) in low power A/D conversion mode (1 of 2) Conditions: VCC = AVCC0 = 2.7 to 3.6 V, VREFH0 = 2.7 to 3.6 V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions Frequency 1 - 24 MHz - Analog input capacitance*2 Cs - - 8 (reference data) pF High-precision channel - - 9 (reference data) pF Normal-precision channel Analog input resistance Rs - - 2.5 (reference data) k Ω High-precision channel - - 6.7 (reference data) k Ω Normal-precision channel Analog input voltage range Ain 0 - VREFH0 V - 12-bit mode Resolution - - 12 Bit - Conversion time* (Operation at PCLKC = 24 MHz) Permissible signal source impedance Max. = 1.1 kΩ 2.25 - - μs High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 3.38 - - μs Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h Offset error - ±0.5 ±4.5 LSB High-precision channel ±6.0 LSB Other than above Full-scale error - ±0.75 ±4.5 LSB High-precision channel ±6.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±1.25 ±5.0 LSB High-precision channel ±8.0 LSB Other than above DNL differential nonlinearity error - ±1.0 - LSB - INL integral nonlinearity error - ±1.0 ±3.0 LSB - Table 2.42 A/D conversion characteristics (2) in high-speed A/D conversion mode (2 of 2) Conditions: VCC = AVCC0 = 2.4 to 3.6 V, VREFH0 = 2.4 to 3.6 V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions

R01DS0359EJ0100 Rev.1.00 Page 75 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics Note: The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Note 2. Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics. 14-bit mode Resolution - - 14 Bit - Conversion time* (Operation at PCLKC = 24 MHz) Permissible signal source impedance Max. = 1.1 kΩ 2.50 - - μs High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 3.63 - - μs Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h Offset error - ±2.0 ±18 LSB High-precision channel ±24.0 LSB Other than above Full-scale error - ±3.0 ±18 LSB High-precision channel ±24.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±5.0 ±20 LSB High-precision channel ±32.0 LSB Other than above DNL differential nonlinearity error - ±4.0 - LSB - INL integral nonlinearity error - ±4.0 ±12.0 LSB - Table 2.44 A/D conversion characteristics (4) in low power A/D conversion mode (1 of 2) Conditions: VCC = AVCC0 = 2.4 to 3.6 V, VREFH0 = 2.4 to 3.6 V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions Frequency 1 - 16 MHz - Analog input capacitance*2 Cs - - 8 (reference data) pF High-precision channel - - 9 (reference data) pF Normal-precision channel Analog input resistance Rs - - 2.5 (reference data) k Ω High-precision channel - - 6.7 (reference data) k Ω Normal-precision channel Analog input voltage range Ain 0 - VREFH0 V - 12-bit mode Resolution - - 12 Bit - Conversion time* (Operation at PCLKC = 16 MHz) Permissible signal source impedance Max. = 2.2 kΩ 3.38 - - μs High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 5.06 - - μs Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h Offset error - ±0.5 ±4.5 LSB High-precision channel ±6.0 LSB Other than above Full-scale error - ±0.75 ±4.5 LSB High-precision channel ±6.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±1.25 ±5.0 LSB High-precision channel ±8.0 LSB Other than above DNL differential nonlinearity error - ±1.0 - LSB - Table 2.43 A/D conversion characteristics (3) in low power A/D conversion mode (2 of 2) Conditions: VCC = AVCC0 = 2.7 to 3.6 V, VREFH0 = 2.7 to 3.6 V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions

R01DS0359EJ0100 Rev.1.00 Page 76 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics Note: The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Note 2. Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics. INL integral nonlinearity error - ±1.0 ±3.0 LSB - 14-bit mode Resolution - - 14 Bit - Conversion time* (Operation at PCLKC = 16 MHz) Permissible signal source impedance Max. = 2.2 kΩ 3.75 - - μs High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 5.44 - - μs Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h Offset error - ±2.0 ±18 LSB High-precision channel ±24.0 LSB Other than above Full-scale error - ±3.0 ±18 LSB High-precision channel ±24.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±5.0 ±20 LSB High-precision channel ±32.0 LSB Other than above DNL differential nonlinearity error - ±4.0 - LSB - INL integral nonlinearity error - ±4.0 ±12.0 LSB - Table 2.45 A/D conversion characteristics (5) in low power A/D conversion mode (1 of 2) Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions Frequency 1 - 8 MHz - Analog input capacitance*2 Cs - - 8 (reference data) pF High-precision channel - - 9 (reference data) pF Normal-precision channel Analog input resistance Rs - - 3.8 (reference data) k Ω High-precision channel - - 8.2 (reference data) k Ω Normal-precision channel Analog input voltage range Ain 0 - VREFH0 V - 12-bit mode Resolution - - 12 Bit - Conversion time* (Operation at PCLKC = 8 MHz) Permissible signal source impedance Max. = 5 kΩ 6.75 - - μs High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 10.13 - - μs Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h Offset error - ±1.0 ±7.5 LSB High-precision channel ±10.0 LSB Other than above Full-scale error - ±1.5 ±7.5 LSB High-precision channel ±10.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±3.0 ±8.0 LSB High-precision channel ±12.0 LSB Other than above Table 2.44 A/D conversion characteristics (4) in low power A/D conversion mode (2 of 2) Conditions: VCC = AVCC0 = 2.4 to 3.6 V, VREFH0 = 2.4 to 3.6 V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions

R01DS0359EJ0100 Rev.1.00 Page 77 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics Note: The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Note 2. Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics. Figure 2.64 Equivalent circuit for analog input DNL differential nonlinearity error - ±1.0 - LSB - INL integral nonlinearity error - ±1.0 ±3.0 LSB - 14-bit mode Resolution - - 14 Bit - Conversion time* (Operation at PCLKC = 8 MHz) Permissible signal source impedance Max. = 5 kΩ 7.50 - - μs High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 10.88 - - μs Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h Offset error - ±4.0 ±30.0 LSB High-precision channel ±40.0 LSB Other than above Full-scale error - ±6.0 ±30.0 LSB High-precision channel ±40.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±12.0 ±32.0 LSB High-precision channel ±48.0 LSB Other than above DNL differential nonlinearity error - ±4.0 - LSB - INL integral nonlinearity error - ±4.0 ±12.0 LSB - Table 2.46 14-bit A/D converter channel classification (1 of 2) Classification Channel Conditions Remarks High-precision channel AN004 to AN006, AN009, AN010 AVCC0 = 1.8 to 3.6 V Pins AN004 to AN006, AN009 and AN010 cannot be used as general I/ O, IRQ3 inputs, and TS transmission, when the A/D converter is in useNormal-precision channel AN017, AN019, AN020 Internal reference voltage input channel Internal reference voltage AVCC0 = 2.0 to 3.6 V - Table 2.45 A/D conversion characteristics (5) in low power A/D conversion mode (2 of 2) Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions Rs Cin Rs Cin Cs ADC MCU Analog input ANn Analog input ANn Sensor

R01DS0359EJ0100 Rev.1.00 Page 78 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics Note 1. The internal reference voltage cannot be selected for input channels when AVCC0 < 2.0 V. Note 2. The 14-bit A/D internal reference voltage indicates the vo ltage when the internal reference voltage is input to the 14-bit A/D converter. Note 3. This is a parameter for ADC14 when the internal reference voltage is used as a high-potential reference voltage. Note 4. This is a parameter for ADC14 when the internal refe rence voltage is selected for an analog input channel in ADC14. Temperature sensor input channel Temperature sensor output AVCC0 = 2.0 to 3.6 V - Table 2.47 A/D internal reference voltage characteristics Conditions: VCC = AVCC0 = VREFH0 = 2.0 to 3.6 V*1 Parameter Min Typ Max Unit Test conditions Internal reference voltage input channel*2 1.36 1.43 1.50 V - Frequency*3 1- 2M H z - Sampling time*4 5 . 0 --µ s - Table 2.46 14-bit A/D converter channel classification (2 of 2) Classification Channel Conditions Remarks

R01DS0359EJ0100 Rev.1.00 Page 79 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics Figure 2.65 Illustration of 14-bit A/D converter characteristic terms Absolute accuracy Absolute accuracy is the difference between output code based on the theoretical A/D conversion characteristics, and the actual A/D conversion result. When measuring absolute accuracy, the voltage at the midpoint of the width of analog input voltage (1-LSB width), which can meet the expectation of outputting an equal code based on the theoretical A/D conversion characteristics, is used as the analog input voltage. For example, if 12-bit resolution is used and the reference voltage VREFH0 = 3.072 V , then 1-LSB width becomes 0.75 mV, and 0 mV , 0.75 mV , and 1.5 mV are used as the analog input voltages. If analog input voltage is 6 mV , an absolute accuracy of ±5 LSB means that the actual A/D conversion result is in the range of 003h to 00Dh, though an output code of 008h can be expected from the theoretical A/D conversion characteristics. Integral nonlinearity error (INL) Integral nonlinearity error is the maximum deviation between the ideal line when the measured offset and full-scale errors are zeroed, and the actual output code. Differential nonlinearity error (DNL) Differential nonlinearity error is the difference between 1-LSB width based on the ideal A/D conversion characteristics and the width of the actually output code. Offset error Offset error is the difference between the transition point of the ideal first output code and the actual first output code. Full-scale error Full-scale error is the difference between the transition point of the ideal last output code and the actual last output code. Integral nonlinearity error (INL) Actual A/D conversion characteristic Ideal A/D conversion characteristic Analog input voltage Offset error Absolute accuracy Differential nonlinearity error (DNL) Full-scale error 3FFFh 0000h Ideal line of actual A/D conversion characteristic 1-LSB width for ideal A/D conversion characteristic Differential nonlinearity error (DNL) 1-LSB width for ideal A/D conversion characteristic VREFH0 (full-scale) A/D converter output code

R01DS0359EJ0100 Rev.1.00 Page 80 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics

2.6 DAC12 Characteristics

Table 2.48 D/A conversion characteristics (1) Conditions: VCC = AVCC0 = 1.8 to 3.6 V Reference voltage = AVCC0 or AVSS0 selected Parameter Min Typ Max Unit Test conditions Resolution - - 12 bit - Resistive load 30 - - k Ω - Capacitive load - - 50 pF - Output voltage range 0.35 - AVCC0 – 0.47 V - DNL differential nonlinearity error - ±0.5 ±2.0 LSB - INL integral nonlinearity error - ±2.0 ±8.0 LSB - Offset error - - ±30 mV - Full-scale error - - ±30 mV - Output impedance - 5 - Ω - Conversion time - - 30 μs- Table 2.49 D/A conversion characteristics (2) Conditions: VCC = AVCC0 = 1.8 to 3.6 V Reference voltage = internal reference voltage selected Parameter Min Typ Max Unit Test conditions Resolution - - 12 bit - Internal reference voltage (Vbgr) 1.36 1.43 1.50 V - Resistive load 30 - - k Ω - Capacitive load - - 50 pF - Output voltage range 0.35 - Vbgr V - DNL differential nonlinearity error - ±2.0 ±16.0 LSB - INL integral nonlinearity error - ±8.0 ±16.0 LSB - Offset error - - ±30 mV - Output impedance - 5 - Ω - Conversion time - - 30 μs-

R01DS0359EJ0100 Rev.1.00 Page 81 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics Figure 2.66 Illustration of D/A converter characteristic terms Integral nonlinearity error (INL) Integral nonlinearity error is the maximum deviation between the ideal output voltage based on the ideal conversion characteristic when the measured offset and full-scale errors are zeroed, and the actual output voltage. Differential nonlinearity error (DNL) Differential nonlinearity error is the difference between 1-LSB voltage width based on the ideal D/A conversion characteristics and the width of the actual output voltage. Offset error Offset error is the difference between the highest actual output voltage that falls below the lower output limit and the ideal output voltage based on the input code. Full-scale error Full-scale error is the difference between the lowest actual output voltage that exceeds the upper output limit and the ideal output voltage based on the input code. 000h D/A converter input code FFFh Output analog voltage Upper output limit Lower output limit Offset error Ideal output voltage 1-LSB width for ideal D/A conversion characteristic Differential nonlinearity error (DNL) Actual D/A conversion characteristic Integral nonlinearity error (INL) Full-scale error Gain error Offset error Ideal output voltage Note 1. Ideal D/A conversion output voltage that is adjus ted so that offset and full scale errors are zeroed.

R01DS0359EJ0100 Rev.1.00 Page 82 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics

2.7 TSN Characteristics

2.8 OSC Stop Detect Characteristics

Figure 2.67 Oscillation stop detection timing Table 2.50 TSN characteristics Conditions: VCC = AVCC0 = 2.0 to 3.6 V Parameter Symbol Min Typ Max Unit Test conditions Relative accuracy - - ±1.5 - °C 2.4 V or above - - ±2.0 - °C Below 2.4 V Temperature slope - - –3.65 - mV/°C - Output voltage (at 25°C) - - 1.05 - V VCC = 3.3 V Temperature sensor start time t START --5 μs- Sampling time - 5 - - μs- Table 2.51 Oscillation stop detection circuit characteristics Parameter Symbol Min Typ Max Unit Test conditions Detection time t dr --1 m s Figure 2.67 tdr Main clock OSTDSR.OSTDF MOCO clock ICLK PLL clock tdr Main clock OSTDSR.OSTDF MOCO clock ICLK When the main clock is selected When the PLL clock is selected

R01DS0359EJ0100 Rev.1.00 Page 83 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics

2.9 POR and LVD Characteristics

Note 1. These characteristics apply when noise is not superimposed on the power supply. Note 2. # in the symbol Vdet0_# denotes the value of the OFS1.VDSEL1[2:0] bits. Note 3. # in the symbol Vdet1_# denotes the value of the LVDLVLR.LVD1LVL[4:0] bits. Table 2.52 Power-on reset circuit and voltag e detection circuit characteristics (1) Parameter Symbol Min Typ Max Unit Test conditions Voltage detection level*1 Power-on reset (POR) V POR 1.27 1.42 1.57 V Figure 2.68, Figure 2.69 Voltage detection circuit (LVD0)*2 Vdet0_1 2.68 2.85 2.96 V Figure 2.70 At falling edge VCCV det0_2 2.38 2.53 2.64 Vdet0_3 1.78 1.90 2.02 Voltage detection circuit (LVD1)*3 Vdet1_4 2.98 3.10 3.22 V Figure 2.71 At falling edge VCCV det1_5 2.89 3.00 3.11 Vdet1_6 2.79 2.90 3.01 Vdet1_7 2.68 2.79 2.90 Vdet1_8 2.58 2.68 2.78 Vdet1_9 2.48 2.58 2.68 Vdet1_A 2.38 2.48 2.58 Vdet1_B 2.10 2.20 2.30 Vdet1_C 1.84 1.96 2.05 Vdet1_D 1.74 1.86 1.95 Vdet1_E 1.63 1.75 1.84 Vdet1_F 1.60 1.65 1.73

R01DS0359EJ0100 Rev.1.00 Page 86 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics Figure 2.71 Voltage detection circuit timing (V det1) tVOFF Vdet1VCC tdettdet tLVD1 td(E-A) LVCMPCR.LVD1E LVD1 Comparator output LVD1CR0.CMPE LVD1SR.MON Internal reset signal (active-low) When LVD1CR0.RN = 0 When LVD1CR0.RN = 1 VLVH tLVD1

R01DS0359EJ0100 Rev.1.00 Page 87 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics

2.10 VBATT Characteristics

Note: The VCC-off period for starting power supply switching indica tes the period in which VCC is below the minimum value of the voltage level for switching to battery backup (VDETBATT). Figure 2.72 Power supply switching and LVD0 reset timing Table 2.54 Battery backup function characteristics Conditions: VCC = AVCC0 = 1.8V to 3.6V, VBATT = 1.6 to 3.6 V Parameter Symbol Min Typ Max Unit Test conditions Voltage level for switching to battery backup (falling) V DETBATT 1.99 2.09 2.19 V Figure 2.72, Figure 2.73Hysteresis width for switching to battery back up V VBATTH - 100 - mV VCC-off period for starting power supply switching t VOFFBATT 300 - - μs- Voltage detection level VBATT_Power-on reset (VBATT_POR) VVBATPOR 1.30 1.40 1.50 V Figure 2.72, Figure 2.73 Wait time after VBATT_POR reset time cancellation t VBATPOR - - 3 mS - Level for detection of voltage drop on the VBATT pin (falling) VBTLVDLVL[1:0] = 10b V DETBATLVD 2.11 2.2 2.29 V Figure 2.74 VBTLVDLVL[1:0] = 11b 1.92 2 2.08 V Hysteresis width for VBATT pin LVD V VBATLVDTH - 50 - mV VBATT pin LVD operation stabilization time t d_vbat - - 300 μs Figure 2.74 VBATT pin LVD response delay time t det_vbat - - 350 μs Allowable voltage change rising/falling gradient dt/dVCC 1.0 - - ms/V - VCC voltage level for access to the VBATT backup registers V _BKBATT 1.8 - - V - VDETBATT VVBATH VCC supplied VBATT VCC VVBATPOR VBATT supplied VCC supplied Backup power area Internal reset signal (active-low) tLVD0 Vdet0 VLVH tdettdet VPOR

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2.11 CTSU Characteristics

Table 2.55 VBATT-I/O characteristics Parameter Symbol Min Typ Max Unit Test conditions VBATWIOn I/O output characteristics (n = 0) VCC > VDETBATT VCC = 2.7 to 3.6 V V OH VCC - 0.5 - - I OH = -100 µA VOL -- 0 . 5 I OL = 100 µA VCC = VDETBATT to 2.7 V V OH VCC - 0.3 - - I OH = -50 µA VOL -- 0 . 3 I OL = 50 µA VCC < VDETBATT VBATT = 2.7 to 3.6 V V OH VBATT - 0.5 - - I OH = -100 µA VOL -- 0 . 5 I OL = 100 µA VBATT = 1.8 to 2.7 V V OH VBATT - 0.3 - - I OH = -50 µA VOL -- 0 . 3 I OL = 50 µA Table 2.56 CTSU characteristics Conditions: VCC = AVCC0 = 1.8 to 3.6 V Parameter Symbol Min Typ Max Unit Test conditions External capacitance connected to TSCAP pin C tscap 91 0 1 1 n F - TS pin capacitive load C base --5 0 p F - Permissible output high current ΣIoH - - -24 mA When the mutual capacitance method is applied

R01DS0359EJ0100 Rev.1.00 Page 90 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics

2.12 Segment LCD Contro ller Characteristics

2.12.1 Resistance Division Method

[Static Display Mode] [1/2 Bias Method, 1/4 Bias Method] [1/3 Bias Method]

2.13 Comparator Characteristics

Note 1. When 8-bit DAC output is used as the reference voltage, the offset voltage increases up to 2.5 x VCC/256. Note 2. In window mode, be sure to satisfy the following condition: IVREF1 - IVREF0 > 0.2 V. Table 2.57 Resistance division method LCD characteristics (1) Conditions: VL4 ≤ VCC ≤ 3.6 V Parameter Symbol Min Typ Max Unit Test conditions LCD drive voltage V L4 2.0 - VCC V - Table 2.58 Resistance division method LCD characteristics (2) Conditions: VL4 ≤ VCC ≤ 3.6 V Parameter Symbol Min Typ Max Unit Test conditions LCD drive voltage V L4 2.7 - VCC V - Table 2.59 Resistance division method LCD characteristics (3) Conditions: VL4 ≤ VCC ≤ 3.6 V Parameter Symbol Min Typ Max Unit Test conditions LCD drive voltage V L4 2.5 - VCC V - Table 2.60 ACMPLP characteristics Conditions: VCC = 1.8 to 3.6 V Parameter Symbol Min Typ Max Unit Test conditions Reference voltage range Standard mode IVREFn (n=0,1) VREF 0 - VCC–1.4 V - Window mode*2 IVREF1 VREFH 1.4 - VCC V - IVREF0 VREFL 0 - VCC–1.4 V - Input voltage range VI 0 - VCC V - Internal reference voltage - 1.36 1.44 1.50 V - Output delay High-speed mode Td - - 1.2 μsV C C = 3 . 0 Slew rate of input signal > 50 mV/μsLow-speed mode - - 5 μs Window mode - - 2 μs Offset voltage*1 High-speed mode - - - 50 mV - Low-speed mode - - - 40 mV - Window mode - - - 60 mV - Operation stabilization wait time T cmp 100 - - μs-

R01DS0359EJ0100 Rev.1.00 Page 91 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics

2.14 OPAMP Characteristics

Note 1. When the operational amplifier referenc e current circuit is activated in advance. Table 2.61 OPAMP characteristics Conditions: VCC = AVCC0 = 1.8 to 3.6 V (AVCC0 = VCC when VCC < 2.0 V) Parameter Symbol Conditions Min Typ Max Unit Common mode input range Vicm1 Low-power mode 0.2 - AVCC0 – 0.5 V Vicm2 High-speed mode 0.3 - AVCC0 – 0.6 V Output voltage range Vo1 Low-power mode 0.1 - AVCC0 – 0.1 V Vo2 High-speed mode 0.1 - AVCC0 – 0.1 V Input offset voltage Vioff 3 σ –10 - 10 mV Open gain Av 60 120 - dB Gain-bandwidth (GB) product GBW1 Low-power mode - 0.04 - MHz GBW2 High-speed mode - 1.7 - MHz Phase margin PM CL = 20 pF 50 - - deg Gain margin GM CL = 20 pF 10 - - dB Equivalent input noise Vnoise1 f = 1 kHz Low-power mode - 230 - nV/ √Hz Vnoise2 f = 10 kHz - 200 - nV/ √Hz Vnoise3 f = 1 kHz High-speed mode - 90 - nV/ √Hz Vnoise4 f = 2 kHz - 70 - nV/ √Hz Power supply reduction ratio PSRR - 90 - dB Common mode signal reduction ratio CMRR - 90 - dB Stabilization wait time Tstd1 CL = 20 pF Only operational amplifier is activated * Low-power mode 650 - - μs Tstd2 High-speed mode 13 - - μs Tstd3 CL = 20 pF Operational amplifier and reference current circuit are activated simultaneously Low-power mode 650 - - μs Tstd4 High-speed mode 13 - - μs Settling time Tset1 CL = 20 pF Low-power mode - - 750 μs Tset2 High-speed mode - - 13 μs Slew rate Tslew1 CL = 20 pF Low-power mode - 0.02 - V/ μs Tslew2 High-speed mode - 1.1 - V/ μs Load current Iload1 Low power mode –100 - 100 μA Iload2 High-speed mode –100 - 100 μA Load capacitance CL --2 0 p F

R01DS0359EJ0100 Rev.1.00 Page 92 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics

2.15 Flash Memory Characteristics

2.15.1 Code Flash Memory Characteristics

Note 1. The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times (n = 1,000), erasing can be done n times for each block. For instance, when 8-byte programming is performed 256 times for different addresses in 2-KB blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However, programming the same address for several times as one erasure is not enabled (overwriting is prohibited). Note 2. Characteristic when usin g the flash memory programmer and the self-programming library provided by Renesas Electronics. Note 3. This result is obtained from reliability testing. Note: Does not include the time until each oper ation of the flash memory is started after instructions are executed by software. Note: The lower-limit frequency of FCLK is 1 MHz during progra mming or erasing the flash memory. When using FCLK at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. Note: The frequency accuracy of FCLK must be ±3.5%. Confirm the frequency accuracy of the clock source. Table 2.62 Code flash characteristics (1) Parameter Symbol Min Typ Max Unit Test conditions Reprogramming/erasure cycle*1 NPEC 1000 - - Times - Data hold time After 1000 times of N PEC tDRP 20*2, *3 --Y e a r T a = +85°C Table 2.63 Code flash characteristics (2) High-speed operating mode Conditions: VCC = 2.7 to 3.6 V Parameter Symbol FCLK = 1 MHz FCLK = 32 MHz UnitMin Typ Max Min Typ Max Programming time 8-byte t P8 - 116 998 - 54 506 μs Erasure time 2-KB t E2K - 9.03 287 - 5.67 222 ms Blank check time 8-byte t BC8 - - 56.8 - - 16.6 μs 2-KB t BC2K - - 1899 - - 140 μs Erase suspended time t SED - - 22.5 - - 10.7 μs Startup area switching setting time t SAS - 21.7 585 - 12.1 447 ms Access window time t AWS - 21.7 585 - 12.1 447 ms OCD/serial programmer ID setting time t OSIS - 21.7 585 - 12.1 447 ms Flash memory mode transition wait time 1 tDIS 2- - 2- - μs Flash memory mode transition wait time 2 tMS 5- - 5- - μs

R01DS0359EJ0100 Rev.1.00 Page 93 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics Note: Does not include the time until each oper ation of the flash memory is started after instructions are executed by software. Note: The lower-limit frequency of FCLK is 1 MHz during progra mming or erasing the flash memory. When using FCLK at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. Note: The frequency accuracy of FCLK must be ±3.5%. Confirm the frequency accuracy of the clock source.

2.15.2 Data Flash Memory Characteristics

Note 1. The reprogram/erase cycle is the number of erasure for ea ch block. When the reprogram/erase cycle is n times (n = 100,000), erasing can be performed n times for each block. For instance, when 1-byte programming is performed 1,000 times for different addresses in 1-byte blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However, programming the same address for several times as one erasure is not enabled. (overwriting is prohibited). Note 2. Characteristics when using the flas h memory programmer and the self-programming library provided by Renesas Electronics. Note 3. These results are obtained from reliability testing. Note: Does not include the time until each oper ation of the flash memory is started after instructions are executed by software. Note: The lower-limit frequency of FCLK is 1 MHz during progra mming or erasing the flash memory. When using FCLK at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. Note: The frequency accuracy of FCLK must be ±3.5%. Confirm the frequency accuracy of the clock source. Table 2.64 Code flash characteristics (3) Middle-speed operating mode Conditions: VCC = 1.8 to 3.6 V, Ta = –40 to +85°C Parameter Symbol FCLK = 1 MHz FCLK = 8 MHz UnitMin Typ Max Min Typ Max Programming time 8-byte t P8 - 157 1411 - 101 966 μs Erasure time 2-KB t E2K - 9.10 289 - 6.10 228 ms Blank check time 8-byte t BC8 - - 87.7 - - 52.5 μs 2-KB t BC2K - - 1930 - - 414 μs Erase suspended time t SED - - 32.7 - - 21.6 μs Startup area switching setting time t SAS - 22.5 592 - 14.0 464 ms Access window time t AWS - 22.5 592 - 14.0 464 ms OCD/serial programmer ID setting time t OSIS - 22.5 592 - 14.0 464 ms Flash memory mode transition wait time 1 t DIS 2 --2 -- μs Flash memory mode transition wait time 2 t MS 720 - - 720 - - ns Table 2.65 Data flash characteristics (1) Parameter Symbol Min Typ Max Unit Test conditions Reprogramming/erasure cycle*1 NDPEC 100000 1000000 - Times - Data hold time After 10000 times of N DPEC tDDRP 20*2, *3 - - Year Ta = +85°C After 100000 times of NDPEC 5*2, *3 - - Year After 1000000 times of NDPEC -1 * 2, *3 - Year Ta = +25°C Table 2.66 Data flash characteristics (2) High-speed operating mode Conditions: VCC = 2.7 to 3.6 V Parameter Symbol FCLK = 4 MHz FCLK = 32 MHz UnitMin Typ Max Min Typ Max Programming time 1-byte t DP1 - 52.4 463 - 42.1 387 μs Erasure time 1-KB t DE1K - 8.98 286 - 6.42 237 ms Blank check time 1-byte t DBC1 - - 24.3 - - 16.6 μs 1-KB t DBC1K - - 1872 - - 512 μs Suspended time during erasing t DSED - - 13.0 - - 10.7 μs Data flash STOP recovery time t DSTOP 5- - 5- - μs

R01DS0359EJ0100 Rev.1.00 Page 94 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics Note: Does not include the time until each oper ation of the flash memory is started after instructions are executed by software. Note: The lower-limit frequency of FCLK is 1 MHz during progra mming or erasing the flash memory. When using FCLK at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. Note: The frequency accuracy of FCLK must be ±3.5%. Confirm the frequency accuracy of the clock source.

2.16 Joint Test Action Group (JTAG)

Table 2.67 Data flash characteristics (3) Middle-speed operating mode Conditions: VCC = 1.8 to 3.6 V, Ta = –40 to +85°C Parameter Symbol FCLK = 4 MHz FCLK = 8 MHz UnitMin Typ Max Min Typ Max Programming time 1-byte t DP1 - 94.7 886 - 89.3 849 μs Erasure time 1-KB t DE1K - 9.59 299 - 8.29 273 ms Blank check time 1-byte t DBC1 - - 56.2 - - 52.5 μs 1-KB t DBC1K - - 2.17 - - 1.51 ms Suspended time during erasing t DSED - - 23.0 - - 21.7 μs Data flash STOP recovery time t DSTOP 720 - - 720 - - ns Table 2.68 JTAG (debug) characteristics (1) Conditions: VCC = 2.4 to 3.6 V Parameter Symbol Min Typ Max Unit Test conditions TCK clock cycle time t TCKcyc 80 - - ns Figure 2.75 TCK clock high pulse width t TCKH 35 - - ns TCK clock low pulse width t TCKL 35 - - ns TCK clock rise time t TCKr -- 5 n s TCK clock fall time t TCKf -- 5 n s TMS setup time t TMSS 16 - - ns Figure 2.76 TMS hold time t TMSH 16 - - ns TDI setup time t TDIS 16 - - ns TDI hold time t TDIH 16 - - ns TDO data delay time t TDOD - - 70 ns Table 2.69 JTAG (debug) characteristics (2) Conditions: VCC = 1.8 to 2.4 V Parameter Symbol Min Typ Max Unit Test conditions TCK clock cycle time t TCKcyc 250 - - ns Figure 2.75 TCK clock high pulse width t TCKH 120 - - ns TCK clock low pulse width t TCKL 120 - - ns TCK clock rise time t TCKr -- 5 n s TCK clock fall time t TCKf -- 5 n s TMS setup time t TMSS 50 - - ns Figure 2.76 TMS hold time t TMSH 50 - - ns TDI setup time t TDIS 50 - - ns TDI hold time t TDIH 50 - - ns TDO data delay time t TDOD - - 150 ns

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2.16.1 Serial Wire Debug (SWD)

Figure 2.77 SWD SWCLK timing Table 2.70 SWD characteristics (1) Conditions: VCC = 2.4 to 3.6 V Parameter Symbol Min Typ Max Unit Test conditions SWCLK clock cycle time t SWCKcyc 80 - - ns Figure 2.77 SWCLK clock high pulse width t SWCKH 35 - - ns SWCLK clock low pulse width t SWCKL 35 - - ns SWCLK clock rise time t SWCKr -- 5 n s SWCLK clock fall time t SWCKf -- 5 n s SWDIO setup time t SWDS 16 - - ns Figure 2.78 SWDIO hold time t SWDH 16 - - ns SWDIO data delay time t SWDD 2 - 70 ns Table 2.71 SWD characteristics (2) Conditions: VCC = 1.8 to 2.4 V Parameter Symbol Min Typ Max Unit Test conditions SWCLK clock cycle time t SWCKcyc 250 - - ns Figure 2.77 SWCLK clock high pulse width t SWCKH 120 - - ns SWCLK clock low pulse width t SWCKL 120 - - ns SWCLK clock rise time t SWCKr -- 5 n s SWCLK clock fall time t SWCKf -- 5 n s SWDIO setup time t SWDS 50 - - ns Figure 2.78 SWDIO hold time t SWDH 50 - - ns SWDIO data delay time t SWDD 2 - 150 ns SWCLK tSWCKcyc tSWCKH tSWCKf tSWCKr tSWCKL

R01DS0359EJ0100 Rev.1.00 Page 97 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics Figure 2.78 SWD input/output timing

2.17 BLE Characteristics

2.17.1 Transmission Characteristics

Note: The characteristics are based on pi ns and functions other than those for the BLE interface not being in use. Note 1. This does not take frequency errors due to manufacturing i rregularities, drift with temperature, or deterioration of the crystal over time into account. Table 2.72 Transmission Characteristics Conditions: VCC = VCC_RF = AVCC_RF = 3.3 V, VSS = VSS_RF = 0 V, Ta = +25°C Parameter Symbol Min Typ Max Unit Test conditions Range of frequency RF CF 2402 - 2480 MHz Data rate RF DATA_2M -2 - M b p s RFDATA_1M -1 - M b p s RFDATA_500k - 500 - kbps RFDATA_125k - 125 - kbps Maximum transmitted output power RFPOWER - 0 2 dBm 0 dBm output mode - 4 6 dBm 4 dBm output mode Output frequency error RF TXFERR –10 - 10 ppm * 1 SWDIO (Output) SWDIO (Output) SWDIO (Output) tSWDD tSWDD tSWDD SWCLK SWDIO (Input) tSWDS tSWDH

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2.17.2 Reception Charac teristics (2 Mbps)

Note: The characteristics are based on pi ns and functions other than those for the BLE interface not being in use. Note 1. PER ≤ 30.8%, and a 37-byte payload Note 2. Allowable range of difference between the center frequen cy for the RF input signals and the carrier frequency generated within the chip

2.17.3 Reception Charac teristics (1 Mbps)

Note: The characteristics are based on pi ns and functions other than those for the BLE interface not being in use. Note 1. PER ≤ 30.8%, and a 37-byte payload Note 2. Allowable range of difference between the center frequen cy for the RF input signals and the carrier frequency generated within the chip Table 2.73 Reception Characteristics Conditions:VCC = VCC_RF = AVCC_RF = 3.3 V, VSS = VSS_RF = 0 V, Ta = +25°C Item Symbol Min. Typ. Max. Unit Test Conditions Input frequency RF RXFIN_2M 2402 — 2480 MHz Maximum input level RF LEVL_2M –10 4 — dBm * 1 Receiver sensitivity RF STY_2M —– 9 2 —d B m * 1 Secondary emission strength RF RXSP_2M — –72 –57 dBm 30 MHz to 1 GHz — –54 –47 dBm 1 GHz to 12 GHz Co-channel rejection ratio RF CCR_2M — –8 — dB Prf = –67 dBm* 1 Adjacent channel rejection ratio RFADCR_2M — 2 — dB Prf = –67 dBm* 1 ±2 MHz —3 5—d B ± 4 M H z —3 9—d B ± 6 M H z Blocking RF BLK_2M — –1 — dBm Prf = –67 dBm* 1 30 MHz to 2000 MHz — –25 — dBm 2000 MHz to 2399 MHz — –21 — dBm 2484 MHz to 3000 MHz — –10 — dBm > 3000 MHz Allowable frequency deviation*2 RFRXFER_2M –120 — 120 ppm * 1 RSSI accuracy RF RSSIS_2M — ±4 — dB –70 dBm ≤ Prf ≤ –10 dBm Table 2.74 Reception Characteristics Conditions:VCC = VCC_RF = AVCC_RF = 3.3 V, VSS = VSS_RF = 0 V, Ta = +25°C Item Symbol Min. Typ. Max. Unit Test Conditions Input frequency RF RXFIN_1M 2402 — 2480 MHz Maximum input level RF LEVL_1M –10 4 — dBm * 1 Receiver sensitivity RF STY_1M — –95 — dBm * 1 Secondary emission strength RF RXSP_1M — –72 –57 dBm 30MHz to 1GHz — –54 –47 dBm 1GHz to 12GHz Co-channel rejection ratio RF CCR_1M — –7 — dB Prf = –67dBm* 1 Adjacent channel rejection ratio RF ADCR_1M — –1 — dB Prf = –67dBm* 1 ±1MHz —3 4—d B ± 2 M H z —3 5—d B ± 3 M H z Blocking RF BLK_1M — 0 — dBm Prf = –67dBm* 1 30MHz to 2000MHz — –24 — dBm 2000MHz to 2399MHz — –20 — dBm 2484MHz to 3000MHz — –4 — dBm > 3000MHz Allowable frequency deviation*

2 RFRXFER_1M –120 — 120 ppm * 1

RSSI accuracy RF RSSIS_1M — ±4 — dB –70dBm ≤ Prf ≤ –10dBm

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2.17.4 Reception Characteristics (500 kbps)

Note: The characteristics are based on pi ns and functions other than those for the BLE interface not being in use. Note 1. PER ≤ 30.8%, and a 37-byte payload Note 2. Allowable range of difference between the center frequen cy for the RF input signals and the carrier frequency generated within the chip

2.17.5 Reception Characteristics (125 kbps)

Note: The characteristics are based on pi ns and functions other than those for the BLE interface not being in use. Note 1. PER ≤ 30.8%, and a 37-byte payload Note 2. Allowable range of difference between the center frequen cy for the RF input signals and the carrier frequency generated within the chip Table 2.75 Reception Characteristics Conditions:VCC = VCC_RF = AVCC_RF = 3.3 V, VSS = VSS_RF = 0 V, Ta = +25°C Item Symbol Min. Typ. Max. Unit Test Conditions Input frequency RF RXFIN_500k 2402 — 2480 MHz Maximum input level RF LEVL_500k –10 4 — dBm * 1 Receiver sensitivity RF STY_500k — –100 — dBm * 1 Secondary emission strength RF RXSP_500k — –72 –57 dBm 30MHz to 1GHz — –54 –47 dBm 1GHz to 12GHz Co-channel rejection ratio RF CCR_500k — –4 — dB Prf = –72dBm* 1 Adjacent channel rejection ratio RF ADCR_500k — 6 — dB Prf = –72dBm* 1 ±1MHz —3 6—d B ± 2 M H z —4 2—d B ± 3 M H z Blocking RF BLK_500k — 0 — dBm Prf = –72dBm* 1 30MHz to 2000MHz — –23 — dBm 2000MHz to 2399MHz — –20 — dBm 2484MHz to 3000MHz — –7 — dBm > 3000MHz Allowable frequency deviation*

2 RFRXFER_500k –120 — 120 ppm * 1

RSSI accuracy RF RSSIS_500k — ±4 — dB –70dBm ≤ Prf ≤ –10dBm Table 2.76 Reception Characteristics Conditions:VCC = VCC_RF = AVCC_RF = 3.3 V, VSS = VSS_RF = 0 V, Ta = +25°C Item Symbol Min. Typ. Max. Unit Test Conditions Input frequency RF RXFIN_125k 2402 — 2480 MHz Maximum input level RF LEVL_125k –10 4 — dBm * 1 Receiver sensitivity RF STY_125k — –105 — dBm * 1 Secondary emission strength RF RXSP_125k — –72 –57 dBm 30 MHz to 1 GHz — –54 –47 dBm 1 GHz to 12 GHz Co-channel rejection ratio RF CCR_125k — –2 — dB Prf = –79 dBm* 1 Adjacent channel rejection ratio RF ADCR_125k — 12 — dB Prf = –79 dBm* 1 ±1 MHz —3 9—d B ± 2 M H z —4 5—d B ± 3 M H z Blocking RF BLK_125k — 0 — dBm Prf = –79 dBm* 1 30 MHz to 2000 MHz — –23 — dBm 2000 MHz to 2399 MHz — –20 — dBm 2484 MHz to 3000 MHz — –1 — dBm > 3000MHz Allowable frequency deviation*

2 RFRXFER_125k –120 — 120 ppm * 1

RSSI accuracy RF RSSIS_125k —± 4—d B T a = +25°C, –70 dBm ≤ Prf ≤ –10 dBm

R01DS0359EJ0100 Rev.1.00 Page 100 of 105 Mar 31, 2020 RA4W1 Datasheet Appendix 1. Package Dimensions Appendix 1. Package Dimensions Figure 1.1 QFN 56-pin

R01DS0359EJ0100 Rev.1.00 Page 101 of 105 Mar 31, 2020 RA4W1 Datasheet Appendix 1. Package Dimensions Figure 1.2 Land Pattern

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1.00 Mar 31, 2020 First release

Revision History

Publication Date: Rev.1.00 Mar 31, 2020 Published by: Renesas Electronics Corporation Colophon

1. Precaution against Electro static Discharge (ESD) A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices. 2. Processing at power-on The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the level at which resetting is specified. 3. Input of signal during power-off state Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Follow the guideline for input signal during power- off state as described in your product documentation. 4. Handling of unused pins Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. 5. Clock signals After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable. 6. V oltage application waveform at input pin Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V IL (Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.). 7. Prohibition of access to reserved addresses Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these addresses as the correct operation of the LSI is not guaranteed. 8. Differences between products Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system-evaluation test for the given product. http://www.renesas.com Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics Corporation TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan Renesas Electronics America Inc. 1001 Murphy Ranch Road, Milpitas, CA 95035, U.S.A. Renesas Electronics Canada Limited

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Renesas Electronics disclaims any and all liability for any losses or damages incurred by you or third parties arising from such alteration, modification, copying or reverse engineering. 5. Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. Th e intended applications for each Renesas Electronics product depends on the product’s quality grade, as indicated below. "Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; industrial robots; etc. "High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale comm unication equipment; key financial terminal systems; safety control equipment; etc. Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data she et or other Renesas Electronics document, Renesas Electronics products are not intended or authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artific ial life support devices or systems; surgical implantations; etc.), or may cause serious property damage (space system; undersea repeaters; nuclear power control systems; aircraft control systems; key plant s ystems; military equipment; etc.). Renesas Electronics disclaims any and all liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics produc t that is inconsistent with any Renesas Electronics data sheet, user’s manual or other Renesas Electronics document. 6. When using Renesas Electronics products, refer to the latest product information (data sheets, user’s manuals, application no tes, “General Notes for Handling and Using Semiconductor Devices” in the reliability handbook, etc.), and ensure that usage conditions are within the ranges specified by Renesas Electronics with respe ct to maximum ratings, operating power supply voltage range, heat dissipation characteristics, installation, etc. Renesas Electronics disclaims any and all liability for any malfunctions, failure or accide nt arising out of the use of Renesas Electronics products outside of such specified ranges. 7. Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics products, semiconductor products have specific characteristics, such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Unless designated as a high reliability product or a product for ha rsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are not subject to radiation resistance design. You are responsible for implementing safety measures to guard against the possibility of bodily injury, injury or damage caused by fire, and/or danger to the public in the event of a failure or malfunction of Renesas Electronics products, such as safety design for hardware and software, including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measu res. Because the evaluation of microcomputer software alone is very difficult and impractical, you are responsible for evaluating the safety of the final products or systems manufactured by you. 8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatib ility of each Renesas Electronics product. You are responsible for carefully and sufficiently investigating applicable laws and regulations that regulate the inclusion or use of controlled substances, includi ng without limitation, the EU RoHS Directive, and using Renesas Electronics products in compliance with all these applicable laws and regulations. Renesas Electronics disclaims any and all liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. Renesas Electronics products and technologies shall not be used for or incorporated into any products or systems whose manuf acture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. You shall comply with any applicable export control laws and regulations promulgated and administered by the go vernments of any countries asserting jurisdiction over the parties or transactions. 10. It is the responsibility of the buyer or distributor of Renesas Electronics products, or any other party who distributes, d isposes of, or otherwise sells or transfers the product to a third party, to notify such third party in advance of the contents and conditions set forth in this document. 11. This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written cons ent of Renesas Electronics. 12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this doc ument or Renesas Electronics products. (Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its directly o r indirectly controlled subsidiaries. (Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.