Microcontroller

RA0E1

Renesas Technology Corp

Renesas Microcontrollers Rev.1.20 Nov 28, 2025

Manufacturer: Renesas Technology Corp

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Rev.1.20 Nov 28, 2025 ■ Arm Cortex-M23 Core

Armv8-M architecture
Maximum operating frequency: 32 MHz
Debug and Trace: DWT, FPB, CoreSight™ MTB-M23
CoreSight Debug Port: SW-DP ■ Memory
Up to 64-KB code flash memory
1-KB data flash memory (1,000,000 (TYP) program/erase cycles)
12-KB SRAM
Flash read protection (FRP)
128-bit unique ID ■ Connectivity
Serial Array Unit (SAU) – Simplified SPI × 3 – Simplified IIC × 3 – UART × 2 – UART (LIN-bus supported) × 1
Serial Interface UARTA (UARTA) × 1
I2C Bus interface (IICA) × 1 ■ Analog
12-bit A/D Converter (ADC12)
Temperature Sensor (TSN) ■ Timers
16-bit Timer Array Unit (TAU) × 8
32-bit interval timer (TML32) × 1 – 1 channel in 32-bit counter mode – 2 channels in 16-bit counter mode – 4 channels in 8-bit counter mode ■ Safety
SRAM parity error check
Flash area protection
ADC self-diagnosis function
Cyclic Redundancy Check (CRC)
Independent Watchdog Timer (IWDT)
GPIO readback level detection
Register write protection
Illegal memory access detection ■ Security
True Random Number Generator (TRNG) ■ System and Power Management
Low power modes
Realtime Clock (RTC)
Event Link Controller (ELC)
Data Transfer Controller (DTC)
Power-on reset
Low V oltage Detection (LVD) with voltage settings ■ Multiple Clock Sources
Main clock oscillator (MOSC) (1 to 20 MHz)
Sub-clock oscillator (SOSC) (32.768 kHz)
High-speed on-chip oscillator (HOCO) (24/32 MHz)
Middle-speed on-chip oscillator (MOCO) (4 MHz)
Low-speed on-chip oscillator (LOCO) (32.768 kHz)
Clock trim function for HOCO/MOCO/LOCO
Clock out support ■ Up to 29 pins for general I/O ports
5-V tolerance, open drain, input pull-up ■ Operating Voltage
VCC: 1.6 to 5.5 V ■ Operating Temperature and Packages – 32-pin LQFP (7 mm × 7 mm, 0.8 mm pitch) – 32-pin HWQFN (5 mm × 5 mm, 0.5 mm pitch) – 24-pin HWQFN (4 mm × 4 mm, 0.5 mm pitch) – 20-pin LSSOP (4.4 mm × 6.5 mm, 0.65 mm pitch) – 16-pin HWQFN (3 mm × 3 mm, 0.5 mm pitch) Datasheet R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 1 of 86

Overview The MCU integrates multiple series of software- and pin-compatible Arm®-based 32-bit cores that share a common set of Renesas peripherals to facilitate design scalability. The MCU in this series incorporates an energy-efficient Arm Cortex®-M23 32-bit core, that is particularly well suited for cost-sensitive and low-power applications, with the following features:

Up to 64-KB code flash memory
12-KB SRAM
Serial Interface (SAU, UARTA, IICA)
General Purpose Timer (TAU, TML32)
12-bit A/D Converter (ADC12)

1.1 Function Outline

Table 1.1 Arm core Feature Functional description Arm Cortex-M23 core ● Maximum operating frequency: up to 32 MHz

Arm Cortex-M23 core: – Revision: r1p0-00rel0 – Armv8-M architecture profile – Single-cycle integer multiplier – 19-cycle integer divider
SysTick timer: – Driven by SYSTICCLK (LOCO) or ICLK Table 1.2 Memory Feature Functional description Code flash memory Maximum 64-KB of code flash memory. Data flash memory 1-KB of data flash memory. Option-setting memory The option-setting memory determines the state of the MCU after a reset. SRAM On-chip SRAM with parity bit. Table 1.3 System (1 of 2) Feature Functional description Operating modes Operating mode:
Single-chip mode Resets The MCU provides 7 resets (RES pin reset, power-on reset, independent watchdog timer reset, voltage monitor 0/1 resets, SRAM parity error reset, software reset). Low Voltage Detection (LVD) The Low Voltage Detection (LVD) module monitors the voltage level input to the VCC pin. The detection level can be selected by register settings. The LVD module consists of two separate voltage level detectors (LVD0, LVD1). LVD0 and LVD1 measure the voltage level input to the VCC pin. LVD registers allow your application to configure detection of VCC changes at various voltage thresholds. Clocks ● Main clock oscillator (MOSC)
Sub-clock oscillator (SOSC)
High-speed on-chip oscillator (HOCO)
Middle-speed on-chip oscillator (MOCO)
Low-speed on-chip oscillator (LOCO)
Clock output / Buzzer output support Interrupt Controller Unit (ICU) The Interrupt Controller Unit (ICU) controls which event signals are linked to the Nested Vector Interrupt Controller (NVIC), and the Data Transfer Controller (DTC) modules. The ICU also controls non-maskable interrupts. Low power modes Power consumption can be reduced in multiple ways, including setting clock dividers, stopping modules, selecting power control mode in normal operation, and transitioning to low power modes. RA0E1 Datasheet 1. Overview R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 2 of 86

Table 1.3 System (2 of 2) Feature Functional description Register write protection The register write protection function protects important registers from being overwritten due to software errors. The registers to be protected are set with the Protect Register (PRCR). Flash Read Protection The MCU incorporates the flash read protection with one secure regions that include the code flash. The secure region can be protected from non-secure program accesses. A non-secure program cannot access a protected region. Independent Watchdog Timer (IWDT) The Independent Watchdog Timer (IWDT) consists of a 14-bit down counter that must be serviced periodically to prevent counter underflow. The IWDT provides functionality to reset the MCU or to generate a non-maskable interrupt or an underflow interrupt. Because the timer operates with the LOCO, it is particularly useful in returning the MCU to a known state as a fail- safe mechanism when the system runs out of control. The IWDT can be triggered automatically by a reset, underflow, refresh error, or a refresh of the count value in the registers. Table 1.4 Event link Feature Functional description Event Link Controller (ELC) The Event Link Controller (ELC) uses the event requests generated by various peripheral modules as source signals to connect them to different modules, allowing direct link between the modules without CPU intervention. Table 1.5 Direct memory access Feature Functional description Data Transfer Controller (DTC) A Data Transfer Controller (DTC) module is provided for transferring data when activated by an interrupt request. Table 1.6 Timers Feature Functional description Timer Array Unit (TAU) The timer array unit has eight 16-bit timers. Each 16-bit timer is called a channel and can be used as an independent timer. In addition, two or more channels can be used to create a High functional timer. 32-bit Interval Timer (TML32) The 32-bit interval timer is made up of four 8-bit interval timers (referred to as channels 0 to 3). Each is capable of operating independently and in that case they all have the same functions. Two 8-bit interval timer channels can be connected to operate as a 16-bit interval timer. Four 8-bit interval timer channels can be connected to operate as a 32-bit interval timer. Realtime Clock (RTC) The Realtime Clock (RTC) has the following features.

Capable of counting years, months, days of the week, dates, hours, minutes, and seconds, for up to 99 years
Fixed-cycle interrupt (with period selectable from among 0.5 of a second, 1 second, 1 minute, 1 hour, 1 day, or 1 month)
Alarm interrupt (alarm set by day of week, hour, and minute)
Pin output function of 1 Hz Table 1.7 Communication interfaces Feature Functional description Serial Array Unit (SAU) A Serial Array Unit (SAU) has up to two units. Unit0 has four channels and Unit1 has two channels. Each channel can achieve simplified SPI, UART or simplified IIC. I2C Bus Interface (IICA) The I2C Bus Interface (IICA) has 1 channel. The IICA module conforms I2C (Inter-Integrated Circuit) Bus Interface functions. Serial Interface UARTA (UARTA) The Serial Interface UARTA (UARTA) has 1 channel. UARTA performs an asynchronous communication. Table 1.8 Analog (1 of 2) Feature Functional description 12-bit A/D Converter (ADC12) A 12-bit successive approximation A/D converter is provided. Up to 10 analog input channels are selectable. Temperature sensor output and internal reference voltage are selectable for conversion. RA0E1 Datasheet 1. Overview R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 3 of 86

Table 1.8 Analog (2 of 2) Feature Functional description Temperature Sensor (TSN) The on-chip Temperature Sensor (TSN) determines and monitors the die temperature for reliable operation of the device. The sensor outputs a voltage directly proportional to the die temperature, and the relationship between the die temperature and the output voltage is fairly linear. The output voltage is provided to the ADC12 for conversion and can be further used by the end application. Table 1.9 Data processing Feature Functional description Cyclic Redundancy Check (CRC) calculator The Cyclic Redundancy Check (CRC) generates CRC codes to detect errors in the data. Two CRC-generation polynomials (CRC-CCITT, CRC-32) are available. Table 1.10 I/O ports Feature Functional description I/O ports ● I/O ports for the 32-pin LQFP/HWQFN – I/O pins: 26 – Input pins: 3 – Pull-up resistors: 16 – N-ch open-drain outputs: 15 – 5-V tolerance: 2

I/O ports for the 24-pin HWQFN – I/O pins: 20 – Input pins: 1 – Pull-up resistors: 12 – N-ch open-drain outputs: 11 – 5-V tolerance: 2
I/O ports for the 20-pin LSSOP – I/O pins: 16 – Input pins: 1 – Pull-up resistors: 12 – N-ch open-drain outputs: 9
I/O ports for the 16-pin HWQFN – I/O pins: 12 – Input pins: 1 – Pull-up resistors: 9 – N-ch open-drain outputs: 6 RA0E1 Datasheet 1. Overview R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 4 of 86

1.2 Block Diagram

Figure 1.1 shows a block diagram of the MCU superset. Some individual devices within the group have a subset of the features. High-speed on-chip oscillator (HOCO) Arm Cortex-M23 Core 64 KB Code flash 1 KB Data flash Bus matrix Clock generation circuit Serial interface UARTA (UARTA) × 1 ch Serial interface IICA (IICA) × 1 ch Interrupt controller unit (ICU) Main clock oscillator (MOSC) Sub-clock oscillator (SOSC) Middle-speed on-chip oscillator (MOCO) Low-speed on-chip oscillator (LOCO) 32-bit interval timer (TML32) × 1 ch Realtime clock (RTC) Independent watchdog timer (IWDT) Register write protection Data transfer controller (DTC) Event link controller (ELC) NVIC SysTick MTB True random number generator (TRNG) 12-bit A/D converter (ADC12) Flash control block (FCB) GPIO Timer array unit (TAU) × 8 ch Voltage detector (LVD) X2/EXCLK XCIN XCOUT SWCLK SWDIO P*** IRQ* TI TO RXDA* TXDA* SCLA* SDAA* AN*** PCLBUZ* Internal peripheral bus 1 Internal peripheral bus 9 Internal peripheral bus 3 Internal peripheral bus 7 RTCOUT Cyclic redundancy check (CRC) SWD NMI Temperature sensor P200, P214, P215 FRP 12 KB SRAM (Parity) Serial array unit 0 (SAU0) × 4 ch Serial array unit 1 (SAU1) × 2 ch SCK SI SO** RXD* TXD* SCL SDA SSI** Note: Not available on all parts Note: The asterisks (*) in the signal names represent variable numbers that are specific to each part. Figure 1.1 Block diagram

1.3 Part Numbering

Figure 1.2 shows the product part number information, including memory capacity and package type. Table 1.11 shows a list of products. RA0E1 Datasheet 1. Overview R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 5 of 86

FJ ： LQFP 32 pins NH ： HWQFN 32 pins NK: HWQFN 24 pins SC: LSSOP 20 pins SD: TSSOP 20 pins NL: HWQFN 16 pins Quality Grade Operating temperature Code flash memory size 7 ： 64 KB 5 ： 32 KB Feature set Series name RA Family Flash memory Renesas microcontroller 7 3 C F JR 7 F A 0 E1 0 Group name A A 0 Production identification code Terminal material (Pb-free) A: Sn (Tin) only C: Others Packaging A: Tray B: Tray (Full carton) C: Magazine H: Tape and reel U: Tray (Full tray) V: Magazine (Full magazine) Note: Check the order screen for each product on the Renesas website for valid symbols after the #. Figure 1.2 Part numbering scheme Table 1.11 Product list (1 of 2) Product part number Package code Code flash Data flash SRAM Operating temperature R7FA0E1073CFJ PLQP0032GB-A 64 KB 1 KB 12 KB -40 to +105°C R7FA0E1073CNH PWQN0032KE-A R7FA0E1073CNK PWQN0024KG-A R7FA0E1073CSC PLSP0020JB-A R7FA0E1073CSD PTSP0020JI-A R7FA0E1073CNL PWQN0016KD-A RA0E1 Datasheet 1. Overview R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 6 of 86

Table 1.11 Product list (2 of 2) Product part number Package code Code flash Data flash SRAM Operating temperature R7FA0E1053CFJ PLQP0032GB-A 32 KB 1 KB 12 KB -40 to +105°C R7FA0E1053CNH PWQN0032KE-A R7FA0E1053CNK PWQN0024KG-A R7FA0E1053CSC PLSP0020JB-A R7FA0E1053CNL PWQN0016KD-A RA0E1 Datasheet 1. Overview R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 7 of 86

1.4 Function Comparison

Table 1.12 Function comparison Parts number R7FA0E1073CFJ R7FA0E1073CNH R7FA0E1053CFJ R7FA0E1053CNH R7FA0E1073CNK R7FA0E1053CNK R7FA0E1073CSC R7FA0E1073CSD R7FA0E1053CSC R7FA0E1073CNL R7FA0E1053CNL Pin count 32 24 20 16 Package LQFP/HWQFN HWQFN LSSOP/ TSSOP LSSOP HWQFN Code flash memory 64 KB 32 KB 64 KB 32 KB 64 KB 32 KB 64 KB 32 KB Data flash memory 1 KB 1 KB 1 KB 1 KB SRAM (Parity) 12 KB 12 KB 12 KB 12 KB System CPU clock 32 MHz 32 MHz 32 MHz 32 MHz Sub-clock oscillator Yes Yes (CMC.XTSEL=1) Yes (CMC.XTSEL=1) Yes (CMC.XTSEL=1) ICU Yes Yes Yes Yes Event control ELC Yes Yes Yes Yes DMA DTC Yes Yes Yes Yes Timers TAU 8 (PWM outputs: 7) 8 (PWM outputs: 7) 8 (PWM outputs: 7) 8 (PWM outputs: 7) TML32 1 (32-bit counter mode), 2 (16-bit counter mode), 4 (8-bit counter mode) 1 (32-bit counter mode), 2 (16-bit counter mode), 4 (8-bit counter mode) 1 (32-bit counter mode), 2 (16-bit counter mode), 4 (8-bit counter mode) 1 (32-bit counter mode), 2 (16-bit counter mode), 4 (8-bit counter mode) RTC Yes Yes Yes Yes IWDT Yes Yes Yes Yes Communication SAU*1 3 (simplified SPI), 3 (simplified IIC), 2 (UART), 1 (UART supporting LIN-bus) 3 (simplified SPI), 3 (simplified IIC), 2 (UART), 1 (UART supporting LIN-bus) 3 (simplified SPI), 3 (simplified IIC), 2 (UART), 1 (UART supporting LIN-bus) 2 (simplified SPI), 2 (simplified IIC), 2 (UART) UARTA 1 1 1 1 IICA 1 1 1 1 Analog ADC12 10 8 6 5 TSN Yes Yes Yes Yes Data processing CRC Yes Yes Yes Yes Security TRNG TRNG TRNG TRNG I/O ports I/O pins 26 20 16 12 Input pins 3 1 1 1 Pull-up resistors 16 12 12 9 N-ch open-drain outputs 15 11 9 6 5-V tolerance 2 2 — — Note 1. SAU consists of several channels. Each channel can be assigned only one function at a time. RA0E1 Datasheet 1. Overview R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 8 of 86

1.5 Pin Functions

Table 1.13 Pin functions (1 of 2) Function Signal I/O Description Power supply VCC Input Power supply pin. Connect it to the system power supply. Connect this pin to VSS by a 0.1-µF capacitor. Place the capacitor close to the pin. VCL I/O Connect this pin to the VSS pin by the smoothing capacitor used to stabilize the internal power supply. Place the capacitor close to the pin. VSS Input Ground pin. Connect it to the system power supply (0 V). Clock X2 I/O Pins for a crystal resonator. An external clock signal can be input through the X2 pin.X1 Input XCIN Input Input/output pins for the sub-clock oscillator. Connect a crystal resonator between XCOUT and XCIN.XCOUT Output PCLBUZ0 Output Clock output / Buzzer output EXCLK Input External clock input for the main clock System control RES Input Reset signal input pin. The MCU enters the reset state when this signal goes low. On-chip debug SWDIO I/O Serial wire debug data input/output pin SWCLK Input Serial wire clock pin Interrupt NMI Input Non-maskable interrupt request pin IRQ0 to IRQ5 Input Maskable interrupt request pins TAU TI00 to TI07 Input Pins for inputting an external counting clock/capture trigger to 16-bit timers 00 to 07 TO00 to TO07 I/O Timer output pins for 16-bit timers 00 to 07 RTC RTCOUT Output Output pin for 1-Hz clock IICA SCLAn (n = 0) I/O Input/output pins for the clock SDAAn (n = 0) I/O Input/output pins for data SAU SCK00, SCK11, SCK20 I/O Serial clock I/O pins for serial interfaces SPI00, SPI11 and SPI20 SI00, SI11, SI20 Input Serial data input pins for serial interfaces SPI00, SPI11 and SPI20 SO00, SO11, SO20 Output Serial data output pins for serial interfaces SPI00, SPI11, and SPI20 SSI00 Input Chip select pin for serial interfaces SPI00 SCL00, SCL11, SCL20 Output Serial clock output pins for serial interfaces IIC00, IIC11, and IIC20 SDA00, SDA11, SDA20 I/O Serial data I/O pins for serial interfaces IIC00, IIC11, and IIC20 RXD0, RXD1, RXD2 Input Serial data input pins for serial interfaces UART0, UART1, and UART2 TXD0, TXD1, TXD2 Output Serial data output pins for serial interfaces UART0, UART1, and UART2 UARTA RXDAn (n = 0) Input Serial data input pin for the UARTA serial interface TXDAn (n = 0) Output Serial data output pin for the UARTA serial interface Analog power supply VREFH0 Input Analog reference voltage supply pin for the ADC12. Connect this pin to external reference voltage or VCC. VREFL0 Input Analog reference ground pin for the ADC12. Connect this pin to external reference ground voltage or VSS. ADC12 AN000 to AN007, AN021 to AN022 Input Input pins for the analog signals to be processed by the A/D converter. RA0E1 Datasheet 1. Overview R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 9 of 86

Table 1.13 Pin functions (2 of 2) Function Signal I/O Description I/O ports P008 to P015 I/O General-purpose input/output pins P100 to P103, P108 to P110, P112 I/O General-purpose input/output pins P200 Input General-purpose input pin P201, P206 to P208, P212, P213 I/O General-purpose input/output pins P214, P215 Input General-purpose input pins P300 I/O General-purpose input/output pins P407 I/O General-purpose input/output pins P913, P914 I/O General-purpose input/output pins RA0E1 Datasheet 1. Overview R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 10 of 86

1.6 Pin Assignments

Figure 1.3 to Figure 1.6 show the pin assignments from the top view. P015 P014 P013 P012 P009 P008 P011/VREFL0 P300/SWCLK P200 P201 P206/RES P207 P208 P913 P914 P100 P102 P103 P112 P110 P109 P108/SWDIO P101 VCL P214/XCOUT VSS P213/X2/EXCLK P212/X1 VCC P407 P215/XCIN P010/VREFH0 Figure 1.3 Pin assignment for LQFP / HWQFN 32-pin (top view) Note: For the QFN package product, solder the exposed die pad to the PCB. The potential of the exposed die pad is recommended to design as electrically open. RA0E1 Datasheet 1. Overview R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 11 of 86

Note: For the QFN package product, solder the exposed die pad to the PCB. The potential of the exposed die pad is recommended to design as electrically open. Figure 1.6 Pin assignment for HWQFN 16-pin (top view) RA0E1 Datasheet 1. Overview R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 13 of 86

1.7 Pin Lists

Table 1.14 Pin list Pin number Interrupt Timers Communication interfaces Analogs 32-pin 24-pin 20-pin 16-pin Power, System, Clock, Debug I/O ports TAU RTC SAU IICA UARTA ADC 5 3 4 2 X2/EXCLK/ XCOUT*1 P213 IRQ0_B TI00_A/TI02_B/ TO02_B — TXD1_A/ SO11_A SDAA0_B TXDA0_B — 6 4 5 3 X1/XCIN*1 P212 IRQ1_B TO00_A/ TI03_C/TO03_C — RXD1_A/ SI11_A/ SDA11_A SCLA0_B RXDA0_B — 8 — — — PCLBUZ0_C P407 IRQ4_C — RTCOUT_A SCK11_A/ SCL11_A — — — 14 9 8 6 PCLBUZ0_A P201 IRQ5_B TI05_B/TO05_B RTCOUT_B SSI00_B/ SCK11_B/ SCL11_B — — — 16 11 10 8 SWCLK P300 — TI04_B/TO04_B — — — — — 17 12 11 9 SWDIO P108 — TI03_B/TO03_B — — — — — 18 13 12 — — P109 IRQ4_B TI02_A/TO02_A — TXD2_A/ SO20_A SDAA0_C TXDA0_C — 19 14 13 — — P110 IRQ3_B TI01_A/TO01_A — RXD2_A/ SI20_A/ SDA20_A SCLA0_C RXDA0_C — 20 15 14 — — P112 IRQ2_B TI03_A/TO03_A — SCK20_A/ SCL20_A/ SSI00_C — — — 22 16 15 10 PCLBUZ0_B P102 IRQ4_A TI06_A/ TO06_A/ TO00_C RTCOUT_C SCK00_A/ SCL00_A — — — 23 17 16 11 — P101 IRQ3_A TI07_A/ TO07_A/TI00_C — TXD0_A/ SO00_A SDAA0_D TXDA0_D AN021 24 18 17 12 — P100 IRQ2_A TI04_A/ TO04_A/ TI01_B/TO01_B — RXD0_A/ SI00_A/ SDA00_A SCLA0_D RXDA0_D AN022 28 22 19 13 — P012 — — — — — — AN004 31 23 20 14 VREFL0 P011 — — — — — — AN001 32 24 1 15 VREFH0 P010 — — — — — — AN000 Note 1. When setting CMC.XTSEL = 1 for 24-, 20-, and 16-pin products Note: Some signal names have _A, _B, _C or _D suffixes, but these suffixes can be ignored when assigning functionality, except for SAU and IICA. For SAU and IICA, only signals, except for SCK11, SCL11, and SSI00, bearing the same suffix can be selected. Assigning the same function to two or more pins simultaneously is prohibited. RA0E1 Datasheet 1. Overview R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 14 of 86

Electrical Characteristics Unless otherwise specified, the electrical characteristics of the MCU are defined under the following conditions: VCC*1 = VREFH0 = 1.6 to 5.5 V VSS = VREFL0 = 0 V , Ta = Topr Note 1. The typical condition is set to VCC = 3.3 V. Figure 2.1 shows the timing conditions. For example, P300 C V OH = VCC × 0.7, V OL = VCC × 0.3 V IH = VCC × 0.7, V IL = VCC × 0.3 Load capacitance C = 30 pF Figure 2.1 Input or output timing measurement conditions

2.1 Absolute Maximum Ratings

Table 2.1 Absolute maximum ratings (1 of 2) Parameter Symbol Value Unit Power supply voltage VCC -0.5 to +6.5 V VCL pin input voltage VIVCL -0.3 to +2.1 and -0.3 to VCC + 0.3*1 V Input voltage P100 to P103, P108 to P110, P112, P200, P201, P206 to P208, P300, P407 VI1 -0.3 to VCC + 0.3*2 V P913, P914 (5 V tolerant) VI2 -0.3 to +6.5 V P008 to P015, P212 to P215 VI3 -0.3 to VCC + 0.3*2 V Output voltage P100 to P103, P108 to P110, P112, P201, P206 to P208, P300, P407 VO1 -0.3 to VCC + 0.3*2 V P913, P914 (N-ch open-drain) VO2 -0.3 to +6.5 V P008 to P015, P212, P213 VO3 -0.3 to VCC + 0.3*2 V Analog input voltage AN000 to AN007 VAI1 -0.3 to VCC + 0.3 and -0.3 to VREFH0 + 0.3*2 *3 V AN021 to AN022 VAI2 -0.3 to VCC + 0.3 and -0.3 to VREFH0 + 0.3*2 *3 V RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 15 of 86

Table 2.1 Absolute maximum ratings (2 of 2) Parameter Symbol Value Unit High-level output current P100 to P103, P108 to P110, P112, P201 to P207, P208, P300, P407 Per pin IOH1 -40 mA Total of all pins -100 mA P008 to P015, P212, P213 Per pin IOH2 -5 mA Total of all pins -20 mA Low-level output current P100 to P103, P108 to P110, P112, P201, P206 to P208, P300, P407, P913, P914 Per pin IOL1 40 mA Total of all pins 100 mA P008 to P015, P212, P213 Per pin IOL2 10 mA Total of all pins 20 mA Ambient operating temperature In normal operation mode Ta -40 to +105 °C In flash memory programming mode -40 to +105 °C Storage temperature Tstg -65 to +150 °C Note 1. Connect the VCL pin to VSS through a capacitor (0.47 to 1 µF). The listed value is the absolute maximum rating of the VCL pins. Only use the capacitor connection. Do not apply a specific voltage to this pin. Note 2. This voltage must be no higher than 6.5 V. Note 3. The voltage on a pin in use for A/D conversion must not exceed VREFH0 + 0.3. Note: The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified. Note: VREFH0 refers to the positive reference voltage of the A/D converter. Note: The reference voltage is VSS. Caution: Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Table 2.2 Recommended operating conditions Parameter Symbol Min Typ Max Unit Power supply voltages VCC 1.6 — 5.5 V VSS — 0 — V Analog power supply voltages VREFH0 When used as ADC12 Reference 1.6 — VCC V VREFL0 — 0 — V

2.1.1 Tj/Ta Definition

Table 2.3 Tj/Ta definition Conditions: Products with operating temperature Ta = -40 to +105°C Parameter Symbol Typ Max Unit Test conditions Permissible junction temperature Tj — 125*1 °C High-speed mode Middle-speed mode Low-speed mode Subosc-speed mode Note 1. The upper limit of operating temperature is 105°C. Note: Make sure that Tj = T a + θja × total power consumption (W), where total power consumption = (VCC - VOH) × ΣIOH + VOL × ΣIOL + ICCmax × VCC. RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 16 of 86

2.2 Oscillators Characteristics

2.2.1 Main clock Oscillator Characteristics

Table 2.4 Main clock oscillator characteristics Conditions: VCC = 1.6 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Min Typ Max Unit Test conditions Main clock oscillation allowable input cycle time*1 Ceramic resonator Crystal resonator 0.05 — 1 µs — Note 1. The listed time and frequency indicate permissible ranges of the oscillator. For actual applications, request evaluation by the manufacturer of the oscillator circuit mounted on a board so you can use appropriate values. Refer to AC Characteristics for instruction execution time. Note: Since the CPU is started by the high-speed on-chip oscillator clock after release from the reset state, the user should use the oscillation stabilization time counter status register (OSTC) to check the X1 clock oscillation stabilization time. Specify the values for the oscillation stabilization time in the OSTC register and the oscillation stabilization time select register (OSTS) after having sufficiently evaluated the oscillation stabilization time with the resonator to be used.

2.2.2 Sub-clock Oscillator Characteristics

Table 2.5 Sub-clock oscillator characteristics Conditions: VCC = 2.4 to 5.5 V (16- to 24-pin products), VCC = 1.6 to 5.5 V (32-pin products), VSS = 0 V, Ta = -40 to +105°C Parameter Min Typ Max Unit Test conditions Sub-clock oscillation frequency (fSOSC)*1 Crystal resonator — 32.768 — kHz — Note 1. The listed time and frequency indicate permissible ranges of the oscillator. For actual applications, request evaluation by the manufacturer of the oscillator circuit mounted on a board so you can use appropriate values. Refer to AC Characteristics for instruction execution time.

2.2.3 On-chip Oscillators Characteristics

Table 2.6 On-chip oscillators characteristics (1 of 2) Conditions: VCC = 1.6 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol Min Typ Max Unit Test conditions High-speed on-chip oscillator clock frequency fHOCO 1 — 32 MHz — High-speed on-chip oscillator clock frequency accuracy OSCSF.HOCOSF = 1 — -1.0 — +1.0 % Ta = -40 to +105°C, 1.6 V ≤ VCC ≤ 5.5 V OSCSF.HOCOSF = 0*3 — -15 — 0 % — High-speed on-chip oscillator clock frequency trimming resolution — — 0.05 — % — High-speed on-chip oscillator clock oscillation stabilization time*4 tHOCO — — 4.4 µs — Middle-speed on-chip oscillator clock frequency*1 fMOCO 1 — 4 MHz — Middle-speed on-chip oscillator clock frequency accuracy — -12 — 12 % — Middle-speed on-chip oscillator clock frequency trimming resolution — — 0.15 — % — Middle-speed on-chip oscillator clock oscillation stabilization time tMOCO — — 1 µs — Middle-speed on-chip oscillator frequency temperature coefficient Low-speed on-chip oscillator clock frequency*1 fLOCO — 32.768 — kHz — Low-speed on-chip oscillator clock frequency accuracy — -15 — 15 % — RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 17 of 86

Table 2.6 On-chip oscillators characteristics (2 of 2) Conditions: VCC = 1.6 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol Min Typ Max Unit Test conditions Low-speed on-chip oscillator clock frequency trimming resolution — — 0.3 — % — Low-speed on-chip oscillator clock oscillation stabilization time tLOCO — — 100 µs — Low-speed on-chip oscillator frequency temperature coefficient Note 1. The listed values only indicate the characteristics of the oscillators. Refer to AC Characteristics for instruction execution time. Note 2. These values are the results of characteristic evaluation and are not checked for shipment. Note 3. The listed condition applies when OFS1.HOCOFRQ1[2:0] = 010b. Note 4. Check OSCSF.HOCOSF to confirm whether stabilization time has elapsed.

2.3 DC Characteristics

2.3.1 Pin Characteristics

Table 2.7 I/O IOH Conditions: VCC = 1.6 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol Min Typ Max Unit Test conditions Allowable high-level output current*1 Per pin for P100 to P103, P108 to P110, P112, P201, P206 to P208, P300, P407 IOH1 — — -10*2 mA 1.6 V ≤ VCC ≤ 5.5 V Total of all pins (when duty ≤ 70%*3) — — -80*4 mA 4.0 V ≤ VCC ≤ 5.5 V — — -19 mA 2.7 V ≤ VCC < 4.0 V — — -10 mA 1.8 V ≤ VCC < 2.7 V — — -5 mA 1.6 V ≤ VCC < 1.8 V Per pin for P008 to P015, P212, P213 IOH2 — — -3*2 mA 4.0 V ≤ VCC ≤ 5.5 V Total of all pins (when duty ≤ 70%*3) — — -20 mA 4.0 V ≤ VCC ≤ 5.5 V — — -10 mA 2.7 V ≤ VCC < 4.0 V — — -5 mA 1.8 V ≤ VCC < 2.7 V — — -5 mA 1.6 V ≤ VCC < 1.8 V Note 1. Device operation is guaranteed at the listed currents even if current is flowing from the VCC pin to an output pin. Note 2. The combination of these and other pins must also not exceed the value for maximum total current. Note 3. The listed currents apply when the duty cycle is no greater than 70%. Use the following formula to calculate the output current when the duty cycle is greater than 70%, where n is the duty cycle.

Total output current from the listed pins = (I OH × 0.7)/(n × 0.01) Example when n = 80% and IOH = -10.0 mA Total output current from the listed pins = (-10.0 × 0.7)/(80 × 0.01) = -8.75 mA Note that the duty cycle has no effect on the current that is allowed to flow into a single pin. A current higher than the absolute maximum rating must not flow into a single pin. Note 4. The maximum value is -50 mA with an ambient operating temperature range of 85°C to 105°C. Note: The following pins are not capable of the output of high-level signals in the N-ch open-drain mode. P100 to P103, P109, P110, P112, P201, P207, P208, P212, P213 and P407. Note: The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified. RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 18 of 86

Table 2.8 I/O IOL Conditions: VCC = 1.6 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol Min Typ Max Unit Test conditions Allowable low-level output current*1 Per pin for P100 to P103, P108 to P110, P112, P201, P206 to P208, P300, P407 IOL1 — — 20*2 mA — Per pin for P913, P914 — — 15*2 mA — Total of all pins (when duty ≤ 70%*3) — — 80*4 mA 4.0 V ≤ VCC ≤ 5.5 V — — 35 mA 2.7 V ≤ VCC < 4.0 V — — 20 mA 1.8 V ≤ VCC < 2.7 V — — 10 mA 1.6 V ≤ VCC < 1.8 V Per pin for P008 to P015, P212, P213 IOL2 — — 8.5*2 mA 4.0 V ≤ VCC ≤ 5.5 V — — 1.5*2 mA 2.7 V ≤ VCC < 4.0 V — — 0.6*2 mA 1.8 V ≤ VCC < 2.7 V — — 0.4*2 mA 1.6 V ≤ VCC < 1.8 V Total of all pins (when duty ≤ 70%*3) — — 20 mA 4.0 V ≤ VCC ≤ 5.5 V — — 20 mA 2.7 V ≤ VCC < 4.0 V — — 15 mA 1.8 V ≤ VCC < 2.7 V — — 10 mA 1.6 V ≤ VCC < 1.8 V Note 1. Device operation is guaranteed at the listed currents even if current is flowing from an output pin to VSS pin. Note 2. The combination of these and other pins must also not exceed the value for maximum total current. Note 3. The listed currents apply when the duty cycle is no greater than 70%. Use the following formula to calculate the output current when the duty cycle is greater than 70%, where n is the duty cycle.

Total output current from the listed pins = (I OL × 0.7)/(n × 0.01) Example when n = 80% and IOL = 10.0 mA Total output current from the listed pins = (10.0 × 0.7)/(80 × 0.01) = 8.75 mA Note that the duty cycle has no effect on the current that is allowed to flow into a single pin. A current higher than the absolute maximum rating must not flow into a single pin. Note 4. The maximum value is 40 mA with an ambient operating temperature range of 85°C to 105°C. Note: The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified. Table 2.9 I/O VIH, VIL (1 of 2) Conditions: VCC = 1.6 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol Min Typ Max Unit Test conditions Input voltage, high P100 to P103, P108 to P110, P112, P200, P201, P206 to P208, P300, P407 Normal input buffer VIH1 VCC × 0.8 — VCC V — P100 to P103, P108 to P110, P112, P201, P207, P208, P300, P407 TTL input buffer VIH2 2.2 — VCC V 4.0 V ≤ VCC ≤ 5.5 V 2.0 — VCC V 3.3 V ≤ VCC < 4.0 V 1.5 — VCC V 1.6 V ≤ VCC < 3.3 V P008 to P015 VIH3 VCC × 0.7 — VCC V — P913, P914 VIH4 VCC × 0.7 — 6.0 V — P212 to P215 VIH5 VCC × 0.8 — VCC V — RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 19 of 86

Table 2.9 I/O VIH, VIL (2 of 2) Conditions: VCC = 1.6 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol Min Typ Max Unit Test conditions Input voltage, low P100 to P103, P108 to P110, P112, P200, P201, P206 to P208, P300, P407 Normal input buffer VIL1 0 — VCC × 0.2 V — P100 to P103, P108 to P110, P112, P201, P207, P208, P300, P407 TTL input buffer VIL2 0 — 0.8 V 4.0 V ≤ VCC ≤ 5.5 V 0 — 0.5 V 3.3 V ≤ VCC < 4.0 V 0 — 0.32 V 1.6 V ≤ VCC < 3.3 V P008 to P015 VIL3 0 — VCC × 0.3 V — P913, P914 VIL4 0 — VCC × 0.3 V — P212 to P215 VIL5 0 — VCC × 0.2 V — Note: The maximum value of V IH of pins P100 to P103, P109, P110, P112, P201, P207, P208, P212, P213 and P407 is VCC, even in the N-ch open-drain mode. Note: The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified. Table 2.10 I/O VOH, VOL (1 of 2) Conditions: VCC = 1.6 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol Min Typ Max Unit Test conditions Output voltage, high P100 to P103, P108 to P110, P112, P201, P206 to P208, P300, P407 VOH1 VCC - 1.5 — — V 4.0 V ≤ VCC ≤ 5.5 V IOH1 = -10 mA VCC - 0.7 — — V 4.0 V ≤ VCC ≤ 5.5 V IOH1 = -3 mA VCC - 0.6 — — V 2.7 V ≤ VCC ≤ 5.5 V IOH1 = -2 mA VCC - 0.5 — — V 1.8 V ≤ VCC ≤ 5.5 V IOH1 = -1.5 mA VCC - 0.5 — — V 1.6 V ≤ VCC ≤ 5.5 V IOH1 = -1 mA P008 to P015, P212, P213 VOH2 VCC - 0.7 — — V 4.0 V ≤ VCC ≤ 5.5 V IOH2 = -3 mA VCC - 0.5 — — V 2.7 V ≤ VCC < 4.0 V IOH2 = -1 mA VCC - 0.5 — — V 1.8 V ≤ VCC < 2.7 V IOH2 = -1 mA VCC - 0.5 — — V 1.6 V ≤ VCC < 1.8 V IOH2 = -0.5 mA RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 20 of 86

Table 2.10 I/O VOH, VOL (2 of 2) Conditions: VCC = 1.6 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol Min Typ Max Unit Test conditions Output voltage, low P100 to P103, P108 to P110, P112, P201, P206 to P208, P300, P407 VOL1 — — 1.3 V 4.0 V ≤ VCC ≤ 5.5 V IOL1 = 20 mA — — 0.7 V 4.0 V ≤ VCC ≤ 5.5 V IOL1 = 8.5 mA — — 0.6 V 2.7 V ≤ VCC ≤ 5.5 V IOL1 = 3 mA — — 0.4 V 2.7 V ≤ VCC ≤ 5.5 V IOL1 = 1.5 mA — — 0.4 V 1.8 V ≤ VCC ≤ 5.5 V IOL1 = 0.6 mA — — 0.4 V 1.6 V ≤ VCC ≤ 5.5 V IOL1 = 0.3 mA P008 to P015, P212, P213 VOL2 — — 0.7 V 4.0 V ≤ VCC ≤ 5.5 V IOL2 = 8.5 mA — — 0.5 V 2.7 V ≤ VCC < 4.0 V IOL2 = 1.5 mA — — 0.4 V 1.8 V ≤ VCC < 2.7 V IOL2 = 0.6 mA — — 0.4 V 1.6 V ≤ VCC < 1.8 V IOL2 = 0.4 mA P913, P914 VOL3 — — 2.0 V 4.0 V ≤ VCC ≤ 5.5 V IOL3 = 15 mA — — 0.4 V 4.0 V ≤ VCC ≤ 5.5 V IOL3 = 5 mA — — 0.4 V 2.7 V ≤ VCC ≤ 5.5 V IOL3 = 3 mA — — 0.4 V 1.8 V ≤ VCC ≤ 5.5 V IOL3 = 2 mA — — 0.4 V 1.6 V ≤ VCC ≤ 5.5 V IOL3 = 1 mA Note: P100 to P103, P109, P110, P112, P201, P207, P208, P212, P213 and P407 do not output high-level signals in the N-ch open-drain mode. Note: The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified. Table 2.11 I/O other characteristics (1 of 2) Conditions: VCC = 1.6 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol Min Typ Max Unit Test conditions Input leakage current, high P100 to P103, P108 to P110, P112, P200, P201, P206 to P208, P300, P407, P913, P914 ILIH1 — — 1 µA VI = VCC P008 to P015 ILIH2 — — 1 µA VI = VCC P212 to P215 ILIH3 — — 1 µA VI = VCC RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 21 of 86

Table 2.11 I/O other characteristics (2 of 2) Conditions: VCC = 1.6 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol Min Typ Max Unit Test conditions Input leakage current, low P100 to P103, P108 to P110, P112, P200, P201, P206 to P208, P300, P407, P913, P914 ILIL1 — — -1 µA VI = VSS P008 to P015 ILIL2 — — -1 µA VI = VSS P212 to P215 ILIL3 — — -1 µA VI = VSS On-chip pull-up resistance P100 to P103, P108 to P110, P112, P201, P206 to P208, P212, P213, P300, P407 RU 10 20 100 kΩ VI = VSS In input port Input capacitance P200 Cin — — 30 pF Vin = 0 V, f = 1 MHz, Ta = 25°COther input pins — — 15 Note: The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified. RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 22 of 86

2.3.2 Operating and Standby Current

Table 2.12 Operating and standby current (1) (1 of 2) Conditions: VCC = 1.6 to 5.5 V Parameter Symbol Typ*5 Max Unit Test Conditions Supply current*1 High- speed mode*2 Normal mode All peripheral clocks disabled, CoreMark code executing from flash ICLK = 32 MHz Icc 2.7 — mA — All peripheral clocks enabled, CoreMark code executing from flash*6 ICLK = 32 MHz — 5.0 — Sleep mode All peripheral clocks disabled ICLK = 32 MHz 0.82 — — All peripheral clocks enabled*6 ICLK = 32 MHz — 2.7 — Middle- speed mode*2 Normal mode All peripheral clocks disabled, CoreMark code executing from flash ICLK = 24 MHz 2.1 — — ICLK = 16 MHz 1.5 — — ICLK = 8 MHz 1.0 — — ICLK = 4 MHz 0.70 — — All peripheral clocks enabled, CoreMark code executing from flash*6 ICLK = 24 MHz — 3.8 — ICLK = 16 MHz — 2.7 — ICLK = 8 MHz — 1.6 — ICLK = 4 MHz — 1.1 — Sleep mode All peripheral clocks disabled ICLK = 24 MHz 0.67 — — ICLK = 16 MHz 0.61 — — ICLK = 8 MHz 0.50 — — ICLK = 4 MHz 0.44 — — All peripheral clocks enabled*6 ICLK = 24 MHz — 2.1 — ICLK = 16 MHz — 1.6 — ICLK = 8 MHz — 1.1 — ICLK = 4 MHz — 0.8 — Low- speed mode*3 Normal mode All peripheral clocks disabled, CoreMark code executing from flash ICLK = 2 MHz 180 — µA — All peripheral clocks enabled, CoreMark code executing from flash*6 ICLK = 2 MHz — 323 — Sleep mode All peripheral clocks disabled ICLK = 2 MHz 47 — — All peripheral clocks enabled*6 ICLK = 2 MHz — 161 — RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 23 of 86

Table 2.12 Operating and standby current (1) (2 of 2) Conditions: VCC = 1.6 to 5.5 V Parameter Symbol Typ*5 Max Unit Test Conditions Supply current*1 Subosc- speed mode*4 Normal mode Peripheral clocks disabled ICLK = 32.768 kHz Ta = -40°C Icc 3.3 — µA — Ta = 25°C 3.7 — Ta = 50°C 3.9 — Ta = 70°C 4.3 — Ta = 85°C 4.8 — Ta = 105°C 6.2 — Peripheral clocks enabled*7 ICLK = 32.768 kHz Ta = -40°C — 7.2 Ta = 25°C — 7.9 Ta = 50°C — 9.6 Ta = 70°C — 13.0 Ta = 85°C — 18.8 Ta = 105°C — 36.5 Sleep mode Peripheral clocks disabled ICLK = 32.768 kHz Ta = -40°C 1.0 — — Ta = 25°C 1.3 — Ta = 50°C 1.5 — Ta = 70°C 1.8 — Ta = 85°C 2.2 — Ta = 105°C 3.2 — Peripheral clocks enabled*7 ICLK = 32.768 kHz Ta = -40°C — 4.8 Ta = 25°C — 5.4 Ta = 50°C — 7.0 Ta = 70°C — 10.5 Ta = 85°C — 16.1 Ta = 105°C — 33.3 Note 1. Supply current is the total current flowing into VCC. Supply current values apply when internal pull-up MOSs are in the off state and these values do not include output charge/discharge current from any of the pins. Note 2. The clock source is high-speed on-chip oscillator (HOCO). Note 3. The clock source is middle-speed on-chip oscillator (MOCO). Note 4. The clock source is the Sub-clock oscillator (SOSC) and CMC.SODRV[1:0] are 10b (Low power mode 2). Note 5. VCC = 3.3 V. Note 6. Includes operating current for PCLBUZ, TAU, SAU, and IICA functions only. For other peripheral operating currents, please add the current in Peripheral Functions Supply current in Table 2.14. Note 7. Includes operating current for PCLBUZ, TAU and SAU functions only. For other peripheral operating currents, please add the current in Table 2.14. Sub-clock Oscillator Characteristics. RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 24 of 86

Table 2.13 Operating and standby current (2) Conditions: VCC = 1.6 to 5.5 V Parameter Symbol Typ*3 Max Unit Test conditions Supply current Software Standby mode*2 Peripheral modules stop PSMCR.RA MSD[1:0] are 00b All SRAMs (0x2000_4000 to 0x2000_6FFF) are on Ta = -40°C Icc 0.20 1.1 µA — Ta = 25°C 0.20 1.1 Ta = 50°C 0.30 2.4 Ta = 70°C 0.50 5.5 Ta = 85°C 0.80 11 Ta = 105°C 1.8 28 PSMCR.RA MSD[1:0] are 11b Only 4KB SRAM (0x2000_4000 to 0x2000_4FFF) is on Ta = 25°C 0.20 1.1 Ta = 50°C 0.30 2.4 Ta = 70°C 0.50 5.0 Ta = 85°C 0.70 10 Ta = 105°C 1.7 25 Note 1. Supply current is the total current flowing into VCC. Supply current values apply when internal pull-up MOSs are in the off state and these values do not include output charge/discharge current from any of the pins. Note 2. The IWDT and LVD are not operating. Note 3. VCC = 3.3 V. RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 25 of 86

Table 2.14 Peripheral Functions Supply current Conditions: VCC = 1.6 to 5.5 V Parameter Symbol Typ*12 Max Unit Test conditions Peripheral Functions Supply current*1 High-speed on chip oscillator operating current*1 OFS1.HOCOFRQ1[2:0] are 010b IHOCO 320 — µA — Middle-speed on chip oscillator operating current*1 IMOCO 20 — µA — Low-speed on chip oscillator operating current*1 ILOCO 0.24 — µA — Main-clock oscillator CMC.MODRV is 0 fMOSC = 10MHz IMOSC 160 — µA — CMC.MODRV is 1 fMOSC = 20MHz 330 — µA — Sub-clock oscillator SBYCR.RTCLPC is 1 CMC.SODRV[1:0] are 11b (Low power mode 3) ISOSC 0.13 — µA — CMC.SODRV[1:0] are 10b (Low power mode 2) 0.34 — µA — CMC.SODRV[1:0] are 00b (Low power mode 1) 0.49 — µA — CMC.SODRV[1:0] are 01b (Normal mode) 0.62 — µA — SBYCR.RTCLPC is 0 CMC.SODRV[1:0] are 11b (Low power mode 3) 0.30 — µA CMC.SODRV[1:0] are 10b (Low power mode 2) 0.51 — µA CMC.SODRV[1:0] are 00b (Low power mode 1) 0.65 — µA CMC.SODRV[1:0] are 01b (Normal mode) 0.80 — µA RTC*1*2*3 RTCC0.RTC128EN is 0 IRTC 0.006 — µA — RTCC0.RTC128EN is 1 0.001 — µA — 32-bit interval timer operating current*1*2*4 IIT 0.06 — µA — Independent watchdog timer operating current*1*2*5 fLOCO = 32.768 kHz (typ.) IIWDT 0.03 — µA — A/D converter operating current*1*6 When conversion at maximum speed Normal mode, VREFH0 = VCC = 5.0 V IADC 0.81 1.6 mA — Low voltage mode, VREFH0 = VCC = 3.0 V 0.46 0.75 mA — VREFH0 current*7 VREFH0 = 5.0 V IADREF 62 — µA — A/D converter internal reference voltage current*1 IADREF 82 — µA — Temperature sensor operating current*1 ITMPS 100 — µA — LVD operating current*1 LVD0 is enabled*8 ILVD0 0.03 — µA — LVD1 is enabled*9 ILVD1 0.03 — µA — Self-programming operating current*1*10 IFSP — 12.2 mA — Data flash rewrite operating current*1*11 IBGO — 12.2 mA — Operating current of the true random number generator*1 ITRNG 1.1 — mA — DTC Data transfer to RAM IDTC 1.82 — mA — Note 1. This current flows into VCC. Note 2. The listed currents apply when the high-speed on-chip oscillator (HOCO), middle-speed on-chip oscillator (MOCO), and Main clock oscillator (MOSC) are stopped. Note 3. This current flows into the realtime clock (RTC). It does not include the operating current of the low-speed on-chip oscillator (LOCO) or the Sub-clock oscillator (SOSC). The supply current of the RA0 microcontrollers is the sum of either Icc, and IRTC. RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 26 of 86

When the low-speed on-chip oscillator (LOCO) is selected, ILOCO should be included in the supply current. When the Sub-clock oscillator (SOSC) is selected, ISOSC should be included in the supply current. Note 4. This current only flows to the 32-bit interval timer. It does not include the operating current of the low-speed on-chip oscillator (LOCO) or Sub-clock oscillator (SOSC). The supply current of the RA0 microcontrollers is the sum of either Icc and IIT. When the low-speed on-chip oscillator (LOCO) is selected, ILOCO should be included in the supply current. When the Sub-clock oscillator (SOSC) is selected, ISOSC should be included in the supply current. Note 5. This current only flows to the independent watchdog timer. It does not include the operating current of the low-speed on-chip oscillator (LOCO) . The supply current of the RA0 microcontrollers is the sum of either Icc, IIWDT and ILOCO. Note 6. This current only flows to the A/D converter. The supply current of the RA0 microcontrollers is the sum of Icc and IADC when the A/D converter is operating or in the SLEEP mode. Note 7. This current flows into VREFH0. Note 8. This current only flows to the LVD0 circuit. The supply current of the RA0 microcontrollers is the sum of Icc and ILVD0 when the LVD0 circuit is in operation. Note 9. This current only flows to the LVD1 circuit. The supply current of the RA0 microcontrollers is the sum of Icc and ILVD1 when the LVD1 circuit is in operation. Note 10. This current only flows during self programming. Note 11. This current only flows while the data flash memory is being rewritten. Note 12. VCC = 3.3 V.

2.3.3 Thermal Characteristics

Maximum value of junction temperature (Tj) must not exceed the value specified in the section 2.1.1. Tj/Ta Definition. Tj is calculated by either of the following equations.

Tj = Ta + θja × Total power consumption
Tj = Tt + Ψjt × Total power consumption Tj : Junction Temperature (°C) Ta : Ambient Temperature (°C) Tt : Top Center Case Temperature (°C) θja : Thermal Resistance of “Junction”-to-“Ambient” (°C/W) Ψjt : Thermal Resistance of “Junction”-to-“Top Center Case” (°C/W)
Total power consumption = V oltage × (Leakage current + Dynamic current)
Leakage current of IO = Σ (IOL × VOL) /V oltage + Σ (|IOH| × |VCC – VOH|) /V oltage
Dynamic current of IO = Σ IO (Cin + Cload) × IO switching frequency × V oltage Cin: Input capacitance Cload: Output capacitance Regarding θja and Ψjt, see Table 2.15. Table 2.15 Thermal Resistance Parameter Package Symbol Value*1 Unit Test conditions Thermal Resistance 32-pin LQFP θja 68.4 ℃/W JESD 51-2 and 51-7 compliant32-pin HWQFN 24.8 24-pin HWQFN 25.3 20-pin LSSOP 64.2 20-pin TSSOP 72.8 16-pin HWQFN 30.7 32-pin LQFP Ψjt 7.87 ℃/W JESD 51-2 and 51-7 compliant32-pin HWQFN 0.38 24-pin HWQFN 0.39 20-pin LSSOP 3.34 20-pin TSSOP 1.86 16-pin HWQFN 0.48 RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 27 of 86

Note 1. The values are reference values when the 4-layer board is used. Thermal resistance depends on the number of layers or size of the board. For details, refer to the JEDEC standards.

2.4 AC Characteristics

Table 2.16 AC characteristics Conditions: VCC = 1.6 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol Min Typ Max Unit Test conditions Instruction cycle (minimum instruction execution time) Main system clock (FMAIN) operation High- speed mode TCY 0.03125 — 1 µs 1.8 V ≤ VCC ≤ 5.5 V 0.25 — 1 µs 1.6 V ≤ VCC < 1.8 V Middle- speed mode 0.04167 — 1 µs 1.8 V ≤ VCC ≤ 5.5 V 0.25 — 1 µs 1.6 V ≤ VCC < 1.8 V Low-speed mode 0.5 — 1 µs 1.6 V ≤ VCC ≤ 5.5 V In the self-programming mode High- speed mode 0.03125 — 1 µs 1.8 V ≤ VCC ≤ 5.5 V Middle- speed mode 0.04167 — 1 µs 1.8 V ≤ VCC ≤ 5.5 V External system clock frequency fEX 1.0 — 20.0 MHz 1.8 V ≤ VCC ≤ 5.5 V 1.0 — 4.0 MHz 1.6 V ≤ VCC < 1.8 V External system clock input high-level width, low-level width tEXHtEXL 24 — — ns 1.8 V ≤ VCC ≤ 5.5 V 120 — — ns 1.6 V ≤ VCC < 1.8 V TI00 to TI07 input high-level width, low-level width tTIH tTIL 1/fMCK +10*1 — — ns TO00 to TO07 output frequency High- speed mode Middle- speed mode fTO — — 16 MHz 4.0 V ≤ VCC ≤ 5.5 V — — 8 MHz 2.7 V ≤ VCC < 4.0 V — — 4 MHz 1.8 V ≤ VCC < 2.7 V — — 2 MHz 1.6 V ≤ VCC < 1.8 V Low-speed mode — — 2 MHz 1.6 V ≤ VCC ≤ 5.5 V PCLBUZ0, PCLBUZ1 output frequency High- speed mode Middle- speed mode fPCL — — 16 MHz 4.0 V ≤ VCC ≤ 5.5 V — — 8 MHz 2.7 V ≤ VCC < 4.0 V — — 4 MHz 1.8 V ≤ VCC < 2.7 V — — 2 MHz 1.6 V ≤ VCC < 1.8 V Low-speed mode — — 2 MHz 1.6 V ≤ VCC ≤ 5.5 V Interrupt input high-level width, low-level width NMI/IRQ0, IRQ1 to IRQ5 fIRQH fIRQL 1 — — µs 1.6 V ≤ VCC ≤ 5.5 V Note 1. fMCK: Timer array unit operating clock frequency To set this operating clock, use the CKS[1:0] bits of the timer mode register 0n (TMR0n). m: Unit number (m = 0), n: Channel number (n = 0 to 7) RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 28 of 86

Figure 2.7 TI/TO timing IRQ0/NMI, IRQ1 to IRQ5 t IRQL t IRQH Figure 2.8 IRQ interrupt input timing

2.4.1 Reset Timing

Table 2.17 Reset timing Parameter Symbol Min Typ Max Unit Test conditions RES pulse width At power-on*3 tRESWP 9.9 — — ms — Not at power-on tRESW 10 — — µs — Wait time after RES cancellation (at power-on) LVD0 enabled*1 tRESWT — 0.506 0.694 ms — LVD0 disabled*2 — 0.201 0.335 ms — Wait time after RES cancellation (during powered-on state) LVD0 enabled*1 tRESWT2 — 0.476 0.616 ms — LVD0 disabled*2 — 0.170 0.257 ms — Internal reset by Independent watch dog timer reset, SRAM parity error reset, software reset tRESW2 — 0.04 0.041 ms — Note 1. When OFS1.LVDAS = 0. Note 2. When OFS1.LVDAS = 1. Note 3. When RES pin is not used as the external reset input, this specification can be ignore. RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 31 of 86

2.4.2 Wakeup Time

Table 2.18 Timing of recovery from low power modes (1) Parameter Symbol Min Typ Max Unit Test conditions Recovery time from Software Standby mode*1 High-speed mode Crystal resonator connected to main clock oscillator System clock source is main clock oscillator (20 MHz)*2 VCC = 1.8 V to 5.5 V tSBYMC — 1.64 — ms Figure 2.12 System clock source is main clock oscillator (4 MHz)*2 VCC = 1.6 V to 1.8 V — 8.19 — ms External clock input to main clock oscillator System clock source is main clock oscillator (20 MHz) VCC = 1.8 V to 5.5 V tSBYEX — 2.8 2.8 µs System clock source is main clock oscillator (4 MHz) VCC = 1.6 V to 1.8 V — 13.8 14.0 µs System clock source is HOCO System clock source is HOCO (32 MHz) VCC = 1.8 V to 5.5 V SBYCR.FWKUP = 0 tSBYHO — 4.2 4.6 µs System clock source is HOCO (32 MHz) VCC = 1.8 V to 5.5 V SBYCR.FWKUP = 1 — 0.9 1.1 µs System clock source is HOCO (4 MHz) VCC = 1.6 V to 1.8 V — 5.2 5.6 µs System clock source is MOCO (4 MHz) tSBYMO — 3.3 4.2 µs Note 1. The division ratio of ICLK is the minimum division ratio within the allowable frequency range. The recovery time is determined by the system clock source. Note 2. The Oscillation Stabilization Time Select Register (OSTS) is set to 0x05. RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 33 of 86

Table 2.19 Timing of recovery from low power modes (2) Parameter Symbol Min Typ Max Unit Test conditions Recovery time from Software Standby mode*1 Middle-speed mode Crystal resonator connected to main clock oscillator System clock source is main clock oscillator (20 MHz)*2 VCC = 1.8 V to 5.5 V tSBYMC — 1.64 — ms Figure 2.12 System clock source is main clock oscillator (4 MHz)*2 VCC = 1.6 V to 1.8 V — 8.19 — ms External clock input to main clock oscillator System clock source is main clock oscillator (20 MHz) VCC = 1.8 V to 5.5 V tSBYEX — 2.8 2.8 µs System clock source is main clock oscillator (4 MHz) VCC = 1.6 V to 1.8 V — 13.8 14.0 µs System clock source is HOCO System clock source is HOCO (24 MHz) VCC = 1.8 V to 5.5 V tSBYHO — 5.1 5.5 µs System clock source is HOCO (3 MHz) VCC = 1.6 V to 1.8 V — 5.6 6.1 µs System clock source is MOCO (4 MHz) tSBYMO — 3.3 4.2 µs Note 1. The division ratio of ICLK is the minimum division ratio within the allowable frequency range. The recovery time is determined by the system clock source. Note 2. The Oscillation Stabilization Time Select Register (OSTS) is set to 0x05. Table 2.20 Timing of recovery from low power modes (3) Parameter Symbol Min Typ Max Unit Test conditions Recovery time from Software Standby mode*1 Low-speed mode Crystal resonator connected to main clock oscillator System clock source is main clock oscillator (2 MHz)*2 tSBYMC — 4.1 — ms Figure 2.12 External clock input to main clock oscillator System clock source is main clock oscillator (2 MHz)*2 tSBYEX — 27.5 28.0 µs System clock source is MOCO (2 MHz) tSBYMO — 6.0 7.5 µs Note 1. The division ratio of ICLK is the minimum division ratio within the allowable frequency range. The recovery time is determined by the system clock source. Note 2. The Oscillation Stabilization Time Select Register (OSTS) is set to 0x05. Crystal resonator frequency is 8 MHz and the MOSC Clock Division Register (MOSCDIV) is set to 0x02. Table 2.21 Timing of recovery from low power modes (4) Parameter Symbol Min Typ Max Unit Test conditions Recovery time from Software Standby mode*1 Subosc-speed mode System clock source is sub- clock oscillator (32.768 kHz) SBYCR.RTCLPC = 0 tSBYSC — 0.29 0.31 ms Figure 2.12 SBYCR.RTCLPC = 1 — 0.32 0.34 ms System clock source is LOCO (32.768 kHz) tSBYLO — 0.29 0.36 ms Note 1. The sub-clock oscillator or LOCO itself continues oscillating in Software Standby mode during Subosc-speed mode. RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 34 of 86

t SBYSC , t SBYLO Oscillator ICLK IRQ Software Standby mode t SBYMC, t SBYEX, t SBYMO , t SBYHO Figure 2.12 Software Standby mode cancellation timing Table 2.22 Timing of recovery from low power modes (5) Parameter Symbol Min Typ Max Unit Test conditions Recovery time from Software Standby mode to Snooze mode High-speed mode System clock source is HOCO SBYCR.FWKUP = 0 tSNZ — 4.1 4.4 µs Figure 2.13 SBYCR.FWKUP = 1 — 0.9 1.0 µs Middle-speed mode System clock source is HOCO (24 MHz) VCC = 1.8 V to 5.5 V tSNZ — 4.2 4.4 µs Middle-speed mode System clock source is HOCO (3 MHz) VCC = 1.6 V to 1.8 V tSNZ — 4.8 5.3 µs Low-speed mode System clock source is MOCO (2 MHz) tSNZ — 4.0 5.4 µs RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 35 of 86

Software Standby mode Snooze mode Figure 2.13 Recovery timing from Software Standby mode to Snooze mode

2.5 Peripheral Function Characteristics

2.5.1 Serial Array Unit (SAU)

Table 2.23 In UART communications with devices operating at same voltage levels Conditions: VCC = 1.6 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol High-speed mode Middle-speed mode Low-speed mode Unit Test Transfer rate*1 1.6 V ≤ VCC ≤ 5.5 V — — fMCK/6 — fMCK/6 — fMCK/6 bps Figure 2.15 Theoretical value of the maximum transfer rate fMCK = PCLKB*2 — 5.3 — 4 — 0.33 Mbps Note 1. The transfer rate in SNOOZE mode is within the range from 4800 to 9600 bps when SBYCR.FWKUP = 0, and within the range from 4800 to 115200 bps when SBYCR.FWKUP = 1. Note 2. The maximum operating frequencies of the peripheral module clock (PCLKB) are as follows. High-speed mode: 32 MHz (1.8 V ≤ VCC ≤ 5.5 V), 4 MHz (1.6 V ≤ VCC ≤ 5.5 V) Middle-speed mode: 24 MHz (1.8 V ≤ VCC ≤ 5.5 V), 4 MHz (1.6 V ≤ VCC ≤ 5.5 V) Low-speed mode: 2 MHz (1.6 V ≤ VCC ≤ 5.5 V) Note: Select the normal input buffer for the RXDq pin and the normal output mode for the TXDq pin by using the Port gh Pin Function Select Register (PghPFS_A.PIM and PghPFS_A.NCODR). gh: Port number (gh = 100, 101, 109, 110, 212, 213) RA0 microcontroller User device TXDq RXDq RX TX Figure 2.14 Connection in the UART communications with devices operating at same voltage levels RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 36 of 86

Table 2.25 In simplified SPI communications in the master mode with devices operating at same voltage levels with the internal SCKp clock Conditions: VCC = 1.6 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol High-speed mode Middle-speed mode Low-speed mode Unit Test SCKp cycle time tKCY1 ≥ 4/ PCLKB 2.7 V ≤ VCC ≤ 5.5 V tKCY1 125 — 166 — 2000 — ns Figure 2.17 Figure 2.18 2.4 V ≤ VCC ≤ 5.5 V 250 — 250 — 2000 — ns 1.8 V ≤ VCC ≤ 5.5 V 500 — 500 — 2000 — ns 1.6 V ≤ VCC ≤ 5.5 V 1000 — 1000 — 2000 — ns SCKp high-/ low-level width 4.0 V ≤ VCC ≤ 5.5 V tKH1, tKL1 tKCY1/2 - 12 — tKCY1/2 - 21 — tKCY1/2 - 50 — ns 2.7 V ≤ VCC ≤ 5.5 V tKCY1/2 - 18 — tKCY1/2 - 25 — tKCY1/2 - 50 — ns 2.4 V ≤ VCC ≤ 5.5 V tKCY1/2 - 38 — tKCY1/2 - 38 — tKCY1/2 - 50 — ns 1.8 V ≤ VCC ≤ 5.5 V tKCY1/2 - 50 — tKCY1/2 - 50 — tKCY1/2 - 50 — ns 1.6 V ≤ VCC ≤ 5.5 V tKCY1/2 - 100 — tKCY1/2 - 100 — tKCY1/2 - 100 — ns SIp setup time (to SCKp↑)*1 4.0 V ≤ VCC ≤ 5.5 V tSIK1 44 — 54 — 110 — ns 2.7 V ≤ VCC ≤ 5.5 V 44 — 54 — 110 — ns 2.4 V ≤ VCC ≤ 5.5 V 75 — 75 — 110 — ns 1.8 V ≤ VCC ≤ 5.5 V 110 — 110 — 110 — ns 1.6 V ≤ VCC ≤ 5.5 V 220 — 220 — 220 — ns SIp hold time (from SCKp↑)*1 1.6 V ≤ VCC ≤ 5.5 V tKSI1 19 — 19 — 19 — ns Delay time from SCKp↓ to SOp output*2 1.6 V ≤ VCC ≤ 5.5 V C = 30 pF*3 tKSO1 — 25 — 25 — 25 ns Note 1. This setting applies when SCRmn.DCP[1:0] = 00b or 11b. The setting for the SIp setup time becomes to SCKp↓ and that for the SIp hold time becomes from SCKp↓ when SCRmn.DCP[1:0] = 01b or 10b. Note 2. This setting applies when SCRmn.DCP[1:0] = 00b or 11b. The setting for the delay time to SOp output becomes from SCKp↑ when SCRmn.DCP[1:0] = 01b or 10b. Note 3. C is the load capacitance of the SCKp and SOp output lines. Note: Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using the Port gh Pin Function Select Register (PghPFS_A.PIM and PghPFS_A.NCODR). Note: ● p: Simplified SPI number (p = 00, 11, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 3), gh: Port number (gh= 100 to 103, 109, 110, 112, 201, 212, 213, 407)

f MCK: Serial array unit operation clock frequency To set this operating clock, use the CKS bit in the serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 03, 10) RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 38 of 86

Table 2.26 In simplified SPI communications in the slave mode with devices operating at same voltage levels with the SCKp external clock Conditions: VCC = 1.6 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Item Conditions Symbol High-speed mode Middle-speed mode Low-speed mode Unit Test SCKp cycle time*4 4.0 V ≤ VCC ≤ 5.5 V 20 MHz < fMCK tKCY2 8/fMCK — 8/fMCK — — — ns Figure 2.17 Figure 2.18 fMCK ≤ 20 MHz 6/fMCK — 6/fMCK — 6/fMCK — ns 2.7 V ≤ VCC ≤ 5.5 V 16 MHz < fMCK 8/fMCK — 8/fMCK — — — ns fMCK ≤ 16 MHz 6/fMCK — 6/fMCK — 6/fMCK — ns 2.4 V ≤ VCC ≤ 5.5 V Greater of: 6/fMCK or 500 — Greater of: 6/ fMCK or 500 — Greater of: 6/ fMCK or 500 — ns 1.8 V ≤ VCC ≤ 5.5 V Greater of: 6/fMCK or 750 — Greater of: 6/ fMCK or 750 — Greater of: 6/ fMCK or 750 — ns 1.6 V ≤ VCC ≤ 5.5 V Greater of: 6/fMCK or 1500 — Greater of: 6/ fMCK or 1500 — Greater of: 6/ fMCK or 1500 — ns SCKp high-/ low-level width 4.0 V ≤ VCC ≤ 5.5 V tKH2, tKL2 tKCY2/2 - 7 — tKCY2/2 - 7 — tKCY2/2 - 7 — ns 2.7 V ≤ VCC ≤ 5.5 V tKCY2/2 - 8 — tKCY2/2 - 8 — tKCY2/2 - 8 — ns 1.8 V ≤ VCC ≤ 5.5 V tKCY2/2 - 18 — tKCY2/2 - 18 — tKCY2/2 - 18 — ns 1.6 V ≤ VCC ≤ 5.5 V tKCY2/2 - 66 — tKCY2/2 - 66 — tKCY2/2 - 66 — ns SIp setup time (to SCKp↑)*1 2.7 V ≤ VCC ≤ 5.5 V tSIK2 1/fMCK + 20 — 1/fMCK + 30 — 1/fMCK + 30 — ns 1.8 V ≤ VCC ≤ 5.5 V 1/fMCK + 30 — 1/fMCK + 30 — 1/fMCK + 30 — ns 1.6 V ≤ VCC ≤ 5.5 V 1/fMCK + 40 — 1/fMCK + 40 — 1/fMCK + 40 — ns SIp hold time (from SCKp↑)*1 1.8 V ≤ VCC ≤ 5.5 V tKSI2 1/fMCK + 31 — 1/fMCK + 31 — 1/fMCK + 31 — ns 1.6 V ≤ VCC ≤ 5.5 V 1/fMCK + 250 — 1/fMCK + 250 — 1/fMCK + 250 — ns Delay time from SCKp↓ to SOp output*2 C = 30 pF*3 2.7 V ≤ VCC ≤ 5.5 V tKSO2 — 2/fMCK + — 2/fMCK + 110 — 2/fMCK + 110 ns 2.4 V ≤ VCC ≤ 5.5 V — 2/fMCK + — 2/fMCK + 110 — 2/fMCK + 110 ns 1.8 V ≤ VCC ≤ 5.5 V — 2/fMCK + 110 — 2/fMCK + 110 — 2/fMCK + 110 ns 1.6 V ≤ VCC ≤ 5.5 V — 2/fMCK + 220 — 2/fMCK + 220 — 2/fMCK + 220 ns Note 1. This setting applies when SCRmn.DCP[1:0] = 00b or 11b. The setting for the SIp setup time becomes to SCKp↓ and that for the SIp hold time becomes from SCKp↓ when SCRmn.DCP[1:0] = 01b or 10b. Note 2. This setting applies when SCRmn.DCP[1:0] = 00b or 11b. The setting for the delay time to SOp output becomes from SCKp↑ when SCRmn.DCP[1:0] = 01b or 10b. Note 3. C is the load capacitance of the SOp output line. Note 4. Transfer rate in the SNOOZE mode is 1 Mbps at the maximum. Note: Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using the Port gh Pin Function Select Register (PghPFS_A.PIM and PghPFS_A.NCODR). Note: ● p: Simplified SPI number (p = 00, 11, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 3), gh: Port number (gh = 100 to 103, 109, 110, 112, 201, 212, 213, 407)

f MCK: Serial array unit operation clock frequency To set this operating clock, use the CKS bit in the serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 03, 10) RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 39 of 86

t KCY1, 2 t KH1, 2 t KL1, 2 t SIK1, 2 t KSI1, 2 t KSO1, 2 Input data Output data Figure 2.18 Timing of serial transfer in the simplified SPI communications with devices operating at same voltage levels when SCRmn.DCP[1:0] = 01b or 10b Note: ● p: Simplified SPI number (p = 00, 11, 20)

m: Unit number, n: Channel number (mn = 00, 03, 10) RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 41 of 86

Table 2.27 In simplified IIC communications with devices operating at same voltage levels (1 of 2) Conditions: VCC = 1.6 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol High-speed mode Middle-speed mode Low-speed mode Unit Test SCLr clock frequency 2.7 V ≤ VCC ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ fSCL — 1000*1 — 1000*1 — 400*1 kHz Figure 2.20 1.8 V ≤ VCC ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 1.8 V ≤ VCC < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 1.6 V ≤ VCC < 1.8 V, Cb = 100 pF, Rb = 5 kΩ Hold time when SCLr is low 2.7 V ≤ VCC ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ tLOW 475 — 475 — 1150 — ns 1.8 V ≤ VCC ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 1150 — 1150 — 1150 — ns 1.8 V ≤ VCC < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 1550 — 1550 — 1550 — ns 1.6 V ≤ VCC < 1.8 V, Cb = 100 pF, Rb = 5 kΩ 1850 — 1850 — 1850 — ns Hold time when SCLr is high 2.7 V ≤ VCC ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ tHIGH 475 — 475 — 1150 — ns 1.8 V ≤ VCC ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 1150 — 1150 — 1150 — ns 1.8 V ≤ VCC < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 1550 — 1550 — 1550 — ns 1.6 V ≤ VCC < 1.8 V, Cb = 100 pF, Rb = 5 kΩ 1850 — 1850 — 1850 — ns RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 42 of 86

Table 2.27 In simplified IIC communications with devices operating at same voltage levels (2 of 2) Conditions: VCC = 1.6 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol High-speed mode Middle-speed mode Low-speed mode Unit Test Data setup time (reception) 2.7 V ≤ VCC ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ tSU:DAT 1/fMCK + 85*2 — 1/fMCK +85*2 — 1/fMCK +145*2 — ns Figure 2.20 1.8 V ≤ VCC ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 1/fMCK + 145*2 — 1/fMCK + 145*2 — 1/fMCK +145*2 — ns 1.8 V ≤ VCC < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 1/fMCK + 230*2 — 1/fMCK + 230*2 — 1/fMCK + 230*2 — ns 1.6 V ≤ VCC < 1.8 V, Cb = 100 pF, Rb = 5 kΩ 1/fMCK + 290*2 — 1/fMCK + 290*2 — 1/fMCK + 290*2 — ns Data hold time (transmission) 2.7 V ≤ VCC ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ tHD:DAT 0 305 0 305 0 305 ns 1.8 V ≤ VCC ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 0 355 0 355 0 355 ns 1.8 V ≤ VCC < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 0 405 0 405 0 405 ns 1.6 V ≤ VCC < 1.8 V, Cb= 100 pF, Rb = 5 kΩ 0 405 0 405 0 405 ns Note 1. The listed times must be no greater than fMCK/4. Note 2. Set fMCK so that it will not exceed the hold time when SCLr is low or high. Note: Select the normal input buffer and the N-ch open drain output [withstand voltage of VCC] mode for the SDAr pin and the normal output mode for the SCLr pin by using the Port gh Pin Function Select Register (PghPFS_A.PIM and PghPFS_A.NCODR). RA0 microcontroller User device SDAr SCLr SDA SCL VCC R b Figure 2.19 Connection in the simplified IIC communications with devices operating at same voltage levels RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 43 of 86

tHD:DAT tSU:DAT Figure 2.20 Timing of serial transfer in the simplified IIC communications with devices operating at same voltage levels Note: ● R b[Ω]: Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance

r: IIC number (r = 00, 11, 20), gh: Port number (gh = 100, 102, 110, 112, 201, 212, 407)
f MCK: Serial array unit operation clock frequency To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 03, 10) Table 2.28 In UART communications with devices operating at different voltage levels (1.8 V, 2.5 V, 3 V) (1) Conditions: VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol High-speed mode Middle-speed mode Low-speed mode Unit Test Transfer rate Reception 4.0 V ≤ VCC ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V — — fMCK/6*1 — fMCK/6*1 — fMCK/6*1 bps Figure 2.22 Theoretical value of the maximum transfer rate fMCK = PCLKB*3 — 5.3 — 4 — 0.33 Mbps 2.7 V ≤ VCC < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V — fMCK/6*1 — fMCK/6*1 — fMCK/6*1 bps Theoretical value of the maximum transfer rate fMCK*3 = PCLKB*3 — 5.3 — 4 — 0.33 Mbps 1.8 V ≤ VCC < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V — fMCK/6*1 bps Theoretical value of the maximum transfer rate fMCK = PCLKB*3 — 5.3 — 4 — 0.33 Mbps Note 1. Transfer rate in the SNOOZE mode is within the range from 4800 to 9600 bps. Note 2. Use this rate with VCC ≥ Vb. Note 3. The maximum operating frequencies of the system clock (PCLKB) are: High-speed mode: 32 MHz (1.8 V ≤ VCC ≤ 5.5 V), 4 MHz (1.6 V ≤ VCC ≤ 5.5 V) Middle-speed mode: 24 MHz (1.8 V ≤ VCC ≤ 5.5 V), 4 MHz (1.6 V ≤ VCC ≤ 5.5 V) Low-speed mode: 2 MHz (1.6 V ≤ VCC ≤ 5.5 V) Note: Select the TTL input buffer for the RXDq pin and the N-ch open drain output [withstand voltage of VCC] mode for the TXDq pin by using the Port gh Pin Function Select Register (PghPFS_A.PIM and PghPFS_A.NCODR). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Note: ● V b[V]: Communication line voltage
q: UART number (q = 0 to 2), gh: Port number (gh=100, 101, 109, 110, 212, 213)
f MCK: Serial array unit operation clock frequency RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 44 of 86

To set this operating clock, use the CKS bit in the serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01, 02, 03, 10, 11)

Communications by using P212 and P213 with devices operating at different voltage levels are not possible since P212PFS_A and P213PFS_A registers do not have PIM bit. Table 2.29 In UART communications with devices operating at different voltage levels (1.8 V, 2.5 V, 3 V) (2) Conditions: VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol High-speed mode Middle-speed mode Low-speed mode Unit Test Transfer rate Transmission 4.0 V ≤ VCC ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 1.4 kΩ, Vb = 2.7 V 2.7 V ≤ VCC < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 2.7 kΩ, Vb = 2.3 V 1.8 V ≤ VCC < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 5.5 kΩ, Vb = 1.6 V Note 1. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 4.0 V ≤ VCC ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V Maximum transfer rate = − C b × R b × ln 1 − 2.2 V b × 3 [bps] Baud rate error (theoretical value) = Transfer rate × 2 2.2 V b Transfer rate × Number of transferred bits × 100[%] This value is the theoretical value of the relative difference between the transmission and reception sides. Note 2. This rate is calculated as an example when the conditions described in the Conditions column are met. See *1 above to calculate the maximum transfer rate under conditions of the customer. Note 3. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V ≤ VCC < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V Maximum transfer rate = − C b × R b × ln 1 − 2.0 V b × 3 [bps] Baud rate error (theoretical value) = Transfer rate × 2 2.0 V b Transfer rate × Number of transferred bits × 100[%] This value is the theoretical value of the relative difference between the transmission and reception sides. Note 4. This rate is calculated as an example when the conditions described in the Conditions column are met. See *3 above to calculate the maximum transfer rate under conditions of the customer. Note 5. Use this rate with VCC ≥ Vb. Note 6. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 1.8 V ≤ VCC < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Maximum transfer rate = − C b × R b × ln 1 − 1.5 V b × 3 [bps] Baud rate error (theoretical value) = Transfer rate × 2 1.5 V b Transfer rate × Number of transferred bits × 100[%] RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 45 of 86

Table 2.30 In simplified SPI communications in the master mode with devices operating at different voltage levels (2.5 V or 3 V) with the internal SCKp clock (the ratings below are only applicable to SPI00) Conditions: VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol High-speed mode Middle-speed mode Low-speed mode Unit Test SCKp cycle time tKCY1 ≥ 2/PCLKB 4.0 V ≤ VCC ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ tKCY1 200 — 200 — 2300 — ns Figure 2.24 Figure 2.25 2.7 V ≤ VCC < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ 300 — 300 — 2300 — ns SCKp high-level width 4.0 V ≤ VCC ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ tKH1 tKCY1/2 - 50 — tKCY1/2 - 50 — tKCY1/2 - 50 — ns 2.7 V ≤ VCC < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ tKCY1/2 - 120 — tKCY1/2 - 120 — tKCY1/2 - 120 — ns SCKp low-level width 4.0 V ≤ VCC ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ tKL1 tKCY1/2 -7 — tKCY1/2 -7 — tKCY1/2 - 50 — ns 2.7 V ≤ VCC < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ tKCY1/2 - 10 — tKCY1/2 - 10 — tKCY1/2 - 50 — ns SIp setup time (to SCKp↑)*1 4.0 V ≤ VCC ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ tSIK1 58 — 58 — 479 — ns 2.7 V ≤ VCC < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ 121 — 121 — 479 — ns SIp hold time (from SCKp↑)*1 4.0 V ≤ VCC ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ tKSI1 10 — 10 — 10 — ns 2.7 V ≤ VCC < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ 10 — 10 — 10 — ns Delay time from SCKp↓ to SOp output*1 4.0 V ≤ VCC ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ tKSO1 — 60 — 60 — 60 ns 2.7 V ≤ VCC < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ — 130 — 130 — 130 ns SIp setup time (to SCKp↓)*2 4.0 V ≤ VCC ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ tSIK1 23 — 23 — 110 — ns 2.7 V ≤ VCC < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ 33 — 33 — 110 — ns SIp hold time (from SCKp↓)*2 4.0 V ≤ VCC ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ tKSI1 10 — 10 — 10 — ns 2.7 V ≤ VCC < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ 10 — 10 — 10 — ns Delay time from SCKp↑ to SOp output*2 4.0 V ≤ VCC ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ tKSO1 — 10 — 10 — 10 ns 2.7 V ≤ VCC < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ — 10 — 10 — 10 ns Note 1. This setting applies when SCRmn.DCP[1:0] = 00b or 11b. Note 2. This setting applies when SCRmn.DCP[1:0] = 01b or 10b. Note: Select the TTL input buffer for the SIp pin and the N-ch open drain output [withstand voltage of VCC] mode for the SOp pin and SCKp pin by using the Port gh Pin Function Select Register (PghPFS_A.PIM and PghPFS_A.NCODR). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Note: ● R b[Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage

p: Simplified SPI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), gh: Port number (gh = 100, 101, 102)
f MCK: Serial array unit operation clock frequency RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 47 of 86

To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00) Table 2.31 In simplified SPI communications in the master mode with devices operating at different voltage levels (1.8 V, 2.5 V, or 3 V) with the internal SCKp clock (1) Conditions: VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol High-speed mode Middle-speed mode Low-speed mode Unit Test SCKp cycle time tKCY1 ≥ 4/ PCLKB 4.0 V ≤ VCC ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ tKCY1 300 — 300 — 2300 — ns Figure 2.24 Figure 2.25 2.7 V ≤ VCC < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ 500 — 500 — 2300 — ns 1.8 V ≤ VCC < 3.3 V, Cb = 30 pF, Rb = 5.5 kΩ 1150 — 1150 — 2300 — ns SCKp high- level width 4.0 V ≤ VCC ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ tKH1 tKCY1/2 - 75 — tKCY1/2 - 75 — tKCY1/2 - 75 — ns 2.7 V ≤ VCC < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ tKCY1/2 - 170 — tKCY1/2 - 170 — tKCY1/2 - 170 — ns 1.8 V ≤ VCC < 3.3 V, Cb = 30 pF, Rb = 5.5 kΩ tKCY1/2 - 458 — tKCY1/2 - 458 — tKCY1/2 - 458 — ns SCKp low- level width 4.0 V ≤ VCC ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ tKL1 tKCY1/2 -12 — tKCY1/2 -12 — tKCY1/2 - 50 — ns 2.7 V ≤ VCC < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ tKCY1/2 - 18 — tKCY1/2 - 18 — tKCY1/2 - 50 — ns 1.8 V ≤ VCC < 3.3 V, Cb = 30 pF, Rb = 5.5 kΩ tKCY1/2 - 50 — tKCY1/2 - 50 — tKCY1/2 - 50 — ns Note 1. Use this setting with VCC ≥ Vb. Note: Select the TTL input buffer for the SIp pin and the N-ch open drain output [withstand voltage of VCC] mode for the SOp pin and SCKp pin by using the Port gh Pin Function Select Register (PghPFS_A.PIM and PghPFS_A.NCODR). For VIH and VIL, see the DC characteristics with TTL input buffer selected. RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 48 of 86

Table 2.32 In simplified SPI communications in the master mode with devices operating at different voltage levels (1.8 V, 2.5 V, or 3 V) with the internal SCKp clock (2) Conditions: VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol High-speed mode Middle-speed mode Low-speed mode Unit Test SIp setup time (to SCKp↑)*1 4.0 V ≤ VCC ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ tSIK1 81 — 81 — 479 — ns Figure 2.24 Figure 2.25 2.7 V ≤ VCC < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ 177 — 177 — 479 — ns 1.8 V ≤ VCC < 3.3 V, Cb = 30 pF, Rb = 5.5 kΩ 479 — 479 — 479 — ns SIp hold time (from SCKp↑)*1 4.0 V ≤ VCC ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ tKSI1 19 — 19 — 19 — ns 2.7 V ≤ VCC < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ 19 — 19 — 19 — ns 1.8 V ≤ VCC < 3.3 V, Cb = 30 pF, Rb = 5.5 kΩ 19 — 19 — 19 — ns Delay time from SCKp↓ to SOp output*1 4.0 V ≤ VCC ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ tKSO1 — 100 — 100 — 100 ns 2.7 V ≤ VCC < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ — 195 — 195 — 195 ns 1.8 V ≤ VCC < 3.3 V, Cb = 30 pF, Rb = 5.5 kΩ — 483 — 483 — 483 ns Note 1. This setting applies when SCRmn.DCP[1:0] = 00b or 11b. Note 2. Use this setting with VCC ≥ Vb. Note: Select the TTL input buffer for the SIp pin and the N-ch open drain output [withstand voltage of VCC] mode for the SOp pin and SCKp pin by using the Port gh Pin Function Select Register (PghPFS_A.PIM and PghPFS_A.NCODR). For VIH and VIL, see the DC characteristics with TTL input buffer selected. RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 49 of 86

p: Simplified SPI number (p = 00, 11, 20), m: Unit number, n: Channel number (mn = 00, 03, 10), gh: Port number (gh = 100 to 103, 109, 110, 112, 201, 212, 213, 407)
f MCK: Serial array unit operation clock frequency To set this operating clock, use the CKS bit in the serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 03, 10)
Communications by using P212 and P213 with devices operating at different voltage levels are not possible since P212PFS_A and P213PFS_A registers do not have PIM bit. SCKp SIp SOp Input data Output data t KCY1 t KL1 t KH1 t SIK1 t KSI1 t KSO1 Figure 2.24 Timing of serial transfer in the simplified SPI communications in the master mode with devices operating at different voltage levels when SCRmn.DCP[1:0] = 00b or 11b RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 51 of 86

Figure 2.25 Timing of serial transfer in the simplified SPI communications in the master mode with devices operating at different voltage levels when SCRmn.DCP[1:0] = 01b or 10b Note: ● p: Simplified SPI number (p = 00, 11, 20), m: Unit number, n: Channel number (mn = 00, 03, 10), gh: Port number (gh = 100 to 103, 109, 110, 112, 201, 212, 213, 407)

Communications by using P212 and P213 with devices operating at different voltage levels are not possible since P212PFS_A and P213PFS_A registers do not have PIM bit. RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 52 of 86

Table 2.34 In simplified SPI communications in the slave mode with devices operating at different voltage levels (1.8 V, 2.5 V, or 3 V) with the external SCKp clock Conditions: VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol High-speed mode Middle-speed mode Low-speed mode Unit Test SCKp cycle time*1 4.0 V ≤ VCC ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V 24 MHz < fMCK tKCY2 14/fMCK — — — — — ns Figure 2.27 Figure 2.28

20 MHz < fMCK ≤ 24 MHz 12/fMCK — 12/fMCK — — — ns

8 MHz < fMCK ≤ 20 MHz 10/fMCK — 10/fMCK — — — ns

4 MHz < fMCK ≤ 8 MHz 8/fMCK — 8/fMCK — — — ns

fMCK ≤ 4 MHz 6/fMCK — 6/fMCK — 10/fMCK — ns 2.7 V ≤ VCC < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V

24 MHz < fMCK 20/fMCK — — — — — ns

20 MHz < fMCK ≤ 24 MHz 16/fMCK — 16/fMCK — — — ns

16 MHz < fMCK ≤ 20 MHz 14/fMCK — 14/fMCK — — — ns

8 MHz < fMCK ≤ 16 MHz 12/fMCK — 12/fMCK — — — ns

fMCK ≤ 4 MHz 6/fMCK — 6/fMCK — 10/fMCK — ns 1.8 V ≤ VCC < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V*2

24 MHz < fMCK 48/fMCK — — — — — ns

20 MHz < fMCK ≤ 24 MHz 36/fMCK — 36/fMCK — — — ns

16 MHz < fMCK ≤ 20 MHz 32/fMCK — 32/fMCK — — — ns

8 MHz < fMCK ≤ 16 MHz 26/fMCK — 26/fMCK — — — ns

4 MHz < fMCK ≤ 8 MHz 16/fMCK — 16/fMCK — — — ns

fMCK ≤ 4 MHz 10/fMCK — 10/fMCK — 10/fMCK — ns SCKp high-/ low-level width 4.0 V ≤ VCC ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V tKH2, tKL2 tKCY2/2 - — tKCY2/2 - — tKCY2/2 - — ns 2.7 V ≤ VCC < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V tKCY2/2 - — tKCY2/2 - — tKCY2/2 - — ns 1.8 V ≤ VCC < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V*2 tKCY2/2 - — tKCY2/2 - — tKCY2/2 - — ns SIp setup time (to SCKp↑)*3 4.0 V ≤ VCC ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V tSIK2 1/fMCK + — 1/fMCK + — 1/fMCK + — ns 2.7 V ≤ VCC < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V 1/fMCK + — 1/fMCK + — 1/fMCK + — ns 1.8 V ≤ VCC < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V*2 1/fMCK + — 1/fMCK + — 1/fMCK + — ns SIp hold time (from SCKp↑)*3 tKSI2 1/fMCK + — 1/fMCK + — 1/fMCK + — ns Delay time from SCKp↓ to SOp output*4 4.0 V ≤ VCC ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ tKSO2 — 2/fMCK + 120 — 2/fMCK + 120 — 2/fMCK + 573 ns 2.7 V ≤ VCC < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ — 2/fMCK + 214 — 2/fMCK + 214 — 2/fMCK + 573 ns 1.8 V ≤ VCC < 3.3 V, Cb = 30 pF, Rb = 5.5 kΩ — 2/fMCK + 573 — 2/fMCK + 573 — 2/fMCK + 573 ns Note 1. Transfer rate in the SNOOZE mode: 1 Mbps (max.) Note 2. Use this setting with VCC ≥ Vb. Note 3. This setting applies when SCRmn.DCP[1:0] = 00b or 11b. The SIp setup time becomes to SCKp↓ and SIp hold time becomes from SCKp↓ when SCRmn.DCP[1:0] = 01b or 10b. Note 4. This setting applies when SCRmn.DCP[1:0] = 00b or 11b. The delay time to SOp output becomes from SCKp↑ when SCRmn.DCP[1:0] = 01b or 10b. Note: Select the TTL input buffer for the SIp pin and the N-ch open drain output [withstand voltage of VCC] mode for the SOp pin and SCKp pin by using the Port gh Pin Function Select Register (PghPFS_A.PIM and PghPFS_A.NCODR). For VIH and VIL, see the DC characteristics with TTL input buffer selected. RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 53 of 86

Figure 2.28 Timing of serial transfer in the simplified SPI communications in the slave mode with devices operating at different voltage levels when SCRmn.DCP[1:0] = 01b or 10b Note: ● p: Simplified SPI number (p = 00, 11, 20), m: Unit number, n: Channel number (mn = 00, 03, 10), gh: Port number (gh = 100 to 103, 109, 110, 112, 201, 212, 213, 407)

Communications by using P212 and P213 with devices operating at different voltage levels are not possible since P212PFS_A and P213PFS_A registers do not have PIM bit. RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 55 of 86

Table 2.35 Simplified IIC communications with devices operating at different voltage levels (1.8 V, 2.5 V, or 3 V) (1 of 2) Conditions: VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol High-speed mode Middle-speed mode Low-speed mode SCLr clock frequency 4.0 V ≤ VCC ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ fSCL — 1000*1 — 1000*1 — 300*1 kHz Figure 2.30 2.7 V ≤ VCC < 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 4.0 V ≤ VCC ≤ 5.5 V, Cb = 100 pF, Rb = 2.8 kΩ 2.7 V ≤ VCC < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ 1.8 V ≤ VCC < 3.3 V, Cb = 100 pF, Rb = 5.5 kΩ Hold time when SCLr is low 4.0 V ≤ VCC ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ tLOW 475 — 475 — 1550 — ns 2.7 V ≤ VCC < 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 475 — 475 — 1550 — ns 4.0 V ≤ VCC ≤ 5.5 V, Cb = 100 pF, Rb = 2.8 kΩ 1150 — 1550 — 1550 — ns 2.7 V ≤ VCC < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ 1150 — 1550 — 1550 — ns 1.8 V ≤ VCC < 3.3 V, Cb = 100 pF, Rb = 5.5 kΩ 1550 — 1550 — 1550 — ns Hold time when SCLr is high 4.0 V ≤ VCC ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ tHIGH 245 — 245 — 610 — ns 2.7 V ≤ VCC < 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 200 — 200 — 610 — ns 4.0 V ≤ VCC ≤ 5.5 V, Cb = 100 pF, Rb = 2.8 kΩ 675 — 675 — 610 — ns 2.7 V ≤ VCC < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ 600 — 600 — 610 — ns 1.8 V ≤ VCC < 3.3 V, Cb = 100 pF, Rb = 5.5 kΩ 610 — 610 — 610 — ns RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 56 of 86

Table 2.35 Simplified IIC communications with devices operating at different voltage levels (1.8 V, 2.5 V, or 3 V) (2 of 2) Conditions: VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol High-speed mode Middle-speed mode Low-speed mode Data setup time (reception) 4.0 V ≤ VCC ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ tSU:DAT 1/fMCK +135*3 — 1/fMCK +135*3 — 1/fMCK +190*3 — ns Figure 2.30 2.7 V ≤ VCC < 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 1/fMCK +135*3 — 1/fMCK +135*3 — 1/fMCK +190*3 — ns 4.0 V ≤ VCC ≤ 5.5 V, Cb = 100 pF, Rb = 2.8 kΩ 1/fMCK +190*3 — 1/fMCK +190*3 — 1/fMCK +190*3 — ns 2.7 V ≤ VCC < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ 1/fMCK +190*3 — 1/fMCK +190*3 — 1/fMCK +190*3 — ns 1.8 V ≤ VCC < 3.3 V, Cb = 100 pF, Rb = 5.5 kΩ 1/fMCK +190*3 — 1/fMCK +190*3 — 1/fMCK +190*3 — ns Data hold time (transmission) 4.0 V ≤ VCC ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ tHD:DAT 0 305 0 305 0 305 ns 2.7 V ≤ VCC < 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 0 305 0 305 0 305 ns 4.0 V ≤ VCC ≤ 5.5 V, Cb = 100 pF, Rb = 2.8 kΩ 0 355 0 355 0 355 ns 2.7 V ≤ VCC < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ 0 355 0 355 0 355 ns 1.8 V ≤ VCC < 3.3 V, Cb = 100 pF, Rb = 5.5 kΩ 0 405 0 405 0 405 ns Note 1. The listed times must be no greater than fMCK/4. Note 2. Use this setting with VCC ≥ Vb. Note 3. Set fMCK so that it will not exceed the hold time when SCLr is low or high. Note: Select the TTL input buffer and the N-ch open drain output [withstand voltage of VCC] mode for the SDAr pin and the N-ch open drain output [withstand voltage of VCC] mode for the SCLr pin by using the Port gh Pin Function Select Register (PghPFS_A.PIM and PghPFS_A.NCODR). For VIH and VIL, see the DC characteristics with TTL input buffer selected. RA0 microcontroller User device SDAr SCLr SDA SCL R b V b V b R b Figure 2.29 Connection in the IIC communications with devices operating at different voltage levels RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 57 of 86

tHD:DAT tSU:DAT Figure 2.30 Timing of serial transfer in the simplified IIC communications with devices operating at different voltage levels Note: ● R b[Ω]: Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance, Vb[V]: Communication line voltage

r: Simplified IIC number (r = 00, 11, 20), gh: Port number (gh = 100 to 102, 110, 112, 201, 212, 407)
f MCK: Serial array unit operation clock frequency To set this operating clock, use the CKS bit in the serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 03, 10)

2.5.2 UART Interface (UARTA)

Table 2.36 UARTA communications Conditions: VCC = 1.6 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol Min. Typ. Max. Unit Test conditions Transfer rate — 200 0 153600 bps — Note: Select the normal input buffer for the RXDA0 pin and the normal output mode for the TXDA0 pin by using the Port gh Pin Function Select Register (PghPFS_A.PIM and PghPFS_A.NCODR). Note: n: Unit number (n = 0), gh: Port number (gh = 100, 101, 109, 110, 207, 208, 212, 213) Note: Communications by using P212 and P213 with devices operating at different voltage levels are not possible since P212PFS_A and P213PFS_A registers do not have PIM bit. RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 58 of 86

2.5.3 I2C Bus Interface (IICA)

Table 2.37 I2C standard mode Conditions: VCC = 1.6 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol Min. Typ. Max. Unit Test conditions SCLA0 clock frequency Standard mode: PCLKB ≥ 1 MHz fSCL 0 — 100 kHz Figure 2.31 Setup time of restart condition — tSU:STA 4.7 — — µs Hold time*1 — tHD:STA 4 — — µs Hold time when SCLA0 is low — tLOW 4.7 — — µs Hold time when SCLA0 is high — tHIGH 4 — — µs Data setup time (reception) — tSU:DAT 250 — — ns Data hold time (transmission)*2 — tHD:DAT 0 — 3.45 µs Setup time of stop condition — tSU:STO 4 — — µs Bus-free time — tBUF 4.7 — — µs Note 1. The first clock pulse is generated after this period when the start or restart condition is detected. Note 2. The maximum value of tHD:DAT applies to normal transfer. The clock stretching will be inserted on reception of an acknowledgment (ACK) signal. Note: Communications by using P212 and P213 with devices operating at different voltage levels are not possible since P212PFS_A and P213PFS_A registers do not have PIM bit. Note: The maximum value of communication line capacitance (C b) and communication line pull-up resistor (Rb) are as follows. Cb = 400 pF, Rb = 2.7 kΩ Table 2.38 I2C fast mode Conditions: VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol Min. Typ. Max. Unit Test conditions SCLA0 clock frequency Fast mode: PCLKB ≥ 3.5 MHz 1.8 V ≤ VCC ≤ 5.5 V fSCL 0 — 400 kHz Figure 2.31 Setup time of restart condition 1.8 V ≤ VCC ≤ 5.5 V tSU:STA 0.6 — — µs Hold time*1 1.8 V ≤ VCC ≤ 5.5 V tHD:STA 0.6 — — µs Hold time when SCLA0 is low 1.8 V ≤ VCC ≤ 5.5 V tLOW 1.3 — — µs Hold time when SCLA0 is high 1.8 V ≤ VCC ≤ 5.5 V tHIGH 0.6 — — µs Data setup time (reception) 1.8 V ≤ VCC ≤ 5.5 V tSU:DAT 100 — — ns Data hold time (transmission)*2 1.8 V ≤ VCC ≤ 5.5 V tHD:DAT 0 — 0.9 µs Setup time of stop condition 1.8 V ≤ VCC ≤ 5.5 V tSU:STO 0.6 — — µs Bus-free time 1.8 V ≤ VCC ≤ 5.5 V tBUF 1.3 — — µs Note 1. The first clock pulse is generated after this period when the start or restart condition is detected. Note 2. The maximum value of tHD:DAT applies to normal transfer. The clock stretching will be inserted on reception of an acknowledgment (ACK) signal. Note: Communications by using P212 and P213 with devices operating at different voltage levels are not possible since P212PFS_A and P213PFS_A registers do not have PIM bit. Note: The maximum value of communication line capacitance (C b) and communication line pull-up resistor (Rb) are as follows. Cb = 320 pF, Rb = 1.1 kΩ RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 59 of 86

Table 2.39 I2C fast mode plus Conditions: VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol Min. Typ. Max. Unit Test conditions SCLA0 clock frequency Fast mode plus: PCLKB ≥ 10 MHz 2.7 V ≤ VCC ≤ 5.5 V fSCL 0 — 1000 kHz Figure 2.31 Setup time of restart condition 2.7 V ≤ VCC ≤ 5.5 V tSU:STA 0.26 — — µs Hold time*1 2.7 V ≤ VCC ≤ 5.5 V tHD:STA 0.26 — — µs Hold time when SCLA0 is low 2.7 V ≤ VCC ≤ 5.5 V tLOW 0.5 — — µs Hold time when SCLA0 is high 2.7 V ≤ VCC ≤ 5.5 V tHIGH 0.26 — — µs Data setup time (reception) 2.7 V ≤ VCC ≤ 5.5 V tSU:DAT 50 — — ns Data hold time (transmission)*2 2.7 V ≤ VCC ≤ 5.5 V tHD:DAT 0 — 0.45 µs Setup time of stop condition 2.7 V ≤ VCC ≤ 5.5 V tSU:STO 0.26 — — µs Bus-free time 2.7 V ≤ VCC ≤ 5.5 V tBUF 0.5 — — µs Note 1. The first clock pulse is generated after this period when the start or restart condition is detected. Note 2. The maximum value of tHD:DAT applies to normal transfer. The clock stretching will be inserted on reception of an acknowledgment (ACK) signal. Note: Communications by using P212 and P213 with devices operating at different voltage levels are not possible since P212PFS_A and P213PFS_A registers do not have PIM bit. Note: The maximum value of communication line capacitance (C b) and communication line pull-up resistor (Rb) are as follows. Cb = 120 pF, Rb = 1.1 kΩ SCLAn SDAAn Stop condition Start condition tHD:STA tBUF tLOW tR tHD:DAT tHIGH tF tSU:DAT tSU:STA Restart condition tHD:STA tSU:STO Stop condition Note: n = 0 Figure 2.31 IICA serial transfer timing

2.6 Analog Characteristics

2.6.1 A/D Converter Characteristics

Table 2.40 A/D conversion characteristics in Normal modes 1 and 2 (1 of 2) Conditions: 2.4V ≤ VREFH0 ≤ VCC ≤ 5.5 V, VSS = 0 V, Ta = -40 to +105°C Reference voltage range applied to the VREFH0 (ADREFP[1:0] = 01b) and VREFL0 (ADREFM = 1b). Target pins: AN000 to AN007, AN021 to AN022, internal reference voltage, and temperature sensor output voltage Parameter Symbol Min Typ Max Unit Test conditions Resolution RES 8 — 12 bit — Conversion clock fAD 1 — 32 MHz — RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 60 of 86

Table 2.40 A/D conversion characteristics in Normal modes 1 and 2 (2 of 2) Conditions: 2.4V ≤ VREFH0 ≤ VCC ≤ 5.5 V, VSS = 0 V, Ta = -40 to +105°C Reference voltage range applied to the VREFH0 (ADREFP[1:0] = 01b) and VREFL0 (ADREFM = 1b). Target pins: AN000 to AN007, AN021 to AN022, internal reference voltage, and temperature sensor output voltage Parameter Symbol Min Typ Max Unit Test conditions Overall error*1 *3 *4 *5 12-bit resolution AINL — — ±7.5 LSB 4.5 V ≤ VREFH0 = VCC ≤ 5.5 V — — ±9.0 LSB 2.7 V ≤ VREFH0 = VCC ≤ 5.5 V — — ±9.0 LSB 2.4 V ≤ VREFH0 = VCC ≤ 5.5 V Conversion time*6 12-bit resolution tCONV 2.0 — — µs 4.5 V ≤ VREFH0 = VCC ≤ 5.5 V 2.0 — — µs 2.7 V ≤ VREFH0 = VCC ≤ 5.5 V 2.0 — — µs 2.4 V ≤ VREFH0 = VCC ≤ 5.5 V Zero-scale error*1 *2 *3 *4 *5 12-bit resolution EZS — — ±0.17 %FSR 4.5 V ≤ VREFH0 = VCC ≤ 5.5 V — — ±0.21 %FSR 2.7 V ≤ VREFH0 = VCC ≤ 5.5 V — — ±0.21 %FSR 2.4 V ≤ VREFH0 = VCC ≤ 5.5 V Full-scale error*1 *2 *3 *4 *5 12-bit resolution EFS — — ±0.17 %FSR 4.5 V ≤ VREFH0 = VCC ≤ 5.5 V — — ±0.21 %FSR 2.7 V ≤ VREFH0 = VCC ≤ 5.5 V — — ±0.21 %FSR 2.4 V ≤ VREFH0 = VCC ≤ 5.5 V Integral linearity error*1 *4 *5 12-bit resolution ILE — — ±3.0 LSB 4.5 V ≤ VREFH0 = VCC ≤ 5.5 V — — ±3.0 LSB 2.7 V ≤ VREFH0 = VCC ≤ 5.5 V — — ±3.0 LSB 2.4 V ≤ VREFH0 = VCC ≤ 5.5 V Differential linearity error*1 12-bit resolution DLE — ±1.0 — LSB 4.5 V ≤ VREFH0 = VCC ≤ 5.5 V — ±1.0 — LSB 2.7 V ≤ VREFH0 = VCC ≤ 5.5 V — ±1.0 — LSB 2.4 V ≤ VREFH0 = VCC ≤ 5.5 V Analog input voltage VAIN 0 — VREFH0 V — Note 1. This value does not include the quantization error (±1/2 LSB). Note 2. This value is indicated as a ratio (%FSR) to the full-scale value. Note 3. When pins AN021 to AN022 are selected as the target pins for conversion, the maximum values are as follows. Overall error: Add ±3 LSB to the maximum value. Zero-scale/full-scale error: Add ±0.04%FSR to the maximum value. Note 4. When reference voltage (+) = VCC (ADREFP[1:0] = 00b) and reference voltage (-) = VSS (ADREFM = 0b), the maximum values are as follows. Overall error: Add ±10 LSB to the maximum value. Zero-scale/full-scale error: Add ±0.25%FSR to the maximum value. Integral linearity error: Add ±4 LSB to the maximum value. Note 5. When VREFH0 < VCC, the maximum values are as follows. Overall error / Zero-scale error / Full-scale error: Add ±0.75 LSB × (VCC − VREFH0) to the maximum value. Integral linearity error: Add ±0.2 LSB × (VCC − VREFH0) to the maximum value. Note 6. When the internal reference voltage or the temperature sensor output voltage is selected as the target for conversion, the sampling time must be at least 5 µs. Accordingly, use standard mode 2 with the longer sampling time. Table 2.41 A/D conversion characteristics in Low-voltage modes 1 and 2 (1) (1 of 2) Conditions: 1.6 V ≤ VREFH0 ≤ VCC ≤ 5.5 V, VSS = 0 V, Ta = -40 to +105°C Reference voltage range applied to the VREFH0 (ADREFP[1:0] = 01b) and VREFL0 (ADREFM = 1b). Target pins: AN000 to AN007, AN021 to AN022, internal reference voltage*7, and temperature sensor output voltage*7 Parameter Symbol Min Typ Max Unit Test conditions Resolution RES 8 — 12 bit — Conversion clock fAD 1 — 24 MHz — Overall error*1 *3 *4 *5 12-bit resolution AINL — — ±9 LSB 2.7 V ≤ VREFH0 = VCC ≤ 5.5 V — — ±9 LSB 2.4 V ≤ VREFH0 = VCC ≤ 5.5 V — — ±11.5 LSB 1.8 V ≤ VREFH0 = VCC ≤ 5.5 V — — ±12.0 LSB 1.6 V ≤ VREFH0 = VCC ≤ 5.5 V RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 61 of 86

Table 2.41 A/D conversion characteristics in Low-voltage modes 1 and 2 (1) (2 of 2) Conditions: 1.6 V ≤ VREFH0 ≤ VCC ≤ 5.5 V, VSS = 0 V, Ta = -40 to +105°C Reference voltage range applied to the VREFH0 (ADREFP[1:0] = 01b) and VREFL0 (ADREFM = 1b). Target pins: AN000 to AN007, AN021 to AN022, internal reference voltage*7, and temperature sensor output voltage*7 Parameter Symbol Min Typ Max Unit Test conditions Conversion time*6 12-bit resolution tCONV 3.3 — — µs 2.7 V ≤ VREFH0 = VCC ≤ 5.5 V 5.0 — — µs 2.4 V ≤ VREFH0 = VCC ≤ 5.5 V 10.0 — — µs 1.8 V ≤ VREFH0 = VCC ≤ 5.5 V 20.0 — — µs 1.6 V ≤ VREFH0 = VCC ≤ 5.5 V Zero-scale error*1 *2 *3 *4 *5 12-bit resolution EZS — — ±0.21 %FSR 2.7 V ≤ VREFH0 = VCC ≤ 5.5 V — — ±0.21 %FSR 2.4 V ≤ VREFH0 = VCC ≤ 5.5 V — — ±0.27 %FSR 1.8 V ≤ VREFH0 = VCC ≤ 5.5 V — — ±0.28 %FSR 1.6 V ≤ VREFH0 = VCC ≤ 5.5 V Full-scale error*1 *2 *3 *4 *5 12-bit resolution EFS — — ±0.21 %FSR 2.7 V ≤ VREFH0 = VCC ≤ 5.5 V — — ±0.21 %FSR 2.4 V ≤ VREFH0 = VCC ≤ 5.5 V — — ±0.27 %FSR 1.8 V ≤ VREFH0 = VCC ≤ 5.5 V — — ±0.28 %FSR 1.6 V ≤ VREFH0 = VCC ≤ 5.5 V Integral linearity error*1 *4 *5 12-bit resolution ILE — — ±4.0 LSB 2.7 V ≤ VREFH0 = VCC ≤ 5.5 V — — ±4.0 LSB 2.4 V ≤ VREFH0 = VCC ≤ 5.5 V — — ±4.5 LSB 1.8 V ≤ VREFH0 = VCC ≤ 5.5 V — — ±4.5 LSB 1.6 V ≤ VREFH0 = VCC ≤ 5.5 V Differential linearity error*1 12-bit resolution DLE — ±1.5 — LSB 2.7 V ≤ VREFH0 = VCC ≤ 5.5 V — ±1.5 — LSB 2.4 V ≤ VREFH0 = VCC ≤ 5.5 V — ±2.0 — LSB 1.8 V ≤ VREFH0 = VCC ≤ 5.5 V — ±2.0 — LSB 1.6 V ≤ VREFH0 = VCC ≤ 5.5 V Analog input voltage VAIN 0 — VREFH0 V — Note 1. This value does not include the quantization error (±1/2 LSB). Note 2. This value is indicated as a ratio (%FSR) to the full-scale value. Note 3. When pins AN021 to AN022 are selected as the target pins for conversion, the maximum values are as follows. Overall error: Add ±3 LSB to the maximum value. Zero-scale/full-scale error: Add ±0.04%FSR to the maximum value. Note 4. When reference voltage (+) = VCC (ADREFP[1:0] = 00b) and reference voltage (-) = VSS (ADREFM = 0b), the maximum values are as follows. Overall error: Add ±10 LSB to the maximum value. Zero-scale/full-scale error: Add ±0.25%FSR to the maximum value. Integral linearity error: Add ±4 LSB to the maximum value. Note 5. When VREFH0 < VCC, the maximum values are as follows. Overall error / Zero-scale error / Full-scale error: Add ±0.75 LSB × (VCC − VREFH0) to the maximum value. Integral linearity error: Add ±0.2 LSB × (VCC − VREFH0) to the maximum value. Note 6. When the internal reference voltage or the temperature sensor output voltage is selected as the target for conversion, the sampling time must be at least 5 µs. Accordingly, use standard mode 2 with the longer sampling time, and use the conversion clock (fAD) of no more than 16 MHz. Note 7. If the internal reference voltage or temperature sensor output voltage is to be A/D converted, VCC must be at least 1.8 V. Table 2.42 A/D conversion characteristics in Low-voltage modes 1 and 2 (2) (1 of 2) Conditions: 1.8 V ≤ VCC ≤ 5.5 V, VSS = 0 V, Ta = -40 to +105°C Reference voltage range applied to the internal reference voltage (ADREFP[1:0] = 10b) and VREFL0 (ADREFM = 1b). Parameter Symbol Min Typ Max Unit Test conditions Resolution RES 8 bit — Conversion clock fAD 1 — 2 MHz 1.8 V ≤ VCC ≤ 5.5 V Zero-scale error*1 *2 *4 EZS — — ±0.6 %FSR 1.8 V ≤ VCC ≤ 5.5 V Integral linearity error*1 *4 ILE — — ±2.0 LSB 1.8 V ≤ VCC ≤ 5.5 V RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 62 of 86

error (INL) Actual A/D conversion characteristic Ideal A/D conversion characteristic Analog input voltage Offset error Absolute accuracy Differential nonlinearity error (DNL) Full-scale error 0xFFF 0x000 Ideal line of actual A/D conversion characteristic 1-LSB width for ideal A/D conversion characteristic Differential nonlinearity error (DNL) 1-LSB width for ideal A/D conversion characteristic VREFH0 (full-scale) A/D converter output code Figure 2.33 Illustration of 12-bit A/D converter characteristic terms Absolute accuracy Absolute accuracy is the difference between output code based on the theoretical A/D conversion characteristics, and the actual A/D conversion result. When measuring absolute accuracy, the voltage at the midpoint of the width of the analog input voltage (1-LSB width), which can meet the expectation of outputting an equal code based on the theoretical A/D conversion characteristics, is used as the analog input voltage. For example, if 12-bit resolution is used and the reference voltage VREFH0 = 3.072 V , then 1-LSB width becomes 0.75 mV , and 0 mV , 0.75 mV , and 1.5 mV are used as the analog input voltages. If analog input voltage is 6 mV , an absolute accuracy of ±5 LSB means that the actual A/D conversion result is in the range of 0x003 to 0x00D, though an output code of 0x008 can be expected from the theoretical A/D conversion characteristics. Integral nonlinearity error (INL) Integral nonlinearity error is the maximum deviation between the ideal line when the measured offset and full-scale errors are zeroed, and the actual output code. Differential nonlinearity error (DNL) Differential nonlinearity error is the difference between 1-LSB width based on the ideal A/D conversion characteristics and the width of the actual output code. Offset error Offset error is the difference between the transition point of the ideal first output code and the actual first output code. RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 64 of 86

Full-scale error is the difference between the transition point of the ideal last output code and the actual last output code.

2.6.2 Temperature Sensor/Internal Reference Voltage Characteristics

Table 2.44 Temperature sensor/internal reference voltage characteristics Conditions: 1.8 V ≤ VCC ≤ 5.5 V, VSS = 0 V, Ta = -40 to +105 °C Parameter Symbol Min Typ Max Unit Test conditions Temperature sensor output voltage VTMPS25 — 1.05 — V 25 °C Internal reference voltage VBGR 1.40 1.48 1.56 V — Temperature coefficient FVTMPS — -3.3 — mV/°C — Operation stabilization wait time tAMP 5 — — µs —

2.6.3 POR Characteristics

Table 2.45 POR characteristics Conditions: VSS = 0 V, Ta = -40 to +105°C Parameter Symbol Min Typ Max Unit Test Conditions Detection voltage VPOR VPDR 1.43 1.50 1.57 V — Minimum pulse width*1 TPW 300 — — µs — Note 1. This width is the minimum time required for a POR reset when VCC falls below VPDR. This width is also the minimum time required for a POR reset from when VCC falls below 0.7 V to when VCC exceeds VPOR in the Software standby mode or while the main system clock is stopped through setting HOCOCR.HCSTOP bit and MOSCCR.MOSTP bit. T PW V POR V PDR or 0.7 V Supply voltage (VCC) Figure 2.34 Minimum VCC pulse width RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 65 of 86

2.6.4 LVD Characteristics

Table 2.46 LVD0 characteristics Conditions: VPDR ≤ VCC ≤ 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol Min Typ Max Unit Test Conditions Detection voltage Supply voltage level Vdet0_0 3.84 3.96 4.08 V The power supply voltage is rising. 3.76 3.88 4.00 V The power supply voltage is falling. Vdet0_1 2.88 2.97 3.06 V The power supply voltage is rising. 2.82 2.91 3.00 V The power supply voltage is falling. Vdet0_2 2.59 2.67 2.75 V The power supply voltage is rising. 2.54 2.62 2.70 V The power supply voltage is falling. Vdet0_3 2.31 2.38 2.45 V The power supply voltage is rising. 2.26 2.33 2.40 V The power supply voltage is falling. Vdet0_4 1.84 1.90 1.95 V The power supply voltage is rising. 1.80 1.86 1.91 V The power supply voltage is falling. Vdet0_5 1.64 1.69 1.74 V The power supply voltage is rising. 1.60 1.65 1.70 V The power supply voltage is falling. Minimum pulse width tLW0 500 — — µs — Detection delay time tdet0 — — 500 µs — Table 2.47 LVD1 characteristics (1 of 2) Conditions: VPDR ≤ VCC ≤ 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol Min Typ Max Unit Test Conditions Detection voltage Supply voltage level Vdet1_0 4.08 4.16 4.24 V The power supply voltage is rising. 4.00 4.08 4.16 V The power supply voltage is falling. Vdet1_1 3.88 3.96 4.04 V The power supply voltage is rising. 3.80 3.88 3.96 V The power supply voltage is falling. Vdet1_2 3.68 3.75 3.82 V The power supply voltage is rising. 3.60 3.67 3.74 V The power supply voltage is falling. Vdet1_3 3.48 3.55 3.62 V The power supply voltage is rising. 3.40 3.47 3.54 V The power supply voltage is falling. Vdet1_4 3.28 3.35 3.42 V The power supply voltage is rising. 3.20 3.27 3.34 V The power supply voltage is falling. Vdet1_5 3.07 3.13 3.19 V The power supply voltage is rising. 3.00 3.06 3.12 V The power supply voltage is falling. Vdet1_6 2.91 2.97 3.03 V The power supply voltage is rising. 2.85 2.91 2.97 V The power supply voltage is falling. Vdet1_7 2.76 2.82 2.87 V The power supply voltage is rising. 2.70 2.76 2.81 V The power supply voltage is falling. Vdet1_8 2.61 2.66 2.71 V The power supply voltage is rising. 2.55 2.60 2.65 V The power supply voltage is falling. Vdet1_9 2.45 2.50 2.55 V The power supply voltage is rising. 2.40 2.45 2.50 V The power supply voltage is falling. Vdet1_A 2.35 2.40 2.45 V The power supply voltage is rising. 2.30 2.35 2.40 V The power supply voltage is falling. RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 66 of 86

Table 2.47 LVD1 characteristics (2 of 2) Conditions: VPDR ≤ VCC ≤ 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol Min Typ Max Unit Test Conditions Detection voltage Supply voltage level Vdet1_B 2.25 2.30 2.34 V The power supply voltage is rising. 2.20 2.25 2.29 V The power supply voltage is falling. Vdet1_C 2.15 2.20 2.24 V The power supply voltage is rising. 2.10 2.15 2.19 V The power supply voltage is falling. Vdet1_D 2.05 2.09 2.13 V The power supply voltage is rising. 2.00 2.04 2.08 V The power supply voltage is falling. Vdet1_E 1.94 1.98 2.02 V The power supply voltage is rising. 1.90 1.94 1.98 V The power supply voltage is falling. Vdet1_F 1.84 1.88 1.91 V The power supply voltage is rising. 1.80 1.84 1.87 V The power supply voltage is falling. Vdet1_10 1.74 1.78 1.81 V The power supply voltage is rising. 1.70 1.74 1.77 V The power supply voltage is falling. Vdet1_11 1.64 1.67 1.70 V The power supply voltage is rising. 1.60 1.63 1.66 V The power supply voltage is falling. Minimum pulse width tLW1 500 — — µs — Detection delay time tdet1 — — 500 µs — LVD1 detection voltage stabilization time (after changing the LVD1 detection voltage) td(E-A) — — 1500 µs — LVD reset signal (active-low) Supply voltage (VCC) V detn t det n t det n Time t LWn Note: n = 0, 1 Figure 2.35 Voltage detection circuit timing RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 67 of 86

2.6.5 Power Supply Voltage Rising Slope Characteristics

Table 2.48 Power supply voltage rising slope characteristics Conditions: VSS = 0 V, Ta = -40 to +105°C Parameter Symbol Min Typ Max Unit Test Conditions Power supply voltage rising slope SVCC — — 54 V/ms — Note: Make sure to keep the internal reset state by the LVD0 circuit or an external reset until VCC reaches the operating voltage range shown in AC characteristics.

2.7 RAM Data Retention Characteristics

Table 2.49 RAM data retention characteristics Conditions: VSS = 0 V, Ta = -40 to +105°C Parameter Symbol Min Typ Max Unit Test Conditions Data retention supply voltage VCCDR 1.43*1 — 5.5 V — Note 1. This voltage depends on the POR detection voltage. When the voltage drops, the data in RAM are retained until a POR is applied, but are not retained following a POR. VCC Software standby instruction execution Software standby release signal (interrupt request) Software Standby mode RAM data retention Operation mode V CCDR Figure 2.36 RAM data retention

2.8 Flash Memory Programming Characteristics

Table 2.50 Flash memory programming characteristics Conditions: 1.8 V ≤ VCC ≤ 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol Min Typ Max Unit Test Conditions CPU/peripheral hardware clock frequency ICLK 1 — 32 MHz — Number of code flash rewrites*1 *2 *3 Cerwr 10000 — — Times Retained for 10 years Ta = 85°C 1000 — — Retained for 20 years Ta = 85°C Number of data flash rewrites*1 *2 *3 — 1000000 — Retained for 1 year Ta = 25°C 100000 — — Retained for 5 years Ta = 85°C 10000 — — Retained for 20 years Ta = 85°C Note 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite. Note 2. The listed numbers of times apply when using the flash memory programmer and self-programming. Note 3. These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics Corporation. RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 68 of 86

Table 2.51 Code flash memory characteristics Conditions: 1.8 V ≤ VCC ≤ 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol ICLK = 1 MHz ICLK = 2 MHz, 3 MHz 4 MHz ≤ ICLK < 8 MHz 8 MHz ≤ ICLK < 32 MHz ICLK = 32 MHz Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max Programming time Blank checking time Time taken to forcibly stop the erasure Time until programming starts following cancellation of the Software standby instruction Flash memory mode transition wait time 1 Flash memory mode transition wait time 2 Note: The listed values do not include the time until the operations of the flash memory start following execution of an instruction by software. Table 2.52 Data flash memory characteristics Conditions: 1.8 V ≤ VCC ≤ 5.5 V, VSS = 0 V, Ta = -40 to +105°C Parameter Symbol ICLK = 1 MHz ICLK = 2 MHz, 3 MHz 4 MHz ≤ ICLK < 8 MHz 8 MHz ≤ ICLK < 32 MHz ICLK = 32 MHz Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max Programming time Blank checking time Time taken to forcibly stop the erasure Time until programming starts following cancellation of the Software standby instruction Time until reading starts following setting DFLEN to 1 Flash memory mode transition wait time 1 Flash memory mode transition wait time 2 Note: The listed values do not include the time until the operations of the flash memory start following execution of an instruction by software.

2.9 Serial Wire Debug (SWD)

Table 2.53 SWD characteristics (1) (1 of 2) Conditions: VCC = 2.4 to 5.5 V Parameter Symbol Min Typ Max Unit Test conditions SWCLK clock cycle time tSWCKcyc 80 — — ns Figure 2.37 SWCLK clock high pulse width tSWCKH 35 — — ns SWCLK clock low pulse width tSECKL 35 — — ns SWCLK clock rise time tSWCKr — — 5 ns SWCLK clock fall time tSWCKf — — 5 ns RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 69 of 86

Table 2.53 SWD characteristics (1) (2 of 2) Conditions: VCC = 2.4 to 5.5 V Parameter Symbol Min Typ Max Unit Test conditions SWDIO setup time tSWDS 16 — — ns Figure 2.38 SWDIO hold time tSWDH 16 — — ns SWDIO data delay time tSWDD 2 — 70 ns Table 2.54 SWD characteristics (2) Conditions: VCC = 1.6 to 2.4 V Parameter Symbol Min Typ Max Unit Test conditions SWCLK clock cycle time tSWCKcyc 250 — — ns Figure 2.37 SWCLK clock high pulse width tSWCKH 120 — — ns SWCLK clock low pulse width tSECKL 120 — — ns SWCLK clock rise time tSWCKr — — 5 ns SWCLK clock fall time tSWCKf — — 5 ns SWDIO setup time tSWDS 50 — — ns Figure 2.38 SWDIO hold time tSWDH 50 — — ns SWDIO data delay time tSWDD 2 — 170 ns t SWCKH t SWCKf t SWCKcyc SWCLK t SWCKr t SWCKL Figure 2.37 SWD SWCLK timing RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 70 of 86

(Input) t SWDD SWDIO (Output) t SWDD SWDIO (Output) t SWDD SWDIO (Output) Figure 2.38 SWD input/output timing RA0E1 Datasheet 2. Electrical Characteristics R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 71 of 86

Appendix 1. Port States in each Processing Mode Table A1.1 Port states in each processing mode (1 of 3) Port name Reset Software Standby Mode P008/AN002 Hi-Z Keep-O P009/AN003 Hi-Z Keep-O P010/VREFH0/AN000 Hi-Z Keep-O P011/VREFL0/AN001 Hi-Z Keep-O P012/AN004 Hi-Z Keep-O P013/AN005 Hi-Z Keep-O P014/AN006 Hi-Z Keep-O P015/AN007/IRQ1_A Hi-Z [IRQ1_A selected] IRQ1_A input [Other than the above] Keep-O P100/AN022/IRQ2_A/TI04_A/TO04_A/TI01_B/TO01_B/RXD0_A/SI00_A/SDA00_A/ RXDA0_D/SCLA0_D Hi-Z [IRQ2_A selected] IRQ2_A input [SCLA0_D selected] SCLA0_D input/output [RXDA0_D selected] RXDA0_D input [Other than the above] Keep-O P101/AN021/IRQ3_A/TI07_A/TO07_A/TI00_C/TXD0_A/SO00_A/TXDA0_D/ SDAA0_D Hi-Z [IRQ3_A selected] IRQ3_A input [SDAA0_D selected] SDDA0_D input/output [TXDA0_D selected] TXDA0_D output [Other than the above] Keep-O P102/IRQ4_A/TI06_A/TO06_A/TO00_C/RTCOUT_C/PCLBUZ0_B/SCK00_A/ SCL00_A Hi-Z [IRQ4_A selected] IRQ4_A input [RTCOUT_C selected] RTCOUT_C output [PCLBUZ0_B selected] PCLBUZ0_B output [Other than the above] Keep-O P103/IRQ5_A/TI05_A/TO05_A/SSI00_A Hi-Z [IRQ5_A selected] IRQ5_A input [Other than the above] Keep-O P108/SWDIO/TI03_B/TO03_B Pull-up Keep-O P109/IRQ4_B/TI02_A/TO02_A/TXD2_A/SO20_A/TXDA0_C/SDAA0_C Hi-Z [IRQ4_B selected] IRQ4_B input [TXDA0_C selected] TXDA0_C output [SDAA0_C selected] SDAA0_C input/output [Other than the above] Keep-O P110/IRQ3_B/TI01_A/TO01_A/RXD2_A/SI20_A/SDA20_A/RXDA0_C/SCLA0_C Hi-Z [IRQ3_B selected] IRQ3_B input [RXDA0_C selected] RXDA0_C input [SCLA0_C selected] SCLA0_C input [Other than the above] Keep-O RA0E1 Datasheet Appendix 1. Port States in each Processing Mode R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 72 of 86

Table A1.1 Port states in each processing mode (2 of 3) Port name Reset Software Standby Mode P112/IRQ2_B/TI03_A/TO03_A/SCK20_A/SCL20_A/SSI00_C Hi-Z [IRQ2_B selected] IRQ2_B input [Other than the above] Keep-O P200/NMI/IRQ0_A Hi-Z [NMI/IRQ0_A selected] NMI/IRQ0_A input [Other than the above] Hi-Z P201/IRQ5_B/TI05_B/TO05_B/RTCOUT_B/PCLBUZ0_A/SSI00_B/SCK11_B/ SCL11_B Hi-Z [IRQ5_B selected] IRQ5_B input [RTCOUT_B selected] RTCOUT_B output [PCLBUZ0_A selected] PCLBUZ0_A output [Other than the above] Keep-O P206/RES Pull-up [RES(OFS1.PORTSELB=1) selected] RES input [P206(OFS1.PORTSELB=0) selected] Keep-O P207/IRQ2_C/TO00_B/RXDA0_A Hi-Z [IRQ2_C selected] IRQ2_C input [RXDA0_A selected] RXDA0_A input [Other than the above] Keep-O P208/IRQ3_C/TI00_B/TXDA0_A Hi-Z [IRQ3_C selected] IRQ3_C input [TXDA0_A selected] TXDA0_A output [Other than the above] Keep-O P212/X1/(XCIN*1)/IRQ1_B/TO00_A/TI03_C/TO03_C/RXD1_A/SI11_A/SDA11_A/ RXDA0_B/SCLA0_B Hi-Z [Sub-clock Oscillator selected]*1 Sub-clock Oscillator is operating [IRQ1_B selected] IRQ1_B input [RXDA0_B selected] RXDA0_B input [SCLA0_B selected] SCLA0_B input/output [Other than the above] Keep-O P213/X2/(XCOUT*1)/EXCLK/IRQ0_B/TI00_A/TI02_B/TO02_B/TXD1_A/SO11_A/ TXDA0_B/SDAA0_B Hi-Z [Sub-clock Oscillator selected]*1 Sub-clock Oscillator is operating [IRQ0_B selected] IRQ0_B input [TXDA0_B selected] TXDA0_B output [SDAA0_B selected] SDAA0_B input/output [Other than the above] Keep-O P214/XCOUT Hi-Z [Sub-clock Oscillator selected] Sub-clock Oscillator is operating [Other than the above] Hi-Z P215/XCIN Hi-Z [Sub-clock Oscillator selected] Sub-clock Oscillator is operating [Other than the above] Hi-Z RA0E1 Datasheet Appendix 1. Port States in each Processing Mode R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 73 of 86

Table A1.1 Port states in each processing mode (3 of 3) Port name Reset Software Standby Mode P300/SWCLK/TI04_B/TO04_B Pull-up Keep-O P407/IRQ4_C/RTCOUT_A/PCLBUZ0_C/SCK11_A/SCL11_A Hi-Z [IRQ4_C selected] IRQ4_C input [RTCOUT_A selected] RTCOUT_A output [PCLBUZ0_C selected] PCLBUZ0_C output [Other than the above] Keep-O P913/SDAA0_A Hi-Z [SDAA0_A selected] SDAA0_A input/output [Other than the above] Keep-O P914/SCLA0_A Hi-Z [SCLA0_A selected] SCLA0_A input/output [Other than the above] Keep-O Note: Hi-Z: High-impedance Keep-O: Output pins retain their previous values. Input pins become high-impedance. Note 1. When setting CMC.XTSEL = 1 for 24-, 20-, and 16-pin products. RA0E1 Datasheet Appendix 1. Port States in each Processing Mode R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 74 of 86

Appendix 2. Package Dimensions Information on the latest version of the package dimensions or mountings is displayed in “Packages” on the Renesas Electronics Corporation website. 201 2 Renesas Electronics Corporation. All rights reserved. 0.145 ±0.055 (UNIT:mm) ITEM DIMENSIONS D E HD HE A 7.00 ±0.10 7.00 ±0.10 9.00 ±0.20 9.00 ±0.20 1.70 MAX. 0.10 ±0.10 1.40 c θ e x y 0.80 0.20 0.10 L 0.50 ±0.20 0° to 8° 0.37 ±0.05b NOTE 1.Dimensions “ 1” and “ 2” do not include mold flash. 2.Dimension “ 3” does not include trim offset. y e xb M θ L c HD HE A D E detail of lead end 32 9 P-LQFP32-7x7-0.80 PLQP0032GB-A P32GA-80-GBT -1 0.2 Figure A2.1 LQFP 32-pin RA0E1 Datasheet Appendix 2. Package Dimensions R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 75 of 86

INDEX AREA(D/2 X E/2)D E SEATING PLANEcccC32X bbbCABdddC eb(32X) 321 89 161724 L(32X)K(32X) C aaaC B2XaaaC (A3)A1AeeeC fffCABfffCAB A32 2524 1716 981 外形図 Outline drawingRenesasコード PWQN0032KE-Aルネサスエレクトロニクス株式会社Renesas Electronics CorporationRDK-G-0014451/1 Figure A2.2 HWQFN 32-pin RA0E1 Datasheet Appendix 2. Package Dimensions R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 76 of 86

P-HWQFN24-4x4-0.50 PWQN0024KG-A MASS(Typ.) [g] 0.04 Figure A2.3 HWQFN 24-pin RA0E1 Datasheet Appendix 2. Package Dimensions R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 77 of 86

P-LSSOP20-4.4x6.5-0.65 PLSP0020JB-A P20MA-65-NAA-1 0.1 1 10 detail of lead end ITEM DIMENSIONS D E e A L c y bp 0.10 0.10 0 to 10 A A1 ey HE c 6.50 4.40 0.20 0.10 6.40 0.100.10 1.45 MAX . 1.15 0.65 0.12 0.10 0.050.22 0.05 0.020.15 0.50 0.20 bp HE E D L NOTE 1.Dimensions “ 1” and “ 2” 2.Dimension “ ” does not include tr MASS (TYP.) [g] 2012 Renesas Electronics Corporation. All rights reserved. (UNIT: mm) Figure A2.4 LSSOP 20-pin RA0E1 Datasheet Appendix 2. Package Dimensions R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 78 of 86

DAaaaCCSEATINGPLANECDetail of Lead EndHL1Lθ0.25GAUGE PLANEcccAA2A1S 外形図 Outline drawingRenesasコード PTSP0020JI-Aルネサスエレクトロニクス株式会社Renesas Electronics CorporationRDK-G-001493 1/1 Figure A2.5 TSSOP 20-pin RA0E1 Datasheet Appendix 2. Package Dimensions R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 79 of 86

EXPOSED DIE PADDABEINDEX AREA(D/2 X E/2)2XaaaCcccC(A3)A1eeeC16XAeb(16X)bbbCABdddCE2D2fffCABfffCABL(16X)K(16X) Figure A2.6 HWQFN 16-pin RA0E1 Datasheet Appendix 2. Package Dimensions R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 80 of 86

Appendix 3. I/O Registers This appendix describes I/O register addresses, access cycles, and reset values by function.

3.1 Peripheral Base Addresses

This section provides the base addresses for peripherals described in this manual. Table A3.1 shows the name, description, and the base address of each peripheral. Table A3.1 Peripheral base address Name Description Base address SRAM SRAM Control 0x4000_2000 BUS BUS Control 0x4000_3000 DTC Data Transfer Controller 0x4000_5400 ICU Interrupt Controller 0x4000_6000 DBG Debug Function 0x4001_B000 SYSC System Control 0x4001_E000 ELC Event Link Controller 0x4004_1000 IWDT Independent Watchdog Timer 0x4004_4400 MSTP Module Stop Control 0x4004_7000 CRC CRC Calculator 0x4007_4000 PORT0 Port 0 Control 0x400A_0000 PORT1 Port 1 Control 0x400A_0020 PORT2 Port 2 Control 0x400A_0040 PORT3 Port 3 Control 0x400A_0060 PORT4 Port 4 Control 0x400A_0080 PORT9 Port 9 Control 0x400A_0120 PFS_A Pmn Pin Function Select 0x400A_0200 PORGA Product Organize 0x400A_1000 ADC_D 12-bit A/D Converter 0x400A_1800 SAU0 Serial Array Unit 0 0x400A_2000 SAU1 Serial Array Unit 1 0x400A_2200 TAU Timer Array Unit 0x400A_2600 RTC_C Realtime Clock 0x400A_2C00 IICA I2C Bus Interface 0x400A_3000 UARTA Serial Interface UARTA 0x400A_3400 TML32 32-bit Interval Timer 0x400A_3800 PCLBUZ Clock Output/Buzzer Output Controller 0x400A_3B00 TRNG True Random Number Generator 0x400D_1000 FLCN Flash I/O Registers 0x407E_C000 Note: Name = Peripheral name Description = Peripheral functionality Base address = Lowest reserved address or address used by the peripheral

3.2 Access Cycles

This section provides access cycle information for the I/O registers described in this manual. The following information applies to Table A3.2: RA0E1 Datasheet Appendix 3. I/O Registers R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 81 of 86

Registers are grouped by associated module.
The number of access cycles indicates the number of cycles based on the specified reference clock.
In the internal I/O area, reserved addresses that are not allocated to registers must not be accessed, otherwise operations cannot be guaranteed.
The number of I/O access cycles depends on bus cycles of the internal peripheral bus, divided clock synchronization cycles, and wait cycles of each module. Note: This applies to the number of cycles when access from the CPU does not conflict with the instruction fetching to the external memory or bus access from other bus master such as DTC. Table A3.2 shows the register access cycles. Table A3.2 Access cycles Peripherals Address Number of access cycles From To Read Write Cycle unit Related function SRAM, BUS, DTC, ICU, DBG 0x4000_2000 0x4001_BFFF 3 ICLK Memory Protection Unit, SRAM, Buses, Data Transfer Controller, Interrupt Controller, CPU, Flash Memory SYSC 0x4001_E000 0x4001_E6FF 2 ICLK Low Power Modes, Resets, Low Voltage Detection, Clock Generation Circuit, Register Write Protection ELC, IWDT, MSTP 0x4004_0000 0x4004_7FFF 3 PCLKB Event Link Controller, Watchdog Timer, Module Stop Control CRC 0x4007_4000 0x4007_4FFF 3 PCLKB CRC Calculator PORT, PFS_A, PORGA, ADC12, SAU0, SAU1, TAU, RTC, IICA, UARTA, TML32, PCLBUZ 0x400A_0000 0x400A_3FFF 2 PCLKB I/O Ports, 12-bit A/D Converter, Serial Array Unit 0, Serial Array Unit 1, Timer Array Unit, Real time Clock, I2C Bus Interface, Serial Interface UARTA, 32- bit Interval Timer, Clock/Buzzer Output Controller TRNG 0x400D_1000 0x400D_1FFF 3 PCLKB True Random Number Generator FLCN 0x407E_C000 0x407E_FFFF 7 ICLK Data Flash, Flash Control RA0E1 Datasheet Appendix 3. I/O Registers R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 82 of 86

Appendix 4. Peripheral Variant Table A4.1 shows the correspondence between the module name used in this manual and the Peripheral Variant. Table A4.1 Module name vs Peripheral Variant Module name Peripheral Variant ADC12 ADC_D RTC RTC_C RA0E1 Datasheet Appendix 4. Peripheral Variant R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 83 of 86

Revision History

Revision 1.00 — January 31, 2024 Initial release Revision 1.10 — December 13, 2024 1. Overview:

Updated Figure 1.1 Block diagram.
Updated Figure 1.2 Part numbering scheme.
Updated Note in Table 1.14 Pin list. 2. Electrical Characteristics:
Updated Table 2.1 Absolute maximum ratings.
Updated 2.2.3 On-chip Oscillators Characteristics.
Updated Table 2.11 I/O other characteristics.
Updated Table 2.14 Peripheral Functions Supply current.
Added 2.3.3 Thermal Characteristics.
Updated Figure 2.13 Recovery timing from Software Standby mode to Snooze mode.
Updated Note in Figure 2.20 Timing of serial transfer in the simplified IIC communications with devices operating at same voltage levels.
Updated Note in Table 2.30 In simplified SPI communications in the master mode with devices operating at different voltage levels (2.5 V or 3 V) with the internal SCKp clock (the ratings below are only applicable to SPI00).
Updated the SCKp in Figure 2.28 Timing of serial transfer in the simplified SPI communications in the slave mode with devices operating at different voltage levels when SCRmn.DCP[1:0] = 01b or 10b.
Updated Note 2 in Table 2.49 Flash memory programming characteristics. Revision 1.20 — November 28, 2025 Features:
Updated Memory. 1. Overview:
Updated Figure 1.1 Block diagram.
Updated 1.3 Part Numbering.
Updated Table 1.13 Function comparison.
Updated Table 1.14 Pin functions.
Updated 1.6 Pin Assignments.
Updated Table 1.15 Pin list. 2. Electrical Characteristics:
Updated Table 2.12 Operating and standby current (1).
Updated Table 2.15 Thermal Resistance.
Updated Table 2.23 In UART communications with devices operating at the same voltage levels.
Updated 2.6.1 A/D Converter Characteristics.
Updated Table 2.44 Temperature sensor/internal reference voltage characteristics. Appendix 1. Port States in each Processing Mode:
Updated Table A1.1 Port states in each processing mode. Appendix 2. Package Dimensions:
Added Figure A2.5 TSSOP 20-pin. RA0E1 Datasheet Revision History R01DS0427EJ0120 Rev.1.20 Nov 28, 2025 Page 84 of 86

General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1. Precaution against Electrostatic Discharge (ESD) A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices. 2. Processing at power-on The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the level at which resetting is specified. 3. Input of signal during power-off state Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Follow the guideline for input signal during power-off state as described in your product documentation. 4. Handling of unused pins Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. 5. Clock signals After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable. 6. Voltage application waveform at input pin Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.). 7. Prohibition of access to reserved addresses Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these addresses as the correct operation of the LSI is not guaranteed. 8. Differences between products Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system- evaluation test for the given product.

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Product Information

RA0E1 specifications and overview.

Summary

Renesas Microcontrollers Rev.1.20 Nov 28, 2025

Description

Renesas Microcontrollers Rev.1.20 Nov 28, 2025

Source title RA0E1 Datasheet(PDF) - Renesas Technology Corp

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