R9A09G055MA3GBG

Renesas Technology Corp

RZ/V Series, VisionAI_ASSP RZ/V2MA Rev.1.00 Jul 24, 2024

Manufacturer: Renesas Technology Corp

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R01DS0459EJ0100 Rev.1.00 Page 1 of 79 Jul 24, 2024 DATASHEET Section 1 Overview

1.1 Features

This LSI chip is equipped with a highly power efficient AI accelerator (DRP-AI) and an OpenCV accelerator for pre/post AI processing. It realizes low power consumption of AI inference and allows for a variety of embedded AI products that require image streaming via USB, PCI Express®, or Gigabit Ethernet interfaces. The AI inference accelerator IP, DRP-AI, which consists of a dynamic reconfigurable processor (DRP) and AI-MAC, provides both high-speed AI inference and low power consumption at the same time. It delivers 1TOPS/W class power performance. The OpenCV accelerator powered by DRP delivers high-performance image processing functions. Application software can be accelerated without any API modification since the accelerator has the same API interface as Linux based open source. The LSI integrates Cortex-A53 dual CPU cores available to customers and is suitable for a variety of AI integrated applications such as AI gateway, machine vision, security gate, and mobile robot.  CPU and DDR Memory Interfaces

Cortex®-A53 Dual (996 MHz maximum)
32-bit LPDDR4-3200  Sensing and Analyzing
AI accelerator: DRP-AI (1.0 TOPS/W class)
OpenCV accelerator (DRP)  Video and Graphics
H.265/H.264 Multi Codec Encoding: H.265 up to 2160p, H.264 up to 1080p Decoding: H.265 up to 2160p, H.264 up to 1080p  High Speed Interfaces
1× Gigabit Ethernet
1× USB3.1 Gen1 Host/Peripheral
1× PCIe® Gen 2 (2 lanes)
2× SDIO 3.0
1× eMMC™ 4.5.1  Package
FCBGA (15×15 mm, 0.5-mm pitch) RZ/V Series, VisionAI_ASSP RZ/V2MA R01DS0459EJ0100 Rev.1.00 Jul 24, 2024

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 1 Overview R01DS0459EJ0100 Rev.1.00 Page 2 of 79 Jul 24, 2024 System Analog Timers WDT (2 ch.) Timer (32 ch.) PWM (16 ch.) Arm debugger (CoreSight) DMAC (16 ch.) Memory RAMA 200 KB Sensing and analyzing AI accelerator (DRP-AI) Video and graphics H.265/H.264 multi codec Temperature sensor (2 ch.) RAMB 1 MB External memory I/F LPDDR4 (32 bits) eMMC (1 ch.) Peripheral I/F SDI (2 ch.) USB3.1 (1 ch.) Host/Peripheral PCI Express (2 lanes) Ethernet MAC (1 ch.) IIC (4 ch.) CSI (6 ch.) UART (2 ch.) GPIO CPU Arm Cortex-A53 L2 cache: 512 KB Core 0 L1 I cache 32 KB Neon FPU L1 D cache 32 KB Core 1 L1 I cache 32 KB Neon FPU L1 D cache 32 KB OpenCV accelerator (DRP) Power control Figure 1.1-1 Diagram of Functional Overview

1.2 Product Lineup

The group currently consists of the following products. Table 1.2-1 Product Lineup Product Part Number Part Number for Ordering Package Packing R9A09G055MA3GBG R9A09G055MA3GBG#ACC PRBG0841KA-A Individual tray R9A09G055MA3GBG#BCC PRBG0841KA-A Full carton

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 1 Overview R01DS0459EJ0100 Rev.1.00 Page 3 of 79 Jul 24, 2024

1.3 Functions

Table 1.3-1 Overview of Functions (1/2) Item Function CPU ● Arm® Cortex-A53 dual core (CA53): 996 MHz – L1 cache: 32 KB (for instructions) + 32 KB (for data) for each core – L2 cache: 512 KB – FPU, Neon™ extension – ECC supported

Debugger interface (JTAG/SWD) – CoreSight™ debugging components incorporated – ETF (64-Kbyte trace RAM), ETR, and STM incorporated – External trace output (16-bit width) Memory ● RAM A (RAMA): 200 KB (with ECC)
RAM B (RAMB): 1 MB
ROM: 128 KB Timers ● Watchdog timer (WDT): 2 channels (CA53 core 0, CA53 core 1)
Compare-match timer: 32 channels
Pulse-width modulation timer (PWM): 16 channels DMA controller DMA controller (16 channels) Sensing and analyzing ● AI accelerator (DRP-AI)
OpenCV accelerator Video & graphics ● H.265/H.264 multi codec – Supported functions H.265 encoding and H.265 decoding, or H.264 encoding and H.264 decoding – Support encoding/decoding standard H.265/HEVC main profile at level 5 H.264/AVC constrained baseline/main/high profile at level 4.2 – I-/P-slice supported for H.264/H.265 encoding and decoding – H.265 encoding and decoding performance 3840 × 2160 p encoding, 3840 × 2160 p decoding – H.264 encoding and decoding performance 1920 × 1080 p encoding, 1920 × 1080 p decoding External memory interfaces ● LPDDR4 interface – 3200 Mbps – 32-bit data width – Up to 4 GB supported
eMMC interface conforming to eMMC version 4.51 – Supports HS200 (high-speed DDR and HS400 are not supported) – 1/4/8-bit data bus

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 1 Overview R01DS0459EJ0100 Rev.1.00 Page 4 of 79 Jul 24, 2024 Table 1.3-1 Overview of Functions (2/2) Item Function Peripheral interfaces ● SD host interface (SDI): 2 channels (SD specification version 3.01 compliant) – SD memory / I/O card interface (1-bit/4-bit SD bus) – SD memory card access for SD, SDHC, and SDXC – Supports default, high-speed, UHS-I/SDR12, SDR25, SDR50, and SDR104 transfer modes (DDR50, not supported) – Supports card detection and write protection

USB interface: 1 channel – USB3.1 Gen1 standard compliant – Dual-role device function supported (static switching of the host controller function and the peripheral controller function) – Supports super-speed (5 Gbps), high-speed (480 Mbps), full-speed (12 Mbps), and low- speed (1.5 Mbps) transfer (low-speed is only supported for the host controller)
PCI Express interface Gen2 (5GT/s): 2 lanes – PCI Express base specification revision 4.0 compliant – Supports root complex/endpoint
Ethernet MAC interface: 1 channel – Supports transfer at 1000 Mbps, and 100 Mbps in full-duplex mode – Supports IEEE802.3 PHY GMII, MII compliant interface
IIC bus interface: 4 channels
Clocked serial interface: 6 channels
UART: 2 channels
GPIO Analog ● Temperature sensor: 2 channels Power control ● External power supply sequence control
Internal power domain control Power voltage ● 0.8-V power supply VDD08, UnVDD08 (n = 2, 3, 4, 7), RTVDD08, PWVDD08, LPVDD, PLDVDD08n (n = 1, 2, 3, 4, 6), OTVDD08, TSnDVDD08A (n = 0, 1), PCVDD08, USDVDD, USVP, USVPTX
1.1-V power supply LPVDDQ
1.5-V power supply RTVDD
1.8-V power supply PLVDDn (n = 1, 2, 3, 4, 6), OTVDD18, TSnAVDD18 (n = 0, 1), LPVAA, PCVDD18, USVDDH, PWVDD, VDD18, PAPREDVDD, PBPREDVDD, PCPREDVDD, MMPREDVDD, SD0PREDVDD, SD1FVDD, GEPREDVDD, PREDVDD33, UnVDD18 (n = 10, 11, 2, 3, 4, 5, 6, 7)
3.3-V power supply USVD330, USVPH, VDD33
3.3-V/1.8-V switchable power supply PAMODVDD, PBMODVDD, PCMODVDD, MMMODVDD, SD0MODVDD, SD1FMODVDD, GEMODVDD, UnMODVDD (n = 10, 11) Operating temperature Tj = 103ºC (max.) Tj: Junction temperature

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 5 of 79 Jul 24, 2024 Section 2 Pins

2.1 Pin Assignment

A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ 29 GND RTXIN GND LPDQSAT1 LPDQSAC1 LPDQA14 LPDQA12 LPVDDQ LPDQA6 GND LPDQA4 LPVDDQ LPCSA0 GND LPMRESETL LPVDDQ LPVAA LPZN GND LPVDDQ GND LPDMDBIB0 LPVDDQ LPDQB12 LPDQB15 LPDQSBC1 LPDQSBT1 GND GND 29 28 RTXOUT RTRSTN RTISO GND LPDQA10 LPDQA11 GND LPVDDQ GND LPDQA5 GND LPVDDQ GND LPCAA1 GND LPVDDQ LPVAA GND LPCKEB0 LPVDDQ LPDQB7 GND LPVDDQ GND LPDQB14 LPDQB11 GND P0013 RFU3 28 27 PWEN1 RETESTH6 PWISO PWRSTN GND LPDMDBIA1 LPDQA15 LPVDDQ LPDMDBIA0 LPDQA3 LPDQA7 LPVDDQ LPCKEA0 LPCKEA1 LPCAB2 LPVDDQ GND LPCAB1 LPCKEB1 LPVDDQ LPDQB5 LPDQB6 LPVDDQ LPDQB13 LPDMDBIB1 GND P0012 P0009 MMDAT5 27 RETESTH2 RFU0 RETESTH1 RETESTH4 GND LPDQA9 LPDQA13 LPVDDQ LPDQA1 LPDQSAT0 LPDQSAC0 LPVDDQ LPCAA0 LPCSA1 LPCAB5 LPVDDQ LPCLKBT LPCSB1 LPCAB0 LPVDDQ LPDQB3 LPDQB1 LPVDDQ LPDQB9 LPDQB10 GND MMCLK GND MMPREDVDD 25 RTVDD GND RETESTH0 PWEN3 RFU1 GND LPDQA8 GND LPDQA2 GND LPCAA4 GND LPCAA5 GND LPCAB4 GND LPCLKBC LPCSB0 GND GND LPDQSBC0 LPDQB2 GND LPDQB8 GND P0008 GND MMMODVDD MMMODVDD 24 RTVDD08 PWSD0SEL RETESTH3 PWEN5 PWEN2 PWEN0 GND GND GND LPDQA0 LPCAA3 GND LPCAA2 LPCLKAT LPCLKAC GND LPCAB3 GND LPDQB4 GND LPDQSBT0 LPDQB0 GND GND MMCMD MMDAT3 MMDAT0 MMDAT6 MMDAT4 24 PWVDD08 PWCTEST1 RFU2 PWSD1SEL PWEN4 RETESTH5 PWSYSRSTN GND GND GND GND GND GND GND LPATEST GND LPDTEST GND GND GND GND GND GND MMDAT1 MMDAT7 MMDAT2 GND U3REF U3REF 23 22 PWVDD GND PWTEST PWME MSWI E NA PWCTEST0 GND GND GND GND GND GND GND GND GND GND GND GND GND GND U3VDD18 GND GND GND GND GND GND GND RFU6 RFU7 22 U5GND10 U5GND9 U5GND5 U5GND3 U5GND2 U5GND1 U5GND0 GND GND GND LPVDD LPVDD LPVDD LPVDD LPVDD LPVDD LPVDD LPVDD LPVDD U3VDD18 GND U3GND1 U3GND0 RFU8 RFU9 RFU15 RFU14 GND GND 21 20 U5GND8 U5GND11 U5GND7 U5GND4 U5GND6 U5VSS U5VDD18 GND VDD08 GND VDD08 GND VDD08 GND GND PLVDD3 TS1AVDD18 GND VDD08 GND U3VDD08 U3GND3 U3GND2 RFU10 RFU11 RFU12 RFU13 GND RFU16 20 19 U6GND7 U6GND5 U6GND4 U6GND1 U6GND3 U6VSS U6VDD18 GND VDD08 GND VDD08 GND VDD08 GND PLDVDD083 PLVSS3 TS1DVDD08A GND VDD08 GND U3VDD08 VDD18 GND GND GND GND GND U4VDD18 U4VDD18 SD0MODVDD SD0WP SD0DAT1 SD0CLK U6GND6 U6GND2 U6GND0 GND GND VDD08 GND VDD08 GND VDD08 GND VDD08 GND VDD08 GND U4VDD08 U4VDD08 GND RFU22 RFU21 GND RFU24 RFU23 GND P2001 18 SD1FMODVDD GND SD1FCLK SD0DAT2 SD0CMD SD0CD SD0DAT0 SD0PREDVDD GND VDD08 GND VDD08 GND VDD08 GND VDD08 GND VDD08 U7VDD18 U7VSS U7VDD08 GND RFU20 RFU19 GND RFU18 RFU17 GND P2002 17 16 SD1FVDD SD1FCD SD1FDAT1 SD0DAT3 SD1FCMD SD1FDAT0 GND GND VDD08 GND VDD08 GND VDD08 PLDVDD081 PLVSS1 PLVDD1 VDD08 GND VDD08 GND USDVDD USVP GND GND GND GND GND P2000 RFU25 16 15 PCREXT GND GND GND SD1FDAT3 SD1FWP SD1FDAT2 GND VDD08 GND VDD08 GND VDD08 PLDVDD082 PLVSS2 PLVDD2 VDD08 GND VDD08 GND USDVDD USVPTX GND GND USRX0M USRX0P GND GND USVDDH 15 14 GND GND PCRXD1M PCRXD1P GND PCVDD18 PCVDD18 PCVDD08 GND VDD08 GND VDD08 GND PLDVDD084 PLVSS4 PLVDD4 GND VDD08 GND VDD08 GND GND USTX0M USTX0P GND GND USOTGID USVPH USVD330 14 PCTXD1M PCTXD1P GND GND GND PCVDD18 PCVDD18 PCVDD08 GND VDD08 GND VDD08 GND PLDVDD086 PLVSS6 PLVDD6 GND VDD08 GND VDD08 GND RSTN GND GND USDM USDP GND USVBUS USRESREF 12 GND GND PCRXD0M PCRXD0P GND GND U2VSS U2VDD08 VDD08 GND VDD08 GND VDD08 GND VDD08 GND VDD08 GND VDD08 GND VDD08 GND GERXD4 GERXD6 GND GND GERXD5 GND XOUT 12 PCTXD0M PCTXD0P GND GND GND U2VSS U2VSS U2VDD08 VDD08 GND VDD08 GND VDD08 GND VDD08 GND VDD08 GND VDD08 GND VDD08 GND GND GERXD2 GERXD1 GECRS GERXC GND XIN 11 RETESTRL GND PCREFCKP PCREFCKM U2VSS U2VSS U2VSS U2VDD08 GND TS0DVDD08A GND VDD08 GND VDD08 GND VDD08 GND VDD08 GND VDD08 GND GND PM3 PM6 GERXER GERXDV GND GEMODVDD GEMODVDD U2VDD18 U2VDD18 U2VSS U2VSS U2VSS U2VSS U2VSS U2VDD08 GND OTVDD08 GND VDD08 GND VDD08 GND VDD08 GND VDD08 GND VDD08 GND GND GND PM2 GND GEINT GELINK GETXER GEPREDVDD 8 U2GND1 U2GND0 U2GND3 U2GND2 U2GND9 U2GND8 GND GND PM11 PM12 PM10 MD8 P1309 RETEST1 P1300 GND P1302 MD0 MD1 MD4 MD5 P0600 P0602 PM1 PM7 GETXD3 GETXD4 GND PAPREDVDD 7 U2VSS U2VSS U2VSS U2VSS U2VSS U2VSS CSSCLK4 CSTXD4 PM13 PM14 PM8 PM9 P1402 P1310 P1311 P1305 P1401 PCRSTOUTB MD2 MD7 MD6 P0608 P0601 PM0 PM5 PM4 GND PAMODVDD PAMODVDD 6 U2GND5 U2GND4 U2GND7 U2GND6 U2GND19 U2GND18 GND CSCS4 P0705 GND PM15 P1002 RETEST0 P1301 P1308 P1304 P1405 USOVC INEXINT5 MD3 INEXINT4 P0610 P0604 CSCS2 CSRXD2 CSSCLK3 GEGTXCLK GEMDIO GECOL 6 U2VDD18 U2VDD18 U2VDD18 U2VDD18 U2VSS U2VSS CSRXD4 CSSCLK5 GND P0701 P1003 P1007 P1200 GND P1400 P1406 GND DETCK DETDO INEXINT3 GND P0606 P0611 CSTXD2 CSSCLK2 GND GETXD6 GETXD2 P1700 5 U2GND11 U2GND10 U2GND13 U2GND12 U2VSS P1006 CSTXD5 CSCS5 P0704 P0700 P1008 P1202 P1201 P1307 P1404 GND DETMS DETDI INEXINT1 INEXINT7 I2SCL0 GND P0603 CSRXD0 CSCS1 CSCS3 GETXD5 GETXD1 GEMDC 4 3 U2VSS U2VSS U2VSS U2VSS P1004 RFU4 P1104 CSRXD5 GND P0703 P1107 P1203 GND DETRSTN P1303 PREDVDD33 DESRSTN GND INEXINT0 GND I2SCL1 P0609 P0607 CSTXD0 CSTXD1 CSTXD3 GETXD7 GERXD0 GERXD7 3 U2GND15 U2GND14 U2GND17 U2GND16 GND P1106 P1102 P1108 TS0AVDD18 P0702 P1100 P1105 PBMODVDD P1407 USPWEN U11VDD18 U11MODVDD VDD33 INEXINT2 VDD18 I2SDA0 GND P0605 CSCS0 CSSCLK1 GND GETXC GECLK GERXD3 2 1 U2VSS U2VSS U2VSS U2VSS P1005 P1103 P1000 RFU5 OTVDD18 P1001 P1101 PBPREDVDD PBMODVDD P1403 P1306 U10VDD18 U10MODVDD VDD33 INEXINT6 VDD18 I2SDA1 PCMODVDD PCPREDVDD CSSCLK0 CSRXD1 CSRXD3 GETXD0 GETXEN GND 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ Figure 2.1-1 Pin Assignment (Top view)

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 6 of 79 Jul 24, 2024 Table 2.1-1 Ball Numbers and External Pin Names (1/5) Ball Num. External Pin Name Ball Num. External Pin Name Ball Num. External Pin Name Ball Num. External Pin Name A1 U2VSS B17 GND D4 U2GND12 E20 U5GND6 A2 U2GND15 B18 SD0WP D5 U2VDD18 E21 U5GND2 A3 U2VSS B19 U6GND5 D6 U2GND6 E22 PWCTEST0 A4 U2GND11 B20 U5GND11 D7 U2VSS E23 PWEN4 A5 U2VDD18 B21 U5GND9 D8 U2GND2 E24 PWEN2 A6 U2GND5 B22 GND D9 U2VSS E25 RFU1 A7 U2VSS B23 PWCTEST1 D10 PCREFCKM E26 GND A8 U2GND1 B24 PWSD0SEL D11 GND E27 GND A9 U2VDD18 B25 GND D12 PCRXD0P E28 LPDQA10 A10 RETESTRL B26 RFU0 D13 GND E29 LPDQSAC1 A11 PCTXD0M B27 RETESTH6 D14 PCRXD1P F1 P1103 A12 GND B28 RTRSTN D15 GND F2 P1106 A13 PCTXD1M B29 RTXIN D16 SD0DAT3 F3 RFU4 A14 GND C1 U2VSS D17 SD0DAT2 F4 P1006 A15 PCREXT C2 U2GND17 D18 SD0CLK F5 U2VSS A16 SD1FVDD C3 U2VSS D19 U6GND1 F6 U2GND18 A17 SD1FMODVDD C4 U2GND13 D20 U5GND4 F7 U2VSS A18 SD0MODVDD C5 U2VDD18 D21 U5GND3 F8 U2GND8 A19 U6GND7 C6 U2GND7 D22 PWMEMSWIENA F9 U2VSS A20 U5GND8 C7 U2VSS D23 PWSD1SEL F10 U2VSS A21 U5GND10 C8 U2GND3 D24 PWEN5 F11 U2VSS A22 PWVDD C9 U2VSS D25 PWEN3 F12 GND A23 PWVDD08 C10 PCREFCKP D26 RETESTH4 F13 PCVDD18 A24 RTVDD08 C11 GND D27 PWRSTN F14 PCVDD18 A25 RTVDD C12 PCRXD0M D28 GND F15 SD1FWP A26 RETESTH2 C13 GND D29 LPDQSAT1 F16 SD1FDAT0 A27 PWEN1 C14 PCRXD1M E1 P1005 F17 SD0CD A28 RTXOUT C15 GND E2 GND F18 U6GND2 A29 GND C16 SD1FDAT1 E3 P1004 F19 U6VSS B1 U2VSS C17 SD1FCLK E4 U2VSS F20 U5VSS B2 U2GND14 C18 SD0DAT1 E5 U2VSS F21 U5GND1 B3 U2VSS C19 U6GND4 E6 U2GND19 F22 GND B4 U2GND10 C20 U5GND7 E7 U2VSS F23 RETESTH5 B5 U2VDD18 C21 U5GND5 E8 U2GND9 F24 PWEN0 B6 U2GND4 C22 PWTEST E9 U2VSS F25 GND B7 U2VSS C23 RFU2 E10 U2VSS F26 LPDQA9 B8 U2GND0 C24 RETESTH3 E11 GND F27 LPDMDBIA1 B9 U2VDD18 C25 RETESTH0 E12 GND F28 LPDQA11 B10 GND C26 RETESTH1 E13 GND F29 LPDQA14 B11 PCTXD0P C27 PWISO E14 GND G1 P1000 B12 GND C28 RTISO E15 SD1FDAT3 G2 P1102 B13 PCTXD1P C29 GND E16 SD1FCMD G3 P1104 B14 GND D1 U2VSS E17 SD0CMD G4 CSTXD5 B15 GND D2 U2GND16 E18 U6GND6 G5 CSRXD4 B16 SD1FCD D3 U2VSS E19 U6GND3 G6 GND

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 7 of 79 Jul 24, 2024 Table 2.1-1 Ball Numbers and External Pin Names (2/5) Ball Num. External Pin Name Ball Num. External Pin Name Ball Num. External Pin Name Ball Num. External Pin Name G7 CSSCLK4 H23 GND K10 TS0DVDD08A L26 LPDQSAC0 G8 GND H24 GND K11 GND L27 LPDQA7 G9 U2VSS H25 GND K12 GND L28 GND G10 U2VSS H26 LPVDDQ K13 VDD08 L29 LPDQA4 G11 U2VSS H27 LPVDDQ K14 VDD08 M1 PBPREDVDD G12 U2VSS H28 LPVDDQ K15 GND M2 P1105 G13 PCVDD18 H29 LPVDDQ K16 GND M3 P1203 G14 PCVDD18 J1 OTVDD18 K17 VDD08 M4 P1202 G15 SD1FDAT2 J2 TS0AVDD18 K18 VDD08 M5 P1007 G16 GND J3 GND K19 GND M6 P1002 G17 SD0DAT0 J4 P0704 K20 GND M7 PM9 G18 U6GND0 J5 GND K21 GND M8 MD8 G19 U6VDD18 J6 P0705 K22 GND M9 VDD08 G20 U5VDD18 J7 PM13 K23 GND M10 VDD08 G21 U5GND0 J8 PM11 K24 LPDQA0 M11 GND G22 GND J9 GND K25 GND M12 GND G23 PWSYSRSTN J10 GND K26 LPDQSAT0 M13 VDD08 G24 GND J11 VDD08 K27 LPDQA3 M14 VDD08 G25 LPDQA8 J12 VDD08 K28 LPDQA5 M15 GND G26 LPDQA13 J13 GND K29 GND M16 GND G27 LPDQA15 J14 GND L1 P1101 M17 VDD08 G28 GND J15 VDD08 L2 P1100 M18 VDD08 G29 LPDQA12 J16 VDD08 L3 P1107 M19 GND H1 RFU5 J17 GND L4 P1008 M20 GND H2 P1108 J18 GND L5 P1003 M21 LPVDD H3 CSRXD5 J19 VDD08 L6 PM15 M22 GND H4 CSCS5 J20 VDD08 L7 PM8 M23 GND H5 CSSCLK5 J21 GND L8 PM10 M24 GND H6 CSCS4 J22 GND L9 GND M25 GND H7 CSTXD4 J23 GND L10 GND M26 LPVDDQ H8 GND J24 GND L11 VDD08 M27 LPVDDQ H9 U2VDD08 J25 LPDQA2 L12 VDD08 M28 LPVDDQ H10 U2VDD08 J26 LPDQA1 L13 GND M29 LPVDDQ H11 U2VDD08 J27 LPDMDBIA0 L14 GND N1 PBMODVDD H12 U2VDD08 J28 GND L15 VDD08 N2 PBMODVDD H13 PCVDD08 J29 LPDQA6 L16 VDD08 N3 GND H14 PCVDD08 K1 P1001 L17 GND N4 P1201 H15 GND K2 P0702 L18 GND N5 P1200 H16 GND K3 P0703 L19 VDD08 N6 RETEST0 H17 SD0PREDVDD K4 P0700 L20 VDD08 N7 P1402 H18 GND K5 P0701 L21 LPVDD N8 P1309 H19 GND K6 GND L22 GND N9 GND H20 GND K7 PM14 L23 GND N10 GND H21 GND K8 PM12 L24 LPCAA3 N11 VDD08 H22 GND K9 OTVDD08 L25 LPCAA4 N12 VDD08

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 8 of 79 Jul 24, 2024 Table 2.1-1 Ball Numbers and External Pin Names (3/5) Ball Num. External Pin Name Ball Num. External Pin Name Ball Num. External Pin Name Ball Num. External Pin Name N13 GND P29 GND T16 PLVDD1 V3 GND N14 GND R1 P1306 T17 VDD08 V4 DETDI N15 VDD08 R2 USPWEN T18 VDD08 V5 DETCK N16 VDD08 R3 P1303 T19 PLVSS3 V6 USOVC N17 GND R4 P1404 T20 PLVDD3 V7 PCRSTOUTB N18 GND R5 P1400 T21 LPVDD V8 MD0 N19 VDD08 R6 P1308 T22 GND V9 VDD08 N20 VDD08 R7 P1311 T23 GND V10 VDD08 N21 LPVDD R8 P1300 T24 GND V11 GND N22 GND R9 GND T25 GND V12 GND N23 GND R10 GND T26 LPVDDQ V13 VDD08 N24 LPCAA2 R11 VDD08 T27 LPVDDQ V14 VDD08 N25 LPCAA5 R12 VDD08 T28 LPVDDQ V15 GND N26 LPCAA0 R13 PLVSS6 T29 LPVDDQ V16 GND N27 LPCKEA0 R14 PLVSS4 U1 U10MODVDD V17 VDD08 N28 GND R15 PLVSS2 U2 U11MODVDD V18 VDD08 N29 LPCSA0 R16 PLVSS1 U3 DESRSTN V19 GND P1 P1403 R17 GND U4 DETMS V20 GND P2 P1407 R18 GND U5 GND V21 LPVDD P3 DETRSTN R19 PLDVDD083 U6 P1405 V22 GND P4 P1307 R20 GND U7 P1401 V23 GND P5 GND R21 LPVDD U8 P1302 V24 GND P6 P1301 R22 GND U9 GND V25 LPCSB0 P7 P1310 R23 LPATEST U10 GND V26 LPCSB1 P8 RETEST1 R24 LPCLKAC U11 VDD08 V27 LPCAB1 P9 VDD08 R25 LPCAB4 U12 VDD08 V28 GND P10 VDD08 R26 LPCAB5 U13 GND V29 LPZN P11 GND R27 LPCAB2 U14 GND W1 INEXINT6 P12 GND R28 GND U15 VDD08 W2 INEXINT2 P13 PLDVDD086 R29 LPMRESETL U16 VDD08 W3 INEXINT0 P14 PLDVDD084 T1 U10VDD18 U17 GND W4 INEXINT1 P15 PLDVDD082 T2 U11VDD18 U18 GND W5 DETDO P16 PLDVDD081 T3 PREDVDD33 U19 TS1DVDD08A W6 INEXINT5 P17 VDD08 T4 GND U20 TS1AVDD18 W7 MD2 P18 VDD08 T5 P1406 U21 LPVDD W8 MD1 P19 GND T6 P1304 U22 GND W9 GND P20 GND T7 P1305 U23 LPDTEST W10 GND P21 LPVDD T8 GND U24 LPCAB3 W11 VDD08 P22 GND T9 VDD08 U25 LPCLKBC W12 VDD08 P23 GND T10 VDD08 U26 LPCLKBT W13 GND P24 LPCLKAT T11 GND U27 GND W14 GND P25 GND T12 GND U28 LPVAA W15 VDD08 P26 LPCSA1 T13 PLVDD6 U29 LPVAA W16 VDD08 P27 LPCKEA1 T14 PLVDD4 V1 VDD33 W17 U7VDD18 P28 LPCAA1 T15 PLVDD2 V2 VDD33 W18 GND

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 9 of 79 Jul 24, 2024 Table 2.1-1 Ball Numbers and External Pin Names (4/5) Ball Num. External Pin Name Ball Num. External Pin Name Ball Num. External Pin Name Ball Num. External Pin Name W19 VDD08 AA6 INEXINT4 AB22 GND AD9 PM2 W20 VDD08 AA7 MD6 AB23 GND AD10 PM6 W21 LPVDD AA8 MD5 AB24 LPDQB0 AD11 GERXD2 W22 GND AA9 GND AB25 LPDQB2 AD12 GERXD6 W23 GND AA10 GND AB26 LPDQB1 AD13 GND W24 LPDQB4 AA11 VDD08 AB27 LPDQB6 AD14 USTX0P W25 GND AA12 VDD08 AB28 GND AD15 GND W26 LPCAB0 AA13 GND AB29 LPDMDBIB0 AD16 GND W27 LPCKEB1 AA14 GND AC1 PCPREDVDD AD17 RFU19 W28 LPCKEB0 AA15 USDVDD AC2 P0605 AD18 RFU21 W29 GND AA16 USDVDD AC3 P0607 AD19 GND Y1 VDD18 AA17 U7VDD08 AC4 P0603 AD20 RFU10 Y2 VDD18 AA18 U4VDD08 AC5 P0611 AD21 RFU8 Y3 GND AA19 U3VDD08 AC6 P0604 AD22 GND Y4 INEXINT7 AA20 U3VDD08 AC7 P0601 AD23 MMDAT1 Y5 INEXINT3 AA21 GND AC8 P0602 AD24 GND Y6 MD3 AA22 GND AC9 GND AD25 LPDQB8 Y7 MD7 AA23 GND AC10 PM3 AD26 LPDQB9 Y8 MD4 AA24 LPDQSBT0 AC11 GND AD27 LPDQB13 Y9 VDD08 AA25 LPDQSBC0 AC12 GERXD4 AD28 GND Y10 VDD08 AA26 LPDQB3 AC13 GND AD29 LPDQB12 Y11 GND AA27 LPDQB5 AC14 USTX0M AE1 CSRXD1 Y12 GND AA28 LPDQB7 AC15 GND AE2 CSSCLK1 Y13 VDD08 AA29 GND AC16 GND AE3 CSTXD1 Y14 VDD08 AB1 PCMODVDD AC17 RFU20 AE4 CSCS1 Y15 GND AB2 GND AC18 RFU22 AE5 CSSCLK2 Y16 GND AB3 P0609 AC19 GND AE6 CSRXD2 Y17 U7VSS AB4 GND AC20 U3GND2 AE7 PM5 Y18 U4VDD08 AB5 P0606 AC21 U3GND0 AE8 PM7 Y19 GND AB6 P0610 AC22 GND AE9 GND Y20 GND AB7 P0608 AC23 GND AE10 GERXER Y21 U3VDD18 AB8 P0600 AC24 GND AE11 GERXD1 Y22 U3VDD18 AB9 GND AC25 GND AE12 GND Y23 GND AB10 GND AC26 LPVDDQ AE13 USDM Y24 GND AB11 GND AC27 LPVDDQ AE14 GND Y25 GND AB12 GND AC28 LPVDDQ AE15 USRX0M Y26 LPVDDQ AB13 RSTN AC29 LPVDDQ AE16 GND Y27 LPVDDQ AB14 GND AD1 CSSCLK0 AE17 GND Y28 LPVDDQ AB15 USVPTX AD2 CSCS0 AE18 GND Y29 LPVDDQ AB16 USVP AD3 CSTXD0 AE19 GND AA1 I2SDA1 AB17 GND AD4 CSRXD0 AE20 RFU11 AA2 I2SDA0 AB18 GND AD5 CSTXD2 AE21 RFU9 AA3 I2SCL1 AB19 VDD18 AD6 CSCS2 AE22 GND AA4 I2SCL0 AB20 U3GND3 AD7 PM0 AE23 MMDAT7 AA5 GND AB21 U3GND1 AD8 PM1 AE24 MMCMD

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 10 of 79 Jul 24, 2024 Table 2.1-1 Ball Numbers and External Pin Names (5/5) Ball Num. External Pin Name Ball Num. External Pin Name Ball Num. External Pin Name Ball Num. External Pin Name AE25 GND AF27 GND AG29 LPDQSBT1 AJ2 GERXD3 AE26 LPDQB10 AF28 LPDQB11 AH1 GETXEN AJ3 GERXD7 AE27 LPDMDBIB1 AF29 LPDQSBC1 AH2 GECLK AJ4 GEMDC AE28 LPDQB14 AG1 GETXD0 AH3 GERXD0 AJ5 P1700 AE29 LPDQB15 AG2 GETXC AH4 GETXD1 AJ6 GECOL AF1 CSRXD3 AG3 GETXD7 AH5 GETXD2 AJ7 PAMODVDD AF2 GND AG4 GETXD5 AH6 GEMDIO AJ8 PAPREDVDD AF3 CSTXD3 AG5 GETXD6 AH7 PAMODVDD AJ9 GEPREDVDD AF4 CSCS3 AG6 GEGTXCLK AH8 GND AJ10 GEMODVDD AF5 GND AG7 GND AH9 GETXER AJ11 XIN AF6 CSSCLK3 AG8 GETXD4 AH10 GEMODVDD AJ12 XOUT AF7 PM4 AG9 GELINK AH11 GND AJ13 USRESREF AF8 GETXD3 AG10 GND AH12 GND AJ14 USVD330 AF9 GEINT AG11 GERXC AH13 USVBUS AJ15 USVDDH AF10 GERXDV AG12 GERXD5 AH14 USVPH AJ16 RFU25 AF11 GECRS AG13 GND AH15 GND AJ17 P2002 AF12 GND AG14 USOTGID AH16 P2000 AJ18 P2001 AF13 USDP AG15 GND AH17 GND AJ19 U4VDD18 AF14 GND AG16 GND AH18 GND AJ20 RFU16 AF15 USRX0P AG17 RFU17 AH19 U4VDD18 AJ21 GND AF16 GND AG18 RFU23 AH20 GND AJ22 RFU7 AF17 RFU18 AG19 GND AH21 GND AJ23 U3REF AF18 RFU24 AG20 RFU13 AH22 RFU6 AJ24 MMDAT4 AF19 GND AG21 RFU14 AH23 U3REF AJ25 MMMODVDD AF20 RFU12 AG22 GND AH24 MMDAT6 AJ26 MMPREDVDD AF21 RFU15 AG23 GND AH25 MMMODVDD AJ27 MMDAT5 AF22 GND AG24 MMDAT0 AH26 GND AJ28 RFU3 AF23 MMDAT2 AG25 GND AH27 P0009 AJ29 GND AF24 MMDAT3 AG26 MMCLK AH28 P0013 — — AF25 P0008 AG27 P0012 AH29 GND — — AF26 GND AG28 GND AJ1 GND — —

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 11 of 79 Jul 24, 2024

2.2 External Pins

2.2.1 List of External Pins

Table 2.2-1 List of External Pins (1/16) Pin Name I/O Voltage (V) I/O Group Initial Value after Power- on Reset Pin State when not in Use Input Output Multiplexed Pin Schmitt Trigger Pull-up/ Pull-down N-ch Open- Drain Drive Strength Selectable / Fixed RTXIN I 1.5 1.5-V OSC CLOCK Pull down — — — — — RTXOUT O 1.5 1.5-V OSC CLOCK Open — — — — — RTRSTN I 1.5 PWC I/O Don’t care Pull down  — — — — RTISO I 1.5 PWC I/O Hi-Z Pull up  — — — — RTVDD — 1.5 PWC I/O, PWC clock power supply RTVDD08 — 0.8 XTAL power supply — — — — — — — PWRSTN I 1.8 PWC I/O Don’t care Pull down  — — — — PWTEST I 1.8 PWC I/O Don’t care Pull down  — — — — PWEN0 O 1.8 PWC I/O L Open — — — Fixed*2 — PWEN1 O 1.8 PWC I/O L Open — — — Fixed*2 — PWEN2 O 1.8 PWC I/O L Open — — — Fixed*2 — PWEN3 O 1.8 PWC I/O L Open — — — Fixed*2 — PWEN4 O 1.8 PWC I/O L Open — — — Fixed*2 — PWEN5 O 1.8 PWC I/O L Open — — — Fixed*2 — PWSYSRSTN O 1.8 PWC I/O L Open — —  Fixed*2 — PWSD0SEL O 1.8 PWC I/O L Open — — — Fixed*2 — PWSD1SEL O 1.8 PWC I/O L Open — — — Fixed*2 — PWCTEST0 O 1.8 PWC I/O L Open — — — Fixed*2 — PWCTEST1 I 1.8 PWC I/O Don’t care Pull up  — — — — PWMEMSWIENA O 1.8 PWC I/O L Open — — — Fixed*2 — PWISO O 1.8 PWC I/O Hi-Z Open — —  Fixed*2 — PWVDD08 — 0.8 PWC core power supply PWVDD — 1.8 PWC I/O power supply MMDAT0 IO 3.3/1.8 PORT00 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*

2 Multiplexed

pin (see Table 2.2-2 and Table 2.2-3) MMDAT1 IO 3.3/1.8 PORT00 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-3) MMDAT2 IO 3.3/1.8 PORT00 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-3) MMDAT3 IO 3.3/1.8 PORT00 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-3) MMDAT4 IO 3.3/1.8 PORT00 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-3) MMDAT5 IO 3.3/1.8 PORT00 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-3) MMDAT6 IO 3.3/1.8 PORT00 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-3)

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 12 of 79 Jul 24, 2024 Table 2.2-1 List of External Pins (2/16) Pin Name I/O Voltage (V) I/O Group Initial Value after Power- on Reset Pin State when not in Use Input Output Multiplexed Pin Schmitt Trigger Pull-up/ Pull-down N-ch Open- Drain Drive Strength Selectable / Fixed MMDAT7 IO 3.3/1.8 PORT00 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-3) P0008 IO 3.3/1.8 PORT00 I/O PU Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-3) P0009 IO 3.3/1.8 PORT00 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-3) MMCMD IO 3.3/1.8 PORT00 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-3) MMCLK IO 3.3/1.8 PORT00 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-3) P0012 IO 3.3/1.8 PORT00 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-3) P0013 IO 3.3/1.8 PORT00 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-3) MMMODVDD — 3.3/1.8 PORT00 I/O power supply MMPREDVDD — 1.8 PORT00 pre-driver power supply PM0 IO 3.3/1.8 PORT01(A) I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-4) PM1 IO 3.3/1.8 PORT01(A) I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-4) PM2 IO 3.3/1.8 PORT01(A) I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-4) PM3 IO 3.3/1.8 PORT01(A) I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-4) PM4 IO 3.3/1.8 PORT01(A) I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-4) PM5 IO 3.3/1.8 PORT01(A) I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-4) PM6 IO 3.3/1.8 PORT01(A) I/O PD Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-4) PM7 IO 3.3/1.8 PORT01(A) I/O PD Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-4) PAMODVDD — 3.3/1.8 PORT01(A), PORT03 I/O power supply

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 13 of 79 Jul 24, 2024 Table 2.2-1 List of External Pins (3/16) Pin Name I/O Voltage (V) I/O Group Initial Value after Power- on Reset Pin State when not in Use Input Output Multiplexed Pin Schmitt Trigger Pull-up/ Pull-down N-ch Open- Drain Drive Strength Selectable / Fixed PAPREDVDD — 1.8 PORT01(A), PORT03 pre-driver power supply PM8 IO 3.3/1.8 PORT01(B) I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-4) PM9 IO 3.3/1.8 PORT01(B) I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-4) PM10 IO 3.3/1.8 PORT01(B) I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-4) PM11 IO 3.3/1.8 PORT01(B) I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-4) PM12 IO 3.3/1.8 PORT01(B) I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-4) PM13 IO 3.3/1.8 PORT01(B) I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-4) PM14 IO 3.3/1.8 PORT01(B) I/O PD Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-4) PM15 IO 3.3/1.8 PORT01(B) I/O PD Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-4) PBMODVDD — 3.3/1.8 PORT01(B), PORT04, PORT07, PORT21 I/O power supply PBPREDVDD — 1.8 PORT01(B), PORT04, PORT07, PORT21 pre-driver power supply INEXINT0*1 IO 1.8 PORT02 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-5) INEXINT1*1 IO 1.8 PORT02 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-5) INEXINT2*1 IO 1.8 PORT02 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-5) INEXINT3*1, IO 1.8 PORT02 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-5) INEXINT4*1 IO 1.8 PORT02 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-5) INEXINT5*1 IO 1.8 PORT02 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-5)

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 14 of 79 Jul 24, 2024 Table 2.2-1 List of External Pins (4/16) Pin Name I/O Voltage (V) I/O Group Initial Value after Power- on Reset Pin State when not in Use Input Output Multiplexed Pin Schmitt Trigger Pull-up/ Pull-down N-ch Open- Drain Drive Strength Selectable / Fixed INEXINT6*1 IO 1.8 PORT02 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-5) INEXINT7*1 IO 1.8 PORT02 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-5) CSTXD0 IO 3.3/1.8 PORT03 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-6) CSRXD0 IO 3.3/1.8 PORT03 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-6) CSSCLK0 IO 3.3/1.8 PORT03 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-6) CSCS0 IO 3.3/1.8 PORT03 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-6) CSTXD1 IO 3.3/1.8 PORT03 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-6) CSRXD1 IO 3.3/1.8 PORT03 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-6) CSSCLK1 IO 3.3/1.8 PORT03 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-6) CSCS1 IO 3.3/1.8 PORT03 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-6) CSTXD2 IO 3.3/1.8 PORT03 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-6) CSRXD2 IO 3.3/1.8 PORT03 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-6) CSSCLK2 IO 3.3/1.8 PORT03 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-6) CSCS2 IO 3.3/1.8 PORT03 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-6) CSTXD3 IO 3.3/1.8 PORT03 I/O PD Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-6) CSRXD3 IO 3.3/1.8 PORT03 I/O PD Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-6) CSSCLK3 IO 3.3/1.8 PORT03 I/O PD Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-6)

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 15 of 79 Jul 24, 2024 Table 2.2-1 List of External Pins (5/16) Pin Name I/O Voltage (V) I/O Group Initial Value after Power- on Reset Pin State when not in Use Input Output Multiplexed Pin Schmitt Trigger Pull-up/ Pull-down N-ch Open- Drain Drive Strength Selectable / Fixed CSCS3 IO 3.3/1.8 PORT03 I/O PD Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-6) CSTXD4 IO 3.3/1.8 PORT04 I/O PD Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-7) CSRXD4 IO 3.3/1.8 PORT04 I/O PD Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-7) CSSCLK4 IO 3.3/1.8 PORT04 I/O PD Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-7) CSCS4 IO 3.3/1.8 PORT04 I/O PD Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-7) CSTXD5 IO 3.3/1.8 PORT04 I/O PD Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-7) CSRXD5 IO 3.3/1.8 PORT04 I/O PD Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-7) CSSCLK5 IO 3.3/1.8 PORT04 I/O PD Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-7) CSCS5 IO 3.3/1.8 PORT04 I/O PD Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-7) I2SDA0*1 IO 1.8 PORT05 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-8) I2SCL0*1 IO 1.8 PORT05 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-8) I2SDA1*1 IO 1.8 PORT05 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-8) I2SCL1*1 IO 1.8 PORT05 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-8) P0600 IO 3.3/1.8 PORT06 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-9) P0601 IO 3.3/1.8 PORT06 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-9) P0602 IO 3.3/1.8 PORT06 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-9) P0603 IO 3.3/1.8 PORT06 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-9)

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 16 of 79 Jul 24, 2024 Table 2.2-1 List of External Pins (6/16) Pin Name I/O Voltage (V) I/O Group Initial Value after Power- on Reset Pin State when not in Use Input Output Multiplexed Pin Schmitt Trigger Pull-up/ Pull-down N-ch Open- Drain Drive Strength Selectable / Fixed P0604 IO 3.3/1.8 PORT06 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-9) P0605 IO 3.3/1.8 PORT06 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-9) P0606 IO 3.3/1.8 PORT06 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-9) P0607 IO 3.3/1.8 PORT06 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-9) P0608 IO 3.3/1.8 PORT06 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-9) P0609 IO 3.3/1.8 PORT06 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-9) P0610 IO 3.3/1.8 PORT06 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-9) P0611 IO 3.3/1.8 PORT06 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-9) PCMODVDD — 3.3/1.8 PORT06 I/O power supply PCPREDVDD — 1.8 PORT06 pre-driver power supply P0700 IO 3.3/1.8 PORT07 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable* pin (see Table 2.2-2 and Table 2.2-10) P0701 IO 3.3/1.8 PORT07 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-10) P0702 IO 3.3/1.8 PORT07 I/O PD Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-10) P0703 IO 3.3/1.8 PORT07 I/O PD Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-10) P0704 IO 3.3/1.8 PORT07 I/O PD Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-10) P0705 IO 3.3/1.8 PORT07 I/O PD Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-10) SD0CMD IO 3.3/1.8 PORT08 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-11) SD0CLK IO 3.3/1.8 PORT08 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-11)

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 17 of 79 Jul 24, 2024 Table 2.2-1 List of External Pins (7/16) Pin Name I/O Voltage (V) I/O Group Initial Value after Power- on Reset Pin State when not in Use Input Output Multiplexed Pin Schmitt Trigger Pull-up/ Pull-down N-ch Open- Drain Drive Strength Selectable / Fixed SD0DAT0 IO 3.3/1.8 PORT08 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-11) SD0DAT1 IO 3.3/1.8 PORT08 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-11) SD0DAT2 IO 3.3/1.8 PORT08 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-11) SD0DAT3 IO 3.3/1.8 PORT08 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-11) SD0WP IO 3.3/1.8 PORT08 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-11) SD0CD IO 3.3/1.8 PORT08 I/O PU Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-11) SD0MODVDD — 3.3/1.8 PORT08 I/O power supply SD0PREDVDD — 1.8 PORT08 pre-driver power supply SD1FCMD IO 3.3/1.8 PORT09 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable* pin (see Table 2.2-2 and Table 2.2-12) SD1FCLK IO 3.3/1.8 PORT09 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-12) SD1FDAT0 IO 3.3/1.8 PORT09 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-12) SD1FDAT1 IO 3.3/1.8 PORT09 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-12) SD1FDAT2 IO 3.3/1.8 PORT09 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-12) SD1FDAT3 IO 3.3/1.8 PORT09 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-12) SD1FWP IO 3.3/1.8 PORT09 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-12) SD1FCD IO 3.3/1.8 PORT09 I/O PU Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-12) SD1FMODVDD — 3.3/1.8 PORT09 I/O power supply SD1FVDD — 1.8 PORT09 pre-driver power supply P1000 IO 3.3/1.8 PORT10 I/O PD Open — PU/PD/OFF changeable — Selectable* pin (see Table 2.2-2 and Table 2.2-13)

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 18 of 79 Jul 24, 2024 Table 2.2-1 List of External Pins (8/16) Pin Name I/O Voltage (V) I/O Group Initial Value after Power- on Reset Pin State when not in Use Input Output Multiplexed Pin Schmitt Trigger Pull-up/ Pull-down N-ch Open- Drain Drive Strength Selectable / Fixed P1001 IO 3.3/1.8 PORT10 I/O PD Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-13) P1002 IO 3.3/1.8 PORT10 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-13) P1003 IO 3.3/1.8 PORT10 I/O PD Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-13) P1004 IO 3.3/1.8 PORT10 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-13) P1005 IO 3.3/1.8 PORT10 I/O PD Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-13) P1006 IO 3.3/1.8 PORT10 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-13) P1007 IO 3.3/1.8 PORT10 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-13) P1008 IO 3.3/1.8 PORT10 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-13) U10MODVDD — 3.3/1.8 PORT10 I/O power supply U10VDD18 — 1.8 PORT10 pre-driver power supply P1100 IO 3.3/1.8 PORT11 I/O PD Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-14) P1101 IO 3.3/1.8 PORT11 I/O PD Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-14) P1102 IO 3.3/1.8 PORT11 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-14) P1103 IO 3.3/1.8 PORT11 I/O PD Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-14) P1104 IO 3.3/1.8 PORT11 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-14) P1105 IO 3.3/1.8 PORT11 I/O PD Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-14) P1106 IO 3.3/1.8 PORT11 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-14) P1107 IO 3.3/1.8 PORT11 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-14)

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 19 of 79 Jul 24, 2024 Table 2.2-1 List of External Pins (9/16) Pin Name I/O Voltage (V) I/O Group Initial Value after Power- on Reset Pin State when not in Use Input Output Multiplexed Pin Schmitt Trigger Pull-up/ Pull-down N-ch Open- Drain Drive Strength Selectable / Fixed P1108 IO 3.3/1.8 PORT11 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-14) U11MODVDD — 3.3/1.8 PORT11 I/O power supply U11VDD18 — 1.8 PORT11 pre-driver power supply P1200 IO 3.3 PORT12 I/O PD Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-15) P1201 IO 3.3 PORT12 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-15) P1202 IO 3.3 PORT12 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-15) P1203 IO 3.3 PORT12 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-15) P1300 IO 3.3 PORT13 I/O PD Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-16) P1301 IO 3.3 PORT13 I/O PD Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-16) P1302 IO 3.3 PORT13 I/O PD Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-16) P1303 IO 3.3 PORT13 I/O PD Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-16) P1304 IO 3.3 PORT13 I/O PD Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-16) P1305 IO 3.3 PORT13 I/O PD Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-16) P1306 IO 3.3 PORT13 I/O PD Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-16) P1307 IO 3.3 PORT13 I/O PD Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-16) P1308 IO 3.3 PORT13 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-16) P1309 IO 3.3 PORT13 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-16) P1310 IO 3.3 PORT13 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-16)

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 20 of 79 Jul 24, 2024 Table 2.2-1 List of External Pins (10/16) Pin Name I/O Voltage (V) I/O Group Initial Value after Power- on Reset Pin State when not in Use Input Output Multiplexed Pin Schmitt Trigger Pull-up/ Pull-down N-ch Open- Drain Drive Strength Selectable / Fixed P1311 IO 3.3 PORT13 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-16) P1400 IO 3.3 PORT14 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-17) P1401 IO 3.3 PORT14 I/O PD Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-17) P1402 IO 3.3 PORT14 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-17) P1403 IO 3.3 PORT14 I/O PD Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-17) P1404 IO 3.3 PORT14 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-17) P1405 IO 3.3 PORT14 I/O PD Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-17) P1406 IO 3.3 PORT14 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-17) P1407 IO 3.3 PORT14 I/O PD Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-17) GETXC IO 3.3/1.8 PORT15 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-18) GETXEN IO 3.3/1.8 PORT15 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-18) GETXER IO 3.3/1.8 PORT15 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-18) GETXD0 IO 3.3/1.8 PORT15 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-18) GETXD1 IO 3.3/1.8 PORT15 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-18) GETXD2 IO 3.3/1.8 PORT15 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-18) GETXD3 IO 3.3/1.8 PORT15 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-18) GETXD4 IO 3.3/1.8 PORT15 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-18)

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 21 of 79 Jul 24, 2024 Table 2.2-1 List of External Pins (11/16) Pin Name I/O Voltage (V) I/O Group Initial Value after Power- on Reset Pin State when not in Use Input Output Multiplexed Pin Schmitt Trigger Pull-up/ Pull-down N-ch Open- Drain Drive Strength Selectable / Fixed GETXD5 IO 3.3/1.8 PORT15 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-18) GETXD6 IO 3.3/1.8 PORT15 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-18) GETXD7 IO 3.3/1.8 PORT15 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-18) GERXC IO 3.3/1.8 PORT15 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-18) GERXDV IO 3.3/1.8 PORT15 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-18) GERXER IO 3.3/1.8 PORT15 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-18) GERXD0 IO 3.3/1.8 PORT15 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-18) GERXD1 IO 3.3/1.8 PORT15 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-18) GERXD2 IO 3.3/1.8 PORT16 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-19) GERXD3 IO 3.3/1.8 PORT16 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-19) GERXD4 IO 3.3/1.8 PORT16 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-19) GERXD5 IO 3.3/1.8 PORT16 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-19) GERXD6 IO 3.3/1.8 PORT16 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-19) GERXD7 IO 3.3/1.8 PORT16 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-19) GECRS IO 3.3/1.8 PORT16 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-19) GECOL IO 3.3/1.8 PORT16 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-19) GEMDC IO 3.3/1.8 PORT16 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-19)

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 22 of 79 Jul 24, 2024 Table 2.2-1 List of External Pins (12/16) Pin Name I/O Voltage (V) I/O Group Initial Value after Power- on Reset Pin State when not in Use Input Output Multiplexed Pin Schmitt Trigger Pull-up/ Pull-down N-ch Open- Drain Drive Strength Selectable / Fixed GEMDIO IO 3.3/1.8 PORT16 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-19) GEGTXCLK IO 3.3/1.8 PORT16 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-19) GELINK IO 3.3/1.8 PORT16 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-19) GEINT IO 3.3/1.8 PORT16 I/O Hi-Z Open  PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-19) GECLK IO 3.3/1.8 PORT16 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-19) P1700 IO 3.3/1.8 PORT17 I/O Hi-Z Open — PU/PD/OFF changeable — Selectable*2 Multiplexed pin (see T able 2.2-2 and Table 2.2-20) GEMODVDD — 3.3/1.8 PORT15, PORT16, PORT17 I/O power supply GEPREDVDD — 1.8 PORT15, PORT16, PORT17 pre-driver power supply DETCK I 1.8 Debugger I/O PD Open — PD — — — DETDI I 1.8 Debugger I/O PU Open — PU — — — DETDO O 1.8 Debugger I/O Hi-Z Open — — — Selectable*2 — DETMS IO 1.8 Debugger I/O PU Open — PU — Selectable*2 — DETRSTN I 1.8 Debugger I/O PU Open — PU — — — DESRSTN I 1.8 Debugger I/O PU Open — PU — — — RETEST0 I 3.3 LSI test I/O PD Pull down  PD — — — RETEST1 I 3.3 LSI test I/O PD Pull down  PD — — — LPATEST O 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPCAA0 O 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPCAA1 O 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPCAA2 O 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPCAA3 O 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPCAA4 O 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPCAA5 O 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPCAB0 O 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPCAB1 O 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPCAB2 O 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPCAB3 O 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPCAB4 O 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPCAB5 O 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPCKEA0 O 1.1 LPDDR4 PHY L Open — — — — — LPCKEA1 O 1.1 LPDDR4 PHY L Open — — — — — LPCKEB0 O 1.1 LPDDR4 PHY L Open — — — — — LPCKEB1 O 1.1 LPDDR4 PHY L Open — — — — — LPCLKAC O 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPCLKAT O 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPCLKBC O 1.1 LPDDR4 PHY Hi-Z Open — — — — —

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 23 of 79 Jul 24, 2024 Table 2.2-1 List of External Pins (13/16) Pin Name I/O Voltage (V) I/O Group Initial Value after Power- on Reset Pin State when not in Use Input Output Multiplexed Pin Schmitt Trigger Pull-up/ Pull-down N-ch Open- Drain Drive Strength Selectable / Fixed LPCLKBT O 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPCSA0 O 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPCSA1 O 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPCSB0 O 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPCSB1 O 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDMDBIA0 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDMDBIA1 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDMDBIB0 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDMDBIB1 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQA0 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQA1 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQA2 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQA3 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQA4 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQA5 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQA6 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQA7 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQA8 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQA9 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQA10 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQA11 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQA12 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQA13 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQA14 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQA15 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQB0 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQB1 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQB2 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQB3 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQB4 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQB5 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQB6 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQB7 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQB8 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQB9 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQB10 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQB11 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQB12 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQB13 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQB14 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQB15 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQSAC0 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQSAC1 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQSAT0 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQSAT1 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQSBC0 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQSBC1 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQSBT0 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPDQSBT1 IO 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPMRESETL O 1.1 LPDDR4 PHY L Open — — — — —

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 24 of 79 Jul 24, 2024 Table 2.2-1 List of External Pins (14/16) Pin Name I/O Voltage (V) I/O Group Initial Value after Power- on Reset Pin State when not in Use Input Output Multiplexed Pin Schmitt Trigger Pull-up/ Pull-down N-ch Open- Drain Drive Strength Selectable / Fixed LPZN O 1.1 LPDDR4 PHY Hi-Z Open — — — — — LPVAA — 1.8 LPDDR4 PLL 1.8-V power supply LPVDD — 0.8 LPDDR4 core 0.8-V power supply LPVDDQ — 1.1 LPDDR4 PHY 1.1-V power supply LPDTEST O 1.1 LPDDR4 PHY Hi-Z Open — — — — — U2VDD18 — 1.8 1.8-V power supply — — — — — — — U2VDD08 — 0.8 0.8-V power supply — — — — — — — U3VDD18 — 1.8 1.8-V power supply — — — — — — — U3REF — 1.2 1.2-V reference — — — — — — — U3VDD08 — 0.8 0.8-V power supply — — — — — — — PCRXD0P I 1.8 PCIe PHY — Open — — — — — PCRXD0M I 1.8 PCIe PHY — Open — — — — — PCTXD0P O 1.8 PCIe PHY X Open — — — — — PCTXD0M O 1.8 PCIe PHY X Open — — — — — PCREFCKP I 1.8 PCIe PHY CLOCK Open — — — — — PCREFCKM I 1.8 PCIe PHY CLOCK Open — — — — — PCREXT I 1.8 PCIe PHY — Open — — — — — PCRXD1P I 1.8 PCIe PHY — Open — — — — — PCRXD1M I 1.8 PCIe PHY — Open — — — — — PCTXD1P O 1.8 PCIe PHY X Open — — — — — PCTXD1M O 1.8 PCIe PHY X Open — — — — — PCVDD08 — 0.8 PCIe PHY 0.8-V power supply PCVDD18 — 1.8 PCIe PHY 1.8-V power supply PCRSTOUTB O 3.3 PCIe I/O H Open — — — Selectable*2 — USDP IO 3.3 USB PHY L Open — - — — — USDM IO 3.3 USB PHY L Open — - — — — USRESREF I 0.25 USB RESREF — Open — — — — — USVD330 — 3.3 USB PHY HS section 3.3-V power supply USVDDH — 1.8 USB PHY HS section 1.8-V power supply USDVDD*3 — 0.8 USB PHY HS section 0.8-V power supply USVBUS I 3.3*4 USB PHY Hi-Z Open — — — — — USRX0M I 0.8 USB PHY — Open — — — — — USRX0P I 0.8 USB PHY — Open — — — — — USTX0M O 0.8 USB PHY — Open — — — — — USTX0P O 0.8 USB PHY — Open — — — — — USOTGID I 1.8 USB PHY — Open — — — — — USVP — 0.8 USB PHY SS section 0.8-V power supply USVPH — 3.3 USB PHY SS section 3.3-V power supply USVPTX — 0.8 USB PHY SS section transmitter power supply USPWEN O 3.3 USB I/O L Open — — — Selectable*2 — USOVC I 3.3 USB I/O Hi-Z Pull up — — — — — U4VDD18 — 1.8 1.8-V power supply — — — — — — —

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 25 of 79 Jul 24, 2024 Table 2.2-1 List of External Pins (15/16) Pin Name I/O Voltage (V) I/O Group Initial Value after Power- on Reset Pin State when not in Use Input Output Multiplexed Pin Schmitt Trigger Pull-up/ Pull-down N-ch Open- Drain Drive Strength Selectable / Fixed U4VDD08 — 0.8 0.8-V power supply — — — — — — — P2000 IO 1.8 PORT20 I/O Hi-Z Open  — — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-21) P2001 IO 1.8 PORT20 I/O Hi-Z Open  — — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-21) P2002 IO 1.8 PORT20 I/O Hi-Z Open  — — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-21) U5VDD18 — 1.8 1.8-V power supply — — — — — — — U6VDD18 — 1.8 1.8-V power supply — — — — — — — MD0 I 1.8 MD7-0 I/O Hi-Z Always in use MD1 I 1.8 MD7-0 I/O Hi-Z Always in use MD2 I 1.8 MD7-0 I/O Hi-Z Always in use MD3 I 1.8 MD7-0 I/O Hi-Z Always in use MD4 I 1.8 MD7-0 I/O Hi-Z Always in use MD5 I 1.8 MD7-0 I/O PD Always in use — PD — — — MD6 I 1.8 MD7-0 I/O PD Always in use — PD — — — MD7 I 1.8 MD7-0 I/O Hi-Z Always in use MD8*5 IO 3.3/1.8 PORT21 I/O Hi-Z Always in use — — — Selectable*2 Multiplexed pin (see Table 2.2-2 and Table 2.2-22) OTVDD18 — 1.8 1.8-V power supply for test OTVDD08 — 0.8 0.8-V power supply for test TS0AVDD18 — 1.8 TSU ch. 0 1.8-V power supply TS0DVDD08A — 0.8 TSU ch. 0 0.8-V power supply TS1AVDD18 — 1.8 TSU ch. 1 1.8-V power supply TS1DVDD08A — 0.8 TSU ch. 1 0.8-V power supply XIN I 1.8 1.8-V OSC CLOCK Always in use XOUT O 1.8 1.8-V OSC CLOCK Always in use RSTN I 1.8 RSTN I/O PU Always in use  PU — — — PLVDD1 — 1.8 PLL ch. 1 1.8-V power supply PLVDD2 — 1.8 PLL ch. 2 1.8-V power supply

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 26 of 79 Jul 24, 2024 Table 2.2-1 List of External Pins (16/16) Pin Name I/O Voltage (V) I/O Group Initial Value after Power- on Reset Pin State when not in Use Input Output Multiplexed Pin Schmitt Trigger Pull-up/ Pull-down N-ch Open- Drain Drive Strength Selectable / Fixed PLVDD3 — 1.8 PLL ch. 3 1.8-V power supply PLVDD4 — 1.8 PLL ch. 4 1.8-V power supply PLVDD6 — 1.8 PLL ch. 6 1.8-V power supply U7VDD18 — 1.8 1.8-V power supply — — — — — — — PLDVDD081 — 0.8 PLL ch. 1 0.8-V power supply PLDVDD082 — 0.8 PLL ch. 2 0.8-V power supply PLDVDD083 — 0.8 PLL ch. 3 0.8-V power supply PLDVDD084 — 0.8 PLL ch. 4 0.8-V power supply PLDVDD086 — 0.8 PLL ch. 6 0.8-V power supply U7VDD08 — 0.8 0.8-V power supply — — — — — — — VDD08 — 0.8 VDD08 0.8-V power supply VDD18 — 1.8 VDD18 group I/O power supply (PORT02 I/O, PORT05 I/O, PORT20 I/O. 1.8-V OSC, RSTN I/O, debugger I/O, MD0-7 I/O) VDD33 — 3.3 VDD33 group I/O power supply (PORT12 I/O, PORT13 I/O, PORT14 I/O, PCIe I/O, USB I/O, LSI test I/O) PREDVDD33 — 1.8 VDD33 group pre-driver power supply (PORT12 I/O, PORT13 I/O, PORT14 I/O, PCIe I/O, USB I/O, LSI test I/O) RFU0-25 O 1.8 Reserved*6 — Open — — — — — RETESTH0-6 I 1.8 LSI test I/O Don’t care Pull up — — — — — RETESTRL I 1.8 LSI test I/O Hi-Z Pull down (10kΩ) U2GND0-19, U3GND0-3, U5GND0-11, U6GND0-7 Note 1. For 3.3-V input tolerant Note 2. For the drive strength, see Section 3.4.2, Standard I/O Characteristics.

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 27 of 79 Jul 24, 2024 Note 3. Connect an external resistor (1.1kΩ). For details, refer to the RZ/V2MA High-Speed Interface PCB Design Guidelines. Note 4. See Section 2.3, Pin Functions of Functional Blocks for how to connect the USVBUS. Note 5. This pin is intended to be used for LED control during boot sequence. Therefore, do not use this pin for any other purpose. Note 6. Leave these pins open-circuit. <Usage Note> In this LSI, supply power to all power pins. It is necessary to supply power even if the power pin is an unused function and to connect the ground pin to the ground.

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 28 of 79 Jul 24, 2024

2.2.2 List of Multiplexed Functional Blocks

Table 2.2-2 List of Multiplexed Functional Blocks I/O Group Share Group 0 Share Group 1 Share Group 2 Share Group 3 Share Group 4 Share Group 5 Share Group 6 Share Group 7 PORT01 GPIO PWM Ex. interrupt CLK out — — — — PORT02 GPIO — Ex. interrupt — — — — — PORT03 GPIO CSI0 CSI1 CSI2 CSI3 UART0 UART1 IIC2 IIC3 CSI3 CSI0 CSI1 CSI2 TRACE — — — PORT04 GPIO CSI4 CSI5 CSI4 CSI5 — TRACE — — — PORT05 GPIO — IIC0 IIC1 PORT09 GPIO SDI1 Ex. interrupt — — — — — PORT10 GPIO — Ex. interrupt — — — — — PORT11 GPIO — Ex. interrupt — — — — — PORT12 GPIO — Ex. interrupt — — — — — PORT13 GPIO — Ex. interrupt — — — — — PORT14 GPIO — Ex. interrupt — — — — — PORT15 GPIO ETHER — — TRACE — — — PORT16 GPIO ETHER — — TRACE — — —

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 29 of 79 Jul 24, 2024 Table 2.2-3 I/O Group PORT00 in the Multiplexed Mode External Pin Name Share Pin Name 0 Share Pin Name 1 Share Pin Name 2 Share Pin Name 3 Share Pin Name 4 Share Pin Name 5 Share Pin Name 6 Share Pin Name 7 Table 2.2-4 I/O Group PORT01 in the Multiplexed Mode External Pin Name Share Pin Name 0 Share Pin Name 1 Share Pin Name 2 Share Pin Name 3 Share Pin Name 4 Share Pin Name 5 Share Pin Name 6 Share Pin Name 7 GPIO PWM Ex. interrupt CLK out — — — — PM0 P01_00 PM0 INEXINT8 — — — — — PM1 P01_01 PM1 INEXINT9 — — — — — PM2 P01_02 PM2 INEXINT10 — — — — — PM3 P01_03 PM3 INEXINT11 — — — — — PM4 P01_04 PM4 INEXINT12 — — — — — PM5 P01_05 PM5 INEXINT13 — — — — — PM6 P01_06 PM6 INEXINT14 GMCLK0 — — — — PM7 P01_07 PM7 INEXINT15 GMCLK1 — — — — PM8 P01_08 PM8 INEXINT16 — — — — — PM9 P01_09 PM9 INEXINT17 — — — — — PM10 P01_10 PM10 INEXINT18 — — — — — PM11 P01_11 PM11 INEXINT19 — — — — — PM12 P01_12 PM12 INEXINT20 — — — — — PM13 P01_13 PM13 INEXINT21 — — — — — PM14 P01_14 PM14 INEXINT22 GMCLK0 — — — — PM15 P01_15 PM15 INEXINT23 GMCLK1 — — — —

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 30 of 79 Jul 24, 2024 Table 2.2-5 I/O Group PORT02 in the Multiplexed Mode External Pin Name Share Pin Name 0 Share Pin Name 1 Share Pin Name 2 Share Pin Name 3 Share Pin Name 4 Share Pin Name 5 Share Pin Name 6 Share Pin Name 7 GPIO — Ex. interrupt — — — — — INEXINT0 P02_00 — INEXINT0 — — — — — INEXINT1 P02_01 — INEXINT1 — — — — — INEXINT2 P02_02 — INEXINT2 — — — — — INEXINT3 P02_03 — INEXINT3 — — — — — INEXINT4 P02_04 — INEXINT4 — — — — — INEXINT5 P02_05 — INEXINT5 — — — — — INEXINT6 P02_06 — INEXINT6 — — — — — INEXINT7 P02_07 — INEXINT7 — — — — — Table 2.2-6 I/O Group PORT03 in the Multiplexed Mode External Pin Name Share Pin Name 0 Share Pin Name 1 Share Pin Name 2 Share Pin Name 3 Share Pin Name 4 Share Pin Name 5 Share Pin Name 6 Share Pin Name 7 GPIO CSI0, CSI1, CSI2, CSI3 UART0, UART1, IIC2, IIC3, CSI3 CSI0, CSI1, CSI2 TRACE — — — CSTXD0 P03_00 CSTXD0 UATX0 CSRXD0 — — — — CSRXD0 P03_01 CSRXD0 UARX0 — — — — — CSSCLK0 P03_02 CSSCLK0 UACTS0N — — — — — CSCS0 P03_03 CSCS0 UARTS0N — — — — — CSTXD1 P03_04 CSTXD1 UATX1 CSRXD1 — — — — CSRXD1 P03_05 CSRXD1 UARX1 — — — — — CSSCLK1 P03_06 CSSCLK1 UACTS1N — TRDAT15 — — — CSCS1 P03_07 CSCS1 UARTS1N — TRDAT14 — — — CSTXD2 P03_08 CSTXD2 I2SDA2 CSRXD2 TRDAT13 — — — CSRXD2 P03_09 CSRXD2 I2SCL2 — TRDAT12 — — — CSSCLK2 P03_10 CSSCLK2 I2SDA3 — TRDAT11 — — — CSCS2 P03_11 CSCS2 I2SCL3 — TRDAT10 — — — CSTXD3 P03_12 CSTXD3 CSRXD3 — TRDAT9 — — — CSRXD3 P03_13 CSRXD3 — — TRDAT8 — — — CSSCLK3 P03_14 CSSCLK3 — — TRDAT7 — — — CSCS3 P03_15 CSCS3 — — TRDAT6 — — —

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 31 of 79 Jul 24, 2024 Table 2.2-7 I/O Group PORT04 in the Multiplexed Mode External Pin Name Share Pin Name 0 Share Pin Name 1 Share Pin Name 2 Share Pin Name 3 Share Pin Name 4 Share Pin Name 5 Share Pin Name 6 Share Pin Name 7 GPIO CSI4, CSI5 CSI4, CSI5 — TRACE — — — CSTXD4 P04_00 CSTXD4 CSRXD4 — TRDAT5 — — — CSRXD4 P04_01 CSRXD4 — — TRDAT4 — — — CSSCLK4 P04_02 CSSCLK4 — — TRDAT3 — — — CSCS4 P04_03 CSCS4 — — TRDAT2 — — — CSTXD5 P04_04 CSTXD5 CSRXD5 — TRDAT1 — — — CSRXD5 P04_05 CSRXD5 — — TRDAT0 — — — CSSCLK5 P04_06 CSSCLK5 — — TRCLK — — — CSCS5 P04_07 CSCS5 — — TRCTL — — — Table 2.2-8 I/O Group PORT05 in the Multiplexed Mode External Pin Name Share Pin Name 0 Share Pin Name 1 Share Pin Name 2 Share Pin Name 3 Share Pin Name 4 Share Pin Name 5 Share Pin Name 6 Share Pin Name 7 Table 2.2-9 I/O Group PORT06 in the Multiplexed Mode External Pin Name Share Pin Name 0 Share Pin Name 1 Share Pin Name 2 Share Pin Name 3 Share Pin Name 4 Share Pin Name 5 Share Pin Name 6 Share Pin Name 7

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 32 of 79 Jul 24, 2024 Table 2.2-10 I/O Group PORT07 in the Multiplexed Mode External Pin Name Share Pin Name 0 Share Pin Name 1 Share Pin Name 2 Share Pin Name 3 Share Pin Name 4 Share Pin Name 5 Share Pin Name 6 Share Pin Name 7 Table 2.2-11 I/O Group PORT08 in the Multiplexed Mode External Pin Name Share Pin Name 0 Share Pin Name 1 Share Pin Name 2 Share Pin Name 3 Share Pin Name 4 Share Pin Name 5 Share Pin Name 6 Share Pin Name 7 Table 2.2-12 I/O Group PORT09 in the Multiplexed Mode External Pin Name Share Pin Name 0 Share Pin Name 1 Share Pin Name 2 Share Pin Name 3 Share Pin Name 4 Share Pin Name 5 Share Pin Name 6 Share Pin Name 7 GPIO SDI1 Ex. interrupt — — — — — SD1FDAT0 P09_02 SD1FDAT0 — — — — — — SD1FDAT1 P09_03 SD1FDAT1 — — — — — — SD1FDAT2 P09_04 SD1FDAT2 — — — — — — SD1FDAT3 P09_05 SD1FDAT3 — — — — — — SD1FWP P09_06 SD1FWP INEXINT24 — — — — — SD1FCD P09_07 SD1FCD INEXINT25 — — — — —

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 33 of 79 Jul 24, 2024 Table 2.2-13 I/O Group PORT10 in the Multiplexed Mode External Pin Name Share Pin Name 0 Share Pin Name 1 Share Pin Name 2 Share Pin Name 3 Share Pin Name 4 Share Pin Name 5 Share Pin Name 6 Share Pin Name 7 GPIO — Ex. interrupt — — — — — Table 2.2-14 I/O Group PORT11 in the Multiplexed Mode External Pin Name Share Pin Name 0 Share Pin Name 1 Share Pin Name 2 Share Pin Name 3 Share Pin Name 4 Share Pin Name 5 Share Pin Name 6 Share Pin Name 7 GPIO — Ex. interrupt — — — — — Table 2.2-15 I/O Group PORT12 in the Multiplexed Mode External Pin Name Share Pin Name 0 Share Pin Name 1 Share Pin Name 2 Share Pin Name 3 Share Pin Name 4 Share Pin Name 5 Share Pin Name 6 Share Pin Name 7 GPIO — Ex. interrupt — — — — —

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 34 of 79 Jul 24, 2024 Table 2.2-16 I/O Group PORT13 in the Multiplexed Mode External Pin Name Share Pin Name 0 Share Pin Name 1 Share Pin Name 2 Share Pin Name 3 Share Pin Name 4 Share Pin Name 5 Share Pin Name 6 Share Pin Name 7 GPIO — Ex. interrupt — — — — — Table 2.2-17 I/O Group PORT14 in the Multiplexed Mode External Pin Name Share Pin Name 0 Share Pin Name 1 Share Pin Name 2 Share Pin Name 3 Share Pin Name 4 Share Pin Name 5 Share Pin Name 6 Share Pin Name 7 GPIO — Ex. interrupt — — — — —

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 35 of 79 Jul 24, 2024 Table 2.2-18 I/O Group PORT15 in the Multiplexed Mode External Pin Name Share Pin Name 0 Share Pin Name 1 Share Pin Name 2 Share Pin Name 3 Share Pin Name 4 Share Pin Name 5 Share Pin Name 6 Share Pin Name 7 GPIO ETHER — — TRACE — — — GETXC P15_00 GETXC — — TRCLK — — — GETXEN P15_01 GETXEN — — TRCTL — — — GETXD5 P15_08 GETXD5 — — TRDAT0 — — — GETXD6 P15_09 GETXD6 — — TRDAT1 — — — GETXD7 P15_10 GETXD7 — — TRDAT2 — — — GERXC P15_11 GERXC — — TRDAT3 — — — GERXDV P15_12 GERXDV — — TRDAT4 — — — GERXER P15_13 GERXER — — TRDAT5 — — — GERXD0 P15_14 GERXD0 — — TRDAT6 — — — GERXD1 P15_15 GERXD1 — — TRDAT7 — — — Table 2.2-19 I/O Group PORT16 in the Multiplexed Mode External Pin Name Share Pin Name 0 Share Pin Name 1 Share Pin Name 2 Share Pin Name 3 Share Pin Name 4 Share Pin Name 5 Share Pin Name 6 Share Pin Name 7 GPIO ETHER — — TRACE — — — GERXD2 P16_00 GERXD2 — — TRDAT8 — — — GERXD3 P16_01 GERXD3 — — TRDAT9 — — — GERXD4 P16_02 GERXD4 — — TRDAT10 — — — GERXD5 P16_03 GERXD5 — — TRDAT11 — — — GERXD6 P16_04 GERXD6 — — TRDAT12 — — — GERXD7 P16_05 GERXD7 — — TRDAT13 — — — GECRS P16_06 GECRS — — TRDAT14 — — — GECOL P16_07 GECOL — — TRDAT15 — — — GEGTXCLK P16_10 GEGTXCLK — — — — — — Table 2.2-20 I/O Group PORT17 in the Multiplexed Mode External Pin Name Share Pin Name 0 Share Pin Name 1 Share Pin Name 2 Share Pin Name 3 Share Pin Name 4 Share Pin Name 5 Share Pin Name 6 Share Pin Name 7

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 36 of 79 Jul 24, 2024 Table 2.2-21 I/O Group PORT20 in the Multiplexed Mode External Pin Name Share Pin Name 0 Share Pin Name 1 Share Pin Name 2 Share Pin Name 3 Share Pin Name 4 Share Pin Name 5 Share Pin Name 6 Share Pin Name 7 Table 2.2-22 I/O Group PORT21 in the Multiplexed Mode External Pin Name Share Pin Name 0 Share Pin Name 1 Share Pin Name 2 Share Pin Name 3 Share Pin Name 4 Share Pin Name 5 Share Pin Name 6 Share Pin Name 7

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 37 of 79 Jul 24, 2024

2.3 Pin Functions of Functional Blocks

Table 2.3-1 List of Pin Functions (1/5) Classification Pin Name I/O Function Power control (PWC) RTXIN I To connect a 32.768-kHz crystal resonator RTXOUT O To connect a 32.768-kHz crystal resonator RTRSTN I PWC reset input (active low) RTISO I PWC isolation input pin PWRSTN I PWC reset input (active low) PWTEST I LSI test pin, fixed to the low level PWEN5 to PWEN0 O Power enable 5 to 0 (active high) PWSYSRSTN O System reset output. Connected to the RSTN pin to use the power control function of PWC. PWSD0SEL O PWC SDI0 interface power supply selection PWSD1SEL O PWC SDI1 interface power supply selection PWCTEST0 O LSI test pin: leave this pin open-circuit. PWCTEST1 I LSI test pin: fixed to the high level. (pulled up by the PWVDD) PWMEMSWIENA O Enable signal output pin for controlling the LPVDD power supply on/off PWISO O Open drain output. Connected to the RTISO pin and pulled up (with 10kΩ to 100kΩ) to a 1.5-V power supply.*1 eMMC interface (eMMC) MMDAT7 to MMDAT0 I/O eMMC data [7:0] MMCMD I/O eMMC command MMCLK O eMMC clock Pulse-width modulation timer (PWM) PM15 to PM0 O PWM output External interrupt INEXINT38 to INEXINT0 I External interrupt CSI ch. 0 (CSI0) CSTXD0 O CSI0 serial data output CSRXD0 I CSI0 serial data input CSSCLK0 I/O CSI0 serial clock CSCS0 I CSI0 serial chip select CSI ch. 1 (CSI1) CSTXD1 O CSI1 serial data output CSRXD1 I CSI1 serial data input CSSCLK1 I/O CSI1 serial clock CSCS1 I CSI1 serial chip select CSI ch. 2 (CSI2) CSTXD2 O CSI2 serial data output CSRXD2 I CSI2 serial data input CSSCLK2 I/O CSI2 serial clock CSCS2 I CSI2 serial chip select CSI ch. 3 (CSI3) CSTXD3 O CSI3 serial data output CSRXD3 I CSI3 serial data input CSSCLK3 I/O CSI3 serial clock CSCS3 I CSI3 serial chip select CSI ch. 4 (CSI4) CSTXD4 O CSI4 serial data output CSRXD4 I CSI4 serial data input CSSCLK4 I/O CSI4 serial clock CSCS4 I CSI4 serial chip select

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 38 of 79 Jul 24, 2024 Table 2.3-1 List of Pin Functions (2/5) Classification Pin Name I/O Function CSI ch. 5 (CSI5) CSTXD5 O CSI5 serial data output CSRXD5 I CSI5 serial data input CSSCLK5 I/O CSI5 serial clock CSCS5 I CSI5 serial chip select IIC ch. 0 (IIC0) I2SDA0 I/O IIC0 serial data I2SCL0 I/O IIC0 serial clock IIC ch. 1 (IIC1) I2SDA1 I/O IIC1 serial data I2SCL1 I/O IIC1 serial clock IIC ch. 2 (IIC2) I2SDA2 I/O IIC2 serial data I2SCL2 I/O IIC2 serial clock IIC ch. 3 (IIC3) I2SDA3 I/O IIC3 serial data I2SCL3 I/O IIC3 serial clock UART ch. 0 (UART0) UATX0 O UART0 transmission data UARX0 I UART0 reception data UACTS0N I UART0 transmission enable signal (active low) UARTS0N O UART0 reception enable signal (active low) UART ch. 1 (UART1) UATX1 O UART1 transmission data UARX1 I UART1 reception data UACTS1N I UART1 transmission enable signal (active low) UARTS1N O UART1 reception enable signal (active low) SD host interface ch. 0 (SDI0) SD0CMD I/O SDI0 command/response signal SD0CLK O SDI0 clock SD0DAT3 to SD0DAT0 I/O SDI0 data line bits [3:0] SD0WP I SDI0 write protect signal SD0CD I SDI0 card detection signal SD host interface ch. 1 (SDI1) SD1FCMD I/O SDI1 command/response signal SD1FCLK O SDI1 clock SD1FDAT3 to SD1FDAT0 I/O SDI1 data line bits [3:0] SD1FWP I SDI1 write protect signal SD1FCD I SDI1 card detection signal

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 39 of 79 Jul 24, 2024 Table 2.3-1 List of Pin Functions (3/5) Classification Pin Name I/O Function Gigabit Ethernet MAC interface (ETHER) GETXC I Transmission clock for Ethernet 100-Mbps mode GETXEN O Transmission enable signal (active high) GETXER O Transmission error signal (active high) GETXD7 to GETXD0 O Transmission data [7:0] GERXC I Ethernet reception clock GERXDV I Reception data valid signal (active high) GERXER I Reception error signal (active high) GERXD7 to GERXD0 I Receive data [7:0] GECRS I Carrier detection signal (active high) GECOL I Transmission collision signal (active high) GEMDC O PHY management clock GEMDIO I/O PHY management I/O data GEGTXCLK O GMII transmission clock GELINK I PHY LINK signal GEINT I PHY interrupt signal GECLK*2 I Clock input Debugger interface DETCK I JTAG TCK DETDI I JTAG TDI DETDO O JTAG TDO DETMS I/O JTAG TMS DETRSTN I JTAG TRST (active low) DESRSTN I System reset from debugger (active low) For LSI test RETEST0 I LSI test enable, fixed to the low level RETEST1 I LSI test enable, fixed to the low level RETESTH6 to RETESTH0 I LSI test enable, fixed to the high level (pulled up by PWVDD) RETESTRL I External reference resistor connection pin for LSI test * Resistance: 10kΩ±1% 1.2-V reference U3REF I Reference pin. Supplied with 1.2 V by the resistance voltage divider of VDD33. Connected with a capacitor to prevent noise.*3 RFU RFU25 to RFU0 O Reserved. Leave these pins open-circuit.

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 40 of 79 Jul 24, 2024 Table 2.3-1 List of Pin Functions (4/5) Classification Pin Name I/O Function LPDDR4 interface LPATEST O LSI test pin, leave this pin open-circuit. LPCAA5 to LPCAA0 O DRAM address and command bits: Ch-A command/address input LPCAB5 to LPCAB0 O DRAM address and command bits: Ch-B command/address input LPCKEA1, LPCKEA0 O DRAM address and command bits: Ch-A clock enable LPCKEB1, LPCKEB0 O DRAM address and command bits: Ch-B clock enable LPCLKAC O DRAM address and command bits: Ch-A clock (negative) LPCLKAT O DRAM address and command bits: Ch-A clock (positive) LPCLKBC O DRAM address and command bits: Ch-B clock (negative) LPCLKBT O DRAM address and command bits: Ch-B clock (positive) LPCSA1, LPCSA0 O DRAM address and command bits: Ch-A chip select LPCSB1, LPCSB0 O DRAM address and command bits: Ch-B chip select LPDMDBIA1, LPDMDBIA0 I/O DRAM data bits and strobes: Ch-A data mask inversion LPDMDBIB1, LPDMDBIB0 I/O DRAM data bits and strobes: Ch-B data mask inversion LPDQA15 to LPDQA0 I/O DRAM data bits and strobes: Ch-A data input/output LPDQB15 to LPDQB0 I/O DRAM data bits and strobes: Ch-B data input/output LPDQSAC1, LPDQSAC0 I/O DRAM data bits and strobes: Ch-A data strobe (negative) LPDQSAT1, LPDQSAT0 I/O DRAM data bits and strobes: Ch-A data strobe (positive) LPDQSBC1, LPDQSBC0 I/O DRAM data bits and strobes: Ch-B data strobe (negative) LPDQSBT1, LPDQSBT0 I/O DRAM data bits and strobes: Ch-B data strobe (positive) LPMRESETL O DRAM reset. Note that this requires no external resistor. LPZN O External reference resistor connection pin for use in calibration. * To connect a pull-down resistor. Resistance: 240Ω±1% LPDTEST O LSI test pin, leave this pin open-circuit. PCI Express interface PCRXD1P, PCRXD0P I Rx serial data inputs 1, 0 (positive) PCRXD1M, PCRXD0M I Rx serial data inputs 1, 0 (negative) PCTXD1P, PCTXD0P O Tx serial data outputs 1, 0 (positive) PCTXD1M, PCTXD0M O Tx serial data outputs 1, 0 (negative) PCREFCKP I Differential reference clock (positive) PCREFCKM I Differential reference clock (negative) PCREXT I Reference resistor connection pin for band-gap reference (BGR) and bias generator * To connect a pull-down resistor. Resistance: 8.2kΩ ±1% PCRSTOUTB O Reset output (for other-party PCIe devices) (active low) USB interface USDP I/O USB2.0 USB D+ signal (positive) USDM I/O USB2.0 USB D− signal (negative) USRESREF I Reference resistor connection pin * To connect a pull-down resistor. Resistance: 200Ω ±1% USVBUS I USB VBUS signal detection pin*4 * Resistance partial pressure outside the chip USRX0M I USB3.1 super-speed differential reception pair (negative) USRX0P I USB3.1 super-speed differential reception pair (positive) USTX0M O USB3.1 super-speed differential transmission pair (negative) USTX0P O USB3.1 super-speed differential transmission pair (positive) USOTGID I ID detection (OTG ID input, 0: Host, 1: Peripheral) In the initial state, an internal pull-up resistor is enabled.*5 USPWEN O VBUS control signal (active high) USOVC I Overcurrent detection (active low)

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 41 of 79 Jul 24, 2024 Table 2.3-1 List of Pin Functions (5/5) Classification Pin Name I/O Function Boot MD2 to MD0 I Boot device select [2:0] MD3 I Boot device write interface select When not using security, fix the input level to low. When using security, prepare a circuit that is capable of switching the input level externally to low or high (pull up with VDD18). MD4, MD5 I Boot mode select [1:0] (reserved) Fix the pin to the low level. MD6 I Boot mode select [2] MD7 I Boot mode select [3] (reserved) Fix the pin to the low level. MD8 I/O Boot GPIO (LED control when booted)*6 Clock/reset XIN I To connect a 48-MHz crystal resonator XOUT O To connect a 48-MHz crystal resonator RSTN I System reset (active low) Clock output GMCLK0 O Clock output 0 GMCLK1 O Clock output 1 Trace interface (TRACE) TRDAT15 to TRDAT0 O Trace data [15:0] TRCLK O Trace clock TRCTL O Trace control General-purpose input/output ports (GPIO) P00_13 to P00_00 I/O GPIO port 00 [13:0] P01_15 to P01_00 I/O GPIO port 01 [15:0] P02_07 to P02_00 I/O GPIO port 02 [7:0] P03_15 to P03_00 I/O GPIO port 03 [15:0] P04_07 to P04_00 I/O GPIO port 04 [7:0] P05_03 to P05_00 I/O GPIO port 05 [3:0] P06_11 to P06_00 I/O GPIO port 06 [11:0] P07_05 to P07_00 I/O GPIO port 07[5:0] P08_07 to P08_00 I/O GPIO port 08[7:0] P09_07 to P09_00 I/O GPIO port 09[7:0] P10_08 to P10_00 I/O GPIO port 10[8:0] P11_08 to P11_00 I/O GPIO port 11[8:0] P12_03 to P12_00 I/O GPIO port 12[3:0] P13_11 to P13_00 I/O GPIO port 13[11:0] P14_07 to P14_00 I/O GPIO port 14[7:0] P15_15 to P15_00 I/O GPIO port 15[15:0] P16_13 to P16_00 I/O GPIO port 16[13:0] P17_00 I/O GPIO port 17[0] P20_02 to P20_00 I/O GPIO port 20[2:0] P21_00 I/O GPIO port 21[0]*6

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 42 of 79 Jul 24, 2024 Note 1. The PWISO and RTISO pins are connected to this LSI, and these nodes should be pulled up with a 10kΩ to 100kΩ resistor. The schematic diagram is shown below. This LSI PWISO 10kΩ to 100kΩ RTISO Low level (fixed) RTVDD (PWC clock power supply) Note 2. GECLK is the input clock for GEGTXCLK. Note 3. U3REF is supplied with 1.2 V by the resistance voltage divider of VDD33. The schematic diagram is shown below. This LSI VDD33 U3REF 82kΩ (1%) 3.3V GND GND 47kΩ (1%) 0.1 µF

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 2 Pins R01DS0459EJ0100 Rev.1.00 Page 43 of 79 Jul 24, 2024 Note 4. Since this LSI has a resistor mounted between the USVBUS pin and GND, connect the pin to the USVBUS pin via a 30- kΩ (±1%) resistor. The schematic diagram is shown below. In addition, design so that the voltage is applied to the USVBUS pin after supplying USDVDD, USVP and USVPTX. This LSI USVBUS GND 30kΩ (±1%) 1 µF USB VBUS GND Note 5. USOTGID has the internal pull-up resistor. This LSI USVDDH USOTGID 13kΩ (typ) 1.8V USOTGID Note 6. This pin is intended to be used for LED control during boot sequence. Therefore, do not use this pin for any other purpose.

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 3 Electrical Characteristics R01DS0459EJ0100 Rev.1.00 Page 44 of 79 Jul 24, 2024 Section 3 Electrical Characteristics

3.1 Absolute Maximum Ratings

Permanent damage to the LSI may result if absolute maximum ratings are exceeded. Table 3.1-1 Absolute Maximum Ratings (1/3) Item Symbol Min. Max. Unit VDD08 core power supply VDD08 −0.4 1.2 V XTAL power supply RTVDD08 −0.4 1.2 V PWC clock power supply RTVDD −0.4 2.5 V PWC core power supply PWVDD08 −0.4 1.2 V PWC I/O power supply PWVDD −0.4 2.5 V PORT01(A), PORT03 pre-driver power supply PAPREDVDD −0.4 2.5 V PORT01(A), PORT03 I/O power supply PAMODVDD −0.4 3.8 V PORT01(B), PORT04, PORT07, PORT21 pre-driver power supply PBPREDVDD −0.4 2.5 V PORT01(B), PORT04, PORT07, PORT21 I/O power supply PBMODVDD −0.4 3.8 V PORT06 pre-driver power supply PCPREDVDD −0.4 2.5 V PORT06 I/O power supply PCMODVDD −0.4 3.8 V PORT10 pre-driver power supply U10VDD18 −0.4 2.5 V PORT10 I/O power supply U10MODVDD −0.4 3.8 V PORT11 pre-driver power supply U11VDD18 −0.4 2.5 V PORT11 I/O power supply U11MODVDD −0.4 3.8 V PORT00 pre-driver power supply MMPREDVDD −0.4 2.5 V PORT00 I/O power supply MMMODVDD −0.4 3.8 V PORT08 pre-driver power supply SD0PREDVDD −0.4 2.5 V PORT08 I/O power supply SD0MODVDD −0.4 3.8 V PORT09 pre-driver power supply SD1FVDD −0.4 2.5 V PORT09 I/O power supply SD1FMODVDD −0.4 3.8 V PORT15, PORT16, PORT17 pre-driver power supply GEPREDVDD −0.4 2.5 V PORT15, PORT16, PORT17 I/O power supply GEMODVDD −0.4 3.8 V

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 3 Electrical Characteristics R01DS0459EJ0100 Rev.1.00 Page 45 of 79 Jul 24, 2024 Table 3.1-1 Absolute Maximum Ratings (2/3) Item Symbol Min. Max. Unit VDD18 group I/O power supply (PORT02 I/O, PORT05 I/O, PORT20 I/O. 1.8-V OSC, RSTN I/O, debugger I/O, MD0-7 I/O) VDD18 −0.4 2.5 V VDD33 group pre-driver power supply (PORT12 I/O, PORT13 I/O, PORT14 I/O, PCIe I/O, USB I/O, LSI test I/O) PREDVDD33 −0.4 2.5 V VDD33 group I/O power supply (PORT12 I/O, PORT13 I/O, PORT14 I/O, PCIe I/O, USB I/O, LSI test I/O) VDD33 −0.4 3.8 V PLL ch. 1, 2, 3, 4, 6 0.8-V power supply PLDVDD08n −0.4 1.2 V PLL ch. 1, 2, 3, 4, 6 1.8-V power supply PLVDDn −0.4 2.5 V 0.8-V power supply for test OTVDD08 −0.4 1.2 V 1.8-V power supply for test OTVDD18 −0.4 2.5 V TSU ch. 0 0.8-V power supply TS0DVDD08A −0.4 1.2 V TSU ch. 1 0.8-V power supply TS1DVDD08A −0.4 1.2 V TSU ch. 0 1.8-V power supply TS0AVDD18 −0.4 2.5 V TSU ch. 1 1.8-V power supply TS1AVDD18 −0.4 2.5 V Sub-unit 0.8-V power supply UnVDD08 (n = 2, 3, 4, 7) −0.4 1.2 V Sub-unit 1.8-V power supply UnVDD18 −0.4 2.5 V LPDDR4 core 0.8-V power supply LPVDD −0.4 1.2 V LPDDR4 PLL 1.8-V power supply LPVAA −0.4 2.5 V LPDDR4 I/O 1.1-V power supply LPVDDQ −0.4 1.5 V PCIe PHY 0.8-V power supply PCVDD08 −0.4 1.2 V PCIe PHY 1.8-V power supply PCVDD18 −0.4 2.5 V USB PHY HS section 3.3-V power supply USVD330 −0.4 3.8 V USB PHY HS section 1.8-V power supply USVDDH −0.4 2.5 V USB PHY HS section 0.8-V power supply USDVDD −0.4 1.2 V USB PHY SS section 0.8-V power supply USVP −0.4 1.2 V USB PHY SS section 3.3-V power supply USVPH −0.4 3.8 V USB3.0 transmitter power supply USVPTX −0.4 1.2 V Input voltage (1.1-V I/O) Vin11 −0.4 LPVDDQ+0.3*3 V Input voltage (1.5-V I/O) Vin15 −0.4 RTVDD + 0.3*4 V Input voltage (1.8-V I/O)*1 Vin18 −0.4 V18 + 0.3*5 V

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 3 Electrical Characteristics R01DS0459EJ0100 Rev.1.00 Page 46 of 79 Jul 24, 2024 Table 3.1-1 Absolute Maximum Ratings (3/3) Item Symbol Min. Max. Unit Input voltage (1.8-V I/O (3.3-V tolerant))*2 Vin18_tol −0.4 3.6 V Input voltage (3.3-V I/O) Vin33 −0.4 V33 + 0.3*6 V Junction temperature Tj −40 125 °C Storage temperature Tstg −40 150 °C Note 1. 1.8-V I/O (except for PORT02 I/O and PORT05 I/O) Note 2. 1.8-V I/O (PORT02 I/O and PORT05 I/O) Note 3. The voltage to be applied must be within the absolute maximum rating (1.5 V). Note 4. The voltage to be applied must be within the absolute maximum rating (2.5 V). Note 5. The voltage to be applied must be within the absolute maximum rating (2.5 V). V18 indicates the power supply voltage for 1.8-V I/O pins. Note 6. The voltage to be applied must be within the absolute maximum rating (3.8 V). V33 indicates the power supply voltage for 3.3-V I/O pins.

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 3 Electrical Characteristics R01DS0459EJ0100 Rev.1.00 Page 47 of 79 Jul 24, 2024

3.2 Recommended Operating Range

Table 3.2-1 Recommended Operating Range (1/2) Item Symbol Min. Typ. Max. Unit Note VDD08 core power supply VDD08 0.76 0.8 0.84 V XTAL power supply RTVDD08 0.76 0.8 0.84 V PWC clock power supply RTVDD 1.425 1.5 1.575 V PWC core power supply PWVDD08 0.76 0.8 0.84 V PWC I/O power supply PWVDD 1.71 1.8 1.89 V PORT01(A), PORT03 pre-driver power supply PAPREDVDD 1.71 1.8 1.89 V selectable PORT01(B), PORT04, PORT07, PORT21 pre-driver power supply PBPREDVDD 1.71 1.8 1.89 V PORT01(B), PORT04, PORT07, PORT21 I/O power supply PBMODV selectable PORT06 pre-driver power supply PCPREDVDD 1.71 1.8 1.89 V selectable PORT10 pre-driver power supply U10VDD18 1.71 1.8 1.89 V selectable PORT11 pre-driver power supply U11VDD18 1.71 1.8 1.89 V selectable PORT00 pre-driver power supply MMPREDVDD 1.71 1.8 1.89 V selectable PORT08 pre-driver power supply SD0PREDVDD 1.71 1.8 1.89 V selectable PORT09 pre-driver power supply SD1FVDD 1.71 1.8 1.89 V selectable PORT15, PORT16, PORT17 pre-driver power supply GEPREDVDD 1.71 1.8 1.89 V selectable VDD18 group I/O power supply (PORT02 I/O, PORT05 I/O, PORT20 I/O. 1.8-V OSC, RSTN I/O, debugger I/O, MD0-7 I/O) VDD18 1.71 1.8 1.89 V VDD33 group pre-driver power supply (PORT12 I/O, PORT13 I/O, PORT14 I/O, PCIe I/O, USB I/O, LSI test I/O) PREDVDD33 1.71 1.8 1.89 V

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 3 Electrical Characteristics R01DS0459EJ0100 Rev.1.00 Page 48 of 79 Jul 24, 2024 Table 3.2-1 Recommended Operating Range (2/2) Item Symbol Min. Typ. Max. Unit Note VDD33 group I/O power supply (PORT12 I/O, PORT13 I/O, PORT14 I/O, PCIe I/O, USB I/O, LSI test I/O) VDD33 3.135 3.3 3.465 V PLL ch. 1, 2, 3, 4, 6 0.8-V power supply PLDVDD08n, 0.76 0.8 0.84 V PLL ch. 1, 2, 3, 4, 6 1.8-V power supply PLVDDn 1.71 1.8 1.89 V 0.8-V power supply for test OTVDD08 0.76 0.8 0.84 V 1.8-V power supply for test OTVDD18 1.71 1.8 1.89 V Sub-unit 0.8-V power supply UnVDD08 (n = 2, 3, 4, 7) 0.76 0.8 0.84 V Sub-unit 1.8-V power supply UnVDD18 1.71 1.8 1.89 V LPDDR4 core 0.8-V power supply LPVDD 0.76 0.8 0.84 V LPDDR4 PLL 1.8-V power supply LPVAA 1.71 1.8 1.89 V LPDDR4 PHY 1.1-V power supply LPVDDQ 1.06 1.1 1.17 V PCIe PHY 0.8-V power supply PCVDD08 0.76 0.8 0.84 V PCIe PHY 1.8-V power supply PCVDD18 1.71 1.8 1.89 V USB PHY SS section 0.8-V power supply USVP 0.76 0.8 0.84 V USB PHY HS section 1.8-V power supply USVDDH 1.71 1.8 1.89 V USB PHY HS section 3.3-V power supply USVD330 3.135 3.3 3.465 V USB PHY HS section 0.8-V power supply USDVDD 0.76 0.8 0.84 V USB PHY SS section transmitter power supply USVPTX 0.76 0.8 0.84 V USB PHY SS section 3.3-V power supply USVPH 3.135 3.3 3.465 V Junction temperature Tj — — 103 °C

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 3 Electrical Characteristics R01DS0459EJ0100 Rev.1.00 Page 49 of 79 Jul 24, 2024

3.3 Power-On/Off Procedures

3.3.1 Power-On Sequence (PWC)

Min.: 10 µs Max.: None PWRSTN PWVDD RTRSTN RTVDD08 RTVDD PWVDD08 No restriction on relative timing Timing of both RTVDD and RTVDD08 rising Min.: 10 µs Max.: None Timing of both PWVDD and PWVDD08 rising Min.: 32-kHz OSC oscillation stabilization time No restriction on relative timing Timing of either PWVDD or PWVDD08 rising 10% 90% 10% 90% Min.: 1 ms, Max.: None 0.4 × PWVDD 0.4 × RTVDD Figure 3.3-1 Power-On Sequence (PWC)

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 3 Electrical Characteristics R01DS0459EJ0100 Rev.1.00 Page 50 of 79 Jul 24, 2024

3.3.2 Power-On/Off Sequence (other than for PWC)

3.3.2.1 Power-On Sequence (other than for PWC)

Min.: 1 µs Max.: None Min.: 20 µs Max.: None Min.: 0 µs Max.: None Min.: 0 µs Max.: 10 ms 0.8 V 1.8 V 0.8 V Timing.4 Timing.3 Timing.2 Timing.1 0.8 V 1.1 V 1.8 V Min.: 40 µs, Max.: None Timing.5 Min.: 10 µs, Max.: None 3.3 V: Min.: 40 µs, Max.: None (USVD330, USVPH) 3.3 V: Min., Max.: None (VDD33) Min.: 40 µs, Max.: None Min.: 10 µs Max.: None 3.3 V 0.8 V: Min.: 10 µs, Max.:10 ms 1.1 V: Min.: 80 µs, Max.: None 1.8 V: Min.: 80 µs, Max.:10 ms 90% 10% 10% 10% 10% 90% 90% 90% 90% RSTN (Input) 0.4 × VDD18 LPVDD 0.8 V 10% 90% Min.: 10 µs, Max.: None Min.: 48-MHz OSC oscillation stabilization time 10% Note: See Table 3.3-1, Table 3.3-2, and Table 3.3-3 for the power supplies which are turned on with the given timing. Figure 3.3-2 Power-On Sequence (other than for PWC) Table 3.3-1, Table 3.3-2, and Table 3.3-3 show the correspondence between the power supplies and the power-on (off) timings. Table 3.3-1 Various Power Supplies and Power On/Off Timings Power Voltage Power Supply Name Timing 0.8 V VDD08 Timing.1

1.1 V LPVDDQ

1.8 V VDD18, LPVAA

0.8 V U2VDD08, U3VDD08, U4VDD08, PCVDD08, OTVDD08 Timing.2 1.8 V U2VDD18, U3VDD18, U4VDD18, PCVDD18, OTVDD18, USVDDH Timing.3 3.3 V VDD33, USVD330, USVPH Timing.4 0.8 V USDVDD, USVP, USVPTX, LPVDD*1 Timing.5 Note 1. When not controlled by the System FW, the power is on (off) at Timing.5. When controlled by the System FW, connect the 0.8-V power supply to the LPVDD pin of this LSI via the power switch. In addition, connect the PWMEMSWIENA pin of this LSI to an enable pin of this power switch.

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 3 Electrical Characteristics R01DS0459EJ0100 Rev.1.00 Page 51 of 79 Jul 24, 2024 Table 3.3-2 Various Power Supplies and Power On/Off Timings (PLL, TSU, etc.) Power Voltage Power Supply Name Timing 0.8 V U7VDD08, PLDVDD08n (n = 1, 2, 3, 4, 6), TSnDVDD08A (n = 0, 1) Timing.1 or Timing.2

1.8 V U5VDD18, U6VDD18, U7VDD18, PLVDDn (n = 1, 2, 3, 4, 6), TSnAVDD18 (n = 0, 1),

Timing.1 or Timing.3 Table 3.3-3 Various Power Supplies and Power On/Off Timings (1.8-V/3.3-V Switching I/O) I/O Voltage Power Supply Name Case Timing Used as the 1.8-V I/O Pre-driver power supply*1 1 Timing.1 I/O power supply*2 Pre-driver power supply*1 2 Timing.1 I/O power supply*2 Timing.3 Pre-driver power supply*1 3 Timing.3 I/O power supply*2 Used as the 3.3-V IO Pre-driver power supply*1 4 Timing.1 I/O power supply*2 Timing.4 Pre-driver power supply*1 5 Timing.3 I/O power supply*2 Timing.4 Note 1. MMPREDVDD, PAPREDVDD,PBPREDVDD, PCPREDVDD, SD0PREDVDD, SD1FVDD, U10VDD18, U11VDD18, GEPREDVDD Note 2. MMMODVDD, PAMODVDD, PBMODVDD, PCMODVDD, SD0MODVDD, SD1FMODVDD, U10MODVDD, U11MODVDD, GEMODVDD The following restrictions apply to the order of turning on the pre-driver power supply and the I/O power supply for the power supply of the 1.8-V/3.3-V switching I/O.

When used as the 1.8-V I/O, “the pre-driver power supply and the I/O power supply are turned on at the same time” or “the pre-driver power supply is turned on first and then the I/O power supply”.
When used as the 3.3-V I/O, “the pre-driver power supply is turned on first and then the I/O power supply”. When used as the 1.8-V I/O, the pre-driver power supply and the I/O power supply must be turned on or off in case 1, 2, or 3. When used as the 3.3-V I/O, they must be turned on or off in case 4 or 5.

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 3 Electrical Characteristics R01DS0459EJ0100 Rev.1.00 Page 52 of 79 Jul 24, 2024

3.3.2.2 Power-Off Sequence (other than for PWC)

0.8 V (USDVDD, USVP, USVPTX, LPVDD)

RSTN (Input) Timing.3 Timing.2 0.8 V (VDD08), 1.1 V (LPVDDQ), 1.8 V (LPVAA, VDD18) Timing.5 0.4 × VDD18 90% 90% 10% 90% Min.: 0 µs*2 Max.: None Min.: 0 µs*1 Max.: None Min.: 0 µs Max.: None 90%

0.8 V (U7VDD08, PLDVDD08n (n = 1, 2, 3, 4, 6), TSnDVDD08A (n = 0, 1))

90%

1.8 V (U5VDD18, U6VDD18, U7VDD18, PLVDDn (n = 1, 2, 3, 4, 6), TSnAVDD18 (n = 0, 1), )

PLL, TSU power supply*3 Min.: 0 µs Max.: None Min.: 0 µs Max.: None 1.8-V/3.3-V switching I/O power supply (when used as the 3.3-V IO)*4 10% Pre-driver power supply (MMPREDVDD, PAPREDVDD, PBPREDVDD, PCPREDVDD, SD0PREDVDD, SD1FVDD, U10VDD18, U11VDD18, GEPREDVDD) IO power supply (MMMODVDD, PAMODVDD, PBMODVDD, PCMODVDD, SD0MODVDD, SD1FMODVDD, U10MODVDD, U11MODVDD, GEMODVDD) 90% Min.: 0 µs Max.: None90% Min.: 0 µs Max.: None Timing.1 Timing.3 Timing.1 Timing.4 Timing.1 Timing.3 1.8 V (PREDVDD33) 90% 10%

3.3 V (VDD33, USVD330, USVPH)

90% Min.: 0 µs Max.: None Timing.4

1.8 V (U2VDD18, U3VDD18, U4VDD18, PCVDD18, OTVDD18, USVDDH)

0.8 V (U2VDD08, U3VDD08, U4VDD08, PCVDD08, OTVDD08)

Min.: 0 µs Max.: None Note: The power off time difference must be minimized. Note 1. The power supply in the case of Timing.2 (0.8 V) must be turned off no less than 0 ns after the power supply in the case of Timing.3 (1.8 V) is turned off Note 2. The power supply in the case of Timing.3 (1.8 V) must be turned off no less than 0 ns after the power supply in the case of Timing.4 (3.3 V) is turned off. No restrictions apply to the order of turning off the 0.8-V power supply and the 1.8-V power supply.

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 3 Electrical Characteristics R01DS0459EJ0100 Rev.1.00 Page 53 of 79 Jul 24, 2024 (Continuation of the previous page) Note 4. This is used as the 3.3-V I/O, and the pre-driver power supply and the I/O power supply are indicated in the case of Timing.1 and Timing.4, respectively. The pre-driver power supply must be turned off no less than 0 ns after the I/O power supply is turned off. When used as the 1.8-V I/O, no restrictions apply to the order of turning on the pre-driver power supply and the I/O power supply. Figure 3.3-3 Power-Off Sequence (other than for PWC)

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 3 Electrical Characteristics R01DS0459EJ0100 Rev.1.00 Page 54 of 79 Jul 24, 2024

3.3.3 Timing Limitations when Power is being Turned On

Control the input signals according to the timing limitations for power being turned on.

0.8 V (PCI)

1.8 V (PCI)Timing.3 Timing.2 Timing.1 0.8 V (VDD08)

1.8 V (IO)

PCIe reference clock*1 <PCREFCKP, PCREFCKM (Input)> Min.: 0 µs, Max.: NoneUnstable clock Stable clock signals 10% 90% 10% 90% 10% 90% : Don’t Care Note 1. For the PCIe reference clock, input the clock signal after the oscillation stabilization before the PCI 1.8-V power supply (PCVDD18) is risen. Figure 3.3-4 PCI Reference Clock Input Timing

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 3 Electrical Characteristics R01DS0459EJ0100 Rev.1.00 Page 55 of 79 Jul 24, 2024 RSTN (Input) Timing 4 Timing 1 0.8 V (VDD08)

1.8 V (I/O)

3.3 V (I/O)

1.8 V GPIO (I/O)*1

3.3 V GPIO (I/O)*1

10% 90% 10% 90% Max.: 10 µs Max.: 10 µs : Unknown value Hi-Z, pull-down, or pull-up*2 Hi-Z, pull-down, or pull-up*2 Note 1. After both the internal power and I/O power supply voltages (1.8 V or 3.3 V) have risen, the reset is effective by the time 10 µs (max.) have elapsed and the pin states are stable. The pin states are not guaranteed between the supply voltages rising and the reset becoming effective. Note 2. The state depends on the pin. For the initial states of the respective pins, refer to “Initial Value after POR” in the list of external pins. Figure 3.3-5 GPIO Timing at Power-On

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3.4 DC Characteristics

3.4.1 Supply Current

3.4.1.1 Maximum Supply Current

Conditions for the supply current: Power supply voltage = Max. value, Tj = −40 to 125ºC Table 3.4-1 Max. Supply Currents during Operation (1/2) Item Symbol Max. Unit Note VDD08 core power supply current IDD08 3816 mA The current must be within the maximum supply current. XTAL power supply current IDDRTVDD08 700 µA RTVDD08*1 PWC clock power supply current IDDRTVDD 300*3 µA RTVDD*2 PWC core power supply current IDDPWVDD08 1 mA PWVDD08 PWC I/O power supply current IDDPWVDD 3 mA PWVDD PORT01(A), PORT03 pre-driver power supply current IDDPAPRE 2 mA PAPREDVDD: PWM0 - 7, CSI0, TRDAT6 - 15 PORT01(A), PORT03 I/O power supply current IDDPAMOD 23 mA PAMODVDD: PWM0 - 7, CSI0, TRDAT6 - 15 PORT01(B), PORT04, PORT07, PORT21 pre- driver power supply current IDDPBPRE 1 mA PBPREDVDD: PWM8 - 15, TRACE0 - 6 PORT01(B), PORT04, PORT07, PORT21 I/O power supply current IDDPBMOD 16 mA PBMODVDD: PWM8 - 15, TRACE0 - 6 PORT06 pre-driver power supply current IDDPCPRE 1 mA PCPREDVDD: P0600 - 11 PORT06 I/O power supply current IDDPCMOD 11 mA PCMODVDD: P0600 - 11 PORT10 pre-driver power supply current IDDU10PRE 1 mA U10VDD18 PORT10 I/O power supply current IDDU10MOD 4 mA U10MODVDD PORT11 pre-driver power supply current IDDU11PRE 1 mA U11VDD18 PORT11 I/O power supply current IDDU11MOD 4 mA U11MODVDD PORT00 pre-driver power supply current IDDMMPRE 2 mA MMPREDVDD: eMMC HS200 PORT00 I/O power supply current IDDMMMOD 10 mA MMMODVDD: eMMC HS200 PORT08 pre-driver power supply current IDDSD0PRE 1 mA SD0PREDVDD: SDIO SDR104 PORT08 I/O power supply current IDDSD0MOD 16 mA SD0MODVDD: SDIO SDR104 PORT09 pre-driver power supply current IDDSD1F 1 mA SD1FVDD: SDIO SDR104 PORT09 I/O power supply current IDDSD1MOD 16 mA SD1FMODVDD: SDIO SDR104 PORT15, PORT16, PORT17 pre-driver power supply current IDDGEPRE 1 mA GEPREDVDD PORT15, PORT16, PORT17 I/O power supply current IDDGEMOD 17 mA GEMODVDD VDD18 group I/O power supply current (PORT02 I/O, PORT05 I/O, PORT20 I/O. 1.8-V OSC, RSTN I/O, debugger I/O, MD0-7 I/O) IDD18 3 mA VDD18: IIC0 - 1, DEBUG

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 3 Electrical Characteristics R01DS0459EJ0100 Rev.1.00 Page 57 of 79 Jul 24, 2024 Table 3.4-1 Max. Supply Currents during Operation (2/2) Item Symbol Max. Unit Note VDD33 group pre-driver power supply current (PORT12 I/O, PORT13 I/O, PORT14 I/O, PCIe I/O, USB I/O, LSI test I/O) IDDPRE33 2 mA PREDVDD33 VDD33 group I/O power supply current (PORT12 I/O, PORT13 I/O, PORT14 I/O, PCIe I/O, USB I/O, LSI test I/O) IDD33 20 mA VDD33 PLL ch. 1, 2, 3, 4, 6 0.8-V power supply current IDDPL08 16 mA Total of PLDVDD081, PLDVDD082, PLDVDD083, PLDVDD084, PLDVDD086 PLL ch. 1, 2, 3, 4, 6 1.8-V power supply current IDDPL18 14 mA Total of PLVDD1, PLVDD2, PLVDD3, PLVDD4, PLVDD6 0.8-V power supply current IDDOT08 9 mA OTVDD08 1.8-V power supply current IDDOT18 60 mA OTVDD18 TSU ch. 0 0.8-V power supply current IDDTS08 1 mA TS0DVDD08A TSU ch. 1 0.8-V power supply current IDDTS08 1 mA TS1DVDD08A TSU ch. 0 1.8-V power supply current IDDTS18 4 mA TS0AVDD18 TSU ch. 1 1.8-V power supply current IDDTS18 4 mA TS1AVDD18 Sub-unit 0.8-V power supply IDDU08 15 mA Total of U2VDD08, U3VDD08, U4VDD08, U7VDD08 Sub-unit 1.8-V power supply IDDU18 8 mA Total of U2VDD18, U3VDD18, U4VDD18, U5VDD18, U6VDD18, U7VDD18 LPDDR4 core 0.8-V power supply current IDDLPVDD 800 mA LPVDD: 3200 Mbps LPDDR4 PLL 1.8-V power supply current IDDLPVAA 6 mA LPVAA: 3200 Mbps LPDDR4 PHY 1.1-V power supply current IDDLPVDDQ 314 mA LPVDDQ: 3200 Mbps PCIe PHY 0.8-V power supply current IDDPC08 188 mA PCVDD08 PCIe PHY 1.8-V power supply current IDDPC18 132 mA PCVDD18 USB PHY 0.8-V power supply current IDDUS08 88 mA Total of USDVDD, USVP, USVPTX USB PHY 1.8-V power supply current IDDUS18 21 mA USVDDH USB PHY 3.3-V power supply current IDDUS33 57 mA Total of USVD330, USVPH Note 1. Reference value for the XTAL power supply current (at normal temperature at 0.8 V): 35 µA Note 2. Reference value for the PWC clock power supply current (at normal temperature at 1.5 V): 10 µA Note 3. In normal operation, current flows to the PWISO pin via a pull-up resistor, so this amount of current must be taken into account when the current drawn is estimated. [Example] When the pull-up resistance is 10kΩ, 1.5 V/10kΩ = 150 µA

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3.4.2 Standard I/O Characteristics

For the I/O groups, refer to the multiplexed pin group numbers in the list of external pins. Table 3.4-2 DC Characteristics Item Symbol Min. Typ. Max. Unit Condition External voltage tolerance 1.8-V I/O group 3*4 VTOL — — 3.6 V VDD power-off & on High-level input voltage — VIH 0.7 × VDD — VDD + 0.3 V — Low-level input voltage — VIL −0.3 — 0.3 × VDD V — Hysteresis voltage 1.5-V I/O group*1 ΔV 0.1 × VDD — — V — 1.8-V I/O group 1*2 1.8-V I/O group 2*3 ΔV 0.1 × VDD — — V 1.8-V I/O group 3*4 ΔV 0.08 × VDD — — V 3.3/1.8-V switching I/O group 1*6 ΔV 0.08 × VDD — — V 3.3/1.8-V switching I/O group 2*7 ΔV 0.1 — — V 3.3-V I/O group*8 ΔV 0.08 × VDD — — V High-level input current (Non-tolerant input buffer) 1.5V I/O group*1 IIH — — 12 µA Vin15 = VDD max & VDD power-on 1.8-V I/O group 1*2 1.8-V I/O group 2*3 1.8-V I/O group 4*5 IIH — — 12 µA Vin18 = VDD max & VDD power-on 3.3/1.8-V switching I/O group 1*6 3.3/1.8-V switching I/O group 2*7 IIH — — 12 µA Vin33 = VDD max & VDD power-on 3.3-V I/O group*8 IIH — — 12 µA High-level input current (Tolerant input buffer) 1.8-V I/O group 3*4 IIH — — 12 µA Vin18_tol = VDD max & VDD power-on High-level input current (Input buffer with pull-down resistor) 1.8-V I/O group 3*4 1.8-V I/O group 4*5 IIH — — 200 µA Vin18 = VDD max 3.3/1.8-V switching I/O group 1*6 IIH — — 200 µA Vin33 = VDD max 3.3/1.8-V switching I/O group 2*7 IIH — — 150 µA 3.3-V I/O group*8 IIH — — 200 µA Low-level input current (Non-tolerant input buffer) 1.5-V I/O group*1 IIL −12 — — µA Vin15 = VSS 1.8-V I/O group 1*2 1.8-V I/O group 2*3 IIL −12 — — µA Vin18 = VSS 1.8-V I/O group 4*5 IIL −12 — — µA 3.3/1.8-V switching I/O group 1*6 IIL −12 — — µA Vin33 = VSS 3.3/1.8-V switching I/O group 2*7 IIL −12 — — µA 3.3-V I/O group*8 IIL −12 — — µA Low-level input current (Tolerant input buffer) 1.8-V I/O group 3*4 IIL −12 — — µA Vin18_tol = VSS Low-level input current (Input buffer with pull-down resistor) 1.8-V I/O group 2*3 IIL −180 — — µA Vin18 = VSS 1.8-V I/O group 3*4 1.8-V I/O group 4*5 IIL −200 — — µA 3.3/1.8-V switching I/O group 1*6 IIL −200 — — µA Vin33 = VSS 3.3/1.8-V switching I/O group 2*7 IIL −190 — — µA 3.3-V I/O group*8 IIL −200 — — µA

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 3 Electrical Characteristics R01DS0459EJ0100 Rev.1.00 Page 59 of 79 Jul 24, 2024 Item Symbol Min. Typ. Max. Unit Condition High-level output voltage 1.5-V I/O group*1 VOH 0.8 × VDD — VDD V IOH = −1.8 mA- 1.8-V I/O group 1*2 VOH 0.8 × VDD — VDD V IOH = −3.8 mA mA (drive strength X1/X2/X4/X6) 1.8-V I/O group 3*4 1.8-V I/O group 4*5 mA (drive strength X1/X2/X4/X6) 3.3/1.8-V switching I/O group 1 (1.8 V)*6 mA (drive strength X1/X2/X4/X6) 3.3/1.8-V switching I/O group 1 (3.3 V)*6 VOH 0.8 × VDD — VDD V IOH = −2/−4/−8/−12 mA (drive strength X1/X2/X4/X6) 3.3/1.8-V switching I/O group 2 (1.8 V)*7 VOH 0.8 × VDD — VDD V IOH = −5/−6/−7/−10 mA (drive strength X1/X2/X4/X6) 3.3/1.8-V switching I/O group 2 (3.3 V)*7 VOH 0.8×VDD — VDD V IOH = −9/−11/−13/−18 mA (drive strength X1/X2/X4/X6) 3.3-V I/O group*8 VOH 0.8 × VDD — VDD V IOH = −2/−4/−8/−12 mA (drive strength X1/X2/X4/X6) Low-level output voltage 1.5-V I/O group*1 VOL 0 — 0.2 × VDD V IOL = 1.8 mA 1.8-V I/O group 1*2 VOL 0 — 0.2 × VDD V IOL = 3.8 mA (drive strength X1/X2/X4/X6) 1.8-V I/O group 3*4 1.8-V I/O group 4*5 (drive strength X1/X2/X4/X6) 3.3/1.8-V switching I/O group 1 (1.8 V)*6 (drive strength X1/X2/X4/X6) 3.3/1.8-V switching I/O group 1 (3.3 V)*6 VOL 0 — 0.2 × VDD V IOL = 2/4/8/12 mA (drive strength X1/X2/X4/X6) 3.3/1.8-V switching I/O group 2 (1.8 V)*7 VOL 0 — 0.2 × VDD V IOL = 5/6/7/10 mA (drive strength X1/X2/X4/X6) 3.3/1.8-V switching I/O group 2 (3.3 V)*7 VOL 0 — 0.2×VDD V IOL = 9/11/13/18 mA (drive strength X1/X2/X4/X6) 3.3-V I/O group*8 VOL 0 — 0.2 × VDD V IOL = 2/4/8/12 mA (drive strength X1/X2/X4/X6) Pull-up resistance 1.8-V I/O group 2*3 RPU 11 — 47 kΩ — 1.8-V I/O group 3*4 1.8-V I/O group 4*5 RPU 11 — 49 kΩ — 3.3/1.8-V switching I/O group 1 (1.8 V)*6 RPU 11 — 49 kΩ — 3.3/1.8-V switching I/O group 1 (3.3 V)*6 RPU 15 — 83 kΩ — 3.3/1.8-V switching I/O group 2 (1.8 V)*7 RPU 12 — 92 kΩ — 3.3/1.8-V switching I/O group 2 (3.3 V)*7 RPU 18 — 72 kΩ — 3.3-V I/O group*8 RPU 15 — 83 kΩ —

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 3 Electrical Characteristics R01DS0459EJ0100 Rev.1.00 Page 60 of 79 Jul 24, 2024 Item Symbol Min. Typ. Max. Unit Condition Pull-down resistance 1.8-V I/O group 3*4 1.8V I/O group 4*5 RPD 12 — 45 kΩ — 3.3/1.8-V switching I/O group 1 (1.8 V)*6 RPD 12 — 45 kΩ — 3.3/1.8-V switching I/O group 1 (3.3 V)*6 RPD 20 — 75 kΩ — 3.3/1.8-V switching I/O group 2 (1.8 V)*7 RPD 13 — 92 kΩ — 3.3/1.8-V switching I/O group 2 (3.3 V)*7 RPD 24 — 87 kΩ — 3.3-V I/O group*8 RPD 20 — 75 kΩ — Input capacitance — Cin — — 10 pF Note 1. Target I/O group: 1.5-V PWC I/O Note 2. Target I/O group: PWC I/O Note 3. Target I/O group: PORT20 I/O, RSTN I/O, 1.8-V OSC Note 4. Target I/O group: PORT02 I/O, PORT05 I/O Note 5. Target I/O group: MD0-7 I/O, debugger I/O Note 6. Target I/O group: PORT01(A) I/O, PORT03 I/O, PORT01(B) I/O, PORT04 I/O, PORT07 I/O, PORT21 I/O, PORT06 I/O, PORT10 I/O, PORT11 I/O Note 7. Target I/O group: PORT00 I/O, PORT08 I/O, PORT09 I/O, PORT15 I/O, PORT16 I/O, PORT17 I/O Note 8. Target I/O group: PORT12 I/O, PORT13 I/O, PORT14 I/O, PCIe I/O, USB I/O, LSI test I/O

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3.5 AC Characteristics

AC characteristics measurement conditions

I/O signal reference levels: VDD18/2, VDD33/2, MMMODVDD/2, PAMODCDD/2, PBMODVDD/2, PCMODVDD/2, SD0MODVDD/2, SD1FMODVDD/2, U10MODVDD/2, GEMODVDD/2, U11MODVDD/2, VIH, VOH (min.), VIL, VOL (max.) (Refer to the corresponding timing charts.)
Output load: CL = 20 pF if not otherwise stated

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3.5.1 IIC Bus Interface

Table 3.5-1 IIC Timing Item Symbol Min. Typ. Max. Unit Note I2SCLn cycle time tcyc 2500 — — ns I2SCLn low level width tLOW 1300 — — ns I2SCLn high level width tHIGH 600 — — ns Bus free time (time from start to stop condition) tBUF 1300 — — ns Start condition hold time tHSTA 600 — — ns Restart condition setup time tSSTA 600 — — ns Stop condition setup time tSSTO 600 — — ns I2SDAn setup time tSDAT 100 — — ns I2SDAn hold time tHDAT 0 — 900 ns Note: n = 0 to 3 I2SDA I2SCL P S Sr P tBUF tHSTA tSSTA tLOW tHDAT tcyc tSDAT tHIGH tSSTO Note: S: START condition P: STOP condition Sr: Repeated START condition Figure 3.5-1 IIC Timing

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3.5.2 Clocked Serial Interface (CSI)

3.5.2.1 Master Mode

Table 3.5-2 Master Mode Timing Item Symbol Min. Typ. Max. Unit Note CSSCLKn cycle time tcyc 41.66 — — ns CSSCLKn output low level width tLOW 18 — — ns Falling edge mode*1 CSSCLKn output high level width tHIGH 18 — — ns Rising edge mode*1 CSRXDn setup time (CSSCLKn rising and falling edges) tSRXD tLOW − 9 — — ns CSRXDn hold time (CSSCLKn rising and falling edges) t HRXD 5.0 — — ns CSTXDn output delay time (CSSCLKn rising and falling edges) tDTXD −5.0 — 7.5 ns *1 Note: n = 0 to 5 Note 1. The 3-wire serial interface (CSI) should be used with a driving ability of at least X2. Select one of the driving abilities listed below according to the load capacitance. X2 @CL = 15 pF, X4@CL = 20 pF CSSCLKn (Output) CSRXDn (Input) CSTXDn (Output) tcyc tHIGH tLOW tSRXD tHRXD tDTXD (Max.) tDTXD (Min.) CSSCLKn Inverted clock (Output) tLOW tHIGH Figure 3.5-2 Master Mode Timing

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3.5.2.2 Slave Mode

Table 3.5-3 Slave Mode Timing Item Symbol Min. Typ. Max. Unit Note CSSCLKn cycle time tcyc 41.66 — — ns CSSCLKn input low level width tLOW 18 — — ns Falling edge mode CSSCLKn input high level width tHIGH 18 — — ns Rising edge mode CSRXDn setup time (CSSCLKn rising and falling edges) tSRXD 7.5 — — ns CSRXDn hold time (CSSCLKn rising and falling edges) tHRXD 5.0 — — ns CSCSn setup time (CSSCLKn rising and falling edges) tSCS 84 — — ns CSCSn hold time (CSSCLKn rising and falling edges) tHCS 21 — — ns CSTXDn output delay time (CSSCLKn rising and falling edges) t DTXD −5.0 — 10.5 ns *1 Note: n＝0 to 5 Note 1. The 3-wire serial interface (CSI) should be used with a driving ability of at least X2. Select one of the driving abilities listed below according to the load capacitance. X2 @CL = 15 pF, X4@CL = 20 pF CSSCLKn (Input) CSRXDn (Input) CSTXDn (Output) tcyc tHIGH tLOW tSRXD tHRXD tDTXD (Max.) tDTXD (Min.) CSSCLKn Inverted clock (Input) tLOW tHIGH CSCSn (Input) tHCStSCS Figure 3.5-3 Slave Mode Timing

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3.5.3 Ethernet MAC interface (ETHER)

3.5.3.1 100-Mbps Ethernet Mode Table 3.5-4 100-Mbps Ethernet Mode Timing Item Symbol Min. Typ. Max. Unit Note GETXC cycle time tTcyc 39.5 40 40.5 ns GETXEN output delay time tDTXE 0 — 25 ns GETXD output delay time tDTXD 0 — 25 ns GERXC cycle time tRcyc 39.5 40 40.5 ns GERXDV setup time tSRXV 10 — — ns GERXDV hold time tHRXV 10 — — ns GERXD setup time tSRXD 10 — — ns GERXD hold time tHRXD 10 — — ns GERXER setup time tSRER 10 — — ns GERXER hold time tHRER 10 — — ns SFD DATA CRC tDTXD GETXC GETXEN GETXD GETXER GECRS GECOL Preamble tTcyc tDTXE Figure 3.5-4 Transmission Timing SFD DATA CRC tSRXV tHRXD GERXC GERXDV Preamble tHRXV GERXD GERXER tSRXD tRcyc Figure 3.5-5 Reception Timing (Normal)

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 3 Electrical Characteristics R01DS0459EJ0100 Rev.1.00 Page 66 of 79 Jul 24, 2024 SFD DATA GERXC GERXDV Preamble tHRER GERXD GERXER tSRER XXX Figure 3.5-6 Reception Timing (in Cases of Error)

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 3 Electrical Characteristics R01DS0459EJ0100 Rev.1.00 Page 68 of 79 Jul 24, 2024 SFD DATA GERXC GERXDV Preamble tHGRER GERXD GERXER tSGRER XXX Figure 3.5-9 Reception Timing (in Cases of Error)

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3.5.4 SD Host Interface (SDI)

This LSI includes the SD host interfaces that are compliant with the SD specification version 3.01. 3.5.5 eMMC Interface (eMMC) The eMMC interface should be used with a driving ability of at least X2. Table 3.5-6 HS200 Timing Item Symbol Min. Typ. Max. Unit Note MMCLK cycle time tcyc 5 — 10 ns CL = 15 pF VOH = 0.65 × VDD(MMMODVDD) VOL = 0.35 × VDD(MMMODVDD) MMCLK output low level width tLOW 1.5 — — ns MMCLK output high level width tHIGH 1.5 — — ns MMCLK rise time tr — — 1 ns MMCLK fall time tf — — 1 ns MMCMD/ MMDAT output delay time tDDAT −1.5 — 0.9 ns MMCMD/ MMDAT setup time*1 tSDAT — — — ns MMCMD/ MMDAT hold time*1 tHDAT — — — ns MMCMD/ MMDAT data width*1 tWDAT 2.88 — — ns Note 1. In HS200 mode, the sampling clock controller (SCC) must be used for tuning. Table 3.5-7 High Speed Timing Item Symbol Min. Typ. Max. Unit Note MMCLK cycle time tcyc 20 — — ns CL = 30 pF 1.8-V operation: VOH = 0.65 × VDD(MMMODVDD) VOL = 0.35 × VDD(MMMODVDD) 3.3-V operation: VOH = 0.625 × VDD(MMMODVDD) VOL = 0.25 × VDD(MMMODVDD) MMCLK output low level width tLOW 6.5 — — ns MMCLK output high level width tHIGH 6.5 — — ns MMCLK rise time tr — — 3 ns MMCLK fall time tf — — 3 ns MMCMD/ MMDAT output delay time tDDAT −6.5 — 2.5 ns MMCMD/ MMDAT setup time tSDAT 4.0 — — ns MMCMD/ MMDAT hold time tHDAT 2.0 — — ns

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 3 Electrical Characteristics R01DS0459EJ0100 Rev.1.00 Page 70 of 79 Jul 24, 2024 Table 3.5-8 Backward Compatible Timing Item Symbol Min. Typ. Max. Unit Note MMCLK cycle time tcyc 40 — — ns CL = 30 pF 1.8-V operation: VOH = 0.65 × VDD(MMMODVDD) VOL = 0.35 × VDD(MMMODVDD) 3.3-V operation: VOH = 0.625 × VDD(MMMODVDD) VOL = 0.25 × VDD(MMMODVDD) MMCLK output low level width tLOW 10 — — ns MMCLK output high level width tHIGH 10 — — ns MMCLK rise time tr — — 10 ns MMCLK fall time tf — — 10 ns MMCMD/ MMDAT output delay time tDDAT −7.5 — 2.5 ns MMCMD/ MMDAT setup time tSDAT 4.0 — — ns MMCMD/ MMDAT hold time tHDAT 2.0 — — ns tWDAT tSDAT tHDAT tDDAT (Max.) tDDAT (Min.) tf tLOW tr tHIGH tcyc MMCLK (Output) MMCMD / MMDAT (Output) MMCMD / MMDAT (Input) Figure 3.5-10 eMMC Timing

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3.5.6 TRACE Interface (TRACE)

Table 3.5-9 TRACE Interface Timing Item Symbol Min. Typ. Max. Unit Note TRCLK cycle time tcyc 20 — — ns TRCLK output low level width tLOW 9 — — ns TRCLK output high level width tHIGH 9 — — ns TRCTL/ TRDATA output delay time (TRCLK rising edge) tDRDAT 2 — 7 ns TRCTL/ TRDATA output delay time (TRCLK falling edge) tDFDAT 2 — 7 ns tcyc TRCLK (Output) TRDAT, TRCTL (Output) tLOW tHIGH tDRDAT tDFDAT tDRDAT Figure 3.5-11 TRACE Interface Timing

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3.6 Various Analog Characteristics

3.6.1 LPDDR4 PHY Characteristics

The LPDDR4 PHY of this LSI is compliant with the JEDEC 209-4A standard.

3.6.2 USB PHY Characteristics

The USB PHY of this LSI is compliant with the following USB 3.1 GEN1 standard: Universal Serial Bus 3.1 Specification

3.6.3 PCI Express PHY Characteristics

The PCI Express PHY of this LSI is compliant with the following PCIe standard: Revision 4.0 of the PCI Express® Base Specification for Gen1/Gen 2

3.6.4 Temperature Sensor Characteristics

Table 3.6-1 Temperature Sensor Characteristics Item Symbol Min. Typ. Max. Unit Test Condition Accuracy from 70°C to 125°C Acc70_125 — ±2.0 ±3.0 °C Accuracy from −40°C to 70°C Accm40_70 — ±3.0 ±5.0 °C

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 3 Electrical Characteristics R01DS0459EJ0100 Rev.1.00 Page 73 of 79 Jul 24, 2024

3.7 Oscillation Circuits for Connecting Crystal Resonators (OSC)

This LSI chip includes two oscillation circuits (OSC) for connection to crystal resonators, specifically a 48-MHz crystal resonator for the system clock and a 32.768-kHz crystal resonator for the real-time clock. Table 3.7-1 lists the pins for connecting the crystal resonators and the clock frequencies. Figure 3.7-1 shows an example of the connections with crystal resonators. Table 3.7-1 Pins for Connecting Crystal Resonators and Clock Frequency External Pin Name I/O Clock Frequency For the system clock XIN Input 48 MHz (frequency deviation: ±50 ppm, frequency temperature characteristic: ±30 ppm) XOUT Output 48 MHz For the power sequence clock RTXIN Input 32.768 kHz (frequency deviation: ±20 ppm) RTXOUT Output 32.768 kHz This LSI PWC 32-kHz oscillation circuit (OSC IO) Rf RTXIN Rd Crystal resonator 32.768 kHz CL1 CL2 RTXOUT CPG 48-MHz oscillation circuit (OSC IO) Rf XIN Rd Crystal resonator

48 MHz

Note: Rf: Feedback resistor Rd: Dumping resistor Cload (load capacitance of the crystal): See below for the formula. C load = {CL1 × CL2 / (CL1 + CL2)} + PCB’s floating capacitance Figure 3.7-1 Example of Connections with Crystal Resonators

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 3 Electrical Characteristics R01DS0459EJ0100 Rev.1.00 Page 74 of 79 Jul 24, 2024 Place the crystal resonators and the capacitors CL1 and CL2 as close as possible to the pins to connect crystal resonators. To avoid interference and to ensure correct oscillation, the grounding points of the capacitors appended to the crystal resonators should be shared, and no wiring patterns should be placed near these components. The characteristics of the crystal resonators are closely related to the design of the user board. Therefore, the user should sufficiently evaluate them with reference to the example of connection of crystal resonators in Figure 3.7-1. The circuit rating of a crystal resonator depends on the crystal resonator and the stray capacitance of the mounting circuit. Therefore, contact the manufacturer of the crystal resonator before deciding upon the circuit rating. The user should thoroughly evaluate and then set the parameters (resistor and capacitor values). Table 3.7-2 is a list of recommended values for the crystal resonators. Table 3.7-2 Recommended Model Values for the Crystal Resonators Clock Frequency Model Values for the Crystal Resonators Max. ESR*1 Max. CL*2 Max. C0*3 Max. Drive Level 32.768 kHz 70 kΩ 12.5 pF 1.4 pF 1 μW

48 MHz 50 Ω 10 pF 7 pF 100 μW

Note 1. ESR means the equivalent series resistor of the crystal resonator. Note 2. CL is the load capacitance of the crystal resonator. Note 3. C0 is the parallel capacitance of the crystal resonator.

RZ/V Series, VisionAI_ASSP RZ/V2MA Section 4 Package Dimensions R01DS0459EJ0100 Rev.1.00 Page 75 of 79 Jul 24, 2024 Section 4 Package Dimensions Unit:mm P-FBGA841-15x15-0.50 PRBG0841KA-A - 0.71 Figure 4.1 Package Dimensions

RZ/V Series, VisionAI_ASSP RZ/V2MA REVISION HISTORY R01DS0459EJ0100 Rev.1.00 Page 76 of 79 Jul 24, 2024 REVISION HISTORY RZ/V Series, VisionAI_ASSP RZ/V2MA Datasheet

REVISION HISTORY

Description

Rev. Date Page Summary

1.00 Jul 24, 2024  First edition issued

General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1. Precaution against Electrostatic Discharge (ESD) A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices. 2. Processing at power-on The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the level at which resetting is specified. 3. Input of signal during power-off state Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Follow the guideline for input signal during power-off state as described in your product documentation. 4. Handling of unused pins Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. 5. Clock signals After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable. 6. Voltage application waveform at input pin Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.). 7. Prohibition of access to reserved addresses Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these addresses as the correct operation of the LSI is not guaranteed. 8. Differences between products Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system- evaluation test for the given product.

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© 2024 Renesas Electronics Corporation. All rights reserved. Trademarks (continued) For the “Cortex” notation, it is used as follows; — Arm® Cortex®-A53 Note that in each section of the Manual, this may be noted as Cortex-A53. Examples of trademark or registered trademark used in the document of RZ/V2MA; CoreSight™: CoreSight is a trademark of Arm Limited. Neon™ : Neon is a trademark of Arm Limited. eMMC™: eMMC is a trademark of MultiMediaCard Association PCIe®: PCIe is a registered trademark of PCI-SIG, Inc. PCI Express®: PCI Express is a registered trademark of PCI-SIG, Inc. Note that in each section of the Manual, trademark notation of ® and TM may be omitted. All other trademarks and registered trademarks are the property of their respective owners.

Product Information

R9A09G055MA3GBG specifications and overview.

Summary

RZ/V Series, VisionAI_ASSP RZ/V2MA Rev.1.00 Jul 24, 2024

Description

RZ/V Series, VisionAI_ASSP RZ/V2MA Rev.1.00 Jul 24, 2024

Source title R9A09G055MA3GBG Datasheet(PDF) - Renesas Technology Corp

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