R9A07G043F05GBG RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 65

Technical content

Features

This LSI has following features.  CPU

  • AndesCore™ AX45MP, single-core Max. operating frequency: 1.0 GHz  On-chip SRAM and external memory interfaces
  • On-chip shared SRAM (128-Kbytes on-chip SRAM with ECC)
  • External DDR memory interface 1-channel memory controller for DDR3L-1333 or DDR4-1600 with a 16-bit bus width
  • SPI Multi I/O Bus Controller × 1 channel (4-bit Double data rate)
  • SD card host interface × 2 channels
  • Multimedia card interface × 1 channel (Shared with SDHI)  Various communication/storage/network interfaces
  • USB 2.0 × 2 channels (Host only 1 channel/Host-Function 1 channel)
  • Gigabit Ethernet controller × 2 channels
  • CANFD interface × 2 channels
  • I2C bus interface × 4 channels
  • Serial communication interface (SCI) × 2 channels
  • Serial communication interface with FIFO (SCIF) × 5 channels
  • Serial Peripheral Interface (RSPI) × 3 channels  Extended-function timers
  • Multi-Function Timer Pulse Unit 32-bit × 1 channel, 16-bit × 8 channels  Audio
  • Serial sound interface × 4 channels  Analog/Digital converter (ADC) and sensor
  • 12-bit A/D converter × 2 channels
  • Thermal Sensor Unit × 1 channel  Security
  • Hardware cryptographic engine [option] RZ/Five Group RZ 32 & 64-bit MPUs, RZ/G Series R01DS0488EJ0110 Rev.1.10 Jun 30, 2025

RZ/Five Group 1. Overview R01DS0488EJ0110 Rev.1.10 Page 2 of 65 Jun 30, 2025 1. Overview

1.1 Outline of Specification

1.1.1 CPU Core

System CPU AX45MP [RZ/Five]

  • AndesCore™ AX45MP Single core 1.0 GHz
  • L1 I-cache 32 Kbytes (Parity) / D-cache 32 Kbytes (ECC)
  • ILM 64 Kbytes (ECC) / DLM 64 Kbytes (ECC), Total 128 Kbytes*1
  • L2 cache 256 KBytes (ECC)
  • Floating point extension DSP/SIMD ISA
  • AndeStar™ V5 Instruction Set Architecture (ISA) Note 1. The ILM and DLM are generally not used in Linux. Please refer also AndesCoreAX45MP-1C Processor Reference Manual for details. Boot [RZ/Five]
  • 6 boot modes Boot Mode 0: Booting from eSD Boot Mode 1: Booting from eMMC (1.8 V) Boot Mode 2: Booting from eMMC (3.3 V) Boot Mode 3: Booting from a serial flash memory (Single / Quad) connected to the SPI Multi I/O bus space (1.8 V) Boot Mode 4: Booting from a serial flash memory (Single / Quad) connected to the SPI Multi I/O bus space (3.3 V) Boot Mode 5: Booting from SCIF download Debug Interface [RZ/Five]
  • AndesCore™ AX45MP Debug Subsystem
  • JTAG interface supported
  • Embedded Debug Module with up to 8 triggers

RZ/Five Group 1. Overview R01DS0488EJ0110 Rev.1.10 Page 3 of 65 Jun 30, 2025

1.1.2 CPU Peripheral

(CPG) [RZ/Five]

  • Generates the clocks from external clock (EXCLK 24 MHz). Maximum AndesCore™ AX45MP Single core clock: 1.0 GHz Maximum DDR clock: 666 MHz (DDR3L-1333), 800 MHz (DDR4-1600) Maximum AXI-bus clock: 200 MHz Maximum APB-bus clock: 100 MHz
  • SSC (Spread Spectrum Clock) supported Direct Memory Access Controller (DMAC) [RZ/Five]
  • 2 modules, 16 channels per module
  • Transfer request: On-chip peripheral request / auto request (software trigger)
  • A specific DMA transfer interval can be specified to adjust the bus occupancy.
  • LINK mode (DMA transfer under descriptor control) supported
  • Transfer information can be automatically reloaded Platform-Level Interrupt Controller (PLIC) [RZ/Five]
  • Andes Platform-Level Interrupt Controller
  • 255 priority levels available
  • Software-programmable interrupt generation
  • External Interrupt pins (NMI, IRQ7 to IRQ0, TINT31-0)
  • On-chip peripheral Interrupts: priority level set for each module General-purpose I/O (GPIO) [RZ/Five]
  • General-purpose I/O ports Thermal Sensor Unit (TSU) [RZ/Five]
  • 1 channel

1.1.3 Internal Memory

System RAM [RZ/Five]

  • RAM of 128 Kbytes (ECC)

RZ/Five Group 1. Overview R01DS0488EJ0110 Rev.1.10 Page 4 of 65 Jun 30, 2025

1.1.4 External Memory Interface

External Bus Controller for DDR3L / DDR4 SDRAM (DDR) [RZ/Five]

  • Support DDR3L-1333 / DDR4-1600
  • Bus Width: 16-bit
  • In line ECC supported (Support error detection interrupt)
  • Memory Size: Up to 4 Gbyes
  • Auto Refresh supported SPI Multi I/O Bus Controller [RZ/Five]
  • 1 channel (4-bit Double data rate)
  • 1 serial flash memory with multiple I/O bus sizes (single / quad) can be connected
  • External address space read mode (built-in read cache)
  • SPI operation mode
  • Maximum Clock Frequency: – 50 MHz (Quad-SPI DDR) – 66 MHz (Quad-SPI SDR) SD Card Host Interface / Multimedia Card Interface (SD/MMC) [RZ/Five]
  • 2 channels
  • Channel 0 supports SDHI / e-MMC (boot supported)
  • Channel 1 supports SDHI
  • SD memory I/O card interface (1-bit / 4-bit SD bus)
  • SD, SDHC and SDXC SD memory card access supported
  • Compliant with SD 3.0
  • Default, high-speed, UHS-I/SDR50, SDR104 transfer modes supported
  • Error check function: CRC7 (Command), CRC16 (Data)
  • Card detection function, write protect supported
  • MMC interface (1-bit / 4-bit / 8-bit MMC bus)
  • e-MMC device access supported
  • Compliant with eMMC 4.51
  • High-speed, HS200 transfer modes supported

RZ/Five Group 1. Overview R01DS0488EJ0110 Rev.1.10 Page 5 of 65 Jun 30, 2025

1.1.5 Sound Interface

(SSI) [RZ/Five]

  • 4 channels bidirectional serial transfer
  • 2 external clock sources available
  • Duplex communication (channel 0, 1, and 3)
  • Support of I2S / Monaural / TDM audio formats
  • Support of master and slave functions
  • Generation of programmable word clock and bit clock
  • Multi-channel formats
  • Support of 8, 16, 18, 20, 22, 24, and 32-bit data formats
  • Support of 32-stage FIFO for transmission and reception
  • Support of LR-clock continue function in which the LR-clock signal is not stopped

1.1.6 Storage and Network

USB2.0 Host / Function (USB) [RZ/Five]

  • 2 channels (ch0: Host-Function ch1: Host only)
  • Compliance with USB2.0
  • Supports On-The-Go (OTG) Function
  • Supports Battery Charging Function
  • Internal dedicated DMA Gigabit Ethernet Interface (GbE) [RZ/Five]
  • Number of channels – 2 channels: Support by 361-pin BGA – 1 channel: Support by 266-pin BGA
  • Supports transfer at 1000 Mbps and 100 Mbps, 10 Mbps
  • Supports filtering of Ethernet frames
  • Supports interface conforming to IEEE802.3 PHY RGMII (Reduced Gigabit Media Independent Interface)
  • Supports interface conforming to IEEE802.3 PHYMII (Media Independent Interface) Controller Area Network Interface (CAN) [RZ/Five]
  • 2 channels
  • ISO 11898-1 (2003) compliant
  • CAN-FD ISO 11898-1 (CD2014) compliant
  • Message buffer – Up to 64 × 2-channel receive message buffer: Shared among all channels – 16 transmit message buffers per channel

RZ/Five Group 1. Overview R01DS0488EJ0110 Rev.1.10 Page 6 of 65 Jun 30, 2025

1.1.7 Timer

Multi-function Timer Pulse Unit 3 (MTU3a) [RZ/Five]

  • 9 channels (16 bits × 8 channels, 32 bits × 1 channel)
  • Module clock frequency (P0ϕ): 100 MHz
  • Maximum 28 lines of pulse inputs/outputs and 3 lines of pulse inputs
  • 14 types of count clocks selectable
  • Input capture function
  • 39 outputs compare and input capture registers
  • Counter clear operation (Simultaneous counter clearing by Compare match or Input capture is available)
  • Simultaneous writing to multiple timer counters (TCNT)
  • Synchronous input/output of each register due to synchronous operation of the counter
  • Buffered operation
  • Cascade-connected operation
  • 43 types of interrupt sources
  • Automatic transfer of register data
  • Pulse output modes Toggle, PWM, complementary PWM, and reset-synchronized PWM modes
  • Synchronization of multiple counters
  • Phase counting mode – 16-bit mode (channel 1 and 2) – 32-bit mode (channel 1 and 2)
  • Counter function of dead time compensation
  • Digital filter functions for the input capture and external count clock pin Port Output Enable 3 (POE3) [RZ/Five]
  • Control of the high-impedance state of the MTU3a waveform output pins
  • Activation with four input pins
  • Activation on detection of short-circuited outputs
  • Activation by register write
  • Additional programming of output control target pins is possible. Watchdog Timer (WDT) [RZ/Five]
  • 1 channel
  • A counter overflow can reset the LSI
  • CPU parity error can reset the LSI General Timer (GTM) [RZ/Five]
  • 32 bits × 3 channels
  • Two operating modes – Interval timer mode – Free-running comparison mode

RZ/Five Group 1. Overview R01DS0488EJ0110 Rev.1.10 Page 7 of 65 Jun 30, 2025

1.1.8 Peripheral Module

(I2C) [RZ/Five]

  • 4 channels (ch0,1 = Dedicated pin, ch2,3 = Multiplexed pin)
  • Master mode and slave mode supported
  • Support for 7-bit and 10-bit slave address formats
  • Support for multi-master operation
  • Timeout detection Serial Communication Interface with FIFO (SCIFA) [RZ/Five]
  • 5 channels
  • Clock synchronous mode or asynchronous mode selectable
  • Simultaneous transmission and reception (full-duplex communication) supported
  • Dedicated baud rate generator
  • Separate 16-byte FIFO registers for transmission and reception
  • Modem control function (channel 0, 1, and 2 in asynchronous mode) Serial Communication Interface (SCI) [RZ/Five]
  • 2 channels
  • Clock synchronous mode, asynchronous mode, or smart card interface mode is selectable
  • Simultaneous transmission and reception (full-duplex communication) supported
  • Dedicated baud rate generator
  • LSB first / MSB first selectable
  • Modem control function
  • Encoding and decoding of IrDA communications waveforms in accord with version 1.0 of the IrDA standard (on channel 0) Renesas Serial Peripheral Interface (RSPI) [RZ/Five]
  • 3 channels
  • SPI operation
  • Master mode and slave mode supported
  • Programmable bit length, clock polarity, clock phase can be selected
  • Consecutive transfers
  • LSB first / MSB first selectable

1.1.9 Security

(TSIP) [option] [RZ/Five]

  • Security algorism – Common key encryption: AES – Non-common key encryption: RSA, ECC
  • Other features – TRNG (true-random number generator) – Hash value generation: SHA-1, SHA-224, SHA-256, GHASH – Support of Unique ID One Time Programmable memory (OTP) [RZ/Five]
  • A nonvolatile memory that can be written only once
  • Security setting, authentication setting are possible
  • Support one time read function (128 bytes)

RZ/Five Group 1. Overview R01DS0488EJ0110 Rev.1.10 Page 8 of 65 Jun 30, 2025

1.1.10 Analog

(ADC) [RZ/Five]

  • 2 channels
  • Resolution: 12-bit
  • Input Range: 0 V ~ 1.8 V
  • Conversion Time: 1 µs
  • Operation Mode: Single Scan / Continuous Scan
  • Condition for A/D conversion start – Software trigger – Asynchronous trigger: External trigger supported – Synchronous trigger: MTU timer

1.1.11 Others

Boundary Scan [RZ/Five]

  • Boundary scan based on IEEE 1149.1 via JTAG interface is supported. Note that some module pins are not available on this boundary scan.

1.1.12 Power Supply Voltage

Power supply voltage [RZ/Five]

  • VDD, PLLn_DVDD11 (n = 23, 5): 1.05 to 1.15 V
  • DDR_VDDQ: 1.14 to 1.26 V (DDR4) / 1.283 to 1.45 V (DDR3L)
  • VDD18, ADC_AVDD18, PLLn_AVDD18 (n = 1, 23, 4, 5, 6): 1.62 to 1.98 V
  • OTP_VDD18, USB_VDD18: 1.65 to 1.95 V
  • PVDD: 2.97 to 3.63 V
  • USB_VDD33: 3.00 to 3.60 V
  • SDn_PVDD (n = 0, 1), SPI_PVDD: 2.97 to 3.63 V / 1.70 to 1.95 V

1.1.13 Temperature Range

Temperature range [RZ/Five]

  • Ta: −40°C to +85°C*1
  • Tj: −40°C to +125°C Note 1. If wider temp is required than this range, use case has to be investigated.

RZ/Five Group 1. Overview R01DS0488EJ0110 Rev.1.10 Page 9 of 65 Jun 30, 2025

1.1.14 Quality level

Quality level [RZ/Five]

  • Industrial usage, etc.

1.1.15 Package

Package [RZ/Five]

  • 361-pin LFBGA, 13-mm square, 0.5-mm pitch
  • 266-pin LFBGA, 11-mm square, 0.5-mm pitch

RZ/Five Group 1. Overview R01DS0488EJ0110 Rev.1.10 Page 10 of 65 Jun 30, 2025

1.2 Block Diagram

The LSI internal bus of this LSI consists of the ACPU bus, MCPU bus, and system bus. Figure 1.1 shows the configuration of the buses. ACPU bus: A bus connected to AX45MP, DDR memory controllers, image processing units, and Storage and Network MCPU bus: A bus connected to serial interface units System bus: A bus connected to the control registers of each unit

RZ/Five Group 1. Overview R01DS0488EJ0110 Rev.1.10 Page 11 of 65 Jun 30, 2025 L2$ 256 Kbytes RISC-V 64-bit: AndesCore AX45MP CPG PLL/SSCG DDR3L/DDR4 SDRAM Sound Interface SDHI / eMMC External Memory Storage and Network MTU3a WDT (1 ch) I2C (4 ch) SCIF (5 ch) SCI/IrDA (1 ch) RSPI (3 ch) Analog Security PWM Timer Peripheral USB2.0 Host USB2.0 Host / Function GbEthernet GbEthernet CAN (2 ch) SSIF (4ch) ADC (2ch) TrustedSecureIP (Option) OTPGPIO TSU (1 ch) ACPU Bus PLIC SDHI System Secure DMAC (16 ch) On-Chip RAM

64 Kbytes

SCI (1 ch) GTM (3 ch) Internal MemorySystem DMAC (16 ch) Machine Timer TZC System Bus MCPU Bus TZCTZC Core 0

32 Kbytes

Figure 1.1 Configuration of LSI Internal Bus

RZ/Five Group 1. Overview R01DS0488EJ0110 Rev.1.10 Page 12 of 65 Jun 30, 2025

1.3 Product Lineup

Table 1.1 Product Lineup Group Package Part Number Security*1 RZ/Five 13 mm BGA R9A07G043F05GBG Available R9A07G043F01GBG Not supported 11 mm BGA R9A07G043F04GBG Available R9A07G043F00GBG Not supported Note 1. The product with security function supports the following features. — Trusted Secure IP — Secure Boot — Secure Debug — HW Key protection — True Random Generator

RZ/Five Group 2. Pin R01DS0488EJ0110 Rev.1.10 Page 13 of 65 Jun 30, 2025 2. Pin

2.1 Pin Assignment

Refer to attached excel file for the “ball view” about pin assignment of this LSI. (Please double-click the icon on the right side)

2.2 External Pins and Multiplexed Functional Pins

Refer to attached excel file for the “pn function list” about information of external pins and multiplexed functional pins of this LSI. (Please double-click the icon on the right side)

RZ/Five Group 3. Electrical Characteristics R01DS0488EJ0110 Rev.1.10 Page 14 of 65 Jun 30, 2025 3. Electrical Characteristics

3.1 Absolute Maximum Ratings

Table 3.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage (3.3 V) PVDD −0.5 to +3.8 V USB_VDD33 Power supply voltage (1.8-V/3.3-V switchable) SD0_PVDD −0.5 to +3.8 V SD1_PVDD SPI_PVDD Power supply voltage (1.8-V/ 2.5-V/ 3.3-V switchable) PVDD182533_0/1 −0.5 to +3.8 V Power supply voltage (1.8 V) VDD18 −0.5 to +2.5 V PLL1_AVDD18 PLL23_AVDD18 PLL4_AVDD18 PLL6_AVDD18 USB_VDD18 ADC_AVDD18 OTP_VDD18 DDR power supply voltage (DDR4/ DDR3L switchable) DDR_VDDQ −0.5 to +2.5 V Power supply voltage (1.1-V) VDD −0.5 to +1.5 V PLL23_DVDD11 Input voltage 3.3-V I/O input pins — −0.3 to 3.3-V power supply (PVDD, USB_VDD33) + 0.3 V 1.8-V/3.3-V switchable I/O input pins — −0.3 to 1.8-V/3.3-V switchable power supply (SD0_PVDD, SD1_PVDD, SPI_PVDD) + 0.3 V 1.8-V/2.5-V/3.3-V switchable I/O input pins — −0.3 to 1.8-V/2.5-V/3.3-V switchable power supply (PVDD182533_0.1) + 0.3 V 1.8-V I/O input pins — −0.3 to 1.8-V power supply (VDD18, CSI_VDD18, USB_VDD18) + 0.3 V Operating temperature Ambient temperature Ta −40°C to +85°C*1 °C Junction temperature Tj −40°C to +125°C °C Storage temperature Ambient temperature T stg −40°C to +150°C °C Note 1. If wider temp is required than this range, use case has to be investigated.

RZ/Five Group 3. Electrical Characteristics R01DS0488EJ0110 Rev.1.10 Page 15 of 65 Jun 30, 2025

3.2 Power Supply

Table 3.2 Power Supply Item Symbol Min. Typ. Max. Unit Remarks Power supply voltage (3.3 V) PVDD 2.97 3.30 3.63 V — Power supply voltage (1.8 V) VDD18, ADC_AVDD18 1.62 1.80 1.98 V — OTP_VDD18 1.65 1.80 1.95 V — Power supply voltage (1.1 V) VDD 1.05 1.10 1.15 V — Power supply voltage (USB) USB_VDD33 3.00 3.30 3.60 V — USB_VDD18 1.65 1.80 1.95 V — Power supply voltage (SD) SD0_PVDD, SD1_PVDD 2.97 3.30 3.63 V When 3.3 V is supplied 1.70 1.80 1.95 V When 1.8 V is supplied Power supply voltage (SPI) SPI_PVDD 2.97 3.30 3.63 V When 3.3 V is supplied 1.70 1.80 1.95 V When 1.8 V is supplied Power supply voltage (Ether) PVDD182533_0/1 2.97 3.30 3.63 V When 3.3 V is supplied 2.25 2.50 2.75 V When 2.5 V is supplied 1.62 1.80 1.98 V When 1.8 V is supplied Power supply voltage (DDR) DDR_VDDQ 1.14 1.20 1.26 V When using DDR4 1.283 1.35 1.45 V When using DDR3L Power supply voltage (PLL) PLL1_AVDD18, PLL23_AVDD18, PLL4_AVDD18, PLL6_AVDD18 1.62 1.80 1.98 V — PLL23_DVDD11 1.05 1.10 1.15 V —

RZ/Five Group 3. Electrical Characteristics R01DS0488EJ0110 Rev.1.10 Page 16 of 65 Jun 30, 2025

3.3 Power-On/Power-Off Sequence

VDD (Core) PLL23_DVDD11 DDR_VDDQ (DDR IO Power) VDD18 ADC_AVDD18 PVDD182533_0/1 (1.8V) OTP_VDD18 PLL1/23/4/6_AVDD18 SD0/1_PVDD (only 1.8 V using) SPI_PVDD (1.8 V) USB_VDD18 PVDD182533_0/1 (2.5 V) PVDD (GPIO 3.3 V) SD0/1_PVDD (1.8 V/3.3 V switching*1 or only 3.3 V using) SPI_PVDD (3.3 V) PVDD182533_0/1 (3.3 V) USB_VDD33 OSC Input PRST# 1.1 V 3.3 V 1.2/1.35 V 1.8 V 2.5 V clock signal 100ms (Max) 100ms (Max) After 1.1 V power-on or the same clock need to be stable 100ms (Max) 1 µsec (Min) 1 µsec (Min) 100ms (Max) Figure 3.1 Power-On/Power-Off Sequence NOTES Note 1. About SD0/1_PVDD, especially in the case of switching between 1.8 V and 3.3 V at same power rail, 1.8-V power-on/off timing can also follow 3.3-V power rail sequence as shown in the Figure 3.1. 2. Turn on the DDR IO power supply at the same time as or after the 1.1-V power supply. 3. From first power rising start to last power rising end must be within 100 ms. 4. The power-off sequence is the reverse of the power-on sequence (PRST# → Low  3.3 V = OFF  Other = OFF) 5. PRST# should be changed from Low to High after the 3.3-V power supply is turned on, after 1 µsec, and after the input clock from the oscillator stabilizes. 6. Refer to SD0/1_PVDD when connecting eMMC.

RZ/Five Group 3. Electrical Characteristics R01DS0488EJ0110 Rev.1.10 Page 18 of 65 Jun 30, 2025

3.4 DC Characteristics

Table 3.3 DC Characteristics (1) [3.3-V I/O] Item Symbol Min. Typ. Max. Unit Remarks High-level input voltage VIH 2 — PVDD + 0.3 V Low-level input voltage VIL −0.3 — 0.8 V Hysteresis threshold ↑ VT+ 0.9 — 2.1 V Hysteresis threshold ↓ VT− 0.7 — 1.9 V Input hysteresis voltage VHYS 0.306 — 0.420 V Output logic high voltage (IOH = –2mA) VOH PVDD – 0.4 — PVDD V (IOH = –4mA) (IOH = –8mA) (IOH = –12mA) Output logic low voltage (IOL = 2mA) VOL 0 — 0.4 V (IOL = 4mA) (IOL = 8mA) (IOL = 12mA) Weak pull-up resistor (input mode) RUP 7K — 100K Ω Weak pull-down resistor (input mode) RDN 7K — 100K Ω Input leakage current ILI — — 5 µA 0V ≤ Vin ≤ PVDD In case of 3state buffer, the leak current when output mode OFF Note: Vin means input voltage of external input pin. Note: Schmitt can be used at only RIIC mode. Table 3.4 DC Characteristics (2) [1.8-V I/O] Item Symbol Min. Typ. Max. Unit Remarks High-level input voltage VIH 0.65 × VDD18 — VDD18 + 0.3 V Low-level input voltage VIL −0.3 — 0.35 × VDD18 V Output logic high voltage (IOH = –2mA) VOH VDD18 – 0.4 — VDD18 V (IOH= –4mA) (IOH = –8mA) (IOH = –12mA) Output logic low voltage (IOL = 2mA) VOL 0 — 0.4 V (IOL = 4mA) (IOL = 8mA) (IOL = 12mA) Table 3.5 DC Characteristics (3) [3.3-V Input] Item Symbol Min. Typ. Max. Unit Remarks High-level input voltage VIH 2.3 — PVDD + 0.3 V Low-level input voltage VIL −0.3 — 0.8 V Hysteresis threshold ↑ VT+ 0.9 — 2.1 V Hysteresis threshold ↓ VT− 0.7 — 1.9 V Input hysteresis voltage VHYS 0.306 — 0.420 V

RZ/Five Group 3. Electrical Characteristics R01DS0488EJ0110 Rev.1.10 Page 19 of 65 Jun 30, 2025 Table 3.6 DC Characteristics (4) [1.8-V Input] Item Symbol Min. Typ. Max. Unit Remarks High-level input voltage VIH 0.65 × VDD18 — VDD18 + 0.3 V Low-level input voltage VIL −0.3 — 0.35 × VDD18 V Table 3.7 DC Characteristics (5) [RGMII/MII] Item Symbol Min. Typ. Max. Unit Remarks Power supply voltage PVDD182533_n 2.97 3.3 3.63 V 3.3-V RGMII/MII Input logic high VIH 2.6 — — V Input logic low VIL — — 0.7 V Output logic high voltage @ 7.7 mA VOH 2.1 — 3.6 V Output logic low voltage @ 9.3 mA VOL 0 — 0.5 V Power supply voltage PVDD182533_n 2.25 2.5 2.75 V 2.5-V RGMII/MII Input logic high VIH 1.9 — — V Input logic low VIL — — 0.7 V Output logic high voltage VOH 2.0 — PVDD182533_n V Output logic low voltage VOL VSS — 0.4 V Power supply voltage PVDD182533_n 1.62 1.8 1.98 V 1.8-V RGMII/MII Input logic high VIH 0.7 × PVDD182533_n — PVDD182533_n + 0.3 V Input logic low VIL VSS − 0.3 — 0.3 × PV DD182533_n V Output logic high @ IOH = 100 µA VOH 0.85 × PV DD182533_n — PVDD182533_n V Output logic low @ IOL = 100 µA VOL VSS — 0.15 × PV DD182533_n V Note: n = 0, 1 Table 3.8 DC Characteristics (6) [3.3 V I/O (SD, QSPI)] Item Symbol Min. Typ. Max. Unit Remarks High-level input voltage VIH 0.625 × SDn_PV DD — SDn_PVDD + 0.3 V Low-level input voltage VIL SDn_PVDD − 0.3 — 0.25 × SDn_PV DD V Output logic high voltage (× 0.5) VOH 0.75 × SDn_PV DD — SDn_PVDD V (× 0.75) (× 1.0) (× 1.5) Output logic low voltage (× 0.5) VOL 0 — 0.125 × SDn_PV DD V (× 0.75) (× 1.0) (× 1.5)

RZ/Five Group 3. Electrical Characteristics R01DS0488EJ0110 Rev.1.10 Page 20 of 65 Jun 30, 2025 Table 3.9 DC Characteristics (7) [1.8 V I/O (SD, QSPI)] Item Symbol Min. Typ. Max. Unit Remarks High-level input voltage VIH 1.27 — 2.00 V Low-level input voltage VIL SDn_PVDD − 0.3 — 0.58 V Output logic high voltage (× 0.5) VOH 0.8 × SDn_PVDD — SDn_PVDD V (× 0.75) (× 1.0) (× 1.5) Output logic low voltage (× 0.5) VOL 0 — 0.2 × SDn_PVDD V (× 0.75) (× 1.0) (× 1.5) Table 3.10 DC Characteristics(8) [I2C Open Drain 3.3 V I/O] Item Symbol Min. Typ. Max. Unit Remarks External pull-up supply VVDDP 2.7 — PVDD V Input high voltage VIH 0.7 × VVDDP — VVDDP + 0.5 V Input Low Voltage VIL −0.5 — 0.3 × VVDDP V Low level output current IOL 20 — — mA VOL = 0.4 V Low level output voltage VOL — — 0.4 V VVDDP > 2 V Input hysteresis VHYST 0.1 × VVDDP — — mV Table 3.11 DC Characteristics (9) [1.2-V Input (DDR4)] Item Symbol Min. Typ. Max. Unit Remarks DC input high level VIH(DC) VREF + 0.068 — — V DC input low level VIL(DC) — — VREF − 0.068 V AC input high level VIH(AC) VREF + 0.093 — — V AC input Low level VIL(AC) — — VREF − 0.093 V DC differential input high VIHdiff 0.136 — — V DC differential input low VILdiff — — −0.136 V AC differential input high VIHdiff(AC) 2 × (VIH(AC) − VREF) — — V AC differential input low VILdiff(AC) — — 2 × (VREF − VIL(AC)) V Differential input cross point voltage relative to 0.8 × VDDIO for DQS VIX(DQS) −0.15 — 0.06 V

RZ/Five Group 3. Electrical Characteristics R01DS0488EJ0110 Rev.1.10 Page 21 of 65 Jun 30, 2025 Table 3.12 DC Characteristics (10) [1.35-V Input (DDR3L)] Item Symbol Min. Typ. Max. Unit Remarks DC input high level VIH(DC) VREF + 0.09 — — V DC input low level VIL(DC) — — VREF − 0.09 VREF =0.5 x DDR_VDDQ AC input high level VIH(AC) VREF + 0.135 — — V AC input low level VIL(AC) — — VREF − 0.135 V VREF =0.5 x DDR_VDDQ DC differential input high VIHdiff 0.18 — — V DC differential input low VILdiff — — −0.18 V AC differential input high VIHdiff(AC) 2 × (VIH(AC) − VREF) — — V AC differential input low VILdiff(AC) — — 2 × (VREF − VIL(AC)) V VREF =0.5 x DDR_VDDQ Differential input cross point voltage relative to 0.5 × DDR_VDDQ for DQS VIX(DQS) −0.075 — 0.075 V Table 3.13 DC Characteristics (11) [1.2-V Output (DDR4)] Item Symbol Min. Typ. Max. Unit Remarks DC output high measurement level (for IV curve linearity) VOH(DC) — 1.1 × DDR_VDDQ — V The swing of ± 0.15 × DDR_VDDQ is based on approximately 50% of the static single-ended output peak-to-peak swing with a driver impedance of 40Ω and an effective test load of 50Ω to V TT = DDR_VDDQ. DC output mid measurement level (for IV curve linearity) VOM(DC) — 0.8 × DDR_VDDQ — V DC output low measurement level (for IV curve linearity) VOL(DC) — 0.5 × DDR_VDDQ — V AC output high measurement level (for output slew rate) VOH(AC) — 0.85 × DDR_VDDQ — V AC output low measurement level (for output slew rate) VOL(AC) — 0.55 × DDR_V DDQ — V Table 3.14 DC Characteristics (12) [1.35-V Output (DDR3L)] Item Symbol Min. Typ. Max. Unit Remarks DC output high measurement level (for IV curve linearity) VOH(DC) — 0.8 × DDR_VDDQ — V The swing of ± 0.1 × DDR_V DDQ is based on approximately 50% of the static single-ended output high or low swing with a driver impedance of 40Ω and an effective test load of 25Ω to VTT = DDR_VDDQ/2. DC output mid measurement level (for IV curve linearity) VOM(DC) — 0.5 × DDR_VDDQ — V DC output low measurement level (for IV curve linearity) VOL(DC) — 0.2 × DDR_VDDQ — V AC output high measurement level (for output slew rate) VOH(AC) — VTT + 0.1 × DDR_V DDQ — V AC output low measurement level (for output slew rate) VOL(AC) — VTT − 0.1 × DDR_VDDQ — V Table 3.15 DC Characteristics (13) [DDR4 Cross Point Voltage for Differential Output Signals (CK/DQS)] Item Symbol Min. Typ. Max. Unit Remarks Differential output cross point voltage relative to 0.67 × DDR_VDDQ V OX(CK/DQS) −0.06 — 0.06 V

RZ/Five Group 3. Electrical Characteristics R01DS0488EJ0110 Rev.1.10 Page 22 of 65 Jun 30, 2025 Table 3.16 DC Characteristics (14) [DDR3L Cross Point Voltage For Differential Output Signals (CK/DQS)] Item Symbol Min. Typ. Max. Unit Remarks Differential output cross point voltage relative to 0.5 × DDR_VDDQ VOX(CK/DQS) −0.1 — 0.1 V Table 3.17 DC Characteristics (15) [USB 2.0] Item Symbol Min. Typ. Max. Unit Remarks Input levels for low/full speed High (driven) VIH 2.0 — — V Low VIL — — 0.8 V Differential input sensitivity VDI 0.2 — — V Differential common mode range VCM 0.8 — 2.5 V Input levels for high speed High-speed squelch detection threshold (differential signal amplitude) VHSSQ 100 — 150 mV High-speed data signaling common mode voltage range (guideline for receiver) VHSCM −50 — 500 mV Output levels for low/full speed Low VOL 0.0 — 0.3 V High (driven) VOH 2.8 — 3.6 V Output signal crossover voltage VCRS 1.3 — 2.0 V Output levels for high-speed High-speed idle level VHSOI −10.0 — 10.0 mV High-speed data signaling high VHSOH 360 — 440 mV High-speed data signaling low VHSOL −10.0 — 10.0 mV Chirp J level (differential voltage) VCHIRPJ 700 — 1100 mV Chirp K level (differential voltage) VCHIRPK −900 — −500 mV Table 3.18 DC Characteristics (16) [ADC] Item Symbol Min. Typ. Max. Unit Remarks Resolution — — 12 — Bit Analog input channel — — — 2 Channel Analog input range AIN VSS — ADC_AVDD18 V Differential non-linearity DNL — — ±3.0 LSB Integral non-linearity INL — — ±6.0 LSB Full-scale error — — ±10 ±20 LSB Offset error — — ±10 ±20 LSB Analog input capacitance CIN — — 12.5 pF Analog input resistance RIN — — 1754 Ω External capacitance CEXT — — (*1) pf External resistance REXT — — (*1) Ω Note 1. Refer to Figure 3.4 for Cext and Rext. The Cext and Rext need to satisfy the sampling time. A/D conversion time = sampling time (6T to 2800T) + 14T. T stands for the cycle of ADIVCLK (20 MHz). If A/D conversion is performed with the minimum conversion time, the sampling time must be 6T. (Minimum conversion time per channel is 1 μs when A/D conversion clock ADIVCLK is 20 MHz.)

RZ/Five Group 3. Electrical Characteristics R01DS0488EJ0110 Rev.1.10 Page 23 of 65 Jun 30, 2025 GND RIN CINCext GNDGND External signal source Rext This LSI Figure 3.4 Analog Input Equivalent Circuit

RZ/Five Group 3. Electrical Characteristics R01DS0488EJ0110 Rev.1.10 Page 24 of 65 Jun 30, 2025 Table 3.19 DC Characteristics (17) [Current Consumption] Item Power rail symbol Max Current Unit Remarks Power Supply voltage(3.3V) PVDD 430 mA PVDD=3.6V Power Supply voltage(1.8V) VDD18 20 mA VDD18=1.98V OTP_AVDD18 20 mA OTP_VDD18=1.95V ADC_AVDD18 10 mA ADC_AVDD18=1.98V Power Supply voltage(1.1V) VDD 2010 mA VDD=1.15V, Condition: AX45MP, Dhrystone Power supply voltage (USB/3.3V) USB_VDD33 20 mA USB_VDD33=3.6V Power supply voltage (USB/1.8V) USB_VDD18 140 mA USB_VDD18=1.95V Power supply voltage (SD/3.3V) SD0_PVDD 260 mA SD0_PVDD=3.63V SD1_PVDD 170 mA SD1_PVDD=3.63V Power supply voltage (SD/1.8V) SD0_PVDD 110 mA SD0_PVDD=1.95V SD1_PVDD 70 mA SD1_PVDD=1.95V Power supply voltage (SPI/3.3V) SPI_PVDD 50 mA SPI_PVDD=3.63V Power supply voltage (SPI/1.8V) SPI_PVDD 100 mA SPI_PVDD=1.95V Power supply voltage (Ether/3.3V) PVDD182533_n 380 mA PVDD182533_n=3.63V when 2 channels are in use Power supply voltage (Ether/2.5V) PVDD182533_n 240 mA PVDD182533_n=2.75V when 2 channels are in use Power supply voltage (Ether/1.8V) PVDD182533_n 140 mA PVDD182533_n=1.98V when 2 channels are in use Power supply voltage (DDR/1.2V) DDR_VDDQ 220 mA DDR_VDDQ=1.26V Power supply voltage (DDR/1.35V) DDR_VDDQ 210 mA DDR_VDDQ=1.45V Power supply voltage (PLL/1.8V) PLL1_AVDD18 10 mA PLL1_AVDD18=1.98V PLL23_AVDD18 20 mA PLL23_AVDD18=1.98V PLL4_AVDD18 10 mA PLL4_AVDD18=1.98V PLL6_AVDD18 10 mA PLL6_AVDD18=1.98V Power supply voltage (PLL/1.1V) PLL23_DVDD11 20 mA PLL23_DVDD11=1.15V Note: Tj = 125°C, n = 0, 1

RZ/Five Group 3. Electrical Characteristics R01DS0488EJ0110 Rev.1.10 Page 25 of 65 Jun 30, 2025

3.5 AC Characteristics

Conditions: VDD = PLL23_DVDD11 = 1.1 ± 0.05 V, PLL1_AVDD18 = PLL23_AVDD18 = PLL4_AVDD18 = PLL6_AVDD18 = 1.8 ± 0.18 V, ADC_AVDD18 = VDD18 = 1.8 ± 0.18 V, OTP_VDD18 = 1.8 V ± 0.15 V, USB_VDD18 = 1.8 ± 0.15 V, SPI_PVDD = SDn_PVDD (n = 0, 1) = 3.3 ± 0.33 V/1.70 to 1.95 V, Ta = −40 to +85°C, Tj = −40 to +125°C

3.5.1 Clock Timing

Table 3.20 Clock Timing Table Item Symbol Min. Max. Unit Figures EXCLK clock input frequency fEX 24 – 50ppm*1 24 + 50ppm*1 MHz Figure 3.5 EXCLK clock input cycle time tEXcyc 41.67 41.67 ns AUDIO_CLK1, AUDIO_CLK2 clock input frequency (external clock is input) fEX 10 50 MHz AUDIO_CLK1, AUDIO_CLK2 clock input cycle time (external clock is input) tEXcyc 20 100 ns EXCLK, AUDIO_CLK1, AUDIO_CLK2 clock input low level pulse width tEXL 0.4 0.6 tEXcyc EXCLK, AUDIO_CLK1, AUDIO_CLK2 clock input high level pulse width tEXH 0.4 0.6 tEXcyc EXCLK, AUDIO_CLK1, AUDIO_CLK2 clock input rise time tEXr — 4 ns EXCLK, AUDIO_CLK1, AUDIO_CLK2 clock input fall time t EXf — 4 ns Oscillator stabilization time tOSC — 1 ms Figure 3.6, Figure 3.7 Mode hold time tMDH — 100 ns Mode setup time tMDS — 100 ns Note 1. When using RGMII interface. If not using RGMII mode, this spec is ±100 ppm. 1/2 PVDD EXCLK, AUDIO_CLK1, AUDIO_CLK2 (input) tEXcyc tEXH tEXL VIH VIH VIL VIL VIH 1/2 PVDD tEXf tEXr Note: When the clock is input on the EXCLK, AUDIO_CLK1 or AUDIO_CLK2 Figure 3.5 EXCLK, AUDIO_CLK1 and AUDIO_CLK2 Clock Input Timing

RZ/Five Group 3. Electrical Characteristics R01DS0488EJ0110 Rev.1.10 Page 27 of 65 Jun 30, 2025

3.5.2 SDHI Access Timing

3.5.2.1 SDHI Access Timing (SDR 3.3-V) Table 3.21 SDHC AC Access Timing (SDR at 3.3-V Operation) Default Speed Mode (16.67 MHz) High Speed Mode (33.33 MHz) Item Symbol Min. Max. Min. Max. Unit Figures SD_CLK clock cycle tSDCYC 60.00 — 30.0 — ns Figure 3.8 SD_CLK clock high level width tSDWH 23.50 — 13.50 — ns SD_CLK clock low level width tSDWL 23.50 — 13.50 — ns SD_CLK clock rise time tSDLH — 10 — 3 ns SD_CLK clock fall time tSDHL — 10 — 3 ns SD_CMD,SD_DATA output delay tSDODLY −4.50 4.0 −4.50 4.0 ns SD_CMD,SD_DATA input set up time tSDIS 5.5 — 5.5 — ns SD_CMD,SD_DATA input hold time tSDIH 2.0 — 2.0 — ns SD_CMD,SD_DATA input data width tSDIDW — — — — ns SD_CLK (output) SD_CMD/SD_DATA (input) tSDCYC tSDWL tSDWH tSDLHtSDHL tSDIS tSDIH tSDIDW tSDODLY (max) tSDODLY (min) SD_CMD/SD_DATA (output) Figure 3.8 SDHC Interface Timing (SDR 3.3-V Power Supply) NOTE The disclosure of other characteristics of the SD interface needs the conclusion of the following agreement.

  • SD Host/Ancillary Product License Agreement (SD HALA) For details, contact your local sales representatives.

RZ/Five Group 3. Electrical Characteristics R01DS0488EJ0110 Rev.1.10 Page 28 of 65 Jun 30, 2025 3.5.3 eMMC Access Timing 3.5.3.1 eMMC Host Interface Timing (Default) Table 3.22 eMMC Host Interface Timing (MMC Default 3.3-V Power Supply) Item Symbol Min. Max. Unit Figures SD0_CLK clock cycle tMMCPP 40.00 — ns Figure 3.9 SD0_CLK clock high level width tMMCWH 18.50 — ns SD0_CLK clock low level width tMMCWL 18.50 — ns SD0_CLK clock rise time tMMCLH — 3 ns SD0_CLK clock fall time tMMCHL — 3 ns SD0_CMD/SDDAT output delay tMMCODLY −4.50 4.0 ns SD0_CMD/SDDAT input set up time tMMCISU 5.5 — ns SD0_CMD/SDDAT input hold time tMMCIH 2.0 — ns SD0_CMD/SDDAT input data width tMMCIDW — — ns Table 3.23 eMMC Host Interface Timing (MMC Default 1.8-V Power Supply) Item Symbol Min. Max. Unit Figures SD0_CLK clock cycle tMMCPP 40.00 — ns Figure 3.9 SD0_CLK clock high level width tMMCWH 19.25 — ns SD0_CLK clock low level width tMMCWL 19.25 — ns SD0_CLK clock rise time tMMCLH — 2.45 ns SD0_CLK clock fall time tMMCHL — 2.45 ns SD0_CMD/SDDAT output delay tMMCODLY −2.00 2.50 ns SD0_CMD/SDDAT input set up time tMMCISU 4.00 — ns SD0_CMD/SDDAT input hold time tMMCIH 1.40 — ns SD0_CMD/SDDAT input data width tMMCIDW — — ns

RZ/Five Group 3. Electrical Characteristics R01DS0488EJ0110 Rev.1.10 Page 29 of 65 Jun 30, 2025 3.5.3.2 eMMC host interface timing (HS-SDR) Table 3.24 eMMC Host Interface Timing (MMC HS-SDR 3.3-V Power Supply) Item Symbol Min. Max. Unit Figures SD0_CLK clock cycle tMMCPP 30.00 — ns Figure 3.9 SD0_CLK clock high level width tMMCWH 13.50 — ns SD0_CLK clock low level width tMMCWL 13.50 — ns SD0_CLK clock rise time tMMCLH — 3 ns SD0_CLK clock fall time tMMCHL — 3 ns SD0_CMD/SDDAT output delay tMMCODLY −4.50 4.0 ns SD0_CMD/SDDAT input set up time tMMCISU 5.5 — ns SD0_CMD/SDDAT input hold time tMMCIH 2.0 — ns SD0_CMD/SDDAT input data width tMMCIDW — — ns Table 3.25 eMMC Host Interface Timing (MMC HS-SDR 1.8-V Power Supply) Item Symbol Min. Max. Unit Figures SD0_CLK clock cycle tMMCPP 20.00 — ns Figure 3.9 SD0_CLK clock high level width tMMCWH 9.25 — ns SD0_CLK clock low level width tMMCWL 9.25 — ns SD0_CLK clock rise time tMMCLH — 2.45 ns SD0_CLK clock fall time tMMCHL — 2.45 ns SD0_CMD/SDDAT output delay tMMCODLY −2.00 2.50 ns SD0_CMD/SDDAT input set up time tMMCISU 4.00 — ns SD0_CMD/SDDAT input hold time tMMCIH 1.40 — ns SD0_CMD/SDDAT input data width tMMCIDW — — ns tMMCPP tMMCWL tMMCWH tMMCLHtMMCHL tMMCISU tMMCIH tMMCODLY (max) tMMCODLY (min) SD_CLK (output) SD_CMD, SD_D7 to SD_D0 (input) SD_CMD, SD_D7 to SD_D0 (output) Figure 3.9 eMMC Host Interface Timing (MMC Default/HS-SDR 1.8-V/3.3-V Power Supply)

RZ/Five Group 3. Electrical Characteristics R01DS0488EJ0110 Rev.1.10 Page 30 of 65 Jun 30, 2025 3.5.3.3 eMMC host interface timing (HS200) Table 3.26 eMMC Host Interface Timing (HS200 1.8-V Power Supply Operation, Output Load 15 pF) Item Symbol Min. Max. Unit Figures SD0_CLK clock cycle tMMCPP 7.50 15.0 ns Figure 3.10 SD0_CLK clock high level width tMMCWH 3.20 — ns SD0_CLK clock low level width tMMCWL 3.20 — ns SD0_CLK clock rise time tMMCLH — 1.22 ns SD0_CLK clock fall time tMMCHL — 1.22 ns SD0_CMD/SDDAT output delay tMMCODLY −1.50 1.75 ns SD0_CMD/SDDAT input set up time tMMCISU — — ns SD0_CMD/SDDAT input hold time tMMCIH — — ns SD0_CMD/SDDAT input data width tMMCIDW 4.31 — ns tMMCPP tMMCWL tMMCWH tMMCLHtMMCHL tMMCISU tMMCIH tMMCIDW tMMCODLY (max) tMMCODLY (min) SD_CLK (output) SD_CMD, SD_D7 to SD_D0 (input) SD_CMD, SD_D7 to SD_D0 (output) Figure 3.10 eMMC Host Interface (MMC Interface HS200 Mode 1.8-V Power Supply Selection)

RZ/Five Group 3. Electrical Characteristics R01DS0488EJ0110 Rev.1.10 Page 34 of 65 Jun 30, 2025

3.5.5 Ethernet Interface Access Timing

Table 3.30 Ethernet Interface Access Timing Item Symbol Min. Max. Unit Figures MDC half cycle tMDC 0 300 ns Figure 3.17 MDI setup time tMDIsetup 10 — ns MDI hold time tMDIhold 10 — ns ETn_MDC ETn_MDIO tMDC 0 ns (Min) to 300 ns (Max). Setting value of CYC_OCLK bit in MDIOMOD register ETn_MDC ETn_MDIO tMDIsetup 10 ns (Min) tMDIhold 10 ns (Min) Note: (n = 0, 1) Figure 3.17 Management Interface

RZ/Five Group 3. Electrical Characteristics R01DS0488EJ0110 Rev.1.10 Page 35 of 65 Jun 30, 2025

3.5.5.1 Ethernet-IF (Ether MII)

Table 3.31 Ethernet-IF Access Timing (Ether MII) Item Symbol Min. Max. Unit Figures Ether MII ETH_GTXTXC_TXC period tTcyc 40 — ns Figure 3.18 ETH_TXCTL output delay tTENd 0 25 ns ETH_TXD3-0 output delay tMTDd 0 25 ns ETH_RXC period tRcyc 40 — ns ETH_RXDV setup time tRDVs 10 — ns ETH_RXDV hold time tRDVh 10 — ns ETH_RXD3-0 setup time tMRDs 10 — ns ETH_RXD3-0 hold time tMRDh 10 — ns ETH_RXER setup time tRERs 10 — ns ETH_RXER hold time tRERh 10 — ns Note: I/O driving ability: 8 mA CL = 8 pF ETn_TXD[3:0] ETn_TX_ERR ETn_TX_CTL/TX_EN ETn_TXC/TX_CLK (external clock) Preamble SFD Data CRC tTENd tMTDd ETn_RXD[3:0] ETn_RX_CTL/RX_DV ETn_RXC/RX_CLK (external clock) Preamble SFD Data tRDVs CRC tMRDs tRDVh ETn_RX_ERR tRERs tMRDh tRERh Figure 3.18 MII Transmission Timing Validated with IEEE802.3 regulation. The propagation delay for each twisted pair, measured from the MII connector to the PHY, shall not exceed 2.5 ns. The variation in the propagation delay of the twisted pairs in a given cable bundle, measured from the MII connector to the PHY, shall not exceed 0.1 ns.

RZ/Five Group 3. Electrical Characteristics R01DS0488EJ0110 Rev.1.10 Page 36 of 65 Jun 30, 2025

3.5.5.2 Ethernet-IF (Ether RGMII)

Table 3.32 Ethernet-IF Access Timing (Ether RGMII) Item Symbol Min. Typ. Max. Unit capaci- tance Remarks Figures Ether RGMII Data to clock output skew @ transmitter T skewT −500 0 500 ps 8 pF Tx RGMII Figure 3.19 Data to clock input skew @ receiver T skewR 1 1.8 2.6 ns 8 pF Data to clock output setup @ transmitter integrated delay TsetupT 1.2 2.0 — ns 8 pF Rx RGMII-ID Figure 3.20 Clock to data output hold @ transmitter integrated delay TholdT 1.2 2.0 — ns 8 pF Data to clock input setup setup @ receiver integrated delay T setupR 1.0 2.0 — ns 8 pF Rx RGMII-ID Figure 3.20 Data to clock input setup hold @ receiver integrated delay TholdR 1.0 2.0 — ns 8 pF Clock cycle duration*1 Tcyc 7.2 8 8.8 ns 8 pF — — Duty cycle for gigabit Duty_G 45 50 55 % 8 pF Duty cycle for 10/100T Duty_T 40 50 60 % 8 pF Rise/fall time (20-80%) Tr/Tf — — 0.75 ns 8 pF Note 1. For 10 Mbps and 100 Mbps, Tcyc will scale to 400ns ±40ns and 40ns ±4ns respectively.

RZ/Five Group 3. Electrical Characteristics R01DS0488EJ0110 Rev.1.10 Page 38 of 65 Jun 30, 2025

3.5.6 JTAG Debugger Interface Access Timing

Table 3.33 Debugger IF Timing Item Symbol Min. Max. Unit Figures TCK_SWCLK cycle time tTCKcyc 50 — ns Figure 3.21 TCK_SWCLK high pulse width tTCKH 20 — ns Figure 3.22 TCK_SWCLK low pulse width tTCKL 20 — ns TDI setup time tTDIS 15 — ns TDI hold time tTDIH 15 — ns TMS_SWDIO setup time tTMSS 15 — ns TMS_SWDIO hold time tTMSH 15 — ns SWDIO delay time tSWDO — 14 ns TDO delay time tTDOD — 14 ns Capture register setup time tCAPTS 10 — ns Figure 3.23 Capture register hold time tCAPTH 10 — ns Update register delay time tUPDATED — 20 ns 1/2 JTAG_PVDD tTCKcyc tTCKH tTCKL VIH VIH VIL VIL VIH 1/2 JTAG_PVDD Figure 3.21 TCK_SWDCLK Input Timing

RZ/Five Group 3. Electrical Characteristics R01DS0488EJ0110 Rev.1.10 Page 40 of 65 Jun 30, 2025

3.5.7 SPI Multi I/O Bus Controller Access Timing

Table 3.34 SPI Multi I/O Bus Contoller Access Timing 1.8 V 3.3 V (Serial flash connected) (Serial flash connected) Item Symbol Min. Max. Min. Max. Unit Figures Clock cycle tSPBcyc 15.0 — 15.0 — ns Figure 3.24 CLK rise time tSPBR — 1.0 — 3.2 ns Figure 3.24 CLK fall time tSPBF — 1.0 — 3.2 ns Figure 3.24 Data input setup time QSPI0_SPCLK base point (SDR mode timing adjusted) t SU 6.7 — 7.5 — ns Figure 3.25 QSPI0_SPCLK base point (DDR mode timing adjusted) 4.5 — 4.5 — ns Figure 3.26 Data input hold time QSPI0_SPCLK base point (SDR mode timing adjusted) t H 0.5 — 0.5 — ns Figure 3.25 QSPI0_SPCLK base point (DDR mode timing adjusted) 1.0 — 1.0 — ns Figure 3.26 SSL setup time tLEAD 1.5 × tSPBcyc − 3 8.5 × tSPBcyc + 3 1.5 × tSPBcyc − 3 8.5 × tSPBcyc + 3 ns Figure 3.25, Figure 3.26 SSL hold time tLAG 1 × tSPBcyc − 3 8 × tSPBcyc + 3 1 × tSPBcyc − 3 8 × tSPBcyc + 3 ns Figure 3.25, Figure 3.26 Continuous transfer delay time tTD 1 × tSPBcyc − 3 8 × tSPBcyc + 3 1 × tSPBcyc − 3 8 × tSPBcyc + 3 ns Figure 3.25, Figure 3.26 Data output delay time SDR t OD ― 2.0 ― 5.0 ns Figure 3.25 DDR ― 6.5*2 ― 7.5*3 ns Figure 3.26 Data output hold time SDR t OH −2.0 ― -5.0 ― ns Figure 3.25 DDR 1.0*2 ― 2.1*3 ― ns Figure 3.26 Data output buffer off time SDR t BOFF ― 2.0 ― 3.0 ns Figure 3.27 DDR ― 2.0 ― 3.0 ns Figure 3.27 Note 1. Output load: 15 pF/driving ability: 12 mA Note 2. QSPI0_SPCLK frequency: 100 MHz. Note 3. QSPI0_SPCLK frequency: 66 MHz

RZ/Five Group 3. Electrical Characteristics R01DS0488EJ0110 Rev.1.10 Page 43 of 65 Jun 30, 2025

3.5.8 Control Signal Access Timing

Table 3.35 Control Signal Timing Item Symbol Min. Max. Unit Figures PRST# pulse width tRESW 20 — tcyc*1 Figure 3.28 TRST# pulse width tTRSW 20 — tcyc*1 NMI pulse width tNMIW 20 — tcyc*1 Figure 3.30 IRQ pulse width tIRQW 20 — tcyc*1 TINT pulse width tTINTW 20 — tcyc*1 PRST# input rise time tRSr — 500 μs Figure 3.29 Note 1. tcyc = 41.666 ns (24 MHz) PRST# TRST# tRESW / tTRSW Figure 3.28 Reset Input Timing 1 PRST# TRST# tRSr Figure 3.29 Reset Input Timing 2

RZ/Five Group 3. Electrical Characteristics R01DS0488EJ0110 Rev.1.10 Page 44 of 65 Jun 30, 2025 NMI tNMIW IRQ tIRQW TINT tTINTW Note: This specification “(Min. 20 tcycle)” is the min. pulse width the case that the digital noise filter is off. For details on digital noise filter settings, refer to Section 41, General Purpose Input Output Port (GPIO), in the User's Manual: Hardware. Figure 3.30 Interrupt Signal Input Timing

RZ/Five Group 3. Electrical Characteristics R01DS0488EJ0110 Rev.1.10 Page 45 of 65 Jun 30, 2025

3.5.9 Serial Sound Interface (SSIF-2) Access Timing

Table 3.36 SSIF-2 Timing Item I/O Symbol Min. Max. Unit Figures Output clock cycle Output tO 80 64000 ns Figure 3.31 Input clock cycle Input tI 80 — ns Clock high Bidirectional tHC 32 — ns Clock low tLC 32 — ns Clock rise time/clock fall time Output tRC/tFC — 25 ns Setup time Input tSR 25 — ns Figure 3.32, Figure 3.33, Figure 3.34 Hold time tHR 5 — ns SILRCK output delay time Output tDTR −5 25 ns Data output delay time (Noise canceler not in use) tDTR −5 25 ns Data output delay time (Noise canceler in use) tDTR 10 50 ns Note: AC access timing condition: drive ability 12mA, output load 30pF, slew rate = fast SSIn_BCK tHC tLC tRC tFC tO, tI Figure 3.31 Bit Clock Input/Output Timing SSIn_RCK (input), SSIn_RXD, SSI2_DATA (input) SSIn_BCK SSIn_RCK (output), SSIn_TXD, SSI2_DATA (output) tHRtSR tDTR Figure 3.32 Transmission and Reception Timing (SSIBCK Falling Output)

RZ/Five Group 3. Electrical Characteristics R01DS0488EJ0110 Rev.1.10 Page 47 of 65 Jun 30, 2025

3.5.10 CAN-FD Interface Access Timing

Table 3.37 CAN-FD Interface Timing CAN CAN-FD Item Symbol Min. Max. Min. Max. Unit Figures Internal delay time tnode*1 — 100 — 75 ns Figure 3.35 Transmission rate — — 1 — 4 Mbps Note: AC access timing condition: drive ability 12mA, output load 15pF, slew rate = fast Note 1. Internal delay time (tnode) = Internal transfer delay time (toutput) + Internal receive delay time (tinput) CANFD interface Internal transfer delay time (toutput) Internal receive delay time (tinput) CAN1_TX, CAN0_TX pins CAN1_RX, CAN0_RX pins Figure 3.35 CAN-FD Interface Condition

RZ/Five Group 3. Electrical Characteristics R01DS0488EJ0110 Rev.1.10 Page 48 of 65 Jun 30, 2025

3.5.11 Multi-Function Timer Pulse Unit 3 (MTU3a) Access Timing

Table 3.38 MTU3a Timing Item Symbol Min. Max. Unit*1 Figures MTU3a Input capture input pulse width Single-edge setting tMTICW 1.5 — tp1cyc*1 Figure 3.36 Both-edge setting 2.5 — Timer clock pulse width Single-edge setting tMTCKWH, tMTCKWL 1.5 — tp1cyc*1 Figure 3.37 Both-edge setting 2.5 — Phase counting mode 2.5 — Note: AC access timing condition: drive ability 4mA, output load 30pF, slew rate = fast Note 1. tp1cyc indicates peripheral clock means MTU_X_MCLK_MTU3 (P0ϕ). Input capture Input tMTICW Figure 3.36 MTU3a Input Capture Input Timing MTCLKA to MTCLKD tMTCKWL tMTCKWH Figure 3.37 MTU3a Clock Input Timing

RZ/Five Group 3. Electrical Characteristics R01DS0488EJ0110 Rev.1.10 Page 49 of 65 Jun 30, 2025

3.5.12 Port Output Enable 3 (POE3) Access Timing

Table 3.39 POE3 Timing Item Symbol Min. Max. Unit Figures POE3 POEn# input pulse width tPOE3W 1.5 — tp1cy*1 Figure 3.38 Note 1. tp1cyc indicates peripheral clock means POE3_CLKM_POE (P0ϕ). POEn# input tPOE3W Figure 3.38 POEn# Input Pulse Timing

RZ/Five Group 3. Electrical Characteristics R01DS0488EJ0110 Rev.1.10 Page 50 of 65 Jun 30, 2025

3.5.13 I2C Bus Interface Access Timing

Table 3.40 I2C Bus Interface Timing Standard Mode (Sm) Fast Mode (Fm) Fast Mode Plus (Fm+) SCL clock frequency fCLK I/O 0 100 0 400 0 1000 kHz Bus free time (between stop and start condition) tBUF I/O 4.7 — 1.3 — 0.5 — μs Hold time*1 tHD:STA I/O 4.0 — 0.6 — 0.26 — μs Low period of SCL clock tLOW I/O 4.7 — 1.3 — 0.5 — μs High period of SCL clock tHIGH I/O 4.0 — 0.6 — 0.26 — μs Setup time for start / restart condition tSU:STA I/O 4.7 — 0.6 — 0.26 — μs Data hold time (I2C bus device) tHD:DAT I/O 0*2 — 0*2 — 0 — μs Data setup time tSU:DAT I/O 250 — 100*3 — 50 — ns SDA and SCL signal rise time t R Input — 1000 20 300 — 120 ns SDA and SCL signal fall time* tF Input — 300 20 × (PVDD/ 5.5 V) 300 20 × (PVDD/ 5.5 V) 120 ns Output — 300 20 × (PVDD/

5.5 V)*6

300*6 20 × (PVDD/

5.5 V)*7

120*7 ns Setup time for STOP condition t SU:STO I/O 4.0 — 0.6 — 0.26 — μs Capacitive load for each bus line C Pulse width of spikes that must be suppressed by the input filter t SP Input — — 0 50*5 0 50*5 ns Note: In the above table and subsequently, SCL and SDA refer to the RIICnSCL and RIICnSDA signals, respectively. Note: AC access timing condition: drive ability 4mA, output load 400pF, slew rate = slow Note 1. The first clock pulse is generated on the SCL line after the start condition has been issued and the hold time has elapsed. Note 2. This module requires a minimum of 300 ns hold time internally for the SDA signal to handle the period over which the falling edge of SCL has not reached a defined level (time until the CnSCL signal reaches VIL (max.) from VIH (min.)). Note 3. The fast-mode I2C bus device can be used in the standard mode I2C bus system. In this case, the minimum value of the data setup time (tSU: DAT (min.) 250 [ns]) must be satisfied. If the system does not extend the low period of SCL clock (tLOW), this condition is automatically satisfied. If the system extends the low period of SCL clock (tLOW), transmit the subsequent data bit to the SDA line before the SCL line is released (tR (max.) + tSU: DAT (min.) = 1000 + 250 = 1250 [ns]: (standard mode I2C bus specification)). Note 4. Total capacitance of one bus line. The allowable maximum bus capacitance may differ from this specification, depending on the actual operating voltage and frequency of an application. For techniques to cope with a large bus capacitance, see the I2C bus specification provided by NXP Semiconductors. Note 5. Noise is removed by the analog and digital input filters. The level of noise reduction of the digital input filter is determined by the period of internal reference clock (IICϕ) and the NF[1:0] bits in RIICnMR3. For details, refer to Section 26, I²C Bus Interface, in the User's Manual: Hardware. Note 6. External pull-up resistor is required 1077Ω to 1770Ω when using RIIC ch2 or RIIC ch3. Note 7. External pull-up resistor is required 240Ω to 257Ω when using RIIC ch2 or RIIC ch3.

RZ/Five Group 3. Electrical Characteristics R01DS0488EJ0110 Rev.1.10 Page 51 of 65 Jun 30, 2025 SCL SDA tLOW tR tHIGH tF tHD:STA tHD:DAT tSU:DAT tBUF P S tSPtHD:STAtSU:STA tSU:STO PSr Note: P: Stop condition S: Start condition Sr: Start condition for retransmission Figure 3.39 Input/Output Timing

RZ/Five Group 3. Electrical Characteristics R01DS0488EJ0110 Rev.1.10 Page 52 of 65 Jun 30, 2025

3.5.14 Serial Communications Interface with FIFO (SCIFA) Access Timing

Table 3.41 SCIFA Timing Item Symbol Min. Max. Unit Figures SCIFA Input clock cycle Asynchronous tScyc 4 — tp1cyc*1 Figure 3.40 Clocked synchronous 12 — Input clock pulse width tSCKW 0.4 0.6 tp1cyc*1 Input clock rise time tSCKr — 5 ns Input clock fall time tSCKf — 5 ns Output clock cycle Asynchronous*2 tScyc 8 — tp1cyc*1 Clocked synchronous 4 — Output clock pulse width tSCKW 0.4 0.6 tp1cyc*1 Output clock rise time tSCKr — 9 ns Output clock fall time tSCKf — 9 ns Transmit data delay time Internal clock tTXD −10 10 ns Figure 3.41 External clock 3 × tp1cyc*1 4 × tp1cyc*1 + 20 Receive data setup time Internal clock tRXS 3 × tp1cyc*1 + 20 — ns External clock tp1cyc*1 + Receive data hold time Internal clock tRXH −3 × tp1cyc*1 — ns External clock 2 × tp1cyc*1 + 10 Note: AC access timing condition: drive ability 12mA, output load 30pF, slew rate = fast Note 1. tp1cyc indicates peripheral clock means SCIFn_CLK_PCK (P0ϕ) (n = 0 to 4). Note 2. When the SEMR.ABCS0 and SEMR.BGDM bits are set to 1. SCIFn_SCK (n = 0 to 4) tSCKW tScyc tSCKr tSCKf Figure 3.40 SCK Input Clock Timing

RZ/Five Group 3. Electrical Characteristics R01DS0488EJ0110 Rev.1.10 Page 53 of 65 Jun 30, 2025 SCIFn_SCK SCIFn_TXD SCIFn_RXD tRXS tRXH tTXD Note: n = 0 to 4 Figure 3.41 SCIFA Input/Output Timing in Clocked Synchronous Mode

RZ/Five Group 3. Electrical Characteristics R01DS0488EJ0110 Rev.1.10 Page 54 of 65 Jun 30, 2025

3.5.15 Serial Communications Interface (SCIg) Access Timing

Table 3.42 SCIg Timing Item Symbol Min. Max. Unit Figures SCIg Input clock cycle Asynchronous tScyc 4 — tp1cyc*1 Figure 3.42 Clocked synchronous 6 — Input clock pulse width tSCKW 0.4 0.6 tp1cyc*1 Input clock rise time tSCKr — 5 ns Input clock fall time tSCKf — 5 ns Output clock cycle Asynchronous*2 tScyc 8 — tp1cyc*1 Clocked synchronous 4 — Output clock pulse width tSCKW 0.4 0.6 tp1cyc*1 Output clock rise time tSCKr — 5 ns Output clock fall time tSCKf — 5 ns Transmit data delay time Clocked synchronous t TXD — 28 ns Figure 3.43 Receive data setup time Clocked synchronous t RXS 15 — ns Receive data hold time Clocked synchronous tRXH 5 — ns Note: AC access timing condition: drive ability 12mA, output load 30pF, slew rate = fast Note 1. tp1cyc indicates peripheral clock means SCIn_CLKP (P0ϕ) (n = 0 to 1). Note 2. When the SEMR.ABCS0 and SEMR.BGDM bits are set to 1. SCIn_SCK (n = 0, 1) tSCKW tScyc tSCKr tSCKf Figure 3.42 SCK Input Clock Timing

RZ/Five Group 3. Electrical Characteristics R01DS0488EJ0110 Rev.1.10 Page 55 of 65 Jun 30, 2025 SCIn_SCK SCIn_TXD SCIn_RXD tRXS tRXH tTXD Note: n = 0, 1 Figure 3.43 SCIFA Input/Output Timing in Clocked Synchronous Mode

RZ/Five Group 3. Electrical Characteristics R01DS0488EJ0110 Rev.1.10 Page 56 of 65 Jun 30, 2025

3.5.16 Renesas Serial Peripheral Interface (RSPI) Access Timing

Table 3.43 Renesas Serial Peripheral Interface Timing Item Symbol Min. Max. Unit Figure RSPCK clock cycle Master tSPcyc 2 4096 tp1cyc*1 Figure 3.44 Slave 8 4096 RSPCK clock high pulse width Master tSPCKWH 0.4 — tSPcyc*1 Slave 0.4 — RSPCK clock low pulse width Master tSPCKWL 0.4 — tSPcyc*1 Slave 0.4 — Data input setup time Master tSU 10 — ns Figure 3.45 to Figure 3.48 Slave 0 — tp1cyc*1 Data input hold time Master tH 0 — ns Slave 4 — tp1cyc*1 SSL setup time Master tLEAD 1 × tSPcyc − 20 8 × tSPcyc ns Slave 4 — tp1cyc*1 SSL hold time Master tLAG 1 × tSPcyc 8 × tSPcyc + 20 ns Slave 4 — tp1cyc*1 Data output delay time Master tOD — 19 ns Slave — 4 tp1cyc*1 Data output hold time Master tOH 5 — ns Slave 2 — tp1cyc*1 Continuous transmission delay time Master tTD 1 × tSPcyc + 2 × tcyc 8 × tSPcyc + 2 × tcyc ns Slave 4 × tcyc — Slave access time tSA — 4 tp1cyc*1 Figure 3.47, Figure 3.48 Slave out release time tREL — 3 tp1cyc*1 Note: AC access timing condition: drive ability 12mA, output load 30pF, slew rate = fast Note 1. tp1cyc indicates peripheral clock means RSPIn_CLKB (P0ϕ) (0 to 2). RSPIn_CK slave select input tSPCKWH RSPIn_CK master select output tSPCKWL tSPcyc VIL VIH VIH VIL tSPCKWH tSPCKWL tSPcyc VOL VOH VOH VOL Note: n = 0 to 2 Figure 3.44 Clock Timing

RZ/Five Group 3. Electrical Characteristics R01DS0488EJ0110 Rev.1.10 Page 59 of 65 Jun 30, 2025

3.5.17 A/D Converter Access Timing

Table 3.44 A/D Converter Timing Item Symbol Min. Max. Unit Figures ADC Trigger Input Pulse Width tTRGW 1.5*2 tP1cyc*1 Figure 3.49 Note 1. tp1cyc indicates peripheral clock means ADC_ADCLK (TSUϕ). Note 2. When a noise filter in ADC is off. ADC_TRG tTRGW Figure 3.49 ADC Trigger Input Timing

3.5.18 Watchdog Timer Access Timing

Table 3.45 Watchdog Timer Timing Item Symbol Min. Max. Unit Figures WDTOVF_PERROUT# Output Time tL 64 64 tP1cyc*1 Figure 3.50 Note 1. tP1cyc indicates peripheral clock means WDTn_CLK (OSCCLK) (n = 0, 2). WDTOVF_PERROUT# tL Figure 3.50 Watchdog Timer Output Timing

RZ/Five Group 4. Package Dimensions R01DS0488EJ0110 Rev.1.10 Page 60 of 65 Jun 30, 2025 4. Package Dimensions Figure 4.1 Package Dimen sions for LFBGA 13 mm/0.5 mm pitch/361 pin 1 35 79 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 21 23 25 22 24 A C E G J L N R U W B D F H K M P T V Y AA AB AC AD AE Max. D 13.00 E 13.00 D1 12.00 E1 12.00 A 1.40 A1 0.11 b 0.20 0.25 0.30 e 0.50 aaa 0.15 ccc 0.20 ddd 0.08 eee 0.15 fff 0.08 n 361 0.40 E D A aaa C ccc C A ddd C e φeee C A B φfff C nXφ b B C P-LFBGA361-13x13-0.50 RENESAS code PLBG0361KB-A MASS(TYP.)[g] INDEX AREA Reference Symbol Dimension in Millimeters Min. Nom.

RZ/Five Group 4. Package Dimensions R01DS0488EJ0110 Rev.1.10 Page 61 of 65 Jun 30, 2025 Figure 4.2 Package Dimen sions for LFBGA 11 mm/0.5 mm pitch/266 pin C ddd C ccc C Φ eee C A B Φ fff C nx φ b e B E A D A aaa C Max. D 11.00 E 11.00 D1 10.00 E1 10.00 A 1.40 A1 0.11 b 0 . 2 00 . 2 50 . 3 0 e 0.50 aaa 0.15 ccc 0.20 ddd 0.08 eee 0.15 fff 0.08 n 266 0.29 P-LFBGA266-11x11-0.50 RENESAS code PLBG0266KA-A MASS(TYP.)[g] INDEX AREA Reference Symbol Dimension in Millimeters Min. Nom.

RZ/Five Group REVISION HISTORY R01DS0488EJ0110 Rev.1.10 Page 62 of 65 Jun 30, 2025 REVISION HISTORY RZ/Five Group DATASHEET

REVISION HISTORY

Description

Rev. Date Page Summary

1.00 Dec 25, 2024  First edition issued

1.10 Jun 30, 2025 1. Overview 11 Figure 1.1 Configuration of LSI Internal Bus Text, modified (MPU Bus → MCPU Bus) SRC, deleted 3. Electrical Characteristics 18 Table 3.3 DC Characteristics (1) [3.3-V I/O] Input leakage current, added 19 Table 3.7 DC Characteristics (5) [RGMII/MII] Input logic low (Remarks: 1.8-V RGMII/MII): The Min value, modified 20 Table 3.9 DC Characteristics (7) [1.8 V I/O (SD, QSPI)] Output logic high voltage: The Min value, modified Output logic low voltage: The Max value, modified 22 Table 3.18 DC Characteristics (16) [ADC] Full-scale error, Offset error, Analog input capacitance, Analog input resistance, External capacitance, and External resistance, added Note 1, added 23 Figure 3.4 Analog Input Equivalent Circuit, added 27 Table 3.21 SDHC AC Access Timing (SDR at 3.3-V Operation) SD_CLK clock high level width, SD_CLK clock low level width, SD_CMD,SD_DATA output delay: The Min values, modified 28 Table 3.22 eMMC Host Interface Timing (MMC Default 3.3-V Power Supply) SD0_CLK clock cycle, SD0_CLK clock high level width, SD0_CLK clock low level width, SD0_CMD/SDDAT output delay: The Min values, modified 28 Table 3.23 eMMC Host Interface Timing (MMC Default 1.8-V Power Supply) SD0_CLK clock cycle, SD0_CLK clock high level width, SD0_CLK clock low level width: The Min values, modified SD0_CMD/SDDAT output delay: The Min and Max values, modified 29 3.5.3.2 eMMC host interface timing (HS-SDR), modified 30 Table 3.26 eMMC Host Interface Timing (HS200 1.8-V Power Supply Operation, Output Load 15 pF) SD0_CLK clock high level width, SD0_CLK clock low level width: The Min values, modified SD0_CMD/SDDAT output delay: The Min and Max values, modified 36 Table 3.32 Ethernet-IF Access Timing (Ether RGMII) Duty cycle for gigabit: The Min and Max values, modified Note, modified

General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1. Precaution against Electrostatic Discharge (ESD) A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices. 2. Processing at power-on The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the level at which resetting is specified. 3. Input of signal during power-off state Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Follow the guideline for input signal during power-off state as described in your product documentation. 4. Handling of unused pins Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. 5. Clock signals After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable. 6. Voltage application waveform at input pin Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.). 7. Prohibition of access to reserved addresses Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these addresses as the correct operation of the LSI is not guaranteed. 8. Differences between products Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system- evaluation test for the given product.

© 2025 Renesas Electronics Corporation. All rights reserved. Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by you or third parties arising from the use of these circuits, software, or information. 2. Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims involving patents, copyrights, or other intellectual property rights of third parties, by or arising from the use of Renesas Electronics products or technical information described in this document, including but not limited to, the product data, drawings, charts, programs, algorithms, and application examples. 3. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. 4. You shall be responsible for determining what licenses are required from any third parties, and obtaining such licenses for the lawful import, export, manufacture, sales, utilization, distribution or other disposal of any products incorporating Renesas Electronics products, if required. 5. You shall not alter, modify, copy, or reverse engineer any Renesas Electronics product, whether in whole or in part. Renesas Electronics disclaims any and all liability for any losses or damages incurred by you or third parties arising from such alteration, modification, copying or reverse engineering. 6. Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The intended applications for each Renesas Electronics product depends on the product’s quality grade, as indicated below. "Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; industrial robots; etc. "High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication equipment; key financial terminal systems; safety control equipment; etc. Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are not intended or authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems; surgical implantations; etc.), or may cause serious property damage (space system; undersea repeaters; nuclear power control systems; aircraft control systems; key plant systems; military equipment; etc.). Renesas Electronics disclaims any and all liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or other Renesas Electronics document. 7. No semiconductor product is absolutely secure. Notwithstanding any security measures or features that may be implemented in Renesas Electronics hardware or software products, Renesas Electronics shall have absolutely no liability arising out of any vulnerability or security breach, including but not limited to any unauthorized access to or use of a Renesas Electronics product or a system that uses a Renesas Electronics product. RENESAS ELECTRONICS DOES NOT WARRANT OR GUARANTEE THAT RENESAS ELECTRONICS PRODUCTS, OR ANY SYSTEMS CREATED USING RENESAS ELECTRONICS PRODUCTS WILL BE INVULNERABLE OR FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (“Vulnerability Issues”). RENESAS ELECTRONICS DISCLAIMS ANY AND ALL RESPONSIBILITY OR LIABILITY ARISING FROM OR RELATED TO ANY VULNERABILITY ISSUES. FURTHERMORE, TO THE EXTENT PERMITTED BY APPLICABLE LAW, RENESAS ELECTRONICS DISCLAIMS ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, WITH RESPECT TO THIS DOCUMENT AND ANY RELATED OR ACCOMPANYING SOFTWARE OR HARDWARE, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE. 8. When using Renesas Electronics products, refer to the latest product information (data sheets, user’s manuals, application notes, “General Notes for Handling and Using Semiconductor Devices” in the reliability handbook, etc.), and ensure that usage conditions are within the ranges specified by Renesas Electronics with respect to maximum ratings, operating power supply voltage range, heat dissipation characteristics, installation, etc. Renesas Electronics disclaims any and all liability for any malfunctions, failure or accident arising out of the use of Renesas Electronics products outside of such specified ranges. 9. Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics products, semiconductor products have specific characteristics, such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Unless designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are not subject to radiation resistance design. You are responsible for implementing safety measures to guard against the possibility of bodily injury, injury or damage caused by fire, and/or danger to the public in the event of a failure or malfunction of Renesas Electronics products, such as safety design for hardware and software, including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult and impractical, you are responsible for evaluating the safety of the final products or systems manufactured by you. 10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. You are responsible for carefully and sufficiently investigating applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive, and using Renesas Electronics products in compliance with all these applicable laws and regulations. Renesas Electronics disclaims any and all liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. Renesas Electronics products and technologies shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. You shall comply with any applicable export control laws and regulations promulgated and administered by the governments of any countries asserting jurisdiction over the parties or transactions. 12. It is the responsibility of the buyer or distributor of Renesas Electronics products, or any other party who distributes, disposes of, or otherwise sells or transfers the product to a third party, to notify such third party in advance of the contents and conditions set forth in this document. 13. This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics. 14. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products. (Note1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its directly or indirectly controlled subsidiaries. (Note2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics. (Rev.5.0-1 October 2020) Corporate Headquarters Contact information TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners.

© 2025 Renesas Electronics Corporation. All rights reserved. Trademarks (continued) AndesCore™ AX45MP is a trademark owned by Andes Technology Corporation. AMBA®: AMBA is a registered trademark of Arm Limited. CoreLink™: CoreLink is a trademark of Arm Limited. TrustZone®: TrustZone is a registered trademark of Arm Limited. eMMC™: eMMC is a trademark of MultiMediaCard Association.