Interface

R9A02G015

Renesas Technology Corp

ASSP (USB Power Delivery Controller) Mar 29, 2019

Manufacturer: Renesas Technology Corp

Document: 55 Pages / 2Mb

Request Quote Download Datasheet Read online HTML view

More from Renesas Technology Corp Browse R parts

Online Datasheet

Read R9A02G015 online.

R9A02G015 RENESAS | Alldatasheet

Document overview

Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 55

Technical content

R19DS0101EJ0100 Rev.1.00 Page 1 of 53 Mar 29, 2019 R9A02G015 ASSP (USB Power Delivery Controller) 1. OUTLINE

1.1 Features

Ultra-low power consumption technology  VDD = single power supply voltage of 2.7 to 5.5 V  HALT mode  STOP mode  SNOOZE mode RL78 CPU core  CISC architecture with 3-stage pipeline  Minimum instruction execution time: 0.04167 μs: @ 24 MHz operation with high-speed on-chip oscillator  Multiply/divide/multiply & accumulate instructions are supported.  Address space: 1 MB  General-purpose registers: (8-bit register × 8) × 4 banks  On-chip RAM: 7 KB Code flash memory  Code flash memory: 128 KB  Block size: 1 KB  Prohibition of block erase and rewriting (security function)  On-chip debug function  Self-programming (with boot swap function/flash shield window function) Data flash memory  Data flash memory: 2 KB  Back ground operation (BGO): Instructions can be executed from the program memory while rewriting the data flash memory.  Number of rewrites: 1,000,000 times (TYP.)  Voltage of rewrites: VDD = 2.7 to 5.5 V High-speed on-chip oscillator  Select from 48 MHz, 24 MHz, 16 MHz, 12 MHz,

8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz,

 High accuracy: ±1.0% (VDD = 2.7 to 5.5 V, TA = -20 to +85°C) Operating ambient temperature  TA = -40 to +85°C (A: Consumer applications) Power management and reset function  On-chip power-on-reset (POR) circuit  On-chip voltage detector (LVD) (Select reset from 6 levels) USB  Complying with USB Specification Revision 2.0, incorporating host/function controller  Corresponding to full-speed transfer (12 Mbps) and low-speed (1.5 Mbps)  Complying with Battery Charging Specification Revision 1.2  Compliant with the 2.1 A/1.0 A charging mode. Serial interfaces  CSI: 2 channels  UART: 1 channel  Simplified I2C: 2 channels  I2C: 2 or 3 channels Timers  16-bit timer: 8 channels  12-bit interval timer: 1 channel  Watchdog timer: 1 channel A/D converter  8/10-bit resolution A/D converter (VDD = 2.7 to 5.5 V)  Analog input: 8 channels  Internal reference voltage (1.45 V) and temperature sensor I/O ports  I/O port: 23 or 28 (N-ch open drain I/O [withstand voltage of 6 V]: 5, N-ch open drain I/O [VDD withstand voltage]: 8 or 13)  Can be set to N-ch open drain, TTL input buffer, and on-chip pull-up resistor  On-chip clock output/buzzer output controller Others  On-chip BCD (binary-coded decimal) correction circuit Remark The functions mounted depend on the product. See 1.6 Outline of Functions. R19DS0101EJ0100 Rev.1.00 Mar 29, 2019

R9A02G015 1. OUTLINE R19DS0101EJ0100 Rev.1.00 Page 2 of 53 Mar 29, 2019 ROM, RAM capacities Flash ROM Data flash RAM R9A02G015 32 pins (with USB) 32 pins (without USB)

128 KB 2 KB 7 KB Note R9A02G0150 R9A02G0151

Note The flash library uses RAM in self-programming and rewriting of the data flash memory. The target products and start address of the RAM areas used by the flash library are shown below. R9A02G0150/R9A02G0151: Start address FE300H

1.2 Ordering Information

Figure 1 - 1 Part Number and Package of R9A02G015 Pin count Package Ordering Part Number Remarks 32 pins 32-pin QFN (4 × 4 mm, 0.4 mm pitch) R9A02G015020GNP#AC0 Product with USB (R9A02G0150) R9A02G015120GNP#AC0 Product without USB (R9A02G0151) Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website.

R9A02G015 1. OUTLINE R19DS0101EJ0100 Rev.1.00 Page 3 of 53 Mar 29, 2019

1.3 Pin Configuration (Top View)

1.3.1 32-pin product (with USB)

32-pin QFN (4 × 4 mm, 0.4 mm pitch) P53/INTP9/TI02/TO02/SCL01/SCK01/UOVRCUR 1 P52/INTP8/TI01/TO01/SO00/TXD0/TOOLTXD /UVBUSEN 1 P51/INTP7/TI00/TO00/SDA00/SI00/RXD0/TOOLRXD P50/INTP6/SCL00/SCK00 P64/INTP5 P63/INTP4/SDAA1 P62/INTP3/SCLA1 P61/INTP2/SDAA0 exposed die pad (VSS) P25/ANI5 P24/ANI4 P23/ANI3 P21/ANI1/AVREFM P20/ANI0/AVREFP P01/INTP13/TI06/TO06/ANI17 P40/TOOL0 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VDD P60/INTP1/SCLA0 RESETB P54/INTP10/TI03/TO03/SDA01/SI01/UVBUSEN 0 P55/INTP11/TI04/TO04/SO01/UOVRCUR 0 UDM1 UDP1 UVDD UVBUS UDM0 UDP0 P00/INTP12/TI05/TO05/ANI16/PCLBUZ 0 P22/ANI2 INDEX MARK R9A02G0150 (Top View) 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 Caution 1. Connect the exposed die pad (VSS) to ground. Caution 2. Connect the REGC pin to VSS via a capacitor (0.47 to 1 μF). Remark For pin identification, see 1.4 Pin Identification.

R9A02G015 1. OUTLINE R19DS0101EJ0100 Rev.1.00 Page 4 of 53 Mar 29, 2019 1.3.2 32-pin product (without USB)

32-pin QFN (4 × 4 mm, 0.4 mm pitch) P53/INTP9/TI02/TO02/SCL01/SCK01 P52/INTP8/TI01/TO01/SO00/TXD0/TOOLTXD P51/INTP7/TI00/TO00/SDA00/SI00/RXD0/TOOLRXD P50/INTP6/SCL00/SCK00 P64/INTP5 P63/INTP4/SDAA1 P62/INTP3/SCLA1 P61/INTP2/SDAA0 P25/ANI5 P24/ANI4 P23/ANI3 P21/ANI1/AVREFM P20/ANI0/AVREFP P01/INTP13/TI06/TO06/ANI17 P40/TOOL0 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VDD P60/INTP1/SCLA0 RESETB P70/SCLA2 P71/SDAA2 UVDD P72/INTP14 P73/INTP15 P74/TI07/TO07 P00/INTP12/TI05/TO05/ANI16/PCLBUZ 0 P22/ANI2 INDEX MARK R9A02G0151 (Top View) 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17

9 P54/INTP10/TI03/TO03/SDA01/SI01

exposed die pad (VSS) Caution 1. Connect the exposed die pad (VSS) to ground. Caution 2. Connect the REGC pin to VSS via a capacitor (0.47 to 1 μF). Remark For pin identification, see 1.4 Pin Identification.

R9A02G015 1. OUTLINE R19DS0101EJ0100 Rev.1.00 Page 5 of 53 Mar 29, 2019

1.4 Pin Identification

ANI0 to ANI5, ANI16, ANI17: Analog input AVREFM: A/D converter reference potential (- side) input AVREFP: A/D converter reference potential (+ side) input EXCLK: External clock input (main system clock) INTP0 to INTP15: External interrupt input P00, P01: Port 0 P20 to P25: Port 2 P40: Port 4 P50 to P55: Port 5 P60 to P64: Port 6 P70 to P74: Port 7 P121, P122: Port 12 P137: Port 13 PCLBUZ0: Programmable clock output/buzzer output REGC: Regulator capacitance RESETB: Reset RxD0: Receive data SCK00, SCK01: Serial clock input/output SCLA0 to SCLA2, SCL00, SCL01: Serial clock input/output SDAA0 to SDAA2, SDA00, SDA01: Serial data input/output SI00, SI01: Serial data input SO00, SO01: Serial data output TI00 to TI07: Timer input TO00 to TO07: Timer output TOOL0: Data input/output for tool TOOLRXD, TOOLTXD: Data input/output for external device TxD0: Transmit data UDM0, UDM1, UDP0, UDP1: USB Input/Output UOVRCUR0, UOVRCUR1: USB Input UVBUSEN0, UVBUSEN1: USB Output UVDD: USB Power Supply/USB Regulator Capacitance UVBUS: USB Input/USB Power Supply (USB Optional BC) VDD: Power supply VSS: Ground X1, X2: Crystal oscillator (main system clock)

R9A02G015 1. OUTLINE R19DS0101EJ0100 Rev.1.00 Page 6 of 53 Mar 29, 2019

1.5 Block Diagram

1.5.1 32-pin products 6Port 2 Port 4 Port 5 Port 6 Port 12 Port 13 Port 7 P2 0 to P25 P40 P5 0 to P55 P6 0 to P64 P7 0 to P74 P1 21, P1 22 P1 37 CSI00 UART0 CLOCK GENERATOR RESET CIRC UIT A/D CO NV ER TE R PO R/ LVD HIGH-SP EED ON-CHIP OSCILLATOR 4 8 M Hz LOW-SP EED ON-CHIP OSCILLATOR 1 5 kHz MAIN SYS TEM CLOCK GENERATOR 1 to 2 0 M Hz REGULATO R Port 0 RAM 7 KB INT CODE FLAS H: 12 8 KB DATA FLA SH: 2 KB M UL D I V SERIAL ARRAY UNIT0 (2ch) RxD0 TxD0 SCK00 SI00 SO00 SCK01 SI01 SO01 SCL00 SDA00 SCL01 RL7 8 CPU CORE X1 X2/EX CLK REGC VDD VSS TO O L RX D/P51, TOO LTXD/P52 P00, P01 ANI2 to ANI5, ANI16, ANI17 ANI0/AVR E FP ANI1/AVR E FM BCD CORRECTION CIR CUIT TI07 TO07 ch07 TIMER ARRAY UNIT 0 (8ch) TI00 TO00 ch00 TI01 TO01 ch01 TI02 TO02 ch02 TI03 TO03 ch03 TI04 TO04 ch04 TI05 TO05 ch05 TI06 TO06 ch06 CSI01 IIC00 IIC01 WATCH DOG TIMER (WDT) CRCUSB Voltag e Reg ulator PLL IICA0 IICA2 IICA1 SCLA0 SDA A0 SCLA1 SDA A1 SCLA2 SDA A2 CLOCK OUTPUT/ BUZZER OUTPUT CONTROLLER PCLBUZ0 16EXTERNAL INTERRUPT 16ch INTP0 to INTP15 12-BIT INTERV AL TIME R ON-CHIP DEBUG TOOL0/P40 USB SDA01 UDM0 UDP1 UDM1 UVBUS UOVRCUR0 UVB USEN0 UOVRCUR1 UDP0 UVB USEN1 UVDD RES ETB

R9A02G015 1. OUTLINE R19DS0101EJ0100 Rev.1.00 Page 7 of 53 Mar 29, 2019

1.6 Outline of Functions

(1/2) Item 32-pin (with USB) 32-pin (without USB) R9A02G0150 R9A02G0151 Code flash memory (KB) 128 KB Data flash memory (KB) 2 KB RAM 7KB Note 1 Address space 1 MB Main system clock High-speed system clock (fMX) X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) HS (High-speed main) mode: 1 to 20 MHz (VDD = 2.7 to 5.5 V) High-speed on-chip oscillator clock (fIH) Max: 24 MHz HS (High-speed main) mode: 1 to 24 MHz (VDD = 2.7 to 5.5 V) PLL clock 6, 12, 24 MHz Note 2: VDD = 2.7 to 5.5 V Subsystem clock Low-speed on-chip oscillator clock(fIL) 15 kHz (TYP.): VDD = 2.7 to 5.5 V General-purpose register 8 bits × 32 registers (8 bits × 8 registers × 4 banks) Minimum instruction execution time 0.04167 μs (High-speed on-chip oscillator clock: fHOCO = 48MHz/fIH = 24 MHz operation) 0.04167 μs (PLL clock: fPLL = 48 MHz/fIH = 24 MHz Note 2 operation) 0.05 μs (High-speed system clock: fMX = 20 MHz operation) Instruction set • Data transfer (8/16 bits)

Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits × 8 bits, 16 bits × 16 bits), Division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits)
Multiplication and Accumulation (16 bits × 16 bits + 32 bits)
Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc. I/O port Total 23 28 CMOS I/O 15 20 CMOS input 3 N-ch open-drain I/O (6 V tolerance) Timer 16-bit timer 8 channels Watchdog timer 1 channel 12-bit interval timer 1 channel Timer output 7 8 Clock output/buzzer output 1 2.93 kHz, 5.86 kHz, 11.7 kHz, 1.5 MHz, 3 MHz, 6 MHz (Main system clock: fMAIN = 24 MHz operation) 10-bit resolution A/D converter 8 channels Serial interface CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels I2C bus 2 channels 3 channels

R9A02G015 1. OUTLINE R19DS0101EJ0100 Rev.1.00 Page 8 of 53 Mar 29, 2019 (2/2) Item 32-pin (with USB) 32-pin (without USB) R9A02G0150 R9A02G0151 USB Host controller 2 channels — Function controller 1channel — Vectored interrupt sources Internal 22 21 External 14 16 Reset • Reset by RESETB pin

Internal reset by watchdog timer
Internal reset by power-on-reset
Internal reset by voltage detector
Internal reset by illegal instruction execution Note 3
Internal reset by RAM parity error
Internal reset by illegal-memory access Power-on-reset circuit • Power-on-reset: 1.51 ± 0.04 V (TA = -40 to +85°C)
Power-down-reset: 1.50 ± 0.04 V (TA = -40 to +85°C) Voltage detector Power on 2.81 V to 4.06 V (6 stages) Power down 2.75 V to 3.98 V (6 stages) On-chip debug function Provided (Enable to tracing) Power supply voltage V DD = 2.7 to 5.5 V Operating ambient temperature TA = -40 to +85°C Note 1. The flash library uses RAM in self-programming and rewriting of the data flash memory. The target products and start address of the RAM areas used by the flash library are shown below. R9A02G0150/R9A02G0151: Start address FE300H Note 2. In the PLL clock 48 MHz operation, the system clock is 2/4/8 dividing ratio. Note 3. The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution is not issued by emulation with the in-circuit emulator or on-chip debug emulator.

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 9 of 53 Mar 29, 2019 2. ELECTRICAL SPECIFICATIONS The target products A: Consumer applications; TA = -40 to +85°C R9A02G0150, R9A02G0151 Cautions 1. The R9A02G015 has an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. 2. The pins mounted depend on the product. Refer to 2.1 Port Function to 2.2 Functions other than port pins in the R9A02G015 User’s Manual.

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 10 of 53 Mar 29, 2019

2.1 Absolute Maximum Ratings

Absolute Maximum Ratings (TA = 25°C) (1/2) Parameter Symbols Conditions Ratings Unit Supply voltage VDD −0.5 to +6.5 V REGC pin input voltage VIREGC REGC −0.3 to +2.8 and −0.3 to VDD +0.3Note 1 V UVDD pin input voltage VIUVDD UVDD −0.3 to VDD +0.3 V Input voltage VI1 P00, P01, P20 to P25, P40, P50 to P55, P70 to P74, P121, P122, P137, RESETB −0.3 to VDD +0.3Note 2 V VI2 P60 to P64 (N-ch open-drain) −0.3 to +6.5 V VI3 UDP0, UDM0, UDP1, UDM1 −0.3 to +6.5 V VI4 UVBUS −0.3 to +6.5 V Output voltage VO1 P00, P01, P20 to P25, P40, P50 to P55, P70 to P74 −0.3 to VDD +0.3 Note 2 V VO2 UDP0, UDM0, UDP1, UDM1 −0.3 to +6.5 V Analog input voltage VAI1 ANI16, ANI17 −0.3 to VDD +0.3 and −0.3 to AVREF (+) +0.3 Notes 2, 3 V VAI2 ANI0 to ANI5 −0.3 to VDD +0.3 and −0.3 to AVREF (+) +0.3 Notes 2, 3 V Notes 1. Connect the REGC pin to Vss via a capacitor (0.47 to 1 µF). This value regulates the absolute maximum rating of the REGC pin. Do not use this pin with voltage applied to it. 2. Must be 6.5 V or lower. 3. Do not exceed AV REF (+) + 0.3 V in case of A/D conversion target pin Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. 2. AVREF (+) : The + side reference voltage of the A/D converter. This can be selected from AVREFP, the internal reference voltage (1.45 V), and VDD. 3. VSS : Reference voltage

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 11 of 53 Mar 29, 2019 Absolute Maximum Ratings (TA = 25°C) (2/2) Parameter Symbols Conditions Ratings Unit Output current, high IOH1 Per pin P00, P01, P40, P50 to P55, P70- P74 −40 mA Total of all pins −170 mA P00, P01, P40 −70 mA P50 to P55, P70 to P74 −100 mA IOH2 Per pin P20 to P25 −0.5 mA Total of all pins −2 mA Output current, low IOL1 Per pin P00, P01, P40, P50 to P55, P60 to P64, P70 to P74 40 mA Total of all pins 170 mA P00, P01, P40 70 mA P50 to P55, P60 to P64, P70 to P74 100 mA IOL2 Per pin P20 to P25 1 mA Total of all pins 5 mA Operating ambient temperature TA In normal operation mode −40 to +85 °C In flash memory programming mode Storage temperature Tstg −65 to +150 °C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 12 of 53 Mar 29, 2019

2.2 Oscillator Characteristics

2.2.1 X1 oscillator characteristics

(TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Resonator Conditions MIN. TYP. MAX. Unit X1 clock oscillation frequency (fX)Note Ceramic resonator/ crystal resonator 2.7 V ≤ VDD ≤ 5.5 V 1.0 20.0 MHz Note Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution time. Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator characteristics. Caution Since the CPU is started by the high -speed on-chip oscillator clock after a reset release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscillation stabili zation time of the OSTC register and the oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used.

2.2.2 On-chip oscillator characteristics

(TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Oscillators Parameters Conditions MIN. TYP. MAX. Unit High-speed on-chip oscillator clock frequency Notes 1, 2 fHOCO 1 48 MHz High-speed on-chip oscillator clock frequency accuracy Low-speed on-chip oscillator clock frequency fIL 15 kHz Low-speed on-chip oscillator clock frequency accuracy −15 +15 % Notes 1. High-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000C2H/010C2H) and bits 0 to 2 of HOCODIV register. 2. This indicates the oscillator characteristics only. Refer to AC Characteristics for instruction execution time.

2.2.3 PLL oscillator characteristics

(TA = −40 to +85°C, 2.7V ≤ VDD ≤ 5.5 V, VSS = 0 V) Oscillators Parameters Conditions MIN. TYP. MAX. Unit PLL input frequency Note fPLLIN High-speed system clock 6.00 16.00 MHz PLL output frequency Note fPLL 48.00 MHz Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 13 of 53 Mar 29, 2019

2.3 DC Characteristics

2.3.1 Pin characteristics

(TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Items Symbol Conditions MIN. TYP. MAX. Unit Input voltage, high VIH1 P00, P01, P40, P50 to P55, P70 to P74 Normal input buffer 0.8VDD VDD V VIH2 P00, P01, P50 to P55, P70 to P74 TTL input buffer 4.0 V ≤ VDD ≤ 5.5 V

2.2 VDD V

3.3 V ≤ VDD < 4.0 V

2.0 VDD V

2.7 V ≤ VDD < 3.3 V

1.5 VDD V

VIH3 P20 to P25 0.7VDD VDD V VIH4 P60 to P64 0.7VDD 6.0 V VIH5 P121, P122, P137, RESETB 0.8VDD VDD V Input voltage, low VIL1 P00, P01, P40, P50 to P55, P70 to P74 Normal input buffer 0 0.2VDD V VIL2 P00, P01, P50 to P55, P70 to P74 TTL input buffer 4.0 V ≤ VDD ≤ 5.5 V 0 0.8 V TTL input buffer 3.3 V ≤ VDD < 4.0 V 0 0.5 V TTL input buffer 2.7 V ≤ VDD < 3.3 V 0 0.32 V VIL3 P20 to P25 0 0.3VDD V VIL4 P60 to P64 0 0.3VDD V VIL5 P121, P122, P137, RESETB 0 0.2VDD V Caution The maximum value of VIH of pins P00, P01, P50-P55, and P70-P74 is VDD, even in the N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 14 of 53 Mar 29, 2019 (TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Items Symbol Conditions MIN. TYP. MAX. Unit Output voltage, high VOH1 P00, P01. P40, P50 to P55, P70 to P74 2.7 V ≤ VDD ≤ 5.5 V, IOH1 = −1.5 mA VDD − 0.5 V VOH2 P20 to P25 2.7 V ≤ VDD ≤ 5.5 V, IOH2 = −100 µA VDD − 0.5 V Output voltage, low VOL1 P00, P01, P40, P50 to P55, P70 to P74 2.7 V ≤ VDD ≤ 5.5 V, IOL1 = 1.5 mA 0.4 V VOL2 P20 to P25 2.7 V ≤ VDD ≤ 5.5 V, IOL2 = 400 µA 0.4 V VOL3 P60 to P64 2.7 V ≤ VDD ≤ 5.5 V, IOL1 = 3.0 mA 0.4 V Caution P00, P01, P50-P55, and P70-P74 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. (TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Items Symbol Conditions MIN. TYP. MAX. Unit Input leakage current, high ILIH1 P00, P01, P20 to P25, P40, P50 to P55, P60 to P64, P70 to P74, P137, RESETB VI = VDD 1 µA ILIH2 P121, P122 VI = VDD In input port or external clock input 1 µA Input leakage current, low ILIL1 P00, P01, P20 to P25, P40, P50 to P55, P60 to P64, P70 to P74, P137, RESETB VI = VSS −1 µA ILIL2 P121, P122 VI = VSS In input port or external clock input −1 µA On-chip pll-up resistance RU P00, P01, P40, P50 to P55, P70 to P74 VI = VSS, In input port 10 20 100 kΩ Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 15 of 53 Mar 29, 2019

2.3.2 Supply current characteristics

(TA = 25 °C, VDD = 3.3 V , VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply current Note 1 IDD1 Operating mode HS (High-speed main) mode fHOCO = 48 MHz fIH = 24 MHz Note 2 2.8 mA fHOCO = 24 MHz fIH = 24 MHz Note 2 2.6 mA IDD2 Note 3 HALT mode HS (High-speed main) mode fHOCO = 48 MHz fIH = 24 MHz Note 4 0.92 mA fHOCO = 24 MHz fIH = 24 MHz Note 4 0.72 mA IDD3Note 5 STOP mode 0.26 µA Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD, or VSS. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on- chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. When high-speed system clock is stopped. 3. During HALT instruction execution by flash memory. 4. When high-speed system clock and Low-speed on-chip oscillator clock are stopped. 5. Not including the current flowing into the 12-bit interval timer and watchdog timer. Remarks 1. fHOCO: High-speed on-chip oscillator clock frequency (Max. 48 MHz) 2. fIH: Main system clock source frequency obtained by dividing the high-speed on-chip oscillator clock by 2, 4, or 8 (Max. 24 MHz)

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 16 of 53 Mar 29, 2019 (TA = 25 °C, VDD = UVDD = 3.3 V , VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit USB operating current Note 1 IUSBF Note 2 During USB communication operation under the following settings and conditions:

The function controller is set to operate in full-speed mode
The internal power supply for the USB is stopped.
fHOCO = 48MHz, fIH = 24MHz 1.8 mA ISUSP Note 3 During suspended state under the following settings and conditions:
The function controller is set to full-speed mode (the UDP0 pin is pulled up).
The internal power supply for the USB is stopped.
The system is set to STOP mode (When the high-speed on-chip oscillator and high-speed system clock are stopped. When the watchdog timer is stopped.). 180 µA Notes 1. Current flowing into VDD and UVDD. 2. Current consumed only by the USB module. 3. Includes the current supplied from the pull -up resistor of the UDP0 pin to the pull -down resistor of the host device, in addition to the current consumed by this MCU during the suspended state. Remarks 1. fHOCO: High-speed on-chip oscillator clock frequency (Max. 48 MHz) 2. fIH: Main system clock source frequency obtained by dividing the high-speed on-chip oscillator clock by 2, 4, or 8 (Max. 24 MHz)

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 17 of 53 Mar 29, 2019

2.4 AC Characteristics

2.4.1 Basic operation

(TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Items Symbol Conditions MIN. TYP. MAX. Unit Instruction cycle (minimum instruction execution time) TCY Main system clock (fMAIN) operation HS (High- speed main) mode 2.7 V ≤ VDD ≤ 5.5 V 0.04167 1 µs In the self programming mode HS (High- speed main) mode 2.7 V ≤ VDD ≤ 5.5 V 0.04167 1 µs External system clock frequency fEX 2.7 V ≤ VDD ≤ 5.5 V 1.0 20.0 MHz External system clock input high-level width, low-level width tEXH, tEXL 2.7 V ≤ VDD ≤ 5.5 V 24 ns Interrupt input high-level width, low-level width tINTH, tINTL INTP0 to INTP15 2.7 V ≤ VDD ≤ 5.5 V 1 µs RESETB low-level width tRSL 10 µs Remark fMCK: Timer array unit operation clock frequency (Operation clock to be set by the CKS0n bit of timer mode register 0n (TMR0n). n: Channel number (n = 0 to 7)) AC Timing Test Points External System Clock Timing RESETB Input Timing RESETB

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 18 of 53 Mar 29, 2019

2.5 Peripheral Functions Characteristics

2.5.1 Serial array unit

(1) During communication at same potential (UART mode) (dedicated baud rate generator output) (TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate fMCK/6 bps Theoretical value of the maximum transfer rate fMCK = fCLK Note

4.0 Mbps

Note The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 24 MHz (2.7 V ≤ VDD ≤ 5.5 V) Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). UART mode connection diagram (during communication at same potential) UART mode bit width (during communication at same potential) (reference) Remarks 1. q: UART number (q = 0), g: PIM and POM number (g = 5) 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) R9A02G015

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 19 of 53 Mar 29, 2019 (2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output, corresponding CSI00 only) (TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKp cycle time tKCY1 tKCY1 ≥ 2/fCLK 2.7 V ≤ VDD ≤ 5.5 V 83.3 ns SCKp high-/low-level width tKH1, tKL1 4.0 V ≤ VDD ≤ 5.5 V tKCY1/2 − 7 ns 2.7 V ≤ VDD ≤ 5.5 V tKCY1/2 − 10 ns SIp setup time (to SCKp↑) Note 1 tSIK1 4.0 V ≤ VDD ≤ 5.5 V 23 ns 2.7 V ≤ VDD ≤ 5.5 V 33 ns SIp hold time (from SCKp↑) Note 2 tKSI1 2.7 V ≤ VDD ≤ 5.5 V 10 ns Delay time from SCKp↓ to SOp output Note 3 tKSO1 C = 20 pFNote 4 10 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓ ” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or D APmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. This specification is valid only when CSI00’s peripheral I/O redirect function is not used. 2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM numbers (g = 5) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00))

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 20 of 53 Mar 29, 2019 (3) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output) (TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM and POM numbers (g = 5) 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01)) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKp cycle time tKCY1 tKCY1 ≥ 4/fCLK 2.7 V ≤ VDD ≤ 5.5 V 167 ns SCKp high-/low-level width tKH1, tKL1 4.0 V ≤ VDD ≤ 5.5 V tKCY1/2 − 12 ns 2.7 V ≤ VDD ≤ 5.5 V tKCY1/2 − 18 ns SIp setup time (to SCKp↑) Note 1 tSIK1 4.0 V ≤ VDD ≤ 5.5 V 44 ns 2.7 V ≤ VDD ≤ 5.5 V 44 ns SIp hold time (from SCKp↑) Note 2 tKSI1 19 ns Delay time from SCKp↓ to SOp output Note 3 tKSO1 C = 30 pFNote 4 25 ns

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 21 of 53 Mar 29, 2019 (4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKp cycle time Note 5 tKCY2 4.0 V ≤ VDD ≤ 5.5 V 20 MHz < fMCK 8/fMCK ns fMCK ≤ 20 MHz 6/fMCK ns 2.7 V ≤ VDD ≤ 5.5 V 16 MHz < fMCK 8/fMCK ns fMCK ≤ 16 MHz 6/fMCK ns SCKp high-/low-level width tKH2, tKL2 4.0 V ≤ VDD ≤ 5.5 V tKCY2/2 − 7 ns 2.7 V ≤ VDD ≤ 5.5 V tKCY2/2 − 8 ns SIp setup time (to SCKp↑) Note 1 tSIK2 2.7 V ≤ VDD ≤ 5.5 V 1/fMCK+20 ns SIp hold time (from SCKp↑) Note 2 tKSI2 2.7 V ≤ VDD ≤ 5.5 V 1/fMCK+31 ns Delay time from SCKp↓ to SOp output Note 3 tKSO2 C = 30 pF Note 4 2.7 V ≤ VDD ≤ 5.5 V 2/fMCK+44 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓ ” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SOp output lines. 5. Transfer rate in the SNOOZE mode : MAX. 1 Mbps Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM number (g = 0, 5, 7) 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01))

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 22 of 53 Mar 29, 2019 CSI mode connection diagram (during communication at same potential) CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) Remarks 1. p: CSI number (p = 00, 01) 2. m: Unit number, n: Channel number (mn = 00, 01) R9A02G015

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 23 of 53 Mar 29, 2019 (5) During communication at same potential (simplified I2C mode) (TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. MAX. Unit SCLr clock frequency fSCL 2.7 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ

1000 Note 1 kHz

2.7 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ

400 Note 1 kHz

Hold time when SCLr = “L” tLOW 2.7 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 475 ns 2.7 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 1150 ns Hold time when SCLr = “H” tHIGH 2.7 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 475 ns 2.7 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 1150 ns Data setup time (reception) tSU:DAT 2.7 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 1/fMCK + 85 Note 2 ns 2.7 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 1/fMCK + 145 Note 2 ns Data hold time (transmission) tHD:DAT 2.7 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 0 305 ns 2.7 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 0 355 ns Notes 1. The value must also be equal to or less than fMCK/4. 2. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H". Caution Select the normal input buffer and the N -ch open drain output (V DD tolerance) mode for the SDAr pin and the normal output mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register h (POMh). (Caution and Remarks are listed on the next page.)

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 24 of 53 Mar 29, 2019 Simplified I2C mode mode connection diagram (during communication at same potential) Simplified I2C mode serial transfer timing (during communication at same potential) Remarks 1. Rb[Ω]:Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance 2. r: IIC number (r = 00, 01), g: PIM number (g = 5), h: POM number (h = 5) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0), n: Channel number (n = 0, 1), mn = 00, 01) R9A02G015

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 25 of 53 Mar 29, 2019 (6) Communication at different potential (2.5 V, 3 V) (UART mode) (1/2) (TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate reception 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V fMCK/6Note 1 bps Theoretical value of the maximum transfer rate fMCK = fCLK Note 2 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V fMCK/6Note 1 bps Theoretical value of the maximum transfer rate fMCK = fCLK Note 2 Notes 1. Use it with VDD≥Vb. 2. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 24 MHz (2.7 V ≤ VDD ≤ 5.5 V) Caution Select the TTL input buffer for the RxDq pin and the N -ch open drain output ( VDD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remarks 1. Vb[V]: Communication line voltage 2. q: UART number (q = 0), g: PIM and POM number (g = 5) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 26 of 53 Mar 29, 2019 (6) Communication at different potential (2.5 V, 3 V) (UART mode) (2/2) (TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate transmission 4.0 V ≤ VDD ≤ 5.5 V, Note 1 bps 2.7 V ≤ Vb ≤ 4.0 V Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 1.4 kΩ, Vb = 2.7 V

2.8 Note 2 Mbps

2.7 V ≤ VDD < 4.0 V Note 3 bps 2.3 V ≤ Vb ≤ 2.7 V Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 2.7 kΩ, Vb = 2.3 V

1.2 Note 4 Mbps

Notes 1. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 4.0 V ≤ VDD ≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V Maximum transfer rate = [bps] Vb )} × 3 Transfer rate × 2 − {−Cb × Rb × ln (1 − 2.2 Vb Baud rate error (theoretical value) = × 100 [%] ( 1 Transfer rate ) × Number of transferred bits * This value is the theoretical value of the relative difference between the transmission and reception sides. 2. This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer. 3. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V ≤ VDD < 4.0 V and 2.3 V ≤ Vb ≤ 2.7 V Maximum transfer rate = [bps] Vb )} × 3 Transfer rate × 2 − {−Cb × Rb × ln (1 − 2.0 Vb Baud rate error (theoretical value) = × 100 [%] ( 1 Transfer rate ) × Number of transferred bits * This value is the theoretical value of the relative difference between the transmission and reception sides. 4. This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer.

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 27 of 53 Mar 29, 2019 Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For V IH and VIL, see the DC characteristics with TTL input buffer selected. UART mode connection diagram (during communication at different potential) UART mode bit width (during communication at different potential) (reference) Remarks 1. Rb[Ω]:Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage 2. q: UART number (q = 0), g: PIM and POM number (g = 5) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) R9A02G015

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 28 of 53 Mar 29, 2019 (7) Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output, corresponding CSI00 only) (TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKp cycle time tKCY1 tKCY1 ≥ 2/fCLK 4.0 V ≤ VDD ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ 200 ns 2.7 V ≤ VDD < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ 300 ns SCKp high-level width tKH1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ tKCY1/2 − 50 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ tKCY1/2 − 120 ns SCKp low-level width tKL1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ tKCY1/2 − 7 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ tKCY1/2 − 10 ns SIp setup time (to SCKp↑) Note 1 tSIK1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ 58 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ 121 ns SIp hold time (from SCKp↑) Note 1 tKSI1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ 10 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ 10 ns Delay time from SCKp↓ to SOp output Note 1 tKSO1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ 60 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ 130 ns SIp setup time (to SCKp↓) Note 2 tSIK1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ 23 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ 33 ns SIp hold time (from SCKp↓) Note 2 tKSI1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ 10 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ 10 ns Delay time from SCKp↑ to SOp output Note 2 tKSO1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ 10 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ 10 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. 2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. (Caution and Remark are listed on the next page.)

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 29 of 53 Mar 29, 2019 Caution Select the TTL input buffer for the SIp pin and the N -ch open drain output (VDD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port outpu t mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM number (g = 5) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00) 4. This value is valid only when CSI00’s peripheral I/O redirect function is not used.

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 30 of 53 Mar 29, 2019 (TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKp cycle time tKCY1 tKCY1 ≥ 4/fCLK 4.0 V ≤ VDD ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ 300 ns 2.7 V ≤ VDD < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ 500 ns SCKp high-level width tKH1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ tKCY1/2 − 75 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ tKCY1/2 − 170 ns SCKp low-level width tKL1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ tKCY1/2 − 12 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ tKCY1/2 − 18 ns Cautions 1. Select the TTL input buffer for the SIp pin and the N -ch open drain output (VDD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. 2. Use it with VDD ≥ Vb. (Remarks are listed two pages after the next page.)

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 31 of 53 Mar 29, 2019 (TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit SIp setup time (to SCKp↑) Note 1 tSIK1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 81 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 177 ns SIp hold time (from SCKp↑) Note 1 tKSI1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 19 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 19 ns Delay time from SCKp↓ to SOp output Note 1 tKSO1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 100 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 195 ns SIp setup time (to SCKp↓) Note 2 tSIK1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 44 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 44 ns SIp hold time (from SCKp↓) Note 2 tKSI1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 19 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 19 ns Delay time from SCKp↑ to SOp output Note 2 tKSO1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 25 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 25 ns (Notes, Cautions and Remarks are listed on the next page.)

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 32 of 53 Mar 29, 2019 Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. 2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. CSI mode connection diagram (during communication at different potential) Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00), m: Unit number, n: Channel number (mn = 00), g: PIM and POM number (g = 5) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) 4. CSI01 cannot communicate at different potential. Use other CSI for communication at different potential. R9A02G015

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 33 of 53 Mar 29, 2019 CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) Remarks 1. p: CSI number (p = 00), m: Unit number, n: Channel number (mn = 00), g: PIM and POM number (g =5) 2. CSI01 cannot communicate at different potential. Use other CSI for communication at different potential.

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 34 of 53 Mar 29, 2019 (TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKp cycle time Note 1 tKCY2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V

20 MHz < fMCK ≤ 24 MHz 12/fMCK ns

8 MHz < fMCK ≤ 20 MHz 10/fMCK ns

4 MHz < fMCK ≤ 8 MHz 8/fMCK ns

fMCK ≤ 4 MHz 6/fMCK ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V

20 MHz < fMCK ≤ 24 MHz 16/fMCK ns

16 MHz < fMCK ≤ 20 MHz 14/fMCK ns

8 MHz < fMCK ≤ 16 MHz 12/fMCK ns

fMCK ≤ 4 MHz 6/fMCK ns SCKp high-/low-level width tKH2, tKL2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V tKCY2/2 − ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V tKCY2/2 − ns SIp setup time (to SCKp↑) Note 2 tSIK2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V 1/fMCK + ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V 1/fMCK + ns SIp hold time (from SCKp↑) Note 3 tKSI2 1/fMCK + 31 ns Delay time from SCKp↓ to SOp output Note 4 tKSO2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 2/fMCK + 120 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 2/fMCK + 214 ns Notes 1. Transfer rate in the SNOOZE mode : MAX. 1 Mbps 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓ ” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. (Caution and Remarks are listed on the next page.)

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 35 of 53 Mar 29, 2019 Caution Select the TTL input buffer for the SIp pin and the N -ch open drain output (VDD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. CSI mode connection diagram (during communication at different potential) Remarks 1. Rb[Ω]:Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00), m: Unit number, n: Channel number (mn = 00), g: PIM and POM number (g = 5) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) 4. CSI01 cannot communicate at different potential. Use other CSI for communication at different potential. R9A02G015

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 36 of 53 Mar 29, 2019 CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) Remarks 1. p: CSI number (p = 00), m: Unit number, n: Channel number (mn = 00), g: PIM and POM number (g = 5) 2. CSI01 cannot communicate at different potential. Use other CSI for communication at different potential.

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 37 of 53 Mar 29, 2019 (10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (1/2) (TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. MAX. Unit SCLr clock frequency fSCL 4.0 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 2.7 V ≤ VDD < 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 4.0 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 2.8 kΩ 2.7 V ≤ VDD < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ Hold time when SCLr = “L” tLOW 4.0 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 475 ns 2.7 V ≤ VDD < 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 475 ns 4.0 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 2.8 kΩ 1150 ns 2.7 V ≤ VDD < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ 1150 ns Hold time when SCLr = “H” tHIGH 4.0 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 245 ns 2.7 V ≤ VDD < 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 200 ns 4.0 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 2.8 kΩ 675 ns 2.7 V ≤ VDD < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ 600 ns (Notes, Caution and Remarks are listed on the next page.)

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 38 of 53 Mar 29, 2019 (10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (2/2) (TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. MAX. Unit Data setup time (reception) tSU:DAT 4.0 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 1/fMCK + 135 Note 2 ns 2.7 V ≤ VDD < 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 1/fMCK + 135 Note 2 ns 4.0 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 2.8 kΩ 1/fMCK + 190 Note 2 ns 2.7 V ≤ VDD < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ 1/fMCK + 190 Note 2 ns Data hold time (transmission) tHD:DAT 4.0 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 0 305 ns 2.7 V ≤ VDD < 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 0 305 ns 4.0 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 2.8 kΩ 0 355 ns 2.7 V ≤ VDD < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ 0 355 ns Notes 1. The value must also be equal to or less than fMCK/4. 2. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H". Caution Select the TTL input buffer and the N -ch open drain output (VDD tolerance) mode for the SDAr pin and the N-ch open drain output (VDD tolerance) mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.)

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 39 of 53 Mar 29, 2019 Simplified I2C mode connection diagram (during communication at different potential) Simplified I2C mode serial transfer timing (during communication at different potential) Remarks 1. Rb[Ω]:Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance, Vb[V]: Communication line voltage 2. r: IIC number (r = 00), g: PIM, POM number (g = 5) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00) R9A02G015

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 40 of 53 Mar 29, 2019

2.5.2 Serial interface IICA

(1) I2C standard mode (TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) mode Unit MIN. MAX. SCLA0 clock frequency fSCL Standard mode: fCLK ≥ 1 MHz 2.7 V ≤ VDD ≤ 5.5 V 0 100 kHz Setup time of restart condition tSU:STA 2.7 V ≤ VDD ≤ 5.5 V 4.7 µs Hold timeNote 1 tHD:STA 2.7 V ≤ VDD ≤ 5.5 V 4.0 µs Hold time when SCLA0 = “L” tLOW 2.7 V ≤ VDD ≤ 5.5 V 4.7 µs Hold time when SCLA0 = “H” tHIGH 2.7 V ≤ VDD ≤ 5.5 V 4.0 µs Data setup time (reception) tSU:DAT 2.7 V ≤ VDD ≤ 5.5 V 250 µs Data hold time (transmission)Note 2 tHD:DAT 2.7 V ≤ VDD ≤ 5.5 V 0 3.45 µs Setup time of stop condition tSU:STO 2.7 V ≤ VDD ≤ 5.5 V 4.0 µs Bus-free time tBUF 2.7 V ≤ VDD ≤ 5.5 V 4.7 µs Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected. 2. The maximum value (MAX.) of t HD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull -up resistor) at that time in each mode are as follows. Standard mode: Cb = 400 pF, Rb = 2.7 kΩ (2) I2C fast mode (TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SCLA0 clock frequency fSCL Fast mode: fCLK ≥ 3.5 MHz 2.7 V ≤ VDD ≤ 5.5 V 0 400 kHz Setup time of restart condition tSU:STA 2.7 V ≤ VDD ≤ 5.5 V 0.6 µs Hold timeNote 1 tHD:STA 2.7 V ≤ VDD ≤ 5.5 V 0.6 µs Hold time when SCLA0 = “L” tLOW 2.7 V ≤ VDD ≤ 5.5 V 1.3 µs Hold time when SCLA0 = “H” tHIGH 2.7 V ≤ VDD ≤ 5.5 V 0.6 µs Data setup time (reception) tSU:DAT 2.7 V ≤ VDD ≤ 5.5 V 100 ns Data hold time (transmission)Note 2 tHD:DAT 2.7 V ≤ VDD ≤ 5.5 V 0 0.9 µs Setup time of stop condition tSU:STO 2.7 V ≤ VDD ≤ 5.5 V 0.6 µs Bus-free time tBUF 2.7 V ≤ VDD ≤ 5.5 V 1.3 µs Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected. 2. The maximum value (MAX.) of t HD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull -up resistor) at that time in each mode are as follows. Fast mode: Cb = 320 pF, Rb = 1.1 kΩ

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 41 of 53 Mar 29, 2019 (3) I2C fast mode plus (TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SCLA0 clock frequency fSCL Fast mode plus: fCLK ≥ 10 MHz 2.7 V ≤ VDD ≤ 5.5 V 0 1000 kHz Setup time of restart condition tSU:STA 2.7 V ≤ VDD ≤ 5.5 V 0.26 µs Hold timeNote 1 tHD:STA 2.7 V ≤ VDD ≤ 5.5 V 0.26 µs Hold time when SCLA0 = “L” tLOW 2.7 V ≤ VDD ≤ 5.5 V 0.5 µs Hold time when SCLA0 = “H” tHIGH 2.7 V ≤ VDD ≤ 5.5 V 0.26 µs Data setup time (reception) tSU:DAT 2.7 V ≤ VDD ≤ 5.5 V 50 ns Data hold time (transmission)Note 2 tHD:DAT 2.7 V ≤ VDD ≤ 5.5 V 0 0.45 µs Setup time of stop condition tSU:STO 2.7 V ≤ VDD ≤ 5.5 V 0.26 µs Bus-free time tBUF 2.7 V ≤ VDD ≤ 5.5 V 0.5 µs Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected. 2. The maximum value (MAX.) of t HD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull -up resistor) at that time in each mode are as follows. Fast mode plus: Cb = 120 pF, Rb = 1.1 kΩ IICA serial transfer timing

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 42 of 53 Mar 29, 2019

2.5.3 USB

(1) Electrical specifications (TA = −40 to +85°C, 3.0 V ≤ UVDD ≤ 3.6 V, 3.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit UVDD UVDD input voltage characteristic UVDD VDD = 3.0 to 5.5 V, PXXCON = 1, VDDUSEB = 0 (UVDD ≤ VDD) 3.0 3.3 3.6 V UVDD output voltage characteristic UVDD VDD = 4.0 to 5.5 V, PXXCON = VDDUSEB = 1 3.0 3.3 3.6 V UVBUS UVBUS input voltage characteristic UVBUS Function 4.35 (4.02Note) 5.00 5.5 V Host 4.75 5.00 5.5 V Note Value of instantaneous voltage (TA = −40 to +85°C, 3.0 V ≤ UVDD ≤ 3.6 V, 3.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit UDPi/UDMi pins input characteristic Input voltage VIH 2.0 V VIL 0.8 V Difference input sensitivity VDI | UDP voltage − UDM voltage | 0.2 V Difference common mode range VCM 0.8 2.5 V UDPi/UDMi pins output characteristic (FS driver) Output voltage VOH IOH = −200 µA 2.8 3.6 V VOL IOL = 2.4 mA 0 0.3 V Transi- tion time Rising tFR Rising: From 10% to 90 % of amplitude, Falling: From 90% to 10 % of amplitude, CL = 50 pF 4 20 ns Falling tFF 4 20 ns Matching (TFR/TFF) TFRFM 90 111.1 % Crossover voltage VFCRS 1.3 2.0 V Output Impedance ZDRV UVDD voltage = 3.3 V, Pin voltage = 1.65 V 28 44 Ω UDPi/UDMi pins pull-up, pull-down Pull-down resistor RPD 14.25 24.80 kΩ Pull-up resistor (i = 0 only) Idle RPUI 0.9 1.575 kΩ Recep- tion RPUA 1.425 3.09 kΩ UVBUS UVBUS pull-down resistor RVBUS UVBUS voltage = 5.5 V 1000 kΩ UVBUS input voltage VIH 3.20 V VIL 0.8 V Remark i = 0, 1

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 43 of 53 Mar 29, 2019 Timing of UDPi and UDMi (2) BC standard (TA = −40 to +85°C, 3.0 V ≤ UVDD ≤ 3.6 V, 3.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit USB standard BC1.2 UDPi sink current IDP_SINK 25 175 µA UDMi sink current IDM_SINK 25 175 µA Dedicated charging port resistor RDCP_DAT 0 V < UDP/UDM voltage < 1.0 V 200 Ω Data detection voltage VDAT_REF 0.25 0.4 V UDPi source voltage VDP_SRC Output current 250 µA 0.5 0.7 V UDMi source voltage VDM_SRC Output current 250 µA 0.5 0.7 V Remark i = 0, 1

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 44 of 53 Mar 29, 2019 (3) BC option standard (Host) Parameter Symbol Conditions MIN. TYP. MAX. Unit UDPi output voltage (UVBUS divider ratio)

VDOUEi = 1 VDSELi [3:0]

1000 VP20 38 40 42 % UVBUS

1001 VP27 51.6 53.6 55.6 % UVBUS

1010 VP20 38 40 42 % UVBUS

1100 VP33 60 66 72 % UVBUS

(UVBUS divider ratio)

VDOUEi = 1 VDSELi [3:0]

1000 VM20 38 40 42 % UVBUS

1001 VM20 38 40 42 % UVBUS

1010 VM27 51.6 53.6 55.6 % UVBUS

1100 VM33 60 66 72 % UVBUS

(UVBUS divider ratio)

VDOUEi = 1
CUSDETEi = 1 VDSELi [3:0] 1000 VHDETP_UP0 The rise of pin voltage detection voltage 56.2 % UVBUS VHDETP_DWN0 The fall of pin voltage detection voltage 29.4 % UVBUS 1001 VHDETP_UP1 The rise of pin voltage detection voltage 60.5 % UVBUS VHDETP_DWN1 The fall of pin voltage detection voltage 45.0 % UVBUS 1010 VHDETP_UP2 The rise of pin voltage detection voltage 56.2 % UVBUS VHDETP_DWN2 The fall of pin voltage detection voltage 29.4 % UVBUS UDMi comparing voltage Note 1 (UVBUS divider ratio)
VDOUEi = 1
CUSDETEi = 1 VDSELi [3:0] 1000 VHDETM_UP0 The rise of pin voltage detection voltage 56.2 % UVBUS VHDETM_DWN0 The fall of pin voltage detection voltage 29.4 % UVBUS 1001 VHDETM_UP1 The rise of pin voltage detection voltage 56.2 % UVBUS VHDETM_DWN1 The fall of pin voltage detection voltage 29.4 % UVBUS 1010 VHDETM_UP2 The rise of pin voltage detection voltage 60.5 % UVBUS VHDETM_DWN2 The fall of pin voltage detection voltage 45.0 % UVBUS UDPi pull-up detection Note 2 Connect detection with the full speed function (pull-up resistor)

1000 RHDET_PULL In full-speed mode, the power supply

voltage range of pull-up resistors connected to the USB function module is between 3.0 V and 3.6 V. 1.575 kΩ 1001 1010 UDMi pull-up detection Note 2 Connect detection with the low-speed (pull-up resistor)

1000 RHDET_PULL In low-speed mode, the power supply

voltage range of pull-up resistors connected to the USB function module is between 3.0 V and 3.6 V. 1.575 kΩ 1001 1010 UDMi sink current detection Note 2 Connect detection with the BC1.2 portable device (sink resistor)

1000 IHDET_SINK 25 µA

Notes 1. If the voltage output from UDPi or UDMi exceeds the range of the MAX and MIN values prescribed in this specification, DPCUSDETi (bit 8) and DMCUSDETi (bit 9) of the USBBCOPTi register are set to 1. 2. If the pull-up resistance or sink current prescribed in this specification is applied to UDPi or UDMi, DPCUSDETi (bit 8) and DMCUSDETi (bit 9) of the USBBCOPTi register are set to 1. Remark i = 0, 1

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 45 of 53 Mar 29, 2019 (4) BC option standard (Function) Parameter Symbol Conditions MIN. TYP. MAX. Unit UDPi/UDMi input reference voltage (UVBUS divider ratio)

VDOUEi = 0 VDSELi [3:0]

0000 VDDET0 27 32 37 % UVBUS

0001 VDDET1 29 34 39 % UVBUS

0010 VDDET2 32 37 42 % UVBUS

0011 VDDET3 35 40 45 % UVBUS

0100 VDDET4 38 43 48 % UVBUS

0101 VDDET5 41 46 51 % UVBUS

0110 VDDET6 44 49 54 % UVBUS

0111 VDDET7 47 52 57 % UVBUS

1000 VDDET8 51 56 61 % UVBUS

1001 VDDET9 55 60 65 % UVBUS

1010 VDDET10 59 64 69 % UVBUS

1011 VDDET11 63 68 73 % UVBUS

1100 VDDET12 67 72 77 % UVBUS

1101 VDDET13 71 76 81 % UVBUS

1110 VDDET14 75 80 85 % UVBUS

1111 VDDET15 79 84 89 % UVBUS

Remark i = 0, 1

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 46 of 53 Mar 29, 2019

2.6 Analog Characteristics

2.6.1 A/D converter characteristics

Classification of A/D converter characteristics Input channel Reference Voltage Reference voltage (+) = AVREFP Reference voltage (−) = AVREFM Reference voltage (+) = VDD Reference voltage (−) = VSS Reference voltage (+) = VBGR Reference voltage (−) = AVREFM ANI16, ANI17 Refer to 2.6.1 (2). Internal reference voltage Temperature sensor output voltage Refer to 2.6.1 (1). − (1) When AVREF (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage ( −) = AVREFM/ANI1 (ADREFM = 1), target pin : ANI2 to ANI5, internal reference voltage, and temperature sensor output voltage (TA = −40 to +85°C, 2.7 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (−) = AVREFM = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 8 10 bit Overall errorNote 1 AINL 10-bit resolution AVREFP = VDD Note 2 2.7 V ≤ VDD ≤ 5.5 V 1.2 ±3.5 LSB Analog input voltage VAIN ANI2 to ANI7 0 AVREFP V Internal reference voltage (2.7 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode) VBGR Note 3 V Temperature sensor output voltage (2.7 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode) VTMPS25 Note 3 V Notes 1. Excludes quantization error (±1/2 LSB). 2. When AVREFP < VDD, the MAX. values are as follows. Overall error: Add ±1.0 LSB to the MAX. value when AVREFP = VDD. 3. Refer to 2.6.2 Temperature sensor/internal reference voltage characteristics.

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 47 of 53 Mar 29, 2019 (2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage ( −) = AVREFM/ANI1 (ADREFM = 1), target pin : ANI16, ANI17 (TA = −40 to +85°C, 2.7 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (−) = AVREFM = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 8 10 bit Overall errorNote 1 AINL 10-bit resolution AVREFP = VDD Note 2 2.7 V ≤ VDD ≤ 5.5 V 1.2 ±5.0 LSB Analog input voltage VAIN ANI16, ANI17 0 AVREFP and VDD V Notes 1. Excludes quantization error (±1/2 LSB). 2. When AVREFP < VDD, the MAX. values are as follows. Overall error: Add ±4.0 LSB to the MAX. value when AVREFP = VDD. (3) Reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), Reference voltage ( −) = VSS (ADREFM = 0), target ANI pin : ANI0 to ANI5, ANI16, ANI17, internal reference voltage, and temperature sensor output voltage (TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = VDD, Reference voltage (−) = VSS) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 8 10 bit Overall errorNote 1 AINL 10-bit resolution 2.7 V ≤ VDD ≤ 5.5 V 1.2 ±7.0 LSB Analog input voltage VAIN ANI0 to ANI5, ANI16, ANI17 0 VDD V Internal reference voltage (2.7 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode) VBGR Note 2 V Temperature sensor output voltage (2.7 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode) VTMPS25 Note 2 V Notes 1. Excludes quantization error (±1/2 LSB). 2. Refer to 2.6.2 Temperature sensor/internal reference voltage characteristics.

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 48 of 53 Mar 29, 2019 (4) When Reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), Reference voltage (−) = AVREFM/ANI1 (ADREFM = 1), target pin : ANI0 to ANI5, ANI16, ANI17 (TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = VBGR Note 1, Reference voltage (−) = AVREFM = 0 V, HS (high-speed main) mode) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 8 Bit Analog input voltage VAIN 0 VBGR Note 1 V Notes 1. Refer to 2.6.2 Temperature sensor/internal reference voltage characteristics.

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 49 of 53 Mar 29, 2019

2.6.2 Temperature sensor/internal reference voltage characteristics

(TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V, HS (high-speed main) mode) Parameter Symbol Conditions MIN. TYP. MAX. Unit Temperature sensor output voltage VTMPS25 Setting ADS register = 80H, TA = +25°C 1.05 V Internal reference voltage VBGR Setting ADS register = 81H 1.38 1.45 1.5 V Temperature coefficient FVTMPS Temperature sensor that depends on the temperature −3.6 mV/°C Operation stabilization wait time tAMP 5 µs

2.6.3 POR circuit characteristics

(TA = −40 to +85°C, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage VPOR Power supply rise time 1.47 1.51 1.55 V VPDR Power supply fall time 1.46 1.50 1.54 V Minimum pulse widthNote TPW 300 µs Note Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time required for a POR reset from when V DD exceeds below 0.7 V to when V DD exceeds VPOR while STOP mode is entered or the main system clock (f MAIN) is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control register (CSC).

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 50 of 53 Mar 29, 2019

2.6.4 LVD circuit characteristics

LVD Detection Voltage of Reset Mode and Interrupt Mode (TA = −40 to +85°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage Supply voltage level VLVD0 Power supply rise time 3.98 4.06 4.14 V Power supply fall time 3.90 3.98 4.06 V VLVD1 Power supply rise time 3.68 3.75 3.82 V Power supply fall time 3.60 3.67 3.74 V VLVD2 Power supply rise time 3.07 3.13 3.19 V Power supply fall time 3.00 3.06 3.12 V VLVD3 Power supply rise time 2.96 3.02 3.08 V Power supply fall time 2.90 2.96 3.02 V VLVD4 Power supply rise time 2.86 2.92 2.97 V Power supply fall time 2.80 2.86 2.91 V VLVD5 Power supply rise time 2.76 2.81 2.87 V Power supply fall time 2.70 2.75 2.81 V Minimum pulse width tLW 300 µs Detection delay time tLD 300 µs LVD Detection Voltage of Interrupt & Reset Mode (TA = −40 to +85°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Interrupt and reset mode VLVDC0 VPOC2, VPOC1, VPOC0 = 0, 1, 0, falling reset voltage 2.40 2.45 2.50 V VLVDC1 LVIS1, LVIS0 = 1, 0 Rising release reset voltage 2.56 2.61 2.66 V Falling interrupt voltage 2.50 2.55 2.60 V VLVDC2 LVIS1, LVIS0 = 0, 1 Rising release reset voltage 2.66 2.71 2.76 V Falling interrupt voltage 2.60 2.65 2.70 V VLVDC3 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 3.68 3.75 3.82 V Falling interrupt voltage 3.60 3.67 3.74 V VLVDD0 VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage 2.70 2.75 2.81 V VLVDD1 LVIS1, LVIS0 = 1, 0 Rising release reset voltage 2.86 2.92 2.97 V Falling interrupt voltage 2.80 2.86 2.91 V VLVDD2 LVIS1, LVIS0 = 0, 1 Rising release reset voltage 2.96 3.02 3.08 V Falling interrupt voltage 2.90 2.96 3.02 V VLVDD3 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 3.98 4.06 4.14 V Falling interrupt voltage 3.90 3.98 4.06 V

2.6.5 Power supply voltage rising slope characteristics

(TA = −40 to +85°C, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Power supply voltage rising slope SVDD 54 V/ms Caution Make sure to keep the internal reset state by the LVD circuit or an external reset until V DD reaches the operating voltage range shown in 2.4 AC Characteristics.

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 51 of 53 Mar 29, 2019

2.7 RAM Data Retention Characteristics

(TA = −40 to +85°C, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention supply voltage VDDDR 1.46Note 5.5 V Note The value depends on the POR detection voltage. When the voltage drops, the data is retained before a POR reset is effected, but data is not retained when a POR reset is effected.

2.8 Flash Memory Programming Characteristics

(TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit CPU/peripheral hardware clock frequency fCLK 2.7 V ≤ VDD ≤ 5.5 V 1 24 MHz Number of code flash rewrites Cerwr Retaining years: 20 years TA = +85°C 1,000 Times Number of data flash rewrites Notes 1, 2, 3 Retaining years: 1 year TA = +25°C 1,000,000 Retaining years: 5 years TA = +85°C 100,000 Retaining years: 20 years TA = +85°C 10,000 Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite. 2. When using flash memory programmer and Renesas Electronics self programming library. 3. These specifications show the characterist ics of the flash memory and the results obtained from Renesas Electronics reliability testing.

2.9 Dedicated Flash Memory Programmer Communication (UART)

(TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate During serial programming 115,200 1,000,000 bps

R9A02G015 2. ELECTRICAL SPECIFICATIONS R19DS0101EJ0100 Rev.1.00 Page 52 of 53 Mar 29, 2019

2.10 Timing Specs for Switching Flash Memory Programming Modes

(TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit How long from when an external reset ends until the initial communication settings are specified tSUINIT POR and LVD reset must end before the external reset ends. 100 ms How long from when the TOOL0 pin is placed at the low level until an external reset ends tSU POR and LVD reset must end before the external reset ends. 10 µs How long the TOOL0 pin must be kept at the low level after an external reset ends (excluding the processing time of the firmware to control the flash memory) tHD POR and LVD reset must end before the external reset ends. 1 ms <1> The low level is input to the TOOL0 pin. <2> The external reset ends (POR and LVD reset must end before the external reset ends.). <3> The TOOL0 pin is set to the high level. <4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting. Remark tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from when the resets end. tSU: How long from when the TOOL0 pin is placed at the low level until an external reset ends tHD: How long to keep the TOOL0 pin at the low level from when the external and internal resets end (excluding the processing time of the firmware to control the flash memory) RESETB

R9A02G015 3. PACKAGE DRAWING R19DS0101EJ0100 Rev.1.00 Page 53 of 53 Mar 29, 2019 3. PACKAGE DRAWINGS 32-pin QFN (4 x 4 mm)

All trademarks and registered trademarks are the property of their respective owners. C - 1 Revision History R9A02G015 Data Sheet Rev. Date Description Page Summary

0.10 Oct 31, 2018 — First Draft of the Preliminary Data Sheet

0.20 Nov 9, 2018 15 Updated section 2.3.2 44-45 Updated section 2.5.3 0.90 Feb 15, 2019 15 Updated section 2.3.2 42-43 Updated section 2.5.3

53 Updated section 3

1.00 Mar 29, 2019 — First Edition issued. SuperFlash(R) is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. NOTE) This product uses SuperFlash(R) technology licensed from Silicon Storage Technology, inc.

http://www.renesas.com Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics Corporation TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan Renesas Electronics America Inc. 1001 Murphy Ranch Road, Milpitas, CA 95035, U.S.A. Renesas Electronics Canada Limited

9251 Yonge Street, Suite 8309 Richmond Hill, Ontario Canada L4C 9T3

Tel: +1-905-237-2004 Renesas Electronics Europe GmbH Arcadiastrasse 10, 40472 Düsseldorf, Germany Renesas Electronics (China) Co., Ltd. Room 101-T01, Floor 1, Building 7, Yard No. 7, 8th Street, Shangdi, Haidian District, Beijing 100085, China Tel: +86-10-8235-1155, Fax: +86-10-8235-7679 Renesas Electronics (Shanghai) Co., Ltd. Unit 301, Tower A, Central Towers, 555 Langao Road, Putuo District, Shanghai 200333, China Tel: +86-21-2226-0888, Fax: +86-21-2226-0999 Renesas Electronics Hong Kong Limited Unit 1601-1611, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong Tel: +852-2265-6688, Fax: +852 2886-9022 Renesas Electronics Taiwan Co., Ltd. 13F, No. 363, Fu Shing North Road, Taipei 10543, Taiwan Tel: +886-2-8175-9600, Fax: +886 2-8175-9670 Renesas Electronics Singapore Pte. Ltd.

80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre, Singapore 339949

Tel: +65-6213-0200, Fax: +65-6213-0300 Renesas Electronics Malaysia Sdn.Bhd. Unit No 3A-1 Level 3A Tower 8 UOA Business Park, No 1 Jalan Pengaturcara U1/51A, Seksyen U1, 40150 Shah Alam, Selangor, Malaysia Renesas Electronics India Pvt. Ltd. No.777C, 100 Feet Road, HAL 2nd Stage, Indiranagar, Bangalore 560 038, India Tel: +91-80-67208700 Renesas Electronics Korea Co., Ltd. 17F, KAMCO Yangjae Tower, 262, Gangnam-daero, Gangnam-gu, Seoul, 06265 Korea SALES OFFICES © 2019 Renesas Electronics Corporation. All rights reserved. Colophon 8.0 (Rev.4.0-1 November 2017) Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by you or third parties arising from the use of these circuits, software, or information. 2. Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims involving patents, copyrights, or other intellectual property rights of third parties, by or arising from the use of Renesas Electronics products or technical information described in this document, including but not limited to, the product data, drawings, charts, programs, algorithms, and application examples. 3. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. 4. You shall not alter, modify, copy, or reverse engineer any Renesas Electronics product, whether in whole or in part. Renesas Electronics disclaims any and all liability for any losses or damages incurred by you or third parties arising from such alteration, modification, copying or reverse engineering. 5. Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The intended applications for each Renesas Electronics product depends on the product’s quality grade, as indicated below. "Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; industrial robots; etc. "High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication equipment; key financial terminal systems; safety control equipment; etc. Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are not intended or authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems; surgical implantations; etc.), or may cause serious property damage (space system; undersea repeaters; nuclear power control systems; aircraft control systems; key plant systems; military equipment; etc.). Renesas Electronics disclaims any and all liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or other Renesas Electronics document. 6. When using Renesas Electronics products, refer to the latest product information (data sheets, user’s manuals, application notes, “General Notes for Handling and Using Semiconductor Devices” in the reliability handbook, etc.), and ensure that usage conditions are within the ranges specified by Renesas Electronics with respect to maximum ratings, operating power supply voltage range, heat dissipation characteristics, installation, etc. Renesas Electronics disclaims any and all liability for any malfunctions, failure or accident arising out of the use of Renesas Electronics products outside of such specified ranges. 7. Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics products, semiconductor products have specific characteristics, such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Unless designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are not subject to radiation resistance design. You are responsible for implementing safety measures to guard against the possibility of bodily injury, injury or damage caused by fire, and/or danger to the public in the event of a failure or malfunction of Renesas Electronics products, such as safety design for hardware and software, including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult and impractical, you are responsible for evaluating the safety of the final products or systems manufactured by you. 8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. You are responsible for carefully and sufficiently investigating applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive, and using Renesas Electronics products in compliance with all these applicable laws and regulations. Renesas Electronics disclaims any and all liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. Renesas Electronics products and technologies shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. You shall comply with any applicable export control laws and regulations promulgated and administered by the governments of any countries asserting jurisdiction over the parties or transactions. 10. It is the responsibility of the buyer or distributor of Renesas Electronics products, or any other party who distributes, disposes of, or otherwise sells or transfers the product to a third party, to notify such third party in advance of the contents and conditions set forth in this document. 11. This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics. 12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products. (Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its directly or indirectly controlled subsidiaries. (Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.

Product Information

R9A02G015 specifications and overview.

Summary

ASSP (USB Power Delivery Controller) Mar 29, 2019

Description

ASSP (USB Power Delivery Controller) Mar 29, 2019

Source title R9A02G015 Datasheet(PDF) - Renesas Technology Corp

Related Parts

More parts from the same family.

Browse manufacturer