R8C10

R8C10 RENESAS | Alldatasheet

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RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / R8C /Tiny SERIES R8C/10 Group16 Rev. 1.20 Revision date: Jan 27, 2006 Hardware Manual www.renesas.com REJ09B0019-0120 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp. website (http://www.renesas.com).

Keep safety first in your circuit designs! Notes regarding these materials 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with ap- propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non- flammable material or (iii) prevention against any malfunction or mishap. 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, pro- grams, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, pro- grams and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers con- tact Renesas Technology Corp. or an authorized Renesas Technology Corp. product dis- tributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by vari- ous means, including the Renesas Technology Corp. Semiconductor home page (http:// www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all informa- tion as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liabil- ity or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or repro- duce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be im- ported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/ or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.

1. Introduction This hardware manual provides detailed information on the R8C/10 Group of microcomputers. Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers. 2. Register Diagram The symbols, and descriptions, used for bit function in each register are shown below. Blank:Set to “0” or “1” according to the application 0: Set to “0” 1: Set to “1” X: Nothing is assigned RW: Read and write RO: Read only WO: Write only −: Nothing is assigned

• Reserved bit Reserved bit. Set to specified value.
• Nothing is assigned Nothing is assigned to the bit concerned. As the bit may be use for future functions, set to “0” when writing to this bit.
• Do not set to this value The operation is not guaranteed when a value is set.
• Function varies depending on mode of operation Bit function varies depending on peripheral function mode. Refer to respective register for each mode. Follow the text in each manual for binary and hexadecimal notations. X X X r e g i s t e r S y m b o lA d d r e s sA f t e r r e s e t X X XX X Bit NameBit symbol RW b 3b 2b X X X B i t 1 0 : X X X X X X A v o i d t h i s s e t t i n g X X X b 1 b 0 XXX1 X X X 0 XXX4 R e s e r v e d B i t XXX5 X X X 7 X X X 6 Function N o t h i n g i s a s s i g n e d . W h e n w r i t e s h o u l d s e t t o W h e n r e a d i t s c o n t e n t i s i n d e t e r m i n a t e XXX Bit Function varies depending on each operation mode Must set to “0” ( b 3 ) (b2) RW RW RW R W W O R W RO X X X B i t 0: XXX 1: XXX

Appendix 2 Connecting Examples for Serial Writer and Appendix 3 Example of Oscillation Evaluation Circuit.. 178

W a t c h d o g t i m e r s t a r t r e g i s t e rW D T S5 4 W a t c h d o g t i m e r c o n t r o l r e g i s t e rW D C5 4 P r o c e s s o r m o d e r e g i s t e r 0P M 03 1 System clock control register 0 CM0 19 S y s t e m c l o c k c o n t r o l r e g i s t e r 1C M 11 9 Address match interrupt enable register AIER 52 P r o t e c t r e g i s t e rP R C R3 0 P r o c e s s o r m o d e r e g i s t e r 1P M 13 1 O s c i l l a t i o n s t o p d e t e c t i o n r e g i s t e rO C D2 0 I N T 0 i n p u t f i l t e r s e l e c t r e g i s t e rI N T 0 F4 6 0 0 0 01 C 1 D 1 C 1 D 1 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C 16 002D 16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C 16 003D 16 003E16 003F16 A d d r e s s R e g i s t e rS y m b o l A d d r e s s m a t c h i n t e r r u p t r e g i s t e r 0R M A D 05 2 A d d r e s s m a t c h i n t e r r u p t r e g i s t e r 1R M A D 15 2 W a t c h d o g t i m e r r e s e t r e g i s t e rW D T R5 4 P a g e A d d r e s s R e g i s t e rS y m b o l P a g e U A R T 0 t r a n s m i t i n t e r r u p t c o n t r o l r e g i s t e r S 0 T I C3 9 U A R T 0 r e c e i v e i n t e r r u p t c o n t r o l r e g i s t e r S 0 R I C3 9 U A R T 1 t r a n s m i t i n t e r r u p t c o n t r o l r e g i s t e r S 1 T I C3 9 U A R T 1 r e c e i v e i n t e r r u p t c o n t r o l r e g i s t e r S 1 R I C3 9 K e y i n p u t i n t e r r u p t c o n t r o l r e g i s t e rK U P I C3 9 A D c o n v e r s i o n i n t e r r u p t c o n t r o l r e g i s t e rA D I C3 9 I N T 1 i n t e r r u p t c o n t r o l r e g i s t e rI N T 1 I C3 9 I N T 2 i n t e r r u p t c o n t r o l r e g i s t e rI N T 2 I C3 9 I N T 0 i n t e r r u p t c o n t r o l r e g i s t e rI N T 0 I C3 9 I N T 3 i n t e r r u p t c o n t r o l r e g i s t e rI N T 3 I C3 9 0 0 4 01 C 1 D 1 C 1 D 1 0 0 6 01 C 1 D 1 C 1 D 1 T i m e r X i n t e r r u p t c o n t r o l r e g i s t e rT X I C3 9 T i m e r Y i n t e r r u p t c o n t r o l r e g i s t e rT Y I C3 9 T i m e r Z i n t e r r u p t c o n t r o l r e g i s t e rT Z I C3 9 T i m e r C i n t e r r u p t c o n t r o l r e g i s t e rT C I C3 9 Blank columns are all reserved space. No use is allowed.

A d d r e s s R e g i s t e rS y m b o l P a g e 0 0 8 01 C 1 D 1 C 1 D 1 0 0 A 01 A A A A A A A A A A A A C 1 A D 1 A A B B B B B B B B B B B B B C 1 B D 1 B B T i m e r X r e g i s t e r r e g i s t e rT X5 7 T i m e r Y s e c o n d a r y r e g i s t e rT Y S C6 6 E x t e r n a l i n p u t e n a b l e r e g i s t e rI N T E N4 6 Pr e s c a l e r Y r e g i s t e rP R E Y6 6 U A R T 0 t r a n s m i t / r e c e i v e m o d e r e g i s t e r U 0 M R9 2 U A R T 0 r e c e i v e b u f f e r r e g i s t e r U 0 R B9 1 U A R T 1 t r a n s m i t / r e c e i v e m o d e r e g i s t e r U 1 M R9 2 U A R T 1 t r a n s m i t b u f f e r r e g i s t e rU 1 T B9 1 U A R T 1 r e c e i v e b u f f e r r e g i s t e r U 1 R B9 1 U A R T 0 b i t r a t e g e n e r a t o r U 0 B R G9 1 U A R T 0 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 0 U 0 C 09 2 U A R T 0 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 1 U 0 C 19 3 U A R T 1 b i t r a t e r e g i s t e rU 1 B R G9 1 U A R T 1 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 0 U 1 C 09 2 U A R T 1 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 1 U 1 C 19 3 T i m e r Y , Z m o d e r e g i s t e rT Y Z M R6 5 / 7 3 T i m e r Y p r i m a r y r e g i s t e rT Y P R6 6 T i m e r Y , Z w a v e f o r m o u t p u t c o n t r o l r e g i s t e r P U M6 7 / 7 5 Pr e s c a l e r Z r e g i s t e rP R E Z7 4 T i m e r Z s e c o n d a r y r e g i s t e rT Z S C7 4 T i m e r Z p r i m a r y r e g i s t e rT Z P R7 4 T i m e r Y , Z o u t p u t c o n t r o l r e g i s t e rT Y Z O C6 6 / 7 4 T i m e r X m o d e r e g i s t e rT X M R5 6 Pr e s c a l e r X r e g i s t e rP R E X5 7 T i m e r c o u n t s o u r c e s e t t i n g r e g i s t e rT C S S5 7 T i m e r C r e g i s t e rT C8 7 K e y i n p u t e n a b l e r e g i s t e rK I E N5 0 T i m e r C c o n t r o l r e g i s t e r 0T C C 08 7 T i m e r C c o n t r o l r e g i s t e r 1T C C 18 7 C a p t u r e r e g i s t e rT M 08 7 U A R T t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 2 U C O N9 3 U A R T 0 t r a n s m i t b u f f e r r e g i s t e rU 0 T B9 1 A d d r e s s R e g i s t e rS y m b o l P a g e 0 0 C 01 C C C C C C C C C C C C C 1 C D 1 C C D D D D D D D D D D D D D C 1 D D 1 D D 0 0 E 01 E E E E E E E E E E E E C 1 E D 1 E E F F F F F F F F F F F F F C 1 F D 1 F F B B B B B A D r e g i s t e rA D1 0 7 AD c o n t r o l r e g i s t e r 0A D C O N 01 0 6 A D c o n t r o l r e g i s t e r 2A D C O N 21 0 7 A D c o n t r o l r e g i s t e r 1 A D C O N 11 0 6 P o r t P 0 r e g i s t e rP 01 2 0 P o r t P 0 d i r e c t i o n r e g i s t e rP D 01 2 0 P o r t P 1 r e g i s t e rP 11 2 0 P o r t P 1 d i r e c t i o n r e g i s t e rP D 11 2 0 P o r t P 3 r e g i s t e rP 31 2 0 P o r t P 3 d i r e c t i o n r e g i s t e rP D 31 2 0 P o r t P 4 r e g i s t e rP 41 2 0 P o r t P 4 d i r e c t i o n r e g i s t e rP D 41 2 0 P u l l - u p c o n t r o l r e g i s t e r 0 P U R 01 2 1 P o r t P 1 d r i v e c a p a c i t y c o n t r o l r e g i s t e r D R R1 2 1 P u l l - u p c o n t r o l r e g i s t e r 1 P U R 11 2 1 F l a s h m e m o r y c o n t r o l r e g i s t e r 1 F M R 11 4 7 F l a s h m e m o r y c o n t r o l r e g i s t e r 0 F M R 01 4 6 F l a s h m e m o r y c o n t r o l r e g i s t e r 4 F M R 41 4 7 Blank columns are all reserved space. No use is allowed.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.20 Jan 27, 2006 page 1 of 180 REJ09B0019-0120 REJ09B0019-0120 Rev.1.20 Jan 27, 2006 1. Overview This MCU is built using the high-performance silicon gate CMOS process using a R8C/Tiny Series CPU core and is packaged in a 32-pin plastic molded LQFP. This MCU operates using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, it is capable of executing instructions at high speed.

1.1 Applications

Electric household appliance, office equipment, housing equipment (sensor, security), general industrial equipment, audio, etc.

Rev.1.20 Jan 27, 2006 page 2 of 180 REJ09B0019-0120 R8C/10 Group 1. Overview Table 1.1 Performance outline

1.2 Performance Overview

Table 1.1. lists the performance outline of this MCU. Item Performance CPU Number of basic instructions 89 instructions Minimum instruction execution time62.5 ns (f(XIN) = 16 MHZ, VCC = 3.0 to 5.5 V) 100 ns (f(XIN) = 10 MHZ, VCC = 2.7 to 5.5 V) Operating mode Single-chip Address space 1M bytes Memory capacity See Table 1.2 “Product List” Peripheral Port Input/Output: 22 (including LED drive port), Input: 2 function LED drive port I/O port: 8 Timer Timer X: 8 bits x 1 channel, Timer Y: 8 bits x 1 channel, Timer Z: 8 bits x 1 channel (Each timer equipped with 8-bit prescaler) Timer C: 16 bits x 1 channel (Input capture circuit) Serial interface •1 channel Clock synchronous, UART

• 1 channel UART A/D converter 10-bit A/D converter: 1 circuit, 8 channels Watchdog timer 15 bits x 1 (with prescaler) Interrupt Internal: 9 factors, External: 5 factors, Software: 4 factors, Priority level: 7 levels Clock generation circuit 2 circuits
• Main clock generation circuit (Equipped with a built-in feedback resistor)
• On-chip oscillator Oscillation stop detection functionMain clock oscillation stop detection function Electrical Supply voltage V CC = 3.0 to 5.5 V (f(XIN) = 16 MHZ) characteristics VCC = 2.7 to 5.5 V (f(XIN) = 10 MHZ) Power consumption Typ. 8mA (VCC = 5.0 V, (f(XIN) = 16MHZ) Typ. 5mA (VCC = 3.0 V, (f(XIN) = 10MHZ) Typ. 35µA (VCC = 3.0 V, Wait mode, Peripheral clock off) Typ. 0.7µA (VCC = 3.0 V, Stop mode) Flash memory Program/erase supply voltageVCC = 2.7 to 5.5 V Program/erase endurance 100 times Operating ambient temperature -20 to 85 °C -40 to 85 °C (D-version) Package 32-pin plastic mold LQFP

Rev.1.20 Jan 27, 2006 page 3 of 180 REJ09B0019-0120 R8C/10 Group 1. Overview

1.3 Block Diagram

Figure 1.1 shows this MCU block diagram. Figure 1.1 Block Diagram T i m e r X b i t s T i m e r Y b i t s T i m e r Z b i t s T i m e r C b i t s W a t c h d o g t i m e r b i t s M e m o r y R O M R 8 C / T i n y S e r i e s C P U c o r e I / O p o r t P o r t P 0 Port P1 P o r t P 3 M u l t i p l i e r System clock generator XI N - XO U T O n c h i p o s c i l l a t o r U A R T b i t s c h a n n e l Port P4 1 2 Pe r i p h e r a l f u n c t i o n s U A R T o r C l o c k s y n c h r o n o u s s e r i a l I O b i t s c h a n n e l A D c o n v e r t e r b i t s c h a n n e l s RAM NOTES: 1. ROM size depends on MCU type. 2. RAM size depends on MCU type. R 0 LR 0 H R1H R1L R 2 R 3 A 0 FB SB I S P USP INTB P C FLG T i m e r (2)

Rev.1.20 Jan 27, 2006 page 4 of 180 REJ09B0019-0120 R8C/10 Group 1. Overview

1.4 Product Information

Table 1.2 lists the product inforamation. Table 1.2 Product Information RAM capacityROM capacity Package type RemarksType No. As of January 2006 Flash memory versionR5F21102FP PLQP0032GB-A8K bytes 512 bytes PLQP0032GB-A12K bytes 768 bytes PLQP0032GB-A16K bytes 1K bytes R5F21103FP R5F21104FP R5F21102DFP PLQP0032GB-A8K bytes 512 bytes PLQP0032GB-A12K bytes 768 bytes PLQP0032GB-A16K bytes 1K bytes R5F21103DFP R5F21104DFP D version Figure 1.2 Type No., Memory Size, and Package Package type: FP : PLQP0032GB-A ROM capacity: 2 : 8 KBytes. 3 : 12 KBytes. 4 : 16 KBytes. Memory type: F: Flash memory version T y p e N o .R 5 F 2 11 04D F P R8C/10 group R8C/Tiny series Classification: D: Operating ambient temperature –40 °C to 85 °C No symbol: Operating ambient temperature –20 °C to 85 °C Renesas MCU Renesas semiconductors

Rev.1.20 Jan 27, 2006 page 5 of 180 REJ09B0019-0120 R8C/10 Group 1. Overview Figure 1.3 Pin Assignments (Top View) PIN CONFIGURATION (top view) 1 2 3 4 5 6 7 8 1 0 1 1 1 2 1 3 1 4 1 5 1 6 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 3 2 3 1 3 0 R 8 C / 1 0 G r o u pXI N / P 46 XO U T/ P 47 VS S R E S E T VC C C N VS S P 17/ I N T1/ C N T R 0 P 16/ C L K0 P15/RxD0 P 14/ T x D 0 P 37/ T x D 1 0/ R x D 1 P 30/ C N T R 0 P 33/ I N T3/ T C I N P 31/ T ZO U T P 32/ I N T2/ C N T R 1 I VC C A VS S A VC C / VR E F P03/AN4 P 02/ A N 5 P 01/ A N 6 P 00/ A N 7/T x D 1 P 06/ A N 1 P05/AN2 P 04/ A N 3 P45/INT0 P 10/ K I0 P 11/ K I1 P 12/ K I2 P 13/ K I3 P 07/ A N 0 M O D E NOTES: 1. P47 functions only as an input port. 2. When using On-chip debugger, do not use pins P00/AN7/TxD11 and P37/TxD10/RxD1. 3. Do not connect IVcc to Vcc.

1.5 Pin Assignment

Figure 1.3 shows the pin Assignments (top view).

Rev.1.20 Jan 27, 2006 page 6 of 180 REJ09B0019-0120 R8C/10 Group 1. Overview Signal name Pin name I/O type Power supply Vcc, I input Vss IVcc IVcc O Analog power AVcc, I supply input AVss Reset input RESET I CNVss CNVss I MODE MODE I Main clock input XIN I Main clock output XOUT O INT interrupt input INT0 to INT3 I Key input interrupt KI0 to KI3 I CNTR 0 O Timer Y CNTR 1 I/O Timer Z TZ OUT O Timer C TC IN I Serial interface CLK0 I/O RxD 0, RxD1 I TxD 0, TxD10,O TxD 11 Reference voltage VREF I input A/D converter AN 0 to AN7 I I/O port P0 0 to P07, I/O P10 to P17, P30 to P33, P37, P45 Input port P4 6, P47 I Function Apply 2.7 V to 5.5 V to the Vcc pin. Apply 0 V to the Vss pin. This pin is to stabilize internal power supply. Connect this pin to Vss via a capacitor (0.1 µF). Do not connect to Vcc. Power supply input pins for A/D converter. Connect the AVcc pin to Vcc. Connect the AVss pin to Vss. Connect a capacitor between pins AVcc and AVss. Input “L” on this pin resets the MCU. Connect this pin to Vss via a resistor.(1) Connect this pin to Vcc via a resistor. These pins are provided for the main clock generat- ing circuit I/O. Connect a ceramic resonator or a crys- tal oscillator between the XIN and XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open.______ INT interrupt input pins. Key input interrupt pins. Timer X I/O pin Timer X output pin Timer Y I/O pin Timer Z output pin Timer C input pin Transfer clock I/O pin. Serial data input pins. Serial data output pins. Reference voltage input pin for A/D converter. Con- nect the VREF pin to Vcc. Analog input pins for A/D converter These are 8-bit CMOS I/O ports. Each port has an I/O select direction register, allowing each pin in that port to be directed for input or output individually. Any port set to input can select whether to use a pull- up resistor or not by program. 0 to P17 also function as LED drive ports. Port for input-only.

1.6 Pin Description

Table 1.3 shows the pin description Table 1.3 Pin description NOTES : 1. Refer to "19.8 Noise" for the connecting reference resistor value.

R8C/10 Group 2. Central Processing Unit (CPU) Rev.1.20 Jan 27, 2006 page 7 of 180 REJ09B0019-0120 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. Two sets of register banks are provided.

2.1 Data Registers (R0, R1, R2 and R3)

R0 is a 16-bit register for transfer, arithmetic and logic operations. The same applies to R1 to R3. The R0 can be split into high-order bit (R0H) and low-order bit (R0L) to be used separately as 8-bit data registers. The same applies to R1H and R1L as R0H and R0L. R2 can be combined with R0 to be used as a 32-bit data register (R2R0). The same applies to R3R1 as R2R0. Data registers(1) Address registers(1) Frame base registers(1) Program counter Interrupt table register User stack pointer Interrupt stack pointer Static base register Flag register N O T E S : A r e g i s t e r b a n k c o m p r i s e s t h e s e r e g i s t e r s T w o s e t s o f r e g i s t e r b a n k s a r e p r o v i d e d R 0 H ( h i g h - o r d e r o f R 0 ) b 1 5 b 8 b7 b 0 R 3 I N T B H U S P ISP SB CDZSBOIUI P L R 0 L ( h i g h - o r d e r o f R 0 ) R1H (high-order of R1)R1L (high-order of R1) R 2 b 3 1 R 3 R 2 A 1 FB b 1 9 I N T B L b 1 5 b 0 P C b19 b0 b 1 5 b 0 FLG b 1 5 b 0 b 1 5 b 0 b7 b8 Reserved bit Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved bit Processor interrupt priority level The 4-high order bits of INTB are INTBH and the 16-low bits of INTB are INTBL. Figure 2.1 CPU Register

R8C/10 Group 2. Central Processing Unit (CPU) Rev.1.20 Jan 27, 2006 page 8 of 180 REJ09B0019-0120

2.2 Address Registers (A0 and A1)

A0 is a 16-bit register for address register indirect addressing and address register relative address- ing. They also are used for transfer, arithmetic and logic operations. The same applies to A1 as A0. A0 can be combined with A0 to be used as a 32-bit address register (A1A0).

2.3 Frame Base Register (FB)

FB is a 16-bit register for FB relative addressing.

2.4 Interrupt Table Register (INTB)

INTB is a 20-bit register indicates the start address of an interrupt vector table.

2.5 Program Counter (PC)

PC, 20 bits wide, indicates the address of an instruction to be executed.

2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)

The stack pointer (SP), USP and ISP, are 16 bits wide each. The U flag of FLG is used to switch between USP and ISP.

2.7 Static Base Register (SB)

SB is a 16-bit register for SB relative addressing.

2.8 Flag Register (FLG)

FLG is a 11-bit register indicating the CPU state.

2.8.1 Carry Flag (C)

The C flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic logic unit.

2.8.2 Debug Flag (D)

The D flag is for debug only. Set to “0”.

2.8.3 Zero Flag (Z)

The Z flag is set to “1” when an arithmetic operation resulted in 0; otherwise, “0”.

2.8.4 Sign Flag (S)

The S flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, “0”.

2.8.5 Register Bank Select Flag (B)

The register bank 0 is selected when the B flag is “0”. The register bank 1 is selected when this flag is set to “1”.

2.8.6 Overflow Flag (O)

The O flag is set to “1” when the operation resulted in an overflow; otherwise, “0”.

2.8.7 Interrupt Enable Flag (I)

The I flag enables a maskable interrupt. An interrupt is disabled when the I flag is set to “0”, and are enabled when the I flag is set to “1”. The I flag is set to “0” when an interrupt request is acknowledged.

2.8.8 Stack Pointer Select Flag (U)

ISP is selected when the U flag is set to “0”, USP is selected when the U flag is set to “1”. The U flag is set to “0” when a hardware interrupt request is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed.

2.8.9 Processor Interrupt Priority Level (IPL)

IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has greater priority than IPL, the interrupt is enabled.

2.8.10 Reserved Bit

When write to this bit, set to “0”. When read, its content is indeterminate.

R8C/10 Group 4. Special Function Register (SFR) Rev.1.20 Jan 27, 2006 page 10 of 180 REJ09B0019-0120 Watchdog timer start register WDTS XX 16 W a t c h d o g t i m e r c o n t r o l r e g i s t e rW D C0 0 0 1 1 1 1 12 P r o c e s s o r m o d e r e g i s t e r 0P M 0X X X X0X 0 02 System clock control register 0 CM0 01101000 2 System clock control register 1 CM1 00100000 2 A d d r e s s m a t c h i n t e r r u p t e n a b l e r e g i s t e rA I E RX X X X X X 0 02 P r o t e c t r e g i s t e rP R C R0 0 X X X 0 0 02 P r o c e s s o r m o d e r e g i s t e r 1P M 10 0 X X X 0 X 02 N O T E S : B l a n k s p a c e s a r e r e s e r v e d N o a c c e s s i s a l l o w e d X U n d e f i n e d O s c i l l a t i o n s t o p d e t e c t i o n r e g i s t e rO C D0 0 0 0 0 1 0 02 INT0 input filter select register INT0F XXXXX000 2 0 0 0 01 C 1 D 1 C 1 D 1 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C 16 002D 16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C 16 003D 16 003E16 003F16 A d d r e s s R e g i s t e rS y m b o l A f t e r r e s e t A d d r e s s m a t c h i n t e r r u p t r e g i s t e r 0R M A D 00 01 X A d d r e s s m a t c h i n t e r r u p t r e g i s t e r 1R M A D 10 01 X W a t c h d o g t i m e r r e s e t r e g i s t e rW D T RX X1 4. Special Function Register (SFR) SFR(Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.4 list the SFR information Table 4.1 SFR Information(1)(1)

R8C/10 Group 4. Special Function Register (SFR) Rev.1.20 Jan 27, 2006 page 11 of 180 REJ09B0019-0120 UART0 transmit interrupt control register S0TIC XXXXX000 2 UART0 receive interrupt control register S0RIC XXXXX000 2 UART1 transmit interrupt control register S1TIC XXXXX000 2 UART1 receive interrupt control register S1RIC XXXXX000 2 Key input interrupt control register KUPIC XXXXX000 2 A D c o n v e r s i o n i n t e r r u p t c o n t r o l r e g i s t e rA D I CX X X X X 0 0 02 INT1 interrupt control register INT1IC XXXXX000 2 INT2 interrupt control register INT2IC XXXXX000 2 INT0 interrupt control register INT0IC XX00X000 2 INT3 interrupt control register INT3IC XXXXX000 2 NOTES : 1. Blank spaces are reserved. No access is allowed. X : Undefined 0 0 4 01 C 1 D 1 C 1 D 1 006016 006116 006216 006316 006416 006516 006616 006716 006816 006916 006A16 006B16 006C 16 006D 16 006E16 006F16 007016 007116 007216 007316 007416 007516 007616 007716 007816 007916 007A16 007B16 007C 16 007D 16 007E16 007F16 A d d r e s s R e g i s t e r Symbol A f t e r r e s e t Timer X interrupt control register TXIC XXXXX000 2 Timer Y interrupt control register TYIC XXXXX000 2 Timer Z interrupt control register TZIC XXXXX000 2 Timer C interrupt control register TCIC XXXXX000 2 Table 4.2 SFR Information(2)(1)

R8C/10 Group 4. Special Function Register (SFR) Rev.1.20 Jan 27, 2006 page 12 of 180 REJ09B0019-0120 0 0 8 01 C 1 D 1 C 1 D 1 0 0 A 01 A A A A A A A A A A A A C 1 A D 1 A A B B B B B B B B B B B B B C 1 B D 1 B B T i m e r X r e g i s t e rT XF F1 T i m e r Y s e c o n d a r y r e g i s t e rT Y S CF F1 E x t e r n a l i n p u t e n a b l e r e g i s t e rI N T E N0 01 P r e s c a l e r Y r e g i s t e rP R E YF F1 UART0 transmit/receive mode register U0MR 00 16 U A R T 0 t r a n s m i t b u f f e r r e g i s t e rU 0 T BX X1 X U A R T 0 r e c e i v e b u f f e r r e g i s t e r U 0 R BX X1 X UART1 transmit/receive mode register U1MR 00 16 UART1 transmit buffer register U1TB XX 16 XX 16 UART1 receive buffer register U1RB XX 16 XX 16 UART0 bit rate generator U0BRG XX 16 U A R T t r a n s m i t r e c e i v e c o n t r o l r e g i s t e r

0 U 0 C 00 0 0 0 1 0 0 02

U A R T t r a n s m i t r e c e i v e c o n t r o l r e g i s t e r

1 U 0 C 10 0 0 0 0 0 1 02

UART1 bit rate generator U1BRG XX 16 UART1 transmit/receive control register 0 U1C0 00001000 2 U A R T t r a n s m i t r e c e i v e c o n t r o l r e g i s t e r

1 U 1 C 10 0 0 0 0 0 1 02

UART transmit/receive control register 2 UCON 00 16 N O T E S : B l a n k s p a c e s a r e r e s e r v e d N o a c c e s s i s a l l o w e d X U n d e f i n e d A d d r e s s R e g i s t e rS y m b o l A f t e r r e s e t T i m e r Y , Z m o d e r e g i s t e rT Y Z M R0 01 Timer Y primary register TYPR FF 16 T i m e r Y , Z w a v e f o r m o u t p u t c o n t r o l r e g i s t e rP U M0 01 P r e s c a l e r Z r e g i s t e rP R E ZF F1 T i m e r Z s e c o n d a r y r e g i s t e rT Z S CF F1 T i m e r Z p r i m a r y r e g i s t e rT Z P RF F1 T i m e r Y , Z o u t p u t c o n t r o l r e g i s t e rT Y Z O C0 01 T i m e r X m o d e r e g i s t e rT X M R0 01 P r e s c a l e r X r e g i s t e rP R E XF F1 C o u n t s o u r c e s e t r e g i s t e rT C S S0 01 T i m e r C r e g i s t e rT C0 01 K e y i n p u t e n a b l e r e g i s t e rK I E N0 01 T i m e r C c o n t r o l r e g i s t e r 0T C C 00 01 Timer C control register 1 TCC1 00 16 Capture register TM0 00 16 0016 Table 4.3 SFR Information(3)(1)

R8C/10 Group 4. Special Function Register (SFR) Rev.1.20 Jan 27, 2006 page 13 of 180 REJ09B0019-0120 0 0 C 01 C C C C C C C C C C C C C 1 C D 1 C C D D D D D D D D D D D D D C 1 D D 1 D D 00E016 00E116 00E216 00E316 00E416 00E516 00E616 00E716 00E816 00E916 00EA 16 00EB 16 00EC 16 00ED 16 00EE 16 00EF 16 00F016 00F116 00F216 00F316 00F416 00F516 00F616 00F716 00F816 00F916 03FA 16 00FB 16 00FC 16 00FD 16 00FE 16 00FF16 01B316 01B416 01B516 01B616 01B716 NOTES: 1. Blank columns, 010016 to 01B216 and 01B816 to 02FF16 are all reserved. No access is allowed. X : Undefined A D r e g i s t e rA DX X X X X X X X2 X X X X X X X A D c o n t r o l r e g i s t e r 0A D C O N 00 0 0 0 0 X X X2 A D c o n t r o l r e g i s t e r 2A D C O N 20 01 A D c o n t r o l r e g i s t e r 1 A D C O N 10 01 P o r t P 0 r e g i s t e rP 0X X1 P o r t P 0 d i r e c t i o n r e g i s t e rP D 00 01 P o r t P 1 r e g i s t e rP 1X X1 Port P1 direction register PD1 00 16 P o r t P 3 r e g i s t e rP 3X X1 Port P3 direction register PD3 00 16 Port P4 register P4 XX 16 P o r t P 4 d i r e c t i o n r e g i s t e rP D 40 01 P u l l - u p c o n t r o l r e g i s t e r 0 P U R 00 0 X X 0 0 0 02 Port P1 drive capacity control register DRR 00 16 R e g i s t e r Symbol After resetA d d r e s s Pull-up control register 1 PUR1 XXXXXX0X 2 F l a s h m e m o r y c o n t r o l r e g i s t e r 1 F M R 10 1 0 0 X X 0 X2 F l a s h m e m o r y c o n t r o l r e g i s t e r 0 F M R 00 0 0 0 0 0 0 12 Flash memory control register 4 FMR4 01000000 2 Table 4.4 SFR Information(4)(1)

R8C/10 Group 5. Reset Rev.1.20 Jan 27, 2006 page 14 of 180 REJ09B0019-0120 5. Reset There are three types of resets: a hardware reset, a software reset, and an watchdog timer reset.

5.1 Hardware Reset

A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the power supply voltage is within the recommended operating condition, the pins are initial- ized (see Table 5.1 “Pin Status When RESET Pin Level is 'L'”). When the input level at the RESET pin is released from “L” to “H ”, the CPU and SFR are initialized, and the program is executed starting from the address indicated by the reset vector. Figure 5.1 shows the CPU register status after reset and figure 5.2 shows the reset sequence. After reset, the on-chip oscillator clock divided by 8 is automatically selected for the CPU. The internal RAM is not initialized. If the RESET pin is pulled “L” while writing to the internal RAM, the internal RAM becomes indeterminate. Figures 5.3 to 5.4 show the reset circuit example. Refer to Chapter 4, “Special Function Register (SFR)” for the status of SFR after reset.

• When the power supply is stable (1) Apply an “L” signal to the RESET pin. (2) Wait for 500 µs (1/fRING ✕ 20). (3) Apply an “H ” signal to the RESET pin.
• Power on (1) Apply an “L” signal to the RESET pin. (2) Let the power supply voltage increase until it meets the recommended operating condition. (3) Wait td(P-R) or more until the internal power supply stabilizes. (4) Wait for 500 µs (1/fRING ✕ 20). (5) Apply an “H ” signal to the RESET pin.

5.3 Watchdog Timer Reset

Where the PM12 bit in the PM1 register is “1” (reset when watchdog timer underflows), the microcom- puter initializes its pins, CPU and SFR if the watchdog timer underflows. Then the program is ex- ecuted starting from the address indicated by the reset vector. After reset, the on-chip oscillator clock divided by 8 is automatically selected for the CPU. Table 5.1 Pin Status When RESET Pin Level is “L” Status CNV SS = VSS Pin name P30 to P33, P37 P45 to P47 Input port Input port Input port Input port

5.2 Software Reset

When the PM03 bit in the PM0 register is set to “1” (microcomputer reset), the microcomputer has its pins, CPU, and SFR initialized. Then the program is executed starting from the address indicated by the reset vector. After reset, the on-chip oscillator clock divided by 8 is automatically selected for the CPU.

R8C/10 Group 5. Reset Rev.1.20 Jan 27, 2006 page 15 of 180 REJ09B0019-0120 Figure 5.2 Reset Sequence Figure 5.1 CPU Register Status After Reset b15 b0 Data register(R0) Address register(A0) Frame base register(FB) Program counter(PC) Interrupt table register(INTB) User stack pointer(USP) Interrupt stack pointer(ISP) Static base register(SB) Flag register(FLG) 000016 000016 000016 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines CDZSBOIUIPL 000016 000016 000016 000016 000016 b19 b0 Content of addresses 0FFFE16 to 0FFFC16 b15 b0 b15 b0 b15 b0 b7 b8 0000016 Data register(R1) Data register(R2) Data register(R3) Address register(A1) 000016 000016 000016 fR I N G A d d r e s s I n t e r n a l a d d r e s s s i g n a l Content of reset vector0FFFD 16 More than 20 cycles are needed CPU clock CPU clock ✕ 28cycles Internal on-chip oscillation

0 F F F C 1

Flash memory activated time (CPU clock ✕ 64 cycles) N O T E S : T h i s s h o w s h a r d w a r e r e s e t (1)

Rev.1.20 Jan 27, 2006 page 17 of 180 REJ09B0019-0120 C P U c l o c k s o u r c e P e r i p h e r a l f u n c t i o n c l o c k s o u r c eU s e o f c l o c k M a i n c l o c k o s c i l l a t i o n c i r c u i tI t e m C l o c k f r e q u e n c y 0 to 16 MHz C e r a m i c r e s o n a t o r C r y s t a l o s c i l l a t o r U s a b l e o s c i l l a t o r XI N , XO U i n s t o c o n n e c t o s c i l l a t o r P r e s e n t S t o p p e dO s c i l l a t o r s t a t u s a f t e r r e s e t Externally derived clock can be input Other On-chip oscillator

• CPU clock source
• Peripheral function clock source
• CPU and peripheral function clock sources when the main clock sto ps oscillating About 125 kHz P r e s e n t Oscillating NOTES: 1. Can be used as P46 and P47 when the on-chip oscillator clock is used for CPU clock while the main clock oscillation circuit is not used. C P U a n d p e r i p h e r a l f u n c t i o n c l o c k s o u r c e s w h e n t h e m a i n c l o c k s t o p s o s c i l l a t i n g (Note 1) O s c i l l a t i o n s t a r t s a n d s t o p s 6. Clock Generation Circuit The clock generation circuit contains two oscillator circuits as follows:
• Main clock oscillation circuit
• On-chip oscillator (with oscillation stop detection function) Table 6.1 lists the clock generation circuit specifications. Figure 6.1 shows the clock generation circuit. Figures 6.2 and 6.3 show the clock-related registers. Table 6.1 Clock Generation Circuit Specifications 6. Clock Generation Circuit

Rev.1.20 Jan 27, 2006 page 18 of 180 REJ09B0019-0120 C P U c l o c k I n t e r r u p t r e q u e s t l e v e l j u d g m e n t o u t p u t C M S t o p m o d e W A I T i n s t r u c t i o n O n c h i p o s c i l l a t o r c l o c k M a i n c l o c k C M R E S E T R QS c R C M 0 2 QS R XO U TXI N fA D a d cb O C D O C D C M S I O S I O fR I N G fR I N G S I O e e C M 0 2 , C M 0 5 , C M 0 6 : B i t s i n C M 0 r e g i s t e r C M C M C M C M C M B i t s i n C M r e g i s t e r O C D O C D O C D B i t s i n O C D r e g i s t e r D e t a i l s o f d i v i d e r 1 / 2 1 / 2 1 / 2 1 / 2 C M 0 6 = 0 C M t o C M C M 0 6 = 0 C M t o C M C M 0 6 = 0 C M t o C M C M 0 6 = 1 C M 0 6 = 0 C M t o C M d a b F o r c i b l e d i s c h a r g e w h e n O C D 0(1 ) O C D 2 b i t s w i t c h s i g n a l O C D 1(1 ) C M 1 4 b i t s w i t c h s i g n a l P u l s e g e n e r a t i o n c i r c u i t f o r c l o c k e d g e d e t e c t i o n a n d c h a r g e d i s c h a r g e c o n t r o l c i r c u i t C h a r g e , d i s c h a r g e c i r c u i t N O T E S : S e t t h e s a m e v a l u e t o t h e O C D b i t a n d O C D b i t O s c i l l a t i o n s t o p d e t e c t i o n i n t e r r u p t g e n e r a t i o n c i r c u i t M a i n c l o c k W a t c h d o g t i m e r i n t e r r u p t O s c i l l a t i o n s t o p d e t e c t i o n W a t c h d o g t i m e r i n t e r r u p t O s c i l l a t i o n s t o p d e t e c t i o n c i r c u i t O n c h i p o s c i l l a t o r O s c i l l a t i o n s t o p d e t e c t i o n D i v i d e r P e r i p h e r a l f u n c t i o n c l o c k C M Figure 6.1 Clock Generation Circuit 6. Clock Generation Circuit

Rev.1.20 Jan 27, 2006 page 19 of 180 REJ09B0019-0120 S y s t e m c l o c k c o n t r o l r e g i s t e r 0(1 S y m b o lA d d r e s sA f t e r r e s e t C M 6 6 B i t n a m eF u n c t i o nB i t s y m b o l b Set to “0” C M 0 5 ( b 3 ) ( b 1 - b 0 ) C M 0 2 CM0 6 R e s e r v e d b i t W A I T p e r i p h e r a l f u n c t i o n c l o c k s t o p b i t 0 : Do not stop peripheral function clock in wait mode 1 : Stop peripheral function clock in wait mode R e s e r v e d b i t Set to “1” R e s e r v e d b i t Set to “0” M a i n c l o c k ( XI N - XO U T) s t o p b i 0 : On 1 : Off(3) C P U c l o c k d i v i s i o n s e l e c t b i t 0 : CM16 and CM17 valid 1 : Divide-by-8 mode R e s e r v e d b i t Set to “0” N O T E S : S e t t h e P R C b i t o f P R C R r e g i s t e r t o w r i t e e n a b l e b e f o r e w r i t i n g t o t h i s r e g i s t e r T h e C M b i t i s p r o v i d e d t o s t o p t h e m a i n c l o c k w h e n t h e o n c h i p o s c i l l a t o r m o d e i s s e l e c t e d T h i s b i t c a n n o t b e u s e d f o r d e t e c t i o n a s t o w h e t h e r t h e m a i n c l o c k s t o p p e d o r n o t T o s t o p t h e m a i n c l o c k t h e f o l l o w i n g s e t t i n g i s r e q u i r e d S e t t h e O C D a n d O C D b i t s i n t h e O C D r e g i s t e r t o 02” d i s a b l i n g o s c i l l a t i o n s t o p d e t e c t i o n f u n c t i o n S e t t h e O C D b i t t o s e l e c t i n g o n c h i p o s c i l l a t o r c l o c k S e t t h e C M b i t t o m a i n c l o c k s t o p s a n d t h e C M b i t i n t h e C M r e g i s t e r t o XI N - XO U T p i n w h e n t h e e x t e r n a l c l o c k i s i n p u t W h e n t h e C M b i t i s s e t t o m a i n c l o c k s t o p P a n d P c a n b e u s e d a s i n p u t p o r t s W h e n e n t e r i n g s t o p m o d e f r o m h i g h o r m i d d l e s p e e d m o d e t h e C M b i t i s s e t t o d i v i d e b y m o d e R W R W R W R W R W R W R W R W 000 0 1 ( b 4 ) ( b 7 ) Figure 6.2 CM0 Register and CM1 Register 6. Clock Generation Circuit System clock control register 1(1) S y m b o lA d d r e s sA f t e r r e s e t C M 6 2 B i t n a m eF u n c t i o nBit symbol b7 b6 b5 b4 b 3 b2 b1 b 0 C M 1 0 A l l c l o c k s t o p c o n t r o l b i ) 0 : C l o c k o n A l l c l o c k s o f f s t o p m o d e N O T E S : W r i t e t o t h i s r e g i s t e r a f t e r s e t t i n g t h e P R C b i t o f P R C R r e g i s t e r t o w r i t e e n a b l e W h e n e n t e r i n g s t o p m o d e f r o m h i g h o r m i d d l e s p e e d m o d e t h e C M b i t i s s e t t o d r i v e c a p a c i t y h i g h E f f e c t i v e w h e n t h e C M b i t i s C M a n d C M b i t s e n a b l e I f t h e C M b i t i s s t o p m o d e t h e i n t e r n a l f e e d b a c k r e s i s t o r b e c o m e s i n e f f e c t i v e T h e C M b i t c a n b e s e t t o o n c h i p o s c i l l a t o r o f f i f t h e O C D b i t s e l e c t i n g m a i n c l o c k W h e n t h e O C D b i t i s s e t t o s e l e c t i n g o n c h i p o s c i l l a t o r c l o c k t h e C M b i t i s s e t t o o n c h i p o s c i l l a t o r o n T h i s b i t r e m a i n s u n c h a n g e d w h e n i s w r i t t e n W h e n t h e C M b i t i s s e t t o s t o p m o d e o r t h e C M b i t i n t h e C M r e g i s t e r t o m a i n c l o c k s t o p s a n d t h e C M b i t i s s e t t o XI N - XO U T p i n t h e XO U P 47) p i n i s h e l d H W h e n t h e C M b i t i s s e t t o i n p u t p o r t P 46, P 47) t h e P i s i n i n p u t s t a t e R W R e s e r v e d b i t S e t t o 0 0 C M 1 5 XI N - XO U T d r i v e c a p a c i t y s e l e c t b i 0 : L O W H I G H C M 1 6 C M 1 7 M a i n c l o c k d i v i s i o n s e l e c t b i t 0 0 : N o d i v i s i o n m o d e D i v i s i o n b y m o d e D i v i s i o n b y m o d e D i v i s i o n b y m o d e b b R W R W R W ( b 2 ) P o r t XI N - XO U T s w i t c h b i t C M 1 4 O n - c h i p o s c i l l a t i o n s t o p b i t 0 : O n - c h i p o s c i l l a t o r o n O n c h i p o s c i l l a t o r o f f ) R W R e s e r v e d b i t S e t t o ”( b 1 ) C M 1 3 0 : I n p u t p o r t P 4 6, P 47 XI N - XO U T p i n R W R W R W R W

Rev.1.20 Jan 27, 2006 page 20 of 180 REJ09B0019-0120 R W R W R W R O b O C D 0 O C D 1 O C D 2 O C D 3 0000 O s c i l l a t i o n s t o p d e t e c t i o n r e g i s t e r( S y m b o lA d d r e s sA f t e r r e s e t O C D 0 0 0 C 1 6 0 41 B i t n a m e F u n c t i o nB i t s y m b o l S y s t e m c l o c k s e l e c t b i T h e f u n c t i o n i s d i s a b l e A v o i d t h i s s e t t i n g A v o i d t h i s s e t t i n g T h e f u n c t i o n i s e n a b l e S e l e c t m a i n c l o c S e l e c t o n c h i p o s c i l l a t o r c l o c 0 : M a i n c l o c k o n M a i n c l o c k o f f O s c i l l a t i o n s t o p d e t e c t i o n e n a b l e b i t C l o c k m o n i t o r b i R e s e r v e d b i t S e t t o " 0 " N O T E S : S e t t h e P R C b i t i n t h e P R C R r e g i s t e r t o w r i t e e n a b l e b e f o r e r e w r i t i n g t h i s r e g i s t e r T h e O C D b i t i s s e t t o s e l e c t i n g o n c h i p o s c i l l a t o r c l o c k a u t o m a t i c a l l y i f a m a i n c l o c k o s c i l l a t i o n s t o p i s d e t e c t e d w h i l e t h e O C D t o O C D b i t s a r e s e t t o 12” o s c i l l a t i o n s t o p d e t e c t i o n f u n c t i o n d i s a b l e d I f t h e O C D b i t i s s e t t o m a i n c l o c k s t o p t h e O C D b i t r e m a i n s u n c h a n g e d w h e n t r y i n g t o w r i t e s e l e c t i n g m a i n c l o c k T h e O C D b i t i s e n a b l e d w h e n t h e O C D t o O C D b i t s a r e s e t t o 12” o s c i l l a t i o n s t o p d e t e c t i o n f u n c t i o n e n a b l e d T h e O C D t o O C D b i t s m u s t b e s e t t o 02” o s c i l l a t i o n s t o p d e t e c t i o n f u n c t i o n d i s a b l e d b e f o r e e n t e r i n g s t o p m o d e o r o n c h i p o s c i l l a t o r m o d e m a i n c l o c k s t o p s T h e O C D b i t r e m a i n s s e t t o m a i n c l o c k o n i f t h e O C D t o O C D b i t s a r e s e t t o 02” T h e C M b i t g o e s t o o n c h i p o s c i l l a t o r o n i f t h e O C D b i t i s s e t t o s e l e c t i n g o n c h i p o s c i l l a t o r c l o c k R e f e r t o F i g u r e s w i t c h i n g c l o c k s o u r c e f r o m o n c h i p o s c i l l a t o r t o m a i n c l o c k f o r t h e s w i t c h i n g p r o c e d u r e w h e n t h e m a i n c l o c k r e o s c i l l a t e s a f t e r d e t e c t i n g a n o s c i l l a t i o n s t o p b 1 b 0 ( b 7 - b 4 ) R W Figure 6.3 OCD Register 6. Clock Generation Circuit

Rev.1.20 Jan 27, 2006 page 21 of 180 REJ09B0019-0120 Microcomputer (Built-in feedback resistor) XIN XOUT E x t e r n a l l y d e r i v e d c l o c k O pen Vcc V s s M i c r o c o m p u t e r B u i l t i n f e e d b a c k r e s i s t o r XI N XO U T R d C I N C O U T ( N o t e 1 ) N O T E S n s e r t a d a m p i n g r e s i s t o r i f r e q u i r e d T h e r e s i s t a n c e w i l l v a r y d e p e n d i n g o n t h e o s c i l l a t o r a n d t h e o s c i l l a t i o n d r i v e c a p a c i t y s e t t i n g U s e t h e v a l u e r e c o m m e n d e d b y t h e m a k e r o f t h e o s c i l l a t o r W h e n t h e o s c i l l a t i o n d r i v e c a p a c i t y i s s e t t o l o w c h e c k t h a t o s c i l l a t i o n i s s t a b l e A l s o i f t h e o s c i l l a t o r m a n u f a c t u r e r s d a t a s h e e t s p e c i f i e s t h a t a f e e d b a c k r e s i s t o r b e a d d e d e x t e r n a l t o t h e c h i p i n s e r t a f e e d b a c k r e s i s t o r b e t w e e n XI N a n d XO U T f o l l o w i n g t h e i n s t r u c t i o n Figure 6.4 Examples of Main Clock Connection Circuit The following describes the clocks generated by the clock generation circuit.

6.1 Main Clock

This clock is supplied by a main clock oscillation circuit. This clock is used as the clock source for the CPU and peripheral function clocks. The main clock oscillator circuit is configured by connecting a resonator between the X IN and XOUT pins. The main clock oscillator circuit contains a feedback resistor, which is disconnected from the oscillator circuit during stop mode in order to reduce the amount of power con- sumed in the chip. The main clock oscillator circuit may also be configured by feeding an externally generated clock to the X IN pin. Figure 6.4 shows examples of main clock connection circuit. During reset and after reset, the main clock is turned off. The main clock starts oscillating when the CM05 bit in the CM0 register is set to “0” (main clock on) after setting the CM13 bit in the CM1 register to “1” (X IN- XOUT pin). To use the main clock for the CPU clock, set the OCD2 bit in the OCD register to “0” (selecting main clock) after the main clock becomes oscillating stably. The power consumption can be reduced by setting the CM05 bit in the CM0 register to “1” (main clock off) if the OCD2 bit is set to “1” (selecting on-chip oscillator clock). Note that if an externally generated clock is fed into the X IN pin, the main clock cannot be turned off by setting the CM05 bit to “1”. If necessary, use an external circuit to turn off the clock. During stop mode, all clocks including the main clock are turned off. Refer to Section 6.3, “Power Con- trol.”

Rev.1.20 Jan 27, 2006 page 22 of 180 REJ09B0019-0120

6.2 On-Chip Oscillator Clock

This clock, approximately 125 kHz, is supplied by the on-chip oscillator. This clock is used as the clock source for the CPU clock, peripheral function clock, fRING , and fRING128 . After reset, the on-chip oscillator clock divided by 8 is selected for the CPU clock. To use the main clock for the CPU clock, set the OCD2 in the OCD register to “0” (selecting main clock) after the main clock becomes oscillating stably. If the main clock stops oscillating when the OCD1 to OCD0 bits in the OCD register is “11 2” (oscillation stop detection function enabled), the on-chip oscillator automatically starts operating, supplying the necessary clock for the microcomputer. The frequency of the on-chip oscillator varies depending on the supply voltage and the operation ambient temperature. The application products must be designed with sufficient margin for the frequency change.

Rev.1.20 Jan 27, 2006 page 23 of 180 REJ09B0019-0120

6.3 CPU Clock and Peripheral Function Clock

There are two types of clocks: CPU clock to operate the CPU and peripheral function clock to operate the peripheral functions. Also refer to “Figure 6.1 Clock Generating Circuit”.

6.3.1 CPU Clock

This is an operating clock for the CPU and watchdog timer. The clock source for the CPU clock can be chosen to be the main clock or on-chip oscillator clock. The selected clock source can be divided by 1 (undivided), 2, 4, 8 or 16 to produce the CPU clock. Use the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 register to select the divide- by-n value. After reset, the on-chip oscillator clock divided by 8 provides the CPU clock. Note that when entering stop mode from high or middle speed mode, the CM06 bit is set to “1” (divide- by-8 mode).

6.3.2 Peripheral Function Clock (f

1, f2, f8, f32, fAD , f1SIO, f8SIO, f32SIO) These are operating clocks for the peripheral functions. Of these, fi (i=1, 2, 8, 32) is derived from the main clock or on-chip oscillator clock by dividing them by i. The clock fi is used for timers X, Y, Z and C. The clock fj SIO (j=1, 8, 32) is derived from the main clock or on-chip oscillator clock by dividing them by j. The clock fjSIO is used for serial interface. The fAD clock is produced from the main clock is used for the A/D converter. When the WAIT instruction is executed after setting the CM02 bit in the CM0 register to “1” (peripheral function clock turned off during wait mode), the clocks fi, fjSIO, and fAD are turned off. 6.3.3 fRING and fRING128 These are operating clocks for the peripheral functions. The fRING runs at the same frequency as the on-chip oscillator, and can be used as the source for the timer Y. The fRING128 is derived from the fRING by dividing it by 128, and can used for the timer C. When the WAIT instruction is executed, the clocks fRING and fRING128 are not turned off.

Rev.1.20 Jan 27, 2006 page 24 of 180 REJ09B0019-0120 M o d e s O C D r e g i s t e r O C D C M r e g i s t e r C M C M C M r e g i s t e r CM06 CM05 H i g h s p e e d m o d e M e d i u m s p e e d m o d e d i v i d e d b y 01 0 O n - c h i p o s c i l l a t o r m o d e d i v i d e d b y d i v i d e d b y d i v i d e d b y 10 12 00 o r 1 11 02 00 o r 1 11 0 o r 1 11 12 00 o r 1 10 02 00 o r 1 d i v i d e d b y 2 d i v i d e d b y 4 d i v i d e d b y 8 d i v i d e d b y 1 6 n o d i v i s i o n C M

6.4 Power Control

There are three power control modes. All modes other than wait and stop modes are referred to as normal operation mode.

6.4.1 Normal Operation Mode

Normal operation mode is further classified into three modes. In normal operation mode, because the CPU clock and the peripheral function clocks both are on, the CPU and the peripheral functions are operating. Power control is exercised by controlling the CPU clock frequency. The higher the CPU clock frequency, the greater the processing capability. The lower the CPU clock frequency, the smaller the power consumption in the chip. If the unnecessary oscillator circuits are turned off, the power consumption is further reduced. Before the clock sources for the CPU clock can be switched over, the new clock source to which switched must be oscillating stably. If the new clock source is the main clock, allow a sufficient wait time in a program until it becomes oscillating stably.

• High-speed Mode The main clock divided by 1 undivided provides the CPU clock. If the CM14 bit is set to “0” (on-chip oscillator on), the f RING is used as the count source for timer Y.
• Medium-speed Mode The main clock divided by 2, 4, 8 or 16 provides the CPU clock. If the CM14 bit is set to “0” (on-chip oscillator on), the fRING is used as the count source for timer Y.
• On-Chip Oscillator Mode The on-chip oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the CPU clock. The on- chip oscillator clock is also the clock source for the peripheral function clocks.

Table 6.2 Setting Clock Related Bit and Modes

6.4.2 Wait Mode

peripheral functions using these clocks keep operating.

• Peripheral Function Clock Stop Function If the CM02 bit is “1” (peripheral function clocks turned off during wait mode), the f 1, f2, f8, f32, f1SIO, f8SIO, f32SIO, and fAD clocks are turned off when in wait mode, with the power consumption reduced that much.
• Entering Wait Mode The microcomputer is placed into wait mode by executing the WAIT instruction.
• Pin Status During Wait Mode The status before wait mode is retained.
• Exiting Wait Mode The microcomputer is moved out of wait mode by a hardware reset or peripheral function interrupt. When using a hardware reset to exit wait mode, set the ILVL2 to ILVL0 bits for the peripheral function interrupts to “000 2” (interrupts disabled) before executing the WAIT instruction. The peripheral function interrupts are affected by the CM02 bit. If CM02 bit is “0” (peripheral function clocks not turned off during wait mode), all peripheral function interrupts can be used to exit wait mode. If CM02 bit is “1” (peripheral function clocks turned off during wait mode), the peripheral functions using the peripheral function clocks stop operating, so that only the peripheral functions clocked by external signals can be used to exit wait mode.

Table 6. 3 lists the interrupts to exit wait mode and the usage conditions.

1. In the ILVL2 to ILVL0 bits in the interrupt control register, set the interrupt priority level of the

peripheral function interrupt to be used to exit wait mode.

1. Enable the peripheral function whose interrupt is to be used to exit wait mode.

interrupt sequence is executed. clock that was on when the WAIT instruction was executed.

Rev.1.20 Jan 27, 2006 page 26 of 180 REJ09B0019-0120

6.4.3 Stop Mode

In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks. Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The least amount of power is consumed in this mode. If the voltage applied to Vcc pin is V RAM or more, the internal RAM is retained. However, the peripheral functions clocked by external signals keep operating. The following interrupts can be used to exit stop mode.

• Key interrupt
• INT0 to INT2 interrupts (INT0 can be used only when there is no filter.)
• Timer X interrupt (when counting external pulses in event counter mode)
• Timer Y interrupt (when counting inputs from CNTR1 pin in timer mode)
• Serial interface interrupt (when external clock is selected)
• Entering Stop Mode The microcomputer is placed into stop mode by setting the CM10 bit of CM1 register to “1” (all clocks turned off). At the same time, the CM06 bit of CM0 register is set to “1” (divide-by-8 mode) and the CM15 bit of CM10 register is set to “1” (main clock oscillator circuit drive capacity high). Before entering stop mode, set the OCD1 to OCD0 bits to “002” (oscillation stop detection function disable).
• Pin Status in Stop Mode The status before wait mode is retained. However, the X OUT (P47) pin is held “H ” when the CM13 bit in the CM1 register is set to “1” (XIN-XOUT pin). The P47(XOUT ) is in input state when the CM13 bit is set to “0” (input port P46, P47).
• Exiting Stop Mode The microcomputer is moved out of stop mode by a hardware reset or peripheral function interrupt. When using a hardware reset to exit stop mode, set the ILVL2 to ILVL0 bits for the peripheral function interrupts to “000 2” (interrupts disabled) before setting the CM10 bit to “1”. When using a peripheral function interrupt to exit stop mode, set up the following before setting the CM10 bit to “1”. 1. In the ILVL2 to ILVL0 bits in the interrupt control register, set the interrupt priority level of the peripheral function interrupt to be used to exit stop mode. Also, for all of the peripheral function interrupts not used to exit stop mode, set the ILVL2 to ILVL0 bits to “000 2”. 2. Set the I flag to “1”. 3. Enable the peripheral function whose interrupt is to be used to exit stop mode. In this case, when an interrupt request is generated and the CPU clock is thereby turned on, an interrupt sequence is executed. The main clock divided by 8 of the clock which is used right before stop mode is used for the CPU clock when exiting stop mode by a peripheral function interrupt.

Rev.1.20 Jan 27, 2006 page 27 of 180 REJ09B0019-0120 Figure 6.5 State Transition of Power Control Figure 6.5 shows the state transition of Power control OCD2=1 CM14=0 CM05: Bit in CM0 register CM10, CM13, CM14: Bit in CM1 register OCD2: Bit in OCD register High-speed Mode, Middle-speed mode OCD2=0 CM05=0 CM13=1 Reset Wait Mode WAIT InstructionInterrupt Stop Mode CM10=1 (All clocks stop) Interrupt CM14=0, OCD2=1 CM13=1, CM05=0, OCD2=0 There are five power control modes. (1) High-speed mode (2) Middle-speed mode (3) On-chip oscillator mode (4) Wait mode (5) Stop mode

Rev.1.20 Jan 27, 2006 page 28 of 180 REJ09B0019-0120

6.5 Oscillation Stop Detection Function

The oscillation stop detection function is such that main clock oscillation circuit stop is detected. The oscillation stop detection function can be enabled and disabled by the OCD1 to OCD0 bits in the OCD register. Table 6.4 lists the specifications of the oscillation stop detection function. Where the main clock corresponds to the CPU clock source and the OCD1 to OCD0 bits are “11 (oscillation stop detection function enabled), the system is placed in the following state if the main clock comes to a halt:

• The on-chip oscillator starts oscillation, and the on-chip oscillator clock becomes the clock source for CPU clock and peripheral functions in place of the main clock
• OCD register OCD2 bit = 1 (selecting on-chip oscillator clock)
• OCD register OCD3 bit = 1 (main clock stopped)
• CM1 register CM14 bit = 0 (on-chip oscillator oscillating)
• Oscillation stop detection interrupt request occurs Table 6.4 Oscillation Stop Detection Function Specifications Item Specification Oscillation stop detectable clock and f(XIN) ≥ 2 MHz frequency bandwidth Enabling condition for oscillation stop Set OCD1 to OCD0 bits to “112” (oscillation stop detection detection function function enabled) Operation at oscillation stop detection Oscillation stop detection interrupt occurs

6.5.1 How to Use Oscillation Stop Detection Function

• The oscillation stop detection interrupt shares the vector with the watchdog timer interrupt. If the oscillation stop detection and watchdog timer interrupts both are used, the interrupt factor must be determined. Table 6.5 shows to determine the interrupt factor with the oscillation stop detection interrupt, watchdog timer interrupt and voltage detection interrupt.
• Where the main clock re-oscillated after oscillation stop, the clock source for the CPU clock and peripheral functions must be switched to the main clock in the program. Figure 6.6 shows the procedure for switching the clock source from the on-chip oscillator to the main clock.
• To enter wait mode while using the oscillation stop detection function, set the CM02 bit to “0” (periph- eral function clocks not turned off during wait mode).
• Since the oscillation stop detection function is provided in preparation for main clock stop due to external factors, set the OCD1 to OCD0 bits to “00 2” (oscillation stop detection function disabled) where the main clock is stopped or oscillated in the program, that is where the stop mode is selected or the CM05 bit is altered.
• This function cannot be used when the main clock frequency is below 2 MHz. Set the OCD1 to OCD0 bits to “00 2” (oscillation stop detection function disabled).

Rev.1.20 Jan 27, 2006 page 29 of 180 REJ09B0019-0120 Generated Interrupt Factor Bit showing interrupt factor Oscillation stop detection (a) The OCD3 bit in the OCD register = 1 ( (a) or (b) ) (b) The OCD1 to OCD0 bits in the OCD register = 11 2 and the OCD2 bit = 1 Figure 6.6 Switching Clock Source From On-Chip Oscillator to Main Clock Table 6.5 Determination of Interrupt Factor of Oscillation Stop Detection Switch to Main clock Verify OCD3 bit Determine several times 1(main clock stop) 0(main clock oscillating) Determine several times that the main clock is supplied Set OCD2 bit to 0 (selecting main clock) OCD3 to OCD0 bits: Bits in OCD register End Set OCD1 to OCD0 bits to 002 (oscillation stop detection function disabled)

R8C/10 Group 7. Protection Rev.1.20 Jan 27, 2006 page 30 of 180 REJ09B0019-0120 7. Protection In the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily. Figure 7.1 shows the PRCR register. The following lists the registers protected by the PRCR register.

• Registers protected by PRC0 bit: CM0, CM1, and OCD registers
• Registers protected by PRC1 bit: PM0 and PM1 registers
• Registers protected by PRC2 bit: PD0 register Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be set to “0” (write protected). The registers protected by the PRC2 bit should be changed in the next instruction after setting the PRC2 bit to “1”. Make sure no interrupts will occur between the instruction in which the PRC2 bit is set to “1” and the next instruction. The PRC0 and PRC1 bits are not automatically set to “0” by writing to any address. They can only be set to “0” in a program. Figure 7.1 PRCR Register P r o t e c t r e g i s t e r Symbol Address After reset PRCR 000A 16 00XXX000 2 B i t n a m eB i t s y m b o l b7 b6 b5 b4 b3 b2 b1 b0 0 : W r i t e p r o t e c t e d W r i t e e n a b l e d PRC1 PRC0 Function R W N O T E S : T h e P R C b i t i s s e t t o b y w r i t i n g t o a n y a d d r e s s a f t e r s e t t i n g i t t o O t h e r b i t s a r e n o t s e t t o b y w r i t i n g t o a n y a d d r e s s a n d m u s t t h e r e f o r e b e s e t t o i n a p r o g r a m R W R W Protect bit 0 Protect bit 1 Protect bit 2 E n a b l e w r i t e t o C M 0 , C M 1 , O C D r e g i s t e r s 0 : W r i t e p r o t e c t e d W r i t e e n a b l e d Enable write to PM0, PM1 registers 0 : Write protected 1 : Write enabled1 Enable write to PD0 register 000 R W When read, its content is “0”. ( b 7 - b 6 ) Reserved bit W h e n w r i t e , m u s t s e t t o " 0 "( b 5 - b 3 ) Reserved bit RO PRC2 R W

R8C/10 Group 8. Processor Mode Rev.1.20 Jan 27, 2006 page 31 of 180 REJ09B0019-0120 8. Processor Mode

8.1 Types of Processor Mode

The processor mode is single-chip mode. Table 8.1 shows the features of the processor mode. Figure 8.1 shows the PM0 and PM1 register. Processor mode register 0(1) S y m b o lA d d r e s sA f t e r r e s e t P M 6 0 B i t n a m e FunctionBit symbol R W b 4 b PM03 ( b 1 - b 0 ) R e s e r v e d b i t Software reset bit Setting this bit to “1” resets the microcomputer. When read, its content is “0”. R W R W M u s t s e t t o “ 0 ” N O T E S : S e t t h e P R C b i t i n t h e P R C R r e g i s t e r t o w r i t e e n a b l e b e f o r e w r i t i n g t o t h i s r e g i s t e r N o t h i n g i s a s s i g n e d . W h e n w r i t e , s e t t o “ 0 ” . W h e n r e a d , i t s c o n t e n t i s i n d e t e r m i n a t e (b2) N o t h i n g i s a s s i g n e d . W h e n w r i t e , s e t t o “ 0 ” . W h e n r e a d , i t s c o n t e n t i s .( b 7 - b 4 ) Figure 8.1 PM0 Register and PM1 Register Table 8.1 Features of Processor Mode Processor mode register 1(1) S y m b o lA d d r e s sA f t e r r e s e t P M 6 0 B i t n a m e FunctionBit symbol R W b 5 b 2 b RW N O T E S : S e t t h e P R C b i t i n t h e P R C R r e g i s t e r t o w r i t e e n a b l e b e f o r e w r i t i n g t o t h i s r e g i s t e r P M b i t i s s e t t o b y w r i t i n g a i n a p r o g r a m W r i t i n g a h a s n o e f f e c t 0 : Watchdog timer interrupt 1 : Watchdog timer reset(2) W D T i n t e r r u p t / r e s e t s w i t c h b i t PM12 R W ( b 1 ) S e t t o “ 0 ” ( b 0 ) Reserved bit Nothing is assigned. When write, set to “0”. When read, its content is 0.( b 6 - b 3 ) R WS e t t o “ 0 ” R e s e r v e d b i t R WS e t t o “ 0 ” (b7) R e s e r v e d b i t Processor mode Access space Pins which are assigned I/O ports Single-chip mode SFR, internal RAM, internal ROM All pins are I/O ports or peripheral function I/O pins

R8C/10 Group 9. Bus Rev.1.20 Jan 27, 2006 page 32 of 180 REJ09B0019-0120 9. Bus During access, the ROM/RAM and the SFR have different bus cycles. Table 9.1 shows bus cycles for access space. The ROM/RAM and SFR are connected to the CPU through an 8-bit bus. When accessing in word (16 bits) units, these spaces are accessed twice in 8-bit units. Table 9.2 shows bus cycles in each access space. Space Even address byte access CPU clock Data Address SFR, Data flash Program ROM/RAM Even Odd Data Data Data Data Data Data Data Data Data Data Data Odd Odd Odd+1 Odd Odd+1 Even Even Even+1 Even+1 Data Address Data Address Data Address Data Address Data Address Data Address Data Address Odd address byte access Even address word access Odd address word access Data Even CPU clock CPU clock CPU clock CPU clock CPU clock CPU clock CPU clock Table 9.1 Bus Cycles for Access Space Access space Bus cycle SFR/Data flash 2 CPU clock cycles Program ROM/RAM 1 CPU clock cycles Table 9.2 Access Unit and Bus Operation

Rev.1.20 Jan 27, 2006 page 33 of 180 REJ09B0019-0120

• Maskable Interrupt: An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority can be changed by priority level.
• Non-maskable Interrupt: An interrupt which cannot be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority cannot be changed by priority level. Figure 10.1 Interrupts Interrupt Software (Non-maskable interrupt) Hardware Special (Non-maskable interrupt) Peripheral function(1) (Maskable interrupt) Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction INT instruction Watchdog timer Oscillation stop detection Single step (2) Address match NOTES: 1. Peripheral function interrupts are generated by the peripheral functions built in the microcomputer system. 2. Avoid using this interrupt because this is a dedicated interrupt for development support tools only. 10. Interrupt

10.1 Interrupt Overview

10.1.1 Type of Interrupts

Figure 10.1 shows types of interrupts.

Rev.1.20 Jan 27, 2006 page 34 of 180 REJ09B0019-0120

10.1.2 Software Interrupts

A software interrupt occurs when executing certain instructions. Software interrupts are non- maskable interrupts.

• Undefined Instruction Interrupt An undefined instruction interrupt occurs when executing the UND instruction.
• Overflow Interrupt An overflow interrupt occurs when executing the INTO instruction with the O flag set to “1” (the operation resulted in an overflow). The following are instructions whose O flag changes by arith- metic: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
• BRK Interrupt A BRK interrupt occurs when executing the BRK instruction.
• INT Instruction Interrupt An INT instruction interrupt occurs when executing the INT instruction. Software interrupt numbers 0 to 63 can be specified for the INT instruction. Because software interrupt numbers 4 to 31 are as- signed to peripheral function interrupts, the same interrupt routine as for peripheral function inter- rupts can be executed by executing the INT instruction. In software interrupt numbers 0 to 31, the U flag is saved to the stack during instruction execution and is cleared to “0” (ISP selected) before executing an interrupt sequence. The U flag is restored from the stack when returning from the interrupt routine. In software interrupt numbers 32 to 63, the U flag does not change state during instruction execution, and the SP then selected is used.

Rev.1.20 Jan 27, 2006 page 35 of 180 REJ09B0019-0120

10.1.3 Hardware Interrupts

Hardware interrupts are classified into two types — special interrupts and peripheral function inter- rupts. (1) Special Interrupts Special interrupts are non-maskable interrupts.

• Watchdog Timer Interrupt Generated by the watchdog timer. Once a watchdog timer interrupt is generated, be sure to initialize the watchdog timer. For details about the watchdog timer, refer to Chapter 11, “Watchdog Timer.”
• Oscillation Stop Detection Interrupt Generated by the oscillation stop detection function. For details about the oscillation stop detection function, refer to Chapter 6, “Clock Generation Circuit.”
• Single-step Interrupt Do not normally use this interrupt because it is provided exclusively for use by development support tools.
• Address Match Interrupt An address match interrupt is generated immediately before executing the instruction at the address indicated by the RMAD0 to RMAD1 register that corresponds to one of the AIER register's AIER0 or AIER1 bit which is "1" (address match interrupt enabled). For details about the address match inter- rupt, refer to Section 10.4, “Address Match Interrupt.” (2) Peripheral Function Interrupts Peripheral function interrupts are maskable interrupts and generated by the microcomputer's internal functions. The interrupt factors for peripheral function interrupts are listed in Table 10.2. “Relocatable Vector Tables”. For details about the peripheral functions, refer to the description of each peripheral function in this manual.

Rev.1.20 Jan 27, 2006 page 36 of 180 REJ09B0019-0120 Interrupt factor Vector addresses Remarks Reference Address (L) to address (H) Undefined instruction 0FFDC16 to 0FFDF16 Interrupt on UND instruction R8C/Tiny series Overflow 0FFE0 16 to 0FFE316 Interrupt on INTO instruction software manual BRK instruction 0FFE4 16 to 0FFE716 Address match 0FFE8 16 to 0FFEB16 10.4 Address match interrupt Single step(1) 0FFEC 16 to 0FFEF16 Watchdog timer, 0FFF0 16 to 0FFF316 11.Watchdog timer, oscillation stop 6. Clock generation detection circuit (Reserved) 0FFF4 16 to 0FFF716 (Reserved) 0FFF8 16 to 0FFFB16 Reset 0FFFC 16 to 0FFFF16 5. Reset NOTES: 1. Do not normally use this interrupt because it is provided exclusively for use by development support tools. Figure 10.2 Interrupt Vector /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Mid address /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Low address /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines 0 0 0 0 High address /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines 0 0 0 0 0 0 0 0 Vector address (L) LSBMSB Vector address (H)

10.1.4 Interrupts and Interrupt Vector

One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respec- tive interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the corresponding interrupt vector. Figure 10.2 shows the interrupt vector.

• Fixed Vector Tables The fixed vector tables are allocated to the addresses from 0FFDC 16 to 0FFFF16. Table 10.1 lists the fixed vector tables. In the flash memory version of microcomputer, the vector ad- dresses (H) of fixed vectors are used by the ID code check function. For details, refer to Sec- tion 17.3, “Functions to Prevent Flash Memory from Rewriting.” Table 10.1 Fixed Vector Tables If the contents of address 0FFE7 16 is FF16, program ex- ecution starts from the address shown by the vector in the relocatable vector table.

Rev.1.20 Jan 27, 2006 page 37 of 180 REJ09B0019-0120 Table 10.2 Relocatable Vector Tables S o f t w a r e i n t e r r u p t n u m b e r Reference NOTES: 1. Address relative to address in INTB. 2. These interru pts cannot be disabled using the I flag. V e c t o r a d d r e s s(1 ) A d d r e s s L t o a d d r e s s H t o I n t e r r u p t f a c t o r BRK instruction(2) R C T i n y S e r i e s s o f t w a r e m a n u a l R e s e r v e d +0 to +3 (000016 to 000316) t o t o t o t o t o t o +72 to +75 (004816 to 004B16) t o C 1 t o +80 to +83 (005016 to 005316) t o t o +88 to +91 (005816 to 005B16) t o C 1 t o t o t o t o t o +104 to +107 (006816 to 006B16) t o C 1 t o +116 to +119 (007416 to 007716) +128 to +131 (008016 to 008316) t o F C 1 t o F to t o Key input A D C o n v e r s i o n U A R T t r a n s m i t U A R T r e c e i v e U A R T t r a n s m i t U A R T r e c e i v e T i m e r X Timer Y T i m e r Z Timer C INT1 I N T I N T S o f t w a r e i n t e r r u p t(2 ) K e y i n p u t i n t e r r u p t A D c o n v e r t e r S e r i a l i n t e r f a c e I N T i n t e r r u p t R e s e r v e d I N T (Reserved) R e s e r v e d R e s e r v e d

10.2.3 INT2 interrupt

12.1 Timer X

T i m e r Y

12.3 Timer Z

T i m e r C I N T i n t e r r u p t R8C/Tiny Series software manual

12.2.4 INT3 interrupt

• Relocatable Vector Tables The 256 bytes beginning with the start address set in the INTB register comprise a relocatable vector table area. Table 10.2 lists interrupts and vector tables located in the relocatable vector table.

Rev.1.20 Jan 27, 2006 page 38 of 180 REJ09B0019-0120

10.1.5 Interrupt Control

The following describes how to enable/disable the maskable interrupts, and how to set the priority in which order they are accepted. What is explained here does not apply to nonmaskable interrupts. Use the FLG register’s I flag, IPL, and each interrupt control register's ILVL2 to ILVL0 bits to enable/ disable the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each interrupt control register. Figure 10.3 shows the interrupt control registers.

Rev.1.20 Jan 27, 2006 page 39 of 180 REJ09B0019-0120 Figure 10.3 Interrupt Control Registers S y m b o l A d d r e s sA f t e r r e s e t I N T I C D 1 6 X X X B i t n a m eF u n c t i o nB i t s y m b o l b 7b 6b 4b 3b ILVL0 IR P O L Interrupt priority level select bit Interrupt request bit Polarity select bit(3, 4) Reserved bit 0: Interrupt not requested 1: Interrupt requested 0 : Selects falling edge 1 : Selects rising edge Set to “0” I L V L 1 ILVL2 N O T E S : O n l y c a n b e w r i t t e n t o t h e I R b i t D o n o t w r i t e T o r e w r i t e t h e i n t e r r u p t c o n t r o l r e g i s t e r d o s o a t a p o i n t t h a t d o e s n o t g e n e r a t e t h e i n t e r r u p t r e q u e s t f o r t h a t r e g i s t e r R e f e r t o t h e p a r a g r a p h C h a n g i n g I n t e r r u p t C o n t r o l R e g i s t e r s I f t h e I N T O P L b i t i n t h e I N T E N r e g i s t e r i s s e t t o b o t h e d g e s s e t t h e P O L b i t t o s e l e c t i n g f a l l i n g e d g e T h e I R b i t m a y b e s e t t o i n t e r r u p t r e q u e s t e d w h e n t h e P O L b i t i s r e w r i t t e n R e f e r t o t h e p a r a g r a p h C h a n g i n g I n t e r r u p t F a c t o r I n t e r r u p t c o n t r o l r e g i s t e r(2 b Bit name FunctionBit symbol R W Symbol Address After reset KUPIC 004D 16 XXXXX000 2 ADIC 004E 16 XXXXX000 2 S0TIC, S1TIC 0051 16, 005316 XXXXX000 2 S0RIC, S1RIC 0052 16, 005416 XXXXX000 2 INT2IC 0055 16 XXXXX000 2 TXIC 0056 16 XXXXX000 2 TYIC 0057 16 XXXXX000 2 TZIC 0058 16 XXXXX000 2 INT1IC 0059 16 XXXXX000 2 INT3IC 005A 16 XXXXX000 2 TCIC 005B 16 XXXXX000 2 I L V L 0 IR I n t e r r u p t p r i o r i t y l e v e l s e l e c t b i t Interrupt request bit 0 : I n t e r r u p t n o t r e q u e s t e d I n t e r r u p t r e q u e s t e d ILVL1 ILVL2 Nothing is assigned. When write, set to “0”. When read, its content is indeterminate. 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b 0 0 0 : L e v e l 0 ( i n t e r r u p t d i s a b l e d ) L e v e l L e v e l L e v e l L e v e l L e v e l L e v e l L e v e l b2 b1 b0 R W R W R W R W (1 (b7-b4) R W R W R W R W RW RW (1) R W (b7-b6) N o t h i n g i s a s s i g n e d . W h e n w r i t e s e t t o W h e n r e a d i t s c o n t e n t i s i n d e t e r m i n a t e ( b 5 )

Rev.1.20 Jan 27, 2006 page 40 of 180 REJ09B0019-0120

• I Flag The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (enabled) enables the maskable interrupt. Setting the I flag to “0” (disabled) disables all maskable interrupts.
• IR Bit The IR bit is set to “1” (interrupt requested) when an interrupt request is generated. Then, when the interrupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is cleared to “0” (= interrupt not requested). The IR bit can be cleared to “0” in a program. Note that do not write “1” to this bit. Table 10.4 Interrupt Priority Levels Enabled by IPLTable 10.3 Settings of Interrupt Priority Levels ILVL2 to ILVL0 bits Interrupt priority level Priority order 0002 0012 0102 0112 1002 1012 1102 1112 Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Lowest Highest Enabled interrupt priority levels Interrupt levels 1 and above are enabled Interrupt levels 2 and above are enabled Interrupt levels 3 and above are enabled Interrupt levels 4 and above are enabled Interrupt levels 5 and above are enabled Interrupt levels 6 and above are enabled Interrupt levels 7 and above are enabled All maskable interrupts are disabled IPL 000 0012 0102 0112 1002 1012 1102 1112
• ILVL2 to ILVL0 Bits and IPL Interrupt priority levels can be set using the ILVL2 to ILVL0 bits. Table 10.3 shows the settings of interrupt priority levels and Table 10.4 shows the interrupt priority levels enabled by the IPL. The following are conditions under which an interrupt is accepted:
• I flag = 1
• IR bit = 1
• interrupt priority level > IPL The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. In no case do they affect one another.

Rev.1.20 Jan 27, 2006 page 41 of 180 REJ09B0019-0120 Figure 10.4 Time Required for Executing Interrupt Sequence

• Interrupt Sequence An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed — is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. The CPU behavior during the interrupt sequence is described below. Figure 10.4 shows time re- quired for executing the interrupt sequence. (1) The CPU gets interrupt information (interrupt number and interrupt request priority level) by read- ing the address 00000 16. Then it clears the IR bit for the corresponding interrupt to “0” (interrupt not requested). (2) The FLG register immediately before entering the interrupt sequence is saved to the CPU internal temporary register(1). (3) The I, D and U flags in the FLG register become as follows: The I flag is cleared to “0” (interrupts disabled). The D flag is cleared to “0” (single-step interrupt disabled). The U flag is cleared to “0” (ISP selected). However, the U flag does not change state if an INT instruction for software interrupt numbers 32 to 63 is executed. (4) The CPU’s internal temporary register (1) is saved to the stack. (5) The PC is saved to the stack. (6) The interrupt priority level of the accepted interrupt is set in the IPL. (7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC. After the interrupt sequence is completed, the processor resumes executing instructions from the start address of the interrupt routine. NOTES: 1. This register cannot be used by user. Indeterminate Indeterminate SP-2

contents

000016 Indeterminate SP-2 SP-4 VEC VEC+2 PC

The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the instruction queue buffer is ready to accept instructions. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 RD VEC+1 contentsSP-3

Rev.1.20 Jan 27, 2006 page 42 of 180 REJ09B0019-0120 Interrupt factors Level that is set to IPL Watchdog timer, oscillation stop detection Software, address match, single-step Not changed

• Variation of IPL when Interrupt Request is Accepted When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL. When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed in Table 10.5 is set in the IPL. Shown in Table 10.5 are the IPL values of software and special interrupts when they are accepted. Table 10.5 IPL Level That Is Set to IPL When A Software or Special Interrupt Is Accepted Figure 10.5 Interrupt Response Time
• Interrupt Response Time Figure 10.5 shows the interrupt response time. The interrupt response or interrupt acknowledge time denotes a time from when an interrupt request is generated till when the first instruction in the inter- rupt routine is executed. Specifically, it consists of a time from when an interrupt request is gener- ated till when the instruction then executing is completed (see #a in Figure 10.5) and a time during which the interrupt sequence is executed (20 cycles, see #b in Figure 10.5). Instruction Interrupt sequence Instruction in interrupt routine Time Interrupt response time (a) 20 cycles (b) Interrupt request acknowledgedInterrupt request generated (a) A time from when an interrupt request is generated till when the instruction then executing is completed. The length of this time varies with the instruction being executed. The DIVX instruction requires the longest time, which is equal to 30 cycles (without wait state, the divisor being a register). (b) 21 cycles for address match and single-step interrupts.

Rev.1.20 Jan 27, 2006 page 43 of 180 REJ09B0019-0120

• Saving Registers In the interrupt sequence, the FLG register and PC are saved to the stack. At this time, the 4 high-order bits in the PC and the 4 high-order (IPL) and 8 low-order bits in the FLG register, 16 bits in total, are saved to the stack first. Next, the 16 low-order bits in the PC are saved. Figure 10.6 shows the stack status before and after an interrupt request is accepted. The other necessary registers must be saved in a program at the beginning of the interrupt routine. The PUSHM instruction can save several registers in the register bank being currently used (1) with a single instruction. NOTES: 1. Selectable from registers R0, R1, R2, R3, A0, A1, SB, and FB. Address Content of previous stack Stack [SP] SPvalue before interrupt occurs m m – 1 m – 2 m – 3 m – 4 Stack status before interrupt request is acknowledged Stack status after interrupt request is acknowledged Content of previous stackm + 1 MSB LSB m m – 1 m – 2 m – 3 m – 4 Address FLG L Content of previous stack Stack FLG H PC H [SP] New SP value Content of previous stackm + 1 MSB LSB PC L PC M Figure 10.6 Stack Status Before and After Acceptance of Interrupt Request Figure 10.7 Operation of Saving Register S P S P S P S P S P S P A d d r e s s Sequence in which order registers are saved ( 2 ) ( 1 ) F i n i s h e d s a v i n g r e g i s t e r s i n f o u r o p e r a t i o n s ( 3 ) ( 4 ) N O T E S S P d e n o t e s t h e i n i t i a l v a l u e o f t h e S P w h e n i n t e r r u p t r e q u e s t i s a c k n o w l e d g e d A f t e r r e g i s t e r s a r e s a v e d t h e S P c o n t e n t i s S P m i n u s PC M Stack FLG L PC L S a v e d b i t s a t a t i m e FLG H PC H The registers are saved in four steps, 8 bits at a time. Figure 10.7 shows the operation of the saving registers. NOTES: 1. When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indi- cated by the U flag. Otherwise, it is the ISP.

Rev.1.20 Jan 27, 2006 page 44 of 180 REJ09B0019-0120

• Interrupt Priority If two or more interrupt requests are generated while executing one instruction, the interrupt request that has the highest priority is accepted. For maskable interrupts (peripheral functions), any desired priority level can be selected using the ILVL2 to ILVL0 bits. However, if two or more maskable interrupts have the same priority level, their interrupt priority is resolved by hardware, with the highest priority interrupt accepted. The watchdog timer and other special interrupts have their priority levels set in hardware. Figure 10.8 shows the Hardware Interrupt Priority. Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches invariably to the interrupt routine.
• Returning from an Interrupt Routine The FLG register and PC in the state in which they were immediately before entering the interrupt sequence are restored from the stack by executing the REIT instruction at the end of the interrupt routine. Thereafter the CPU returns to the program which was being executed before accepting the interrupt request. Return the other registers saved by a program within the interrupt routine using the POPM or similar instruction before executing the REIT instruction. Figure 10.8 Hardware Interrupt Priority Reset > WDT/Oscillation stop detection > Peripheral function > Single step > Address match

Rev.1.20 Jan 27, 2006 page 45 of 180 REJ09B0019-0120 Figure 10.9 Interrupts Priority Select Circuit Interrupt request accepted Highest Lowest P r i o r i t y o f p e r i p h e r a l f u n c t i o n i n t e r r u p t s i f p r i o r i t y l e v e l s a r e s a m e Interrupt request level resolution output signal Timer Z Timer X Timer C Timer Y U A R T 1 r e c e p t i o n UART0 reception A/D conversion UART1 transmission UART0 transmission Key input interrupt I P L I f l a g I N T 3 INT2 I N T 1 Priority level of each interrupt A d d r e s s m a t c h Watchdog timer I N T 0 Oscillation stop detection

• Interrupt Priority Resolution Circuit The interrupt priority resolution circuit is used to select the interrupt with the highest priority among those requested. Figure 10.9 shows the Interrupts Priority Select Circuit.

Rev.1.20 Jan 27, 2006 page 46 of 180 REJ09B0019-0120

10.2 INT Interrupt

10.2.1 INT0 Interrupt

INT0 interrupt is triggered by an INT0 input. When using INT0 interrupts, the INT0EN bit in the INTEN register must be set to “1” (enabling). The edge polarity is selected using the INT0PL bit in the INTEN register and the POL bit in the INT0IC register. Inputs can be passed through a digital filter with three different sampling clocks. The INT0 pin is shared with the external trigger input pin of Timer Z. Figure 10.10 shows the INTEN and INT0F registers. Figure 10.10 INTEN Register and INT0F Register E x t e r n a l i n p u t e n a b l e r e g i s t e r Bit name F u n c t i o nBit symbol R W S y m b o lA d d r e s sA f t e r r e s e t I N T E N 6 0 I N T 0 E N b 5b 4b I N T i n p u t e n a b l e b i t(1 ) 0 : D i s a b l e d E n a b l e d 0 : O n e e d g e B o t h e d g e s Set to “0” I N T i n p u t p o l a r i t y s e l e c t b i t(2 Reserved bit I N T 0 P L ( b 7 - b 2 ) NOTES: 1. This bit must be set while the INT0STG bit in the PUM register is set to “0” (one-shot trigger disabled). 2. When setting the INT0PL bit to “1” (selecting both edges), the POL bit in the INT0IC must be set to “0” (selecting falling edge). 3. The IR bit in the INT0IC register may be set to “1” (interrupt requested) when the INT0PL bit is rewritten. Refer to the paragraph 19.2.5 “Changing Interrupt Factor” in the Usage Notes Reference Book. I N T 0 i n p u t f i l t e r s e l e c t r e g i s t e r Bit name F u n c t i o nB i t s y m b o l S y m b o lA d d r e s sA f t e r r e s e t I N T F 6 X X X X X INT0F0 b7 b6 b5 b4 b3 b2 b1 b0 0 0 : N o f i l t e r F i l t e r w i t h s a m p l i n g F i l t e r w i t h s a m p l i n g F i l t e r w i t h s a m p l i n g Set to “0”Reserved bit I N T 0 F 1 b b INT0 input filter select bit Nothing is assigned. When write, set to “0”. If read, it content is indeterminate. R W R W RW RW RW R W RW (b2) ( b 7 - b 3 ) 0000 00

Rev.1.20 Jan 27, 2006 page 47 of 180 REJ09B0019-0120

10.2.2 INT0 Input Filter

The INT0 input has a digital filter which can be sampled by one of three sampling clocks. The sampling clock is selected using the INT0F1 to INT0F0 bits in the INT0F register. The IR bit in the INT0IC register is set to “1” (interrupt requested) when the sampled input level matches three times. When the INT0F1 to INT0F0 bits are set to “01 2”, “102”, or “112”, the P4_5 bit in the P4 register indicates the filtered value. Figure 10.11 shows the INT0 input filter configuration. Figure 10.12 shows an operation example of INT0 input filter. Figure 10.11 INT0 Input Filter Digital filter (input level matches 3x)Port P45 direction register f32 INT0 INT0 interrupt INT0EN INT0F1 to INT0F0 =012 =102 =112 INT0F1 to INT0F0 =002 =002 P4_5 bit Other than Sampling clock INT0F0, INT0F1: Bits in INT0F register INT0EN: Bit in INTEN register Figure 10.12 Operation Example of INT0 Input Filter P45 input Sampling timing P4_5 in P4 register IR bit in INT0IC register Set to “0” in program This is an operation example when the INT0F1 to INT0F0 bits in the INT0F register is set to “012”, “102”, or “112” (passing digital filter).

Rev.1.20 Jan 27, 2006 page 48 of 180 REJ09B0019-0120

10.2.3 INT1 Interrupt and INT2 Interrupt

INT1 interrupts are triggered by INT1 inputs. The edge polarity is selected with the R0EDG bit in the TXMR register. The INT1 pin is shared with the CNTR0 pin. INT2 interrupts are triggered by INT2 inputs. The edge polarity is selected with the R1EDG bit in the TYZMR register. The INT2 pin is shared with the CNTR1 pin. Figure 10.13 shows the TXMR and TYZMR registers when using INT1 and INT2 interrupts. Figure 10.13 TXMR Register and TYZMR Register when INT1 and INT2 Interrupt Used T i m e r X m o d e r e g i s t e r S y m b o lA d d r e s sA f t e r r e s e t T X M 6 0 Bit name FunctionB i t s y m b o l R W b 7 b 6 b 5 b 4 b 3 b 2 b1 b 0 0 0 : Timer mode or pulse period measurement mode(3) b b T X M O D 2 TXS T X M O D 1 R 0 E D G T X M O D 0 T X O C N T Operation mode select bit 0, 1 Timer X count start flag 0 : S t o p s c o u n t i n g S t a r t s c o u n t i n g O p e r a t i o n m o d e s e l e c t b i t 00 0 S e t t o " 0 " i n t i m e r m o d e 0 : R i s i n g e d g e F a l l i n g e d g e TXEDG TXUND R W R W R W R W RW R W RW RW INT1/CNTR 0 polarity switching bit(1, 2) Set to "0" in timer mode S e t t o " 0 " i n t i m e r m o d e 0 : Other than pulse period measurement mode (3) N O T E S : T h e I R b i t i n t h e I N T I C m a y b e s e t t o i n t e r r u p t r e q u e s t e d w h e n t h e R E D G b i t i s r e w r i t t e n R e f e r t o t h e p a r a g r a p h C h a n g i n g I n t e r r u p t F a c t o r i n t h e U s a g e N o t e s R e f e r e n c e B o o k T h i s b i t i s u s e d t o s e l e c t t h e p o l a r i t y o f I N T i n t e r r u p t i n t i m e r m o d e W h e n u s i n g I N T i n t e r r u p t s s h o u l d s e l e c t t i m e r m o d e T i m e r Y , Z m o d e r e g i s t e r S y m b o lA d d r e s sA f t e r r e s e t T Y Z M 6 0 B i t n a m e F u n c t i o nB i t s y m b o l b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 T Z M O D 1 T Y S T Y W C T Y M O D 0 T Z M O D 0 T i m e r Y o p e r a t i o n m o d e b i t T i m e r Y w r i t e c o n t r o l b i t 0 : Timer mode(1) T Z W C T Z S 0 : Stops counting 1 : Starts counting Timer Z-related bit Timer Y count start flag R W R W R W R W R W R W R 1 E D G 0 : Rising edge 1 : Falling edge I N T 2 / C N T R 1 p o l a r i t y s w i t c h i n g b i t(2 R W R W R W N O T E S : W h e n u s i n g I N T i n t e r r u p t s m u s t s e t t o t i m e r m o d e T h e I R b i t i n t h e I N T I C m a y b e s e t t o i n t e r r u p t r e q u e s t e d w h e n t h e R E D G b i t i s r e w r i t t e n R e f e r t o t h e p a r a g r a p h C h a n g i n g I n t e r r u p t F a c t o r i n t h e U s a g e N o t e s R e f e r e n c e B o o k F u n c t i o n v a r i e s d e p e n d i n g o n t h e o p e r a t i o n m o d e

Rev.1.20 Jan 27, 2006 page 49 of 180 REJ09B0019-0120 Figure 10.14 TCC0 Register and TCC1 Register

10.2.4 INT3 Interrupt

INT3 interrupts are triggered by INT3 inputs. The TCC07 bit in the TCC0 register should be se to “0” (INT3). The INT3 input has a digital filter which can be sampled by one of three sampling clocks. The sampling clock is selected using the TCC11 to TCC10 bits in the TCC1 register. The IR bit in the INT3IC register is set to “1” (interrupt requested) when the sampled input level matches three times. The P3_3 bit in the P3 register indicates the previous value before filtering regardless of values set in the TCC11 to TCC10 bits. The INT3 pin is shared with the TCIN pin. When setting the TCC07 bit to “1” (fRING128 ), INT3 interrupts are triggered by fRING128 clock. The IR bit in the INT3IC register is set to “1” (interrupt requested) every fRING128 clock cycle or every half fRING128 clock cycle. Figure 10.14 shows the TCC0 and TCC1 registers. T i m e r C c o n t r o l r e g i s t e r 0 S y m b o lA d d r e s sA f t e r r e s e t T C C 6 0 B i t n a m e F u n c t i o nB i t s y m b o l b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 0 : f1 A v o i d t h i s s e t t i n g T C C 0 4 T C C 0 2 T C C 0 1 T C C 0 0 T C C 0 3 C a p t u r e c o n t r o l b i t T i m e r C c o u n t s o u r c e s e l e c t b i t(1) 0 : C a p t u r e d i s a b l e d C a p t u r e e n a b l e d T C C 0 7 b b T i m e r C c o n t r o l r e g i s t e r 1 S y m b o lA d d r e s sA f t e r r e s e t T C C 6 0 B i t n a m e F u n c t i o nB i t s y m b o l b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 T C C 1 1 T C C 1 0 0 0 : R i s i n g e d g e F a l l i n g e d g e B o t h e d g e s A v o i d t h i s s e t t i n g b b b b I N T i n p u t f i l t e r s e l e c t b i t(1 N O T E S : I n p u t i s r e c o g n i z e d o n l y w h e n t h e s a m e v a l u e f r o m I N T p i n i s s a m p l e d t h r e e t i m e s i n s u c c e s s i o n R W ( b 6 - b 5 ) I N T 3 i n t e r r u p t / c a p t u r e i n p u t p o l a r i t y s e l e c t b i t(1 I N T 3 i n t e r r u p t / c a p t u r e i n p u t s w i t c h i n g b i t(1 0 : I N T 3 fR I N G R W R W R W R W R e s e r v e d b i t ( b 7 - b 2 ) R W R W R W R W 0 0 : N o f i l t e r F i l t e r w i t h s a m p l i n g F i l t e r w i t h s a m p l i n g F i l t e r w i t h s a m p l i n g N O T E S : M o d i f y t h i s b i t w h e n t h e T C C b i t i s s e t t o c o u n t s t o p s T h e I R b i t i n t h e I N T I C m a y b e s e t t o i n t e r r u p t r e q u e s t e d w h e n t h e T C C T C C o r T C C b i t i s r e w r i t t e n R e f e r t o t h e p a r a g r a p h C h a n g i n g I n t e r r u p t F a c t o r i n t h e U s a g e N o t e s R e f e r e n c e B o o k 0 0 0 0 0 0 R W R W r e s e r v e d b i t S e t t o " 0 " S e t t o " 0 " R W

Rev.1.20 Jan 27, 2006 page 50 of 180 REJ09B0019-0120 Key input interrupt request Pull-up transistor Pull-up transistor Pull-up transistor KI3 KI2 PU02 bit in PUR0 register PD1_3 bit in PD1 register KI1 KI0 PD1_3 bit KI3EN bit PD1_2 bit KI2EN bit PD1_1 bit KI1EN bit PD1_0 bit KI0EN bit KI3PL=1 KI3PL=0 KI2PL=1 KI2PL=0 KI1PL=1 KI1PL=0 KI0PL=1 KI0PL=0 KUPIC register Interrupt control circuit Pull-up transistor KI0EN, KI1EN, KI2EN, KI3EN, KI0PL, KI1PL, KI2PL, KI3PL: Bits in KIEN register PD1_0, PD1_1, PD1_2, PD1_3: Bits in PD1 registerFigure 10.15 Key Input Interrupt

10.3 Key Input Interrupt

A key input interrupt is generated on an input edge of any of the K10 to K13 pins. Key input interrupts can be used as a key-on wakeup function to exit wait or stop mode. KIi input can be enabled or disabled selecting with the KIiEN (i=0 to 3) bit in the KIEN register. The edge polarity can be rising edge or falling edge selecting with the KIiPL bit in the KIEN register. Note, however, that while input on any KIi pin which has had the KIiPL bit set to “0” (falling edge) is pulled low, inputs on all other pins of the port are not detected as interrupts. Similarly, while input on any KIi pin which has had the KIiPL bit set to “1” (rising edge) is pulled high, inputs on all other pins of the port are not detected as interrupts. Figure 10.15 shows a block diagram of the key input interrupt. Figure 10.16 KIEN Register Key input enable register Bit name FunctionBit symbol R W S y m b o lA d d r e s sA f t e r r e s e t K I E N 6 0 K I 0 E N b 6b 5b 2b 1b KI0 input enable bit 0 : Disabled 1 : Enabled 0 : Falling edge 1 : Rising edges 0 : Disabled 1 : Enabled 0 : Falling edge 1 : Rising edges 0 : Disabled 1 : Enabled KI0 input polarity select bit KI1 input enable bit KI1 input polarity select bit KI2 input enable bit KI2 input polarity select bit 0 : Falling edge 1 : Rising edges K I 0 P L K I 1 E N K I 1 P L K I 2 E N K I 2 P L KI3 input enable bit 0 : Disabled 1 : Enabled K I 3 E N KI3 input polarity select bit 0 : Falling edge 1 : Rising edges K I 3 P L R W R W R W R W R W RW RW R W N O T E S : T h e I R b i t i n t h e K U P I C r e g i s t e r m a y b e s e t t o i n t e r r u p t r e q u e s t e d w h e n t h e K I E N r e g i s t e r i s r e w r i t t e n R e f e r t o t h e p a r a g r a p h C h a n g i n g I n t e r r u p t F a c t o r i n t h e U s a g e N o t e s R e f e r e n c e B o o k

Rev.1.20 Jan 27, 2006 page 51 of 180 REJ09B0019-0120

10.4 Address Match Interrupt

An address match interrupt is generated immediately before executing the instruction at the address indicated by the RMADi register (i=0, 1). Set the start address of any instruction in the RMADi register. Use the AIER0 and AIER1 bits in the AIER register to enable or disable the interrupt. Note that the address match interrupt is unaffected by the I flag and IPL. The value of the PC that is saved to the stack when an address match interrupt is acknowledged varies depending on the instruction at the address indicated by the RMAD i register (see the paragraph “register saving” for the value of the PC). Not appropriate return address is pushed on the stack. There are two ways to return from the address match interrupt as follows:

• Change the content of the stack and use a REIT instruction.
• Use an instruction such as POP to restore the stack as it was before an interrupt request was acknowl- edged. And then use a jump instruction. Table 10.6 lists the value of the PC that is saved to the stack when an address match interrupt is acknowl- edged. Figure 10.17 shows the AIER, and RMAD1 to RMAD0 registers. Table 10.6 Value of PC Saved to Stack when Address Match Interrupt Acknowledged Address indicated by RMADi register (i=0,1) PC value saved(1)
• 16-bit operation code instruction Address indicated by
• Instruction shown below among 8-bit operation code instructions RMADi register + 2 ADD.B:S #IMM8,dest SUB.B:S #IMM8,dest AND.B:S #IMM8,dest OR.B:S #IMM8,dest MOV.B:S #IMM8,dest STZ.B:S #IMM8,dest STNZ.B:S #IMM8,dest STZX.B:S #IMM81,#IMM82,dest CMP.B:S #IMM8,dest PUSHM src POPM dest JMPS #IMM8 JSRS #IMM8 MOV.B:S #IMM,dest (However, dest = A0 or A1)
• Instructions other than the above Address indicated by RMADi register + 1 NOTES: 1. See the paragraph “saving registers” for the PC value saved. Table 10.7 Relationship Between Address Match Interrupt Factors and Associated Registers Address match interrupt factors Address match interrupt enable bit Address match interrupt register Address match interrupt 0 AIER0 RMAD0 Address match interrupt 1 AIER1 RMAD1

Rev.1.20 Jan 27, 2006 page 52 of 180 REJ09B0019-0120 Bit nameBit symbol Symbol Address After reset AIER 0009 16 XXXXXX00 2 Address match interrupt enable register Function RW /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Address match interrupt 0 enable bit 0 : Interrupt disabled 1 : Interrupt enabled AIER0 Address match interrupt 1 enable bit AIER1 b7 b6 b5 b4 b3 b2 b1 b0 0 : Interrupt disabled 1 : Interrupt enabled RW RW (b7-b2) Nothing is assigned. When write, set to “0”. When read, their contents are indeterminate. Symbol Address After reset RMAD0 0012 16 to 001016 X0000016 RMAD1 0016 16 to 001416 X0000016 Address setting register for address match interrupt Function Setting range Address match interrupt register i (i = 0, 1) 0000016 to FFFFF16 b0 b7 b0b3 (b19) (b16) b7 b0 (b15) (b8) (b23) RW RW Nothing is assigned. When write, set to “0”. When read, its content is indeterminate.(b7-b4) Figure 10.17 AIER Register and RMAD0 to RMAD1 Registers

R8C/10 Group 11. Watchdog Timer Rev.1.20 Jan 27, 2006 page 54 of 180 REJ09B0019-0120 Watchdog timer start register Symbol Address After reset WDTS 000E 16 Indeterminate WO b7 b0 Function The watchdog timer starts counting after a write instruction to this register. RW Watchdog timer reset register Symbol Address After reset WDTR 000D 16 Indeterminate WO b7 b0 Function RW The watchdog is initialized after a write instruction to this register. The watchdog timer value is always initialized to “7FFF 16” regardless of whatever value is written. Figure 11.2 WDC Register, WDTR Register, and WDTS Register W a t c h d o g t i m e r c o n t r o l r e g i s t e r Symbol Address After reset WDC 000F 16 000111112 F u n c t i o nB i t s y m b o lR W b 1b 0 H i g h - o r d e r b i t o f w a t c h d o g t i m e r W D C 7 B i t n a m e P r e s c a l e r s e l e c t b i t0 : D i v i d e d b y 1 6 D i v i d e d b y R e s e r v e d b i tM u s t s e t t o “ 0 ” RO RW RW RW ( b 4 - b 0 ) ( b 6 ) ( b 5 ) R e s e r v e d b i tM u s t s e t t o “ 0 ”

Rev.1.20 Jan 27, 2006 page 55 of 180 REJ09B0019-0120 12. Timers The microcomputer has three 8-bit timers and one 16-bit timer. The three 8-bit timers are Timer X, Timer Y, and Timer Z and each one has an 8-bit prescaler. The 16-bit timer is Timer C and has a capture. All these timers function independently. The count source for each timer is the operating clock that regulates the timing of timer operations such as counting and reloading. Table 12.1 lists functional comparison. Item Timer X Timer Y Timer Z Timer C Configuration 8-bit timer 8-bit timer 8-bit timer 16-bit timer with 8-bit with 8-bit with 8-bit prescaler prescaler prescaler Count Down Down Down Up Count source •f 1 •f1 •f1 •f1

• f2 •f8 •f2 •f8
• f8 •fRING •f8 •f32
• f32 •Input from •Timer Y CNTR 1 pin underflow Function Timer mode provided provided provided not provided Pulse output mode provided not provided not provided not provided Event counter mode provided provided (1) not provided not provided Pulse width measurement mode provided not provided not provided not provided Pulse period measurement mode provided not provided not provided not provided Programmable waveform generation mode not provided provided provided not provided Programmable one-shot generation mode not provided not provided provided not provided Programmable wait one-shot generation mode not provided not provided provided not provided Capture not provided not provided not provided provided Input pin CNTR 0 CNTR 1 INT0 TC IN Output pin CNTR 0 CNTR 0 CNTR 1 TZOUT not provided Related interrupt Timer X int Timer Y int Timer Z int Timer C int INT1 int INT2 int INT0 int INT3 int Timer stop provided provided provided provided Table 12.1 Functional Comparison NOTES: 1. Select the input from the CNTR1 pin as a count source of timer mode. 12. Timers

Rev.1.20 Jan 27, 2006 page 56 of 180 REJ09B0019-0120 T X C K 1 t o T X C K 0 f32 Toggle flip-flop P o l a r i t y s w i t c h i n g Q Q C K TXOCNT bit CNTR 0 R0EDG=0 CLR T X M O D 1 t o T X M O D 0 b i t s = 0 1 Counter Reload register C o u n t e r R e l o a d r e g i s t e r T X S b i t PREX register TX registe r Write to TX register T i m e r X i n t e r r u p t Data bus I N T 1 i n t e r r u p tI N T1/ C N T R 0 R0EDG =1 T X M O D 1 t o T X M O D 0 b i t s = 0 12 = 0 12 = 1 02 = 1 12 T X M O D 1 t o T X M O D 0 o r = 1 02 = 1 12 Figure 12.1 Timer X Block Diagram Figure 12.2 TXMR Register The Timer X is an 8-bit timer with an 8-bit prescaler. Figure 12.1 shows the block diagram of Timer X. Figures 12.2 and 12.3 show the Timer X-related registers. The Timer X has five operation modes listed as follows:

• Timer mode: The timer counts an internal count source.
• Pulse output mode: The timer counts an internal count source and outputs the pulses whose polarity is inverted at the timer the timer underflows.
• Event counter mode: The timer counts external pulses.
• Pulse width measurement mode: The timer measures an external pulse's pulse width.
• Pulse period measurement mode:The timer measures an external pulse's period.

12.1 Timer (Timer X)

T i m e r X m o d e r e g i s t e r Symbol Address After reset TXMR 008B 16 0016 B i t n a m e FunctionB i t s y m b o l RW b7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 0 : Timer mode or pulse period measurement mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode b1 b0 T X M O D 2 TXS T X M O D 1 R0EDG T X M O D 0 TXOCNT I N T 1 / C N T R 0 p o l a r i t y s w i t c h i n g b i t(1 Operation mode select bit 0, 1 T i m e r X c o u n t s t a r t f l a g 0 : Stops counting 1 : Starts counting P 30/ C N T R 0 s e l e c t b i t Operation mode select bit 2 0 : Except in pulse period measurement mode 1 : Pulse period measurement mode Function varies with each operation mode T X E D G T X U N D T i m e r X u n d e r f l o w f l a g Function varies depending on operation mode.Active edge reception flag F u n c t i o n v a r i e s d e p e n d i n g o n o p e r a t i o n m o d e . RW RW RW RW RW RW RW RW Function varies with each operation mode N O T E S : T h e I R b i t i n t h e I N T I C r e g i s t e r m a y b e s e t t o i n t e r r u p t r e q u e s t e d w h e n t h e R E D G b i t i s r e w r i t t e n R e f e r t o t h e p a r a g r a p h C h a n g i n g I n t e r r u p t F a c t o r i n t h e U s a g e N o t e s R e f e r e n c e B o o k

Rev.1.20 Jan 27, 2006 page 57 of 180 REJ09B0019-0120 Figure 12.3 PREX Register, TX Register, and TCSS Register B i t n a m e Function B i t s y m b o l T i m e r X c o u n t s o u r c e s e l e c t b i t(1 b1 b0 T X C K 1 T X C K 0 T Y C K 0 T i m e r Y c o u n t s o u r c e s e l e c t b i t(1 T Z C K 0 T Y C K 1 T Z C K 1 M u s t b e s e t t o “ 0 ” ( b 7 - b 6 ) R e s e r v e d b i t T i m e r Z c o u n t s o u r c e s e l e c t b i t(1 N O T E S : A v o i d s w i t c h i n g a c o u n t s o u r c e w h i l e a c o u n t e r i s i n p r o g r e s s T i m e r c o u n t e r m u s t b e s t o p p e d b e f o r e s w i t c h i n g a c o u n t s o u r c e T i m e r c o u n t s o u r c e s e t t i n g r e g i s t e r S y m b o lA d d r e s sA f t e r r e s e t T C S 6 0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : f2 b3 b2 0 0 : f1 0 1 : f8 1 0 : fRING 1 1 : Selects input from CNTR1 pin b b 0 0 : f1 0 1 : f8 1 0 : Selects Timer Y underflow 1 1 : f2 RW RW RW RW RW RW R W R W 0 0 Symbol Address After reset TX 008D 16 FF16 Underflow of Prescaler X is counted Function Timer X Register Symbol Address After reset PREX 008C 16 FF16 b7 b0 RW Internal count source is counted Function Setting range Prescaler X Register b7 b0 0016 to FF16 0016 to FF16 Internal count source is counted 0016 to FF16 Externally input pulses are counted0016 to FF16 Pulse width of externally input pulses is measured (Internal count source is counted) 0016 to FF16 Pulse period of externally input pulses is measured (Internal count source is counted) 0016 to FF16 Timer mode Pulse output mode Event counter mode Pulse width measurement mode Pulse period measurement mode Mode RW RW RW RW RW RW RW Setting range

Rev.1.20 Jan 27, 2006 page 58 of 180 REJ09B0019-0120

12.1.1 Timer Mode

In this mode, the timer counts an internally generated count source (See “Table 12.2 Timer Mode Specifications”). Figure 12.4 shows the TXMR register in timer mode. Item Specification Count source f 1, f2, f8, f32 Count operation • Down-count

• When the timer underflows, the contents in the reload register is reloaded and the count is continued Divide ratio 1/(n+1)(m+1) n: set value of PREX register, m: set value of TX register Count start condition Write “1” (count start) to TXS bit in TXMR register Count stop condition Write “0” (count stop) to TXS bit in TXMR register Interrupt request generation timingWhen Timer X underflows [Timer X interruption] INT1/CNTR 0 pin function Programmable I/O port, or INT1 interrupt input CNTR 0 pin function Programmable I/O port Read from timer Count value can be read by reading TX register Same applies to PREX register. Write to timer Value written to TX register is written to both reload register and counter. Same applies to PREX register. Table 12.2 Timer Mode Specifications Figure 12.4 TXMR Register in Timer Mode

S y m b o lA d d r e s sA f t e r r e s e t T X M 6 0 B i t n a m e FunctionB i t s y m b o l R W b 7 b 6 b5 b 4 b 3 b 2 b 1 b 0 0 0 : Timer mode or pulse period measurement mode b1 b0 T X M O D 2 T X S TXMOD1 R0EDG TXMOD0 T X O C N T O p e r a t i o n m o d e s e l e c t b i t T i m e r X c o u n t s t a r t f l a g 0 : S t o p s c o u n t i n g S t a r t s c o u n t i n g O p e r a t i o n m o d e s e l e c t b i t 00 0 S e t t o " 0 " i n t i m e r m o d e 0 : Rising edge 1 : Falling edge TXEDG T X U N D R W RW RW RW R W R W R W R W INT1/CNTR 0 polarity switching bit(1, 2) S e t t o " 0 " i n t i m e r m o d e Set to "0" in timer mode 0 : Other than pulse period measurement mode N O T E S : T h e I R b i t i n t h e I N T I C r e g i s t e r m a y b e s e t t o i n t e r r u p t r e q u e s t e d w h e n t h e R E D G b i t i s r e w r i t t e n R e f e r t o t h e p a r a g r a p h C h a n g i n g I n t e r r u p t F a c t o r i n t h e U s a g e N o t e s R e f e r e n c e B o o k T h i s b i t i s u s e d t o s e l e c t t h e p o l a r i t y o f I N T i n t e r r u p t i n t i m e r m o d e

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12.1.2 Pulse Output Mode

In this mode, the timer counts an internally generated count source, and outputs from the CNTR0 pin a pulse whose polarity is inverted each time the timer underflows (See “Table 12.3 Pulse Output mode Specifications”). Figure 12.5 shows TXMR register in pulse output mode. Item Specification Count source f 1, f2, f8, f32 Count operation • Down-count

• When the timer underflows, the contents in the reload register is reloaded and the count is continued Divide ratio 1/(n+1)(m+1) n: set value of PREX register, m: set value of TX register Count start condition Write “1” (count start) to TXS bit in TXMR register Count stop condition Write “0” (count stop) to TXS bit in TXMR register Interrupt request • When Timer X underflows [Timer X interruption] generation timing INT1/CNTR 0 pin function Pulse output CNTR 0 pin function Programmable I/O port or inverted output of CNTR0 Read from timer Count value can be read by reading TX register. Same applies to PREX register. Write to timer Value written to TX register is written to both reload register and counter. Same applies to PREX register. Select function
• INT1/CNTR0 polarity switching function Polarity level at starting of pulse output can be selected with R0EDG bit(1)
• Inverted pulse output function The inverted pulse of CNTR0 output polarity can be output from the CNTR0 pin (selected by the TXOCNT bit) NOTES: 1. The level of the output pulse becomes the level when the pulse output starts when the TX register is written to. Table 12.3 Pulse Output Mode Specifications Figure 12.5 TXMR Register in Pulse Output Mode

S y m b o lA d d r e s sA f t e r r e s e t T X M 6 0 B i t n a m e F u n c t i o nB i t s y m b o l b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 1 : P u l s e o u t p u t m o d e b b T X M O D 2 TXS T X M O D 1 R 0 E D G T X M O D 0 T X O C N T O p e r a t i o n m o d e s e l e c t b i t 0 : C N T R 0 o u t p u t s t a r t s a t " H " C N T R 0 o u t p u t s t a r t s a t L Timer X count start flag 0 : Stops counting 1 : Starts counting P 30/ C N T R 0 s e l e c t b i t 0 : P o r t P 30 C N T R 0 o u t p u t S e t t o " 0 " i n p u l s e o u t p u t m o d e 0 0 1 T X E D G T X U N D R W R W R W R W R W R W R W R W R W I N T 1 / C N T R 0 p o l a r i t y s w i t c h i n g b i t(1 S e t t o " 0 " i n p u l s e o u t p u t m o d e S e t t o " 0 " i n p u l s e o u t p u t m o d e N O T E S : T h e I R b i t i n t h e I N T I C r e g i s t e r m a y b e s e t t o i n t e r r u p t r e q u e s t e d w h e n t h e R E D G b i t i s r e w r i t t e n R e f e r t o t h e p a r a g r a p h C h a n g i n g I n t e r r u p t F a c t o r i n t h e U s a g e N o t e s R e f e r e n c e B o o k

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12.1.3 Event Counter Mode

In this mode, the timer counts an external signal fed to INT1/CNTR0 pin (See “Table 12.4 Event Counter Mode Specifications”). Figure 12.6 shows TXMR register in event counter mode. Item Specification Count source External signals fed to CNTR 0 pin (Active edge is selected by program) Count operation • Down count

• When the timer underflows, the contents in the reload register is reloaded and the count is continued Divide ratio 1/(n+1)(m+1) n: set value of PREX register, m: set value of TX register Count start condition Write “1” (count start) to TXS bit in TXMR register Count stop condition Write “0” (count stop) to TXS bit in TXMR register Interrupt request • When Timer X underflows [Timer X interrupt] generation timing INT1/CNTR0 pin function Count source input (INT1 interrupt input) CNTR 0 pin function Programmable I/O port Read from timer Count value can be read by reading TX register Same applies to PREX register. Write to timer Value written to TX register is written to both reload register and counter. Same applies to PREX register. Select function
• INT1/CNTR0 polarity switching function Active edge of count source can be selected with R0EDG. T i m e r X m o d e r e g i s t e r S y m b o lA d d r e s sA f t e r r e s e t T X M 6 0 Bit name FunctionB i t s y m b o l RW b7 b6 b5 b4 b3 b2 b1 b0 1 0 : Event counter mode b1 b0 T X M O D 2 T X S T X M O D 1 R 0 E D G T X M O D 0 TXOCNT Operation mode select bit 0, 1 Timer X count start flag 0 : Stops counting 1 : Starts counting 0 0 Set to "0" in event counter mode 0 : Rising edge 1 : Falling edge T X E D G T X U N D RW R W R W R W R W R W R W R W I N T 1 / C N T R 0 p o l a r i t y s w i t c h i n g b i t(1 Set to "0" in event counter mode S e t t o " 0 " i n e v e n t c o u n t e r m o d e N O T E S : T h e I R b i t i n t h e I N T I C r e g i s t e r m a y b e s e t t o i n t e r r u p t r e q u e s t e d w h e n t h e R E D G b i t i s r e w r i t t e n R e f e r t o t h e p a r a g r a p h C h a n g i n g I n t e r r u p t F a c t o r i n t h e U s a g e N o t e s R e f e r e n c e B o o k 00 1 S e t t o " 0 " i n e v e n t c o u n t e r m o d e Figure 12.6 TXMR Register in Event Counter Mode Table 12.4 Event Counter Mode Specifications

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12.1.4 Pulse Width Measurement Mode

In this mode, the timer measures the pulse width of an external signal fed to INT1/CNTR0 pin (See “Table 12.5 Pulse Width Measurement Mode Specifications”). Figure 12.7 shows the TXMR register in pulse width measurement mode. Figure 12.8 shows an operation example in pulse width measure- ment mode. Item Specification Count source f 1, f2, f8, f32 Count operation • Down-count

• Continuously counts the selected signal only when the measurement pulse is "H" level, or conversely only "L" level.
• When the timer underflows, the contents in the reload register is reloaded and the count is continued Count start condition Write “1” (count start) to TXS bit in TXMR register Count stop condition Write “0” (count stop) to TXS bit in TXMR register Interrupt request • When Timer X underflows [Timer X interruption] generation timing • Rising or falling of CNTR0 input (end of measurement period) [INT1 interrupt] INT1/CNTR0 pin function Measurement pulse input CNTR 0 pin function Programmable I/O port Read from timer Count value can be read by reading TX register Same applies to PREX register. Write to timer Value written to TX register is written to both reload register and counter. Same applies to PREX register. Select function • INT1/CNTR0 polarity switching function “H ” or “L” level duration can be selected with R0EDG bit as the input pulse measurement Table 12.5 Pulse Width Measurement Mode Specifications Figure 12.7 TXMR Register in Pulse Width Measurement Mode

T i m e r X m o d e r e g i s t e r S y m b o lA d d r e s sA f t e r r e s e t T X M 6 0 B i t n a m e F u n c t i o nB i t s y m b o l RW b7 b 6 b5 b 4 b3 b 2 b 1 b 0 b1 b0 T X M O D 1 T X M O D 0 O p e r a t i o n m o d e s e l e c t b i t 0 10 R W R W 00 1 1 1 : P u l s e w i d t h m e a s u r e m e n t m o d e R 0 E D G R W INT1/CNTR 0 polarity switching bit(1) T X M O D 2 T X S T X O C N T T i m e r X c o u n t s t a r t f l a g 0 : Stops counting 1 : Starts counting Set to "0" in pulse width measurement mode T X E D G T X U N D R W R W R W R W R W N O T E S : I T h e I R b i t i n t h e I N T I C r e g i s t e r m a y b e s e t t o i n t e r r u p t r e q u e s t e d w h e n t h e R E D G b i t i s r e w r i t t e n R e f e r t o t h e p a r a g r a p h C h a n g i n g I n t e r r u p t F a c t o r i n t h e U s a g e N o t e s R e f e r e n c e B o o k S e t t o " 0 " i n p u l s e w i d t h m e a s u r e m e n t m o d e S e t t o " 0 " i n p u l s e w i d t h m e a s u r e m e n t m o d e S e t t o " 0 " i n p u l s e w i d t h m e a s u r e m e n t m o d e [CNTR0] 0 : Measures “H ” level width 1 : Measures “L” level width [INT1] 0 : Rising edge 1 : Falling edge

Rev.1.20 Jan 27, 2006 page 62 of 180 REJ09B0019-0120 FFFF 16 n 000016 Counter contents (hex) n = high-level: the contents of TX register, low-level: the contents of PREX register Count stop Set to "1" by program Count start Underflow TXS bit in TXMR register Measurement pulse (CNTR0 pin input) IR bit in INT1IC register Conditions: "H" level width of measurement pulse is measured. (R0EDG=1) “1” “0” IR bit in TXIC register Cleared to “0” when interrupt request is accepted, or cleared by program “H ” “L” “1” “0” “1” “0” Count stop Count restart Time Cleared to “0” when interrupt request is accepted, or cleared by program Figure 12.8 Operation Example in Pulse Width Measurement Mode

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12.1.5 Pulse Period Measurement Mode

In this mode, the timer measures the pulse period of an external signal fed to INT1/CNTR0 pin (See “Table 12.6 Pulse Period Measurement Mode Specifications”). Figure 12.9 shows the TXMR register in pulse period measurement mode. Figure 12.10 shows an operation example in pulse period mea- surement mode. Item Specification Count source f 1, f2, f8, f32 Count operation • Down-count

• After an active edge of measurement pulse is input, contents in the read-out buffer is retained in the first underflow of prescaler X. Then the timer X reloads contents in the reload register in the second underflow of prescaler X and continues counting. Count start condition Write “1” (count start) to TXS bit in TXMR register Count stop condition Write “0” (count stop) to TXS bit in TXMR register Interrupt request • When Timer X underflows or reloads [Timer X interrupt] generation timing • Rising or falling of CNTR0 input (end of measurement period) [INT1 interrupt] INT1/CNTR 0 pin function Measurement pulse input(1) (INT1 interrupt input) CNTR 0 pin function Programmable I/O port Read from timer Contents in the read-out buffer can be read by reading TX register. The value retained in the read-out buffer is released by reading TX register. Write to timer Value written to TX register is written to both reload register and counter. Same applies to PREX register. Select function • INT1/CNTR0 polarity switching function Measurement period of input pulse can be selected with R0EDG bit. NOTES: 1. The period of input pulse must be longer than twice the period of prescaler X. Longer pulse for H width and L width than the prescaler X period must be input. If shorter pulse than the period is input to the CNTR0 pin, the input may be disabled. Table 12.6 Pulse Period Measurement Mode Specifications T i m e r X m o d e r e g i s t e r Symbol Address After reset TXMR 008B 16 0016 Bit name F u n c t i o nB i t s y m b o l b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 0 : T i m e r m o d e o r p u l s e p e r i o d m e a s u r e m e n t m o d e b1 b0 T X M O D 1 R 0 E D G T X M O D 0 I N T 1 / C N T R 0 p o l a r i t y s w i t c h i n g b i t(1 O p e r a t i o n m o d e s e l e c t b i t 1 0 00 RW R W R W R W T X M O D 2 TXS T X O C N T Timer X count start flag 0 : Stops counting 1 : Starts counting O p e r a t i o n m o d e s e l e c t b i t 2 1 : P u l s e p e r i o d m e a s u r e m e n t m o d e S e t t o “ 0 ” i n p u l s e p e r i o d m e a s u r e m e n t m o d e T X E D G (2 T X U N D (2 ) T i m e r X u n d e r f l o w f l a g 0 : N o u n d e r f l o w U n d e r f l o w f o u n d 0 : N o a c t i v e e d g e A c t i v e e d g e f o u n d Active edge judgment flag N O T E S: T h e I R b i t i n t h e I N T I C r e g i s t e r m a y b e s e t t o i n t e r r u p t r e q u e s t e d w h e n t h e R E D G b i t i s r e w r i t t e n R e f e r t o t h e p a r a g r a p h C h a n g i n g I n t e r r u p t F a c t o r i n t h e U s a g e N o t e s R e f e r e n c e B o o k T h i s b i t i s s e t t o b y w r i t i n g i n a p r o g r a m I t r e m a i n s u n c h a n g e d e v e n i f w r i t i n g R W R W R W R W R W [CNTR 0] 0: Measures a measurement pulse from one rising edge to the next rising edge 1: Measures a measurement pulse from one falling edge to the next falling edge [INT1] 0: Rising edge 1: Falling edge Figure 12.9 TXMR Register in Pulse Period Measurement Mode

Rev.1.20 Jan 27, 2006 page 64 of 180 REJ09B0019-0120 0 F1 6 0 E1 6 0 E1 6 0 D 1 6 0 C 1 6 0B16 0A16 0916 0 F1 6 0 E1 6 0 D 1 6 0 11 6 0 01 6 0F16 0 E1 0F16 0E16 0A16 0816 Timer X reloads 0D 16 0116 0 F1 6 0E16 Timer X read TXEDG bit in TXMR register ( 2 ) Cleared to "0" by program T X U N D b i t i n T X M R r e g i s t e r N O T E S : T h e c o n t e n t s o f t h e r e a d o u t b u f f e r c a n b e r e a d w h e n t h e T X r e g i s t e r i s r e a d i n p u l s e p e r i o d m e a s u r e m e n t m o d e A f t e r a n a c t i v e e d g e o f m e a s u r e m e n t p u l s e i s i n p u t t h e T X E D G b i t i n t h e T X M R r e g i s t e r i s s e t t o a c t i v e e d g e f o u n d w h e n t h e p r e s c a l e r X u n d e r f l o w s f o r t h e s e c o n d t i m e T h e T X r e g i s t e r s h o u l d b e r e a d b e f o r e t h e n e x t a c t i v e e d g e i s i n p u t a f t e r t h e T X E D G b i t i s s e t t o a c t i v e e d g e f o u n d T h e c o n t e n t s i n t h e r e a d o u t b u f f e r i s r e t a i n e d u n t i l t h e T X r e g i s t e r i s r e a d I f t h e T X r e g i s t e r i s n o t r e a d b e f o r e t h e n e x t a c t i v e e d g e i s i n p u t t h e m e a s u r e d r e s u l t o f t h e p r e v i o u s p e r i o d i s r e t a i n e d W h e n s e t t o b y p r o g r a m u s e a M O V i n s t r u c t i o n t o w r i t e t o t h e T X E D G i n t h e T X M R r e g i s t e r A t t h e s a m e t i m e w r i t e t o t h e T X U N D b i t W h e n s e t t o b y p r o g r a m u s e a M O V i n s t r u c t i o n t o w r i t e t o t h e T X U N D i n t h e T X M R r e g i s t e r A t t h e s a m e t i m e w r i t e t o t h e T X E D G b i t T h e T X U N D a n d T X E D G b i t s a r e b o t h s e t t o i f t h e t i m e r u n d e r f l o w s a n d r e l o a d s o n a n a c t i v e e d g e s i m u l t a n e o u s l y I n t h i s c a s e t h e v a l i d i t y o f t h e T X U N D b i t s h o u l d b e d e t e r m i n e d b y t h e c o n t e n t s o f t h e r e a d o u t b u f f e r I f t h e C N T R 0 a c t i v e e d g e i s i n p u t w h e n t h e p r e s c a l e r X u n d e r f l o w s i g n a l i s H l e v e l i t s c o u n t v a l u e i s t h e o n e o f t h e r e a d b u f f e r I f L l e v e l t h e f o l l o w i n g c o u n t v a l u e i s t h e o n e o f t h e r e a d b u f f e r C o n d i t i o n s : A p e r i o d f r o m o n e r i s i n g e d g e t o t h e n e x t r i s i n g e d g e o f m e a s u r e m e n t p u l s e i s m e a s u r e d ( R 0 E D G = 0 ) w i t h T X r e g i s t e r i n i t i a l v a l u e S e t t o " 1 " b y p r o g r a m S t a r t s c o u n t i n g T X S b i t i n T X M R r e g i s t e r “ 1 ” “ 0 ” “ 1 ” “ 0 ” C N T R 0 p i n i n p u t T i m e r X c o n t e n t s Contents of read-out buffer1 T i m e r X r e l o a d s T i m e r X r e l o a d s Timer X read (2) (4) (6) Cleared to "0" by program “ 1 ” “0” “ 1 ” “0” “ 1 ” “ 0 ” “ 1 ” “ 0 ” C l e a r e d t o “ 0 ” w h e n i n t e r r u p t r e q u e s t i s a c c e p t e d , o r c l e a r e d b y p r o g r a m C l e a r e d t o “ 0 ” w h e n i n t e r r u p t r e q u e s t i s a c c e p t e d , o r c l e a r e d b y p r o g r a m IR bit in INT1IC register I R b i t i n T X I C r e g i s t e r 0916 0016 Retained R e t a i n e d 08160 F1 U n d e r f l o w s i g n a l o f p r e s c a l e r X ( 3 )(3) ( 7 ) ( 7 ) (5) Figure 12.10 Operation Example in Pulse Period Measurement Mode

Rev.1.20 Jan 27, 2006 page 65 of 180 REJ09B0019-0120

12.2 Timer Y

Timer Y is an 8-bit timer with an 8-bit prescaler and has two reload registers-Timer Y Primary and Timer PREY, TYSC, TYPR, TYZOC, PUM, and YCSS registers. The Timer Y has two operation modes as follows:

• Timer mode: The timer counts an internal count source.
• Programmable waveform generation mode: The timer outputs pulses of a given width successively. Figure 12.11 Timer Y Block Diagram Figure 12.12 TYZMR Register Toggle flip-flop Timer Y interrupt INT2 interrupt TYPR register Q CK fRING TYSC register TYOCNT=1 TYOPL=1 Q TYOPL=0P3_2 bit in P3 register TYOCNT=0TYMOD0=1 TYS=1 PREY register INT2/CNTR 1 TYCK1 to TYCK0 =002 =012 =102 =112 Counter Reload register Counter Reload register Peripheral data bus Reload register Polarity switching CLR Write to TYZMR register TYMOD0 bit=1 T i m e r Y , Z m o d e r e g i s t e r Symbol Address After reset TYZMR 0080 16 0016 B i t n a m e F u n c t i o nB i t s y m b o l b7 b6 b5 b4 b3 b2 b1 b0 0 0 : T i m e r m o d e P r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e P r o g r a m m a b l e o n e s h o t g e n e r a t i o n m o d e P r o g r a m m a b l e w a i t o n e s h o t g e n e r a t i o n m o d e T Z M O D 1 T Y S T Y W C TYMOD0 T Z M O D 0 T i m e r Y o p e r a t i o n m o d e b i t T i m e r Y w r i t e c o n t r o l b i t F u n c t i o n v a r i e s d e p e n d i n g o n t h e o p e r a t i o n m o d e 0 : Timer mode 1 : Programmable waveform generation mode T Z W C T Z S 0 S t o p s c o u n t i n g S t a r t s c o u n t i n g 0 : S t o p s c o u n t i n g S t a r t s c o u n t i n g T i m e r Z c o u n t s t a r t f l a g Timer Z operation mode bit b b Timer Y count start flag T i m e r Z w r i t e c o n t r o l b i t F u n c t i o n v a r i e s d e p e n d i n g o n t h e o p e r a t i o n m o d e RW R W R W R W R W R W R W R W R W R 1 E D G 0 : R i s i n g e d g e F a l l i n g e d g e I N T 2 / C N T R 1 p o l a r i t y s w i t c h i n g b i t(1 N O T E S : T h e I R b i t i n t h e I N T I C r e g i s t e r m a y b e s e t t o i n t e r r u p t r e q u e s t e d w h e n t h e R E D G b i t i s r e w r i t t e n R e f e r t o t h e p a r a g r a p h C h a n g i n g I n t e r r u p t F a c t o r i n t h e U s a g e N o t e s R e f e r e n c e B o o k

12.2 Timer (Timer Y)

Rev.1.20 Jan 27, 2006 page 66 of 180 REJ09B0019-0120 T i m e r Y , Z o u t p u t c o n t r o l r e g i s t e r( Symbol Address After reset TYZOC 008A 16 0016 B i t n a m e F u n c t i o nB i t s y m b o l b 7 b 6 b 5 b 4 b 3 b 2 b 1 b0 T Z O C N T T Y O C N T T Z O S Nothing is assigned. When write, set to "0". When read, its content is "0". Timer Z one-shot start bit(1) Timer Y programmable waveform generation output switching bit(2) 0 : O u t p u t s p r o g r a m m a b l e w a v e f o r m O u t p u t s t h e v a l u e o f P p o r t r e g i s t e r 0 : Outputs programmable waveform 1 : Outputs the value of P31 port register 0 : S t o p s o n e - s h o t S t a r t s o n e s h o t T i m e r Z p r o g r a m m a b l e w a v e f o r m g e n e r a t i o n o u t p u t s w i t c h i n g b i N O T E S : T h i s b i t i s s e t t o w h e n t h e o u t p u t o f o n e s h o t w a v e f o r m i s c o m p l e t e d T h e T Z O S b i t s h o u l d b e s e t t o i f t h e o n e s h o t w a v e f o r m o u t p u t i s t e r m i n a t e d b y s e t t i n g t h e T Z S b i t i n t h e T Y Z M R t o d u r i n g t h e w a v e f o r m o u t p u t T h i s b i t i s e n a b l e d o n l y w h e n o p e r a t i n g i n p r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e I f e x e c u t i n g a n i n s t r u c t i o n w h i c h c h a n g e s t h i s r e g i s t e r w h e n t h e T Z O S b i t i s d u r i n g t h e c o u n t t h e T Z O S i s a u t o m a t i c a l l y s e t t o w h e n t h e c o u n t c o m p l e t e s w h i l e t h e i n s t r u c t i o n i s e x e c u t e d I f t h i s c a u s e s s o m e p r o b l e m s e x e c u t e a n i n s t r u c t i o n w h i c h c h a n g e s t h i s r e g i s t e r w h e n t h e T Z O S b i t i s o n e s h o t s t o p R W R W R W R W ( b 7 - b 3 ) Figure 12.13 PREY Register, TYSC Register, TYPR Register, and TYZOC Register Timer Y primary register T i m e r Y s e c o n d a r y r e g i s t e r S y m b o lA d d r e s sA f t e r r e s e t T Y S 6 F N O T E S : T h e v a l u e s o f T Y P R r e g i s t e r a n d T Y S C r e g i s t e r a r e r e l o a d e d t o t h e c o u n t e r a l t e r n a t e l y f o r c o u n t i n g T h e c o u n t v a l u e c a n b e r e a d o u t b y r e a d i n g t h e T Y P R r e g i s t e r e v e n w h e n t h e s e c o n d a r y p e r i o d i s b e i n g c o u n t e d Symbol Address After reset PREY 0081 16 FF16 b 0 RW I n t e r n a l c o u n t s o u r c e o r C N T R 1 i n p u t i s c o u n t e d Function S e t t i n g r a n g e P r e s c a l e r Y r e g i s t e r 0016 to FF16 I n t e r n a l c o u n t s o u r c e i s c o u n t e d 0016 to FF16 T i m e r m o d e P r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e M o d e RW R W Symbol Address After reset TYPR 0083 16 FF16 b 7 R W D i s a b l e d Function Setting range Underflow of Prescaler Y is counted(1) 0016 to FF16 Timer mode P r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e M o d e WO (2) RW U n d e r f l o w o f P r e s c a l e r Y i s c o u n t e d Function Setting range Underflow of Prescaler Y is counted(1) 0016 to FF16 Timer mode P r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e Mode 0016 to FF16 R W RW NOTES: 1. The values of TYPR register and TYSC register are reloaded to the counter alternately for counting. b 0b 7 b0b 7

Rev.1.20 Jan 27, 2006 page 67 of 180 REJ09B0019-0120 Bit name Function Bit symbol T i m e r Y , Z w a v e f o r m o u t p u t c o n t r o l r e g i s t e r Symbol Address After reset PUM 0084 16 0016 b 7 b 6 b5 b 4 b 3 b 2 b 1 b0 N O T E S : T h e I N O S E G b i t i s v a l i d o n l y w h e n t h e I N T P L b i t i n t h e I N T E N r e g i s t e r i s o n e e d g e T h e I N O S G T b i t m u s t b e s e t t o a f t e r t h e I N T E N b i t i n t h e I N T E N r e g i s t e r a n d t h e I N O S E G b i t i n t h e P U M r e g i s t e r a r e s e t 0000 T Y O P L TZOPL INOSEG I N O S T G INT0 pin one-shot trigger polarity select bit(1) Timer Z output level latch T i m e r Y o u t p u t l e v e l l a t c h I N T 0 p i n o n e - s h o t t r i g g e r c o n t r o l b i t(2 Function varies depending on the operation mode Function varies depending on the operation mode 0 : Edge trigger at falling edge 1 : Edge trigger at rising edge ( T i m e r Z ) (Timer Z) 0 : INT0 pin one-shot trigger invalid 1 : INT0 pin one-shot trigger valid ( b 3 - b 0 ) R e s e r v e d b i t Must set to “0” RW RW R W RW R W RW Figure 12.14 PUM Register and TCSS Register Bit name Function B i t s y m b o l Timer X count source select bit(1) b1 b0 T X C K 1 TXCK0 TYCK0 Timer Y count source select bit(1) T Z C K 0 T Y C K 1 T Z C K 1 Must be set to “0” ( b 7 - b 6 ) Reserved bit Timer Z count source select bit(1) NOTES: 1. Avoid switching a count source, while a counter is in progress. Timer counter must be stopped before switching a count source. Timer count source setting register Symbol Address After reset TCSS 008E 16 0016 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : f2 b3 b2 0 0 : f1 0 1 : f8 1 0 : fRING 1 1 : Selects input from CNTR1 pin b5 b4 0 0 : f1 0 1 : f8 1 0 : Selects Timer Y underflow 1 1 : f2 R W RW R W RW RW R W R W R W 0 0

Rev.1.20 Jan 27, 2006 page 68 of 180 REJ09B0019-0120

12.2.1 Timer Mode

In this mode, the timer counts an internally generated count source (see “Table 12.7 Timer Mode Specifications”). An external signal input to the CNTR1 pin can be counted. The TYSC register is unused in timer mode. Figure 12.15 shows the TYZMR and PUM registers in timer mode. Item Specification Count source f 1, f8, fRING , external signal fed to CNTR1 pin Count operation • Down-count

• When the timer underflows, it reloads the reload register contents before continuing counting (When the Timer Y underflows, the contents of the Timer Y primary reload register is reloaded.) Divide ratio 1/(n+1)(m+1) n: set value in PREY register, m: set value in TYPR register Count start condition Write “1” (count start) to TYS bit in TYZMR register Count stop condition Write “0” (count stop) to TYS bit in TYZMR register Interrupt request • When Timer Y underflows [Timer Y interrupt] generation timing INT2/CNTR 1 pin function Programmable I/O port, count source input or INT2 interrupt input
• When the TYCK1 to TYCK0 bits in the TCSS register are set to “00b”, “01b” or “10b” (Timer Y count source is f1, f8 or fRING ), programmable I/O port or INT2 interrupt input
• When the TYCK1 to TYCK0 bits are set to “11b” (Timer Y count source is CNTR1 input), count source input (INT2 interrupt input) Read from timer Count value can be read out by reading TYPR register. Same applies to PREY register. Write to timer(1) Value written to TYPR register is written to both reload register and counter or written to only reload register. Selected by program. Same applies to PREY register. Select function • Event counter function When setting TYCK1 to TYCK0 bits to “112”, an external signal fed to CNTR1 pin is counted.
• INT2/CNTR1 switching bit Active edge of count source is selected by R1EDG bit. NOTES: 1. The IR bit in the TYIC register is set to "1" (interrupt requested) if you write to the TYPR or PREY register while both of the following conditions are met. Conditions:
• TYWC bit in TYZMR register is "0" (write to reload register and counter simultaneously)
• TYS bit is "1" (count start) To write to the TYPR or PREY register in the above state, disable interrupts before writing. Table 12.7 Timer Mode Specifications

Rev.1.20 Jan 27, 2006 page 69 of 180 REJ09B0019-0120 Figure 12.15 TYZMR Register and PUM Register in Timer Mode T i m e r Y , Z m o d e r e g i s t e r Symbol Address After reset TYZMR 0080 16 0016 Bit name F u n c t i o nB i t s y m b o l b 7 b 6 b 5 b 4 b 3 b2 b 1 b 0 T Z M O D 1 TYS T Y W C TYMOD0 T Z M O D 0 Timer Y operation mode bit N O T E S : T h e I R b i t i n t h e I N T I C r e g i s t e r m a y b e s e t t o i n t e r r u p t r e q u e s t e d w h e n t h e R E D G b i t i s r e w r i t t e n R e f e r t o t h e p a r a g r a p h C h a n g i n g I n t e r r u p t F a c t o r i n t h e U s a g e N o t e s R e f e r e n c e B o o k W h e n T Y S b i t s t a r t s c o u n t i n g t h e v a l u e s e t i n t h e T Y W C b i t i s v a l i d I f T Y W C b i t t h e t i m e r Y c o u n t v a l u e i s w r i t t e n t o b o t h r e l o a d r e g i s t e r a n d c o u n t e r I f T Y W C b i t t h e t i m e r Y c o u n t v a l u e i s w r i t t e n t o t h e r e l o a d r e g i s t e r o n l y W h e n T Y S b i t s t o p s c o u n t i n g t h e t i m e r Y c o u n t v a l u e i s w r i t t e n t o b o t h r e l o a d r e g i s t e r a n d c o u n t e r r e g a r d l e s s o f h o w t h e T Y W C b i t i s s e t Timer Y write control bit(2) 0 : Write to reload register and counter simultaneously 1 : Write to reload register 0 : T i m e r m o d e T Z W C T Z S S t o p s c o u n t i n g S t a r t s c o u n t i n g Timer Z-related bit Timer Y count start flag R W R W RW R W RW RW R 1 E D G 0 : Rising edge 1 : Falling edge INT2/CNTR1 polarity switching bit(1) R W R W R W Bit name Function Bit symbol TYOPL TZOPL INOSEG INOSTG Timer Z-related bits Timer Y, Z waveform output control register Symbol Address After reset PUM 0084 16 0016 b7 b6 b5 b4 b3 b2 b1 b0 Timer Y output level latch Invalid in timer mode 0000 (b3-b0) Reserved bit Must set to “0” RW RW RW RW RW RW

Rev.1.20 Jan 27, 2006 page 70 of 180 REJ09B0019-0120

12.2.2 Programmable Waveform Generation Mode

In this mode, an signal output from the TYOUT pin is inverted each time the counter underflows, while the values in the TYPR register and TYSC register are counted alternately (see “Table 12.8 Program- mable Waveform Generation Mode Specifications”). A counting starts by counting the set value in the TYPR register. Figure 12.16 shows the TYZMR register in programmable waveform generation mode. Figure 12.17 shows the operation example. Item Specification Count source f 1, f8, fRING Count operation • Down count

• When the timer underflows, it reloads the contents of primary reload register and sec- ondary reload register alternately before continuing counting. Output waveform width Primary period : (n+1)(m+1)/fi and period Secondary period : (n+1)(p+1)/f i Period : (n+1){(m+1)+(p+1)}/fi n: set value in PREY register, m: set value in TYPR register, p: set value in TYSC register fi : Count source frequency Count start condition Write “1” (count start) to TYS bit in TYZMR register Count stop condition Write “0” (count stop) to TYS bit in TYZMR register Interrupt request generation timingIn half of count source, after timer Y underflows during secondary period (at the same time as the CNTR, output change) [Timer Y interrupt] INT2/CNTR 1 pin functions Pulse output Use timer mode when using this pin as a programmable I/O port. Read from timer Count value can be read out by reading TYPR register. Same applies to PREY register(1). Write to timer Value written to TYPR register is written to only reload register. Same applies to TYSC register and PREY register(2). Select function • Output level latch select function The output level during primary and secondary periods is selected by the TYOPL bit.
• Programmable waveform generation output switching function When the TYOCNT bit in the TYZOC register is set to “0”, the output from TYOUT is inverted synchronously when Timer Y underflows during the secondary period. And when set to “1”, a value in the P3_2 bit is output from TYOUT synchronously when Timer Y underflows during the secondary period(3). NOTES: 1. Even when counting the secondary period, read out the TYPR register. 2. The set value in the TYPR register and TYSC register are made effective by writing a value to the TYPR register. The written values are reflected to the waveform output from the next primary period after writing to the TYPR register. 3. The TYOCNTbit is enabled in the following timings
• When count starts
• When Timer Y interrupt request is generated Therefore, pulse is output from the next primary period depending on the setting value of the TYOCNT bit. Table 12.8 Programmable Waveform Generation Mode Specifications

Rev.1.20 Jan 27, 2006 page 71 of 180 REJ09B0019-0120 Figure 12.16 TYZMR Register and PUM Register in Programmable Waveform Generation Mode Bit name Function Bit symbol TYOPL TZOPL INOSEG INOSTG Timer Z-related bits Timer Y, Z waveform output control register Symbol Address After reset PUM 0084 16 0016 b7 b6 b5 b4 b3 b2 b1 b0 Timer Y output level latch 0 : Outputs "H" for primary period Outputs "L" for secondary period Outputs "L" when the timer is stopped 1 : Outputs "L" for primary period Outputs "H" for secondary period Outputs "H" when the timer is stopped (b3-b0) Reserved bit Must set to “0” RW RW RW RW RW RW 0000 T i m e r Y , Z m o d e r e g i s t e r S y m b o lA d d r e s sA f t e r r e s e t T Y Z M 6 0 B i t n a m e F u n c t i o nB i t s y m b o l b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 T Z M O D 1 T Y S T Y W C T Y M O D 0 T Z M O D 0 T i m e r Y o p e r a t i o n m o d e b i t N O T E S : T h e I R b i t i n t h e I N T I C r e g i s t e r m a y b e s e t t o i n t e r r u p t r e q u e s t e d w h e n t h e R E D G b i t i s r e w r i t t e n R e f e r t o t h e p a r a g r a p h C h a n g i n g I n t e r r u p t F a c t o r i n t h e U s a g e N o t e s R e f e r e n c e B o o k 1 : P r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e T Z W C T Z S 0 : S t o p s c o u n t i n g S t a r t s c o u n t i n g T i m e r Z - r e l a t e d b i t T i m e r Y c o u n t s t a r t f l a g T i m e r Y w r i t e c o n t r o l b i t R W R W R W R W R W R W R 1 E D G D i s a b l e d i n p r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e I N T 2 / C N T R 1 p o l a r i t y s w i t c h i n g b i t(1 R W R W R W S e t t o “ 1 ” i n p r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e(2 2 . W h e n T Y S b i t = 1 ( s t a r t s c o u n t i n g ) , t h e t i m e r Y c o u n t v a l u e i s w r i t t e n t o t h e r e l o a d r e g i s t e r o n l y . W h e n T Y S b i t s t o p s c o u n t i n g t h e t i m e r Y c o u n t v a l u e i s w r i t t e n t o b o t h r e l o a d r e g i s t e r a n d c o u n t e r T h e I N T i n t e r r u p t r e q u e s t i s n o t g e n e r a t e d w h e n t h e T Y M O D b i t i s s e t t o p r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e

Rev.1.20 Jan 27, 2006 page 72 of 180 REJ09B0019-0120 CNTR1 pin output"H" "L" IR bit in TYIC register "1" "0" TYS bit in TYZMR register "1" "0" Set to "1" by program Count starts 0116 0016 0216 Set to "0" when interrupt request is accepted, or set by program Waveform output started Waveform output inverted Waveform output inverted "1" "0" TYOPL bit in PUM register Contents of Timer Y Count source Primary period Secondary period Primary period Prescaler Y underflow signal 0116 0016 0116 0016 0216 Timer Y primary reloads Timer Y secondary reloads Conditions: PREY=0116, TYPR=0116, TYSC=02 16 TYZOC register TYOCNT bit = 0 Set to "0" by program Figure 12.17 Timer Y Operation Example in Programmable Waveform Generation Mode

Rev.1.20 Jan 27, 2006 page 73 of 180 REJ09B0019-0120 TZSC register T i m e r Y u n d e r f l o w T o g g l e f l i p - f l o p P3_1 bit in P3 register T ZO U T Q Q Data bus Reload registerR e l o a d r e g i s t e rR e l o a d r e g i s t e r T Z P R r e g i s t e r Counter C o u n t e r P R E Z r e g i s t e r Input polarity selected to be one edge or both edges Digital filter P o l a r i t y s e l e c t INT0 T Z S TZOS INOSEG TZOCNT=0 INT0PL T Z M O D 1 t o T Z M O D 0 = 0 12, 1 02, 1 12 INT0EN T Z O C N T = 1 TZOPL=0 TZOPL=1 T Z M O D t o T Z M O D 02, 1 T Z C K t o T Z C K =012 T i m e r Z i n t e r r u p t I N T 0 i n t e r r u p t C K C L R Write to TYZMR register TZMOD1 to TZMOD0 bits=012, 102, 112 Figure 12.19 TYZMR Register Timer Z is an 8-bit timer with an 8-bit prescaler and has two reload registers-Timer Z Primary and Timer PREZ, TZSC, TZPR, TYZOC, PUM, and TCSS registers. Timer Z has the following four operation modes.

• Timer mode: The timer counts an internal count source or Timer Y underflow.
• Programmable waveform generation mode: The timer outputs pulses of a given width successively.
• Programmable one-shot generation mode: The timer outputs one-shot pulse.
• Programmable wait one-shot generation mode: The timer outputs delayed one-shot pulse. Timer Y, Z mode register S y m b o lA d d r e s sA f t e r r e s e t T Y Z M 6 0 Bit name FunctionBit symbol b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 0 : Timer mode 0 1 : Programmable waveform generation mode 1 0 : Programmable one-shot generation mode 1 1 : Programmable wait one-shot generation mode T Z M O D 1 T Y S T Y W C T Y M O D 0 T Z M O D 0 T i m e r Y o p e r a t i o n m o d e b i t T i m e r Y w r i t e c o n t r o l b i t Function varies depending on the operation mode 0 : Timer mode 1 : Programmable waveform generation mode T Z W C T Z S 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting T i m e r Z c o u n t s t a r t f l a g T i m e r Z o p e r a t i o n m o d e b i t b b T i m e r Y c o u n t s t a r t f l a g T i m e r Z w r i t e c o n t r o l b i t Function varies depending on the operation mode R W R W R W R W R W R W R W R W R W R 1 E D G 0 : Rising edge 1 : Falling edge INT2/CNTR 1 polarity switching bit(1) N O T E S : T h e I R b i t i n t h e I N T I C r e g i s t e r m a y b e s e t t o i n t e r r u p t r e q u e s t e d w h e n t h e R E D G b i t i s r e w r i t t e n R e f e r t o t h e p a r a g r a p h C h a n g i n g I n t e r r u p t F a c t o r i n t h e U s a g e N o t e s R e f e r e n c e B o o k Figure 12.18 Timer Z Block Diagram

12.3 Timer (Timer Z)

Rev.1.20 Jan 27, 2006 page 74 of 180 REJ09B0019-0120 Figure 12.20 PREZ Register, TZSC Register, TZPR Register, and TYZOC Register NOTES: 1. Each value in the TZPR register and TZSC register is reloaded to the counter alternately for counting. 2. The count value can be read out by reading the TZSC register even when the secondary period is being counted. N O T E S : E a c h v a l u e i n t h e T Z P R r e g i s t e r a n d T Z S C r e g i s t e r i s r e l o a d e d t o t h e c o u n t e r a l t e r n a t e l y f o r c o u n t i n g Symbol Address After reset PREZ 0085

16 FF16

I n t e r n a l c o u n t s o u r c e o r T i m e r Y u n d e r f l o w i s c o u n t e d F u n c t i o nS e t t i n g r a n g e P r e s c a l e r Z r e g i s t e r 0016 to FF16 Internal count source or Timer Y underflow is counted 0016 to FF16 I n t e r n a l c o u n t s o u r c e o r T i m e r Y u n d e r f l o w i s c o u n t e d0 0 16 to FF16 T i m e r m o d e P r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e P r o g r a m m a b l e o n e s h o t g e n e r a t i o n m o d e M o d e R W RW R W I n t e r n a l c o u n t s o u r c e o r T i m e r Y u n d e r f l o w i s c o u n t e d 0 01 6 t o F F1 P r o g r a m m a b l e w a i t o n e s h o t g e n e r a t i o n m o d e R W Symbol Address After reset TZSC 0086 16 FF16 b 7 b0 R W Invalid F u n c t i o nS e t t i n g r a n g e T i m e r Z S e c o n d a r y r e g i s t e r Underflow of Prescaler Z is counted(1) 0016 to FF16 I n v a l i d T i m e r m o d e P r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e P r o g r a m m a b l e o n e s h o t g e n e r a t i o n m o d e M o d e WO (2) Underflow of Prescaler Z is counted (One-shot width is counted) 16 to FF16 Programmable wait one-shot generation mode W O Symbol Address After reset TZPR 0087 16 FF16 b7 b0 RW U n d e r f l o w o f P r e s c a l e r Z i s c o u n t e d F u n c t i o nS e t t i n g r a n g e T i m e r Z P r i m a r y r e g i s t e r 0016 to FF16 Underflow of Prescaler Z is counted(1) 0016 to FF16 U n d e r f l o w o f P r e s c a l e r Z i s c o u n t e d O n e s h o t w i d t h i s c o u n t e d 0016 to FF16 Timer mode Programmable waveform generation mode P r o g r a m m a b l e o n e s h o t g e n e r a t i o n m o d e M o d e R W RW R W U n d e r f l o w o f P r e s c a l e r Z i s c o u n t e d W a i t p e r i o d i s c o u n t e d 0016 to FF16 Programmable wait one-shot generation mode R WT i m e r Y , Z o u t p u t c o n t r o l r e g i s t e r( S y m b o lA d d r e s sA f t e r r e s e t T Y Z O 6 0 B i t n a m e F u n c t i o nB i t s y m b o l b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 T Z O C N T T Y O C N T T Z O S N o t h i n g i s a s s i g n e d . W h e n w r i t e s e t t o W h e n r e a d i t s c o n t e n t i s T i m e r Z o n e - s h o t s t a r t b i T i m e r Y p r o g r a m m a b l e w a v e f o r m g e n e r a t i o n o u t p u t s w i t c h i n g b i 0 : O u t p u t s p r o g r a m m a b l e w a v e f o r m O u t p u t s t h e v a l u e o f P p o r t r e g i s t e r 0 : O u t p u t s p r o g r a m m a b l e w a v e f o r m O u t p u t s t h e v a l u e o f P p o r t r e g i s t e r 0 : S t o p s o n e - s h o t S t a r t s o n e s h o t T i m e r Z p r o g r a m m a b l e w a v e f o r m g e n e r a t i o n o u t p u t s w i t c h i n g b i N O T E S : T h i s b i t i s s e t t o w h e n t h e o u t p u t o f o n e s h o t w a v e f o r m i s c o m p l e t e d T h e T Z O S b i t s h o u l d b e s e t t o i f t h e o n e s h o t w a v e f o r m o u t p u t i s t e r m i n a t e d b y s e t t i n g t h e T Z S b i t i n t h e T Y Z M R t o d u r i n g t h e w a v e f o r m o u t p u t T h i s b i t i s e n a b l e d o n l y w h e n o p e r a t i n g i n p r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e I f e x e c u t i n g a n i n s t r u c t i o n w h i c h c h a n g e s t h i s r e g i s t e r w h e n t h e T Z O S b i t i s d u r i n g t h e c o u n t t h e T Z O S i s a u t o m a t i c a l l y s e t t o w h e n t h e c o u n t c o m p l e t e s w h i l e t h e i n s t r u c t i o n i s e x e c u t e d I f t h i s c a u s e s s o m e p r o b l e m s e x e c u t e a n i n s t r u c t i o n w h i c h c h a n g e s t h i s r e g i s t e r w h e n t h e T Z O S b i t i s o n e s h o t s t o p R W R W R W R W ( b 7 - b 3 )

Rev.1.20 Jan 27, 2006 page 75 of 180 REJ09B0019-0120 Figure 12.21 PUM Register and TCSS Register B i t n a m e F u n c t i o n Bit symbol T i m e r Y , Z w a v e f o r m o u t p u t c o n t r o l r e g i s t e r Symbol Address After reset PUM 0084 16 0016 b7 b6 b5 b4 b3 b2 b1 b0 N O T E S : T h e I N O S E G b i t i s v a l i d o n l y w h e n t h e I N T P L b i t i n t h e I N T E N r e g i s t e r i s o n e e d g e T h e I N O S G T b i t m u s t b e s e t t o a f t e r t h e I N T E N b i t i n t h e I N T E N r e g i s t e r a n d t h e I N O S E G b i t i n t h e P U M r e g i s t e r a r e s e t 0000 T Y O P L TZOPL INOSEG I N O S T G I N T 0 p i n o n e - s h o t t r i g g e r p o l a r i t y s e l e c t b i t(1 T i m e r Z o u t p u t l e v e l l a t c h T i m e r Y o u t p u t l e v e l l a t c h I N T 0 p i n o n e - s h o t t r i g g e r c o n t r o l b i t(2 F u n c t i o n v a r i e s d e p e n d i n g o n t h e o p e r a t i o n m o d e F u n c t i o n v a r i e s d e p e n d i n g o n t h e o p e r a t i o n m o d e 0 : E d g e t r i g g e r a t f a l l i n g e d g e E d g e t r i g g e r a t r i s i n g e d g e (Timer Z) (Timer Z) 0 : I N T 0 p i n o n e - s h o t t r i g g e r i n v a l i d I N T p i n o n e s h o t t r i g g e r v a l i d ( b 3 - b 0 ) R e s e r v e d b i t S e t t o “ 0 ” RW RW R W RW R W R W Bit name F u n c t i o n Bit symbol Timer X count source select bit(1) b1 b0 TXCK1 TXCK0 T Y C K 0 Timer Y count source select bit(1) T Z C K 0 T Y C K 1 T Z C K 1 Must be set to “0” (b7-b6) R e s e r v e d b i t Timer Z count source select bit(1) N O T E S : A v o i d s w i t c h i n g a c o u n t s o u r c e w h i l e a c o u n t e r i s i n p r o g r e s s T i m e r c o u n t e r m u s t b e s t o p p e d b e f o r e s w i t c h i n g a c o u n t s o u r c e Timer count source setting register Symbol Address After reset TCSS 008E 16 0016 b7 b6 b5 b4 b3 b2 b1 b0 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : f2 b3 b2 0 0 : f1 0 1 : f8 1 0 : fRING 1 1 : Selects input from CNTR1 pin b5 b4 0 0 : f1 S e l e c t s T i m e r Y u n d e r f l o w RW RW RW RW R W RW RW RW 0 0

Rev.1.20 Jan 27, 2006 page 76 of 180 REJ09B0019-0120

12.3.1 Timer Mode

In this mode, the timer counts an internally generated count source or Timer Y underflow (see “Table 12.9 Timer Mode Specifications”). The Timer Z secondary is unused in timer mode. Figure 12.22 shows the TYZMR register and PUM register in timer mode. Item Specification Count source f 1, f2, f8, Timer Y underflow Count operation • Down-count

• When the timer underflows, it reloads the reload register contents before continuing counting (When the Timer Z underflows, the contents of the Timer Z primary reload register is reloaded.) Divide ratio 1/(n+1)(m+1) n: set value in PREZ register, m: set value in TZPR register Count start condition Write “1” (count start) to TZS bit in TYZMR register Count stop condition Write “0” (count stop) to TZS bit in TYZMR register Interrupt request • When Timer Z underflows [Timer Z interrupt] generation timing TZOUT pin function Programmable I/O port INT0 pin function Programmable I/O port, or INT0 interrupt input Read from timer Count value can be read out by reading TZPR register. Same applies to PREZ register. Write to timer(1) Value written to TZPR register is written to both reload register and counter or written to reload register only. Selected by program. Same applies to PREZ register. NOTES: 1. The IR bit in the TZIC register is set to "1" (interrupt requested) if you write to the TZPR or PREZ register while both of the following conditions are met. <Conditions>
• TZWC bit in TYZMR register is set to "0" (write to reload register and counter simultaneously)
• TZS bit in TYZMR register is set to "1" (count start) To write to the TZPR or PREZ register in the above state, disable interrupts before the writing. Table 12.9 Timer Mode Specifications

Rev.1.20 Jan 27, 2006 page 77 of 180 REJ09B0019-0120 Figure 12.22 TYZMR Register and PUM Register in Timer Mode Bit name Function Bit symbol Timer Y, Z waveform output control register Symbol Address After reset PUM 0084 16 0016 b7 b6 b5 b4 b3 b2 b1 b0 0000 TYOPL TZOPL INOSEG INOSTG Timer Z output level latch Must set to “0” in timer mode INT0 pin one-shot trigger control bit INT0 pin one-shot trigger polarity select bit (b3-b0) Reserved bit Must set to “0” RW RW RW RW RW RW Timer Y-related bit Must set to “0” in timer mode Must set to “0” in timer mode 000 T i m e r Y , Z m o d e r e g i s t e r S y m b o lA d d r e s sA f t e r r e s e t T Y Z M 6 0 B i t n a m e F u n c t i o nB i t s y m b o l b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 0 : Timer mode T Z M O D 1 T Y S T Y W C T Y M O D 0 T Z M O D 0 T i m e r Y - r e l a t e d b i t T Z W C T Z S 0 S t o p s c o u n t i n g S t a r t s c o u n t i n g Timer Z count start flag T i m e r Z o p e r a t i o n m o d e b i t b5 b4 T i m e r Z w r i t e c o n t r o l b i t(1 0 : Write to reload register and counter 1 : Write to reload register only R W R W R W R W RW R W R W R W R1EDG R W N O T E S : W h e n T Z S b i t s t a r t s c o u n t i n g t h e v a l u e s e t i n t h e T Z W C b i t i s v a l i d I f T Z W C b i t t h e t i m e r Z c o u n t v a l u e i s w r i t t e n t o b o t h r e l o a d r e g i s t e r a n d c o u n t e r I f T Z W C b i t t h e t i m e r Z c o u n t v a l u e i s w r i t t e n t o t h e r e l o a d r e g i s t e r o n l y W h e n T Z S b i t s t o p s c o u n t i n g t h e t i m e r Z c o u n t v a l u e i s w r i t t e n t o b o t h r e l o a d r e g i s t e r a n d c o u n t e r r e g a r d l e s s o f h o w t h e T Z W C b i t i s s e t

Rev.1.20 Jan 27, 2006 page 78 of 180 REJ09B0019-0120

12.3.2 Programmable Waveform Generation Mode

In this mode, an signal output from the TZOUT pin is inverted each time the counter underflows, while the values in the TZPR register and TZSC register are counted alternately (see “Table 12.10 Program- mable Waveform Generation Mode Specifications”). A counting starts by counting the value set in the TZPR register. Figure 12.23 shows TYZMR and PUM registers in this mode. The Timer Z operates in the same way as the Timer Y in this mode. See Figure 12.17 (Timer Y operation example in program- mable waveform generation mode ). Item Specification Count source f 1, f2, f8, Timer Y underflow Count operation • Down-count

• When the timer underflows, it reloads the contents of primary reload register and sec- ondary reload register alternately before continuing counting. Output waveform width Primary period : (n+1)(m+1)/fi and period Secondary period : (n+1)(p+1)/f i Period : (n+1){(m+1)+(p+1)}/fi fi : Count source frequency n: Set value in PREZ register, m: Set value in TZPR register, p: Set value in TZSC register Count start condition Write “1” (count start) to the TZS bit in the TYZMR register Count stop condition Write “0” (count stop) to the TZS bit in the TYZMR register Interrupt request generation timingIn half of count source, after timer Z underflows during secondary period (at the same time as the TZout output change) [Timer Z interrupt] TZOUT pin function Pulse output Use timer mode when using this pin as a programmable I/O port. INT0 pin functions Programmable I/O port, or INT0 interrupt input Read from timer Count value can be read out by reading TZPR register. Same applies to PREZ register(1). Write to timer Value written to TZPR register is written to reload register only. Same applies to TZSC register and PREZ register(2). Select function • Output level latch select function The output level during primary and secondary periods is selected by the TZOPL bit.
• Programmable waveform generation output switching function The output from TZOUT is inverted synchronously when Timer Z underflows by setting the TZOCNT bit in the TYZOC register to “0”. A value in the P3_1 bit is output from the TZOUT by setting to “1”(3). NOTES: 1. Even when counting the secondary period, read out the TZPR register. 2. The set value in the TZPR register and TZSC register are made effective by writing a value to the TZPR register. The set values are reflected to the waveform output beginning with the next primary period after writing to the Timer Z primary register. 3. The TZOCNTbit is enabled in the following timings
• When count starts
• When Timer Z interrupt request is generated Therefore, pulse is output from the next primary period depending on the setting value of the TZOCNT bit. Table 12.10 Programmable Waveform Generation Mode Specifications

Rev.1.20 Jan 27, 2006 page 79 of 180 REJ09B0019-0120 Figure 12.23 TYZMR Register and PUM Register in Programmable Waveform Generation Mode Bit name Function Bit symbol Timer Y, Z waveform output control register S y m b o lA d d r e s sA f t e r r e s e t P U 6 0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 T Y O P L T Z O P L I N O S E G I N O S T G I N T 0 p i n o n e - s h o t t r i g g e r p o l a r i t y s e l e c t b i t Timer Z output level latch T i m e r Y - r e l a t e d b i t I N T 0 p i n o n e - s h o t t r i g g e r c o n t r o l b i t M u s t s e t t o “ 0 ” i n p r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e M u s t s e t t o “ 0 ” i n p r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e 0 : Outputs "H" for primary period Outputs "L" for secondary period Outputs "L" when the timer is stopped 1 : Outputs "L" for primary period Outputs "H" for secondary period Outputs "H" when the timer is stopped ( b 3 - b 0 ) Reserved bit M u s t s e t t o “ 0 ” RW RW RW RW RW RW 000000 T i m e r Y , Z m o d e r e g i s t e r S y m b o lA d d r e s sA f t e r r e s e t T Y Z M 6 0 B i t n a m e F u n c t i o nB i t s y m b o l b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 T Z M O D 1 T Y S T Y W C T Y M O D 0 T Z M O D 0 T i m e r Y - r e l a t e d b i t T Z W C T Z S 0 S t o p s c o u n t i n g S t a r t s c o u n t i n g T i m e r Z c o u n t s t a r t f l a g T i m e r Z o p e r a t i o n m o d e b i t b b T i m e r Z w r i t e c o n t r o l b i t N O T E S : W h e n T Z S b i t s t a r t s c o u n t i n g t h e t i m e r Y c o u n t v a u e i s w r i t t e n t o t h e r e l o a d r e g i s t e r o n l y W h e n T Z S b i t s t o p s c o u n t i n g t h e t i m e r Y c o u n t v a l u e i s w r i t t e n t o b o t h r e l o a d r e g i s t e r a n d c o u n t e r R W R W R W R W R W R W R W R W R 1 E D G R W S e t t o " 1 " i n p r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e(1 0 1 : P r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e

Rev.1.20 Jan 27, 2006 page 80 of 180 REJ09B0019-0120

12.3.3 Programmable One-shot Generation Mode

In this mode, upon program command or external trigger input (input to the INT0 pin), the microcom- puter outputs the one-shot pulse from the TZ OUT pin (see “Table 12.11 Programmable One-shot Generation Mode Specifications”). When a trigger occurs, the timer starts operating from the point only once for a given period equal to the set value in the TZPR register. The TZSC is unused in this mode. Figure 12.24 shows the TYZMR register and PUM register in this mode. Figure 12.25 shows an operation example in this mode. Item Specification Count source f 1, f2, f8, Timer Y underflow Count operation • Downcounts set value in TZPR register

• When the timer underflows, it reloads the contents of reload register before completing counting and the TZOS bit is “0”.
• When a count stops, the timer reloads the contents of the reload register before it stops. One-shot pulse output (n+1)(m+1)/fi duration fi : count source frequency, n: set value in PREZ register, m: set value in TZPR register Count start condition • Set TZOS bit in TYZOC register to “1” (start one-shot)(1)
• Input active trigger to INT0 pin(2) Count stop condition • When reloading is completed after count value was set to "0016"
• When TZS bit in TYZMR register is set to “0” (stop counting)
• When TZOS bit in TYZOC register is set to “0” (stop one-shot) Interrupt request generation timingIn half cycles of count source, after the timer underflows (at the same time as the TZout output ends) [Timer Z interrupt] TZOUT pin function Pulse output Use timer mode when using this pin as a programmable I/O port. INT0 pin function Programmable I/O port, INT0 interrupt input or external trigger input
• When the INOSTG bit in the PUM register is set to “0” (INT0 one-shot trigger disabled) Programmable I/O port or INT0 interrupt input
• When the INOSTG bit in the PUM register is set to “1” (INT0 one-shot trigger enabled) external trigger (INT0 interrupt input) Read from timer Count value can be read out by reading TZPR register. Same applies to PREZ register. Write to timer Value written to TZPR register is written to reload register only(3). Same applies to PREZ register. Select function • Output level latch select function Output level for one-shot pulse waveform is selected by TZOPL bit.
• INT0 pin one-shot trigger control function and polarity select function Trigger input from INT0 pin can be set to active or inactive by INOSTG bit. Also, an active trigger's polarity can be selected by INOSEG bit. NOTES: 1. The TZS bit in the TYZMR register must be set to "1" (start counting). 2. The TZS bit must be set to "1" (start counting), the INT0EN bit in the INTEN register to "1" (enabling INT0 input), and the INOSTG bit in the PUM register to "1" (enabling INT0 one-shot trigger). Although the trigger input during counting cannot be acknowledged, the INT0 interrupt request is generated. 3. The set values are reflected beginning with the next one-shot pulse after writing to the TZPR register. Table 12.11 Programmable One-shot Generation Mode Specifications

Rev.1.20 Jan 27, 2006 page 81 of 180 REJ09B0019-0120 Figure 12.24 TYZMR Register and PUM Register in Programmable One-shot Generation Mode B i t n a m e F u n c t i o n B i t s y m b o l T i m e r Y , Z w a v e f o r m o u t p u t c o n t r o l r e g i s t e r Symbol Address After reset PUM 0084 16 0016 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 T Y O P L T Z O P L I N O S E G I N O S T G I N T 0 p i n o n e - s h o t t r i g g e r p o l a r i t y s e l e c t b i t Timer Z output level latch T i m e r Y - r e l a t e d b i t I N T 0 p i n o n e - s h o t t r i g g e r c o n t r o l b i t(2 R e s e r v e d b i t M u s t s e t t o “ 0 ”( b 3 - b 0 ) R W R W R W R W R W R W 0000 0 : E d g e t r i g g e r a t f a l l i n g e d g e E d g e t r i g g e r a t r i s i n g e d g e 0 : O u t p u t s " H " l e v e l o n e - s h o t p u l s e . O u t p u t s L w h e n t h e t i m e r i s s t o p p e d O u t p u t s L l e v e l o n e s h o t p u l s e O u t p u t s H w h e n t h e t i m e r i s s t o p p e d 0 : I N T 0 p i n o n e - s h o t t r i g g e r d i s a b l e d I N T p i n o n e s h o t t r i g g e r e n a b l e d(2 N O T E S : T h e I N O S E G b i t i s v a l i d o n l y w h e n t h e I N T P L b i t i n t h e I N T E N r e g i s t e r i s s e t t o o n e e d g e T h e I N O S G T b i t m u s t b e s e t t o a f t e r t h e I N T E N b i t i n t h e I N T E N r e g i s t e r a n d t h e I N O S E G b i t i n t h e P U M r e g i s t e r a r e s e t W h e n s e t t i n g t h e I N O S T G b i t t o I N T p i n o n e s h o t t r i g g e r e n a b l e d t h e I N T F a n d I N T F b i t s i n t h e I N T F r e g i s t e r m u s t b e s e t T h e I N O S T G b i t m u s t b e s e t t o I N T p i n o n e s h o t t r i g g e r d i s a b l e d a f t e r t h e T Z S b i t i n t h e T Y Z M R r e g i s t e r i s s e t t o c o u n t s t o p T i m e r Y , Z m o d e r e g i s t e r S y m b o lA d d r e s sA f t e r r e s e t T Y Z M 6 0 Bit name F u n c t i o nB i t s y m b o l b 7 b 6 b 5 b4 b 3 b2 b 1 b 0 TZMOD1 T Y S T Y W C T Y M O D 0 TZMOD0 T i m e r Y - r e l a t e d b i t TZWC TZS 0 : Stops counting 1 : Starts counting T i m e r Z c o u n t s t a r t f l a g Timer Z operation mode bit b b Timer Z write control bit NOTES: 1. When the TZS bit is set to “1”(count starts), the count value is written to the reload register only. When the TZS bit is set to “0”(count stops), the count value is written to both the reload register and counter. RW RW RW RW RW RW RW RW R1EDG RW Set to "1" in programmable one-shot generation mode (1) 1 0 : Programmable one-shot generation mode

Rev.1.20 Jan 27, 2006 page 82 of 180 REJ09B0019-0120 Figure 12.25 Operation Example in Programmable One-shot Generation Mode Count source TZOUT pin output IR bit in TZIC register TZS bit in TYZMR register “1” “0” 0116 0016 0116 0016 Timer Z primary reload Set to “0” when interrupt request is acknowledged or by program Waveform output starts Waveform output completes TZOPL bit in PUM register TZOS bit in TYZOC register Contents of Timer Z Set to “1” by program 0116 Count starts Set to “1” by INT0 pin input trigger Set to “0” when count completes The above applies to the following conditions; PREZ=01 16, TZPR=0116 TZOPL bit in PUM register=0, INOSTG bit= 1(INT0 one-shot trigger enabled) INOSEG bit= 1(rising edge trigger) INT0 pin input Prescaler Z underflow signal “1” “0” “1” “0” “1” “0” “0” “1” “H ” “L” Set to “1” by program Set to “1” by program Count starts Timer Z primary reload Waveform output starts Waveform output completes

Rev.1.20 Jan 27, 2006 page 83 of 180 REJ09B0019-0120

12.3.4 Programmable Wait One-shot Generation Mode

In this mode, upon program or external trigger input (input to the INT0 pin), the microcomputer outputs the one-shot pulse from the TZ OUT pin after waiting for a given length of time (see “Table 12.12 Programmable Wait One-shot Generation Mode Specifications”). When a trigger occurs, from this point, the timer starts outputting pulses only once for a given length of time equal to the set value in the TZSC register after waiting for a given length of time equal to the set value in the TZPR register. Figure 12.26 shows the TYZMR and PUM registers in this mode. Figure 12.27 shows an operation example in this mode. Item Specification Count source f 1, f2, f8, Timer Y underflow Count operation • Downcounts set value in Timer Z primary

• When a counting of TZPR register underflows, the timer reloads the contents of TZSC register before continuing counting.
• When a counting of TZSC register underflows, the timer reloads the contents of TZPR register before completing counting and the TZOS bit is “0”.
• When a count stops, the timer reloads the contents of the reload register before it stops. Wait time (n+1)(m+1)/fi n: set value in PREZ register, m: set value in TZPR register One-shot pulse output time (n+1)(p+1)/fi n : set value in PREZ, p: set value in TZSC register Count start condition • Set TZOS bit in TYZOC register to “1” (start one-shot)(1)
• Input active trigger to INT0 pin(2) Count stop condition • When reloading is completed after count value at counting TZSC register was set to "0016"
• When TZS bit in TYZMR register is set to “0” (stop counting)
• When TZOS bit in TYZOC register is set to “0” (stop one-shot) Interrupt request generation timingIn half cycles of count source, after count value at counting TZSC register is set "0016" (at the same time as the TZout output change) [Timer Z interrupt] TZOUT pin function Pulse output Use timer mode when using this pin as a programmable I/O port. INT0 pin function Programmable I/O port, INT0 interrupt input or external trigger input
• When the INOSTG bit in the PUM register is set to “0” (INT0 one-shot trigger disabled) Programmable I/O port or INT0 interrupt input
• When the INOSTG bit in the PUM register is set to “1” (INT0 one-shot trigger enabled) external trigger (INT0 interrupt input) Read from timer Count value can be read out by reading TZPR register. Same applies to PREZ register. Write to timer Value written to TZPR register and PREZ register are written to reload register only(3). Same applies to TZSC register. Select function • Output level latch select function Output level for one-shot pulse waveform is selected by TZOPL bit.
• INT0 pin one-shot trigger control function and polarity select function Trigger input from INT0 pin can be set to active or inactive by INOSTG bit. Also, an active trigger's polarity can be selected by INOSEG bit. NOTES: 1. The TZS bit in the TYZMR register must be set to "1" (start counting). 2. The TZS bit must be set to "1" (start counting), the INT0EN bit in the INTEN register to "1" (enabling INT0 input), and the INOSTG bit in the PUM register to "1" (enabling INT0 one-shot trigger) Although the trigger input during counting cannot be acknowledged, the INT0 interrupt request is generated. 3. The set values are reflected beginning with the next one-shot pulse after writing to the TZPR register. Table 12.12 Programmable Wait One-shot Generation Mode Specifications

Rev.1.20 Jan 27, 2006 page 84 of 180 REJ09B0019-0120 Figure 12.26 TYZMR Register and PUM Register in Programmable Wait One-shot Generation Mode Bit name Function Bit symbol Timer Y, Z waveform output control register Symbol Address After reset PUM 0084 16 0016 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 TYOP L TZOPL INOSEG INOSTG I N T 0 p i n o n e - s h o t t r i g g e r p o l a r i t y s e l e c t b i t(1 T i m e r Z o u t p u t l e v e l l a t c h T i m e r Y - r e l a t e d b i t I N T 0 p i n o n e - s h o t t r i g g e r c o n t r o l b i t(2 R e s e r v e d b i t Must set to “0”(b3-b0) RW R W R W R W R W R W 0000 0 : Edge trigger at falling edge 1 : Edge trigger at rising edge 0 : Outputs "H" level one-shot pulse. Outputs "L" when the timer is stopped. 1 : Outputs "L" level one-shot pulse Outputs "H" when the timer is stopped. 0 : INT0 pin one-shot trigger disabled 1 : INT0 pin one-shot trigger enabled(2) N O T E S : T h e I N O S E G b i t i s v a l i d o n l y w h e n t h e I N T P L b i t i n t h e I N T E N r e g i s t e r i s s e t t o o n e e d g e T h e I N O S G T b i t m u s t b e s e t t o a f t e r t h e I N T E N b i t i n t h e I N T E N r e g i s t e r a n d t h e I N O S E G b i t i n t h e P U M r e g i s t e r a r e s e t W h e n s e t t i n g t h e I N O S T G b i t t o I N T p i n o n e s h o t t r i g g e r e n a b l e d t h e I N T F a n d I N T F b i t s i n t h e I N T F r e g i s t e r m u s t b e s e t T h e I N O S T G b i t m u s t b e s e t t o I N T p i n o n e s h o t t r i g g e r d i s a b l e d a f t e r t h e T Z S b i t i n t h e T Y Z M R r e g i s t e r i s s e t t o c o u n t s t o p T i m e r Y , Z m o d e r e g i s t e r S y m b o lA d d r e s sA f t e r r e s e t T Y Z M 6 0 Bit name F u n c t i o nB i t s y m b o l b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 T Z M O D 1 TYS T Y W C T Y M O D 0 T Z M O D 0 Timer Y-related bit TZWC TZS 0 : Stops counting 1 : Starts counting Timer Z count start flag Timer Z operation mode bit b5 b4 Timer Z write control bit N O T E S : W h e n t h e T Z S b i t i s s e t t o c o u n t s t a r t s t h e c o u n t v a l u e i s w r i t t e n t o t h e r e l o a d r e g i s t e r o n l y W h e n t h e T Z S b i t i s s e t t o c o u n t s t o p s t h e c o u n t v a l u e i s w r i t t e n t o b o t h t h e r e l o a d r e g i s t e r a n d c o u n t e r R W R W R W R W R W R W RW RW R 1 E D G R W Must set to "1" in programmable wait one-shot generation mode1 1 1 : P r o g r a m m a b l e w a i t o n e - s h o t g e n e r a t i o n m o d e

Rev.1.20 Jan 27, 2006 page 85 of 180 REJ09B0019-0120 T ZO U T p i n o u t p u t The above applies to the following conditions; PREZ=01 16, TZPR=0116, TZSC=0216 TZOPL bit in PUM register=0, INOSTG bit=1(INT0 one-shot trigger enabled) INOSEG bit=1(rising edge trigger) IR bit in TZIC register 0 11 6 0016 0 21 W ait starts TZOPL bit in PUM register I N T0 i n p u t p i n Contents of Timer Z T Z S b i t i n T Y Z M R r e g i s t e r “ 1 ” “0” 01160 11 6 0016 Timer Z secondary reload C o u n t s o u r c e P r e s c a l e r Z u n d e r f l o w s i g n a l T Z O S b i t i n T Y Z O C r e g i s t e r S e t t o “1” b y p r o g r a m o r “1” b y I N p i n i n p u t t r i g g e r “ 1 ” “ 0 ” “ 1 ” “ 0 ” “ 1 ” “ 0 ” “ 1 ” “ 0 ” “H ” “ L ” S e t t o “1” b y p r o g r a m Set to “0” when count completes C o u n t s t a r t s Timer Z primary reload Set to “0” when interrupt request is acknowledged or by program S e t t o “0” b y p r o g r a m W a v e f o r m o u t p u t s t a r t s W a v e f o r m o u t p u t c o m p l e t e s Figure 12.27 Operation Example in Programmable Wait One-shot Generation Mode

Rev.1.20 Jan 27, 2006 page 86 of 180 REJ09B0019-0120

12.4 Timer C

Timer C is a 16-bit free-running timer. Figure 12.28 shows a block diagram of Timer C. The Timer C uses an edge input to TCIN pin or the fRING128 clock as trigger to latch the timer count value and generates an interrupt request. The TCIN input has a digital filter and this prevents an error caused by noise or so on from occurring. Table 12.13 shows Timer C specifications. Figure 12.29 shows TC, TM0, TCC0, and TCC1 registers. Figure 12.30 shows an operation example of Timer C. Item Specification Count source f 1, f8, f32 Count operation • Count up

• Transfer value in TC register to TM0 register at active edge of measurement pulse
• Value in TC register is set to “000016” when a counting stops Count start condition TCC00 bit in TCC0 register is set to “1” (capture enabled) Count stop condition TCC00 bit in TCC0 register is set to “0” (capture disabled) Interrupt request
• When active edge of measurement pulse is input [INT3 interrupt] generation timing • When Time C underflows [Timer C interrupt] INT3/TCIN pin function Programmable I/O or measurement pulse input Counter value reset timing When TCC00 bit in TCC0 register is set to “0” (capture disabled) Read from timer(1) • Counter value can be read out by reading TC register.
• Counter value at measurement pulse active edge input can be read out by reading TM0 register. Write to timer Write to TC register and TM0 register is disabled Select function
• INT3/TCIN switching function Measurement pulse active edge is selected by TCC03 to TCC04 bits
• Digital filter function Digital filter sampling frequency is selected by TCC11 to TCC10 bits
• Trigger select function TC IN input or fRING128 is selected by TCC07 bit. NOTES: 1. TC register and TM0 register must be read in 16-bit units. TM0 register Upper 8 bits Lower 8 bits Counter f32 Edge detection fRING128 Timer C interrupt TCC07=1 Transfer signal Digital filter f32 TCC11 to TCC10 =012 TC register Data bus Upper 8 bits Lower 8 bits INT3/TCIN =102 =112 TCC07=0 TCC02 to TCC01 =002 =012 =102 INT3 interrupt TCC11 to TCC10 =002 Other than 002 TCC01, TCC02, TCC07: Bits in TCC0 register TCC10, TCC11: Bits in TCC1 register Sampling clock Table 12.13 Timer C Specifications Figure 12.28 Timer C Block Diagram

12.4 Timer (Timer C)

Rev.1.20 Jan 27, 2006 page 87 of 180 REJ09B0019-0120 Symbol Address After reset TC 0091 16-009016 000016 RW Internal count source is counted Function Timer C register Symbol Address After reset TM0 009D 16-009C16 000016 When active edge of measurement pulse is input, the counter value of Timer C is stored Function Capture register b7 b0 b7b0 (b15) (b8) b7 b0 b7b0 (b15) (b8) RO RW RO Figure 12.29 TC Register, TM0 Register, TCC0 Register, and TCC1 Register T i m e r C c o n t r o l r e g i s t e r 0 S y m b o lA d d r e s sA f t e r r e s e t T C C 6 0 B i t n a m e FunctionB i t s y m b o l b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 0 : f1 A v o i d t h i s s e t t i n g T C C 0 4 TCC02 T C C 0 1 TCC00 T C C 0 3 Timer C count start bit Timer C count source select bit(1) 0 : C o u n t s t o p s C o u n t s t a r t s T C C 0 7 b b T i m e r C c o n t r o l r e g i s t e r 1 S y m b o lA d d r e s sA f t e r r e s e t T C C 6 0 B i t n a m e FunctionB i t s y m b o l b7 b6 b5 b4 b3 b2 b1 b0 T C C 1 1 T C C 1 0 0 0 : Rising edge 0 1 : Falling edge 1 0 : Both edges 1 1 : Avoid this setting b4 b3 b b I N T i n p u t f i l t e r s e l e c t b i t(1 N O T E S : I n p u t i s r e c o g n i z e d o n l y w h e n t h e s a m e v a l u e f r o m I N T p i n i s s a m p l e d t h r e e t i m e s i n s u c c e s s i o n R W ( b 6 - b 5 ) INT3 interrupt and capture input polarity select bit(1, 2) I N T 3 i n t e r r u p t a n d c a p t u r e i n p u t s w i t c h i n g b i t(1 0 : INT3 1 : fRING128 R W RW RW R W R e s e r v e d b i t (b7-b2) R W R W R W R W 0 0 : No filter 0 1 : Filter with f1 sampling 1 0 : Filter with f8 sampling 1 1 : Filter with f32 sampling N O T E S : C h a n g e t h i s b i t w h e n T C C b i t i s s e t t o c o u n t s t o p T h e I R b i t i n t h e I N T I C m a y b e s e t t o i n t e r r u p t r e q u e s t e d w h e n t h e T C C T C C o r T C C b i t i s r e w r i t t e n R e f e r t o t h e p a r a g r a p h C h a n g i n g I n t e r r u p t F a c t o r i n t h e U s a g e N o t e s R e f e r e n c e B o o k 0 0 0 0 0 0 RW RW r e s e r v e d b i t S e t t o " 0 " S e t t o " 0 " R W

Rev.1.20 Jan 27, 2006 page 88 of 180 REJ09B0019-0120 Counter contents (hex) TCC00 bit in TCC0 register Measurement pulse (TCIN pin input) TM0 register FFFF 16 000016 Conditions: TCC0 register TCC04 to TCC03 bits=012 (capture input polarity is set for falling edge), TCC07=0 (INT3/TCIN input as capture input trigger) Count start IR bit in TCIC register “H ” “L” “1” “0” Set to “0” when interrupt request is accepted, or set by program Set to "0" by program Set to "1" by program Overflow Measurement value 2 Indeterminate Set to “0” when interrupt request is accepted, or set by program IR bit in INT3IC register Measurement value 1 Transmit timing from Timer C counter to TM0 register Measurement value 1 Measurement value 2 Measurement value 3 Indeterminate Transmit (Measurement value 3) Transmit (Measurement value 2) Transmit (Measurement value 1) Time Measure- ment value 3 “1” “0” “1” “0” The delay caused by digital filter Figure 12.30 Operation Example of Timer C

R8C/10 Group 13. Serial InterfaceI Rev.1.20 Jan 27, 2006 page 90 of 180 REJ09B0019-0120 i S P S t o p b i t P A R P a r i t y b i t SP SP PAR 2SP 1SP UART UART (7 bits) UART (8 bits) U A R T ( 7 b i t s ) U A R T ( 9 b i t s ) Clock synchronous type Clock synchronous type TxDi U A R T i t r a n s m i t r e g i s t e r PAR enabled P A R d i s a b l e d D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 UiTB register M S B / L S B c o n v e r s i o n c i r c u i t UART (8 bits) UART (9 bits) Clock synchronous type U i R B r e g i s t e r UARTi receive register 2SP 1SP P A R e n a b l e d P A R d i s a b l e d U A R T UART (7 bits) U A R T ( 9 b i t s ) C l o c k s y n c h r o n o u s t y p e Clock synchronous type UART (7 bits) UART (8 bits) R x D i Clock synchronous type UART (8 bits) UART (9 bits) D a t a b u s l o w - o r d e r b i t s MSB/LSB conversion circuit D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0D 80000000 S PS P PAR “0” D a t a b u s h i g h - o r d e r b i t s NOTES: 1. Clock synchronous type is provide in UART0 only. P R Y E = 1 PRYE=0 P R Y E = 0 P R Y E = 1 Figure 13.2 UARTi Transmit/Receive Unit

R8C/10 Group 13. Serial Interface Rev.1.20 Jan 27, 2006 page 91 of 180 REJ09B0019-0120 Figure 13.3 U0TB and U1TB Registers, U0RB and U1RB Registers, and U0BRG and U1BRG Registers b 7 ( b 1 5 ) ( b 1 5 ) S y m b o lA d d r e s sA f t e r r e s e t U R A A 6 I n d e t e r m i n a t e U R A A 6 I n d e t e r m i n a t e b 7 b 0 ( b 8 ) b 7 b 0 U A R T i r e c e i v e b u f f e r r e g i s t e r( ) ( i = 0 , 1 ) F u n c t i o nB i t n a m eB i t s y m b o l 0 : N o f r a m i n g e r r o r F r a m i n g e r r o r f o u n d 0 : N o p a r i t y e r r o r P a r i t y e r r o r f o u n d 0 : N o e r r o r E r r o r f o u n d N O T E S : R e a d o u t t h e U i R B r e g i s t e r i n b i t u n i t A l l o f t h e S U M P E R F E R a n d O E R b i t s a r e s e t t o n o e r r o r w h e n t h e S M D t o S M D b i t s i n t h e U i M R r e g i s t e r a r e s e t t o 02” s e r i a l i n t e r f a c e d i s a b l e d o r t h e R E b i t i n t h e U i C r e g i s t e r i s s e t t o r e c e p t i o n d i s a b l e d T h e S U M b i t i s s e t t o n o e r r o r w h e n a l l o f t h e P E R F E R a n d O E R b i t s a r e s e t t o n o e r r o r T h e P E R a n d F E R b i t s a r e s e t t o e v e n w h e n t h e h i g h e r b y t e o f t h e U i R B r e g i s t e r i s r e a d O E R F E R P E R S U M O v e r r u n e r r o r f l a g(2 F r a m i n g e r r o r f l a g(2 P a r i t y e r r o r f l a g(2 E r r o r s u m f l a g(2 0 : N o o v e r r u n e r r o r O v e r r u n e r r o r f o u n d R e c e i v e d a t a ( D 7 t o D 0) U A R T i b i t r a t e r e g i s t e r( ) ( i = 0 , 1 ) b 0 S y m b o lA d d r e s sA f t e r r e s e t U B R A 6 I n d e t e r m i n a t e U B R A 6 I n d e t e r m i n a t e F u n c t i o n A s s u m i n g t h a t s e t v a l u e = n , U i B R G d i v i d e s t h e c o u n t s o u r c e b y n 1 0 01 6 t o F F1 S e t t i n g r a n g e N O T E S : W r i t e t o t h i s r e g i s t e r w h i l e s e r i a l i n t e r f a c e i s n e i t h e r t r a n s m i t t i n g n o r r e c e i v i n g U s e M O V i n s t r u c t i o n t o w r i t e t o t h i s r e g i s t e r A f t e r s e t t i n g t h e C L K t o C L K b i t s o f t h e U i C r e g i s t e r w r i t e t o t h e U i B R G r e g i s t e r b 7 b 0 ( b 8 ) b 7 b 0 U A R T i t r a n s m i t b u f f e r r e g i s t e r(1 ) ( i = 0 , 1 ) F u n c t i o n T r a n s m i t d a t a N o t h i n g i s a s s i g n e d . W h e n w r i t e s e t t o W h e n r e a d i t s c o n t e n t i s i n d e t e r m i n a t e S y m b o lA d d r e s sA f t e r r e s e t U T A A 6 I n d e t e r m i n a t e U T A A 6 I n d e t e r m i n a t e R W N O T E S : W h e n t r a n s f e r d a t a l e n g t h i s b i t l o n g w r i t e h i g h b y t e f i r s t t h e n l o w b y t e U s e M O V i n s t r u c t i o n t o w r i t e t o t h i s r e g i s t e r W O R W R O R O R O R O R O ( b 7 - b 0 ) ( b 1 1 - b 9 ) R W W O R e c e i v e d a t a ( D 8) R O( b 8 ) N o t h i n g i s a s s i g n e d . W h e n w r i t e s e t t o W h e n r e a d i t s c o n t e n t i s i n d e t e r m i n a t e B i t s y m b o l ( b 8 - b 0 ) ( b 1 5 - b 9 )

R8C/10 Group 13. Serial InterfaceI Rev.1.20 Jan 27, 2006 page 92 of 180 REJ09B0019-0120 U A R T i t r a n s m i t / r e c e i v e m o d e r e g i s t e r ( i = 0 , 1 ) Symbol Address After reset U0MR 00A0 16 0016 U1MR 00A8 16 0016 b 7b 6b B i t n a m eB i t s y m b o l R W C K D I R S M D 1 S M D 0 S e r i a l i n t e r f a c e m o d e s e l e c t b i t(2 S M D 2 Internal/external clock select bit(3) S T P S P R Y PRYE (b7) Parity enable bit 0 : Internal clock 1 : External clock(1) Stop bit length select bit Odd/even parity select bit Reserved bit 0 : 1 s t o p b i t s t o p b i t s 0 : P a r i t y d i s a b l e d P a r i t y e n a b l e d 0 0 0 : Serial interface disabled 0 0 1 : Clock synchronous serial I/O mode 1 0 0 : UART mode transfer data 7 bits long 1 0 1 : UART mode transfer data 8 bits long 1 1 0 : UART mode transfer data 9 bits long Do not set except above b2 b1 b0 E f f e c t i v e w h e n P R Y E = 1 O d d p a r i t y E v e n p a r i t y Set to “0” F u n c t i o n NOTES: 1. Must set the P1_6 bit in the PD1 register to “0” (input). 2. For the U1MR register, the SMD2 to SMD0 bits must not be set except the followings: “0002”, “1002”, “1012”, or “1102”. 3. Must set the CKDIR bit to “0” (internal clock) in UART1. U A R T i t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 0 ( i = 0 , 1 ) Symbol Address After reset U0C0 00A4 16 0816 U1C0 00AC 16 0816 b F u n c t i o n TXEPT CLK1 CLK0 (b2) NCH CKPOL BRG count source select bit(1) Transmit register empty flag 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge CLK polarity select bit Data output select bit 0 0 : f1SIO is selected 0 1 : f8SIO is selected 1 0 : f32SIO is selected 1 1 : Avoid this setting b1 b0 0 : LSB first 1 : MSB first 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) Nothing is assigned. When write, set to “0”. When read, its content is indeterminate. 0 : TxDi pin is a pin of CMOS output 1 : TxDi pin is a pin of N-channel open-drain output U F O R MT r a n s f e r f o r m a t s e l e c t b i t B i t n a m eB i t s y m b o l R W R W R W R W R W RW RW RW RW RW RW R W RW R W R W RO Reserved bit Set to “0” ( b 4 ) N O T E S : I f t h e B R G c o u n t s o u r c e i s s w i t c h e d s e t t h e U i B R G r e g i s t e r a g a i n Figure 13.4 U0MR and U1MR Registers and U0C0 and U1C0 Registers

R8C/10 Group 13. Serial Interface Rev.1.20 Jan 27, 2006 page 93 of 180 REJ09B0019-0120 U A R T i t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 1 ( i = 0 , 1 ) S y m b o lA d d r e s sA f t e r r e s e t U C A 6 0 U C A D 1 6 0 b Bit nameBit symbol R WFunction T E T I R E R I Transmit enable bit Receive enable bit(1) Receive complete flag(2) Transmit buffer empty flag 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in UiTB register 1 : No data present in UiTB register 0 : Reception disabled 1 : Reception enabled 0 : No data present in UiRB register 1 : Data present in UiRB register N o t h i n g i s a s s i g n e d . W h e n w r i t e s e t W h e n r e a d i t s c o n t e n t i s R W R W R O R O ( b 7 - b 4 ) N O T E S : A s f o r t h e U A R T s e t t h e T X D E N b i t i n t h e U C O N r e g i s t e r b e f o r e s e t t i n g t h i s b i t t o r e c e p t i o n e n a b l e d T h e R I b i t i s s e t t o w h e n t h e h i g h e r b y t e o f t h e U i R B r e g i s t e r i s r e a d Figure 13.5 U0C1 and U1C1 Registers and UCON Register N O T E S : F o r P 37, s e l e c t R x D 1) f o r d a t a r e c e i v e a n d T x D 1 f o r d a t a t r a n s f e r S e t t h e P D b i t i n t h e P D r e g i s t e r t o i n p u t m o d e w h e n r e c e i v i n g D o n o t s e t t h e T X D S E L a n d T X D E N b i t s t o a t t h e s a m e t i m e s i n c e t h e y f u n c t i o n i n d e p e n d e n t l y U A R T t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 2 S y m b o lA d d r e s sA f t e r r e s e t U C O B 6 0 b 6b 5b 1b 0 Bit nameBit symbol RWF u n c t i o n T X D 1 S E L T X D 1 E N UART0 transmit interrupt cause select bit UART0 continuous receive mode enable bit 0 : Continuous receive mode disabled 1 : Continuous receive mode enable Port TxD11 switching bit(2) UART1 transmit interrupt cause select bit 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : RxD1 1 : TxD10 N o t h i n g i s a s s i g n e d . W h e n w r i t e s e t W h e n r e a d i t s c o n t e n t i s U 0 I R S U 1 I R S U0RRM TxD 10/RxD1 select bit(2) 0 : I/O port P00 1 : TxD11 Must set to “0” R W RW R W R W R W R W ( b 7 ) (b4-b3) R e s e r v e d b i t 0 0

R8C/10 Group 13.1 Clock Synchronous Serial I/O Mode Rev.1.20 Jan 27, 2006 page 94 of 180 REJ09B0019-0120

13.1 Clock Synchronous Serial I/O Mode

The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. This mode can be selected with UART0. Table 13.1 lists the specifications of the clock synchronous serial I/O mode. Table 13.2 lists the registers used in clock synchronous serial I/O mode and the register values set. Item Specification Transfer data format • Transfer data length: 8 bits Transfer clock • CKDIR bit in U0MR register is set to “0” (internal clock): fi/(2(n+1)) fi=f1SIO, f8SIO, f32SIO n=setting value in UiBRG register: 0016 to FF16

• CKDIR bit is set to “1” (external clock ): input from CLK0 pin Transmission start condition• Before transmission can start, the following requirements must be met(1) _ TE bit in U0C1 register is set to “1” (transmission enabled) _ TI bit in U0C1 register is set to “0” (data present in U0TB register) Reception start condition• Before reception can start, the following requirements must be met(1) _ RE bit in U0C1 register is set to “1” (reception enabled) _ TE bit in U0C1 register is set to “1” (transmission enabled) _ TI bit in U0C1 register is set to “0” (data present in the U0TB register)
• For transmission, one of the following conditions can be selected _ U0IRS bit is set to “0” (transmit buffer empty): when transferring data from U0TB register to UART0 transmit register (at start of transmission) _ U0IRS bit is set to “1” (transfer completed): when serial interface finished sending data from UARTi transmit register
• For reception When transferring data from the UART0 receive register to the U0RB register (at completion of reception) Error detection • Overrun error(2) This error occurs if serial interface started receiving the next data before reading the U0RB register and received the 7th bit of the next data Select function • CLK polarity selection Transfer data I/O can be chosen to occur synchronously with the rising or the falling edge of the transfer clock
• LSB first, MSB first selection Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can be selected
• Continuous receive mode selection Reception is enabled immediately by reading the U0RB register NOTES: 1. When an external clock is selected, the conditions must be met while if the U0C0 register 0 CKPOL bit = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the external clock is in the high state; if the CKPOL bit in the U0C0 register is set to “1” (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state. 2. If an overrun error occurs, the value of U0RB register will be indeterminate. The IR bit of S0RIC register does not change. Interrupt request generation timing Table 13.1 Clock Synchronous Serial I/O Mode Specifications

Table 13. 2 Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode

1. Not all register bits are described above. Set those bits to “0” when writing to the registers in clock

synchronous serial I/O mode.

R8C/10 Group 13.1 Clock Synchronous Serial I/O Mode Rev.1.20 Jan 27, 2006 page 96 of 180 REJ09B0019-0120 Figure 13.6 Transmit and Receive Operation

• Example of transmit timing (when internal clock is selected) Stopped pulsing because the TE bit = 0 Write data to U0TB register Tc = TCLK = 2(n + 1) / fi fi: frequency of U0BRG count source (f1SIO, f8SIO, f32SIO) n: value set to U0BRG register “0” “1” “0” “1” “0” “1” “0” “1” Transferred from U0TB register to UART0 transmit register The above timing diagram applies to the case where the register bits are set as follows:
• U0MR register CKDIR bit = 0 (internal clock)
• U0C0 register CKPOL bit = 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock)
• U0IRS bit = 0 (an interrupt request occurs when the transmit buffer becomes empty): Set to “0” when interrupt request is accepted, or set by a program Transfer clock U0C1 register TE bit U0C1 register TI bit CLK 0 TxD 0 U0C0 register TXEPT bit S0TIC register IR bit D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 Tc TCLK Write dummy data to U0TB register Transferred from U0TB register to UART0 transmit register fEXT : frequency of external clock U0C1 register TE bit CLK 0 RxD 0 U0C1 register RI bit “0” “1” “0” “1” U0C1 register RE bit “0” “1” S0RIC register IR bit “0” “1” Make sure the following conditions are met when input to the CLK0 pin before receiving data is high:
• U0C1 register TE bit = 1 (transmit enabled)
• U0C1 register RE bit = 1 (receive enabled)
• Write dummy data to the U0TB register Receive data is taken in Read out from U0RB registerTransferred from UART0 receive register to U0RB register Set to “0” when interrupt request is accepted, or set by a program The above timing diagram applies to the case where the register bits are set as follows:
• U0MR register CKDIR bit = 1 (external clock)
• U0C0 register CKPOL bit = 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock) 1 / fEXT D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 “0” “1”U0C1 register TI bit
• Example of receive timing (when external clock is selected)

R8C/10 Group 13.1 Clock Synchronous Serial I/O Mode Rev.1.20 Jan 27, 2006 page 97 of 180 REJ09B0019-0120

13.1.1 Polarity Select Function

Figure 13.7 shows the polarity of the transfer clock. Use the CKPOL bit in the U0C0 register to select the transfer clock polarity. ( 2 ) W h e n t h e U 0 C 0 r e g i s t e r C K P O L b i t = 1 ( t r a n s m i t d a t a o u t p u t a t t h e r i s i n g e d g e a n d t h e r e c e i v e d a t a t a k e n i n a t t h e f a l l i n g e d g e o f t h e t r a n s f e r c l o c k D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 0 TXD 0 R XD 0 C L K0 ( 1 ) W h e n t h e U 0 C 0 r e g i s t e r C K P O L b i t = 0 ( t r a n s m i t d a t a o u t p u t a t t h e f a l l i n g e d g e a n d t h e r e c e i v e d a t a t a k e n i n a t t h e r i s i n g e d g e o f t h e t r a n s f e r c l o c k D 1 D 2 D 3 D 4 D 5 D 6 D 7D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7D 0 TXD 0 R XD 0 C L K0 NOTES: 1. When not transferring, the CLK0 pin outputs a high signal. 2. When not transferring, the CLK0 pin outputs a low signal. Figure 13.7 Transfer Clock Polarity

13.1.2 LSB First/MSB First Select Function

Figure 13.8 shows the transfer format. Use the UFORM bit in the U0C0 register to select the transfer format. Figure 13.8 Transfer Format ( 1 ) W h e n U 0 C 0 r e g i s t e r U F O R M b i t = 0 ( L S B f i r s t ) D 0 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 1 D 2 D 3 D 4 D 5 D 6 D 7 TXD 0 R XD 0 C L K0 ( 2 ) W h e n U 0 C 0 r e g i s t e r U F O R M b i t = 1 ( M S B f i r s t ) D 6 D 5 D 4 D 3 D 2 D 1 D 0D 7 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 TXD 0 R XD 0 C L K0 N O T E S : h i s a p p l i e s t o t h e c a s e w h e r e t h e C K P O L b i t i n t h e U C r e g i s t e r i s s e t t o t r a n s m i t d a t a o u t p u t a t t h e f a l l i n g e d g e a n d t h e r e c e i v e d a t a t a k e n i n a t t h e r i s i n g e d g e o f t h e t r a n s f e r c l o c k

R8C/10 Group 13.1 Clock Synchronous Serial I/O Mode Rev.1.20 Jan 27, 2006 page 98 of 180 REJ09B0019-0120

13.1.3 Continuous Receive Mode

The unit is configured to continuous receive mode by setting the U0RRM bit in the UCON register to “1” (enabling continuous receive mode). In this mode, reading the U0RB register sets the TI bit in the U0C1 register to “0”(data in the U0TB register). When the U0RRM bit is set to “1”, do not write dummy data to tge U0TB register in a program.

R8C/10 Group 13.2 Clock Asynchronous Serial I/O (UART) Mode Rev.1.20 Jan 27, 2006 page 99 of 180 REJ09B0019-0120 Item Specification Transfer data format • Character bit (transfer data): selectable from 7, 8 or 9 bits

• Start bit: 1 bit
• Parity bit: selectable from odd, even, or none
• Stop bit: selectable from 1 or 2 bits Transfer clock • UiMR(i=0, 1) register CKDIR bit = 0 (internal clock) : fj/(16(n+1)) fj=f1SIO, f8SIO, f32SIO n=setting value in UiBRG register: 0016 to FF16
• CKDIR bit = “1” (external clock) : fEXT /(16(n+1)) fEXT : input from CLKi pin n=setting value in UiBRG register: 0016 to FF16 Transmission start condition• Before transmission can start, the following requirements must be met _ TE bit in UiC1 register= 1 (transmission enabled) _ TI bit in UiC1 register = 0 (data present in UiTB register) Reception start condition• Before reception can start, the following requirements must be met _ RE bit in UiC1 register= 1 (reception enabled) _ Start bit detection Interrupt request •For transmission, one of the following conditions can be selected generation timing _ UiIRS bit = 0 (transmit buffer empty): when transferring data from UiTB register to UARTi transmit register (at start of transmission) _ UiIRS bit =1 (transfer completed): when serial interface finished sending data from UARTi transmit register
• For reception When transferring data from UARTi receive register to UiRB register (at completion of reception) Error detection • Overrun error(1) This error occurs if serial interface started receiving the next data before reading UiRB register and received the bit one before the last stop bit of the next data
• Framing error This error occurs when the number of stop bits set is not detected
• Parity error This error occurs when if parity is enabled, the number of 1’s in parity and character bits does not match the number of 1’s set
• Error sum flag This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered Select function • TXD 10, RXD 1 selection (UART) P37 pin can be used as RxD1 pin or TxD10 pin in UART1. Select by a program.
• TxD11 pin selection (UART1) P00 pin can be used as TxD11 pin in UART1 or port P00. Select by a program. NOTES: 1. If an overrun error occurs, the value of U0RB register will be indeterminate. The IR bit in the S0RIC register does not change.

13.2 Clock Asynchronous Serial I/O (UART) Mode

The UART mode allows transmitting and receiving data after setting the desired bit rate and transfer data format. Tables 13.4 lists the specifications of the UART mode. Table 13.5 lists the registers and settings for UART mode. Table 13.4 UART Mode Specifications

R8C/10 Group 13.2 Clock Asynchronous Serial I/O (UART) Mode Rev.1.20 Jan 27, 2006 page 100 of 180 REJ09B0019-0120 Table 13.5 Registers to Be Used and Settings in UART Mode Register Bit Function UiTB 0 to 8 Set transmission data (1) UiRB 0 to 8 Reception data can be read (1) OER,FER,PER,SUM Error flag UiBRG 0 to 7 Set a bit rate UiMR SMD2 to SMD0 Set these bits to ‘1002’ when transfer data is 7 bits long Set these bits to ‘1012’ when transfer data is 8 bits long Set these bits to ‘1102’ when transfer data is 9 bits long CKDIR Select the internal clock or external clock (2) STPS Select the stop bit PRY, PRYE Select whether parity is included and whether odd or even UiC0 CLK0, CLK1 Select the count source for the UiBRG register TXEPT Transmit register empty flag NCH Select TxDi pin output mode CKPOL Set to “0” UFORM LSB first or MSB first can be selected when transfer data is 8 bits long. Set this bit to “0” when transfer data is 7 or 9 bits long. UiC1 TE Set this bit to “1” to enable transmission TI Transmit buffer empty flag RE Set this bit to “1” to enable reception RI Reception complete flag UCON U0IRS, U1IRS Select the source of UART0/UART1 transmit interrupt U0RRM Set to “0” TXD1SEL Select output pin for UART1 transfer data TXD1EN Select TxD 10 or RxD1 to be used NOTES: 1. The bits used for transmit/receive data are as follows: Bit 0 to bit 6 when transfer data is 7 bits long; bit 0 to bit 7 when transfer data is 8 bits long; bit 0 to bit 8 when transfer data is 9 bits long. 2. An external clock can be selected in UART0 only. Table 13.6 lists the functions of the input/output pins during UART mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an “H ”. (If the NCH bit is set to “1”(N-channel open-drain output), this pin is in high-impedance state.) Table 13.6 I/O Pin Functions in UART Mode Pin name Function Method of selection TxD 0 (P14) Serial data output Serial data input Programmable I/O port Transfer clock input Serial data output (Cannot be used as a port when performing reception only) RxD 0 (P15) CLK 0 (P16) U0MR register CKDIR bit=0 U0MR register CKDIR bit=1 PD1 register PD1_6 bit=0 PD1 register PD1_5 bit=0 (Can be used as an input port when performing transmission only) TXD1EN=1 TXD1EN=0, PD3 register PD3_7 bit=0 Serial data output, TXD1SEL=1 Serial data output Serial data input TxD 10/RxD1 (P37) TxD 11 (P00)

R8C/10 Group 13.2 Clock Asynchronous Serial I/O (UART) Mode Rev.1.20 Jan 27, 2006 page 101 of 180 REJ09B0019-0120 TxDi Transfer clock UiC1 register TE bit UiC1 register TI bit UiC0 register TXEPT bit SiTIC register IR bit Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT fj: frequency of UiBRG count source (f1SIO, f8SIO, f32SIO) fEXT : frequency of UiBRG count source (external clock) n: value set to UiBRG i: 0, 1 “1” “0” “1” “0” “1” “0” “1” “0” The above timing diagram applies to the case where the register bits are set as follows:

• UiMR register PRYE bit = 1 (parity enabled)
• UiMR register STPS bit = 0 (1 stop bit)
• UiIRS bit = 1 (an interrupt request occurs when transmit completed): Set to “0” when interrupt request is accepted, or set by a program D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST PS P D 0 D 1ST Tc SP Start bit Parity bit Stop bit Stopped pulsing because the TE bit = “0” Write data to UiTB register Transferred from UiTB register to UARTi transmit register
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits) Figure 13.9 Transmit Operation TxDi Transfer clock UiC1 register TE bit UiC1 register TI bit UiC0 register TXEPT bit SiRIC register IR bit “0” “1” “0” “1” “0” “1” “0” “1” The above timing diagram applies to the case where the register bits are set as follows:
• UiMR register PRYE bit = 0 (parity disabled)
• UiMR register STPS bit = 1 (2 stop bits)
• UiIRS bit = 0 (an interrupt request occurs when transmit buffer becomes empty) Tc D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST D 8 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST D 8 D 0 D 1STSP SPSPSP Write data to UiTB register Transferred from UiTB register to UARTi transmit register Set to “0” when interrupt request is accepted, or set by a program Stop bit Stop bit Start bit Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT fj: frequency of UiBRG count source (f1SIO, f8SIO, f32SIO) fEXT : frequency of UiBRG count source (external clock) n: value set to UiBRG i: 0, 1

R8C/10 Group 13.2 Clock Asynchronous Serial I/O (UART) Mode Rev.1.20 Jan 27, 2006 page 102 of 180 REJ09B0019-0120

• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) Figure 13.10 Receive Operation UiBRG output RxDi Transfer clock “1” “0” “0” “1” “0” “1” UiC1 register RE bit UiC1 register RI bit SiRIC register IR bit Start bit Sampled “L” Stop bit (GA 13 UM60) Set to “0” when interrupt request is accepted, or set by a program The above timing diagram applies to the case where the register bits are set as follows:
• UiMR register PRYE bit = 0 (parity disabled)
• UiMR register STPS bit = 0 (1 stop bit) i = 0, 1 D 0 D 1 D 7 Receive data taken in Reception triggered when transfer clock is generated by falling edge of start bit Transferred from UARTi receive register to UiRB register

13.2.1 TxD10/RxD1 Select Function (UART1)

P37 can be used as TxD10 output pin or RxD1 input pin by selecting with the TXD1EN bit in the UCON register. P37 is used as TxD10 output pin if the TXD1EN bit is set to “1” (TxD10) and used as RxD1 input pin if set to “0” (RxD1).

13.2.2 TxD11 Select Function (UART1)

P00 can be used as TxD11 output pin or a port by selecting with the TXD1SEL bit in the UCON register. P00 is used as TxD11 output pin if the TXD1SEL bit is set to “1” (TxD11) and used as an I/O port if set to “0” (P00).

R8C/10 Group 13.2 Clock Asynchronous Serial I/O (UART) Mode Rev.1.20 Jan 27, 2006 page 103 of 180 REJ09B0019-0120

13.2.3 Bit Rate

Divided-by-16 of frequency by the UiBRG (i=0 to 1) register in UART mode is a bit rate. <UART Mode>

• When selecting internal clock Setting value to the UiBRG register = –1 fj : Count source frequency of the UiBRG register (f1SIO, f8SIO and f32SIO)
• When selecting external clock Setting value to the UiBRG register = –1 fEXT : Count source frequency of the UiBRG register (external clock) fj Bit Rate ✕ 16 fEXT Bit Rate ✕ 16 Figure 13.11 Calculation Formula of UiBRG (i=0 to 1) Register Setting Value Table 13.7 Bit Rate Setting Example in UART Mode Bit Rate BRG System Clock = 16MHz System Clock = 8MHz (bps) Count Source BRG Setting ValueActual Time(bps)Error(%)BRG Setting ValueActual Time(bps)Error(%) 1200 f8 103 (67 16) 1201.92 0.16 51 (33 16) 1201.92 0.16 2400 f8 51 (33 16) 2403.85 0.16 25 (19 16) 2403.85 0.16 4800 f8 25 (19 16) 4807.69 0.16 12 (0C 16) 4807.69 0.16 9600 f1 103 (67 16) 9615.38 0.16 51 (33 16) 9615.38 0.16 14400 f1 68 (44 16) 14492.75 0.64 34 (22 16) 14285.71 –0.79 19200 f1 51 (33 16) 19230.77 0.16 25 (19 16) 19230.77 0.16 28800 f1 34 (22 16) 28571.43 –0.79 16 (10 16) 29411.76 2.12 31250 f1 31 (1F 16) 31250.00 0.00 15 (0F 16) 31250.00 0.00 38400 f1 25 (19 16) 38461.54 0.16 12 (0C 16) 38461.54 0.16 51200 f1 19 (13 16) 50000.00 –2.34 9 (09 16) 50000.00 –2.34

Rev.1.20 Jan 27, 2006 page 104 of 180 REJ09B0019-0120 14. A/D Converter The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive coupling amplifier. The analog inputs share the pins with P00 to P07. Therefore, when using these pins, make sure the corresponding port direction bits are set to “0” (input mode). When not using the A/D converter, set the VCUT bit to “0” (Vref unconnected), so that no current will flow from the VREF pin into the resistor ladder, helping to reduce the power consumption of the chip. The result of A/D conversion is stored in the AD register. Table 14.1 shows the performance of the A/D converter. Figure 14.1 shows a block diagram of the A/D converter, and Figures 14.2 and 14.3 show the A/D converter-related registers. Table 14.1 Performance of A/D converter Item Performance Method of A/D conversion Successive approximation (capacitive coupling amplifier) Analog input voltage(1) 0V to Vref Operating clock φAD (2) AV CC = 5V fAD , divide-by-2 of fAD , divide-by-4 of fAD AV CC = 3V divide-by-2 of fAD , divide-by-4 of fAD Resolution 8-bit or 10-bit (selectable) Integral nonlinearity error AVCC = Vref = 5V

• 8-bit resolution ±2LSB
• 10-bit resolution ±3LSB AVcc = Vref = 3.3V
• 8-bit resolution ±2LSB
• 10-bit resolution ±5LSB Operating modes One-shot mode and repeat mode (3) Analog input pins 8 pins (AN 0 to AN7) A/D conversion start conditionADST bit in ADCON0 register is set to “1” (A/D conversion starts) Conversion speed per pin•Without sample and hold function 8-bit resolution: 49 φAD cycles, 10-bit resolution: 59 φAD cycles
• With sample and hold function 8-bit resolution: 28 φAD cycles, 10-bit resolution: 33 φAD cycles NOTES: 1. Does not depend on use of sample and hold function. 2. The frequency of φ AD must be 10 MHz or less. When AVcc is less than 4.2V, φAD must be fAD /2 or less by dividing fAD . Without sample and hold function, the φAD frequency should be 250 kHz or more. With the sample and hold function, the φAD frequency should be 1 MHz or more. 3. In repeat mode, only 8-bit mode can be used. 14. A/D Converter

Rev.1.20 Jan 27, 2006 page 105 of 180 REJ09B0019-0120 φAD 1/2fA D A/D conversion rate selection C K S 1 = 1 C K S 0 = 0 AD register Resistor ladder S u c c e s s i v e c o n v e r s i o n r e g i s t e r A D C O N 0 Vcom VI N D a t a b u s VR E F A VS S V C U T = 0 V C U T = 1 CKS 0=1 C K S 1 = 0 D e c o d e r Comparator CH 2,CH 1,CH 0=0002 C H 2 , C H 1 , C H 0 = 0 0 12 C H 2 , C H 1 , C H 0 = 0 1 02 C H 2 , C H 1 , C H 0 = 0 1 12 C H 2 , C H 1 , C H 0 = 1 0 02 C H 2 , C H 1 , C H 0 = 1 0 12 CH 2,CH 1,CH 0=1102 C H 2 , C H 1 , C H 0 = 1 1 12 P07/AN0 P 06/ A N 1 P 05/ A N 2 P 04/ A N 3 P 02/ A N 5 P01/AN6 P00/AN7 P 03/ A N 4 CH0 to CH2: Bits in ADCON0 register Figure 14.1 A/D Converter Block Diagram 14. A/D Converter

Rev.1.20 Jan 27, 2006 page 106 of 180 REJ09B0019-0120 A D c o n t r o l r e g i s t e r 0(1 S y m b o lA d d r e s sA f t e r r e s e t A D C O N D 6 0 X X b 7 b 6 b5 b 4 b 3 b 2 b 1 b 0 A n a l o g i n p u t p i n s e l e c t b i 0 0 0 : A N 0 i s s e l e c t e d A N 1 i s s e l e c t e d A N 2 i s s e l e c t e d A N 3 i s s e l e c t e d A N 4 i s s e l e c t e d A N 5 i s s e l e c t e d A N 6 i s s e l e c t e d A N 7 i s s e l e c t e d C H 0 B i t s y m b o l Bit name Function C H 1 C H 2 A D o p e r a t i o n m o d e s e l e c t b i t 0 : O n e - s h o t m o d e R e p e a t m o d eM D A D S T A / D c o n v e r s i o n s t a r t f l a g 0 : A/D conversion disabled 1 : A/D conversion started F r e q u e n c y s e l e c t b i t ) 0 : fA D / 4 i s s e l e c t e d fA D / i s s e l e c t e dC K S 0 R W A D c o n t r o l r e g i s t e r 1( S y m b o l A d d r e s sA f t e r r e s e t A D C O N D 6 0 B i t n a m eF u n c t i o nB i t s y m b o l b 7 b 6 b5 b 4 b 3 b 2 b 1 b 0 b b b NOTES: 1. If the ADCON register is rewritten during A/D conversion, the conversion result is indeterminate. 2. When changing A/D operation mode, set analog input pin again. 3. This bit is valid when the CKS1 bit in the ADCON1 register is set to “0”. N O T E S : I f t h e A D C O N r e g i s t e r i s r e w r i t t e n d u r i n g A D c o n v e r s i o n t h e c o n v e r s i o n r e s u l t i s i n d e t e r m i n a t e I n r e p e a t m o d e t h e B I T S b i t m u s t b e s e t t o b i t m o d e T h e φ A D f r e q u e n c y m u s t b e M H z o r l e s s I f t h e V C U T b i t i s r e s e t f r o m V r e f u n c o n n e c t e d t o V r e f c o n n e c t e d w a i t f o r µ s o r m o r e b e f o r e s t a r t i n g A D c o n v e r s i o n B I T S 8/10-bit mode select bit(2) 0 : 8-bit mode 1 : 10-bit mode V C U T Vref connect bit(4) 0 : Vref not connected 1 : Vref connected Frequency select bit 1(3) C K S 1 Set to “0” R e s e r v e d b i t R W R W R W R W R W R W R W R W ( b 4 ) Set to “0”R e s e r v e d b i t ( b 5 ) S e t t o “ 0 ”R e s e r v e d b i t ( b 2 - b 0 ) R W R W R W R W R W R WS e t t o “ 0 ”R e s e r v e d b i t( b 6 - b 7 ) 0 : CKS0 bit in ADCON0 register is valid 1 : fAD is selected Figure 14.2 ADCON0 Register and ADCON1 Register 14. A/D Converter

Rev.1.20 Jan 27, 2006 page 107 of 180 REJ09B0019-0120 Figure 14.3 ADCON2 Register and AD Register 14. A/D Converter A D c o n t r o l r e g i s t e r 2( Symbol Address After reset ADCON2 00D4 16 0016 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 A D c o n v e r s i o n m e t h o d s e l e c t b i t 0 : W i t h o u t s a m p l e a n d h o l d W i t h s a m p l e a n d h o l d B i t s y m b o lB i t n a m e Function R W N O T E S : I f t h e A D C O N r e g i s t e r i s r e w r i t t e n d u r i n g A D c o n v e r s i o n t h e c o n v e r s i o n r e s u l t i s i n d e t e r m i n a t e N o t h i n g i s a s s i g n e d . W h e n w r i t e w r i t e W h e n r e a d i t s c o n t e n t i s A D r e g i s t e r S y m b o lA d d r e s sA f t e r r e s e t A D 0 C C 6 I n d e t e r m i n a t e When BITS bit in ADCON1 register is set to “1” (10-bit mode) Function (b15) b7b7 b0 b0 (b8) A/D conversion result N o t h i n g i s a s s i g n e d . W h e n w r i t e s e t t o W h e n r e a d i t s c o n t e n t i s When read, its content is indeterminate. SMP 000 R e s e r v e d b i tS e t t o “ 0 ”( b 3 - b 1 ) ( b 7 - b 4 ) R W R W R W RO RO 8 l o w - o r d e r b i t s o f A / D c o n v e r s i o n r e s u l t 2 high-order bits of A/D conversion result When BITS bit in ADCON1 register is set to “0” (8-bit mode)

Rev.1.20 Jan 27, 2006 page 108 of 180 REJ09B0019-0120

14.1 One-shot Mode

In one-shot mode, the input voltage on one selected pin is A/D converted once. Table 14.2 lists the specifications of one-shot mode. Figure 14.4 shows the ADCON0 and ADCON1 registers in one-shot mode. A D c o n t r o l r e g i s t e r 0( S y m b o lA d d r e s sA f t e r r e s e t A D C O N D 6 0 X X b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 A n a l o g i n p u t p i n s e l e c t b i 0 0 0 : A N 0 i s s e l e c t e d A N 1 i s s e l e c t e d A N 2 i s s e l e c t e d A N 3 i s s e l e c t e d A N 4 i s s e l e c t e d A N 5 i s s e l e c t e d A N 6 i s s e l e c t e d A N 7 i s s e l e c t e d C H 0 B i t s y m b o lB i t n a m e Function CH1 CH2 AD operation mode select bit(2) 0 : O n e - s h o t m o d eM D ADST A/D conversion start flag 0 : A/D conversion disabled 1 : A/D conversion started F r e q u e n c y s e l e c t b i t ) 0 : fA D / 4 i s s e l e c t e d fA D / i s s e l e c t e dC K S 0 R W AD control register 1(1) S y m b o l A d d r e s sA f t e r r e s e t A D C O N D 6 0 Bit name FunctionBit symbol b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b b b N O T E S : I f t h e A D C O N r e g i s t e r i s r e w r i t t e n d u r i n g A D c o n v e r s i o n t h e c o n v e r s i o n r e s u l t i s i n d e t e r m i n a t e W h e n c h a n g i n g A D o p e r a t i o n m o d e s e t a n a l o g i n p u t p i n a g a i n T h i s b i t i s v a l i d w h e n t h e C K S b i t i n t h e A D C O N r e g i s t e r i s s e t t o N O T E S : I f t h e A D C O N r e g i s t e r i s r e w r i t t e n d u r i n g A D c o n v e r s i o n t h e c o n v e r s i o n r e s u l t i s i n d e t e r m i n a t e T h e φA D f r e q u e n c y m u s t b e M H z o r l e s s I f t h e V C U T b i t i s r e s e t f r o m V r e f u n c o n n e c t e d t o V r e f c o n n e c t e d w a i t f o r µ s o r m o r e b e f o r e s t a r t i n g A D c o n v e r s i o n B I T S 8/10-bit mode select bit 0 : 8 - b i t m o d e b i t m o d e V C U T Vref connect bit(3) 1 : V r e f c o n n e c t e d Frequency select bit 1(2) C K S 1 Must set to “0” Reserved bit R W R W R W RW R W R W R W R W (b4) Must set to “0”Reserved bit(b5) Must set to “0”R e s e r v e d b i t(b2-b0) R W R W R W R W R W R WMust set to “0”R e s e r v e d b i t ( b 6 - b 7 ) 0 : CKS0 bit in ADCON0 register is valid 1 : fAD is selected Figure 14.4 ADCON0 Register and ADCON1 Registers in One-shot Mode Item Specification Function Input voltage on one pin selected by CH2 to CH0 bits is A/D converted once. Start condition Set ADST bit to “1” Stop condition •Completion of A/D conversion (ADST bit is set to “0”)

• Set ADST bit to “0” Interrupt request generation timingEnd of A/D conversion Input pin One of AN 0 to AN7, as selected Reading of result of A/D converterRead AD register Table 14.2 One-shot Mode Specifications

Rev.1.20 Jan 27, 2006 page 109 of 180 REJ09B0019-0120

14.2 Repeat Mode

In repeat mode, the input voltage on one selected pin is A/D converted repeatedly. Table 14.3 lists the specifications of repeat mode. Figure 14.5 shows the ADCON0 and ADCON1 registers in repeat mode. A D c o n t r o l r e g i s t e r 0( S y m b o lA d d r e s sA f t e r r e s e t A D C O N D 6 0 X X b 7 b 6 b 5 b 4 b 3 b 2 b1 b 0 A n a l o g i n p u t p i n s e l e c t b i 0 0 0 : A N 0 i s s e l e c t e d A N 1 i s s e l e c t e d A N 2 i s s e l e c t e d A N 3 i s s e l e c t e d A N 4 i s s e l e c t e d A N 5 i s s e l e c t e d A N 6 i s s e l e c t e d A N 7 i s s e l e c t e d C H 0 B i t s y m b o lB i t n a m e Function C H 1 CH2 A D o p e r a t i o n m o d e s e l e c t b i 1 : Repeat modeMD A D S T A/D conversion start flag 0 : A/D conversion disabled 1 : A/D conversion started F r e q u e n c y s e l e c t b i t ) 0 : fA D / 4 i s s e l e c t e d fA D / i s s e l e c t e dC K S 0 R W A D c o n t r o l r e g i s t e r 1( S y m b o l A d d r e s sA f t e r r e s e t A D C O N D 6 0 Bit name FunctionBit symbol b 7 b 6 b 5 b 4 b 3 b 2 b1 b 0 b b b N O T E S : I f t h e A D C O N r e g i s t e r i s r e w r i t t e n d u r i n g A D c o n v e r s i o n t h e c o n v e r s i o n r e s u l t i s i n d e t e r m i n a t e W h e n c h a n g i n g A D o p e r a t i o n m o d e s e t a n a l o g i n p u t p i n a g a i n T h i s b i t i s v a l i d w h e n t h e C K S b i t i n t h e A D C O N r e g i s t e r i s s e t t o N O T E S : I f t h e A D C O N r e g i s t e r i s r e w r i t t e n d u r i n g A D c o n v e r s i o n t h e c o n v e r s i o n r e s u l t i s i n d e t e r m i n a t e I n r e p e a t m o d e t h e B I T S b i t m u s t b e s e t t o b i t m o d e T h e φA D f r e q u e n c y m u s t b e M H z o r l e s s I f t h e V C U T b i t i s r e s e t f r o m V r e f u n c o n n e c t e d t o V r e f c o n n e c t e d w a i t f o r µ s o r m o r e b e f o r e s t a r t i n g A D c o n v e r s i o n B I T S 8 / 1 0 - b i t m o d e s e l e c t b i 0 : 8-bit mode V C U T V r e f c o n n e c t b i ) 1 : Vref connected Frequency select bit 1(3) 0 : CKS0 bit in ADCON0 register is valid 1 : fAD is selectedC K S 1 Must set to “0” R e s e r v e d b i t R W R W R W R W R W R W R W R W (b4) Must set to “0”R e s e r v e d b i t ( b 5 ) M u s t s e t t o “ 0 ”Reserved bit ( b 2 - b 0 ) R W R W RW R W R W R WM u s t s e t t o “ 0 ”Reserved bit ( b 6 - b 7 ) 1 0 Figure 14.5 ADCON0 Register and ADCON1 Register in Repeat Mode Item Specification Function Input voltage on one pin selected by CH2 to CH0 bits is A/D converted repeatedly Start condition Set ADST bit to “1” Stop condition Set ADST bit to “0” Interrupt request generation timingNone generated Input pin One of AN 0 to AN7, as selected Reading of result of A/D converterRead AD register Table 14.3 Repeat Mode Specifications

Rev.1.20 Jan 27, 2006 page 110 of 180 REJ09B0019-0120

14.3 Sample and Hold

If the SMP bit in the ADCON2 register is set to “1” (with sample-and-hold), the conversion speed per pin is increased to 28 ØAD cycles for 8-bit resolution or 33 ØAD cycles for 10-bit resolution. Sample- and-hold is effective in all operation modes. Select whether or not to use the sample-and-hold function before starting A/D conversion. When performing the A/D conversion, charge the comparator capacitor inside the microcomputer. Figure 14.6 shows the A/D conversion timing diagram. 14.3 Sample & Hold/14.4 A/D conversion cycles Figure 14.6 A/D Conversion Timing Diagram Sampling time 4φ AD cycle Comparison time Sampling time 2.5φ AD cycle Comparison time Sampling time 2.5φ AD cycle Comparison time * Repeat until conversion ends Conversion time at the 1st bit at the 2nd bitSample & Hold disabled Sample & Hold enabled Conversion time at the 1st bitat the 2nd bit Sampling time 4φ AD cycle Comparison time Comparison time Comparison time * Repeat until conversion ends * Repeat until conversion ends

14.4 A/D conversion cycles

Figure 14.7 shows the A/D conversion cycles. Figure 14.7 A/D Conversion Cycles A/D conversion mode Without sample & hold Without sample & hold With sample & hold With sample & hold 8 bits 10 bits 8 bits 10 bits Conversion time Comparison time Comparison time End processSampling time Sampling time 49 φ AD 59 φ AD 28 φ AD 33 φ AD 2.0 φ AD 2.0 φ AD 2.5 φ AD 2.5 φ AD 2.5 φ AD 2.5 φ AD 2.5 φ AD 2.5 φ AD 8.0 φ AD 8.0 φ AD 4.0 φ AD 4.0 φ AD 4 φ AD 4 φ AD 4 φ AD 4 φ AD 2.5 φ AD 2.5 φ AD 0.0 φ AD 0.0 φ AD End processConversion time at the 2nd bit and the follows Conversion time at the 1st bit

Rev.1.20 Jan 27, 2006 page 111 of 180 REJ09B0019-0120

14.5 Internal Equivalent Circuit of Analog Input

Figure 14.8 shows the internal equivalent circuit of analog input. Figure 14.8 Internal Equivalent Circuit to Analog Input VCC VCC VSS i =10 VSS SW2SW1 AN0 ANi VREF Parasitic diode Parasitic diode ON resistor approx. 2kΩ Wiring resistor approx. 0.2kΩ ON resistor approx. 0.6kΩ ON resistor approx. 0.6kΩ ON resistor approx. 5kΩ Analog input voltage VIN SW1 ON resistor approx. 2kΩ Wiring resistor approx. 0.2kΩ AV CC AMP SW3 Chopper-type amplifier A/D successive conversion register A/D conversion interrupt request SW1 conducts only on the ports selected for analog input. SW2 and SW3 are open when A/D conversion is not in progress; their status varies as shown by the waveforms in the diagrams on the left. SW4 conducts only when A/D conversion is not in progress. Warning: Use only as a standard for designing this data. Mass production may cause some changes in device characteristics. SW4 AV SS C = Approx.1.5pF SW2 Vref Comparison voltage Sampling control signal Reference control signal Comparison reference voltage (Vref) generator Sampling Connect to Connect to Comparison Resistor ladder AV SS Control signal for SW2 A/D control register 0 b1b2 b0 Connect to Connect to Control signal for SW3 i ladder-type switches (i = 10) i ladder-type wiring resistors (i = 10)

Rev.1.20 Jan 27, 2006 page 112 of 180 REJ09B0019-0120

14.6 Inflow Current Bypass Circuit

Figure 14.9 shows the configuration of the inflow current bypass circuit, figure 14.10 shows the ex- ample of an inflow current bypass circuit where V CC or more is applied. Figure 14.9 Configuration of the Inflow Current Bypass Circuit To the internal logic of the A/D Converter OFF ON Unselected channel Fixed to GND level OFF ON OFF Selected channel External input latched into ON Figure 14.10 Example of an Inflow Current Bypass Circuit where VCC or More is Applied To the internal logic of the A/D Converter OFF ON Unselected channel Leakage current generated Unaffected by leakage Leakage current generated OFF ON OFF Selected channelSensor input VCC or more ON

Rev.1.20 Jan 27, 2006 page 113 of 180 REJ09B0019-0120

14.7 Output Impedance of Sensor under A/D Conversion

To carry out A/D conversion properly, charging the internal capacitor C shown in Figure 14.11 has to be completed within a specified period of time. T (sampling time) as the specified time. Let output impedance of sensor equivalent circuit be R0, microcomputer’s internal resistance be R, precision (error) of the A/D converter be X, and the A/D converter’s resolution be Y (Y is 1024 in the 10-bit mode, and 256 in the 8-bit mode). VC is generally VC = VIN {1 – e} And when t = T, VC=VIN – VIN = VIN(1 – ) – T = ln Hence, R0 = –– R Figure 14.11 shows analog input pin and external sensor equivalent circuit. When the difference between VIN and VC becomes 0.1 LSB, we find impedance R0 when voltage between pins VC changes from 0 to VIN – (0.1/1024) VIN in time T. (0.1/1024) means that A/D precision drop due to insufficient capacitor charge is held to 0.1 LSB at time of A/D conversion in the 10-bit mode. Actual error however is the value of absolute precision added to 0.1 LSB. When f(X IN) = 10 MHz, T = 0.25 µs in the A/D conversion mode with sample & hold. Output impedance R0 for sufficiently charging capaci- tor C within time T is determined as follows. R0 = –– 2.8 X 10 3 7.3 X 103 Thus, the allowable output impedance of the sensor circuit capable of thoroughly driving the A/D converter turns out to be approximately 7.3 kΩ . C (R0 +R) Y X Y X Y X Y X C • ln T Y X T C (R0 + R) C (R0 + R)– t

6.0 X 10 –12 • ln

0.1

0.25 X 10 –6

Rev.1.20 Jan 27, 2006 page 114 of 180 REJ09B0019-0120 Figure 14.11 Analog Input Pin and External Sensor Equivalent Circuit R0 R ( 2 . 8 kΩ ) C ( 6 p F ) VIN V C N O T E : Microcomputer S e n s o r e q u i v a l e n t c i r c u i t 1 . T h e c a p a c i t y o f t h e t e r m i n a l i s a s s u m e d t o b e 4 . 5 p F .

R8C/10 Group 15. Programmable I/O Ports Rev.1.20 Jan 27, 2006 page 115 of 180 REJ09B0019-0120 15. Programmable I/O Ports 15. 1 Description The programmable input/output ports (hereafter referred to as “I/O ports”) consist of 22 lines P0, P1, P30 to P33, P37, and P45. Each port can be set for input or output every line by using a direction register, and can also be chosen to be or not be pulled high every 4 lines. The port P1 allows the drive capacity of its N- channel output transistor to be set as necessary. The port P1 can be used as LED drive port if the drive capacity is set to “HIGH ”. 6 and P47 can be used as an input only port if the main clock oscillation circuit is not used. Each pin functions as an I/O port or a peripheral function input/output. For details on how to set peripheral functions, refer to each functional description in this manual. If any pin is used as a peripheral function input, set the direction bit for that pin to “0” (input mode). Any pin used as an output pin for peripheral functions is directed for output no matter how the corresponding direction bit is set.

15.1.1 Port Pi Direction Register (PDi Register, i = 0, 1, 3, 4)

Figure 15.6 shows the PDi register. This register selects whether the I/O port is to be used for input or output. The bits in this register correspond one for one to each port.

15.1.2 Port Pi Register (Pi Register, i = 0 to 4)

Figure 15.7 shows the Pi register. Data I/O to and from external devices are accomplished by reading and writing to the Pi register. The Pi register consists of a port latch to hold the output data and a circuit to read the pin status. For ports set for input mode, the input level of the pin can be read by reading the corresponding Pi register, and data can be written to the port latch by writing to the Pi register. For ports set for output mode, the port latch can be read by reading the corresponding Pi register, and data can be written to the port latch by writing to the Pi register. The data written to the port latch is output from the pin. The bits in the Pi register correspond one for one to each port.

15.1.3 Pull-up Control Register 0, Pull-up Control Register 1 (PUR0 and PUR1 Registers)

Figure 15.8 shows the PUR0 and PUR1 registers. The PUR0 and PUR1 register bits can be used to select whether or not to pull the corresponding port high in 4 bit units. The port chosen to be pulled high has a pull-up resistor connected to it when the direction bit is set for input mode.

15.1.4 Port P1 Drive Capacity Control Register (DRR Register)

Figure 15.8 shows the DRR register. The DRR register is used to control the drive capacity of the port P1 N-channel output transistor. The bits in this register correspond one for one to each port.

R8C/10 Group 15. Programmable I/O Ports Rev.1.20 Jan 27, 2006 page 116 of 180 REJ09B0019-0120 Figure 15.1 Programmable I/O Ports (1) D a t a b u s A / D i n p u t P u l l - u p s e l e c t i o nP 00 t o P 07 Direction register Port latch Data bus P u l l - u p s e l e c t i o n Direction register Port latch P 10 t o P 13 P 15 Select drive capacity "1" Output Data bus P u l l - u p s e l e c t i o n D i r e c t i o n r e g i s t e r Port latch P14 S e l e c t d r i v e c a p a c i t y I n p u t t o r e s p e c t i v e p e r i p h e r a l f u n c t i o n s (Note 1) N O T E S : s y m b o l i z e s a p a r a s i t i c d i o d e M a k e s u r e t h e i n p u t v o l t a g e o n e a c h p i n w i l l n o t e x c e e d V c c (Note 1) (Note 1)

R8C/10 Group 15. Programmable I/O Ports Rev.1.20 Jan 27, 2006 page 117 of 180 REJ09B0019-0120 Figure 15.2 Programmable I/O Ports (2) " 1 " Output P 30 P 31 D a t a b u s Pull-up selection D i r e c t i o n r e g i s t e r P o r t l a t c h P 16 P 17 S e l e c t d r i v e c a p a c i t y Data bus Pull-up selection D i r e c t i o n r e g i s t e r P o r t l a t c h "1" O u t p u t I n p u t t o r e s p e c t i v e p e r i p h e r a l f u n c t i o n s (Note 1) N O T E S : s y m b o l i z e s a p a r a s i t i c d i o d e M a k e s u r e t h e i n p u t v o l t a g e o n e a c h p i n w i l l n o t e x c e e d V c c (Note 1)

R8C/10 Group 15. Programmable I/O Ports Rev.1.20 Jan 27, 2006 page 118 of 180 REJ09B0019-0120 Figure 15.3 Programmable I/O Ports (3) P 45 P 32, P 37 " 1 " Output D a t a b u s P u l l - u p s e l e c t i o n D i r e c t i o n r e g i s t e r P o r t l a t c h P 33 D a t a b u s P u l l - u p s e l e c t i o n D i r e c t i o n r e g i s t e r P o r t l a t c h Data bus Pull-up selection Direction register P o r t l a t c h I n p u t t o r e s p e c t i v e p e r i p h e r a l f u n c t i o n s Digital filterInput to respective peripheral functions I n p u t t o r e s p e c t i v e p e r i p h e r a l f u n c t i o n s Digital filter ( N o t e 1 ) N O T E S : s y m b o l i z e s a p a r a s i t i c d i o d e M a k e s u r e t h e i n p u t v o l t a g e o n e a c h p i n w i l l n o t e x c e e d V c c (Note 1) (Note 1)

R8C/10 Group 15. Programmable I/O Ports Rev.1.20 Jan 27, 2006 page 121 of 180 REJ09B0019-0120 P u l l - u p c o n t r o l r e g i s t e r 0 Symbol Address After reset PUR0 00FC 16 00XX0000 2 Bit name FunctionBit symbol R W b 1b 0 PU00 P0 0 to P03 pull-up(1) PU01 P0 4 to P07 pull-up(1) PU02 P1 0 to P13 pull-up(1) PU06 P3 0 to P33 pull-up(1) PU07 P3 7 pull-up(1) N o t h i n g i s a s s i g n e d . W h e n w r i t e s e t t o W h e n r e a d i t s c o n t e n t i s i n d e t e r m i n a t e .(b5-b4) 0 : N o t p u l l e d u p P u l l e d u p(1 Pull-up control register 1 Symbol Address After reset PUR1 00FD 16 XXXXXX0X 2 Bit name Function Bit symbol b 1b 0 P U p u l l u p(1 N O T E S : T h e p i n f o r w h i c h t h i s b i t i s p u l l e d u p a n d t h e d i r e c t i o n b i t i s i n p u t m o d e i s p u l l e d u p R W RW RW PU03 P1 4 to P17 pull-up(1) R W R W RW RW RW P o r t P 1 d r i v e c a p a c i t y c o n t r o l r e g i s t e r Symbol Address After reset DRR 00FE 16 0016 Bit name FunctionBit symbol b 1b 0 DRR0 P1 0 drive capacity D R R 1P 11 d r i v e c a p a c i t y D R R 2P 12 d r i v e c a p a c i t y D R R 3P 1 3 d r i v e c a p a c i t y D R R 4P 1 4 d r i v e c a p a c i t y D R R 5P 1 5 d r i v e c a p a c i t y 0 : LOW 1 : HIGH R W RW R W R W RW R W R W 0 : Not pulled up 1 : Pulled up(1) 0 : Not pulled up 1 : Pulled up(1) Nothing is assigned. When write, set to “0”. When read, its content is indeterminate.( b 0 ) Nothing is assigned. When write, set to “0”. When read, its content is indeterminate.( b 7 - b 2 ) NOTES: 1. The P45 pin for which the PU11 bit is “1” (pulled up) and the PD4_5 bit is “0” (input mode) is pulled high. D R R 6P 16 d r i v e c a p a c i t y DRR7 P1 7 drive capacity R W R W Set P1 N-channel output transistor drive capacity Figure 15.8 PUR0 Register, PUR1 Register, and DRR Register

R8C/10 Group 15. Programmable I/O Ports Rev.1.20 Jan 27, 2006 page 122 of 180 REJ09B0019-0120 PD0 PD0_1 PUR0 PU00 X ADCON0 CH2, CH1, CH0 XXX XXX 1102 XXX Table 15.1 Port P00/AN7/TXD 11 Setting

15.2 Port setting

Table 15.1 to Table 15.23 list the port setting. Register Bit Setting value PD0 PD0_0 X X PUR0 PU00 X X ADCON0 CH2, CH1, CH0 XXX XXX 1112 XXX XXX XXX UCON TXD1SEL X X X X U1MR SMD2, SMD0 002 XX 002 XX 002 XX 002 XX U1C0 NCH X X X X Function Input port (not pulled up) Input port (pulled up) A/D input (AN7) Output port TXD 11 TXD 11, N-channel open output Table 15.2 Port P01/AN6 Setting Register Bit Setting value Function Input port (not pulled up) Input port (pulled up) A/D input (AN6) Output port PD0 PD0_2 PUR0 PU00 X ADCON0 CH2, CH1, CH0 XXX XXX 1012 XXX Table 15.3 Port P02/AN5 Setting Register Bit Setting value Function Input port (not pulled up) Input port (pulled up) A/D input (AN5) Output port PD0 PD0_3 PUR0 PU00 X ADCON0 CH2, CH1, CH0 XXX XXX 1002 XXX Table 15.4 Port P03/AN4 Setting Register Bit Setting value Function Input port (not pulled up) Input port (pulled up) A/D input (AN4) Output port X: “0” or “1” X: “0” or “1” X: “0” or “1” X: “0” or “1”

R8C/10 Group 15. Programmable I/O Ports Rev.1.20 Jan 27, 2006 page 123 of 180 REJ09B0019-0120 PD0 PD0_4 PUR0 PU01 X ADCON0 CH2, CH1, CH0 XXX XXX 0112 XXX Table 15.5 Port P04/AN3 Setting Register Bit Setting value Function Input port (not pulled up) Input port (pulled up) A/D input (AN3) Output port PD0 PD0_5 PUR0 PU01 X ADCON0 CH2, CH1, CH0 XXX XXX 0102 XXX Table 15.6 Port P05/AN2 setting Register Bit Setting value Function Input port (not pulled up) Input port (pulled up) A/D input (AN2) Output port PD0 PD0_6 PUR0 PU01 X ADCON0 CH2, CH1, CH0 XXX XXX 0012 XXX Table 15.7 Port P06/AN1 Setting Register Bit Setting value Function Input port (not pulled up) Input port (pulled up) A/D input (AN1) Output port PD0 PD0_7 PUR0 PU01 X ADCON0 CH2, CH1, CH0 XXX XXX 0002 XXX Table 15.8 Port P07/AN0 Setting Register Bit Setting value Function Input port (not pulled up) Input port (pulled up) A/D input (AN0) Output port X: “0” or “1” X: “0” or “1” X: “0” or “1” X: “0” or “1”

R8C/10 Group 15. Programmable I/O Ports Rev.1.20 Jan 27, 2006 page 124 of 180 REJ09B0019-0120 Table 15.10 Port P11/KI1 Setting Register Bit Setting value P1_1 X X X X X Function Input port (not pulled up) Input port (pulled up) KI1 input Output port Output port (High drive) Table 15.11 Port P12/KI2 Setting Register Bit Setting value P1_2 X X X X X Function Input port (not pulled up) Input port (pulled up) KI2 input Output port Output port (High drive) Table 15.12 Port P13/KI3 Setting Register Bit Setting value PD1 PD1_3 PUR0 PU02 X X Function Input port (not pulled up) Input port (pulled up) KI3 input Output port Output port (High drive) DRR DRR3 X X X KIEN KI3EN X X X X PD1 PD1_1 PUR0 PU02 X X DRR DRR1 X X X KIEN KI1EN X X X X PD1 PD1_2 PUR0 PU02 X X DRR DRR2 X X X KIEN KI2EN X X X X Table 15.9 Port P10/KI0 Setting Register Bit Setting value PD1 PD1_0 PUR0 PU02 X X P1_0 X X X X X Function Input port (not pulled up) Input port (pulled up) KI0 input Output port Output port (High drive) DRR DRR0 X X X KIEN KI0EN X X X X X: “0” or “1” X: “0” or “1” X: “0” or “1” X: “0” or “1”

R8C/10 Group 15. Programmable I/O Ports Rev.1.20 Jan 27, 2006 page 125 of 180 REJ09B0019-0120 Table 15.13 Port P14/TXD 0 Setting Register Bit Setting value PD1 PD1_4 X X X X PUR0 PU03 X X X X X X U0MR SMD2, SMD0 002 002 002 002 Function Input port (not pulled up) Input port (pulled up) Output port Output port (High drive) TXD 0 output, CMOS output TXD 0 output, CMOS output (High drive) TXD 0 output, N-channel open output TXD 0 output, N-channel open output (High drive) DRR DRR4 X X U0C0 NCH X X X X Table 15.14 Port P15/RXD 0 Setting Register Bit Setting value PD1 PD1_5 PUR0 PU03 X X Function Input port (not pulled up) Input port (pulled up) R XD 0 input Output port Output port (High drive) DRR DRR5 X X X Table 15.15 Port P16/CLK0 Setting Register Bit Setting value PD1 PD1_6 X X PUR0 PU03 X X X X U0MR SMD2, SMD0, CKDIR Other than 0102 Other than 0102 XX1 Other than 0102 Other than 0102 0102 0102 Function Input port (not pulled up) Input port (pulled up) CLK 0 (external clock) input Output port Output port (High drive) CLK 0 (internal clock) output CLK 0 (internal clock) output (High drive) DRR DRR6 X X X X: “0” or “1” X: “0” or “1” X: “0” or “1”

R8C/10 Group 15. Programmable I/O Ports Rev.1.20 Jan 27, 2006 page 126 of 180 REJ09B0019-0120 Table 15.17 Port P30/CNTR 0 Setting Register Bit Setting value PD3 PD3_0 X PUR0 PU06 X X Function Input port (not pulled up) Input port (pulled up) Output port CNTR 0 output TXMR TXOCNT P3_0 X X X X Table 15.18 Port P3 1/TZOUT Setting Register Bit Setting value PD3 PD3_1 X PUR0 PU06 X X Function Input port (not pulled up) Input port (pulled up) Output port TZOUT output TYZMR TZMOD1, TZMOD0 002 012 002 012 002 012 012 P3_1 X X X X TYZOC TZOCNT X X X X Table 15.19 Port P32/INT2/CNTR 1 Setting Register Bit Setting value PD3 PD3_2 X PUR0 PU06 X X Function Input port (not pulled up) Input port (pulled up) CNTR 1/INT2 input Output port CNTR 1 output TYZMR TYMOD1 P3_2 X X X X X TYZOC TZOCNT Table 15.16 Port P17/INT1/CNTR 0 Setting Register Bit Setting value PD1 PD1_7 X X PUR0 PU03 X X X X TXMR TXMOD1, TXMOD0 Other than 012 Other than 012 Other than 012 Other than 012 Other than 012 012 012 Function Input port (not pulled up) Input port (pulled up) CNTR 0/INT1 input Output port Output port (High drive) CNTR 0 output CNTR 0 (High drive) DRR DRR5 X X X X: “0” or “1” X: “0” or “1” X: “0” or “1” X: “0” or “1”

R8C/10 Group 15. Programmable I/O Ports Rev.1.20 Jan 27, 2006 page 127 of 180 REJ09B0019-0120 Table 15.21 Port P37/TXD 10/RXD 1 Setting Register Bit Setting value PD3 PD3_7 X X PUR0 PU07 X X X U1C0 NCH X X X X Function Input port (not pulled up) Input port (pulled up) R XD 1 Output port TXD 0 output, CMOS output TXD 10 output, N-channel open output UCON TXD1EN X X X U1MR SMD2, SMD0 002 002 002 Table 15.22 Port P45/INT0 Setting Register Bit Setting value PD4 PD4_5 PUR1 PU11 X Function Input port (not pulled up) Input port (pulled up) INT0 input Output port INTEN INT0EN X Table 15.23 Port XIN/P46, XOUT /P47 Setting Register Bit Setting value CM1 CM13 CM1 CM10 X Oscillation buffer OFF OFF OFF ON OFF Function XIN-XOUT oscillatoin stop External input to XIN pin, “H ” output from XOUT pin XIN-XOUT oscillatoin stop XIN-XOUT oscillatoin Input port CM0 CM05 X Circuit specification Feedback resistance OFF ON ON ON OFF Table 15.20 Port P33/INT3/TCIN Setting Register Bit Setting value PD3 PD3_3 PUR0 PU06 X Function Input port (not pulled up) Input port (pulled up) TC IN/INT3 input Output port X: “0” or “1” X: “0” or “1” X: “0” or “1” X: “0” or “1”

R8C/10 Group 15. Programmable I/O Ports Rev.1.20 Jan 27, 2006 page 128 of 180 REJ09B0019-0120 P i n n a m eC o n n e c t i o n P o r t s P 0 , P 1 , P 30 t o P 33, P 37, P A VC C , VR E F A VS S C o n n e c t t o VC C C o n n e c t t o VS S N O T E S : W h e n t h e s e p o r t s a r e s e t f o r o u t p u t m o d e a n d l e f t o p e n t h e y r e m a i n i n p u t m o d e u n t i l t h e y a r e s e t f o r o u t p u t m o d e b y a p r o g r a m T h e v o l t a g e l e v e l o f t h e s e p i n s m a y b e u n s t a b l e a n d t h e p o w e r s u p p l y c u r r e n t m a y i n c r e a s e f o r t h e t i m e t h e p o r t s r e m a i n i n p u t m o d e T h e c o n t e n t o f t h e d i r e c t i o n r e g i s t e r s m a y c h a n g e d u e t o n o i s e o r r u n a w a y c a u s e d b y n o i s e I n o r d e r t o e n h a n c e p r o g r a m r e l i a b i l i t y s e t t h e d i r e c t i o n r e g i s t e r s p e r i o d i c a l l y b y a p r o g r a m C o n n e c t t h e s e u n a s s i g n e d p i n s t o t h e m i c r o c o m p u t e r u s i n g t h e s h o r t e s t w i r e l e n g t h w i t h i n c m p o s s i b l e Connect to VCC via resistor (pull-up)(2)P o r t s P 46, P 47

• A f t e r s e t t i n g f o r i n p u t m o d e , c o n n e c t e v e r y p i n t o VS S v i a a r e s i s t o r ( p u l l - d o w n ) o r c o n n e c t e v e r y p i n t o VC C v i a a r e s i s t o r p u l l u p S e t t o o u t p u t m o d e a n d l e a v e t h e s e p i n s o p e n(1 Table 15.24 Unassigned Pin Handling

15.3 Unassigned Pin Handling

Table 15.24 lists the handling of unassigned pins. Figure 15.9 Unassigned Pin Handling Port P0, P1, P30 to P33, P37, P45 Microcomputer (Input mode) (Input mode) (Output mode) Open Port P46, P47 AV CC /VREF AV SS

R8C/10 Group 16. Electrical Characteristics Rev.1.20 Jan 27, 2006 page 129 of 180 REJ09B0019-0120 16. Electrical Characteristics Table 16.1 Absolute Maximum Ratings Operating ambient temperature Parameter Unit Supply voltage Output voltageVO Pd Power dissipation Storage temperature Rated value V V Condition VCC Tstg Topr Symbol mW VCC =AV CC VAV CC V -0.3 to 6.5 -65 to 150 300 -20 to 85 / -40 to 85 (D version) C Topr=25 C Analog supply voltage VCC =AV CC -0.3 to 6.5 VI Input voltage -0.3 to VCC +0.3 -0.3 to VCC +0.3 C Table 16.2 Recommended Operating Conditions 2 . 75 . 5 T y p a x . U n i tP a r a m e t e r VC C S u p p l y v o l t a g e S y m b o l M i n Standard A n a l o g s u p p l y v o l t a g e VC C (3 )A V c c V 0A n a l o g s u p p l y v o l t a g e S u p p l y v o l t a g e VI H V s s A V s s 0 . 8 VC C V VVC C 0 . 2 VC C"L" input voltage " H " i n p u t v o l t a g e V f ( XI N ) M a i n c l o c k i n p u t o s c i l l a t i o n f r e q u e n c y V VIL 1 0 3 . 0 V ≤ V c c ≤ 5 . 5 V 2 . 7 V ≤ V c c < 3 . 0 V M H z M H z NOTES: 1. VCC = AVCC = 2.7 to 5.5V at Topr = -20 to 85 °C / -40 to 85 °C, unless otherwise specified. 2. The typical values when average output current is 100ms. 3. Hold Vcc=AVcc. IOH (sum) " H " p e a k a l l o u t p u t c u r r e n t s Conditions S u m o f a l l p i n s ' I O H p e a k ) -60.0 m A IOH (peak) "H" peak output current - 1 0 . 0 m A IOH (avg) " H " a v e r a g e o u t p u t c u r r e n t - 5 . 0m A IOL (sum) "L" peak all output currents S u m o f a l l p i n s ' I O L p e a k ) 60 mA IOL (peak) "L" peak output current Except P10 to P17 P10 to P17 10 mA Drive capacity HIGH Drive capacity LOW mA mA IO L a v g ) "L" average output current Except P10 to P17 P10 to P17 D r i v e c a p a c i t y H I G H Drive capacity LOW mA mA mA

R8C/10 Group 16. Electrical Characteristics Rev.1.20 Jan 27, 2006 page 130 of 180 REJ09B0019-0120 Table 16.3 A/D Conversion Characteristics Standard M i n .T y p . M a x –R e s o l u t i o n BitVr e f = VC C 1 0 S y m b o lP a r a m e t e rM e a s u r i n g c o n d i t i o nU n i t LSB± 3 R L A D D E R tC O N V L a d d e r r e s i s t a n c e C o n v e r s i o n t i m e R e f e r e n c e v o l t a g e A n a l o g i n p u t v o l t a g e V VI A VR E F VC C ( Vref NOTES: 1. VCC =AV CC =2.7 to 5.5V at Topr = -20 to 85 °C / -40 to 85 °C, unless otherwise specified. 2. If fAD exceeds 10 MHz, divide the fAD and hold A/D operating clock frequency (ØAD) 10 MHz or below. 3. If the AVcc is less than 4.2V, divide the fAD and hold A/D operating clock frequency (ØAD) fAD /2 or below. 4. Hold Vcc=Vref. øAD=10 MHz, Vref=Vcc=5.0V VREF =VCC A b s o l u t e a c c u r a c y– 1 b i t m o d e 8 bit mode ø A D = 1 0 M H z , V r e f = V c c = 5 . 0 V ± 2 L S B b i t m o d e b i t m o d e øAD=10 MHz, Vref=Vcc=3.3V(3) ± 5L S B ø A D M H z V r e f V c c V(3 ) ± 2L S B 1 0 40 kΩ 10 bit mode 8 bit mode ø A D = 1 0 M H z , V r e f = V c c = 5 . 0 V ø A D = 1 0 M H z , V r e f = V c c = 5 . 0 V 3 . 3 2 . 8 µs µs V A D o p e r a t i n g c l o c k f r e q u e n c y(2 Without sample & hold With sample & hold 0 . 2 5 10 MHz 1.0 1 0 MHz Table 16.4 Flash Memory Version Electrical Characteristics B y t e p r o g r a m t i m e B l o c k e r a s e t i m e P r o g r a m E r a s e v o l t a g e R e a d v o l t a g e µs P a r a m e t e r Standard M i n y p a x U n i t N O T E S : VC C A V c c t o V a t T o p r t o C u n l e s s o t h e r w i s e s p e c i f i e d T h e d a t a h o l d t i m e i n c l u d e s t i m e t h a t t h e p o w e r s u p p l y i s o f f o r t h e c l o c k i s n o t s u p p l i e d Measuring conditionS y m b o l P r o g r a m E r a s e t e m p e r a t u r e 2.7 2.7 400 s V V °C– Time delay from suspend request until erase suspend td(SR-ES) Program/erase endurance 8 ms 100 times – D a t a h o l d t i m ) Ambient temperature=55 °C 20 year – E r a s e S u s p e n d R e q u e s t I n t e r v a l 10 m s Table 16.5 Power Circuit Timing Characteristics S y m b o l S t a n d a r d T y p . U n i tMeasuring condition M i n .M a x .Parameter 2000 N O T E S : T h e m e a s u r i n g c o n d i t i o n i s V c c A V c c t o V a n d T o p r C T h i s s h o w s t h e w a i t i n g t i m e u n t i l t h e i n t e r n a l p o w e r s u p p l y g e n e r a t i n g c i r c u i t i s s t a b i l i z e d d u r i n g p o w e r i n g o n T h i s s h o w s t h e t i m e u n t i l B C L K s t a r t s f r o m t h e i n t e r r u p t a c k n o w l e d g e m e n t t o c a n c e l s t o p m o d e 1 5 0td(R-S) S T O P r e l e a s e t i m e(3 µ std(P-R) Time for internal power supply stabilization during powering-on(2) µ s

R8C/10 Group 16. Electrical Characteristics Rev.1.20 Jan 27, 2006 page 132 of 180 REJ09B0019-0120 Table 16.6 Electrical Characteristics (1) [Vcc=5V] Symbol VOH VOL "L" output voltage "H" output voltage Standard Typ. UnitMeasuring condition V V Min. Max. VCC -2.0 Parameter IOH =-5mA V NOTES: 1. Referenced to VCC =AV CC =4.2 to 5.5V at Topr = -20 to 85 °C / -40 to 85 °C, f(XIN)=20MHz unless otherwise specified. VCCExcept XOUT XOUT IOH =-200µA Drive capacity HIGH Drive capacity LOW VCC -0.3 VCC V IOH =-1 mA V CC -2.0 VCC -2.0IOH =-500µA V V VCC VCC Except P10 to P17, XOUT P10 to P17 Drive capacity HIGH Drive capacity LOW IOL = 5 mA IOL = 200 µA IOL = 15 mA IOL = 5 mA 2.0 0.45 V 2.0 V V Hysteresis "H" input currentIIH "L" input currentIIL VRAM RAM retention voltage VT+-VT- 0.2 V µA At stop mode 2.0 VI=5V VI=0V R fXIN Feedback resistance X IN M Ω R PULLUP Pull-up resistance 167 kΩ30 125 XOUT Drive capacity HIGH Drive capacity LOW IOL = 1 mA IOL =500µA 2.0 2.0 V INTo, INT1, INT2, INT3, KI0, KI1, KI2, KI3, CNTR0, CNTR1, TCIN, RxD 0, RxD1, P45 RESET 0.2 1.0 2.2 V V 5.0 -5.0 µA VI=0V 50 1.0 fRING On-chip oscillator frequency 40 250 kHz IOL = 200 µA 0.45 2.0 Drive capacity LOW V

R8C/10 Group 16. Electrical Characteristics Rev.1.20 Jan 27, 2006 page 133 of 180 REJ09B0019-0120 Table 16.7 Electrical Characteristics (2) [Vcc=5V] S y m b o l S t a n d a r d Typ. U n i tM e a s u r i n g c o n d i t i o n M i n .M a x .P a r a m e t e r N o d i v i s i o n m A In single-chip mode, the output pins are open and other pins are V SS 8 1 4 XIN=16 MH z (square wave) mA H i g h - s p e e d m o d e IC C P o w e r s u p p l y c u r r e n t VC C = t o V N O T E S : T i m e r Y i s o p e r a t e d w i t h t i m e r m o d e R e f e r e n c e d t o VC C A VC C t o V a t T o p r t o C t o C f XI N ) M H z u n l e s s o t h e r w i s e s p e c i f i e d W a i t m o d e µA µ A µ A m AMedium-speed mode On-chip oscillator mode W a i t m o d e O n-chip oscillator on=125 kHz XIN=10 MH z (square wave) O n-chip oscillator on=125 kHz N o division XI N = 1 6 M H z ( s q u a r e w a v e ) O n-chip oscillator on=125 kHz Division by 8 XIN=10 MH z (square wave) O n-chip oscillator on=125 kHz Division by 8 2 m A M a i n c l o c k o f f O n - c h i p o s c i l l a t o r o n = 1 2 5 k H z M a i n c l o c k o f f O n-chip oscillator on=125 kHz P e r i p h e r a l c l o c k o p e r a t i o n 4 0 M a i n c l o c k o f f O n-chip oscillator on=125 kHz P e r i p h e r a l c l o c k o f f S t o p m o d e M ain clock off, Topr = 25 °C O n - c h i p o s c i l l a t o r o f f CM 10="1" Peripheral clock off 0.8 3 . 0 Division by 8 470 When a WAIT instruction is executed(1) W h e n a W A I T i n s t r u c t i o n i s e x e c u t e d(1) 9 0 0 7 6 µ A

R8C/10 Group 16. Electrical Characteristics Rev.1.20 Jan 27, 2006 page 134 of 180 REJ09B0019-0120 Timing requirements (Unless otherwise noted: VCC = 5V, VSS = 0V at Topr = 25 °C) [VCC =5V] Table 16.8 XIN input Table 16.9 CNTR0 input, CNTR1 input, INT2 input Table 16.10 TCIN input, INT3 input Table 16.11 Serial Interface Table 16.12 External interrupt INT0 input Symbol tC (XIN) tWH (XIN) tWL (XIN) Parameter XIN input cycle time XIN input HIGH pulse width XIN input LOW pulse width Min. 62.5 Max. Unit ns ns ns Standard Symbol tC (CNTR0 ) tWH (CNTR0 ) tWL (CNTR0 ) Parameter CNTR0 input cycle time CNTR0 input HIGH pulse width CNTR0 input LOW pulse width Min. 100 Max. Unit ns ns ns Standard Symbol tC (TCIN) tWH (TCIN) tWL (TCIN) Parameter TCIN input cycle time TCIN input HIGH pulse width TCIN input LOW pulse width Min. 400(1) 200(2) 200(2) Max. Unit ns ns ns Standard NOTES: 1. When using the Timer C capture function, adjust the cycle time above ( 1/ Timer C count source frequency x 3). 2. When using the Timer C capture function, adjust the pulse width above ( 1/ Timer C count source frequency x 1.5). NOTES: 1. When selecting the digital filter by the INT0 input filter select bit, use the INT0 input HIGH pulse width to the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard.________ ________ 2. When selecting the digital filter by the INT0 input filter select bit, use the INT0 input LOW pusle width to the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard. Symbol tC (CK ) tW (CKH ) tW (CKL ) td(C-Q ) th(C-Q ) tsu(D-C) th(C-D) Parameter CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width TxDi output delay time TxDi hold time RxDi input setup time RxDi input hold time Min. 200 100 100 Max. Unit ns ns ns ns ns ns ns Standard Symbol tW (INH) tW (INL) Parameter INT0 input LOW pulse width Min. 250(1) 250(2) Max. Unit ns ns Standard

R8C/10 Group 16. Electrical Characteristics Rev.1.20 Jan 27, 2006 page 135 of 180 REJ09B0019-0120 Figure 16.3 Vcc=5V timing diagram CLK i TxD i RxD i INTi tW(CKH) tc(CK) tW(CKL) th(C-Q) th(C-D)tsu(D-C)td(C-Q) tW(INL) tW(INH) XIN input tWH(XIN) tc(XIN) tWL(XIN) TCIN input tWH(TCIN) tc(TCIN) tWL(TCIN) CNTR0 input tWH(CNTR0) tc(CNTR0) tWL(CNTR0) VCC = 5V

R8C/10 Group 16. Electrical Characteristics Rev.1.20 Jan 27, 2006 page 136 of 180 REJ09B0019-0120 Table 16.13 Electrical Characteristics (3) [Vcc=3V] S y m b o l VO H VO L " L " o u t p u t v o l t a g e " H " o u t p u t v o l t a g e S t a n d a r d T y p . U n i tMeasuring condition V V V M i n .M a x . VC C -0 P a r a m e t e r IO H =-1m A V H y s t e r e s i s " H " i n p u t c u r r e n tII H " L " i n p u t c u r r e n tII L VR A M R A M r e t e n t i o n v o l t a g e VT -VT - 0 . 2 V µ A At stop mode 2 . 0 VI=3V R f X I N F e e d b a c k r e s i s t a n c e XI N M Ω R P U L L U P P u l l - u p r e s i s t a n c e kΩ66 125 N O T E S : R e f e r e n c e d t o VC C = A VC C =2 t o V a t T o p r t o C t o C f XI N ) M H z u n l e s s o t h e r w i s e s p e c i f i e d VC CE x c e p t XO U T XO U T D r i v e c a p a c i t y H I G H Drive capacity LOW IO H =-0 m AV CC -0.5 VC C -0 5IO H =-50 µ A V V VCC VC C E x c e p t P 10 t o P 17, XO U T P 10 t o P 17 XO U T D r i v e c a p a c i t y H I G H D r i v e c a p a c i t y L O W IO L= 1 m A IOL = 2 mA IO L= 1 m A 0 . 5 V0 . 5 0.5 VDrive capacity HIGH Drive capacity LOW IO L= 0 m A IO L= 5 0 µ A 0 . 5 0 . 5 V R E S E T 0.2 0 . 8 1 . 8 V 4. 0 -4. 0µ AVI= 0 V 160 3. 0 fR I N G O n - c h i p o s c i l l a t o r f r e q u e n c y 40 2 5 0 k H z VI= 0 V 5 0 0 INTo, INT1, INT2, INT3, KI0, KI1, KI2, KI3, CNTR0, CNTR1, TCIN, RxD 0, RxD1, P45

R8C/10 Group 16. Electrical Characteristics Rev.1.20 Jan 27, 2006 page 137 of 180 REJ09B0019-0120 Table 16.14 Electrical Characteristics (4) [Vcc=3V] S y m b o l S t a n d a r d T y p . U n i tM e a s u r i n g c o n d i t i o n M i n .M a x .Parameter N o d i v i s i o n m A I n s i n g l e - c h i p m o d e , t h e o u t p u t p i n s a r e o p e n a n d o t h e r p i n s a r e VS S 71 2 XI N = 1 6 M H z ( s q u a r e w a v e ) m A High-speed mode IC C P o w e r s u p p l y c u r r e n t VC C t o V 420 N O T E S : T i m e r Y i s o p e r a t e d w i t h t i m e r m o d e R e f e r e n c e d t o VC C = A VC C =2 t o V a t T o p r t o C t o C f XI N ) M H z u n l e s s o t h e r w i s e s p e c i f i e d W a i t m o d e µA µ A µA m AM e d i u m - s p e e d m o d e O n - c h i p o s c i l l a t o r m o d e W a i t m o d e O n-chip oscillator on=125 kHz XI N = 1 0 M H z ( s q u a r e w a v e ) O n-chip oscillator on=125 kHz N o division XI N = 1 6 M H z ( s q u a r e w a v e ) O n - c h i p o s c i l l a t o r o n = 1 2 5 k H z D i v i s i o n b y 8 2 . 5 XI N = 1 0 M H z ( s q u a r e w a v e ) O n-chip oscillator on=125 kHz D i v i s i o n b y 8 1 . 6 m A M a i n c l o c k o f f O n - c h i p o s c i l l a t o r o n = 1 2 5 k H z Division by 8 M ain clock off O n - c h i p o s c i l l a t o r o n = 1 2 5 k H z P e r i p h e r a l c l o c k o p e r a t i o n M ain clock off O n - c h i p o s c i l l a t o r o n = 1 2 5 k H z P e r i p h e r a l c l o c k o f f Stop mode M a i n c l o c k o f f, T o p r = 2 5 ° C O n - c h i p o s c i l l a t o r o f f C M 1 0 = " 1 " P e r i p h e r a l c l o c k o f f 0 . 73 . 0 3 7 3 5 W h e n a W A I T i n s t r u c t i o n i s e x e c u t e d(1) W h e n a W A I T i n s t r u c t i o n i s e x e c u t e d(1) 8 0 0 7 4 7 0 µ A

R8C/10 Group 16. Electrical Characteristics Rev.1.20 Jan 27, 2006 page 138 of 180 REJ09B0019-0120 Timing requirements (Unless otherwise noted: VCC = 3V, VSS = 0V at Topr = 25 °C) [VCC =3V] Table 16.15 XIN input Table 16.16 CNTR0 input, CNTR1 input, INT2 input Table 16.17 TCIN input, INT3 input Table 16.18 Serial Interface Table 16.19 External interrupt INT0 input Symbol tC (XIN) tWH (XIN) tWL (XIN) Parameter XIN input cycle time XIN input HIGH pulse width XIN input LOW pulse width Min. 100 Max. Unit ns ns ns Standard Symbol tC (CNTR0 ) tWH (CNTR0 ) tWL (CNTR0 ) Parameter CNTR0 input cycle time CNTR0 input HIGH pulse width CNTR0 input LOW pulse width Min. 300 120 120 Max. Unit ns ns ns Standard Symbol tC (TCIN) tWH (TCIN) tWL (TCIN) Parameter TCIN input cycle time TCIN input HIGH pulse width TCIN input LOW pulse width Min. 1200(1) 600(2) 600(2) Max. Unit ns ns ns Standard NOTES: 1. When using the Timer C capture function, adjust the cycle time above ( 1/ Timer C count source frequency x 3). 2. When using the Timer C capture function, adjust the pulse width above ( 1/ Timer C count source frequency x 1.5). NOTES: 1. When selecting the digital filter by the INT0 input filter select bit, use the INT0 input HIGH pulse width to the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard.________ ________ 2. When selecting the digital filter by the INT0 input filter select bit, use the INT0 input LOW pusle width to the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard. Symbol tC (CK ) tW (CKH ) tW (CKL ) td(C-Q ) th(C-Q ) tsu(D-C) th(C-D) Parameter CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width TxDi output delay time TxDi hold time RxDi input setup time RxDi input hold time Min. 300 150 150 Max. Unit ns ns ns ns ns ns ns Standard 160 Symbol tW (INH) tW (INL) Parameter INT0 input LOW pulse width Min. 380(1) 380(2) Max. Unit ns ns Standard

R8C/10 Group 16. Electrical Characteristics Rev.1.20 Jan 27, 2006 page 139 of 180 REJ09B0019-0120 Figure 16.4 Vcc=3V timing diagram CLK i TxD i RxD i INTi tW(CKH) tc(CK) tW(CKL) th(C-Q) th(C-D)tsu(D-C)td(C-Q) tW(INL) tW(INH) XIN input tWH(XIN) tc(XIN) tWL(XIN) TCIN input tWH(TCIN) tc(TCIN) tWL(TCIN) CNTR0 input tWH(CNTR0) tc(CNTR0) tWL(CNTR0) VCC = 3V

R8C/10 Group 17. Memory Map Rev.1.20 Jan 27, 2006 page 140 of 180 REJ09B0019-0120 Table 17.1 Flash Memory Version Performance 17. Flash Memory Version

17.1 Overview

The flash memory version has two modes— CPU rewrite and standard serial I/O— in which its flash memory can be operated on. Table 17.1 outlines the performance of flash memory version (see “Table 1.1 Performance” for the items not listed on Table 17.1). Item Flash memory operating mode Erase block Method for program Method for erasure Program, erase control method Protect method Number of commands Number of program and erasure ROM code protection Specification 2 modes (CPU rewrite and standard serial I/O) See “Figure 17.1. Flash Memory Block Diagram” In units of byte Block erase Program and erase controlled by software command Blocks 0 and 1 protected by block 0, 1 program enable bit 5 commands 100 times Standard serial I/O mode is supported. Table 17.2 Flash Memory Rewrite Modes Flash memory CPU rewrite mode Standard serial I/O mode rewrite mode Function Areas which User ROM area User ROM area can be rewritten Operation Single chip mode Boot mode mode ROM None Serial programmer programmer User ROM area is rewritten by executing software commands from the CPU. EW0 mode: Can be rewritten in any area other than the flash memory EW1 mode: Can be rewritten in the flash memory User ROM area is rewritten by using a dedicated serial programmer. Standard serial I/O mode 1 : Clock synchronous serial I/O Standard serial I/O mode 2 : UART

1. Flash Memory VersionR8C/10 Group Rev.1.20 Jan 27, 2006 page 141 of 180 REJ09B0019-0120

17.2 Memory Map

The ROM in the flash memory version is separated between a user ROM area and a boot ROM area (reserved area). Figure 17.1 shows the block diagram of flash memory. The user ROM area is divided into several blocks. The user ROM area can be rewritten in CPU rewrite and standard serial I/O modes. Block 1 and Block 0 are enabled for rewrite in CPU rewrite mode by setting the FMR02 bit in the FMR0 register to “1” (rewrite enabled). The rewrite program for standard serial I/O mode is stored in the boot ROM area before shipment. The boot ROM area and the user ROM area share the same address, but have an another memory. Figure 17.1 Flash Memory Block Diagram

8 Kbytes

F F F Boot ROM area (reserved area)(2) NOTES: 1. When setting the FMR02 bit in the FMR0 register to “1” (rewrite enabled) and the FMR15 bit in the FMR1 register to “0” (rewrite enabled), the Block 0 is rewritable. When setting the FMR16 bit to “0” (rewrite enabled), the Block 1 is rewritable (only for CPU rewrite mode). 2. This area is to store the boot program provided by Renesas Technology. B l o c k K b y t e B l o c k K b y t e F F F E U s e r R O M a r e a C D F F E B l o c k K b y t e B l o c k K b y t e F F F U s e r R O M a r e a D D F F E B l o c k K b y t e F F F User ROM area E K b y t e s R O M P r o d u c t K b y t e s R O M P r o d u c t K b y t e s R O M P r o d u c t

Rev.1.20 Jan 27, 2006 page 142 of 180 REJ09B0019-0120

17.3 Functions To Prevent Flash Memory from Rewriting

To prevent the flash memory from being read or rewritten easily, standard serial I/O mode has an ID code check function.

17.3.1 ID Code Check Function

Use this function in standard serial I/O mode. Unless the flash memory is blank, the ID codes sent from the programmer and the ID codes written in the flash memory are compared to see if they match. If the ID codes do not match, the commands sent from the programmer are not accepted. The ID code consists of 8-bit data, the areas of which, beginning with the first byte, are 00FFDF 16, 00FFE316, 00FFEB 16, 00FFEF16, 00FFF316, 00FFF716, and 00FFFB16. Prepare a program in which the ID codes are preset at these addresses and write it in the flash memory. Figure 17.2 Address for ID Code Stored Reset vector Oscillation stop detection/ watchdog timer vector/ Single step vector Address match vector BRK instruction vector Overflow vector Undefined instruction vector ID7 ID6 ID5 ID4 ID3 ID2 ID1 (Reserved) ( R e s e r v e d ) 0 0 F F F F1 6 t o 0 0 F F F C 1 0 0 F F F B1 6 t o 0 0 F F F 81 0 0 F F F 71 6 t o 0 0 F F F 41 0 0 F F F 31 6 t o 0 0 F F F 01 0 0 F F E F1 6 t o 0 0 F F E C 1 0 0 F F E B1 6 t o 0 0 F F E 81 0 0 F F E 71 6 t o 0 0 F F E 41 00FFE3 16 to 00FFE016 00FFDF 16 to 00FFDC16 4 bytes Address (Note 1) N O T E S : W h e n w r i t e t o a d d r e s s F F F w r i t e F

Rev.1.20 Jan 27, 2006 page 143 of 180 REJ09B0019-0120

17.4 CPU Rewrite Mode

In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the CPU. Therefore, the user ROM area can be rewritten directly while the microcomputer is mounted on- board without having to use a ROM programmer, etc. Make sure the Program and the Block Erase commands are executed only on each block in the user ROM area. For interrupts requested during an erase operation in CPU rewrite mode, the R8C/10 flash module offers an \erase-suspend\ feature which allow the erase operation to be suspended, and access made avail- able to the flash. During CPU rewrite mode, the user ROM area be operated on in either Erase Write 0 (EW0) mode or Erase Write 1 (EW1) mode. Table 17.3 lists the differences between Erase Write 0 (EW0) and Erase Write 1 (EW1) modes. Table 17.3 EW0 Mode and EW1 Mode Item EW0 mode EW1 mode Operation mode Single chip mode Single chip mode Areas in which a User ROM area User ROM area rewrite control program can be located Areas in which a Must be transferred to any area other Can be executed directly in the user rewrite control than the flash memory (e.g., RAM) ROM area program can be executed before being executed Areas which can be User ROM area User ROM area rewritten However, this does not include the block in which a rewrite control program exists(1) Software command None • Program, Block Erase command limitations Cannot be executed on any block in which a rewrite control program exists

• Read Status Register command Cannot be executed Modes after Program or Read Status Register mode Read Array mode Erase CPU status during Auto Operating Hold state (I/O ports retain the state in Write and Auto Erase which they were before the command was executed) Flash memory status • Read the FMR0 register FMR00, Read the FMR0 register FMR00, detection FMR06, and FMR07 bits in a FMR06, and FMR07 bits in a program program
• Execute the Read Status Register command to read the status register SR7, SR5, and SR4. Conditions for Set the FMR40 and FMR41 bits in When an interrupt which is set for transferring to the FMR4 register to “1” by program. enabled occurs while the FMR40 bit in erase-suspend the FMR4 register is set to “1”. NOTES: 1. Block 1 and Block 0 are enabled for rewrite by setting the FMR02 bit in the FMR0 register to “1” (rewrite enabled).

Rev.1.20 Jan 27, 2006 page 144 of 180 REJ09B0019-0120

17.4.1 EW0 Mode

The microcomputer is placed in CPU rewrite mode by setting the FMR01 bit in the FMR0 register to “1” (CPU rewrite mode enabled), ready to accept commands. In this case, because the FMR1 register's FMR11 bit = 0, EW0 mode is selected. Use software commands to control program and erase operations. Read the FMR0 register or status register to check the status of program or erase operation at completion. When moving to an erase-suspend during auto-erase, set the FMR40 bit to “1” (erase-suspend en- abled ) and the FMR41 bit to “1” (erase-suspend requested). Make sure that the FMR46 bit is set to “1” (enables reading) before accessing the user ROM space. The auto-erase operation resumes by set- ting the FMR41 bit to “0” (erase restart).

17.4.2 EW1 Mode

EW1 mode is selected by setting FMR11 bit to “1” (EW1 mode) after setting the FMR01 bit to “1” (CPU rewrite mode enabled). Read the FMR0 register to check the status of program or erase operation at completion. Avoid ex- ecuting software commands of Read Status register in EW1 mode. To enable the erase-suspend function, the Block Erase command should be executed after setting the FMR40 bit to “1” (erase-suspend enabled). An interrupt to request an erase-suspend must be in en- abled state. After passing td(SR-ES) since the block erase command is executed, an interrupt request can be acknowledged. The FMR41 bit is automatically set to “1” (erase-suspend requested) if the auto-erase operation is halted by an interrupt request. If the erase operation is not completed (FMR00 bit is “0”) when the interrupt routine is ended, the Block Erase command should be executed again by setting the FMR41 bit to “0” (erase restart).

Rev.1.20 Jan 27, 2006 page 145 of 180 REJ09B0019-0120 Figure 17.3 shows the FMR0 register. Figure 17.4 shows the FMR1 and FMR4 registers.

• FMR00 Bit This bit indicates the operating status of the flash memory. The bit is “0” during programming, eras- ing, or erase-suspend mode; otherwise, the bit is “1”.
• FMR01 Bit The microcomputer is made ready to accept commands by setting the FMR01 bit to “1” (CPU rewrite mode).
• FMR02 Bit The Block1 and Block0 do not accept the Program and Block Erase commands if the FMR02 bit is set to “0” (rewrite disabled).
• FMSTP Bit This bit is provided for initializing the flash memory control circuits, as well as for reducing the amount of current consumed in the flash memory. The flash memory is disabled against access by setting the FMSTP bit to “1”. Therefore, the FMSTP bit must be written to by a program in other than the flash memory. In the following cases, set the FMSTP bit to “1”:
• When flash memory access resulted in an error while erasing or programming in EW0 mode (FMR00 bit not reset to “1” (ready))
• When entering on-chip oscillator mode (main clock stop). Figure 17.6 shows a flow chart to be followed before and after entering on-chip oscillator mode (main clock stop). Note that when going to stop or wait mode while the CPU rewrite mode is disabled, the FMR0 register does not need to be set because the power for the flash memory is automatically turned off and is turned back on again after returning from stop or wait mode.
• FMR06 Bit This is a read-only bit indicating the status of auto program operation. The bit is set to “1” when a program error occurs; otherwise, it is cleared to “0”. For details, refer to the description of the full status check.
• FMR07 Bit This is a read-only bit indicating the status of auto erase operation. The bit is set to “1” when an erase error occurs; otherwise, it is set to “0”. For details, refer to the description of "17.4.5 Full status check".
• FMR11 Bit Setting this bit to “1” (EW1 mode) places the microcomputer in EW1 mode.
• FMR40 bit The erase-suspend function is enabled by setting the FMR40 bit to “1” (valid).
• FMR41 bit In EW0 mode, the flash module goes to erase-suspend mode when the FMR41 bit is set to “1”. In EW1 mode, the FMR41 bit is automatically set to “1” (erase-suspend requested) when an enabled interrupt occurred, and then the flash module goes to erase-suspend mode. The auto-erase operation restarts when the FMR41 bit is set to “0” (erase restart).
• FMR46 bit The FMR46 bit is set to “0”(disables reading) during auto-erase execution and set to “1”(enables reading) during erase-suspend mode. Do not access to the flash memory when this bit is set to “0”.

Rev.1.20 Jan 27, 2006 page 146 of 180 REJ09B0019-0120 Flash memory control register 0 S y m b o lA d d r e s sA f t e r r e s e t F M R B 6 0 b7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 F M R 0 0 B i t s y m b o l B i t n a m eF u n c t i o nR W 0: Busy (being written or erased) 1: Ready CPU rewrite mode select bit(1, 6) 0: Disable CPU rewrite mode 1: Enable CPU rewrite mode F M R 0 1 B l o c k 1 , 0 r e w r i t e e n a b l e b i t(2 0: Rewrite disabled 1: Rewrite enabled F l a s h m e m o r y s t o p b i t(3 F M R 0 2 F M S T P R Y / B Y s t a t u s f l a g Reserved bit Set to “0” 0: Terminated normally 1: Terminated in error Program status flag(4)FMR06 0: Terminated normally 1: Terminated in errorErase status flag(4)FMR07 R W R W R W R W RO RO RO ( b 5 - b 4 ) 0 : E n a b l e f l a s h m e m o r y o p e r a t i o n S t o p f l a s h m e m o r y o p e r a t i o n p l a c e d i n l o w p o w e r m o d e f l a s h m e m o r y i n i t i a l i z e d NOTES: 1. To set this bit to “1”, write “0” and then “1” in succession. Make sure no interrupts will occur before writing “1” after writing “0”. Set the microcomputer in read array mode before writing “0” to this bit. 2. To set this bit to “1”, write “0” and then “1” in succession when the FMR01 bit = 1. Make sure no interrupts will occur before writing “1” after writing “0”. 3. Write to this bit from a program in other than the flash memory. 4. This flag is set to “0” by executing the Clear Status command. 5. Effective when the FMR01 bit = 1 (CPU rewrite mode). If the FMR01 bit = 0, although the FMSTP bit can be set to “1” by writing “1”, the flash memory is neither placed in low power mode nor initialized. 6. Use the bit process instruction to set the FMR01, FMR02 and FMSTP bits (Refer to “R8C/Tiny Series Software Manual”. Figure 17.3 FMR0 Register

Rev.1.20 Jan 27, 2006 page 147 of 180 REJ09B0019-0120 Figure 17.4 FMR1 and FMR4 F l a s h m e m o r y c o n t r o l r e g i s t e r 4 S y m b o lA d d r e s sA f t e r r e s e t F M R B 6 0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 Bit symbol Bit name F u n c t i o n Erase-suspend request bit(2) 0: Erase restart 1: Erase-suspend request FMR41 Erase-suspend function enable bit(1) 0: Invalid 1: Valid R e a d s t a t u s f l a g 0 : D i s a b l e r e a d i n g E n a b l e r e a d i n g RO R W R W R W RW FMR40 FMR46 R e s e r v e d b i t Set to “0”(b7) R e s e r v e d b i t S e t t o “ 0 ” ( b 5 - b 2 ) R O N O T E S T o s e t t h i s b i t t o w r i t e a n d t h e n i n s u c c e s s i o n M a k e s u r e n o i n t e r r u p t s w i l l o c c u r b e f o r e w r i t i n g a f t e r w r i t i n g T h i s b i t i s v a l i d o n l y w h e n t h e F M R b i t i s s e t t o v a l i d a n d c a n o n l y b e w r i t t e n b e f o r e e n d i n g a n e r a s e a f t e r i s s u i n g a n e r a s e c o m m a n d O t h e r t h a n t h i s p e r i o d t h i s b i t i s s e t t o I n E W m o d e t h i s b i t c a n b e s e t t o a n d b y p r o g r a m I n E W m o d e t h i s b i t i s a u t o m a t i c a l l y s e t t o i f a m a s k a b l e i n t e r r u p t o c c u r s d u r i n g a n e r a s e o p e r a t i o n w h i l e t h e F M R b i t i s s e t t o T h i s b i t c a n n o t b e s e t t o b y p r o g r a m C a n b e s e t t o F l a s h m e m o r y c o n t r o l r e g i s t e r 1 S y m b o lA d d r e s sA f t e r r e s e t F M R B 6 0 X X b 7 b 6 b 5 b 4 b3 b 2 b 1 b 0 Bit symbol B i t n a m eF u n c t i o n EW1 mode select bit(1) 0: EW0 mode 1: EW1 mode F M R 1 1 R e s e r v e d b i t Set to “0” Reserved bit W h e n r e a d , i t s c o n t e n t i s i n d e t e r m i n a t e R e s e r v e d b i t Set to “0” R W R O R W RW R W ( b 0 ) ( b 5 - b 4 ) (b7) Reserved bit When read, its content is indeterminate.( b 3 - b 2 ) R O N O T E S : T o s e t t h i s b i t t o w r i t e a n d t h e n i n s u c c e s s i o n w h e n t h e F M R b i t M a k e s u r e n o i n t e r r u p t s w i l l o c c u r b e f o r e w r i t i n g a f t e r w r i t i n g T h e F M R a n d F M R b i t s b o t h a r e s e t t o b y s e t t i n g t h e F M R b i t t o N o t h i n g i s a s s i g n e d . W h e n w r i t e s e t t o .( b 6 )

Rev.1.20 Jan 27, 2006 page 148 of 180 REJ09B0019-0120 Figure 17.7 Setting and Resetting of EW1 Mode S e t C M a n d C M r e g i s t e r s(1 ) S e t t h e F M R b i t b y w r i t i n g a n d t h e n C P U r e w r i t e m o d e e n a b l e d )(2 S e t t h e F M R b i t b y w r i t i n g a n d t h e n E W m o d e P r o g r a m i n R O M E W 1 m o d e o p e r a t i o n p r o c e d u r e E x e c u t e s o f t w a r e c o m m a n d s W r i t e t o t h e F M R b i t C P U r e w r i t e m o d e d i s a b l e d N O T E S S e l e c t M H z o r l e s s f o r C P U c l o c k u s i n g t h e C M b i t i n t h e C M r e g i s t e r a n d t h e C M t o C M b i t s i n t h e C M r e g i s t e r T o s e t t h e F M R b i t t o w r i t e a n d t h e n i n s u c c e s s i o n M a k e s u r e n o i n t e r r u p t s w i l l o c c u r b e f o r e w r i t i n g a f t e r w r i t i n g Execute the Read Array command(3) S e t C M a n d C M r e g i s t e r s( 1 ) E x e c u t e s o f t w a r e c o m m a n d s J u m p t o t h e r e w r i t e c o n t r o l p r o g r a m w h i c h h a s b e e n t r a n s f e r r e d t o a n y a r e a o t h e r t h a n t h e f l a s h m e m o r y T h e s u b s e q u e n t p r o c e s s i n g i s e x e c u t e d b y t h e r e w r i t e c o n t r o l p r o g r a m i n a n y a r e a o t h e r t h a n t h e f l a s h m e m o r y Transfer a CPU rewrite mode based rewrite control program to any area other than the flash memory W r i t e “ 0 ” t o t h e F M R 0 1 b i t C P U r e w r i t e m o d e d i s a b l e d S e t t h e F M R 0 1 b i t b y w r i t i n g “ 0 ” a n d t h e n “ 1 ” C P U r e w r i t e m o d e e n a b l e d )(2 EW0 mode operation procedure R e w r i t e c o n t r o l p r o g r a m Jump to a specified address in the flash memory N O T E S : S e l e c t M H z o r l e s s f o r C P U c l o c k u s i n g t h e C M b i t i n t h e C M r e g i s t e r a n d t h e C M t o C M b i t s i n t h e C M r e g i s t e r T o s e t t h e F M R b i t t o w r i t e a n d t h e n i n s u c c e s s i o n M a k e s u r e n o i n t e r r u p t s w i l l o c c u r b e f o r e w r i t i n g a f t e r w r i t i n g W r i t e t o t h e F M R b i t f r o m a p r o g r a m i n o t h e r t h a n t h e f l a s h m e m o r y D i s a b l e s t h e C P U r e w r i t e m o d e a f t e r e x e c u t i n g t h e R e a d A r r a y c o m m a n d Figure 17.6 Setting and Resetting of EW0 Mode Figures 17.6 and 17.7 show the setting and resetting of EW0 mode and EW1 mode, respectively. Check that the FMR00 bit is set to “0”, and that the erase operation has not ended. Check the status, and that the program ends normally. Erase Ends During Erase Figures 17.5 shows the timing on suspend operation. Figure 17.5 Timing on Suspend Operation

Rev.1.20 Jan 27, 2006 page 149 of 180 REJ09B0019-0120 Figure 17.8 Process to Reduce Power Consumption in On-Chip Oscillator Mode (Main Clock Stop) T u r n m a i n c l o c k o n T r a n s f e r a n o n c h i p o s c i l l a t o r m o d e m a i n c l o c k s t o p p r o g r a m t o a n y a r e a o t h e r t h e f l a s h m e m o r y S w i t c h t h e c l o c k s o u r c e f o r C P U c l o c k T u r n XI N o f f J u m p t o t h e o n c h i p o s c i l l a t o r m o d e m a i n c l o c k s t o p p r o g r a m w h i c h h a s b e e n t r a n s f e r r e d t o a n y a r e a o t h e r t h e f l a s h m e m o r y T h e s u b s e q u e n t p r o c e s s i n g i s e x e c u t e d b y a p r o g r a m i n a n y a r e a o t h e r t h a n t h e f l a s h m e m o r y W a i t u n t i l t h e f l a s h m e m o r y c i r c u i t s t a b i l i z e s µs )(3 S e t t h e F M S T P b i t t o f l a s h m e m o r y o p e r a t i o n )(4 ) S e t t h e F M S T P b i t t o f l a s h m e m o r y s t o p p e d L o w p o w e r s t a t e )(1 P r o c e s s o f o n c h i p o s c i l l a t o r m o d e m a i n c l o c k s t o p s w i t c h t h e c l o c k s o u r c e f o r C P U c l o c k(2 ) O n c h i p o s c i l l a t o r m o d e m a i n c l o c k s t o p p r o g r a m W r i t e t o t h e F M R b i t C P U r e w r i t e m o d e d i s a b l e d S e t t h e F M R b i t b y w r i t i n g a n d t h e n C P U r e w r i t e m o d e e n a b l e d J u m p t o a s p e c i f i e d a d d r e s s i n t h e f l a s h m e m o r y w a i t u n t i l o s c i l l a t i o n s t a b i l i z e s N O T E S S e t t h e F M R b i t t o C P U r e w r i t e m o d e b e f o r e s e t t i n g t h e F M S T P b i t t o B e f o r e t h e c l o c k s o u r c e f o r C P U c l o c k c a n b e c h a n g e d t h e c l o c k t o w h i c h t o b e c h a n g e d m u s t b e s t a b l e I n s e r t a µ s w a i t t i m e i n a p r o g r a m A v o i d a c c e s s i n g t o t h e f l a s h m e m o r y d u r i n g t h i s w a i t t i m e E n s u r e µ s u n t i l s e t t i n g f l a s h m e m o r y o p e r a t e s a f t e r s e t t i n g t h e F M S T P b i t t o f l a s h m e m o r y s t o p s

Rev.1.20 Jan 27, 2006 page 150 of 180 REJ09B0019-0120

17.4.3 Software Commands

Software commands are described below. The command code and data must be read and written in 8-bit units. Table 17.4 Software Commands

• Read Array Command This command reads the flash memory. Writing ‘FF 16’ in the first bus cycle places the microcomputer in read array mode. Enter the read address in the next or subsequent bus cycles, and the content of the specified address can be read in 8-bit units. Because the microcomputer remains in read array mode until another command is written, the con- tents of multiple addresses can be read in succession.
• Read Status Register Command This command reads the status register. Write ‘70 16’ in the first bus cycle, and the status register can be read in the second bus cycle. (Refer to Section 17.4.4, “Status Register.”) When reading the status register too, specify an address in the user ROM area. Avoid executing this command in EW1 mode.
• Clear Status Register Command This command sets the status register to “0”. Write ‘50 16’ in the first bus cycle, and the FMR06 to FMR07 bits in the FMR0 register and SR4 to SR5 in the status register will be set to “0”. Command Program Clear status register Read array Read status register First bus cycle Second bus cycle Block erase Write Write Write Write Write Mode Read Write Write Mode X WA BA Address SRD WD D0 16 Data (D7 to D0) FF16 7016 5016 4016 2016 Data (D7 to D0) X X X WA X Address SRD: Status register data (D7 to D0) WA: Write address (Make sure the address value specified in the the first bus cycle is the same address as the write address specified in the second bus cycle.) WD: Write data (8 bits) BA: Given block address X: Any address in the user ROM area

Rev.1.20 Jan 27, 2006 page 151 of 180 REJ09B0019-0120 Start Program completed YES NO Write the command code ‘4016’ to the write address Write data to the write address FMR00=1? Full status check Figure 17.9 Program Flow Chart

• Program This command writes data to the flash memory in one byte units. Write ‘40 16’ in the first bus cycle and write data to the write address in the second bus cycle, and an auto program operation (data program and verify) will start. Make sure the address value specified in the first bus cycle is the same address as the write address specified in the second bus cycle. Check the FMR00 bit in the FMR0 register to see if auto programming has finished. The FMR00 bit is “0” during auto programming and set to “1” when auto programming is completed. Check the FMR06 bit in the FMR0 register after auto programming has finished, and the result of auto programming can be known. (Refer to Section 17.4.5, “Full Status Check.”) Writing over already programmed addresses is inhibited. When the FMR02 bit in the FMR0 register is set to “0” (rewrite disabled), the Program command on the Block0 and Block1 is not accepted. In EW1 mode, do not execute this command on any address at which the rewrite control program is located. In EW0 mode, the microcomputer goes to read status register mode at the same time auto program- ming starts, making it possible to read the status register. The status register bit 7 (SR7) is set to “0” at the same time auto programming starts, and set back to “1” when auto programming finishes. In this case, the microcomputer remains in read status register mode until a read array command is written next. The result of auto programming can be known by reading the status register after auto programming has finished.

Rev.1.20 Jan 27, 2006 page 152 of 180 REJ09B0019-0120 Write ‘D0 16’ to the given block address Start Block erase completed YES NO Write the command code ‘2016’ FMR00=1? Full status check Figure 17.10 Block Erase Flow Chart (When Not Using Erase-suspend Function)

• Block Erase Write ‘2016’ in the first bus cycle and write ‘D0 16’ to the given address of a block in the second bus cycle, and an auto erase operation (erase and verify) will start. Check the FMR00 bit in the FMR0 register to see if auto erasing has finished. The FMR00 bit is “0” during auto erasing and set to “1” when auto erasing is completed. Check the FMR07 bit in the FMR0 register after auto erasing has finished, and the result of auto erasing can be known. (Refer to Section 17.4.5, “Full Status Check.”) When the FMR02 bit in the FMR0 register is set to “0” (rewrite disabled), the Block Erase command on the Block0 and Block1 is not accepted. Figure 17.10 shows an example of a block erase flowchart when the erase-suspend function is not used. Figure 17.11 shows an example of a block erase flowchart when the erase-suspend function is used. In EW1 mode, do not execute this command on any address at which the rewrite control program is located. In EW0 mode, the microcomputer goes to read status register mode at the same time auto erasing starts, making it possible to read the status register. The status register bit 7 (SR7) is cleared to “0” at the same time auto erasing starts, and set back to “1” when auto erasing finishes. In this case, the microcomputer remains in read status register mode until the Read Array command is written next.

Rev.1.20 Jan 27, 2006 page 153 of 180 REJ09B0019-0120 Figure 17.11 Block Erase Command (When Using Erase-suspend Function) Write ‘D0 16’ to the any block address S t a r t Block erase completed Y E S N O W r i t e t h e c o m m a n d c o d e ‘ 2 01 F M R 0 0 = 1 ? Full status check Interrupt(1, 2) REIT Y E S NO F M R 4 6 = 1 ? A c c e s s t o f l a s h m e m o r y F M R 4 0 = 1 FMR40=1 FMR41=0 < E W 0 M o d e > Write ‘D0 16’ to the any block address S t a r t W r i t e t h e c o m m a n d c o d e ‘ 2 01 Block erase completed YES N O FMR00=1? Full status check Interrupt(2) R E I T Access to flash memoryFMR40=1 E W 1 M o d e FMR41=0 N O T E S : I n E W m o d e i n t e r r u p t v e c t o r t a b l e f o r a n i n t e r r u p t u s e d s h o u l d b e l o c a t e d i n t h e R A M s p a c e t d S R E S i s n e e d e d a f t e r a n i n t e r r u p t r e q u e s t i s g e n e r a t e d b e f o r e b e i n g a c k n o w l e d g e d T h e i n t e r r u p t t o e n t e r a n e r a s e s u s p e n d s h o u l d b e i n i n t e r r u p t e n a b l e d s t a t u s

Rev.1.20 Jan 27, 2006 page 154 of 180 REJ09B0019-0120

17.4.4 Status Register

The status register indicates the operating status of the flash memory and whether an erase or pro- gramming operation terminated normally or in error. The status of the status register can be known by reading the FMR00, FMR06, and FMR07 bits in the FMR0 register. Table 17.5 lists the status register. In EW0 mode, the status register can be read in the following cases: (1) When a given address in the user ROM area is read after writing the Read Status Register com- mand (2) When a given address in the user ROM area is read after executing the Program or Block Erase command but before executing the Read Array command.

• Sequence Status (SR7 and FMR00 Bits ) The sequence status indicates the operating status of the flash memory. SR7 = 0 (busy) during auto programming and auto erase, and is set to “1” (ready) at the same time the operation finishes.
• Erase Status (SR5 and FMR07 Bits) Refer to Section 17.4.5, “Full Status Check.”
• Program Status (SR4 and FMR06 Bits) Refer to Section 17.4.5, “Full Status Check.” Table 17.5 Status Register Status register bit SR4 (D4) SR5 (D5) SR7 (D7) SR6 (D6) Status name Contents SR1 (D1) SR2 (D2) SR3 (D3) SR0 (D0) Program status Erase status Sequencer status Reserved Reserved Reserved Reserved "1" Ready Terminated in error Terminated in error "0" Busy Terminated normally Terminated normally -Reserved FMR0 register bit FMR00 FMR07 FMR06 Value after reset
• D7 to D0: Indicates the data bus which is read out when the Read Status Register command is executed.
• The FMR07 bit (SR5) and FMR06 bit (SR4) are set to “0” by executing the Clear Status Register com- mand.
• When the FMR07 bit (SR5) or FMR06 bit (SR4) = 1, the Program and Block Erase commands are not accepted.

Rev.1.20 Jan 27, 2006 page 155 of 180 REJ09B0019-0120

17.4.5 Full Status Check

When an error occurs, the FMR06 to FMR07 bits in the FMR0 register are set to “1”, indicating occur- rence of each specific error. Therefore, execution results can be verified by checking these status bits (full status check). Table 17.6 lists errors and FMR0 register status. Figure 17.12 shows a full status check flowchart and the action to be taken when each error occurs. Table 17.6 Errors and FMR0 Register Status FRM00 register (status register) status Error Error occurrence condition FMR07 FMR06 (SR5) (SR4) 1 1 Command • When any command is not written correctly sequence error• When invalid data was written other than those that can be writ- ten in the second bus cycle of the Block Erase command (i.e., other than ‘D0 16’ or ‘FF16’)(1)

• When executing the program command or block erase command while rewriting is disabled using the FMR02 bit in the FMR0 regis- ter, the FMR15 or FMR16 bit in the FMR1 register.
• When inputting and erasing the address in which the Flash memory is not allocated during the erase command input.
• When executing to erase the block which disables rewriting dur- ing the erase command input.
• When inputting and writing the address in which the Flash memory is not allocated during the write command input.
• When executing to write the block which disables rewriting during the write command input. 1 0 Erase error • When the Block Erase command was executed but not automati- cally erased correctly 0 1 Program error • When the Program command was executed but not automatically programmed correctly. NOTES: 1. Writing ‘FF 16’ in the second bus cycle of these commands places the microcomputer in read array mode, and the command code written in the first bus cycle is nullified.

Rev.1.20 Jan 27, 2006 page 156 of 180 REJ09B0019-0120 F u l l s t a t u s c h e c k F M R 0 6 = 1 a n d F M R N o Y e s FMR07=0? N o Y e s N O T E S T o r e w r i t e t o t h e a d d r e s s w h e r e t h e p r o g r a m e r r o r o c c u r s c h e c k i f t h e f u l l s t a t u s c h e c k i s c o m p l e t e n o r m a l l y a n d w r i t e t o t h e a d d r e s s a f t e r t h e b l o c k e r a s e c o m m a n d i s e x e c u t e d FMR06=0? N o Y e s Full status check completed C o m m a n d s e q u e n c e e r r o r E r a s e e r r o r P r o g r a m e r r o r C o m m a n d s e q u e n c e e r r o r E r a s e e r r o r E x e c u t e t h e c l e a r s t a t u s r e g i s t e r c o m m a n d s e t t h e s e s t a t u s f l a g s t o C h e c k i f c o m m a n d i s p r o p e r l y i n p u t R e - e x e c u t e t h e c o m m a n d Execute the clear status register command (set these status flags to 0) Erase command re-execution times ≤ 3 times? No Block targeting for erasure cannot be used Re-execute block erase command Program error E x e c u t e t h e c l e a r s t a t u s r e g i s t e r c o m m a n d s e t t h e s e s t a t u s f l a g s t o Specify the other address besides the write address where the error occurs for the program address (1) Re-execute program command Yes Figure 17.12 Full Status Check and Handling Procedure for Each Error

R8C/10 Group 17.5 Standard Serial I/O Mode Rev.1.20 Jan 27, 2006 page 157 of 180 REJ09B0019-0120

17.5 Standard Serial I/O Mode

In standard serial I/O mode, the user ROM area can be rewritten while the microcomputer is mounted on- board by using a serial programmer suitable for this microcomputer. Standard serial I/O mode has stan- dard serial I/O mode 1 of the clock synchronous serial and standard serial I/O mode 2 of the clock asynchronous serial. Refer to "Appendix 2 Connecting Examples for Serial Writer and On-chip Debug- ging Emulator". For more information about serial programmers, contact the manufacturer of your serial programmer. For details on how to use, refer to the user’s manual included with your serial programmer. Table 17.7 lists pin functions (flash memory standard serial input/output mode). Figures 17.13 to 17.15 show pin connections for standard serial I/O mode.

17.5.1 ID Code Check Function

This function determines whether the ID codes sent from the serial programmer and those written in the flash memory match (refer to Section 17.3, “Functions to Prevent Flash Memory from Rewriting”).

R8C/10 Group 17.5 Standard Serial I/O Mode Rev.1.20 Jan 27, 2006 page 158 of 180 REJ09B0019-0120 P i n Description VC C , VS S A p p l y t h e v o l t a g e g u a r a n t e e d f o r P r o g r a m a n d E r a s e t o V c c p i n a n d V t o V s s p i n IVCC Connect capacitor (0.1 µF) to Vss. R E S E T P 46/ XI N Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins in standard serial I/O mode 2. When using the main clock in standard serial I/O mode 1, connect a ceramic resonator or crystal oscillator between XIN and XOUT pins. When not using the main clock in standard serial I/O mode 1, connect this pin to Vcc via a resistor (pull-up). P 47/ XO U T A VC C , A VS S VR E F Connect AVss to Vss and AVcc to Vcc, respectively. Enter the reference voltage for AD from this pin. P t o P 07 Input "H" or "L" level signal or open. P t o P 17 Input "H" or "L" level signal or open. P30 to P33 Input "H" or "L" level signal or open. P 45 Input "H" or "L" level signal or open. P

00 Serial data output pin

M O D E C N VS S Standard serial I/O mode 1: connect to flash programmer Standard serial I/O mode 2: Input "L". P37 Serial data input pin N a m e P o w e r i n p u t IVCC R e s e t i n p u t P i n p u t C l o c k i n p u t P i n p u t C l o c k o u t p u t A n a l o g p o w e r s u p p l y i n p u t R e f e r e n c e v o l t a g e i n p u t I n p u t p o r t P I n p u t p o r t P Input port P3 I n p u t p o r t P T x D o u t p u t M O D E C N V S S RxD input I/O I I I/O I I I I I O I/O I O I S t a n d a r d s e r i a l I O m o d e c o n n e c t t o f l a s h p r o g r a m m e r S t a n d a r d s e r i a l I O m o d e I n p u t L Reset input pin. I Table 17.7 Pin Functions (Flash Memory Standard Serial I/O Mode)

R8C/10 Group 17.5 Standard Serial I/O Mode Rev.1.20 Jan 27, 2006 page 159 of 180 REJ09B0019-0120 Figure 17.13 Pin Connections for Standard Serial I/O Mode Connect oscillator circuit(1) 1 2 3 4 5 6 7 8 1 0 1 1 1 2 1 3 1 4 1 5 1 6 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 3 2 3 1 3 0 R8C/10 Vcc V s s R x D C N V s s R E S E T T x D M O D E NOTES: 1. No need to connect an oscillation circuit when operating with on-chip oscillator clock. CNVss Vss -->VccR E S E T M O D E RxD Mode Setting S i g n a l V a l u e Voltage from programmer Voltage from programmer V o l t a g e f r o m p r o g r a m m e r

R8C/11 Group 18. On-chip Debugger Rev.1.20 Jan 27, 2006 page 161 of 180 REJ09B0019-0120 18. On-chip debugger The microcomputer has functions to execute the on-chip debugger. Refer to "Appendix 2 Connecting examples for serial writer and on-chip debugging emulator". Refer to the respective on-chip debugger manual for the details of the on-chip debugger. Next, here are some explanations for the respective functions. Debugging the user system which uses these functions is not available. When using the on- chip debugger, design the system without using these functions in advance. Additionally, the on-chip debugger uses the address 0C000 16 to 0C7FF16 of the flash memory, thus avoid using for the user system.

18.1 Address match interrupt

The interrupt request is generated right before the arbitrary address instruction is executed. The debugger break function uses the address match interrupt. Refer to "10.4 Address match interrupt" for the details of the address match interrupt. Also, avoid setting the address match interrupt (the registers of AIER, RMAD0, RMAD1 and the fixed vector tables) with using the user system when using the on-chip debugger.

18.2 Single step interrupt

The interrupt request is generated every time one instruction is executed. The debugger single step function uses the single step interrupt. The other interrupt is not generated when using the single step interrupt. The single step interrupt is only for the developed support tool.

18.3 UART1

The UART1 is used for the communication with the debugger (or the personal computer). Refer to "13. Serial Interface" for the details of UART1. Also, avoid using the UART1 and the functions (P0 0/AN7 and P37) which share the UART1 pins.

18.4 BRK instruction

The BRK interrupt request is generated. Refer to "10.1 Interrupt overview" and "R8C/Tiny series soft- ware manual". Also, avoid using the BRK instruction with using the user system when using the on-chip debugger.

R8C/10 Group 19. Usage Notes Rev.1.20 Jan 27, 2006 page 162 of 180 REJ09B0019-0120 19. Usage Notes

19.1 Stop Mode and Wait Mode

19.1.1 Stop Mode

When entering stop mode, set the CM10 bit to “1” (stop mode) after setting the FMR01 bit to “0” (CPU rewrite mode disabled). The instruction queue pre-reads 4 bytes from the instruction which sets the CM10 bit in the CM1 register to “1” (stop mode) and the program stops. Insert at least 4 NOP instruc- tions after inserting the JMP.B instruction immediately after the instruction which sets the CM10 bit to “1”. Use the next program to enter stop mode.

• Program of entering stop mode BCLR 1, FMR0 ; CPU rewrite mode disabled BSET 0, PRCR ; Protect exited BSET 0, CM1 ; Stop mode JMP.B LABEL_001 LABEL_001: NOP NOP NOP NOP

19.1.2 Wait Mode

When entering wait mode, execute the WAIT instruction after setting the FMR01 bit to “0” (CPU re- write mode disabled). The instruction queue pre-reads 4 bytes from the WAIT instruction and the program stops. Insert at least 4 NOP instructions after the WAIT instruction. Also, the value in the specific internal RAM area may be rewritten when exiting wait mode if writing to the interna RAM area before executing the WAIT instruction and entering wait mode. The area for a maximum of 3 bytes is rewirtten from the following address of the internal RAM in which the writing is performed before the WAIT instruction. If this causes a problem, avoid by inserting the JMP.B instruc- tion between the writing instruction to the internal RAM area and WAIT instruction as shown in the following program example.

• Example to execute WAIT instruction Program Example MOV.B #055h,0601h ; Write to internal RAM area
• •• JMP.B LABEL_001 LABEL_001 : FSET I ; Interrupt enabled BCLR 1,FMR0 ; CPU rewrite mode disabled WAIT ; Wait mode NOP NOP NOP NOP When accessing any area other than the internal RAM area between the writing instruction to the internal RAM area and execution of the WAIT instruction, this situation will not occur.

R8C/10 Group 19. Usage Notes Rev.1.20 Jan 27, 2006 page 163 of 180 REJ09B0019-0120

19.2 Interrupt

19.2.1 Reading Address 0000016

Do not read the address 0000016 by a program. When a maskable interrupt request is acknowledged, the CPU reads interrupt information (interrupt number and interrupt request level) from 0000016 in the interrupt sequence. At this time, the acknowledged interrupt IR bit is set to “0”. If the address 0000016 is read by a program, the IR bit for the interrupt which has the highest priority among the enabled interrupts is set to “0”. This may cause a problem that the interrupt is canceled, or an unexpected interrupt is generated.

19.2.2 SP Setting

Set any value in the SP before an interrupt is acknowledged. The SP is set to “000016” after reset. Therefore, if an interrupt is acknowledged before setting any value in the SP, the program may run out of control.

19.2.3 External Interrupt and Key Input Interrupt

Either an “L” level or an ”H ” level of at least 250ns width is necessary for the signal input to the INT0 to INT3 pins and KI0 to KI3 pins regardless of the CPU clock.

19.2.4 Watchdog Timer Interrupt

Reset the watchdog timer after a watchdog timer interrupt is generated.

R8C/10 Group 19. Usage Notes Rev.1.20 Jan 27, 2006 page 164 of 180 REJ09B0019-0120 Figure 19.1 Example of Procedure for Changing Interrupt Factor D i s a b l e I n t e r r u p t(2 , 3 ) C h a n g e i n t e r r u p t f a c t o r ( i n c l u d i n g m o d e o f p e r i p h e r a l f u n c t i o n s E n a b l e i n t e r r u p t(2 , 3 ) I n t e r r u p t f a c t o r c h a n g e Change completed

• I R b i t : T h e i n t e r r u p t c o n t r o l r e g i s t e r b i t o f a n i n t e r r u p t w h o s e f a c t o r i s c h a n g e d N O T E S E x e c u t e t h e a b o v e s e t t i n g i n d i v i d u a l l y D o n o t e x e c u t e t w o o r m o r e s e t t i n g s a t o n c e b y o n e i n s t r u c t i o n U s e t h e I f l a g f o r t h e I N T i i t o i n t e r r u p t T o p r e v e n t i n t e r r u p t r e q u e s t s f r o m b e i n g g e n e r a t e d w h e n u s i n g p e r i p h e r a l f u n c t i o n i n t e r r u p t s o t h e r t h a n t h e I N T i i n t e r r u p t f a c t o r I n t h i s c a s e u s e t h e I f l a g w h e n a l l m a s k a b l e i n t e r r u p t s c a n b e d i s a b l e d W h e n a l l m a s k a b l e i n t e r r u p t s c a n n o t b e d i s a b l e d u s e t h e I L V L t o I L V L b i t s o f t h e i n t e r r u p t w h o s e f a c t o r i s c h a n g e d R e f e r t o C h a n g i n g I n t e r r u p t C o n t r o l R e g i s t e r f o r t h e i n s t r u c t i o n s t o b e u s e d a n d t h e i r u s a g e n o t e s S e t I R b i t t o “ 0 ” ( i n t e r r u p t n o t r e q u e s t e d ) u s i n g M O V i n s t r u c t i o n(3

19.2.5 Changing Interrupt Factor

The IR bit in the interrupt control register may be set to “1” (interrupt requested) when the interrupt factor is changed. When using an interrupt, set the IR bit to “0” (interrupt not request) after changing the interrupt factor. In addition, the changes of interrupt factors include all elements that change the interrupt factors assigned to individual software interrupt numbers, polarities, and timing. Therefore, when a mode change of the peripheral functions involves interrupt factors, edge polarities, and timing, set the IR bit to “0” (interrupt not requested) after the change. Refer to each peripheral function for the interrupts caused by the peripheral functions. Figure 19.1 shows an Example of Procedure for Changing Interrupt Factor.

R8C/10 Group 19. Usage Notes Rev.1.20 Jan 27, 2006 page 165 of 180 REJ09B0019-0120 Example 1: Use NOP instructions to prevent I flag being set to “1” before interrupt control register is changed INT_SWITCH1: FCLR I ; Disable interrupts AND.B #00H, 0056H ; Set TXIC register to “00 16” NOP NOP FSET I ; Enable interrupts Example 2: Use dummy read to have FSET instruction wait INT_SWITCH2: FCLR I ; Disable interrupts AND.B #00H, 0056H ; Set TXIC register to “00 16” MOV.W MEM, R0 ; Dummy read FSET I ; Enable interrupts Example 3: Use POPC instruction to change I flag INT_SWITCH3: PUSHC FLG FCLR I ; Disable interrupts AND.B #00H, 0056H ; Set TXIC register to “00 16” POPC FLG ; Enable interrupts

19.2.6 Changing Interrupt Control Register

(1) Each interrupt control register can only be changed while interrupt requests corresponding to that register are not generated. If interrupt requests may be generated, disable the interrupts before changing the interrupt control register. (2) When changing any interrupt control register after disabling interrupts, be careful with the instruc- tion to be used. When Changing Any Bit Other Than IR Bit If an interrupt request corresponding to that register is generated while executing the instruction, the IR bit may not be set to “1” (interrupt requested), and the interrupt request may be ignored. If this causes a problem, use the following instructions to change the register. Instructions to use: AND, OR, BCLR, BSET When Changing IR Bit If the IR bit is set to “0” (interrupt not requested), it may not be set to “0” depending on the instruction used. Use the MOV instruction to set the IR bit to “0”. (3) When disabling interrupts using the I flag, set the I flag according to the following sample pro- grams. Refer to (2) for the change of interrupt control registers in the sample programs. Sample programs 1 to 3 are preventing the I flag from being set to “1” (interrupt enabled) before writing to the interrupt control registers for reasons of the internal bus or the instruction queue buffer.

R8C/10 Group 19. Usage Notes Rev.1.20 Jan 27, 2006 page 166 of 180 REJ09B0019-0120

19.3 Clock Generation Circuit

19.3.1 Oscillation Stop Detection Function

Since the oscillation stop detection function cannot be used if the main clock frequency is below 2MHz, set the OCD1 to OCD0 bits to “00 2” (oscillation stop detection function disabled).

19.3.2 Oscillation Circuit Constants

Ask the maker of the oscillator to specify the best oscillation circuit constants on your system.

R8C/10 Group 19. Usage Notes Rev.1.20 Jan 27, 2006 page 167 of 180 REJ09B0019-0120

19.4 Timers

19.4.1 Timers X, Y and Z

(1) Timers X, Y and Z stop counting after reset. Therefore, a value must be set to these timers and prescalers before starting counting. (2) Even if the prescalers and timers are read out simultaneously in 16-bit units, these registers are read byte-by-byte in the microcomputer. Consequently, the timer value may be updated during the period these two registers are being read.

19.4.2 Timer X

(1) Do not rewrite the TXMOD0 to TXMOD1 bits, the TXMOD2 bit and TXS bit simultaneously. (2) In pulse period measurement mode, the TXEDG bit and TXUND bit in the TXMR register can be set to “0” by writing “0” to these bits in a program. However, these bits remain unchanged when “1” is written. To set one flag to “0” in a program, write "1" to the other flag by using the MOV instruction. (This prevents any unintended changes of flag.) Example (when setting TXEDG bit to “0”): MOV.B #10XXXXXXB,008BH (3) When changing to pulse period measurement mode from other mode, the contents of the TXEDG bit and TXUND bit are indeterminate. Write "0" to the TXEDG bit and TXUND bit before starting counting. (4) The prescaler X underflow which is generated for the first time after the count start may cause that the TXEDG bit is set to “1”. When using the pulse period measurement mode, leave more than two periods of the prescaler X right after count starts and set the TXEDG bit to “0”.

19.4.3 Timer Y

(1) Do not rewrite the TYMOD0 and TYS bits simultaneously.

19.4.4 Timer Z

(1) Do not rewrite the TZMOD0 to TZMOD1 bits and the TZS bit simultaneously. (2) In programmable one-shot generation mode and programmable wait one-shot generation mode, when setting the TZS bit in the TC register to “0” (stops counting) or setting the TZOS bit in the TZOC register to “0” (stops one-shot), the timer reloads the value of reload register and stops. Therefore, the timer count value should be read out in programmable one-shot generation mode and programmable wait one-shot generation mode before the timer stops.

19.4.5 Timer C

(1) Access the TC, TM0 and TM1 registers in 16-bit units. This prevents the timer value from being updated between the low-order byte and high-order byte are being read. Example (when Timer C is read): MOV.W 0090H,R0 ; Read out timer C

R8C/10 Group 19. Usage Notes Rev.1.20 Jan 27, 2006 page 168 of 180 REJ09B0019-0120

19.5 Serial Interface

(1) When reading data from the UiRB (i=0,1) register even in the clock asynchronous serial I/O mode or in the clock synchronous serial I/O mode. Be sure to read data in 16-bit unit. When the high-byte of the UiRB register is read, the PER and FER bits of the UiRB register and the RI bit of the UiC1 register are set to "0". Example (when reading receive buffer register): MOV.W 00A6H, R0 ; Read the U0RB register (2) When writing data to the UiTB register in the clock asynchronous serial I/O mode with 9-bit transfer data length, data should be written high-byte first then low-byte in 8-bit unit. Example (when reading transmit buffer register): MOV.B #XXH, 00A3H ; Write the high-byte of U0TB register MOV.B #XXH, 00A2H ; Write the low-byte of U0TB register

R8C/10 Group 19. Usage Notes Rev.1.20 Jan 27, 2006 page 169 of 180 REJ09B0019-0120

19.6 A/D Converter

(1) When writing to each bit but except bit 6 in the ADCON0 register, each bit in the ADCON1 register, or the SMP bit in the ADCON2 register, A/D conversion must be stopped (before a trigger occurs). When the VCUT bit in the ADCON1 register is changed from “0” (VREF not connected) to “1” (VREF connected), wait at least 1 µs before starting A/D conversion. (2) When changing AD operation mode, select an analog input pin again. (3) In one-shot mode, A/D conversion must be completed before reading the AD register. The IR bit in the ADIC register or the ADST bit in the ADCON0 register can indicates whether the A/D conversion is completed or not. (4) In repeat mode, the undivided main clock must be used for the CPU clock. (5) If A/D conversion is forcibly terminated while in progress by setting the ADST bit in the ADCON0 register to “0” (A/D conversion halted), the conversion result of the A/D converter is indeterminate. If the ADST bit is set to “0” in a program, ignore the value of AD register. (6) A 0.1 µF capacitor should be connected between the AVcc/V REF pin and AVss pin.

R8C/10 Group 19. Usage Notes Rev.1.20 Jan 27, 2006 page 170 of 180 REJ09B0019-0120

19.7 Flash Memory Version

19.7.1 CPU Rewrite Mode

Before entering CPU rewrite mode (EW0 mode, EW1 mode), select 5MHz or below for the CPU clock using the CM06 bit in the CM0 register and the CM16 to CM17 bits in the CM1 register. G Instructions Diabled Against Use The following instructions cannot be used in EW0 mode because the flash memory internal data is referenced: UND, INTO and BRK instructions. G How to Access Write “0” to the corresponding bits before writing “1” when setting the FMR01, FMR02, and FMR11 bits to ”1”. Do not generate an interrupt between writing “0” and “1”. G Rewriting User ROM Area In EW0 mode, if the power supply voltage drops while rewriting any block in which the rewrite control program is stored, the flash memory may not be able to be rewritten because the rewrite control program cannot be rewritten correctly. In this case, use stnadard serial I/O mode. G Reset Flash Memory Since the CPU stops and cannot return when setting the FMSTP bit in the FMR0 register to “1” (flash memory stops) during erase suspend in EW1 mode, do not set the FMSTP bit to “1”. G Entering Stop Mode or Wait Mode Do not enter stop mode or wait mode during erase-suspend.

R8C/10 Group 19. Usage Notes Rev.1.20 Jan 27, 2006 page 171 of 180 REJ09B0019-0120 G Interrupt Table 19.1 list the Interrupt in EW0 Mode and Table 19.2 lists the Interrupt in EW1 Mode. Mode EW0 Status During auto- matic erasing When maskable interrupt request is acknowledged Any interrupt can be used by allocating a vector to RAM When watchdog timer, oscillation stop detection, and voltage detection interrupt request are acknowledged Once an interrupt request is acknowledged, the auto- programming or auto-erasing is forcibly stoped and resets the flash memory. An interrupt process starts after the fixed period and the flash memory restarts. Since the block during the auto-erasing or the address during the auto-programming is forcibly stopped, the normal value may not be read. Execute the auto-eras- ing again and ensure the auto-erasing is completed normally. Since the watchdog timer does not stop during the command operation, the interrupt request may be generated. Reset the watchdogi timer regularly. Automatic writing Table 19.1 Interrupt in EW0 Mode NOTES: 1. Do not use the address match interrupt while the command is executed because the vector of the address match interrupt is allocated on ROM. 2. Do not use the non-maskable interrupt while Block 0 is automatically erased because the fixed bector is allocated Block 0.

R8C/10 Group 19. Usage Notes Rev.1.20 Jan 27, 2006 page 172 of 180 REJ09B0019-0120 Mode EW1 Status During auto- matic erasing (erase-sus- pend func- tion is en- abled) When maskable interrupt request is acknowledged The auto-erasing is sus- pended and the interrupt pro- cess is executed. The auto- erasing can be restarted by setting the FMR41 bit in the FMR4 register to “0” (erase restart) after the interrupt process completes The auto-erasing has a prior- ity and the interrupt request acknowledgement is waited. The interrupt process is ex- ecuted after the auto-erasing completes The auto-programming has a priority and the interrupt re- quest acknowledgement is waited. The interrupt process is executed after the auto- programming completes When watchdog timer, oscillation stop detection and voltage detection interrupt request area acknowledged Once an interrupt request is acknowledged, the auto-programming or auto-erasing is forc- ibly stopped and resets the flash memory. An interrupt process starts after the fixed period and the flash memory restarts. Since the block during the auto-erasing or the address during the auto-programming is forcibly stopped, the normal value may not be read. Execute the auto-erasing again and ensure the auto-eras- ing is competed normally. Since the watchdog timer does not stop during the command op- eration, the interrupt request may be gener- ated. Reset the watchdog timer regularly using the erase-suspend function. Table 19.2 Interrupt in EW1 Mode During auto- matic erasing (erase-sus- pend func- tion is dis- abled) Auto pro- gramming NOTES: 1. Do not use the address match interrupt while the command is executed because the vector of the address match interrupt is allocated on ROM. 2. Do not use the non-maskable interrupt while Block 0 is automatically erased because the fixed bector is allocated Block 0.

R8C/10 Group 19. Usage Notes Rev.1.20 Jan 27, 2006 page 173 of 180 REJ09B0019-0120

19.8 Noise

(1) Bypass Capacitor between VCC and VSS Pins Insert a bypass capacitor (at least 0.1 µF) between VCC and VSS pins as the countermeasures against noise and latch-up. The connecting wires must be the shortest and widest possible. (2) Port Control Registers Data Read Error During severe noise testing, mainly power supply system noise, and introduction of external noise, the data of port related registers may changed. As a firmware countermeasure, it is recommended to periodically reset the port registers, port direction registers and pull-up control registers. However, you should fully examine before introducing the reset routine as conflicts may be created between this reset routine and interrupt routines (i. e. ports are switched during interrupts). (3) CNVss Pin Wiring In order to improve the pin tolerance to noise, insert a pull down resistance (about 5 kΩ ) between CNVss and Vss, and placed as close as possible to the CNVss pin.

R8C/10 Group 20. Usage Notes for On-chip Debugger Rev.1.20 Jan 27, 2006 page 174 of 180 REJ09B0019-0120 20. Usage notes for on-chip debugger When using the on-chip debugger to develop the R8C/10 group program and debug, pay the following attention. (1) Do not use P00/AN7/TxD11 pin and P37/TxD10/RxD1 pin. (2) When write in the PD3 register (00E716 address), set bit 7 to "0". (3) Do not access the related serial interface 1 register. (4) Do not use from OC000 16 address to OC7FF16 address because the on-chip debugger uses these addresses. (5) Do not set the address match interrupt (the registers of AIER, RMAD0, RMAD1 and the fixed vector tables) in a user system. (6) Do not use the BRK instruction in a user system. (7) Do not set the b5 to “0” by a user program since the on-chip debugger uses after setting the b5 in the FMR0 register to “1”. (8) The stack pointer with upto 8 bytes is used during the user program break. Therefore, save space of 8 bytes for the stack area. Connecting and using the on-chip debugger has some peculiar restrictions. Refer to each on-chip debugger manual for on-chip debugger details.

R8C/10 Group Appendix 1. Package Dimensions Rev.1.20 Jan 27, 2006 page 175 of 180 REJ09B0019-0120 Appendix 1. Package Dimensions DO NOT INCLUDE MOLD FLASH. NOTE) DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. y Index mark F 24 17 x bpe HE E D HD ZD ZE Detail F L A c A2A1 Previous CodeJEITA Package Code RENESAS Code PLQP0032GB-A 32P6U-A MASS[Typ.] 0.2gP-LQFP32-7x7-0.80 1.0 0.125 0.35 0.7 0.7 0.20 0.200.1450.09 0.420.370.32 MaxNomMin Dimension in Millimeters Symbol Reference 7.17.06.9D 7.17.06.9E 1.4A2 9.29.08.8 9.29.08.8 1.7A 0.20.10 0.70.50.3L x 8°0° c 0.8e 0.10y HD HE bp ZD ZE Terminal cross section bp c

R8C/10 Group Appendix 2. Connecting Examples for Serial Writer and On-chip Debugging Emulator Rev.1.20 Jan 27, 2006 page 176 of 180 REJ09B0019-0120 Appendix 2. Connecting examples for serial writer and on-chip debugging emulator Appendix figure. 2.1 shows connecting examples with USB Flash Writer and appendix figure 2.2 shows connecting examples with M16C Flash Starter. 1 2 3 4 5 6 7 8 1 0 1 1 1 2 1 3 1 4 1 5 1 6 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 3 2 3 1 3 0 R8C/10 V c c V s s R x D Connect oscillator circuit(1) C N V s s T x D M O D E NOTES: 1. No need to connect an oscillation circuit when operating with on-chip oscillator clock. U s e r r e s e t s i g n a l T x D R E S E T R x D MODE V c CNVss3 V s s USB Flash Writer (M3A-0665) kΩ Appendix figure 2.1 Connecting examples with USB Flash Writer (M3A-0665) Appendix figure 2.2 Connecting examples with M16C Flash Starter (M3A-0806) 1 2 3 4 5 6 7 8 1 0 1 1 1 2 1 3 1 4 1 5 1 6 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 3 2 3 1 3 0 R8C/10 Vcc V s s R x D Connet oscillator circuit(1) C N V s s T x D M O D E N O T E S : N e e d t o c o n n e c t t h e o s c i l l a t o r c i r c u i t e v e n w h e n o p e r a t i n g w i t h t h e o n c h i p o s c i l l a t o r c l o c k T x D R x D V c c V s s M C F l a s h S t a r t e r M A R E S E T

R8C/10 Group Appendix 2. Connecting Examples for Serial Writer and On-chip Debugging Emulator Rev.1.20 Jan 27, 2006 page 177 of 180 REJ09B0019-0120 Appendix figure 2.3 shows connecting examples with emulator E7. Figure 2.3 Connecting examples with emulator E7 (HS0007TCU01H ) 1 2 3 4 5 6 7 8 1 0 1 1 1 2 1 3 1 4 1 5 1 6 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 3 2 3 1 3 0 R8C/10 Vcc Vss R x D Connect oscillator circuit(1) T x D M O D E N O T E S N o n e e d t o c o n n e c t a n o s c i l l a t i o n c i r c u i t w h e n o p e r a t i n g w i t h o n c h i p o s c i l l a t o r c l o c k User reset signal TxD R E S E T R x D MODE Vcc C N V s s V s s C N V s s Emulator E7 (HS0007TCU01H)

R8C/10 Group Appendix 3. Package Dimensions Rev.1.20 Jan 27, 2006 page 178 of 180 REJ09B0019-0120 Appendix 3. Example of Oscillation Evaluation Circuit Appendix Figure 3.1 shows the Example of Oscillation Evaluation Circuit. 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 R8C/10 Group Vcc Vss Connect oscillation circuit RESET 0.1µF NOTES: 1. Set a program before evaluating. Appendix figure 3.1 Example of Oscillation Evaluation Circuit

R8C/10 Group Register Index Rev.1.20 Jan 27, 2006 page 179 of 180 REJ09B0019-0120 Register Index A AD 107 ADCON0 106, 108, 109 ADCON1 106, 108, 109 ADCON2 107 ADIC 39 AIER 52 C CM0 19 CM1 19 D DRR 121 F FMR0 146 FMR1 147 FMR4 147 I INT0F 46 INT0IC 39 INT1IC 39 INT2IC 39 INT3IC 39 INTEN 46 K KIEN 50 KUPIC 39 O OCD 20 P P0 120 P1 120 P3 120 P4 120 PD0 120 PD1 120 PD3 120 PD4 120 PM0 31 PM1 31 PRCR 30 PREX 57 PREY 66 PREZ 74 PUM 67, 69, 71, 75, 77, 79, 81, 84 PUR0 121 PUR1 121 R RMAD0 52 RMAD1 52 S S0RIC 39 S0TIC 39 S1RIC 39 S1TIC 39 T TC 87 TCC0 49, 87 TCC1 49, 87 TCIC 39 TCSS 57, 67, 75 TM0 87 TX 57 TXIC 39 TXMR 48, 56, 58, 59, 60, 61, 63 TYIC 39 TYPR 66 TYSC 66 TYZMR 48, 65, 69, 71, 73, 77, 79, 81, 84 TYZOC 66, 74 TZIC 39 TZPR 74

R8C/10 Group Register Index Rev.1.20 Jan 27, 2006 page 180 of 180 REJ09B0019-0120 TZSC 74 U U0BRG 91 U0C0 92 U0C1 93 U0MR 92 U0RB 91 U0TB 91 U1BRG 91 U1C0 92 U1C1 93 U1MR 92 U1RB 91 U1TB 91 UCON 93 W WDC 54 WDTR 54 WDTS 54

REVISION HISTORY

Rev. Date Description Page Summary R8C/10 Group Hardware Manual

0.91 Sep 8, 2003 First edition issued –

0.92 Nov 5, 2003 Table1.1 Add on Power Consumption Internal : Revise 10 sources to 9 sources Table 1.2 Delete ** Table1.3 CNVss and MODE : Delete (5 kΩ ) CNVss : Add NOTES 1 Analog power supply input : Add one sentence Reference voltage input : Add one sentence Section 5.1 Add one sentence Section 5.2 Add one sentence Delete sentences Section 5.3 Add one sentence Delet sentecnes Figure 6.2 Revise “on-chip oscillator” to “on-chip oscillator clock” on NOTES 2, CMO Section 6.2 Revise 100 kHz to 125 kHz Section 6.4.3 is revised Table 6.5 Delete “watchdog timer” Table 10.13 Revise “Function of the TYWC bit in the TYZMR” to “Function varies depending on the operation mode” Figure 11.1 is revised Figure 12.1 Delete of CLR Table 12.5 Select function is revised Figure 12.10 Add NOTE 7 and revise 0D 16 to 0E16 Revise some parts in Figure Figure 12.11 Delete of CLR Figure 12.13 TYPR, NOTES 1 : Revise PYSC register to TYSC register TYZOC, NOTES 1 : Revise TYS bit to TZS bit Add NOTE 3 Figure 12.18 Delete of CLR Figure 12.20 TYZOC, NOTE 1 : Revise TYS bit to TZS bit Add NOTE 3 Table 12.11 revised

Rev. Date Description Page Summary R8C/10 Group Hardware Manual 0.92 Nov 5, 2003 Section 17.5 Add sentences Table 17.7 Revise P46/XIN and P47/XOUT Figure 17.13 Add NOTES 3 Figure 17.14 Add NOTES 2 Section 19.3.2 Add (1) and (4) Add Section 19.3.3 (1) Section 20 Add (5) and (6) Add sentences Add 4 pages Words standardized (on-chip oscillator, serial interface, A/D) Table 1.1 revised Figure 1.3, NOTES 3 added Table 1.3 revised Figure 3.1, NOTES added One body sentence in chapter 4 added; Titles of Table 4.1 to 4.4 added Table 4.3 revised ; Table 4.4 revised Figure 6.2 revised (CM0 and CM1) Table 6.3, Timer Z and Timer C interrupt added

6.4.3 Stop Mode, in “Pin Status in Stop Mode”, one sentence added

One sentence in 6.5.1 moves to Chapter 19 One body sentence in 10.2.1 added One body sentence in 10.2.3 added One body sentence in 10.2.4 added Figure 10.15 revised Figure 11.1 revised Line 4 in 12.1 revised Table 12.3 revised Table 12.4 revised Figure 12.7 revised Table 12.6 revised; Figure 12.9 revised Table 12.7 revised Table 12.8 revised, NOTES revised Figure 12.16 revised 5 line in 12.3 revised ; Figure 12.18 revised 150 155 161 147 148

0.93 Feb 18, 2004

1.00 Sep 24, 2004

Rev. Date Description Page Summary R8C/10 Group Hardware Manual Table 12.9 revised Table 12.10 revised, NOTES revised Table 12.11 revised, NOTES revised Figure 12.25 revised Table 12.12 revised, NOTES revised Figure 12.27 revised Figure 12.29 revised Figure 13.2 revised 13.1.3 revised Figure 13.10 revised Table 15.1 revised Table 16.2 revised Table 16.3 revised Table 16.4 revised Table 16.6 revised Table 16.7 revised Table 16.8 revised Table 16.12 revised Table 16.13 revised Table 16.14 revised Table 16.15 revised Table 16.17 revised Table 16.19 revised Line 2 and 8 in 17.4.2 revised FMR46 bit revised Figure 17.3 revised Figure 17.4 revised (FMR4) Figure 17.7 revised ; Figure title revised Table 17.4 revised Figure 17.9 revised Figure 17.10 revised Table 17.6 revised Compositions in Chapter 19 modified ;19.3 added ; 19.4.5 revised ; 19.7 revised (7) in Chapter 20 added Appendix 3 added Page numbers in Register Index revised

1.00 Sep 24, 2004 77

Rev. Date Description Page Summary R8C/10 Group Hardware Manual 5 Figure 1.3 package name revised 10 Table 4.1 revised 12 Table 4.3 revised 14 5.1 partly revised 15 Figure 5.2 partly revised 17 Table 6.1 partly added 19 Figure 6.2 partly revised 21 6.1 partly revised 23 6.3.1 partly deleted 24 6.4.1 partly revised 27 Figure 6.5 revised 28 Figure 6.6 deleted 54 Figure 11.2 partly revised 63 Figure 12.9 partly revised 80 Table 12.11 partly revised 83 Table 12.12 partly revised 87 Figure12.29 partly revised 100 Table 13.6 partly revised 103 13.2.3 Bit Rate added 110 Figure 14.6 partly revised 14.4 added 111 14.5 added 112 14.6 added 114 Figure 15.1 revised 115 Figure 15.2 revised 116 Figure 15.3 revised 120-125 15.2 added 126 Table15.24 partly revised Figure 15.9 added 128 Table 16.3 partly revised Table 16.4 partly added Table 16.5 partly revised 130 Table 16.6 partly revised 134 Table 16.13 partly revised 138 Figure 17.1 revised 146 Figure 17.5 added 149 •Program partly revised 151 Figure 17.11 partly added 157 Figure 17.13 package name revised 159 18.1 partly revised 164 19.3.2 added 165 19.4.4 partly revised 167 19.6 partly revised 168 19.7.1 partly added 172 20 partly revised

Rev. Date Description Page Summary R8C/10 Group Hardware Manual 1.20 Jan.27.2006 113 14.7 Output Impedance of Sensor under A/D Conversion added 116 Figure 15.1 Programmable I/O Ports (1); NOTES: 1 added 117 Figure 15.2 Programmable I/O Ports (2); NOTES: 1 added 118 Figure 15.3 Programmable I/O Ports (3); NOTES: 1 added 119 Figure 15.4 Programmable I/O Ports (4); NOTES: 3 added 127 Table 15.22 Port P45/INT0 Setting; Bit: “PD3_3” → “PD4_5” Table 15.23 Port XIN/P46, XOUT /P47 Setting; Setting value: External input to XIN pin, “H” output from XOUT pin; 129 Table 16.2 Recommended Operating Conditions; NOTES: 1, 2, 3 revised 130 Table 16.3 A/D Conversion Characteristics; “A/D operation clock frequency” → “A/D operating clock frequency” revised NOTES: 1, 2, 3, 4 revised Table 16.4 Flash Memory (Program ROM) Electrical Characteristics; “Data retention duration” → “Data hold time” revised “Topr” → “Ambient temperature” revised NOTES: 2 added Measuring condition of byte program time and block erase time deleted 132 Table 16.6 Electrical Characteristics (1) [VCC =5V]; “P10 to P17 Except XOUT ” → “Except P10 to P17, XOUT ” revised 133 Table 16.7 Electrical Characteristics (2) [VCC =5V] NOTES: 1, 2 revised Measuring condition: Stop mode “Topr = 25 °C” added 136 Table 16.13 Electrical Characteristics (3) [VCC =3V] “P10 to P17 Except XOUT ” → “Except P10 to P17, XOUT ” revised 137 Table 16.14 Electrical Characteristics (4) [VCC =3V] NOTES: 1, 2 revised Measuring condition: Stop mode “Topr = 25 °C” added 147 Figure 17.4 FMR1 and FMR4; Flash memory control register 4 NOTES: 2 “Other than this period, this bit is set to “0”.” revised 153 Figure 17.11 Block Erase Command (When Using Erase-suspend Function); “Write ‘D016’ to the uppermost block address” → “Write ‘D016’ to the any block address” revised 156 Figure 17.12 Full Status Check and Handling Procedure for Each Error revised 158 Table 17.7 Pin Functions (Flash Memory Standard Serial I/O Mode);____________ RESET: revised 162 19.1.1 Stop Mode “Use the next program to enter stop mode.” added “• Example of entering stop mode” → “• Program of entering stop mode” “Program Example” deleted 166 19.3.1 Oscillation Stop Detection Function 176 Appendix figure 2.2 Connecting examples with M16C Flash Starter (M3A-0806); Pulled up added NOTES: 1 revised

RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER HARDWARE MANUAL R8C/10 Group Publication Data : Rev.0.93 Feb 18, 2004 Rev.1.20 Jan 27, 2006 Published by : Sales Strategic Planning Div. Renesas Technology Corp. © 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.

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