R8C/32A

R8C32A RENESAS | Alldatasheet

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www.renesas.com All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp. website (http://www.renesas.com). REJ09B0458-0010 R8C/32A Group Hardware Manual RENESAS MCU M16C FAMILY / R8C/Tiny SERIES Rev.0.10 Revision Date: Apr 01, 2008 Preliminary

1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Notes regarding these materials

General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.  The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied.  The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited.  The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized.  When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems.  The characteristics of MPU/MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different part numbers, implement a system-evaluation test for each of the products.

1. Purpose and Target Readers This manual is designed to provide the user with an understanding of the hardwa re functions and electrical characteristics of the MCU. It is intended for users de signing application systems incorporating the MCU. A basic knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual. The manual comprises an overview of the product; descriptions of the CPU, system control functions, peripheral functions, and electrical characteristics; and usage notes. Particular attention should be paid to the precautio nary notes when using the manual. These notes occur within the body of the text, at the end of each section, and in the Usage Notes section. The revision history summarizes the loca tions of revisions and additions. It does not list all revisions. Refer to the text of the manual for details. The following documents apply to the R8C/32A Group. Make sure to refer to the latest versions of these documents. The newest versions of the documents listed may be obtained from the Renesas Technology Web site. Document Type Description Document Title Document No. Datasheet Hardware overview and electr ical characteristics R8C/32A Group Datasheet REJ03B0229 Hardware manual Hardware specifications (pin assignments, memory maps, peripheral function specifications, electrical characteristics, timing charts) and operation description Note: Refer to the application notes for details on using peripheral functions. R8C/32A Group Hardware Manual This hardware manual Software manual Description of CPU instruction set R8C/Tiny Series Software Manual REJ09B0001 Application note Information on using peripheral functions and application examples Sample programs Information on writing programs in assembly language and C Available from Renesas Technology Web site. Renesas technical update Product specifications, updates on documents, etc.

1. Notation of Numbers and Symbols The notation conventions for register na mes, bit names, numbers, and symbols used in this manual are described below. (1) Register Names, Bit Names, and Pin Names Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word “register,” “bit,” or “pin” to distinguish the three categories. Examples the PM03 bit in the PM0 register P3_5 pin, VCC pin (2) Notation of Numbers The indication “b” is appended to numeric values given in binary format. However, nothing is appended to the values of single bits. The indication “h” is appended to numeric values given in hexadecimal format. Nothing is appended to numeric values given in decimal format. Examples Binary: 11b Hexadecimal: EFA0h Decimal: 1234

1. Register Notation The symbols and terms used in register diagrams are described below. x.x.x XXX Register (Symbol) R/W: Read and write. R: Read only. W: Write only. −: Nothing is assigned.

• Reserved bit Reserved bit. Set to specified value.
• Nothing is assigned. Nothing is assigned to the bit. As the bit may be used for future functions, if necessary, set to 0.
• Do not set to a value. Operation is not guaranteed when a value is set.
• Function varies according to the operating mode. The function of the bit varies with the peripheral functi on mode. Refer to the regist er diagram for information on the individual modes. Address XXXXh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol XXX7 XXX6 XXX5 XXX4 — — XXX1 XXX0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 XXX0 XXX bit b1 b0 0 0: XXX 0 1: XXX 1 0: Do not set. 1 1: XXX R/W b1 XXX1 R/W b2 — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. — b3 — Reserved bit Set to 0. R/W b4 XXX4 XXX bit Function varies acco rding to the operating mode. R/W b5 XXX5 W b6 XXX6 R/W b7 XXX7 XXX bit 0: XXX 1: XXX R *2 *3

1. List of Abbrevia tions and Acronyms All trademarks and registered trademarks are the property of their respective owners. Abbreviation Full Form ACIA Asynchronous Communication Interface Adapter bps bits per second CRC Cyclic Redundancy Check DMA Direct Memory Access DMAC Direct Memory Access Controller GSM Global System for Mobile Communications Hi-Z High Impedance IEBus Inter Equipment Bus I/O Input/Output IrDA Infrared Data Association LSB Least Significant Bit MSB Most Significant Bit NC Non-Connection PLL Phase Locked Loop PWM Pulse Width Modulation SFR Special Function Register SIM Subscriber Identity Module UART Universal Asynchrono us Receiver/Transmitter VCO Voltage Controlled Oscillator

11.2.1 Interrupt Control Register

(TREIC, S2TIC, S2RIC, KUPIC, ADIC, S0TIC, S0RIC, TRAIC, TRBIC, U2BCNIC, VCMP1IC, 11.7 Timer RC Interrupt, Synchronous Serial Communication Unit Interrupt, I 2C bus Interface Interrupt, and

33.17.1 Inserting a Bypass Capacitor between VCC and VSS Pins as a Countermeasure against Noise and

Note: 1. The blank regions are reserved. Do not access locations in these regions. Address Register Symbol Page 0000h 0001h 0002h 0003h 0004h Processor Mode Register 0 PM0 28 0005h Processor Mode Register 1 PM1 158 0006h System Clock Control Register 0 CM0 92 0007h System Clock Control Register 1 CM1 93 0008h Module Standby Control Register MSTCR 224, 355, 386 0009h System Clock Control Register 3 CM3 94 000Ah Protect Register PRCR 120 000Bh Reset Source Determination Register RSTFR 28 000Ch Oscillation Stop Detection Register OCD 95 000Dh Watchdog Timer Reset Register WDTR 158 000Eh Watchdog Timer Start Register WDTS 158 000Fh Watchdog Timer Control Register WDTC 159 0010h 0011h 0012h 0013h 0014h 0015h High-Speed On-Chip Oscillator Control Register 7 FRA7 95 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch Count Source Protection Mode Register CSPR 159 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h High-Speed On-Chip Oscillator Control Register 0 FRA0 96 0024h High-Speed On-Chip Oscillator Control Register 1 FRA1 96 0025h High-Speed On-Chip Oscillator Control Register 2 FRA2 97 0026h On-Chip Reference Voltage Control Register OCVREFCR 434 0027h 0028h Clock Prescaler Reset Flag CPSRF 97 0029h High-Speed On-Chip Oscillator Control Register 4 FRA4 98 002Ah High-Speed On-Chip Oscillator Control Register 5 FRA5 98 002Bh High-Speed On-Chip Oscillator Control Register 6 FRA6 98 002Ch 002Dh 002Eh 002Fh High-Speed On-Chip Oscillator Control Register 3 FRA3 98 0030h Voltage Monitor Circuit/Comparator A Control Register CMPA 41, 458 0031h Voltage Monitor Circuit Edge Select Register VCAC 42, 458 0032h 0033h Voltage Detect Register 1 VCA1 42, 459 0034h Voltage Detect Register 2 VCA2 43, 99, 460 0035h 0036h Voltage Detection 1 Level Select Register VD1LS 44 0037h 0038h Voltage Monitor 0 Circuit Control Register VW0C 45 0039h Voltage Monitor 1 Circuit Control Register VW1C 46, 461 003Ah Voltage Monitor 2 Circuit Control Register VW2C 47, 462 003Bh 003Ch 003Dh 003Eh 003Fh Address Register Symbol Page 0040h 0041h Flash Memory Ready Interrupt Control Register FMRDYIC 127 0042h 0043h 0044h 0045h 0046h 0047h Timer RC Interrupt Control Register TRCIC 127 0048h 0049h 004Ah Timer RE Interrupt Control Register TREIC 126 004Bh UART2 Transmit Interru pt Control Register S2TIC 126 004Ch UART2 Receive Interrupt Control Register S2RIC 126 004Dh Key Input Interrupt Control Register KUPIC 126 004Eh A/D Conversion Interrupt Control Register ADIC 126 004Fh SSU Interrupt Control Register / IIC bus Interrupt Control Register SSUIC/IICIC 127 0050h 0051h UART0 Transmit Interrupt Control Register S0TIC 126 0052h UART0 Receive Interrupt Control Register S0RIC 126 0053h 0054h 0055h 0056h Timer RA Interrupt Control Register TRAIC 126 0057h 0058h Timer RB Interrupt Control Register TRBIC 126 0059h INT1 Interrupt Control Register INT1IC 128 005Ah INT3 Interrupt Control Register INT3IC 128 005Bh 005Ch 005Dh INT0 Interrupt Control Register INT0IC 128 005Eh UART2 Bus Collision Detection Interrupt Control Register U2BCNIC 126 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h Voltage Monitor 1/Compare A1 Interrupt Control Register VCMP1IC 126 0073h Voltage Monitor 2/Compare A2 Interrupt Control Register VCMP2IC 126 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh SFR Page Reference

Note: 1. The blank regions are reserved. Do not access locations in these regions. Address Register Symbol Page 0080h DTC Start Control Register DTCTL 170 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h DTC Start Enable Register 0 DTCEN0 169 0089h DTC Start Enable Register 1 DTCEN1 169 008Ah DTC Start Enable Register 2 DTCEN2 169 008Bh DTC Start Enable Register 3 DTCEN3 169 008Ch 008Dh DTC Start Enable Register 5 DTCEN5 169 008Eh DTC Start Enable Register 6 DTCEN6 169 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h UART0 Transmit/Receive Mode Register U0MR 289 00A1h UART0 Bit Rate Register U0BRG 289 00A2h UART0 Transmit Buffer Register U0TB 290 00A3h 00A4h UART0 Transmit/Receive Control Register 0 U0C0 291 00A5h UART0 Transmit/Receive Control Register 1 U0C1 291 00A6h UART0 Receive Buffer Register U0RB 292 00A7h 00A8h UART2 Transmit/Receive Mode Register U2MR 309 00A9h UART2 Bit Rate Register U2BRG 309 00AAh UART2 Transmit Buffer Register U2TB 310 00ABh 00ACh UART2 Transmit/Receive Control Register 0 U2C0 311 00ADh UART2 Transmit/Receive Control Register 1 U2C1 312 00AEh UART2 Receive Buffer Register U2RB 313 00AFh 00B0h UART2 Digital Filter Function Select Register URXDF 314 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh UART2 Special Mode Register 5 U2SMR5 314 00BCh UART2 Special Mode Register 4 U2SMR4 315 00BDh UART2 Special Mode Register 3 U2SMR3 315 00BEh UART2 Special Mode Register 2 U2SMR2 316 00BFh UART2 Special Mode Register U2SMR 316 Address Register Symbol Page 00C0h A/D Register 0 AD0 435 00C1h 00C2h A/D Register 1 AD1 435 00C3h 00C4h A/D Register 2 AD2 435 00C5h 00C6h A/D Register 3 AD3 435 00C7h 00C8h A/D Register 4 AD4 435 00C9h 00CAh A/D Register 5 AD5 435 00CBh 00CCh A/D Register 6 AD6 435 00CDh 00CEh A/D Register 7 AD7 435 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h A/D Mode Register ADMOD 436 00D5h A/D Input Select Register ADINSEL 437 00D6h A/D Control Register 0 ADCON0 438 00D7h A/D Control Register 1 ADCON1 439 00D8h 00D9h 00DAh 00DBh 00DCh 00DDh 00DEh 00DFh 00E0h 00E1h Port P1 Register P1 66 00E2h 00E3h Port P1 Direction Register PD1 65 00E4h 00E5h Port P3 Register P3 66 00E6h 00E7h Port P3 Direction Register PD3 65 00E8h Port P4 Register P4 66 00E9h 00EAh Port P4 Direction Register PD4 65 00EBh 00ECh 00EDh 00EEh 00EFh 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh

Note: 1. The blank regions are reserved. Do not access locations in these regions. Address Register Symbol Page 0100h Timer RA Control Register TRACR 185 0101h Timer RA I/O Control Register TRAIOC 185, 188, 191, 193, 195, 198 0102h Timer RA Mode Register TRAMR 186 0103h Timer RA Prescaler Register TRAPRE 186 0104h Timer RA Register TRA 187 0105h LIN Control Register 2 LINCR2 419 0106h LIN Control Register LINCR 420 0107h LIN Status Register LINST 420 0108h Timer RB Control Register TRBCR 202 0109h Timer RB One-Shot Control Register TRBOCR 202 010Ah Timer RB I/O Control Register TRBIOC 203, 206, 210, 213, 217 010Bh Timer RB Mode Register TRBMR 203 010Ch Timer RB Prescaler Register TRBPRE 204 010Dh Timer RB Secondary Register TRBSC 204 010Eh Timer RB Primary Register TRBPR 205 010Fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h Timer RE Second Data Register / Counter Data Register TRESEC 272, 280 0119h Timer RE Minute Data Register / Compare Data Register TREMIN 272, 280 011Ah Timer RE Hour Data Register TREHR 273 011Bh Timer RE Day of Week Data Register TREWK 273 011Ch Timer RE Control Register 1 TRECR1 274, 281 011Dh Timer RE Control Register 2 TRECR2 275, 281 011Eh Timer RE Count Source Select Register TRECSR 276, 282 011Fh 0120h Timer RC Mode Register TRCMR 224 0121h Timer RC Control Register 1 TRCCR1 225, 246, 254, 260 0122h Timer RC Interrupt Enable Register TRCIER 225 0123h Timer RC Status Register TRCSR 226 0124h Timer RC I/O Control Register 0 TRCIOR0 227, 241, 247 0125h Timer RC I/O Control Register 1 TRCIOR1 227, 242, 248 0126h Timer RC Counter TRC 228 0127h 0128h Timer RC General Register A TRCGRA 228 0129h 012Ah Timer RC General Register B TRCGRB 228 012Bh 012Ch Timer RC General Register C TRCGRC 228 012Dh 012Eh Timer RC General Register D TRCGRD 228 012Fh 0130h Timer RC Control Register 2 TRCCR2 229, 254, 261 0131h Timer RC Digital Filter Function Select Register TRCDF 229, 261 0132h Timer RC Output Master Enable Register TRCOER 230 0133h Timer RC Trigger Control Register TRCADCR 230 0134h 0135h 0136h 0137h 0138h 0139h 013Ah 013Bh 013Ch 013Dh 013Eh 013Fh Address Register Symbol Page 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014Ah 014Bh 014Ch 014Dh 014Eh 014Fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015Ah 015Bh 015Ch 015Dh 015Eh 015Fh 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016Ah 016Bh 016Ch 016Dh 016Eh 016Fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017Ah 017Bh 017Ch 017Dh 017Eh 017Fh

Note: 1. The blank regions are reserved. Do not access locations in these regions. Address Register Symbol Page 0180h Timer RA Pin Select Register TRASR 67, 187 0181h Timer RC Pin Select Register TRBRCSR 67, 231 0182h Timer RC Pin Select Register 0 TRCPSR0 68, 232 0183h Timer RC Pin Select Register 1 TRCPSR1 68, 232 0184h 0185h 0186h 0187h 0188h UART0 Pin Select Register U0SR 69, 293 0189h 018Ah UART2 Pin Select Register 0 U2SR0 70, 317 018Bh UART2 Pin Select Register 1 U2SR1 70, 317 018Ch SSU/IIC Pin Select Register SSUIICSR 71, 355, 386 018Dh 018Eh INT Interrupt Input Pin Select Register INTSR 71, 136 018Fh 0190h 0191h 0192h 0193h SS Bit Counter Register SSBR 356 0194h SS Transmit Data Register L / IIC bus Transmit Data Register SSTDR / ICDRT 356, 387 0195h SS Transmit Data Register H SSTDRH 0196h SS Receive Data Register L / IIC bus Receive Data Register SSRDR / ICDRR 357, 387 0197h SS Receive Data Register H SSRDRH 0198h SS Control Register H / IIC bus Control Register 1 SSCRH / ICCR1 357, 388 0199h SS Control Register L / IIC bus Control Register 2SSCRL / ICCR2 358, 389 019Ah SS Mode Register / IIC bus Mode Register SSMR / ICMR 359, 390 019Bh SS Enable Register / IIC bus Interrupt Enable Register SSER / ICIER 360, 391 019Ch SS Status Register / IIC bus Status Register SSSR / ICSR 361, 392 019Dh SS Mode Register 2 / Slave Address Register SSMR2 / SAR 362, 393 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 01ABh 01ACh 01ADh 01AEh 01AFh 01B0h 01B1h 01B2h Flash Memory Status Register FST 483 01B3h 01B4h Flash Memory Control Register 0 FMR0 485 01B5h Flash Memory Control Register 1 FMR1 487 01B6h Flash Memory Control Register 2 FMR2 489 01B7h 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh Address Register Symbol Page 01C0h Address Match Interrupt Register 0 RMAD0 142 01C1h 01C2h 01C3h Address Match Interrupt Enable Register 0 AIER0 142 01C4h Address Match Interrupt Register 1 RMAD1 142 01C5h 01C6h 01C7h Address Match Interrupt Enable Register 1 AIER1 142 01C8h 01C9h 01CAh 01CBh 01CCh 01CDh 01CEh 01CFh 01D0h 01D1h 01D2h 01D3h 01D4h 01D5h 01D6h 01D7h 01D8h 01D9h 01DAh 01DBh 01DCh 01DDh 01DEh 01DFh 01E0h Pull-Up Control Register 0 PUR0 72 01E1h Pull-Up Control Register 1 PUR1 72 01E2h 01E3h 01E4h 01E5h 01E6h 01E7h 01E8h 01E9h 01EAh 01EBh 01ECh 01EDh 01EEh 01EFh 01F0h Port P1 Drive Capacity Control Register P1DRR 73 01F1h 01F2h Drive Capacity Control Register 0 DRR0 74 01F3h Drive Capacity Control Register 1 DRR1 75 01F4h 01F5h Input Threshold Control Register 0 VLT0 76 01F6h Input Threshold Control Register 1 VLT1 76 01F7h 01F8h Comparator B Control Register 0 INTCMP 473 01F9h 01FAh External Input Enable Register 0 INTEN 137, 473 01FBh 01FCh INT Input Filter Select Register 0 INTF 137, 474 01FDh 01FEh Key Input Enable Register 0 KIEN 140 01FFh

Note: 1. The blank regions are reserved. Do not access locations in these regions. Address Register Symbol Page 2C00h DTC Transfer Vector Area 2C01h DTC Transfer Vector Area 2C02h DTC Transfer Vector Area 2C03h DTC Transfer Vector Area 2C04h DTC Transfer Vector Area 2C05h DTC Transfer Vector Area 2C06h DTC Transfer Vector Area 2C07h DTC Transfer Vector Area 2C08h DTC Transfer Vector Area 2C09h DTC Transfer Vector Area 2C0Ah DTC Transfer Vector Area : DTC Transfer Vector Area : DTC Transfer Vector Area 2C3Ah DTC Transfer Vector Area 2C3Bh DTC Transfer Vector Area 2C3Ch DTC Transfer Vector Area 2C3Dh DTC Transfer Vector Area 2C3Eh DTC Transfer Vector Area 2C3Fh DTC Transfer Vector Area 2C40h DTCD0 2C41h 2C42h 2C43h 2C44h 2C45h 2C46h 2C47h 2C48h DTCD1 2C49h 2C4Ah 2C4Bh 2C4Ch 2C4Dh 2C4Eh 2C4Fh 2C50h DTCD2 2C51h 2C52h 2C53h 2C54h 2C55h 2C56h 2C57h 2C58h DTCD3 2C59h 2C5Ah 2C5Bh 2C5Ch 2C5Dh 2C5Eh 2C5Fh 2C60h DTCD4 2C61h 2C62h 2C63h 2C64h 2C65h 2C66h 2C67h 2C68h DTCD5 2C69h 2C6Ah 2C6Bh 2C6Ch 2C6Dh 2C6Eh 2C6Fh Address Register Symbol Page 2C70h DTCD6 2C71h 2C72h 2C73h 2C74h 2C75h 2C76h 2C77h 2C78h DTCD7 2C79h 2C7Ah 2C7Bh 2C7Ch 2C7Dh 2C7Eh 2C7Fh 2C80h DTCD8 2C81h 2C82h 2C83h 2C84h 2C85h 2C86h 2C87h 2C88h DTCD9 2C89h 2C8Ah 2C8Bh 2C8Ch 2C8Dh 2C8Eh 2C8Fh 2C90h DTCD10 2C91h 2C92h 2C93h 2C94h 2C95h 2C96h 2C97h 2C98h DTCD11 2C99h 2C9Ah 2C9Bh 2C9Ch 2C9Dh 2C9Eh 2C9Fh 2CA0h DTCD12 2CA1h 2CA2h 2CA3h 2CA4h 2CA5h 2CA6h 2CA7h 2CA8h DTCD13 2CA9h 2CAAh 2CABh 2CACh 2CADh 2CAEh 2CAFh

Note: 1. The blank regions are reserved. Do not access locations in these regions. Address Register Symbol Page 2CB0h DTCD14 2CB1h 2CB2h 2CB3h 2CB4h 2CB5h 2CB6h 2CB7h 2CB8h DTCD15 2CB9h 2CBAh 2CBBh 2CBCh 2CBDh 2CBEh 2CBFh 2CC0h DTCD16 2CC1h 2CC2h 2CC3h 2CC4h 2CC5h 2CC6h 2CC7h 2CC8h DTCD17 2CC9h 2CCAh 2CCBh 2CCCh 2CCDh 2CCEh 2CCFh 2CD0h DTCD18 2CD1h 2CD2h 2CD3h 2CD4h 2CD5h 2CD6h 2CD7h 2CD8h DTCD19 2CD9h 2CDAh 2CDBh 2CDCh 2CDDh 2CDEh 2CDFh 2CE0h DTCD20 2CE1h 2CE2h 2CE3h 2CE4h 2CE5h 2CE6h 2CE7h 2CE8h DTCD21 2CE9h 2CEAh 2CEBh 2CECh 2CEDh 2CEEh 2CEFh Address Register Symbol Page 2CF0h DTCD22 2CF1h 2CF2h 2CF3h 2CF4h 2CF5h 2CF6h 2CF7h 2CF8h DTCD23 2CF9h 2CFAh 2CFBh 2CFCh 2CFDh 2CFEh 2CFFh 2D00h 2D01h 2D01h FFDBh Option Function Select Register 2 OFS2 30, 154, 161 FFFFh Option Function Select Register OFS 29, 48, 153, 160, 481

REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 1 of 572 R8C/32A Group RENESAS MCU 1. Overview

1.1 Features

The R8C/32A Group of single-chip MCUs incorporates the R8C/Tiny Series CPU core, employing sophisticated instructions for a high level of efficiency. With 1 Mbyte of address space, and it is capable of executing instructions at high speed. In addition, the CPU core boasts a multiplier for high-speed operation processing. Power consumption is low, and the supported operating modes allow additional power control. These MCUs also use an anti-noise configuration to reduce emissions of electromagnetic noise and are designed to withstand EMI. Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of system components. The R8C/32A Group has data flash (1 KB × 4 blocks) with the background operation (BGO) function.

1.1.1 Applications

Electronic household appliances, office equipment, audio equipment, consumer equipment, etc. REJ09B0458-0010 Rev.0.10 Apr 01, 2008 PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change.

R8C/32A Group 1. Overview REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 2 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

1.1.2 Specifications

Tables 1.1 and 1.2 outline the Specifications for R8C/32A Group. Table 1.1 Specifications for R8C/32A Group (1) Item Function Specification CPU Central processing unit R8C/Tiny series core

• Number of fundamental instructions: 89
• Minimum instruction execution time: 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V) 100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V) 200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V) 500 ns (f(XIN) = 2 MHz, VCC = 1.8 to 5.5 V)
• Multiplier: 16 bits × 16 bits → 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits
• Operation mode: Single-chip mode (address space: 1 Mbyte) Memory ROM, RAM, Data flash Refer to Table 1.3 Product List for R8C/32A Group. Power Supply Voltage Detection Voltage detection circuit
• Power-on reset
• Voltage detection 3 (detection level of voltage detection 0 and voltage detection 1 selectable) I/O Ports Programmable I/O ports
• Input-only: 1 pin
• CMOS I/O ports: 15, selectable pull-up resistor
• High current drive ports: 15 Clock Clock generation circuits 4 circuits: XIN clock oscillation circuit, XCIN clock oscillation circuit (32 kHz) High-speed on-chip oscillator (with frequency adjustment function), Low-speed on-chip oscillator,
• Oscillation stop detection: XIN clock oscillation stop detection function
• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16
• Low power consumption modes: Standard operating mode (high-speed clock, low-speed clock, high-speed on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode Real-time clock (timer RE) Interrupts • Number of interrupt vectors: 69
• External Interrupt: 7 (INT × 3, Key input × 4)
• Priority levels: 7 levels Watchdog Timer • 15 bits × 1 (with prescaler)
• Reset start selectable
• Low-speed on-chip oscillator for watchdog timer selectable DTC (Data Transfer Controller) • 1 channel
• Activation sources: 21
• Transfer modes: 2 (normal mode, repeat mode) Timer Timer RA 8 bits × 1 (with 8-bit prescaler) Timer mode (period timer), pulse output mode (output level inverted every period), event counter mode, pulse width measurement mode, pulse period measurement mode Timer RB 8 bits × 1 (with 8-bit prescaler) Timer mode (period timer), programmable waveform generation mode (PWM output), programmable one-shot generation mode, programmable wait one- shot generation mode Timer RC 16 bits × 1 (with 4 capture/compare registers) Timer mode (input capture function, output compare function), PWM mode (output 3 pins), PWM2 mode (PWM output pin) Timer RE 8 bits × 1 Real-time clock mode (count seconds, minutes, hours, days of week), output compare mode

R8C/32A Group 1. Overview REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 3 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Note: 1. Specify the D version if D ve rsion functions are to be used. Table 1.2 Specifications for R8C/32A Group (2) Item Function Specification Serial Interface UART0 Clock synchronous serial I/O/UART UART2 Clock synchronous serial I/O/UART, I 2C mode (I2C-bus), multiprocessor communication function Synchronous Serial Communication Unit (SSU) 1 (shared with I 2C-bus) I2C bus 1 (shared with SSU) LIN Module Hardware LIN: 1 (timer RA, UART0) A/D Converter 10-bit resolution × 4 channels, includes sample and hold function, with sweep mode Comparator A • 2 circuits (shared with voltage monitor 1 and voltage monitor 2)

• External reference voltage input available Comparator B 2 circuits Flash Memory • Programming and eras ure voltage: VCC = 2.7 to 5.5 V
• Programming and erasure endurance: 10,000 times (data flash) 1,000 times (program ROM)
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
• Background operation (BGO) function Operating Frequency/Supply Voltage f(XIN) = 20 MHz (VCC = 3.0 to 5.5 V) f(XIN) = 10 MHz (VCC = 2.7 to 5.5 V) f(XIN) = 5 MHz (VCC = 2.2 to 5.5 V) f(XIN) = 2 MHz (VCC = 1.8 to 5.5 V) Current consumption TBD (VCC = 5.0 V, f(XIN) = 20 MHz) TBD (VCC = 3.0 V, f(XIN) = 10 MHz) TBD (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz)) TBD (VCC = 3.0 V, stop mode) Operating Ambient Temperature -20 to 85 °C (N version) -40 to 85°C (D version) (1) Package 20-pin LSSOP

R8C/32A Group 1. Overview REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 4 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

1.2 Product List

Table 1.3 lists Product List for R8C/32A Group, and Figure 1.1 shows a Part Number, Memory Size, and Package of R8C/32A Group. (D): Under development Figure 1.1 Part Number, Memory Size, and Package of R8C/32A Group Table 1.3 Product List for R8C/32A Group Current of Apr. 2008 Part No. ROM Capacity RAM Capacity Package Type RemarksProgram ROM Data flash R5F21321ANSP (D) 4 Kbytes 1 Kbyte × 4 512 bytes PLSP0020JB-A N version R5F21322ANSP (D) 8 Kbytes 1 Kbyte × 4 1 Kbyte PLSP0020JB-A R5F21324ANSP (D) 16 Kbytes 1 Kbyte × 4 1.5 Kbytes PLSP0020JB-A R5F21321ADSP (D) 4 Kbytes 1 Kbyte × 4 512 bytes PLSP0020JB-A D version R5F21322ADSP (D) 8 Kbytes 1 Kbyte × 4 1 Kbyte PLSP0020JB-A R5F21324ADSP (D) 16 Kbytes 1 Kbyte × 4 1.5 Kbytes PLSP0020JB-A Part No. R 5 F 21 32 4 A N FP Package type: FP: PLSP0020JB-A (0.65 mm pin-pitch) Classification N: Operating ambient temperature -20°C to 85°C D: Operating ambient temperature -40°C to 85°C ROM capacity 1: 4 KB 2: 8 KB 4: 16 KB R8C/32A Group R8C/Tiny Series Memory type F: Flash memory Renesas MCU Renesas semiconductor

R8C/32A Group 1. Overview REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 5 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

1.3 Block Diagram

Figure 1.2 shows a Block Diagram. Figure 1.2 Block Diagram R8C/Tiny Series CPU core System clock generation circuit XIN-XOUT High-speed on-chip oscillator Low-speed on-chip oscillator XCIN-XCOUT Memory ROM (1) RAM (2) Multiplier R0H R0L R1H R1L FB SB USP ISP INTB PC FLG I/O ports Notes: 1. ROM size varies with MCU type. 2. RAM size varies with MCU type. Port P1 Port P3 3 1 Port P4 Timers Timer RA (8 bits × 1) Timer RB (8 bits × 1) Timer RC (16 bits × 1) Timer RE (8 bits × 1) UART or clock synchronous serial I/O (8 bits × 2) I2C bus or SSU (8 bits × 1) Peripheral functions Watchdog timer (15 bits) A/D converter (10 bits × 4 channels) LIN module Comparator B Voltage detection circuit Comparator A DTC Low-speed on-chip oscillator for watchdog timer

R8C/32A Group 1. Overview REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 6 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

1.4 Pin Assignment

Figure 1.3 shows Pin Assignment (Top View). Table 1.4 outlines the Pin Name Information by Pin Number. Figure 1.3 Pin Assignment (Top View)

20 P1_0/AN8/LVCMP1/KI0(/TRCIOD)

19 P1_1/AN9/LVCMP2/KI1(/TRCIOA/TRCTRG)

18 P1_2/AN10/LVREF/Kl2(/TRCIOB)

17 P1_3/AN11/LVCOUT1/Kl3/TRBO(/TRCIOC)

16 P1_4(/TXD0/TRCCLK)

15 P1_5(/INT1/RXD0/TRAIO)

14 P1_6/LVCOUT2/IVREF1(/CLK0)

13 P1_7/IVCMP1/INT1(/TRAIO)

12 P4_5/ADTRG/INT0(/RXD2/SCL2)

11 P3_3/IVCMP3/INT3/SCS(/CTS2/RTS2/TRCCLK)

P4_2/VREF MODE RESET P4_7/XOUT(/XCOUT) VSS/AVSS P4_6/XIN(/XCIN) VCC/AVCC P3_7/SDA/SSO/TRAO(/RXD2/SCL2/TXD2/SDA2) P3_5/SCL/SSCK(/CLK2/TRCIOD) P3_4/IVREF3/SSI(/RXD2/SCL2/TXD2/SDA2/TRCIOC) R8C/32A Group PLSP0020JB-A (20P2F-A) (top view) Notes: 1. Can be assigned to the pin in parentheses by a program. 2. Confirm the pin 1 position on the package by referring to the package dimensions.

R8C/32A Group 1. Overview REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 7 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Note: 1. Can be assigned to the pin in parentheses by a program. Table 1.4 Pin Name Information by Pin Number Pin Number Control Pin Port I/O Pin Functions for Peripheral Modules Interrupt Timer Serial Interface SSU I2C bus A/D Converter, Comparator A, Comparator B, Voltage Detection Circuit 1P 4 _ 2 V R E F 2M O D E

3 RESET

4 XOUT(/XCOUT) P4_7

5 VSS/AVSS

6 XIN(/XCIN) P4_6

7 VCC/AVCC

8 P3_7 TRAO (RXD2/SCL2/

TXD2/SDA2) SSO SDA

9 P3_5 (TRCIOD) (CLK2) SSCK SCL

10 P3_4 (TRCIOC) (RXD2/SCL2/

TXD2/SDA2) SSI IVREF3

11 P3_3 INT3

(TRCCLK) (CTS2/RTS2)S C S IVCMP3

12 P4_5 INT0 (RXD2/SCL2) ADTRG

13 P1_7 INT1 (TRAIO) IVCMP1

14 P1_6 (CLK0) LVCOUT2/IVREF1

15 P1_5 (INT1) (TRAIO) (RXD0)

16 P1_4 (TRCCLK) (TXD0)

17 P1_3 KI3 TRBO

(/TRCIOC) AN11/LVCOUT1

18 P1_2 KI2 (TRCIOB) AN10/LVREF

19 P1_1 KI1 (TRCIOA/

TRCTRG) AN9/LVCMP2

20 P1_0 KI0 (TRCIOD) AN8/LVCMP1

R8C/32A Group 1. Overview REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 8 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

1.5 Pin Functions

Tables 1.5 and 1.6 list Pin Functions. I: Input O: Output I/O: Input and output Notes: 1. Refer to the oscillator manufacturer for oscillation characteristics. 2. To use an externally generated clock, input it to XOUT. Table 1.5 Pin Functions (1) Item Pin Name I/O Type Description Power supply input VCC, VSS − Apply 1.8 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin. Analog power supply input AVCC, AVSS − Power supply for the A/D converter. Connect a capacitor between AVCC and AVSS. Reset input RESET I Input “L” on this pin resets the MCU. MODE MODE I Connect this pin to VCC via a resistor. XIN clock input XIN I These pins are provid ed for XIN clock generation circuit I/O. Connect a ceramic resonator or a crystal oscillator between the XIN and XOUT pins (1). To use an external clock, input it to the XOUT pin and leave the XIN pin open.XIN clock output XOUT I/O (2) XCIN clock input XCIN I These pins are provided for XCIN clock generation circuit I/O. Connect a crystal oscillator between the XCIN and XCOUT pins (1). To use an external clock, input it to the XCIN pin and leave the XCOUT pin open. XCIN clock output XCOUT O INT interrupt input INT0 , INT1, INT3 II N T interrupt input pins. INT0 is timer RB, and RC input pin. Key input interrupt KI0 to KI3 I Key input interrupt input pins Timer RA TRAIO I/O Timer RA I/O pin TRAO O Timer RA output pin Timer RB TRBO O Timer RB output pin Timer RC TRCCLK I External clock input pin TRCTRG I External trigger input pin TRCIOA, TRCIOB, TRCIOC, TRCIOD I/O Timer RC I/O pins Serial interface CLK0, CLK2 I/O Transfer clock I/O pins RXD0, RXD2 I Serial data input pins TXD0, TXD2 O Serial data output pins CTS2 I Transmission control input pin RTS2 O Reception control output pin SCL2 I/O I2C mode clock I/O pin SDA2 I/O I2C mode data I/O pin I2C bus SCL I/O Clock I/O pin SDA I/O Data I/O pin SSU SSI I/O Data I/O pin SCS I/O Chip-select signal I/O pin SSCK I/O Clock I/O pin SSO I/O Data I/O pin

R8C/32A Group 1. Overview REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 9 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. I: Input O: Output I/O: Input and output Table 1.6 Pin Functions (2) Item Pin Name I/O Type Description Reference voltage input VREF I Reference voltage input pin to A/D converter A/D converter AN8 to AN11 I Analog input pins to A/D converter ADTRG I AD external trigger input pin Comparator A LVCMP1, LVCMP2 I Comparator A analog voltage input pins LVREF I Comparator A reference voltage input pin LVCOUT1, LVCOUT2 O Comparator A output pins Comparator B IVCMP1, IVCMP3 I Comparator B analog voltage input pins IVREF1, IVREF3 I Comparator B reference voltage input pins Voltage detection circuit LVCMP2 I Detection voltage input pin for voltage detection 2 I/O port P1_0 to P1_7, P3_3 to P3_5, P3_7, P4_5 to P4_7 I/O CMOS I/O ports. Each port has an I/O select direction register, allowing each pin in the port to be directed for input or output individually. Any port set to input can be set to use a pull-up resistor or not by a program. All ports can be used as LED drive ports. Input port P4_2 I Input-only port

R8C/32A Group 2. Central Processing Unit (CPU) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 11 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

2.1 Data Registers (R 0, R1, R2, and R3)

R0 is a 16-bit register for transfer, ar ithmetic, and logic operations. The same applies to R1 to R3. R0 can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is analogous to R2R0.

2.2 Address Registers (A0 and A1)

A0 is a 16-bit register for address register indirect addr essing and address register relative addressing. It is also used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32- bit address register (A1A0).

2.3 Frame Base Register (FB)

FB is a 16-bit register for FB relative addressing.

2.4 Interrupt Table Register (INTB)

INTB is a 20-bit register that indicates the starting address of an interrupt vector table.

2.5 Program Counter (PC)

PC is 20 bits wide and indicates the address of the next instruction to be executed.

2.6 User Stack Pointer (USP) a nd Interrupt Stack Pointer (ISP)

The stack pointers (SP), USP and ISP, are each 16 bits wide. The U flag of FLG is used to switch between USP and ISP.

2.7 Static Base Register (SB)

SB is a 16-bit register for SB relative addressing.

2.8 Flag Register (FLG)

FLG is an 11-bit register indicating the CPU state.

2.8.1 Carry Flag (C)

The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.

2.8.2 Debug Flag (D)

The D flag is for debugging only. Set it to 0.

2.8.3 Zero Flag (Z)

The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.

2.8.4 Sign Flag (S)

The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.

2.8.5 Register Bank Select Flag (B)

Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.

2.8.6 Overflow Flag (O)

The O flag is set to 1 when an operation results in an overflow; otherwise to 0.

R8C/32A Group 2. Central Processing Unit (CPU) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 12 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

2.8.7 Interrupt Enable Flag (I)

The I flag enables maskable interrupts. Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0 when an interrupt request is acknowledged.

2.8.8 Stack Pointer Select Flag (U)

ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1. The U flag is set to 0 when a hardware interrupt requ est is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed.

2.8.9 Processor Interrupt Priority Level (IPL)

IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has higher priority than IPL, the interrupt is enabled.

2.8.10 Reserved Bit

If necessary, set to 0. When read, the content is undefined.

R8C/32A Group 3. Memory REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 13 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 3. Memory

3.1 R8C/32A Group

Figure 3.1 is a Memory Map of R8C/32A Group. The R8C/32A Group has a 1-Mbyte address space from addresses 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a 16-Kbyte internal ROM area is allocated addresses 0C000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt routine is stored here. The internal ROM (data flash) is allocated addresses 03000h to 03FFFh. The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 1.5-Kbyte internal RAM area is allocated addresses 00400h to 009FFh. The internal RAM is used not only for data storage but also as a stack area when a subroutine is called or when an interrupt request is acknowledged. Special function registers (SFRs) are allocated addres ses 00000h to 002FFh and 02C0 0h to 02FFFh. Peripheral function control registers are allocated here. All unallocated spaces within the SFRs are reserved and cannot be accessed by users. Figure 3.1 Memory Map of R8C/32A Group 0FFFFh 0FFDCh Notes: 1. Data flash indicates block A (1 Kbyte), block B (1 Kbyte), block C (1 Kbyte), and block D (1 Kbyte). 2. The blank areas are reserved and cannot be accessed by users. FFFFFh 0FFFFh 0YYYYh 0XXXXh 00400h 002FFh 00000h Internal ROM (program ROM) Internal RAM SFR (Refer to 4. Special Function Registers (SFRs)) 02FFFh 02C00h SFR (Refer to 4. Special Function Registers (SFRs)) ZZZZZh Internal ROM (program ROM) 03FFFh 03000h Internal ROM (data flash) (1) 0FFD8h Reserved area Undefined instruction Overflow BRK instruction Address match Single step Watchdog timer, oscillation stop detection, voltage monitor (Reserved) (Reserved) Reset Part Number R5F21321ANFP, R5F21321ADFP R5F21322ANFP, R5F21322ADFP R5F21324ANFP, R5F21324ADFP Internal ROM Internal RAM Size Address 0YYYYh Size Address 0XXXXhAddress ZZZZZh

4 Kbytes

8 Kbytes

16 Kbytes

1 Kbyte

1.5 Kbytes

R8C/32A Group 4. Special Function Registers (SFRs) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 14 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 4. Special Function Registers (SFRs) An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.12 list the special function registers. Table 4.1 SFR Information (1) (1) X: Undefined Notes: 1. The blank areas are reserved an d cannot be accessed by users. 2. The CWR bit in the RSTFR register is set to 0 after power-on and voltage monitor 0 reset. Software reset, watchdog timer rese t, or oscillation stop detection reset does not affect this bit. 3. The CSPROINI bit in the OFS register is set to 0. 4. The LVDAS bit in the OFS register is set to 1. 5. The LVDAS bit in the OFS register is set to 0. Address Register Symbol After Reset 0000h 0001h 0002h 0003h 0004h Processor Mode Register 0 PM0 00h 0005h Processor Mode Register 1 PM1 00h 0006h System Clock Control Register 0 CM0 00101000b 0007h System Clock Control Register 1 CM1 00100000b 0008h Module Standby Control Register MSTCR 00h 0009h System Clock Control Register 3 CM3 00h 000Ah Protect Register PRCR 00h 000Bh Reset Source Determination Register RSTFR 0XXX00XXb (2) 000Ch Oscillation Stop Detection Register OCD 00000100b 000Dh Watchdog Timer Reset Register WDTR XXh 000Eh Watchdog Timer Start Register WDTS XXh 000Fh Watchdog Timer Control Register WDTC 00111111b 0010h 0011h 0012h 0013h 0014h 0015h High-Speed On-Chip Oscillator Control Register 7 FRA7 When shipping 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch Count Source Protection Mode Register CSPR 00h 10000000b (3) 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h High-Speed On-Chip Oscillator Control Register 0 FRA0 00h 0024h High-Speed On-Chip Oscillator Control Register 1 FRA1 When shipping 0025h High-Speed On-Chip Oscillator Control Register 2 FRA2 00h 0026h On-Chip Reference Voltage Control Register OCVREFCR 00h 0027h 0028h Clock Prescaler Reset Flag CPSRF 00h 0029h High-Speed On-Chip Oscillator Control Register 4 FRA4 When Shipping 002Ah High-Speed On-Chip Oscillator Control Register 5 FRA5 When Shipping 002Bh High-Speed On-Chip Oscillator Control Register 6 FRA6 When Shipping 002Ch 002Dh 002Eh 002Fh High-Speed On-Chip Oscillator Control Register 3 FRA3 When shipping 0030h Voltage Monitor Circuit / Comparator A Control Register CMPA 00h 0031h Voltage Monitor Circuit Edge Select Register VCAC 00h 0032h 0033h Voltage Detect Register 1 VCA1 00001000b 0034h Voltage Detect Register 2 VCA2 00h (4) 00100000b (5) 0035h 0036h Voltage Detection 1 Level Select Register VD1LS 00000111b 0037h 0038h Voltage Monitor 0 Circuit Control Register VW0C 1100X010b (4) 1100X011b (5) 0039h Voltage Monitor 1 Circuit Control Register VW1C 10001010b

R8C/32A Group 4. Special Function Registers (SFRs) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 15 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Table 4.2 SFR Information (2) (1) X: Undefined Notes: 1. The blank areas are reserved an d cannot be accessed by users. 2. Selectable by the IICSEL bit in the SSUIICSR register. Address Register Symbol After Reset 003Ah Voltage Monitor 2 Circuit Control Register VW2C 10000010b 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h Flash Memory Ready Interrupt Control Register FMRDYIC XXXXX000b 0042h 0043h 0044h 0045h 0046h 0047h Timer RC Interrupt Control Register TRCIC XXXXX000b 0048h 0049h 004Ah Timer RE Interrupt Control Register TREIC XXXXX000b 004Bh UART2 Transmit Interrupt Control Register S2TIC XXXXX000b 004Ch UART2 Receive Interrupt Control Register S2RIC XXXXX000b 004Dh Key Input Interrupt Control Register KUPIC XXXXX000b 004Eh A/D Conversion Interrupt Control Register ADIC XXXXX000b 004Fh SSU Interrupt Control Register / IIC bus Interrupt Control Register (2) SSUIC / IICIC XXXXX000b 0050h 0051h UART0 Transmit Interrupt Control Register S0TIC XXXXX000b 0052h UART0 Receive Interrupt Control Register S0RIC XXXXX000b 0053h 0054h 0055h 0056h Timer RA Interrupt Control Register TRAIC XXXXX000b 0057h 0058h Timer RB Interrupt Control Register TRBIC XXXXX000b 0059h INT1 Interrupt Control Register INT1IC XX00X000b 005Ah INT3 Interrupt Control Register INT3IC XX00X000b 005Bh 005Ch 005Dh INT0 Interrupt Control Register INT0IC XX00X000b 005Eh UART2 Bus Collision Detection Interrupt Control Register U2BCNIC XXXXX000b 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h Voltage Monitor 1 / Compare A1 Interrupt Control Register VCMP1IC XXXXX000b 0073h Voltage Monitor 2 / Compare A2 Interrupt Control Register VCMP2IC XXXXX000b 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh

R8C/32A Group 4. Special Function Registers (SFRs) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 16 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Table 4.3 SFR Information (3) (1) X: Undefined Note: 1. The blank areas are reserved an d cannot be accessed by users. Address Register Symbol After Reset 0080h DTC Activation Control Register DTCTL 00h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h DTC Activation Enable Register 0 DTCEN0 00h 0089h DTC Activation Enable Register 1 DTCEN1 00h 008Ah DTC Activation Enable Register 2 DTCEN2 00h 008Bh DTC Activation Enable Register 3 DTCEN3 00h 008Ch 008Dh DTC Activation Enable Register 5 DTCEN5 00h 008Eh DTC Activation Enable Register 6 DTCEN6 00h 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h UART0 Transmit / Receive Mode Register U0MR 00h 00A1h UART0 Bit Rate Register U0BRG XXh 00A2h UART0 Transmit Buffer Register U0TB XXh 00A3h XXh 00A4h UART0 Transmit / Receive Control Register 0 U0C0 00001000b 00A5h UART0 Transmit / Receive Control Register 1 U0C1 00000010b 00A6h UART0 Receive Buffer Register U0RB XXh 00A7h XXh 00A8h UART2 Transmit / Receive Mode Register U2MR 00h 00A9h UART2 Bit Rate Register U2BRG XXh 00AAh UART2 Transmit Buffer Register U2TB XXh 00ABh XXh 00ACh UART2 Transmit / Receive Control Register 0 U2C0 00001000b 00ADh UART2 Transmit / Receive Control Register 1 U2C1 00000010b 00AEh UART2 Receive Buffer Register U2RB XXh 00AFh XXh 00B0h UART2 Digital Filter Function Select Register URXDF 00h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh UART2 Special Mode Register 5 U2SMR5 00h 00BCh UART2 Special Mode Register 4 U2SMR4 00h 00BDh UART2 Special Mode Register 3 U2SMR3 000X0X0Xb 00BEh UART2 Special Mode Register 2 U2SMR2 X0000000b 00BFh UART2 Special Mode Register U2SMR X0000000b

R8C/32A Group 4. Special Function Registers (SFRs) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 17 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Table 4.4 SFR Information (4) (1) X: Undefined Note: 1. The blank areas are reserved an d cannot be accessed by users. Address Register Symbol After Reset 00C0h A/D Register 0 AD0 XXXh 000000XXb00C1h 00C2h A/D Register 1 AD1 XXh 00C3h 000000XXb 00C4h A/D Register 2 AD2 XXh 00C5h 000000XXb 00C6h A/D Register 3 AD3 XXh 00C7h 000000XXb 00C8h A/D Register 4 AD4 XXh 00C9h 000000XXb 00CAh A/D Register 5 AD5 XXh 00CBh 000000XXb 00CCh A/D Register 6 AD6 XXh 00CDh 000000XXb 00CEh A/D Register 7 AD7 XXh 00CFh 000000XXb 00D0h 00D1h 00D2h 00D3h 00D4h A/D Mode Register ADMOD 00h 00D5h A/D Input Select Register ADINSEL 11000000b 00D6h A/D Control Register 0 ADCON0 00h 00D7h A/D Control Register 1 ADCON1 00h 00D8h 00D9h 00DAh 00DBh 00DCh 00DDh 00DEh 00DFh 00E0h 00E1h Port P1 Register P1 XXh 00E2h 00E3h Port P1 Direction Register PD1 00h 00E4h 00E5h Port P3 Register P3 XXh 00E6h 00E7h Port P3 Direction Register PD3 00h 00E8h Port P4 Register P4 XXh 00E9h 00EAh Port P4 Direction Register PD4 00h 00EBh 00ECh 00EDh 00EEh 00EFh 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh

R8C/32A Group 4. Special Function Registers (SFRs) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 18 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Table 4.5 SFR Information (5) (1) Note: 1. The blank areas are reserved an d cannot be accessed by users. Address Register Symbol After Reset 0100h Timer RA Control Register TRACR 00h 0101h Timer RA I/O Control Register TRAIOC 00h 0102h Timer RA Mode Register TRAMR 00h 0103h Timer RA Prescaler Register TRAPRE FFh 0104h Timer RA Register TRA FFh 0105h LIN Control Register 2 LINCR2 00h 0106h LIN Control Register LINCR 00h 0107h LIN Status Register LINST 00h 0108h Timer RB Control Register TRBCR 00h 0109h Timer RB One-Shot Control Register TRBOCR 00h 010Ah Timer RB I/O Control Register TRBIOC 00h 010Bh Timer RB Mode Register TRBMR 00h 010Ch Timer RB Prescaler Register TRBPRE FFh 010Dh Timer RB Secondary Register TRBSC FFh 010Eh Timer RB Primary Register TRBPR FFh 010Fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h Timer RE Second Data Register / Counter Data Register TRESEC 00h 0119h Timer RE Minute Data Register / Compare Data Register TREMIN 00h 011Ah Timer RE Hour Data Register TREHR 00h 011Bh Timer RE Day of Week Data Register TREWK 00h 011Ch Timer RE Control Register 1 TRECR1 00h 011Dh Timer RE Control Register 2 TRECR2 00h 011Eh Timer RE Count Source Select Register TRECSR 00001000b 011Fh 0120h Timer RC Mode Register TRCMR 01001000b 0121h Timer RC Control Register 1 TRCCR1 00h 0122h Timer RC Interrupt Enable Register TRCIER 01110000b 0123h Timer RC Status Register TRCSR 01110000b 0124h Timer RC I/O Control Register 0 TRCIOR0 10001000b 0125h Timer RC I/O Control Register 1 TRCIOR1 10001000b 0126h Timer RC Counter TRC 00h 0127h 00h 0128h Timer RC General Register A TRCGRA FFh 0129h FFh 012Ah Timer RC General Register B TRCGRB FFh 012Bh FFh 012Ch Timer RC General Register C TRCGRC FFh 012Dh FFh 012Eh Timer RC General Register D TRCGRD FFh 012Fh FFh 0130h Timer RC Control Register 2 TRCCR2 00011000b 0131h Timer RC Digital Filter Function Select Register TRCDF 00h 0132h Timer RC Output Master Enable Register TRCOER 0 1111111b 0133h Timer RC Trigger Control Register TRCADCR 00h 0134h 0135h 0136h 0137h 0138h 0139h 013Ah 013Bh 013Ch 013Dh 013Eh 013Fh

R8C/32A Group 4. Special Function Registers (SFRs) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 19 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Table 4.6 SFR Information (6) (1) X: Undefined Note: 1. The blank areas are reserved an d cannot be accessed by users. Address Register Symbol After Reset 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014Ah 014Bh 014Ch 014Dh 014Eh 014Fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015Ah 015Bh 015Ch 015Dh 015Eh 015Fh 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016Ah 016Bh 016Ch 016Dh 016Eh 016Fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017Ah 017Bh 017Ch 017Dh 017Eh 017Fh

R8C/32A Group 4. Special Function Registers (SFRs) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 20 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Table 4.7 SFR Information (7) (1) X: Undefined Notes: 1. The blank areas are reserved an d cannot be accessed by users. 2. Selectable by the IICSEL bit in the SSUIICSR register. Address Register Symbol After Reset 0180h Timer RA Pin Select Register TRASR 00h 0181h Timer RC Pin Select Register TRBRCSR 00h 0182h Timer RC Pin Select Register 0 TRCPSR0 00h 0183h Timer RC Pin Select Register 1 TRCPSR1 00h 0184h 0185h 0186h 0187h 0188h UART0 Pin Select Register U0SR 00h 0189h 018Ah UART2 Pin Select Register 0 U2SR0 00h 018Bh UART2 Pin Select Register 1 U2SR1 00h 018Ch SSU / IIC Pin Select Register SSUIICSR 00h 018Dh 018Eh INT Interrupt Input Pin Select Register INTSR 00h 018Fh 0190h 0191h 0192h 0193h SS Bit Counter Register SSBR 1111 1000b 0194h SS Transmit Data Register L / IIC bus Transmit Data Register (2) SSTDR / ICDRT FFh 0195h SS Transmit Data Register H SSTDRH FFh 0196h SS Receive Data Register L / IIC bus Receive Data Register (2) SSRDR / ICDRR FFh 0197h SS Receive Data Register H (2) SSRDRH FFh 0198h SS Control Register H / IIC bus Control Register 1 (2) SSCRH / ICCR1 00h 0199h SS Control Register L / IIC bus Control Register 2 (2) SSCRL / ICCR2 0 1111101b 019Ah SS Mode Register / IIC bus Mode Register (2) SSMR / ICMR 00011000b 019Bh SS Enable Register / IIC bus Interrupt Enable Register (2) SSER / ICIER 00h 019Ch SS Status Register / IIC bus Status Register (2) SSSR / ICSR 00h / 0000X000b 019Dh SS Mode Register 2 / Slave Address Register (2) SSMR2 / SAR 00h 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 01ABh 01ACh 01ADh 01AEh 01AFh 01B0h 01B1h 01B2h Flash Memory Status Register FST 10000X00b 01B3h 01B4h Flash Memory Control Register 0 FMR0 00h 01B5h Flash Memory Control Register 1 FMR1 00h 01B6h Flash Memory Control Register 2 FMR2 00h 01B7h 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh 01BFh

R8C/32A Group 4. Special Function Registers (SFRs) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 21 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Table 4.8 SFR Information (8) (1) X: Undefined Note: 1. The blank areas are reserved an d cannot be accessed by users. Address Register Symbol After Reset 01C0h Address Match Interrupt Register 0 RMAD0 XXh 01C1h XXh 01C2h 0000XXXXb 01C3h Address Match Interrupt Enable Register 0 AIER0 00h 01C4h Address Match Interrupt Register 1 RMAD1 XXh 01C5h XXh 01C6h 0000XXXXb 01C7h Address Match Interrupt Enable Register 1 AIER1 00h 01C8h 01C9h 01CAh 01CBh 01CCh 01CDh 01CEh 01CFh 01D0h 01D1h 01D2h 01D3h 01D4h 01D5h 01D6h 01D7h 01D8h 01D9h 01DAh 01DBh 01DCh 01DDh 01DEh 01DFh 01E0h Pull-Up Control Register 0 PUR0 00h 01E1h Pull-Up Control Register 1 PUR1 00h 01E2h 01E3h 01E4h 01E5h 01E6h 01E7h 01E8h 01E9h 01EAh 01EBh 01ECh 01EDh 01EEh 01EFh 01F0h Port P1 Drive Capacity Control Register P1DRR 00h 01F1h 01F2h Drive Capacity Control Register 0 DRR0 00h 01F3h Drive Capacity Control Register 1 DRR1 00h 01F4h 01F5h Input Threshold Control Register 0 VLT0 00h 01F6h Input Threshold Control Register 1 VLT1 00h 01F7h 01F8h Comparator B Control Register 0 INTCMP 00h 01F9h 01FAh External Input Enable Register 0 INTEN 00h 01FBh 01FCh INT Input Filter Select Register 0 INTF 00h 01FDh 01FEh Key Input Enable Register 0 KIEN 00h 01FFh

R8C/32A Group 4. Special Function Registers (SFRs) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 22 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Table 4.9 SFR Information (9) (1) X: Undefined Note: 1. The blank areas are reserved an d cannot be accessed by users. Address Register Symbol After Reset 2C00h DTC Transfer Vector Area XXh 2C01h DTC Transfer Vector Area XXh 2C02h DTC Transfer Vector Area XXh 2C03h DTC Transfer Vector Area XXh 2C04h DTC Transfer Vector Area XXh 2C05h DTC Transfer Vector Area XXh 2C06h DTC Transfer Vector Area XXh 2C07h DTC Transfer Vector Area XXh 2C08h DTC Transfer Vector Area XXh 2C09h DTC Transfer Vector Area XXh 2C0Ah DTC Transfer Vector Area XXh : DTC Transfer Vector Area XXh : DTC Transfer Vector Area XXh 2C3Ah DTC Transfer Vector Area XXh 2C3Bh DTC Transfer Vector Area XXh 2C3Ch DTC Transfer Vector Area XXh 2C3Dh DTC Transfer Vector Area XXh 2C3Eh DTC Transfer Vector Area XXh 2C3Fh DTC Transfer Vector Area XXh 2C40h DTC Control Data 0 DTCD0 XXh 2C41h XXh 2C42h XXh 2C43h XXh 2C44h XXh 2C45h XXh 2C46h XXh 2C47h XXh 2C48h DTC Control Data 1 DTCD1 XXh 2C49h XXh 2C4Ah XXh 2C4Bh XXh 2C4Ch XXh 2C4Dh XXh 2C4Eh XXh 2C4Fh XXh 2C50h DTC Control Data 2 DTCD2 XXh 2C51h XXh 2C52h XXh 2C53h XXh 2C54h XXh 2C55h XXh 2C56h XXh 2C57h XXh 2C58h DTC Control Data 3 DTCD3 XXh 2C59h XXh 2C5Ah XXh 2C5Bh XXh 2C5Ch XXh 2C5Dh XXh 2C5Eh XXh 2C5Fh XXh 2C60h DTC Control Data 4 DTCD4 XXh 2C61h XXh 2C62h XXh 2C63h XXh 2C64h XXh 2C65h XXh 2C66h XXh 2C67h XXh 2C68h DTC Control Data 5 DTCD5 XXh 2C69h XXh 2C6Ah XXh 2C6Bh XXh 2C6Ch XXh 2C6Dh XXh 2C6Eh XXh 2C6Fh XXh

R8C/32A Group 4. Special Function Registers (SFRs) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 23 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Table 4.10 SFR Information (10) (1) X: Undefined Note: 1. The blank areas are reserved an d cannot be accessed by users. Address Register Symbol After Reset 2C70h DTC Control Data 6 DTCD6 XXh 2C71h XXh 2C72h XXh 2C73h XXh 2C74h XXh 2C75h XXh 2C76h XXh 2C77h XXh 2C78h DTC Control Data 7 DTCD7 XXh 2C79h XXh 2C7Ah XXh 2C7Bh XXh 2C7Ch XXh 2C7Dh XXh 2C7Eh XXh 2C7Fh XXh 2C80h DTC Control Data 8 DTCD8 XXh 2C81h XXh 2C82h XXh 2C83h XXh 2C84h XXh 2C85h XXh 2C86h XXh 2C87h XXh 2C88h DTC Control Data 9 DTCD9 XXh 2C89h XXh 2C8Ah XXh 2C8Bh XXh 2C8Ch XXh 2C8Dh XXh 2C8Eh XXh 2C8Fh XXh 2C90h DTC Control Data 10 DTCD10 XXh 2C91h XXh 2C92h XXh 2C93h XXh 2C94h XXh 2C95h XXh 2C96h XXh 2C97h XXh 2C98h DTC Control Data 11 DTCD11 XXh 2C99h XXh 2C9Ah XXh 2C9Bh XXh 2C9Ch XXh 2C9Dh XXh 2C9Eh XXh 2C9Fh XXh 2CA0h DTC Control Data 12 DTCD12 XXh 2CA1h XXh 2CA2h XXh 2CA3h XXh 2CA4h XXh 2CA5h XXh 2CA6h XXh 2CA7h XXh 2CA8h DTC Control Data 13 DTCD13 XXh 2CA9h XXh 2CAAh XXh 2CABh XXh 2CACh XXh 2CADh XXh 2CAEh XXh 2CAFh XXh

R8C/32A Group 4. Special Function Registers (SFRs) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 24 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Table 4.11 SFR Information (11) (1) X: Undefined Note: 1. The blank areas are reserved an d cannot be accessed by users. Address Register Symbol After Reset 2CB0h DTC Control Data 14 DTCD14 XXh 2CB1h XXh 2CB2h XXh 2CB3h XXh 2CB4h XXh 2CB5h XXh 2CB6h XXh 2CB7h XXh 2CB8h DTC Control Data 15 DTCD15 XXh 2CB9h XXh 2CBAh XXh 2CBBh XXh 2CBCh XXh 2CBDh XXh 2CBEh XXh 2CBFh XXh 2CC0h DTC Control Data 16 DTCD16 XXh 2CC1h XXh 2CC2h XXh 2CC3h XXh 2CC4h XXh 2CC5h XXh 2CC6h XXh 2CC7h XXh 2CC8h DTC Control Data 17 DTCD17 XXh 2CC9h XXh 2CCAh XXh 2CCBh XXh 2CCCh XXh 2CCDh XXh 2CCEh XXh 2CCFh XXh 2CD0h DTC Control Data 18 DTCD18 XXh 2CD1h XXh 2CD2h XXh 2CD3h XXh 2CD4h XXh 2CD5h XXh 2CD6h XXh 2CD7h XXh 2CD8h DTC Control Data 19 DTCD19 XXh 2CD9h XXh 2CDAh XXh 2CDBh XXh 2CDCh XXh 2CDDh XXh 2CDEh XXh 2CDFh XXh 2CE0h DTC Control Data 20 DTCD20 XXh 2CE1h XXh 2CE2h XXh 2CE3h XXh 2CE4h XXh 2CE5h XXh 2CE6h XXh 2CE7h XXh 2CE8h DTC Control Data 21 DTCD21 XXh 2CE9h XXh 2CEAh XXh 2CEBh XXh 2CECh XXh 2CEDh XXh 2CEEh XXh 2CEFh XXh

R8C/32A Group 4. Special Function Registers (SFRs) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 25 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Table 4.12 SFR Information (12) (1) X: Undefined Notes: 1. The blank areas are reserved an d cannot be accessed by users. 2. This register cannot be changed by a program . Use a flash programmer to write to it. Address Register Symbol After Reset 2CF0h DTC Control Data 22 DTCD22 XXh 2CF1h XXh 2CF2h XXh 2CF3h XXh 2CF4h XXh 2CF5h XXh 2CF6h XXh 2CF7h XXh 2CF8h DTC Control Data 23 DTCD23 XXh 2CF9h XXh 2CFAh XXh 2CFBh XXh 2CFCh XXh 2CFDh XXh 2CFEh XXh 2CFFh XXh 2D00h 2D01h FFDBh Option Function Select Register 2 OFS2 (Note 2) FFFFh Option Function Select Register OFS (Note 2)

R8C/32A Group 5. Resets REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 26 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 5. Resets The following resets are implem ented: hardware reset, power-on reset, volt age monitor 0 reset, watchdog timer reset, and software reset. Table 5.1 lists the Reset Names and Sources and Figure 5.1 shows the Block Diagram of Reset Circuit. Figure 5.1 Block Diagram of Reset Circuit Table 5.1 Reset Names and Sources Reset Name Source Hardware reset Input voltage of RESET pin is held “L” Power-on reset VCC rises Voltage monitor 0 reset VCC falls (monitor voltage: Vdet0) Watchdog timer reset Underflow of watchdog timer Software reset Write 1 to PM03 bit in PM0 register RESET Power-on reset circuit Voltage detection circuit Watchdog timer CPU Pin, CPU, and SFR VCC Hardware reset Power-on reset Voltage monitor 0 reset Watchdog timer reset Software reset Note: 1. The CWR bit in the RSTFR register is set to 0 (cold start-up) after power-on or voltage monitor 0 reset. This bit remains unchanged at a software reset, watchdog timer reset, or oscillation detection reset.

R8C/32A Group 5. Resets REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 28 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

5.1 Registers

5.1.1 Processor Mode Register 0 (PM0)

Set the PRC1 bit in the PRCR register to 1 (write enabled) before rewriting the PM0 register.

5.1.2 Reset Source Determina tion Register (RSTFR)

Notes: 1. The CWR bit is set to 0 (cold start-up) after power-on or voltage monitor 0 reset. This bit remains unchanged at a software reset, or watchdog timer reset. 2. If 1 is written to the CWR bit by a program, it is set to 1. (Writing 0 does not affect this bit.) 3. When the VW0C0 bit in the VW0C register is set to 0 (voltage monitor 0 reset disabled), the CWR bit value is undefined. Address 0004h B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 — Reserved bits Set to 0. R/W b1 — b2 — b3 PM03 Software reset bit The MCU is reset when this bit is set to 1. When read, the content is 0. R/W b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b5 — b6 — b7 — Address 000Bh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — — WDR SWR HWR CWR After Reset 0 X X X 0 0 X X (Note 1) Bit Symbol Bit Name Function R/W b0 CWR Cold start-up/warm start-up determine flag (2, 3) 0: Cold start-up 1: Warm start-up R/W b1 HWR Hardware reset detect flag 0: Not detected 1: Detected R b2 SWR Software reset detect flag 0: Not detected 1: Detected R b3 WDR Watchdog timer reset detect flag 0: Not detected 1: Detected R b4 — Reserved bits When read, the content is undefined. R b5 — b6 — b7 — Reserved bit Set to 0. R/W

R8C/32A Group 5. Resets REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 29 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

5.1.3 Option Function Se lect Register (OFS)

Notes: 1. If the block including the OFS register is er ased, the OFS register value is set to FFh. 2. The same level of the voltage detection 0 level selected by bits VDSEL0 and VDESL1 is set in both functions of voltage monitor 0 reset and power-on reset. 3. To use power-on reset, set the LVDAS bit to 0 (voltage monitor 0 reset enabled after reset). The OFS register is allocated in the flash memory. Write to this register with a program. After writing, do not write additions to this register. LVDAS Bit (Voltage Detection 0 Circuit Start Bit) The Vdet0 voltage to be monitored by the voltage detection 0 circuit is selected by bits VDSEL0 and VDSEL1. Address 0FFFFh B i t b 7 b 6b 5b 4b 3b 2b 1b 0 Symbol CSPROINI LVDAS VDSEL1 VDSEL0 ROMCP1 ROMCR — WDTON W h e n s h i p p i n g 1 1111111 ( N o t e 1 ) Bit Symbol Bit Name Function R/W b0 WDTON Watchdog timer start select bit 0: Watchdog timer automatically starts after reset. 1: Watchdog timer is stopped after reset. R/W b1 — Reserved bit Set to 1. R/W b2 ROMCR ROM code protect disable bit 0: ROM code protect disabled 1: ROMCP1 bit enabled R/W b3 ROMCP1 ROM code protect bi t 0: ROM code protect enabled 1: ROM code protect disabled R/W b4 VDSEL0 Voltage detection 0 level select bit (2) b5 b4 0 0: 3.80 V selected (Vdet0_3) 0 1: 2.85 V selected (Vdet0_2) 1 0: 2.35 V selected (Vdet0_1) 1 1: 1.90 V selected (Vdet0_0) R/W b5 VDSEL1 R/W b6 LVDAS Voltage detection 0 circuit start bit (3) 0: Voltage monitor 0 reset enabled after reset 1: Voltage monitor 0 reset disabled after reset R/W b7 CSPROINI Count source protection mode after reset select bit 0: Count source protect mode enabled after reset 1: Count source protect mode disabled after reset R/W

R8C/32A Group 5. Resets REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 30 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

5.1.4 Option Function Sel ect Register 2 (OFS2)

Note: 1. If the block including the OFS2 register is erased, the OFS2 register value is set to FFh. The OFS2 register is located on the flash memory. Write to this register with a program. After writing, do not write additions to this register. Bits WDTRCS0 and WDTRCS1 (Watchdog Timer Refresh Acknowledgement Period Set Bit) Assuming that the period from when the watchdog timer starts counting until it underflows is 100%, the refresh acknowledgement period for the watchdog timer can be selected. For details, refer to 14.3.1.1 Refresh Acknowledgment Period. Address 0FFDBh B i t b 7 b 6 b 5 b 4 b 3b 2b 1b 0 Symbol — — — — WDTRCS1 WDTRCS0 WDTUFS1 WDTUFS0 When shipping 1 1 1 1 1 1 1 1 (Note 1) Bit Symbol Bit Name Function R/W b0 WDTUFS0 Watchdog timer underflow period set bit b1 b0 0 0: 03FFh 0 1: 0FFFh 1 0: 1FFFh 1 1: 3FFFh R/W b1 WDTUFS1 R/W b2 WDTRCS0 Watchdog timer refresh acknowledgement period set bit b3 b2 0 0: 25% 0 1: 50% 1 0: 75% 1 1: 100% R/W b3 WDTRCS1 R/W b4 — Reserved bits Set to 1. R/W b5 — b6 — b7 —

R8C/32A Group 5. Resets REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 31 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

5.2 Hardware Reset

A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the supply voltage meets the recommended operating conditions, pins, CPU, and SFRs are all reset (refer to Table 5.2 Pin Functions while RESET Pin Level is “L” ). When the input level applied to the RESET pin changes from “L” to “H”, a program is executed beginning with the address indicated by the reset vector. After reset, the low-speed on-chip oscillator clock with no division is automatically selected as the CPU clock. Refer to 4. Special Function Registers (SFRs) for the states of the SFRs after reset. The internal RAM is not reset. If the RESET pin is pulled “L” while writing to the internal RAM is in progress, the contents of internal RAM will be undefined. Figure 5.4 shows an Example of Hardware Reset Circuit and Operation and Figure 5.5 shows an Example of Hardware Reset Circuit (Usage Example of External Supply V oltage Detection Circuit) and Operation.

5.2.1 When Power Supply is Stable

(1) Apply “L” to the RESET pin. (2) Wait for 10 µs. (3) Apply “H” to the RESET pin.

5.2.2 Power On

(1) Apply “L” to the RESET pin. (2) Let the supply voltage increase until it meets the recommended operating conditions. (3) Wait for td(P-R) or more to allow the inte rnal power supply to stabilize (refer to 32. Electrical Characteristics). (4) Wait for 10 µs. (5) Apply “H” to the RESET pin.

R8C/32A Group 5. Resets REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 32 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 5.4 Example of Hardware Reset Circuit and Operation Figure 5.5 Example of Hardware Reset Circuit (Usage Example of External Supply Voltage Detection Circuit) and Operation RESET VCC VCC RESET 1.8 V 0 V

0.2 VCC or below

td(P-R) + 10 µs or more 0 V Note: 1. Refer to 32. Electrical Characteristics. RESET VCC VCC RESET 1.8 V 0 V 0 V 5 V 5 V Example when VCC = 5 V Supply voltage detection circuit Note: 1. Refer to 32. Electrical Characteristics. td(P-R) + 10 µs or more

R8C/32A Group 5. Resets REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 33 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

5.3 Power-On Reset Function

When the RESET pin is connected to the VCC pin via a pull-up resistor, and the VCC pin voltage level rises while the rise gradient is trth or more, the power-on reset function is enabled and the MCU resets its pins, CPU, and SFR. When a capacitor is connected to the RESET pin, too, always keep the voltage to the RESET pin 0.8VCC or more. When the input voltage to the VCC pin reaches the Vdet0 level or above, th e low-speed on-chip oscillator clock starts counting. When the low-speed on-chip oscillator cloc k count reaches 8, the internal reset signal is held “H” and the MCU enters the reset sequence (refer to Figure 5.3). The low-speed on-chip oscillator clock with no division is automatically selected as the CPU clock after reset. Refer to 4. Special Function Registers (SFRs) for the states of the SFR after power-on reset. After power-on reset, voltage monitor 0 reset is enabled when the LVDAS bit in the OFS register is set to 0 (voltage monitor 0 reset enabled after reset). Figure 5.6 shows an Example of Power-On Reset Circuit and Operation. Figure 5.6 Example of Power-On Reset Circuit and Operation RESET VCC 4.7 kΩ (reference) Notes: 1. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection Circuit for details. 2. Refer to 32. Electrical Characteristics. 3. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0, the VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register to 1. Vdet0 Vpor1 Internal reset signal (“L” valid) tw(por1) Vccmin External Power VCC trthtrth fOCO-S × 8 1 fOCO-S × 8

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5.4 Voltage Monitor 0 Reset

A reset is applied using the on-chip voltage detection 0 ci rcuit. The voltage detection 0 circuit monitors the input voltage to the VCC pin. The voltage to monitor is Vdet0. The Vdet0 voltage detection level can be changed by the settings of bits VDSEL0 to VDSEL1 in the OFS register. When the input voltage to the VCC pin reaches the Vdet0 level or below, the pins, CPU, and SFR are reset. When the input voltage to the VCC pin reaches the Vdet0 level or above, th e low-speed on-chip oscillator clock start counting. When th e low-speed on-chip oscillator cl ock count reaches 8, the intern al reset signal is held “H” and the MCU enters the reset sequence (refer to Figure 5.3). The low-speed on-chip oscillator clock with no division is automatically selected as the CPU clock after reset. The LVDAS bit in the OFS register can be used to select whether voltage monitor 0 re set is enabled or disabled after a reset. The setting of the LVDAS bit is enabled at all resets. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0, the VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register to Bits VDSEL0 to VDSEL1 and LVDAS cannot be changed by a program. To set these bits, write values to b4 to b6 of address 0FFFFh using a flash programmer. Refer to 5.1.3 Option Function Select Register (OFS) for details of the OFS register. Refer to 4. Special Function Registers (SFRs) for the status of the SFR after voltage monitor 0 reset. The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet0 level or below while writing to the internal RAM is in progress, the contents of internal RAM are undefined. Refer to 6. Voltage Detection Circuit for details of voltage monitor 0 reset. Figure 5.7 shows an Example of V oltage Monitor 0 Reset Circuit and Operation. Figure 5.7 Example of Voltage Monitor 0 Reset Circuit and Operation RESET VCC 4.7 kΩ (reference) VCC Vccmin Internal reset signal (“L” valid) Sampling time (1, 2) tw(Vdet0) fOCO-S × 8 Vdet0 Vpor1 Notes: 1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage range (1.8 V or above) during the sampling time. 2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit for details. 3. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection Circuit for details. 4. Refer to 32. Electrical Characteristics. 5. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0, the VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register to 1.

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5.5 Watchdog Timer Reset

When the PM12 bit in the PM1 register is set to 1 (reset when watchdog timer underflows), the MCU resets its pins, CPU, and SFR if the watchdog timer underflows. Then the program beginning with the address indicated by the reset vector is executed. After reset, the low-speed on- chip oscillator clock with no division is automatically selected as the CPU clock. Refer to 4. Special Function Registers (SFRs) for the states of the SFRs after watchdog timer reset. The internal RAM is not reset. When the watchdog timer underflows, the contents of internal RAM are undefined. The underflow period and refresh acknowledge period for the watchdog timer can be set by bits WDTUFS0 to WDTUFS1 and bits WDTRCS0 to WDTRCS1 in the OFS2 register, respectively. Refer to 14. Watchdog Timer for details of the watchdog timer.

5.6 Software Reset

When the PM03 bit in the PM0 register is set to 1 (MCU reset), the MCU resets its pins, CPU, and SFR. The program beginning with the address indicated by the reset vector is executed. After reset, the low-speed on-chip oscillator clock with no division is automatically selected for the CPU clock. Refer to 4. Special Function Registers (SFRs) for the states of the SFRs after software reset. The internal RAM is not reset.

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5.7 Cold Start-Up/Warm Start- Up Determination Function

The cold start-up/warm start-up determination function uses the CWR bit in the RSTFR register to determine cold start-up (reset process) at power-on and warm start-up (reset process) when a reset occurred during operation. The CWR bit is set to 0 (cold start-up) at power-on and also set to 0 at a voltage monitor 0 reset. If 1 is written to the CWR bit by a program, it is set to 1. This bit remains unchanged at a software reset, or watchdog timer reset. The cold start-up/warm stat-up determination function uses voltage monitor 0 reset. To set the bits associated with voltage monitor 0 reset, follow Table 6.3 Procedure for Setting Bits Associated with Voltage Monitor 0 Reset. Figure 5.8 shows an Operating Example of Cold Start-Up/Warm Start-Up Function Figure 5.8 Operating Example of Cold Start-Up/Warm Start-Up Function

5.8 Reset Source Determination Function

The RSTFR register can be used to de tect whether a hardware reset, softwa re reset, or watchdog timer reset has occurred. If a hardware reset occurs, the HWR bit is set to 1 (detected). If a software reset occurs, the SWR bit is set to 1 (detected). If a watchdog timer reset occurs, the WDR bit is set to 1 (detected). Set to 1 by a program. Vdet0 CWR bit in RSTFR register Voltage monitor 0 reset VCC Set to 1 by a program. The above applies when the digital filter is not used.

R8C/32A Group 6. Voltage Detection Circuit REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 37 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 6. Voltage Detection Circuit The voltage detection circuit monitors th e voltage input to the VCC pin. This circuit can be used to monitor the VCC input voltage by a program.

6.1 Overview

The detection voltage of voltage detection 0 can be selected among four levels using the OFS register. The detection voltage of voltage detection 1 can be selected among 16 levels using the VD1LS register. As a detection target, the voltage input to VCC and the LVCMP2 pin can be switched for voltage detection 2 only. The voltage monitor 0 reset, and voltage monitor 1 interrupt and voltage monitor 2 interrupt can also be used. Note that voltage monitor 1 and voltage monitor 2 share the voltage detection circuit with comparator A1 and comparator A2. Either voltage monito r 1 and voltage monitor 2 or compar ator A1 and comp arator A2 can be selected. Table 6.1 Voltage Detectio n Circuit Specifications Item Voltage Monitor 0 Voltage Monitor 1 Voltage Monitor 2 VCC monitor Voltage to monitor Vdet0 Vdet1 Vdet2 Detection target Whether passing through Vdet0 by falling Whether passing through Vdet1 by rising or falling Whether passing through Vdet2 by rising or falling The input voltage to VCC and the LVCMP2 pin can be switched by the VCA24 bit in the VCA2 register. Detection voltage Selectable among 4 levels using the OFS register. Selectable among 16 levels using the VD1LS register. The detection voltage level varies depending on when VCC is selected or when LVCMP2 is selected. Each value is set as the fixed level. Monitor None The VW1C3 bit in the VW1C register The VCA13 bit in the VCA1 register Whether VCC is higher or lower than Vdet1 Whether VCC or LVCMP2 input voltage is higher or lower than Vdet2 Process at voltage detection Reset Voltage monitor 0 reset None None Reset at Vdet0 > VCC; CPU operation restarts at VCC > Vdet0 Interrupts None Voltage monitor 1 interrupt Voltage monitor 2 interrupt Non-maskable or maskable selectable Non-maskable or maskable selectable Interrupt request at: Vdet1 > VCC and/or VCC > Vdet1 Interrupt request at: Vdet2 > VCC (LVCMP2) and/or VCC (LVCMP2) > Vdet2 Digital filter Switching enable/disable Supported Supported Supported Sampling time (fOCO-S divided by n) × 4 n: 1, 2, 4, and 8 (fOCO-S divided by n) × 2 n: 1, 2, 4, and 8 (fOCO-S divided by n) × 2 n: 1, 2, 4, and 8

R8C/32A Group 6. Voltage Detection Circuit REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 38 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 6.1 Voltage Detection Circuit Block Diagram Table 6.2 Pin Configuration of Voltage Detection Circuit Pin Name I/O Function LVCMP2 Input Detection target voltage pin for voltage detection 2 VCA25 ≥ Vdet2 Internal reference voltage VCA27 VCA26 VCC Voltage detection 1 signal VCA13 bit Voltage detection 2 signal Voltage detection 0 signal ≥ Vdet1 ≥ Vdet0 VCA1 register VW1C3 bit VW1C register Level Selection Circuit (16 levels) LVCMP2 VCA24 = 1 VCA24 = 0 VCA13: Bit in VCA1 register VCA24, VCA25, VCA26, VCA27: Bits in VCA2 register VW1C3: Bit in VW1C register VD1S0 to VD1S3: Bits in VD1LS register VDSEL0, VDSEL1: Bits in OFS register Shared with comparator A VD1S3 to VD1S0 Level Selection Circuit (4 levels) VDSEL1 to VDSEL0

R8C/32A Group 6. Voltage Detection Circuit REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 40 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 6.4 Block Diagram of Voltage Monitor 2 Interrupt Generation Circuit 1/2 1/2 1/2 Voltage detection 2 circuit VCA27 VCA13 When VCA27 bit is set to 0 (disabled), voltage detection 2 signal is driven high. Voltage detection 2 signal fOCO-S VW2F1 to VW2F0 = 00b = 01b = 10b = 11b VW2C2 bit is set to 0 (not detected) by writing 0 by a program. When VCA27 bit is set to 0 (voltage detection 2 circuit disabled), VW2C2 bit is set to 0. VW2C2 VW2C3 Watchdog timer block Watchdog timer underflow signal VW2C3 bit is set to 0 (not detected) by writing 0 by a program. COMPSEL IRQ2SEL Maskable interrupt signal Non-maskable interrupt signal Voltage monitor 2 interrupt signal Watchdog timer interrupt signal Comparator A2 interrupt signal Voltage monitor 2 interrupt generation circuit VW2C0 to VW2C3, VW2F0, VW2F1, VW2C6, VW2C7: Bits in VW2C VCA13: Bit in VCA1 register VCA23, VCA24, VCA27: Bits in VCA2 register COMPSEL, IRQ2SEL: Bits in CMPA register VCAC2: Bit in VCAC register LVCMP2 VCA24 = 1 VCA24 = 0 VCC VW2C1 = 0 VW2C1 = 1 Digital filter Edge selection circuit VW2C0 Internal reference voltage VCA23 = 0 VCAC2 VW2C6

R8C/32A Group 6. Voltage Detection Circuit REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 41 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

6.2 Registers

6.2.1 Voltage Monitor Ci rcuit/Comparator A Control Register (CMPA)

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol COMPSEL — IRQ2SEL IRQ1SEL CM2OE CM1OE CM2POR CM1POR A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 CM1POR LVCOUT1 output polarity select bit 0: Non-inverted comparator A1 comparison result is output to LVCOUT1. 1: Inverted comparator A1 comparison result is output to LVCOUT1. R/W b1 CM2POR LVCOUT2 output polarity select bit 0: Non-inverted Comparator A2 comparison result is output to LVCOUT2. 1: Inverted comparator A2 comparison result is output to LVCOUT2. R/W b2 CM1OE LVCOUT1 output enable bit 0: Output disabled 1: Output enabled R/W b3 CM2OE LVCOUT2 output enable bit 0: Output disabled 1: Output enabled R/W b4 IRQ1SEL Voltage monitor 1/comparator A1 interrupt type select bit 0: Non-maskable interrupt 1: Maskable interrupt R/W b5 IRQ2SEL Voltage monitor 2/comparator A2 interrupt type select bit 0: Non-maskable interrupt 1: Maskable interrupt R/W b6 — Reserved bit Set to 0. R/W b7 COMPSEL Voltage monitor/comparator A interrupt type selection enable bit 0: Bits IRQ1SEL and IRQ2SEL disabled 1: Bits IRQ1SEL and IRQ2SEL enabled R/W

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6.2.2 Voltage Monito r Circuit Edge Select Register (VCAC)

Notes: 1. When the VCA1 bit is set tot 0 (one edge), the VW1C7 bi t in the VW1C register is enabled. Set the VW1C7 bit after setting the VCAC1 bit to 0. 2. When the VCA2 bit is set tot 0 (one edge), the VW2C7 bi t in the VW2C register is enabled. Set the VW2C7 bit after setting the VCAC2 bit to 0.

6.2.3 Voltage Detect Register (VCA1)

Note: 1. When the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled), the VCA13 bit is enabled. When the VCA27 bit in the VCA2 register is set to 0 (voltage detection 2 circuit disabled), the VCA13 bit is set to 1 (VCC ≥ Vdet2). Address 0031h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — — — VCAC2 VCAC1 — A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b1 VCAC1 Voltage monitor 1 circuit edge select bit (1) 0: One edge 1: Both edges R/W b2 VCAC2 Voltage monitor 2 circuit edge select bit (2) 0: One edge 1: Both edges R/W b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b4 — b5 — b6 — b7 — Address 0033h B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00001000 Bit Symbol Bit Name Function R/W b0 — Reserved bits Set to 0. R/W b1 — b2 — b3 VCA13 Voltage detection 2 signal monitor flag (1) 0: VCC < Vdet2 1: VCC ≥ Vdet2 or voltage detection 2 circuit disabled R b4 — Reserved bits Set to 0. R/W b5 — b6 — b7 —

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6.2.4 Voltage Detect Register 2 (VCA2)

Notes: 1. Use the VCA20 bit only when the MCU enters wait mode. To set the VCA20 bit, follow the procedure shown in Figure 9.3 Procedure for Reducing Internal Power Consumption Using VCA20 bit. 2. When the VCA20 bit is set to 1 (low consumption enabled), do not set the CM10 bit in the CM1 register to 1 (stop mode). 3. To use voltage monitor 0 reset, set the VCA25 bit to 1. After the VCA25 bit is set to 1 from 0, allow td(E-A) to elapse before the voltage detection circuit starts operation. 4. To use the voltage detection 1/comparator A1 interrupt or the VW1C3 bit in the VW1C register, set the VCA26 bit to 1. After the VCA26 bit is set to 1 from 0, allow td(E-A) to elapse before the voltage detection 1/comparator A1 circuit starts operation. 5. To use the voltage detection 2/compar ator A2 interrupt or the VCAC13 bit in the VCA1 register, set the VCA27 bit to 1. After the VCA27 bit is set to 1 from 0, allow td(E-A) to elapse before the voltage detection 2/comparator A2 circuit starts operation. Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting the VCA2 register. Address 0034h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol VCA27 VCA26 VCA25 VCA24 VCA23 VCA22 VCA21 VCA20 After Reset The LVDAS bit in the OFS register is set to 1. 00000000 After Reset The LVDAS bit in the OFS register is set to 0. 00100000 Bit Symbol Bit Name Function R/W b0 VCA20 Internal power low consumption enable bit (1) 0: Low consumption disabled 1: Low consumption enabled (2) R/W b1 VCA21 Comparator A1 reference voltage input select bit 0: Internal reference voltage 1: LVREF pin input voltage R/W b2 VCA22 LVCMP1 comparison voltage external input select bit 0: Supply voltage (VCC) 1: LVCMP1 pin input voltage R/W b3 VCA23 Comparator A2 reference voltage input select bit 0: Internal reference voltage 1: LVREF pin input voltage R/W b4 VCA24 LVCMP2 comparison voltage external input select bit 0: Supply voltage (VCC) (Vdet2_0) 1: LVCMP2 pin input voltage (Vdet2_EXT) R/W b5 VCA25 Voltage detection 0 enable bit (3) 0: Voltage detection 0 circuit disabled 1: Voltage detection 0 circuit enabled R/W b6 VCA26 Voltage detection 1/comparator A1 enable bit (4) 0: Voltage detection 1/comparator A1 circuit disabled 1: Voltage detection 1/comparator A1 circuit enabled R/W b7 VCA27 Voltage detection 2/comparator A2 enable bit (5) 0: Voltage detection 2/comparator A2 circuit disabled 1: Voltage detection 2/comparator A2 circuit enabled R/W

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6.2.5 Voltage Detection 1 Leve l Select Register (VD1LS)

Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting the VD1LS register. Address 0036h B i t b 7b 6b 5b 4b 3b 2b 1b 0 S y m b o l ———— V D 1 S 3 V D 1 S 2 V D 1 S 1 V D 1 S 0 A f t e r R e s e t 00000111 Bit Symbol Bit Name Function R/W b0 VD1S0 Voltage detection 1 level select bit (Reference voltage when the voltage falls) b3 b2 b1 b0 0 0 0 0: 2.20 V (Vdet1_0) 0 0 0 1: 2.35 V (Vdet1_1) 0 0 1 0: 2.50 V (Vdet1_2) 0 0 1 1: 2.65 V (Vdet1_3) 0 1 0 0: 2.80 V (Vdet1_4) 0 1 0 1: 2.95 V (Vdet1_5) 0 1 1 0: 3.10 V (Vdet1_6) 0 1 1 1: 3.25 V (Vdet1_7) 1 0 0 0: 3.40 V (Vdet1_8) 1 0 0 1: 3.55 V (Vdet1_9) 1 0 1 0: 3.70 V (Vdet1_A) 1 0 1 1: 3.85 V (Vdet1_B) 1 1 0 0: 4.00 V (Vdet1_C) 1 1 0 1: 4.15 V (Vdet1_D) 1 1 1 0: 4.30 V (Vdet1_E) 1 1 1 1: 4.45 V (Vdet1_F) R/W b1 VD1S1 R/W b2 VD1S2 R/W b3 VD1S3 R/W b4 — Reserved bits Set to 0. R/W b5 — R/W b6 — R/W b7 — R/W

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6.2.6 Voltage Monitor 0 Circ uit Control Register (VW0C)

Note: 1. The VW0C0 bit is enabled when the VCA25 bit in the VCA2 register is set to 1 (voltage detection 0 circuit enabled). Set the VW0C0 bit to 0 (disabled) when the VCA25 bit in the VCA2 register is set to 0 (voltage detection 0 circuit disabled). To set the VW0C0 bit to 1 (enabled), follow the procedure in Table 6.3 Procedure for Setting Bits Associated with Voltage Monitor 0 Reset. Set the PRC3 bit in the PRCR register to 1 (write enabled) before writing the VW0C register. Address 0038h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — VW0F1 VW0F0 — — VW0C1 VW0C0 After Reset The LVDAS bit in the OFS register is set to 1. 1100X010 After Reset The LVDAS bit in the OFS register is set to 0. 1100X011 Bit Symbol Bit Name Function R/W b0 VW0C0 Voltage monitor 0 reset enable bit (1) 0: Disabled 1: Enabled R/W b1 VW0C1 Voltage monitor 0 digital filter disabled mode select bit 0: Digital filter enabled mode (digital filter circuit enabled) 1: Digital filter disabled mode (digital filter circuit disabled) R/W b2 — Reserved bit Set to 0. R/W b3 — Reserved bit When read, the content is undefined. R b4 VW0F0 Sampling clock select bit b5 b4 0 0: fOCO-S divided by 1 0 1: fOCO-S divided by 2 1 0: fOCO-S divided by 4 1 1: fOCO-S divided by 8 R/W b5 VW0F1 R/W b6 — Reserved bits Set to 1. R/W b7 — R/W

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6.2.7 Voltage Monitor 1 Circ uit Control Register (VW1C)

Notes: 1. The VW1C0 is enabled when the VCA26 bit in the VCA2 r egister is set to 1 (voltage detection 1 circuit enabled). Set the VW1C0 bit to 0 (disabled) when the VCA26 bit is set to 0 (voltage detection 1 circuit disabled). To set the VW0C0 bit to 1 (enabled), follow the procedure shown in Table 6.4 Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt. 2. To use the voltage monitor 1 interrupt to exit stop mode and to return again, write 0 and then 1 to the VW1C1 bit. 3. Bits VW1C2 and VW1C3 are enabled when the VCA26 bit in the VCA2 register is set to 1(voltage detection 1 circuit enabled). 4. Set the VW1C2 bit to 0 by a program. When 0 is written by a program, this bit is set to 0 (and remains unchanged even if 1 is written to it). 5. The VW1C7 bit is enabled when the VCAC1 bit in the VC AC register is set to 0 (one edge). After setting the VCAC1 bit to 0, set the VW1C7 bit. Set the PRC3 bit in the PRCR register to 1 (write enabled) before writing the VW1C register. Rewriting the VW1C register may set the VW1C2 bit to 1. Set the VW1C2 bit to 0 after rewriting the VW1C register. Address 0039h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol VW1C7 — VW1F1 VW1F0 VW1C3 VW1C2 VW1C1 VW1C0 A f t e r R e s e t 10001010 Bit Symbol Bit Name Function R/W b0 VW1C0 Voltage monitor 1 reset enable bit (1) 0: Disabled 1: Enabled R/W b1 VW1C1 Voltage monitor 0 digital filter disable mode select bit (2) 0: Digital filter enabled mode (digital filter circuit enabled) 1: Digital filter disable mode (digital filter circuit disabled) R/W b2 VW1C2 Voltage change detection flag (3, 4) 0: Not detected 1: Vdet1 passing detected R/W b3 VW1C3 Voltage detection 1 signal monitor flag (3) 0: VCC < Vdet1 1: VCC ≥ Vdet1 or voltage detection 1 circuit disabled R b4 VW1F0 Sampling clock select bit b5 b4 0 0: fOCO-S divided by 1 0 1: fOCO-S divided by 2 1 0: fOCO-S divided by 4 1 1: fOCO-S divided by 8 R/W b5 VW1F1 R/W b6 — Reserved bit Set to 1. R/W b7 VW1C7 Voltage monitor 1 reset generation condition select bit (5) 0: When VCC reaches Vdet1 or above. 1: When VCC reaches Vdet1 or below. R/W

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6.2.8 Voltage Monitor 2 Circ uit Control Register (VW2C)

Notes: 1. The VW2C0 is enabled when the VCA27 bit in the VCA2 r egister is set to 1 (voltage detection 2 circuit enabled). Set the VW2C0 bit to 0 (disabled) when the VCA27 bit is set to 0 (voltage detection 2 circuit disabled). To set the VW2C0 bit to 1 (enabled), follow the procedure shown in Table 6.5 Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt. 2. To use the voltage monitor 2 interrupt to exit stop mode and to return again, write 0 and then 1 to the VW2C1 bit. 3. The VW2C2 bit is enabled when the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled). 4. Set this bit to 0 by a program. When 0 is written by a pr ogram, this bit is set to 0 (and remains unchanged even if 1 is written to it). 5. The VW2C7 bit is enabled when the VCAC2 bit in the VC AC register is set to 0 (one edge). After setting the VCAC2 bit to 0, set the VW2C7 bit. Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting the VW2C register. Rewriting the VW2C register may set the VW2C2 bit to 1. After rewriting this register, set the VW2C2 bit to 0. Address 003Ah B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol VW2C7 — VW2F1 VW2F0 VW2C3 VW2C2 VW2C1 VW2C0 A f t e r R e s e t 10000010 Bit Symbol Bit Name Function R/W b0 VW2C0 Voltage monitor 2 interrupt enable bit (1) 0: Disabled 1: Enabled R/W b1 VW2C1 Voltage monitor 2 digital filter disable mode select bit (2) 0: Digital filter enable mode (digital filter circuit enabled) 1: Digital filter disable mode (digital filter circuit disabled) R/W b2 VW2C2 Voltage change detection flag (3, 4) 0: Not detected 1: Vdet2 passing detected R/W b3 VW2C3 WDT detection monitor flag (4) 0: Not detected 1: Detected R/W b4 VW2F0 Sampling clock select bit b5 b4 0 0: fOCO-S divided by 1 0 1: fOCO-S divided by 2 1 0: fOCO-S divided by 4 1 1: fOCO-S divided by 8 R/W b5 VW2F1 R/W b6 — Reserved bit Set to 0. R/W b7 VW2C7 Voltage monitor 2 interrupt generation condition select bit (5) 0: When VCC or LVCMP2 reaches Vdet2 or above. 1: When VCC or LVCMP2 reaches Vdet2 or below. R/W

R8C/32A Group 6. Voltage Detection Circuit REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 48 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

6.2.9 Option Function Se lect Register (OFS)

Notes: 1. If the block including the OFS register is er ased, the OFS register value is set to FFh. 2. The same level of the voltage detection 0 level selected by bits VDSEL0 and VDESL1 is set in both functions of voltage monitor 0 reset and power-on reset. 3. To use power-on reset, set the LVDAS bit to 0 (voltage monitor 0 reset enabled after reset). The OFS register is allocated in the flash memory. Write to this register with a program. After writing, do not write additions to this register. LVDAS Bit (Voltage Detection 0 Circuit Start Bit) The Vdet0 voltage to be monitored by the voltage detection 0 circuit is selected by bits VDSEL0 and VDSEL1. Address 0FFFFh B i t b 7 b 6b 5b 4b 3b 2b 1b 0 Symbol CSPROINI LVDAS VDSEL1 VDSEL0 ROMCP1 ROMCR — WDTON W h e n s h i p p i n g 1 1111111 ( N o t e 1 ) Bit Symbol Bit Name Function R/W b0 WDTON Watchdog timer start select bit 0: Watchdog timer automatically starts after reset. 1: Watchdog timer is stopped after reset. R/W b1 — Reserved bit Set to 1. R/W b2 ROMCR ROM code protect disable bit 0: ROM code protect disabled 1: ROMCP1 bit enabled R/W b3 ROMCP1 ROM code protect bi t 0: ROM code protect enabled 1: ROM code protect disabled R/W b4 VDSEL0 Voltage detection 0 level select bit (2) b5 b4 0 0: 3.80 V selected (Vdet0_3) 0 1: 2.85 V selected (Vdet0_2) 1 0: 2.35 V selected (Vdet0_1) 1 1: 1.90 V selected (Vdet0_0) R/W b5 VDSEL1 R/W b6 LVDAS Voltage detection 0 circuit start bit (3) 0: Voltage monitor 0 reset enabled after reset 1: Voltage monitor 0 reset disabled after reset R/W b7 CSPROINI Count source protection mode after reset select bit 0: Count source protect mode enabled after reset 1: Count source protect mode disabled after reset R/W

R8C/32A Group 6. Voltage Detection Circuit REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 49 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

6.3 VCC Input Voltage

6.3.1 Monitoring Vdet0

Vdet0 cannot be monitored.

6.3.2 Monitoring Vdet1

Once the following settings are made, the comparison re sult of voltage monitor 1 can be monitored by the VW1C3 bit in the VW1C register after td(E-A) has elapsed (refer to 32. Electrical Characteristics). (1) Set bits VD1S3 to VD1S0 in the VD1LS register (voltage detection 1 detection voltage). (2) Set the VCA21 bit in the VCA2 register to 0 (internal reference voltage). (3) Set the VCA22 bit in the VCA2 register to 0 (VCC voltage). (4) Set the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled).

6.3.3 Monitoring Vdet2

Once the following settings are made, the comparison re sult of voltage monitor 2 can be monitored by the VCA13 bit in the VCA1 register after td(E-A) has elapsed (refer to 32. Electrical Characteristics). (1) Set the VCA23 bit in the VCA2 register to 0 (internal reference voltage). (2) Set the VCA24 bit in the VCA2 register to 0 (VCC voltage), or 1 (LVCMP2 pin input voltage). (3) Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled).

R8C/32A Group 6. Voltage Detection Circuit REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 50 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

6.4 Voltage Monitor 0 Reset

Table 6.3 lists the Procedure for Setting Bits Associated with V oltage Monitor 0 Reset and Figure 6.5 shows an Operating Example of V oltage Monitor 0 Reset. To use the voltage monitor 0 reset to exit stop mode, set the VW0C1 bit in the VW0C register to 1 (digital filter disabled). Note: 1. When the VW0C0 bit is set to 0, steps 3 and 4 can be executed simultaneously (with one instruction). Figure 6.5 Operating Example of Voltage Monitor 0 Reset Table 6.3 Procedure for Setting Bits Associated with Voltage Monitor 0 Reset Step When Using Digital Filter When Using No Digital Filter 1 Set the VCA25 bit in the VCA2 register to 1 (voltage detection 0 circuit enabled). 2 Wait for td(E-A).

3 Select the sampling clock of the digital filter by

bits VW0F0 and VW0F1 in the VW0C register. Set the VW0C7 bit in the VW0C register to 1. (1) Set the VW0C1 bit in the VW0C register to 0 (digital filter enabled). Set the VW0C1 bit in the VW0C register to 1 (digital filter disabled). 5 Set the VW0C2 bit in the VW0C register to 0.

6 Set the CM14 bit in the CM1 register to 0

(low-speed on-chip oscillator on).

7 Wait for 4 cycles of the sampling clock of

the digital filter. − (No wait time required) 8 Set the VW0C0 bit in the VW0C register to 1 (voltage monitor 0 reset enabled). Vdet0 Internal reset signal VCC The above applies when:

• VCA25 bit in VCA2 register = 1 (voltage detection 0 circuit enabled)
• VW0C0 bit in VW0C register = 1 (voltage monitor 0 reset enabled) When the internal reset signal is driven low, the pins, CPU, and SFRs are initialized. When the internal reset signal level changes from low to high, a program is executed beginning with the address indicated by the reset vector. Refer to 4. Special Function Registers (SFRs) for the states of the SFRs after reset. fOCO-S × 32Sampling clock of digital filter × 4 cycles VW0C1 bit is set to 0 (digital filter enabled) Internal reset signalVW0C1 bit is set to 1 (digital filter disabled) fOCO-S × 32 VW0C1 and VW0C7: Bits in VW0C register

R8C/32A Group 6. Voltage Detection Circuit REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 51 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

6.5 Voltage Monitor 1 Interrupt

Table 6.4 lists the Procedure for Setting Bits Associated with V oltage Monitor 1 Interrupt. Figure 6.6 shows an Operating Example of V oltage Monitor 1 Interrupt. To use the voltage monitor 1 interrupt to exit stop mode, set the VW1C1 bit in the VW1C register to 1 (digital filter disabled). Notes: When the VW1C0 bit is set to 0, steps 2, 3 and 4 can be executed simultaneously (with one instruction). 2. When the VW1C0 bit is set to 0, steps 6 and 7 can be executed simultaneously (with one instruction). 3. When the VW1C0 bit is set to 0, steps 8 and 9 can be executed simultaneously (with one instruction). Table 6.4 Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt Step When Using Digital Filter When Using No Digital Filter 1 Select the voltage detection 1 detection voltage by bits VD1S3 to VD1S0 in the VD1LS register. 2 Set the VCA21 bit in the VCA2 register to 0 (internal reference voltage). 3 (1) Set the VCA22 bit in the VCA2 register to 0 (VCC voltage). 4 (1) Set the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled). 5 Wait for td(E-A). 6 Set the COMPSEL bit in th e CMPA register to 1. 7 (2) Select the interrupt type by the IRQ1SEL in the CMPA register.

8 Select the sampling clock of the digital filter by

bits VW1F0 and VW1F1 in the VW1C register. Set the VW1C1 bit in the VW1C register to 1 (digital filter disabled). 9 (3) Set the VW1C1 bit in the VW1C register to 0 (digital filter enabled).

10 Select the interrupt request timing by the VCAC1 bit in the VCAC register and

the VW1C7 bit in the VW1C register. 11 Set the VW1C2 bit in the VW1C register to 0.

12 Set the CM14 bit in the CM1 register to 0

(low-speed on-chip oscillator on)

13 Wait for 2 cycles of the sampling clock of

− (No wait time required)

14 Set the VW1C0 bit in the VW1C register to 1 (voltage monitor 1 interrupt enabled)

R8C/32A Group 6. Voltage Detection Circuit REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 52 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 6.6 Operating Example of Voltage Monitor 1 Interrupt Vdet1 VW1C3 bit VCC The above applies when:

• VCA26 bit in VCA2 register = 1 (voltage detection 1 circuit enabled)
• VW1C0 bit in VW1C register = 1 (voltage monitor 1 interrupt enabled) Note: 1. If voltage monitor 0 reset is not used, set the power supply to VCC ≥ 1.8 V.

1.8 V (1)

digital filter × 2 cycles VW1C2 bit VW1C2 bit 1VW1C1 bit is set to 1 (digital filter disabled), VCAC1 bit is set to 0 (one edge), and VW1C7 bit is set to 0 (when VCC reaches Vdet1 or above) VW1C1, VW1C2, VW1C3, VW1C7: Bits in VW1C register VCAC1: Bit in VCAC register Sampling clock of digital filter × 2 cycles Set to 0 by a program. Voltage monitor 1 interrupt request Voltage monitor 1 interrupt request Set to 0 when an interrupt request is acknowledged. VW1C2 bit Voltage monitor 1 interrupt request VW1C1 bit is set to 0 (digital filter enabled) and VCAC1 bit is set to 1 (both edges) VW1C2 bit Set to 0 when an interrupt request is acknowledged. Set to 0 by a program. Voltage monitor 1 interrupt request VW1C1 bit is set to 0 (digital filter enabled), VCAC1 bit is set to 0 (one edge), and VW1C7 bit is set to 0 (when VCC reaches Vdet1 or above) VW1C2 bit Voltage monitor 1 interrupt request VW1C1 bit is set to 0 (digital filter enabled), VCAC1 bit is set to 0 (one edge), and VW1C7 bit is set to 1 (when VCC reaches Vdet1 or below) Set to 0 by a program. VW1C2 bit Voltage monitor 1 interrupt request VW1C1 bit is set to 1 (digital filter disabled) and VCAC1 bit is set to 1 (both edges) Set to 0 by a program. Set to 0 when an interrupt request is acknowledged. Set to 0 by a program. Set to 0 when an interrupt request is acknowledged. Set to 0 by a program. VW1C1 bit is set to 1 (digital filter disabled), VCAC1 bit is set to 0 (one edge), and VW1C7 bit is set to 1 (when VCC reaches Vdet1 or below) Set to 0 when an interrupt request is acknowledged. Set to 0 when an interrupt request is acknowledged.

R8C/32A Group 6. Voltage Detection Circuit REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 53 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

6.6 Voltage Monitor 2 Interrupt

Table 6.5 lists the Procedure for Setting Bits Associated with V oltage Monitor 2 Interrupt. Figure 6.7 shows an Operating Example of V oltage Monitor 2 Interrupt. To use the voltage monitor 2 interrupt to exit stop mode, set the VW2C1 bit in the VW2C register to 1 (digital filter disabled). Notes: When the VW2C0 bit is set to 0, steps 1, 2 and 3 can be executed simultaneously (with one instruction). 2. When the VW2C0 bit is set to 0, steps 5 and 6 can be executed simultaneously (with one instruction). 3. When the VW2C0 bit is set to 0, steps 7 and 8 can be executed simultaneously (with one instruction). Table 6.5 Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt Step When Using Digital Filter When Using No Digital Filter 1 Set the VCA23 bit in the VCA2 register to 0 (internal reference voltage). 2 (1) Set the VCA24 bit in the VCA2 register to 0 (VCC voltage) or 1 (LCVCMP2 pin input voltage). 3 (1) Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled). 4 Wait for td(E-A). 5 Set the COMPSEL bit in th e CMPA register to 1. 6 (2) Select the interrupt type by the IRQ2SEL in the CMPA register.

7 Select the sampling clock of the digital filter by

bits VW2F0 and VW2F1 in the VW2C register. Set the VW2C1 bit in the VW2C register to 1 (digital filter disabled). 8 (3) Set the VW2C1 bit in the VW2C register to 0 (digital filter enabled).

9 Select the interrupt request timing by the VCAC2 bit in the VCAC register and

the VW2C7 bit in the VW2C register. 10 Set the VW2C2 bit in the VW2C register to 0.

11 Set the CM14 bit in the CM1 register to 0

(low-speed on-chip oscillator on).

12 Wait for 2 cycles of the sampling clock of

the digital filter. − (No wait time required) 13 Set the VW2C0 bit in the VW2C register to 1 (voltage monitor 2 interrupt enabled).

R8C/32A Group 6. Voltage Detection Circuit REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 54 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 6.7 Operating Example of Voltage Monitor 2 Interrupt Vdet2 VW1C3 bit VCC or LVCMP2 The above applies when:

• VCA27 bit in VCA2 register = 1 (voltage detection 2 circuit enabled)
• VW2C0 bit in VW2C register = 1 (voltage monitor 2 interrupt enabled) Note: 1. If voltage monitor 0 reset is not used, set the power supply to VCC ≥ 1.8 V.

digital filter × 2 cycles VW2C2 bit VW2C2 bit 1VW2C1 bit is set to 1 (digital filter disabled), VCAC2 bit is set to 0 (one edge), and VW2C7 bit is set to 0 (when VCC or LVCMP2 reaches Vdet2 or above) VCA13: Bit in VCA1 register VW2C1, VW2C2, VW2C3, VW2C7: Bits in VW2C register VCAC2: Bit in VCAC register Sampling clock of digital filter × 2 cycles Set to 0 by a program. Voltage monitor 2 interrupt request Voltage monitor 2 interrupt request Set to 0 when an interrupt request is acknowledged. VW2C2 bit Voltage monitor 2 interrupt request VW2C1 bit is set to 0 (digital filter enabled) and VCAC2 bit is set to 1 (both edges) VW2C2 bit Set to 0 when an interrupt request is acknowledged. Set to 0 by a program. Voltage monitor 2 interrupt request VW2C1 bit is set to 0 (digital filter enabled), VCAC2 bit is set to 0 (one edge), and VW2C7 bit is set to 0 (when VCC or LVCMP2 reaches Vdet2 or above) VW2C2 bit Voltage monitor 2 interrupt request VW2C1 bit is set to 0 (digital filter enabled), VCAC2 bit is set to 0 (one edge), and VW2C7 bit is set to 1 (when VCC or LVCMP2 reaches Vdet2 or below) Set to 0 by a program. VW2C2 bit Voltage monitor 2 interrupt request VW2C1 bit is set to 1 (digital filter disabled) and VCAC2 bit is set to 1 (both edges) Set to 0 by a program. Set to 0 when an interrupt request is acknowledged. Set to 0 by a program. Set to 0 when an interrupt request is acknowledged. Set to 0 by a program.VW2C1 bit is set to 1 (digital filter disabled), VCAC2 bit is set to 0 (one edge), and VW2C7 bit is set to 1 (when VCC or LVCMP2 reaches Vdet2 or below) Set to 0 when an interrupt request is acknowledged. Set to 0 when an interrupt request is acknowledged.

R8C/32A Group 7. I/O Ports REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 55 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 7. I/O Ports There are 15 I/O ports P1, P3_3 to P3_5, P3_7, and P4_5 to P4_7 (P4_6 and P4_7 can be used as I/O ports if the XIN clock oscillation circuit and the XCIN clock oscillation circuit are not used.). If the A/D converter is not used, P4_2 can be used as an input-only port. Table 7.1 lists an Overview of I/O Ports. Notes: 1. In input mode, whether an internal pull-up resistor is connected or not can be selected by registers PUR0 and PUR1. 2. Whether the drive capacity of the output transistor is set to low or high can be selected using the P1DRR register. 3. Whether the drive capacity of the output transistor is set to low or high can be selected using registers DRR0 and DRR1. 4. The input threshold value can be selected among thre e voltage levels (0.35 VCC, 0.50 VCC, and 0.70 VCC) using registers VLT0 and VLT1. 5. When the XIN clock oscillation circuit and the XCIN cl ock oscillation circuit are not used, these ports can be used as I/O ports. 6. When the A/D converter is not used, this port can be used as an input-only ports.

7.1 Functions of I/O Ports

The PDi_j (j = 0 to 7) bit in the PDi (i = 1, 3, 4) register controls I/O of the ports P1, P3_3 to P3_5, P3_7, and P4_5 to P4_7. The Pi register consists of a port latch to hold output data and a circuit to read pin states. i = 1, 3, 4, j = 0 to 7 Note: 1. Nothing is assigned to bits PD4_0 to PD4_2. Also, bits PD3_0 to PD3_2, PD3_6, PD4_3, and PD4_4 are reserved bits. Table 7.1 Overview of I/O Ports Ports I/O Type of Output I/O Setting Internal Pull-Up Resister Drive Capacity Switch Input Level Switch P1 I/O CMOS3 state Set in 1-bit units Set in 4-bit units (1) Set in 1-bit units (2) Set in 8-bit units (4) P3_3 I/O CMOS3 state Set in 1-bit units Set in 1-bit units (1) Set in 1-bit units (3) Set in 4-bit units (4) P3_4, P3_5, P3_7 I/O CMOS3 state Set in 1-bit units Set in 3-bit units (1) Set in 3-bit units (3) P4_5, P4_6 (5), P4_7 (5) I/O CMOS3 state Set in 1-bit units Set in 3-bit units (1) Set in 3-bit units (3) Set in 4-bit units (4) P4_2 (6) I (No output function) None None None Table 7.2 Functions of I/O Ports Operation When Accessing Pi Register Value of PDi_j Bit in PDi Register (1) When PDi_j Bit is Set to 0 (Input Mode) W hen PDi_j Bit is Set to 1 (Output Mode) Read Read the pin input level. Read the port latch. Write Write to the port latch. Write to the port latch. The value written to the port latch is output from the pin.

R8C/32A Group 7. I/O Ports REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 56 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

7.2 Effect on Peripheral Functions

I/O ports function as I/O ports fo r peripheral functions (Refer to Table 1.4 Pin Name Information by Pin Number). Table 7.3 lists the Setting of PDi_j Bit when Functioning as I/O Ports for Peripheral Functions (i = 1, 3, 4, j = 0 to 7). Refer to the description of each function for information on how to set peripheral functions.7.3 Pins Other than I/O Ports Figure 7.8 shows the Configuration of I/O Pins. Table 7.3 Setting of PDi_j Bit when Functioning as I/O Ports for Peripheral Functions I/O of Peripheral Function PDi_j Bit Settings for Shared Pin Function Input Set this bit to 0 (input mode). Output This bit can be set to either 0 or 1 (output regardless of the port setting).

R8C/32A Group 7. I/O Ports REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 57 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 7.1 Configuration of I/O Ports (1) Pin select register P1_0 to P1_2 Drive capacity selection Input to individual peripheral function Analog input of A/D converter Analog input of comparator A Pin select register P1_3 Drive capacity selection Input to individual peripheral function Analog input of A/D converter Note: 1. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC. (Note 1) (Note 1) (Note 1) (Note 1) Port latchData bus Pull-up selection Output from individual peripheral function Drive capacity selection Direction register Input level switch function Pin select register Port latchData bus Pull-up selection Output from individual peripheral function Drive capacity selection Direction register Input level switch function Pin select register

R8C/32A Group 7. I/O Ports REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 58 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 7.2 Configuration of I/O Ports (2) Pin select register P1_5 Drive capacity selection Drive capacity selection Input to individual peripheral function Input to external interrupt Digital filter Pin select register P1_4 Drive capacity selection Input to individual peripheral function (Note 1) (Note 1) (Note 1) (Note 1) Note: 1. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC. Port latchData bus Pull-up selection Output from individual peripheral function Drive capacity selection Direction register Input level switch function Pin select register Port latchData bus Pull-up selection Output from individual peripheral function Direction register Input level switch function Pin select register

R8C/32A Group 7. I/O Ports REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 59 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 7.3 Configuration of I/O Ports (3) Pin select register P1_7 Drive capacity selection Drive capacity selection Input to individual peripheral function Input to external interrupt Digital filter Analog input of comparator B Pin select register Drive capacity selection Drive capacity selection Input to individual peripheral function Analog input of comparator B P1_6 (Note 1) (Note 1) (Note 1) (Note 1) Note: 1. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC. Port latchData bus Pull-up selection Output from individual peripheral function Direction register Input level switch function Pin select register Port latchData bus Pull-up selection Output from individual peripheral function Direction register Input level switch function Pin select register

R8C/32A Group 7. I/O Ports REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 60 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 7.4 Configuration of I/O Ports (4) Pin select register P3_3 Drive capacity selection Input to individual peripheral function Input to external interrupt Digital filter Analog input of comparator B (Note 1) (Note 1) Port latchData bus Pull-up selection Output from individual peripheral function Direction register Input level switch function Pin select register Drive capacity selection Note: 1. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC. Pin select register Drive capacity selection Drive capacity selection Input to individual peripheral function Analog input of comparator B P3_4 (Note 1) (Note 1) Port latchData bus Pull-up selection Output from individual peripheral function Direction register Input level switch function Pin select register

R8C/32A Group 7. I/O Ports REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 61 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 7.5 Configuration of I/O Ports (5) Note: 1. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC. Pin select register P3_5 Drive capacity selection Input to individual peripheral function (Note 1) (Note 1) Port latchData bus Pull-up selection Output from individual peripheral function Direction register Input level switch function Pin select register Drive capacity selection Pin select register P3_7 Drive capacity selection Drive capacity selection Input to individual peripheral function (Note 1) (Note 1) Port latchData bus Pull-up selection Output from individual peripheral function Direction register Input level switch function Pin select register

R8C/32A Group 7. I/O Ports REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 62 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 7.6 Configuration of I/O Ports (6) P4_2/VREF Data bus Input level switch function (Note 1) (Note 1) Pin select register P4_5 Drive capacity selection Drive capacity selection (Note 1) (Note 1) Input to individual peripheral function Input to external interrupt A/D trigger input Digital filter Note: 1. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC. Port latchData bus Pull-up selection Output from individual peripheral function Direction register Input level switch function Pin select register

R8C/32A Group 7. I/O Ports REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 63 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 7.7 Configuration of I/O Ports (7) Note: 1. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC. CM01, CM03, CM04, CM05: Bits in CM0 register CM11, CM12, CM13: Bits in CM1 register CM05 CM11 CM13 RfXIN XIN oscillation circuit CM03 CM12 RfXCIN XCIN oscillation circuit CM04, CM1301 CM01 CM01 Port latchData bus Pull-up selection Drive capacity selection Drive capacity selection Direction register Input level switch function P4_6/XIN/XCIN Port latchData bus Pull-up selection Drive capacity selection Drive capacity selection Direction register Input level switch function P4_7/XOUT/XCOUT (Note 1) (Note 1) (Note 1) (Note 1)

R8C/32A Group 7. I/O Ports REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 64 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 7.8 Configuration of I/O Pins MODE RESET (Note 1) (Note 1) (Note 1) Note: 1. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC. MODE signal input RESET signal input

R8C/32A Group 7. I/O Ports REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 65 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

7.4 Registers

7.4.1 Port Pi Direction Regi ster (PDi) (i = 1, 3, 4)

Notes: 1. Bits PD3_0 to PD3_2 and PD3_6 in the PD3 register are reserved bits. If it is necessary to set bits PD3_0 to PD3_2 and PD3_6, set to 0. When read, the content is 0. 2. Bits PD4_0 to PD4_2 in the PD4 register are unavailabl e on this MCU. If it is necessary to set bits PD4_0 to PD4_2 set to 0. When read, the content is 0. Bits PD4_3, PD4_4 are reserved bits. If it is necessary to set bits PD4_3 and PD4_4, set to 0. When read, the content is 0. The PDi register selects whether I/O ports are used for input or output. Each bit in the PDi register corresponds to one port. Address 00E3h (PD1), 00E7h (PD3 (1)), 00EAh (PD4 (2)) B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol PDi_7 PDi_6 PDi_5 PDi_4 PDi_3 PDi_2 PDi_1 PDi_0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 PDi_0 Port Pi_0 direction bit 0: Input mode (functions as an input port) 1: Output mode (functions as an output port) R/W b1 PDi_1 Port Pi_1 direction bit R/W b2 PDi_2 Port Pi_2 direction bit R/W b3 PDi_3 Port Pi_3 direction bit R/W b4 PDi_4 Port Pi_4 direction bit R/W b5 PDi_5 Port Pi_5 direction bit R/W b6 PDi_6 Port Pi_6 direction bit R/W b7 PDi_7 Port Pi_7 direction bit R/W

R8C/32A Group 7. I/O Ports REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 66 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

7.4.2 Port Pi Register (Pi) (i = 1, 3, 4)

Notes: 1. Bits P3_0 to P3_2 and P3_6 in the P3 register are reserv ed bits. If it is necessary to set bits P3_0 to P3_2 and P3_6, set to 0. When read, the content is 0. 2. Bits P4_0 to P4_1 in the P4 register are unavailable on this MCU. If it is necessary to set bits P4_0 to P4_1 set to 0. When read, the content is 0. Bits P4_3, P4_4 are reserved bits. If it is necessary to set bits P4_3 and P4_4, set to 0. When read, the content is 0. Data input and output to and from exte rnal devices are accomplished by read ing and writing to the Pi register. The Pi register consists of a port latch to retain output data and a circuit to read the pin status. The value written in the port latch is output from the pin. Each bit in the Pi register corresponds to one port. Pi_j Bit (i = 1, 3, 4, j = 0 to 7) (Port Pi_j Bit) The pin level of any I/O port which is set to input mode can be read by reading the corresponding bit in this register. The pin level of any I/O port which is set to output mode can be controlled by writing to the corresponding bit in this register. Address 00E1h(P1), 00E5h(P3 (1)), 00E8h(P4 (2)) B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol Pi_7 Pi_6 Pi_5 Pi_4 Pi_3 Pi_2 Pi_1 Pi_0 A f t e r R e s e t XXXXXXXX Bit Symbol Bit Name Function R/W b0 Pi_0 Port Pi_0 bit 0: “L” level 1: “H” level R/W b1 Pi_1 Port Pi_1 bit R/W b2 Pi_2 Port Pi_2 bit R/W b3 Pi_3 Port Pi_3 bit R/W b4 Pi_4 Port Pi_4 bit R/W b5 Pi_5 Port Pi_5 bit R/W b6 Pi_6 Port Pi_6 bit R/W b7 Pi_7 Port Pi_7 bit R/W

R8C/32A Group 7. I/O Ports REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 67 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

7.4.3 Timer RA Pin Se lect Register (TRASR)

The TRASR register selects which pin is assigned to the timer RA I/O. To use the I/O pin for timer RA, set this register. Set the TRASR register before setting the timer RA associ ated registers. Also, do no t change the setting value in this register during timer RA operation.

7.4.4 Timer RC Pin Sel ect Register (TRBRCSR)

The TRBRCSR register selects which pi n is assigned to the timer RC I/O. To use the I/O pin for timer RC, set this register. Set bits TRCCLKSEL0 and TRCCLKSEL1 before setting the timer RC associated registers. Also, do not change the setting values of bits TRCCLKSEL0 and TRCCLKSEL1 during timer RC operation. Address 0180h B i t b 7b 6b 5 b 4 b 3 b 2 b 1 b 0 Symbol — — — — — — TRAIOSEL1 TRAIOSEL0 A f t e r R e s e t 000 0 0 0 0 0 Bit Symbol Bit Name Function R/W b0 TRAIOSEL0 TRAIO pin select bit b1 b0 0 0: TRAIO pin not used 0 1: P1_7 assigned 1 0: P1_5 assigned 1 1: Do not set. R/W b1 TRAIOSEL1 R/W b2 — Reserved bits Set to 0. R/W b3 — b4 — b5 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b6 — b7 — Address 0181h B i t b 7b 6 b 5 b 4 b 3b 2b 1b 0 Symbol — — TRCCLKSEL1 TRCCLKSEL0 — — — — A f t e r R e s e t 0 00 00 0 0 0 Bit Symbol Bit Name Function R/W b0 — Reserved bits Set to 0. R/W b1 — b2 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b3 — b4 TRCCLKSEL0 TRCCLK pin select bit b5 b4 0 0: TRCCLK pin not used 0 1: P1_4 assigned 1 0: P3_3 assigned 1 1: Do not set. R/W b5 TRCCLKSEL1 R/W b6 — Reserved bit Set to 0. R/W b7 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. —

R8C/32A Group 7. I/O Ports REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 68 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

7.4.5 Timer RC Pin Select Register 0 (TRCPSR0)

The TRCPSR0 register selects which pin is assigned to the timer RC I/O. To use the I/O pin for timer RC, set this register. Set the TRCPSR0 register before setting the timer RC associated registers. Also, do not change the setting value in this register during timer RC operation.

7.4.6 Timer RC Pin Select Register 1 (TRCPSR1)

The TRCPSR1 register selects which pin is assigned to the timer RC I/O. To use the I/O pin for timer RC, set this register. Set the TRCPSR1 register before setting the timer RC associated registers. Also, do not change the setting value in this register during timer RC operation. Address 0182h B i t b 7b 6b 5 b 4 b 3b 2b 1 b 0 Symbol — — — TRCIOBSEL0 — — — TRCIOASEL0 A f t e r R e s e t 000 0 000 0 Bit Symbol Bit Name Function R/W b0 TRCIOASEL0 TRCIOA/TRCTRG pin select bit 0: TRCIOA/TRCTRG pin not used 1: P1_1 assigned R/W b1 — Reserved bits Set to 0. R/W b2 — b3 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b4 TRCIOBSEL0 TRCIOB pin select bit 0: TRCIOB pin not used 1: P1_2 assigned R/W b5 — Reserved bits Set to 0. R/W b6 — b7 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — Address 0183h B i t b 7b 6 b 5 b 4 b 3b 2 b 1 b 0 Symbol — — TRCIODSEL1 TRCIODSEL0 — — TRCIOCSEL1 TRCIOCSEL0 A f t e r R e s e t 0 00 00 00 0 Bit Symbol Bit Name Function R/W b0 TRCIOCSEL0 TRCIOC pin select bit b1 b0 0 0: TRCIOC pin not used 0 1: P1_3 assigned 1 0: P3_4 assigned 1 1: Do not set. R/W b1 TRCIOCSEL1 R/W b2 — Reserved bit Set to 0. R/W b3 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b4 TRCIODSEL0 TRCIOD pin select bit b5 b4 0 0: TRCIOD pin not used 0 1: P1_0 assigned 1 0: P3_5 assigned 1 1: Do not set. R/W b5 TRCIODSEL1 R/W b6 — Reserved bit Set to 0. R/W b7 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. —

R8C/32A Group 7. I/O Ports REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 69 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

7.4.7 UART0 Pin Sele ct Register (U0SR)

The U0SR register selects which pin is assigned to the UART0 I/O. To use the I/O pin for UART0, set this register. Set the U0SR register before setting the UART0 associat ed registers. Also, do not change the setting value in this register during UART0 operation. Address 0188h B i t b 7 b 6 b 5b 4b 3b 2b 1b 0 Symbol — — — CLK0SEL0 — RXD0SEL0 — TXD0SEL0 A f t e r R e s e t 000 0 0 0 0 0 Bit Symbol Bit Name Function R/W b0 TXD0SEL0 TXD0 pin select bit 0: TXD0 pin not used 1: P1_4 assigned R/W b1 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b2 RXD0SEL0 RXD0 pin select bit 0: RXD0 pin not used 1: P1_5 assigned R/W b3 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b4 CLK0SEL0 CLK0 pin select bit 0: CLK0 pin not used 1: P1_6 assigned R/W b5 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b6 — b7 —

R8C/32A Group 7. I/O Ports REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 70 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

7.4.8 UART2 Pin Select Register 0 (U2SR0)

The U2SR0 register selects which pin is assigned to the UART2 I/O. To use the I/O pin for UART2, set this register. Set the U2SR0 register before setting the UART2 associated registers. Also, do not change the setting value in this register during UART2 operation.

7.4.9 UART2 Pin Select Register 1 (U2SR1)

The U2SR1 register selects which pin is assigned to the UART2 I/O. To use the I/O pin for UART2, set this register. Set the U2SR1 register before setting the UART2 associated registers. Also, do not change the setting value in this register during UART2 operation. Address 018Ah B i t b 7 b 6b 5 b 4b 3b 2 b 1 b 0 Symbol — — RXD2SEL1 RXD2SEL0 — — TXD2SEL1 TXD2SEL0 A f t e r R e s e t 0 00 000 0 0 Bit Symbol Bit Name Function R/W b0 TXD2SEL0 TXD2/SDA2 pin select bit b1 b0 0 0: TXD2/SDA2 pin not used 0 1: P3_7 assigned 1 0: P3_4 assigned 1 1: Do not set. R/W b1 TXD2SEL1 R/W b2 — Reserved bit Set to 0. R/W b3 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b4 RXD2SEL0 RXD2/SCL2 pin select bit b5 b4 0 0: RXD2/SCL2 pin not used 0 1: P3_4 assigned 1 0: P3_7 assigned 1 1: P4_5 assigned R/W b5 RXD2SEL1 R/W b6 — Reserved bit Set to 0. R/W b7 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — Address 018Bh B i t b 7b 6b 5 b 4 b 3b 2 b 1 b 0 Symbol — — — CTS2SEL0 — — — CLK2SEL0 A f t e r R e s e t 000 0 00 0 0 Bit Symbol Bit Name Function R/W b0 CLK2SEL0 CLK2 pin select bit 0: CLK2 pin not used 1: P3_5 assigned R/W b1 — Reserved bit Set to 0. R/W b2 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b3 — b4 CTS2SEL0 CTS2 /RTS2 pin select bit 0: CTS2 /RTS2 pin not used 1: P3_3 assigned R/W b5 — Reserved bit Set to 0. R/W b6 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b7 — Reserved bit Set to 0. R/W

R8C/32A Group 7. I/O Ports REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 71 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

7.4.10 SSU/IIC Pin Select Register (SSUIICSR)

7.4.11 INT Interrupt Input Pi n Select Register (INTSR)

The INTSR register selects which pin is assigned to the INT1 input. To use INT1, set this register. Set the INTSR register before setting the INT1 associated registers. Also, do not change the setting values in this register during INT1 operation. Address 018Ch B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 IICSEL SSU/I2C bus switch bit 0: SSU function selected 1: I2C bus function selected R/W b1 — Reserved bit Set to 0. R/W b2 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b3 — b4 — Reserved bits Set to 0. R/W b5 — b6 — b7 — Address 018Eh B i t b 7b 6 b 5 b 4b 3b 2b 1 b 0 A f t e r R e s e t 00 0 0000 0 Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b1 INT1SEL0 INT1 pin select bit 0: P1_7 assigned 1: P1_5 assigned R/W b2 — Reserved bits Set to 0. R/W b3 — b4 — b5 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b6 — Reserved bits Set to 0. R/W b7 —

R8C/32A Group 7. I/O Ports REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 72 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

7.4.12 Pull-Up Contro l Register 0 (PUR0)

Note: 1. When this bit is set to 1 (pulled up), the pin whose port direction bit is set to 0 (input mode) is pulled up. For ports set to output as I/O pins for peripheral functi ons, the setting values in the PUR0 register are invalid and no pull-up resistor is connected.

7.4.13 Pull-Up Contro l Register 1 (PUR1)

Note: 1. When this bit is set to 1 (pulled up), the pin whose port direction bit is set to 0 (input mode) is pulled up. For ports set to output as I/O pins for peripheral functi ons, the setting values in the PUR1 register are invalid and no pull-up resistor is connected. Address 01E0h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol PU07 PU06 — — PU03 PU02 — — A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 — Reserved bits Set to 0. R/W b1 — b2 PU02 P1_0 to P1_3 pull-up 0: Not pulled up 1: Pulled up (1) R/W b3 PU03 P1_4 to P1_7 pull-up R/W b4 — Reserved bits Set to 0. R/W b5 — b6 PU06 P3_3 pull-up 0: Not pulled up 1: Pulled up (1) R/W b7 PU07 P3_4, P3_5, P3_7 pull-up R/W Address 01E1h B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 — Reserved bit Set to 0. R/W b1 PU11 P4_5 to P4_7 pull-up 0: Not pulled up 1: Pulled up (1) R/W b2 — Reserved bits Set to 0. R/W b3 — b4 — b5 — b6 — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. — b7 —

R8C/32A Group 7. I/O Ports REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 73 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

7.4.14 Port P1 Drive Capacity Control Register (P1DRR)

Note: 1. Both “H” and “L” output are set to high drive capacity. The P1DRR register selects whether the drive capacity of the P1 output transistor is set to low or high. The P1DRRi bit (i = 0 to 7) is used to select whether th e drive capacity of the output transistor is set to low or high for each pin. Address 01F0h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol P1DRR7 P1DRR6 P1DRR5 P1DRR4 P1DRR3 P1DRR2 P1DRR1 P1DRR0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 P1DRR0 P1_0 drive capacity 0: Low 1: High (1) R/W b1 P1DRR1 P1_1 drive capacity R/W b2 P1DRR2 P1_2 drive capacity R/W b3 P1DRR3 P1_3 drive capacity R/W b4 P1DRR4 P1_4 drive capacity R/W b5 P1DRR5 P1_5 drive capacity R/W b6 P1DRR6 P1_6 drive capacity R/W b7 P1DRR7 P1_7 drive capacity R/W

R8C/32A Group 7. I/O Ports REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 74 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

7.4.15 Drive Capacity C ontrol Register 0 (DRR0)

Note: 1. Both “H” and “L” output are set to high drive capacity. DRR06 Bit (P3_3 drive capacity) The DRR06 bit selects whether the drive capacity of the P3_3 output transistors is set to low or high. This bit is used to select whether the drive capacity of the output transistors is set to low or high for this pin. DRR07 Bit (P3_4, P3_5, P3_7 drive capacity) The DRR07 bit selects whether the drive capacity of the P3_4, P3_5, P3_7 output transistors is set to low or high. This bit is used to select whether the drive capacity of the output transistors is set to low or high for three pins. Address 01F2h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol DRR07 DRR06 — — — — — — A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 — Reserved bits Set to 0. R/W b1 — b2 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b3 — b4 — b5 — b6 DRR06 P3_3 drive capacity 0: Low 1: High (1) R/W b7 DRR07 P3_4, P3_5, P3_7 drive capacity R/W

R8C/32A Group 7. I/O Ports REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 75 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

7.4.16 Drive Capacity C ontrol Register 1 (DRR1)

Note: 1. Both “H” and “L” output are set to high drive capacity. DRR11 Bit (P4_5 to P4_7 drive capacity) The DRR11 bit selects whether the drive capacity of the P4_5 to P4_7 output transistors is set to low or high. This bit is used to select whether the drive capacity of the output transistors is set to low or high for four pins. Address 01F3h B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 — Reserved bit Set to 0. R/W b1 DRR11 P4_5 to P4_7 drive capacity 0: Low 1: High (1) R/W b2 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b3 — Reserved bits Set to 0. R/W b4 — b5 — b6 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b7 —

R8C/32A Group 7. I/O Ports REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 76 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

7.4.17 Input Threshold Cont rol Register 0 (VLT0)

The VLT0 register selects the voltage level of the input threshold values for ports P1, P3_3 to P3_5, and P3_7. Bits VLT02 to VLT03 and bits VLT06 to VLT07 are used to select the input threshold values among three voltage levels (0.35 VCC, 0.50 VCC, and 0.70 VCC).

7.4.18 Input Threshold Cont rol Register 1 (VLT1)

The VLT1 register selects the voltage level of the input threshold values for ports P4_2 and P4_5 to P4_7. Bits VLT10 to VLT15 are used to select the input threshol d values among three voltage levels (0.35 VCC, 0.50 VCC, and 0.70 VCC). Address 01F5h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol VLT07 VLT06 — — VLT03 VLT02 — — A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 — Reserved bits Set to 0. R/W b1 — b2 VLT02 P1 input level select bit b3 b2 0 0: 0.50 × VCC 0 1: 0.35 × VCC 1 0: 0.70 × VCC 1 1: Do not set. R/W b3 VLT03 R/W b4 — Reserved bits Set to 0. R/W b5 — b6 VLT06 P3_3 to P3_5, P3_7 input level select bit b7 b6 0 0: 0.50 × VCC 0 1: 0.35 × VCC 1 0: 0.70 × VCC 1 1: Do not set. R/W b7 VLT07 R/W Address 01F6h B i t b 7b 6b 5b 4b 3b 2b 1b 0 S y m b o l —————— V L T 1 1 V L T 1 0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 VLT10 P4_2, P4_5 to P4_7 input level select bit b1 b0 0 0: 0.50 × VCC 0 1: 0.35 × VCC 1 0: 0.70 × VCC 1 1: Do not set. R/W b1 VLT11 R/W b2 — Reserved bits Set to 0. R/W b3 — b4 — b5 — b6 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b7 —

R8C/32A Group 7. I/O Ports REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 77 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

7.5 Port Settings

Tables 7.4 to 7.24 list the port settings. X: 0 or 1 Notes: 1. Pulled up by setting the PU02 bit in the PUR0 register to 1. 2. Output drive capacity high by setting the P1DRR0 bit in the P1DRR register to 1. X: 0 or 1 Notes: 1. Pulled up by setting the PU02 bit in the PUR0 register to 1. 2. Output drive capacity high by setting the P1DRR1 bit in the P1DRR register to 1. Table 7.4 Port P1_0/KI0 /AN8/TRCIOD/LVCMP1 Register PD1 KIEN ADINSEL TRCPSR1 VCA2 Timer RC Setting FunctionBit PD1_0 KI0EN CH ADGSEL TRCIODSEL VCA22 —210 1 0 1 0 Setting Value 0X X X X X X Other than 01b XX Input port (1) 1X X X X X X Other than 01b XX Output port (2)

01 X X X X X Other than

01b XX KI0 input (1) 0 0 000 0 1 Other than 01b XX A/D converter input (AN8) (1) 0X X X X X X 0 1 X Refer to Table 7.24 TRCIOD Pin Setting TRCIOD input (1) XX X X X X X 0 1 X Refer to Table 7.24 TRCIOD Pin Setting TRCIOD output (2)

00 X X X X X Other than

01b 1X Comparator A1 input (LVCMP1) Table 7.5 Port P1_1/KI1 /AN9/TRCIOA/TRCTRG/LVCMP2 Register PD1 KIEN ADINSEL TRCPSR0 VCA2 Timer RC Setting FunctionBit PD1_1 KI1EN CH ADGSEL TRCIOASEL0 VCA24 —210 1 0 Setting Value 0X X X X X X 0 X X Input port (1) 1X X X X X X 0 X X Output port (2) 1X X X X X 0 X X KI1 input (1) 00 0 0 1 0 1 0 X X A/D converter input (AN9) (1) 0X X X X X X 1 X Refer to Table 7.21 TRCIOA Pin Setting TRCIOA input (1) XX X X X X X 1 X Refer to Table 7.21 TRCIOA Pin Setting TRCIOA output (2)

00 X X X X X 0 1 X Comparator A2 input

(LVCMP2)

R8C/32A Group 7. I/O Ports REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 78 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. X: 0 or 1 Notes: 1. Pulled up by setting the PU02 bit in the PUR0 register to 1. 2. Output drive capacity high by setting the P1DRR2 bit in the P1DRR register to 1. X: 0 or 1 Notes: 1. Pulled up by setting the PU02 bit in the PUR0 register to 1. 2. Output drive capacity high by setting the P1DRR3 bit in the P1DRR register to 1. Table 7.6 Port P1_2/KI2 /AN10/TRCIOB/LVREF Register PD1 KIEN ADINSEL TRCPSR0 VCA2 Timer RC Setting Function Bit PD1_2 KI2EN CH ADGSEL TRCIOBSEL0 VCA21 VCA23 —210 1 0 Setting Value

0 X XXX X X 0 X X X Input port (1)

1 X XXX X X 0 X X X Output port (2)

0 1 XXX X X 0 X X X KI2 input (1) 00 0 1 0 0 1 0 XX X A/D converter input (AN10) (1)

0 X XXX X X 1 X X

7.22 TRCIOB

TRCIOB input (1) X X XXX X X 1 X X Refer to Table TRCIOB output (2) 0 0 XXX X X 0 1 X X Comparator A1 reference voltage input (LVREF) 0 0 XXX X X 0 X 1 X Comparator A2 reference voltage input (LVREF) Table 7.7 Port P1_3/KI3 /AN11/TRCIOC/LVCOUT1 Register PD1 KIEN ADINSEL TRCPSR1 ACMR Timer RB Setting Timer RC Setting FunctionBit PD1_3 KI3EN CH ADGSEL TRCIOCSEL CM10E — —210 1 0 1 0 Setting Value 0X X X X X X Other than 01b 0 Other than TRBO usage conditions X Input port (1) 1X X X X X X Other than 01b 0 Other than TRBO usage conditions X Output port (2) usage conditions X KI3 input (1) 0 0 011 0 1 Other than 01b 0 Other than TRBO usage conditions X A/D converter input (AN11) (1) XX X X X X X X X0 Refer to Table

7.20 TRBO Pin

X TRBO output (2) 0X X X X X X 0 10 Other than TRBO usage conditions Refer to Table TRCIOC input (1) XX X X X X X 0 10 Other than TRBO usage conditions Refer to Table TRCIOC output (2) XX X X X X X X X1 X X Comparator A1 output (LVCOUT1)

R8C/32A Group 7. I/O Ports REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 79 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. X: 0 or 1 Notes: 1. Pulled up by setting the PU03 bit in the PUR0 register to 1. 2. Output drive capacity high by setting the P1DRR4 bit in the P1DRR register to 1. 3. N-channel open-drain output by setting t he NODC bit in the U0C0 register to 1. X: 0 or 1 Notes: 1. Pulled up by setting the PU03 bit in the PUR0 register to 1. 2. Output drive capacity high by setting the P1DRR5 bit in the P1DRR register to 1. X: 0 or 1 Notes: 1. Pulled up by setting the PU03 bit in the PUR0 register to 1. 2. Output drive capacity high by setting the P1DRR6 bit in the P1DRR register to 1. Table 7.8 Port P1_4/TXD0/TRCCLK Register PD1 U0SR U1MR TRBRCSR TRCCR1 FunctionBit PD1_4 TXD0SEL0 SMD TRCCLKSEL TCK 21010210 Setting Value 0 0 XXXXXXXX Input port (1) 1 0 XXXXXXXX Output port (2) XXXXX TXD0 output (2, 3)

00 X X X 0 1 1 0 1 TRCCLK input (1)

Table 7.9 Port P1_5/RXD0/TRAIO/INT1 Register PD1 U0SR TRASR TRAIOC TRAMR INTSR INTEN INTCMP FunctionBit PD1_5 RXD0SEL0 TRAIOSEL TOPCR TMOD INT1SEL INT1EN INT1CP01 0 210210 Setting Value

0 X Other than 10b X X X X X X X X X Input port (1)

1 X Other than 10b X X X X X X X X X Output port (2)

0 1 Other than 10b X X X X X X X X X RXD0 input (1) 0X 1 0 0 Other than 000b, 001b XXX X X TRAIO input (1)

0 X Other than 10b X X X X 0 0 1 1 0 INT1 input (1)

000b, 001b 001 1 0 TRAIO/INT1 input (1) XX 1 0 0 0 0 1 X X X X X TRAIO pulse output (2) Table 7.10 Port P1_6/CLK0/IVREF1/LVCOUT2 Register PD1 U0SR U0MR INTCMP ACMR FunctionBit PD1_6 CLK0SEL0 SMD CKDIR INT1CP0 CM10E210 Setting Value

00 X X X X X 0 Input port (1)

10 X X X X X 0 Output port (2)

01 X X X 1 X 0 CLK0 (external clock) input (1)

X 1 001 0 X 0 CLK0 (internal clock) output (2) 0 0 X X X X 1 0 Comparator B1 reference voltage input (IVREF1) XX X X X X X 1 Comparator A2 output (2)

R8C/32A Group 7. I/O Ports REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 80 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. X: 0 or 1 Notes: 1. Pulled up by setting the PU03 bit in the PUR0 register to 1. 2. Output drive capacity high by setting the P1DRR7 bit in the P1DRR register to 1. X: 0 or 1 Notes: 1. Pulled up by setting the PU06 bit in the PUR0 register to 1. 2. Output drive capacity high by setting the DRR06 bit in the DRR0 register to 1. 3. N-channel open-drain output by setting the CSOS bit in the SSMR2 register to 1 (N-channel open-drain output). Table 7.11 Port P1_7/INT1 /TRAIO/IVCMP1 Register PD1 TRASR TRAIOC TRAMR INTSR INTEN INTCMP FunctionBit PD1_7 TRAIOSEL TOPCR TMOD INT1SEL INT1EN INT1CP01 0 210210 Setting Value

0 Other than 01b X X X X X X X X X Input port (1)

1 Other than 01b X X X X X X X X X Output port (2)

000b, 001b XXX X X TRAIO input (1)

0 Other than 01b X X X X 0 0 0 1 0 INT1 input (1)

000b, 001b 000 1 0 TRAIO/INT1 input (1) X 0 1 0 001XXX X X TRAIO pulse output (2)

0 Other than 01b X X X X X X X 1 1 Comparator B1 input (IVCMP1)

Table 7.12 Port P3_3/INT3 /TRCCLK/SCS/CTS2/RTS2/IVCMP3 Register PD3 SSMR2 INTEN TRBRCSR TRCCR1 U2SR1 U2MR U2CO INTCMP FunctionBit PD3_3 CSS INT3EN TRCCLKSEL TCK CTS2SEL0 SMD CRS CRD INT3CP010 1 0 210 210 Setting Value 0 00 X X X XXX 0 XXX X X X Input port (1) 1 00 X X X XXX 0 XXX X X X Output port (2) 0 00 1 X X XXX 0 XXX X X 0 INT3 input (1) 00 0 X 1 0 1 0 1 0 X X X X X X TRCCLK input (1) X 0 1 X XX X X XX X X X X SCS input (1) X 10 XX X X X X X X X X X SCS output (2, 3) 00 0 X X XX X X 1 Other than 000b 00 X CTS2 input (1) X0 0 X X X X X X 1 Other than 000b 10 X RTS2 output (2) 0 0 0 1 Other than 10b X X X 0 X X X X X 1 Comparator B3 input (IVCMP1)

R8C/32A Group 7. I/O Ports REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 81 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. X: 0 or 1 Notes: 1. Pulled up by setting the PU07 bit in the PUR0 register to 1. 2. Output drive capacity high by setting the DRR07 bit in the DRR0 register to 1. 3. N-channel open-drain output by setting the SOOS bit in the SSMR2 register to 1 (N-channel open-drain output) and setting the BIDE bit in the SSMR2 register to 0 (standard mode). 4. N-channel open-drain output by setting the NCH bit in the U2C0 register to 1. Table 7.13 Port P3_4/TRCIOC/ SSI/RXD2/SCL2/TXD2/SDA2/IVREF3 Register PD3 SSUIICSR Synchronous Serial Communication Unit (Refer to Table 24.4 Association between Communication Modes and I/O Pins.) TRCPSR1 U2SR0 U2MR U2SMR INTCMP Timer RC Setting Function Bit PD3_4 IICSEL SSI output control SSI input control TRCIOC SEL RXD2 SEL TXD2 SEL SMD IICM INT3 CP0 — 101010210 Setting Value 0X 0 0 Other than 10b Other than 01b Other than 10b XXX X X X Input port (1) 1X 0 0 Other than 10b Other than 01b Other than 10b XXX X X X Output port (2) 0X 0 0 1 0 Other than 01b Other than 10b XXX X X Refer to Table 7.23 TRCIOC Pin Setting TRCIOC input (1) XX 0 0 1 0 Other than 01b Other than 10b XXX X X Refer to Table 7.23 TRCIOC Pin Setting TRCIOC output (2) X 0 0 1 XXXXXXXXX X X X SSI input (1) X 0 1 0 XXXXXXXXX X X X SSI output (2, 3) 0X 0 0 Other than 10b 01 Other than 10b XXX X X X RXD2 input (1) 0X 0 0 X X 0 1 Other than 10b 010 1 X X SCL2 input/ output (2, 4) X X 0 0 XXXX10 XX X TXD2 output (2, 4)1

0 X 0 0 XXXX10010 1 X X SDA2 input/

output (2, 4) 0X 0 0 Other than 10b Other than 01b Other than 10b XXX X 1 X Comparator B3 reference voltage input (IVREF3)

R8C/32A Group 7. I/O Ports REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 82 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. X: 0 or 1 Notes: 1. Pulled up by setting the PU07 bit in the PUR0 register to 1. 2. Output drive capacity high by setting the DRR07 bit in the DRR0 register to 1. 3. N-channel open-drain output by setting the SCKOS bit in the SSMR2 register to 1 (N-channel open-drain output). 4. N-channel open-drain output by setting the NODC bit in the U2SMR3 register to 1. X: 0 or 1 Notes: 1. Pulled up by setting the PU07 bit in the PUR0 register to 1. 2. Output drive capacity high by setting the DRR07 bit in the DRR0 register to 1. 3. N-channel open-drain output by setting the SOOS bit in the SSMR2 register to 1 (N-channel open-drain output). 4. N-channel open-drain output by setting the NCH bit in the U2C0 register to 1. Table 7.14 Port P3_5/SCL/SSCK/TRCIOD/CLK2 Register PD3 SSUIICSR ICCR1 Synchronous Serial Communication Unit (Refer to Table 24.4 Association between Communication Modes and I/O Pins.) TRCPSR1 U2SR1 U2MR Timer RC Setting Function Bit PD3_5 IICSEL ICE SSCK output control SSCK input control TRCIODSEL CLK2SEL0 SMD CKDIR —10 2 1 0 Setting Value 0 0X 0 0 Other than 10b 0 XXX X X Input port (1)

10 X X

10b 0 XXX X X Output port (2) X 1 1 X X X X X XXX X X SCL input/output (2) X 0 X 0 1 X X X XXX X X SSCK input (1) X 0 X 1 0 X X X XXX X X SSCK output (2, 3) 0X 0 0 1 0 0 XXX X Refer to Table

7.24 TRCIOD

TRCIOD input (1) X 0X 0 0 1 0 0 XXX X Refer to Table TRCIOD output (2) 0 0X 0 0 X X 1 XXX 1 X CLK2 input (2) X 0X 0 0 XX 1 0 0 1 0 X CLK2 output (2, 4) Table 7.15 Port P3_7/SSO/TXD 2/SDA2/RXD2/SCL2/TRAO/SDA Register PD3 SSUIICSR ICCR1 Synchronous Serial Communication Unit (Refer to Table 24.4 Association between Communication Modes and I/O Pins.) U2SR0 U2MR U2SMR TRAIOC Function Bit PD3_7 IICSEL ICE SSO output control SSO input control RXD2SEL TXD2SEL SMD IICM TOENA10102 1 0 Setting Value 0 10 X X Other than 10b Other than 01b XXX X 0 Input port (1) 0X 0 0 1 10 X X Other than 10b Other than 01b XXX X 0 Output port (2) 0X 0 0 X 1 1 X X XXXXX X X X X SDA input/output (2) X 0 X 0 1 XXXXX X X X X SSO input (1) X 0 X 1 0 XXXXX X X X X SSO output (2, 3) 0 10 X X 10 Other than 01b XXX X 0 RXD2 input (1) 0X 0 0 0 10 X X 10 Other than 01b 010 1 X SCL2 input/ output (2, 4)0X 0 0 X output (2, 4)1 0X 0 0 1 0 10 X X XX01010 1 X SDA2 input/ output (2, 4)0X 0 0 X 10 X X Other than 01b Other than 01b XXX X 1 TRAO output (2) 0X 0 0

R8C/32A Group 7. I/O Ports REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 83 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. X: 0 or 1 Notes: 1. Pulled up by setting the PU11 bit in the PUR1 register to 1. 2. Output drive capacity high by setting the DRR11 bit in the DRR1 register to 1. 3. N-channel open-drain output by setting the NCH bit in the U2C0 register to 1. X: 0 or 1 Notes: 1. Pulled up by setting the PU11 bit in the PUR1 register to 1. 2. Output drive capacity high by setting the DRR11 bit in the DRR1 register to 1. Table 7.16 Port P4_2/VREF Register ADCON1 FunctionBit ADSTBY Setting Value

0 Input port

1 Input port/VREF input

Table 7.17 Port P4_5/INT0 /RXD2/SCL2/ADTRG Register PD4 INTEN U2SR0 U2MR U2SMR ADMOD FunctionBit PD4_5 INT0EN RXD2SEL SMD IICM ADCAP 1 0 210 1 0 Setting Value

0 X Other than 11b X X X X X X Input port (1)

1 X Other than 11b X X X X X X Output port (2)

0 1 Other than 11b X X X X X X INT0 input (1)

0 X 1 1 XXX X X X RXD2 input (1)

0 X 1 1 010 1 X X SCL2 input/output (2, 3)

0 1 Other than 11b X X X X 1 1 ADTRG input (1) Table 7.18 Port P4_6/XIN/XCIN Register PD4 CM0 CM1 Circuit specifications FunctionBit PD4_6 CM01 CM03 CM04 CM05 CM10 CM11 CM12 CM13 Oscillation buffer Feedback resistor Setting Value

0 XX0X0XX0 O F F O F F Input port (1)

1 XX0X0XX0 O F F O F F Output port (2)

X 0XX ON ON XIN-XOUT oscillation (on-chip feedback resistor enabled) 1O N O F F XIN-XOUT oscillation (on-chip feedback resistor disabled) 0O F F O N XIN-XOUT oscillation stop (on-chip feedback resistor enabled) 1O F F O F F XIN-XOUT oscillation stop (on-chip feedback resistor disabled)

1 X 0 X

ON ON XCIN-XCOUT oscillation (on-chip feedback resistor enabled) 1O N O F F XCIN-XCOUT oscillation (on-chip feedback resistor disabled) 0O F F O N XCIN-XCOUT oscillation stop (on-chip feedback resistor enabled) 1O F F O F F XCIN-XCOUT oscillation stop (on-chip feedback resistor disabled) X X X 1 X X OFF OFF Oscillation stop (STOP mode)

R8C/32A Group 7. I/O Ports REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 84 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. X: 0 or 1 Note: 1. Pulled up by setting the PU11 bit in the PUR1 register to 1. 2. Output drive capacity high by setting the DRR11 bit in the DRR1 register to 1. 3. Since the XCIN-XCOUT oscill ation buffer operates with internal step-down power, the XCOUT output level cannot be used as the CMOS level signal directly. Table 7.19 Port P4_7/XOUT/XCOUT Register PD4 CM0 CM1 Circuit specifications FunctionBit PD4_7 CM01 CM03 CM04 CM05 CM10 CM11 CM12 CM13 Oscillation buffer Feedback resistor Setting Value X 0XX ON ON XIN-XOUT oscillation (on-chip feedback resistor enabled) 1O N O F F XIN-XOUT oscillation (on-chip feedback resistor disabled) 0O F F O N XIN-XOUT oscillation stop (on-chip feedback resistor enabled) 1O F F O F F XIN-XOUT oscillation stop (on-chip feedback resistor disabled) ON ON XCIN-XCOUT oscillation (on-chip feedback resistor enabled) (3) 1O N O F F XCIN-XCOUT oscillation (on-chip feedback resistor disabled) (3) 0O F F O N XCIN-XCOUT oscillation stop (on-chip feedback resistor enabled) 1O F F O F F XCIN-XCOUT oscillation stop (on-chip feedback resistor disabled) X X X 1 X X OFF OFF Oscillation stop (STOP mode)

R8C/32A Group 7. I/O Ports REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 85 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Note: 1. Set the TOCNT bit in the TRBIOC register to 0 in modes except for programmable waveform generation mode. X: 0 or 1 X: 0 or 1 X: 0 or 1 X: 0 or 1 Table 7.20 TRBO Pin Setting Register TRBIOC TRBMR FunctionBit TOCNT (1) TMOD1 TMOD0 Setting value 0 0 1 Programmable waveform generation mode 0 1 0 Programmable one-shot generation mode 0 1 1 Programmable wait one-shot generation mode 1 0 1 Programmable output port Table 7.21 TRCIOA Pin Setting Register TRCOER TRCMR TRCIOR0 TRCCR2 FunctionBit EA PWM2 IOA2 IOA1 IOA0 TCEG1 TCEG0 Setting Value 010 01 XX Timer waveform output (output compare function)1X 0 1 1 X X X X Timer mode (input capture function)1 10XXX 01 PWM2 mode TRCTRG input1X Table 7.22 TRCIOB Pin Setting Register TRCOER TRCMR TRCIOR0 FunctionBit EB PWM2 PWMB IOB2 IOB1 IOB0 Setting Value 0 0 X X X X PWM2 mode waveform output 0 1 1 X X X PWM mode waveform output 0100 01 Timer waveform output (output compare function)1X 0 1 0 1 X X Timer mode (input capture function)1 Table 7.23 TRCIOC Pin Setting Register TRCOER TRCMR TRCIOR1 FunctionBit EC PWM2 PWMC IOC2 IOC1 IOC0 Setting Value 0 1 1 X X X PWM mode waveform output 0 100 01 Timer waveform output (output compare function)1X 0 1 0 1 X X Timer mode (input capture function)1 Table 7.24 TRCIOD Pin Setting Register TRCOER TRCMR TRCIOR1 FunctionBit ED PWM2 PWMD IOD2 IOD1 IOD0 Setting Value 0 1 1 X X X PWM mode waveform output 0 100 01 Timer waveform output (output compare function)1X 0 1 0 1 X X Timer mode (input capture function)1

R8C/32A Group 7. I/O Ports REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 86 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

7.6 Unassigned Pin Handling

Table 7.25 lists Unassigned Pin Handling. Figure 7.9 shows the Unassigned Pin Handling. Notes: 1. If these ports are set to output mode and left open, they remain in input mode until they are switched to output mode by a program. The voltage level of these pins may be undefined and the power current may increase while the ports remain in input mode. The content of the direction registers may chang e due to noise or program runaway caused by noise. In order to enhance program reliability, t he program should periodically repeat the setting of the direction registers. 2. Connect these unassigned pins to the MCU using th e shortest wire length (2 cm or less) possible. 3. When the power-on reset function is in use. Figure 7.9 Unassigned Pin Handling Table 7.25 Unassigned Pin Handling Pin Name Connection Ports P1, P3_3 to P3_5, P3_7, P4_5

• After setting to input mode, connect each pin to VSS via a resistor (pull-down) or connect each pin to VCC via a resistor (pull-up). (2)
• After setting to output mode, leave these pins open. (1, 2) Ports P4_6, P4_7 Connect to VCC via a pull-up resistor (2) Port P4_2/VREF Connect to VCC RESET (3) Connect to VCC via a pull-up resistor (2) Note: 1. When the power-on reset function is in use. MCU Port P1, P3_3 to P3_5, P3_7, P4_5 (Input mode ) (Input mode) (Output mode) Open P4_6, P4_7 RESET (1) Port P4_2/VREF

R8C/32A Group 8. Bus REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 87 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 8. Bus The bus cycles differ when accessing ROM/RAM and when accessing SFR. Table 8.1 lists Bus Cycles by Access Area of R8C/32A Group (with Data Flash). ROM/RAM and SFR are connected to the CPU by an 8-bit bus. When accessing in word (16-bit) units, these areas are accessed twice in 8-bit units. Table 8.2 shows Access Units and Bus Operations. Table 8.2 Access Units and Bus Operations Table 8.1 Bus Cycles by Access Area of R8C/32A Group (with Data Flash) Access Area Bus Cycle SFR/Data flash 2 cycles of CPU clock Program ROM/RAM 1 cycle of CPU clock Area SFR, Data flash Even address Byte access ROM (program ROM), RAM Odd address Byte access Even address Word access Odd address Word access CPU clock Data Data Data Even EvenAddress CPU clock Data Address CPU clock Data Address CPU clock Data Address CPU clock Data Address CPU clock Data Address CPU clock Data Address CPU clock Data Address Data Data Odd Odd Data Even Even + 1 Data Data Odd Odd + 1 Data Data Even Even + 1 Data Data Odd Odd + 1 Data

R8C/32A Group 8. Bus REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 88 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. However, only the following SFRs are connected with the 16-bit bus: Interrupts: Each interrupt control register Timer RC: Registers TRC, TRCGRA, TRCGRB, TRCGRC, and TRCGRD SSU: Registers SSTDR, SSTDRH, SSRDR, and SSRDRH UART2: Registers U2MR, U2BRG, U2TB, U2C0, U2C1, U2RB, U2SMR5, U2SMR4, U2SMR3, U2SMR2, and U2SMR A/D converter: Registers AD0, AD1, AD2, AD3, AD4, AD5, AD6, AD7, ADMOD, ADINSEL, ADCON0, and ADCON1 Address match interrupt: Registers RMAD0, AIER0, RMAD1, and AIER1 Therefore, they are accessed on ce in 16-bit units. The bus operation is th e same as “Area: SFR, Data flash, Even address Byte Access” in Table 8.2 Access Units and Bus Operations, and 16-bit data is accessed at a time.

R8C/32A Group 9. Clock Generation Circuit REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 89 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 9. Clock Generation Circuit The following five circuits are incorporated in the clock generation circuit:

• XIN clock oscillation circuit
• XCIN clock oscillation circuit
• Low-speed on-chip oscillator
• High-speed on-chip oscillator
• Low-speed on-chip oscillator for watchdog timer

9.1 Overview

Table 9.1 lists the Specification Overview of Clock Generation Circuit. Figure 9.1 shows a Clock Generation Circuit (With XIN and XCIN Pins Shared). Figure 9.2 shows a Peripheral Function Clock and Figure 9.3 shows a Procedure for Reducing Internal Power Consumption Using VCA20 bit. Notes: 1. These pins can be used as P4_6 or P4_7 when using the on-chip oscillator clock as the CPU clock while the XIN clock oscillation circuit and the XCIN clock oscillation circuit are not used. 2. To input an external clock, set the CM05 bit in the CM0 register to 1 (XIN clock stops), the CM11 bit in the CM1 register to 1 (internal feedback resistor disabled), and the CM13 bit to 1 (XIN-XOUT pin). 3. The clock frequency is automatically set to up to 20 MHz by a divider when using the high-speed on-chip oscillator as the CPU clock source. Table 9.1 Specification Overview of Clock Generation Circuit Item XIN Clock Oscillation Circuit XCIN Clock Oscillation Circuit On-Chip Oscillator Low-Speed On-Chip Oscillator for Watchdog Timer High-Speed On-Chip Oscillator Low-Speed On-Chip Oscillator Applications • CPU clock source

• Peripheral function clock source
• CPU clock source
• Peripheral function clock source
• CPU clock source
• Peripheral function clock source
• CPU and peripheral function clock source when XIN clock stops oscillating
• CPU clock source
• Peripheral function clock source
• CPU and peripheral function clock source when XIN clock stops oscillating
• Watchdog timer clock source Clock frequency 0 to 20 MHz 32.768 kHz Approx. 40 MHz (3) Approx. 125 kHz Approx. 125 kHz Connectable oscillator
• C e r a m i c resonator
• Crystal oscillator
• Crystal oscillator −−− Oscillator connect pins XIN, XOUT (1) XCIN, XCOUT (1) − (1) − (1) − Oscillation stop, restart function Usable Usable Usable Usable Usable Oscillator status after reset Stop Stop Stop Oscillate Stop Others Externally generated clock can be input (2)
• Externally generated clock can be input
• On-chip feedback resistor Rf (connected/ not connected selectable) −−−

R8C/32A Group 9. Clock Generation Circuit REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 90 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 9.1 Clock Generation Circuit (With XIN and XCIN Pins Shared) S Q R Charge/discharge circuit Oscillation stop detection Interrupt generation circuit S Q R FRA00 High-speed on-chip oscillator FRA01 = 1 FRA01 = 0 CM14 a b c d e OCD2 = 0 OCD2 = 1 Divider Oscillation stop detection XIN clock CM02 WAIT instruction RESET CM10 = 1 (stop mode) a dc h b CM06 = 0 CM17 to CM16 = 11b CM06 = 1 CM06 = 0 CM17 to CM16 = 10b CM06 = 0 CM17 to CM16 = 01b CM06 = 0 CM17 to CM16 = 00b Detail of divider Oscillation Stop Detection Circuit Pulse generation circuit for clock edge detection and charge/discharge control XIN clock Forcible discharge when OCD0 = 0 OCD1 OCD2 bit switch signal CM14 bit switch signal Oscillation stop detection, Watchdog timer, Voltage monitor 1 interrupt, Voltage monitor 2 interrupt CM02, CM03, CM04, CM05, CM06, CM07: Bits in CM0 register CM10, CM13, CM14, CM16, CM17: Bits in CM1 register CM30: Bit in CM3 register OCD0, OCD1, OCD2: Bits in OCD register FRA00, FRA01, FRA03: Bits in FRA0 register e g FRA2 register fOCO (On-chip oscillator clock) fOCO-S g h System clock Low-speed on-chip oscillator FRA1 register Frequency adjustable Divider fC Power-on reset circuit Voltage detection circuit Divider (1/128) Power-on reset Software reset Interrupt request 1/81/2 CPU clock f32 fOCO40M fC4 fC32 fOCO-F fOCO fOCO128 fOCO-S Peripheral function clock fC2 fC fOCO-WDTLow-speed on-chip oscillator for watchdog timerCSPRO CM30 CM07 = 0 CM07 = 1 XIN clock XOUT/XCOUTXIN/XCIN CM04 XCIN clock CM01 = 0 CM13 CM05 Stop signal CM01 CM03 Watchdog timer interrupt Voltage monitor 1 interrupt Voltage monitor 2 interrupt FRA03 = 1 FRA03 = 0

R8C/32A Group 9. Clock Generation Circuit REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 91 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 9.2 Peripheral Function Clock UART0A/D converterTimer RBTimer RAINT0 SSU / I2C bus Watchdog timer Timer RE CPU clock f32 fOCO40M fOCO-F fC4 fC32 fOCO128 Timer RC UART2 fOCO-WDT fOCO CPU fC

R8C/32A Group 9. Clock Generation Circuit REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 92 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

9.2 Registers

9.2.1 System Clock Cont rol Register 0 (CM0)

Notes: 1. The CM05 bit stops the XIN clock when the high-speed on-chip oscillator mode or low-speed on-chip oscillator mode is selected. This bit cannot be used to detect wh ether the XIN clock has stopped. To stop the XIN clock, set the bits in the following order: (a) Set bits OCD1 to OCD0 in the OCD register to 00b. (b) Set the OCD2 bit to 1 (on-chip oscillator clock selected). 2. During external clock input, only the clock oscillation buffer stops and clock input is acknowledged. 3. Only when the CM05 bit is set to 1 (XIN clock stops) and the CM13 bit in the CM1 register is set to 0 (P4_6 and P4_7), P4_6 and P4_7 can be used as I/O ports. 4. When the MCU enters stop mode, the CM06 bit is set to 1 (divide-by-8 mode). 5. The CM04 bit can be set to 1 by a program but cannot be set to 0. 6. To use the XCIN clock, set the CM04 bit to 1. 7. Set the CM07 bit to 1 (XCIN clock) from 0 after se tting the CM04 bit to 1 (XCIN-XCOUT pin) and allowing XCIN clock oscillation to stabilize. Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the CM0 register. Address 0006h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol CM07 CM06 CM05 CM04 CM03 CM02 CM01 — A f t e r R e s e t 00101000 Bit Symbol Bit Name Function R/W b0 — Reserved bit Set to 0. R/W b1 CM01 XIN-XCIN switch bit 0: P4_6 and P4_7 set as XIN-XOUT pin 1: P4_6 and P4_7 set as XCIN-XCOUT pin R/W b2 CM02 Wait mode peripheral function clock stop bit 0: Peripheral function clock does not stop in wait mode 1: Peripheral function clock stops in wait mode R/W b3 CM03 XCIN clock stop bit 0: XCIN clock oscillates 1: XCIN clock stops R/W b4 CM04 Port/XCIN-XCOUT switch bit (5) 0: I/O ports P4_6 and P4_7 1: XCIN-XCOUT pin (6) R/W b5 CM05 XIN clock (XIN-XOUT) stop bit (1, 3) 0: XIN clock oscillates 1: XIN clock stops (2) R/W b6 CM06 System clock division select bit 0 (4) 0: Bits CM16 and CM17 in CM1 register enabled 1: Divide-by-8 mode R/W b7 CM07 XIN, XCIN clock select bit (7) 0: XIN clock 1: XCIN clock R/W

R8C/32A Group 9. Clock Generation Circuit REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 93 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

9.2.2 System Clock Cont rol Register 1 (CM1)

Notes: 1. When the CM06 bit is set to 0 (bits CM16 and CM17 enabled), bits CM16 and CM17 are enabled. 2. If the CM10 bit is set to 1 (stop mode) , the on-chip feedback resistor is disabled. 3. When the OCD2 bit is set to 0 (XIN clock selected), the CM14 bit can be set to 1 (low-speed on-chip oscillator off). When the OCD2 bit is set to 1 (on-chip oscillator clock selected), the CM14 bit is set to 0 (low-speed on-chip oscillator on). It remains unchanged even if 1 is written to it. 4. To use the voltage monitor 1 interrupt or voltage monitor 2 interrupt (when the digital filter is used), set the CM14 bit to 0 (low-speed on-chip oscillator on). 5. Once the CM13 bit is set to 1 by a program, it cannot be set to 0. Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the CM1 register. Address 0007h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol CM17 CM16 — CM14 CM13 CM12 CM11 CM10 A f t e r R e s e t 00100000 Bit Symbol Bit Name Function R/W b0 CM10 All clock stop control bit (2) 0: Clock oscillates 1: All clocks stop (stop mode) R/W b1 CM11 XIN-XOUT on-chip feedback resistor select bit 0: On-chip feedback resistor enabled 1: On-chip feedback resistor disabled R/W b2 CM12 XCIN-XCOUT on-chip feedback resistor select bit 0: On-chip feedback resistor enabled 1: On-chip feedback resistor disabled R/W b3 CM13 Port/XCIN-XCOUT switch bit (5) 0: I/O ports P4_6 and P4_7 1: XIN-XOUT pin R/W b4 CM14 Low-speed on-chip oscillator stop bit (3, 4) 0: Low-speed on-chip oscillator on 1: Low-speed on-chip oscillator off R/W b5 — Reserved bit Set to 1. R/W b6 CM16 System clock division select bit 1 (1) b7 b6 0 0: No division mode 0 1: Divide-by-2 mode 1 0: Divide-by-4 mode 1 1: Divide-by-16 mode R/W b7 CM17 R/W

R8C/32A Group 9. Clock Generation Circuit REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 94 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

9.2.3 System Clock Cont rol Register 3 (CM3)

Notes: 1. When the MCU exits wait mode by a peripheral function inte rrupt, the CM30 bit is set to 0 (other than wait mode). 2. Set the CM35 bit to 0 in stop mode. When the MCU enters wait mode, if the CM35 bit is set to 1 (no division), the CM06 bit in the CM0 register is set to 0 (bits CM16 and CM17 enabled) and bits CM17 and CM16 in the CM1 register is set to 00b (no division mode). 3. When bits CM37 and CM36 are set to 10b (high-speed on-chi p oscillator clock selected), the following will be set when the MCU exits wait mode or stop mode.

• OCD2 bit in OCD register = 1 (on-chip oscillator selected)
• FRA00 bit in FRA0 register = 1 (high-speed on-chip oscillator on)
• FRA01 bit in FRA0 register = 1 (high-speed on-chip oscillator selected) 4. When bits CM37 and CM36 are set to 11b (XIN clock selected), the following will be set when the MCU exits wait mode or stop mode.
• OM05 bit in OM0 register = 1 (XIN clock oscillates)
• OM13 bit in OM1 register = 1 (XIN-XOUT pin)
• OCD2 bit in OCD register = 0 (XIN clock selected) Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the CM3 register. CM30 bit (Wait Control Bit) When the CM30 bit is set to 1 (MCU enters wait mode), the CPU clock stops (wait mode). Since the XIN clock, XCIN clock, and the on-chip oscillator clock do not st op, the peripheral functions using these clocks continue operating. The MCU exits wait mode by a reset or peripheral function interrupt. If the MCU enters wait mode while the I flag is set to 0 (maskable interrupt disabled), it resumes executing the instruction immediately after the instruction to set the CM30 bit to 1 when exiting wait mode. If the MCU enters wait mode with the WAIT instruction, interrupt handling is performed by the CPU when exiting wait mode. Address 0009h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol CM37 CM36 CM35 — — — — CM30 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 CM30 Wait control bit (1) 0: Other than wait mode 1: MCU enters wait mode R/W b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b2 — b3 — b4 — b5 CM35 CPU clock division when exiting wait mode select bit (2) 0: Following settings are enabled: CM06 bit in CM0 register Bits CM16 and CM17 in CM1 register 1: No division R/W b6 CM36 CPU clock when exiting wait mode or stop mode select bit b7 b6 0 0: MCU exits with the CPU clock immediately before entering wait or stop mode. 0 1: Do not set. 1 0: High-speed on-chip oscillator clock selected (3) 1 1: XIN clock selected (4) R/W b7 CM37 R/W

R8C/32A Group 9. Clock Generation Circuit REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 95 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

9.2.4 Oscillation Stop De tection Register (OCD)

Notes: 1. Set bits OCD1 to OCD0 to 00b before the MCU enters stop mode, high-speed on-chip oscillator mode, or low- speed on-chip oscillator mode (XIN clock stops). 2. If the OCD2 bit is set to 1 (on-chip oscillator clock se lected), the CM14 bit is set to 0 (low-speed on-chip oscillator on). 3. The OCD2 bit is automaticall y set to 1 (on-chip oscillator clock selected) if XIN clock oscillation stop is detected while bits OCD1 to OCD0 are set to 11b. If the OCD3 bit is set to 1 (X IN clock stops), t he OCD2 bit remains unchanged even when set to 0 (XIN clock selected). 4. The OCD3 bit is enabled when the OCD0 bit is set to 1 (oscillation stop detection function enabled). 5. The OCD3 bit remains 0 (XIN clock oscillates) if bits OCD1 to OCD0 are set to 00b. 6. Refer to Figure 9.10 Procedure for Switching Clock Source from Low-Speed On-Chip Oscillator to XIN Clock for the switching procedure when the XIN clock re-oscillates after detecting oscillation stop. Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the OCD register.

9.2.5 High-Speed On-Chip Oscillat or Control Register 7 (FRA7)

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — — OCD3 OCD2 OCD1 OCD0 A f t e r R e s e t 00000100 Bit Symbol Bit Name Function R/W b0 OCD0 Oscillation stop detection enable bit (6) 0: Oscillation stop detection function disabled (1) 1: Oscillation stop detection function enabled R/W b1 OCD1 Oscillation stop detection interrupt enable bit 0: Disabled (1) 1: Enabled R/W b2 OCD2 System clock select bit (3) 0: XIN clock selected (6) 1: On-chip oscillator clock selected (2) R/W b3 OCD3 Clock monitor bit (4, 5) 0: XIN clock oscillates 1: XIN clock stops R b4 — Reserved bits Set to 0. R/W b5 — b6 — b7 — Address 0015h B i t b 7b 6b 5b 4b 3b 2b 1b 0 After Reset When shipping Bit Function R/W b7-b0 32 MHz frequency correction data is stored. The frequency can be adjusted by transferring this value to the FRA3 register and by transferring the correction value in the FRA6 register to the FRA1 register. R

R8C/32A Group 9. Clock Generation Circuit REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 96 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

9.2.6 High-Speed On-Chip Oscillat or Control Register 0 (FRA0)

Notes: 1. Change the FRA01 bit in the following conditions.

• FRA00 = 1 (high-speed on-chip oscillator on)
• The CM14 bit in the CM1 register = 0 (low-speed on-chip oscillator on)
• Bits FRA22 to FRA20 in the FRA2 register: All division mode can be set when VCC = 3.0 V to 5.5 V 000b to 111b Divide ratio of 4 or more when VCC = 2.7 V to 5.5 V 010b to 111b (divide-by-4 or more) Divide ratio of 8 or more when VCC = 2.2 V to 5.5 V 110b to 111b (divide-by-8 or more) 2. When setting the FRA01 bit to 0 (low-speed on-chip oscillator selected), do not set the FRA00 bit to 0 (high- speed on-chip oscillator off) at the same time. Set the FRA00 bit to 0 after setting the FRA01 bit to 0. Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the FRA0 register.

9.2.7 High-Speed On-Chip Oscillat or Control Register 1 (FRA1)

Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the FRA1 register. Address 0023h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — — FRA03 — FRA01 FRA00 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 FRA00 High-speed on-chip oscillator enable bit 0: High-speed on-chip oscillator off 1: HIgh-speed on-chip oscillator on R/W b1 FRA01 High-speed on-chip oscillator select bit (1) 0: Low-speed on-chip oscillator selected (2) 1: High-speed on-chip oscillator selected R/W b2 — Reserved bits Set to 0. R/W b3 FRA03 fOCO128 clock select bit 0: fOCO-S divided by 128 selected 1: fOCO-F divided by 128 selected R/W b4 — Reserved bits Set to 0. R/W b5 — b6 — b7 — Address 0024h B i t b 7b 6b 5b 4b 3b 2b 1b 0 After Reset When shipping Bit Function R/W b7-b0 The frequency of the high-speed on-chip o scillator can be adjusted by setting as follows:

40 MHz: FRA3 = value after reset

36.864 MHz: Transfer the value in the FRA4 register to the FRA1 register and the value in

the FRA5 register to the FRA3 register.

32 MHz: Transfer the value in the FRA6 regi ster to the FRA1 register and the value in

the FRA7 register to the FRA3 register. R/W

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9.2.8 High-Speed On-Chip Oscillat or Control Register 2 (FRA2)

Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the FRA2 register.

9.2.9 Clock Prescaler Reset Flag (CPSRF)

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — — — FRA22 FRA21 FRA20 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 FRA20 High-speed on-chip oscillator frequency switching bit Division selection These bits select the division ratio for the high- speed on-chip oscillator clock. b2 b1 b0 0 0 0: Divide-by-2 mode 0 0 1: Divide-by-3 mode 0 1 0: Divide-by-4 mode 0 1 1: Divide-by-5 mode 1 0 0: Divide-by-6 mode 1 0 1: Divide-by-7 mode 1 1 0: Divide-by-8 mode 1 1 1: Divide-by-9 mode R/W b1 FRA21 R/W b2 FRA22 R/W b3 — Reserved bits Set to 0. R/W b4 — b5 — b6 — b7 — Address 0028h B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 — Reserved bits Set to 0. R/W b1 — b2 — b3 — b4 — b5 — b6 — b7 CPSR Clock prescaler reset fl ag Setting this bit to 1 init ializes the clock prescaler. (When read, the content is 0) R/W

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9.2.10 High-Speed On-Chip Oscillat or Control Register 4 (FRA4)

9.2.11 High-Speed On-Chip Oscillat or Control Register 5 (FRA5)

9.2.12 High-Speed On-Chip Oscillat or Control Register 6 (FRA6)

9.2.13 High-Speed On-Chip Oscillat or Control Register 3 (FRA3)

Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the FRA3 register. Address 0029h B i t b 7b 6b 5b 4b 3b 2b 1b 0 After Reset When shipping Bit Function R/W b7-b0 36.864 MHz frequency correction data is stored. The frequency can be adjusted by transferring this value to the FRA1 register and by transferring the correction value in the FRA5 register to the FRA3 register. R Address 002Ah B i t b 7b 6b 5b 4b 3b 2b 1b 0 After Reset When shipping Bit Function R/W b7-b0 36.864 MHz frequency correction data is stored. The frequency can be adjusted by transferring this value to the FRA3 register and by transferring the correction value in the FRA4 register to the FRA1 register. R Address 002Bh B i t b 7b 6b 5b 4b 3b 2b 1b 0 After Reset When shipping Bit Function R/W b7-b0 32 MHz frequency correction data is stored. The frequency can be adjusted by transferring this value to the FRA1 register and by transferring the correction value in the FRA7 register to the FRA3 register. R Address 002Fh B i t b 7b 6b 5b 4b 3b 2b 1b 0 After Reset When shipping Bit Function R/W b7-b0 The frequency of the high-speed on-chip o scillator can be adjusted by setting as follows: the FRA5 register to the FRA3 register. the FRA7 register to the FRA3 register. R/W

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9.2.14 Voltage Detect Register 2 (VCA2)

Notes: 1. Use the VCA20 bit only when the MCU enters wait mode. To set the VCA20 bit, follow the procedure shown in Figure 9.3 Procedure for Reducing Internal Power Consumption Using VCA20 bit. 2. When the VCA20 bit is set to 1 (low consumption enabled), do not set the CM10 bit in the CM1 register to 1 (stop mode). 3. To use voltage monitor 0 reset, set the VCA25 bit to 1. After the VCA25 bit is set to 1 from 0, allow td(E-A) to elapse before the voltage detection circuit starts operation. 4. To use the voltage detection 1/comparator A1 interrupt or the VW1C3 bit in the VW1C register, set the VCA26 bit to 1. After the VCA26 bit is set to 1 from 0, allow td(E-A) to elapse before the voltage detection 1/comparator A1 circuit starts operation. 5. To use the voltage detection 2/compar ator A2 interrupt or the VCAC13 bit in the VCA1 register, set the VCA27 bit to 1. After the VCA27 bit is set to 1 from 0, allow td(E-A) to elapse before the voltage detection 2/comparator A2 circuit starts operation. Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting the VCA2 register. Address 0034h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol VCA27 VCA26 VCA25 VCA24 VCA23 VCA22 VCA21 VCA20 After Reset The LVDAS bit in the OFS register is set to 1. 00000000 After Reset The LVDAS bit in the OFS register is set to 0. 00100000 Bit Symbol Bit Name Function R/W b0 VCA20 Internal power low consumption enable bit (1) 0: Low consumption disabled 1: Low consumption enabled (2) R/W b1 VCA21 Comparator A1 reference voltage input select bit 0: Internal reference voltage 1: LVREF pin input voltage R/W b2 VCA22 LVCMP1 comparison voltage external input select bit 0: Supply voltage (VCC) 1: LVCMP1 pin input voltage R/W b3 VCA23 Comparator A2 reference voltage input select bit 0: Internal reference voltage 1: LVREF pin input voltage R/W b4 VCA24 LVCMP2 comparison voltage external input select bit 0: Supply voltage (VCC) (Vdet2_0) 1: LVCMP2 pin input voltage (Vdet2_EXT) R/W b5 VCA25 Voltage detection 0 enable bit (3) 0: Voltage detection 0 circuit disabled 1: Voltage detection 0 circuit enabled R/W b6 VCA26 Voltage detection 1/comparator A1 enable bit (4) 0: Voltage detection 1/comparator A1 circuit disabled 1: Voltage detection 1/comparator A1 circuit enabled R/W b7 VCA27 Voltage detection 2/comparator A2 enable bit (5) 0: Voltage detection 2/comparator A2 circuit disabled 1: Voltage detection 2/comparator A2 circuit enabled R/W

R8C/32A Group 9. Clock Generation Circuit REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 100 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 9.3 Procedure for Reducing Internal Power Consumption Using VCA20 bit Notes: 1. Execute this routine to handle all interrupts generated in wait mode. However, this does not apply if it is not necessary to start the high-speed clock or high-speed on-chip oscillator during the interrupt routine. 2. Do not set the VCA20 bit to 0 with the instruction immediately after setting the VCA20 bit to 1. Also, do not do the opposite. 3. When the VCA20 bit is set to 1, do not set the CM10 bit to 1 (stop mode). 4. When the MCU enters wait mode, follow 9.7.2 Wait Mode. Procedure for enabling reduced internal power consumption using VCA20 bit Enter low-speed clock mode or low-speed on-chip oscillator mode Stop XIN clock and high-speed on-chip oscillator clock VCA20 ← 1 (internal power low consumption enabled) (2, 3) Enter wait mode (4) VCA20 ← 0 (internal power low consumption disabled) (2) Start XIN clock or high-speed on-chip oscillator clock (Wait until XIN clock or high-speed on-chip oscillator clock oscillation stabilizes) Enter high-speed clock mode or high-speed on-chip oscillator mode In interrupt routine VCA20 ← 0 (internal power low consumption disabled) (2) (This is automatically set when exiting wait mode) Start XIN clock or high-speed on-chip oscillator clock Enter high-speed clock mode or high-speed on-chip oscillator mode Enter low-speed clock mode or low-speed on-chip oscillator mode Exit wait mode by interrupt Stop XIN clock and high-speed on-chip oscillator clock VCA20 ← 1 (internal power low consumption enabled) (2, 3) Interrupt handling completed Step (1) Step (2) Step (3) Step (4) Step (5) Step (6) Step (7) Step (8) Step (5) Step (6) Step (7) Step (8) (Wait until XIN clock or high-speed on-chip oscillator clock oscillation stabilizes) Step (1) Step (2) Step (3) If it is necessary to start the high-speed clock or high-speed on-chip oscillator during the interrupt routine, execute steps (6) to (7) in the routine. If the high-speed clock or high-speed on-chip oscillator starts during the interrupt routine, execute steps (1) to (3) at the end of the routine. (Note 1) Interrupt handling VCA20: Bit in VCA2 register

R8C/32A Group 9. Clock Generation Circuit REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 101 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. The clocks generated by the clock generation circuits are described below.

9.3 XIN Clock

The XIN clock is supplied by the XIN clock oscillation circui t. This clock is used as the clock source for the CPU and peripheral function clocks. The XIN clock oscillatio n circuit is configured by connecting a resonator between pins XIN and XOUT. The XIN clock oscillation circuit includes an on-ch ip feedback resistor, which is disconnected from the oscillation circuit in stop mode in order to reduce the amount of power consumed by the chip. The XIN clock oscillation circuit may also be config ured by feeding an externally generated clock to the XOUT pin. Figure 9.4 shows Examples of XIN Clock Connection Circuit. During and after a reset, the XIN clock stops. After setting the CM13 bit in the CM1 register to 1 (X IN-XOUT pin), the XIN clock starts oscillating when the CM05 bit in the CM0 register is set to 0 (XIN clock osci llates). After the XIN clock oscillation stabilizes, the XIN clock is used as the CPU clock source when the OCD2 bit in the OCD register is set to 0 (XIN clock selected). The power consumption can be reduced by setting the CM05 bit in the CM0 register to 1 (XIN clock stops) if the OCD2 bit is set to 1 (on-chip oscillator clock selected). When an externally generated clock is input to the XOUT pin, the XIN clock does not stop even if the CM05 bit is set to 1. If necessary, use an external circuit to stop the clock. In stop mode, all clocks including the XIN clock stop. Refer to 9.7 Power Control for details. Figure 9.4 Examples of XIN Clock Connection Circuit XIN XOUT MCU (on-chip feedback resistor) Rd (1) COUTCIN XIN XOUT MCU (on-chip feedback resistor) Externally generated clock VCC VSS Note: 1. Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity settings. Use the values recommended by the oscillator manufacturer. If the oscillator manufacturer's datasheet specifies that a feedback resistor be added to the chip externally, insert a feedback resistor between XIN and XOUT following the instructions. Open Ceramic resonator external circuit External clock input circuit Rf (1)

• When CM05 bit in CM0 register is set to 0 (XIN clock oscillates) and CM13 bit in CM1 register is set to 1 (XIN-XOUT pin)
• When CM05 bit in CM0 register is set to 1 (XIN clock stops), CM11 bit in CM1 register is set to 1 (internal feedback resistor disabled), and the CM13 bit is set to 1 (XIN-XOUT pin)

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9.4 On-Chip Oscillator Clock

The on-chip oscillator clock is supplied by the on-chip os cillator (high-speed on-chip oscillator or low-speed on- chip oscillator). This clock is selected by the FRA01 bit in the FRA0 register.

9.4.1 Low-Speed On-Chi p Oscillator Clock

The clock generated by the low-speed on-chip oscilla tor is used as the clock source for the CPU clock, peripheral function clock, fOCO, fOCO-S, and fOCO128. After a reset, the on-chip oscillator clock generate d by the low-speed on-chip oscillator divided by 1 (no division) is selected as the CPU clock. If the XIN clock stops oscillating when bits OCD1 to OCD0 in the OCD register ar e set to 11b, the low-speed on-chip oscillator automatically starts operating and supplies the necessary clock for the MCU. The frequency of the low-speed on-chip oscillator vari es depending on the supply voltage and the operating ambient temperature. Application products must be de signed with sufficient margin to allow for frequency changes.

9.4.2 High-Speed On-Chip Oscillator Clock

The clock generated by the high-speed on-chip oscillato r is used as the clock source for the CPU clock, peripheral function clock, fOCO, fOCO-F, fOCO40M, and fOCO128. To use the high-speed on-chip oscillator clock as the cl ock source for the CPU clock, peripheral clock, fOCO, and fOCO-F, set bits FRA20 to FRA22 in the FRA2 register as follows:

• All division mode can be set when VCC = 3.0 V to 5.5 V 000b to 111b
• Divide ratio of 4 or more when VCC = 2.7 V to 5.5 V 010b to 111b (divide by 4 or more)
• Divide ratio of 8 or more when VCC = 2.2 V to 5.5 V 110b to 111b (divide by 8 or more) After a reset, the on-chip oscillator cl ock generated by the high-speed on-c hip oscillator stops. Oscillation is started by setting the FRA00 bit in the FRA0 register to 1 (high-speed on-chip oscillator on). Frequency correction data is stored in registers FRA4 to FRA7. To adjust the frequency of the high-speed on-chip oscillat or clock to 36.864 MHz, first transfer the correction value in the FRA4 register to the FRA1 register and the correction valu e in the FRA5 register to the FRA3 register before using the values. This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in UART mode (refer to Table 21.8 and Table 22.8 Bit Rate Setting Example in UART Mode). To adjust the frequency of the high-speed on-chip oscillator clock to 32 MHz, first transfer the correction value in the FRA6 register to the FRA1 re gister and the correction value in the FRA7 register to the FRA3 register before using the values.

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9.5 XCIN Clock

The XCIN clock is supplied by the XCIN clock oscillation circuit. This clock is used as the clock source for the CPU and peripheral function clocks. The XCIN clock osci llation circuit is configured by connecting a resonator between the XCIN and XCOUT pins. The XCIN clock oscilla tion circuit includes an on-chip a feedback resistor, which is disconnected from the oscillation circuit in stop mode in order to reduce the amount of power consumed by the chip. The XCIN clock oscillation circuit may also be configured by feeding an externally generated clock to the XCIN pin. Figure 9.5 shows Examples of XCIN Clock Connection Circuits. During and after a reset, the XCIN clock stops. After setting the CM04 bit in the CM0 register to 1 (X CIN-XCOUT pin), the XCIN clock starts oscillating when the CM03 bit in the CM0 register is set to 1 (XCIN cloc k oscillates). After the XCIN clock oscillation stabilizes, the XCIN clock is used as the CPU clock source when the CM07 bit in the CM0 register is set to 1 (XCIN clock). To input an externally generated clock to the XCIN pin, also set the CM04 bit in the CM0 register to 1 (XCIN- XCOUT pin). Leave the XCOUT pin open at this time. This MCU has an on-chip feedback resistor, which can be disabled/enabled by the CM12 bit in the CM1 register. In stop mode, all clocks including the XCIN clock stop. Refer to 9.7 Power Control for details. Figure 9.5 Examples of XCIN Clock Connection Circuits XCIN XCOUT MCU (on-chip feedback resistor) Rd (1) COUTCIN XCIN XCOUT MCU (on-chip feedback resistor) Externally generated clock VCC VSS Note: 1. Insert a damping resistor and feedback resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the oscillator manufacturer. When the oscillation drive capacity is set to low, check that oscillation is stable. If the oscillator manufacturer's datasheet specifies that a feedback resistor be added to the chip externally, insert a feedback resistor between XCIN and XCOUT following the instructions. Open External crystal oscillator circuit External clock input circuit Rf (1)

• When CM03 bit in CM0 register is set to 0 (XCIN clock oscillates) and CM04 bit is set to 1 (XCIN-XCOUT pin)
• When CM03 bit in CM0 register is set to 1 (XCIN clock stops) and CM04 bit is set to 1 (XCIN-XCOUT pin)

R8C/32A Group 9. Clock Generation Circuit REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 104 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

9.6 CPU Clock and Peri pheral Function Clock

There are a CPU clock to operate the CPU and a peripheral function clock to operate the peripheral functions. Refer to Figure 9.1 Clock Generation Circuit (With XIN and XCIN Pins Shared).

9.6.1 System Clock

The system clock is the clock source for the CPU a nd peripheral function clocks. The XIN clock, the XCIN clock, or the on-chip oscillator clock can be selected.

9.6.2 CPU Clock

The CPU clock is an operating clock for the CPU and the watchdog timer. The system clock divided by 1 (no division), 2, 4, 8, or 16 is used as the CPU clock. Use the CM06 bit in the CM0 register and bits CM16 and CM17 in the CM1 register to select the value of the division. Also, use the XCIN clock while the XCIN clock oscillation stabilizes. After a reset, the low-speed on-chip oscillator clock divided by 1 (no division) is used as the CPU clock. When the MCU enters stop mode, the CM06 bit is set to 1 (divide-by-8 mode). To enter stop mode, set the CM35 bit in the CM3 register to 0 (settings of CM 06 in CM0 register and bits CM16 and CM17 in CM1 register enabled).

9.6.3 Peripheral Function Clo ck (f1, f2, f4, f8, and f32)

The peripheral function clock is an operating clock for the peripheral functions. The fi (i = 1, 2, 4, 8, and 32) clock is generated by the system clock divided by i. It is used for timers RA, RB, RC, RE, the serial interface, and the A/D converter. If the MCU enters wait mode after the CM02 bit in the CM0 register is set to 1 (peripheral function clock stops in wait mode), the fi clock stops. 9.6.4 fOCO fOCO is an operating clock for the peripheral functions. This clock runs at the same frequency as the on-chip os cillator clock and can be used as the source for timer RA. In wait mode, the fOCO clock does not stop. 9.6.5 fOCO40M fOCO40M is used as the count source for timer RC. This clock is generated by the high-speed on-chip oscillator and supplied by setting the FRA00 bit to 1. In wait mode, the fOCO40M clock does not stop. This clock can be used with supply voltage VCC = 3.0 to 5.5 V . 9.6.6 fOCO-F fOCO-F is used as the count source for timer RC and the A/D converter. fOCO-F is a clock generated by the high-speed on-chip oscilla tor and divided by i (i = 2, 3, 4, 5, 6, 7, 8, and 9; divide ratio selected by the FRA2 register). This clock is supplied by setting the FRA00 bit to 1. In wait mode, the fOCO-F clock does not stop.

R8C/32A Group 9. Clock Generation Circuit REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 105 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 9.6.7 fOCO-S fOCO-S is an operating clock for the voltage detection circuit. This clock is generated by the low-speed on-chip oscillator and supplied by setting the CM14 bit to 0 (low- speed on-chip oscillator on). In wait mode, the fOCO-S clock does not stop. 9.6.8 fOCO128 fOCO128 is a clock generated by dividing fOCO-S or fO CO-F by 128. When the FRA03 bit is set to 0, fOCO- S divided by 128 is selected. When this bit is set to 1, fOCO-F divided by 128 is selected. fOCO128 is configured as the capture signal used in the TRCGRA register for timer RC. 9.6.9 fC, fC2, fC4, and fC32 fC, fC2, fC4, and fC32 are used for timers RA, RE, and the serial interface. Use theses clocks while the XCIN clock oscillation stabilizes. 9.6.10 fOCO-WDT fOCO-WDT is an operating clock for the watchdog timer. This clock is generated by the low-speed on-chip oscillator for the watchdog timer and supplied by setting the CSPRO bit in the CSPR register to 1 (count source protect mode enabled). In count source protection mode for the watchdog timer, the fOCO-WDT clock does not stop.

R8C/32A Group 9. Clock Generation Circuit REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 106 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

9.7 Power Control

There are three power control modes. Al l modes other than wait mode and stop mode are referred to as standard operating mode.

9.7.1 Standard Operating Mode

Standard operating mode is further separated into four modes. In standard operating mode, the CPU and peripheral function clocks are supplied to operate the CPU and the peripheral functions. Power consumption control is enabled by controlling the CPU clock frequency. The higher the CPU clock frequency, the more processing power increases. The lower the CPU clock frequency, the more power consumption decreases. If unnecessary oscillator circuits st op, power consumption is further reduced. Before the clock sources for the CPU clock can be switch ed over, the new clock source needs to be oscillating and stable. If the new clock source is the XIN clock or XCIN clock, allow suffic ient wait time in a program until oscillation stabilizes before the MCU exits. −: Indicates that either 0 or 1 can be set. Table 9.2 Settings and Modes of Clock Associated Bits Modes OCD Register CM1 Register CM0 Register FRA0 Register OCD2 CM17, CM16 CM14 CM13 CM07 CM06 CM05 CM04 CM03 FRA01 FRA00 High-speed clock mode No division 0 00b − 10 0 0 −− − − Divide-by-2 0 01b − 10 0 0 −− − − Divide-by-4 0 10b − 10 0 0 −− − − Divide-by-8 0 −− 10 1 0 −− − − Divide-by-16 0 11b − 10 0 0 −− − − Low-speed clock mode No division − 00b −− 10 − 10 −− Divide-by-2 − 01b −− 10 − 10 −− Divide-by-4 − 10b −− 10 − 10 −− Divide-by-16 − 11b −− 10 − 10 −− High-speed on-chip oscillator mode No division 1 00b −− 00 −−− 11 Divide-by-2 1 01b −− 00 −−− 11 Divide-by-4 1 10b −− 00 −−− 11 Divide-by-16 1 11b −− 00 −−− 11 Low-speed on-chip oscillator mode No division 1 00b 0 − 00 −−− 0 − Divide-by-2 1 01b 0 − 00 −−− 0 − Divide-by-4 1 10b 0 − 00 −−− 0 − Divide-by-8 1 − 0 − 01 −−− 0 − Divide-by-16 1 11b 0 − 00 −−− 0 −

R8C/32A Group 9. Clock Generation Circuit REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 107 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

9.7.1.1 High-Speed Clock Mode

The XIN clock divided by 1 (no division), 2, 4, 8, or 16 is used as the CPU clock. If the CM14 bit is set to 0 (low-speed on-chip oscillator on) or the FRA00 bit in the FRA0 register is set to 1 (high-speed on-chip oscillator on), fOCO can be used for timer RA. Also, if the FRA00 bit is set to 1, fOCO40M can be used for timer RC. If the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used for the voltage detection circuit.

9.7.1.2 Low-Speed Clock Mode

The XCIN clock divided by 1 (no division), 2, 4, 8, or 16 is used as the CPU clock. In this mode, low consumption operation is enabled by stopping the XIN clock and the high-speed on-chip oscillator, and by setting the FMR27 bit in the FMR2 register to 1 (flash memory low-consumption-current read mode enabled). Also, if the FRA00 bit is set to 1, fOCO40M can be used for timer RC. If the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used for the voltage detection circuit. To enter wait mode from low-speed clock mode, lower consumption current in wait mode is enabled by setting the VCA20 bit in the VCA2 register to 1 (internal power low consumption enabled). To reduce the power consumption, refer to 31. Reducing Power Consumption.

9.7.1.3 High-Speed On-Chip Oscillator Mode

The high-speed on-chip oscillator is used as the on-chip oscillator clock when the FRA00 bit in the FRA0 register is set to 1 (high-speed on-chip oscillator on) and the FRA01 bit in the FRA0 register is set to 1. The on- chip oscillator divided by 1 (no division), 2, 4, 8, or 16 is used as the CPU clock. If the FRA00 bit is set to 1, fOCO40M can be used for timer RC. Also, if the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used for the voltage detection circuit.

9.7.1.4 Low-Speed On-Chip Oscillator Mode

If the CM14 bit in the CM1 register is set to 0 (low-speed on-chip oscillator on) and the FRA01 bit in the FRA0 register is set to 0, the low-speed on-chip oscillator is used as the on-chip oscillator clock. At this time, the on- chip oscillator clock divided by 1 (no division), 2, 4, 8 or 16 is used as the CPU clock. The on-chip oscillator clock is also the clock source for the peripheral function clocks. If the FRA00 bit is set to 1, fOCO40M can be used for timer RC. Also, if the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used for the voltage detection circuit. In this mode, low consumption operation is enabled by stopping the XIN clock and the high-speed on-chip oscillator, and by setting the FMR27 bit in the FMR2 register to 1 (flash memory low-consumption-current read mode enabled). To enter wait mode from low-speed clock mode, lower consumption current in wait mode is enabled by setting the VCA20 bit in the VCA2 register to 1 (internal power low consumption enabled). To reduce the power consumption, refer to 31. Reducing Power Consumption.

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9.7.2 Wait Mode

Since the CPU clock stops in wait mode, the CPU operating with the CPU clock and the watchdog timer when count source protection mode is disabled stop. Since th e XIN clock, XCIN clock, an d on-chip oscillator clock do not stop, the peripheral functions using these clocks continue operating.

9.7.2.1 Peripheral Functi on Clock Stop Function

If the CM02 bit is set to 1 (peripheral function clock stops in wait mode), the f1, f2, f4, f8, and f32 clocks stop in wait mode. This reduces power consumption.

9.7.2.2 Entering Wait Mode

The MCU enters wait mode by executing the WAIT instruction or setting the CM30 bit in the CM3 register to 1 (MCU enters wait mode). When the OCD2 bit in the OCD register is set to 1 (on- chip oscillator selected as system clock), set the OCD1 bit in the OCD register to 0 (oscillation stop det ection interrupt disabled) before executing the WAIT instruction or setting the CM30 bit in the CM3 register to 1(MCU enters wait mode). If the MCU enters wait mode while the OCD1 bit is set to 1 (oscillation stop detection interrupt enabled), current consumption is not reduced because the CPU clock does not stop.

9.7.2.3 Pin Status in Wait Mode

The I/O port retains the status immediately before the MCU enters wait mode.

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9.7.2.4 Exiting Wait Mode

The MCU exits wait mode by a reset or peripheral function interrupt. The peripheral function interrupts are affected by the CM02 bit. When the CM02 bit is set to 0 (peripheral function clock does not stop in wait mode), the peripheral function interrupts other than A/D conversion interrupts can be used to exit wait mode. When the CM02 bit is set to 1 (peripheral function clock stops in wait mode), the peripheral functions using the peripheral func tion clock stop and the peripheral functions operating with external signals or the on-chip oscillator clock can be used to exit wait mode. Table 9.3 lists Interrupts to Exit Wait Mode and Usage Conditions. Table 9.3 Interrupts to Exit Wait Mode and Usage Conditions Interrupt CM02 = 0 CM02 = 1 Serial interface interrupt Usable when operating with internal or external clock Usable when operating with external clock Synchronous serial communication unit interrupt / I 2C bus interface interrupt Usable in all modes (Do not use) Key input interrupt Usable Usable A/D conversion interrupt (Do not use) (Do not use) Timer RA interrupt Usable in all modes Us able if there is no filter in event counter mode. Usable by selecting fOCO, fC, or fC32 as count source. Timer RB interrupt Usable in all modes (Do not use) Timer RC interrupt Usable in all modes (Do not use) Timer RE interrupt Usable in all modes Usable when operating in real time clock mode INT interrupt Usable Usable (INT0, INT1, INT3 can be used if there is no filter.) Voltage monitor 1 interrupt Usable Usable Voltage monitor 2 interrupt Usable Usable Oscillation stop detection interrupt Usable (Do not use) Comparator A1 interrupt Usable Usable Comparator A2 interrupt Usable Usable

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9.7.3 Stop Mode

Since all oscillator circuits except fOCO-WDT stop in stop mode, the CPU and peripheral function clocks stop and the CPU and the peripheral functions operating with these clocks also stop. The least power required to operate the MCU is in stop mode. If the voltage applied to the VCC pin is VRAM or more, the contents of internal RAM is retained. The peripheral functions clocked by external signals continue operating. Table 9.4 lists Interrupts to Exit Stop Mode and Usage Conditions.

9.7.3.1 Entering Stop Mode

The MCU enters stop mode when the CM10 bit in the CM1 register is set to 1 (all clocks stop). At the same time, the CM06 bit in the CM0 register is set to 1 (divide-by-8 mode). To use stop mode, set the following before the MCU enters stop mode:

• Bits OCD1 to OCD0 in the OCD register = 00b
• CM35 bit in CM3 register = 0 (settings of CM06 bi t in CM0 register and bits CM16 and CM17 in CM1 register enabled)

9.7.3.2 Pin Status in Stop Mode

The I/O port retains the status before the MCU enters wait mode. However, when the CM13 bit in the CM1 register is set to 1 (XIN-XOUT pin), the XOUT(P4_7) pin is held “H”. When the CM13 bit is set to 0 (input ports P4_6 and P4_7), the P4_7(XOUT pin) is held in an input status. Table 9.4 Interrupts to Exit Stop Mode and Usage Conditions Interrupt Usage Conditions Key input interrupt − INT0 , INT1, INT3 interrupt Usable if there is no filter Timer RA interrupt Usable if there is no filter when external pulse is counted in event counter mode Serial interface interrupt When external clock selected Voltage monitor 1 interrupt Usable in digital filter disa bled mode (VW1C1 bit in VW1C register is set to 1) Voltage monitor 2 interrupt Usable in digital filter disa bled mode (VW2C1 bit in VW2C register is set to 1) Comparator A1 interrupt Usable in digital filter disabled mode (VW1C1 bit in VW1C register is set to 1) Comparator A2 interrupt Usable in digital filter disabled mode (VW2C1 bit in VW2C register is set to 1)

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9.7.3.3 Exiting Stop Mode

The MCU exits stop mode by a reset or peripheral function interrupt. Figure 9.8 shows the Time from Stop Mode to Interrupt Routine Execution. To use a peripheral function interrupt to exit stop mode, set up the following before setting the CM10 bit to 1. (1) Set the interrupt priority level in bits ILVL2 to IL VL0 of the peripheral function interrupts to be used for exiting stop mode. Set bits ILVL2 to ILVL0 of the peripheral function interrupts that are not to be used for exiting stop mode to 000b (interrupt disabled). (2) Set the I flag to 1. (3) Operate the peripheral function to be used for exiting stop mode. When the MCU exits stop mode by a peripheral function interrupt, the interrupt sequence is executed when an interrupt request is generated and the CPU clock supply starts. The clock used immediately before stop mode divided by 8 is used as the CPU clock when the MCU exits stop mode by a peripheral function interrupt. To enter stop mode, set the CM35 bit in the CM3 register to 0 (settings of CM06 bit in CM0 register and bits CM16 and CM17 in CM1 register enabled) Figure 9.8 Time from Stop Mode to Interrupt Routine Execution 100 µs (max.) FMSTP Bit (flash memory operates) (flash memory stops) FMR0 Register Period of system clock × 1 cycle + 60 µs (max.) Period of system clock × 1 cycle Period of CPU clock × 2 cycles Same as above Time until CPU Clock Supply (T3) Interrupt request generation Internal Power Stabilization Time (T0) Time until Flash Memory Activation (T2) 100 ms (max.) Stop mode Internal power stabilization time Oscillation time of CPU clock source used immediately before stop mode T4T2 Interrupt sequenceFlash memory activation sequence CPU clock restart sequence Time for Interrupt Sequence (T4) Period of CPU clock × 20 cycles The total of T0 to T4 is the time from wait mode to interrupt routine execution. Remarks Same as above100 µs (max.)

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9.8 Oscillation Stop Detection Function

The oscillation stop detection function detects the stop of the XIN clock oscillating circuit. The oscillation stop detection function can be enabled and disabled by the OCD0 bit in the OCD register. Table 9.5 lists the Specifications of Oscillation Stop Detection Function. When the XIN clock is the CPU clock so urce and bits OCD1 to OCD0 are set to 11b, the MCU is placed in the following state if the XIN clock stops.

• OCD2 bit in OCD register = 1 (on-chip oscillator clock selected)
• OCD3 bit in OCD register = 1 (XIN clock stops)
• CM14 bit in CM1 register = 0 (low-speed on-chip oscillator oscillates)
• Oscillation stop detection interrupt request is generated Table 9.5 Specifications of Oscillation Stop Detection Function Item Specification Oscillation stop detection clock and frequency bandwidth f(XIN) ≥ 2 MHz Enabled condition for oscillation stop detection function Bits OCD1 to OCD0 set to 11b Operation at oscillation stop detection Osc illation stop detection interrupt generated

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9.8.1 How to Use Oscillat ion Stop Detection Function

• The oscillation stop detection interr upt shares a vector with the voltage monitor 1 interrupt, the voltage monitor 2 interrupt, and the watchdog timer interrupt. To use the oscillation stop detection interrupt and watchdog timer interrupt, the interrupt source needs to be determined. Table 9.6 lists the Determination of Interrupt Sources for Oscillation Stop Detection, Watchdog Timer, V oltage Monitor 1, or V oltage Monitor 2 Interrupt. Figure 9.11 shows an Example of Determining Interrupt Sources for Oscillation Stop Detection, Watchdog Timer, V oltage Monitor 1, or V oltage Monitor 2 Interrupt.
• When the XIN clock restarts after oscillation stop, switch the XIN clock to the clock source for the CPU clock and the peripheral functions by a program. Figure 9.10 shows the Procedure for Switching Clock Source from Low-Speed On-C hip Oscillator to XIN Clock.
• To enter wait mode while the oscillation stop detection function is used, set the CM02 bit to 0 (peripheral function clock does not stop in wait mode).
• Since the oscillation stop detection function is a fu nction for cases where the XIN clock is stopped by an external cause, set bits OCD1 to OCD0 to 00b to stop or start the XIN clock by a program (select stop mode or change the CM05 bit).
• This function cannot be used when the XIN clock freque ncy is below 2 MHz. In this case, set bits OCD1 to OCD0 to 00b.
• To use the low-speed on-chip oscillator clock as th e clock source for the CPU clock and the peripheral functions after detecting the oscillat ion stop, set the FRA01 bit in the FRA0 register to 0 (low-speed on-chip oscillator selected) and bits OCD1 to OCD0 to 11b. To use the high-speed on-chip oscillator clock as the clock source for the CP U clock and the peripheral functions after detecting the oscillation stop, first se t the FRA00 bit to 1 (high-speed on-chip oscillator oscillates) and the FRA01 bit to 1 (high-speed on-chip oscillator selected). Then set bits OCD1 to OCD0 to 11b.

R8C/32A Group 9. Clock Generation Circuit REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 117 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 9.10 Procedure for Switching Clock Sour ce from Low-Speed On-Chip Oscillator to XIN Clock Table 9.6 Determination of Interrupt Sources fo r Oscillation Stop Detection, Watchdog Timer, Voltage Monitor 1, or Voltage Monitor 2 Interrupt Generated Interrupt Source Bit Indicati ng Interrupt Source Oscillation stop detection ((a) or (b)) (a) OCD3 bit in OCD register = 1 (b) OCD1 to OCD0 bits in OCD register = 11b and OCD2 bit = 1 Watchdog timer VW2C3 bit in VW2C register = 1 Voltage monitor 1 VW1C2 bit in VW1C register = 1 Voltage monitor 2 VW2C2 bit in VW2C register = 1 OCD3 to OCD0: Bits in OCD register Switch to XIN clock Check several times whether OCD3 bit is set to 0 (XIN clock oscillates) Set bits OCD1 to OCD0 to 00b Set OCD2 bit to 0 (XIN clock selected) End YES NO

R8C/32A Group 9. Clock Generation Circuit REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 118 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 9.11 Example of Determining Interrupt Sources for Oscillation Stop Detection, Watchdog Timer, Voltage Monitor 1, or Voltage Monitor 2 Interrupt Determination of Interrupt sources OCD3 = 1? (XIN clock stops) OCD1 = 1 (oscillation stop detection interrupt enabled) and OCD2 = 1 (on-chip oscillator clock selected as system clock)? VW2C3 = 1? (watchdog timer underflow) VW2C2 = 1? (Vdet2 passed) To oscillation stop detection interrupt routine To voltage monitor 1 interrupt routine To voltage monitor 2 interrupt routine To watchdog timer interrupt routine NO YES NO YES NO YES NO YES Note: 1. This disables multiple osc illation stop detection interrupts. OCD1 to OCD3: Bits in OCD register VW2C2, VW2C3: Bits in VW2C register Set OCD1 bit to 0 (oscillation stop detection interrupt disabled) (1)

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9.9 Notes on Clock Generation Circuit

9.9.1 Stop Mode

To enter stop mode, set the FMR01 bit in the FMR0 regi ster to 0 (CPU rewrite mode disabled) and then the CM10 bit in the CM1 register to 1 (stop mode). An instruction queue pre-reads 4 bytes from the instruction which sets the CM10 bit to 1 (stop mode) and the program stops. Insert at least four NOP instructions following the JM P.B instruction after the instruction which sets the CM10 bit to 1.

• Program example to enter stop mode BCLR 1,FMR0 ; CPU rewrite mode disabled BSET 0,PRCR ; Protect disabled FSET I ; Enable interrupt BSET 0,CM1 ; Stop mode JMP.B LABEL_001 LABEL_001: NOP NOP NOP NOP

9.9.2 Wait Mode

To enter wait mode with the WAIT instruction, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and then execute the WAIT instruction. An instruction queu e pre-reads 4 bytes from the WAIT instruction and the program stops. Insert at least four NOP instructions after the WAIT instruction.

• Program example to execute the WAIT instruction BCLR 1,FMR0 ; CPU rewrite mode disabled FSET I ; Enable interrupt WAIT ; Wait mode NOP NOP NOP NOP

9.9.3 Oscillation Stop Detection Function

Since the oscillation stop detection function cannot be used if the XIN clock frequency is below 2 MHz, set bits OCD1 to OCD0 to 00b.

9.9.4 Oscillation Circuit Constants

Consult the oscillator manufacturer to determine the optimal oscillation circuit constants for the user system. To use the MCU with supply voltage below VCC = 2.7 V , it is recommended to set the CM11 bit in the CM1 register to 1 (on-chip feedback resistor disabled) and connect the feedback resistor to the chip externally.

R8C/32A Group 10. Protection REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 120 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 10. Protection The protection function protects important registers from being easily overwritten if a program runs out of control. The registers protected by the PRCR register are as follows:

• Registers protected by PRC0 bit: Registers CM0, CM1, CM3, OCD, FRA0, FRA1, FRA2, and FRA3
• Registers protected by PRC1 bit: Registers PM0 and PM1
• Registers protected by PRC3 bit: Registers OCVREFCR, VCA2, VD1LS, VW0C, VW1C, and VW2C

10.1 Register

10.1.1 Protect Register (PRCR)

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — — PRC3 — PRC1 PRC0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 PRC0 Protect bit 0 Enables writing to re gisters CM0, CM1, CM3, OCD, FRA0, FRA1, FRA2, and FRA3. 0: Write disabled 1: Write enabled R/W b1 PRC1 Protect bit 1 Enables writing to registers PM0 and PM1. 0: Write disabled 1: Write enabled R/W b2 — Reserved bit Set to 0. R/W b3 PRC3 Protect bit 3 Enables writing to registers OCVREFCR, VCA2, VD1LS, VW0C, VW1C, and VW2C. 0: Write disabled 1: Write enabled R/W b4 — Reserved bits Set to 0. R/W b5 — b6 — Reserved bits When read, the content is 0. R b7 —

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11.1 Overview

11.1.1 Types of Interrupts

Figure 11.1 shows the Types of Interrupts. Figure 11.1 Types of Interrupts

• Maskable interrupts: These interrupts are enabled or disabled by the interrupt enable flag (I flag). The interrupt priority can be changed based on the interrupt priority level.
• Non-maskable interrupts: These interrup ts are not enabled or disabled by the interrupt enable flag (I flag). The interrupt priority cannot be changed based on the interrupt priority level. Interrupts (non-maskable interrupts) Hardware Software (non-maskable interrupts) (maskable interrupts) Special Peripheral function (1) Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction INT instruction Watchdog timer Oscillation stop detection Voltage monitor 1/comparator A1 (3) Voltage monitor 2/comparator A2 (3) Single step (2) Address break (2) Address match Notes: 1. Peripheral function interrupts are generated by the peripheral functions in the MCU. 2. Do not use these interrupts. This is provided exclusively for use by development tools. 3. A non-maskable or maskable interrupt can be selected by bits IRQ1SEL and IRQ2SEL in the CMPA register.

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11.1.2 Software Interrupts

A software interrupt is generated when an instruction is executed. Software interrupts are non-maskable.

11.1.2.1 Undefined Instruction Interrupt

An undefined instruction interrupt is generated when the UND instruction is executed.

11.1.2.2 Overflow Interrupt

An overflow interrupt is generated wh en the O flag is set to 1 (arithmetic operation overflow) and the INTO instruction is executed. Instructions that set the O flag are as follows: ABS, ADC, ADCF, ADD, CMP, DIV , DIVU, DIVX, NEG , RMPA, SBB, SHA, and SUB.

11.1.2.3 BRK Interrupt

A BRK interrupt is generated when the BRK instruction is executed.

11.1.2.4 INT Instruction Interrupt

An INT instruction interrupt is generated when the INT instruction is executed. Software interrupt numbers 0 to 63 can be specified with the INT in struction. Because some software interrupt numbers are assigned to peripheral function interrupts, the same interrupt routine as for peripheral function interrupts can be executed by executing the INT instruction. For software interrupt numbers 0 to 31, the U flag is saved on the stack during in struction execution and the U flag is set to 0 (ISP selected) before the interrupt sequ ence is executed. The U flag is restored from the stack when returning from the interrupt routine. For software interrupt numbers 32 to 63, the U flag does not change state during instruction execution, and the selected SP is used.

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11.1.3 Special Interrupts

Special interrupts are non-maskable.

11.1.3.1 Watchdog Timer Interrupt

A watchdog timer interrupt is generated by the watchdog timer. For details, refer to 14. Watchdog Timer.

11.1.3.2 Oscillation Stop Detection Interrupt

An oscillation stop detection interrupt is generated by the oscillation stop detection function. For details of the oscillation stop detection function, refer to 9. Clock Generation Circuit.

11.1.3.3 Voltage Monitor 1/Comparator A1 Interrupt

A voltage monitor 1/comparator A1 interrupt is generate d by the voltage detection circuit or the comparator A. A non-maskable or maskable interrupt can be selected by IRQ1SEL bit in the CMPA register. For details of the voltage detection circuit, refer to 6. Voltage Detection Circuit and for details of the comparator A, refer to 28. Comparator A.

11.1.3.4 Voltage Monitor 2/Comparator A2 Interrupt

A voltage monitor 2/comparator A2 interrupt is generate d by the voltage detection circuit or the comparator A. A non-maskable or maskable interrupt can be selected by IRQ2SEL bit in the CMPA register. For details of the voltage detection circuit, refer to 6. Voltage Detection Circuit and for details of the comparator A, refer to 28. Comparator A.

11.1.3.5 Single-Step Interrupt, and Address Break Interrupt

Do not use these interrupts. They are provided exclusively for use by development tools.

11.1.3.6 Address Match Interrupt

An address match interrupt is generated immediately before executing an instruction that is stored at an address indicated by registers RMAD0 to RMAD1 if the AIER0 bit in the AIER0 register or the AIER1 bit in the AIER1 register is set to 1 (address match interrupt enabled). For details of the address match interrupt, refer to 11.6 Address Match Interrupt.

11.1.4 Peripheral Function Interrupts

A peripheral function interrupt is generated by a peripheral function in the MCU. Peripheral function interrupts are maskable. Refer to Table 11.2 Relocatable Vector Tables for sources of the corresponding peripheral function interrupt. For details of peripheral functions , refer to the descriptions of individual peripheral functions.

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11.1.5 Interrupts and Interrupt Vectors

There are 4 bytes in each vector. Set the starting addre ss of an interrupt routine in each interrupt vector. When an interrupt request is acknowledged, the CPU branches to the address set in the corresponding interrupt vector. Figure 11.2 shows an Interrupt Vector. Figure 11.2 Interrupt Vector

11.1.5.1 Fixed Vector Tables

The fixed vector tables are allocated addresses 0FFDCh to 0FFFFh. Table 11.1 lists the Fixed Vector Ta bles. The vector addresses (H) of fixed vectors are used by the ID code check function. For details, refer to 30.3 Functions to Prevent Flash Memory from being Rewritten. Note: 1. Do not use these interrupts. They are provid ed exclusively for use by development tools. Table 11.1 Fixed Vector Tables Interrupt Source Vector Addresses Address (L) to (H) Remarks Reference Undefined instruction 0FFDCh to 0FFDFh Interrupt with UND instruction R8C/Tiny Series Software Manual Overflow 0FFE0h to 0FFE3h Interrupt with INTO instruction BRK instruction 0FFE4h to 0FFE7h If the content of address 0FFE7h is FFh, program execution starts from the address shown by the vector in the relocatable vector table. Address match 0FFE8h to 0FFEBh 11.6 Address Match Interrupt Single step (1) 0FFECh to 0FFEFh Watchdog timer, Oscillation stop detection, Voltage monitor 1/comparator A1, Voltage monitor 2/comparator A2 0FFF0h to 0FFF3h 14. Watchdog Timer 9. Clock Generation Circuit 6. Voltage Detection Circuit 28. Comparator A Address break (1) 0FFF4h to 0FFF7h (Reserved) 0FFF8h to 0FFFBh Reset 0FFFCh to 0FFFFh 5. Resets Vector address (L) Vector address (H) MSB LSB Low-order address Middle-order address High-order address0 0 0 0 0 0 0 0 0 0 0 0

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11.1.5.2 Relocatable Vector Tables

The relocatable vector tables occupy 256 bytes beginning from the starting address set in the INTB register. Table 11.2 lists the Relocatable Vector Tables. Notes: 1. These addresses are relative to those in the INTB register. 2. Selectable by the IICSEL bit in the SSUIICSR register. 3. These interrupts are not disabled by the I flag. Table 11.2 Relocatable Vector Tables Interrupt Source Vector Addresses (1) Address (L) to Address (H) Software Interrupt Number Interrupt Control Register Reference BRK instruction (3) +0 to +3 (0000h to 0003h) 0 − R8C/Tiny Series Software Manual Flash memory ready +4 to +7 (0004h to 0007h) 1 FMRDYIC 30. Flash Memory (Reserved) 2 to 5 −− (Reserved) +24 to +27 (0018h to 001Bh) 6 −− Timer RC +28 to +31 (001Ch to 001Fh) 7 TRCIC 19. Timer RC (Reserved) +32 to +35 (0020h to 0023h) 8 −− (Reserved) +36 to +39 (0024h to 0027h) 9 −− Timer RE +40 to +43 (0028h to 002Bh) 10 TREIC 20. Timer RE UART2 transmit/NACK2 +44 to +47 (002Ch to 002Fh) 11 S2TIC 22. Serial Interface (UART2)UART2 receive/ACK2 +48 to +51 (0030h to 0033h) 12 S2RIC Key input +52 to +55 (0034h to 0037h) 13 KUPIC 11.5 Key Input Interrupt A/D conversion +56 to +59 (0038h to 003Bh) 14 ADIC 27. A/D Converter Synchronous serial communication unit / I bus interface (2) +60 to +63 (003Ch to 003Fh) 15 SSUIC/IICIC 24. Synchronous Serial Communication Unit (SSU), 25. I2C bus Interface (Reserved) 16 −− UART0 transmit +68 to +71 (0044h to 0047h) 17 S0TIC 21. Serial Interface (UART0)UART0 receive +72 to +75 (0048h to 004Bh) 18 S0RIC (Reserved) 19 −− (Reserved) 20 −− (Reserved) +84 to +87 (0054h to 0057h) 21 −− Timer RA +88 to +91 (0058h to 005Bh) 22 TRAIC 17. Timer RA (Reserved) 23 −− Timer RB +96 to +99 (0060h to 0063h) 24 TRBIC 18. Timer RB INT1 +100 to +103 (0064h to 0067h) 25 INT1IC 11.4 INT Interrupt INT3 +104 to +107 (0068h to 006Bh) 26 INT3IC (Reserved) 27 −− (Reserved) 28 −− INT0 +116 to +119 (0074h to 0077h) 29 INT0IC 11.4 INT Interrupt UART2 bus collision detection +120 to +123 (0078h to 007Bh) 30 U2BCNIC 22. Serial Interface (UART2) (Reserved) 31 −− Software (3) +128 to +131 (0080h to 0083h) to +164 to +167 (00A4h to 00A7h) 32 to 41 − R8C/Tiny Series Software Manual (Reserved) 42 to 49 −− Voltage monitor 1/ comparator A1 +200 to +203 (00C8h to 00CBh) 50 VCMP1IC 6. Voltage Detection Circuit 28. Comparator AVoltage monitor 2/ comparator A2 +204 to +207 (00CCh to 00CFh) 51 VCMP2IC (Reserved) 52 to 55 −− Software (3) +224 to +227 (00E0h to 00E3h) to +252 to +255 (00FCh to 00FFh) 56 to 63 − R8C/Tiny Series Software Manual

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11.2 Registers

(TREIC, S2TIC, S2RIC, KUPIC, ADIC, S0TIC, S0RIC, TRAIC, TRBIC, U2BCNIC, VCMP1IC, VCMP2IC) Note: 1. Only 0 can be written to the IR bit. Do not write 1 to this bit. Rewrite the interrupt control register when an interrupt request corresponding to the register is not generated. Refer to 11.8.5 Rewriting Interrupt Control Register. Address 004Ah (TREIC), 004Bh (S2TIC), 004Ch (S2RIC), 004Dh (KUPIC), 004Eh (ADIC), 0051h (S0TIC), 0052h (S0RIC), 0056h (TRAIC), 0058h (TRBIC), 005Eh (U2BCNIC), 0072h (VCMP1IC), 0073h (VCMP2IC), B i t b 7b 6b 5b 4b 3b 2b 1b 0 S y m b o l — — — — I R I L V L 2 I L V L 1 I L V L 0 A f t e r R e s e t XXXXX000 Bit Symbol Bit Name Function R/W b0 ILVL0 Interrupt priority level select bit b2 b1 b0 0 0 0: Level 0 (interrupt disabled) 0 0 1: Level 1 0 1 0: Level 2 0 1 1: Level 3 1 0 0: Level 4 1 0 1: Level 5 1 1 0: Level 6 1 1 1: Level 7 R/W b1 ILVL1 R/W b2 ILVL2 R/W b3 IR Interrupt request bit 0: No interrupt requested 1: Interrupt requested R/W (1) b4 — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. b5 — b6 — b7 —

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11.2.2 Interrupt Control Register (FMRDYIC TRCIC, SSUIC/IICIC)

Note: 1. Selectable by the IICSEL bi t in the SSUIICSR register. Rewrite the interrupt control register when an interrupt request corresponding to the register is not generated. Refer to 11.8.5 Rewriting Interrupt Control Register. Address 0041h (FMRDYIC), 0047h (TRCIC), 004Fh (SSUIC/IICIC (1)) B i t b 7b 6b 5b 4b 3b 2b 1b 0 S y m b o l ————I R I L V L 2 I L V L 1 I L V L 0 A f t e r R e s e t XXXXX000 Bit Symbol Bit Name Function R/W b0 ILVL0 Interrupt priority level select bit b2 b1 b0 0 0 0: Level 0 (interrupt disabled) 0 0 1: Level 1 0 1 0: Level 2 0 1 1: Level 3 1 0 0: Level 4 1 0 1: Level 5 1 1 0: Level 6 1 1 1: Level 7 R/W b1 ILVL1 R/W b2 ILVL2 R/W b3 IR Interrupt request bit 0: No interrupt requested 1: Interrupt requested R b4 — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. b5 — b6 — b7 —

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11.2.3 INTi Interrupt Control Regi ster (INTiIC) (i = 0, 1, 3)

Notes: 1. Only 0 can be written to the IR bit. Do not write 1 to this bit. 2. If the INTiPL bit in the INTEN register is set to 1 (both edges), set the POL bit to 0 (falling edge selected). 3. The IR bit may be set to 1 (interrupt requeste d) when the POL bit is rewritten. Refer to 11.8.4 Changing Interrupt Sources. Rewrite the interrupt control register when an interrupt request corresponding to the register is not generated. Refer to 11.8.5 Rewriting Interrupt Control Register. Address 0059h (INT1IC), 005Ah (INT3IC), 005Dh (INT0IC) B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — POL IR ILVL2 ILVL1 ILVL0 After Reset X X 0 0 X 0 0 0 Bit Symbol Bit Name Function R/W b0 ILVL0 Interrupt priority level select bit b2 b1 b0 0 0 0: Level 0 (interrupt disabled) 0 0 1: Level 1 0 1 0: Level 2 0 1 1: Level 3 1 0 0: Level 4 1 0 1: Level 5 1 1 0: Level 6 1 1 1: Level 7 R/W b1 ILVL1 R/W b2 ILVL2 R/W b3 IR Interrupt request bit 0: No interrupt requested 1: Interrupt requested R/W (1) b4 POL Polarity switch bit (3) 0: Falling edge selected 1: Rising edge selected (2) R/W b5 — Reserved bit Set to 0. R/W b6 — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. b7 —

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11.3 Interrupt Control

The following describes enabling and disabling maskable interrupts and setting the acknowledgement priority. This description does not apply to non-maskable interrupts. Use the I flag in the FLG register, IPL, and bits ILVL2 to ILVL0 in the corresponding interrupt control register to enable or disable a maskab le interrupt. Whether an inte rrupt is requested or not is indicated by the IR bit in the corresponding interrupt control register.

11.3.1 I Flag

The I flag enables or disables maskable interrupts. Setting the I flag to 1 (enabled) enables maskable interrupts. Setting the I flag to 0 (disabled) disables all maskable interrupts.

11.3.2 IR Bit

The IR bit is set to 1 (interrupt requ ested) when an interrupt request is ge nerated. After the interrupt request is acknowledged and the CPU branches to the corresponding interrupt vector, the IR bit is set to 0 (no interrupt requested). The IR bit can be set to 0 by a program. Do not write 1 to this bit. However, the IR bit operations of the timer RC interrupt, the synchronous serial communication unit interrupt, the I 2C bus interface interrupt, and the flash memory interrupt are different. Refer to 11.7 Timer RC Interrupt, Synchronous Serial Communic ation Unit Interrupt, I 2C bus Interface Interrupt, and Flash Memory Interrupt (Interrupts with Multiple Interrupt Request Sources).

11.3.3 Bits ILVL2 to ILVL0, IPL

Interrupt priority levels can be set using bits ILVL2 to ILVL0. Table 11.3 lists the Settings of Interrupt Priority Leve ls and Table 11.4 lists the Interrupt Priority Levels Enabled by IPL. The following are the conditions when an interrupt is acknowledged:

• I flag = 1
• IR bit = 1
• Interrupt priority level > IPL The I flag, IR bit, bits ILVL2 to ILVL0, and IPL are independent of each other. They do not affect one another. Table 11.3 Settings of Interrupt Priority Levels Bits ILVL2 to ILVL0 Interrupt Priority Level Priority 000b Level 0 (interrupt disabled) − 001b Level 1 Low 010b Level 2 011b Level 3 100b Level 4 101b Level 5 110b Level 6 111b Level 7 High Table 11.4 Interrupt Priority Levels Enabled by IPL IPL Enabled Interrupt Priority Level 000b Interrupt level 1 and above 001b Interrupt level 2 and above 010b Interrupt level 3 and above 011b Interrupt level 4 and above 100b Interrupt level 5 and above 101b Interrupt level 6 and above 110b Interrupt level 7 and above 111b All maskable interrupts are disabled

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11.3.4 Interrupt Sequence

The following describes an interrupt sequence which is performed from when an interrupt request is acknowledged until the interrupt routine is executed. When an interrupt request is generated while an instruct ion is being executed, the CPU determines its interrupt priority level after the instruction is completed. The CPU starts the interrupt sequence from the following cycle. However, for the SMOVB, SMOVF, SSTR, or RMPA instruction, if an interrupt request is generated while the instruction is being executed, the MCU suspends the instruction to start the interrupt sequence. The interrupt sequence is performed as indicated below. Figure 11.3 shows the Time Required for Executing Interrupt Sequence. (1) The CPU obtains interrupt information (interrupt nu mber and interrupt request level) by reading address 00000h. The IR bit for the corresponding interrupt is set to 0 (no interrupt requested). (2) (2) The FLG register is saved to a temporary register (1) in the CPU immediately before entering the interrupt sequence. (3) The I, D and U flags in the FLG register are set as follows: The I flag is set to 0 (interrupts disabled). The D flag is set to 0 (single-step interrupt disabled). The U flag is set to 0 (ISP selected). However, the U flag does not change state if an INT instruction for software interrupt number 32 to 63 is executed. (4) The CPU internal temporary register (1) is saved on the stack. (5) The PC is saved on the stack. (6) The interrupt priority level of the acknowledged interrupt is set in the IPL. (7) The starting address of the interrupt routine se t in the interrupt vector is stored in the PC. After the interrupt sequence is completed, instructions are executed from the starting address of the interrupt routine. Figure 11.3 Time Required for Executing Interrupt Sequence Notes: 1. These registers cannot be accessed by the user. 2. Refer to 11.7 Timer RC Interrupt, Synchronous Serial Communication Unit Interrupt, I 2C bus Interface Interrupt, and Flash Memory Interrupt (Interrupts with Multiple Interrupt Request Sources) for the IR bit operations of the timer RC Interrupt, the Synchronous Serial Communication unit Interrupt, and the I2C bus Interface Interrupt. 123456789 1 0 11 12 13 14 15 16 17 18 19 20 CPU Clock Address Bus Data Bus RD WR Address 0000h Undefined Undefined Undefined Interrupt information SP-2 SP-1 SP-4 SP-3 VEC VEC+1 VEC+2 PC SP-2

contents

Note: The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the instruction queue buffer is ready to acknowledge instructions.

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11.3.5 Interrupt Response Time

Figure 11.4 shows the Interrupt Response Time. The interrupt response time is the period from when an interrupt request is generated until the first instruction in the interrupt routine is executed. The interrupt response time includes the period from when an interru pt request is generated until the currently executing instruction is completed (refer to (a) in Figure 11.4) and the period required for executing the interrupt sequence (20 cycles, refer to (b) in Figure 11.4). Figure 11.4 Interrupt Response Time

11.3.6 IPL Change when Interrupt Request is Acknowledged

When a maskable interrupt request is acknowledged, the interrupt priority level of the acknowledged interrupt is set in the IPL. When a software interrupt or special interrupt request is acknowledged, the level listed in Table 11.5 is set in the IPL. Table 11.5 lists the IPL Value When Software or Special Interrupt is Acknowledged. Table 11.5 IPL Value When Software or Special Interrupt is Acknowledged Interrupt Source without Interrupt Priority Level Value Set in IPL Watchdog timer, oscillation stop detection, voltage monitor 1/comparator A1, voltage monitor 2/comparator A2, address break Software, address match, single-step Not changed Interrupt request generation Interrupt request acknowledgement Instruction Interrupt sequence Instruction in interrupt routine Time (a) 20 cycles (b) Interrupt response time (a) The period from when an interrupt request is generated until the currently executing instruction is completed. The length of time varies depending on the instruction being executed. The DIVX instruction requires the longest time, 30 cycles (no wait states if the divisor is a register). (b) 21 cycles for address match and single-step interrupts.

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11.3.7 Saving Registers

In the interrupt sequence, the FLG register and PC are saved on the stack. After an extended 16 bits, 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order bits in the FLG register, are saved on the stack, the 16 low-order bits in the PC are saved. Figure 11.5 shows the Stack State Before and After Acknowledgement of Interrupt Request. The other necessary registers should be saved by a progr am at the beginning of the interrupt routine. The PUSHM instruction can save several registers in the register bank being currently used (1) with a single instruction. Note: 1. Selectable from registers R0, R1, R2, R3, A0, A1, SB, and FB. Figure 11.5 Stack State Before and After Acknowledgement of Interrupt Request Stack [SP] SP value before interrupt request acknowledgement (1) Previous stack contents LSBMSB Address Previous stack contents m−4 m−3 m−2 m−1 m m+1 Stack state before interrupt request acknowledgement [SP] New SP value (1) Previous stack contents LSBMSB Previous stack contents m m+1 Stack state after interrupt request acknowledgement PCL PCM FLGL FLGH PCH m−4 m−3 m−2 m−1 StackAddress PCL : 8 low-order bits of PC PCM : 8 middle-order bits of PC PCH : 4 high-order bits of PC FLGL : 8 low-order bits of FLG FLGH : 4 high-order bits of FLG Note: 1.When an INT instruction for software numbers 32 to 63 has been executed, this SP is indicated by the U flag. Otherwise it is ISP.

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11.3.8 Returning from Interrupt Routine

When the REIT instruction is executed at the end of an interrupt rout ine, the FLG register and PC, which have been saved on the stack, are automatical ly restored. The program, that was running before the interrupt request was acknowledged, starts running again. Registers saved by a program in an interrupt routine s hould be saved using the POPM instruction or a similar instruction before executing the REIT instruction.

11.3.9 Interrupt Priority

If two or more interrupt requests are generated while a single instruction is being executed, the interrupt with the higher priority is acknowledged. Set bits ILVL2 to ILVL0 to select any priority level fo r maskable interrupt s (peripheral function). However, if two or more maskable interrupts have the same priority level, their interrupt priority is resolved by hardware, with the higher priority interrupts acknowledged. The priority of watchdog timer and other special interrupts is set by hardware. Figure 11.7 shows the Hardware Interrupt Priority. Software interrupts are not affected by the interrupt priority. If an instruction is executed, the MCU executes the interrupt routine. Figure 11.7 Hardware Interrupt Priority Address break Watchdog timer Oscillation stop detection Voltage monitor 1/comparator A1 Voltage monitor 2/comparator A2 Peripheral function Single step Address match High Low Reset

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11.3.10 Interrupt Priority Level Selection Circuit

The interrupt priority level selection circuit is used to select the highest priority interrupt. Figure 11.8 shows the Interrupt Priority Level Selection Circuit. Figure 11.8 Interrupt Priority Level Selection Circuit Timer RB Timer RA INT1 Timer RE UART0 transmit SSU / I2C bus (1) Flash memory ready Lowest Highest Peripheral function interrupt priority (if the priority levels are same) Interrupt request level selection output signal Interrupt request acknowledgementI flag Address match Watchdog timer Oscillation stop detection Voltage monitor 1/comparator A1 Note: 1. Selectable by the IICSEL bit in the SSUIICSR register. A/D conversion UART2 receive/ACK2 Timer RC UART0 receive UART2 transmit/NACK2 Voltage monitor 1/comparator A1 Voltage monitor 2/comparator A2 Priority level of interrupts Level 0 (initial value) Voltage monitor 2/comparator A2 UART2 bus collision detection INT3 INT0 Key input IPL

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11.4 INT Interrupt

11.4.1 INTi Interrupt (i = 0, 1, 3)

The INTi interrupt is generated by an INTi input. To use the INTi interrupt, set the INTiEN bit in the INTEN register is to 1 (enabled). The edge polarity is selected using the INTiPL bit in the INTEN register and the POL bit in the INTiIC register. The input pins used as the INT1 input can be selected. Also, inputs can be passed through a digital filter with three different sampling clocks. The INT0 pin is shared with the pulse output forced cutoff input of timer RC, and the external trigger input of timer RB. Table 11.6 lists the Pin Configuration of INT Interrupt.

11.4.2 INT Interrupt Input Pi n Select Register (INTSR)

The INTSR register selects which pin is assigned to the INT1 input. To use INT1, set this register. Set the INTSR register before setting the INT1 associated registers. Also, do not change the setting values in this register during INT1 operation. Table 11.6 Pin Configuration of INT Interrupt Pin Name Assigned Pin I/O Function INT0 P4_5 Input INT0 interrupt input, timer RB external trigger input, timer RC pulse output forced cutoff input INT1 P1_5 or P1_7 Input INT1 interrupt input INT3 P3_3 Input INT3 interrupt input Address 018Eh B i t b 7b 6 b 5 b 4b 3b 2b 1 b 0 A f t e r R e s e t 00 0 0000 0 Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b1 INT1SEL0 INT1 pin select bit 0: P1_7 assigned 1: P1_5 assigned R/W b2 — Reserved bits Set to 0. R/W b3 — b4 — b5 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b6 — Reserved bits Set to 0. R/W b7 —

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11.4.3 External Input Enab le Register 0 (INTEN)

Notes: 1. To set the INTiPL bit (i = 0, 1, 3) to 1 (both edges), set the POL bit in the INTiIC register to 0 (falling edge selected). 2. The IR bit in the INTiIC register may be set to 1 (inter rupt requested) if the INTiPL bit is rewritten. Refer to 11.8.4 Changing Interrupt Sources.

11.4.4 INT Input Filter Se lect Register 0 (INTF)

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol INT3PL INT3EN — — INT1PL INT1EN INT0PL INT0EN A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 INT0EN INT0 input enable bit 0: Disabled 1: Enabled R/W b1 INT0PL INT0 input polarity select bit (1, 2) 0: One edge 1: Both edges R/W b2 INT1EN INT1 input enable bit 0: Disabled 1: Enabled R/W b3 INT1PL INT1 input polarity select bit (1, 2) 0: One edge 1: Both edges R/W b4 — Reserved bits Set to 0. R/W b5 — b6 INT3EN INT3 input enable bit 0: Disabled 1: Enabled R/W b7 INT3PL INT3 input polarity select bit (1, 2) 0: One edge 1: Both edges R/W Address 01FCh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol INT3F1 INT3F0 — — INT1F1 INT1F0 INT0F1 INT0F0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 INT0F0 INT0 input filter select bit b1 b0 0 0: No filter 0 1: Filter with f1 sampling 1 0: Filter with f8 sampling 1 1: Filter with f32 sampling R/W b1 INT0F1 R/W b2 INT1F0 INT1 input filter select bit b3 b2 0 0: No filter 0 1: Filter with f1 sampling 1 0: Filter with f8 sampling 1 1: Filter with f32 sampling R/W b3 INT1F1 R/W b4 — Reserved bits Set to 0. R/W b5 — b6 INT3F0 INT3 input filter select bit b7 b6 0 0: No filter 0 1: Filter with f1 sampling 1 0: Filter with f8 sampling 1 1: Filter with f32 sampling R/W b7 INT3F1 R/W

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11.4.5 INTi Input Filter (i = 0, 1, 3)

The INTi input contains a digital filter. The sampling clock is selected using bits INTiF1 and INTiF0 in the INTF register. The INTi level is sampled every sampling clock cycl e and if the sampled input level matches three times, the IR bit in the INTiIC register is set to 1 (interrupt requested). Figure 11.9 shows the INTi Input Filter Configuration. Figure 11.10 shows an Operating Example of INTi Input Filter. Figure 11.9 INTi Input Filter Configuration Figure 11.10 Operating Example of INTi Input Filter INTiF0, INTiF1: Bits in INTF register INTiEN, INTiPL: Bits in INTEN register i = 0, 1, 3 = 01b INTi Port direction register (1) Sampling clock Digital filter (input level matches 3 times) INTi interrupt = 10b = 11bf32 INTiF1 to INTiF0 INTiEN Other than INTiF1 to INTiF0 = 00b = 00b INTiPL = 0 INTiPL = 1 Note: 1. INT0: Port P4_5 direction register INT1: Port P1_5 direction register when P1_5 pin used Port P1_7 direction register when P1_7 pin used INT3: Port P3_3 direction register when P3_3 pin used Both edges detection circuit INTi input Sampling timing IR bit in INTiIC register Set to 0 by a program. Note: This is an operating example when bits INTiF1 to INTiF0 in the INTiF register are set to 01b, 10b, or 11b (digital filter en abled). i = 0, 1, 3

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11.5 Key Input Interrupt

A key input interrupt request is generated by one of the input edges of pins K10 to K13. The key input interrupt can be used as a key-on wake-up function to exit wait or stop mode. The KIiEN (i = 0 to 3) bit in the KIEN register is be used to select whether or not the pins are used as the KIi input. The KIiPL bit in the KIEN register is also be used to select the input polarity. When inputting “L” to the KIi pin, which sets the KIiPL bit to 0 (falling edge), the input to the other pins K10 to K13 is not detected as interrupts. When inputting “H” to the KIi pin, which sets the KIiPL bit to 1 (rising edge), the input to the other pins K10 to K13 is not also detected as interrupts. Figure 11.11 shows a Block Diagram of Key Input Interrup t. Table 11.7 lists the Pin Configuration of Key Input Interrupt. Figure 11.11 Block Diagram of Key Input Interrupt Table 11.7 Pin Configuration of Key Input Interrupt Pin Name I/O Function KI0 Input KI0 interrupt input KI1 Input KI1 interrupt input KI2 Input KI2 interrupt input KI3 Input KI3 interrupt input KI3 Pull-up transistor KI2 Pull-up transistor KI3PL = 0 KI3PL = 1 PD1_3 bit KI3EN bit PU02 bit in PUR0 register PD1_3 bit in PD1 register KUPIC register Interrupt control circuit Key input interrupt request KI2PL = 0 KI2PL = 1 PD1_2 bit KI2EN bit KI1 Pull-up transistor KI1PL = 0 KI1PL = 1 PD1_1 bit KI1EN bit KI0 Pull-up transistor KI0PL = 0 KI0PL = 1 PD1_0 bit KI0EN bit KI0EN, KI1EN, KI2EN, KI3EN, KI0PL, KI1PL, KI2PL, KI3PL: Bits in KIEN register PD1_0, PD1_1, PD1_2, PD1_3: Bits in PD1 register

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11.5.1 Key Input Enable Register 0 (KIEN)

The IR bit in the KUPIC register may be set to 1 (interrupt requested) when the KIEN register is rewritten. Refer to 11.8.4 Changing Interrupt Sources. Address 01FEh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol KI3PL KI3EN KI2PL KI2EN KI1PL KI1EN KI0PL KI0EN A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 KI0EN KI0 input enable bit 0: Disabled 1: Enabled R/W b1 KI0PL KI0 input polarity select bit 0: Falling edge 1: Rising edge R/W b2 KI1EN KI1 input enable bit 0: Disabled 1: Enabled R/W b3 KI1PL KI1 input polarity select bit 0: Falling edge 1: Rising edge R/W b4 KI2EN KI2 input enable bit 0: Disabled 1: Enabled R/W b5 KI2PL KI2 input polarity select bit 0: Falling edge 1: Rising edge R/W b6 KI3EN KI3 input enable bit 0: Disabled 1: Enabled R/W b7 KI3PL KI3 input polarity select bit 0: Falling edge 1: Rising edge R/W

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11.6 Address Match Interrupt

An address match interrupt request is generated immediat ely before execution of the instruction at the address indicated by the RMADi register (i = 0 or 1). This interr upt is used as a break function by the debugger. When the on-chip debugger is used, do not set an address match interrupt (registers AIER0, AIER1, RMAD0, and RMAD1, and fixed vector tables) in the user system. Set the starting address of an y instruction in the RMADi register (i = 0 or 1). The AIERi bit in the AIERi register can be used to select enable or disable the interrupt. Th e address match interrupt is not affected by the I flag and IPL. The PC value (Refer to 11.3.7 Saving Registers ) which is saved on the stack wh en an address match interrupt request is acknowledged varies depending on the instruc tion at the address indicated by the RMADi register. (The appropriate return address is not save d on the stack.) When returning from the address match interrupt, follow one of the following means:

• Rewrite the contents of the stack and use the REIT instruction to return.
• Use an instruction such as POP to restore the stack to its previous st ate before the interrupt request was acknowledged. Then use a jump instruction to return. Table 11.8 lists the PC Value Saved on Stack When Address Match Interrupt Request is Acknowledged and Table 11.9 lists the Correspondence Between Address Match Interrupt Sources and Associated Registers. Notes: 1. Refer to the 11.3.7 Saving Registers. 2. Operation code: Refer to the R8C/Tiny Series Software Manual (REJ09B0001). Chapter 4. Instruction Code/Number of Cycles contains diagrams showing operation code below each syntax. Operation code is shown in the bold frame in the diagrams. Table 11.8 PC Value Saved on Stack When Address Match Interrupt Request is Acknowledged Address Indicated by RMADi Register (i = 0 or 1) PC Value Saved (1)
• Instruction with 2-byte operation code (2)
• Instruction with 1-byte operation code (2) ADD.B:S #IMM8,dest SUB.B:S #I MM8,dest AND.B:S #IMM8,dest OR.B:S #IMM8,dest MOV.B: S #IMM8,dest STZ #IMM8,dest STNZ #IMM8,dest S TZX #IMM81,#IMM82,dest CMP .B:S #IMM8,dest PUSHM src POPM dest JMPS #IMM8 JSRS #IMM8 MOV.B:S #IMM,dest (however, dest = A0 or A1) Address indicated by RMADi register + 2
• Instructions other than above Address indicated by RMADi register + 1 Table 11.9 Correspondence Between Address Match Interrupt Sources and Associated Registers Address Match Interrupt Source Address Match Inte rrupt Enable Bit Address Match Interrupt Register Address match interrupt 0 AIER0 RMAD0 Address match interrupt 1 AIER1 RMAD1

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11.6.1 Address Match Interrupt Enable Register i (AIERi) (i = 0 or 1)

11.6.2 Address Match Interrupt Re gister i (RMADi) (i = 0 or 1)

Address 01C3h (AIER0), 01C7h (AIER1) B i t b 7b 6b 5b 4b 3b 2b 1b 0 S y m b o l ——————— A I E R 0 A I E R 0 r e g i s t e r A f t e r R e s e t 00000000 S y m b o l ——————— A I E R 1 A I E R 1 r e g i s t e r A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 AIERi Address match interrupt i enable bit 0: Disabled 1: Enabled R/W b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b2 — b3 — b4 — b5 — b6 — b7 — Address 01C2h to 01C0h (RMAD0), 01C6h to 01C4h (RMAD1) B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t XXXXXXXX Bit b15 b14 b13 b12 b11 b10 b9 b8 A f t e r R e s e t XXXXXXXX Bit b23 b22 b21 b20 b19 b18 b17 b16 A f t e r R e s e t 0000XXXX Bit Symbol Function Setting Range R/W b19 to b0 — Address setting register for address match interrupt 00000h to FFFFFh R/W b20 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b21 — b22 — b23 —

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11.7 Timer RC Interrupt, Sy nchronous Serial Communicat ion Unit Interrupt, I 2C

bus Interface Interrupt, and Flash Memory Interrupt (Interrupts with Multiple Interrupt Request Sources) The timer RC interrupt, synchronous serial communication unit interrupt, I 2C bus interface interrupt, and flash memory interrupt each have multiple interrupt request so urces. An interrupt request is generated by the logical OR of several interrupt request sources and is reflected in th e IR bit in the correspondin g interrupt control register. Therefore, each of these peripheral functions has its own interrupt request source status register (status register) and interrupt request source enable regist er (enable register) to control the ge neration of interrupt requests (change of the IR bit in the interrupt control register). Table 11.10 lists the Registers Associated with Timer RC Interrupt, Synchronous Serial Communication Unit Interrupt, I2C bus Interface Interrupt, and Flash Memory Interrupt. Table 11.10 Registers Associated with Timer RC Interrupt, Synchronous Serial Communication Unit Interrupt, I2C bus Interface Interrupt, and Flash Memory Interrupt Peripheral Function Name Status Register of Interrupt Request Source Enable Register of Interrupt Request Source Interrupt Control Register Timer RC TRCSR TRCIER TRCIC Synchronous serial communication unit SSSR SSER SSUIC I2C bus interface ICSR ICIER IICIC Flash memory RDYSTI RDYSTIE FMRDYIC BSYAEI BSYAEIE CMDERIE

R8C/32A Group 11. Interrupts REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 144 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. As with other maskable interrupts, the timer RC interrupt, synchronous serial communication unit interrupt, I 2C bus interface interrupt, and flash memory interrupt are c ontrolled by the combination of the I flag, IR bit, bits ILVL0 to ILVL2, and IPL. However, since each interrupt source is generated by a combination of multiple interrupt request sources, the following differences from other maskable interrupts apply:

• When bits in the enable register are set to 1 and the corresponding bits in the status register are set to 1 (interrupt enabled), the IR bit in the interrupt control register is set to 1 (interrupt requested).
• When either bits in the status register or the corresponding bits in the enable register, or both are set to 0, the IR bit is set to 0 (no interrupt requested). That is, even if the interrupt is not acknowledged after th e IR bit is set to 1, the interrupt request will not be retained. Also, the IR bit is not set to 0 even if 0 is written to this bit.
• Individual bits in the status register are not automatically set to 0 even if the interrupt is acknowledged. The IR bit is also not automatically set to 0 when the interrupt is acknowledged. Set individual bits in the status register to 0 in the interrupt routine. Refer to the status register figure for how to set individual bits in the status register to 0.
• When multiple bits in the enable register are set to 1 and other request sources are generated after the IR bit is set to 1, the IR bit remains 1.
• When multiple bits in the enable regi ster are set to 1, use the status regi ster to determine which request source causes an interrupt. Refer to chapters of the individual peripheral functions ( 19. Timer RC, 24. Synchronous Serial Communication Unit (SSU), 25. I2C bus Interface, and 30. Flash Memory) for the status register and enable register. For the interrupt control register, refer to 11.3 Interrupt Control.

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11.8 Notes on Interrupts

11.8.1 Reading Address 00000h

Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At this time, the IR bit for the acknowledged interrupt is set to 0. If address 00000h is read by a program, the IR bit for the interrupt which has the highest priority among the enabled interrupts is set to 0. This may cause the interrupt to be cancel ed, or an unexpected interrupt to be generated.

11.8.2 SP Setting

Set a value in the SP before an interrupt is acknowledged. The SP is set to 0000h after a reset. If an interrupt is acknowledged before setting a value in the SP, the program may run out of control.

11.8.3 External Interrupt and Key Input Interrupt

Either the “L” level width or “H” level width shown in the Electrical Characteristic s is required for the signal input to pins INT0, INT1, INT3 and pins KI0 to KI3, regardless of the CPU clock. For details, refer to Table 32.22 (VCC = 5V), Table 32.28 (VCC = 3V), Table 32.34 (VCC = 2.2V) External Interrupt INTi (i = 0, 1, 3) Input, Key Input Interrupt KIi (i = 0 to 3).

R8C/32A Group 11. Interrupts REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 146 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

11.8.4 Changing Interrupt Sources

The IR bit in the interrupt control register may be se t to 1 (interrupt requested) when the interrupt source changes. To use an interrupt, set the IR bit to 0 (no interrupt requested) after changing interrupt sources. Changing interrupt sources as referred to here includes all factors that change the source, polarity, or timing of the interrupt assigned to a software interrupt number. Therefore, if a m ode change of a peripheral function involves the source, polarity, or timing of an interrupt, set the IR bit to 0 (no interrupt requested) after making these changes. Refer to the descriptions of the individual peripheral functions for related interrupts. Figure 11.12 shows a Procedure Example for Changing Interrupt Sources. Figure 11.12 Procedure Example for Changing Interrupt Sources Notes: 1. The above settings must be executed individually. Do not execute two or more settings simultaneously (using one instruction). 2. To prevent interrupt requests from being generated disable the peripheral function before changing the interrupt source. In this case, use the I flag if all maskable interrupts can be disabled. If all maskable interrupts cannot be disabled, use bits ILVL0 to ILVL2 for the interrupt whose source is to be changed. 3. Refer to 11.8.5 Rewriting Interrupt Control Register for the instructions to use and related notes. Interrupt source change Disable interrupts (2, 3) Set the IR bit to 0 (no interrupt request) using the MOV instruction (3) Change interrupt sources (including mode of peripheral function) Enable interrupts (2, 3) Change completed IR bit: The interrupt control register bit for the interrupt whose source is to be changed

R8C/32A Group 11. Interrupts REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 147 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

11.8.5 Rewriting Interr upt Control Register

(a) The contents of the interrupt control register can be rewritten only while no interrupt requests corresponding to that regist er are generated. If an interrupt reques t may be generated, disable the interrupt before rewriting the contents of the interrupt control register. (b) When rewriting the contents of the interrupt control register after disabling th e interrupt, be careful to choose appropriate instructions. Changing any bit other than the IR bit If an interrupt request corresponding to the register is generated while executing the instruction, the IR bit may not be set to 1 (interrupt requested), and the interrupt may be ignored. If this causes a problem, use one of the following instructions to rewrite the contents of the register: AND, OR, BCLR, and BSET. Changing the IR bit Depending on the instruction used, the IR bit may not be set to 0 (no interrupt requested). Use the MOV instruction to set the IR bit to 0. (c) When using the I flag to disable an interrupt, set the I flag as shown in the sample programs below. Refer to (b) regarding rewriting the contents of interrupt control registers using the sample programs. Examples 1 to 3 shows how to prevent the I flag from being set to 1 (interrupts enabled) before the contents of the interrupt control register are rewritten for the effects of the internal bus and the instruction queue buffer. Example 1: Use the NOP instructions to pause program until the interrupt control register is rewritten INT_SWITCH1: FCLR I ; Disable interrupts AND.B #00H,0056H ; Set the TRAIC register to 00h NOP ; NOP FSET I ; Enable interrupts Example 2: Use a dummy read to delay the FSET instruction INT_SWITCH2: FCLR I ; Disable interrupts AND.B #00H,0056H ; Set the TRAIC register to 00h MOV .W MEM,R0 ; Dummy read FSET I ; Enable interrupts Example 3: Use the POPC inst ruction to change the I flag INT_SWITCH3: PUSHC FLG FCLR I ; Disable interrupts AND.B #00H,0056H ; Set the TRAIC register to 00h POPC FLG ; Enable interrupts

R8C/32A Group 12. ID Code Areas REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 148 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 12. ID Code Areas The ID code areas are used to implement a function that prevents the flash memory from being rewritten in standard serial I/O mode. This function prevents the flash memory from being read, rewritten, or erased.

12.1 Overview

The ID code areas are assigned to 0FFDFh, 0FFE3h, 0FFEBh, 0FFEFh, 0FFF3h, 0FFF7h, and 0FFFBh of the respective vector highest-order addresses of the fixed vector table. Figure 12.1 shows the ID Code Areas. Figure 12.1 ID Code Areas 4 bytes Address Watchdog timer, oscillation stop detection, voltage monitor 1, voltage monitor 2 (Reserved) Undefined instruction vector Overflow vector BRK instruction vector Address match vector Single step vector Address break vector Reset vector ID code areas ID1 ID2 ID3 ID4 ID5 ID6 ID7 OFS 0FFDFh to 0FFDCh 0FFE3h to 0FFE0h 0FFE7h to 0FFE4h 0FFEBh to 0FFE8h 0FFEFh to 0FFECh 0FFF3h to 0FFF0h 0FFF7h to 0FFF4h 0FFFBh to 0FFF8h 0FFFFh to 0FFFCh

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12.2 Functions

The ID code areas are used in standard serial I/O mode. Unless 3 bytes (addresses 0FFFCh to 0FFFEh) of the reset vector are set to FFFFFFh, the ID codes stored in the ID code areas and the ID codes sent from the serial programmer or the on-chip debugging emulator are checked to see if they match. If the ID codes match, the commands sent from the seri al programmer or the on-chip debugging emulator are ackno wledged. If the ID codes do not match, the commands are not acknowledged. To use the serial programmer or the on-chip debugging emulator, first write predetermined ID codes to the ID code areas. If 3 bytes (addresses 0FFFCh to 0FFFEh) of the reset vector are set to FFFFFFh, the ID codes are not checked and all commands are accepted. As the ID code areas are allocated in the flash memory ( not in the SFRs), they cannot be rewritten by executing an instruction. Write appropriate values when creating a program. The character sequence of the ASCII codes “ALeRASE” is the reserved word used for the forced erase function. The character sequence of the ASCII codes “Protect” is th e reserved word used for th e standard serial I/O mode disabled function. Table 12.1 shows the ID Code Reserved Word. The reserved word is a set of reserved characters when all the addresses and data in the ID code storage addresses sequentially match Table 12.1. When the forced erase function or standard serial I/O mode disabled fu nction is not used, use anot her character sequence of the ASCII codes. Table 12.1 ID Code Reserved Word Note: 1. Reserve word:A set of characters when all the addresses and data in the ID code storage addresses sequentially match Table 12.1. ID Code Storage Address lD Code Reserved Word (ASCII) (1) ALeRASE Protect 0FFDFh ID1 41h (upper-case “A”) 50h (upper-case “P”) 0FFE3h ID2 4Ch (upper-case “L”) 72h (lower-case “r”) 0FFEBh ID3 65h (lower-case “e”) 6Fh (lower-case “o”) 0FFEFh ID4 52h (upper-case “R”) 74h (lower-case “t”) 0FFF3h ID5 41h (upper-case “A”) 65h (lower-case “e”) 0FFF7h ID6 53h (upper-case “S”) 63h (lower-case “c”) 0FFFBh ID7 45h (upper-case “E”) 74h (lower-case “t”)

R8C/32A Group 12. ID Code Areas REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 150 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

12.3 Forced Erase Function

This function is used in standard serial I/O mode. When the ID codes sent from the serial programmer or the on- chip debugging emulator are “ALeRASE” in ASCII code, the content of the user ROM area will be erased at once. However, if the contents of the ID code addre sses are set to other than “ALeRASE” (other than Table 12.1 ID Code Reserved Word) when the ROMCR bit in the OFS register is set to 1 and the ROMCP1 bit is set to 0 (ROM code protect enabled), forced erasure is not executed and the ID codes are checked with the ID code check function. Table 12.2 lists the Conditions and Operations of Forced Erase Function. Also, when the contents of the ID code addresses are set to “ALeRASE” in ASCII code, if the ID codes sent from the serial programmer or the on-chip debugging emulator are “ALeRASE”, the content of the user ROM area will be erased. If the ID codes sent from the serial progra mmer are other than “ALeRASE”, the ID codes do not match and no command is acknowledged, thus the user ROM area remains protected. Note: 1. For “Protect”, refer to 12.4 Standard Serial II/O Mode Disabled Function.

12.4 Standard Serial II/O Mode Disabled Function

This function is used in standard serial I/O mode. When the I/D codes in the ID code storage addresses are set to the reserved character sequence of the ASCII codes “Protect” (refer to Table 12.1 ID Code Reserved Word ), communication with the serial programmer or the on-chip debugging emulator is not performed. This does not allow the flash memory to be read, rewritten, or eras ed using the serial programmer or the on-chip debugging emulator. Also, if the ID codes are also set to the reserved ch aracter sequence of the ASCI I codes “Protect” when the ROMCR bit in the OFS register is set to 1 and the ROMCP1 bit is set to 0 (ROM code protect enabled), ROM code protection cannot be disabled using the serial programmer or the on-chip debugging emulator. This prevents the flash memory from being read, rewritten, or erased using the serial programmer, the on-chip debugging emulator, or parallel programmer. Table 12.2 Conditions and Operations of Forced Erase Function Condition Operation ID code from serial programmer or the on-chip debugging emulator ID code in ID code storage address Bits ROMCP1 and ROMCR in OFS register ALeRASE ALeRASE – All erasure of user ROM area (forced erase function)Other than ALeRASE (1) Other than 01b (ROM code protect disabled) 01b (ROM code protect enabled) ID code check (ID code check function) Other than ALeRASE ALeR ASE – ID code check (ID code check function. No ID code match.) Other than ALeRASE (1) – ID code check (ID code check function)

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12.5 Notes on ID Code Areas

12.5.1 Setting Example of ID Code Areas

As the ID code areas are allocated in the flash memory (not in the SFRs), they cannot be rewritten by executing an instruction. Write appropriate values when creating a program. The following shows a setting example.

• To set 55h in all of the ID code areas .org 00FFDCH .lword dummy | (55000000h) ; UND .lword dummy | (55000000h) ; INTO .lword dummy ; BREAK .lword dummy | (55000000h) ; ADDRESS MATCH .lword dummy | (55000000h) ; SET SINGLE STEP .lword dummy | (55000000h) ; WDT .lword dummy | (55000000h) ; ADDRESS BREAK .lword dummy | (55000000h) ; RESERVE (Programming formats vary depending on the compiler. Check the compiler manual.)

R8C/32A Group 13. Option Function Select Area REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 152 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 13. Option Function Select Area

13.1 Overview

The option function select area is used to select the MCU state after a reset, the function to prevent rewriting in parallel I/O mode, or the watchdog timer operation. The re set vector highest-order-address, 0FFFFh and 0FFDBh, are assigned as the option function select area. Figure 13.1 shows the Option Function Select Area. Figure 13.1 Option Function Select Area Address 0FFDBh to 0FFD8h OFS2 Option function select area 4 bytes 0FFFFh to 0FFFCh OFS Reset vector Reserved area

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13.2 Registers

Registers OFS and OFS2 are used to select the MCU state after a reset, the function to prevent rewriting in parallel I/O mode, or the watchdog timer operation.

13.2.1 Option Function Se lect Register (OFS)

Notes: 1. If the block including the OFS register is er ased, the OFS register value is set to FFh. 2. The same level of the voltage detection 0 level selected by bits VDSEL0 and VDESL1 is set in both functions of voltage monitor 0 reset and power-on reset. 3. To use power-on reset, set the LVDAS bit to 0 (voltage monitor 0 reset enabled after reset). The OFS register is allocated in the flash memory. Write to this register with a program. After writing, do not write additions to this register. LVDAS Bit (Voltage Detection 0 Circuit Start Bit) The Vdet0 voltage to be monitored by the voltage detection 0 circuit is selected by bits VDSEL0 and VDSEL1. Address 0FFFFh B i t b 7 b 6b 5b 4b 3b 2b 1b 0 Symbol CSPROINI LVDAS VDSEL1 VDSEL0 ROMCP1 ROMCR — WDTON W h e n s h i p p i n g 1 1111111 ( N o t e 1 ) Bit Symbol Bit Name Function R/W b0 WDTON Watchdog timer start select bit 0: Watchdog timer automatically starts after reset. 1: Watchdog timer is stopped after reset. R/W b1 — Reserved bit Set to 1. R/W b2 ROMCR ROM code protect disable bit 0: ROM code protect disabled 1: ROMCP1 bit enabled R/W b3 ROMCP1 ROM code protect bi t 0: ROM code protect enabled 1: ROM code protect disabled R/W b4 VDSEL0 Voltage detection 0 level select bit (2) b5 b4 0 0: 3.80 V selected (Vdet0_3) 0 1: 2.85 V selected (Vdet0_2) 1 0: 2.35 V selected (Vdet0_1) 1 1: 1.90 V selected (Vdet0_0) R/W b5 VDSEL1 R/W b6 LVDAS Voltage detection 0 circuit start bit (3) 0: Voltage monitor 0 reset enabled after reset 1: Voltage monitor 0 reset disabled after reset R/W b7 CSPROINI Count source protection mode after reset select bit 0: Count source protect mode enabled after reset 1: Count source protect mode disabled after reset R/W

R8C/32A Group 13. Option Function Select Area REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 154 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

13.2.2 Option Function Sel ect Register 2 (OFS2)

Note: 1. If the block including the OFS2 register is erased, the OFS2 register value is set to FFh. The OFS2 register is located on the flash memory. Write to this register with a program. After writing, do not write additions to this register. Bits WDTRCS0 and WDTRCS1 (Watchdog Timer Refresh Acknowledgement Period Set Bit) Assuming that the period from when the watchdog timer starts counting until it underflows is 100%, the refresh acknowledgement period for the watchdog timer can be selected. For details, refer to 14.3.1.1 Refresh Acknowledgment Period. Address 0FFDBh B i t b 7 b 6 b 5 b 4 b 3b 2b 1b 0 Symbol — — — — WDTRCS1 WDTRCS0 WDTUFS1 WDTUFS0 When shipping 1 1 1 1 1 1 1 1 (Note 1) Bit Symbol Bit Name Function R/W b0 WDTUFS0 Watchdog timer underflow period set bit b1 b0 0 0: 03FFh 0 1: 0FFFh 1 0: 1FFFh 1 1: 3FFFh R/W b1 WDTUFS1 R/W b2 WDTRCS0 Watchdog timer refresh acknowledgement period set bit b3 b2 0 0: 25% 0 1: 50% 1 0: 75% 1 1: 100% R/W b3 WDTRCS1 R/W b4 — Reserved bits Set to 1. R/W b5 — b6 — b7 —

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13.3 Notes on Option Function Select Area

13.3.1 Setting Example of Op tion Function Select Area

As the option function select area is allocated in the flash memory (not in the SFRs), they cannot be rewritten by executing an instruction. Write appropriate values when creating a program. The following shows a setting example.

• To set FFh in the OFS register .org 00FFFCH .lword reset | (0FF000000h) ; RESET (Programming formats vary depending on the compiler. Check the compiler manual.)

R8C/32A Group 14. Watchdog Timer REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 156 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 14. Watchdog Timer The watchdog timer is a function that detects when a pr ogram is out of control. Use of the watchdog timer is recommended to improve the reliability of the system.

14.1 Overview

The watchdog timer contains a 15-bit counter and allows selection of count source protection mode enable or disable. Table 14.1 lists the Watchdog Timer Specifications. Refer to 5.5 Watchdog Timer Reset for details of the watchdog timer reset. Figure 14.1 shows a Watchdog Timer Block Diagram. Table 14.1 Watchdog Timer Specifications Item Count Source Protection Mode Disabled Count Source Protection Mode Enabled Count source CPU clock Low-sp eed on-chip oscillator clock for the watchdog timer Count operation Decrement Count start condition Either of the following can be selected:

• After a reset, count starts automatically.
• Count starts by writing to the WDTS register. Count stop condition Stop mode, wait mode None Watchdog timer initialization conditions
• Reset
• Write 00h and then FFh to the WDTR register (with acknowledgement period setting).
• Underflow Operations at underflow Watchdog timer interrupt or watchdog timer reset Watchdog timer reset Selectable functions • Divisio n ratio of the prescaler Selected by the WDTC7 bit in the WDTC register or the CM07 bit in the CM0 register.
• Count source protection mode Whether count source protection mode is enabled or disabled after a reset can be selected by the CSPROINI bit in the OFS register (flash memory). If count source protection mode is disabled after a reset, it can be enabled or disabled by the CSPRO bit in the CSPR register (program).
• Start or stop of the watchdog timer after a reset Selected by the WDTON bit in the OFS register (flash memory).
• Initial value of the watchdog timer Selectable by bits WDTUFS0 and WDTUFS1 in the OFS2 register.
• Refresh acknowledgement period for the watchdog timer Selectable by bits WDTRCS0 and WDTRCS1 in the OFS2 register.

R8C/32A Group 14. Watchdog Timer REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 157 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 14.1 Watchdog Timer Block Diagram 1/2 Watchdog timer CPU clock Bits WDTRCS0 and WDTRCS1 CM07 = 1 (Note 1) PM12 = 1 Watchdog timer reset PM12 = 0 Watchdog timer interrupt request Prescaler CSPRO = 0 CSPRO = 1 CSPRO: Bit in CSPR register WDTC7: Bit in WDTC register PM12: Bit in PM1 register CM07: Bit in CM0 register WDTUFS0, WDTUFS1, WDTRCS0, WDTRCS1: Bits in OFS2 register Note: 1. A value set by bits WDTUFS0 and WDTUFS1 is set in the watchdog timer (value when shipping: 3FFFh). Internal reset signal (Low active) CM07 = 0, WDTC7 = 0 CM07 = 0, WDTC7 = 1 Low-speed on-chip oscillator for watchdog timer Oscillation starts when CSPRO = 1 Refresh period control circuitWrite to WDTR register

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14.2 Registers

14.2.1 Processor Mode Register 1 (PM1)

Note: 1. The PM12 bit is set to 1 when 1 is written by a pr ogram (and remains unchanged even if 0 is written to it). This bit is automatically set to 1 when the CSPRO bit in the CSPR register is set to 1 (count source protection mode enabled). Set the PRC1 bit in the PRCR register to 1 (write enabled) before rewriting the PM1 register.

14.2.2 Watchdog Timer Reset Register (WDTR)

14.2.3 Watchdog Timer Start Register (WDTS)

B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 — Reserved bits Set to 0. R/W b1 — b2 PM12 WDT interrupt/reset switch bit 0: Watchdog timer interrupt 1: Watchdog timer reset (1) R/W b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b4 — b5 — b6 — b7 — Reserved bit Set to 0. R/W Address 000Dh B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t XXXXXXXX Bit Function R/W b7 to b0 Writing 00h and then FFh to this register initializes the watchdog timer. The initial value of the watchdog timer is specified by bits WDTUFS0 and WDTUF1 in the OFS2 register. W Address 000Eh B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t XXXXXXXX Bit Function R/W b7 to b0 A write instruction to this re gister starts the watchdog timer. W

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14.2.4 Watchdog Timer C ontrol Register (WDTC)

14.2.5 Count Source Protecti on Mode Register (CSPR)

Notes: 1. When 0 is written to the CSPROINI bit in t he OFS register, the value after reset is 10000000b. 2. To set the CSPRO bit to 1, write 0 and then 1 to it. This bit cannot be set to 0 by a program. Address 000Fh B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00111111 Bit Symbol Bit Name Function R/W b0 — When read, b6 to b10 of the watchdog timer can be read. R b1 — b2 — b3 — b4 — b5 — When read, b11 of the watchdog timer can be read. R b6 — Reserved bit When read , the content is 0. R b7 WDTC7 Prescaler select bit 0: Divided-by-16 1: Divided-by-128 R/W Address 001Ch B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00000000 ( N o t e 1 ) Bit Symbol Bit Name Function R/W b0 — Reserved bits Set to 0. R/W b1 — b2 — b3 — b4 — b5 — b6 — b7 CSPRO Count source protection mode select bit (2) 0: Count source protection mode disabled 1: Count source protection mode enabled R/W

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14.2.6 Option Function Se lect Register (OFS)

Notes: 1. If the block including the OFS register is er ased, the OFS register value is set to FFh. 2. The same level of the voltage detection 0 level selected by bits VDSEL0 and VDESL1 is set in both functions of voltage monitor 0 reset and power-on reset. 3. To use power-on reset, set the LVDAS bit to 0 (voltage monitor 0 reset enabled after reset). The OFS register is allocated in the flash memory. Write to this register with a program. After writing, do not write additions to this register. LVDAS Bit (Voltage Detection 0 Circuit Start Bit) The Vdet0 voltage to be monitored by the voltage detection 0 circuit is selected by bits VDSEL0 and VDSEL1. Address 0FFFFh B i t b 7 b 6b 5b 4b 3b 2b 1b 0 Symbol CSPROINI LVDAS VDSEL1 VDSEL0 ROMCP1 ROMCR — WDTON W h e n s h i p p i n g 1 1111111 ( N o t e 1 ) Bit Symbol Bit Name Function R/W b0 WDTON Watchdog timer start select bit 0: Watchdog timer automatically starts after reset. 1: Watchdog timer is stopped after reset. R/W b1 — Reserved bit Set to 1. R/W b2 ROMCR ROM code protect disable bit 0: ROM code protect disabled 1: ROMCP1 bit enabled R/W b3 ROMCP1 ROM code protect bi t 0: ROM code protect enabled 1: ROM code protect disabled R/W b4 VDSEL0 Voltage detection 0 level select bit (2) b5 b4 0 0: 3.80 V selected (Vdet0_3) 0 1: 2.85 V selected (Vdet0_2) 1 0: 2.35 V selected (Vdet0_1) 1 1: 1.90 V selected (Vdet0_0) R/W b5 VDSEL1 R/W b6 LVDAS Voltage detection 0 circuit start bit (3) 0: Voltage monitor 0 reset enabled after reset 1: Voltage monitor 0 reset disabled after reset R/W b7 CSPROINI Count source protection mode after reset select bit 0: Count source protect mode enabled after reset 1: Count source protect mode disabled after reset R/W

R8C/32A Group 14. Watchdog Timer REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 161 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

14.2.7 Option Function Sel ect Register 2 (OFS2)

Note: 1. If the block including the OFS2 register is erased, the OFS2 register value is set to FFh. The OFS2 register is located on the flash memory. Write to this register with a program. After writing, do not write additions to this register. Bits WDTRCS0 and WDTRCS1 (Watchdog Timer Refresh Acknowledgement Period Set Bit) Assuming that the period from when the watchdog timer starts counting until it underflows is 100%, the refresh acknowledgement period for the watchdog timer can be selected. For details, refer to 14.3.1.1 Refresh Acknowledgment Period. Address 0FFDBh B i t b 7 b 6 b 5 b 4 b 3b 2b 1b 0 Symbol — — — — WDTRCS1 WDTRCS0 WDTUFS1 WDTUFS0 When shipping 1 1 1 1 1 1 1 1 (Note 1) Bit Symbol Bit Name Function R/W b0 WDTUFS0 Watchdog timer underflow period set bit b1 b0 0 0: 03FFh 0 1: 0FFFh 1 0: 1FFFh 1 1: 3FFFh R/W b1 WDTUFS1 R/W b2 WDTRCS0 Watchdog timer refresh acknowledgement period set bit b3 b2 0 0: 25% 0 1: 50% 1 0: 75% 1 1: 100% R/W b3 WDTRCS1 R/W b4 — Reserved bits Set to 1. R/W b5 — b6 — b7 —

R8C/32A Group 14. Watchdog Timer REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 162 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

14.3 Functional Description

14.3.1 Common Items for Multiple Modes

14.3.1.1 Refresh Acknowledgment Period

The period for acknowledging refreshment operation to the watchdog timer (write to the WDTR register) can be selected by bits WDTRCS0 and WDTRCS1 in th e OFS2 register. Figure 14.2 shows the Refresh Acknowledgement Period for Watchdog Timer. Assuming that the period from when the watchdog timer starts counting until it underflows is 100%, a refresh operation executed during the refresh acknowledgement period is acknowledged. Any refresh operation executed during the period other than the above is processed as an incorrect write, and a watchdog timer interrupt or watchdog timer reset (selectable by the PM12 bit in the PM1 register) is generated. Figure 14.2 Refresh Acknowledgement Period for Watchdog Timer Count starts Note: 1. A watchdog timer interrupt or watchdog timer reset is generated. Watchdog timer period Underflow Refresh can be acknowledged Refresh can be acknowledged Refresh can be acknowledged Processed as incorrect write (1) Refresh can be acknowledged Processed as incorrect write (1) Processed as incorrect write (1) 25% 50% 75% 100% Refresh acknowledge period 100% (WDTRCS1 to WDTRCS0 = 11b) 75% (WDTRCS1 to WDTRCS0 = 10b) 50% (WDTRCS1 to WDTRCS0 = 01b) 25% (WDTRCS1 to WDTRCS0 = 00b) WDTRCS0, WDTRCS1: Bits in OFS2 register

R8C/32A Group 14. Watchdog Timer REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 163 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

14.3.2 Count Source Protection Mode Disabled

The count source for the watchdog timer is the CPU clock when count source protection mode is disabled. Table 14.2 lists the Watchdog Timer Specifications (Count Source Protection Mode Disabled). Notes: 1. The watchdog timer is initialized when 00h and then FFh is wri tten to the WDTR register. The prescaler is initialized after a reset. This may cause some errors due to the prescaler during the watchdog timer period. 2. The WDTON bit cannot be changed by a program. To set this bit, write 0 to bit 0 of address 0FFFFh with a flash programmer. Table 14.2 Watchdog Timer Specifications (Count Source Protection Mode Disabled) Item Specification Count source CPU clock Count operation Decrement Period Division ratio of prescaler (n) × count value of watchdog timer (m) (1) CPU clock n: 16 or 128 (selected by the WDTC7 bit in the WDTC register), or 2 when selecting the low-speed clock (CM07 bit in CM0 register = 1) m: Value set by bits WDTUFS0 and WDTUFS1 in the OFS2 register Example: The period is approximately 13.1 ms when: - The CPU clock frequency is set to 20 MHz. - The prescaler is divided by 16. - Bits WDTUFS1 to WDTUFS0 are set to 11b (3FFFh). Watchdog timer initialization conditions

• Reset
• Write 00h and then FFh to the WDTR register.
• Underflow Count start conditions The operation of the watchdog timer after a reset is selected by the WDTON bit (2) in the OFS register (address 0FFFFh).
• When the WDTON bit is set to 1 (watchdog timer is stopped after reset). The watchdog timer and prescaler are stopped after a reset and start counting when the WDTS register is written to.
• When the WDTON bit is set to 0 (watchdog timer starts automatically after reset). The watchdog timer and prescaler start counting automatically after a reset. Count stop condition Stop mode, wait mode (Count resumes from the retained value after exiting.) Operations at underflow • When the PM12 bit in the PM1 register is set to 0. Watchdog timer interrupt
• When the PM12 bit in the PM1 register is set to 1. Watchdog timer reset (refer to 5.5 Watchdog Timer Reset)

R8C/32A Group 14. Watchdog Timer REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 164 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

14.3.3 Count Source Protection Mode Enabled

The count source for the watchdog timer is the low-spee d on-chip oscillator clock for the watchdog timer when count source protection mode is enabled. If the CPU cloc k stops when a program is out of control, the clock can still be supplied to the watchdog timer. Table 14.3 lists the Watchdog Timer Specifications (Count Source Protection Mode Enabled). Notes: 1. The WDTON bit cannot be changed by a program. To set this bit, write 0 to bit 0 of address 0FFFFh with a flash programmer. 2. Even if 0 is written to the C SPROINI bit in the OFS register, the CSPRO bit is set to 1. The CSPROINI bit cannot be changed by a program. To set this bit, write 0 to bit 7 of address 0FFFFh with a flash programmer. Table 14.3 Watchdog Timer Specifications (Count Source Protection Mode Enabled) Item Specification Count source Low-speed on -chip oscillator clock Count operation Decrement Period Count value of watchdog timer (m) Low-speed on-chip oscillator clock for the watchdog timer m: Value set by bits WDTUFS0 and WDTUFS1 in the OFS2 register Example: The period is approximately 8.2 ms when: - The on-chip oscillator clock for the watchdog timer is set to 125 kHz. - Bits WDTUFS1 to WDTUFS0 are set to 00b (03FFh). Watchdog timer initialization conditions

• R e s e t
• Write 00h and then FFh to the WDTR register.
• Underflow Count start conditions The operation of the wa tchdog timer after a reset is selected by the WDTON bit (1) in the OFS register (address 0FFFFh).
• When the WDTON bit is set to 1 (watchdog timer is stopped after reset). The watchdog timer and prescaler are stopped after a reset and start counting when the WDTS register is written to.
• When the WDTON bit is set to 0 (watchdog timer starts automatically after reset). The watchdog timer and prescaler start counting automatically after a reset. Count stop condition None (Count does not stop even in wait mode once it starts. The MCU does not enter stop mode.) Operation at underflow Watc hdog timer reset (Refer to 5.5 Watchdog Timer Reset.) Registers, bits • When the CSPPRO bit in the CSPR register is set to 1 (count source protection mode enabled) (2), the following are set automatically: - The low-speed on-chip oscillator for the watchdog timer is on. - The PM12 bit in the PM1 register is set to 1 (watchdog timer reset when the watchdog timer underflows).

R8C/32A Group 15. DTC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 165 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 15. DTC The DTC (data transfer controller) is a function that transfers data between the SFR and on-chip memory without using the CPU. This chip incorporates one DTC channel. The DTC is activated by a peripheral function interrupt to perform data transfers. The DTC and CPU use the same bus, and the DTC takes priority over the CPU in using the bus. To control DTC data transfers, control da ta comprised of a transfer source address, a transfer destination address, and operating modes are allocated in the DTC control data area. Each time the DTC is activated, the DTC reads control data to perform data transfers.

15.1 Overview

Table 15.1 shows the DTC Specifications. i = 0 to 3, 5, 6 Table 15.1 DTC Specifications Item Specification Activation sources 21 sources Allocatable control data 24 sets Address space which can be transferred 64 Kbytes (00000h to 0FFFFh) Maximum number of transfer times Normal mode 256 times Repeat mode 255 times Maximum size of block to be transferred Normal mode 256 bytes Repeat mode 255 bytes Unit of transfers Byte Transfer mode Normal mode Transfers end on completion of the transfer causing the DTCCT register value to change from 1 to 0. Repeat mode On completion of the transfer causing the DTCCT register value to change from 1 to 0, the repeat area address is initialized and the DTRLD register value is reloaded to the DTCCT register to continue transfers. Address control Normal mode Fixed or incremented Repeat mode Addresses of the area not sele cted as the repeat area are fixed or incremented. Priority of activation sources See Table 15.6 DTC Activation Sources and DTC Vector Addresses. Interrupt request Normal mode On completion of t he data transfer causing the DTCCT register value to change from 1 to 0, the activation source interrupt request is generated for the CPU. Repeat mode When the RPTINT bit in the DT CCR register is 1 (interrupt generation enabled), the activation source interrupt request is generated for the CPU on completion of the data transfer causing the DTCCT register value to change from 1 to 0. Transfer start When bits DTCENi0 to DTCE Ni1 and bits DTCENi3 to DTCENi7 in the DTCENi registers are 1 (activation enabled), data transfer is started each time the corresponding DTC activation sources are generated. Transfer stop Normal mode • When bits DTCENi0 to DTCENi1 and bits DTCENi3 to DTCENi7 are set to 0 (activation disabled).

• When the data transfer causing the DTCCT register value to change from 1 to 0 is completed. Repeat mode • When bits DTCENi0 to DTCENi1 and bits DTCENi3 to DTCENi7 are set to 0 (activation disabled).
• When the data transfer causing the DTCCT register value to change from 1 to 0 is completed while the RPTINT bit is 1 (interrupt generation enabled).

R8C/32A Group 15. DTC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 166 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 15.1 DTC Block Diagram

15.2 Registers

Table 15.2 shows the Register Configuration and Tabl e 15.3 shows the Correspondenc es between Bits DTCENi0 to DTCENi1, Bits DTCENi3 to DTCENi7 (i = 0 to 3, 5, 6) and Interrupt Sources. Notes: 1. The registers in the DTC cannot be directly read or written to. 2. Allocated as control data at addresses from 2C40h to 2CFFh in the DTC control data area. Table 15.2 Register Configuration Register Name Symbol R/W After Reset Address DTC control register DTCCR — (1) 00h — (2) DTC block size register DTBLS — (1) 00h — (2) DTC transfer count register DTCCT — (1) 00h — (2) DTC transfer count reload register DTRLD — (1) 00h — (2) DTC source address register DTSAR — (1) 00h — (2) DTC destination address register DTDAR — (1) 00h — (2) DTC activation control register DTCTL R/W 00h 0080h DTC activation enable register 0 DTCEN0 R/W 00h 0088h DTC activation enable register 1 DTCEN1 R/W 00h 0089h DTC activation enable register 2 DTCEN2 R/W 00h 008Ah DTC activation enable register 3 DTCEN3 R/W 00h 008Bh DTC activation enable register 5 DTCEN5 R/W 00h 008Dh DTC activation enable register 6 DTCEN6 R/W 00h 008Eh DTCENi (i = 0 to 3, 5, 6) Interrupt controller Peripheral interrupt request Control circuit DTCCR DTBLS DTCCT DTRLD DTSAR DTDAR DTC activation request Peripheral interrupt request Internal bus CPU Bus interface ROM RAM Peripheral functions DTCCR: DTC control register DTBLS: DTC block size register DTCCT: DTC transfer count register DTRLD: DTC transfer count reload register DTSAR: DTC source address register DTDAR: DTC destination address register DTCTL: DTC activation control register DTCEN0 to DTCEN6: DTC activation enable registers 0 to 6Peripheral bus DTCTL

R8C/32A Group 15. DTC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 167 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

15.2.1 DTC Control Register (DTCCR)

Notes: 1. This bit is valid when the MODE bit is 1 (repeat mode). 2. Settings of bits SAMOD and DAMOD are invalid for the repeat area.

15.2.2 DTC Block Size Register (DTBLS)

Note: 1. When the DTBLS register is set to 00h, the block size is 256 bytes. Address See Table 15.5 Control Data Allocation Addresses. B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — RPTINT CHNE DAMOD SAMOD RPTSEL MODE A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 MODE Transfer mode select bit 0: Normal mode 1: Repeat mode b1 RPTSEL Repeat area select bit (1) 0: Transfer destination is the repeat area. 1: Transfer source is the repeat area. b2 SAMOD Source address control bit (2) 0: Fixed 1: Incremented b3 DAMOD Destination address control bit (2) 0: Fixed 1: Incremented b4 CHNE Chain transfer enable bit 0: Chain transfers disabled 1: Chain transfers enabled b5 RPTINT Repeat mode interrupt enable bit (1) 0: Interrupt generation disabled 1: Interrupt generation enabled b6 — Reserved bits Set to 0. R/W b7 — Address See Table 15.5 Control Data Allocation Addresses. B i t b 7b 6b 5b 4b 3b 2b 1 b 0 A f t e r R e s e t 0000000 0 Bit Function Setting Range R/W b7 to b0 These bits specify the size of the data block to be transferred by one activation. 00h to FFh (1) —

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15.2.3 DTC Transfer C ount Register (DTCCT)

Note: 1. When the DTCCT register is set to 00h, the number of tr ansfer times is 256. Each time the DTC is activated, the DTCCT register is decremented by 1.

15.2.4 DTC Transfer Count Reload Register (DTRLD)

Note: 1. Set the initial value for the DTCCT register.

15.2.5 DTC Source Addr ess Register (DTSAR)

15.2.6 DTC Destinatio n Register (DTDAR)

Address See Table 15.5 Control Data Allocation Addresses. B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00000000 Bit Function Setting Range R/W b7 to b0 These bits specify the number of times of DTC data transfers. 00h to FFh (1) — Address See Table 15.5 Control Data Allocation Addresses. B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00000000 Bit Function Setting Range R/W b7 to b0 This register value is reloaded to the DTCCT register in repeat mode. 00h to FFh (1) — Address See Table 15.5 Control Data Allocation Addresses. B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00000000 Bit b15 b14 b13 b12 b11 b10 b9 b8 A f t e r R e s e t 00000000 Bit Function Setting Range R/W b15 to b0 These bits specify a transfer source address for data transfer. 0000h to FFFFh — Address See Table 15.5 Control Data Allocation Addresses. B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00000000 Bit b15 b14 b13 b12 b11 b10 b9 b8 A f t e r R e s e t 00000000 Bit Function Setting Range R/W b15 to b0 These bits specify a transfer destination address for data transfer. 0000h to FFFFh —

R8C/32A Group 15. DTC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 169 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

15.2.7 DTC Activation Enable Register s (DTCENi) (i = 0 to 3, 5, 6)

i = 0 to 3, 5, 6 The DTCENi registers enable/disable DTC activation by interrupt sources. Table 15.3 shows Correspondences between Bits DTCENi0 to DTCENi1, Bits DTCENi3 to DTCENi7 (i = 0 to 3, 5, 6) and Interrupt Sources. Address 0088h (DTCEN0), 0089h (DTCEN1), 008Ah (DTCEN2), 008Bh (DTCEN3), 008Dh (DTCEN5), 008Eh (DTCEN6) B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol DTCENi7 DTCENi6 DTCENi5 DTCENi4 DTCENi3 — DTCENi1 DTCENi0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 DTCENi0 DTC activation enable bit 0: Activation disabled 1: Activation enabled R/W b1 DTCENi1 R/W b2 — Reserved bit Set to 0. R/W b3 DTCENi3 DTC activation enable bit 0: Activation disabled 1: Activation enabled R/W b4 DTCENi4 R/W b5 DTCENi5 R/W b6 DTCENi6 R/W b7 DTCENi7 R/W Table 15.3 Correspondences between Bits DTCENi0 to DTCENi1, Bits DTCENi3 to DTCENi7 (i = 0 to 3, 5, 6) and Interrupt Sources Register DTCENi7 Bit DTCENi6 Bit DTCENi5 Bit DTCENi4 Bit DTCENi3 Bit DTCENi1 Bit DTCENi0 Bit DTCEN0 INT0 INT1 — INT3 ——— DTCEN1 Key input A/D conversion UART0 reception UART0 transmission — UART2 reception UART2 transmission DTCEN2 I2C bus/SSU receive data full I2C bus/SSU transmit data empty Voltage monitor 2/ comparator A2 Voltage monitor 1/ comparator A1 Timer RC input-capture/ compare- match A Timer RC input-capture/ compare- match B DTCEN3 Timer RC input-capture/ compare- match C Timer RC input-capture/ compare- match D DTCEN6 — Timer RA — Timer RB Flash memory ready status ——

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15.2.8 DTC Activation Co ntrol Register (DTCTL)

Note: 1. This bit is set to 0 when the read result is 1 a nd 0 is written to the same bit. This bit remains unchanged even if the read result is 0 and 0 is written to the same bit. This bit remains unchanged if 1 is written to it. The DTCTL register controls DTC act ivation when a non-maskable interrupt (an interrupt by the watchdog timer, oscillation stop detection, voltage monitor 1, or voltage monitor 2) is generated. NMIF Bit (Non-Maskable Interrupt Generation Bit) The NMIF bit is set to 1 when a watchdog timer inte rrupt, an oscillation stop detection interrupt, a voltage monitor 1 interrupt, or a voltage monitor 2 interrupt is generated. When the NMIF bit is 1, the DTC is not activated even if the interrupt which enables DTC activation is generated. If the NMIF bit is changed to 1 during DTC transfer, the transfer is continued until it is completed. Address 0080h B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 — Reserved bit Set to 0. R/W b1 NMIF Non-maskable interrupt generation bit (1) 0: Non-maskable interrupts not generated 1: Non-maskable interrupts generated R/W b2 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b3 — b4 — b5 — b6 — b7 —

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15.3 Function Description

15.3.1 Overview

When the DTC is activated, control data is read from th e DTC control data area to perform data transfers and control data after data transfer is written back to the DTC control data area. Twenty-four sets of control data can be stored in the DTC control data area, which allows 24 types of data transfers to be performed. There are two transfer modes: normal mode and repeat mode. In additi on, multiple transfers can be performed by one activation source (chain transfers) when the CHNE bit in the DTCCR register is set to 1 (chain transfers enabled). A transfer source address is specified by the 16-bit re gister DTSAR, and a transf er destination address is specified by the 16-bit register DTDAR. The values in the registers DTSAR and DTDAR are separately fixed or incremented according to the control data on completion of the data transfer.

15.3.2 Activation Sources

The DTC is activated by an interrupt source. Figure 15.2 is a Block Diagram Showing Control of DTC Activation Sources. The interrupt sources to activ ate the DTC are selected with the DTCENi registers (i = 0 to 3, 5, 6). After one data transfer is completed (after the first transfer is completed in chain transfers), set 0 (activation disabled) to either of the following: the interrupt source flag in the status register for the peripheral function which generates the activation source or the corresponding bit amo ng bits DTCENi0 to DTCENi 1, and bits DTCENi3 to DTCENi7 in the DTCENi register. Table 15.4 shows the DTC Activation Sources and Interr upt Source Flags for Setting to 0 at Data Transfer Completion. If multiple activation sources are simultaneously gene rated, the DTC activation will be performed according to the DTC activation source priority. DTC activation is not affected by the I flag or interrupt control register, unlike with interrupt request operation. Therefore, even if interrupt requests cannot be ackno wledged because interrupts ar e disabled, DTC activation requests can be acknowledged. The IR bit in the inte rrupt control register does not change when a DTC activation request is acknowledged. Figure 15.2 Block Diagram Showing Co ntrol of DTC Activation Sources Interrupt controller Select interrupt source or DTC activation source DTCENi Clear control Peripheral function 1 Peripheral function 2 (I2C bus/SSU, timer RC, flash memory) DTC Interrupt request Peripheral interrupt request Peripheral interrupt request DTC activation request Select DTC activation or interrupt generation. Set the bit among bits DTCENi0 to DTCENi1, DTCENi3 to DTCENi7 (i = 0 to 3, 5, 6) to 0.Set the interrupt source flag in the status register to 0.

R8C/32A Group 15. DTC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 172 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Table 15.4 DTC Activation Sources and Interrupt Source Flags for Setting to 0 at Data Transfer Completion DTC activation source generation Interrupt Source Flag for Setting to 0 I2C bus/SSU receive data full ICSR register/RDRF bit in SSSR register I2C bus/SSU transmit data empty ICSR register/TDRE bit in SSSR register Timer RC input-capture/compare-match A IMFA bit in TRCSR register Timer RC input-capture/compare-match B IMFB bit in TRCSR register Timer RC input-capture/compare-match C IMFC bit in TRCSR register Timer RC input-capture/compare-match D IMFD bit in TRCSR register Flash memory ready status RDYSTI bit in FST register

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15.3.3 Control Data Allocatio n and DTC Vector Table

Control data is allocated in the order: Register s DTCCR, DTBLS, DTCCT, DTRLD, DTSAR, and DTDAR. Table 15.5 shows the Control Data Allocation Addresses. Table 15.5 Control Data Allocation Addresses Register Symbol Control Data No. Address DTCCR Register DTBLS Register DTCCT Register DTRLD Register DTSAR Register (Lower

8 Bits)

(Higher (Lower (Higher 2C47h 2C40h 2C41h 2C42h 2C43h 2C44h 2C45h 2C46h 2C47h DTCD1 Control Data 1 2C48h to 2C4Fh 2C48h 2C49h 2C4Ah 2C4Bh 2C4Ch 2C4Dh 2C4Eh 2C4Fh DTCD2 Control Data 2 2C50h to 2C57h 2C50h 2C51h 2C52h 2C53h 2C54h 2C55h 2C56h 2C57h DTCD3 Control Data 3 2C58h to 2C5Fh 2C58h 2C59h 2C5Ah 2C5Bh 2C5Ch 2C5Dh 2C5Eh 2C5Fh DTCD4 Control Data 4 2C60h to 2C67h 2C60h 2C61h 2C62h 2C63h 2C64h 2C65h 2C66h 2C67h DTCD5 Control Data 5 2C68h to 2C6Fh 2C68h 2C69h 2C6Ah 2C6Bh 2C6Ch 2C6Dh 2C6Eh 2C6Fh DTCD6 Control Data 6 2C70h to 2C77h 2C70h 2C71h 2C72h 2C73h 2C74h 2C75h 2C76h 2C77h DTCD7 Control Data 7 2C78h to 2C7Fh 2C78h 2C79h 2C7Ah 2C7Bh 2C7Ch 2C7Dh 2C7Eh 2C7Fh DTCD8 Control Data 8 2C80h to 2C87h 2C80h 2C81h 2C82h 2C83h 2C84h 2C85h 2C86h 2C87h DTCD9 Control Data 9 2C88h to 2C8Fh 2C88h 2C89h 2C8Ah 2C8Bh 2C8Ch 2C8Dh 2C8Eh 2C8Fh DTCD10 Control Data 10 2C90h to 2C97h 2C90h 2C91h 2C92h 2C93h 2C94h 2C95h 2C96h 2C97h DTCD11 Control Data 11 2C98h to 2C9Fh 2C98h 2C99h 2C9Ah 2C9Bh 2C9Ch 2C9Dh 2C9Eh 2C9Fh DTCD12 Control Data 12 2CA0h to 2CA7h 2CA0h 2CA1h 2CA2h 2CA3h 2CA4h 2CA5h 2CA6h 2CA7h DTCD13 Control Data 13 2CA8h to 2CAFh 2CA8h 2CA9h 2CAAh 2CABh 2CACh 2CADh 2CAEh 2CAFh DTCD14 Control Data 14 2CB0h to 2CB7h 2CB0h 2CB1h 2CB2h 2CB3h 2CB4h 2CB5h 2CB6h 2CB7h DTCD15 Control Data 15 2CB8h to 2CBFh 2CB8h 2CB9h 2CBAh 2CBBh 2CBCh 2CBDh 2CBEh 2CBFh DTCD16 Control Data 16 2CC0h to 2CC7h 2CC0h 2CC1h 2CC2h 2CC3h 2CC4h 2CC5h 2CC6h 2CC7h DTCD17 Control Data 17 2CC8h to 2CCFh 2CC8h 2CC9h 2CCAh 2CCBh 2CCCh 2CCDh 2CCEh 2CCFh DTCD18 Control Data 18 2CD0h to 2CD7h 2CD0h 2CD1h 2CD2h 2CD3h 2CD4h 2CD5h 2CD6h 2CD7h DTCD19 Control Data 19 2CD8h to 2CDFh 2CD8h 2CD9h 2CDAh 2CDBh 2CDCh 2CDDh 2CDEh 2CDFh DTCD20 Control Data 20 2CE0h to 2CE7h 2CE0h 2CE1h 2CE2h 2CE3h 2CE4h 2CE5h 2CE6h 2CE7h DTCD21 Control Data 21 2CE8h to 2CEFh 2CE8h 2CE9h 2CEAh 2CEBh 2CECh 2CEDh 2CEEh 2CEFh DTCD22 Control Data 22 2CF0h to 2CF7h 2CF0h 2CF1h 2CF2h 2CF3h 2CF4h 2CF5h 2CF6h 2CF7h DTCD23 Control Data 23 2CF8h to 2CFFh 2CF8h 2CF9h 2CFAh 2CFBh 2CFCh 2CFDh 2CFEh 2CFFh

R8C/32A Group 15. DTC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 174 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. When the DTC is activated, one control data is selected according to the data read from the vector table which has been assigned to each activation s ource, and the selected control data is read from the DTC control data area. Table 15.6 shows the DTC Activation Sources and DTC Ve ctor Addresses. A one-byte vector table area is assigned to each activation source and one value from 00000000b to 00010111b is stored in each area to select one of the 24 control data sets. Figure 15.3 shows a DTC Internal Operation Flowchart. Table 15.6 DTC Activation Sources and DTC Vector Addresses Interrupt Request Source Interrupt Name So urce No. DTC Vector Address Priority External input INT0 0 2C00h High INT1 1 2C01h (Reserved) 2 2C02h INT3 3 2C03h (Reserved) 4 2C04h Key input Key input 8 2C08h A/D A/D conversion 9 2C09h UART0 UART0 reception 10 2C0Ah UART0 transmission 11 2C0Bh (Reserved) — 12 2C0Ch —1 3 2 C 0 D h UART2 UART2 reception 14 2C0Eh UART2 transmission 15 2C0Fh I 2C bus/SSU Receive data full 16 2C10h Transmit data empty 17 2C11h Voltage detection circuit Voltage monitor 2/comparator A2 18 2C12h Voltage monitor 1/comparator A1 19 2C13h Timer RC Input-capture/compare-match A 22 2C16h Input-capture/compare-match B 23 2C17h Input-capture/compare-match C 24 2C18h Input-capture/compare-match D 25 2C19h (Reserved) — 26 2C1Ah —2 7 2 C 1 B h —2 8 2 C 1 C h —2 9 2 C 1 D h —3 0 2 C 1 E h —3 1 2 C 1 F h — 32 2C20h — 33 2C21h Timer RE Timer RE 42 2C2Ah Timer RA Timer RA 49 2C31h Timer RB Timer RB 51 2C33h Flash memory Flash memory ready status 52 2C34h Low

R8C/32A Group 15. DTC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 175 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 15.3 DTC Internal Operation Flowchart DTC activation source generation NMIF = 1? Read DTC vector Read control data Transfer data Write back control data CHNE = 1? Branch 1 Branch 2 Write 0 to the interrupt source flag in the status register End Write 0 to the bit among DTCENi0 to DTCENi1, DTCENi3 to DTCENi7 Generate an interrupt request for the CPU Interrupt handling Branch 1 On completion of DTC transfer (on completion of the first DTC transfer in chain transfers), 0 is written to the bit among bits DTCENi0 to DTCENi1, DTCENi3 to DTCENi7 and an interrupt request is generated in either of the following: - When the DTCCT register value changes to 0 in normal mode - When the RPTINT bit is 1 and the DTCCT register value changes to 0 in repeat mode Branch 2 0 is written to the interrupt source flag in the peripheral status register when the DTC activation source is either of the following: - I2C bus/SSU receive data full - I2C bus/SSU transmit data empty - timer RC input-capture/compare-match A to D - Flash memory ready status Yes No Yes No Yes No No Yes DTCENi0 to DTCENi1, DTCENi3 to DTCENi7: Bits in DTCENi registers (i = 0 to 3, 5, 6) RPTINT: Bit in DTCCR register

R8C/32A Group 15. DTC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 176 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

15.3.4 Normal Mode

One to 256 bytes of data are transferred by one activatio n. The number of transfer times can be 1 to 256. When the specified number of transfer times is completed, an interrupt request is generated for the CPU. Table 15.7 shows Register Functions in Normal Mode. Figure 15.4 shows Data Transfers in Normal Mode. Figure 15.4 Data Transfers in Normal Mode Table 15.7 Register Functions in Normal Mode Register Symbol Function DTC block size register DTBLS Size of the da ta block to be transferred by one activation DTC transfer count register DTCCT Num ber of times of data transfers DTC transfer count reload register DTRLD Not used DTC source address register DTSAR Data transfer source address DTC destination address register DTDAR Data transfer destination address SRC Transfer DST Transfer source Transfer destination Size of the data block to be transferred by one activation (N bytes) DTBLS = N DTSAR = SRC DTDAR = DST Bits b3 to b0 in DTCCR register 00X0b 01X0b 10X0b 11X0b Source address control Fixed Incremented Fixed Incremented Destination address control Fixed Fixed Incremented Incremented Source address after transfer SRC SRC+N SRC SRC+N Destination address after transfer DST DST DST+N DST+N X: 0 or 1

R8C/32A Group 15. DTC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 177 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

15.3.5 Repeat Mode

One to 255 bytes of data are transferred by one activation. Either of the transfer source or destination should be specified as the repeat area. The nu mber of transfer times can be 1 to 255. On completion of the specified number of transfer times, the DTCCT register and the address specified fo r the repeat area are initialized to continue transfers. When the RPTINT bit in the DTCCR register is 1 to enable the interrupt generation, an interrupt request is generated for the CPU after the specified number of transfer times. The lower 8 bits of the initial value for the repeat area a ddress must be 00h. The size of data to be transferred must be set to 255 bytes or less before the specified number of transfer times is completed. Table 15.8 shows Register Functions in Repeat Mode. Figure 15.5 shows Data Transfers in Repeat Mode. Figure 15.5 Data Transfers in Repeat Mode Table 15.8 Register Functions in Repeat Mode Register Symbol Function DTC block size register DTBLS Size of the da ta block to be transferred by one activation DTC transfer count register DTCCT Num ber of times of data transfers DTC transfer count reload register DTRLD This register value is reloaded to the DTCCT register. (Data transfer count is initialized.) DTC source address register DTSAR Data transfer source address DTC destination address register DTDAR Data transfer destination address SRC Transfer DST Transfer source Transfer destination Size of the data block to be transferred by one activation (N bytes) DTBLS = N DTCCT ≠ 1 DTSAR = SRC DTDAR = DSTBits b3 to b0 in DTCCR register 0X11b 1X11b X001b X101b Source address control Repeat area Repeat area Fixed Incremented Destination address control Fixed Incremented Repeat area Repeat area Source address after transfer SRC+N SRC+N SRC SRC+N Destination address after transfer DST DST+N DST+N DST+N DTCCT register ≠ 1 DTCCT register = 1 SRC0/DST0 Repeat area Bits b3 to b0 in DTCCR register 0X11b 1X11b X001b X101b Source address control Repeat area Repeat area Fixed Incremented Destination address control Fixed Incremented Repeat area Repeat area Source address after transfer SRC0 SRC0 SRC SRC+N Destination address after transfer DST DST+N DST0 DST0 SRC/DST Address of the repeat area is initialized after a transfer. DTBLS = N DTCCT = 1 DTSAR = SRC DTDAR = DST SRC0: Initial source address value DST0: Initial destination address value X: 0 or 1 X: 0 or 1

R8C/32A Group 15. DTC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 178 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

15.3.6 Chain Transfers

When the CHNE bit in the DTCCR register is 1 (chain transfers enabled), multiple data transfers can be continuously performed by one activation source. Figure 15.6 shows a Flow of Chain Transfers. When the DTC is activated, one control data is selected according to the data read from the DTC vector address corresponding to the activation source, and the selected control data is read from the DTC control data area. When the CHNE bit for the control data is 1 (chain transfers enabled), the next control data immediately following the current control data is read and transferred after the current transfer is completed. This operation is repeated until the data transfer with the control data for which the CHNE bit is 0 (chain transfers disabled) is completed. Figure 15.6 Flow of Chain Transfers

15.3.7 Interrupt Sources

When the specified number of times of data transfers is completed in normal mode or when completed while the PRTINT bit in the DTCCR register is 1 (interrupt generation enabled) in repeat mode, the interrupt request corresponding to the activation source is generated for th e CPU. Interrupt requests for the CPU are affected by the I flag or interrupt control regist er. In chain transfers, whether the in terrupt request is generated or not is determined either by the number of tr ansfer times specified for the first type of the transfer or the RPTINT bit. When an interrupt request is generated for the CPU, the bit among bits DTCENi0 to DTCENi1, and bits DTCENi3 to DTCENi7 in the DTCENi registers (i = 0 to 3, 5, 6) corresponding to the activation source are set to 0 (activation disabled). DTC activation source generation Read DTC vector Read control data 1 Transfer data Write back control data 1 Read control data 2 Data transfer Write back control data 2 End of DTC transfers Control data 1 CHNE = 1 Control data 2 CHNE = 0 DTC control data area CHNE: Bit in DTCCR register

R8C/32A Group 15. DTC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 179 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

15.3.8 Operation Timings

The DTC requires four clock cycles to read control data allocated in the DTC control data area. The number of clock cycles required to write back control data differs depending on the control data settings. Figure 15.7 shows an Example of DTC Operation Timi ngs and Figure 15.8 shows an Example of DTC Operation Timings in Chain Transfers. Table 15.9 shows the Specifications of Control Data Write-Back Operation. Figure 15.7 Example of DTC Operation Timings Figure 15.8 Example of DTC Operat ion Timings in Chain Transfers X: 0 or 1 Table 15.9 Specifications of Control Data Write-Back Operation Bits b3 to b0 in DTCCR Register Operating Mode Address Control Control Data to be Written Back Number of Clock CyclesSource Destination DTCCT Register DTRLD Register DTSAR Register DTDAR Register 00X0b Normal mode Fixed Fixed Written back Written back Not written back Not written back 1 01X0b Incremented Fixed Written back Written back Written back Not written back 2 10X0b Fixed Incremented Written back Written back Not written back Written back 2 11X0b Incremented Incremented Written bac k Written back Written back Written back 3 0X11b Repeat mode Repeat area Fixed Written back Wri tten back Written back Not written back 2 1X11b Incremented Written back Wri tten back Written back Written back 3 X001b Fixed Repeat area Written back Written back Not written back Written back 2 X101b Incremented Written back Writt en back Written back Written back 3 Used by CPU Read Write Used by CPU Read control data Transfer data Write back control data Read vector CPU clock Address Used by CPU Read Write Used by CPU Read vector Read control data Transfer data Write back control data Read control data Transfer data Write back control data CPU clock Address Read Write

R8C/32A Group 15. DTC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 180 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

15.3.9 Number of DTC Execution Cycles

Table 15.10 shows the Operations Following DTC Ac tivation and Required Number of Cycles for each operation. Table 15.11 shows the Number of Clock Cycles Required for Data Transfers. Note: 1. For the number of clock cycles required for data read/write, see Table 15.11 Number of Clock Cycles Required for Data Transfers. Data is transferred as described below, when the DTBLS register = N, (1) When N = 2n (even), two-byte transfers are performed n times. (2) When N = 2n + 1 (odd), two-byte transfers are perf ormed n times followed by one time of one-byte transfer. From Tables 15.10 and 15.11, the total number of requi red execution cycles can be obtained by the following formula: Number of required execution cycles = 1 + Σ[formula A] + 2 Σ: Sum of the cycles for th e number of transfer times performed by one activation sour ce ([the number of transfer times for which CHNE is set to 1] + 1) (1) For N = 2n (even) Formula A = J + n • SK2 + n • SL2 (2) For N = 2n+1 (odd) Formula A = J + n • SK2 + 1 • SK1 + n • SL2 + 1 • SL1 J: Number of cycles required to read or write back control data Table 15.10 Operations Following DTC Activation and Required Number of Cycles Vector Read Control Data Read Write (J) Data Read Data Write Internal Operation 1 5 to 7 (Note 1) (Note 1) 2 1 5 to 7 (Note 1) (Note 1) 2 Table 15.11 Number of Clock Cycles Required for Data Transfers Operation Unit of Transfers On-Chip RAM (During DTC Transfers) On-Chip ROM (User Area) On-Chip ROM (Data Area) SFR (Word Access) SFR (Byte Access)Even Address Odd Address Even Address Odd Address Data read 1-byte SK1 1 1 2 2 2 2 - b y t e S K 2 1224244 Data write 1-byte SL1 1 —— 22 2-byte SL2 12 —— 244

R8C/32A Group 15. DTC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 181 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

15.4 Notes on DTC

15.4.1 DTC activation source

• Do not generate any DTC activation sources before entering wait mode or during wait mode.
• Do not generate any DTC activation sources before entering stop mode or during stop mode.

15.4.2 DTCENi Registers (i = 0 to 3, 5, 6)

• Modify bits DTCENi0 to DTCENi1, and bits DT CENi3 to DTCENi7 only while an interrupt request corresponding to the bit is not generated.
• When the interrupt source flag in the status register for the peripheral function is 1, do not modify the corresponding activation source bit among bits DTCENi0 to DTCENi1, and bits DTCENi3 to DTCENi7.
• Do not access the DTCENi registers using DTC transfers.

15.4.3 Peripheral Modules

• Do not set the status register bit for the peripheral function to 0 using a DTC transfer.
• When the DTC activation source is I 2C bus/SSU receive data full, read the SSRDR register/the ICDRR register using a DTC transfer.
• When the DTC activation source is I2C bus/SSU transmit data empty, write to the SSTDR register/the ICDRT register using a DTC transfer.

R8C/32A Group 16. General Overview of Timers REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 182 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 16. General Overview of Timers The MCU has two 8-bit timers with 8-bi t prescalers, a 16-bit timer, and a ti mer with a 4-bit counter and an 8-bit counter. The two 8-bit timers with 8-bit prescalers are timer RA and timer RB. These timers contain a reload register to store the default value of the counter. The 16-bit timers are timer RC, and have inpu t capture and output compare functions. The 4-bit and 8-bit counters are timer RE, and has an output compare function. All the timers operate independently. Table 16.1 lists Functional Comparison of Timers.

R8C/32A Group 16. General Overview of Timers REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 183 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Note: 1. Rectangular waves are output in these modes. Since the waves are inverted at each overflow, the “H” and “L” level widths of the pulses are the same. Table 16.1 Functional Comparison of Timers Item Timer RA Timer RB Timer RC Timer RE Configuration 8-bit timer with 8-bit prescaler (with reload register) 8-bit timer with 8-bit prescaler (with reload register) 16-bit timer (with input capture and output compare) 4-bit counter 8-bit counter Count Decrement Decrement Increment Increment Count sources • f1

• f 2
• f 8
• f O C O
• f C 3 2
• f C
• f 1
• f 2
• f 8
• Timer RA underflow
• f 1
• f 2
• f 4
• f 8
• f 3 2
• fOCO40M
• fOCO-F
• TRCCLK
• f 4
• f 8
• f 3 2
• f C 4 Function Count of the internal count source Timer mode Timer mode Timer mode (output compare function) Count of the external count source Event counter mode — Timer mode (output compare function) External pulse width/ period measurement Pulse width measurement mode, pulse period measurement mode — Timer mode (input capture function; 4 pins) PWM output Pulse output mode (1), Event counter mode (1) Programmable waveform generation mode Timer mode (output compare function; 4 pins) (1), PWM mode (3 pins), PWM2 mode (1 pin) Output compare mode (1) One-shot waveform output — Programmable one- shot generation mode, Programmable wait one-shot generation mode PWM mode (3 pins) — Three-phase waveforms output ———— Timer Timer mode (only fC32 count) — — Real-time clock mode Input pin TRAIO INT0 INT0, TRCCLK, TRCTRG, TRCIOA, TRCIOB, TRCIOC, TRCIOD Output pin TRAO TRAIO TRBO TRCIOA, TRCIOB, TRCIOC, TRCIOD Related interrupt Timer RA interrupt Timer RB interrupt, INT0 interrupt Compare match/input capture A to D interrupt, Overflow interrupt, INT0 interrupt Timer RE interrupt Timer stop Provided Prov ided Provided Provided

R8C/32A Group 17. Timer RA REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 184 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 17. Timer RA Timer RA is an 8-bit timer with an 8-bit prescaler.

17.1 Overview

The prescaler and timer each consist of a reload register a nd counter. The reload register and counter are allocated at the same address, and can be accessed when accessing registers TRAP RE and TRA (refer to Tables 17.2 to 17.6 the Specification of Each Modes). The count source for timer RA is the operating clock that regulates the timing of timer operations such as counting and reloading. Figure 17.1 shows a Timer RA Block Diagram. Table 17.1 lists Pin Configuration of Timer RA. Timer RA contains the following five operating modes:

• Timer mode: The timer counts the internal count source.
• Pulse output mode: The timer counts the internal count source and outputs pulses which invert the polarity by underflow of the timer.
• Event counter mode: The timer counts external pulses.
• Pulse width measurement mode: T he timer measures the pulse width of an external pulse.
• Pulse period measurement mode: The timer measures the pulse period of an external pulse. Figure 17.1 Timer RA Block Diagram Table 17.1 Pin Configuration of Timer RA Pin Name Assigned Pin I/O Function TRAIO P1_5 or P1_7 I/O Function differs according to the mode. Refer to descriptions of individual modes for detailsTRAO P3_7 Output Counter Reload register TRAPRE register (prescaler) Data bus Timer RA interrupt Write to TRAMR register Write 1 to TSTOP bit TCSTF, TSTOP: TRACR register TEDGSEL, TOPCR, TOENA, TIPF1, TIPF0, TIOGT1, TIOGT0: TRAIOC register TMOD2 to TMOD0, TCK2 to TCK0, TCKCUT: TRAMR register Toggle flip-flop Q Q CLR CK TOENA bit TRAO pin TCSTF bit TMOD2 to TMOD0 = 011b or 100b Counter Reload register TRA register (timer) Count control circle TMOD2 to TMOD0 = 001b TOPCR bit Underflow signal Measurement completion signal TEDGSEL = 1 TEDGSEL = 0 Note: 1. Bits TRAIOSEL0 and TRAIOSEL1 in the TRASR register are used to select which pin is assigned. TRAIO pin (1) TCK2 to TCK0 bit TMOD2 to TMOD0 = other than 010b TMOD2 to TMOD0 = 010b Polarity switching Digital filter TIPF1 to TIPF0 bits = 01b = 10bf8 = 11bf32 TIPF1 to TIPF0 bits = other than 000b = 00b = 000b = 001b = 011bf2 = 010bfOCO = 100bfC32 TIOGT1 to TIOGT0 bits = 01b = 10b Do not set Event input always enabled = 00b Event enabled for “H” period of TRCIOD (timer RC compare match signal) = 110bfC TCKCUT bit

R8C/32A Group 17. Timer RA REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 185 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

17.2 Registers

17.2.1 Timer RA Cont rol Register (TRACR)

Notes: 1. Refer to 17.8 Notes on Timer RA for precautions regarding bits TSTART and TCSTF. 2. When the TSTOP bit is set to 1, bits TSTART and TCSTF and registers TPRAPRE and TRA are set to the values after a reset. 3. Bits TEDGF and TUNDF can be set to 0 by writing 0 to these bits by a program. However, their value remains unchanged when 1 is written. 4. Set to 0 in timer mode, pulse output mode, and event counter mode. In pulse width measurement mode and pulse period m easurement mode, use the MOV instruction to set the TRACR register. If it is necessary to avoid changing the values of bits TEDGF and TUNDF, write 1 to them.

17.2.2 Timer RA I/O Cont rol Register (TRAIOC)

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — TUNDF TEDGF — TSTOP TCSTF TSTART A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TSTART Timer RA count start bit (1) 0: Count stops 1: Count starts R/W b1 TCSTF Timer RA count status flag (1) 0: Count stops 1: During count R b2 TSTOP Timer RA count forcible stop bit (2) When this bit is set to 1, the count is forcibly stopped. When read, its content is 0. R/W b3 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b4 TEDGF Active edge judgment flag (3, 4) 0: Active edge not received 1: Active edge received (end of measurement period) R/W b5 TUNDF Timer RA underflow flag (3, 4) 0: No underflow 1: Underflow R/W b6 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b7 — Address 0101h B i t b 7b 6b 5b 4b 3b 2b 1 b 0 Symbol TIOGT1 TIOGT0 TIPF1 TIPF0 TIOSEL TOENA TOPCR TEDGSEL A f t e r R e s e t 0000000 0 Bit Symbol Bit Name Function R/W b0 TEDGSEL TRAIO polarity switch bit Function varies according to the operating mode. R/W b1 TOPCR TRAIO output control bit R/W b2 TOENA TRAO output enable bit R/W b3 TIOSEL Hardware LIN fu nction select bit R/W b4 TIPF0 TRAIO input filter select bit R/W b5 TIPF1 R/W b6 TIOGT0 TRAIO event input control bit R/W b7 TIOGT1 R/W

R8C/32A Group 17. Timer RA REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 186 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

17.2.3 Timer RA Mode Register (TRAMR)

When both the TSTART and TCSTF bits in the TRACR register are set to 0 (count stops), rewrite this register.

17.2.4 Timer RA Prescal er Register (TRAPRE)

Note: 1. When the TSTOP bit in the TRACR register is set to 1, the TRAPRE register is set to FFh. Address 0102h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TCKCUT TCK2 TCK1 TCK0 — TMOD2 TMOD1 TMOD0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TMOD0 Timer RA operating mode select bit b2 b1 b0 0 0 0: Timer mode 0 0 1: Pulse output mode 0 1 0: Event counter mode 0 1 1: Pulse width measurement mode 1 0 0: Pulse period measurement mode 1 0 1: Do not set. 1 1 0: Do not set. 1 1 1: Do not set. R/W b1 TMOD1 R/W b2 TMOD2 R/W b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b4 TCK0 Timer RA count source select bit b6 b5 b4 0 0 0: f1 0 0 1: f8 0 1 0: fOCO 0 1 1: f2 1 0 0: fC32 1 0 1: Do not set. 1 1 0: fC 1 1 1: Do not set. R/W b5 TCK1 R/W b6 TCK2 R/W b7 TCKCUT Timer RA count source cu toff bit 0: Provides count source 1: Cuts off count source R/W Address 0103h B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 11111111 ( N o t e 1 ) Bit Mode Function Setting Range R/W b7 to b0 Timer mode Counts an internal count source 00h to FFh R/W Pulse output mode 00h to FFh R/W Event counter mode Counts an external count source 00h to FFh R/W Pulse width measurement mode Measure pulse width of input pulses from external (counts internal count source) 00h to FFh R/W Pulse period measurement mode Measure pulse period of input pulses from external (counts internal count source) 00h to FFh R/W

R8C/32A Group 17. Timer RA REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 187 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

17.2.5 Timer RA Register (TRA)

Note: 1. When the TSTOP bit in the TRACR register is set to 1, the TRAPRE register is set to FFh.

17.2.6 Timer RA Pin Se lect Register (TRASR)

The TRASR register selects which pin is assigned to the timer RA I/O. To use the I/O pin for timer RA, set this register. Set the TRASR register before setting the timer RA associ ated registers. Also, do no t change the setting value in this register during timer RA operation. Address 0104h B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 11111111 ( N o t e 1 ) Bit Mode Function Setting Range R/W b7 to b0 All modes Counts on underflow of TRAPRE register 00h to FFh R/W Address 0180h B i t b 7b 6b 5 b 4 b 3 b 2 b 1 b 0 Symbol — — — — — — TRAIOSEL1 TRAIOSEL0 A f t e r R e s e t 000 0 0 0 0 0 Bit Symbol Bit Name Function R/W b0 TRAIOSEL0 TRAIO pin select bit b1 b0 0 0: TRAIO pin not used 0 1: P1_7 assigned 1 0: P1_5 assigned 1 1: Do not set. R/W b1 TRAIOSEL1 R/W b2 — Reserved bits Set to 0. R/W b3 — b4 — b5 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b6 — b7 —

R8C/32A Group 17. Timer RA REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 188 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

17.3 Timer Mode

In this mode, the timer counts an internally generated count source (refer to Table 17.2 Timer Mode Specifications).

17.3.1 Timer RA I/O Control Regi ster (TRAIOC) in Timer Mode

Table 17.2 Timer M ode Specifications Item Specification Count sources f1, f2, f8, fOCO, fC32 Count operations • Decrement

• When the timer underflows, the contents of the reload register are reloaded and the count is continued. Divide ratio 1/(n+1)(m+1) n: Value set in TRAPRE register, m: Value set in TRA register Count start condition 1 (count starts) is writte n to the TSTART bit in the TRACR register. Count stop conditions • 0 (count stops) is wri tten to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register. Interrupt request generation timing When timer RA underflows [timer RA interrupt]. TRAIO pin function Programmable I/O port TRAO pin function Programmable I/O port Read from timer The count value can be read by reading registers TRA and TRAPRE. Write to timer • When registers TRAPRE and TRA are written while the count is stopped, values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are written to the reload register and counter (refer to 17.3.2 Timer Write Control during Count Operation). Address 0101h B i t b 7b 6b 5b 4b 3b 2b 1 b 0 Symbol TIOGT1 TIOGT0 TIPF1 TIPF0 TIOSEL TOENA TOPCR TEDGSEL A f t e r R e s e t 0000000 0 Bit Symbol Bit Name Function R/W b0 TEDGSEL TRAIO polarity switch bit Set to 0 in timer mode. R/W b1 TOPCR TRAIO output control bit R/W b2 TOENA TRAO output enable bit R/W b3 TIOSEL Hardware LIN function select bit Set to 0. However, set to 1 when the hardware LIN function is used. R/W b4 TIPF0 TRAIO input filter select bit Set to 0 in timer mode. R/W b5 TIPF1 R/W b6 TIOGT0 TRAIO event input control bit R/W b7 TIOGT1 R/W

R8C/32A Group 17. Timer RA REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 189 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

17.3.2 Timer Write Contro l during Count Operation

Timer RA has a prescaler and a time r (which counts the prescaler unde rflows). The prescaler and timer each consist of a reload register and a coun ter. When writing to the prescaler or timer, values are written to both the reload register and counter. However, values are transferred from the reload register to the counter of the prescaler in synchronization with the count source. In addition, values are transferred from the reload register to the counter of the timer in synchronization with prescaler underflows. Therefore, if the prescaler or timer is written to when count operation is in progress, the counter value is not updated immediately after the WRITE instruction is executed. Figure 17.2 shows an Operating Example of Timer RA when Counter Value is Rewritten during Count Operation. Figure 17.2 Operating Example of Timer RA when Counter Value is Rewritten during Count Operation Count source Reload register of timer RA prescaler IR bit in TRAIC register 0 Counter of timer RA prescaler Reload register of timer RA Counter of timer RA Set 01h to the TRAPRE register and 25h to the TRA register by a program. After writing, the reload register is written to at the first count source. Reload at second count source Reload at underflow After writing, the reload register is written to at the first underflow.Reload at the second underflow The IR bit remains unchanged until underflow is generated by a new value. 05h 04h 01h 00h 01h 00h 01h 00h 01h 00h06h New value (01h)Previous value New value (25h)Previous value 03h 24h 02h 25h The above applies under the following conditions. Both bits TSTART and TCSTF in the TRACR register are set to 1 (during count).

R8C/32A Group 17. Timer RA REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 190 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

17.4 Pulse Output Mode

In pulse output mode, the internally generated count sour ce is counted, and a pulse with inverted polarity is output from the TRAIO pin each time the timer underflows (refer to Table 17.3 Pulse Output Mode Specifications). Note: 1. The level of the output pulse becomes the level when the pulse output starts when the TRAMR register is written to. Table 17.3 Pulse Output Mode Specifications Item Specification Count sources f1, f2, f8, fOCO, fC32 Count operations • Decrement

• When the timer underflows, the contents in the reload register is reloaded and the count is continued. Divide ratio 1/(n+1)(m+1) n: Value set in TRAPRE register, m: Value set in TRA register Count start condition 1 (count starts) is writte n to the TSTART bit in the TRACR register. Count stop conditions • 0 (count stops) is writ ten to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register. Interrupt request generation timing When timer RA underflows [timer RA interrupt]. TRAIO pin function Pulse output, programmable output port TRAO pin function Programmable I/O po rt or inverted output of TRAIO Read from timer The count value can be read by reading registers TRA and TRAPRE. Write to timer • When registers TRAPRE and TRA are written while the count is stopped, values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are written to the reload register and counter (refer to 17.3.2 Timer Write Control during Count Operation). Selectable functions • TRAIO signal polarity switch function The level when the pulse output starts is selected by the TEDGSEL bit in the TRAIOC register. (1)
• TRAO output function Pulses inverted from the TRAIO output polarity can be output from the TRAO pin (selectable by the TOENA bit in the TRAIOC register).
• Pulse output stop function Output from the TRAIO pin is stopped by the TOPCR bit in the TRAIOC register.
• TRAIO pin select function P1_5 or P1_7 is selected by bits TRAIOSEL0 to TRAIOSEL1 in the TRASR register.

R8C/32A Group 17. Timer RA REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 191 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

17.4.1 Timer RA I/O Cont rol Register (TRAIOC) in Pulse Output Mode

B i t b 7b 6b 5b 4b 3b 2b 1 b 0 Symbol TIOGT1 TIOGT0 TIPF1 TIPF0 TIOSEL TOENA TOPCR TEDGSEL A f t e r R e s e t 0000000 0 Bit Symbol Bit Name Function R/W b0 TEDGSEL TRAIO polarity switch bit 0: TRAIO output starts at “H” 1: TRAIO output starts at “L” R/W b1 TOPCR TRAIO output control bit 0: TRAIO output 1: Port P1_7 or P1_5 R/W b2 TOENA TRAO output enable bit 0: Port P3_7 1: TRAO output (inverted TRAIO output from P3_7) R/W b3 TIOSEL Hardware LIN function select bit Set to 0. R/W b4 TIPF0 TRAIO input filter select bit Set to 0 in pulse output mode. R/W b5 TIPF1 R/W b6 TIOGT0 TRAIO event input control bit R/W b7 TIOGT1 R/W

R8C/32A Group 17. Timer RA REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 192 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

17.5 Event Counter Mode

In event counter mode, external signal inputs to the TRAIO pin are counted (refer to Table 17.4 Event Counter Mode Specifications). Note: 1. The level of the output pulse becomes the level when the pulse output starts when the TRAMR register is written to. Table 17.4 Event Counter Mode Specifications Item Specification Count source External signal which is input to TRAIO pin (active edge selectable by a program) Count operations • Decrement

• When the timer underflows, the contents of the reload register are reloaded and the count is continued. Divide ratio 1/(n+1)(m+1) n: setting value of TRAPRE register, m: setting value of TRA register Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register. Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register. Interrupt request generation timing When timer RA underflows [timer RA interrupt]. TRAIO pin function Count source input TRAO pin function Programmable I/O port or pulse output (1) Read from timer The count value can be read by reading registers TRA and TRAPRE. Write to timer • When registers TRAPRE and TRA ar e written while the count is stopped, values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are written to the reload register and counter (refer to 17.3.2 Timer Write Control during Count Operation). Selectable functions •I N T 1 input polarity switch function The active edge of the count source is selected by the TEDGSEL bit in the TRAIOC register.
• Count source input pin select function P1_5 or P1_7 is selected by bits TRAIOSEL0 to TRAIOSEL1 in the TRASR register.
• Pulse output function Pulses of inverted polarity can be output from the TRAO pin each time the timer underflows (selectable by the TOENA bit in the TRAIOC register). (1)
• Digital filter function Whether enabling or disabling the digital filter and the sampling frequency is selected by bits TIPF0 and TIPF1 in the TRAIOC register.
• Event input control function The enabled period for the event input to the TRAIO pin is selected by bits TIOGT0 and TIOGT1 in the TRAIOC register.

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17.5.1 Timer RA I/O Cont rol Register (TRAIOC) in Event Counter Mode

Note: 1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined. Address 0101h B i t b 7b 6b 5b 4b 3b 2b 1 b 0 Symbol TIOGT1 TIOGT0 TIPF1 TIPF0 TIOSEL TOENA TOPCR TEDGSEL A f t e r R e s e t 0000000 0 Bit Symbol Bit Name Function R/W b0 TEDGSEL TRAIO polarity switch bit 0: Starts counting at rising edge of the TRAIO input and TRAO starts output at “L” 1: Starts counting at falling edge of the TRAIO input and TRAO starts output at “H” R/W b1 TOPCR TRAIO output control bit Set to 0 in event counter mode. R/W b2 TOENA TRAO output enable bit 0: Port P3_7 1: TRAO output R/W b3 TIOSEL Hardware LIN function select bit Set to 0. R/W b4 TIPF0 TRAIO input filter select bit (1) b5 b4 0 0: No filter 0 1: Filter with f1 sampling 1 0: Filter with f8 sampling 1 1: Filter with f32 sampling R/W b5 TIPF1 R/W b6 TIOGT0 TRAIO event input control bit b7 b6 0 0: Event input always enabled 0 1: Do not set. 1 0: Event enabled for “H” period of timer RC compare match signal 1 1: Do not set. R/W b7 TIOGT1 R/W

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17.6 Pulse Width Measurement Mode

In pulse width measurement mode, the pulse width of an external si gnal input to the TRAIO pin is measured (refer to Table 17.5 Pulse Width Measurement Mode Specifications). Figure 17.3 shows an Operating Example of Pulse Width Measurement Mode. Table 17.5 Pulse Width Measurement Mode Specifications Item Specification Count sources f1, f2, f8, fOCO, fC32 Count operations • Decrement

• Continuously counts the selected signal only when measurement pulse is “H” level, or conversely only “L” level.
• When the timer underflows, the contents of the reload register are reloaded and the count is continued. Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register. Count stop conditions • 0 (count stops) is writ ten to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register. Interrupt request generation timing
• When timer RA underflows [timer RA interrupt].
• Rising or falling of the TRAIO input (end of measurement period) [timer RA interrupt] TRAIO pin function Measured pulse input TRAO pin function Programmable I/O port Read from timer The count value can be read by reading registers TRA and TRAPRE. Write to timer • When registers TRAPRE and TR A are written while the count is stopped, values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are written to the reload register and counter (refer to 17.3.2 Timer Write Control during Count Operation). Selectable functions • Measurement level setting The “H” level or “L” level period is selected by the TEDGSEL bit in the TRAIOC register.
• Measured pulse input pin select function P1_5 or P1_7 is selected by bits TRAIOSEL0 to TRAIOSEL1 in the TRASR register.
• Digital filter function Whether enabling or disabling the digital filter and the sampling frequency is selected by bits TIPF0 and TIPF1 in the TRAIOC register.

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17.6.1 Timer RA I/O Control Register (TRAIOC) in Pulse Width Measurement

Note: 1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined. Address 0101h B i t b 7b 6b 5b 4b 3b 2b 1 b 0 Symbol TIOGT1 TIOGT0 TIPF1 TIPF0 TIOSEL TOENA TOPCR TEDGSEL A f t e r R e s e t 0000000 0 Bit Symbol Bit Name Function R/W b0 TEDGSEL TRAIO polarity switch bit 0: TRAIO input starts at “L” 1: TRAIO input starts at “H” R/W b1 TOPCR TRAIO output control bit Set to 0 in pulse width measurement mode. R/W b2 TOENA TRAO output enable bit R/W b3 TIOSEL Hardware LIN function select bit Set to 0. However, set to 1 when the hardware LIN function is used. R/W b4 TIPF0 TRAIO input filter select bit (1) b5 b4 0 0: No filter 0 1: Filter with f1 sampling 1 0: Filter with f8 sampling 1 1: Filter with f32 sampling R/W b5 TIPF1 R/W b6 TIOGT0 TRAIO event input control bit Set to 0 in pulse width measurement mode. R/W b7 TIOGT1 R/W

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17.6.2 Operating Example

Figure 17.3 Operating Example of Pulse Width Measurement Mode FFFFh n 0000h Content of counter (hex) n = high level: the contents of TRA register, low level: the contents of TRAPRE register Count start Count stop Underflow Period TSTART bit in TRACR register Measured pulse (TRAIO pin input) TEDGF bit in TRACR register TUNDF bit in TRACR register

• “H” level width of measured pulse is measured. (TEDGSEL = 1)
• TRAPRE = FFh Set to 1 by program IR bit in TRAIC register Set to 0 by program Count stop Count start Set to 0 when interrupt request is acknowledged, or set by program Count start Set to 0 by program The above applies under the following conditions.

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17.7 Pulse Period Measurement Mode

In pulse period measur ement mode, the pulse period of an external signal input to the TRAIO pin is measured (refer to Table 17.6 Pulse Period Measurement Mode Specifications). Figure 17.4 shows an Operating Example of Pulse Period Measurement Mode. Note: 1. Input a pulse with a period longer than twice th e timer RA prescaler period. Input a pulse with a longer “H” and “L” width than the timer RA prescaler period. If a pulse with a shorter period is input to the TRAIO pin, the input may be ignored. Table 17.6 Pulse Period Measurement Mode Specifications Item Specification Count sources f1, f2, f8, fOCO, fC32 Count operations • Decrement

• After the active edge of the measured pulse is input, the contents of the read- out buffer are retained at the first underflow of timer RA prescaler. Then timer RA reloads the contents in the reload register at the second underflow of timer RA prescaler and continues counting. Count start condition 1 (count starts) is writte n to the TSTART bit in the TRACR register. Count stop conditions • 0 (count stops) is wr itten to TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register. Interrupt request generation timing
• When timer RA underflows or reloads [timer RA interrupt].
• Rising or falling of the TRAIO input (end of measurement period) [timer RA interrupt] TRAIO pin function Measured pulse input (1) TRAO pin function Programmable I/O port Read from timer The count value can be read by reading registers TRA and TRAPRE. Write to timer • When registers TRAPRE and TRA are written while the count is stopped, values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are written to the reload register and counter (refer to 17.3.2 Timer Write Control during Count Operation). Selectable functions • Measurement period selection The measurement period of the input pulse is selected by the TEDGSEL in the TRAIOC register.
• Measured pulse input pin select function P1_5 or P1_7 is selected by bits TRAIOSEL0 to TRAIOSEL1 in the TRASR register.
• Digital filter function Whether enabling or disabling the digital filter and the sampling frequency is selected by bits TIPF0 and TIPF1 in the TRAIOC register.

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17.7.1 Timer RA I/O Control Register (T RAIOC) in Pulse Period Measurement

Note: 1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined. Address 0101h B i t b 7b 6b 5b 4b 3b 2b 1 b 0 Symbol TIOGT1 TIOGT0 TIPF1 TIPF0 TIOSEL TOENA TOPCR TEDGSEL A f t e r R e s e t 0000000 0 Bit Symbol Bit Name Function R/W b0 TEDGSEL TRAIO polarity switch bit 0: Meas ures measurement pulse from one rising edge to next rising edge 1: Measures measurement pulse from one falling edge to next falling edge R/W b1 TOPCR TRAIO output control bit Set to 0 in pulse period measurement mode. R/W b2 TOENA TRAO output enable bit R/W b3 TIOSEL Hardware LIN function select bit Set to 0. R/W b4 TIPF0 TRAIO input filter select bit (1) b5 b4 0 0: No filter 0 1: Filter with f1 sampling 1 0: Filter with f8 sampling 1 1: Filter with f32 sampling R/W b5 TIPF1 R/W b6 TIOGT0 TRAIO event input control bit Set to 0 in pulse period measurement mode. R/W b7 TIOGT1 R/W

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17.7.2 Operating Example

Figure 17.4 Operating Example of Pulse Period Measurement Mode Underflow signal of timer RA prescaler Notes: 1. The contents of the read-out buffer can be read by reading the TRA register in pulse period measurement mode. 2. After an active edge of the measured pulse is input, the TEDGF bit in the TRACR register is set to 1 (active edge received) when the timer RA prescaler underflows for the second time. 3. The TRA register should be read before the next active edge is input after the TEDGF bit is set to 1 (active edge received). The contents in the read-out buffer are retained until the TRA register is read. If the TRA register is not read before the next active edge is input, the measured result of the previous period is retained. 4. To set to 0 by a program, use a MOV instruction to write 0 to the TEDGF bit in the TRACR register. At the same time, write 1 to the TUNDF bit in the TRACR register. 5. To set to 0 by a program, use a MOV instruction to write 0 to the TUNDF bit. At the same time, write 1 to the TEDGF bit. 6. Bits TUNDF and TEDGF are both set to 1 if timer RA underflows and reloads on an active edge simultaneously. 0Eh 0Dh 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 0Fh 0Eh 0Dh 01h 00h 0Fh 0Eh0Fh 0Dh0Fh 0Bh 0Ah 0Dh 01h 00h 0Fh 0Eh09h TSTART bit in TRACR register TEDGF bit in TRACR register Measurement pulse (TRAIO pin input) Contents of TRA Contents of read-out buffer (1) IR bit in TRAIC register TUNDF bit in TRACR register Set to 1 by program Count start TRA reloaded TRA read (3) Retained Set to 0 by program Conditions: The period from one rising edge to the next rising edge of the measured pulse is measured (TEDGSEL = 0) with the default value of the TRA register as 0Fh. 0Eh TRA reloaded Retained Set to 0 when interrupt request is acknowledged, or set by program Set to 0 by program Underflow (Note 2) (Note 2) (Note 4) (Note 6) (Note 5)

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17.8 Notes on Timer RA

• Timer RA stops counting after a reset. Set the values in the timer RA and timer RA prescalers before the count starts.
• Even if the prescaler and timer RA are read out in 16-bit units, these register s are read 1 byte at a time by the MCU. Consequently, the timer value may be updated during the period when these two registers are being read.
• In pulse period measurement mode, bits TEDGF and TUNDF in the TRACR register can be set to 0 by writing 0 to these bits by a program. However, these bits re main unchanged if 1 is written. When using the READ- MODIFY-WRITE instruction for the TRACR register, the TEDGF or TUNDF bit may be set to 0 although these bits are set to 1 while the instruction is being executed. In this case, write 1 to the TEDGF or TUNDF bit which is not supposed to be set to 0 with the MOV instruction.
• When changing to pulse period measurement mode from another mode, the contents of bits TEDGF and TUNDF are undefined. Write 0 to bits TEDGF and TUNDF before the count starts.
• The TEDGF bit may be set to 1 by the first timer RA prescaler underflow generated after the count starts.
• When using the pulse period measurement mode, leave two or more periods of the timer RA prescaler immediately after the count starts, then set the TEDGF bit to 0.
• The TCSTF bit retains 0 (count stops) for 0 to 1 cycle of the count source after setting the TSTART bit to 1 (count starts) while the count is stopped. During this time, do not access regi sters associated with timer RA (1) other than the TCSTF bit. Timer RA starts counting at the first valid edge of the count source after The TCSTF bit is set to 1 (during count). The TCSTF bit remains 1 for 0 to 1 cycle of the count source after setting the TSTART bit to 0 (count stops) while the count is in progress. Timer RA counting is stopped when the TCSTF bit is set to 0. During this time, do not access registers associated with timer RA (1) other than the TCSTF bit. Note: 1. Registers associated with timer RA: TRACR, TRAIOC, TRAMR, TRAPRE, and TRA.
• When the TRAPRE register is continuously written during count operation (TCSTF bit is set to 1), allow three or more cycles of the count source clock for each write interval.
• When the TRA register is continuously written during count operation (TCSTF bit is set to 1), allow three or more cycles of the prescaler underflow for each write interval.

R8C/32A Group 18. Timer RB REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 201 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 18. Timer RB Timer RB is an 8-bit timer with an 8-bit prescaler.

18.1 Overview

The prescaler and timer each consist of a reload register and counter (refer to Tables 18.2 to 18.5 the Specifications of Each Mode). Timer RB has timer RB primary and timer RB secondary as reload registers. The count source for timer RB is the opera ting clock that regulates the timing of timer operations such as counting and reloading. Figure 18.1 shows a Timer RB Block Diagram. Table 18.1 lists Pin Configuration of Timer RB. Timer RB has four operation modes listed as follows:

• Timer mode: The timer counts an internal count source (peripheral function clock or timer RA underflows).
• Programmable waveform generation mode: The timer outputs pulses of a given width successively.
• Programmable one-shot generation mode: The timer outputs a one-shot pulse.
• Programmable wait one-shot generation mode: The timer outputs a delayed one-shot pulse. Figure 18.1 Timer RB Block Diagram Table 18.1 Pin Configuration of Timer RB Pin Name Assigned Pin I/O Function TRBO P1_3 Output Pulse output (Programmable waveform generation mode, Programmable one-shot generation mode, Programmable wait one- shot generation mode) INT0PL bit = 00b = 01b = 11b = 10bTimer RA underflow Bits TCK1 to TCK0 TSTART bit TRBPRE register (prescaler) Timer RB interrupt INT0 interrupt TCSTF bit Toggle flip-flop Q Q CLR CK TOPL = 1 TOPL = 0P1_3 bit in P1 register f2 TMOD1 to TMOD0 bits = 10b or 11b TOSSTF bit Polarity select INOSEG bit Input polarity selected to be one edge or both edges Digital filterINT0 pin INT0EN bit Bits TMOD1 to TMOD0 = 01b, 10b, 11b Counter Reload register Counter (timer RB) Reload register TRBPR register Data bus TRBSC register Reload register TCKCUT bit INOSTG bit TSTART, TCSTF: Bits in TRBCR register TOSSTF: Bit in TRBOCR register TOPL, TOCNT, INOSTG, INOSEG: Bits in TRBIOC register TMOD1 to TMOD0, TCK1 to TCK0, TCKCUT: Bits in TRBMR register (Timer) TOCNT = 0 TOCNT = 1 Bits TMOD1 to TMOD0 = 01b, 10b, 11b TRBO pin

R8C/32A Group 18. Timer RB REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 202 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

18.2 Registers

18.2.1 Timer RB Cont rol Register (TRBCR)

Notes: 1. Refer to 18.7 Notes on Timer RB for precautions regarding bits TSTART, TCSTF and TSTOP. 2. When the TSTOP bit is set to 1, registers TRBPRE, TRBSC, TRBPR, and bits TSTART and TCSTF, and the TOSSTF bit in the TRBOCR register are set to values after a reset. 3. Indicates that count operation is in progress in time r mode or programmable waveform mode. In programmable one-shot generation mode or programmable wait one-sh ot generation mode, indicates that a one-shot pulse trigger has been acknowledged.

18.2.2 Timer RB One-Shot Control Register (TRBOCR)

Note: 1. When 1 is set to the TSTO P bit in the TRBCR register, the TOSSTF bit is set to 0. This register is enabled when bits TMOD1 to TMOD0 in the TRBMR register is set to 10b (programmable one- shot generation mode) or 11b (programmable wait one-shot generation mode). Address 0108h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — — — TSTOP TCSTF TSTART A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TSTART Timer RB count start bit (1) 0: Count stops 1: Count starts R/W b1 TCSTF Timer RB count status flag (1) 0: Count stops 1: During count (3) R b2 TSTOP Timer RB count forcible stop bit (1, 2) When this bit is set to 1, the count is forcibly stopped. When read, the content is 0. R/W b3 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b4 — b5 — b6 — b7 — Address 0109h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — — — TOSSTF TOSSP TOSST A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TOSST Timer RB one-shot start bit When th is bit is set to 1, one-shot trigger generated. When read, its content is 0. R/W b1 TOSSP Timer RB one-shot stop bit When this bit is set to 1, counting of one-shot pulses (including programmable wait one-shot pulses) stops. When read, the content is 0. R/W b2 TOSSTF Timer RB one-shot status flag (1) 0: One-shot stopped 1: One-shot operating (Including wait period) R b3 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b4 — b5 — b6 — b7 —

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18.2.3 Timer RB I/O Cont rol Register (TRBIOC)

18.2.4 Timer RB Mode Register (TRBMR)

Notes: 1. Change bits TMOD1 and TMOD0; TCK1 and TCK0; and TCKCUT when both the TSTART and TCSTF bits in the TRBCR register set to 0 (count stops). 2. The TWRC bit can be set to either 0 or 1 in timer mode. In programmable waveform generation mode, programmable one-shot generation mode, or programmable wait one-shot generation mode, the TWRC bit must be set to 1 (write to reload register only). Address 010Ah B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — — INOSEG INOSTG TOCNT TOPL A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TOPL Timer RB output level select bit Function varies according to the operating mode. R/W b1 TOCNT Timer RB output switch bit R/W b2 INOSTG One-shot trigger control bit R/W b3 INOSEG One-shot trigger polarity select bit R/W b4 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b5 — b6 — b7 — Address 010Bh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TCKCUT — TCK1 TCK0 TWRC — TMOD1 TMOD0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TMOD0 Timer RB operating mode select bit (1) b1 b0 0 0: Timer mode 0 1: Programmable waveform generation mode 1 0: Programmable one-shot generation mode 1 1: Programmable wait one-shot generation mode R/W b1 TMOD1 R/W b2 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b3 TWRC Timer RB write control bit (2) 0: Write to reload register and counter 1: Write to reload register only R/W b4 TCK0 Timer RB count source select bit (1) b5 b4 0 0: f1 0 1: f8 1 0: Timer RA underflow 1 1: f2 R/W b5 TCK1 R/W b6 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b7 TCKCUT Timer RB count source cutoff bit (1) 0: Provides count source 1: Cuts off count source R/W

R8C/32A Group 18. Timer RB REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 204 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

18.2.5 Timer RB Prescal er Register (TRBPRE)

When the TSTOP bit in the TRBCR register is set to 1, the TRBPRE register is set to FFh.

18.2.6 Timer RB Seconda ry Register (TRBSC)

Notes: 1. The values of registers TRBPR and TRBSC are re loaded to the counter alternately and counted. 2. The count value can be read out by reading the TR BPR register even when the secondary period is being counted. When the TSTOP bit in the TRBCR register is set to 1, the TRBSC register is set to FFh. To write to the TRBSC register, perform the following steps. (1) Write the value to the TRBSC register. (2) Write the value to the TRBPR register. (If the valu e does not change, write the same value second time.) Address 010Ch B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 11111111 Bit Mode Function Setting Range R/W b7 to b0 Timer mode Counts an internal count source or timer RA underflows 00h to FFh R/W Programmable waveform generation mode 00h to FFh R/W Programmable one-shot generation mode 00h to FFh R/W Programmable wait one-shot generation mode 00h to FFh R/W Address 010Dh B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 11111111 Bit Mode Function Setting Range R/W b7 to b0 Timer mode Disabled 00h to FFh — Programmable waveform generation mode Counts timer RB prescaler underflows (1) 00h to FFh W (2) Programmable one-shot generation mode Disabled 00h to FFh — Programmable wait one-shot generation mode Counts timer RB prescaler underflows (one-shot width is counted) 00h to FFh W (2)

R8C/32A Group 18. Timer RB REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 205 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

18.2.7 Timer RB Primar y Register (TRBPR)

Note: 1. The values of registers TRBPR and TRBSC are re loaded to the counter alternately and counted. When the TSTOP bit in the TRBCR register is set to 1, the TRBPR register is set to FFh. Address 010Eh B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 11111111 Bit Mode Function Setting Range R/W b7 to b0 Timer mode Counts timer RB prescaler underflows 00h to FFh R/W Programmable waveform generation mode Counts timer RB prescaler underflows (1) 00h to FFh R/W Programmable one-shot generation mode Counts timer RB prescaler underflows (one-shot width is counted) 00h to FFh R/W Programmable wait one-shot generation mode Counts timer RB prescaler underflows (wait period width is counted) 00h to FFh R/W

R8C/32A Group 18. Timer RB REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 206 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

18.3 Timer Mode

In timer mode, a count source which is internally gene rated or timer RA underflows are counted (refer to Table 18.2 Timer Mode Specifications). Registers TRBOCR and TRBSC are not used in timer mode.

18.3.1 Timer RB I/O Control Regi ster (TRBIOC) in Timer Mode

Table 18.2 Timer M ode Specifications Item Specification Count sources f1, f2, f8, timer RA underflow Count operations • Decrement

• When the timer underflows, it reloads the reload register contents before the count continues (when timer RB underflows, the contents of timer RB primary reload register is reloaded). Divide ratio 1/(n+1)(m+1) n: setting value in TRBPRE register, m: setting value in TRBPR register Count start condition 1 (count starts) is writte n to the TSTART bit in the TRBCR register. Count stop conditions • 0 (count stops) is writt en to the TSTART bit in the TRBCR register.
• 1 (count forcibly stop) is written to the TSTOP bit in the TRBCR register. Interrupt request generation timing When timer RB underflows [timer RB interrupt]. TRBO pin function Programmable I/O port INT0 pin function Programmable I/O port or INT0 interrupt input Read from timer The count value can be read out by reading registers TRBPR and TRBPRE. Write to timer • When registers TRBPRE and TRBP R are written while the count is stopped, values are written to both the reload register and counter.
• When registers TRBPRE and TRBPR are written to while count operation is in progress: If the TWRC bit in the TRBMR register is set to 0, the value is written to both the reload register and the counter. If the TWRC bit is set to 1, the value is written to the reload register only. (Refer to 18.3.2 Timer Write Control during Count Operation.) Address 010Ah B i t b 7b 6b 5b 4b 3b 2b 1 b 0 S y m b o l ———— I N O S E G I N O S T G T O C N T T O P L A f t e r R e s e t 0000000 0 Bit Symbol Bit Name Function R/W b0 TOPL Timer RB output level select bit Set to 0 in timer mode. R/W b1 TOCNT Timer RB output switch bit R/W b2 INOSTG One-shot trigger control bit R/W b3 INOSEG One-shot trigger polarity select bit R/W b4 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b5 — b6 — b7 —

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18.3.2 Timer Write Contro l during Count Operation

Timer RB has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each consist of a reload register and a co unter. In timer mode, the TWRC bit in the TRBMR register can be used to select whether writing to the prescaler or timer during count operation is performed to both the reload register and counter or only to the reload register. However, values are transferred from the reload register to the counter of the prescaler in synchronization with the count source. In addition, values are transferred from the reload register to the counter of the timer in synchronization with prescaler underflows. Therefore, even if the TWRC bit is set for writing to both the reload register and counter, the counter va lue is not updated immediately after the WRITE instruction is executed. In addition, if the TWRC bit is set for writing to the reload register only, the synchronization of the writing will be shifted if the prescaler value changes. Figure 18.2 s hows an Operating Example of Timer RB when Counter Value is Rewritten during Count Operation.

R8C/32A Group 18. Timer RB REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 208 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 18.2 Operating Example of Timer RB when Counter Value is Rewritten during Count Operation Count source Reloads register of timer RB prescaler IR bit in TRBIC register 0 Counter of timer RB prescaler Reloads register of timer RB Counter of timer RB Set 01h to the TRBPRE register and 25h to the TRBPR register by a program. After writing, the reload register is written with the first count source. Reload with the second count source Reload on underflow After writing, the reload register is written on the first underflow. Reload on the second underflow The IR bit remains unchanged until underflow is generated by a new value. When the TWRC bit is set to 0 (write to reload register and counter) Count source Reloads register of timer RB prescaler IR bit in TRBIC register Counter of timer RB prescaler Reloads register of timer RB Counter of timer RB Set 01h to the TRBPRE register and 25h to the TRBPR register by a program. After writing, the reload register is written with the first count source. Reload on underflow After writing, the reload register is written on the first underflow. Reload on underflow Only the prescaler values are updated, extending the duration until timer RB underflow. When the TWRC bit is set to 1 (write to reload register only) 05h 04h 03h 02h 01h 00h 01h 00h 01h 00h06h 01h 00h 01h 03h 00h 02h 01h 25h New value (25h)Previous value New value (01h)Previous value New value (01h)Previous value 05h 04h 01h 00h 01h 00h 01h 00h 01h 00h06h New value (25h)Previous value 03h 24h 02h 25h The above applies under the following conditions. Both bits TSTART and TCSTF in the TRBCR register are set to 1 (During count).

R8C/32A Group 18. Timer RB REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 209 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

18.4 Programmable Waveform Generation Mode

In programmable waveform ge neration mode, the signal output from th e TRBO pin is inverted each time the counter underflows, while the values in registers TRBPR and TRBSC are counted alternately (refer to Table 18.3 Programmable Waveform Generation Mode Specifications). Counting starts by counting the setting value in the TRBPR register. The TRBOCR register is unused in this mode. Figure 18.3 shows an Operating Example of Timer RB in Programmable Waveform Generation Mode. Notes: 1. Even when counting the secondary period, the TRBPR register may be read. 2. The set values are reflected in the waveform output begi nning with the following primary period after writing to the TRBPR register. 3. The value written to the TOCNT bit is enabled by the following.

• When counting starts.
• When a timer RB interrupt request is generated. The contents after the TOCNT bit is changed are reflected from the output of the following primary period. Table 18.3 Programmable Waveform Generation Mode Specifications Item Specification Count sources f1, f2, f8, timer RA underflow Count operations • Decrement
• When the timer underflows, it reloads the contents of the primary reload and secondary reload registers alternately before the count continues. Width and period of output waveform Primary period: (n+1)(m+1)/fi Secondary period: (n+1)(p+1)/fi Period: (n+1){(m+1)+(p+1)}/fi fi: Count source frequency n: Value set in TRBPRE register m: Value set in TRBPR register p: Value set in TRBSC register Count start condition 1 (count start) is writ ten to the TSTART bit in the TRBCR register. Count stop conditions • 0 (count stop) is written to the TSTART bit in the TRBCR register.
• 1 (count forcibly stop) is written to the TSTOP bit in the TRBCR register. Interrupt request generation timing In half a cycle of the count source, after timer RB underflows during the secondary period (at the same time as the TRBO output change) [timer RB interrupt] TRBO pin function Programmable output port or pulse output INT0 pin function Programm able I/O port or INT0 interrupt input Read from timer The count value can be read out by reading registers TRBPR and TRBPRE (1). Write to timer • When registers TRBPRE, TRBSC, a nd TRBPR are written while the count is stopped, values are written to both the reload register and counter.
• When registers TRBPRE, TRBSC, and TRBPR are written to during count operation, values are written to the reload registers only. (2) Selectable functions • Output level select function The output level during primary and secondary periods is selected by the TOPL bit in the TRBIOC register.
• TRBO pin output switch function Timer RB pulse output or P1_3 latch output is selected by the TOCNT bit in the TRBIOC register. (3)

R8C/32A Group 18. Timer RB REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 210 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

18.4.1 Timer RB I/O Contro l Register (TRBIOC) in Programmable Waveform

B i t b 7b 6b 5b 4b 3b 2b 1 b 0 S y m b o l ———— I N O S E G I N O S T G T O C N T T O P L A f t e r R e s e t 0000000 0 Bit Symbol Bit Name Function R/W b0 TOPL Timer RB output level select bit 0: Outputs “H” for primary period Outputs “L” for secondary period Outputs “L” when the timer is stopped 1: Outputs “L” for primary period Outputs “H” for secondary period Outputs “H” when the timer is stopped R/W b1 TOCNT Timer RB output switch bit 0: Outputs timer RB waveform 1: Outputs value in P1_3 port register R/W b2 INOSTG One-shot trigger control bit Set to 0 in programmable waveform generation mode. R/W b3 INOSEG One-shot trigger polarity select bit R/W b4 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b5 — b6 — b7 —

R8C/32A Group 18. Timer RB REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 211 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

18.4.2 Operating Example

Figure 18.3 Operating Example of Timer RB in Programmable Waveform Generation Mode IR bit in TRBIC register Count source Timer RB prescaler underflow signal Counter of timer RB TRBO pin output TOPL bit in TRBIO register Set to 1 by program Set to 0 when interrupt request is acknowledged, or set by program. The above applies under the following conditions. TSTART bit in TRBCR register 01h 00h 02h Timer RB secondary reloads Timer RB primary reloads Set to 0 by program TRBPRE = 01h, TRBPR = 01h, TRBSC = 02h TRBIOC register TOCNT = 0 (timer RB waveform is output from the TRBO pin) 02h 01h 00h 01h 00h Primary period Primary period Secondary period Waveform output starts Waveform output inverted Waveform output starts Initial output is the same level as during secondary period.

R8C/32A Group 18. Timer RB REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 212 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

18.5 Programmable One-shot Generation Mode

In programmable one-shot generation mode, a one-shot pulse is output from the TRBO pin by a program or an external trigger input (input to the INT0 pin) (refer to Table 18.4 Programmable One-Shot Generation Mode Specifications). When a trigger is gene rated, the timer starts operating from the point only once for a given period equal to the set value in the TRBPR register. The TRBSC register is not used in this mode. Figure 18.4 shows an Operating Example of Programmable One-Shot Generation Mode. Note: 1. The set value is reflected at the following one- shot pulse after writing to the TRBPR register. Table 18.4 Programmable One-Shot Generation Mode Specifications Item Specification Count sources f1, f2, f8, timer RA underflow Count operations • Decrement the setting value in the TRBPR register

• When the timer underflows, it reloads the contents of the reload register before the count completes and the TOSSTF bit is set to 0 (one-shot stops).
• When the count stops, the timer reloads the contents of the reload register before it stops. One-shot pulse output time (n+1)(m+1)/fi fi: Count source frequency, n: Setting value in TRBPRE register, m: Setting value in TRBPR register Count start conditions • The TSTART bit in the TRBCR register is set to 1 (count starts) and the next trigger is generated
• Set the TOSST bit in the TRBOCR register to 1 (one-shot starts)
• Input trigger to the INT0 pin Count stop conditions • When reloading completes after timer RB underflows during primary period
• When the TOSSP bit in the TRBOCR register is set to 1 (one-shot stops)
• When the TSTART bit in the TRBCR register is set to 0 (stops counting)
• When the TSTOP bit in the TRBCR register is set to 1 (forcibly stops counting) Interrupt request generation timing In half a cycle of the count source, after the timer underflows (at the same time as the TRBO output ends) [timer RB interrupt] TRBO pin function Pulse output INT0 pin functions • When the INOSTG bit in the TRBIOC register is set to 0 (INT0 one-shot trigger disabled): programmable I/O port or INT0 interrupt input
• When the INOSTG bit in the TRBIOC register is set to 1 (INT0 one-shot trigger enabled): external trigger (INT0 interrupt input) Read from timer The count value can be re ad out by reading registers TRBPR and TRBPRE. Write to timer • When registers TRBPRE and TRBPR are written while the count is stopped, values are written to both the reload register and counter.
• When registers TRBPRE and TRBPR are written during the count, values are written to the reload register only (the data is transferred to the counter at the following reload) (1). Selectable functions • Output level select function The output level of the one-shot pulse waveform is selected by the TOPL bit in the TRBIOC register.
• One-shot trigger select function Refer to 18.5.3 One-Shot Trigger Selection.

R8C/32A Group 18. Timer RB REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 213 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

18.5.1 Timer RB I/O Contro l Register (TRBIOC) in Programmable One-Shot

Note: 1. Refer to 18.5.3 One-Shot Trigger Selection. Address 010Ah B i t b 7b 6b 5b 4b 3b 2b 1 b 0 S y m b o l ———— I N O S E G I N O S T G T O C N T T O P L A f t e r R e s e t 0000000 0 Bit Symbol Bit Name Function R/W b0 TOPL Timer RB output level select bit 0: Outputs one-shot pulse “H” Outputs “L” when the timer is stopped 1: Outputs one-shot pulse “L” Outputs “H” when the timer is stopped R/W b1 TOCNT Timer RB output switch bit Set to 0 in programmable one-shot generation mode. R/W b2 INOSTG One-shot trigger control bit (1) 0: INT0 pin one-shot trigger disabled 1: INT0 pin one-shot trigger enabled R/W b3 INOSEG One-shot trigger polarity select bit (1) 0: Falling edge trigger 1: Rising edge trigger R/W b4 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b5 — b6 — b7 —

R8C/32A Group 18. Timer RB REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 214 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

18.5.2 Operating Example

Figure 18.4 Operating Example of Progr ammable One-Shot Generation Mode TOSSTF bit in TRBOCR register INT0 pin input IR bit in TRBIC register Count source Timer RB prescaler underflow signal Counter of timer RB TRBIO pin output TOPL bit in TRBIOC register Set to 1 by program Set to 1 by program Set to 0 when interrupt request is acknowledged, or set by program The above applies under the following conditions. TSTART bit in TRBCR register 01h 00h 01h 00h 01h Count starts Timer RB primary reloads Count starts Timer RB primary reloads Set to 0 by program Waveform output starts Waveform output ends Waveform output starts Waveform output ends Set to 0 when counting ends Set to 1 by INT0 pin input trigger TRBPRE = 01h, TRBPR = 01h TRBIOC register TOPL = 0, TOCNT = 0 INOSTG = 1 (INT0 one-shot trigger enabled) INOSEG = 1 (edge trigger at rising edge)

R8C/32A Group 18. Timer RB REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 215 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

18.5.3 One-Shot Trigger Selection

In programmable one-shot generation mode and programmable wait one-shot generation mode, operation starts when a one-shot trigger is generated while the TCSTF bit in the TRBCR register is set to 1 (count starts). A one-shot trigger can be generated by either of the following causes:

• 1 is written to the TOSST bit in the TRBOCR register by a program.
• Trigger input from the INT0 pin. When a one-shot trigger occurs, the TOSSTF bit in the TRBOCR register is set to 1 (one-shot operation in progress) after one or two cycles of the count source have elapsed. Then, in programmable one-shot generation mode, count operation begins and one-shot waveform output starts. (In programmable wait one-shot generation mode, count operation starts for the wait period.) If a one- shot trigger occurs while the TOSSTF bit is set to 1, no retriggering occurs. To use trigger input from the INT0 pin, input the trigger after making the following settings:
• Set the PD4_5 bit in the PD4 register to 0 (input port).
• Select the INT0 digital filter with bits INT0F1 and INT0F0 in the INTF register.
• Select both edges or one edge with the INT0PL bit in INTEN register. If one edge is select ed, further select falling or rising edge with the INOSEG bit in TRBIOC register.
• Set the INT0EN bit in the INTEN register to 0 (enabled).
• After completing the above, set the INOSTG bit in the TRBIOC register to 1 (INT pin one-shot trigger enabled). Note the following points with regard to generating interrupt requests by trigger input from the INT0 pin.
• Processing to handle the interrupts is required. Refer to 11. Interrupts, for details.
• If one edge is selected, use the POL bit in the INT0IC register to select falling or rising edge. (The INOSEG bit in the TRBIOC register does not affect INT0 interrupts).
• If a one-shot trigger occurs while the TOSSTF bit is set to 1, timer RB operation is not affected, but the value of the IR bit in the INT0IC register changes.

R8C/32A Group 18. Timer RB REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 216 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

18.6 Programmable Wait One-Shot Generation Mode

In programmable wait one-shot generation mode, a one-shot pulse is output from the TRBO pin by a program or an external trigger input (input to the INT0 pin) (refer to Table 18.5 Programmable Wait One-Shot Generation Mode Specifications). When a trigger is generated from that point, the timer outputs a pulse only once for a given length of time equal to the setting value in the TRBSC register after waiting for a given length of time equal to the setting value in the TRBPR register. Figure 18.5 shows an Operating Example of Programmable Wait One-Shot Generation Mode. Note: 1. The set value is reflected at the following one-sho t pulse after writing to registers TRBSC and TRBPR. Table 18.5 Programmable Wait One-Shot Generation Mode Specifications Item Specification Count sources f1, f2, f8, timer RA underflow Count operations • Decrement the timer RB primary setting value.

• When a count of the timer RB primary underflows, the timer reloads the contents of timer RB secondary before the count continues.
• When a count of the timer RB secondary underflows, the timer reloads the contents of timer RB primary before the count completes and the TOSSTF bit is set to 0 (one-shot stops).
• When the count stops, the timer reloads the contents of the reload register before it stops. Wait time (n+1)(m+1)/fi fi: Count source frequency n: Value set in the TRBPRE register, m Value set in the TRBPR register One-shot pulse output time (n+1)(p+1)/fi fi: Count source frequency n: Value set in the TRBPRE register, p: Value set in the TRBSC register Count start conditions • The TSTART bit in the TRBCR regist er is set to 1 (count starts) and the next trigger is generated.
• Set the TOSST bit in the TRBOCR register to 1 (one-shot starts).
• Input trigger to the INT0 pin Count stop conditions • When reloading completes after timer RB underflows during secondary period.
• When the TOSSP bit in the TRBOCR register is set to 1 (one-shot stops).
• When the TSTART bit in the TRBCR register is set to 0 (starts counting).
• When the TSTOP bit in the TRBCR register is set to 1 (forcibly stops counting). Interrupt request generation timing In half a cycle of the count source after timer RB underflows during secondary period (complete at the same time as waveform output from the TRBO pin) [timer RB interrupt]. TRBO pin function Pulse output INT0 pin functions • When the INOSTG bit in the TRBIOC register is set to 0 (INT0 one-shot trigger disabled): programmable I/O port or INT0 interrupt input
• When the INOSTG bit in the TRBIOC register is set to 1 (INT0 one-shot trigger enabled): external trigger (INT0 interrupt input) Read from timer The count value can be re ad out by reading registers TRBPR and TRBPRE. Write to timer • When registers TRBPRE, TRBSC, and TRBPR are written while the count stops, values are written to both the reload register and counter.
• When registers TRBPRE, TRBSC, and TRBPR are written to during count operation, values are written to the reload registers only. (1) Selectable functions • Output level select function The output level of the one-shot pulse waveform is selected by the TOPL bit in the TRBIOC register.
• One-shot trigger select function Refer to 18.5.3 One-Shot Trigger Selection.

R8C/32A Group 18. Timer RB REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 217 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

18.6.1 Timer RB I/O Control Register (T RBIOC) in Programmable Wait One-Shot

Note: 1. Refer to 18.5.3 One-Shot Trigger Selection. Address 010Ah B i t b 7b 6b 5b 4b 3b 2b 1 b 0 S y m b o l ———— I N O S E G I N O S T G T O C N T T O P L A f t e r R e s e t 0000000 0 Bit Symbol Bit Name Function R/W b0 TOPL Timer RB output level select bit 0: Outputs one-shot pulse “H” Outputs “L” when the timer stops or during wait 1: Outputs one-shot pulse “L” Outputs “H” when the timer stops or during wait R/W b1 TOCNT Timer RB output switch bit Set to 0 in programmable wait one-shot generation mode. R/W b2 INOSTG One-shot trigger control bit (1) 0: INT0 pin one-shot trigger disabled 1: INT0 pin one-shot trigger enabled R/W b3 INOSEG One-shot trigger polarity select bit (1) 0: Falling edge trigger 1: Rising edge trigger R/W b4 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b5 — b6 — b7 —

R8C/32A Group 18. Timer RB REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 218 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

18.6.2 Operating Example

Figure 18.5 Operating Example of Programmable Wait One-Shot Generation Mode TOSSTF bit in TRBOCR register INT0 pin input IR bit in TRBIC register Count source Timer RB prescaler underflow signal Counter of timer RB TRBIO pin output TOPL bit in TRBIOC register Set to 1 by program Set to 1 by setting 1 to TOSST bit in TRBOCR register, or INT0 pin input trigger. Set to 0 when interrupt request is acknowledged, or set by program. The above applies under the following conditions. TSTART bit in TRBCR register 01h 00h 00h 01h Count starts Timer RB secondary reloads Timer RB primary reloads Set to 0 by program Wait starts Waveform output starts Waveform output ends Set to 0 when counting ends TRBPRE = 01h, TRBPR = 01h, TRBSC = 04h INOSTG = 1 (INT0 one-shot trigger enabled) INOSEG = 1 (edge trigger at rising edge) 04h 03h 02h 01h Wait (primary period) One-shot pulse (secondary period)

R8C/32A Group 18. Timer RB REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 219 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

18.7 Notes on Timer RB

• Timer RB stops counting after a reset. Set the values in the timer RB and timer RB prescalers before the count starts.
• Even if the prescaler and timer RB is read out in 16-bit units, these registers are read 1 byte at a time by the MCU. Consequently, the timer value may be updated during the period when these two registers are being read.
• In programmable one-shot generation mode and programma ble wait one-shot generation mode, when setting the TSTART bit in the TRBCR register to 0, 0 (stops counting) or setting the TOSSP bit in the TRBOCR register to 1 (stops one-shot), the timer reloads th e value of reload register and stops. Therefore, in programmable one-shot generation mode and programmable wait one-shot generation mode, read the timer count value before the timer stops.
• The TCSTF bit remains 0 (count stops) for 1 to 2 cycles of the count source after setting the TSTART bit to 1 (count starts) while the count is stopped. During this time, do not access registers associated with timer RB (1) other than the TCSTF bit. Timer RB starts counting at the first valid edge of the count source after the TCSTF bit is set to 1 (during count). The TCSTF bit remains 1 for 1 to 2 cycles of the count source after setting the TSTART bit to 0 (count stops) while the count is in progress. Timer RB counting is stopped when the TCSTF bit is set to 0. During this time, do not access registers associated with timer RB (1) other than the TCSTF bit. Note: 1. Registers associated with timer RB: TRBCR, TRBOCR, TRBIOC , TRBMR, TRBPRE, TRBSC, and TRBPR.
• If the TSTOP bit in the TRBCR register is set to 1 during timer operation, timer RB stops immediately.
• If 1 is written to the TOSST or TOSSP bit in the TRBO CR register, the value of the TOSSTF bit changes after one or two cycles of the count source have elapsed. If the TOSSP bit is written to 1 during the period between when the TOSST bit is written to 1 and when the TOSSTF bit is set to 1, the TOSSTF bit may be set to either 0 or 1 depending on the content state. Likewise, if the TOSST bit is written to 1 during the period between when the TOSSP bit is written to 1 and when the TOSSTF bit is set to 0, the TOSSTF bit may be set to either 0 or 1.

18.7.1 Timer Mode

To write to registers TRBPRE and TRBPR during count op eration (TCSTF bit in the TRBCR register is set to 1), note the following points:

• When the TRBPRE register is writte n continuously, allow three or more cycles of the count source for each write interval.
• When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for each write interval.

18.7.2 Programmable Waveform Generation Mode

To write to registers TRBPRE and TRBPR during count op eration (TCSTF bit in the TRBCR register is set to 1), note the following points:

• When the TRBPRE register is writte n continuously, allow three or more cycles of the count source for each write interval.
• When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for each write interval.

R8C/32A Group 18. Timer RB REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 220 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

18.7.3 Programmable One-shot Generation Mode

To write to registers TRBPRE and TRBPR during count op eration (TCSTF bit in the TRBCR register is set to 1), note the following points:

• When the TRBPRE register is written continuously during count operation (TCSTF bit is set to 1), allow three or more cycles of the count source for each write interval.
• When the TRBPR register is written continuously during count operation (TCSTF bit is set to 1), allow three or more cycles of the prescaler underflow for each write interval.

18.7.4 Programmable Wait One-shot Generation Mode

To write to registers TRBPRE and TRBPR during count op eration (TCSTF bit in the TRBCR register is set to 1), note the following points:

• When the TRBPRE register is writte n continuously, allow three or more cycles of the count source for each write interval.
• When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for each write interval.

R8C/32A Group 19. Timer RC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 221 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 19. Timer RC Timer RC is a 16-bit timer with four I/O pins.

19.1 Overview

Timer RC uses either f1, fOCO40M or fOCO-F as its ope ration clock. Table 19.1 lists the Timer RC Operation Clock. Table 19.2 lists the Pin Configuration of Timer RC, and Figure 19.1 shows a Timer RC Block Diagram. Timer RC has three modes.

• Timer mode - Input capture function The counter value is captured to a register, using an external signal as the trigger. - Output compare function Matches betw een the counter and register values are detected. (Pin output state changes when a match is detected.) The following two modes use the output compare function.
• PWM mode Pulses of a given width are output continuously.
• PWM2 mode A one-shot waveform or PWM waveform is output following the trigger after the wait time has elapsed. Input capture function, output compare function, and PWM mode settings may be specified independently for each pin. In PWM2 mode waveforms are output based on a combination of the counter or the register. Table 19.1 Timer RC Operation Clock Condition Timer RC Operation Clock Count source is f1, f2, f4, f8, f32, or TRCCLK input (bits TCK2 to TCK0 in TRCCR1 register are set to a value from 000b to 101b) Count source is fOCO40M (bits TCK2 to TCK0 in TRCCR1 register are set to 110b) fOCO40M Count source is fOCO-F (bits TCK2 to TCK0 in TRCCR1 register are set to 111b) fOCO-F

R8C/32A Group 19. Timer RC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 222 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 19.1 Timer RC Block Diagram Table 19.2 Pin Configuration of Timer RC Pin Name Assigned Pin I/O Function TRCIOA P1_1 I/O Function differs according to the mode. Refer to descriptions of individual modes for detailsTRCIOB P1_2 TRCIOC P1_3 or P3_4 TRCIOD P1_0 or P3_5 TRCCLK P1_4 or P3_3 Input External clock input TRCTRG P1_1 Input PWM2 mode external trigger input TRCMR register Data bus TRCCR1 register TRCIER register TRCSR register TRCIOR0 register TRC register TRCGRA register TRCGRB register TRCGRC register TRCGRD register TRCCR2 register TRCDF register TRCOER register Timer RC control circuit INT0 TRCCLKCount source select circuit f1, f2, f4, f8, f32, fOCO40M, fOCO-F Timer RC interrupt request TRCIOR1 register TRCIOB TRCIOC TRCIOD TRCIOA/TRCTRG TRCADCR register

R8C/32A Group 19. Timer RC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 223 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

19.2 Registers

Table 19.3 lists the Registers Associated with Timer RC. −: Invalid Table 19.3 Registers Associated with Timer RC Address Symbol Mode Related Information Timer PWM PWM2Input Capture Function Output Compare Function 0008h MSTCR Valid Valid Valid Valid 19.2.1 Module Standby Control Register (MSTCR) 0120h TRCMR Valid Valid Valid Valid 19.2.2 Timer RC Mode Register (TRCMR) 0121h TRCCR1 Valid Valid Valid Valid Timer RC control register 1

19.2.3 Timer RC Control Register 1 (TRCCR1)

19.5.1 Timer RC Control Register 1 (TRCCR1) for

19.6.1 Timer RC Control Register 1 (TRCCR1) in

19.7.1 Timer RC Control Register 1 (TRCCR1) in

0122h TRCIER Valid Valid Valid Valid 19.2.4 Time r RC Interrupt Enable Register (TRCIER) 0123h TRCSR Valid Valid Valid Valid 19.2.5 Timer RC Status Register (TRCSR) 0124h TRCIOR0 Valid Valid −− Timer RC I/O control register 0, timer RC I/O control register 1

19.2.6 Timer RC I/O Control Register 0 (TRCIOR0)

19.2.7 Timer RC I/O Control Register 1 (TRCIOR1)

19.4.1 Timer RC I/O Control Register 0 (TRCIOR0)

for Input Capture Function

19.4.2 Timer RC I/O Control Register 1 (TRCIOR1)

for Input Capture Function

19.5.2 Timer RC I/O Control Register 0 (TRCIOR0)

for Output Compare Function

19.5.3 Timer RC I/O Control Register 1 (TRCIOR1)

for Output Compare Function 0125h TRCIOR1 0126h 0127h TRC Valid Valid Valid Valid 19.2.8 Timer RC Counter (TRC) 0128h 0129h TRCGRA Valid Valid Valid Valid 19.2.9 Timer RC General Registers A, B, C, and D (TRCGRA, TRCGRB, TRCGRC, TRCGRD) 012Ah 012Bh TRCGRB 012Ch 012Dh TRCGRC 012Eh 012Fh TRCGRD 0130h TRCCR2 −− − Valid 19.2.10 Timer RC Control Register 2 (TRCCR2) 0131h TRCDF Valid −− Valid 19.2.11 Timer RC Digital Filter Function Select Register (TRCDF) 0132h TRCOER − Valid Valid Valid 19.2.12 Timer RC Output Master Enable Register (TRCOER) 0133h TRCADCR − Valid Valid Valid 19.2.13 Timer RC Trigger Control Register (TRCADCR) 0181h TRBRCSR Valid Valid Valid Valid 19.2.14 Timer RC Pin Select Register (TRBRCSR) 0182h TRCPSR0 Valid Valid Valid Valid 19.2.15 Timer RC Pin Select Register 0 (TRCPSR0) 0183h TRCPSR1 Valid Valid Valid Valid 19.2.16 Timer RC Pin Select Register 1 (TRCPSR1)

R8C/32A Group 19. Timer RC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 224 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

19.2.1 Module Standby Control Register (MSTCR)

Notes: 1. When the MSTIIC bit is set to 1 (standby), any access to the SSU or the I 2C bus associated registers (addresses 0193h to 019Dh) is disabled. 2. When the MSTTRC bit is set to 1 (standby), any acce ss to the timer RC associated registers (addresses 0120h to 0133h) is disabled.

19.2.2 Timer RC Mode Register (TRCMR)

Notes: 1. These bits are enabled when the PWM2 bit is set to 1 (timer mode or PWM mode). 2. Set the BFC bit to 0 (general register) in PWM2 mode. For notes on PWM2 mode, refer to 19.9.6 TRCMR Register in PWM2 Mode. Address 0008h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — MSTTRC MSTTRD MSTIIC — — — A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b1 — b2 — b3 MSTIIC SSU, I 2C bus standby bit 0: Active 1: Standby (1) R/W b4 MSTTRD Peripheral function power consumption reduce bit Set to 1. The power consumption of the peripheral functions can be reduced. R/W b5 MSTTRC Timer RC standby bit 0: Active 1: Standby (2) R/W b6 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b7 — Address 0120h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TSTART — BFD BFC PWM2 PWMD PWMC PWMB A f t e r R e s e t 01001000 Bit Symbol Bit Name Function R/W b0 PWMB PWM mode of TRCIOB select bit (1) 0: Timer mode 1: PWM mode R/W b1 PWMC PWM mode of TRCIOC select bit (1) 0: Timer mode 1: PWM mode R/W b2 PWMD PWM mode of TRCIOD select bit (1) 0: Timer mode 1: PWM mode R/W b3 PWM2 PWM2 mode select bit 0: PWM 2 mode 1: Timer mode or PWM mode R/W b4 BFC TRCGRC register function select bit (2) 0: General register 1: Buffer register of TRCGRA register R/W b5 BFD TRCGRD register function se lect bit 0: General register 1: Buffer register of TRCGRB register R/W b6 — Nothing is assigned. If necessary, se t to 0. When read, the content is 1. — b7 TSTART TRC count start bit 0: Count stops 1: Count starts R/W

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19.2.3 Timer RC Contro l Register 1 (TRCCR1)

Note: 1. Set to these bits when the TSTART bit in th e TRCMR register is set to 0 (count stops). 2. To select fOCO-F, set it to the clock frequency higher than the CPU clock frequency.

19.2.4 Timer RC Interrupt Enable Register (TRCIER)

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol CCLR TCK2 TCK1 TCK0 TOD TOC TOB TOA A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TOA TRCIOA output level select bit (1) Function varies according to the operating mode (function). R/W b1 TOB TRCIOB output level select bit (1) R/W b2 TOC TRCIOC output level select bit (1) R/W b3 TOD TRCIOD output level select bit (1) R/W b4 TCK0 Count source select bit (1) b6 b5 b4 0 0 0: f1 0 0 1: f2 0 1 0: f4 0 1 1: f8 1 0 0: f32 1 0 1: TRCCLK input rising edge 1 1 0: fOCO40M 1 1 1: fOCO-F (2) R/W b5 TCK1 R/W b6 TCK2 R/W b7 CCLR TRC counter clear select bit 0: Disable clear (free-running operation) 1: Clear TRC counter by input capture or by compare match in TRCGRA R/W Address 0122h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol OVIE — — — IMIED IMIEC IMIEB IMIEA A f t e r R e s e t 01110000 Bit Symbol Bit Name Function R/W b0 IMIEA Input capture / compare match interrupt enable bit A 0: Disable interrupt (IMIA) by the IMFA bit 1: Enable interrupt (IMIA) by the IMFA bit R/W b1 IMIEB Input capture / compare match interrupt enable bit B 0: Disable interrupt (IMIB) by the IMFB bit 1: Enable interrupt (IMIB) by the IMFB bit R/W b2 IMIEC Input capture / compare match interrupt enable bit C 0: Disable interrupt (IMIC) by the IMFC bit 1: Enable interrupt (IMIC) by the IMFC bit R/W b3 IMIED Input capture / compare match interrupt enable bit D 0: Disable interrupt (IMID) by the IMFD bit 1: Enable interrupt (IMID) by the IMFD bit R/W b4 — Nothing is assigned. If necessary, se t to 0. When read, the content is 1. — b5 — b6 — b7 OVIE Overflow interrupt enable bit 0: Dis able interrupt (OVI) by the OVF bit 1: Enable interrupt (OVI) by the OVF bit R/W

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19.2.5 Timer RC Status Register (TRCSR)

Note: 1. The writing results are as follows:

• This bit is set to 0 when the read result is 1 and 0 is written to the same bit.
• This bit remains unchanged even if the read result is 0 and 0 is written to the same bit. (This bit remains 1 even if it is set to 1 from 0 after reading, and writing 0.)
• This bit remains unchanged if 1 is written to it. Notes: 1. Edge selected by bits IOj1 to IOj0 (j = A, B, C, or D). 2. Includes the condition that bits BFC and BFD are set to 1 (buffer registers of registers TRCGRA and TRCGRB). Address 0123h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol OVF — — — IMFD IMFC IMFB IMFA A f t e r R e s e t 01110000 Bit Symbol Bit Name Function R/W b0 IMFA Input capture / compare match flag A [Source for setting this bit to 0] Write 0 after read (1). [Source for setting this bit to 1] Refer to Table 19.4 Source for Setting Bit of Each Flag to 1. R/W b1 IMFB Input capture / co mpare match flag B R/W b2 IMFC Input capture / co mpare match flag C R/W b3 IMFD Input capture / co mpare match flag D R/W b4 — Nothing is assigned. If necessary, se t to 0. When read, the content is 1. — b5 — b6 — b7 OVF Overflow flag [Source for setting this bit to 0] Write 0 after read (1). [Source for setting this bit to 1] Refer to Table 19.4 Source for Setting Bit of Each Flag to 1. R/W Table 19.4 Source for Setting Bit of Each Flag to 1 Bit Symbol Timer Mode PWM Mode PWM2 ModeInput capture Function Output Compare Function IMFA TRCIOA pin input edge (1) When the values of the registers TRC and TRCGRA match. IMFB TRCIOB pin input edge (1) When the values of the registers TRC and TRCGRB match. IMFC TRCIOC pin input edge (1) When the values of the registers TRC and TRCGRC match. (2) IMFD TRCIOD pin input edge (1) When the values of the registers TRC and TRCGRD match. (2) OVF When the TRC register overflows.

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19.2.6 Timer RC I/O Cont rol Register 0 (TRCIOR0)

Notes: 1. When the BFC bit in the TRCMR register is set to 1 (buffe r register of TRCGRA register), set the IOC2 bit in the TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register. 2. When the BFD bit in the TRCMR register is set to 1 (buffe r register of TRCGRB register), set the IOD2 bit in the TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register. 3. The IOA3 bit is enabled when the IOA2 bit is set to 1 (input capture function). The TRCIOR0 register is enabled in timer mode. It is disabled in modes PWM and PWM2.

19.2.7 Timer RC I/O Cont rol Register 1 (TRCIOR1)

Notes: 1. When the BFC bit in the TRCMR register is set to 1 (buffe r register of TRCGRA register), set the IOC2 bit in the TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register. 2. When the BFD bit in the TRCMR register is set to 1 (buffe r register of TRCGRB register), set the IOD2 bit in the TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register. The TRCIOR1 register is enabled in timer mode. It is disabled in modes PWM and PWM2. Address 0124h B i t b 7b 6b 5b 4b 3b 2b 1b 0 S y m b o l — I O B 2I O B 1I O B 0I O A 3I O A 2I O A 1I O A 0 A f t e r R e s e t 10001000 Bit Symbol Bit Name Function R/W b0 IOA0 TRCGRA control bit Function varies according to the operating mode (function). R/W b1 IOA1 R/W b2 IOA2 TRCGRA mode select bit (1) 0: Output compare function 1: Input capture function R/W b3 IOA3 TRCGRA input capture input switch bit (3) 0: fOCO128 signal 1: TRCIOA pin input R/W b4 IOB0 TRCGRB control bit Function varies according to the operating mode (function). R/W b5 IOB1 R/W b6 IOB2 TRCGRB mode select bit (2) 0: Output compare function 1: Input capture function R/W b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — Address 0125h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 A f t e r R e s e t 10001000 Bit Symbol Bit Name Function R/W b0 IOC0 TRCGRC control bit Function varies according to the operating mode (function). R/W b1 IOC1 R/W b2 IOC2 TRCGRC mode select bit (1) 0: Output compare function 1: Input capture function R/W b3 IOC3 TRCGRC register function sele ct bit 0: TRCIOA output register 1: General register or buffer register R/W b4 IOD0 TRCGRD control bit Function varies according to the operating mode (function). R/W b5 IOD1 R/W b6 IOD2 TRCGRD mode select bit (2) 0: Output compare function 1: Input capture function R/W b7 IOD3 TRCGRD register function sele ct bit 0: TRCIOB output register 1: General register or buffer register R/W

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19.2.8 Timer RC Counter (TRC)

Access the TRC register in 16-bit units. Do not access it in 8-bit units.

19.2.9 Timer RC General Registers A, B, C, and D (TRCGRA, TRCGRB, TRCGRC,

TRCGRD) Access registers TRCGRA to TRCGRD in 16-bit units. Do not access them in 8-bit units. Address 0127h to 0126h B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00000000 Bit b15 b14 b13 b12 b11 b10 b9 b8 A f t e r R e s e t 00000000 Bit Function Setting Range R/W b15 to b0 Count a count source. Count operation is incremented. When an overflow occurs, the OVF bit in the TRCSR register is set to 1. 0000h to FFFFh R/W Address 0129h to 0128h (TRCGRA), 012Bh to 012Ah (TRCGRB), 012Dh to 012Ch (TRCGRC), 012Fh to 012Eh (TRCGRD) B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 11111111 Bit b15 b14 b13 b12 b11 b10 b9 b8 A f t e r R e s e t 11111111 Bit Function R/W b15 to b0 Function varies according to the operating mode. R/W

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19.2.10 Timer RC Contro l Register 2 (TRCCR2)

Notes: 1. Enabled when in PWM mode. 2. For notes on PWM2 mode, refer to 19.9.6 TRCMR Register in PWM2 Mode. 3. In timer mode and PWM mode these bits are disabled.

19.2.11 Timer RC Digital Filter Function Select Register (TRCDF)

Notes: 1. These bits are enabled for the input capture function. 2. These bits are enabled when in PWM2 mode and bits TCEG1 to TCEG0 in the TRCCR2 register are set to 01b, 10b, or 11b (TRCTRG trigger input enabled). Address 0130h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TCEG1 TCEG0 CSTP — — POLD POLC POLB A f t e r R e s e t 00011000 Bit Symbol Bit Name Function R/W b0 POLB PWM mode output level control bit B (1) 0: TRCIOB output level selected as “L” active 1: TRCIOB output level selected as “H” active R/W b1 POLC PWM mode output level control bit C (1) 0: TRCIOC output level selected as “L” active 1: TRCIOC output level selected as “H” active R/W b2 POLD PWM mode output level control bit D (1) 0: TRCIOD output level selected as “L” active 1: TRCIOD output level selected as “H” active R/W b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b4 — b5 CSTP TRC count operation select bit (2) 0: Count continues at compare match with the TRCGRA register 1: Count stops at compare match with the TRCGRA register R/W b6 TCEG0 TRCTRG input edge select bit (3) b7 b6 0 0: Disable the trigger input from the TRCTRG pin 0 1: Rising edge selected 1 0: Falling edge selected 1 1: Both edges selected R/W b7 TCEG1 R/W Address 0131h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol DFCK1 DFCK0 — DFTRG DFD DFC DFB DFA A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 DFA TRCIOA pin digital filter function select bit (1) 0: Function is not used 1: Function is used R/W b1 DFB TRCIOB pin digital filter function select bit (1) R/W b2 DFC TRCIOC pin digital filter function select bit (1) R/W b3 DFD TRCIOD pin digital filter function select bit (1) R/W b4 DFTRG TRCTRG pin digital filter function select bit (2) R/W b5 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b6 DFCK0 Clock select bits for digital filter function (1, 2) b7 b6 0 0: f32 0 1: f8 1 0: f1 1 1: Count source (clock selected by bits TCK2 to TCK0 in the TRCCR1 register) R/W b7 DFCK1 R/W

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19.2.12 Timer RC Output Master Enable Register (TRCOER)

Note: 1. These bits are disabled for input pins set to the input capture function.

19.2.13 Timer RC Trigger C ontrol Register (TRCADCR)

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol PTO — — — ED EC EB EA A f t e r R e s e t 01111111 Bit Symbol Bit Name Function R/W b0 EA TRCIOA output disable bit (1) 0: Enable output 1: Disable output (The TRCIOA pin is used as a programmable I/O port.) R/W b1 EB TRCIOB output disable bit (1) 0: Enable output 1: Disable output (The TRCIOB pin is used as a programmable I/O port.) R/W b2 EC TRCIOC output disable bit (1) 0: Enable output 1: Disable output (The TRCIOC pin is used as a programmable I/O port.) R/W b3 ED TRCIOD output disable bit (1) 0: Enable output 1: Disable output (The TRCIOD pin is used as a programmable I/O port.) R/W b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b5 — b6 — b7 PTO INT0 of pulse output forced cutoff signal input enabled bit 0: Pulse output forced cutoff input disabled 1: Pulse output forced cutoff input enabled (Bits EA, EB, EC, and ED are set to 1 (disable output) when “L” is applied to the INT0 pin) R/W Address 0133h B i t b 7b 6b 5b 4 b 3 b 2 b 1 b 0 Symbol — — — — ADTRGDE ADTRGCE ADTRGBE ADTRGAE A f t e r R e s e t 0000 0 0 0 0 Bit Symbol Bit Name Function R/W b0 ADTRGAE A/D trigger A enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRC and TRCGRA R/W b1 ADTRGBE A/D trigger B enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRC and TRCGRB R/W b2 ADTRGCE A/D trigger C enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRC and TRCGRC R/W b3 ADTRGDE A/D trigger D enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRC and TRCGRD R/W b4 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b5 — b6 — b7 —

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19.2.14 Timer RC Pin Sel ect Register (TRBRCSR)

The TRBRCSR register selects which pi n is assigned to the timer RC I/O. To use the I/O pin for timer RC, set this register. Set bits TRCCLKSEL0 and TRCCLKSEL1 before setting the timer RC associated registers. Also, do not change the setting values of bits TRCCLKSEL0 and TRCCLKSEL1 during timer RC operation. Address 0181h B i t b 7b 6 b 5 b 4 b 3b 2b 1b 0 Symbol — — TRCCLKSEL1 TRCCLKSEL0 — — — — A f t e r R e s e t 0 00 00 0 0 0 Bit Symbol Bit Name Function R/W b0 — Reserved bits Set to 0. R/W b1 — b2 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b3 — b4 TRCCLKSEL0 TRCCLK pin select bit b5 b4 0 0: TRCCLK pin not used 0 1: P1_4 assigned 1 0: P3_3 assigned 1 1: Do not set. R/W b5 TRCCLKSEL1 R/W b6 — Reserved bit Set to 0. R/W b7 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. —

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19.2.15 Timer RC Pin Select Register 0 (TRCPSR0)

The TRCPSR0 register selects which pin is assigned to the timer RC I/O. To use the I/O pin for timer RC, set this register. Set the TRCPSR0 register before setting the timer RC associated registers. Also, do not change the setting value in this register during timer RC operation.

19.2.16 Timer RC Pin Select Register 1 (TRCPSR1)

The TRCPSR1 register selects which pin is assigned to the timer RC I/O. To use the I/O pin for timer RC, set this register. Set the TRCPSR1 register before setting the timer RC associated registers. Also, do not change the setting value in this register during timer RC operation. Address 0182h B i t b 7b 6b 5 b 4 b 3b 2b 1 b 0 Symbol — — — TRCIOBSEL0 — — — TRCIOASEL0 A f t e r R e s e t 000 0 000 0 Bit Symbol Bit Name Function R/W b0 TRCIOASEL0 TRCIOA/TRCTRG pin select bit 0: TRCIOA/TRCTRG pin not used 1: P1_1 assigned R/W b1 — Reserved bits Set to 0. R/W b2 — b3 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b4 TRCIOBSEL0 TRCIOB pin select bit 0: TRCIOB pin not used 1: P1_2 assigned R/W b5 — Reserved bits Set to 0. R/W b6 — b7 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — Address 0183h B i t b 7b 6 b 5 b 4 b 3b 2 b 1 b 0 Symbol — — TRCIODSEL1 TRCIODSEL0 — — TRCIOCSEL1 TRCIOCSEL0 A f t e r R e s e t 0 00 00 00 0 Bit Symbol Bit Name Function R/W b0 TRCIOCSEL0 TRCIOC pin select bit b1 b0 0 0: TRCIOC pin not used 0 1: P1_3 assigned 1 0: P3_4 assigned 1 1: Do not set. R/W b1 TRCIOCSEL1 R/W b2 — Reserved bit Set to 0. R/W b3 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b4 TRCIODSEL0 TRCIOD pin select bit b5 b4 0 0: TRCIOD pin not used 0 1: P1_0 assigned 1 0: P3_5 assigned 1 1: Do not set. R/W b5 TRCIODSEL1 R/W b6 — Reserved bit Set to 0. R/W b7 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. —

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19.3 Common Items for Multiple Modes

19.3.1 Count Source

The method of selecting the count source is common to all modes. Table 19.5 lists the Count Source Selection, and Figure 19.2 shows a Count Source Block Diagram. Figure 19.2 Count Source Block Diagram The pulse width of the external clock input to the TRCCLK pin should be three cycles or more of the timer RC operation clock (see Table 19.1 Timer RC Operation Clock). To select fOCO40M or fOCO-F as the count source, set the FRA00 bit in the FRA0 register set to 1 (high-speed on-chip oscillator on), and then set bits TCK2 to TC K0 in the TRCCR1 register to 110b (fOCO40M) or 111b (fOCO-F). Table 19.5 Count Source Selection Count Source Selection Method f1, f2, f4, f8, f32 Count source selected using bits TCK2 to TCK0 in TRCCR1 register fOCO40M fOCO-F FRA00 bit in FRA0 register set to 1 (high-speed on-chip oscillator on) Bits TCK2 to TCK0 in TRCCR1 register are set to 110b (fOCO40M) Bits TCK2 to TCK0 in TRCCR1 register are set to 111b (fOCO-F) External signal input to TRCCLK pin Bits TCK2 to TCK0 in TRCCR1 register are set to 101b (count source is rising edge of external clock) and the corresponding direction bit in the corresponding direction register is set is set to 0 (input mode) TCK2 to TCK0 TRC register TCK2 to TCK0: Bits in TRCCR1 register f32 = 001b = 010b = 011b = 000b = 110b = 100b Count source TRCCLK = 101b fOCO40M = 111bfOCO-F

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19.3.2 Buffer Operation

Bits BFC and BFD in the TRCMR regist er are used to select the TRCGRC or TRCGRD register as the buffer register for the TRCGRA or TRCGRB register.

• Buffer register for TRCGRA register: TRCGRC register
• Buffer register for TRCGRB register: TRCGRD register Buffer operation differs depending on the mode. Table 19.6 lists the Buffer Operation in Each Mode, Figure 19.3 shows the Buffer Operation for Input Capture Function, and Figure 19.4 shows the Buffer Operation for Output Compare Function. Figure 19.3 Buffer Operation for Input Capture Function Table 19.6 Buffer Operation in Each Mode Function, Mode Transfer Timing Transfer Destination Register Input capture function Input capture signal input Contents of TRCGRA (TRCGRB) register are transferred to buffer register Output compare function Co mpare match between TRC register and TRCGRA (TRCGRB) register Contents of buffer register are transferred to TRCGRA (TRCGRB) registerPWM mode PWM2 mode • Compare match between TRC register and TRCGRA register
• TRCTRG pin trigger input Contents of buffer register (TRCGRD) are transferred to TRCGRB register m Transfer n n-1 n+1 TRCIOA input TRC register The above applies under the following conditions:
• The BFC bit in the TRCMR register is set to 1 (the TRCGRC register functions as the buffer register for the TRCGRA register).
• Bits IOA2 to IOA0 in the TRCIOR0 register are set to 100b (input capture at the rising edge). m Transfer n TRCGRC register TRCGRA register TRC TRCIOA input (input capture signal) TRCGRA register TRCGRC register (buffer)

R8C/32A Group 19. Timer RC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 235 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 19.4 Buffer Operation for Output Compare Function Make the following settings in timer mode.

• To use the TRCGRC register as the buffer register for the TRCGRA register: Set the IOC2 bit in the TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.
• To use the TRCGRD register as the buffer register for the TRCGRB register: Set the IOD2 bit in the TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register. The output compare function, PWM mode, or PWM2 mode, and the TRCGRC or TRCGRD register is functioning as a buffer register, the IMFC bit or IMFD bit in the TRCSR register is set to 1 when a compare match with the TRC register occurs. The input capture function and the TRCGRC register or TRCGRD register is functioning as a buffer register, the IMFC bit or IMFD bit in the TRCSR register is set to 1 at the input edge of a signal input to the TRCIOC pin or TRCIOD pin. mnTRCGRA register m-1 m+1TRC register The above applies under the following conditions:
• The BFC bit in the TRCMR register is set to 1 (the TRCGRC register functions as the buffer register for the TRCGRA register).
• Bits IOA2 to IOA0 in the TRCIOR0 register are set to 001b (“L” output at compare match). n Transfer TRCGRC register (buffer) m TRCIOA output TRCGRC register TRCGRA register Comparator TRC Compare match signal

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19.3.3 Digital Filter

The input to TRCTRG or TRCIOj (j = A, B, C, or D) is sampled, and the level is considered to be determined when three matches occur. The digital filter function and sampling clock are selected using the TRCDF register. Figure 19.5 shows a Digital Filter Block Diagram. Figure 19.5 Digital Filter Block Diagram C DQ Latch C DQ Latch C DQ Latch Match detect circuit Edge detect circuit DFj (or DFTRG) Sampling clock IOA2 to IOA0 IOB2 to IOB0 IOC2 to IOC0 IOD2 to IOD0 (or TCEG1 to TCEG0) DFCK1 to DFCK0 TRCIOj input signal (or TRCTRG input signal) Clock cycle selected by TCK2 to TCK0 (or DFCK1 to DFCK0) Sampling clock TRCIOj input signal (or TRCTRG input signal) Input signal after passing through digital filter If fewer than three matches occur, the matches are treated as noise and no transmission is performed. Maximum signal transmission delay is five sampling clock pulses. Three matches occur and a signal change is confirmed. f32 j = A, B, C, or D TCK0 to TCK2: Bits in TRCCR1 register DFTRG, DFCK0 to DFCK1, DFj: Bits in TRCDF register IOA0 to IOA2, IOB0 to IOB2: Bits in TRCIOR0 register IOC0 to IOC2, IOD0 to IOD2: Bits in TRCIOR1 register TCEG1 to TCEG0: Bits in TRCCR2 register C DQ Latch C DQ Latch Timer RC operation clock f1 or fOCO40M Count source = 00b = 01b = 10b = 11b TCK2 to TCK0 = 001b = 010b = 011b = 000b = 100b = 101b f32 TRCCLK fOCO40M = 110b fOCO-F = 111b

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19.3.4 Forced Cutoff of Pulse Output

When using the timer mode’s output compare function, the PWM mode, or the PWM2 mode, pulse output from the TRCIOj (j = A, B, C, or D) output pin can be fo rcibly cut off and the TRCIOj pin set to function as a programmable I/O port by means of input to the INT0 pin. A pin used for output by the timer mode’s output compare function, the PWM mode, or the PWM2 mode can be set to function as the timer RC output pin by setting the Ej bit in the TRCOER register to 0 (timer RC output enabled). If “L” is input to the INT0 pin while the PTO bit in the TRCOER register is set to 1 (pulse output forced cutoff signal input INT0 enabled), bits EA, EB, EC , and ED in the TRCOER re gister are all set to 1 (timer RC output disabled, TRCIOj output pin functions as the programmable I/ O port). When one or two cycles of the timer RC operation clock after “L” input to the INT0 pin (refer to Table 19.1 Timer RC Operation Clock) has elapsed, the TRCIOj output pin becomes a programmable I/O port. Make the following settings to use this function.

• Set the pin state following forced cutoff of pulse output (high impedance (input), “L” output, or “H” output). (Refer to 7. I/O Ports.)
• Set the INT0EN bit to 1 (INT0 input enabled) and the INT0PL bit to 0 (one edge) in the INTEN register.
• Set the PD4_5 bit in the PD4 register to 0 (input mode).
• Select the INT0 digital filter by means of bits INT0F1 to INT0F0 in the INTF register.
• Set the PTO bit in the TRCOER register to 1 (pulse output forced cutoff signal input INT0 enabled). The IR bit in the INT0IC register is set to 1 (interrupt request) in accordance with the setting of the POL bit and a change in the INT0 pin input (refer to 11.8 Notes on Interrupts). For details on interrupts, refer to 11. Interrupts.

R8C/32A Group 19. Timer RC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 238 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 19.6 Forced Cutoff of Pulse Output INT0 input TRCIOA PTO bit D S Q EA bitEA bit write value TRCIOB D S Q EB bitEB bit write value TRCIOC D S Q EC bitEC bit write value TRCIOD D S Q ED bitED bit write value EA, EB, EC, ED, PTO: Bits in TRCOER register Timer RC output data Port P1_1 output data Port P1_1 input data Timer RC output data Port P1_2 output data Port P1_2 input data Timer RC output data Port P3_4 output data Port P3_4 input data Timer RC output data Port P3_5 output data Port P3_5 input data

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19.4 Timer Mode (I nput Capture Function)

This function measures the width or period of an external si gnal. An external signal input to the TRCIOj (j = A, B, C, or D) pin acts as a trigger for tr ansferring the contents of the TRC regi ster (counter) to the TRCGRj register (input capture). The input capture function, or any other mode or function, can be selected for each individual pin. The TRCGRA register can also select fOCO128 signal as input-capture trigger input. Table 19.7 lists the Specifications of Input Capture Function, Figure 19.7 shows a Block Diagram of Input Capture Function, Table 19.8 lists the Functions of TRCGRj Register when Using Input Capture Function, and Figure 19.8 shows an Operating Example of Input Capture Function. j = A, B, C, or D Table 19.7 Specifications of Input Capture Function Item Specification Count source f1, f2, f4, f8, f32, fOCO40M, fOCO-F, or external signal (rising edge) input to TRCCLK pin Count operation Increment Count period 1/fk × 65,536 fk: Count source frequency Count start condition 1 (count starts) is written to the TSTART bit in the TRCMR register. Count stop condition 0 (count stops) is writte n to the TSTART bit in the TRCMR register. The TRC register retains a value before count stops. Interrupt request generation timing

• Input capture (valid edge of TRCIOj input or fOCO128 signal edge)
• The TRC register overflows. TRCIOA, TRCIOB, TRCIOC, and TRCIOD pin functions Programmable I/O port or input capture input (selectable individually for each pin) INT0 pin function Programmable I/O port or INT0 interrupt input Read from timer The count value can be read by reading TRC register. Write to timer The TRC register can be written to. Select functions • Input capture input pin selection One or more of pins TRCIOA, TRCIOB, TRCIOC, and TRCIOD
• Input capture input valid edge selection Rising edge, falling edge, or both rising and falling edges
• Buffer operation (Refer to 19.3.2 Buffer Operation.)
• Digital filter (Refer to 19.3.3 Digital Filter.)
• Timing for setting the TRC register to 0000h Overflow or input capture
• Input-capture trigger selected fOCO128 can be selected for input-capture trigger input of the TRCGRA register.

R8C/32A Group 19. Timer RC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 240 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 19.7 Block Diagram of Input Capture Function IOA3: Bit in TRCIOR0 register Notes: 1. The BFC bit in the TRCMR register is set to 1 (TRCGRC register functions as the buffer register for the TRCGRA register) 2. The BFD bit in the TRCMR register is set to 1 (TRCGRD register functions as the buffer register for the TRCGRB register) 3. The trigger input of the TRCGRA register can select the TRCIOA pin input or fOCO128 signal. TRCGRA register TRC register Input capture signal (3) TRCGRC register TRCGRB register TRCGRD register TRCIOB (Note 1) (Note 2) TRCIOC TRCIOD Input capture signal Input capture signal Input capture signal Divided by 128 IOA3 = 0 IOA3 = 1 fOCO-S or fOCO-F fOCO128 TRCIOA Edge selection Edge selection Edge selection Edge selection

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19.4.1 Timer RC I/O Contro l Register 0 (TRCIOR0) for Input Capture Function

Notes: 1. When the BFC bit in the TRCMR register is set to 1 (buffe r register of TRCGRA register), set the IOC2 bit in the TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register. 2. When the BFD bit in the TRCMR register is set to 1 (buffe r register of TRCGRB register), set the IOD2 bit in the TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register. 3. The IOA3 bit is enabled when the IOA2 bit is set to 1 (input capture function). Address 0124h B i t b 7b 6b 5b 4b 3b 2b 1b 0 S y m b o l — I O B 2I O B 1I O B 0I O A 3I O A 2I O A 1I O A 0 A f t e r R e s e t 10001000 Bit Symbol Bit Name Function R/W b0 IOA0 TRCGRA control bit b1 b0 0 0: Input capture to the TRCGRA register at the rising edge 0 1: Input capture to the TRCGRA register at the falling edge 1 0: Input capture to the TRCGRA register at both edges 1 1: Do not set. R/W b1 IOA1 R/W b2 IOA2 TRCGRA mode select bit (1) Set to 1 (input capture) in the input capture function. R/W b3 IOA3 TRCGRA input capture input switch bit (3) 0: fOCO128 signal 1: TRCIOA pin input R/W b4 IOB0 TRCGRB control bit b5 b4 0 0: Input capture to the TRCGRB register at the rising edge 0 1: Input capture to the TRCGRB register at the falling edge 1 0: Input capture to the TRCGRB register at both edges 1 1: Do not set. R/W b5 IOB1 R/W b6 IOB2 TRCGRB mode select bit (2) Set to 1 (input capture) in the input capture function. R/W b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. —

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19.4.2 Timer RC I/O Contro l Register 1 (TRCIOR1) for Input Capture Function

Notes: 1. When the BFC bit in the TRCMR register is set to 1 (buffe r register of TRCGRA register), set the IOC2 bit in the TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register. 2. When the BFD bit in the TRCMR register is set to 1 (buffe r register of TRCGRB register), set the IOD2 bit in the TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register. j = A, B, C, or D BFC, BFD: Bits in TRCMR register Address 0125h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 A f t e r R e s e t 10001000 Bit Symbol Bit Name Function R/W b0 IOC0 TRCGRC control bit b1 b0 0 0: Input capture to the TRCGRC register at the rising edge 0 1: Input capture to the TRCGRC register at the falling edge 1 0: Input capture to the TRCGRC register at both edges 1 1: Do not set. R/W b1 IOC1 R/W b2 IOC2 TRCGRC mode select bit (1) Set to 1 (input capture) in the input capture function. R/W b3 IOC3 TRCGRC register function select bit Set to 1. R/W b4 IOD0 TRCGRD control bit b5 b4 0 0: Input capture to the TRCGRD register at the rising edge 0 1: Input capture to the TRCGRD register at the falling edge 1 0: Input capture to the TRCGRD register at both edges 1 1: Do not set. R/W b5 IOD1 R/W b6 IOD2 TRCGRD mode select bit (2) Set to 1 (input capture) in the input capture function. R/W b7 IOD3 TRCGRD register function select bit Set to 1. R/W Table 19.8 Functions of TRCGRj Register when Using Input Capture Function Register Setting Register Function Input Capture Input Pin TRCGRA − General register. Can be used to read the TRC register value at input capture. TRCIOA TRCGRB TRCIOB TRCGRC BFC = 0 General register. Can be used to read the TRC register value at input capture. TRCIOC TRCGRD BFD = 0 TRCIOD TRCGRC BFC = 1 Buffer registers. Can be used to hold transferred value from the general register. (Refer to 19.3.2 Buffer Operation.) TRCIOA TRCGRD BFD = 1 TRCIOB

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19.4.3 Operating Example

Figure 19.8 Operating Example of Input Capture Function TRC register count value TSTART bit in TRCMR register TRCGRA register TRCIOA input TRCGRC register IMFA bit in TRCSR register OVF bit in TRCSR register TRCCLK input count source The above applies under the following conditions:

• The CCLR bit in the TRCCR1 register is set to 1 (Clear TRC counter by input capture).
• Bits TCK2 to TCK0 in the TRCCR1 register are set to 101b (the count source is TRCCLK input).
• Bits IOA2 to IOA0 in the TRCIORA register are set to 101b (input capture at the falling edge of the TRCIOA input).
• The BFC bit in the TRCMR register is set to 1 (the TRCGRC register functions as the buffer register for the TRCGRA register). Set to 0 by a program Transfer FFFFh 0009h 0006h 65536 0000h 0009h0006h 0006h Transfer

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19.5 Timer Mode (Out put Compare Function)

This function detects when the contents of the TRC register (counter) and the TRCGRj register (j = A, B, C, or D) match (compare match). When a match occurs a signal is output from the TRCIOj pin at a given level. The output compare function, or other mode or function, can be selected for each individual pin. Table 19.9 lists the Specifications of Output Compar e Function, Figure 19.9 shows a Block Diagram of Output Compare Function, Table 19.10 lists the Functions of TRCGRj Register when Using Output Compare Function, and Figure 19.10 shows an Operating Example of Output Compare Function. j = A, B, C, or D Table 19.9 Specifications of Output Compare Function Item Specification Count source f1, f2, f4, f8, f32, fOCO40M, fOCO-F , or external signal (rising edge) input to TRCCLK pin Count operation Increment Count period • The CCLR bit in the TRCCR1 regist er is set to 0 (free running operation): 1/fk × 65,536 fk: Count source frequency

• The CCLR bit in the TRCCR1 register is set to 1 (TRC register set to 0000h at TRCGRA compare match): 1/fk × (n + 1) n: TRCGRA register setting value Waveform output timing Compare match Count start condition 1 (count starts) is written to the TSTART bit in the TRCMR register. Count stop condition • When the CSEL bit in the TRCCR2 register is set to 0 (count continues after compare match with TRCGRA). 0 (count stops) is written to the TSTART bit in the TRCMR register. The output compare output pin retains output level before count stops, the TRC register retains a value before count stops.
• When the CSEL bit in the TRCCR2 register is set to 1 (count stops at compare match with TRCGRA register). The count stops at the compare match with the TRCGRA register. The output- compare output pin retains the level after the output is changed by the compare match. Interrupt request generation timing
• Compare match (contents of registers TRC and TRCGRj match)
• The TRC register overflows. TRCIOA, TRCIOB, TRCIOC, and TRCIOD pin functions Programmable I/O port or output compare output (Selectable individually for each pin) INT0 pin function Programmable I/O port, pulse ou tput forced cutoff signal input, or INT0 interrupt input Read from timer The count value can be read by reading the TRC register. Write to timer The TRC register can be written to. Select functions • Output comp are output pin selection One or more of pins TRCIOA, TRCIOB, TRCIOC, and TRCIOD
• Compare match output level selection “L” output, “H” output, or toggle output
• Initial output level selection Sets output level for period from count start to compare match
• Timing for setting the TRC register to 0000h Overflow or compare match with the TRCGRA register
• Buffer operation (Refer to 19.3.2 Buffer Operation.)
• Pulse output forced cutoff signal input (Refer to 19.3.4 Forced Cutoff of Pulse Output.)
• Can be used as an internal timer by disabling timer RC output
• Changing output pins for registers TRCGRC and TRCGRD TRCGRC can be used for output control of the TRCIOA pin and TRCGRD can be used for output control of the TRCIOB pin.
• A/D trigger generation

R8C/32A Group 19. Timer RC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 245 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 19.9 Block Diagram of Output Compare Function TRCIOA Output control Comparator TRCGRA TRC TRCIOC TRCGRC TRCIOB TRCGRB TRCIOD TRCGRD Output control Output control Output control Compare match signal Compare match signal Compare match signal Compare match signal Comparator Comparator Comparator

R8C/32A Group 19. Timer RC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 246 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

19.5.1 Timer RC Control Register 1 (TRCCR1) for Output Compare Function

Notes: 1. Set to these bits when the TSTART bit in th e TRCMR register is set to 0 (count stops). 2. If the pin function is set for waveform output (refer to 7.5 Port Settings), the initial output level is output when the TRCCR1 register is set. 3. To select fOCO-F, set it to the clock frequency higher than the CPU clock frequency. j = A, B, C, or D BFC, BFD: Bits in TRCMR register Address 0121h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol CCLR TCK2 TCK1 TCK0 TOD TOC TOB TOA A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TOA TRCIOA output level select bit (1, 2) 0: Initial output “L” 1: Initial output “H” R/W b1 TOB TRCIOB output level select bit (1, 2) R/W b2 TOC TRCIOC output level select bit (1, 2) R/W b3 TOD TRCIOD output level select bit (1, 2) R/W b4 TCK0 Count source select bit (1) b6 b5 b4 0 0 0: f1 0 0 1: f2 0 1 0: f4 0 1 1: f8 1 0 0: f32 1 0 1: TRCCLK input rising edge 1 1 0: fOCO40M 1 1 1: fOCO-F (3) R/W b5 TCK1 R/W b6 TCK2 R/W b7 CCLR TRC counter clear select bit 0: Disable clear (free-running operation) 1: Clear by compare match in the TRCGRA register R/W Table 19.10 Functions of TRCGRj Register when Using Output Compare Function Register Setting Register Function Output Compare Output Pin TRCGRA − General register. Write a compare value to one of these registers. TRCIOA TRCGRB TRCIOB TRCGRC BFC = 0 General register. Write a compare value to one of these registers. TRCIOC TRCGRD BFD = 0 TRCIOD TRCGRC BFC = 1 Buffer register. Write the next compare value to one of these registers. (Refer to 19.3.2 Buffer Operation.) TRCIOA TRCGRD BFD = 1 TRCIOB

R8C/32A Group 19. Timer RC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 247 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

19.5.2 Timer RC I/O Contro l Register 0 (TRCIOR0) for Output Compare Function

Notes: 1. When the BFC bit in the TRCMR register is set to 1 ( buffer register of TRCGRA re gister), set the IOC2 bit in theTRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register. 2. When the BFD bit in the TRCMR register is set to 1 (buffe r register of TRCGRB register), set the IOD2 bit in the TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register. Address 0124h B i t b 7b 6b 5b 4b 3b 2b 1b 0 S y m b o l — I O B 2I O B 1I O B 0I O A 3I O A 2I O A 1I O A 0 A f t e r R e s e t 10001000 Bit Symbol Bit Name Function R/W b0 IOA0 TRCGRA control bit b1 b0 0 0: Disable pin output by compare match (TRCIOA pin functions as the programmable I/O port) 0 1: “L” output by compare match in the TRCGRA register 1 0: “H” output by compare match in the TRCGRA register 1 1: Toggle output by compare match in the TRCGRA register R/W b1 IOA1 R/W b2 IOA2 TRCGRA mode select bit (1) Set to 0 (output compare) in the output compare function. R/W b3 IOA3 TRCGRA input capture input switch bit Set to 1. R/W b4 IOB0 TRCGRB control bit b5 b4 0 0: Disable pin output by compare match (TRCIOB pin functions as the programmable I/O port) 0 1: “L” output by compare match in the TRCGRB register 1 0: “H” output by compare match in the TRCGRB register 1 1: Toggle output by compare match in the TRCGRB register R/W b5 IOB1 R/W b6 IOB2 TRCGRB mode select bit (2) Set to 0 (output compare) in the output compare function. R/W b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. —

R8C/32A Group 19. Timer RC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 248 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

19.5.3 Timer RC I/O Contro l Register 1 (TRCIOR1) for Output Compare Function

Notes: 1. When the BFC bit in the TRCMR register is set to 1 ( buffer register of TRCGRA re gister), set the IOC2 bit in theTRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register. 2. When the BFD bit in the TRCMR register is set to 1 ( buffer register of TRCGRB re gister), set the IOD2 bit in theTRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register. Address 0125h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 A f t e r R e s e t 10001000 Bit Symbol Bit Name Function R/W b0 IOC0 TRCGRC control bit b1 b0 0 0: Disable pin output by compare match 0 1: “L” output by compare match in the TRCGRC register 1 0: “H” output by compare match in the TRCGRC register 1 1: Toggle output by compare match in the TRCGRC register R/W b1 IOC1 R/W b2 IOC2 TRCGRC mode select bit (1) Set to 0 (output compare) in the output compare function. R/W b3 IOC3 TRCGRC register function select bit 0: TRCIOA output register 1: General register or buffer register R/W b4 IOD0 TRCGRD control bit b5 b4 0 0: Disable pin output by compare match 0 1: “L” output by compare match in the TRCGRD register 1 0: “H” output by compare match in the TRCGRD register 1 1: Toggle output by compare match in the TRCGRD register R/W b5 IOD1 R/W b6 IOD2 TRCGRD mode select bit (2) Set to 0 (output compare) in the output compare function. R/W b7 IOD3 TRCGRD register function select bit 0: TRCIOB output register 1: General register or buffer register R/W

R8C/32A Group 19. Timer RC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 249 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

19.5.4 Operating Example

Figure 19.10 Operating Example of Output Compare Function Output level held m n p TRC register value Count source m+1 m+1 TSTART bit in TRCMR register TRCIOA output IMFA bit in TRCSR register n+1 TRCIOB output “H” output at compare match Set to 0 by a program IMFB bit in TRCSR register Initial output “L” Initial output “L” TRCIOC output Set to 0 by a program IMFC bit in TRCSR register Initial output “H” “L” output at compare match P+1 m: TRCGRA register setting value n: TRCGRB register setting value p: TRCGRC register setting value The above applies under the following conditions: Count restarts Count stops Output level held Set to 0 by a program

• Bits BFC and BFD in the TRCMR register are set to 0 (TRCGRC and TRCGRD do not operate as buffers).
• Bits EA, EB, and EC in the TRCOER register are set to 0 (output from TRCIOA, TRCIOB, and TRCIOC enabled).
• The CCLR bit in the TRCCR1 register is set to 1 (set the TRC register to 0000h by TRCGRA compare match).
• In the TRCCR1 register, bits TOA and TOB are set to 0 (“L” initial output until compare match) and the TOC bit is set to 1 (“H” initial output until compare match).
• Bits IOA2 to IOA0 in the TRCIOR0 register are set to 011b (TRCIOA output inverted at TRCGRA compare match).
• Bits IOB2 to IOB0 in the TRCIOR0 register are set to 010b (“H” TRCIOB output at TRCGRB compare match).
• Bits IOC2 to IOC2 in the TRCIOR1 register are set to 001b (“L” TRCIOC output at TRCGRC compare match).
• The CSEL bit in the TRCCR2 register is set to 0 (TRC count continues after TRCGRA compare match). Output level held Output inverted at compare match

R8C/32A Group 19. Timer RC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 250 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

19.5.5 Changing Output Pins in Registers TRCGRC and TRCGRD

The TRCGRC register can be used for output control of the TRCIOA pin, and the TRCGRD register can be used for output control of the TRCIOB pin. Therefore, each pin output can be controlled as follows:

• TRCIOA output is controlled by the values in registers TRCGRA and TRCGRC.
• TRCIOB output is controlled by the values in registers TRCGRB and TRCGRD. Change output pins in registers TRCGRC and TRCGRD as follows:
• Set the IOC3 bit in the TRCIOR1 register to 0 (TRCIOA output register) and set the IOD3 bit to 0 (TRCIOB output register).
• Set bits BFC and BFD in the TRCMR register to 0 (general register).
• Set different values in register s TRCGRC and TRCGRA. Also, set diff erent values in registers TRCGRD and TRCGRB. Figure 19.12 shows an Operating Example When TRCGRC Register is Used for Output Control of TRCIOA Pin and TRCGRD Register is Used for Output Control of TRCIOB Pin. Figure 19.11 Changing Output Pins in Registers TRCGRC and TRCGRD TRCIOA Output control Comparator TRCGRA TRC TRCIOC Output control Comparator TRCGRC Compare match signal TRCIOB Output control Comparator TRCGRB TRCIOD Output control Comparator TRCGRD Compare match signal Compare match signal Compare match signal IOC3 = 0 in TRCIOR1 register IOC3 = 1 IOD3 = 0 in TRCIOR1 register IOD3 = 1

R8C/32A Group 19. Timer RC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 251 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 19.12 Operating Example When TRCGRC Regist er is Used for Output Control of TRCIOA Pin and TRCGRD Register is Used for Output Control of TRCIOB Pin Set to 0 by a programSet to 0 by a program Value in TRC register Count source TRCIOA output FFFFh TRCIOB output m: Value set in TRCGRA register n: Value set in TRCGRC register p: Value set in TRCGRB register q: Value set in TRCGRD register The above applies under the following conditions: Bits BFC and BFD in the TRCMR register are set to 0 (registers TRCGRC and TRCGRD are not used as buffer register). Bits EA and EB in the TRCOER register are set to 0 (enable TRCIOA and TRCIOB pin outputs). The CCLR bit in the TRCCR1 register are set to 1 (set the TRC register to 0000h by compare match in the TRCGRA register). Bits TOA and TOB in the TRCCR1 register are set to 0 (initial output “L” to compare match). Bits IOA2 to IOA0 in the TRCIOR0 register are set to 011b (TRCIOA output inverted at TRCGRA register compare match). Bits IOB2 to IOB0 in the TRCIOR0 register are set to 011b (TRCIOB output inverted at TRCGRB register compare match). Bits IOC2 to IOC0 in the TRCIOR1 register are set to 011b (TRCIOA output inverted at TRCGRC register compare match). The IOC3 bit in the TRCIOR1 register are set to 0 (TRCIOA output register). Bits IOD2 to IOD0 in the TRCIOR1 register are set to 011b (TRCIOB output inverted at TRCGRD register compare match). The IOD3 bit in the TRCIOR1 register are set to 0 (TRCIOB output register). The CSEL bit in the TRCCR2 register are set to 0 (TRC continues counting after compare match). i = 0 or 1 m n p m+1 n+1 q 0000h m-n p+1 p-qq+1 IMFA bit in TRCSR register IMFC bit in TRCSR register Set to 0 by a program Output inverted by compare match Initial output “L” IMFB bit in TRCSR register IMFD bit in TRCSR register Initial output “L” Set to 0 by a program Output inverted by compare match

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19.6 PWM Mode

This mode outputs PWM waveforms. A maximum of three PWM waveforms with the same period are output. The PWM mode, or the timer mode, can be selected for each individual pin. (However, since the TRCGRA register is used when using any pin for the PWM mode, the TRCGRA register cannot be used for the timer mode.) Table 19.11 lists the Specifications of PWM Mode, Figure 19.13 shows a PWM Mode Block Diagram, Table 19.12 lists the Functions of TRCGRj Register in PWM Mode, and Figures 19.14 and 19.15 show Operating Examples of PWM Mode. j = B, C, or D h = A, B, C, or D Table 19.11 Specifications of PWM Mode Item Specification Count source f1, f2, f4, f8, f32, fOCO40M, fO CO-F, or external signal (rising edge) input to TRCCLK pin Count operation Increment PWM waveform PWM period: 1/fk × (m + 1) Active level width: 1/fk × (m - n) Inactive width: 1/fk × (n + 1) fk: Count source frequency m: TRCGRA register setting value n: TRCGRj register setting value Count start condition 1 (count starts) is writte n to the TSTART bit in the TRCMR register. Count stop condition • When the CSEL bit in the TRCCR2 register is set to 0 (count continues after compare match with TRCGRA). 0 (count stops) is written to the TSTART bit in the TRCMR register. PWM output pin retains output level before count stops, TRC register retains value before count stops.

• When the CSEL bit in the TRCCR2 register is set to 1 (count stops at compare match with TRCGRA register). The count stops at the compare match with the TRCGRA register. The PWM output pin retains the level after the output is changed by the compare match. Interrupt request generation timing
• Compare match (contents of registers TRC and TRCGRh match)
• The TRC register overflows. TRCIOA pin function Programmable I/O port TRCIOB, TRCIOC, and TRCIOD pin functions Programmable I/O port or PWM output (selectable individually for each pin) INT0 pin function Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt input Read from timer The count value can be read by reading the TRC register. Write to timer The TRC register can be written to. Select functions • One to three pins selectable as PWM output pins One or more of pins TRCIOB, TRCIOC, and TRCIOD
• Active level selectable for each pin
• Initial level selectable for each pin
• Buffer operation (Refer to 19.3.2 Buffer Operation.)
• Pulse output forced cutoff signal input (Refer to 19.3.4 Forced Cutoff of Pulse Output.)
• A/D trigger generation m+1 n+1 m-n (“L” is active level)

R8C/32A Group 19. Timer RC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 253 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 19.13 PWM Mode Block Diagram TRCIOB Output control Comparator TRCGRA TRC Compare match signal TRCGRBTRCIOC TRCGRC TRCGRD TRCIOD Notes: 1. The BFC bit in the TRCMR register is set to 1 (TRCGRC register functions as the buffer register for the TRCGRA register) 2. The BFD bit in the TRCMR register is set to 1 (TRCGRD register functions as the buffer register for the TRCGRB register) (Note 1) (Note 2) Compare match signal Compare match signal Compare match signal Comparator Comparator Comparator

R8C/32A Group 19. Timer RC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 254 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

19.6.1 Timer RC Control Regist er 1 (TRCCR1) in PWM Mode

j = B, C or D Notes: 1. Set to these bits when the TSTART bit in th e TRCMR register is set to 0 (count stops). 2. If the pin function is set for waveform output (refer to 7.5 Port Settings), the initial output level is output when the TRCCR1 register is set. 3. To select fOCO-F, set it to the clock frequency higher than the CPU clock frequency.

19.6.2 Timer RC Contro l Register 2 (TRCCR2)

Notes: 1. Enabled when in PWM mode. 2. For notes on PWM2 mode, refer to 19.9.6 TRCMR Register in PWM2 Mode. 3. In timer mode and PWM mode these bits are disabled. Address 0121h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol CCLR TCK2 TCK1 TCK0 TOD TOC TOB TOA A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TOA TRCIOA output level select bit (1) Disabled in PWM mode R/W b1 TOB TRCIOB output level select bit (1, 2) 0: Initial output selected as non-active level 1: Initial output selected as active level R/W b2 TOC TRCIOC output level select bit (1, 2) R/W b3 TOD TRCIOD output level select bit (1, 2) R/W b4 TCK0 Count source select bit (1) b6 b5 b4 0 0 0: f1 0 0 1: f2 0 1 0: f4 0 1 1: f8 1 0 0: f32 1 0 1: TRCCLK input rising edge 1 1 0: fOCO40M 1 1 1: fOCO-F (3) R/W b5 TCK1 R/W b6 TCK2 R/W b7 CCLR TRC counter clear select bit 0: Disable clear (free-running operation) 1: Clear by compare match in the TRCGRA register R/W Address 0130h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TCEG1 TCEG0 CSTP — — POLD POLC POLB A f t e r R e s e t 00011000 Bit Symbol Bit Name Function R/W b0 POLB PWM mode output level control bit B (1) 0: TRCIOB output level selected as “L” active 1: TRCIOB output level selected as “H” active R/W b1 POLC PWM mode output level control bit C (1) 0: TRCIOC output level selected as “L” active 1: TRCIOC output level selected as “H” active R/W b2 POLD PWM mode output level control bit D (1) 0: TRCIOD output level selected as “L” active 1: TRCIOD output level selected as “H” active R/W b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b4 — b5 CSTP TRC count operation select bit (2) 0: Count continues at compare match with the TRCGRA register 1: Count stops at compare match with the TRCGRA register R/W b6 TCEG0 TRCTRG input edge select bit (3) b7 b6 0 0: Disable the trigger input from the TRCTRG pin 0 1: Rising edge selected 1 0: Falling edge selected 1 1: Both edges selected R/W b7 TCEG1 R/W

R8C/32A Group 19. Timer RC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 255 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. j = A, B, C, or D BFC, BFD: Bits in TRCMR register Note: 1. The output level does not change even when a compare match occurs if the TRCGRA register value (PWM period) is the same as the TRCGRB, TRCGRC, or TRCGRD register value. Table 19.12 Functions of TRCGRj Register in PWM Mode Register Setting Register Function PWM Output Pin TRCGRA − General register. Set the PWM period. − TRCGRB − General register. Set the PWM output change point. TRCIOB TRCGRC BFC = 0 General register. Set the PWM output change point. TRCIOC TRCGRD BFD = 0 TRCIOD TRCGRC BFC = 1 Buffer register. Set the next PWM period. (Refer to 19.3.2 Buffer Operation.) TRCGRD BFD = 1 Buffer register. Set the next PWM output change point. (Refer to 19.3.2 Buffer Operation.) TRCIOB

R8C/32A Group 19. Timer RC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 256 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

19.6.3 Operating Example

Figure 19.14 Operating Example of PWM Mode TRCIOC output TRCIOD output m: TRCGRA register setting value n: TRCGRB register setting value p: TRCGRC register setting value q: TRCGRD register setting value TRCIOB output IMFA bit in TRCSR register IMFB bit in TRCSR register IMFC bit in TRCSR register IMFD bit in TRCSR register The above applies under the following conditions:

• Bits BFC and BFD in the TRCMR register are set to 0 (registers TRCGRC and TRCGRD do not operate as buffers).
• Bits EB, EC, and ED in the TRCOER register are set to 0 (output from TRCIOB, TRCIOC, and TRCIOD enabled).
• Bits TOB and TOC in the TRCCR1 register are set to 0 (inactive level), the TOD bit is set to 1 (active level).
• The POLB bit in the TRCCR2 register is set to 1 (“H” active), bits POLC and POLD are set to 0 (“L” active). m n p Value in TRC register Count source m+1 n+1 q m-n p+1 m-p m-qq+1 Inactive level “L” Active level “H” Inactive level “H” Active level “L” Set to 0 by a program Set to 0 by a program Set to 0 by a program Set to 0 by a program Initial output “L” to compare match Initial output “H” to compare match Initial output “L” to compare match

R8C/32A Group 19. Timer RC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 257 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 19.15 Operating Example of PWM Mode (Duty 0% and Duty 100%) Rewritten by a program m p q TRC register value n m: TRCGRA register setting value Set to 0 by a program Rewritten by a program 0000h q Duty 0% TRCGRB register IMFA bit in TRCSR register IMFB bit in TRCSR register TSTART bit in TRCMR register TRCIOB output p (p>m)n m p TRC register value n 0000h TRCGRB register IMFA bit in TRCSR register IMFB bit in TRCSR register TSTART bit in TRCMR register TRCIOB output pn m The above applies under the following conditions:

• The EB bit in the TRCOER register is set to 0 (output from TRCIOB enabled).
• The POLB bit in the TRCCR2 register is set to 0 (“L” active). TRCIOB output does not switch to “L” because no compare match with the TRCGRB register has occurred If compare matches occur simultaneously with registers TRCGRA and TRCGRB, the compare match with the TRCGRB register has priority. TRCIOB output switches to “L”. (In other words, no change).TRCIOB output switches to “L” at compare match with the TRCGRB register. (In other words, no change). Set to 0 by a programSet to 0 by a program Duty 100% Set to 0 by a program

R8C/32A Group 19. Timer RC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 258 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

19.7 PWM2 Mode

This mode outputs a single PWM waveform. After a given wait duration has elapsed following the trigger, the pin output switches to active level. Then, after a given duration, the output switches back to inactive level. Furthermore, the counter stops at the same time the output returns to inactive level, making it possible to use PWM2 mode to output a programmable wait one-shot waveform. Since timer RC uses multiple general registers in PWM2 mode, other modes cannot be used in conjunction with it. Figure 19.16 shows a PWM2 Mode Block Diagram, Table 19.13 lists the Specificatio ns of PWM2 Mode, Table 19.14 lists the Functions of TRCGRj Register in PWM2 Mode, and Figures 19.17 to 19.19 show Operating Examples of PWM2 Mode. Figure 19.16 PWM2 Mode Block Diagram TRCTRG Input control TRCIOB Output control Comparator TRCGRATRC TRCGRD register Compare match signal Comparator TRCGRB Comparator TRCGRC Note: 1. The BFD bit in the TRCMR register is set to 1 (the TRCGRD register functions as the buffer register for the TRCGRB register) . Count clear signal Trigger signal (Note 1)

R8C/32A Group 19. Timer RC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 259 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. j = A, B, or C Table 19.13 Specifications of PWM2 Mode Item Specification Count source f1, f2, f4, f8, f32, fOCO40M, fOCO-F, or external signal (rising edge) input to TRCCLK pin Count operation Increment TRC register PWM waveform PWM period: 1/fk × (m + 1) (no TRCTRG input) Active level width: 1/fk × (n - p) Wait time from count start or trigger: 1/fk × (p + 1) fk: Count source frequency m: TRCGRA register setting value n: TRCGRB register setting value p: TRCGRC register setting value Count start conditions • Bits TCEG1 to TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger disabled) or the CSEL bit in the TRCCR2 register is set to 0 (count continues). 1 (count starts) is written to the TSTART bit in the TRCMR register.

• Bits TCEG1 to TCEG0 in the TRCCR2 register are set to 01b, 10b, or 11b (TRCTRG trigger enabled) and the TSTART bit in the TRCMR register is set to 1 (count starts). A trigger is input to the TRCTRG pin Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRCMR register while the CSEL bit in the TRCCR2 register is set to 0 or 1. The TRCIOB pin outputs the initial level in accordance with the value of the TOB bit in the TRCCR1 register. The TRC register retains the value before count stops.
• The count stops due to a compare match with TRCGRA while the CSEL bit in the TRCCR2 register is set to 1 The TRCIOB pin outputs the initial level. The TRC register retains the value before count stops if the CCLR bit in the TRCCR1 register is set to 0. The TRC register is set to 0000h if the CCLR bit in the TRCCR1 register is set to 1. Interrupt request generation timing
• Compare match (contents of TRC and TRCGRj registers match)
• The TRC register overflows TRCIOA/TRCTRG pin function Programmable I/O port or TRCTRG input TRCIOB pin function PWM output TRCIOC and TRCIOD pin functions Programmable I/O port INT0 pin function Programmable I/O port, pulse out put forced cutoff signal input, or INT0 interrupt input Read from timer The count value can be read by reading the TRC register. Write to timer The TRC register can be written to. Select functions • External trigger and valid edge selection The edge or edges of the signal input to the TRCTRG pin can be used as the PWM output trigger: rising edge, falling edge, or both rising and falling edges
• Buffer operation (Refer to 19.3.2 Buffer Operation.)
• Pulse output forced cutoff signal input (Refer to 19.3.4 Forced Cutoff of Pulse Output.)
• Digital filter (Refer to 19.3.3 Digital Filter.)
• A/D trigger generation m+1 TRCTRG input TRCIOB output (TRCTRG: Rising edge, active level is “H”) n-p n+1 p+1 p+1 n+1 n-p

R8C/32A Group 19. Timer RC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 260 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

19.7.1 Timer RC Control Regist er 1 (TRCCR1) in PWM2 Mode

Notes: 1. Set to these bits when the TSTART bit in th e TRCMR register is set to 0 (count stops). 2. If the pin function is set for waveform output (refer to 7.5 Port Settings), the initial output level is output when the TRCCR1 register is set. 3. To select fOCO-F, set it to the clock frequency higher than the CPU clock frequency. Address 0121h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol CCLR TCK2 TCK1 TCK0 TOD TOC TOB TOA A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TOA TRCIOA output level select bit (1) Disabled in PWM2 mode R/W b1 TOB TRCIOB output level select bit (1, 2) 0: Active level “H” (Initial output “L” “H” output by compare match in the TRCGRC register “L” output by compare match in the TRCGRB register 1: Active level “L” (Initial output “H” “L” output by compare match in the TRCGRC register “H” output by compare match in the TRCGRB register R/W b2 TOC TRCIOC output level select bit (1) Disabled in PWM2 mode R/W b3 TOD TRCIOD output level select bit (1) R/W b4 TCK0 Count source select bit (1) b6 b5 b4 0 0 0: f1 0 0 1: f2 0 1 0: f4 0 1 1: f8 1 0 0: f32 1 0 1: TRCCLK input rising edge 1 1 0: fOCO40M 1 1 1: fOCO-F (3) R/W b5 TCK1 R/W b6 TCK2 R/W b7 CCLR TRC counter clear select bit 0: Disable clear (free-running operation) 1: Clear by compare match in the TRCGRA register R/W

R8C/32A Group 19. Timer RC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 261 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

19.7.2 Timer RC Control Regist er 2 (TRCCR2) in PWM2 Mode

Notes: 1. Enabled when in PWM mode. 2. For notes on PWM2 mode, refer to 19.9.6 TRCMR Register in PWM2 Mode. 3. In timer mode and PWM mode these bits are disabled.

19.7.3 Timer RC Digital Filt er Function Select Register (TRCDF) in PWM2 Mode

Notes: 1. These bits are enabled for the input capture function. 2. These bits are enabled when in PWM2 mode and bits TCEG1 to TCEG0 in the TRCCR2 register are set to 01b, 10b, or 11b (TRCTRG trigger input enabled). Address 0130h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TCEG1 TCEG0 CSTP — — POLD POLC POLB A f t e r R e s e t 00011000 Bit Symbol Bit Name Function R/W b0 POLB PWM mode output level control bit B (1) 0: TRCIOB output level selected as “L” active 1: TRCIOB output level selected as “H” active R/W b1 POLC PWM mode output level control bit C (1) 0: TRCIOC output level selected as “L” active 1: TRCIOC output level selected as “H” active R/W b2 POLD PWM mode output level control bit D (1) 0: TRCIOD output level selected as “L” active 1: TRCIOD output level selected as “H” active R/W b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b4 — b5 CSTP TRC count operation select bit (2) 0: Count continues at compare match with the TRCGRA register 1: Count stops at compare match with the TRCGRA register R/W b6 TCEG0 TRCTRG input edge select bit (3) b7 b6 0 0: Disable the trigger input from the TRCTRG pin 0 1: Rising edge selected 1 0: Falling edge selected 1 1: Both edges selected R/W b7 TCEG1 R/W Address 0131h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol DFCK1 DFCK0 — DFTRG DFD DFC DFB DFA A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 DFA TRCIOA pin digital filter function select bit (1) 0: Function is not used 1: Function is used R/W b1 DFB TRCIOB pin digital filter function select bit (1) R/W b2 DFC TRCIOC pin digital filter function select bit (1) R/W b3 DFD TRCIOD pin digital filter function select bit (1) R/W b4 DFTRG TRCTRG pin digital filter function select bit (2) R/W b5 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b6 DFCK0 Clock select bits for digital filter function (1, 2) b7 b6 0 0: f32 0 1: f8 1 0: f1 1 1: Count source (clock selected by bits TCK2 to TCK0 in the TRCCR1 register) R/W b7 DFCK1 R/W

R8C/32A Group 19. Timer RC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 262 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. j = A, B, C, or D BFC, BFD: Bits in TRCMR register Note: 1. Do not set the TRCGRB and TRCG RC registers to the same value. Table 19.14 Functions of TRCGRj Register in PWM2 Mode Register Setting Register Function PWM2 Output Pin TRCGRA − General register. Set the PWM period. TRCIOB pin TRCGRB − General register. Set the PWM output change point. TRCGRC BFC = 0 General register. Set the PWM output change point (wait time after trigger). TRCGRD BFD = 0 (Not used in PWM2 mode) − TRCGRD BFD = 1 Buffer register. Set the next PWM output change point. (Refer to 19.3.2 Buffer Operation.) TRCIOB pin

R8C/32A Group 19. Timer RC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 263 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

19.7.4 Operating Example

Figure 19.17 Operating Example of PWM2 Mode (TRCTRG Trigger Input Disabled) Set to 0 by a program Set to 0 by a program TRC register value Count source m+1 n+1 0000h FFFFh p+1 TRCIOB output m: TRCGRA register setting value n: TRCGRB register setting value p: TRCGRC register setting value m n p TSTART bit in TRCMR register Count stops because the CSEL bit is set to 1 “L” initial output “H” output at TRCGRC register compare match “L” output at TRCGRB register compare match IMFA bit in TRCSR register Set to 0 by a programIMFB bit in TRCSR register CSEL bit in TRCCR2 register Set to 1 by a program IMFC bit in TRCSR register Transfer TRCGRB register TRCGRD register nN e x t d a t a Transfer n Transfer from buffer register to general register The above applies under the following conditions:

• The TOB bit in the TRCCR1 register is set to 0 (initial level is “L”, “H” output at compare match with the TRCGRC register, “L” output at compare match with the TRCGRB register).
• Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger input disabled). Set to 0000h by a program Previous value held if the TSTART bit is set to 0 TSTART bit is set to 0 TRC register cleared at TRCGRA register compare match p+1 “H” output at TRCGRC register compare match No changeNo change Return to initial output if the TSTART bit is set to 0

R8C/32A Group 19. Timer RC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 264 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 19.18 Operating Example of PWM2 Mode (TRCTRG Trigger Input Enabled) Set to 0 by a program TRC register value Count source m+1 n+1 0000h FFFFh p+1 TRCIOB output m: TRCGRA register setting value n: TRCGRB register setting value p: TRCGRC register setting value m n p TSTART bit in TRCMR register Count stops because the CSEL bit is set to 1 “L” initial output “H” output at TRCGRC register compare match IMFA bit in TRCSR register Set to 0 by a programIMFB bit in TRCSR register CSEL bit in TRCCR2 register IMFC bit in TRCSR register Transfer TRCGRB register TRCGRD register Next data Transfer n Transfer from buffer register to general register The above applies under the following conditions:

• The TOB bit in the TRCCR1 register is set to 0 (initial level is “L”, “H” output at compare match with the TRCGRC register, “L” output at compare match with the TRCGRB register).
• Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 11b (trigger at both rising and falling edges of TRCTRG input). Set to 0000h by a program Previous value held if the TSTART bit is set to 0 The TSTART bit is set to 0 TRC register cleared at TRCGRA register compare match Return to initial value if the TSTART bit is set to 0 TRC register (counter) cleared at TRCTRG pin trigger input TRCTRG input Count starts TSTART bit is set to 1 n+1 p+1 p+1 “L” output at TRCGRB register compare match Inactive level so TRCTRG input is enabled Active level so TRCTRG input is disabled Set to 0 by a program Set to 0 by a program n Transfer n n Transfer Transfer from buffer register to general register n Set to 1 by a program Changed by a program Count starts at TRCTRG pin trigger input

R8C/32A Group 19. Timer RC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 265 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 19.19 Operating Example of PWM2 Mode (Duty 0% and Duty 100%)

• TRCGRC register setting value greater than TRCGRA register setting value m n TRC register value p Set to 0 by a program 0000h IMFB bit in TRCSR register IMFC bit in TRCSR register TSTART bit in TRCMR register TRCIOB output The above applies under the following conditions:
• The TOB bit in the TRCCR1 register is set to 0 (initial level is “L”, “H” output at compare match with the TRCGRC register, “L” output at compare match with the TRCGRB register).
• Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger input disabled). p+1 IMFA bit in TRCSR register “L” initial output No compare match with TRCGRB register, so “H” output continues “H” output at TRCGRC register compare match m+1
• TRCGRB register setting value greater than TRCGRA register setting value m p TRC register value n 0000h IMFB bit in TRCSR register IMFC bit in TRCSR register TSTART bit in TRCMR register TRCIOB output n+1 IMFA bit in TRCSR register “L” initial output “L” output at TRCGRB register compare match with no change. No compare match with TRCGRC register, so “L” output continues m+1 m: TRCGRA register setting value n: TRCGRB register setting value p: TRCGRC register setting value

R8C/32A Group 19. Timer RC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 266 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

19.8 Timer RC Interrupt

Timer RC generates a timer RC interrupt request from five sources. The timer RC interrupt uses the single TRCIC register (bits IR and ILVL0 to ILVL2) and a single vector. Table 19.15 lists the Registers Associated with Timer RC Interrupt, and Figure 19.20 is a Timer RC Interrupt Block Diagram. Figure 19.20 Timer RC In terrupt Block Diagram Like other maskable interrupts, the timer RC interrupt is controlled by the combination of the I flag, IR bit, bits ILVL0 to ILVL2, and IPL. However, it differs from other maskable interrupts in the following respects because a single interrupt source (timer RC interrupt) is generated from multiple interrupt request sources.

• The IR bit in the TRCIC register is set to 1 (interrupt requested) when a bit in the TRCSR register is set to 1 and the corresponding bit in the TRCIER register is also set to 1 (interrupt enabled).
• The IR bit is set to 0 (no interrupt requested) when the bit in the TRCSR register or the corresponding bit in the TRCIER register is set to 0, or both are set to 0. In other words, the interrupt request is not maintained if the IR bit is once set to 1 but the interrupt is not acknowledged.
• If another interrupt source is triggered after the IR bit is set to 1, the IR bit remains set to 1 and does not change.
• If multiple bits in the TRCIER register are set to 1, use the TRCSR register to determine the source of the interrupt request.
• The bits in the TRCSR register are not automatically set to 0 when an interrupt is acknowledged. Set them to 0 within the interrupt routine. Refer to 19.2.5 Timer RC Status Register (TRCSR) , for the procedure for setting these bits to 0. Refer to 19.2.4 Timer RC Interrupt Enable Register (TRCIER), for details of the TRCIER register. Refer to 11.3 Interrupt Control , for details of the TRCIC register and 11.1.5.2 Relocatable Vector Tables , for information on interrupt vectors. Table 19.15 Registers Associat ed with Timer RC Interrupt Timer RC Status Register Timer RC Interrupt Enab le Register Timer RC Inte rrupt Control Register TRCSR TRCIER TRCIC Timer RC interrupt request (IR bit in TRCIC register) IMFA bit IMIEA bit IMFB bit IMIEB bit IMFC bit IMIEC bit IMFD bit IMIED bit OVF bit OVIE bit IMFA, IMFB, IMFC, IMFD, OVF: Bits in TRCSR register IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRCIER register

R8C/32A Group 19. Timer RC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 267 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

19.9 Notes on Timer RC

19.9.1 TRC Register

• The following note applies when the CCLR bit in the TRCCR1 register is set to 1 (clear TRC register at compare match with TRCGRA register). When using a program to write a valu e to the TRC register while the TSTART bit in the TRCMR register is set to 1 (count starts), ensure that the write does not overlap with the timing with which the TRC register is set to 0000h. If the timing of the write to the TRC register and the setting of the TRC register to 0000h coincide, the write value will not be written to the TRC register and the TRC register will be set to 0000h.
• Reading from the TRC register immedi ately after writing to it can result in the value previous to the write being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions. Program Example MOV .W #XXXXh, TRC ;Write JMP.B L1 ;JMP.B instruction L1: MOV .W TRC,DATA ;Read

19.9.2 TRCSR Register

Reading from the TRCSR register immediately after writin g to it can result in the value previous to the write being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions. Program Example MOV .B #XXh, TRCSR ;Write JMP.B L1 ;JMP.B instruction L1: MOV .B TRCSR,DATA ;Read

19.9.3 TRCCR1 Register

To set bits TCK2 to TCK0 in the TRCCR1 register to 111b (fOCO-F), set fOCO-F to the clock frequency higher than the CPU clock frequency.

19.9.4 Count Source Switching

• Stop the count before switching the count source. Switching procedure (1) Set the TSTART bit in the TRCMR register to 0 (count stops). (2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register.
• After switching the count source from fOCO40M to another clock, allow a minimum of two cycles of f1 to elapse after changing the clock setting before stopping fOCO40M. Switching procedure (1) Set the TSTART bit in the TRCMR register to 0 (count stops). (2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register. (3) Wait for a minimum of two cycles of f1. (4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator off).

R8C/32A Group 19. Timer RC REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 268 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

• After switching the count source from fOCO-F to fOCO40M, allow a minimum of two cycles of fOCO-F to elapse after changing the clock setting before stopping fOCO-F. Switching procedure (1) Set the TSTART bit in the TRCMR register to 0 (count stops). (2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register. (3) Wait for a minimum of two cycles of fOCO-F. (4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator off).
• After switching the count source from fOCO-F to a clock other than fOCO40M, allow a minimum of one cycle of fOCO-F + fOCO40M to elapse after changing the clock setting before stopping fOCO-F. Switching procedure (1) Set the TSTART bit in the TRCMR register to 0 (count stops). (2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register. (3) Wait for a minimum of one cycle of fOCO-F + fOCO40M. (4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator off).

19.9.5 Input Capture Function

• The pulse width of the input capture signal should be three cycles or more of the timer RC operation clock (refer to Table 19.1 Timer RC Operation Clock).
• The value of the TRC register is tr ansferred to the TRCGRj register one or two cycles of the timer RC operation clock after the input capture signal is input to the TRCIOj (j = A, B, C, or D) pin (when the digital filter function is not used).

19.9.6 TRCMR Regist er in PWM2 Mode

When the CSEL bit in the TRCCR2 register is set to 1 (count stops at compare match with the TRCGRA register), do not set the TRCMR register at compare match timing of registers TRC and TRCGRA.

19.9.7 Count Source fOCO40M

The count source fOCO40M can be used with supply voltage VCC = 2.7 to 5.5 V . For supply voltage other than that, do not set bits TCK2 to TCK0 in the TRCCR1 register to 110b (select fOCO40M as the count source).

R8C/32A Group 20. Timer RE REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 269 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 20. Timer RE Timer RE has the 4-bit counter and 8-bit counter.

20.1 Overview

Timer RE has the following 2 modes:

• Real-time clock mode Generate 1-second signal from fC4 and count seconds, minutes, hours, and days of the week.
• Output compare mode Count a count source and detect compare matches. The count source for timer RE is the operating clock that regulates the timing of timer operations.

R8C/32A Group 20. Timer RE REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 270 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

20.2 Real-Time Clock Mode

In real-time clock mode, a 1-second si gnal is generated from fC4 using a divide-by-2 frequency divider, 4-bit counter, and 8-bit counter and used to count seconds, minutes, hours, and days of the week. Figure 20.1 shows a Block Diagram of Real-Time Clock Mode and Table 20.1 lists the Real-Time Clock Mode Specifications. Table 20.2 lists the Interrupt Sources, Figure 20.2 shows the Definition of Time Representation and Figure 20.3 shows the Operating Example in Real-Time Clock Mode. Figure 20.1 Block Diagram of Real-Time Clock Mode TREWK register TREHR register TREMIN register TRESEC register H12_H24 bit PM bit MNIE HRIE WKIE 000 DYIE SEIE Timer RE interrupt INT bit BSY bit Overflow Timing control Data bus Overflow Overflow (1s) Overflow (1/256)(1/16) fC4 (8.192kHz) 8-bit counter4-bit counter1/2 H12_H24, PM, INT: Bits in TRECR1 register SEIE, MNIE, HRIE, DYIE, WKIE: Bits in TRECR2 register BSY: Bit in TRESEC, TREMIN, TREHR, TREWK register

R8C/32A Group 20. Timer RE REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 271 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Table 20.1 Real-Time Clock Mode Specifications Item Specification Count source fC4 Count operation Increment Count start condition 1 (count starts) is wr itten to TSTART bit in TRECR1 register Count stop condition 0 (count stops) is written to TSTART bit in TRECR1 register Interrupt request generation timing Select any one of the following:

• Update second data
• Update minute data
• Update hour data
• Update day of week data
• When day of week data is set to 000b (Sunday) Read from timer When readin g TRESEC, TREMIN, TREHR, or TREWK register, the count value can be read. The values read from registers TRESEC, TREMIN, and TREHR are represented by the BCD code. Write to timer When bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer stops), the value can be written to registers TRESEC, TREMIN, TREHR, and TREWK. The values written to registers TRESEC, TREMIN, and TREHR are represented by the BCD codes. Select function 12-hour mode/24-hour mode switch function

R8C/32A Group 20. Timer RE REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 272 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

20.2.1 Timer RE Second Da ta Register (TRESEC) in Real-Time Clock Mode

20.2.2 Timer RE Minute Da ta Register (TREMIN) in Real-Time Clock Mode

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol BSY SC12 SC11 SC10 SC03 SC02 SC01 SC00 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function Setting Range R/W b0 SC00 1st digit of second count bit Count 0 to 9 every second. When the digit moves up, 1 is added to the 2nd digit of second. 0 to 9 (BCD code) R/W b1 SC01 R/W b2 SC02 R/W b3 SC03 R/W b4 SC10 2nd digit of second count bit When counting 0 to 5, 60 seconds are counted. 0 to 5 (BCD code) R/W b5 SC11 R/W b6 SC12 R/W b7 BSY Timer RE busy flag This bit is set to 1 while registers TRESEC, TREMIN, TREHR, and TREWK are updated R Address 0119h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol BSY MN12 MN11 MN10 MN03 MN02 MN01 MN00 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function Setting Range R/W b0 MN00 1st digit of minute count bit Count 0 to 9 every minute. When the digit moves up, 1 is added to the 2nd digit of minute. 0 to 9 (BCD code) R/W b1 MN01 R/W b2 MN02 R/W b3 MN03 R/W b4 MN10 2nd digit of minute count bit When counting 0 to 5, 60 minutes are counted. 0 to 5 (BCD code) R/W b5 MN11 R/W b6 MN12 R/W b7 BSY Timer RE busy flag This bit is set to 1 while registers TRESEC, TREMIN, TREHR, and TREWK are updated. R

R8C/32A Group 20. Timer RE REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 273 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

20.2.3 Timer RE Hour Data Register (TREHR) in Real-Time Clock Mode

20.2.4 Timer RE Day of W eek Data Register (TREWK) in Real-Time Clock Mode

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol BSY — HR11 HR10 HR03 HR02 HR01 HR00 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function Setting Range R/W b0 HR00 1st digit of hour count bit Count 0 to 9 every hour. When the digit moves up, 1 is added to the 2nd digit of hour. 0 to 9 (BCD code) R/W b1 HR01 R/W b2 HR02 R/W b3 HR03 R/W b4 HR10 2nd digit of hour count bit Count 0 to 1 w hen the H12_H24 bit is set to 0 (12-hour mode). Count 0 to 2 w hen the H12_H24 bit is set to 1 (24-hour mode). 0 to 2 (BCD code) R/W b5 HR11 R/W b6 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b7 BSY Timer RE busy flag This bit is set to 1 while registers TRESEC, TREMIN, TREHR, and TREWK are updated. R Address 011Bh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol BSY — — — — WK2 WK1 WK0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 WK0 Day of week count bit b2 b1 b0 0 0 0: Sunday 0 0 1: Monday 0 1 0: Tuesday 0 1 1: Wednesday 1 0 0: Thursday 1 0 1: Friday 1 1 0: Saturday 1 1 1: Do not set. R/W b1 WK1 R/W b2 WK2 R/W b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b4 — b5 — b6 — b7 BSY Timer RE busy flag This bit is set to 1 while registers TRESEC, TREMIN, TREHR, and TREWK are updated. R

R8C/32A Group 20. Timer RE REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 274 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

20.2.5 Timer RE Control Register 1 (TRECR1) in Real-Time Clock Mode

Note: 1. This bit is automatically modified while timer RE counts. Figure 20.2 Definition of Time Representation Address 011Ch B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TSTART H12_H24 PM TRERST INT — TCSTF — A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b1 TCSTF Timer RE count status flag 0: Count stopped 1: Counting R b2 — Reserved bit Set to 0. R/W b3 INT Interrupt request timing bit Set to 1 in real-time clock mode. R/W b4 TRERST Timer RE reset bit When setting this bit to 0, after setting it to 1, the followings will occur.

• Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2 are set to 00h.
• Bits TCSTF, INT, PM, H12_H24, and TSTART in the TRECR1 register are set to 0.
• The 8-bit counter is set to 00h and the 4-bit counter is set to 0h. R/W b5 PM A.m./p.m. bit When the H12_H24 bit is set to 0 (12-hour mode) (1) 0: a.m. 1: p.m. When the H12_H24 bit is set to 1 (24-hour mode), its value is undefined. R/W b6 H12_H24 Operating mode select bit 0: 12-hour mode 1: 24-hour mode R/W b7 TSTART Timer RE count start bit 0: Count stops 1: Count starts R/W Noon H12_H24 bit = 1 (24-hour mode) Contents of PM bit 0 (a.m.) 1 (p.m.) Contents of TREHR Register H12_H24 bit = 0 (12-hour mode) Contents in TREWK register 000 (Sunday) 0 1 2 3 4 5 7 9 11 13 15 176 8 10 12 14 16 0 1 2 3 4 5 7 9 11 1 3 56 8 10 0 2 4 H12_H24 bit = 1 (24-hour mode) Contents of PM bit 1 (p.m.) Contents of TREHR Register H12_H24 bit = 0 (12-hour mode) Contents in TREWK register 000 (Sunday) 18 19 20 21 22 23 1 30 2 ⋅⋅⋅ 6 7 8 9 10 11 1 30 2 Date changes ⋅⋅⋅ ⋅⋅⋅0 (a.m.) 001 (Monday) ⋅⋅⋅ PM bit and H12_H24 bits: Bits in TRECR1 register The above applies to the case when count starts from a.m. 0 on Sunday.

R8C/32A Group 20. Timer RE REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 275 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

20.2.6 Timer RE Control Register 2 (TRECR2) in Real-Time Clock Mode

Note: 1. Do not set multiple enable bits to 1 (enable interrupt). Address 011Dh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — COMIE WKIE DYIE HRIE MNIE SEIE A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 SEIE Periodic interrupt triggered every second enable bit (1) 0: Disable periodic interrupt triggered every second 1: Enable periodic interrupt triggered every second R/W b1 MNIE Periodic interrupt triggered every minute enable bit (1) 0: Disable periodic interrupt triggered every minute 1: Enable periodic interrupt triggered every minute R/W b2 HRIE Periodic interrupt triggered every hour enable bit (1) 0: Disable periodic interrupt triggered every hour 1: Enable periodic interrupt triggered every hour R/W b3 DYIE Periodic interrupt triggered every day enable bit (1) 0: Disable periodic interrupt triggered every day 1: Enable periodic interrupt triggered every day R/W b4 WKIE Periodic interrupt triggered every week enable bit (1) 0: Disable periodic interrupt triggered every week 1: Enable periodic interrupt triggered every week R/W b5 COMIE Compare match interrupt enable bi t Set to 0 in real-time clock mode. R/W b6 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b7 — Table 20.2 Interrupt Sources Factor Interrupt Source Interrupt Enable Bit Periodic interrupt triggered every week Value in TREWK register is set to 000b (Sunday) (1-week period) WKIE Periodic interrupt triggered every day TREWK register is updated (1-day period) DYIE Periodic interrupt triggered every hour TREHR register is updated (1-hour period) HRIE Periodic interrupt triggered every minute TREMIN register is updated (1-minute period) MNIE Periodic interrupt triggered every second TRESEC register is updated (1-second period) SEIE

R8C/32A Group 20. Timer RE REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 276 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

20.2.7 Timer RE Count Sour ce Select Register (TRECSR) in Real-Time Clock

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — — RCS3 RCS2 RCS1 RCS0 A f t e r R e s e t 00001000 Bit Symbol Bit Name Function R/W b0 RCS0 Count source select bit Set to 00b in real-time clock mode. R/W b1 RCS1 R/W b2 RCS2 4-bit counter select bit Set to 0 in real-time clock mode. R/W b3 RCS3 Real-time clock mode select bit Set to 1 in real-time clock mode. R/W b4 — Reserved bits Set to 0. R/W b5 — b6 — b7 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. —

R8C/32A Group 20. Timer RE REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 277 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

20.2.8 Operating Example

Figure 20.3 Operating Example in Real-Time Clock Mode IR bit in TREIC register IR bit in TREIC register Bits WK2 to WK0 in TREWK register (when SEIE bit in TRECR2 register is set to 1 (enable periodic interrupt triggered every second)) (when MNIE bit in TRECR2 register is set to 1 (enable periodic interrupt triggered every minute)) PM bit in TRECR1 register Bits HR11 to HR00 in TREHR register (Not changed) Set to 0 by acknowledgement of interrupt request or a program Bits MN12 to MN00 in TREMIN register 58 59 00 BSY bit Approx. 62.5 ms Bits SC12 to SC00 in TRESEC register BSY: Bit in registers TRESEC, TREMIN, TREHR, and TREWK Approx. 62.5 ms (Not changed) (Not changed)

R8C/32A Group 20. Timer RE REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 278 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

20.3 Output Compare Mode

In output compare mode, the internal count source divided by 2 is counted using the 4-bit or 8-bit counter and compare value match is detected with the 8-bit counter. Figure 20.4 shows a Block Diagram of Output Compare Mode and Table 20.3 lists the Output Compare Mode Specifications. Figure 20.5 shows the Operating Example in Output Compare Mode. Figure 20.4 Block Diagram of Output Compare Mode fC4 f32 f8 4-bit counter 8-bit counter TRESEC TREMIN RCS2 = 1 RCS2 = 0 COMIE Timer RE interrupt Match signal = 00b = 01b = 10b = 11b RCS1 to RCS0 TRERST: Bit in TRECR1 register COMIE: Bit in TRECR2 register RCS0 to RCS2: Bits in TRECSR register Data bus Comparison circuit

R8C/32A Group 20. Timer RE REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 279 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Table 20.3 Output Compare Mode Specifications Item Specification Count sources f4, f8, f32, fC4 Count operations • Increment

• When the 8-bit counter content matches with the TREMIN register content, the value returns to 00h and count continues. The count value is held while count stops. Count period • When RCS2 = 0 (4-bit counter is not used) 1/fi x 2 x (n+1)
• When RCS2 = 1 (4-bit counter is used) 1/fi x 32 x (n+1) fi: Frequency of count source n: Setting value of TREMIN register Count start condition 1 (count starts) is writt en to the TSTART bit in the TRECR1 register Count stop condition 0 (count stops) is writte n to the TSTART bit in the TRECR1 register Interrupt request generation timing When the 8-bit counter content matches with the TREMIN register content Read from timer When reading the TRESEC register, the 8-bit counter value can be read. When reading the TREMIN register, the compare value can be read. Write to timer Writing to the TRESEC register is disabled. When bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer stops), writing to the TREMIN register is enabled. Selectable functions • Select use of 4-bit counter

R8C/32A Group 20. Timer RE REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 280 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

20.3.1 Timer RE Counter Data Register (TRESEC) in Output Compare Mode

20.3.2 Timer RE Compare Data Register (TREMIN) in Output Compare Mode

B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00000000 Bit Function R/W b7 to b0 8-bit counter data can be read. Although Timer RE stops counting, the count value is held. The TRESEC register is set to 00h at the compare match. R Address 0119h B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00000000 Bit Function R/W b7 to b0 8-bit compare data is stored. R/W

R8C/32A Group 20. Timer RE REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 281 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

20.3.3 Timer RE Control Register 1 (TRECR1) in Output Compare Mode

20.3.4 Timer RE Control Register 2 (TRECR2) in Output Compare Mode

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TSTART H12_H24 PM TRERST INT — TCSTF — A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b1 TCSTF Timer RE count status flag 0: Count stopped 1: Counting R b2 — Reserved bit Set to 0. R/W b3 INT Interrupt request timing bit Set to 0 in output compare mode. R/W b4 TRERST Timer RE reset bit When setting this bit to 0, after setting it to 1, the following will occur.

• Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2 are set to 00h.
• Bits TCSTF, INT, PM, H12_H24, and TSTART in the TRECR1 register are set to 0.
• The 8-bit counter is set to 00h and the 4-bit counter is set to 0h. R/W b6 H12_H24 Operating mode select bit R/W b7 TSTART Timer RE count start bit 0: Count stops 1: Count starts R/W Address 011Dh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — COMIE WKIE DYIE HRIE MNIE SEIE A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 SEIE Periodic interrupt triggered every second enable bit Set to 0 in output compare mode. R/W b1 MNIE Periodic interrupt triggered every minute enable bit R/W b2 HRIE Periodic interrupt triggered every hour enable bit R/W b3 DYIE Periodic interrupt triggered every day enable bit R/W b4 WKIE Periodic interrupt triggered every week enable bit R/W b5 COMIE Compare match interrupt enable bit 0: Disable compare match interrupt 1: Enable compare match interrupt R/W b6 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b7 —

R8C/32A Group 20. Timer RE REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 282 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

20.3.5 Timer RE Count Sour ce Select Register (TRECS R) in Output Compare

Note: 1. Write to bits RCS0 to RCS1 when the TCSTF bit in the TRECR1 register is set to 0 (count stopped). Address 011Eh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — — RCS3 RCS2 RCS1 RCS0 A f t e r R e s e t 00001000 Bit Symbol Bit Name Function R/W b0 RCS0 Count source select bit (1) b1 b0 0 0: f4 0 1: f8 1 0: f32 1 1: fC4 R/W b1 RCS1 R/W b2 RCS2 4-bit counter select bit 0: Not used 1: Used R/W b3 RCS3 Real-time clock mode select bit Set to 0 in output compare mode. R/W b4 — Reserved bits Set to 0. R/W b5 — b6 — b7 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. —

R8C/32A Group 20. Timer RE REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 283 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

20.3.6 Operating Example

Figure 20.5 Operating Example in Output Compare Mode 2 cycles of maximum count source 00h 8-bit counter content (hexadecimal number) Count starts Time TSTART bit in TRECR1 register IR bit in TREIC register The above applies under the following conditions. COMIE bit in TRECR2 register = 1 (enable compare match interrupt) Set to 1 by a program Set to 0 by acknowledgement of interrupt request or a program TREMIN register setting value Matched TCSTF bit in TRECR1 register Matched Matched

R8C/32A Group 20. Timer RE REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 284 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

20.4 Notes on Timer RE

20.4.1 Starting and Stopping Count

Timer RE has the TSTART bit for instructing the count to start or stop, and the TCSTF bit, which indicates count start or stop. Bits TSTART and TCSTF are in the TRECR1 register. Timer RE starts counting and the TCSTF bit is set to 1 (count starts) when the TSTART bit is set to 1 (count starts). It takes up to 2 cycles of the count source until the TCSTF bit is set to 1 after setting the TSTART bit to 1. During this time, do not access registers associated with timer RE (1) other than the TCSTF bit. Also, timer RE stops counting when setting the TSTART bit to 0 (count stops) and the TCSTF bit is set to 0 (count stops). It takes the time for up to 2 cycles of the count source until the TCSTF bit is set to 0 after setting the TSTART bit to 0. During this time, do not access registers associated with timer RE other than the TCSTF bit. Note: 1. Registers associated with timer RE: TRESEC, TREMIN, TREHR, TREWK, TRECR1, TRECR2, and TRECSR.

20.4.2 Register Setting

Write to the following registers or bits when timer RE is stopped.

• Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2
• Bits H12_H24, PM, and INT in TRECR1 register
• Bits RCS0 to RCS3 in TRECSR register Timer RE is stopped when bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer RE stopped). Also, set all above-mentioned registers and bits (immedia tely before timer RE count starts) before setting the TRECR2 register. Figure 20.6 shows a Setting Example in Real-Time Clock Mode.

R8C/32A Group 20. Timer RE REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 285 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 20.6 Setting Example in Real-Time Clock Mode Stop timer RE operation TCSTF in TRECR1 = 0? TSTART in TRECR1 = 0 TRERST in TRECR1 = 1 TRERST in TRECR1 = 0 Setting of registers TRECSR, TRESEC, TREMIN, TREHR, TREWK, and bits H12_H24, PM, and INT in TRECR1 register Setting of TRECR2 TSTART in TRECR1 = 1 TCSTF in TRECR1 = 1? TREIC ← 00h (disable timer RE interrupt) Setting of TREIC (IR bit ← 0, select interrupt priority level) Timer RE register and control circuit reset Select clock output Select clock source Seconds, minutes, hours, days of week, operating mode Set a.m./p.m., interrupt timing Select interrupt source Start timer RE operation

R8C/32A Group 20. Timer RE REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 286 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

20.4.3 Time Reading Procedur e of Real-Time Clock Mode

In real-time clock mode, read registers TRESEC, TR EMIN, TREHR, and TREWK wh en time data is updated and read the PM bit in the TRECR1 register when the BSY bit is set to 0 (not while data is updated). Also, when reading several registers, an incorrect time will be r ead if data is updated before another register is read after reading any register. In order to prevent this, use the reading procedure shown below.

• Using an interrupt Read necessary contents of registers TRESEC, TR EMIN, TREHR, and TREWK and the PM bit in the TRECR1 register in the timer RE interrupt routine.
• Monitoring with a program 1 Monitor the IR bit in the TREIC register with a prog ram and read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register after the IR bit in the TREIC register is set to 1 (timer RE interrupt request generated).
• Monitoring with a program 2 (1) Monitor the BSY bit. (2) Monitor until the BSY bit is set to 0 after the BSY bi t is set to 1 (approximately 62.5 ms while the BSY bit is set to 1). (3) Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register after the BSY bit is set to 0.
• Using read results if they are the same value twice (1) Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register. (2) Read the same register as (1) and compare the contents. (3) Recognize as the correct value if the contents match. If the contents do not ma tch, repeat until the read contents match with the previous contents. Also, when reading several registers, read them as continuously as possible.

R8C/32A Group 21. Serial Interface (UART0) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 287 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 21. Serial Interface (UART0) The serial interface consists of two channels, UART0, UART2. This chapter describes the UART0.

21.1 Overview

UART0 has a dedicated timer to generate a transfer clock and operate independently. UART0 supports clock synchronous serial I/O mode and clock asynchronous serial I/O mode (UART mode). Figure 21.1 shows a UART0 Block Diagram. Figure 21.2 shows a Block Diagram of UA RT0 Transmit/Receive Unit. Table 21.1 lists the Pin Configuration of UART0. Figure 21.1 UART0 Block Diagram = 01bf8 = 10b CLK1 and CLK0 = 00b RXD0 f32 1/(n0+1) UART reception UART transmission Clock synchronous type (internal clock selected) Clock synchronous type Reception control circuit Transmission control circuit CKDIR = 0 CKDIR = 1 Receive clock Transmit clock Transmit/ receive unit U0BRG register CKDIR = 0 Internal External CKDIR = 1 UART0 TXD0 CLK polarity switch circuit CLK0 Clock synchronous type Clock synchronous type (external clock selected)Clock synchronous type (internal clock selected) CKDIR: Bit in U0MR register CLK0, CLK1: Bits in U0C0 register = 11bfC

R8C/32A Group 21. Serial Interface (UART0) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 288 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 21.2 Block Diagram of UART0 Transmit/Receive Unit Table 21.1 Pin Configuration of UART0 Pin Name Assigned Pin I/O Function TXD0 P1_4 Output Serial data output RXD0 P1_5 Input Serial data input CLK0 P1_6 I/O Transfer clock I/O RXD0 1SP 2SP SP SP PAR PRYE = 0 PAR disabled PAR enabled PRYE = 1 UART UART (9 bits) D7 D6 D5 D4 D3 D2 D1 D0 UART0 receive register U0RB register0000000 D 8 MSB/LSB conversion circuit Data bus high-order bits Data bus low-order bits D7 D6 D5 D4 D3 D2 D1 D0 U0TB registerD8 TXD0 1SP 2SP SP SP PAR UART0 transmit register SP: Stop bit PAR: Parity bit UART (7 bits) UART (8 bits) Clock synchronous type Clock synchronous type UART (7 bits) Clock synchronous type UART (7 bits) Clock synchronous type UART (8 bits) UART (9 bits) UART (7 bits) UART (8 bits) Clock synchronous type UART (9 bits) UART PRYE = 1 PAR enabled PAR disabled PRYE = 0 Clock synchronous type MSB/LSB conversion circuit UART (8 bits) UART (9 bits)

R8C/32A Group 21. Serial Interface (UART0) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 289 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

21.2 Registers

21.2.1 UART0 Transmit/Recei ve Mode Register (U0MR)

21.2.2 UART0 Bit Rate Register (U0BRG)

Write to the U0BRG register while transmission and reception stop. Use the MOV instruction to write to this register. Set bits CLK0 and CLK1 in the U0C0 register before writing to the U0BRG register. Address 00A0h (U0MR) B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — PRYE PRY STPS CKDIR SMD2 SMD1 SMD0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 SMD0 Serial I/O mode select bit b2 b1 b0 0 0 0: Serial interface disabled 0 0 1: Clock synchronous serial I/O mode 1 0 0: UART mode, transfer data 7 bits long 1 0 1: UART mode, transfer data 8 bits long 1 1 0: UART mode, transfer data 9 bits long Other than above: Do not set. R/W b1 SMD1 R/W b2 SMD2 R/W b3 CKDIR Internal/external clock select bit 0: Internal clock 1: External clock R/W b4 STPS Stop bit length select bit 0: One stop bit 1: Two stop bits R/W b5 PRY Odd/even parity select bit Enabled when PRYE = 1 0: Odd parity 1: Even parity R/W b6 PRYE Parity enable bit 0: Parity disabled 1: Parity enabled R/W b7 — Reserved bit Set to 0. R/W Address 00A1h (U0BRG) B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t XXXXXXXX Bit Function Setting Range R/W b7 to b0 If the setting value is n, U0BRG divides the count source by n+1. 00h to FFh W

R8C/32A Group 21. Serial Interface (UART0) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 290 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

21.2.3 UART0 Transmit Bu ffer Register (U0TB)

If the transfer data is 9 bits long, write data to the high-order byte first, then low-order byte of the U0TB register. Use the MOV instruction to write to this register. Address 00A3h to 00A2h (U0TB) B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t XXXXXXXX Bit b15 b14 b13 b12 b11 b10 b9 b8 A f t e r R e s e t XXXXXXXX Bit Symbol Function R/W b0 — Transmit data W b1 — b2 — b3 — b4 — b5 — b6 — b7 — b8 — b9 — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. — b10 — b11 — b12 — b13 — b14 — b15 —

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21.2.4 UART0 Transmit/Receive Control Register 0 (U0C0)

Note: 1. If the BRG count source is swit ched, set the U0BRG register again.

21.2.5 UART0 Transmit/Receive Control Register 1 (U0C1)

Notes: 1. The RI bit is set to 0 when the higher byte of the U0RB register is read. 2. In UART mode, set the U0RRM bit to 0 (continuous receive mode disabled). Address 00A4h (U0C0) B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol UFORM CKPOL NCH — TXEPT — CLK1 CLK0 A f t e r R e s e t 00001000 Bit Symbol Bit Name Function R/W b0 CLK0 BRG count source select bit (1) b1 b0 0 0: f1 selected 0 1: f8 selected 1 0: f32 selected 1 1: fC selected R/W b1 CLK1 R/W b2 — Reserved bit Set to 0. R/W b3 TXEPT Transmit register empty flag 0: Da ta present in the transmit register (transmission in progress) 1: No data in the transmit register (transmission completed) R b4 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b5 NCH Data output select bit 0: TXD0 pin set to CMOS output 1: TXD0 pin set to N-channel open-drain output R/W b6 CKPOL CLK polarity select bit 0: Transmit data output at the falling edge and receive data input at the rising edge of the transfer clock 1: Transmit data output at the rising edge and receive data input at the falling edge of the transfer clock R/W b7 UFORM Transfer format se lect bit 0: LSB first 1: MSB first R/W Address 00A5h (U0C1) B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — U0RRM U0IRS RI RE TI TE A f t e r R e s e t 00000010 Bit Symbol Bit Name Function R/W b0 TE Transmit enable bit 0: Transmission disabled 1: Transmission enabled R/W b1 TI Transmit buffer empty flag 0: Data present in the U0TB register 1: No data in the U0TB register R b2 RE Receive enable bit 0: Reception disabled 1: Reception enabled R/W b3 RI Receive complete flag (1) 0: No data in the U0RB register 1: Data present in the U0RB register R b4 U0IRS UART0 transmit interrupt source select bit 0: Transmission buffer empty (TI = 1) 1: Transmission completed (TXEPT = 1) R/W b5 U0RRM UART0 continuous receive mode enable bit (2) 0: Continuous receive mode disabled 1: Continuous receive mode enabled R/W b6 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b7 —

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21.2.6 UART0 Receive Buff er Register (U0RB)

Note: 1. Bits SUM, PER, FER, and OER are set to 0 (no error) when either of the following is set: - Bits SMD2 to SMD0 in the U0MR register are set to 000b (serial interface disabled), or - The RE bit in the U0C1 register is set to 0 (reception disabled) The SUM bit is set to 0 (no error) when all of bits PER, FER, and OER are set to 0 (no error). Bits PER and FER are also set to 0 when the high-order byte of the U0RB register is read. Always read the U0RB register in 16-bit units. Address 00A7h to 00A6h (U0RB) B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t XXXXXXXX Bit b15 b14 b13 b12 b11 b10 b9 b8 Symbol SUM PER FER OER — — — — A f t e r R e s e t XXXXXXXX Bit Symbol Bit Name Function R/W b0 — — Receive data (D7 to D0) R b1 — b2 — b3 — b4 — b5 — b6 — b7 — b8 — — Receive data (D8) R b9 — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. — b10 — b11 — b12 OER Overrun error flag (1) 0: No overrun error 1: Overrun error R b13 FER Framing error flag (1) 0: No framing error 1: Framing error R b14 PER Parity error flag (1) 0: No parity error 1: Parity error R b15 SUM Error sum flag (1) 0: No error 1: Error R

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21.2.7 UART0 Pin Select Register (U0SR)

The U0SR register selects which pin is assigned to the UART0 I/O. To use the I/O pin for UART0, set this register. Set the U0SR register before setting the UART0 associat ed registers. Also, do not change the setting value in this register during UART0 operation. Address 0188h B i t b 7 b 6 b 5b 4b 3b 2b 1b 0 Symbol — — — CLK0SEL0 — RXD0SEL0 — TXD0SEL0 A f t e r R e s e t 000 0 0 0 0 0 Bit Symbol Bit Name Function R/W b0 TXD0SEL0 TXD0 pin select bit 0: TXD0 pin not used 1: P1_4 assigned R/W b1 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b2 RXD0SEL0 RXD0 pin select bit 0: RXD0 pin not used 1: P1_5 assigned R/W b3 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b4 CLK0SEL0 CLK0 pin select bit 0: CLK0 pin not used 1: P1_6 assigned R/W b5 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b6 — b7 —

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21.3 Clock Synchronous Serial I/O Mode

In clock synchronous serial I/O mode, data is transmitted and received using a transfer clock. Table 21.2 lists the Clock Synchronous Serial I/O Mode Sp ecifications. Table 21.3 lists the Registers Used and Settings in Clock Synchronous Serial I/O Mode (1). Notes: 1. When an external clock is selected, the requirem ents must be met in either of the following states: - The external clock is held high when the CKPOL bit in the U0C0 register is set to 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock) - The external clock is held low when the CKPOL bit in the U0C0 register is set to 1 (transmit data output at the rising edge and receive data input at the falling edge of the transfer clock) 2. If an overrun error oc curs, the receive data (b0 to b8) in the U0RB register will be undefined. The IR bit in the S0RIC register remains unchanged. Table 21.2 Clock Synchronous Serial I/O Mode Specifications Item Specification Transfer data format • Transfer data length: 8 bits Transfer clocks • The CKDIR bit in the U0MR register is set to 0 (internal clock): fi/(2(n+1)) fi = f1, f8, f32, fC n = setting value in the U0BRG register: 00h to FFh

• The CKDIR bit is set to 1 (external clock): Input from the CLK0 pin Transmit start conditions • To start transmission, the following requirements must be met: (1) - The TE bit in the U0C1 register is set to 1 (transmission enabled). - The TI bit in the U0C1 register is set to 0 (data present in the U0TB register). Receive start conditions • To start reception, the following requirements must be met: (1) - The RE bit in the U0C1 register is set to 1 (reception enabled). - The TE bit in the U0C1 register is set to 1 (transmission enabled). - The TI bit in the U0C1 register is set to 0 (data present in the U0TB register). Interrupt request generation timing
• For transmission: One of the following can be selected. - The U0IRS bit is set to 0 (transmit buffer empty): When data is transferred from the U0TB register to the UART0 transmit register (at start of transmission). - The U0IRS bit is set to 1 (transmission completed): When data transmission from the UART0 transmit register is completed.
• For reception: When data is transferred from the UART0 receive register to the U0RB register (at completion of reception). Error detection • Overrun error (2) This error occurs if the serial interface starts receiving the next unit of data before reading the U0RB register and receives the 7th bit of the next unit of data. Selectable functions • CL K polarity selection Transfer data input/output can be selected to occur synchronously with the rising or the falling edge of the transfer clock.
• LSB first, MSB first selection Whether transmitting or receiving data begins with bit 0 or begins with bit 7 can be selected.
• Continuous receive mode selection Reception is enabled immediately by reading the U0RB register.

R8C/32A Group 21. Serial Interface (UART0) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 295 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Note: 1. Set the bits not listed in this table to 0 when writing to the above registers in clock synchronous serial I/O mode. Table 21.3 Registers Used and Settings in Clock Synchronous Serial I/O Mode (1) Register Bit Function U0TB b0 to b7 Set data transmission. U0RB b0 to b7 Receive data can be read. OER Overrun error flag U0BRG b0 to b7 Set a bit rate. U0MR SMD2 to SMD0 Set to 001b. CKDIR Select the internal clock or external clock. U0C0 CLK1, CLK0 Select the count source for the U0BRG register. TXEPT Transmit register empty flag NCH Select TXD0 pin output mode. CKPOL Select the transfer clock polarity. UFORM Select LSB first or MSB first. U0C1 TE Set to 1 to enable transmission/reception TI Transmit buffer empty flag RE Set to 1 to enable reception. RI Receive complete flag U0IRS Select the UART0 transmit interrupt source. U0RRM Set to 1 to use continuous receive mode.

R8C/32A Group 21. Serial Interface (UART0) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 296 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Table 21.4 lists the I/O Pin Functions in Clock Synchronous Serial I/O Mode. After UART0 operating mode is selected, the TXD0 pin out puts a “H” level until transfer starts. (If the NCH bit is set to 1 (N-channel open-drain output), this pin is in the high-impedance state.) Table 21.4 I/O Pin Functions in Clock Synchronous Serial I/O Mode Pin Name Function Selection Method TXD0 (P1_4) Serial data output TXD0SEL0 bit in U0SR register = 1 For reception only: P1_4 can be used as a port by setting TXD0SEL0 bit = 0. RXD0 (P1_5) Serial data input RXD0SEL0 bit in U0SR register = 1 PD1_5 bit in PD1 register = 0 For transmission only: P1_5 can be used as a port by setting RXD0SEL0 bit = 0. CLK0 (P1_6) Transfer clock output CLK0SEL0 bit in U0SR register = 1 CKDIR bit in U0MR register = 0 Transfer clock input CLK0SEL0 bit in U0SR register = 1 CKDIR bit in U0MR register = 1 PD1_6 bit in PD1 register = 0

R8C/32A Group 21. Serial Interface (UART0) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 297 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 21.3 Transmit and Receive Timing in Clock Synchronous Serial I/O Mode Transfer clock TE bit in U0C1 register TXD0

• Transmit Timing Example (Internal Clock Selected) Data is set in U0TB register. Data transfer from U0TB register to UART0 transmit register TC CLK0 TCLK Pulsing stops because TE bit is set to 0. D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 TC = TCLK = 2(n+1)/fi fi: Frequency of U0BRG count source (f1, f8, f32, fC) n: Setting value in U0BRG register The above applies when:
• CKDIR bit in U0MR register = 0 (internal clock)
• CKPOL bit in U0C0 register = 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock)
• U0IRS bit in U0C1 register = 0 (interrupt request generation when the transmit buffer is empty) Set to 0 by an interrupt request acknowledgement or by a program. Dummy data is set in U0TB register. Data transfer from U0TB register to UART0 transmit register 1/fEXT D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 Receive data taken in Data read from U0RB registerData transfer from UART0 receive register to U0RB register TI bit in U0C1 register TXEPT bit in U0C0 register IR bit in S0TIC register Set to 0 when an interrupt request is acknowledged or by a program.
• Receive Timing Example (External Clock Selected) RE bit in U0C1 register TE bit in U0C1 register TI bit in U0C1 register RI bit in U0C1 register IR bit in S0RIC register CLK0 RXD0 The above applies when:
• CKDIR bit in U0MR register = 1 (external clock)
• CKPOL bit in U0C0 register = 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock) The following should be met when “H” is applied to the CLK0 pin before receiving data:
• TE bit in U0C1 register = 1 (transmission enabled)
• RE bit in U0C1 register = 1 (reception enabled)
• Dummy data is written to U0TB register fEXT: Frequency of external clock

R8C/32A Group 21. Serial Interface (UART0) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 298 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

21.3.1 Polarity Select Function

Figure 21.4 shows the Transfer Clock Polarity. Use the CKPOL bit in the U0C0 register to select the transfer clock polarity. Figure 21.4 Transfer Clock Polarity

21.3.2 LSB First/MSB First Select Function

Figure 21.5 shows the Transfer Format. Use the UFORM bit in the U0C0 register to select the transfer format. Figure 21.5 Transfer Format CLK0 (1) D0TXD0

• CKPOL bit in U0C0 register = 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock) D1 D2 Notes: 1. The CLK0 pin level is high during no transfer. 2. The CLK0 pin level is low during no transfer. D3 D4 D5 D6 D7 D0RXD0 D1 D2 D3 D4 D5 D6 D7 CLK0 (2) D0TXD0 D1 D2 D3 D4 D5 D6 D7 D0RXD0 D1 D2 D3 D4 D5 D6 D7
• CKPOL bit in U0C0 register = 1 (transmit data output at the rising edge and receive data input at the falling edge of the transfer clock) CLK0 D0TXD0
• UFORM bit in U0C0 register = 0 (LSB first) (1) D1 D2 D3 D4 D5 D6 D7 D0RXD0 D1 D2 D3 D4 D5 D6 D7 CLK0 D7TXD0 D6 D5 D4 D3 D2 D1 D0 RXD0
• UFORM bit in U0C0 register = 1 (MSB first) (1) Note: 1. The above applies when: CKPOL bit in U0C0 register = 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock). D7 D6 D5 D4 D3 D2 D1 D0

R8C/32A Group 21. Serial Interface (UART0) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 299 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

21.3.3 Continuous Receive Mode

Continuous receive mode is selected by setting the U0RRM bit in the U0C1 register to 1 (continuous receive mode enabled). In this mode, reading the U0RB register sets the TI bit in the U0C1 register to 0 (data present in the U0TB register). If the U0RRM bit is set to 1, do not write dummy data to the U0TB register by a program.

R8C/32A Group 21. Serial Interface (UART0) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 300 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

21.4 Clock Asynchronous Serial I/O (UART) Mode

The UART mode allows data transmission and reception after setting the desire d bit rate and tran sfer data format. Table 21.5 lists the UART Mode Specifications. Table 21.6 lists the Registers Used and Settings in UART Mode. Note: 1. If an overrun error oc curs, the receive data (b0 to b8) in the U0RB register will be undefined. The IR bit in the S0RIC register remains unchanged. Table 21.5 UART M ode Specifications Item Specification Transfer data formats • Character bits (transfer data): Selectable among 7, 8 or 9 bits

• Start bit: 1 bit
• Parity bit: Selectable among odd, even, or none
• Stop bits: Selectable among 1 or 2 bits Transfer clocks • The CKDIR bit in the U0MR regist er is set to 0 (internal clock): fj/(16(n+1)) fj = f1, f8, f32, fC n = setting value in the U0BRG register: 00h to FFh
• The CKDIR bit is set to 1 (external clock): fEXT/(16(n+1)) fEXT: Input from the CLK0 pin, n = setting value in the U0BRG register: 00h to FFh Transmit start conditions • To start transmission, the following requirements must be met: - The TE bit in the U0C1 register is set to 1 (transmission enabled). - The TI bit in the U0C1 register is set to 0 (data present in the U0TB register). Receive start conditions • To start reception, the following requirements must be met: - The RE bit in the U0C1 register is set to 1 (reception enabled). - Start bit detection Interrupt request generation timing
• For transmission: One of the following can be selected. - The U0IRS bit is set to 0 (transmit buffer empty): When data is transferred from the U0TB register to the UART0 transmit register (at start of transmission). - The U0IRS bit is set to 1 (transfer completed): When data transmission from the UART0 transmit register is completed.
• For reception: When data is transferred from the UART0 receive register to the U0RB register (at completion of reception). Error detection • Overrun error (1) This error occurs if the serial interface starts receiving the next unit of data before reading the U0RB register and receive the bit one before the last stop bit of the next unit of data.
• Framing error This error occurs when the set number of stop bits is not detected.
• Parity error This error occurs when parity is enabled, and the number of 1’s in the parity and character bits do not match the set number of 1’s.
• Error sum flag This flag is set is set to 1 if an overrun, framing, or parity error occurs.

R8C/32A Group 21. Serial Interface (UART0) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 301 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Notes: 1. The bits used for transmission/receive data are as follows: - Bits b0 to b6 when transfer data is 7 bits long - Bits b0 to b7 when transfer data is 8 bits long - Bits b0 to b8 when transfer data is 9 bits long 2. The contents of the following are undefined: - Bits 7 and 8 when the transfer data is 7 bits long - Bit 8 when the transfer data is 8 bits long Table 21.6 Registers Used and Settings in UART Mode Register Bit Function U0TB b0 to b8 Set transmit data. (1) U0RB b0 to b8 Receive data can be read. (2) OER,FER,PER,SUM Error flag U0BRG b0 to b7 Set a bit rate. U0MR SMD2 to SMD0 Set to 100b when transfer data is 7 bits long. Set to 101b when transfer data is 8 bits long. Set to 110b when transfer data is 9 bits long. CKDIR Select the internal clock or external clock. STPS Select the stop bit. PRY, PRYE Select whether parity is included and whether odd or even. U0C0 CLK0, CLK1 Select the count source for the U0BRG register. TXEPT Transmit register empty flag NCH Select TXD0 pin output mode. CKPOL Set to 0. UFORM Select LSB first or MSB first when transfer data is 8 bits long. Set to 0 when transfer data is 7 bits or 9 bits long. U0C1 TE Set to 1 to en able transmission. TI Transmit buffer empty flag RE Set to 1 to enable reception. RI Receive complete flag U0IRS Select the UART0 transmit interrupt source. U0RRM Set to 0.

R8C/32A Group 21. Serial Interface (UART0) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 302 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Table 21.7 lists the I/O Pin Functions in UART Mode. After the UART0 operating mode is selected, the TXD0 pin outputs a “H” level until transfer starts. (If the NCH bit is set to 1 (N-channel open-drain output), this pin is in the high-impedance state.) Table 21.7 I/O Pin Functions in UART Mode Pin name Function Selection Method TXD0 (P1_4) Serial data output TXD0SEL0 bit in U0SR register = 1 For reception only: P1_4 can be used as a port by setting TXD0SEL0 bit = 0. RXD0 (P1_5) Serial data input RXD0SEL0 bit in U0SR register = 1 PD1_5 bit in PD1 register = 0 For transmission only: P1_5 can be used as a port by setting RXD0SEL0 bit = 0. CLK0 (P1_6) Programmable I/O port CLK0SEL0 bit in U0SR register = 0 (CLK0 pin not used) Transfer clock input CLK0SEL0 bit in U0SR register = 1 CKDIR bit in U0MR register = 1 PD1_6 bit in PD1 register = 0

R8C/32A Group 21. Serial Interface (UART0) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 303 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 21.6 Transmit Timing in UART Mode Data is set in U0TB register. Data is set in U0TB register. TC D1 D2 D3 D4 D5 D6 D7 P SPST D0 D1 D2 D3 D4 D5 D6 D7 P SPST D0 D1ST TC D1 D2 D3 D4 D5 D6 D7 D8 SP SPST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SPST D0 D1ST Transfer clock TE bit in U0C1 register TXD0 Set to 0 when an interrupt request is acknowledged or by a program.

• Transmit Timing Example When Transfer Data 8 Bits is Long (Parity Enabled, One Stop Bit) TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT fj: Frequency of U0BRG count source (f1, f8, f32, fC) fEXT: Frequency of U0BRG count source (external clock) n: Setting value in U0BRG register The above applies when:
• PRYE bit in U0MR register = 1 (parity enabled)
• STPS bit in U0MR register = 0 (one stop bit)
• U0IRS bit in U0C1 register = 1 (interrupt request generation when transmission is completed) Start bit Parity bit Pulsing stops because TE bit is set to 0. TXD0 Data transfer from U0TB register to UART0 transmit register TI bit in U0C1 register TXEPT bit in U0C0 register IR bit in S0TIC register Stop bit
• Transmit Timing Example When Transfer Data is 9 Bits Long (Parity Disabled, Two Stop Bits) Stop bit Stop bitStart bit Transfer clock TE bit in U0C1 register TI bit in U0C1 register TXEPT bit in U0C0 register IR bit in S0TIC register Data transfer from U0TB register to UART0 transmit register TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT fj: Frequency of U0BRG count source (f1, f8, f32, fC) fEXT: Frequency of U0BRG count source (external clock) n: Setting value in U0BRG register Set to 0 when an interrupt request is acknowledged or by a program. The above applies when:
• PRYE bit in U0MR register = 0 (parity disabled)
• STPS bit in U0MR register = 1 (two stop bits)
• U0IRS bit in U0C1 register = 0 (interrupt request generation when the transmit buffer is empty)

R8C/32A Group 21. Serial Interface (UART0) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 304 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 21.7 Receive Timing in UART Mode U0BRG output Set to 0 when an interrupt request is acknowledged or by a program.

• Receive Timing Example When Transfer Data is 8 Bits Long (Parity Disabled, One Stop Bit) The above applies when :
• PRYE bit in U0MR register = 0 (parity disabled)
• STPS bit in U0MR register = 0 (one stop bit) RE bit in U0C1 register Start bit Stop bit D0 D1 D7RXD0 Transfer clock “L” is determined. Receive data taken in Reception starts when a transfer clock is generated at the falling edge of the start bit. Data transfer from UART0 receive register to U0RB register RI bit in U0C1 register IR bit in S0RIC register

R8C/32A Group 21. Serial Interface (UART0) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 305 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

21.4.1 Bit Rate

In UART mode, the bit rate is the frequency divided by the U0BRG register and divided by 16. Figure 21.8 Formula for Calculating Setting Value in U0BRG Register Note: 1. For the high-speed on-chip oscillator, the correction value in the FRA4 register should be written into the FRA1 register and the correction value in the FRA5 register should be written into the FRA3 register. This applies when the high-speed on-chip oscillator is selected as the system clock and bits FRA22 to FRA20 in the FRA2 register are set to 000b (divide-by-2 mode). For the precision of the high-speed on-chip oscillator, refer to 32. Electrical Characteristics. Table 21.8 Bit Rate Setting Example in UART Mode (Internal Clock Selected) Bit Rate (bps) U0BRG Count Source System Clock = 20 MHz System Clock = 18.432 MHz (1) System Clock = 8 MHz U0BRG Setting Value Actual Time (bps) Setting Error (%) U0BRG Setting Value Actual Time (bps) Setting Error (%) U0BRG Setting Value Actual Time (bps) Setting Error (%) 115200 f1 10 (0Ah) 113636.36 -1.36 9 (09h) 115200.00 0.00 −− − UART mode

• Internal clock selected Setting value in U0BRG register = fj Bit Rate × 16 − 1 fj: Count source frequency of U0BRG register (f1, f8, f32, or fC)
• External clock selected fEXT Bit Rate × 16 − 1 fEXT: Count source frequency of U0BRG register (external clock) Setting value in U0BRG register =

R8C/32A Group 21. Serial Interface (UART0) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 306 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

21.5 Notes on Serial Interface (UART0)

• When reading data from the U0RB register either in clock synchronous serial I/O mode or in clock asynchronous serial I/O mode, always read data in 16-bit units. When the high-order byte of the U0RB register is read, bits PER and FER in the U0RB register and the RI bit in the U0C1 register are set to 0. To check receive errors, read the U0RB register and then use the read data. Program example to read the receive buffer register: MOV .W 00A6H,R0 ; Read the U0RB register
• When writing data to the U0TB register in clock asynch ronous serial I/O mode with 9-bit transfer data length, write data to the high-order byte first and then the low-order byte, in 8-bit units. Program example to write to the transmit buffer register: MOV .B #XXH,00A3H ; Write to the high-order byte of the U0TB register MOV .B #XXH,00A2H ; Write to the low-order byte of the U0TB register

R8C/32A Group 22. Serial Interface (UART2) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 307 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 22. Serial Interface (UART2) The serial interface consists of three channels, UART0 to UART2. This chapter describes the UART2.

22.1 Overview

UART2 has a dedicated timer to generate a transfer clock and operate independently. Figure 22.1 shows a UART2 Block Diagram. Figure 22.2 shows a Block Diagram of UART2 Transmit/Receive Unit. Table 22.1 lists the Pin Configuration of UART2. UART2 has the following modes:

• Clock synchronous serial I/O mode
• Clock asynchronous serial I/O mode (UART mode)
• Special mode 1 (I 2C mode)
• Multiprocessor communication function Figure 22.1 UART2 Block Diagram n: Setting value in U2BRG register RXD2 1/(n+1) 1/16 U2BRG register Clock synchronous type (internal clock selected) Clock synchronous type Clock synchronous type (internal clock selected) Clock synchronous type (external clock selected) CLK2 Clock source selection f32 CKDIR internal CKDIR external RTS2 CTS2 Transmit/ receive unit TXD2 CLK polarity switching circuit CTS/RTS disabled CTS/RTS disabled CTS/RTS selected Receive clock TXD polarity switching circuit (1) CLK1 to CLK0 = 00b = 01b = 10b CKPOL UART reception UART transmission Clock synchronous type CRS = 1 CRS = 0 RXD polarity switching circuit CRD = 0 VSS CKDIR = 0 CKDIR = 1 SMD2 to SMD0 = 010b, 100b, 101b, 110b = 001b CKDIR = 0 SMD2 to SMD0, CKDIR: Bits in U2MR register CLK1, CLK0, CKPOL, CRD, CRS: Bits in U2C0 register DF2EN: Bit in URXDF register CTS2/RTS2 DF2EN = 1 Digital filter DF2EN = 0 = 11b fC CKDIR = 1 = 010b, 100b, 101b, 110b = 001b Transmit clock CRD = 1 Reception control circuit Transmission control circuit

R8C/32A Group 22. Serial Interface (UART2) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 308 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 22.2 Block Diagram of UART2 Transmit/Receive Unit Table 22.1 Pin Configuration of UART2 Pin Name Assigned Pin I/O Function TXD2 P3_4 or P3_7 Output Serial data output RXD2 P3_4, P3_7, or P4_5 Input Serial data input CLK2 P3_5 I/O Transfer clock I/O CTS2 P3_3 Input Transmit control input RTS2 P3_3 Output Receive control input SCL2 P3_4, P3_7, or P4_5 I/O I2C mode clock I/O SDA2 P3_4 or P3_7 I/O I2C mode data I/O UART (8 bits) UART (9 bits) U2ERE = 1 PAR disabled PAR enabled PRYE = 0 PRYE = 1 2SP STPS = 1 1SP SP SP PAR UART UART (7 bits) UART (8 bits) UART (7 bits) UART (9 bits) Clock synchronous type Data bus low-order bits TXD2 UART2 transmit register D8 D7 D6 D5 D4 D3 D2 D1 D0 SP: Stop bit PAR: Parity bit SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR: Bits in U2MR register CLK1, CLK0, CKPOL, CRD, CRS: Bits in U2C0 register U2ERE: Bit in U2C1 register U2TB register UART (8 bits) UART (9 bits) I2C Clock synchronous type U2RB register UART2 receive register PAR 1SP PAR enabled PAR disabled UART UART (7 bits) UART (8 bits) UART (7 bits) I2C Clock synchronous type Clock synchronous type RXD2 Data bus high-order bits Logic inversion circuit + MSB/LSB conversion circuit D7 D6 D5 D4 D3 D2 D1 D0D80000000 Inverted Not inverted Error signal output circuit TXD data inversion circuit Error signal output enabled Error signal output disabled Inverted Not inverted Logic inversion circuit + MSB/LSB conversion circuit IOPOL = 0 RXD data inversion circuit STPS = 0 SP 2SP PRYE = 0 SMD = 0 IOPOL = 0 I2C I2C I2C Clock synchronous type IOPOL = 1 SP STPS = 1 PRYE = 1 UART (9 bits) I2C Clock synchronous type U2ERE = 0 IOPOL = 1 STPS = 0 SMD = 1

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22.2 Registers

22.2.1 UART2 Transmit/Recei ve Mode Register (U2MR)

22.2.2 UART2 Bit Rate Register (U2BRG)

Write to the U2BRG register while transmission and reception stop. Use the MOV instruction to write to this register. Set bits CLK1 to CLK0 in the U2C0 register before writing to the U2BRG register. Address 00A8h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol IOPOL PRYE PRY STPS CKDIR SMD2 SMD1 SMD0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 SMD0 Serial I/O mode select bit b2 b1 b0 0 0 0: Serial interface disabled 0 0 1: Clock synchronous serial I/O mode 0 1 0: I2C mode 1 0 0: UART mode, transfer data 7 bits long 1 0 1: UART mode, transfer data 8 bits long 1 1 0: UART mode, transfer data 9 bits long Other than above: Do not set. R/W b1 SMD1 R/W b2 SMD2 R/W b3 CKDIR Internal/external clock select bit 0: Internal clock 1: External clock R/W b4 STPS Stop bit length select bit 0: One stop bit 1: Two stop bits R/W b5 PRY Odd/even parity select bit Enabled when PRYE = 1 0: Odd parity 1: Even parity R/W b6 PRYE Parity enable bit 0: Parity disabled 1: Parity enabled R/W b7 IOPOL TXD, RXD I/O polarity switch bit 0: Not inverted 1: Inverted R/W Address 00A9h B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t XXXXXXXX Bit Function Setting Range R/W b7 to b0 If the setting value is n, U2BRG divides the count source by n+1. 00h to FFh W

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22.2.3 UART2 Transmit Bu ffer Register (U2TB)

Note: 1. Set bits b0 to b7 after setting the MPTB bit. Address 00ABh to 00AAh B i t b 7b 6b 5b 4b 3b 2b 1 b 0 A f t e r R e s e t XXXXXXX X Bit b15 b14 b13 b12 b11 b10 b9 b8 A f t e r R e s e t XXXXXXX X Bit Symbol Function R/W b0 — Transmit data (D7 to D0) W b1 — b2 — b3 — b4 — b5 — b6 — b7 — b8 MPTB Transmit data (D8) (1) [When the multiprocessor communication function is not used] Transmit data (D8) [When the multiprocessor communication function is used]

• To transfer an ID, set the MPTB bit to 1.
• To transfer data, set the MPTB bit to 0. W b9 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b10 — b11 — b12 — b13 — b14 — b15 —

R8C/32A Group 22. Serial Interface (UART2) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 311 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

22.2.4 UART2 Transmit/Receive Control Register 0 (U2C0)

Notes: 1. If bits CLK1 to CLK0 are switched, set the U2BRG register again. 2. The UFORM bit is enabled when bits SMD2 to SMD0 in the U2MR register are set to 001b (clock synchronous serial I/O mode), or set to 101b (UART mode, transfer data 8 bits long). Set the UFORM bit to 1 when bits SMD2 to SMD0 are set to 010b (I2C mode), and to 0 when bits SMD2 to SMD0 are set to 100b (UART mode, transfer data 7 bits long) or 110b (UART mode, transfer data 9 bits long). Address 00ACh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol UFORM CKPOL NCH CRD TXEPT CRS CLK1 CLK0 A f t e r R e s e t 00001000 Bit Symbol Bit Name Function R/W b0 CLK0 U2BRG count source select bit (1) b1 b0 0 0: f1 selected 0 1: f8 selected 1 0: f32 selected 1 1: fC selected R/W b1 CLK1 R/W b2 CRS CTS /RTS function select bit Enabled when CRD = 0 0: CTS function selected 1: RTS function selected R/W b3 TXEPT Transmit register empty flag 0: Da ta present in the transmit register (transmission in progress) 1: No data in the transmit register (transmission completed) R b4 CRD CTS/RTS disable bit 0: CTS /RTS function enabled 1: CTS/RTS function disabled R/W b5 NCH Data output select bit 0: Pins TXD2/SDA2, SCL2 set to CMOS output 1: Pins TXD2/SDA2, SCL2 set to N-channel open-drain output R/W b6 CKPOL CLK polarity select bit 0: Transmit data output at the falling edge and receive data input at the rising edge of the transfer clock 1: Transmit data output at the rising edge and receive data input at the falling edge of the transfer clock R/W b7 UFORM Transfer format select bit (2) 0: LSB first 1: MSB first R/W

R8C/32A Group 22. Serial Interface (UART2) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 312 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

22.2.5 UART2 Transmit/Receive Control Register 1 (U2C1)

Note: 1. The U2LCH bit is enabled when bits SMD2 to SMD0 in the U2MR register are se t to 001b (clock synchronous serial I/O mode), 100b (UART mode, transfer data 7 bits long), or 101b (UART mode, transfer data 8 bits long). Set the U2LCH bit to 0 when bits SMD2 to SMD0 are set to 010b (I2C mode) or 110b (UART mode, transfer data 9 bits long). Address 00ADh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol U2ERE U2LCH U2RRM U2IRS RI RE TI TE A f t e r R e s e t 00000010 Bit Symbol Bit Name Function R/W b0 TE Transmit enable bit 0: Transmission disabled 1: Transmission enabled R/W b1 TI Transmit buffer empty flag 0: Data present in the U2TB register 1: No data in the U2TB register R b2 RE Receive enable bit 0: Reception disabled 1: Reception enabled R/W b3 RI Receive complete flag 0: No data in the U2RB register 1: Data present in the U2RB register R b4 U2IRS UART2 transmit interrupt source select bit 0: Transmit buffer empty (TI = 1) 1: Transmission completed (TXEPT = 1) R/W b5 U2RRM UART2 continuous receive mode enable bit 0: Continuous receive mode disabled 1: Continuous receive mode enabled R/W b6 U2LCH Data logic select bit (1) 0: Not inverted 1: Inverted R/W b7 U2ERE Error signal output enable bit 0: Output disabled 1: Output enabled R/W

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22.2.6 UART2 Receive Buff er Register (U2RB)

Notes: 1. The ABT bit is set to 0 by writing 0 by a program. (Writing 1 has no effect.) 2. When bits SMD2 to SMD0 in the U2MR register are set to 000b (serial interface disabled) or the RE bit in the U2C1 register is set to 0 (reception disabled), all of bits SUM, PER, FER, and OER are set to 0 (no error). The SUM bit is set to 0 (no error) when all of bits PER, FER, and OER are set to 0 (no error). Bits PER and FER are set to 0 by reading the lower byte of the U2RB register. 3. These error flags are disabled when bits SMD2 to SMD0 in the U2MR register are set to 001b (clock synchronous serial I/O mode) or to 010b (I 2C mode). When read, the content is undefined. Address 00AFh to 00AEh B i t b 7b 6b 5b 4b 3b 2b 1 b 0 A f t e r R e s e t XXXXXXX X Bit b15 b14 b13 b12 b11 b10 b9 b8 Symbol SUM PER FER OER ABT — — MPRB A f t e r R e s e t XXXXXXX X Bit Symbol Bit Name Function R/W b0 — — Receive data (D7 to D0) R b1 — b2 — b3 — b4 — b5 — b6 — b7 — b8 MPRB — Receive data (D8) (2) [When the multiprocessor communication function is not used] Receive data (D8) [When the multiprocessor communication function is used]

• When the MPRB bit is set to 0, received D0 to D7 are data fields.
• When the MPRB bit is set to 1, received D0 to D7 are ID fields. R b9 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b10 — b11 ABT Arbitration lost detect flag (1) 0: Not detected (Won) 1: Detected (Lost) R b12 OER Overrun error flag (2) 0: No overrun error 1: Overrun error R b13 FER Framing error flag (2, 3) 0: No framing error 1: Framing error R b14 PER Parity error flag (2, 3) 0: No parity error 1: Parity error R b15 SUM Error sum flag (2, 3) 0: No error 1: Error R

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22.2.7 UART2 Digital Filter Func tion Select Register (URXDF)

Note: 1. The RXD2 digital filter can be used only in clock a synchronous serial I/O (UART) mode. When bits SMD2 to SMD0 in the U2MR register are set to 001b (clock synchronous serial I/O mode) or 010b (I 2C mode), set the DF2EN bit to 0 (RXD2 digital filter disabled).

22.2.8 UART2 Special Mode Register 5 (U2SMR5)

Note: 1. When the MP bit is set to 1 (multiprocessor communic ation enabled), the settings of bits PRY and PRYE in the U2MR register are disabled. If bits SMD2 to SMD0 in the U2MR register are set to 001b (clock synchronous serial I/O mode), set the MP bit to 0 (multiprocessor communication disabled). Address 00B0h B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b1 — b2 DF2EN RXD2 digital filter enable bit (1) 0: RXD2 digital filter disabled 1: RXD2 digital filter enabled R/W b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b4 — b5 — b6 — b7 — Address 00BBh B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 MP Multiprocessor communication enable bit 0: Multiprocessor communication disabled 1: Multiprocessor communication enabled (1) R/W b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b2 — b3 — b4 MPIE Multiprocessor communication control bit This bit is enabled when the MP bit is set to 1 (multiprocessor communication enabled). When the MPIE bit is set to 1, the following will result:

• Receive data in which the multiprocessor bit is 0 is ignored. Setting of the RI bit in the U2C1 register and bits OER and FER in the U2RB register to 1 is disabled.
• On receiving receive data in which the multiprocessor bit is 1, the MPIE bit is set to 0 and receive operation other than multiprocessor communication is performed. R/W b5 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b6 — b7 — Reserved bit Set to 0. R/W

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22.2.9 UART2 Special Mode Register 4 (U2SMR4)

Note: 1. This bit is set to 0 when each condition is generated.

22.2.10 UART2 Special Mode Register 3 (U2SMR3)

Notes: 1. Bits DL2 to DL0 are used to generate a delay in SDA2 output digitally in I 2C mode. In other than I 2C mode, set these bits to 000b (no delay). 2. The amount of delay varies with the load on pins SC L2 and SDA2. When an external clock is used, the amount of delay increases by about 100 ns. Address 00BCh B i t b 7b 6b 5b 4b 3b 2 b 1 b 0 Symbol SWC9 SCLHI ACKC ACKD STSPSEL STPREQ RSTAREQ STAREQ A f t e r R e s e t 000000 0 0 Bit Symbol Bit Name Function R/W b0 STAREQ Start condition generate bit (1) 0: Clear 1: Start R/W b1 RSTAREQ Restart condition generate bit (1) 0: Clear 1: Start R/W b2 STPREQ Stop condition generate bit (1) 0: Clear 1: Start R/W b3 STSPSEL SCL, SDA output select bit 0: Start and stop conditions not output 1: Start and stop conditions output R/W b4 ACKD ACK data bit 0: ACK 1: NACK R/W b5 ACKC ACK data output enable bit 0: Serial interface data output 1: ACK data output R/W b6 SCLHI SCL output stop enable bit 0: Disabled 1: Enabled R/W b7 SWC9 SCL wait bit 3 0: SCL “L” hold disabled 1: SCL “L” hold enabled R/W Address 00BDh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol DL2 DL1 DL0 — NODC — CKPH — A f t e r R e s e t 000X0X0X Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. — b1 CKPH Clock phase set bit 0: No clock delay 1: With clock delay R/W b2 — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. — b3 NODC Clock output select bit 0: CLK2 set to CMOS output 1: CLK2 set to N-channel open-drain output R/W b4 — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. — b5 DL0 SDA2 digital delay setup bit (1, 2) b7 b6 b5 0 0 0: No delay 0 0 1: 1 to 2 cycle(s) of U2BRG count source 0 1 0: 2 to 3 cycles of U2BRG count source 0 1 1: 3 to 4 cycles of U2BRG count source 1 0 0: 4 to 5 cycles of U2BRG count source 1 0 1: 5 to 6 cycles of U2BRG count source 1 1 0: 6 to 7 cycles of U2BRG count source 1 1 1: 7 to 8 cycles of U2BRG count source R/W b6 DL1 R/W b7 DL2 R/W

R8C/32A Group 22. Serial Interface (UART2) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 316 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

22.2.11 UART2 Special Mode Register 2 (U2SMR2)

22.2.12 UART2 Special Mo de Register (U2SMR)

Notes: 1. The BBS bit is set to 0 by writing 0 by a program (Writing 1 has no effect). 2. When a transfer begins, the SSS bit is set to 0 (not synchronized to RXD2). Address 00BEh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — SDHI SWC2 STAC ALS SWC CSC IICM2 A f t e r R e s e t X0000000 Bit Symbol Bit Name Function R/W b0 IICM2 I2C mode select bit 2 Refer to Table 22.12 I2C Mode Functions. R/W b1 CSC Clock synchronization bit 0: Disabled 1: Enabled R/W b2 SWC SCL wait output bit 0: Disabled 1: Enabled R/W b3 ALS SDA output stop bit 0: Disabled 1: Enabled R/W b4 STAC UART2 initialization bit 0: Disabled 1: Enabled R/W b5 SWC2 SCL wait output bit 2 0: Transfer clock 1: “L” output R/W b6 SDHI SDA output disable bit 0: Enabled 1: Disabled (high-impedance) R/W b7 — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. — Address 00BFh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — SSS ACSE ABSCS — BBS ABC IICM A f t e r R e s e t X0000000 Bit Symbol Bit Name Function R/W b0 IICM I2C mode select bit 0: Other than I 2C mode 1: I2C mode R/W b1 ABC Arbitration lost detect flag control bit 0: Update per bit 1: Update per byte R/W b2 BBS Bus busy flag (1) 0: Stop condition detected 1: Start condition detected (busy) R/W b3 — Reserved bit Set to 0. R/W b4 ABSCS Bus collision detect sampling clock select bit 0: Rising edge of transfer clock 1: Underflow signal of Timer RA (2) R/W b5 ACSE Auto clear function select bit of transmit enable bit 0: No auto clear function 1: Auto clear at bus collision occurrence R/W b6 SSS Transmit start condition sele ct bit 0: Not synchronized to RXD2 1: Synchronized to RXD2 (2) R/W b7 — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. —

R8C/32A Group 22. Serial Interface (UART2) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 317 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

22.2.13 UART2 Pin Select Register 0 (U2SR0)

The U2SR0 register selects which pin is assigned to the UART2 I/O. To use the I/O pin for UART2, set this register. Set the U2SR0 register before setting the UART2 associated registers. Also, do not change the setting value in this register during UART2 operation.

22.2.14 UART2 Pin Select Register 1 (U2SR1)

The U2SR1 register selects which pin is assigned to the UART2 I/O. To use the I/O pin for UART2, set this register. Set the U2SR1 register before setting the UART2 associated registers. Also, do not change the setting value in this register during UART2 operation. Address 018Ah B i t b 7 b 6b 5 b 4b 3b 2 b 1 b 0 Symbol — — RXD2SEL1 RXD2SEL0 — — TXD2SEL1 TXD2SEL0 A f t e r R e s e t 0 00 000 0 0 Bit Symbol Bit Name Function R/W b0 TXD2SEL0 TXD2/SDA2 pin select bit b1 b0 0 0: TXD2/SDA2 pin not used 0 1: P3_7 assigned 1 0: P3_4 assigned 1 1: Do not set. R/W b1 TXD2SEL1 R/W b2 — Reserved bit Set to 0. R/W b3 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b4 RXD2SEL0 RXD2/SCL2 pin select bit b5 b4 0 0: RXD2/SCL2 pin not used 0 1: P3_4 assigned 1 0: P3_7 assigned 1 1: P4_5 assigned R/W b5 RXD2SEL1 R/W b6 — Reserved bit Set to 0. R/W b7 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — Address 018Bh B i t b 7b 6b 5 b 4 b 3b 2 b 1 b 0 Symbol — — — CTS2SEL0 — — — CLK2SEL0 A f t e r R e s e t 000 0 00 0 0 Bit Symbol Bit Name Function R/W b0 CLK2SEL0 CLK2 pin select bit 0: CLK2 pin not used 1: P3_5 assigned R/W b1 — Reserved bit Set to 0. R/W b2 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b3 — b4 CTS2SEL0 CTS2 /RTS2 pin select bit 0: CTS2 /RTS2 pin not used 1: P3_3 assigned R/W b5 — Reserved bit Set to 0. R/W b6 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b7 — Reserved bit Set to 0. R/W

R8C/32A Group 22. Serial Interface (UART2) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 318 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

22.3 Clock Synchronous Serial I/O Mode

In clock synchronous serial I/O mode, data is transmitted and received using a transfer clock. Table 22.2 lists the Clock Synchronous Serial I/O Mode Sp ecifications. Table 22.3 lists the Registers Used and Settings in Clock Synchronous Serial I/O Mode. Notes: 1. When an external clock is selected, the requirements must be met in either of the following states: - The external clock is held high when the CKPOL bit in the U2C0 register is set to 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock) - The external clock is held low when the CKPOL bit in the U2C0 register is set to 1 (transmit data output at the rising edge and receive data input at the falling edge of the transfer clock) 2. If an overrun error occurs, the receive data in the U2RB register will be undefined. The IR bit in the S2RIC register does not change to 1 (interrupt requested). Table 22.2 Clock Synchronous Serial I/O Mode Specifications Item Specification Transfer data format Transfer data length: 8 bits Transfer clock • The CKDIR bit in the U2MR regist er is set to 0 (internal clock): fj/(2(n+1)) fj = f1, f8, f32, fC n = setting value in the U2BRG register: 00h to FFh

• The CKDIR bit is set to 1 (external clock): Input from the CLK2 pin Transmit/receive control Selectable from the CTS function, RTS function, or CTS/RTS function disabled. Transmit start conditions To start transmission, the following requirements must be met: (1)
• The TE bit in the U2C1 register is set to 1 (transmission enabled)
• The TI bit in the U2C1 register is set to 0 (data present in the U2TB register)
• If the CTS function is selected, input to the CTS2 pin = “L”. Receive start conditions To start reception, the following requirements must be met: (1)
• The RE bit in the U2C1 register is set to 1 (reception enabled).
• The TE bit in the U2C1 register is set to 1 (transmission enabled).
• The TI bit in the U2C1 register is set to 0 (data present in the U2TB register). Interrupt request generation timing For transmission, one of the following conditions can be selected.
• The U2IRS bit in the U2C1 register is set to 0 (transmit buffer empty): When data is transferred from the U2TB register to the UART2 transmit register (at start of transmission).
• The U2IRS bit is set to 1 (transmission completed): When data transmission from the UART2 transmit register is completed. For reception
• When data is transferred from the UART2 receive register to the U2RB register (at completion of reception). Error detection Overrun error (2) This error occurs if the serial interface starts receiving the next unit of data before reading the U2RB register and receives the 7th bit of the next unit of data. Selectable functions • CLK polarity selection Transfer data I/O can be selected to occur synchronously with the rising or falling edge of the transfer clock.
• LSB first, MSB first selection Whether transmitting or receiving data begi ns with bit 0 or begins with bit 7 can be selected.
• Continuous receive mode selection Reception is enabled immediately by reading the U2RB register.
• Serial data logic switching This function inverts the logic value of the transmit/receive data.

R8C/32A Group 22. Serial Interface (UART2) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 319 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Note: 1. Set the bits not listed in this table to 0 when writing to the above registers in clock synchronous serial I/O mode. Table 22.3 Registers Used and Settings in Clock Synchronous Serial I/O Mode Register Bit Function U2TB (1) b0 to b7 Set transmit data. U2RB (1) b0 to b7 Receive data can be read. OER Overrun error flag U2BRG b0 to b7 Set a bit rate. U2MR (1) SMD2 to SMD0 Set to 001b. CKDIR Select the internal clock or external clock. IOPOL Set to 0. U2C0 CLK1, CLK0 Select the count source for the U2BRG register. CRS Select either CTS or RTS to use functions. TXEPT Transmit register empty flag CRD Enable or disable the CTS or RTS function. NCH Select TXD2 pin output mode. CKPOL Select the transfer clock polarity. UFORM Select LSB first or MSB first. U2C1 TE Set to 1 to enable transmission/reception. TI Transmit buffer empty flag RE Set to 1 to enable reception. RI Receive complete flag U2IRS Select the source of UART2 transmit interrupt. U2RRM Set to 1 to use continuous receive mode. U2LCH Set to 1 to use inverted data logic. U2ERE Set to 0. U2SMR b0 to b7 Set to 0. U2SMR2 b0 to b7 Set to 0. U2SMR3 b0 to b2 Set to 0. NODC Select clock output mode. b4 to b7 Set to 0. U2SMR4 b0 to b7 Set to 0. URXDF DF2EN Set to 0. U2SMR5 MP Set to 0.

R8C/32A Group 22. Serial Interface (UART2) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 320 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Table 22.4 lists the Pin Functions in Clock Synchronous Serial I/O Mode (Multiple Transfer Clock Output Pin Function Not Selected). Note that for a period from when UART2 operating mode is selected to when transfer starts, the TXD2 pin outputs a “H” level. (When N-channel open-drain output is selected, this pin is in the high-impedance state.) Figure 22.3 shows the Transmit and Receive Timing in Clock Synchronous Serial I/O Mode. Table 22.4 Pin Functions in Clock Synchronous Seri al I/O Mode (Multiple Transfer Clock Output Pin Function Not Selected) Pin Name Function Selection Method TXD2 (P3_4 or P3_7) Serial data output • When TXD2 (P3_4) Bits TXD2SEL1 to TXD2SEL0 in U2SR0 register = 10b (P3_4)

• When TXD2 (P3_7) Bits TXD2SEL1 to TXD2SEL0 in U2SR0 register = 01b (P3_7)
• For reception only: P3_4 and P3_7 can be used as ports by setting TXD2SEL1 to TXD2SEL0 to 00b. RXD2 (P3_4, P3_7, or P4_5) Serial data input • When RXD2 (P3_4) Bits RXD2SEL1 to RXD2SEL0 in U2SR0 register = 01b (P3_4) PD3_4 bit in PD3 register = 0
• When RXD2 (P3_7) Bits RXD2SEL1 to RXD2SEL0 in U2SR0 register = 10b (P3_7) PD3_7 bit in PD3 register = 0
• When RXD2 (P4_5) Bits RXD2SEL1 to RXD2SEL0 in U2SR0 register = 11b (P4_5) PD4_5 bit in PD4 register = 0
• For transmission only: P3_4, P3_7, and P4_5 can be used as ports by setting RXD2SEL1 to RXD2SEL0 to 00b. CLK2 (P3_5) Transfer clock output CLK2SEL0 bit in U2SR1 register = 1 CKDIR bit in U2MR register = 0 Transfer clock input CLK2SEL0 bit in U2SR1 register = 1 CKDIR bit in U2MR register = 1 PD3_5 bit in PD3 register = 0 CTS2 /RTS2 (P3_3) CTS input CTS2SEL0 bit in U2SR1 register = 1 CRD bit in U2C0 register = 0 CRS bit in U2C0 register = 0 PD3_3 bit in PD3 register = 0 RTS output CTS2SEL0 bit in U2SR1 register = 1 CRD bit in U2C0 register = 0 CRS bit in U2C0 register = 1 I/O port CTS2SEL0 bit in U2SR1 register = 0

R8C/32A Group 22. Serial Interface (UART2) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 321 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 22.3 Transmit and Receive Timing in Clock Synchronous Serial I/O Mode D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 TC TCLK Pulsing stops because TE bit is set to 0. Data is set in U2TB register. Data transfer from U2TB register to UART2 transmit register TC = TCLK = 2(n+1)/fj fj: Frequency of U2BRG count source (f1, f8, f32, fC) n: Setting value in U2BRG register Transfer clock TE bit in U2C1 register TI bit in U2C1 register CLK2 TXD2 TXEPT flag in U2C0 register “H” “L” CTS2 IR bit in S2TIC register 0 Set to 0 when an interrupt request is acknowledged or by a program. Pulsing stops because “H” is applied to CTS2. 1/fEXT Dummy data is set in U2TB register. CLK2 RXD2 RTS2 “H” “L” RE bit in U2C1 register 0 Data transfer from U2TB register to UART2 transmit register Data read from U2RB register fEXT: Frequency of external clock Make sure the following conditions are met when the CLK2 pin input before receiving data is high:

• TE bit in U2C0 register = 1 (transmission enabled)
• RE bit in U2C1 register = 1 (reception enabled)
• Dummy data is written to U2TB register Data transfer from UART2 receive register to U2RB register Set to 0 when an interrupt request is acknowledged or by a program. D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D0 D1 D2 D3 D4 D5D7D6 TE bit in U2C1 register TI bit in U2C1 register OER flag in U2RB register IR bit in S2RIC register RI bit in U2C1 register The above applies when:
• CKDIR bit in U2MR register = 0 (internal clock)
• CRD bit in U2C0 register = 0 (CTS/RTS function enabled), CRS bit = 0 (CTS function selected)
• CKPOL bit in U2C0 register = 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock)
• U2IRS bit in U2C1 register = 0 (interrupt request generation when the U2TB register is empty) The above applies when:
• CKDIR bit in U2MR register = 1 (external clock)
• CRD bit in U2C0 register = 0 (CTS/RTS function enabled), CRS bit = 1 (RTS function selected)
• CKPOL bit in U2C0 register = 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock) Received data taken in “L” is applied when U2RB register is read. (1) Transmit Timing Example (Internal Clock Selected) (2) Receive Timing Example (External Clock Selected)

R8C/32A Group 22. Serial Interface (UART2) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 322 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

22.3.1 Measure for Dealing with Communication Errors

If a communication error occurs while transmitting or re ceiving in clock synchronous serial I/O mode, follow the procedures below:

• Resetting the U2RB register (1) Set the RE bit in the U2C1 register to 0 (reception disabled). (2) Set bits SMD2 to SMD0 in the U2MR re gister to 000b (serial interface disabled). (3) Set bits SMD2 to SMD0 in the U2MR register to 001b (clock synchronous serial I/O mode). (4) Set the RE bit in the U2C1 register to 1 (reception enabled).
• Resetting the U2TB register (1) Set bits SMD2 to SMD0 in the U2MR re gister to 000b (serial interface disabled). (2) Set bits SMD2 to SMD0 in the U2MR register to 001b (clock synchronous serial I/O mode). (3) Write 1 to the TE bit in the U2C1 register (transmi ssion enabled), regardless of the TE bit value in the U2C2 register.

22.3.2 CLK Polarity Select Function

Use the CKPOL bit in the U2C0 regist er to select the transfer clock po larity. Figure 22.4 shows the Transfer Clock Polarity. Figure 22.4 Transfer Clock Polarity (2) CKPOL bit in U2C0 register = 1 (transmit data output at the rising edge and receive data input at the falling edge of the transfer clock) D1 D2 D3 D4 D5 D6 D7 D1 D2 D3 D4 D5 D6 D7 TXD2 RXD2 CLK2 (1) CKPOL bit in U2C0 register = 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock) D1 D2 D3 D4 D5 D6 D7D0 D1 D2 D3 D4 D5 D6 D7D0 TXD2 RXD2 CLK2 The above applies when:

• UFORM bit in U2C0 register = 0 (LSB first)
• U2LCH bit in U2C1 register = 0 (not inverted) “H” output from CLK2 pin during no transfer “H” output from CLK2 pin during no transfer

R8C/32A Group 22. Serial Interface (UART2) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 323 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

22.3.3 LSB First/MSB First Select Function

Use the UFORM bit in the U2C0 register to select the transfer format. Figure 22.5 shows the Transfer Format. Figure 22.5 Transfer Format

22.3.4 Continuous Receive Mode

In continuous receive m ode, receive operation is enable d when the receive buffer re gister is read. It is not necessary to write dummy data to the transmit buffer register to enable receive operation in this mode. However, a dummy read of the receive buffer register is required when starting the operating mode. When the U2RRM bit in the U2C1 register is set to 1 (continuous receive mode), the TI bit in the U2C1 register is set to 0 (data present in the U2TB register) by reading the U2RB register. If the U2RRM bit is set to 1, do not write dummy data to the U2TB register by a program. (1) UFORM Bit in U2C0 Register = 0 (LSB first) D1 D2 D3 D4 D5 D6 D7D0 D1 D2 D3 D4 D5 D6 D7D0 TXD2 RXD2 CLK2 (2) UFORM Bit in U2C0 Register = 1 (MSB first) D6 D5 D4 D3 D2 D1 D0D7 D6 D5 D4 D3 D2 D1 D0D7 TXD2 RXD2 CLK2 The above applies when:

• CKPOL bit in U2C0 register = 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock)
• U2LCH bit in U2C1 register = 0 (not inverted)

R8C/32A Group 22. Serial Interface (UART2) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 324 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

22.3.5 Serial Data Logi c Switching Function

If the U2LCH bit in the U2C1 register is set to 1 (inver ted), the data written to the U2TB register has its logic inverted before being transmitted. Si milarly, the received data has its logi c inverted when read from the U2RB register. Figure 22.6 shows the Serial Data Logic Switching. Figure 22.6 Serial Data Logic Switching

22.3.6 CTS /RTS Function

The CTS function is used to start tr ansmit and receive op eration when “L” is applied to the CTS2 /RTS2 pin. Transmit and receive operation begins when the CTS2 /RTS2 pin is held low. If the “L” signal is switched to “H” during a transmit or receive operation, the operation stops before the next data. For the RTS function, the CTS2 /RTS2 pin outputs “L” when the MCU is ready for a receive operation. The output level goes high at the first falling edge of the CLK2 pin.

• The CRD bit in the U2C0 register = 1 (CTS /RTS function disabled) The CTS2/RTS2 pin operates as the programmable I/O function.
• The CRD bit = 0, CRS bit = 0 (CTS function selected) The CTS2/RTS2 pin operates as the CTS function.
• The CRD bit = 0, CRS bit = 1 (RTS function selected) The CTS2/RTS2 pin operates as the RTS function. D0 D1 D2 D3 D4 D5 D6 D7 Transfer Clock TXD2 (not inverted) (1) U2LCH Bit in U2C1 Register = 0 (not inverted) (2) U2LCH Bit in U2C1 Register = 1 (inverted) The above applies when:
• CKPOL bit in U2C0 register = 0 (transmit data output at the falling edge of the transfer clock)
• UFORM bit in U2C0 register = 0 (LSB first) “L” “H” “L” D0 D1 D2 D3 D4 D5 D6 D7 Transfer Clock TXD2 (inverted) “H” “L” “H” “L” “H”

R8C/32A Group 22. Serial Interface (UART2) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 325 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

22.4 Clock Asynchronous Serial I/O (UART) Mode

In UART mode, data is transmitted and received after set ting the desired bit rate and transfer data format. Table 22.5 lists the UART Mode Specifications. Table 22.6 lists the Registers Used and Settings in UART Mode. Notes: 1. If an overrun error occurs, the receive data in the U2RB register will be undefined. The IR bit in the S2RIC register remains unchanged. 2. The timing at which the framing error flag and the parity error flag are set is detected when data is transferred from the UART2 receive register to the U2RB register. Table 22.5 UART M ode Specifications Item Specification Transfer data format • Character bits (transfer data): Selectable from 7, 8, or 9 bits

• Start bit:1 bit
• Parity bit: Selectable from odd, even, or none
• Stop bits: Selectable from 1 bit or 2 bits Transfer clock • The CKDIR bit in the U2MR register is set to 0 (internal clock): fj/(16(n + 1)) fj = f1, f8, f32, fC n = setting value in the U2BRG register: 00h to FFh
• The CKDIR bit is set to 1 (external clock): fEXT/(16(n + 1)) fEXT: Input from CLK2 pin n: Setting value in the U2BRG register: 00h to FFh Transmit/receive control Selectable from the CTS function, RTS function, or CTS/RTS function disabled. Transmit start conditions To start transmission, the following requirements must be met:
• The TE bit in the U2C1 register is set to 1 (transmission enabled).
• The TI bit in the U2C1 register is set to 0 (data present in the U2TB register).
• If the CTS function is selected, input to the CTS2 pin = “L”. Receive start conditions To start reception, the following requirements must be met:
• The RE bit in the U2C1 register is set to 1 (reception enabled).
• Start bit detection Interrupt request generation timing For transmission, one of the following conditions can be selected.
• The U2IRS bit in the U2C1 register is set to 0 (transmit buffer empty): When data is transferred from the U2TB register to the UART2 transmit register (at start of transmission).
• The U2IRS bit is set to 1 (transmission completed): When data transmission from the UART2 transmit register is completed. For reception
• When data is transferred from the UART2 receive register to the U2RB register (at completion of reception). Error detection • Overrun error (1) This error occurs if the serial interface starts receiving the next unit of data before reading the U2RB register and receives t he bit one before the last stop bit of the next unit of data.
• Framing error (2) This error occurs when the set number of stop bits is not detected.
• Parity error (2) This error occurs when if parity is enabled, the number of 1’s in the parity and character bits does not match the set number of 1’s.
• Error sum flag This flag is set to 1 if an overrun, framing, or parity error occurs. Selectable functions • LSB first, MSB first selection Whether transmitting or receiving data begins with bit 0 or begins with bit 7 can be selected.
• Serial data logic switching This function inverts the logic of the transmit/receive data. The start and stop bits are not inverted.
• TXD, RXD I/O polarity switching This function inverts the polarities of the TXD pin output and RXD pin input. The logic levels of all I/O data are inverted.
• RXD2 digital filter selection The RXD2 input signal can be enabled or disabled.

R8C/32A Group 22. Serial Interface (UART2) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 326 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Notes: 1. The bits used for transmit/receive data are as follows: - Bits b0 to b6 when transfer data is 7 bits long - Bits b0 to b7 when transfer data is 8 bits long - Bits b0 to b8 when transfer data is 9 bits long 2. The contents of the following are undefined: - Bits b7 and b8 when transfer data is 7 bits long - Bit b8 when transfer data is 8 bits long Table 22.6 Registers Used and Settings in UART Mode Register Bit Function U2TB b0 to b8 Set transmit data. (1) U2RB b0 to b8 Receive data can be read. (1, 2) OER, FER, PER, SUM Error flag U2BRG b0 to b7 Set a bit rate. U2MR SMD2 to SMD0 Set to 100b when transfer data is 7 bits long. Set to 101b when transfer data is 8 bits long. Set to 110b when transfer data is 9 bits long. CKDIR Select the internal clock or external clock. STPS Select the stop bit. PRY, PRYE Select whether parity is included and whether odd or even. IOPOL Select the TXD/RXD I/O polarity. U2C0 CLK0, CLK1 Select the count source for the U2BRG register. CRS Select CTS or RTS to use functions. TXEPT Transmit register empty flag CRD Enable or disable the CTS or RTS function. NCH Select TXD2 pin output mode. CKPOL Set to 0. UFORM Select LSB first or MSB first when transfer data is 8 bits long. Set to 0 when transfer data is 7 or 9 bits long. U2C1 TE Set to 1 to enable transmission. TI Transmit buffer empty flag RE Set to 1 to enable reception. RI Receive complete flag U2IRS Select the UART2 transmit interrupt source. U2RRM Set to 0. U2LCH Set to 1 to use inverted data logic. U2ERE Set to 0. U2SMR b0 to b7 Set to 0. U2SMR2 b0 to b7 Set to 0. U2SMR3 b0 to b7 Set to 0. U2SMR4 b0 to b7 Set to 0. URXDF DF2EN Select the digital filter disabled or enabled. U2SMR5 MP Set to 0.

R8C/32A Group 22. Serial Interface (UART2) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 327 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Table 22.7 lists the I/O Pin Functions in UART Mode. Note that for a period from when th e UART2 operating mode is selected to when transfer starts, the TXD2 pin outputs “H”. (When N-channel open-drain output is selected, this pin is in the high-impedance state.) Figure 22.7 shows the Transmit Timing in UART Mode. Figure 22.8 shows the Receive Timing in UART Mode. Table 22.7 I/O Pin Functions in UART Mode Pin Name Function Selection Method TXD2 (P3_4 or P3_7) Serial data output • When TXD2 (P3_4) Bits TXD2SEL1 to TXD2SEL0 in U2SR0 register = 10b (P3_4)

• When TXD2 (P3_7) Bits TXD2SEL1 to TXD2SEL0 in U2SR0 register = 01b (P3_7)
• For reception only: P3_4 and P3_7 can be used as ports by setting TXD2SEL1 to TXD2SEL0 to 00b. RXD2 (P3_4, P3_7, or P4_5) Serial data input • When RXD2 (P3_4) Bits RXD2SEL1 to RXD2SEL0 in U2SR0 register = 01b (P3_4)
• When RXD2 (P3_7) Bits RXD2SEL1 to RXD2SEL0 in U2SR0 register = 10b (P3_7) PD3_7 bit in PD3 register = 0
• When RXD2 (P4_5) Bits RXD2SEL1 to RXD2SEL0 in U2SR0 register = 11b (P4_5) PD4_5 bit in PD4 register = 0
• For transmission only: P3_4, P3_7, and P4_5 can be used as ports by setting RXD2SEL1 to RXD2SEL0 to 00b. CLK2 (P3_5) I/O port CLK2SEL0 bit in U2SR1 register = 0 Transfer clock input CLK2SEL0 bit in U2SR1 register = 1 CKDIR bit in U2MR register = 1 PD3_5 bit in PD3 register = 0 CTS2 /RTS2 (P3_3) CTS input CTS2SEL0 bit in U2SR1 register = 1 CRD bit in U2C0 register = 0 CRS bit in U2C0 register = 0 PD3_3 bit in PD3 register = 0 RTS input CTS2SEL0 bit in U2SR1 register = 1 CRD bit in U2C0 register = 0 CRS bit in U2C0 register = 1 I/O port CTS2SEL0 bit in U2SR1 register = 0

R8C/32A Group 22. Serial Interface (UART2) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 328 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 22.7 Transmit Timing in UART Mode D0 D1 D2 D3 D4 D5 D6 D7ST P Parity bit TXD2 CTS2 The above applies when:

• PRYE bit in U2MR register = 1 (parity enabled)
• STPS bit in U2MR register = 0 (one stop bit)
• CRD bit in U2C0 register = 0 (CTS/RTS function enabled), CRS bit = 0 (CTS function selected)
• U2IRS bit in U2C1 register = 1 (interrupt request generation when transmission is completed) “H” TC = 16(n + 1)/fj or 16(n + 1)/fEXT fj: Frequency of U2BRG count source (f1, f8, f32, fC) fEXT: Frequency of U2BRG count source (external clock) n: Setting value in U2BRG Set to 0 when an interrupt request is acknowledged or by a program. D0 D1 D2 D3 D4 D5 D6 D7ST P D0 D1ST TXD2 The above applies when:
• PRYE bit in U2MR register = 0 (parity disabled)
• STPS bit in U2MR register = 1 (two stop bits)
• CRD bit in U2C0 register = 1 (CTS/RTS function disabled)
• U2IRS bit in U2C1 register = 0 (interrupt request generation when the transmit buffer is empty) Transfer clock TC Set to 0 when an interrupt request is acknowledged or by a program. TC Transfer clock Stop bit Data is set in U2TB register. Start bit D0 D1 D2 D3 D4 D5 D6 D7ST D8 D0 D1 D2 D3 D4 D5 D6 D7ST D8 D0 D1STSP SP Stop bit The transfer clock stops once because “H” is applied to CTS pin when the stop bit is verified. The transfer clock resumes running immediately after “L” is applied to CTS pin. Data is set in U2TB register. SP Data transfer from U2TB register to UART2 transmit register Stop bit TE bit in U2C1 register TI bit in U2C1 register TXEPT bit in U2C0 register IR bit in S2TIC register TE bit in U2C1 register TI bit in U2C1 register TXEPT bit in U2C0 register IR bit in S2TIC register “L” Pulsing stops because TE bit is set to 0. SPSP Start bit SP TC = 16(n + 1)/fj or 16(n + 1)/fEXT fj: Frequency of U2BRG count source (f1, f8, f32, fC) fEXT: Frequency of U2BRG count source (external clock) n: Setting value in U2BRG (1) Transmit Timing Example When Transfer Data 8 Bits is Long (Parity Enabled, One Stop Bit) (2) Transmit Timing Example When Transfer Data 9 Bits is Long (Parity Disabled, Two Stop Bits) Data transfer from U2TB register to UART2 transmit register

R8C/32A Group 22. Serial Interface (UART2) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 329 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 22.8 Receive Timing in UART Mode

22.4.1 Bit Rate

In UART mode, the bit rate is the frequency divided by the U2BRG register divided by 16. Table 22.8 lists the Bit Rate Setting Example in UART Mode (Internal Clock Selected). Note: 1. For the high-speed on-chip oscillator, the correction value in the FRA4 register should be written into the FRA1 register and the correction value in the FRA5 register should be written into the FRA3 register. This applies when the high-speed on-chip oscillator is selected as the system clock and bits FRA22 to FRA20 in the FRA2 register are set to 000b (divide-by-2 mode). For the precision of the high-speed on-chip oscillator, refer to 32. Electrical Characteristics. Table 22.8 Bit Rate Setting Example in UART Mode (Internal Clock Selected) Bit Rate (bps) U2BRG Count Source System Clock = 20 MHz System Clock = 18.432 MHz (1) System Clock = 8 MHz U2BRG Setting Value Actual Time (bps) Setting Error (%) U2BRG Setting Value Actual Time (bps) Setting Error (%) U2BRG Setting Value Actual Time (bps) Setting Error (%) 115200 f1 10 (0Ah) 113636.36 -1.36 9 (09h) 115200.00 0.00 −− − D0 D1 D7Start bit Reception starts when a transfer clock is generated at the falling edge of the start bit. “L” is determined. Receive data taken in U2BRG count source RE bit in U2C1 register RXD2 Transfer clock RI bit in U2C1 register RTS2 Stop bit “H” “L” The above applies when:

• PRYE bit in U2MR register = 0 (parity disabled)
• STPS bit in U2MR register = 0 (one stop bit)
• CRD bit in U2C0 register = 0 (CTS2/RTS2 function enabled), CRS bit = 1 (RTS2 function selected) IR bit in S2RIC register 0 Set to 0 when an interrupt request is acknowledged or by a program. Data transfer from UART2 receive register to U2RB register Receive Timing Example When Transfer Data 8 Bits is Long (Parity Disabled, One Stop Bit)

R8C/32A Group 22. Serial Interface (UART2) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 330 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

22.4.2 Measure for Dealing with Communication Errors

If a communication error occurs while transmitting or receiving in UART mode, follow the procedures below:

• Resetting the U2RB register (1) Set the RE bit in the U2C1 register to 0 (reception disabled). (2) Set the RE bit in the U2C1 register to 1 (reception enabled).
• Resetting the U2TB register (1) Set bits SMD2 to SMD0 in the U2MR re gister to 000b (serial interface disabled). (2) Reset bits SMD2 to SMD0 in the U2MR register to 001b, 101b, and 110b. (3) Write 1 to the TE bit in the U2C1 register (transmi ssion enabled), regardless of the TE bit value in the U2C1 register.

22.4.3 LSB First/MSB First Select Function

As shown in Figure 22.9, use the UFORM bit in the U2C0 register to select the transfer format. This function is enabled when transfer data is 8 bits long. Figure 22.9 shows the Transfer Format. Figure 22.9 Transfer Format (1) UFORM Bit in U2C0 Register = 0 (LSB first) D1 D2 D3 D4 D5 D6 SPD0 D1 D2 D3 D4 D5 D6 SPD0 TXD2 RXD2 CLK2 (2) UFORM Bit in U2C0 Register = 1 (MSB first) D6 D5 D4 D3 D2 D1 D0D7 TXD2 RXD2 CLK2 The above applies when:

• CKPOL bit in U2C0 register = 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock)
• U2LCH bit in U2C1 register = 0 (not inverted)
• STPS bit in U2MR register = 0 (one stop bit)
• PRYE bit in U2MR register = 1 (parity enabled) ST ST D7 P D7 P SP SP ST ST P P D6 D5 D4 D3 D2 D1 D0D7 ST: Start bit P: Parity bit SP: Stop bit

R8C/32A Group 22. Serial Interface (UART2) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 331 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

22.4.4 Serial Data Logi c Switching Function

The data written to the U2TB register has its logic in verted before being transmitted. Similarly, the received data has its logic inverted when read from the U2RB register. Figure 22.10 shows the Serial Data Logic Switching. Figure 22.10 Serial Data Logic Switching

22.4.5 TXD and RXD I/O Po larity Inverse Function

This function inverts the polarities of the TXD2 pin output and RXD2 pin input. The logic levels of all I/O data (including bits for start, stop, and parity) are inverted. Figure 22.11 shows the TXD and RXD I/O Inversion. Figure 22.11 TXD and RXD I/O Inversion D0 D1 D2 D3 D4 D5 D6 D7 P SPST SPST D3 D4 D5 D6 D7 PD0 D1 D2 Transfer clock TXD2 (not inverted) TXD2 (inverted) “H” “L” “H” “L” “H” “L” (1) U2LCH bit in U2C1 Register = 0 (not inverted) Transfer clock “H” “L” (2) U2LCH Bit in U2C1 Register = 1 (inverted) ST: Start bit P: Parity bit SP: Stop bitThe above applies when:

• CKPOL bit in U2C0 register = 0 (transmit data output at the falling edge of the transfer clock)
• UFORM bit in U2C0 register = 0 (LSB first)
• STPS bit in U2MR register = 0 (one stop bit)
• PRYE bit in U2MR register = 1 (parity enabled) D0 D1 D2 D3 D4 D5 D6 D7 P SPST SPST D3 D4 D5 D6 D7 PD0 D1 D2 Transfer clock TXD2 (not inverted) TXD2 (not inverted) “H” “L” “H” “L” “H” “L” (1) IOPOL Bit in U2MR Register = 0 (not inverted) The above applies when:
• UFORM bit in U2C0 register = 0 (LSB first)
• STPS bit in U2MR register = 0 (one stop bit)
• PRYE bit in U2MR register = 1 (parity enabled) Transfer clock “H” “L” (2) IOPOL Bit in U2MR Register = 1 (inverted) D0 D1 D2 D3 D4 D5 D6 D7 P SPSTRXD2 (not inverted) “H” “L” SPST D3 D4 D5 D6 D7 PD0 D1 D2RXD2 (not inverted) “H” “L” ST: Start bit P: Parity bit SP: Stop bit

R8C/32A Group 22. Serial Interface (UART2) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 332 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

22.4.6 CTS /RTS Function

The CTS function is used to start transmit operation when “L” is applied to the CTS2 /RTS2 pin. Transmit operation begins when the CTS2 /RTS2 pin is held low. If the “L” signal is switched to “H” during transmit operation, the operation stops after the ongoing transmit/receive operation is completed. When the RTS function is used, the CTS2 /RTS2 pin outputs “L” when the MCU is ready for a receive operation. The output level goes high at the first falling edge of the CLK2 pin.

• The CRD bit in the U2C0 register = 1 (CTS/RTS function disabled) The CTS2/RTS2 pin operates as the programmable I/O function.
• The CRD bit = 0, CRS bit = 0 (CTS function selected) The CTS2/RTS2 pin operates as the CTS function.
• The CRD bit = 0, CRS bit = 1 (RTS function selected) The CTS2/RTS2 pin operates as the RTS function.

22.4.7 RXD2 Digital Filter Select Function

When the DF2EN bit in the URXDF register is set to 1 (RXD2 digital filer enabled), the RXD2 input signal is loaded internally via the digital filter circuit for noi se reduction. The noise canceller consists of three cascaded latch circuits and a match detection circuit. The RXD2 input signal is sampled on the internal basic clock with a frequency 16 times the bit rate. It is recognized as a si gnal and the level is passed forward to the next circuit when three latch outputs match. When the outputs do not match, the previous value is retained. In other words, when the level is changed within three clocks, the change is recognized as not a signal but noise. Figure 22.12 shows a Block Diagram of RXD2 Digital Filter Circuit. Figure 22.12 Block Diagram of RXD2 Digital Filter Circuit C DQ Latch C DQ Latch Match detection circuit RXD2 input signal Sampling clock Sampling clock URXDF register (DF2EN bit) C DQ Latch Internal RXD2 input signal Internal basic clock period (1) Note: 1. When the CKDIR bit in the U2MR register is 0 (interna l clock), the internal basic clock is set to fj/(n+1) (fj = f1, f8, f32, fC; n = setting value in the U2BRG register). When the CKDIR bit in the U2MR register is 1 (external clock), the internal basic clock is set to fEXT/(n+1) (fEXT is input from the CLK2 pin. n = setting value in the U2BRG register).

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22.5 Special Mode 1 (I 2C Mode)

I2C mode is provided for use as a simplified I 2C interface compatible mode. Table 22.9 lists the I 2C Mode Mode Functions, Figure 22.13 shows an I 2C Mode Block Diagram, and Figure 22.14 shows the Transfer to U2RB Register and Interrupt Timing. As shown in Table 22.12, the MCU is placed in I2C mode by setting bits SMD2 to SMD0 to 010b and the IICM bit to 1. Because SDA2 transmit output has a delay circui t attached, SDA2 out put does not change state until SCL2 goes low and remains stably low. Notes: 1. when an external clock is selected, the requirements must be met while the external clock is held high. 2. If an overrun error occurs, the received data in the U2RB register will be undefined. The IR bit in the S2RIC register remains unchanged. Table 22.9 I 2C Mode Specifications Item Specification Transfer data format Transfer data length: 8 bits Transfer clock • Master mode The CKDIR bit in the U2MR register is set to 0 (internal clock): fj/(2(n+1)) fj = f1, f8, f32, fC n = setting value in the U2BRG register: 00h to FFh

• Slave mode The CKDIR bit is set to 1 (external clock): Input from the SCL2 pin Transmit start conditions To start transmission, the following requirements must be met: (1)
• The TE bit in the U2C1 register is set to 1 (transmission enabled).
• The TI bit in the U2C1 register is set to 0 (data present in the U2TB register). Receive start conditions To start reception, the following requirements must be met: (1)
• The RE bit in the U2C1 register is set to 1 (reception enabled).
• The TE bit in the U2C1 register is set to 1 (transmission enabled).
• The TI bit in the U2C1 register is set to 0 (data present in the U2TB register). Interrupt request generation timing Start/stop condition detection, no acknowledgement detection, or acknowledgement detection Error detection Overrun error (2) This error occurs if the serial interface starts receiving the next unit of data before reading the U2RB register and receives the 8th bit of the next unit of data. Selectable functions • Arbitration lost Timing at which the ABT bit in the U2RB register is updated can be selected.
• SDA2 digital delay No digital delay or a delay of 2 to 8 U2BRG count source clock cycles can be selected.
• Clock phase setting With or without clock delay can be selected.

R8C/32A Group 22. Serial Interface (UART2) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 334 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 22.13 I 2C Mode Block Diagram Delay circuit Transmit register SDA2 SCL2 Receive register CLK control Internal clock UART2 External clock Arbitration Start condition detection Stop condition detection Port register (1) Falling edge detection D T Q D T Q D T Q NACK ACK UART2 UART2 UART2 R UART2 transmit/NACK interrupt request UART2 receive/ACK interrupt request DTC request (source number 14) 9th bit IICM = 1 and IICM2 = 0 S R Q Bus busy Start/stop condition detection interrupt request ALS R S SWC 9th bit falling edge IICM = 1 and IICM2 = 0 IICM2 = 1 IICM2 = 1 SWC2 SDHI DTC request (source number 15) The above applies when:

• Bits SMD2 to SMD0 in U2MR register = 010b
• IICM bit in U2SMR register = 1 IICM: Bit in U2SMR register IICM2, SWC, ALS, SWC2, SDHI: Bits in U2SMR2 register STSPSEL, ACKD, ACKC: Bits in U2SMR4 register IICM = 0 IICM = 1 I/O port STSPSEL = 0 STSPSEL = 1 STSPSEL = 1 STSPSEL = 0 SDA (STSP) SCL (STSP) ACKC = 1 ACKC = 0 ACKD bit Note: If the IICM bit is set to 1, the pin can be read even when the port direction bit corresponding to the SCL2 pin is set to 1 (ou tput mode). Q Start/stop condition generation block

R8C/32A Group 22. Serial Interface (UART2) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 335 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Note: 1. Set the bits not listed in this table to 0 when writing to the above registers in I 2C mode. Table 22.10 Registers Used and Settings in I 2C Mode (1) Register Bit Function Master Slave U2TB (1) b0 to b7 Set transmit data. Set transmit data. U2RB (1) b0 to b7 Receive data can be read. Receive data can be read. b8 ACK or NACK is set in this bit. ACK or NACK is set in this bit. ABT Arbitration lost detect flag Disabled OER Overrun error flag Overrun error flag U2BRG b0 to b7 Set a bit rate. Disabled U2MR (1) SMD2 to SMD0 Set to 010b. Set to 010b. CKDIR Set to 0. Set to 1. IOPOL Set to 0. Set to 0. U2C0 CLK1, CLK0 Select the count source for the U2BRG register. Disabled CRS Disabled because CRD = 1. Disabled because CRD = 1. TXEPT Transmit register empty flag Transmit register empty flag CRD Set to 1. Set to 1. NCH Set to 1. Set to 1. CKPOL Set to 0. Set to 0. UFORM Set to 1. Set to 1. U2C1 TE Set to 1 to enable transmission. Set to 1 to enable transmission. TI Transmit buffer empty flag Transmit buffer empty flag RE Set to 1 to enable reception. Set to 1 to enable reception. RI Receive complete flag Receive complete flag U2IRS Disabled Disabled U2RRM, U2LCH, U2ERE Set to 0. Set to 0. U2SMR IICM Set to 1. Set to 1. ABC Select the timing at which an arbitration lost is detected. Disabled BBS Bus busy flag Bus busy flag b3 to b7 Set to 0. Set to 0. U2SMR2 IICM2 Refer to Table 22.12 I2C Mode Functions. Refer to Table 22.12 I2C Mode Functions. CSC Set to 1 to enable clock synchronization. Set to 0. SWC Set to 1 to fix SCL2 output low at the falling edge of the 9th bit of clock. Set to 1 to fix SCL2 output low at the falling edge of the 9th bit of clock. ALS Set to 1 to stop SDA2 output when an arbitration lost is detected. Set to 0. STAC Set to 0. Set to 1 to initialize UART2 at start condition detection SWC2 Set to 1 to forcibly pull SCL2 low. Set to 1 to forcibly pull SCL2 output low. SDHI Set to 1 to disable SDA2 output. Set to 1 to disable SDA2 output. b7 Set to 0. Set to 0.

R8C/32A Group 22. Serial Interface (UART2) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 336 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Table 22.11 Registers Used and Settings in I 2C Mode (2) Register Bit Function Master Slave U2SMR3 b0, b2, b4, and NODC Set to 0. Set to 0. CKPH Refer to Table 22.12 I2C Mode Functions. Refer to Table 22.12 I2C Mode Functions. DL2 to DL0 Set the amount of SDA2 digital delay. Set the amount of SDA2 digital delay. U2SMR4 STAREQ Set to 1 to generate a start condition. Set to 0. RSTAREQ Set to 1 to generate a restart condition. Set to 0. STPREQ Set to 1 to generate a stop condition. Set to 0. STSPSEL Set to 1 to output each condition. Set to 0. ACKD Select ACK or NACK. Select ACK or NACK. ACKC Set to 1 to output ACK data. Set to 1 to output ACK data. SCLHI Set to 1 to stop SCL2 output when a stop condition is detected. Set to 0. SWC9 Set to 0. Set to 1 to hold SCL2 low at the falling edge of the 9th bit of clock. URXDF DF2EN Set to 0. Set to 0. U2SMR5 MP Set to 0. Set to 0.

R8C/32A Group 22. Serial Interface (UART2) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 337 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Notes: 1. If the source of any interrupt is cha nged, the IR bit in the interrupt control r egister for the changed interrupt may inadver tently be set to 1 (interrupt requested). (Refer to 11.8 Notes on Interrupts.) If one of the bits listed below is changed, the interrupt source, the interrupt timing, and others change. Therefore, always be sure to set the IR bit to 0 (interrupt not requested) after changing these bits. Bits SMD2 to SMD0 in the U2MR register, the IICM bit in the U2SMR register, the IICM2 bit in the U2SMR2 register, and the CKPH bit in the U2SMR3 register. 2. Set the initial value of SDA2 output while bits SMD2 to SM D0 in the U2MR register are 000b (serial interface disabled). 3. Second data transfer to the U2RB register (rising edge of SCL2 9th bit) 4. First data transfer to the U2RB register (falling edge of SCL2 9th bit) 5. Refer to Figure 22.16 STSPSEL Bit Functions. 6. Refer to Figure 22.14 Transfer to U2RB Register and Interrupt Timing. Table 22.12 I 2C Mode Functions Function Clock Synchronous Serial I/O Mode (SMD2 to SMD0 = 001b, IICM = 0) I2C Mode (SMD2 to SMD0 = 010b, IICM = 1) IICM2 = 0 (NACK/ACK interrupt) IICM2 = 1 (UART transmit/receive interrupt) CKPH = 0 (No Clock Delay) CKPH = 1 (With Clock Delay) CKPH = 0 (No Clock Delay) CKPH = 1 (With Clock Delay) Source of UART2 bus collision interrupt (1, 5) − Start condition detection or stop condition detection (Refer to Table 22.13 STSPSEL Bit Functions) Source of UART2 transmit/NACK2 (1, 6) UART2 transmission Transmission started or completed (selectable by U2IRS bit) No acknowledgment detection (NACK) Rising edge of SCL2 9th bit UART2 transmission Rising edge of SCL2 9th bit UART2 transmission Falling edge of SCL2 next to 9th bit Source of UART2 receive/ACK2 (1, 6) UART2 reception When 8th bit received CKPOL = 0 (rising edge) CKPOL = 1 (falling edge) Acknowledgment detection (ACK) Rising edge of SCL2 9th bit UART2 reception Falling edge of SCL2 9th bit Timing for transferring data from UART reception shift register to U2RB register CKPOL = 0 (rising edge) CKPOL = 1 (falling edge) Rising edge of SCL2 9th bit Falling edge of SCL2 9th bit Falling and rising edges of SCL2 9th bit UART2 transmission output delay No delay With delay TXD2/SDA2 functions TXD2 output SDA2 I/O RXD2/SCL2 functions RXD2 input SCL2 I/O CLK2 functions CLK2 input or output port selected − (Cannot be used in I2C mode.) Read of RXD2 and SCL2 pin levels Possible when the corresponding port direction bit = 0 Possible regardless of the content of the corresponding port direction bit. Initial value of TXD2 and SDA2 outputs CKPOL = 0 (“H”) CKPOL = 1 (“L”) The value set in the port register before setting I2C mode. (2) Initial and end values of SCL2 DTC source number 14 (6) UART2 reception When 8th bit received CKPOL = 0 (rising edge) CKPOL = 1 (falling edge) Acknowledgment detection (ACK) UART2 reception Falling edge of SCL2 9th bit DTC source number 15 (6) UART2 transmission Transmission started or completed (selectable by U2IRS bit) UART2 transmission Rising edge of SCL2 9th bit UART2 transmission Falling edge of SCL2 next to 9th bit UART2 transmission Rising edge of SCL2 9th bit UART2 transmission Falling edge of SCL2 next to 9th bit Storage of receive data 1st to 8th bits of the received data are stored in bits b0 to b7 in the U2RB register. 1st to 8th bits of the received data are stored in bits b7 to b0 in the U2RB register. 1st to 7th bits of the received data are stored in bits b6 to b0 in the U2RB register. 8th bit is stored in bit b8 in the U2RB register. 1st to 8th bits are stored in bits b7 to b0 in the U2RB register. (3) Read of receive data The U2RB register status is read. Bits b6 to b0 in the U2RB register are read as bits b7 to b1. Bit b8 in the U2RB register is read as bit b0. (4)

R8C/32A Group 22. Serial Interface (UART2) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 338 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 22.14 Transfer to U2RB Register and Interrupt Timing (1) IICM2 = 0 (ACK and NACK interrupts), CKPH = 0 (no clock delay) D6 D5 D4 D3 D2 D1 D8 (ACK, NACK)D7SDA2 SCL2 ACK interrupt (DTC source number 14 request), NACK interrupt Transfer to U2RB register b15 ... b9 b8 b7 b0 U2RB register contents D8 D7 D6 D5 D4 D3 D2 D1 D0 (2) IICM2 = 0, CKPH = 1 (with clock delay) D6 D5 D4 D3 D2 D1D7SDA2 SCL2 ACK interrupt (DTC source number 14 request), NACK interrupt Transfer to U2RB register b15 ... b9 b8 b7 b0 D8 D7 D6 D5 D4 D3 D2 D1 D0 U2RB register contents D8 (ACK, NACK) (3) IICM2 = 1 (UART transmit/receive interrupt), CKPH = 0 D6 D5 D4 D3 D2 D1D7SDA2 SCL2 Receive interrupt (DTC source number 14 request) Transmit interrupt Transfer to U2RB register b15 ... b9 b8 b7 b0 D0 D7 D6 D5 D4 D3 D2 D1 U2RB register contents D8 (ACK, NACK) (4) IICM2 = 1, CKPH = 1 D6 D5 D4 D3 D2 D1D7SDA2 SCL2 Transmit interrupt Transfer to U2RB register The above applies when:

• CKDIR bit in U2MR register = 0 (master selected) Receive interrupt (DTC source number 14 request) b15 ... b9 b8 b7 b0 D0 D7 D6 D5 D4 D3 D2 D1 U2RB register contents Transfer to U2RB register b15 ... b9 b8 b7 b0 D8 D7 D6 D5 D4 D3 D2 D1 D0 U2RB register contents D8 (ACK, NACK) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit

R8C/32A Group 22. Serial Interface (UART2) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 339 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

22.5.1 Detection of Start and Stop Conditions

Whether a start or a stop condition has been detected is determined. A start condition detect interrupt request is generated when the SDA2 pin changes state from high to low while the SCL2 pin is in the high state. A stop condition detect interrupt request is generated when the SDA2 pin changes state from low to high while the SCL2 pin is in the high state. Because the start and stop condition de tect interrupts share an interrupt control regist er and vector, check the BBS bit in the U2SMR register to determine which interrupt source is requesting the interrupt. Figure 22.15 shows the Detection of Start and Stop Conditions. Figure 22.15 Detection of Start and Stop Conditions Setting up duration Holding duration SCL2 SDA2 (Start condition) SDA2 (Stop condition) 5 cycles of f1 < Setting up duration 5 cycles of f1 < Holding duration

R8C/32A Group 22. Serial Interface (UART2) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 340 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

22.5.2 Output of Start and Stop Conditions

A start condition is generated by setting the STAREQ bit in the U2SMR4 register to 1 (start). A restart condition is generated by setting the RSTAREQ bit in the U2SMR4 register to 1 (start). A stop condition is generated by setting the STPREQ bit in the U2SMR4 register to 1 (start). The output procedure is as follows: (1) Set the STAREQ bit, RSTAREQ bit or STPREQ bit to 1 (start). (2) Set the STSPSEL bit in the U2SMR4 register to 1 (output). Table 22.13 lists the STSPSEL Bit Functions. Figure 22.16 shows the STSPSEL Bit Functions. Figure 22.16 STSPSEL Bit Functions Table 22.13 STSPSEL Bit Functions Function STSPSEL = 0 STSPSEL = 1 Output of pins SCL2 and SDA2 Output of transfer clock and data Output of start/stop conditions is accomplished by a program using ports (not automatically generated in hardware) Output of start/stop conditions according to bits STAREQ, RSTAREQ, and STPREQ Start/stop condition interrupt request generation timing Detection of start/stop conditions Co mpletion of start/stop condition generation SDA2 Start condition detection interrupt Stop condition detection interrupt (1) Slave Mode CKDIR = 1 (external clock) SCL2 SDA2 Start condition detection interrupt Stop condition detection interrupt (2) Master Mode CKDIR = 0 (internal clock), CKPH = 1 (with clock delay) SCL2 Set STAREQ = 1 (start) Set STPREQ = 1 (start) STSPSEL bit 0 STSPSEL bit Set to 1 by a program. Set to 0 by a program. Set to 1 by a program. Set to 0 by a program. 1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit 1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit

R8C/32A Group 22. Serial Interface (UART2) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 341 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

22.5.3 Arbitration

Unmatching of the transmit data and SDA2 pin input data is checked in synchronization with the rising edge of SCL2. Use the ABC bit in the U2SMR register to select the timing at which the ABT bit in the U2RB register is updated. If the ABC bit is set to 0 (update per bit), the ABT bit is set to 1 at the same time unmatching is detected during check, and is set to 0 when not detected. If the ABC bit is set to 1, if unmatching is ever detected, the ABT bit is set to 1 (unmatching detected) at the falling edge of the clock pulse of the 9th bit. If the ABT bit needs to be updated per byte, set the ABT bit to 0 (not dete cted) after detecting acknowledge for the first byte, before transferring the next byte. Setting the ALS bit in the U2SMR2 register to 1 (SDA ou tput stop enabled) causes an arbitration lost to occur, in which case the SDA2 pin is placed in the high-impedance state at the same time the ABT bit is set to 1 (unmatching detected).

22.5.4 Transfer Clock

The transfer clock is used to transmit and receive data as is shown in Figure 22.14 Transfer to U2RB Register and Interrupt Timing. The CSC bit in the U2SMR2 register is used to synchr onize an internally generated clock (internal SCL2) and an external clock supplied to the SCL2 pin. When the CSC bit is set to 1 (clock synchronization enabled), if a falling edge on the SCL2 pin is detected while the internal SCL2 is high, the internal SCL2 goes low. The value in the U2BRG register is reloaded and counting of the low-level intervals starts. If the internal SCL2 changes state from low to high while the SCL2 pin is low, counting stops. If the SCL2 pin goes high, counting restarts. In this way, the UART2 transfer clock is equivalent to AND of the internal SCL2 and the clock signal applied to the SCL2 pin. The transfer clock works from a half cycle before the falling edge of the internal SCL2 1st bit to the rising edge of the 9th bit. To use this function, select an internal clock for the transfer clock. The SWC bit in the U2SMR2 register determines whether the SCL2 pin is fixed low or freed from low-level output at the falling edge of the 9th clock pulse. If the SCLHI bit in the U2SMR4 register is set to 1 (ena bled), SCL2 output is turn ed off (placed in the high- impedance state) when a stop condition is detected. Setting the SWC2 bit in the U2SMR2 register to 1 (“L” output) makes it possible to forcibly output a low-level signal from the SCL2 pin even while sending or rece iving data. Setting the SWC2 bit to 0 (transfer clock) allows the transfer clock to be output from or supplied to the SCL2 pin, instead of outputting a low-level signal. If the SWC9 bit in the U2SMR4 register is set to 1 (SCL “L” hold enabled) when the CKPH bit in the U2SMR3 register is 1, the SCL2 pin is fixed low at the falling e dge of the clock pulse next to the 9th. Setting the SWC9 bit to 0 (SCL “L” hold disabled) frees the SCL2 pin from low-level output.

22.5.5 SDA Output

The data written to bits b7 to b0 (D7 to D0) in the U2TB register is output in descending order from D7. The 9th bit (D8) is ACK or NACK. Set the initial value of SDA2 transmit output when IICM is set to 1 (I 2C mode) and bits SMD2 to SMD0 in the U2MR register are set to 000b (serial interface disabled). Bits DL2 to DL0 in the U2SMR3 register allow addition of no delays or a delay of 2 to 8 U2BRG count source clock cycles to the SDA2 output. Setting the SDHI bit in the U2SMR2 register to 1 (SDA output disabled) forcibly places the SDA2 pin in the high-impedance state. Do not write to the SDHI bit at the rising edge of the UART2 transfer clock. This is because the ABT bit may inadvertently be set to 1 (detected).

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22.5.6 SDA Input

When the IICM2 bit is set to 0, the 1st to 8th bits (D7 to D0) of received data are stored in bits b7 to b0 in the U2RB register. The 9th bit (D8) is ACK or NACK. When the IICM2 bit is set to 1, the 1st to 7th bits (D7 to D1) of received data are stored in bits b6 to b0 in the U2RB register and the 8th bit (D0) is stored in bit b8 in the U2RB register. Even when the IICM2 bit is set to 1, if the CKPH bit is 1, the same data as when the IICM2 bit is 0 can be read by reading the U2RB register after the rising edge of 9th bit of the clock.

22.5.7 ACK and NACK

If the STSPSEL bit in the U2SMR4 register is set to 0 (start and stop conditions not output) and the ACKC bit in the U2SMR4 register is set to 1 (ACK data output ), the value of the ACKD bit in the U2SMR4 register is output from the SDA2 pin. If the IICM2 bit is set to 0, a NACK interrupt request is generated if the SDA2 pin remains high at the rising edge of the 9th bit of transmit clock pulse. An ACK inte rrupt request is generated if the SDA2 pin is low at the rising edge of the 9th bit of the transmit clock. If ACK2 (UART2 reception) is selected to generate a DTC request source, a DTC tr ansfer can be activated by detection of an acknowledge.

22.5.8 Initialization of Transmission/Reception

If a start condition is detected while the STAC bit is set to 1 (UART2 initialization enabled), the serial interface operates as described below.

• The transmit shift register is initialized, and the conten ts of the U2TB register ar e transferred to the transmit shift register. In this way, the serial interface star ts sending data when the next clock pulse is applied. However, the UART2 output value does not change state and remains the same as when a start condition was detected until the first bit of data is output in synchronization with the input clock.
• The receive shift register is initialized, and the serial interface starts r eceiving data when the next clock pulse is applied.
• The SWC bit is set to 1 (SCL wait output enabled). Consequently, the SCL2 pin is pulled low at the falling edge of the 9th clock pulse. Note that when UART2 transmission/reception is started using this function, the TI bit does not change state. Select the external clock as the transfer clock to start UART2 transmission/reception with this setting.

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22.6 Multiprocessor Communication Function

When the multiprocessor communication function is used, data transmission/reception can be performed between a number of processors sharing communication lines by asynchronous serial co mmunication, in which a multiprocessor bit is added to the data. For multiprocessor communication, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles; an ID transmission cycle for specifying the receiving station, an d a data transmission cycle for th e specified receiving station. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. When the multiprocessor bit is set to 1, the cycle is an ID transm ission cycle; when the multip rocessor bit is set to 0, the cycle is a data transmission cycl e. Figure 22.17 shows an Inter-Processor Communication Example Using Multiprocessor Format (Data AAh Transmission to Receiving Station A). The transmitting station first sends the ID code of the receiving station to perform communication as communication data with a 1 multiprocessor bit added. It then sends transmit data as communication data with a 0 multiprocessor bit added. When communication data in which the multiprocessor bit is 1 is received, the receiving station compares that data with its own ID. If they match, the data to be sent next is received. If they do not match, the receive station continues to skip communication data until data in which the multiprocessor bit is 1 is again received. UART2 uses the MPIE bit in the U2SMR5 register to implem ent this function. When the MPIE bit is set to 1, data transfer from the UART2 receive register to the U2RB re gister, receive error detection, and the settings of the status flags, the RI bit in the U2C1 register, bits FER and OER in th e U2RB register, are disabled until data in which the multiprocessor bit is 1 is r eceived. On receiving a receive character in which the multiprocessor bit is 1, the MPRB bit in the U2RB register is set to 1 and the MP IE in the U2SMR5 register bit is set to 0, thus normal reception is resumed. When the multiprocessor format is specified, the parity b it specification is invalid. All other bit settings are the same as those in normal asynchrono us mode (UART mode). The clock used for multiprocessor communication is the same as that in normal asynchronous mode (UART mode). Figure 22.18 shows a Block Diagram of Multiprocessor Communication Function. Table 22.14 lists the Registers and Settings in Multiprocessor Communication Function. Figure 22.17 Inter-Processor Communicati on Example Using Multiprocessor Format (Data AAh Transmission to Receiving Station A) 01hSerial data AAh (MPRB = 1) (MPRB = 0) ID transmission cycle = receiving station specification Data transmission cycle = data transmission to receiving station specified by ID MPRB: Multiprocessor bit Receiving station A Receiving station B Receiving station C Receiving station D Transmitting station Communication line

R8C/32A Group 22. Serial Interface (UART2) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 344 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 22.18 Block Diagram of Multiprocessor Communication Function RXD2 1SP 2SP SP SP PAR PRYE = 0 PAR disabled PAR enabled PRYE = 1 Clock synchronous type UART UART (7 bits) UART (8 bits) UART (9 bits) UART (7 bits) UART (8 bits) UART (9 bits) D7 D6 D5 D4 D3 D2 D1 D0 UART2 receive register U2RB register0000000 MPRB Data bus high-order bits Data bus low-order bits D7 D6 D5 D4 D3 D2 D1 D0 U2TB registerMPTB TXD2 1SP 2SP SP SP PAR PAR disabled PRYE = 0 PAR enabled PRYE = 1 Clock synchronous type UART UART (7 bits) UART (8 bits) UART (9 bits) UART (7 bits) UART2 transmit register SP: Stop bit PAR: Parity bit PRYE: Bit in U2MR register DF2EN: Bit in URXDF register MP: Bit in U2SMR5 register DF2EN = 0 DF2EN = 1 Digital filter Reception Transmission (5) (2) (1) [Multiprocessor mode reception when MP = 1 (multiprocessor communication enabled)] (1) Clock asynchronous (7 bits): Received D7 is transferred to b8 in the U2RB register. (2) Clock asynchronous (8 bits): Received D8 is transferred to b8 in the U2RB register. [Multiprocessor mode transmission when MP = 1 (multiprocessor communication enabled)] (3) Clock asynchronous (7 bits): b8 in the U2TB register is transferred externally as transfer data D7. (4) Clock asynchronous (8 bits): b8 in the U2TB register is transferred externally as transfer data D8. [Multiprocessor mode transmission/reception] (5) PAR is disabled. (3)(4) (5) Clock synchronous type MSB/LSB conversion circuit MSB/LSB conversion circuit Clock synchronous type Clock synchronous type UART (8 bits) UART (9 bits) Clock synchronous type

R8C/32A Group 22. Serial Interface (UART2) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 345 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Notes: 1. Set the MPTB bit to 1 when the ID data frame is transmitted. Set this bit to 0 when the data frame is transmitted. 2. If the MPRB bit is set to 1, received D7 to D0 are ID fields. If the MPRB bit is set to 0, received D7 to D0 are data fields. Table 22.14 Registers and Settings in Multiprocessor Communication Function Register Bit Function U2TB (1) b0 to b7 Set transmit data. MPTB Set to 0 or 1. U2RB (2) b0 to b7 Receive data can be read. MPRB Multiprocessor bit OER, FER, SUM Error flag U2BRG b0 to b7 Set the transfer rate. U2MR SMD2 to SMD0 Set to 100b when transfer data is 7 bits long. Set to 101b when transfer data is 8 bits long. CKDIR Select the internal clock or external clock. STPS Select the stop bit. PRY, PRYE Parity detection function disabled IOPOL Set to 0. U2C0 CLK0, CLK1 Select th e U2BRG count source. CRS CTS or RTS function disabled TXEPT Transmit register empty flag CRD Set to 0. NCH Select TXD2 pin output mode. CKPOL Set to 0. UFORM Set to 0. U2C1 TE Set to 1 to enable transmission. TI Transmit buffer empty flag RE Set to 1 to enable reception. RI Receive complete flag U2IRS Select the UART2 transmit interrupt source. U2LCH Set to 0. U2ERE Set to 0. U2SMR b0 to b7 Set to 0. U2SMR2 b0 to b7 Set to 0. U2SMR3 b0 to b7 Set to 0. U2SMR4 b0 to b7 Set to 0. U2SMR5 MP Set to 1. MPIE Set to 1. URXDF DF2EN Select the digital filter enabled or disabled.

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22.6.1 Multiprocessor Transmission

Figure 22.19 shows a Sample Flowchart of Multiprocessor Data Transmission. Set the MPBT bit in the U2TB register to 1 for ID transmission cycles. Set the MPBT bit in the U2TB register to 0 for data transmission cycles. Other operations are the same as in universal asynchronous receiver/transmitter mode (UART mode). Figure 22.19 Sample Flowchart of Multiprocessor Data Transmission (1) Read the U2C1 register to confirm that the TI bit is set to 1. Then set the MPBT bit in the U2TB register to 0 or 1 and write transmit data to the U2TB register. Writing data to the U2TB register sets the TI bit to 0 automatically. (2) When transmission completes, the TXEPT bit is set to 1 automatically. (3) To continue data transmission, read that the TI bit is 1 and write data tot the U2TB register. Writing data to the U2TB register sets the TI bit to 0 automatically. Yes No End Read the TI bit in the U2C1 register(1) Set the MPBT bit in the U2TB register Write transmit data to the U2TB register Read the TXEPT bit in the U2C0 register TXEPT = 1? Set the TE bit in the U2C1 register to 0 Continue data transmission? Yes Yes No (2) (3) TI = 1? Start No

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22.6.2 Multiprocessor Reception

Figure 22.20 shows a Sample Flowchart of Multiprocesso r Data Reception. When the MPIE bit in the U2SMR5 register is set to 1, communication data is ignored un til data in which the multiprocessor bit is 1 is received. Communication data with a 1 multiprocessor bit added is transferred to the U2RB register as receive data. At this time, a reception complete interrupt request is generated. Ot her operations are the same as in universal asynchronous receiver/transmitter mode (UART mode). Figure 22.21 shows a Receive Operation Example during Multiprocessor Communication (with 8-Bit Data/Multiprocessor Bit/One-Stop Bit). Figure 22.20 Sample Flowchart of Multiprocessor Data Reception (1) Set the MPIE bit in the U2SMR5 register to 1. (2) When the MPRB bit is detected to be 1, the MPIE bit is set to 0 and a reception complete interrupt request can be generated. Read the U2C1 register to confirm that the RI bit is set to 1. If the RI bit is 1, read data in the receive shift register and compare the data with its own station ID. Reading data in the U2RB register sets the RI bit to 0 automatically. (3) When the data matches the own station ID, the next data reception starts. When the data does not match the ID, set the MPIE bit to 1 and the MCU enters the idle state. (4) Read the U2C1 register to confirm that the RI bit is set to 1. Then read data in the receive shift register. (5) To discontinue reception, set the RE bit in the U2C0 register to 0 to complete reception. To continue reception, restart the procedure from step (1). Yes No End Set the MPIE bit in the U2SMR5 register to 1(1) Read data in the receive shift register Read the RI bit in the U2C1 register Read receive data in the U2RB register RI = 1? Set the RE bit in the U2C1 register to 0 Continue data reception? Yes No (4) (5) Start RI = 1? Read the RI bit in the U2C1 register Own station ID? Yes Yes (2) (3) No No

R8C/32A Group 22. Serial Interface (UART2) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 348 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 22.21 Receive Operation Example during Multiprocessor Communication (with 8-Bit Data/Multiprocessor Bit/One-Stop Bit) D0 D101 D7 1 D0 D1 D7 0 110 1 Receive data (ID1) Serial data MPRB Start bit Stop bit Receive data (DATA1) MPRB Marked state (Idle state) 1 frame1 frame 1MP bit in U2SMR5 register MPIE bit in U2SMR5 register RI bit in U2C1 register U2RB register MCU operation User processing Detect the MPRB bit and set the MPIE bit to 0. A reception complete interrupt request is generated. Set the RI bit to 0. Read data in the U2RB register. If data does not match own station ID, set the MPIE bit to 1 again. No reception complete interrupt request is generated. The U2RB register retains state. ID1 (a) When Data Does Not Match Own Station ID D0 D101 D7 1 D0 D1 D7 0 110 1 Receive data (ID2) Serial data MPRB Start bit Stop bit Receive data (DATA2) MPRB Marked state (Idle state) 1 frame1 frame 1MP bit in U2SMR5 register MPIE bit in U2SMR5 register RI bit in U2C1 register U2RB register MCU operation User processing Detect the MPRB bit and set the MPIE bit to 0. A reception complete interrupt request is generated. Set the RI bit to 0. Read data in the U2RB register. If data matches own station ID, continue reception without any setting changes. Set the MPIE bit to 1 again. ID2 (b) When Data Matches Own Station ID DATA2ID1 A reception complete interrupt request is generated. Set the RI bit to 0. Read data in the U2RB register. MPRB: Bit in U2RB register MPIE: Bit in U2SMR5 register

R8C/32A Group 22. Serial Interface (UART2) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 349 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

22.6.3 RXD2 Digital Filter Select Function

When the DF2EN bit in the URXDF register is set to 1 (RXD2 digital filer enabled), the RXD2 input signal is loaded internally via the digital filter circuit for noi se reduction. The noise canceller consists of three cascaded latch circuits and a match detection circuit. The RXD2 input signal is sampled on the internal basic clock with a frequency 16 times the bit rate. It is recognized as a si gnal and the level is passed forward to the next circuit when three latch outputs match. When the outputs do not match, the previous value is retained. In other words, when the level is changed within three clocks, the change is recognized as not a signal but noise. Figure 22.22 shows a Block Diagram of RXD2 Digital Filter Circuit. Figure 22.22 Block Diagram of RXD2 Digital Filter Circuit C DQ Latch C DQ Latch Match detection circuit RXD2 input signal Sampling clock Sampling clock URXDF register (DF2EN bit) C DQ Latch Internal RXD2 input signal Internal basic clock period (1) Note: 1. When the CKDIR bit in the U2MR register is 0 (internal clock), the internal basic clock is set to fj/(n+1) (fj = f1, f8, f32, fC; n = setting value in the U2BRG register). When the CKDIR bit in the U2MR register is 1 (external clock), the internal basic clock is set to fEXT/(n+1) (fEXT is input from the CLK2 pin. n = setting value in the U2BRG register).

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22.7 Notes on Serial Interface (UART2)

22.7.1 Clock Synchronous Serial I/O Mode

22.7.1.1 Transmission/Reception

When the RTS function is used with an external clock, the RTS2 pin outputs “L,” which informs the transmitting side that the MCU is re ady for a receive operation. The RTS2 pin outputs “H” when a receive operation starts. Therefore, the transmit timing and receive timing can be synchronized by connecting the RTS2 pin to the CTS2 pin of the transmitting side. The RTS function is disabled when an internal clock is selected.

22.7.1.2 Transmission

If an external clock is selected, the following conditions must be met while the external clock is held high when the CKPOL bit in the U2C0 register is set to 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock), or while the exte rnal clock is held low when the CKPOL bit is set to 1 (transmit data output at the rising edge and receive data input at the falling edge of the transfer clock).

• The TE bit in the U2C1 register = 1 (transmission enabled)
• The TI bit in the U2C1 register = 0 (data present in the U2TB register)
• I f t h e C T S function is selected, input on the CTS2 pin = “L”

22.7.1.3 Reception

In clock synchronous serial I/O mode, the shift clock is generated by activating the transmitter. Set the UART2- associated registers for transmit ope ration even if the MCU is used for receive operation only. Dummy data is output from the TXD2 pin while receiving. When an internal clock is selected, the shift clock is ge nerated by setting the TE bit in the U2C1 register to 1 (transmission enabled) and placing dummy data in the U2TB register. When an external clock is selected, set the TE bit to 1 (transmission enabled), place dummy data in the U2TB register, and input an external clock to the CLK2 pin to generate the shift clock. If data is received consecutively, an overrun error occurs when the RE bit in the U2C1 register is set to 1 (data present in the U2RB register) and the next receive data is received in the UART2 receive register. Then, the OER bit in the U2RB register is set to 1 (overrun error). At this time, the U2RB register value is undefined. If an overrun error occurs, the IR bit in the S2RIC register remains unchanged. To receive data consecutively, set du mmy data in the low-order byte in the U2TB register per each receive operation. If an external clock is selected, the following conditions must be met while the external clock is held high when the CKPOL bit is set to 0, or while the external clock is held low when the CKPOL bit is set to 1.

• The RE bit in the U2C1 register = 1 (reception enabled)
• The TE bit in the U2C1 register = 1 (transmission enabled)
• The TI bit in the U2C1 register = 0 (data present in the U2TB register)

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22.7.2 Clock Asynchronous Se rial I/O (UART) Mode

22.7.2.1 Transmission/Reception

When the RTS function is used with an external clock, the RTS2 pin outputs “L,” which informs the transmitting side that the MCU is re ady for a receive operation. The RTS2 pin outputs “H” when a receive operation starts. Therefore, the transmit timing and receive timing can be synchronized by connecting the RTS2 pin to the CTS2 pin of the transmitting side. The RTS function is disabled when an internal clock is selected.

22.7.2.2 Transmission

If an external clock is selected, the following conditions must be met while the external clock is held high when the CKPOL bit in the U2C0 register is set to 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock), or while the exte rnal clock is held low when the CKPOL bit is set to 1 (transmit data output at the rising edge and receive data input at the falling edge of the transfer clock).

• The TE bit in the U2C1 register = 1 (transmission enabled)
• The TI bit in the U2C1 register = 0 (data present in the U2TB register)
• I f t h e C T S function is selected, input on the CTS2 pin = “L”

22.7.3 Special Mode 1 (I 2C Mode)

When generating start, stop, and rest art conditions, set the STSPSEL bit in the U2SMR4 register to 0 and wait for more than half cycle of the transfer clock before changing each condition generation bit (STAREQ, RSTAREQ, and STPREQ) from 0 to 1.

R8C/32A Group 23. Clock Synchronous Serial Interface REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 352 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 23. Clock Synchronous Serial Interface The clock synchronous serial interface is configured as follows. Clock synchronous serial interface The clock synchronous serial interface uses the registers at addresses 0193h to 019Dh. Registers, bits, symbols, and functions vary even for the same addresses depending on the mode. Refer to the registers of each function for details. Also, the differences between clock synchronous communi cation mode and clock synchronous serial mode are the options of the transfer clock, clock output format, and data output format.

23.1 Mode Selection

The clock synchronous serial interface has four modes. Table 23.1 lists the Mode Selections. Refer to 24. Synchronous Serial Communication Unit (SSU) , 25. I2C bus Interface and the sections that follow for details of each mode. Synchronous serial communication unit (SSU) Clock synchronous communication mode 4-wire bus communication mode I2C bus Interface I 2C bus interface mode Clock synchronous serial mode Table 23.1 Mode Selections IICSEL Bit in SSUIICSR Register Bit 7 in 0198h (ICE Bit in ICCR1 Register) Bit 0 in 019Dh (SSUMS Bit in SSMR2 Register, FS Bit in SAR Register) Function Mode 0 0 0 Synchronous serial communication unit Clock synchronous communication mode 0 0 1 4-wire bus communication mode 11 0 I2C bus interface I 2C bus interface mode 1 1 1 Clock synchronous serial mode

R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 353 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 24. Synchronous Serial Co mmunication Unit (SSU) Synchronous serial communication unit (SSU) supports clock synchronous serial data communication.

24.1 Overview

Table 24.1 lists a Synchronous Serial Communication Unit Specifications, Figure 24.1 shows a Block Diagram of Synchronous Serial Communication Unit and Table 24.2 lists the Pin Configuration of Synchronous Serial Communication Unit. Note: 1. Synchronous serial communication unit has only one interrupt vector table. Table 24.1 Synchronous Serial Communication Unit Specifications Item Specification Transfer data format • Transfer data length: 8 to 16 bits Continuous transmission and reception of serial data are supported since both transmitter and receiver have buffer structures. Operating modes • Clock synchronous communication mode

• 4-wire bus communication mode (including bidirectional communication) Master/slave device Selectable I/O pins SSCK (I/O): Clock I/O pin SSI (I/O): Data I/O pin SSO (I/O): Data I/O pin SCS (I/O): Chip-select I/O pin Transfer clocks • When the MSS bit in the SSCRH register is set to 0 (operates as slave device), external clock is selected (input from SSCK pin).
• When the MSS bit in the SSCRH register is set to 1 (operates as master device), internal clock (selectable among f1/256, f1/128, f1/64, f1/32, f1/16, f1/8 and f1/4, output from SSCK pin) is selected.
• Clock polarity and phase of SSCK can be selected. Receive error detection • Overrun error Overrun error occurs during reception and completes in error. While the RDRF bit in the SSSR register is set to 1 (data in the SSRDR register) and when next serial data receive is completed, the ORER bit is set to 1. Multimaster error detection
• Conflict error When the SSUMS bit in the SSMR2 register is set to 1 (4-wire bus communication mode) and the MSS bit in the SSCRH register is set to 1 (operates as master device) and when starting a serial communication, the CE bit in the SSSR register is set to 1 if “L” applies to the SCS pin input. When the SSUMS bit in the SSMR2 register is set to 1 (4-wire bus communication mode), the MSS bit in the SSCRH register is set to 0 (operates as slave device) and the SCS pin input changes state from “L” to “H”, the CE bit in the SSSR register is set to 1. Interrupt requests 5 interrupt requests (transmit-end, transmit-data-empty, receive-data-full, overrun error, and conflict error) (1). Select functions • Data transfer direction Selects MSB-first or LSB-first
• SSCK clock polarity Selects “L” or “H” level when clock stops
• SSCK clock phase Selects edge of data change and data download

R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 354 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 24.1 Block Diagram of Synchronous Serial Communication Unit Table 24.2 Pin Configuration of Synchronous Serial Communication Unit Pin Name Assigned Pin I/O Function SSI P3_3, P3_4, or P1_6 I/O Data I/O pin SCS P3_3 or P3_4 I/O Chip-select signal I/O pin SSCK P3_5 I/O Clock I/O pin SSO P3_7 I/O Data I/O pin SSMR register Data bus Transmit/receive control circuit SSCRL register SSCRH register SSER register SSSR register SSMR2 register SSTDR register SSTRSR register SSRDR register Selector Multiplexer SSO SSI SCS SSCK Interrupt requests (TXI, TEI, RXI, OEI, and CEI) Internal clock generation circuit Internal clock (f1/i) i = 4, 8, 16, 32, 64, 128, or 256

R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 355 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

24.2 Registers

24.2.1 Module Standby Control Register (MSTCR)

Notes: 1. When the MSTIIC bit is set to 1 (standby), any access to the SSU or the I2C bus associated registers (addresses 0193h to 019Dh) is disabled. 2. When the MSTTRC bit is set to 1 (standby), any access to the timer RC associated registers (addresses 0120h to 0133h) is disabled.

24.2.2 SSU/IIC Pin Select Register (SSUIICSR)

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — MSTTRC MSTTRD MSTIIC — — — A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b1 — b2 — b3 MSTIIC SSU, I 2C bus standby bit 0: Active 1: Standby (1) R/W b4 MSTTRD Peripheral function power consumption reduce bit Set to 1. The power consumption of the peripheral functions can be reduced. R/W b5 MSTTRC Timer RC standby bit 0: Active 1: Standby (2) R/W b6 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b7 — Address 018Ch B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 IICSEL SSU/I2C bus switch bit 0: SSU function selected 1: I2C bus function selected R/W b1 — Reserved bit Set to 0. R/W b2 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b3 — b4 — Reserved bits Set to 0. R/W b5 — b6 — b7 —

R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 356 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

24.2.3 SS Bit Counter Register (SSBR)

Note: 1. Do not write to bits BS0 to BS3 during SSU operation. Write to these bits when the RE bit in the SSER register is set to 0 (reception disabled) and the TE bit is set to 0 (transmission disabled). To set the SSBR register, set the RE bit in the SSER register to 0 and the TE bit to 0. Bits BS0 to BS3 (SSU Data Transfer Length Set Bit) As the SSU data transfer length, 8 to 16 bits can be used.

24.2.4 SS Transmit Data Register (SSTDR)

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — — BS3 BS2 BS1 BS0 A f t e r R e s e t 11111000 Bit Symbol Bit Name Function R/W b0 BS0 SSU data transfer length set bit (1) b3 b2 b1 b0 0 0 0 0: 16 bits 1 0 0 0: 8 bits 1 0 0 1: 9 bits 1 0 1 0: 10 bits 1 0 1 1: 11 bits 1 1 0 0: 12 bits 1 1 0 1: 13 bits 1 1 1 0: 14 bits 1 1 1 1: 15 bits R/W b1 BS1 R/W b2 BS2 R/W b3 BS3 R/W b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b5 — — b6 — — b7 — — Address 0195h to 0194h B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 11111111 Bit b15 b14 b13 b12 b11 b10 b9 b8 A f t e r R e s e t 11111111 Bit Symbol Function R/W b15 to b0 — Store the transmit data. The stored transmit data is transferred to the SSTRSR register and transmission is started when it is detected that the SSTRSR register is empty. When the next transmit data is written to the SSTDR register during the data transmission from the SSTRSR register, the data can be transmitted continuously. When the MLS bit in the SSMR register is set to 1 (transfer data with LSB-first), the data in which MSB and LSB are reversed is read, after writing to the SSTDR register. R/W

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24.2.5 SS Receive Data Register (SSRDR)

Note: 1. The SSRDR register retains the data received before an overrun error occurs (ORER bit in the SSSR register set to 1 (overrun error)). When an overrun error occurs, the receive data may contain errors and therefore should be discarded.

24.2.6 SS Control Register H (SSCRH)

Notes: 1. The set clock is used when th e internal clock is selected. 2. The SSCK pin functions as the transfer clock output pin when the MSS bit is set to 1 (operates as master device). The MSS bit is set to 0 (operates as slave devic e) when the CE bit in the SSSR register is set to 1 (conflict error occurs). 3. The RSSTP bit is disabled when the MSS bit is set to 0 (operates as slave device). Address 0197h to 0196h B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 11111111 Bit b15 b14 b13 b12 b11 b10 b9 b8 A f t e r R e s e t 11111111 Bit Symbol Function R/W b15 to b0 — Store the receive data. (1) The receive data is transferred to the SSRDR register and the receive operation is completed when 1 byte of data has been received by the SSTRSR register. At this time, the next receive operation is possible. Continuous reception is possible using registers SSTRSR and SSRDR. R Address 0198h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — RSSTP MSS — — CKS2 CKS1 CKS0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 CKS0 Transfer clock select bit (1) b2 b1 b0 0 0 0: f1/256 0 0 1: f1/128 0 1 0: f1/64 0 1 1: f1/32 1 0 0: f1/16 1 0 1: f1/8 1 1 0: f1/4 1 1 1: Do not set. R/W b1 CKS1 R/W b2 CKS2 R/W b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b4 — b5 MSS Master/slave device select bit (2) 0: Operates as slave device 1: Operates as master device R/W b6 RSSTP Receive single stop bit (3) 0: Maintains receive operation after receiving 1 byte of data 1: Completes receive operation after receiving 1 byte of data R/W b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

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24.2.7 SS Control Register L (SSCRL)

Notes: 1. Registers SSBR, SSCRH, SS CRL, SSMR, SSER, SSSR, SSMR2, SSTDR, and SSRDR. 2. The data output after serial data is output can be changed by writing to the SOL bit before or after transfer. When writing to the SOL bit, set the SOLP bit to 0 and the SOL bit to 0 or 1 simultaneously by the MOV instruction. 3. Do not write to the SOL bit during data transfer. Address 0199h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — SOL SOLP — — SRES — A f t e r R e s e t 01111101 Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b1 SRES SSU control unit reset bit Writing 1 to this bit resets the SSU control unit and the SSTRSR register. The value in the SSU internal register (1) is retained. R/W b2 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b3 — b4 SOLP SOL write protect bit (2) The output level can be changed by the SOL bit when this bit is set to 0. The SOLP bit remains unchanged even if 1 is written to it. When read, the content is 1. R/W b5 SOL Serial data output value setting bit When read 0: The serial data output is set to “L”. 1: The serial data output is set to “H”. When written (2, 3) 0: The data output is “L” after the serial data output. 1: The data output is “H” after the serial data output. R/W b6 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

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24.2.8 SS Mode Register (SSMR)

Note: 1. Refer to 24.3.1.1 Association between Transfer Clock Polarity, Phase, and Data for the settings of the CPHS and CPOS bits. Address 019Ah B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol MLS CPOS CPHS — BC3 BC2 BC1 BC0 A f t e r R e s e t 00010000 Bit Symbol Bit Name Function R/W b0 BC0 Bits counter 3 to 0 b3 b2 b1 b0 0 0 0 0: 16 bits left 0 0 0 1: 1 bit left 0 0 1 0: 2 bits left 0 0 1 1: 3 bits left 0 1 0 0: 4 bits left 0 1 0 1: 5 bits left 0 1 1 0: 6 bits left 0 1 1 1: 7 bits left 1 0 0 0: 8 bits left 1 0 0 1: 9 bits left 1 0 1 0: 10 bits left 1 0 1 1: 11 bits left 1 1 0 0: 12 bits left 1 1 0 1: 13 bits left 1 1 1 0: 14 bits left 1 1 1 1: 15 bits left R b1 BC1 R b2 BC2 R b3 BC3 R b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b5 CPHS SSCK clock phase select bit (1) 0: Change data at odd edge (Download data at even edge) 1: Change data at even edge (Download data at odd edge) R/W b6 CPOS SSCK clock polarity select bit (1) 0: “H” when clock stops 1: “L” when clock stops R/W b7 MLS MSB first/LSB first select bit 0: Transfers data MSB first 1: Transfers data LSB first R/W

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24.2.9 SS Enable Register (SSER)

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TIE TEIE RIE TE RE — — CEIE A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 CEIE Conflict error interrupt enable bit 0: Disables conflict error interrupt request 1: Enables conflict error interrupt request R/W b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b2 — b3 RE Receive enable bit 0: Disables receive 1: Enables receive R/W b4 TE Transmit enable bit 0: Disables transmit 1: Enables transmit R/W b5 RIE Receive interrupt enable bit 0: Disables receive data full and overrun error interrupt request 1: Enables receive data full and overrun error interrupt request R/W b6 TEIE Transmit end interrupt enable bit 0: Disables transmit end interrupt request 1: Enables transmit end interrupt request R/W b7 TIE Transmit interrupt enable bit 0: Dis ables transmit data empty interrupt request 1: Enables transmit data empty interrupt request R/W

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24.2.10 SS Status Register (SSSR)

Notes: 1. Writing 1 to CE, ORER, RDRF, TEND, or TDRE bits is invalid. To set any of these bits to 0, first read 1 then write 2. When the serial communication is started while the SSUMS bit in the SSMR2 register is set to 1 (four-wire bus communication mode) and the MSS bit in the SSCRH register is set to 1 (operates as master device), the CE bit is set to 1 if “L” is applied to the SCS pin input. Refer to 24.5.4 SCS Pin Control and Arbitration for more information. When the SSUMS bit in the SSMR2 register is set to 1 (four-wire bus communication mode), the MSS bit in the SSCRH register is set to 0 (operates as slave device) and the SCS pin input changes the level from “L” to “H” during transfer, the CE bit is set to 1. 3. Indicates when overrun erro rs occur and receive completes by error reception. If the next serial data receive operation is completed while the RDRF bit is set to 1 (data in the SSRDR register), the ORER bit is set to 1. After the ORER bit is set to 1 (overrun error), receive operation is disabled while the bit remains 1. 4. The RDRF bit is set to 0 when reading out the data from the SSRDR register. 5. Bits TEND and TDRE are set to 0 when writing data to the SSTDR register. 6. The TDRE bit is set to 1 when the TE bit in t he SSER register is set to 1 (transmit enabled). If the SSSR register is accessed cont inuously, insert one or more NOP in structions between the instructions used for access. Address 019Ch B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TDRE TEND RDRF — — ORER — CE A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 CE Conflict error flag (1) 0: No conflict errors generated 1: Conflict errors generated (2) R/W b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b2 ORER Overrun error flag (1) 0: No overrun errors generated 1: Overrun errors generated (3) R/W b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b4 — b5 RDRF Receive data register full flag (1, 4) 0: No data in SSRDR register 1: Data in SSRDR register R/W b6 TEND Transmit end flag (1, 5) 0: The TDRE bit is set to 0 when transmitting the last bit of transmit data 1: The TDRE bit is set to 1 when transmitting the last bit of transmit data R/W b7 TDRE Transmit data empty flag (1, 5, 6) 0: Data is not transferred from registers SSTDR to SSTRSR 1: Data is transferred from registers SSTDR to SSTRSR R/W

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24.2.11 SS Mode Register 2 (SSMR2)

Notes: 1. Refer to 24.3.2.1 Association between Data I/O Pins and SS Shift Register for information on combinations of data I/O pins. 2. The SCS pin functions as a port, regardless of the values of bits CSS0 and CSS1 when the SSUMS bit is set to 0 (clock synchronous communication mode). 3. This bit functions as the SCS input pin before starting transfer. 4. The BIDE bit is disabled when the SSUMS bit is set to 0 (clock synchronous communication mode). 5. When the SOOS bit is set to 0 (CMOS output), set the port direction register bits corresponding to pins SSI and SSO to 0 (input mode). Address 019Dh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol BIDE SCKS CSS1 CSS0 SCKOS SOOS CSOS SSUMS A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 SSUMS SSU mode select bit (1) 0: Clock synchronous communication mode 1: Four-wire bus communication mode R/W b1 CSOS SCS pin open drain output select bit 0: CMOS output 1: N-channel open-drain output R/W b2 SOOS Serial data pin open output drain select bit (1) 0: CMOS output (5) 1: N-channel open-drain output R/W b3 SCKOS SSCK pin open drain output select bit 0: CMOS output 1: N-channel open-drain output R/W b4 CSS0 SCS pin select bit (2) b5 b4 0 0: Functions as port 0 1: Functions as SCS input pin 1 0: Functions as SCS output pin (3) 1 1: Functions as SCS output pin (3) R/W b5 CSS1 R/W b6 SCKS SSCK pin select bit 0: Functions as port 1: Functions as serial clock pin R/W b7 BIDE Bidirectional mode enable bit (1, 4) 0: Standard mode (communication using 2 pins of data input and data output) 1: Bidirectional mode (communication using 1 pin of data input and data output) R/W

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24.3 Common Items for Multiple Modes

24.3.1 Transfer Clock

The transfer clock can be selected fro m among seven internal clocks (f1/256, f1/128, f1/64, f1/32, f1/16, f1/8, and f1/4) and an external clock. When using synchronous serial communication unit, set the SCKS bit in the SSMR2 register to 1 and select the SSCK pin as the serial clock pin. When the MSS bit in the SSCRH register is set to 1 (operates as master device), an internal clock can be selected and the SSCK pin functions as output. When tran sfer is started, the SSCK pin outputs clocks of the transfer rate selected by bits CKS0 to CKS2 in the SSCRH register. When the MSS bit in the SSCRH register is set to 0 (operates as slave device), an external clock can be selected and the SSCK pin functions as input.

24.3.1.1 Association between Transf er Clock Polarity, Phase, and Data

The association between the transfer clock polarity, phase and data changes according to the combination of the SSUMS bit in the SSMR2 register and bits CPHS and CPOS in the SSMR register. Figure 24.2 shows the Association between Transfer Clock Polarity, Phase, and Transfer Data. Also, the MSB-first transfer or LSB-first transfer can be selected by setting the MLS bit in the SSMR register. When the MLS bit is set to 1, transfer is started fr om the LSB and proceeds to th e MSB. When the MLS bit is set to 0, transfer is started from the MSB and proceeds to the LSB.

R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 364 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 24.2 Association between Transfer Clock Polarity, Phase, and Transfer Data SSCK b0SSO, SSI

• SSUMS = 0 (clock synchronous communication mode), CPHS bit = 0 (data change at odd edge), and CPOS bit = 0 (“H” when clock stops) b1 b2 b3 b4 b5 b6 b7 SSCK CPOS = 0 (“H” when clock stops) b0SSO, SSI
• SSUMS = 1 (4-wire bus communication mode) and CPHS = 0 (data change at odd edge) b1 b2 b3 b4 b5 b6 b7 SSCK CPOS = 1 (“L” when clock stops) SCS SSCK CPOS = 0 (“H” when clock stops) SSO, SSI
• SSUMS = 1 (4-wire bus communication mode) and CPHS = 1 (data download at odd edge) SSCK CPOS = 1 (“L” when clock stops) SCS b0 b1 b2 b3 b4 b5 b6 b7 CPHS and CPOS: Bits in SSMR register, SSUMS: Bit in SSMR2 register

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24.3.2 SS Shift Register (SSTRSR)

The SSTRSR register is a shift register for transmitting and receiving serial data. When transmit data is transferred from the SSTDR regi ster to the SSTRSR register and the MLS bit in the SSMR register is set to 0 (MSB-first), the bit 0 in the SSTDR register is transferred to bit 0 in the SSTRSR register. When the MLS bit is set to 1 (LSB-first), bit 7 in the SSTDR register is transferred to bit 0 in the SSTRSR register.

24.3.2.1 Association between Data I/O Pins and SS Shift Register

The connection between the data I/O pins and SSTRSR re gister (SS shift register ) changes according to a combination of the MSS bit in the SSCRH register an d the SSUMS bit in the SSMR2 register. The connection also changes according to the BIDE bit in the SSMR2 register. Figure 24.3 shows the Association between Data I/O Pins and SSTRSR Register. Figure 24.3 Association between Data I/O Pins and SSTRSR Register SSTRSR register SSO SSI

• SSUMS = 0 (clock synchronous communication mode) SSTRSR register SSO SSI
• SSUMS = 1 (4-wire bus communication mode), BIDE = 0 (standard mode), and MSS = 0 (operates as slave device) SSTRSR register SSO SSI
• SSUMS = 1 (4-wire bus communication mode), BIDE = 0 (standard mode), and MSS = 1 (operates as master device) SSTRSR register SSO SSI
• SSUMS = 1 (4-wire bus communication mode) and BIDE = 1 (bidirectional mode)

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24.3.3 Interrupt Requests

Synchronous serial communication unit has five interrupt requests: transmit data empt y, transmit end, receive data full, overrun error, and conflict error. Since these interrupt requests are assigned to the synchronous serial communication unit interrupt vector table, determining interrupt sources by flags is required. Table 24.3 lists the Synchronous Serial Communication Unit Interrupt Requests. CEIE, RIE, TEIE and TIE: Bits in SSER register ORER, RDRF, TEND and TDRE: Bits in SSSR register If the generation conditions in Table 24.3 are met, a s ynchronous serial communication unit interrupt request is generated. Set each interrupt source to 0 by a synchronous serial communication unit interrupt routine. However, the TDRE and TEND bits are automatically set to 0 by writing transmit data to the SSTDR register and the RDRF bit is automatically set to 0 by reading the SSRDR register. In particular, the TDRE bit is set to 1 (data transmitted from registers SSTDR to SST RSR) at the same time transmit data is written to the SSTDR register. Setting the TDRE bit to 0 (data not transmitted from re gisters SSTDR to SSTRSR) can cause an additional byte of data to be transmitted. Table 24.3 Synchronous Serial Communication Unit Interrupt Requests Interrupt Request Abbreviation Generation Condition Transmit data empty TXI TIE = 1, TDRE = 1 Transmit end TEI TEIE = 1, TEND = 1 Receive data full RXI RIE = 1, RDRF = 1 Overrun error OEI RIE = 1, ORER = 1 Conflict error CEI CEIE = 1, CE = 1

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24.3.4 Communication Mo des and Pin Functions

Synchronous serial communication unit switches the func tions of the I/O pins in each communication mode according to the setting of the MSS bit in the SSCRH register and bits RE and TE in the SSER register. Table 24.4 lists the Association between Communication Modes and I/O Pins. Notes: 1. This pin can be used as a programmable I/O port. 2. Do not set both bits TE and RE to 1 in 4-wire bus (bidirectional) communication mode. SSUMS and BIDE: Bits in SSMR2 register MSS: Bit in SSCRH register TE and RE: Bits in SSER register Table 24.4 Association between Communication Modes and I/O Pins Communication Mode Bit Setting Pin State SSUMS BIDE MSS TE RE SSI SSO SSCK Clock synchronous communication mode 0D i s a b l e d 001I n p u t − (1) Input 10 − (1) Output Input

1 Input Output Input

101I n p u t − (1) Output 10 − (1) Output Output

1 Input Output Output

10 001 − (1) Input Input 1 0 Output − (1) Input

1 Output Input Input

101I n p u t − (1) Output 10 − (1) Output Output (bidirectional) communication mode (2) 11 001 − (1) Input Input 10 − (1) Output Input 101 − (1) Input Output 10 − (1) Output Output

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24.4 Clock Synchronous Communication Mode

24.4.1 Initialization in Clock Synchronous Communication Mode

Figure 24.4 shows Initialization in Clock Synchronous Communication Mode. To initialize, set the TE bit in the SSER register to 0 (transmit disabled) and the RE bit to 0 (receive disabled) before data transmission or reception. Set the TE bit to 0 and the RE bit to 0 before changing the communication mode or format. Setting the RE bit to 0 does not change the contents of flags RDRF and ORER or the contents of the SSRDR register. Figure 24.4 Initialization in Clock Synchronous Communication Mode Start SSMR2 register SSUMS bit ← 0 SSCRH register Set bits CKS0 to CKS2 Set RSSTP bit SSSR register ORER bit ← 0 (1) SSER register RE bit ← 1 (receive) TE bit ← 1 (transmit) Set bits RIE, TEIE, and TIE End Note: 1. Write 0 after reading 1 to set the ORER bit to 0. SSER register RE bit ← 0 TE bit ← 0 SSMR2 register SCKS bit ← 1 Set SOOS bit SSCRH register Set MSS bit SSMR register CPHS bit ← 0 CPOS bit ← 0 Set MLS bit

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24.4.2 Data Transmission

Figure 24.5 shows an Example of Synchronous Serial Communication Unit Operation for Data Transmission (Clock Synchronous Communication Mode). During data transmission, the synchronous serial communication unit operates as described below. When synchronous serial communication unit is set as a master device, it outputs a synchronous clock and data. When synchronous serial communication unit is set as a slave device, it outputs data synchronized with the input clock. When the TE bit is set to 1 (transmit enabled) before writing the transmit data to the SSTDR register, the TDRE bit is automatically set to 0 (data not transferred from registers SSTDR to SSTRSR) and the data is transferred from registers SSTDR to SSTRSR. After the TDRE bit is set to 1 (data transferred from registers SSTDR to SSTRSR), transmission starts. When the TIE bit in the SSER register is set to 1, the TXI in terrupt request is generated. When one frame of data is transferred while the TDRE bit is set to 0, data is transferred from registers SSTDR to SSTRSR and transmission of the next frame is star ted. If the 8th bit is transmitted while the TDRE bit is set to 1, the TEND bit in the SSSR register is set to 1 (the TDRE bit is set to 1 when the last bit of the transmit data is transmitted) and the state is retained. The TEI interrupt request is generated when the TEIE bit in the SSER register is set to 1 (transmit-end interrupt request enabled). The SSCK pin is fixed “H” after transmit-end. Transmission cannot be performed while the ORER bit in the SSSR register is set to 1 (overrun error). Confirm that the ORER bit is set to 0 before transmission. Figure 24.6 shows a Sample Flowchart of Data Transmission (Clock Synchronous Communication Mode). The data transfer length can be set from 8 to 16 bits using the SSBR register. Figure 24.5 Example of Synchronous Serial Communication Unit Operation for Data Transmission (Clock Synchronous Communication Mode) SSCK b0SSO

• SSUMS = 0 (clock synchronous communication mode), CPHS = 0 (data change at odd numbers), CPOS = 0 (“H” when clock stops), and BS3 to BS0 = 1000b (8 bits) b1 b7b0 b1b7 1 frame TDRE bit in SSSR register 0 TEND bit in SSSR register 0 TEI interrupt request generation Write data to SSTDR registerProcessing by program 1 frame TXI interrupt request generation BS0 to BS3: Bits in SSBR register CPHS, CPOS: Bits in SSMR register SSUMS: Bit in SSMR2 register

R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 370 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 24.6 Sample Flowchart of Data Transmission (Clock Synchronous Communication Mode) Start Initialization Read TDRE bit in SSSR register SSSR register TEND bit ← 0 (1) End TDRE = 1 ? Write transmit data to SSTDR register Data transmission continues? Read TEND bit in SSSR register TEND = 1 ? No Yes Yes No No Yes SSER register TE bit ← 0 (1) (2) (3) (1) After reading the SSSR register and confirming that the TDRE bit is set to 1, write the transmit data to the SSTDR register. When the transmit data is written to the SSTDR register, the TDRE bit is automatically set to 0. (2) Determine whether data transmission continues. (3) When data transmission is completed, the TEND bit is set to 1. Set the TEND bit to 0 and the TE bit to 0 and complete transmit mode. Note: 1. Write 0 after reading 1 to set the TEND bit to 0.

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24.4.3 Data Reception

Figure 24.7 shows an Ex ample of Synchronou s Serial Communicat ion Unit Operation for Data Reception (Clock Synchronous Communication Mode). During data reception, synchronous serial communication unit operates as described below. When the synchronous serial communication unit is set as the ma ster device, it outputs a synchronous clock and inputs data. When synchronous serial communication unit is set as a slave device, it inputs data synchronized with the input clock. When synchronous serial co mmunication unit is set as a master device, it outputs a recei ve clock and starts receiving by performing dummy read of the SSRDR register. After 8 bits of data are received, the RDRF bit in the SSSR register is set to 1 (data in the SSRDR register) and receive data is stored in the SSRDR register. When the RIE bit in the SSER register is set to 1 (RXI and OEI interrupt requests enabled), the RXI interrupt request is generated. If the SSDR register is read, the RDRF bit is automatically set to 0 (no data in the SSRDR register). Read the receive data after setting the RSSTP bit in the SSCRH register to 1 (after receiving 1 byte of data, the receive operation is completed). Synchronous serial co mmunication unit outputs a clock for receiving 8 bits of data and stops. After that, set the RE bit in the SSER re gister to 0 (receive disabled) and the RSSTP bit to 0 (receive operation is continued afte r receiving the 1 byte of data) and read the receive data. If the SSRDR register is read while the RE bit is set to 1 (receive enabled), a receive clock is output again. When the 8th clock rises while the RDRF bit is set to 1, the ORER bit in the SSSR register is set to 1 (overrun error: OEI) and the operation is stopped. When the ORER bit is se t to 1, receive cannot be performed. Confirm that the ORER bit is set to 0 before restarting receive. Figure 24.8 shows a Sample Flowchart of Data R eception (MSS = 1) (Clock Synchronous Communication Mode). The data transfer length can be set from 8 to 16 bits using the SSBR register. Figure 24.7 Example of Synchronous Serial Co mmunication Unit Operation for Data Reception (Clock Synchronous Communication Mode) SSCK b0SSI

• SSUMS = 0 (clock synchronous communic ation mode), CPHS = 0 (data download at even edges), CPOS bit = 0 (“H” when clock stops), and BS3 to BS0 = 1000b (8 bits) b0b7 1 frame RDRF bit in SSSR register 0 RSSTP bit in SSCRH register 0 Dummy read in SSRDR register Processing by program RXI interrupt request generation b0b7 b7 1 frame RXI interrupt request generation Read data in SSRDR register Read data in SSRDR register Set RSSTP bit to 1 RXI interrupt request generation BS0 to BS3: Bits in SSBR register CPHS, CPOS: Bits in SSMR register SSUMS: Bit in SSMR2 register

R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 372 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 24.8 Sample Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication Mode) Start Initialization Dummy read of SSRDR register Read receive data in SSRDR register Read ORER bit in SSSR register Last data received? Read RDRF bit in SSSR register RDRF = 1 ? No Yes Yes No No Yes (1) (2) (3) (1) After setting each register in the synchronous serial communication unit register, a dummy read of the SSRDR register is performed and the receive operation is started. (2) Determine whether it is the last 1 byte of data to be received. If so, set to stop after the data is received. (3) If a receive error occurs, perform error (6) processing after reading the ORER bit. Then set the ORER bit to 0. Transmission/reception cannot be restarted while the ORER bit is set to 1. (4) Confirm that the RDRF bit is set to 1. If the RDRF bit is set to 1, read the receive data in the SSRDR register. When the SSRDR register is read, the RDRF bit is automatically set to 0. ORER = 1 ? End Read receive data in SSRDR register Read ORER bit in SSSR register Read RDRF in SSSR register RDRF = 1 ? No Yes ORER = 1 ? SSER register RE bit ← 0 SSCRH register RSSTP bit ← 0 SSCRH register RSSTP bit ← 1 Overrun error processing No Yes (4) (5) (6) (7) (7) Confirm that the RDRF bit is set to 1. When the receive operation is completed, set the RSSTP bit to 0 and the RE bit to 0 before reading the last 1 byte of data. If the SSRDR register is read before setting the RE bit to 0, the receive operation is restarted again. (5) Before the last 1 byte of data is received, set the RSSTP bit to 1 and stop after the data is received.

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24.4.3.1 Data Transmission/Reception

Data transmission/reception is an operation combining data transmission and reception which were described earlier. Transmission/reception is started by writing data to the SSTDR register. When the 8th clock rises or the ORER bit is set to 1 (overrun error) while the TDRE bit is set to 1 (data is transferred from registers SSTDR to SSTRSR), the transmit/receive operation is stopped. When switching from transmit mode (TE = 1) or receive mode (RE = 1) to transmit/receive mode (TE = RE = 1), set the TE bit to 0 and RE bit to 0 before switching. After confirming that the TEND bit is set to 0 (the TDRE bit is set to 0 when the last bit of the transmit data is transmitted), the RDRF bit is set to 0 (no data in the SSRDR register), and the ORER bit is set to 0 (no overrun error), set bits TE and RE to 1. Figure 24.9 shows a Sample Flowchart of Data Tr ansmission/Reception (Clock Synchronous Communication Mode). The data transfer length can be set from 8 to 16 bits using the SSBR register.

R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 374 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 24.9 Sample Flowchart of Data Transmission/Reception (Clock Synchronous Communication Mode) Start Initialization Read TDRE bit in SSSR register SSSR register TEND bit ← 0 (1) End TDRE = 1 ? Write transmit data to SSTDR register Data transmission (2) continues? No Yes Yes No SSER register RE bit ← 0 TE bit ← 0 (1) (2) (3) (1) After reading the SSSR register and confirming that the TDRE bit is set to 1, write the transmit data to the SSTDR register. When the transmit data is written to the SSTDR register, the TDRE bit is automatically set to 0. (5) Set the TEND bit to 0 and bits RE and TE in (6) the SSER register to 0 before ending transmit/ receive mode. Read receive data in SSRDR register Read RDRF bit in SSSR register RDRF = 1 ? No Yes (4) (2) Confirm that the RDRF bit is set to 1. If the RDRF bit is set to 1, read the receive data in the SSRDR register. When the SSRDR register is read, the RDRF bit is automatically set to 0. (3) Determine whether the data transmission continues (5) Note: 1. Write 0 after reading 1 to set the TEND bit to 0. Read TEND bit in SSSR register TEND = 1 ? Yes No (6) (4) When the data transmission is completed, the TEND bit in the SSSR register is set to 1.

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24.5 Operation in 4-Wire Bus Communication Mode

In 4-wire bus communication mode, a 4-wire bus consisting of a clock line, a data input line, a data output line, and a chip select line is used for communication. This mode includes bidirectional mode in which the data input line and data output line function as a single pin. The data input line and output line change according to th e settings of the MSS bit in the SSCRH register and the BIDE bit in the SSMR2 register. For details, refer to 24.3.2.1 Association between Data I/O Pins and SS Shift Register . In this mode, clock polarity, phase, and data sett ings are performed by bits CPOS and CPHS in the When this MCU is set as the master device, the chip select line controls out put. When synchronous serial communication unit is set as a slave device, the chip select line controls input. When it is set as the master device, the chip select line controls output of the SCS pin or controls output of a general port according to the setting of the CSS1 bit in the SSMR2 register. When the MCU is set as a slave device, the chip select line sets the SCS pin as an input pin by setting bits CSS1 and CSS0 in the SSMR2 register to 01b. In 4-wire bus communication mode, the MLS bit in the SSMR register is set to 0 and communication is performed MSB-first.

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24.5.1 Initialization in 4-Wire Bus Communication Mode

Figure 24.10 shows Initialization in 4-Wire Bus Communication Mode. Before the data transit/receive operation, set the TE bit in the SSER register to 0 (tra nsmit disabled), the RE bit in the SSER register to 0 (receive disabled), and initialize the synchronous serial communication unit. To change the communication mode or format, set the TE bit to 0 and the RE bit to 0 before making the change. Setting the RE bit to 0 does not change the settings of flags RDRF and ORER or the contents of the SSRDR register. Figure 24.10 Initialization in 4-Wire Bus Communication Mode Start SSMR2 register SSUMS bit ← 1 SSCRH register Set bits CKS0 to CKS2 Set RSSTP bit SSSR register ORER bit ← 0 (1) SSER register RE bit ← 1 (receive) TE bit ← 1 (transmit) Set bits RIE, TEIE, and TIE End SSER register RE bit ← 0 TE bit ← 0 (2) Set the BIDE bit to 1 in bidirectional mode and set the I/O of the SCS pin by bits CSS0 and CSS1. (1) (1) The MLS bit is set to 0 for MSB-first transfer. The clock polarity and phase are set by bits CPHS and CPOS. (2) Note: 1. Write 0 after reading 1 to set the ORER bit to 0. SSMR2 register SCKS bit ← 1 Set bits SOOS, CSS0 to CSS1, and BIDE SSCRH register Set MSS bit SSMR register Set bits CPHS and CPOS MLS bits ← 0

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24.5.2 Data Transmission

Figure 24.11 shows an Example of Synchronous Serial Communication Unit Operation during Data Transmission (4-Wire Bus Communication Mode). During the data transmit operation, synchronous serial communication unit operates as described below. When the MCU is set as the master device, it outputs a synchronous clock and data. When the MCU is set as a slave device, it outputs data in synchronization with the input clock while the SCS pin is “L”. When the transmit data is written to the SSTDR register after setting the TE bit to 1 (transmit enabled), the TDRE bit is automatically set to 0 (data has not been transferred from registers SSTDR to SSTRSR) and the data is transferred from registers SSTDR to SSTRSR. Afte r the TDRE bit is set to 1 (data is transferred from registers SSTDR to SSTRSR), transmissi on starts. When the TIE bit in the SSER register is set to 1, a TXI interrupt request is generated. After 1 frame of data is transferred while the TDRE bit is set to 0, the data is transferred from registers SSTDR to SSTRSR and transmission of the next frame is started. If the 8th bit is transmitted while TDRE is set to 1, TEND in the SSSR register is set to 1 (when the last bit of the transmit data is transmitted, the TDRE bit is set to 1) and the state is retained. If the TEIE bit in the SSER register is set to 1 (transmit-end interrupt requests enabled), a TEI interrupt request is generated. The SSCK pin remains “H” after transmit-end and the SCS pin is held “H”. When transmitting continuously while the SCS pin is held “L”, write the next transmit data to the SSTDR register before transmitting the 8th bit. Transmission cannot be performed while the ORER bit in the SSSR register is set to 1 (overrun error). Confirm that the ORER bit is set to 0 before transmission. In contrast to the clock synchronous communication mode, the SSO pin is placed in high-impedance state while the SCS pin is placed in high-impedance state when opera ting as a master device and the SSI pin is placed in high-impedance state while the SCS pin is placed in “H” input state when operating as a slave device. The sample flowchart is the same as that for th e clock synchronous communication mode (refer to Figure 24.6 Sample Flowchart of Data Transmission (Clock Synchronous Communication Mode)). The data transfer length can be set from 8 to 16 bits using the SSBR register.

R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 378 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 24.11 Example of Synchronous Serial Communication Unit Operation during Data Transmission (4-Wire Bus Communication Mode) TDRE bit in SSSR register 0 TEND bit in SSSR register 0 Data write to SSTDR registerProcessing by program SSCK b0SSO

• CPHS bit = 0 (data change at odd edges), CPOS bit = 0 (“H” when clock stops), and BS3 to BS0 = 1000b (8 bits) SCS (output) SSCK
• CPHS bit = 1 (data change at even edges). CPOS bit = 0 (“H” when clock stops), and BS3 to BS0 = 1000b (8 bits) BS0 to BS3: Bits in SSBR register CPHS, CPOS: Bits in SSMR register 1 frame TDRE bit in SSSR register 0 TEND bit in SSSR register 0 Data write to SSTDR registerProcessing by program 1 frame High-impedance b0b7 High-impedance SCS (output) TXI interrupt request is generated b7 b0SSO 1 frame 1 frame b6 b6 TXI interrupt request is generated TEI interrupt request is generated b6 b7 b0b6 TEI interrupt request is generated TXI interrupt request is generated TXI interrupt request is generated

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24.5.3 Data Reception

Figure 24.12 shows an Example of Sy nchronous Serial Communication Unit Operation during Data Reception (4-Wire Bus Communication Mode). During data reception, synchronous serial communication unit operates as described below. When the MCU is set as the master device, it outputs a synchronous clock and inputs data. When the MCU is set as a slave device, it outputs data synchr onized with the inpu t clock while the SCS pin receives “L” input. When the MCU is set as the master device, it outputs a receive clock and starts receiving by performing a dummy read of the SSRDR register. After 8 bits of data are received, the RDRF bit in the SSSR register is set to 1 (data in the SSRDR register) and receive data is stored in the SSRDR register. When the RIE bit in the SSER register is set to 1 (RXI and OEI interrupt requests enabled), an RXI interrupt request is generated. When the SSRDR register is read, the RDRF bit is automatically set to 0 (no data in the SSRDR register). Read the receive data after setting the RSSTP bit in th e SSCRH register to 1 (after receiving 1-byte data, the receive operation is completed). Synchronous serial co mmunication unit outputs a clock for receiving 8 bits of data and stops. After that, set the RE bit in the SSER re gister to 0 (receive disabled) and the RSSTP bit to 0 (receive operation is continued after receiving 1-byte data) and read the receive data. When the SSRDR register is read while the RE bit is set to 1 (receive enabled), a receive clock is output again. When the 8th clock rises while the RDRF bit is set to 1, the ORER bit in the SSSR register is set to 1 (overrun error: OEI) and the operation is st opped. When the ORER bit is set to 1, reception can not be performed. Confirm that the ORER bit is set to 0 before restarting reception. The timing with which bits RDRF and ORER are set to 1 varies depending on the setting of the CPHS bit in the SSMR register. Figure 24.12 shows when bits RDRF and ORER are set to 1. When the CPHS bit is set to 1 (dat a download at the odd edges), bits RD RF and ORER are set to 1 at some point during the frame. The sample flowchart is the same as that for th e clock synchronous communication mode (refer to Figure 24.8 Sample Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication Mode)). The data transfer length can be set from 8 to 16 bits using the SSBR register.

R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 380 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 24.12 Example of Synchronous Serial Communication Unit Operation during Data Reception (4-Wire Bus Communication Mode) SSCK b0SSI

• CPHS bit = 0 (data download at even edges), CPOS bit = 0 (“H” when clock stops), and BS3 to BS0 = 1000b (8 bits) SCS (output) SSCK
• CPHS bit = 1 (data download at odd edges), CPOS bit = 0 (“H” when clock stops), and BS3 to BS0 = 1000b (8 bits) BS0 to BS3: Bits in SSBR register CPHS and CPOS: Bits in SSMR register 1 frame RDRF bit in SSSR register 0 RSSTP bit in SSCRH register 0 Dummy read in SSRDR register Processing by program 1 frame High-impedance b0b7 High-impedance SCS (output) b7 b0 Data read in SSRDR register RXI interrupt request is generated RXI interrupt request is generated Data read in SSRDR register RXI interrupt request is generated b0b7b0b7b7 b0SSI 1 frame RDRF bit in SSSR register 0 RSSTP bit in SSCRH register 0 Dummy read in SSRDR register Processing by program 1 frame Data read in SSRDR register RXI interrupt request is generated RXI interrupt request is generated RXI interrupt request is generated Set RSSTP bit to 1 Data read in SSRDR register Set RSSTP bit to 1

R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 381 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

24.5.4 SCS Pin Control and Arbitration

When setting the SSUMS bit in the SSMR2 register to 1 (4-wire bus communication mode) and the CSS1 bit in the SSMR2 register to 1 (functions as SCS output pin), set the MSS bit in the SSCRH register to 1 (operates as the master device) and check the arbitration of the SCS pin before starting serial transfer. If synchronous serial communication unit detects that the synchronized internal SCS signal is held “L” in this period, the CE bit in the SSSR register is set to 1 (conflict error) and the MS S bit is automatically set to 0 (operates as a slave device). Figure 24.13 shows the Arbitration Check Timing. Future transmit operations are not performed while the CE bi t is set to 1. Set the CE bit to 0 (no conflict error) before starting transmission. Figure 24.13 Arbitration Check Timing Data write to SSTDR register Maximum time of SCS internal synchronization During arbitration detection High-impedance SCS input Internal SCS (synchronization) MSS bit in SSCRH register Transfer start CE SCS output

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24.6 Notes on Synchronous Se rial Communication Unit

Set the IICSEL bit in the SSUIICSR register to 0 (select SSU function) to use the synchronous serial communication unit function.

R8C/32A Group 25. I2C bus Interface REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 383 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 25. I 2C bus Interface The I2C bus interface is the circuit that performs serial communi cation based on the data transfer format of the Philips I2C bus.

25.1 Overview

Table 25.1 lists the I 2C bus Interface Specifications , Figure 25.1 shows an I 2C bus interface Block Diagram, and Figure 25.2 shows the External Circ uit Connection Example of Pins SCL and SDA, Table 25.2 lists the Pin Configuration of I2C bus Interface. * I2C bus is a trademark of Koninklijke Philips Electronics N. V . Note: 1. All sources use one interrupt vector for I 2C bus interface. Table 25.1 I 2C bus Interface Specifications Item Specification Communication formats •I2C bus format - Selectable as master/slave device. - Continuous transmit/receive operation (because the shift register, transmit data register, and receive data register are independent.) - Start/stop conditions are automatically generated in master mode. - Automatic loading of the acknowledge bit during transmission - Bit synchronization/wait function (In master mode, the state of the SCL signal is monitored per bit and the timing is synchronized automatically. If the transfer is not possible yet, the SCL signal goes “L” and the interface stands by.) - Support for direct drive of pins SCL and SDA (N-channel open-drain output)

• Clock synchronous serial format - Continuous transmit/receive operation (because the shift register, transmit data register, and receive data register are independent.) I/O pins SCL (I/O): Serial clock I/O pin SDA (I/O): Serial data I/O pin Transfer clocks • When the MST bit in the ICCR1 register is set to 0. External clock (input from the SCL pin)
• When the MST bit in the ICCR1 register is set to 1. Internal clock selected by bits CKS0 to CKS3 in the ICCR1 register (output from the SCL pin) Receive error detection • Overrun error detection (clock synchronous serial format) Indicates an overrun error during reception. When the last bit of the next unit of data is received while the RDRF bit in the ICSR register is set to 1 (data in the ICDRR register), the AL bit is set to 1. Transmit data empty (including when slave address matches), end of transmission, receive data full (including when slave address matches), arbitration lost, NACK detection, and stop condition detection (1) Transmit data empty, end of transmission, receive data full, and overrun error Selectable functions •I2C bus format - Selectable output level for the acknowledge signal during reception.
• Clock synchronous serial format - MSB-first or LSB-first selectable as the data transfer direction.

R8C/32A Group 25. I2C bus Interface REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 384 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 25.1 I 2C bus interface Block Diagram Table 25.2 Pin Configuration of I 2C bus Interface Pin Name Assigned Pin Function SCL P3_5 Clock I/O pin SDA P3_7 Data I/O pin ICCR1 register Data bus ICCR2 register ICMR register ICDRT register SAR register ICSR register Address comparison circuit Output control SCL Interrupt request (TXI, TEI, RXI, STPI, NAKI) Transfer clock generation circuit ICDRS register ICDRR register Bus state check circuit Arbitration check circuit ICIER register Interrupt generation circuit Transmit/receive control circuit Noise canceller SDA Output control Noise canceller

R8C/32A Group 25. I2C bus Interface REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 385 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 25.2 External Circuit Connect ion Example of Pins SCL and SDA SCL SDA SCL input SCL output SDA input SDA output (Master) VCC VCC SCL SDA SCL input SCL output SDA input SDA output (Slave 1) SCL SDA SCL input SCL output SDA input SDA output SCL SDA (Slave 2)

R8C/32A Group 25. I2C bus Interface REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 386 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

25.2 Registers

25.2.1 Module Standby Control Register (MSTCR)

Notes: 1. When the MSTIIC bit is set to 1 (standby), any access to the SSU or the I2C bus associated registers (addresses 0193h to 019Dh) is disabled. 2. When the MSTTRC bit is set to 1 (standby), any access to the timer RC associated registers (addresses 0120h to 0133h) is disabled.

25.2.2 SSU/IIC Pin Select Register (SSUIICSR)

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — MSTTRC MSTTRD MSTIIC — — — A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b1 — b2 — b3 MSTIIC SSU, I 2C bus standby bit 0: Active 1: Standby (1) R/W b4 MSTTRD Peripheral function power consumption reduce bit Set to 1. The power consumption of the peripheral functions can be reduced. R/W b5 MSTTRC Timer RC standby bit 0: Active 1: Standby (2) R/W b6 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b7 — Address 018Ch B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 IICSEL SSU/I2C bus switch bit 0: SSU function selected 1: I2C bus function selected R/W b1 — Reserved bit Set to 0. R/W b2 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b3 — b4 — Reserved bits Set to 0. R/W b5 — b6 — b7 —

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25.2.3 IIC bus Transmit Data Register (ICDRT)

25.2.4 IIC bus Receive Data Register (ICDRR)

B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 11111111 Bit Function R/W b7 to b0 This register stores transmit data. When the ICDRS register is detected as empty, the stored transmit data item is transferred to the ICDRS register and data transmission starts. When the next unit of transmit data is written to the ICDRT register while data is transmitted to the ICDRS register, continuous transmission is enabled. When the MLS bit in the ICMR register is set to 1 (data transfer with LSB-first), the MSB-LSB inverted data is read after the data is written to the ICDRT register. R/W Address 0196h B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 11111111 Bit Function R/W b7 to b0 This register stores receive data. When the ICDRS register receives 1 byte of data, the receive data is transferred to the ICDRR register and the next receive operation is enabled. R

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25.2.5 IIC bus Control Register 1 (ICCR1)

Notes: 1. Set according to the necessary transfer rate in master mode. Refer to Table 25.3 Transfer Rate Examples for the transfer rate. This bit is used for maintaining the setup time in transmit mode of slave mode. The time is 10Tcyc when the CKS3 bit is set to 0 and 20Tcyc when the CKS3 bit is set to 1. (1Tcyc = 1/f1(s)) 2. Rewrite the TRS bit between transfer frames. 3. When the first 7 bits after the start condition in slave receive mode match the slave address set in the SAR register and the 8th bit is set to 1, the TRS bit is set to 1. 4. In master mode with the I 2C bus format, if arbitration is lost, bits MST and TRS are set to 0 and the IIC enters slave receive mode. 5. When an overrun error occurs in master receive mode with the clock synchronous serial format, the MST bit is set to 0 and the I2C bus enters slave receive mode. 6. In multimaster operation, use the MOV instruction to set bits TRS and MST. Address 0198h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol ICE RCVD MST TRS CKS3 CKS2 CKS1 CKS0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 CKS0 Transmit clock select bits 3 to 0 (1) b3 b2 b1 b0 0 0 0 0: f1/28 0 0 0 1: f1/40 0 0 1 0: f1/48 0 0 1 1: f1/64 0 1 0 0: f1/80 0 1 0 1: f1/100 0 1 1 0: f1/112 0 1 1 1: f1/128 1 0 0 0: f1/56 1 0 0 1: f1/80 1 0 1 0: f1/96 1 0 1 1: f1/128 1 1 0 0: f1/160 1 1 0 1: f1/200 1 1 1 0: f1/224 1 1 1 1: f1/256 R/W b1 CKS1 R/W b2 CKS2 R/W b3 CKS3 R/W b4 TRS Transfer/receive select bit (2, 3, 6) b5 b4 0 0: Slave Receive Mode (4) 0 1: Slave Transmit Mode 1 0: Master Receive Mode 1 1: Master Transmit Mode R/W b5 MST Master/slave select bit (5, 6) R/W b6 RCVD Receive disable bit After reading the ICDRR register while the TRS bit is set to 0 0: Next receive operation continues 1: Next receive operation disabled R/W b7 ICE I2C bus interface enable bit 0: This module is halted (Pins SCL and SDA are set to a port function) 1: This module is enabled for transfer operations (Pins SCL and SDA are in a bus drive state) R/W

R8C/32A Group 25. I2C bus Interface REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 389 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

25.2.6 IIC bus Control Register 2 (ICCR2)

Notes: 1. When rewriting the SDAO bit, write 0 to the SDAOP bit simultaneously using the MOV instruction. 2. Do not write to the SDAO bit during a transfer operation. 3. Enabled in master mode. When writing to the BBSY bit, write 0 to the SCP bit simultaneously using the MOV instruction. Execute the same way when a start condition is regenerated. 4. Disabled when the clock synchronous serial format is used. Address 0199h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol BBSY SCP SDAO SDAOP SCLO — IICRST — A f t e r R e s e t 01111101 Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b1 IICRST I 2C bus control block reset bit When hang-up occurs due to communication failure during I2C bus interface operation, writing 1 resets the control block of the I2C bus interface without setting ports or initializing registers. R/W b2 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b3 SCLO SCL monitor flag 0: SCL pin is set to “L” 1: SCL pin is set to “H” R b4 SDAOP SDAO write protect bit When rewriting the SDAO bit, write 0 simultaneously (1). When read, the content is 1. R/W b5 SDAO SDA output value control bit When read 0: SDA pin output is held “L” 1: SDA pin output is held “H” When written (1, 2) 0: SDA pin output is changed to “L” 1: SDA pin output is changed to high-impedance (“H” output via external pull-up resistor) R/W b6 SCP Start/stop condition generation disable bit When writing to the to BBSY bit, write 0 simultaneously (3). When read, the content is 1. Writing 1 is invalid. R/W b7 BBSY Bus busy bit (4) When read: 0: Bus is released (SDA signal changes from “L” to “H” while SCL signal is held “H”) 1: Bus is occupied (SDA signal changes from “H” to “L” while SCL signal is held “H”) When written (3): 0: Stop condition generated 1: Start condition generated R/W

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25.2.7 IIC bus Mode Register (ICMR)

Notes: 1. Rewrite between transfer frames. When writing values other than 000b, write when the SCL signal is “L”. 2. When writing to bits BC0 to BC2, write 0 to the BCWP bit simultaneously using the MOV instruction. 3. After data including the acknowledge bit is transferred, these bits are automatically set to 000b. When a start condition is detected, these bits are automatically set to 000b. 4. Do not rewrite when the clock synchronous serial format is used. 5. The setting value is valid in master mode with the I 2C bus format. It is invalid in slave mode with the I 2C bus format or when the clock synchronous serial format is used. 6. Set to 0 when the I 2C bus format is used. Address 019Ah B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol MLS WAIT — — BCWP BC2 BC1 BC0 A f t e r R e s e t 00011000 Bit Symbol Bit Name Function R/W b0 BC0 Bit counters 2 to 0 I2C bus format (Read: Number of remaining transfer bits; Write: Number of next transfer data bits) (1, 2). b2 b1 b0 0 0 0: 9 bits (3) 0 0 1: 2 bits 0 1 0: 3 bits 0 1 1: 4 bits 1 0 0: 5 bits 1 0 1: 6 bits 1 1 0: 7 bits 1 1 1: 8 bits Clock synchronous serial format (Read: Number of remaining transfer bits; Write: Always 000b). b2 b1 b0 0 0 0: 8 bits 0 0 1: 1 bit 0 1 0: 2 bits 0 1 1: 3 bits 1 0 0: 4 bits 1 0 1: 5 bits 1 1 0: 6 bits 1 1 1: 7 bits R/W b1 BC1 R/W b2 BC2 R/W b3 BCWP BC write protect bit When rewriting bits BC0 to BC2, write 0 simultaneously (2, 4). When read, the content is 1. R/W b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b5 — Reserved bit Set to 0. R/W b6 WAIT Wait insertion bit (5) 0: No wait states (Data and the acknowledge bit are transferred consecutively) 1: Wait state (After the clock of the last data bit falls, a “L” period is extended for two transfer clocks) R/W b7 MLS MSB-first/LSB-first select bit 0: Data transfer with MSB-first (6) 1: Data transfer with LSB-first R/W

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25.2.8 IIC bus Interrupt En able Register (ICIER)

Notes: 1. An overrun error interrupt request is generated when the clock synchronous format is used. 2. Set the STIE bit to 1 (stop condition detection interrupt request enabled) when the STOP bit in the ICSR register is set to 0. Address 019Bh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TIE TEIE RIE NAKIE STIE ACKE ACKBR ACKBT A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 ACKBT Transmit acknowledge select bit 0: In receive mode, 0 is transmitted as the acknowledge bit. 1: In receive mode, 1 is transmitted as the acknowledge bit. R/W b1 ACKBR Receive acknowledge bit 0: In transmit mode, the acknowledge bit received from receive device is set to 0. 1: In transmit mode, the acknowledge bit received from receive device is set to 1. R b2 ACKE Acknowledge bit detection select bit 0: Content of the receive acknowledge bit is ignored and continuous transfer is performed. 1: When the receive acknowledge bit is set to 1, continuous transfer is halted. R/W b3 STIE Stop condition detection interrupt enable bit 0: Stop condition detection interrupt request disabled 1: Stop condition detection interrupt request enabled (2) R/W b4 NAKIE NACK receive interrupt enable bit 0: NACK receive interrupt request and arbitration lost/ overrun error interrupt request disabled 1: NACK receive interrupt request and arbitration lost/ overrun error interrupt request (1) R/W b5 RIE Receive interrupt enable bit 0: Receive data full and overrun error interrupt request disabled 1: Receive data full and overrun error interrupt request enabled (1) R/W b6 TEIE Transmit end interrupt enable bit 0: Transmit end interrupt request disabled 1: Transmit end interrupt request enabled R/W b7 TIE Transmit interrupt enable bit 0: Transmit data empty interrupt request disabled 1: Transmit data empty interrupt request enabled R/W

R8C/32A Group 25. I2C bus Interface REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 392 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

25.2.9 IIC bus Status Register (ICSR)

Notes: 1. Each bit is set to 0 by reading 1 before writing 0. 2. This flag is enabled in slave receive mode with the I 2C bus format. 3. When two or more master devices attempt to occupy the bus at nearly the same time, if the I 2C bus Interface monitors the SDA pin and the data which the I 2C bus Interface transmits is different, the AL flag is set to 1 and the bus is occupied by another master. 4. The NACKF bit is enabled when the ACKE bit in the ICIER register is set to 1 (when the receive acknowledge bit is set to 1, transfer is halted). 5. The RDRF bit is set to 0 when data is read from the ICDRR register. 6. Bits TEND and TDRE are set to 0 when data is written to the ICDRT register. When accessing the ICSR register co ntinuously, insert one or more NOP instructions between the instructions to access it. Address 019Ch B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TDRE TEND RDRF NACKF STOP AL AAS ADZ A f t e r R e s e t 0000X000 Bit Symbol Bit Name Function R/W b0 ADZ General call address recognition flag (1, 2) This flag is set to 1 when a general call address is detected. R/W b1 AAS Slave address recognition flag (1) This flag is set to 1 when the first frame immediately after the start condition matches bits SVA0 to SVA6 in the SAR register in slave receive mode (slave address detection and general call address detection) R/W b2 AL Arbitration lost flag/overrun error flag (1) I2C bus format: This flag indicates that arbitration has been lost in master mode. This flag is set to 1 (3) when:

• The internal SDA signal and SDA pin level do not match at the rising edge of the SCL signal in master transmit mode
• The SDA pin is held “H” at start condition detection in master transmit/receive mode Clock synchronous format: This flag indicates an overrun error. This flag is set to 1 when:
• The last bit of the next unit of data is received while the RDRF bit is set to 1 R/W b3 STOP Stop condition detection flag (1) This flag is set to 1 when a stop condition is detected after the frame is transferred. R/W b4 NACKF No acknowledge detection flag (1, 4) This flag is set to 1 when no ACKnowledge is detected from the receive device after transmission. R/W b5 RDRF Receive data register full flag (1, 5) This flag is set to 1 when receive data is transferred from registers ICDRS to ICDRR. R/W b6 TEND Transmit end flag (1, 6) I2C bus format: This flag is set to 1 at the rising edge of the 9th clock cycle of the SCL signal while the TDRE bit is set to 1. Clock synchronous format: This flag is set to 1 when the last bit of the transmit frame is transmitted. R/W b7 TDRE Transmit data empty flag (1, 6) This flag is set to 1 when:
• Data is transferred from registers ICDRT to ICDRS and the CDRT register is empty
• The TRS bit in the ICCR1 register is set to 1 (transmit mode)
• A start condition is generated (including retransmission)
• Slave receive mode is changed to slave transmit mode R/W

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25.2.10 Slave Address Register (SAR)

25.2.11 IIC bus Shift Register (ICDRS)

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 FS Format select bit 0: I2C bus format 1: Clock synchronous serial format R/W b1 SVA0 Slave addresses 6 to 0 Set an address different from that of the other slave devices connected to the I2C bus. When the 7 high-order bits of the first frame transmitted after the start condition match bits SVA0 to SVA6 in slave mode of the I 2C bus format, the MCU operates as a slave device. R/W b2 SVA1 R/W b3 SVA2 R/W b4 SVA3 R/W b5 SVA4 R/W b6 SVA5 R/W b7 SVA6 R/W B i t b 7b 6b 5b 4b 3b 2b 1b 0 Bit Function R/W b7 to b0 This register transmits and receives data. During transmission, data is transferred from registers ICRDT to ICDRS and transmitted from the SDA pin. During reception, data is transferred from registers ICDRS to the ICDRR after 1 byte of data reception ends.

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25.3 Common Items for Multiple Modes

25.3.1 Transfer Clock

When the MST bit in the ICCR1 register is set to 0, the transfer clock is the external clock input from the SCL pin. When the MST bit in the ICCR1 register is set to 1, the transfer clock is the internal clock selected by bits CKS0 to CKS3 in the ICCR1 register and the transfer clock is output from the SCL pin. Table 25.3 lists the Transfer Rate Examples. Table 25.3 Transfer Rate Examples ICCR1 Register Transfer Clock Transfer Rate CKS3 CKS2 CKS1 CKS0 f1 = 5 MHz f1 = 8 MHz f1 = 10 MHz f1 = 16 MHz f1 = 20 MHz 0 0 0 0 f1/28 179 kHz 286 kHz 357 kHz 571 kHz 714 kHz 1 f1/40 125 kHz 200 kHz 250 kHz 400 kHz 500 kHz 1 0 f1/48 104 kHz 167 kHz 208 kHz 333 kHz 417 kHz 1 f1/64 78.1 kHz 125 kHz 156 kHz 250 kHz 313 kHz 1 0 0 f1/80 62.5 kHz 100 kHz 125 kHz 200 kHz 250 kHz 1 f1/100 50.0 kHz 80.0 kHz 100 kHz 160 kHz 200 kHz 1 0 f1/112 44.6 kHz 71.4 kHz 89.3 kHz 143 kHz 179 kHz 1 f1/128 39.1 kHz 62.5 kHz 78.1 kHz 125 kHz 156 kHz 1 0 0 0 f1/56 89.3 kHz 143 kHz 179 kHz 286 kHz 357 kHz 1 f1/80 62.5 kHz 100 kHz 125 kHz 200 kHz 250 kHz 1 0 f1/96 52.1 kHz 83.3 kHz 104 kHz 167 kHz 208 kHz 1 f1/128 39.1 kHz 62.5 kHz 78.1 kHz 125 kHz 156 kHz 1 0 0 f1/160 31.3 kHz 50.0 kHz 62.5 kHz 100 kHz 125 kHz 1 f1/200 25.0 kHz 40.0 kHz 50.0 kHz 80.0 kHz 100 kHz

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25.3.2 Interrupt Requests

The I2C bus interface has six interrupt requests when the I 2C bus format is used and four interrupt requests when the clock synchronous serial format is used. Table 25.4 lists the Interrupt Requests of I2C bus Interface. Because these interrupt requests are allocated at the I 2C bus interface interrupt vect or table, the source must be determined bit by bit. STIE, NAKIE, RIE, TEIE, TIE: Bits in ICIER register AL, STOP, NACKF, RDRF, TEND, TDRE: Bits in ICSR register When generation conditions listed in Table 25.4 are met, an I2C bus interface interrupt request is generated. Set the interrupt generation conditions to 0 by the I2C bus interface interrupt routine. Note that bits TDRE and TEND are automatically set to 0 by writing transmit data to the ICDRT register and that the RDRF bit is automatically set to 0 by reading the ICDRR register. Especially, the TDRE bit is set to 0 when writing transmit data to the ICDRT register and set to 1 when transferring data from the ICDRT register to the ICDRS register. If the TDRE bit is further set to 0, additional 1 byte may be transmitted. Also, set the STIE bit to 1 (stop condition detection interrupt request enabled) when the STOP bit is set to 0. Table 25.4 Interrupt Requests of I 2C bus Interface Interrupt Request Generation Condition Format I2C bus Clock Synchronous Serial Transmit data empty TXI TIE = 1 and TDRE = 1 Enabled Enabled Transmit ends TEI TEIE = 1 and TEND = 1 Enabled Enabled Receive data full RXI RIE = 1 and RDRF = 1 Enabled Enabled Stop condition detection STPI STIE = 1 and STOP = 1 Enabled Disabled NACK detection NAKI NAKIE = 1 and AL = 1 (or NAKIE = 1 and NACKF = 1) Enabled Disabled Arbitration lost/overrun error Enabled Enabled

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25.4 I 2C bus Interface Mode

25.4.1 I 2C bus Format

When the FS bit in the SAR register is set to 0, the I2C bus format is used for communication. Figure 25.3 shows the I2C bus Format and Bus Timing. The first frame following the start condition consists of 8 bits. Figure 25.3 I 2C bus Format and Bus Timing S R/W A DATA A A/A P 1 7 1 1 n 1 1 1 1 m (a) I2C bus format (FS = 0) Number of transfer bits (n = 1 to 8) Number of transfer frames (m = 1 or more) S R/W A DATA A/A P 1 7 1 1 n1 1 1 1 m1 (b) I2C bus format When Start Condition is Retransmitted (FS = 0) Upper: Number of transfer bits (n1, n2 = 1 to 8) Lower: Number of transfer frames (m1, m2 = 1 or more) SLA SLA A/A S R/W A DATA 7 1 1 n2 SLA 1 m2 SDA SCL S SLA R/W A DATA A DATA A P 1 to 7 8 9 1 to 7 8 9 1 to 7 8 9 (1) I2C bus format (2) I2C bus timing Legend: S : Start condition The master device changes the SDA signal from “H” to “L” while the SCL signal is held “H”. SLA : Slave address R/W : Indicates the direction of data transmission/reception Data is transmitted when: R/W value is 1: From the slave device to the master device R/W value is 0: From the master device to the slave device A : Acknowledge The receive device sets the SDA signal to “L”. DATA : Transmit/receive data P : Stop condition The master device changes the SDA signal from “L” to “H” while the SCL signal is held “H”.

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25.4.2 Master Transmit Operation

In master transmit mode, the master device outputs th e transmit clock and data, and the slave device returns an acknowledge signal. Figures 25.4 and 25.5 show the Operating Timing in Master Transmit Mode (I2C bus Interface Mode). The transmit procedure and operation in master transmit mode are as follows. (1) Set the STOP bit in the ICSR regist er to 0 for initia lization, and set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Then, set bits WAIT and MLS in the ICMR register and bits CKS0 to CKS3 in the ICCR1 register (initial setting). (2) After confirming that the bus is released by reading the BBSY bit in the ICCR2 register, set bits TRS and MST in the ICCR1 register to master transmit mode. Then, write 1 to the BBSY bit and 0 to the SCP bit with the MOV instruction (start condition generated). This will generate a start condition. (3) After confirming that the TDRE bit in the ICSR regist er is set to 1 (data is transferred from registers ICDRT to ICDRS), write transmit data to the ICDRT register (data in which a slave address and R/W are indicated in the 1st byte). At this time, the TDRE bit is automatically set to 0. When data is transferred from registers ICDRT to ICDRS, the TDRE bit is set to 1 again. (4) When 1 byte of data transmission is completed while the TDRE bit is set to 1, the TEND bit in the ICSR register is set to 1 at the rising edge of the 9th cloc k cycle of the transmit clock. After confirming that the slave device is selected by reading the ACKBR bit in th e ICIER register, write the 2nd byte of data to the ICDRT register. Since the slave device is not acknowl edged when the ACKBR bit is set to 1, generate a stop condition. Stop condition generation is enabled by writing 0 to the BBSY bit and 0 to the SCP bit with the MOV instruction. The SCL signal is fixed “L” until data is ready or a stop condition is generated. (5) Write the transmit data after the 2nd byte to the ICDRT register every time the TDRE bit is set to 1. (6) When the number of bytes to be transmitted is written to the ICDRT register, wait until the TEND bit is set to 1 while the TDRE bit is set to 1. Or wait for NA CK (NACKF bit in ICSR register = 1) from the receive device while the ACKE bit in the ICIER register is set to 1 (when the receive acknowledge bit is set to 1, transfer is halted). Then, generate a stop condition before setting the TEND bit or the NACKF bit to 0. (7) When the STOP bit in the ICSR register is set to 1, return to slave receive mode.

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25.4.3 Master Receive Operation

In master receive mode, the master device outputs the r eceive clock, receives data from the slave device, and returns an acknowledge signal. Figures 25.6 and 25.7 show the Operating Timing in Master Receive Mode (I2C bus Interface Mode). The receive procedure and operation in master receive mode are shown below. (1) After setting the TEND bit in the ICSR register to 0, set the TRS bit in the ICCR1 register to 0 to switch from master transmit mode to master receive mode. Then set the TDRE bit in the ICSR register to 0. (2) Dummy reading the ICDRR register st arts receive operation. The receive clock is output in synchronization with the internal clock and data is received. The master device outputs the level set by the ACKBT bit in the ICIER register to the SDA pin at the rising edge of the 9th clock cycle of the receive clock. (3) When 1-frame of data reception is completed, the RDRF bit in the ICSR register is set to 1 at the rising edge of the 9th clock cycle of the receive clock. At this time, if the ICDRR register is read, the received data can be read and the RDRF bit is set to 0 simultaneously. (4) Continuous receive operati on is enabled by reading the ICDRR register every time the RDRF bit is set to 1. If reading the ICDRR register is delayed by another process and the 8th clock cycle falls while the RDRF bit is set to 1, the SCL signal is fixed “L” until the ICDRR register is read. (5) If the next frame is the last recei ve frame and the RCVD bit in the ICCR1 register is set to 1 (next receive operation disabled) before reading the ICDRR register , stop condition generation is enabled after the next receive operation. (6) When the RDRF bit is set to 1 at the rising edge of the 9th clock cycle of the receive clock, generate a stop condition. (7) When the STOP bit in the ICSR register is set to 1, read the ICDRR register and set the RCVD bit to 0 (next receive operation continues). (8) Return to slave receive mode.

R8C/32A Group 25. I2C bus Interface REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 400 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 25.6 Operating Timing in Master Receive Mode (I 2C bus Interface Mode) (1) SDA (master output) SCL (master output) 1896 7 453 b7 b6 b5 b4 b3 b2 b1 b0 b7 SDA (slave output) TDRE bit in ICSR register TEND bit in ICSR register ICDRR register ICDRS register Data 1 Program processing (1) After setting bits TEND and TRS to 0, set TDRE bit to 0. A (2) Read ICDRR register. Data 1 TRS bit in ICCR1 register RDRF bit in ICSR register A (3) Read ICDRR register. Master transmit mode Master receive mode

R8C/32A Group 25. I2C bus Interface REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 401 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 25.7 Operating Timing in Master Receive Mode (I 2C bus Interface Mode) (2) SDA (master output) SCL (master output) 12 8967453 b7 b6 b5 b4 b3 b2 b1 b0SDA (slave output) RCVD bit in ICCR1 register ICDRR register ICDRS register Data n-1 Program processing (6) Generate a stop condition. A/A (8) Set to slave receive mode. A Data n RDRF bit in ICSR register Data n Data n-1 (5) Read ICDRR register after setting RCVD bit to 1. (7) Set RCVD bit to 0 after reading ICDRR register.

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25.4.4 Slave Transmit Operation

In slave transmit mode, the slave device outputs the tran smit data while the master device outputs the receive clock and returns an acknowledge signal. Figures 25.8 and 25.9 show the Operating Timing in Slave Transmit Mode (I2C bus Interface Mode). The transmit procedure and operation in slave transmit mode are as follows. (1) Set the ICE bit in the ICCR1 register to 1 (transfe r operation enabled), and set bits WAIT and MLS in the ICMR register and bits CKS0 to CK S3 in the ICCR1 register (initial se tting). Then, set bits TRS and MST in the ICCR1 register to 0 and wait until the slave address matches in slave receive mode. (2) When the slave address matches at the first frame after detecting the start condition, the slave device outputs the level set by the ACKBT bit in the ICIER register to the SDA pin at the rising edge of the 9th clock cycle. At this time, if the 8th bit of data (R/W ) is 1, bits TRS and TDRE in the ICSR register are set to 1, and the mode is switched to slave transmit mode automatically. Continuous transmission is enabled by writing transmit data to the ICDRT register every time the TDRE bit is set to 1. (3) When the TDRE bit in the ICDRT register is set to 1 after the last transmit data is written to the ICDRT register, wait until the TEND bit in the ICSR register is set to 1 while the TDRE bit is set to 1. When the TEND bit is set to 1, set the TEND bit to 0. (4) Set the TRS bit to 0 and dummy read the ICDRR regi ster to end the process. This will release the SCL signal. (5) Set the TDRE bit to 0.

R8C/32A Group 25. I2C bus Interface REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 403 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 25.8 Operating Timing in Slave Transmit Mode (I 2C bus Interface Mode) (1) SDA (master output) SCL (master output) 1896 7 453 b7 b6 b5 b4 b3 b2 b1 b0 b7 SDA (slave output) TDRE bit in ICSR register TEND bit in ICSR register ICDRR register ICDRS register Data 1 Program Processing A Data 2 TRS bit in ICCR1 register A Slave transmit modeSlave receive mode SCL (slave output) ICDRT register Data 1 (1) Write data to ICDRT register (data 1). (2) Write data to ICDRT register (data 2). Data 2 (2) Write Data to ICDRT register (data 3). Data 3

R8C/32A Group 25. I2C bus Interface REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 404 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 25.9 Operating Timing in Slave Transmit Mode (I 2C bus Interface Mode) (2) SDA (slave output) SCL (master output) 12 8967453 b7 b6 b5 b4 b3 b2 b1 b0 SDA (master output) TDRE bit in ICSR register TEND bit in ICSR register ICDRT register ICDRS register Data n Program processing (3) Set TEND bit to 0. A A Data n Slave receive mode Slave transmit mode TRS bit in ICCR1 register ICDRR register (4) Dummy read ICDRR register after setting TRS bit to 0. (5) Set TDRE bit to 0. SCL (slave output)

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25.4.5 Slave Receive Operation

In slave receive mode, the master de vice outputs the transmit clock and data, and the slave device returns an acknowledge signal. Figures 25.10 and 25.11 show the Operating Timing in Slave Receive Mode (I2C bus Interface Mode). The receive procedure and operation in slave receive mode are as follows. (1) Set the ICE bit in the ICCR1 register to 1 (transfe r operation enabled), and set bits WAIT and MLS in the ICMR register and bits CKS0 to CK S3 in the ICCR1 register (initial se tting). Then, set bits TRS and MST in the ICCR1 register to 0 and wait until the slave address matches in slave receive mode. (2) When the slave address matches at the first frame after detecting the start condition, the slave device outputs the level set in the ACKBT bit in the ICIER register to the SDA pin at the rising edge of the 9th clock cycle. Since the RDRF bit in the ICSR register is set to 1 simultaneously, dummy read the ICDRR register (the read data is unnecessary because it indicates the slave address and R/W (3) Read the ICDRR register every time the RDRF bit is set to 1. If the 8th clock cycle falls while the RDRF bit is set to 1, the SCL signal is fixed “L” until the ICDRR register is read. The setting change of the acknowledge signal returned to the master device before reading th e ICDRR register takes affect from the following transfer frame. (4) Reading the last byte is also performed by reading the ICDRR register.

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25.5 Clock Synchronous Serial Mode

25.5.1 Clock Synchronous Serial Format

When the FS bit in the SAR register is set to 1, the clock synchronous serial format is used for communication. Figure 25.12 shows the Transfer Format of Clock Synchronous Serial Format. When the MST bit in the ICCR 1 register is set to 1, the transfer clock is output from the SCL pin. When the MST bit is set to 0, the external clock is input. The transfer data is output between su ccessive falling edges of the SCL clock, and data is determined at the rising edge of the SCL clock. MSB-first or LSB-first can be selected as the order of the data transfer by setting the MLS bit in the ICMR register. The SDA output level can be changed by the SDAO bit in the ICCR2 register during transfer standby. Figure 25.12 Transfer Format of Clock Synchronous Serial Format SCL b0SDA b1 b2 b3 b4 b5 b6 b7

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25.5.2 Transmit Operation

In transmit mode, transmit data is output from the SDA pin in synchronization with the falling edge of the transfer clock. The transfer clock is output when the MST bit in the ICCR1 register is set to 1 and input when the MST bit is set to 0. Figure 25.13 shows the Operating Timing in Transmit Mode (Clock Synchronous Serial Mode). The transmit procedure and operation in transmit mode are as follows. (1) Set the ICE bit in the I CCR1 register to 1 (transfer operation enable d). Then set bits CKS0 to CKS3 in the ICCR1 register and the MST bit (initial setting). (2) Set the TRS bit in the ICCR1 register to 1 to select transmit mode. This will set the TDRE bit in the ICSR register is to 1. (3) After confirming that the TDRE bit is set to 1, write transmit data to the ICDRT register. Data is transferred from registers ICDRT to ICDRS and the TDRE bit is automatically set to 1. Continuous transmission is enabled by writing data to the ICDRT register every time the TDRE bit is set to 1. To switch from transmit to receive mode, set the TRS bit to 0 while the TDRE bit is set to 1. Figure 25.13 Operating Timing in Transmit Mode (Clock Synchronous Serial Mode) SDA (output) SCL 87 b7b1b0 ICDRT register ICDRS register Program processing 17 81 b6 b7 b0 b6 b0 TDRE bit in ICSR register TRS bit in ICCR1 register Data 1 Data 2 Data 3 Data 1 Data 2 Data 3 (2) Set TRS bit to 1. (3) Write data to ICDRT register. (3) Write data to ICDRT register. (3) Write data to ICDRT register. (3) Write data to ICDRT register.

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25.5.3 Receive Operation

In receive mode, data is latched at the rising edge of the transfer clock. The transf er clock is output when the MST bit in the ICCR1 register is set to 1 and input when the MST bit is set to 0. Figure 25.14 shows the Operating Timing in Receive Mode (Clock Synchronous Serial Mode). The receive procedure and operation in receive mode are as follows. (1) Set the ICE bit in the I CCR1 register to 1 (transfer operation enable d). Then set bits CKS0 to CKS3 in the ICCR1 register and the MST bit (initial setting). (2) Set the MST bit to 1 while the transfer clock is bei ng output. This will start the output of the receive clock. (3) When the receive operation is completed, data is transferred from registers ICDRS to ICDRR and the RDRF bit in the ICSR register is set to 1. When the MST bit is set to 1, the clock is output continuously since the next byte of data is enabled for reception. Continuous reception is enabled by reading the ICDRR register every time the RDRF bit is set to 1. If the 8t h clock cycle falls while the RDRF bit is set to 1, an overrun is detected and the AL bit in the ICSR register is set to 1. At this time, the last receive data is retained in the ICDRR register. (4) When the MST bit is set to 1, set the RCVD bit in th e ICCR1 register to 1 (next receive operation disabled) and read the ICDRR register. The SCL signal is fi xed “H” after the following byte of data reception is completed. Figure 25.14 Operating Timing in Receive Mode (Clock Synchronous Serial Mode) SDA (input) SCL 87 b7b1b0 ICDRR register ICDRS register Program processing 17 81 b6 b7 b0 b6 b0 RDRF bit in ICSR register MST bit in ICCR1 register Data 1 Data 2 (2) Set MST bit to 1 (when transfer clock is output). (3) Read ICDRR register. TRS bit in ICCR1 register Data 2 Data 3Data 1 (3) Read ICDRR register.

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25.6 Examples of Re gister Setting

Figures 25.15 to 25.18 show Examples of Register Setting When Using I2C bus interface. Figure 25.15 Register Setting Example in Master Transmit Mode (I 2C bus Interface Mode) Start Initial setting Read BBSY bit in I CCR2 register End BBSY = 0? Write transmit data to ICDRT register Transmit mode? Master receive mode TEND = 1? No Yes Yes No (1) Determine the state of the SCL and SDA lines. (2) Set to master transmit mode. (3) Generate a start condition. (4) Set the transmit data of the 1st byte (slave address + R/W). (5) Wait until 1 byte of data is transmitted. (6) Determine the ACKBR bit from the specified slave device. (7) Set the transmit data after 2nd byte (except the last byte). (8) Wait until the ICRDT register is empty. (9) Set the transmit data of the last byte. (10) Wait for end of transmission of the last byte. (11) Set the TEND bit to 0. (12) Set the STOP bit to 0. (13) Generate a stop condition. (14) Wait until a stop condition is generated. (15) Set to slave receive mode. Set the TDRE bit to 0. ICCR1 register TRS bit ← 1 MST bit ← 1 ICCR2 register SCP bit ← 0 BBSY bit ← 1 Read TEND bit in ICSR register No Read ACKBR bit in ICIER register Yes ACKBR = 0? Write transmit data to ICDRT register TDRE = 1? Read TDRE bit in ICSR register Last byte? Write transmit data to ICDRT register TEND = 1? Read TEND bit in ICSR register ICSR register TEND bit ← 0 ICSR register STOP bit ← 0 ICCR2 register SCP bit ← 0 BBSY bit ← 0 Read STOP bit in ICSR register STOP = 1? ICCR1 register TRS bit ← 0 MST bit ← 0 ICSR register TDRE bit ← 0 No Yes No Yes No Yes No Yes No Yes (1) (2) (3) (4) (5) (6) (7) (8) (12) (10) (13) (14) (11) (9) (15)

• Set the STOP bit in the ICSR register to 0.
• Set the IICSEL bit in the PMR register to 1.
• Set the MSTIIC bit in the MSTCR register to 0.

R8C/32A Group 25. I2C bus Interface REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 411 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 25.16 Register Setting Example in Master Receive Mode (I 2C bus Interface Mode) End RDRF = 1? Master receive mode No Yes (1) Set the TEND bit to 0 and set to master receive mode. Set the TDRE bit to 0. (1,2) (2) Set the ACKBT bit to the transmit device. (1) (3) Dummy read the ICDRR register. (1) (4) Wait until 1 byte is received. (5) Determine (last receive - 1). (6) Read the receive data. (7) Set the ACKBT bit of the last byte and set continuous receive operation to disable (RCVD = 1). (2) (8) Read the receive data of (last byte - 1). (9) Wait until the last byte is received. (10) Set the STOP bit to 0. (11) Generate a stop condition. (12) Wait until a stop condition is generated. (13) Read the receive data of the last byte. (14) Set the RCVD bit to 0. (15) Set to slave receive mode. ICCR1 register TRS bit ← 0 Dummy read in ICDRR register Read RDRF bit in ICSR register Last receive - 1? ICSR register TEND bit ← 0 ICSR register STOP bit ← 0 ICCR2 register SCP bit ← 0 BBSY bit ← 0 Read STOP bit in ICSR register STOP = 1? ICSR register TDRE bit ← 0 No (1) (2) (3) (4) (5) (6) (7) (8) (12) (10) (13) (14) (11) (9) (15) ICIER register ACKBT bit ← 0 No Yes Read ICDRR register ICIER register ACKBT bit ← 1 ICCR1 register RCVD bit ← 1 Read ICDRR register Read RDRF bit in ICSR register RDRF = 1? Read ICDRR register ICCR1 register RCVD bit ← 0 ICCR1 register MST bit ← 0 No Yes Yes Notes: 1. Do not generate interrupts while processing steps (1) to (3). 2. For 1 byte of data reception, skip steps (2) to (6) after step (1) and jump to process step (7). Process step (8) is a dummy read from the ICDRR register.

R8C/32A Group 25. I2C bus Interface REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 412 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 25.17 Register Setting Example in Slave Transmit Mode (I 2C bus Interface Mode) End Write transmit data to ICDRT register Slave transmit mode No Yes (1) Set the AAS bit to 0. (2) Set the transmit data (except the last byte). (3) Wait until the ICRDT register is empty. (4) Set the transmit data of the last byte. (5) Wait until the last byte is transmitted. (6) Set the TEND bit to 0. (7) Set to slave receive mode. (8) Dummy read the ICDRR register to release the SCL signal. (9) Set the TDRE bit to 0. TDRE = 1? Read TDRE bit in ICSR register Last byte? Write transmit data to ICDRT register TEND = 1? Read TEND bit in ICSR register ICSR register TEND bit ← 0 ICSR register AAS bit ← 0 ICCR1 register TRS bit ← 0 ICSR register TDRE bit ← 0 No Yes No Yes (1) (2) (3) (4) (5) (6) (7) (8) (9) Dummy read ICDRR register

R8C/32A Group 25. I2C bus Interface REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 413 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 25.18 Register Setting Example in Slave Receive Mode (I 2C bus Interface Mode) End RDRF = 1? Slave receive mode No Yes (1) Set the AAS bit to 0. (1) (2) Set the ACKBT bit to the transmit device. (3) Dummy read the ICDRR register. (4) Wait until 1 byte is received. (5) Determine (last receive - 1). (6) Read the receive data. (7) Set the ACKBT bit of the last byte. (1) (8) Read the receive data of (last byte - 1). (9) Wait until the last byte is received. (10) Read the receive data of the last byte. Dummy read ICDRR register Read RDRF bit in ICSR register Last receive - 1? (1) (2) (3) (4) (5) (6) (7) (8) (10) (9) ICIER register ACKBT bit ← 0 No Yes Read ICDRR register ICIER register ACKBT bit ← 1 Read ICDRR register Read RDRF bit in ICSR register RDRF = 1? Read ICDRR register No Yes Note: 1. For 1 byte of data reception, skip steps (2) to (6) after (1) and jump to process step (7). Process step (8) is a dummy read from the ICDRR register. ICSR register AAS bit ← 0

R8C/32A Group 25. I2C bus Interface REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 414 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

25.7 Noise Canceller

The states of pins SCL and SDA are routed through the noise canceller before being latched internally. Figure 25.19 shows a Noise Canceller Block Diagram. The noise canceller consists of two cascaded latch and matc h detector circuits. When the SCL pin input signal (or SDA pin input signal) is sampled on f1 and two latch outputs match, the level is passed forward to the next circuit. When they do not match, the former value is retained. Figure 25.19 Noise Canceller Block Diagram C DQ Latch C DQ Latch Match detection circuit SCL or SDA input signal Internal SCL or SDA signal f1 (sampling clock) f1 period f1 (sampling clock)

R8C/32A Group 25. I2C bus Interface REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 415 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

25.8 Bit Synchronization Circuit

When the I2C bus interface is set to master mode, the high-level period may become shorter if:

• The SCL signal is driven L level by a slave device
• The rise speed of the SCL signal is reduced by a load (load capacity or pull-up resistor) on the SCL line. Therefore, the SCL signal is monitored and communication is synchronized bit by bit. Figure 25.20 shows the Bit Synchronization Circuit Timing and Table 25.5 lists the Time between Changing SCL Signal from “L” Output to High-Impedance and Monitoring SCL Signal. Figure 25.20 Bit Synchronization Circuit Timing 1Tcyc = 1/f1(s) Table 25.5 Time between Changing SCL Signal from “L” Output to High-Impedance and Monitoring SCL Signal ICCR1 Register SCL Monitoring TimeCKS3 CKS2 0 0 7.5Tcyc 1 19.5Tcyc 10 1 7 . 5 T c y c 1 41.5Tcyc VIH Reference clock of SCL monitor timing SCL Internal SCL

R8C/32A Group 25. I2C bus Interface REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 416 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

25.9 Notes on I 2C bus Interface

To use the I 2C bus interface, set the IICSEL bit in the SSUIICSR register to 1 (I 2C bus interface function selected).

R8C/32A Group 26. Hardware LIN REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 417 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 26. Hardware LIN The hardware LIN performs LIN communication in cooperation with timer RA and UART0.

26.1 Overview

The hardware LIN has the features listed below. Figure 26.1 shows a Hardware LIN Block Diagram. Master mode

• Synch Break generation
• Bus collision detection Slave mode
• Synch Break detection
• Synch Field measurement
• Control function for Synch Break and Synch Field signal inputs to UART0
• Bus collision detection Note: 1.The Wake up function is detected using INT1. Figure 26.1 Hardware LIN Block Diagram Timer RA UART0 Interrupt control circuitBus collision detection circuit Synch Field control circuit RXD0 input control circuit RXD0 pin TXD0 pin LSTART bit SBE bit LINE bit Timer RA interrupt TIOSEL = 0 Hardware LIN TIOSEL = 1 RXD data Timer RA underflow signal Bits BCIE, SBIE, and SFIE UART0 transfer clock UART0 TE bit Timer RA output pulse UART0 TXD data MST bit LINE, MST, SBE, LSTART, BCIE, SBIE, SFIE: Bits in LINCR register TIOSEL: Bit in TRAIOC register TE: Bit in U0C1 register

R8C/32A Group 26. Hardware LIN REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 418 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

26.2 Input/Output Pins

The pin configuration for the hardware LIN is listed in Table 26.1. Note: 1. To use the hardware LIN, set the TXD0SEL0 bit in the U0SR register to 1 and the RXD0SEL0 bit to Table 26.1 Hardware LIN Pin Configuration Name Pin Name Assigned Pin Input/Output Function Receive data input RXD0 P1_5 (1) Input Receive data input pin for the hardware LIN Transmit data output TXD0 P1_4 (1) Output Transmit data output pin for the hardware LIN

R8C/32A Group 26. Hardware LIN REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 419 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

26.3 Registers

The hardware LIN contains the following registers:

• LIN Control Register 2 (LINCR2)
• LIN Control Register (LINCR)
• LIN Status Register (LINST)

26.3.1 LIN Control Register 2 (LINCR2)

B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 BCE Bus collision detection during Sync Break transmission enable bit 0: Bus collision detection disabled 1: Bus collision detection enabled R/W b1 — Reserved bits Set to 0. R/W b2 — b3 — b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b5 — b6 — b7 —

R8C/32A Group 26. Hardware LIN REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 420 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

26.3.2 LIN Control Register (LINCR)

Notes: 1. After setting the LSTART bit, confirm that the RXDSF flag is set to 1 before Synch Break input starts. 2. Before switching LIN operation modes, stop the LIN operation (LINE bit = 0) once. 3. Inputs to timer RA and UART0 are disabled immediately after the LINE bit is set to 1 (LIN operation starts). (Refer to Figure 26.3 Header Field Transmission Flowchart Example (1) and Figure 26.7 Header Field Reception Flowchart Example (2).)

26.3.3 LIN Status Register (LINST)

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol LINE MST SBE LSTART RXDSF BCIE SBIE SFIE A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 SFIE Synch Field measurement-completed interrupt enable bit 0: Synch Field measurement-completed interrupt disabled 1: Synch Field measurement-completed interrupt enabled R/W b1 SBIE Synch Break detection interrupt enable bit 0: Synch Break detection interrupt disabled 1: Synch Break detection interrupt enabled R/W b2 BCIE Bus collision det ection interrupt enable bit 0: Bus collision detection interrupt disabled 1: Bus collision detection interrupt enabled R/W b3 RXDSF RXD0 input status flag 0: RXD0 input enabled 1: RXD0 input disabled R b4 LSTART Synch Break detection start bit (1) When this bit is set to 1, timer RA input is enabled and RXD0 input is disabled. When read, the content is 0. R/W b5 SBE RXD0 input unmasking timing select bit (effective only in slave mode) 0: Unmasked after Synch Break detected 1: Unmasked after Synch Field measurement completed R/W b6 MST LIN operation mode setting bit (2) 0: Slave mode (Synch Break detection circuit operation) 1: Master mode (timer RA output OR’ed with TXD0) R/W b7 LINE LIN operation start bit 0: LIN operation stops 1: LIN operation starts (3) R/W Address 0107h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — B2CLR B1CLR B0CLR BCDCT SBDCT SFDCT A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 SFDCT Synch Field measurement-completed flag When this bit is set to 1, Synch Field measurement is completed. R b1 SBDCT Synch Break detection flag when this bit is set to 1, Synch Break is detected or Synch Break generation is completed. R b2 BCDCT Bus collision detection flag When this bi t is set to 1, bus collision is detected. R b3 B0CLR SFDCT bit clear bit When this bit is set to 1, the SFDCT bit is set to 0. When read, the content is 0. R/W b4 B1CLR SBDCT bit clear bit When this bit is set to 1, the SBDCT bit is set to 0. When read, the content is 0. R/W b5 B2CLR BCDCT bit clear bit When this bit is set to 1, the BCDCT bit is set to 0. When read, the content is 0. R/W b6 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b7 —

R8C/32A Group 26. Hardware LIN REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 421 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

26.4 Function Description

26.4.1 Master Mode

Figure 26.2 shows an Operating Example during Header Field Transmission in master mode. Figures 26.3 and 26.4 show Examples of Header Field Transmission Flowchart. During header field transmission, the hardware LIN operates as follows: (1) When 1 is written to the TSTART bit in the TRACR register for timer RA, a “L” level is output from the TXD0 pin for the period set in registers TRAPRE and TRA for timer RA. (2) When timer RA underflows, the TXD0 pin output is inverted and the SBDCT flag in the LINST register is set to 1. If the SBIE bit in the LINCR register is set to 1, a timer RA interrupt is generated. (3) The hardware LIN transmits “55h” via UART0. (4) After the hardware LIN completes transmitting “55h”, it transmits an ID field via UART0. (5) After the hardware LIN completes transmitting th e ID field, it performs communication for a response field. Figure 26.2 Operating Example during Header Field Transmission TXD0 pin Synch Break SBDCT flag in LINST register IR bit in TRAIC register Synch Field IDENTIFIER The above applies when: LINE = 1, MST = 1, SBIE = 1 Set to 0 when an interrupt request is acknowledged or by a program. 1 is written to B1CLR bit in LINST register.

R8C/32A Group 26. Hardware LIN REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 422 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 26.3 Header Field Transm ission Flowchart Example (1) Timer RA Set to timer mode Bits TMOD2 to TMOD0 in TRAMR register ← 000b Timer RA Set the pulse output level from low to start TEDGSEL bit in TRAIOC register ← 1 Timer RA TRAIO pin assigned to P1_5 Bits TRAIOSEL1 to TRAIOSEL0 in TRASR register ← 10b UART0 RXD0 pin assigned to P1_5 RXD0SEL0 bit in U0SR register ← 1 INT1 INT1 pin assigned to P1_5 Bits INT1SEL2 to INT1SEL0 in INTSR register ← 001b Timer RA Set the count source (f1, f2, f8, fOCO) Bits TCK0 to TCK2 in TRAMR register Timer RA Set the Synch Break width TRAPRE register TRA register Hardware LIN Set to master mode. MST bit in LINCR register ← 1 Hardware LIN Set the LIN operation to start LINE bit in LINCR register ← 1 Hardware LIN Set interrupts to enable (Bus collision detection, Synch Break detection, Synch Field measurement) Bits BCIE, SBIE, SFIE in LINCR register Hardware LIN Clear the status flags (Bus collision detection, Synch Break detection, Synch Field measurement) Bits B2CLR, B1CLR, B0CLR in LINST register ← 1 Set the count source and registers TRA and TRAPRE as appropriate for the Synch Break period. In master mode, the Synch Field measurement-completed interrupt cannot be used.A Set the TIOSEL bit in the TRAIOC register to 1 to select the hardware LIN function. If the wake-up function is not necessary, the setting of the INT1 pin can be omitted. UART0 Set to transmit/receive mode (Transfer data 8 bits long, internal clock, 1 stop bit, parity disabled) U0MR register UART0 Set the BRG count source (f1, f8, f32) Bits CLK0 and CLK1 in U0C0 register UART0 Set the bit rate U0BRG register Hardware LIN Set the LIN operation to stop LINE bit in LINCR register ← 0 Set the BRG count source and the U0BRG register as appropriate for the bit rate. Hardware LIN Set bus collision detection to enable BCE bit in LINCR2 register ← 1 Note: 1. When the previous communication completes normally and header field transmission is performed again with the same settings, the above settings can be omitted. (1) (1) (1) (1) (1) (1) (1) (1) (1) (1)

R8C/32A Group 26. Hardware LIN REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 423 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 26.4 Header Field Transm ission Flowchart Example (2) Timer RA Set the timer to start counting TSTART bit in TRACR register ← 1 Timer RA Read the count status flag TCSTF flag in TRACR register Hardware LIN Read the Synch Break detection flag SBDCT flag in LINST register Timer RA Set the timer to stop counting TSTART bit in TRACR register ← 0 Timer RA Read the count status flag TCSTF flag in TRACR register UART0 Communication via UART0 TE bit in U0C1 register ← 1 U0TB register ← 0055h A timer RA interrupt can be used to end Synch Break generation. One or two cycles of the CPU clock are required after Synch Break generation ends before the SBDCT flag is set to 1. The ID field is transmitted. A TCSTF = 1? SBDCT = 1? YES TCSTF = 0? YES UART0 Communication via UART0 U0TB register ← ID field NO YES NO NO After writing 0 to the TSTART bit, if registers TRAPRE and TRA for timer RA are not read or the register settings are not changed, reading 0 from the TCSTF flag can be omitted. Zero or one cycle of the timer RA count source is required after timer RA stops counting before the TCSTF flag is set to 0. The Synch Field is transmitted. After a Synch Break for timer RA is generated, stop the timer count. After writing 1 to the TSTART bit, if registers TRAPRE and TRA for timer RA are not read or the register settings are not changed, reading 1 from the TCSTF flag can be omitted. Zero or one cycle of the timer RA count source is required after timer RA starts counting before the TCSTF flag is set to 1. A Synch Break for timer RA is generated.

R8C/32A Group 26. Hardware LIN REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 424 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

26.4.2 Slave Mode

Figure 26.5 shows an Operating Exam ple during Header Field Reception in slave mode. Figure 26.6 through Figure 26.8 show examples of Header Field Reception Flowchart. During header field reception, the hardware LIN operates as follows: (1) When 1 is written to the LSTART bit in the LINCR register for the hardware LIN, Synch Break detection is enabled. (2) If a “L” level is input for a duration equal to or lo nger than the period set in timer RA, the hardware LIN detected it as a Synch Break. At this time, the SBDCT flag in the LINST register is set to 1. If the SBIE bit in the LINCR register is set to 1, a timer RA interrupt is generated. Then the hardware LIN enters the Synch Field measurement. (3) The hardware LINA receives a Sync h Field (55h) and measures the period of the start bit and bits 0 to 6 is using timer RA. At this time, whether to input the Synch Field signal to RXD0 of UART0 can be selected by the SBE bit in the LINCR register. (4) When the Synch Field measurement is completed, the SF DCT flag in the LINST register is set to 1. If the SFIE bit in the LINCR register is set to 1, a timer RA interrupt is generated. (5) After the Synch Field measurement is completed, a transfer rate is calculated from the timer RA count value. The rate is set in UART0 and registers TR APRE and TRA for timer RA are set again. Then the hardware LIN receives an ID field via UART0. (6) After the hardware LIN completes receiving the ID field, it performs communication for a response field. Figure 26.5 Operating Example during Header Field Reception RXD0 pin Synch Break RXD0 input for UART0 RXDSF flag in LINCR register Synch Field IDENTIFIER (2) (3) (5) (6) The above applies when: LINE = 1, MST = 0, SBE = 1, SBIE = 1, SFIE = 1 (4)(1) SBDCT flag in LINST register SFDCT flag in LINST register IR bit in TRAIC register 1 is written to B0CLR bit in LINST register. This period is measured. 1 is written to B1CLR bit in LINST register. Set to 0 when an interrupt request is acknowledged or by a program. 1 is written to LSTART bit in LINCR register. The flag is set to 0 after Synch Field measurement is completed.

R8C/32A Group 26. Hardware LIN REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 425 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 26.6 Header Field Recep tion Flowchart Example (1) Set the count source and registers TRA and TRAPRE as appropriate for the Synch Break period. Select the timing at which to unmask the RXD0 input for UART0. If the RXD0 input is chosen to be unmasked after Synch Break detection, the Synch Field signal is also input to UART0. A Set the TIOSEL bit in the TRAIOC register to 1 to select the hardware LIN function. If the wake-up function is not necessary, the setting of the INT1 pin can be omitted. Timer RA Set to pulse width measurement mode Bits TMOD2 to TMOD0 in TRAMR register ← 011b Timer RA Set the pulse width measurement level to low TEDGSEL bit in TRAIOC register ← 0 Timer RA TRAIO pin assigned to P1_5 Bits TRAIOSEL1 to TRAIOSEL0 in TRASR register ← 10b UART0 RXD0 pin assigned to P1_5 RXD0SEL0 bit in U0SR register ← 1 INT1 INT1 pin assigned to P1_5 Bits INT1SEL2 to INT1SEL0 in INTSR register ← 001b Timer RA Set the count source (f1, f2, f8, fOCO) Bits TCK0 to TCK2 in TRAMR register Timer RA Set the Synch Break width TRAPRE register TRA register Hardware LIN Set the LIN operation to stop LINE bit in LINCR register ← 0 Hardware LIN Set to slave mode MST bit in LINCR register ← 0 Hardware LIN Set the RXD0 input unmasking timing (After Synch Break detection, or after Synch Field measurement) SBE bit in LINCR register Hardware LIN Set interrupts to enable (Bus collision detection, Synch Break detection, Synch Field measurement) Bits BCIE, SBIE, SFIE in LINCR register Hardware LIN Set the LIN operation to start LINE bit in LINCR register ← 1 Note: 1. When the previous communication completes normally and header field reception is performed again with the same settings, the above settings can be omitted. (1) (1) (1) (1) (1) (1) (1) (1) (1)

R8C/32A Group 26. Hardware LIN REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 426 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 26.7 Header Field Recep tion Flowchart Example (2) Timer RA Set pulse width measurement to start TSTART bit in TRACR register ← 1 Timer RA Read the count status flag TCSTF flag in TRACR register Hardware LIN Set Synch Break detection to start LSTART bit in LINCR register ← 1 Hardware LIN Read the RXD0 input status flag RXDSF flag in LINCR register A TCSTF = 1? YES RXDSF = 1? YES NO NO Wait until timer RA starts counting. Hardware LIN Clear the status flags (Bus collision detection, Synch Break detection, Synch Field measurement) Bits B2CLR, B1CLR, B0CLR in LINST register ← 1 Hardware LIN Read the Synch Break detection flag SBDCT flag in LINST register SBDCT = 1? YES NO B After writing 1 to the LSTART bit, do not apply a “L” level to the RXD pin until 1 is read from the RXDSF flag. Otherwise, the signal applied during this time will be input directly to UART0. One or two cycles of the CPU clock and zero or one cycle of the timer RA count source are required after the LSTART bit is set to 1 before the RXDSF flag is set to 1. After this, input to timer RA and UART0 is enabled. A Synch Break for the hardware LIN is detected. A timer RA interrupt can be used. Wait until the RXD0 input to UART0 for the hardware LIN is masked. When a Synch Break is detected, timer RA is reloaded with the initially set count value. Even if the duration of the input “L” level is shorter than the set period, timer RA is reloaded with the initially set count value. Wait until the next “L” level is input. One or two cycles of the CPU clock are required after Synch Break detection before the SBDCT flag is set to 1. If the SBE bit in the LINCR register is set to 0 (unmasked after Synch Break detected), timer RA can be used in timer mode after the SBDCT flag in the LINST register is set to 1 and the RXDSF flag is set to 0. Zero or one cycle of the timer RA count source is required after timer RA starts counting before the TCSTF flag is set to 1.

R8C/32A Group 26. Hardware LIN REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 427 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 26.8 Header Field Recep tion Flowchart Example (3) Hardware LIN Read the Synch Field measurement- completed flag SFDCT flag in LINST register UART0 Set the UART0 communication rate U0BRG register Communication is performed via UART0. (The SBDCT flag is set when the timer RA counter underflows.) B SFDCT = 1? YES UART0 Communication via UART0 Clock asynchronous serial interface (UART) mode ID field reception NO A Synch Field for the hardware LIN is measured. A timer RA interrupt can be used. (The SBDCT flag is set when the timer RA counter underflows.) If the SBE bit in the LINCR register is set to 1 (unmasked after Synch Field measurement completed), timer RA can be used in timer mode after the SFDCT flag in the LINST register is set to 1 and the RXDSF flag is set to 0. Set a communication rate based on the Synch Field measurement result. YES Timer RA Set the Synch Break width again TRAPRE register TRA register

R8C/32A Group 26. Hardware LIN REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 428 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

26.4.3 Bus Collision Detection Function

The bus collision detection function can be used if UART0 is enabled for transmission (TE bit in U0C1 register = 1). To detect a bus collision during Synch Break transmission, set the BCE bit in the LINCR2 register to 1 (bus collision detection enabled). Figure 26.9 shows an Operating Example When Bus Collision is Detected. Figure 26.9 Operating Example When Bus Collision is Detected TXD0 pin 1 RXD0 pin 1 Transfer clock 1 LINE bit in LINCR register TE bit in U0C1 register BCDCT flag in LINST register IR bit in TRAIC register Set to 0 when an interrupt request is acknowledged or by a program. 1 is written to B2CLR bit in LINST register. Set to 1 by a program. Set to 1 by a program.

R8C/32A Group 26. Hardware LIN REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 429 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

26.4.4 Hardware LI N End Processing

Figure 26.10 shows an Example of Hardware LIN Communication Completion Flowchart. Use the following timing for hardware LIN end processing:

• If the hardware bus collision detection function is used Perform hardware LIN end processing after checksum transmission completes.
• If the bus collision detection function is not used Perform hardware LIN end processing after header field transmission and reception complete. Figure 26.10 Example of Hardware LIN Communication Completion Flowchart Hardware LIN Clear the status flags (Bus collision detection, Synch Break detection, Synch Field measurement) Bits B2CLR, B1CLR, B0CLR in LINST register ← 1 Timer RA Read the count status flag TCSTF flag in TRACR register UART0 Transmission completes via UART0 If the bus collision detection function is not used, UART0 transmission completion processing is not required. TCSTF = 0? YES NO Set the timer to stop counting. Zero or one cycle of the timer RA count source is required after timer RA stops counting before the TCSTF flag is set to 1. After clearing the hardware LIN status flag, stop the hardware LIN operation. Timer RA Set the timer to stop counting TSTART bit in TRACR register ← 0 Hardware LIN Set the LIN operation to stop LINE bit in LINCR register ← 0

R8C/32A Group 26. Hardware LIN REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 430 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

26.5 Interrupt Requests

There are four interrupt requests generated by the hard ware LIN: Synch Break det ection, Completion of Synch Break generation, Completion of Synch Field measuremen t, and bus collision detection. These interrupts are shared with timer RA. Table 26.2 lists the Hardware LIN Interrupt Requests. Table 26.2 Hardware LIN Interrupt Requests Interrupt Request Status Flag Interrupt Source Synch Break detection SBDCT Generated when timer RA underflows after the “L” level duration for the RXD0 input is measured, or when a “L” level is input for a duration longer than the Synch Break period during communication. Completion of Synch Break generation Generated when a “L” level output to TXD0 for the duration set by timer RA is completed. Completion of Synch Field measurement SFDCT Generated when measurement for 6 bits of the Lynch Field by timer RA is completed. Bus collision detection BCDCT Ge nerated when the RXD0 input and TXD0 output values are different at data latch timing while UART0 is enabled for transmission.

R8C/32A Group 26. Hardware LIN REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 431 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

26.6 Notes on Hardware LIN

For the time-out processing of the head er and response fields, use another timer to measure the duration of time with a Synch Break detection interrupt as the starting point.

R8C/32A Group 27. A/D Converter REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 432 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 27. A/D Converter The A/D converter consists of one 10- bit successive approximation A/D converter circuit with a capacitive coupling amplifier. The analog input shares pins and P1_0 to P1_3.

27.1 Overview

Table 27.1 lists the A/D Converter Performance. Figure 27.1 shows a Block Diagram of A/D Converter. Notes: 1. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in 8-bit mode. 2. When 4.0 V ≤ AVCC ≤ 5.5 V, the frequency of φAD must be 20 MHz or below. When 3.2 V ≤ AVCC < 4.0 V, the frequency of φAD must be 16 MHz or below. When 3.0 V ≤ AVCC < 3.2 V, the frequency of φAD must be 10 MHz or below. When 2.2 V ≤ AVCC < 3.0 V, the frequency of φAD must be 5 MHz or below. The φAD frequency should be 2 MHz or above. 3. The conversion rate per pin is minimum 43 φAD cycles for 8-bit and 10-bit resolution. Table 27.1 A/D Con verter Performance Item Performance A/D conversion method Successive approxim ation (with capacitive coupling amplifier) Analog input voltage (1) 0 V to AVCC Operating clock φAD (2) fAD, fAD divided by 2, fAD divided by 4, fAD divided by 8 (fAD=f1 or fOCO-F) Resolution 8 bits or 10 bits selectable Absolute accuracy AVCC = Vref = 5 V, φAD = 20 MHz

• 8-bit resolution ±2 LSB
• 10-bit resolution ±3 LSB AVCC = Vref = 3.3 V, φAD = 16 MHz
• 8-bit resolution ±2 LSB
• 10-bit resolution ±5 LSB AVCC = Vref = 3.0 V, φAD = 10 MHz
• 8-bit resolution ±2 LSB
• 10-bit resolution ±5 LSB AVCC = Vref = 2.2 V, φAD = 5 MHz
• 8-bit resolution ±2 LSB
• 10-bit resolution ±5 LSB Operating mode One-shot mode, repeat mode 0, repeat mode 1, single sweep mode, and repeat sweep mode Analog input pin 4 pins (AN8 to AN11) A/D conversion start condition • Software trigger
• Timer RC
• External trigger (Refer to 27.3.3 A/D Conversion Start Condition.) Conversion rate per pin (φAD = fAD) (3) Minimum 43 φAD cycles

R8C/32A Group 27. A/D Converter REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 433 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 27.1 Block Diagram of A/D Converter VREF Analog circuitADSTBY = 0 AVSS Successive conversion register CH2 to CH0 Decoder Vref Vin P1_0/AN8 P1_1/AN9 P1_2/AN10 P1_3/AN11 CKS0 to CKS2, ADCAP0 to ADCAP1: Bits in ADMOD register CH0 to CH2, SCAN0 to SCAN1, ADGSEL0 to ADGSEL1: Bits in ADINSEL register ADEX0, ADSTBY, ADDDAEN, ADDDAEL: Bits in ADCON1 register OCVREFAN: Bit in OCVREFCR register Software trigger Do not set. ADCAP1 to ADCAP0 Trigger CKS2 = 0 fOCO-F CKS2 = 1 AD0 register ADGSEL1 to ADGSEL0 ADEX0 = 0 SCAN1 to SCAN0 Data bus Comparator CH2 to CH0 = 100b CH2 to CH0 = 101b CH2 to CH0 = 110b CH2 to CH0 = 111b fAD 1/2 1/2 CKS1 to CKS0 = 00b φAD = 01b = 10b = 11b ADSTBY = 1 AD1 register AD2 register AD3 register AD4 register AD5 register AD6 register = 00b = 01b = 10b = 11b Timer RC trigger ADTRG ADGSEL1 to ADGSEL0 = 01b = 11b ADEX0 = 1OCVREFAN = 0 OCVREFAN = 1On-chip reference voltage (OCVREF) AD7 register Note: 1. When on-chip reference voltage is used as analog input, first set the ADEX0 bit to 1 (on-chip reference voltage selected) and then set the OCVREFAN bit to 1 (on-chip reference voltage and analog input are connected). When on-chip reference voltage is not used as analog input, first set the OCVREFAN bit to 0 (on-chip reference voltage and analog input are cut off) and then set the ADEX0 bit to 0 (extended analog input pin not selected). (Note 1) ADDDAEN=0 ADDDAEN=1 ADDDAEL

R8C/32A Group 27. A/D Converter REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 434 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

27.2 Registers

27.2.1 On-Chip Reference Voltag e Control Register (OCVREFCR)

Note: 1. When on-chip reference voltage is used as analog input, first set the ADEX0 bit in the ADCON1 register to 1 (on- chip reference voltage selected) and then set the OC VREFAN bit to 1 (on-chip reference voltage and analog input are connected). When on-chip reference voltage is not used as analog input, first set the OCVREFAN bit to 0 (on-chip reference voltage and analog input are cut off) and then set the ADEX0 bit to 0 (extended analog input pin not selected). Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting the OCVREFCR register. If the contents of the OCVREFCR register are rewrit ten during A/D conversion, the conversion result is undefined. Address 0026h B i t b 7b 6b 5b 4b 3b 2b 1 b 0 A f t e r R e s e t 0000000 0 Bit Symbol Bit Name Function R/W b0 OCVREFAN On-chip reference voltage to analog input connect bit (1) 0: On-chip reference voltage and analog input are cut off 1: On-chip reference voltage and analog input are connected R/W b1 — Reserved bits Set to 0. R/W b2 — b3 — b4 — b5 — b6 — b7 —

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27.2.2 A/D Register i (ADi) (i = 0 to 7)

If the contents of the ADCON1, ADMOD, ADINSEL, or OCVREFCR register are written during A/D conversion, the conversion result is undefined. When using the A/D converter in 10-bit mode, repeat mode 0, repeat mode 1, or repeat sweep mode, access the ADi register in 16-bit units. Do not access it in 8-bit units. Address 00C1h to 00C0h (AD0), 00C3h to 00C2h (AD1), 00C5h to 00C4h (AD2), 00C7h to 00C6h (AD3), 00C9h to 00C8h (AD4), 00CBh to 00CAh (AD5), 00CDh to 00CCh (AD6), 00CFh to 00CEh (AD7) B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t XXXXXXXX Bit b15 b14 b13 b12 b11 b10 b9 b8 A f t e r R e s e t 000000XX Bit Function R/W10-Bit Mode (BITS Bit in ADCON1 Register = 1) 8-Bit Mode (BITS Bit in ADCON1 Register = 0) b0 8 low-order bits in A/D conversion result A/D conversion result R b8 2 high-order bits in A/D conversion result When read, the content is 0. R b10 Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b11 b12 b13 b14 b15 Reserved bit When read, the content is undefined. R

R8C/32A Group 27. A/D Converter REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 436 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

27.2.3 A/D Mode Register (ADMOD)

Note: 1. When the CKS2 bit is changed, wait for 3 φAD cycles or more before starting A/D conversion. If the ADMOD register is rewritten during A/D conversion, the conversion result is undefined. Address 00D4h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol ADCAP1 ADCAP0 MD2 MD1 MD0 CKS2 CKS1 CKS0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 CKS0 Division select bit b1 b0 0 0: fAD divided by 8 0 1: fAD divided by 4 1 0: fAD divided by 2 1 1: fAD divided by 1 (no division) R/W b1 CKS1 R/W b2 CKS2 Clock source select bit (1) 0: Selects f1 1: Selects fOCO-F R/W b3 MD0 A/D operating mode select bit b5 b4 b3 0 0 0: One-shot mode 0 0 1: Do not set. 0 1 0: Repeat mode 0 0 1 1: Repeat mode 1 1 0 0: Single sweep mode 1 0 1: Do not set. 1 1 0: Repeat sweep mode 1 1 1: Do not set. R/W b4 MD1 R/W b5 MD2 R/W b6 ADCAP0 A/D conversion trigger select bit b7 b6 0 0: A/D conversion starts by software trigger (ADST bit in ADCON0 register) 0 1: Do not set. 1 0: A/D conversion starts by conversion trigger from timer RC 1 1: A/D conversion starts by external trigger (ADTRG) R/W b7 ADCAP1 R/W

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27.2.4 A/D Input Select Register (ADINSEL)

If the ADINSEL register is rewritten during A/D conversion, the conversion result is undefined. Address 00D5h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol ADGSEL1 ADGSEL0 — SCAN0 — CH2 CH1 CH0 A f t e r R e s e t 11000000 Bit Symbol Bit Name Function R/W b0 CH0 Analog input pin select bit Refer to Table 27.2 Analog Input Pin Selection R/W b1 CH1 R/W b2 CH2 R/W b3 — Reserved bit Set to 0. R/W b4 SCAN0 A/D sweep pin count select bit 0: 2 pins 1: 4 pins R/W b5 — Reserved bit Set to 0. R/W ADGSEL0 A/D input group select bit b7 b6 0 0: Do not set. 0 1: Port P1 group selected 1 0: Do not set. 1 1: Port group not selected R/W b7 ADGSEL1 R/W Table 27.2 Analog Input Pin Selection Bits CH2 to CH0 Bits ADGSEL1, ADGSEL0 = 01b 000b AN8 001b AN9 010b AN10 011b AN11 100b Do not set. 101b 110b 111b

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27.2.5 A/D Control Re gister 0 (ADCON0)

ADST Bit (A/D conversion start flag) [Conditions for setting to 1] When A/D conversion starts and while A/D conversion is in progress. [Condition for setting to 0] When A/D conversion stops. Address 00D6h B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 ADST A/D conversion start flag 0: Stop A/D conversion 1: Start A/D conversion R/W b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b2 — b3 — b4 — b5 — b6 — b7 —

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27.2.6 A/D Control Re gister 1 (ADCON1)

Notes: 1. When on-chip reference voltage is used as analog input, first set the ADEX0 bit to 1 (on-chip reference voltage selected) and then set the OCVREFAN bit in the OCVREFCR register to 1 (on-chip reference voltage and analog input are connected). When on-chip reference voltage is not used as analog input, first set the OCVREFAN bit to 0 (on-chip reference voltage and analog input are cut off) and then set the ADEX0 bit to 0 (extended analog input pin not selected). 2. Do not set to 1 (A/D conversion using comparison reference voltage as input) in single sweep mode or repeat sweep mode. 3. When the ADSTBY bit is changed from 0 (A/D operation stops) to 1 (A/D operation enabled), wait for 1 φAD cycle or more before starting A/D conversion. 4. To enable the A/D open-circuit detection assist function, select the conversion start state with the ADDDAEL bit after setting the ADDDAEN bit to 1 (enabled). The conversion result with an open circuit varies with external circuits. Careful evaluation should be performed according to the system before using this function. If the ADCON1 register is rewritten during A/D conversion, the conversion result is undefined. Address 00D7h B i t b 7 b 6 b 5b 4b 3b 2b 1b 0 Symbol ADDDAEL ADDDAEN ADSTBY BITS — — — ADEX0 A f t e r R e s e t 0 0 000000 Bit Symbol Bit Name Function R/W b0 ADEX0 Extended analog input pin select bit (1) 0: Extended analog input pin not selected 1: On-chip reference voltage selected (2) R/W b1 — Reserved bits Set to 0. R/W b2 — b3 — b4 BITS 8/10-bit mode select bit 0: 8-bit mode 1: 10-bit mode R/W b5 ADSTBY A/D standby bit (3) 0: A/D operation stops (standby) 1: A/D operation enabled R/W b6 ADDDAEN A/D open-circuit detection assist function enable bit (4) 0: Disabled 1: Enabled R/W b7 ADDDAEL A/D open-circuit detection assist method select bit (4) 0: Discharge before conversion 1: Precharge before conversion R/W

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27.3 Common Items for Multiple Modes

27.3.1 Input/Output Pins

The analog input shares pins P1_0 to P1_3 in AN8 to AN11. When using the ANi (i = 8 to 11) pin as input, set the corresponding port direction bit to 0 (input mode). After changing the A/D operating mode, select an analog input pin again.

27.3.2 A/D Conversion Cycles

Figure 27.2 shows a Timing Diagram of A/D Conversion. Figure 27.3 shows the A/D Conversion Cycles (φAD = fAD). Figure 27.2 Timing Diagram of A/D Conversion Figure 27.3 A/D Conversion Cycles ( φAD = fAD) Sampling time 15 φAD cycles Conversion time of 1st bit 2nd bit Comparison time Comparison time …… * Repeat until conversion ends Comparison time Open-circuit detection Charging time Comparison time End process Open-circuit detection End process Start process Start process A/D conversion execution time Conversion time (Minimum) (1) 43 φAD 1 φAD Open-circuit detection Charging time Comparison timeSampling time End processConversion time at the 1st bit Comparison time Conversion time at the 2nd bit and the follows Disabled: 0 φAD Start process (Minimum) Enabled: 2 φAD End process Open-circuit detection 15 φAD 2.5 φAD 2.5 φAD 2 φAD Note: 1. The conversion time (minimum) is 43 φAD for 8-bit and 10-bit resolution. A/D conversion execution time Start process

R8C/32A Group 27. A/D Converter REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 441 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Table 27.3 shows the Number of Cy cles for A/D Conv ersion Items. The A/D conversion time is defined as follows. The start process time varies depending on which φAD is selected. When 1 (A/D conversion starts) is written to the ADST bit in the ADCON0 regist er, an A/D conversion starts after the start process time has elapsed. Reading th e ADST bit before the A/D conversion returns 0 (A/D conversion stops). In the modes where an A/D conversion is performed on mu ltiple pins or multiple times, the between-execution process time is inserted between the A/D conversion execution time for one pin and the next A/D conversion time. In one-shot mode and single sweep mode, the ADST bit is set to 0 during the end process time and the last A/D conversion result is stored in the ADi register.

• In on-shot mode Start process time + A/D conversion execution time + end process time
• When two pins are selected in single sweep mode Start process time + (A/D conversion execution time + between-execution process time + A/D conversion execution time) + end process time Table 27.3 Number of Cycles for A/D Conversion Items A/D Conversion Item Number of Cycles Start process time φAD = fAD 1 or 2 fAD cycles φAD = fAD divided by 2 2 or 3 fAD cycles φAD = fAD divided by 4 3 or 4 fAD cycles φAD = fAD divided by 8 5 or 6 fAD cycles A/D conversion execution time Open-circuit detection disabled 40 φAD cycles Open-circuit detection enabled 42 φAD cycles Between-execution process time 1 φAD cycle End process time 2 or 3 fAD cycles

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27.3.3 A/D Conversion Start Condition

A software trigger, trigger from timer RC, and external trigger are used as A/D conversion start triggers. Figure 27.4 shows the Block Diagram of A/D Conversion Start Control Unit. Figure 27.4 Block Diagram of A/D Conversion Start Control Unit

27.3.3.1 Software Trigger

A software trigger is selected when bits ADCAP1 to ADCAP0 in the ADMOD register are set to 00b (software trigger). The A/D conversion starts when the ADST bit in the ADCON0 register is set to 1 (A/D conversion starts).

27.3.3.2 Trigger from Timer RC

This trigger is selected when bits ADCAP1 to ADCAP0 in the ADMOD register are set to 10b (timer RC). To use this function, make sure the following conditions are met.

• Bits ADCAP1 to ADCAP0 in the ADMOD register are set to 10b (timer RC).
• Timer RC is used in the output compare function (timer mode, PWM mode, PWM2 mode).
• The ADTRGjE bit (j = A, B, C, D) in the TRCADCR register is set to 1 (A/D trigger occurs at compare match with TRCGRj register).
• The ADST bit in the ADCON0 register is set to 1 (A/D conversion starts). When the IMFj bit in the TRCSR register is changed from 0 to 1, A/D conversion starts. Refer to 19. Timer RC , 19.5 Timer Mode (Output Compare Function) , 19.6 PWM Mode , 19.7 PWM2 Mode for the details of timer RC and the output compare function (timer mode, PWM mode, and PWM2 mode).

27.3.3.3 External Trigger

This trigger is selected when bits ADCAP1 to ADCAP0 in the ADMOD register are set to 11b (external trigger (ADTRG)). To use this function, make sure the following conditions are met.

• Bits ADCAP1 to ADCAP0 in the ADMOD register are set to 11b (external trigger (ADTRG)).
• The INT0EN bit in the INTEN register is set to 1 ((INT0 input enabled)).
• The PD4_5 bit in the PD4 register is set to 0 (input mode).
• The ADST bit in the ADCON0 register is set to 1 (A/D conversion starts). When the ADTRG pin input is changed from “H” to “L” under the above conditions, A/D conversion starts. j = A, B, C, D k = 0 to 1 ADCAP1 to ADCAP0: Bits in ADMOD register ADST: Bit in ADCON0 register ADTRGjE: Bit in TRCADCR register INT0EN: Bit in INTEN register IMFj: Bit in TRCSR register PD4_5: Bit in PD4 register ADST A/D conversion start trigger ADCAP1 to ADCAP0 (1) = 00b = 10b = 11b INT0EN IMFj (TRCSR register) ADTRGjE ADTRG pin PD4_5 Note: 1. Do not set bits ADCAP1 to ADCAP0 to 01b.

R8C/32A Group 27. A/D Converter REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 443 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

27.3.4 A/D Conversion Result

The A/D conversion result is stored in the ADi register (i = 0 to 7). The register where the result is stored varies depending on the A/D operating mode used. The contents of the ADi register are undefined after a reset. Values cannot be written to the ADi register. In repeat mode 0, no interrupt request is generated. After the first AD conversion is completed, determine if the A/D conversion time has elapsed by a program. In one-shot mode, repeat mode 1, single sweep mode, and repeat sweep mode, an interrupt request is generated at certain times, such as when an A/D conversion completes (the IR bit in the ADIC register is set to 1). However, in repeat mode 1 and repeat sweep mode, A/D conversion continues after an interrupt request is generated. Read the ADi register before the next A/ D conversion is completed, since at completion the ADi register is rewritten with the new value. In one-shot mode and single sweep mode, when bits ADCAP1 to ADCAP0 in the ADMOD register is set to 00b (software trigger), the ADST bit in the ADCON0 register is used to determine whether the A/D conversion or sweep has completed. During an A/D conversion operation, if the ADST bit in the ADCON0 register is set to 0 (A/D conversion stops) by a program to forcibly terminate A/D conv ersion, the conversion result of the A/D converter is undefined and no interrupt is generated. If the ADST bit is set to 0 by a program, do not use the value of the ADi register.

27.3.5 Low Current C onsumption Function

When the A/D converter is not used , power consumption can be reduced by setting the ADSTBY bit in the ADCON1 register to 0 (A/D operation stops (standby)) to shut off any analog circuit current flow. To use the A/D converter, set the ADSTBY bit to 1 (A/D operation enabled) and wait for 1 φAD cycle or more before setting the ADST bit in the ADCON0 register to 1 (A/D conversion starts). Do not write 1 to bits ADST and ADSTBY at the same time. Also, do not set the ADSTBY bit to 0 (A/D operation stops (standby)) during A/D conversion.

27.3.6 Extended Analog Input Pins

In one-shot mode, repeat mode 0, and repeat mode 1, the on-chip reference voltage (OCVREF) can be used as analog input. Any variation in VREF can be confirmed using the on-chip reference voltage. Use the ADEX0 bit in the ADCON1 register and the OCVREFAN bit in the OCVREFCR register to select the on-chip reference voltage. The A/D conversion result of the on-chip reference voltage in one-shot mode or in repeat mode 0 is stored in the AD0 register.

27.3.7 A/D Open-Circuit Detection Assist Function

To suppress influences of the analog input voltage leak age from the previously converted channel during A/D conversion operation, a function is incorporated to fix th e electric charge on the chopper amp capacitor to the predetermined state (A VCC or GND) before starting conversion. This function enables more reliable detection of an open circuit in the wiring connected to the analog input pins. Figure 27.5 shows the A/D Open-Circuit Detection Ex ample on A VCC Side (Prech arge before Conversion Selected) and Figure 27.6 shows the A/D Open-Circu it Detection Example on A VSS Side (Discharge before Conversion Selected).

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27.4 One-Shot Mode

In one-shot mode, the input voltage to one pin selected from among AN8 to AN11 or OCVREF is A/D converted once. Table 27.4 lists the One-Shot Mode Specifications. Table 27.4 One-Shot Mode Specifications Item Specification Function The input voltage to the pin selected by bits CH2 to CH0 and bits ADGSEL1 to ADGSEL0 in the ADINSEL register or the ADEX0 bit in the ADCON1 register is A/D converted once. Resolution 8 bits or 10 bits A/D conversion start condition • Software trigger

• Timer RC
• External trigger (Refer to 27.3.3 A/D Conversion Start Condition) A/D conversion stop condition • A/D conversion completes (If bits ADCAP1 to ADCAP0 in the ADMOD register are set to 00b (software trigger), the ADST bit in the ADCON0 register is set to 0.)
• Set the ADST bit to 0 Interrupt request generation timing When A/D conversion completes Analog input pin One pin selectable from among AN8 to AN11, or OCVREF. Storage resister for A/D conversion result AD0 register: AN8, OCVREF AD1 register: AN9 AD2 register: AN10 AD3 register: AN11 Reading of result of A/D converter Read register AD0 to AD3 corresponding to the selected pin.

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27.5 Repeat Mode 0

In repeat mode 0, the input voltage to one pin select ed from among AN8 to AN11 or OCVREF is A/D converted repeatedly. Table 27.5 lists the Repeat Mode 0 Specifications. Table 27.5 Repeat Mode 0 Specifications Item Specification Function The input voltage to the pin selected by bits CH2 to CH0 and bits ADGSEL1 to ADGSEL0 in the ADINSEL register or the ADEX0 bit in the ADCON1 register is A/D converted repeatedly. Resolution 8 bits or 10 bits A/D conversion start condition • Software trigger

• Timer RC
• External trigger (Refer to 27.3.3 A/D Conversion Start Condition) A/D conversion stop condition Set the AD ST bit in the ADCON0 register to 0 Interrupt request generation timing Not generated Analog input pin One pin selectable from among AN8 to AN11, or OCVREF. Storage resister for A/D conversion result AD0 register: AN8, OCVREF AD1 register: AN9 AD2 register: AN10 AD3 register: AN11 Reading of result of A/D converter Read register AD0 to AD3 corresponding to the selected pin.

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27.6 Repeat Mode 1

In repeat mode 1, the input voltage to one pin select ed from among AN8 to AN11 or OCVREF is A/D converted repeatedly. Table 27.6 lists the Repeat Mode 1 Specifications. Figure 27.7 shows the Operating Example of Repeat Mode 1. Table 27.6 Repeat Mode 1 Specifications Item Specification Function The input voltage to the pin selected by bits CH2 to CH0 and bits ADGSEL1 to ADGSEL0 in the ADINSEL register or the ADEX0 bit in the ADCON1 register is A/D converted repeatedly. Resolution 8 bits or 10 bits A/D conversion start condition • Software trigger

• Timer RC
• External trigger (Refer to 27.3.3 A/D Conversion Start Condition) A/D conversion stop condition Set the AD ST bit in the ADCON0 register to 0 Interrupt request generation timing When the A/D conversion result is stored in the AD7 register. Analog input pin One pin selectable from among AN8 to AN11, or OCVREF. Storage resister for A/D conversion result AD0 register: 1st A/D conversion result, 9th A/D conversion result... AD1 register: 2nd A/D conversion result, 10th A/D conversion result... AD2 register: 3rd A/D conversion result, 11th A/D conversion result... AD3 register: 4th A/D conversion result, 12th A/D conversion result... AD4 register: 5th A/D conversion result, 13th A/D conversion result... AD5 register: 6th A/D conversion result, 14th A/D conversion result... AD6 register: 7th A/D conversion result, 15th A/D conversion result... AD7 register: 8th A/D conversion result, 16th A/D conversion result... Reading of result of A/D converter Read registers AD0 to AD7

R8C/32A Group 27. A/D Converter REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 448 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 27.7 Operating Example of Repeat Mode 1 8th A/D conversion result 7th A/D conversion result The above applies under the following conditions: Bits ADCAP1 to ADCAP0 in the ADMOD register are set to 00b (starts by software trigger). Set to 0 when interrupt request is acknowledged, or set by a program. Successive conversion register 1st 2nd 3rd 4th AD0 register Undefined ADST bit in ADCON0 register AD1 register Undefined AD2 register Undefined AD3 register Undefined “1” “0” 1st A/D conversion result 2nd A/D conversion result 3rd A/D conversion result 4th A/D conversion result IR bit in ADIC register “1” “0” 5th 6th 7th 8th 9th Undefined Undefined Undefined Undefined 5th A/D conversion result 6th A/D conversion result AD4 register AD5 register AD6 register AD7 register 9th A/D conversion result

R8C/32A Group 27. A/D Converter REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 449 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

27.7 Single Sweep Mode

In single sweep mode, the input voltage to two or four pins selected from among AN8 to AN11 are A/D converted once. Table 27.7 lists the Single Sweep Mode Specifications. Figure 27.8 shows the Operating Example of Single Sweep Mode. Table 27.7 Single Sweep Mode Specifications Item Specification Function The input voltage to the pins se lected by bits ADGSEL1 to ADGSEL0 and the SCAN0 bit in the ADINSEL register is A/D converted once. Resolution 8 bits or 10 bits A/D conversion start condition • Software trigger

• Timer RC
• External trigger (Refer to 27.3.3 A/D Conversion Start Condition) A/D conversion stop condition • If two pins are sele cted, when A/D conversion of the two selected pins completes (the ADST bit in the ADCON0 register is set to 0).
• If four pins are selected, when A/D conversion of the four selected pins completes (the ADST bit is set to 0).
• Set the ADST bit to 0. Interrupt request generation timing
• If two pins are selected, when A/D conversion of the two selected pins completes.
• If four pins are selected, when A/D conversion of the four selected pins completes. Analog input pin AN8 to AN9(2 pins), AN8 to AN11(4 pins), (Selectable by the SCAN0 bit and bits ADGSEL1 to ADGSEL0.) Storage resister for A/D conversion result AD0 register: AN8 AD1 register: AN9 AD2 register: AN10 AD3 register: AN11 Reading of result of A/D converter Read the registers from AD0 to AD3 corresponding to the selected pin.

R8C/32A Group 27. A/D Converter REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 450 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 27.8 Operating Example of Single Sweep Mode Set to 0 when interrupt request is acknowledged, or set by a program. Successive conversion register AN8 AN9 AN10 AN11 AD0 register Undefined ADST bit in ADCON0 register AD1 register Undefined AD2 register Undefined AD3 register Undefined “1” “0” AN8 in A/D conversion result AN9 in A/D conversion result AN10 in A/D conversion result AN11 in A/D conversion result IR bit in ADIC register “1” “0” The above applies under the following conditions:

• Bits ADCAP1 to ADCAP0 in the ADMOD register are set to 00b (starts by software trigger).
• The SCAN0 bit in the ADINSEL register are set to 1 (4 pins), bits ADGSEL1 to ADGSEL0 are set to 01b (AN8, AN9, AN10, AN11).

R8C/32A Group 27. A/D Converter REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 451 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

27.8 Repeat Sweep Mode

In repeat sweep mode, the input voltage to two or four pins selected from among AN8 to AN11 are A/D converted repeatedly. Table 27.8 lists the Repeat Sweep Mode Specifications. Figure 27.9 shows the Operating Example of Repeat Sweep Mode. Table 27.8 Repeat Sweep Mode Specifications Item Specification Function The input voltage to the pins se lected by bits ADGSEL1 to ADGSEL0 and the SCAN0 bit in the ADINSEL register are A/D converted repeatedly. Resolution 8 bits or 10 bits A/D conversion start condition • Software trigger

• Timer RC
• External trigger (Refer to 27.3.3 A/D Conversion Start Condition) A/D conversion stop condition Set the AD ST bit in the ADCON0 register to 0 Interrupt request generation timing
• If two pins are selected, when A/D conversion of the two selected pins completes.
• If four pins are selected, when A/D conversion of the four selected pins completes. Analog input pin AN8 to AN9(2 pins), AN8 to AN11(4 pins), (Selectable by the SCAN0 bit and bits ADGSEL1 to ADGSEL0.) Storage resister for A/D conversion result AD0 register: AN8 AD1 register: AN9 AD2 register: AN10 AD3 register: AN11 Reading of result of A/D converter Read the registers from AD0 to AD3 corresponding to the selected pin.

R8C/32A Group 27. A/D Converter REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 452 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 27.9 Operating Example of Repeat Sweep Mode Set to 0 when interrupt request is acknowledged, or set by a program. Successive conversion register AN8 AN9 AN10 AN11 AD0 register Undefined ADST bit in ADCON0 register AD1 register Undefined AD2 register Undefined AD3 register Undefined “1” “0” AN8 in A/D conversion result AN9 in A/D conversion result AN10 in A/D conversion result AN11 in A/D conversion result IR bit in ADIC register “1” “0” AN8 AN9 AN10 AN11 The above applies under the following conditions:

• Bits ADCAP1 to ADCAP0 in the ADMOD register are set to 00b (starts by software trigger).
• The SCAN0 bit in the ADINSEL register are set to 1 (4 pins), bits ADGSEL1 to ADGSEL0 are set to 01b (AN8, AN9, AN10, and AN11). AN8 AN8 in A/D conversion result Set to 0 when interrupt request is acknowledged, or set by a program. AN11 in A/D conversion result AN9 in A/D conversion result AN10 in A/D conversion result AN8 in A/D conversion result

R8C/32A Group 27. A/D Converter REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 453 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

27.9 Internal Equivalent Circuit of Analog Input

Figure 27.10 shows the Internal Equivalent Circuit of Analog Input. Figure 27.10 Internal Equivalent Circuit of Analog Input VCC Parasitic Diode Chopper-type Amplifier A/D Successive Conversion Register Comparison voltage VCC VSS AN8 VSS i = 4 AN11 VREF AVSS Vref Comparison reference voltage (Vref) generator SW1 SW2 AVCC AMP SW3 AVSS VIN SW4 SW5 SW1 Parasitic Diode ON Resistor TBD kΩ Wiring Resistor TBD k Ω ON Resistor TBD k Ω ON Resistor TBD kΩ Wiring Resistor TBD kΩ i Ladder-type Switches ADINSEL register ON Resistor TBD kΩ Analog Input Voltage Sampling Control Signal Reference Control Signal ON Resistor Approx. TBD kΩ C = Approx.TBD pF A/D Conversion Interrupt Request SW1 conducts only on the ports selected for analog input. SW2 and SW3 are open when A/D conversion is not in progress; their status varies as shown by the waveforms in the diagrams on the left. SW4 conducts only when A/D conversion is not in progress. SW5 conducts when compare operation is in progress. Control signal for SW2 Control signal for SW3 Sampling Comparison Connect to Connect to Connect to Connect to Note: 1. Use only as a standard for designing this data. Mass production may cause some changes in device characteristics. i Ladder-type Wiring Resistors Resistor ladder ADINSEL register ADINSEL register

R8C/32A Group 27. A/D Converter REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 454 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

27.10 Output Impedance of Sensor under A/D Conversion

To carry out A/D conversion properly, charging the internal capacitor C shown in Figure 27.11 has to be completed within a specified period of time. T (sampling time) as the specified time. Let ou tput impedance of sensor equivalent circuit be R0, internal resistance of microcom puter be R, precision (error) of the A/D converter be X, and the resolution of A/D converter be Y (Y is 1024 in the 10-bit mode, and 256 in the 8-bit mode). VC is generally And when t = T, Hence, Figure 27.11 shows Analog Input Pin and External Sensor Equivalent Circuit. When the difference between VIN and VC becomes 0.1LSB, we find impedance R0 when voltage between pins VC changes from 0 to VIN- (0.1/1024) VIN in time T. (0.1/1024) means that A/D precisi on drop due to insufficient capacitor charge is held to 0.1LSB at time of A/D conversion in the 10-bit mode. Actu al error however is the value of absolute precision added to 0.1LSB. T = TBD µs when f(φAD) = TBD MHz. Output impedance R0 for sufficiently charging capacitor C within time T is determined as follows. T = TBD µs, R = TBD kΩ, C = TBD pF, X = 0.1, and Y = 1024. Hence, Thus, the allowable output impedance of the sensor equivalent circuit, making the precision (error) 0.1LSB or less, is approximately TBD kΩ. maximum. Figure 27.11 Analog Input Pin and Exte rnal Sensor Equivalent Circuit R0 T C X Y----ln• Y----ln= e Y----= VC VIN X Y---- VIN VIN 1 X Y----– =–= VC VIN 1 e = R0 TBD TBD 0.1 R0 R (TBD kΩ) C (TBD pF) VIN VC MCU Sensor equivalent circuit Note: 1. The capacity of the terminal is assumed to be TBD pF.

R8C/32A Group 27. A/D Converter REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 455 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

27.11 Notes on A/D Converter

• Write to the ADMOD register, the ADINSEL register, the ADCON0 register (other than ADST bit), the ADCON1 register, the OCVREFCR register when A/D conversion is stopped (before a trigger occurs).
• To use the A/D converter in repeat mode 0, repeat mode 1, or repeat sweep mode, select the frequency of the A/D converter operating clock φAD or more for the CPU clock during A/D conversion. Do not select fOCO-F as φAD.
• Connect 0.1 µF capacitor between the VREF pin and A VSS pin.
• Do not enter stop mode during A/D conversion.
• Do not enter wait mode during A/D conversion regardless of the state of the CM02 bit in the CM0 register (1: Peripheral function clock stops in wait mode or 0: Peripheral function clock does not stop in wait mode).
• Do not set the FMSTP bit in the FMR0 register to 1 (flash memory stops) during A/D conversion.

R8C/32A Group 28. Comparator A REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 456 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 28. Comparator A Comparator A compares a reference input voltage and an analog input voltage. Comparator A1 and comparator A2 are independent of each other. Note that these comparators share the voltage detection circuit wi th voltage monitor 1 and voltage monitor 2. Either comparator A1 and comparator A2 or voltage monitor 1 and voltage monitor 2 can be selected to use the voltage detection circuit.

28.1 Overview

The comparison result of the referen ce input voltage and analog input voltage can be read by software. The result also can be output from the VCOUTi (i = 1 or 2) pin. An input voltage to the LVREF pi n can be selected as the reference input voltage. Also, the comparator A1 interrupt and comparator A2 interrupt can be used. Table 28.1 lists the Comparator A Sp ecifications, Figure 28.1 shows a Co mparator A Block Diagram, and Table 28.2 lists the Pin Configuration of Comparator A. Table 28.1 Comparator A Specifications Item Comparator A1 Comparator A2 Analog input voltage Input voltage to the LVCMP1 pin Input voltage to the LVCMP2 pin Reference input voltage Input voltage to the LVREF pin Comparison target Whether passing thorough the reference input voltage by rising or falling. Comparison result monitor The VW1C3 bit in the VW1C register The VCA13 bit in the VCA1 register Whether higher or lower than the reference input voltage. Interrupt Comparator A1 interrupt (non-makable or maskable selectable) Comparator A2 interrupt (non-makable or maskable selectable) Interrupt request at: Reference input voltage > input voltage to the LVCMP1 pin and/or Input voltage to the LVCMP1 pin > reference input voltage Interrupt request at: Reference input voltage > input voltage to the LVCMP2 pin and/or Input voltage to the LVCMP2 pin > reference input voltage Digital Filter Switching enable/disable Supported Sampling time (fOCO-S divided by n) × 2 n: 1, 2, 4, and 8 Comparison result output Output from the LVCOUT1 pin (Whether the comparison result output is inverted or not can be selected.) Output from the LVCOUT2 pin (Whether the comparison result output is inverted or not can be selected.)

R8C/32A Group 28. Comparator A REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 457 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 28.1 Comparator A Block Diagram Table 28.2 Pin Configuration of Comparator A Pin Name I/O Function LVCMP1 Input Comparator A1 analog pin LVCOUT1 Output Comparator A1 comparison result output pin LVCMP2 Input Comparator A2 analog pin LVCOUT2 Output Comparator A2 comparison result output pin LVREF Input Comparator reference voltage pin VW1F1 to VW1F0 = 01b = 10b = 11b VCA13: Bit in VCA1 register VCA21, VCA22, VCA23, VCA24, VCA26, VCA27: Bits in VCA2 register VW1C0 to VW1C3, VW1F0, VW1F1: Bits in VW1C register VW2C0, VW2C2, VW2F0, VW2F1: Bits in VW2C register CM1POR, CM2POR, CM1OE, CM2OE, IRQ1SEL, IRQ2SEL: Bits in CMPA register fOCO-S fOCO-S/4 fOCO-S/8 LVCMP1 VCA22 Digital filter LVREF LVCMP2 VCA24 VCA23 = 00b Sampling clock VCA26 VW1C3 fOCO-S/2 VW1C1 VW2F1 to VW2F0 = 01b = 10b = 11b fOCO-S fOCO-S/4 fOCO-S/8 Digital filter = 00b Sampling clock VCA13 fOCO-S/2 VW2C1 Internal reference voltage VCA27 Shared with voltage monitor 1 circuit Shared with voltage monitor 2 circuit VW1C2 IRQ1SEL VW1C0 Edge selection circuit Pin output selection circuit CM1POR CM2POR CM1OE CM2OE VW2C2 IRQ2SEL VW2C0 Edge selection circuit LVCOUT1 LVCOUT2 Non-maskable interrupts Maskable interrupts Non-maskable interrupts Maskable interrupts

R8C/32A Group 28. Comparator A REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 458 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

28.2 Registers

28.2.1 Voltage Monitor Circuit/Comp arator A Control Register (CMPA)

28.2.2 Voltage Monitor Circuit Edge Select Register (VCAC)

Notes: 1. When the VCA1 bit is set tot 0 (one edge), the VW1C7 bit in the VW1C register is enabled. Set the VW1C7 bit after setting the VCAC1 bit to 0. 2. When the VCA2 bit is set tot 0 (one edge), the VW2C7 bit in the VW2C register is enabled. Set the VW2C7 bit after setting the VCAC2 bit to 0. Address 0030h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol COMPSEL — IRQ2SEL IRQ1SEL CM2OE CM1OE CM2POR CM1POR A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 CM1POR LVCOUT1 output polarity select bit 0: Non-inverted comparator A1 comparison result is output to LVCOUT1. 1: Inverted comparator A1 comparison result is output to LVCOUT1. R/W b1 CM2POR LVCOUT2 output polarity select bit 0: Non-inverted Comparator A2 comparison result is output to LVCOUT2. 1: Inverted comparator A2 comparison result is output to LVCOUT2. R/W b2 CM1OE LVCOUT1 output enable bit 0: Output disabled 1: Output enabled R/W b3 CM2OE LVCOUT2 output enable bit 0: Output disabled 1: Output enabled R/W b4 IRQ1SEL Voltage monitor 1/comparator A1 interrupt type select bit 0: Non-maskable interrupt 1: Maskable interrupt R/W b5 IRQ2SEL Voltage monitor 2/comparator A2 interrupt type select bit 0: Non-maskable interrupt 1: Maskable interrupt R/W b6 — Reserved bit Set to 0. R/W b7 COMPSEL Voltage monitor/comparator A interrupt type selection enable bit 0: Bits IRQ1SEL and IRQ2SEL disabled 1: Bits IRQ1SEL and IRQ2SEL enabled R/W Address 0031h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — — — VCAC2 VCAC1 — A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b1 VCAC1 Comparator A1 circuit edge select bit (1) 0: One edge 1: Both edges R/W b2 VCAC2 Comparator A2 circuit edge select bit (2) 0: One edge 1: Both edges R/W b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b4 — b5 — b6 — b7 —

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28.2.3 Voltage Detect Register (VCA1)

Note: 1. When the VCA27 bit in the VCA2 register is set to 1 (comparator A2 circuit enabled), the VCA13 bit is enabled. When the VCA27 bit in the VCA2 register is set to 0 (com parator A2 circuit disabled), the VCA13 bit is set to 1 (VCMP2 ≥ reference voltage). Address 0033h B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00001000 Bit Symbol Bit Name Function R/W b0 — Reserved bits Set to 0. R/W b1 — b2 — b3 VCA13 Comparator A2 signal monitor flag (1) 0: LVCMP2 < reference voltage 1: LVCMP2 ≥ reference voltage or comparator A2 circuit disabled R b4 — Reserved bits Set to 0. R/W b5 — b6 — b7 —

R8C/32A Group 28. Comparator A REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 460 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

28.2.4 Voltage Detect Register 2 (VCA2)

Notes: 1. Use the VCA20 bit only when the MCU enters wait mode. To set the VCA20 bit, follow the procedure shown in Figure 9.3 Procedure for Reducing Internal Power Consumption Using VCA20 bit. 2. When the VCA20 bit is set to 1 (low consumption enabled), do not set the CM10 bit in the CM1 register to 1 (stop mode). 3. To use voltage monitor 0 reset, set the VCA25 bit to 1. After the VCA25 bit is set to 1 from 0, allow td(E-A) to elapse before the voltage detection circuit starts operation. 4. To use the voltage detection 1/comparator A1 interrupt or the VW1C3 bit in the VW1C register, set the VCA26 bit to 1. After the VCA26 bit is set to 1 from 0, allow td(E-A) to elapse before the voltage detection 1/comparator A1 circuit starts operation. 5. To use the voltage detection 2/comparator A2 interrupt or the VCAC13 bit in the VCA1 register, set the VCA27 bit to 1. After the VCA27 bit is set to 1 from 0, allow td(E-A) to elapse before the voltage detection 2/comparator A2 circuit starts operation. Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting the VCA2 register. Address 0034h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol VCA27 VCA26 VCA25 VCA24 VCA23 VCA22 VCA21 VCA20 After Reset The LVDAS bit in the OFS register is set to 1. 00000000 After Reset The LVDAS bit in the OFS register is set to 0. 00100000 Bit Symbol Bit Name Function R/W b0 VCA20 Internal power low consumption enable bit (1) 0: Low consumption disabled 1: Low consumption enabled (2) R/W b1 VCA21 Comparator A1 reference voltage input select bit 0: Internal reference voltage 1: LVREF pin input voltage R/W b2 VCA22 LVCMP1 comparison voltage external input select bit 0: Supply voltage (VCC) 1: LVCMP1 pin input voltage R/W b3 VCA23 Comparator A2 reference voltage input select bit 0: Internal reference voltage 1: LVREF pin input voltage R/W b4 VCA24 LVCMP2 comparison voltage external input select bit 0: Supply voltage (VCC) (Vdet2_0) 1: LVCMP2 pin input voltage (Vdet2_EXT) R/W b5 VCA25 Voltage detection 0 enable bit (3) 0: Voltage detection 0 circuit disabled 1: Voltage detection 0 circuit enabled R/W b6 VCA26 Voltage detection 1/comparator A1 enable bit (3) 0: Voltage detection 1/comparator A1 circuit disabled 1: Voltage detection 1/comparator A1 circuit enabled R/W b7 VCA27 Voltage detection 2/comparator A2 enable bit (5) 0: Voltage detection 2/comparator A2 circuit disabled 1: Voltage detection 2/comparator A2 circuit enabled R/W

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28.2.5 Voltage Monitor 1 Circ uit Control Register (VW1C)

Notes: 1. The VW1C0 is enabled when the VCA26 bit in the VCA2 r egister is set to 1 (comparator A1 circuit enabled). Set the VW1C0 bit to 0 (disabled) when the VCA26 bit is set to 0 (comparator A1 circuit disabled). To set the VW1C0 bit to 1 (enabled), follow the procedure shown in Table 28.3 Procedure for Setting Bits Associated with Comparator A1 Interrupt. 2. To use the comparator A1 interrupt to exit stop mode and to return again, write 0 and then 1 to the VW1C1 bit. 3. Bits VW1C2 and VW1C3 are enabled when the VCA26 bit in the VCA2 register is set to 1 (comparator A1 circuit enabled). 4. Set the VW1C2 bit to 0 by a program. When 0 is written by a program, this bit is set to 0 (and remains unchanged even if 1 is written to it). 5. The VW1C7 bit is enabled when the VCAC1 bit in the VCAC register is set to 0 (one edge). After setting the VCAC1 bit to 0, set the VW1C7 bit. Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting the VW1C register. Rewriting the VW1C register may set the VW1C2 bit to 1. After rewriting this register, set the VW1C2 bit to 0. Address 0039h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol VW1C7 — VW1F1 VW1F0 VW1C3 VW1C2 VW1C1 VW1C0 A f t e r R e s e t 10001010 Bit Symbol Bit Name Function R/W b0 VW1C0 Comparator A1 interrupt enable bit (1) 0: Disabled 1: Enabled R/W b1 VW1C1 Comparator A1 digital filter disable mode select bit (2) 0: Digital filter enable mode (digital filter circuit enabled) 1: Digital filter disable mode (digital filter circuit disabled) R/W b2 VW1C2 Comparator A1 interrupt flag (3, 4) [Condition to set this bit to 0] 0 is written. [Condition to set this bit to 1] When an interrupt request is generated. R/W b3 VW1C3 Comparator A1 signal monitor flag (3) 0: LVCMP1 < reference voltage 1: LVCMP1 ≥ reference voltage or comparator A1 circuit disabled R b4 VW1F0 Sampling clock select bit b5 b4 0 0: fOCO-S divided by 1 0 1: fOCO-S divided by 2 1 0: fOCO-S divided by 4 1 1: fOCO-S divided by 8 R/W b5 VW1F1 R/W b6 — Reserved bit Set to 0. R/W b7 VW1C7 Comparator A1 interrupt generation condition select bit (5) 0: When LVCMP1 reaches reference voltage or above. 1: When LVCMP1 reaches reference voltage or below. R/W

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28.2.6 Voltage Monitor 2 Circ uit Control Register (VW2C)

Notes: 1. The VW2C0 is enabled when the VCA27 bit in the VCA2 r egister is set to 1 (comparator A2 circuit enabled). Set the VW2C0 bit to 0 (disabled) when the VCA27 bit is set to 0 (comparator A2 circuit disabled). To set the VW1C0 bit to 1 (enabled), follow the procedure shown in Table 28.4 Procedure for Setting Bits Associated Comparator A2 Interrupt. 2. To use the comparator A2 interrupt to exit stop mode and to return again, write 0 and then 1 to the VW2C1 bit. 3. The VW2C2 bit is enabled when the VCA27 bit in the VCA2 register is set to 1 (comparator A2 circuit enabled). 4. Set this bit to 0 by a program. When 0 is written by a pr ogram, this bit is set to 0 (and remains unchanged even if 1 is written to it). 5. The VW2C7 bit is enabled when the VCAC2 bit in the VCAC register is set to 0 (one edge). After setting the VCAC2 bit to 0, set the VW2C7 bit. Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting the VW2C register. Rewriting the VW2C register may set the VW2C2 bit to 1. After rewriting this register, set the VW2C2 bit to 0. Address 003Ah B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol VW2C7 VW2C6 VW2F1 VW2 F0 VW2C3 VW2C2 VW2C1 VW2C0 A f t e r R e s e t 10000010 Bit Symbol Bit Name Function R/W b0 VW2C0 Comparator A2 interrupt enable bit (1) 0: Disabled 1: Enabled R/W b1 VW2C1 Comparator A2 digital filter disable mode select bit (2) 0: Digital filter enable mode (digital filter circuit enabled) 1: Digital filter disable mode (digital filter circuit disabled) R/W b2 VW2C2 Comparator A2 interrupt flag (3, 4) [Condition to set this bit to 0] 0 is written. [Condition to set this bit to 1] When an interrupt request is generated. R/W b3 VW2C3 WDT detection monitor flag (4) 0: Not detected 1: Detected R/W b4 VW2F0 Sampling clock select bit b5 b4 0 0: fOCO-S divided by 1 0 1: fOCO-S divided by 2 1 0: fOCO-S divided by 4 1 1: fOCO-S divided by 8 R/W b5 VW2F1 R/W b6 VW2C6 Reserved bit Set to 0. R/W b7 VW2C7 Comparator A2 interrupt generation condition select bit (5) 0: When LVCMP2 reaches reference voltage or above. 1: When LVCMP2 reaches reference voltage or below. R/W

R8C/32A Group 28. Comparator A REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 463 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

28.3 Monitoring Comparison Results

28.3.1 Monitoring Comparator A1

Once the following settings are made, the comparison result of comparator A1 can be monitored by the VW1C3 bit in the VW1C register after td(E-A) has elapsed (refer to 32. Electrical Characteristics). (1) Set the VCA21 bit in the VCA2 register to 1 (LVREF pin input voltage). (2) Set the VCA22 bit in the VCA2 register to 1 (LVCMP1 pin input voltage). (3) Set the VCA26 bit in the VCA2 register to 1 (comparator A1 circuit enabled).

28.3.2 Monitoring Comparator A2

Once the following settings are made, the comparison result of comparator A2 can be monitored by the VCA13 bit in the VCA1 register after td(E-A) has elapsed (refer to 32. Electrical Characteristics). (1) Set the VCA23 bit in the VCA2 register to 1 (LVREF pin input voltage). (2) Set the VCA24 bit in the VCA2 register to 1 (LVCMP2 pin input voltage). (3) Set the VCA27 bit in the VCA2 register to 1 (comparator A2 circuit enabled).

R8C/32A Group 28. Comparator A REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 464 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

28.4 Functional Description

Comparator A1 and comparator A2 operate independently. The comparison result of the referen ce input voltage and analog input voltage can be read by software. The result can also be output from the LVCOUTi (i = 1 or 2) pin. An input voltage to the LVREF pin can be used as the reference input voltage. The comparator A1 interrupt or th e comparator A2 interrupt can be used by selecting non- maskable or maskable for each interrupt type.

28.4.1 Comparator A1

Table 28.3 lists the Procedure for Setting Bits Associat ed with Comparator A1 Interrupt, Figure 28.2 shows a Comparator A1 Operating Example (Digital Filter Enabled), and Figure 28.3 shows a Comparator A1 Operating Example (Digital Filter Disabled). Note: When the VW1C0 bit is set to 0, steps 6 and 7 can be executed at the same time (with one instruction). Table 28.3 Procedure for Setting Bits Associated with Comparator A1 Interrupt Step When Using Digital Filter When Using No Digital Filter 1 Set the COMPSEL bit in the CMPA register to 1 (bits IRQ1SEL and IRQ2SEL enabled).

2 Set the VCA21 bit in the VCA2 register to 1 (LVREF pin input voltage) and

the VCA22 bit to 1 (LVCMP1 pin input voltage). 3 Set the VCA26 bit in the VCA2 register to 1 (comparator A1 circuit enabled). 4 Wait for td(E-A). 5 Select the interrupt type by the IRQ1SEL bit in the CMPA register.

6 Select the sampling clock of the digital filter by

bits VW1F0 and VW1F1 in the VW1C register. Set the VW1C1 bit in the VW1C register to 1 (digital filter disabled). (1) Set the VW1C1 bit in the VW1C register to 0 (digital filter enabled).

8 Select the interrupt request timing by the VCAC1 bit in the VCAC register and

the VW1C7 bit in the VW1C register. 9 Set the VW1C2 bit in the VW1C register to 0.

10 Set the CM14 bit in the CM1 register to 0

(low-speed on-chip oscillator on).

11 Wait for 2 cycles of the sampling clock of

the digital filter. − (No wait time required) 12 Set the VW1C0 bit in the VW1C register to 1 (comparator A1 interrupt enabled).

R8C/32A Group 28. Comparator A REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 465 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 28.2 Comparator A1 Operating Example (Digital Filter Enabled) Reference voltage (LVREF) VW1C3 bit LVCOUT1 output (CM1POR = 0) LVCMP1 The above applies when:

• VCA26 bit in VCA2 register = 1 (comparator A1 circuit enabled)
• VW1C0 bit in VW1C register = 1 (comparator A1 interrupt enabled)
• CM1OE bit in CMPA register = 1 (output enabled)
• VCA22 bit in VCA2 register = 1 (LVCMP1 pin input voltage)
• COMPSEL bit in CMPA register = 1 (bits IRQ1SEL and IRQ2SEL enabled) Sampling clock of digital filter × 2 cycles VW1C2 bit VW1C1, VW1C2, VW1C3, VW1C7: Bits in VW1C register VCAC1: Bit in VCAC register CM1POR, IRQ1SEL: Bits in CMPA register Sampling clock of digital filter × 2 cycles IR bit in VCMP1IC register (IRQ1SEL = 1) VW1C1 bit is set to 0 (digital filter enabled) and VCAC1 bit is set to 1 (both edges) VW1C2 bit Set to 0 by a program. VW1C1 bit is set to 0 (digital filter enabled), VCAC1 bit is set to 0 (one edge), and VW1C7 bit is set to 0 (when LVCMP1 reaches reference voltage or above) VW1C2 bit VW1C1 bit is set to 0 (digital filter enabled), VCAC1 bit is set to 0 (one edge), and VW1C7 bit is set to 1 (when LVCMP1 reaches reference voltage or below) Set to 0 by a program. IR bit in VCMP1IC register (IRQ1SEL = 1) 0 Set to 0 when an interrupt request is acknowledged or by a program. LVCOUT1 output (CM1POR = 0) IR bit in VCMP1IC register (IRQ1SEL = 1) 0 Set to 0 when an interrupt request is acknowledged or by a program. LVCOUT1 output (CM1POR = 1) 0 Set to 0 when an interrupt request is acknowledged or by a program. Set to 0 by a program.

R8C/32A Group 28. Comparator A REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 466 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 28.3 Comparator A1 Operating Example (Digital Filter Disabled) VW1C3 bit VW1C2 bit VW1C1 bit is set to 1 (digital filter disabled), VCAC1 bit is set to 0 (one edge), and VW1C7 bit is set to 0 (when LVCMP1 reaches reference voltage or above) VW1C2 bit VW1C2 bit VW1C1 bit is set to 1 (digital filter disabled) and VCAC1 bit is set to 1 (both edges) Set to 0 by a program. Set to 0 by a program. Set to 0 by a program. VW1C1 bit is set to 1 (digital filter disabled), VCAC1 bit is set to 0 (one edge), and VW1C7 bit is set to 1 (when LVCMP1 reaches reference voltage or below) LVCOUT1 output (CM1POR = 0) IR bit in VCMP1IC register (IRQ1SEL = 1) 0 LVCOUT1 output (CM1POR = 0) 0 IR bit in VCMP1IC register (IRQ1SEL = 1) Set to 0 when an interrupt request is acknowledged or by a program. IR bit in VCMP1IC register (IRQ1SEL = 1) 0 LVCOUT1 output (CM1POR = 1) 0 Set to 0 when an interrupt request is acknowledged or by a program. The above applies under when:

• VCA26 bit in VCA2 register = 1 (comparator A1 circuit enabled)
• VW1C0 bit in VW1C register = 1 (comparator A1 interrupt enabled)
• CM1OE bit in CMPA register = 1 (output enabled)
• VCA22 bit in VCA2 register = 1 (LVCMP1 pin input voltage)
• COMPSEL bit in CMPA register = 1 (bits IRQ1SEL and IRQ2SEL enabled) VW1C1, VW1C2, VW1C3, VW1C7: Bits in VW1C register VCAC1: Bit in VCAC register CM1POR, IRQ1SEL: Bits in CMPA register Reference voltage (LVREF) LVCMP1 Set to 0 when an interrupt request is acknowledged or by a program.

R8C/32A Group 28. Comparator A REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 467 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

28.4.2 Comparator A2

Table 28.4 lists the Procedure for Setting Bits Asso ciated Comparator A2 Interrupt, Figure 28.4 shows a Comparator A2 Operating Example (Dig ital Filter Enabled), and Figure 28.5 shows a Comparator 2 Operating Example (Digital Filter Disabled). Note: 1. When the VW2C0 bit is set to 0, steps 6 an d 7 can be executed at the same time (with one instruction). Table 28.4 Procedure for Setting Bits Associated Comparator A2 Interrupt Step When Using Digital Filter When Using No Digital Filter 1 Set the COMPSEL bit in the CMPA register to 1 (bits IRQ1SEL and IRQ2SEL enabled).

2 Set the VCA23 bit in the VCA2 register to 1 (LVREF pin input voltage) and

the VCA24 bit to 1 (LVCMP2 pin input voltage). 3 Set the VCA27 bit in the VCA2 register to 1 (comparator A2 circuit enabled). 4 Wait for td(E-A). 5 Select the interrupt type by the IR Q2SEL bit in the CMPA register. bits VW2F0 and VW2F1 in the VW2C register. Set the VW2C1 bit in the VW2C register to 1 (digital filter disabled). (1) Set the VW2C1 bit in the VW2C register to 0 (digital filter enabled).

8 Select the interrupt request timing by the VCAC2 bit in the VCAC register and

the VW2C7 bit in the VW2C register. 9 Set the VW2C2 bit in the VW2C register to 0.

10 Set the CM14 bit in the CM1 register to 0 (low-

speed on-chip oscillator on). the digital filter. − (No wait time required) 12 Set the VW2C0 bit in the VW2C register to 1 (comparator A2 interrupt enabled).

R8C/32A Group 28. Comparator A REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 468 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 28.4 Comparator A2 Operating Example (Digital Filter Enabled) Reference voltage (LVREF) VCA13 bit LVCOUT2 output (CM2POR = 0) LVCMP2 The above applies when:

• VCA27 bit in VCA2 register = 1 (comparator A2 circuit enabled)
• VW2C0 bit in VW2C register = 1 (comparator A2 interrupt enabled)
• CM2OE bit in CMPA register = 1 (output enabled)
• VCA24 bit in VCA2 register = 1 (LVCMP2 pin input voltage)
• COMPSEL bit in CMPA register = 1 (bits IRQ1SEL and IRQ2SEL enabled) Sampling clock of digital filter × 2 cycles VW2C2 bit VCA13: Bit in VCA1 register VW2C1, VW2C2, VW2C7: Bits in VW2C register VCAC2: Bit in VCAC register CM2POR, IRQ2SEL: Bits in CMPA register Sampling clock of digital filter × 2 cycles IR bit in VCMP2IC register (IRQ2SEL = 1) VW2C1 bit is set to 0 (digital filter enabled) and VCAC2 bit is set to 1 (both edges) VW2C2 bit VW2C1 bit is set to 0 (digital filter enabled), VCAC2 bit is set to 0 (one edge), and VW2C7 bit is set to 0 (when LVCMP2 reaches reference voltage or above) VW2C2 bit VW2C1 bit is set to 0 (digital filter enabled), VCAC2 bit is set to 0 (one edge), and VW2C7 bit is set to 1 (when LVCMP2 reaches reference voltage or below) IR bit in VCMP2IC register (IRQ2SEL = 1) 0 LVCOUT2 output (CM2POR = 0) 0 IR bit in VCMP2IC register (IRQ2SEL = 1) 0 LVCOUT2 output (CM2POR = 1) 0 Set to 0 when an interrupt request is acknowledged or by a program. Set to 0 by a program. Set to 0 by a program. Set to 0 by a program. Set to 0 when an interrupt request is acknowledged or by a program. Set to 0 when an interrupt request is acknowledged or by a program.

R8C/32A Group 28. Comparator A REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 469 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 28.5 Comparator 2 Operating Example (Digital Filter Disabled) VCA13 bit VW2C2 bit VW2C1 bit is set to 1 (digital filter disabled), VCAC2 bit is set to 0 (one edge), and VW2C7 bit is set to 0 (when LVCMP2 reaches reference voltage or above) VW2C2 bit VW2C2 bit VW2C1 bit is set to 1 (digital filter disabled) and VCAC2 bit is set to 1 (both edges) Set to 0 by a program. Set to 0 by a program. Set to 0 by a program. VW2C1 bit is set to 1 (digital filter disabled), VCAC2 bit is set to 0 (one edge), and VW2C7 bit is set to 1 (when LVCMP2 reaches reference voltage or below) LVCOUT2 output (CM2POR = 0) IR bit in VCMP2IC register (IRQ2SEL = 1) 0 LVCOUT2 output (CM2POR = 0) 0 IR bit in VCMP2IC register (IRQ2SEL = 1) Set to 0 when an interrupt request is acknowledged or by a program. IR bit in VCMP2IC register (IRQ2SEL = 1) 0 LVCOUT2 output (CM2POR = 1) 0 Set to 0 when an interrupt request is acknowledged or by a program. Reference voltage (LVREF) VCMP2 Set to 0 when an interrupt request is acknowledged or by a program. The above applies when:

• VCA27 bit in VCA2 register = 1 (comparator A2 circuit enabled)
• VW2C0 bit in VW2C register = 1 (comparator A2 interrupt enabled)
• CM2OE bit in CMPA register = 1 (output enabled)
• VCA24 bit in VCA2 register = 1 (LVCMP2 pin input voltage)
• COMPSEL bit in CMPA register = 1 (bits IRQ1SEL and IRQ2SEL enabled) VCA13: Bit in VCA1 register VW2C1, VW2C2, VW2C7: Bits in VW2C register VCAC2: Bit in VCAC register CM2POR, IRQ2SEL: Bits in CMPA register

R8C/32A Group 28. Comparator A REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 470 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

28.5 Comparator A1 and Comparator A2 Interrupts

Comparator A generates an interrupt request from two sources, comparator A1 and comparator A2. Non-maskable or maskable can be selected for each interrupt type. Refer to 11. Interrupts for details of interrupts.

28.5.1 Non-Maskable Interrupts

When the COMPSEL bit in the CMPA register is se t to 1 (bits IRQ1SEL and IRQ2SEL enabled) and the IRQiSEL (i = 1 or 2) is set to 0, the comparator Ai interrupt functions as a non-maskable interrupt. When the selected interrupt request timing occurs, the VWiC2 bit in the VWiC register is set to 1. At this time, a non-maskable interrupt request for comparator Ai is generated.

28.5.2 Maskable Interrupts

When the COMPSEL bit in the CMPA register is se t to 1 (bits IRQ1SEL and IRQ2SEL enabled) and the IRQiSEL (i = 1 or 2) is set to 1, the comparator Ai interrupt functions as a maskable interrupt. The comparator Ai in terrupt uses the corresponding VCMPiIC regi ster (bits IR and ILVL0 to ILVL2) and a single vector. When the selected interrupt request timing occurs, the VWiC2 bit in the VWiC register is set to 1. At this time, the IR bit in the VCMPiIC register is set to 1 (interrupt requested). Refer to 11.3 Interrupt Control for the VCMPiIC register and 11.1.5.2 Relocatable Vector Tables for interrupt vectors.

R8C/32A Group 29. Comparator B REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 471 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 29. Comparator B Comparator B compares a reference input voltage and an analog input voltage. Comparator B1 and comparator B3 are independent of each other.

29.1 Overview

The comparison result of the reference input voltage and analog input voltage can be read by software. An input to the IVREFi (i = 1 or 3) pin can be used as the reference input voltage. Table 29.1 lists the Comparat or B Specifications, Figure 29.1 shows a Comparator B Block Diagram, and Table 29.2 lists the I/O Pins. i = 1 or 3 Figure 29.1 Comparator B Block Diagram Table 29.1 Comparator B Specifications Item Specification Analog input voltage Input voltage to the IVCMPi pin Reference input voltage Input voltage to the IVREFi pin Comparison result Read from the INTiCOUT bit in the INTCMP register Interrupt request generation timing When the comparison result changes. Selectable functions • Dig ital filter function Whether the digital filter is applied or not and the sampling frequency can be selected. INT3F1 to INT3F0 = 01b = 10b = 11b INT1CP0, INT1COUT, INT3CP0, INT3COUT: Bits in INTCMP register INT1EN, INT1PL, INT3EN, INT3PL: Bits in INTEN register INT1F0, INT1F1, INT3F0, INT3F1: Bits in INTF register f32 Digital filter (3 times match) INT3CP0 = 0 Sampling clock INT3COUT INT3 Port direction register IVCMP3 IVREF3 INT3CP0 = 1 = other than 00b INT3F1 to INT3F0 = 00b INT3PL = 0 INT3PL = 1 Both edge detection circuit To INT3 interruptINT3EN Digital filter (3 times match) INT1CP0 = 1 INT1CP0 = 0 = other than 00b INT1F1 to INT1F0 = 00b INT1PL = 0 INT1PL = 1 Both edge detection circuit To INT1 interruptINT1EN INT1F1 to INT1F0 =01b =10b =11b f32 Sampling clock INT1COUT INT1 Port direction register IVCMP1 IVREF1

R8C/32A Group 29. Comparator B REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 472 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Table 29.2 I/O Pins Pin Name I/O Function IVCMP1 Input Comparator B1 analog pin IVREF1 Input Comparator B1 reference voltage pin IVCMP3 Input Comparator B3 analog pin IVREF3 Input Comparator B3 reference voltage pin

R8C/32A Group 29. Comparator B REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 473 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

29.2 Registers

29.2.1 Comparator B Cont rol Register (INTCMP)

29.2.2 External Input Enab le Register 0 (INTEN)

Notes: 1. To set the INTiPL bit (i = 0, 1, 3) to 1 (both edges), set the POL bit in the INTiIC register to 0 (falling edge selected). 2. The IR bit in the INTiIC register may be set to 1 (interrupt requested) if the INTiPL bit is rewritten. Refer to 11.8.4 Changing Interrupt Sources. Address 01F8h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol INT3COUT — — INT3CP0 INT1COUT — — INT1CP0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 INT1CP0 Comparator B1 operation enable bit 0: Comparator B1 operation disabled 1: Comparator B1 operation enabled R/W b1 — Reserved bits Set to 0. R/W b2 — b3 INT1COUT Comparator B1 monitor flag 0: IVCMP1 < IVREF1 or comparator B1 operation disabled 1: IVCMP1 > IVREF1 R b4 INT3CP0 Comparator B3 operation enable bit 0: Comparator B3 operation disabled 1: Comparator B3 operation enabled R/W b5 — Reserved bits Set to 0. R/W b6 — b7 INT3COUT Comparator B3 monitor flag 0: IVCMP3 < IVREF3 or comparator B3 operation disabled 1: IVCMP3 > IVREF3 R Address 01FAh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol INT3PL INT3EN — — INT1PL INT1EN INT0PL INT0EN A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 INT0EN INT0 input enable bit 0: Disabled 1: Enabled R/W b1 INT0PL INT0 input polarity select bit (1, 2) 0: One edge 1: Both edges R/W b2 INT1EN INT1 input enable bit 0: Disabled 1: Enabled R/W b3 INT1PL INT1 input polarity select bit (1, 2) 0: One edge 1: Both edges R/W b4 — Reserved bits Set to 0. R/W b5 — b6 INT3EN INT3 input enable bit 0: Disabled 1: Enabled R/W b7 INT3PL INT3 input polarity select bit (1, 2) 0: One edge 1: Both edges R/W

R8C/32A Group 29. Comparator B REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 474 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

29.2.3 INT Input Filter Se lect Register 0 (INTF)

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol INT3F1 INT3F0 — — INT1F1 INT1F0 INT0F1 INT0F0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 INT0F0 INT0 input filter select bit b1 b0 0 0: No filter 0 1: Filter with f1 sampling 1 0: Filter with f8 sampling 1 1: Filter with f32 sampling R/W b1 INT0F1 R/W b2 INT1F0 INT1 input filter select bit b3 b2 0 0: No filter 0 1: Filter with f1 sampling 1 0: Filter with f8 sampling 1 1: Filter with f32 sampling R/W b3 INT1F1 R/W b4 — Reserved bits Set to 0. R/W b5 — b6 INT3F0 INT3 input filter select bit b7 b6 0 0: No filter 0 1: Filter with f1 sampling 1 0: Filter with f8 sampling 1 1: Filter with f32 sampling R/W b7 INT3F1 R/W

R8C/32A Group 29. Comparator B REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 475 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

29.3 Functional Description

Comparator B1 and comparator B3 operate independently. Their operations are the same. Table 29.3 lists the Procedure for Setting Registers Associated with Comparator B. i = 1 or 3 Figure 29.2 shows an Operating Example of Comparator Bi (i = 1 or 3). If the analog input voltage is higher than the reference input voltage, the INTiCOUT bit in the INTCMP register is set to 1. If the analog input voltage is lower than the reference input voltage, the INTiCOUT bit is set to 0. To use the comparator Bi interrupt, set the INTiEN bit in the INTEN register to 1 (i nterrupt enabled). If the comparison result changes at this time, a comparat or Bi interrupt request is generated. Refer to 29.4 Comparator B1 and Comparator B3 Interrupts for details of interrupts. Figure 29.2 Operating Example of Comparator Bi (i = 1 or 3) Table 29.3 Procedure for Setting Registers Associated with Comparator B Step Register Bit Setting Value 1 Select the function of pins IVCMPi and IVREFi. Refer to 7.5 Port Settings. However, set registers and bits other than listed in step 2 and the following steps. 2 INTF Select whether to enable or disable the filter. Select the sampling clock.

3 INTCMP INTiCP0 1 (operation enabled)

4 Wait for comparator stability time (TBD µs max.)

5 INTEN INTiEN When using an interrupt: 1 (interrupt enabled)

INTiPL When using an interrupt: Select the input polarity. 6 INTiIC ILVL2 to ILVL0 When using an interr upt: Select the interrupt priority level. IR When using an interrupt: 0 (no in terrupt requested: initialization) INTiCOUT bit in INTCMP register The above applies when: Bits INTiF1 to INTiF0 in INTF register = 00b (no filter) INTiPL bit in the INTEN register = 0 (both edges) i = 1 or 3 Reference input voltage IR bit in INTiIC register Set to 0 by a program. Analog input voltage (V)

R8C/32A Group 29. Comparator B REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 476 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

29.3.1 Comparator Bi Digita l Filter (i = 1 or 3)

Comparator Bi can use the same digital filter as th e INTi input. The sampling cl ock can be selected by bits INTiF1 and INTiF0 in the INTF register. The INTiCO UT signal output from comparator Bi is sampled every sampling clock. When the level matches three times, the IR bit in the INTiIC register is set to 1 (interrupt requested). Figure 29.3 shows a Configuration of Comparator Bi Digital Filter, and Figure 29.4 shows an Operating Example of Comparator Bi Digital Filter. Figure 29.3 Configuration of Comparator Bi Digital Filter Figure 29.4 Operating Example of Comparator Bi Digital Filter = 01b INTi Port direction register Sampling clock To INTi interrupt = 10b = 11bf32 INTiF1 to INTiF0 INTiEN INTiF1 to INTiF0 = other than 00b = 00b INTiCP0, INTiCOUT: Bits in INTCMP register INTiF0 to INTiF1: Bits in INTF register INTiEN, INTiPL: Bits in INTEN register INTiPL = 0 INTiPL = 1 i = 1 or 3 INTiCOUT IVCMPi IVREFi INTiCP0 = 0 INTiCP0 = 1 Digital filter (match 3 times) Both edge detection circuit INTiCOUT signal Sampling timing IR bit in INTiIC register Set to 0 by a program. Note: The above applies when: Bits INTiF1 to INTiF0 in the INTiF register are set to 01b, 10b, or 11b (digital filter used). i =1 or 3

R8C/32A Group 29. Comparator B REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 477 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

29.4 Comparator B1 and Comparator B3 Interrupts

Comparator B generates an interrupt request from tw o sources, comparator B1 and comparator B3. The comparator Bi (i = 1 or 3) interrupt uses the same INTi IC register (bits IR and ILVL0 to ILVL2) as the INTi (i = 1 or 3) and a single vector. To use the comparator Bi interrupt, set the INTiEN bi t in the INTEN register to 1 (interrupt enabled). In addition, the polarity can be selected by the INTiPL bit in the INTE N register and the POL bit in the INTiIC register. Inputs can also be passed through the digital filter with three different sampling clocks.

R8C/32A Group 30. Flash Memory REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 478 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 30. Flash Memory The flash memory can perform in the following three rewrite modes: CPU rewrite mode, standard serial I/O mode, and parallel I/O mode.

30.1 Overview

Table 30.1 lists the Flash Memory Version Performance. (Refer to Table 1.1 and Table 1.2 R8C/32A Group Specifications for items not listed in Table 30.1.) Notes: 1. To perform programming and erasure, use VCC = 2.7 V to 5.5 V as the supply voltage. Do not perform programming and erasure at less than 2.7 V. 2. Definition of programming and erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 100 or 10,000), each block can be eras ed n times. For example, if 1,024 1-byte writes are performed to block A, a 1-Kbyte block, and then th e block is erased, the eras e count stands at one. When performing 100 or more rewrites, the actual erase count can be reduced by executing program operations in such a way that all blank areas are used before performing an erase operation. Avoid rewriting only particular blocks and try to average out the programming and eras ure endurance of the blocks. It is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. Table 30.1 Flash Memory Version Performance Item Specification Flash memory operating mode 3 modes (CPU rewrite, standard serial I/O, and parallel I/O) Division of erase blocks Refer to Figure 30.1. Programming method Byte units Erasure method Block erase Programming and erasure control method (1) Program and erase control by software commands Rewrite control method Blocks 0 to 2 (Program ROM) Rewrite protect control in block units by the lock bit Blocks A, B, C, and D (Data flash) Individual rewrite protect control on blocks A, B, C, and D by bits FMR14, FMR15, FMR16, and FMR17 in the FMR1 register Number of commands 8 commands Programming and erasure endurance (2) Blocks 0 to 2 (Program ROM) 1,000 times Blocks A, B, C, and D (Data flash) 10,000 times ID code check function Standard serial I/O mode supported ROM code protection Parallel I/O mode supported Table 30.2 Flash Memory Rewrite Mode Flash Memory Rewrite Mode CPU Rewrite Mode Standard Serial I/O Mode Parallel I/O Mode Function User ROM area is rewritten by executing software commands from the CPU. User ROM area is rewritten using a dedicated serial programmer. User ROM area is rewritten using a dedicated parallel programmer. Rewritable area User ROM User ROM User ROM Rewrite programs User program Standard boot program –

R8C/32A Group 30. Flash Memory REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 479 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

30.2 Memory Map

The flash memory contains a user ROM area and a boot ROM area (reserved area). Figure 30.1 show the R8C/32A Group Flash Memory Block Diagrams. The user ROM area contains program ROM and data flash. Program ROM: Flash memory mainly used for storing programs Data flash: Flash memory mainly used for storing data to be rewritten The user ROM area is divided into several blocks. The user ROM area can be rewritten in CPU rewrite mode, standard serial I/O mode, or parallel I/O mode. The rewrite control program (standard boot program) for st andard serial I/O mode is stored in the boot ROM area before shipment. The boot ROM area is allocated separately from the user ROM area. Figure 30.1 R8C/32A Group Flash Memory Block Diagram Program ROM Data flash User ROM area 0F7FFh 03000h 03FFFh ROM 8 KB product Block B: 1 Kbyte Block A: 1 Kbyte Block C: 1 Kbyte Block D: 1 Kbyte Block 2: 4 Kbytes Block 0: 2 Kbytes User ROM area 03000h 03FFFh ROM 4 KB product Block B: 1 Kbyte Block A: 1 Kbyte Block C: 1 Kbyte Block D: 1 Kbyte 0E000h0EFFFh 0F000h Block 1: 2 Kbytes 0F800h 0FFFFh 0F7FFh Block 0: 2 Kbytes 0F000h Block 1: 2 Kbytes 0F800h 0FFFFh 03FFFh User ROM area 0C000h 0FFFFh 03000h ROM 16 KB product Block B: 1 Kbyte Block A: 1 Kbyte Block C: 1 Kbyte Block D: 1 Kbyte Block 2: 8 Kbytes Block 1: 4 Kbytes Block 0: 4 Kbytes 0E000h 0F000h

R8C/32A Group 30. Flash Memory REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 480 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

30.3 Functions to Prevent Flash Me mory from being Rewritten

Standard serial I/O mode has an ID code check function, and parallel I/O mode has a ROM code protect function to prevent the flash memory from being read or rewritten easily.

30.3.1 ID Code Check Function

The ID code check function is used in standard serial I/O mode. Unless 3 bytes (addresses 0FFFCh to 0FFFEh) of the reset vector are set to FFFF FFh, the ID codes sent from the seri al programmer or the on-chip debugging emulator and the 7-byte ID codes written in the flash memo ry are checked to see if they match. If the ID codes do not match, the commands sent from the serial pr ogrammer or the on-chip debugging emulator are not accepted. For details of the ID code check function, refer to 12. ID Code Areas.

R8C/32A Group 30. Flash Memory REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 481 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

30.3.2 ROM Code Protect Function

The ROM protect function prevents the contents of th e flash memory from being read, rewritten, or erased using the OFS register in parallel I/O mode. Refer to 13. Option Function Select Area for details of the OFS register. The ROM code protect function is enabled by writing 1 to the ROMCR bit and writing 0 to the ROMCP1 bit. This prevents the contents of the on-chip flash memory from being read or rewritten. Once ROM code protection is enabled, the content of the internal flash memory cannot be rewritten in parallel I/O mode. To disable ROM code protection, erase th e block including the OFS register using CPU rewrite mode or standard serial I/O mode.

30.3.3 Option Function Se lect Register (OFS)

Notes: 1. If the block including the OFS register is erased, the OFS register value is set to FFh. 2. The same level of the voltage detection 0 level selected by bits VDSEL0 and VDESL1 is set in both functions of voltage monitor 0 reset and power-on reset. 3. To use power-on reset, set the LVDAS bit to 0 (voltage monitor 0 reset enabled after reset). The OFS register is allocated in the flash memory. Write to this register with a program. After writing, do not write additions to this register. LVDAS Bit (Voltage Detection 0 Circuit Start Bit) The Vdet0 voltage to be monitored by the voltage detection 0 circuit is selected by bits VDSEL0 and VDSEL1. Address 0FFFFh B i t b 7 b 6b 5b 4b 3b 2b 1b 0 Symbol CSPROINI LVDAS VDSEL1 VDSEL0 ROMCP1 ROMCR — WDTON W h e n s h i p p i n g 1 1111111 ( N o t e 1 ) Bit Symbol Bit Name Function R/W b0 WDTON Watchdog timer start select bit 0: Watchdog timer automatically starts after reset. 1: Watchdog timer is stopped after reset. R/W b1 — Reserved bit Set to 1. R/W b2 ROMCR ROM code protect disable bit 0: ROM code protect disabled 1: ROMCP1 bit enabled R/W b3 ROMCP1 ROM code protect bit 0: ROM code protect enabled 1: ROM code protect disabled R/W b4 VDSEL0 Voltage detection 0 level select bit (2) b5 b4 0 0: 3.80 V selected (Vdet0_3) 0 1: 2.85 V selected (Vdet0_2) 1 0: 2.35 V selected (Vdet0_1) 1 1: 1.90 V selected (Vdet0_0) R/W b5 VDSEL1 R/W b6 LVDAS Voltage detection 0 circuit start bit (3) 0: Voltage monitor 0 reset enabled after reset 1: Voltage monitor 0 reset disabled after reset R/W b7 CSPROINI Count source protection mode after reset select bit 0: Count source protect mode enabled after reset 1: Count source protect mode disabled after reset R/W

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30.4 CPU Rewrite Mode

In CPU rewrite mode, the user ROM area can be rewr itten by executing software commands from the CPU. Therefore, the user ROM area can be rewritten directly while the MCU is mounted on a board without using a ROM programmer. Execute the software command only to blocks in the user ROM area. The flash module has an erase-suspend function which halts the erase operation te mporarily during an erase operation in CPU rewrite mode. During erase-suspend, the user ROM area can be read by a program. Erase-write 0 mode (EW0 mode) and erase-write 1 mode (EW1 mode) are available in CPU rewrite mode. Table 30.3 lists the Differences between EW0 Mode and EW1 Mode. Table 30.3 Differences between EW0 Mode and EW1 Mode Item EW0 Mode EW1 Mode Operating mode Single-chip mode Single-chip mode Rewrite control program allocatable area User ROM User ROM Rewrite control program executable areas RAM (The rewrite control program must be transferred before being executed.) However, the program can be executed in the program ROM area when rewriting the data flash area. User ROM or RAM Rewritable area User ROM User ROM However, blocks which contain the rewrite control program are excluded. Software command restrictions Read status register command cannot be executed.

• Program and block erase commands cannot be executed to any block which contains the rewrite control program.
• Read status register command cannot be executed. Mode after program or block erase Read array mode Read array mode CPU state during programming and block erasure The CPU operates. • The CPU operates while the data flash area is being programmed or block erased.
• The CPU is put in a hold state while the program ROM area is being programmed or block erased. (I/O ports retain the state before the command execution). Flash memory status detection Read bits FST7, FMT5, and FMT4 in the FST register by a program. Read bits FST7, FMT5, and FMT4 in the FST register by a program. Conditions for entering program-suspend
• Set bits FMR20 and FMR21 in the FMR2 register to 1 by a program.
• Set bits FMR20 and FMR22 in the FMR2 register to 1 and the enabled maskable interrupt is generated.
• Set bits FMR20 and FMR21 in the FMR2 register to 1 by a program (while rewriting the data flash area).
• Set bits FMR20 and FMR22 in the FMR2 register to 1 and the enabled maskable interrupt is generated. CPU clock 20 MHz 20 MHz

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30.4.1 Flash Memory Status Register (FST)

Notes: 1. The RDYSTI bit cannot be set to 1 (flash ready status interrupt request) by a program. In parallel I/O mode, this bit is fixed to 0 (no flash ready status interrupt request). 2. The BSYAEI bit cannot be set to 1 (flash access error interrupt request) by a program. In parallel I/O mode, this bit is fixed to 0 (no flash access error interrupt request). 3. This bit is also set to 1 (e rror) when a command error occurs. RDYSTI Bit (Flash Ready Status Flag Interrupt Request Flag) When the RDYSTIE bit in the FMR0 register is set to 1 (flash ready status interrupt enabled) and auto- programming or auto-erasure completes, or erase-suspe nd mode is entered, the RDYSTI bit is set to 1 (flash ready status interrupt request). During interrupt handling, set the RDYSTI bit to 0 (no flash ready status interrupt request). [Condition for setting to 0] Set to 0 by an interrupt handling program. [Condition for setting to 1] When the flash memory status changes from busy to ready while the RDYSTIE bit in the FRMR0 register is set to 1, the RDYSTI bit is set to 1. The status is changed from busy to ready by the following operations: erasing/writing to the flash memory, suspend acknowledgement, forcible termination, completion of the lock bit program, and completion of the read lock bit status. Address 01B2h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol FST7 FST6 FST5 FST4 — LBDATA BSYAEI RDYSTI A f t e r R e s e t 10000X00 Bit Symbol Bit Name Function R/W b0 RDYSTI Flash ready status interrupt request flag (1) 0: No flash ready status interrupt request 1: Flash ready status interrupt request R/W b1 BSYAEI Flash access error interrupt request flag (2) 0: No flash access error interrupt request 1: Flash access error interrupt request R/W b2 LBDATA LBDATA monitor flag 0: Locked 1: Not locked R b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b4 FST4 Program error status flag (3) 0: No program error 1: Program error R b5 FST5 Erase error status flag (3) 0: No erase error 1: Erase error R b6 FST6 Erase-suspend status flag 0: Other than erase-suspend 1: During erase-suspend R b7 FST7 Ready/busy status flag 0: Busy 1: Ready R

R8C/32A Group 30. Flash Memory REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 484 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. BYSAEI Bit (Flash Access Error Interrupt Request Flag) The BYSAEI bit is set to 1 (flash access error interrupt request) when the BSYAEIE bit in the FMR0 register is set to 1 (flash access error interrupt enabled) and th e block during auto-programming/auto-erasure is accessed. This bit is also set to 1 if an erase or program error occurs when the CMDERIE bit in the FMR0 register is set to 1 (erase/write error interrupt enabled). During interrupt handling, set the BSYAEI bit to 0 (no flash access error interrupt request). [Conditions for setting to 0] (1) Set to 0 by an interrupt handling program. (2) Execute the status clear instruction. [Conditions for setting to 1] (1) Read or write the area that is bei ng erased/written when the BSYAEIE bit in the FRMR0 register is set to 1 and while the flash memory is busy. Or, read the data flash area while erasing/writing to the program ROM area. (Note that the read value is undefined in both cases. Writing has no effect.) (2) If an erase or program error occurs when the CMDERI E bit in the FMR0 register is set to 1 (erase/write error interrupt enabled). LBDATA Bit (LBDATA Monitor Flag) This is a read-only bit indicating the lock bit status. To confirm the lock bit status, execute the read lock bit status command and read the LBDATA bit after the FST7 bit is set to 1 (ready). The condition for updating this bit is when the program, erase, read lock bit status commands are generated. When the read lock bit status command is input, the FST7 bit is set to 0 (busy). At the time when the FST7 bit is set to 1 (ready), the lock bit status is stored in the LBDATA bit. The data in the LBDATA bit is retained until the next command is input. FST4 Bit (Program Error Status Flag) This is a read-only bit indicating the auto-programming status. The bit is set to 1 if a program error occurs; otherwise, it is set to 0. For details, refer to the description in 30.4.17 Full Status Check. FST5 Bit (Erase Error Status Flag) This is a read-only bit indicating the status of auto-pr ogramming or the blank check command. The bit is set to 1 if an erase error or blank check error occu rs; otherwise, it is set to 0. Refer to 30.4.17 Full Status Check for details. FST6 Bit (Erase Suspend Status Flag) This is a read-only bit indicating th e suspend status. The bit is set to 1 when an erase-suspend request is acknowledged and a suspend status is entered; otherwise, it is set to 0. FST7 Bit (Ready/Busy Status Flag) This is a read-only bit indicating the operating status of the flash memory. The bit is set to 0 during program and erase operations; otherwise, it is set to 1.

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30.4.2 Flash Memory Cont rol Register 0 (FMR0)

Notes: 1. To set this bit to 1, first write 0 and then 1 immediately. Do not generate an interrupt between writing 0 and writing 1. 2. Write to the FMSTP bit by a program transferred to the RAM. The FMSTP bit is enabled when the FMR01 bit is set to 1 (CPU rewrite mode enabled). To set the FMSTP bit to 1 (flash memory stops), set it when the FST7 bit in the FST register is set to 1 (ready). 3. The CMDRST bit is enabled when the FMR01 bit is set to 1 (CPU rewrite mode enabled) and the FST7 bit in the FST register is set to 0 (busy). FMR01 Bit (CPU Rewrite Mode Select Bit) When the FMR01 bit is set to 1 (CPU rewrite mode enabled), the MCU is made ready to accept software commands. FMR02 Bit (EW1 Mode Select Bit) When the FMR02 bit is set to 1 (EW1 mode), EW1 mode is selected. Address 01B4h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol RDYSTIE BSYAEIE CMDERIE CMDRST FMSTP FMR02 FMR01 — A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 — Reserved bit Set to 0. R/W b1 FMR01 CPU rewrite mode select bit (1) 0: CPU rewrite mode disabled 1: CPU rewrite mode enabled R/W b2 FMR02 EW1 mode select bit (1) 0: EW0 mode 1: EW1 mode R/W b3 FMSTP Flash memory stop bit (2) 0: Flash memory operates 1: Flash memory stops (Low-power consumption state, flash memory initialization) R/W b4 CMDRST Erase/write sequence reset bit (3) When the CMDRST bit is set to 1, the erase/write sequence is reset and erasure/writing can be forcibly stopped. When read, the content is 0. R/W b5 CMDERIE Erase/write error interrupt enable bit 0: Erase/write error interrupt disabled 1: Erase/write error interrupt enabled R/W b6 BSYAEIE Flash access error interrupt enable bi t 0: Flash access error interrupt disabled 1: Flash access error interrupt enabled R/W b7 RDYSTIE Flash ready status interrupt enable bit 0: Flash ready status interrupt disabled 1: Flash ready status interrupt enabled R/W

R8C/32A Group 30. Flash Memory REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 486 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. FMSTP Bit (Flash Memory Stop Bit) This bit is used to initialize the flash memory contro l circuits, and also to reduce the amount of current consumed by the flash memory. Access to the flash memory is disabled by setting the FMSTP bit to 1. Write to the FMSTP bit by a program transferred to the RAM. To reduce the power consumption further in high-speed on-chip oscillator mode, lo w-speed on-chip oscillator mode (XIN clock stopped), and low-speed clock mode (X IN clock stopped), set the FMSTP bit to 1. Refer to 31.2.10 Stopping Flash Memory for details. When entering stop mode or wait mode while CPU rewr ite mode is disabled, the FMR0 register does not need to be set because the power for the flash memory is automatically turned off and is turned back on when exiting stop or wait mode. CMDRST Bit (Erase/Write Sequence Reset Bit) This bit is used to initialize the flash memory sequence and forcibly stop a program or erase command. The user ROM area can be read while the flash memory sequence is being initialized. For addresses and blocks which the program or eras e command is forcibly stopped by the CMDRST bit, execute a block erasure again and ensure it completes normally. The time from when the command is forcibly stopped and until reading is enabled is some hundreds µs where the suspend response time is 10 ms. CMDERIE Bit (Erase/Write Interrupt Enable Bit) This bit enables an flash command error interrupt to be generated if a program or block erase error occurs. If the CMDERIE bit is set to 1 (erase/write error interrupt enabled) and erasur e/writing is performed, an interrupt is generated if an erase or program error occurs. If a flash command error interrupt is generated, exec ute the clear status register command during interrupt handling. BSYAEIE Bit (Flash Access Error Interrupt Enable Bit) This bit enables a flash access error interrupt to be generated if the flash memory during rewriting is accessed. RDYSTIE Bit (Flash Ready Status Interrupt Enable Bit) This bit enables a flash ready status error interrupt to be generated wh en the status of the flash memory sequence changes from the busy to ready status.

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30.4.3 Flash Memory Cont rol Register 1 (FMR1)

Notes: 1. To set the FMR13 bit to 1, first write 0 and then 1 immediately. Do not generate an interrupt between writing 0 and writing 1. 2. To set this bit to 0, first write 1 and then 0 immediately. Do not generate an interrupt between writing 1 and writing 0. FMR13 Bit (Lock Bit Disable Select Bit) When the FMR13 bit is set to 1 (lock bit disabled), the lock bit is disabled. When the FMR13 bit is set to 0, the lock bit is enabled. Refer to 30.4.10 Data Protect Function for the details of the lock bit. The FMR13 bit enables the lock bit function only and the lock bit data does not change. However, when a block erase command is executed while the FMR13 bit is set to 1, the lock bit data set to 0 (locked) changes to 1 (not locked) after erasure completes. [Conditions for setting to 0] The FMR13 bit is set to 0 when one of the following conditions is met.

• Completion of the program command
• Completion of the erase command
• Generation of a command error
• If the FMR01 bit in the FMR0 register is set to 0 (CPU rewrite mode disabled).
• If the FMSTP bit in the FMR0 register is set to 1 (flash memory stops).
• If the CMDRST bit in the FMR0 register is set to 1 (erasure/writing stopped). [Condition for setting to 1] Set to 1 by a program. Address 01B5h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol FMR17 FMR16 FMR15 FMR14 FMR13 FMR12 FMR11 FMR10 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 FMR10 Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b1 FMR11 — b2 FMR12 — b3 FMR13 Lock bit disable select bit (1) 0: Lock bit enabled 1: Lock bit disabled R/W b4 FMR14 Data flash block A rewrite disable bit (2) 0: Rewrite enabled (software command acceptable) 1: Rewrite disabled (software command not acceptable, no error occurred) R/W b5 FMR15 Data flash block B rewrite disable bit (2) 0: Rewrite enabled (software command acceptable) 1: Rewrite disabled (software command not acceptable, no error occurred) R/W b6 FMR16 Data flash block C rewrite disable bit (2) 0: Rewrite enabled (software command acceptable) 1: Rewrite disabled (software command not acceptable, no error occurred) R/W b7 FMR17 Data flash block D rewrite disable bit (2) 0: Rewrite enabled (software command acceptable) 1: Rewrite disabled (software command not acceptable, no error occurred) R/W

R8C/32A Group 30. Flash Memory REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 488 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. FMR14 Bit (Data Flash Block A Rewrite Disable Bit) When the FMR 14 bit is set to 0, data flash block A accepts program and block erase commands. FMR15 Bit (Data Flash Block B Rewrite Disable Bit) When the FMR 15 bit is set to 0, data flash block B accepts program and block erase commands. FMR16 Bit (Data Flash Block C Rewrite Disable Bit) When the FMR 16 bit is set to 0, data flash block C accepts program and block erase commands. FMR17 Bit (Data Flash Block D Rewrite Disable Bit) When the FMR 17 bit is set to 0, data flash block D accepts program and block erase commands.

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30.4.4 Flash Memory Cont rol Register 2 (FMR2)

Note: 1. To set this bit to 1, first write 0 and then 1 immediately. Do not generate an interrupt between writing 0 and writing 1. FMR20 Bit (Erase-Suspend Enable Bit) When the FMR20 bit is set to 1 (enabled), the erase-suspend function is enabled. FMR21 Bit (Erase-Suspend Request Bit) When the FMR21 bit is set to 1, erase-suspend mode is entered. If the FMR22 bit is set to 1 (erase-suspend request enabled by interrupt request), the FMR21 bit is au tomatically set to 1 (erase-suspend request) when an interrupt request for the enabled interrupt is generated, and erase-suspend mode is entered. To restart auto- erasure, set the FMR21 bit to 0 (erase restart). [Condition for setting to 0] Set to 0 by a program. [Conditions for setting to 1]

• When the FMR22 bit is set to 1 (erase-suspend request enabled by interrupt request) at the time an interrupt is generated.
• Set to 1 by a program. FMR22 Bit (Interrupt Request Suspend-Request Enable Bit) When the FMR 22 bit is set to 1 (erase-suspend request enabled by in terrupt request), the FMR21 bit is automatically set to 1 (erase-suspend request) at the time an interrupt request is generated during auto-erasure. Set the FMR22 bit to 1 when using erase-suspend while rewriting the user ROM area in EW1 mode. FMR27 Bit (Low-Power-Current Read Mode Enable Bit) When the FMR 27 bit is set to 1 (low-consumption-curren t read mode enabled) in low-speed clock mode (XIN clock stopped) or low-speed on-chip oscillator mode (XIN clock stopped), power consumption when reading the flash memory can be reduced. Refer to 31.2.11 Low-Current-Consumption Read Mode for details. Address 01B6h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol FMR27 — — — — FMR22 FMR21 FMR20 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 FMR20 Erase-suspend enable bit (1) 0: Erase-suspend disabled 1: Erase-suspend enabled R/W b1 FMR21 Erase-suspend request bit 0: Erase restart 1: Erase-suspend request R/W b2 FMR22 Interrupt request suspend request enable bit (1) 0: Erase-suspend request disabled by interrupt request 1: Erase-suspend request enabled by interrupt request R/W b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b4 — Reserved bits Set to 0. R/W b5 — R/W b6 — R/W b7 FMR27 Low-consumption-current read mode enable bit (1) 0: Low-consumption-current read mode disabled 1: Low-consumption-current read mode enabled R/W

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30.4.5 EW0 Mode

When the FMR01 bit in the FMR0 register is set to 1 (CPU rewrite mode enabled), the MCU enters CPU rewrite mode and software commands can be accepted. At th is time, the FMR02 bit in the FMR0 register is set to 0 so that EW0 mode is selected. Software commands are used to cont rol program and erase operations. The FST register or the status register can be used to confirm whether programming or erasure has completed. To enter erase-suspend during auto-erasure, set the FMR20 bit to 1 (erase-suspend enabled) and the FMR21 bit to 1 (erase-suspend request). Wait for td(SR-SUS) and ensu re that the FST6 bit in the FST register is set to 1 (during erase-suspend) before accessing the flash memory. Auto-erasure can be restarted by setting the FMR21 bit in the FMR2 register to 0 (erase restart).

30.4.6 EW1 Mode

After the FMR01 bit in the FMR0 register is set to 1 (CPU rewrite mode enabled), EW1 mode is selected by setting the FMR02 bit is set to 1. The FST register can be used to confirm whether prog ramming and erasure has completed. Do not execute the read status register command in EW1 mode. To enable the erase-suspend function during auto-erasure, ex ecute the block erase co mmand after setting the FMR20 bit in the FMR2 register to 1 (suspend enabled). To enter erase-suspend while auto-erasing the user ROM area, set the FMR22 bit in the FMR2 register to 1 (erase-suspend request enab led by interrupt request). Also, the interrupt to enter program-suspend must be enabled beforehand. When an interrupt request is generated, the FMR21 bit in the FMR2 register is auto matically set to 1 (erase- suspend request) and auto-erasure suspends after td (SR-SUS). After interrupt handling completes, set the FMR21 bit to 0 (erase restart) to restart auto-erasure.

30.4.7 Suspend Operation

Figure 30.2 shows the Suspend Operation Timing. Figure 30.2 Suspend Operation Timing Data ROM Data read Suspend (readable) Program Erase User ROM User program Command issue User program Set FMR21 bit to 1 Command issue User program Set FMR21 bit to 0 User program User program FMR21 bit in FMR2 register FST7 bit in FST register FST6 bit in FST register RDYSTI bit in FST register Flash ready interrupt handling Suspend (readable) Flash ready interrupt handling User program Flash ready interrupt handling Suspend (readable) Set to 0 by a program. Set to 0 by a program. Set to 0 by a program. td(SR-SUS) 1 is set automatically. Erase 1 is set automatically. 1 is set automatically.

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30.4.8 How to Set and Exit Each Mode

Figure 30.3 shows How to Set and Exit EW0 Mode and Figure 30.4 shows How to Set and Exit EW0 Mode (When Rewriting Data Flash) and EW1 Mode. Figure 30.3 How to Set and Exit EW0 Mode Figure 30.4 How to Set and Exit EW0 Mode (When Rewriting Data Flash) and EW1 Mode Transfer the rewrite mode program that uses CPU rewrite mode to the RAM Jump to the rewrite control program transferred to the RAM (The subsequent process is executed by the rewrite control program in the RAM) After writing 0 to the FMR01 bit, write 1 (CPU rewrite mode enabled) (1) Execute software commands Write 0 (CPU rewrite mode disabled) to the FMR01 bit Jump to the specified address in the flash memory Rewrite control program Note: To set the FMR01 bit to 1, first write 0 and then 1 immediately. Do not generate an interrupt between writing 0 and writing 1. Writing to the FMR01 bit must be performed in the RAM. EW0 Mode Execution Procedure (When Rewriting User ROM) FMR01: Bit in FMR0 register After writing 0 to the FMR01 bit, write 1 (CPU rewrite mode enabled) (1) Execute software commands Write 0 (CPU rewrite mode disabled) to the FMR01 bit Notes: 1. To set the FMR01 bit to 1, first write 0 and then 1 immediately. Do not generate an interrupt between writing 0 and writing 1. 2. Not required when rewriting the data flash in EW0 mode. EW0 Mode Execution Procedure (When Rewriting Data Flash) EW1 Mode Execution Procedure Program in ROM After writing 0 to the FMR02 bit, write 1 (EW1 mode) (2) FMR01, FMR02: Bits in FMR0 register

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30.4.9 BGO (BackGround Operation) Function

When the program ROM area is specified while a program or block erase operation to the data flash, array data can be read. This eliminates the n eed for writing software commands. Access time is the same as for normal read operations. Figure 30.5 shows the BGO Function. Figure 30.5 BGO Function Time Data flash Program ROM Erase/program Read Read Read Read

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30.4.10 Data Protect Function

Each block in the flash memory has a nonvolatile lock bit. The lock bit is enabled by setting the FMR13 bit in the FMR1 register is set to 0 (lock bit enabled). The lock bit can be used to disable (lock) programming or erasing each block. This prevents data from being writ ten or erased inadvertentl y. A block status changes according to the lock bit as follows:

• When the lock bit data is set to 0: locked (the block cannot be programmed or erased)
• When the lock bit data is set to 1: not locked (the block can be programmed and erased) The lock bit data is set to 0 (locked) by executing the lock bit program command and to 1 (not locked) by erasing the block. No commands can be used to set only the lock bit data to 1. The lock bit data can be read using the read lock bit status command. When the FMR13 bit is set to 1 (lock bit disabled), the lock bit function is disabled and all blocks are not locked (each lock bit data remains unchanged). The lock bit function is enabled by setting the FMR13 bit to 0 (the lock bit data is retained). When the block erase command is executed while the FMR13 bit is set to 1, the target block is erased regardless of the lock bit status. The lock bit of the erase target block is set to 1 after auto-erasure completes. Refer to 30.4.11 Software Commands for the details of individual commands. The FMR13 bit is set to 0 after auto-erasure completes. This bit is also set to 0 if one of the following conditions is met. To erase or program a different locked block, set the FMR 13 bit to 1 again and execute the block erase or program command.
• If the FST7 bit in the FST register is changed from 0 (busy) to 1 (ready).
• If an incorrect command is input.
• If the FMR01 bit in the FMR0 register is set to 0 (CPU mode disabled).
• If the FMSTP bit in the FM0 register is set to 1 (flash memory stops). Figure 30.6 shows the FMR13 Bit Operation Timing. Figure 30.6 FMR13 Bit Operation Timing Erase start Erase completion Operation FST7 bit (Ready/busy status flag) 0 is set at the rising edge of the FST7 bit. FMR13 bit (Lock bit disable select bit) Set to 1 by a program. Lock bit enabled Erase FST7: Bit in FST register FMR13: Bit in FMR1 register

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30.4.11 Software Commands

The software commands are described below. Read or write commands and data in 8-bit units. SRD: Status register data WA: Write address WD: Write data BA: Any block address BT: Starting block address ×: Any address in the user ROM area

30.4.11.1 Read Array Command

The read array command is used to read the flash memory. When FFh is written in the first bus cycle, the MCU ente rs read array mode. When the read address is input in the following bus cycles, the content of the specified address can be read in 8-bit units. Since read array mode remains until another command is written, the contents of multiple addresses can be read continuously. In addition, the MCU enters read array mode after a reset.

30.4.11.2 Read Status Register Command

The read status register command is used to read the status register. When 70h is written in the first bus cycle, the status register can be read in the second bus cycle. When reading the status register, read the same address as the address value in the first bus cycle. In CPU rewrite mode, do not execute this command. Read status register mode remains until the next read array command is written.

30.4.11.3 Clear Status Register Command

The clear status register command is used to set the status register to 0. When 50h is written in the first bus cycle, bits FST4 and FST5 in the FST register and bits SR4 and SR5 in the status register are set to 0. If the clear status register is input in read array mode, the MCU enters read array mode after the status register is set to 0. Table 30.4 Software Commands Command First Bus Cycle Second Bus Cycle Mode Address Data Mode Address Data Read array Write × FFh Read status register Write × 70h Read × SRD Clear status register Write × 50h Program Write WA 40h Write WA WD Block erase Write × 20h Write BA D0h Lock bit program Write BT 77h Write BT D0h Read lock bit status Write × 71h Write BT D0h Block blank check Write × 25h Write BA D0h

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30.4.11.4 Program Command

The program command is used to write data to the flash memory in 1-byte units. When 40h is written in the first bus cycle and data is wri tten in the second bus cycle to the write address, auto- programming (data program and verify op eration) starts. Make sure the addr ess value specified in the first bus cycle is the same address as the write address specified in the second bus cycle. The FST7 bit in the FST register can be used to c onfirm whether auto-programming has completed. The FST7 bit is set to 0 during auto-programming and is set to 1 when auto-programming completes. After auto-programming has completed, the auto-program result can be confirmed by the FST4 bit in the FST register (refer to 30.4.17 Full Status Check). Do not write additions to the already programmed addresses. The program command targeting each block in the program ROM can be disabled using the lock bit. The following commands are not accepted under the following conditions:

• Block erase commands targeting data flash block A when the FMR14 bit in the FMR1 register is set to 1 (rewrite disabled).
• Block erase commands targeting data flash block B when the FMR15 bit is set to 1 (rewrite disabled).
• Block erase commands targeting data flash block C when the FMR16 bit is set to 1 (rewrite disabled).
• Block erase commands targeting data flash block D when the FMR17 bit is set to 1 (rewrite disabled). Figure 30.7 shows a Program Flowchart (Flash Ready Status Interrupt Disabled) and Figure 30.8 shows a Program Flowchart (Flash Ready Status Interrupt Enabled). In EW1 mode, do not execute this command to any address where a rewrite control program is allocated. When RDYSTIE bit in the FMR0 register is set to 1 (flash ready status in terrupt enabled), a flash ready status interrupt can be generated upon completion of auto-pro gramming. The auto-program result can be confirmed by reading the FST register during the interrupt routine. Figure 30.7 Program Flowchart (Flash Ready Status Interrupt Disabled) Start Write the command code 40h Write data to the write address FST7 = 1? Full status check Program completed No Yes FST7: Bit in FST register

R8C/32A Group 30. Flash Memory REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 496 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 30.8 Program Flowchart (Flash Ready Status Interrupt Enabled) Start Write the command code 40h Write data to the write address Program completed RDYSTIE = 1 RDYSTI: Bit in FST register RDYSTIE: Bit in FMR0 register I = 1 (interrupt enabled) Flash ready status interrupt REIT Status check RDYSTI = 0

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30.4.11.5 Block Erase Command

When 20h is written in the first bus cycle and then D0h is written in the second bus cycle to any block address, auto-erasure (erase and erase verify operation) starts in the specified block. The FST7 bit in the FST register can be used to confirm whether auto-erasure has completed. The FST7 bit is set to 0 during auto-erasure and is set to 1 when auto-erasure completes. After auto-erasure has completed, the auto-erase result can be confirmed by the FST5 bit in the FST register. (Refer to 30.4.17 Full Status Check). The block erase command targeting each block in the program ROM can be disabled using the lock bit. The following commands are not accepted under the following conditions:

• Block erase commands targeting data flash block A when the FMR14 bit in the FMR1 register is set to 1 (rewrite disabled).
• Block erase commands targeting data flash block B when the FMR15 bit is set to 1 (rewrite disabled).
• Block erase commands targeting data flash block C when the FMR16 bit is set to 1 (rewrite disabled).
• Block erase commands targeting data flash block D when the FMR17 bit is set to 1 (rewrite disabled). Figure 30.9 shows a Block Erase Flowchart (Flash Read y Status Interrupt Disabled ), Figure 30.10 shows a Block Erase Flowchart (Flash Ready St atus Interrupt Disabled and Suspend Enabled), and Figure 30.11 shows a Block Erase Flowchart (Flash Ready Status Interrupt Enabled and Suspend Enabled). In EW1 mode, do not execute this command to any block where a rewrite control program is allocated. While the RDYSTIE bit in the FMR0 register is set to 1 (flash ready status interrupt enabled), a flash ready status interrupt can be generated upon completion of auto-erasure. While the RDYSTIE bit is set to 1 and the FMR20 bit in the FMR2 register is set to 1 (erase-suspe nd enabled), a flash ready st atus interrupt is generated when the FMR21 bit is set to 1 (erase-suspend request) and auto-erasure suspends. The auto-erase result can be confirmed by reading the FST register during the interrupt routine.

R8C/32A Group 30. Flash Memory REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 498 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 30.9 Block Erase Flowchart (Flash Ready Status Interrupt Disabled) Start Write the command code 20h Write D0h to any block address FST7 = 1? Full status check Block erase completed No Yes FST7: Bit in FST register

R8C/32A Group 30. Flash Memory REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 499 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 30.10 Block Erase Flowchart (Flash Ready Status Interrupt Disabled and Suspend Enabled) Start Write the command code 20h Write D0h to any block address FST7 = 1? Full status check Block erase completed No Yes FMR20 = 1 Maskable interrupt (1) Notes: 1. The interrupt vector table and interrupt routine for interrupts to be used must be allocated to an area other the erase t arget area. 2. td(SR-SUS) is required until suspend is acknowledged after the FMR21 bit is set to 1. The interrupt to enter suspend must be enabled beforehand. FST6 = 1? REIT Yes FMR21 = 1 (2) FMR21 = 0 Access the flash memory No I = 1 (interrupt enabled) I: Flag in CPU register FST6, FST7: Bits in FST register FMR20, FMR21: Bits in FMR2 register

R8C/32A Group 30. Flash Memory REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 500 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 30.11 Block Erase Flowchart (Flash Ready Status Interrupt Enabled and Suspend Enabled) Start Write the command code 20h Write D0h to any block address I = 1 (interrupt enabled) Block erase completed RDYSTIE = 1 Maskable interrupt (1) Notes: 1. The interrupt vector table and interrupt routine for interrupts to be used must be allocated to an area other the erase target area. 2. td(SR-SUS) is required until suspend is acknowledged after the FMR21 bit is set to 1. The interrupt to enter suspend must be enabled beforehand. 3. When auto-erasure suspends, a flash ready status interrupt is generated. REIT FMR21 = 1 (2) Flash ready status interrupt (1, 3) REIT Access the flash memory RDYSTI = 0 FMR21 = 0 FST6 = 1? Yes Full status check No FMR20 = 1 I: Flag in CPU register RDYSTI, FST6: Bits in FST register RDYSTIE: Bit in FMR0 register FMR20, FMR21: Bits in FMR2 register

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30.4.11.6 Lock Bit Program Command

This command is used to set the lock bit of any block in the program ROM area to 0 (locked). When 77h is written in the first bus cycle and D0h is written in the second bus cycle to the starting block address, 0 is written to the lock bit of the specified bl ock. Make sure the address va lue in the first bus cycle is the same address as the starting block address specified in the second bus cycle. Figure 30.12 shows a Lock Bit Program Flowchart. The lock bit status (lock bit data) can be read using the read lock bit status command. The FST7 bit in the FST register can be used to confirm whether writing to the lock bit has completed. Refer to 30.4.10 Data Protect Function for the lock bit function and how to set the lock bit to 1 (not locked). Figure 30.12 Lock Bit Program Flowchart Start Write the command code 77h Write D0h to the starting block address FST7 = 1? Full status check Completed No Yes FST7: Bit in FST register

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30.4.11.7 Read Lock Bit Status Command

This command is used to read the lock bit status of any address in the program ROM area. When 71h written in the first bus cycle and D0h is written in the second cycle to the starting block address, the lock bit status of the specifi ed block is stored in the LBDATA bit in the FST register. After the FST7 bit in the FST register has been set to 1 (ready), read the LBDATA bit. Figure 30.13 shows a Read Lock Bit Status Flowchart. Figure 30.13 Read Lock Bit Status Flowchart Start Write D0h to the starting block address Block not locked No Yes Write the command code 71h FST7 = 1? Yes LBDATA = 1? Block locked No LBDATA, FST7: Bits in FST register

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30.4.11.8 Block Blank Check Command

This command is used to confirm that all addresses in any block are blank data FFh. When 25h is written in the first bus cycle and D0h is written in the second bus cycle to any block address, blank checking starts in the specified block. The FST7 bit in the FST register can be used to confirm whether blank checking has completed. The FST7 bit is set to 0 during the blank-check period and set to 1 when blank checking completes. After blank checking has completed, the blank-check result can be confirmed by the FST5 bit in the FST Figure 30.14 shows a Block Blank Check Flowchart. Figure 30.14 Block Blank Check Flowchart Start Write D0h to the starting block address Blank No Yes Write the command code 25h FST7 = 1? Yes FST5 = 0? Not blank No FST5, FST7: Bits in FST register

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30.4.12 Status Register

The status register indicates the operating status of the flash memory and whether erasure or programming has completed normally or terminated in error. The status of the status register can be read by the FST register.

30.4.13 Sequence Status

The clear sequence status bit indicates the operating status of the flash memory. This bit is set to 0 (busy) during auto-programming and auto-erasure. It is set to 1 (ready) when these operations complete.

30.4.14 Erase Status

Refer to 30.4.17 Full Status Check.

30.4.15 Program Status

Refer to 30.4.17 Full Status Check.

30.4.16 Suspend Status

The suspend status bit indicat es the suspend status of the flash memory commands. This bit is set to 1 (during erase-suspend) while auto-erasure suspends and set to 0 (other than erase-suspend) when auto-erasure restarts. Table 30.5 lists the Status Register. D0 to D7: Indicate the data bus which is read when the read status register command is executed. Bits FST4 (SR4) and FST5 (SR5) are set to 0 by executing the clear status command. When the FST4 bit (SR4) or FST5 bit (SR5) is set to 1, the program and block erase commands cannot be accepted. Table 30.5 Status Register Status Register Bit FST Register Bit Status Name Content Value After Reset01 SR0 (D0) − Reserved −−− SR1 (D1) − Reserved −−− SR2 (D2) − Reserved −−− SR3 (D3) − Reserved −−− SR4 (D4) FST4 Program status Completed normally Terminated in error SR5 (D5) FST5 Erase status/ blank check Completed normally Terminated in error SR6 (D6) FST6 Suspend status Other than erase-suspend During erase-suspend SR7 (D7) FST7 Sequencer status Busy Ready 1

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30.4.17 Full Status Check

If an error occurs, bits FST4 and FST5 in the FST register are set to 1, indicating the occurrence of an error. The execution result can be confirmed by checking these status bits (full status check). Table 30.6 lists the Errors and FST Register Status. Figure 30.15 shows the Full Status Check and Handling Procedure for Individual Errors. Note: 1. When FFh is written in the second bus cycle of these commands, the MCU enters read array mode. At the same time, the command code written in the first bus cycle is invalid. Table 30.6 Errors and FST Register Status FST Register (Status Register) Status Error Error Occurrence Condition FST5 (SR5) FST4 (SR4) 1 1 Command sequence error

• When a command is not written correctly.
• When data other than valid data (i.e., D0h or FFh) is written in the second bus cycle of the block erase command (1). 1 0 Erase error When the block erase command is executed, but auto- erasure does not complete correctly. Blank check error When the blank check command is executed and data other than blank data FFh is read. 0 1 Program error When the program command is executed, but auto- programming does not complete correctly.

R8C/32A Group 30. Flash Memory REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 506 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 30.15 Full Status Check and Ha ndling Procedure for Individual Errors Note: 1. To rewrite to the address where the program error occurs, ensure that the full status check completes normally and write to the address after the block erase command is executed. Full status check FST4 = 1 and FST5 = 1? FST5 = 1? FST4 = 1? Full status check completed No Yes Yes No Yes No Command sequence error Erase error/ blank check error Program error Command sequence error Execute the clear status register command (Set the status flags to 0) Check if the command is properly input Re-execute the command Erase error/ blank check error Execute the clear status register command (Set the status flags to 0) Erase command Re-execution times ≤ 3 times? Re-execute the block erase command Program error Execute the clear status register command (Set the status flags to 0) Specify an address other than the write address where the error occurs (1) as the program address Re-execute the program command The erasure target block cannot be used No Yes FST4, FST5: Bits in FST register FMR13: Bits in FMR1 register Is the lock bit disabled? or Is the command executed on the data flash area? No Yes Set FMR13 bit to 1 Is the lock bit disabled? or Is the command executed on the data flash area? No Yes Set FMR13 bit to 1

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30.5 Standard Serial I/O Mode

In standard serial I/O mode, a serial programmer which supports the MCU can be used to rewrite the user ROM area while the MCU is mounted on-board. There are three types of standard serial I/O modes: programmer Standard serial I/O mode 2 and standard serial I/O mode 3 can be used for the MCU. Refer to Appendix 2. Connection Examples between S erial Writer and On-Chip Debugging Emulator for examples of connecting to a serial programmer. Contact the serial programmer manufacturer for more information. Refer to the user’s manual included with your serial programmer for instructions. Table 30.7 lists the Pin Functions (Flash Memory Standard Serial I/O Mode 2) and Figure 30.16 shows Pin Handling in Standard Serial I/O Mode 2. Table 30.8 lists the Pin Functions (Flash Me mory Standard Serial I/O Mode 3) and Figure 30.17 shows Pin Handling in Standard Serial I/O Mode 3. After handling the pins shown in Table 30.8 and rewrit ing the flash memory using the programmer, apply a “H” level signal to the MODE pin and reset the hardware to run a program in the flash memory in single-chip mode.

30.5.1 ID Code Check Function

The ID code check function determines whether the ID codes sent from the serial programmer and those written in the flash memory match. Refer to 12. ID Code Areas for details of the ID code check.

R8C/32A Group 30. Flash Memory REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 508 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 30.16 Pin Handling in Standard Serial I/O Mode 2 Table 30.7 Pin Functions (Flash Memory Standard Serial I/O Mode 2) Pin Name I/O Description VCC, VSS Power supply input Apply the guaranteed programming and erasure voltage to the VCC pin and 0 V to the VSS pin. RESET Reset input I Reset input pin P4_6/XIN/(XCIN) P4_6 input/clock input I Connect a ceramic resonator or crystal oscillator between pins XIN(XCIN) and XOUT(XCOUT). P4_7/XOUT/(XCOUT) P4_7 input/clock output I/O P1_0 to P1_3, P1_6, P1_7 Input port P1 I Input a “H” or “L” level signal or leave open. P3_3 to P3_5, P3_7 Input port P3 I Input a “H” or “L” level signal or leave open. P4_2/VREF, P4_5 Input port P4 I Input a “H” or “L” level signal or leave open. MODE MODE I/O Input a “L” level signal. P1_4 TXD output O Serial data output pin P1_5 RXD input I Serial data input pin Notes: 1. In this example, modes are switched between single-chip mode and standard serial I/O mode by controlling the MODE input with a switch. 2. Always connect an oscillator. Set the main clock frequency to 1 MHz to 20 MHz. Refer to Appendix Figure 2.1 Connection Example with M16C Flash Starter (M3A-0806). MCU TXD RXD Data output Data input MODE VCC AVCC VSS AVSS RESETUser reset signal Connect an oscillator (2) XIN/ (XCIN ) XOUT/ (XCOUT)

R8C/32A Group 30. Flash Memory REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 509 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 30.17 Pin Handling in Standard Serial I/O Mode 3 Table 30.8 Pin Functions (Flash Memory Standard Serial I/O Mode 3) Pin Name I/O Description VCC, VSS Power supply input Apply the guaranteed programming and erasure voltage to the VCC pin and 0 V to the VSS pin. RESET Reset input I Reset input pin P4_6/XIN/(XCIN) P4_6 input/clo ck input I If an external osc illator is connected, connect a ceramic resonator or crystal oscillator between pins XIN(XCIN) and XOUT(XCOUT). To use as an input port, input a “H” or “L” level signal or leave the pin open. P4_7/XOUT/(XCOUT) P4_7 input/clock output I/O P1_0 to P1_7 Input port P1 I Input a “H” or “L” level signal or leave open. P3_3 to P3_5, P3_7 Input port P3 I Input a “H” or “L” level signal or leave open. P4_2/VREF, P4_5 Input port P4 I Input a “H” or “L” level signal or leave open. MODE MODE I/O Serial data I/O pin. Connect the pin to a programmer. Notes: 1. Controlled pins and external circuits vary depending on the programmer. Refer to the programmer manual for details. 2. In this example, modes are switched between single-chip mode and standard serial I/O mode by connecting a programmer. 3. When operating with the on-chip oscillator clock, it is not necessary to connect an oscillation circuit. MCU MODE RESET MODE I/O Reset input User reset signal VSS AVSS VCC AVCC

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30.6 Parallel I/O Mode

Parallel I/O mode is used to input a nd output software commands, addresses and data necessary to control (read, program, and erase) the on-chip flash memory. Use a parallel programmer which supports the MCU. C ontact the parallel programmer manufacturer for more information. Refer to the user’s manual included with your parallel programmer for instructions. In parallel I/O mode, the user ROM areas shown in Figure 30.1 can be rewritten.

30.6.1 ROM Code Protect Function

The ROM code protect function prevents the flash memo ry from being read and re written. (Refer to the 30.3.2 ROM Code Protect Function.)

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30.7 Notes on Flash Memory

30.7.1 CPU Rewrite Mode

30.7.1.1 Prohibited Instructions

The following instructions cannot be used while the program ROM area is being rewritten in EW0 mode because they reference data in the flash memory: UND, INTO, and BRK.

30.7.1.2 Non-Maskable Interrupts

Tables 30.9 and 30.10 show CPU Rewrite Mode Interrupts (1) and (2), respectively. FMR21, FMR22: Bits in FMR2 register Note: 1. Do not use a non-maskable interrupt while block 0 is being auto-erased because the fixed vector is allocated in block 0. Table 30.9 CPU Rewrite Mode Interrupts (1) Mode Erase/ Write Target Status Maskable Interrupt • Address Match

• Address Break (Note 1) EW0 Data flash During auto-erasure (suspend enabled) When an interrupt request is acknowledged, interrupt handling is executed. If the FMR22 bit is set to 1 (erase-suspend request enabled by interrupt request), the FMR21 bit is automatically set to 1 (erase-suspend request). The flash memory suspends auto-erasure after td(SR-SUS). If erase-suspend is required while the FMR22 bit is set to 0 (erase-suspend request disabled by interrupt request), set the FMR 21 bit to 1 during interrupt handling. The flash memory suspends auto-erasure after td(SR-SUS). While auto-erasure is being suspended, any block other than the block during auto- erasure execution can be read. Auto-erasure can be restarted by setting the FMR21 bit to 0 (erase restart). During auto-erasure (suspend disabled or FMR22 = 0) Interrupt handling is executed while auto-erasure or auto-programming is being performed. During auto-programming Program ROM During auto-erasure (suspend enabled) Usable by allocating a vector in RAM. Not usable during auto-erasure or auto-programming. During auto-erasure (suspend disabled) During auto-programming EW1 Data flash During auto-erasure (suspend enabled) When an interrupt request is acknowledged, interrupt handling is executed. If the FMR22 bit is set to 1, the FMR21 bit is automatically set to 1. The flash memory suspends auto-erasure after td(SR-SUS). If erase-suspend is required while the FMR22 bit is set to 0, set the FMR 21 bit to 1 during interrupt handling. The flash memory suspends auto-erasure after td(SR-SUS). While auto-erasure is being suspended, any block other than the block during auto- erasure execution can be read. Auto-erasure can be restarted by setting the FMR21 bit to 0. During auto-erasure (suspend disabled or FMR22 = 0) Interrupt handling is executed while auto-erasure or auto-programming is being performed. During auto-programming Program ROM During auto-erasure (suspend enabled) Auto-erasure suspends after td(SR-SUS) and interrupt handling is executed. Auto- erasure can be restarted by setting the FMR21 bit to 0 after interrupt handling completes. While auto-erasure is being suspended, any block other than the block during auto- erasure execution can be read. During auto-erasure (suspend disabled or FMR22 = 0) Auto-erasure and auto-programming have priority and interrupt requests are put on standby. Interrupt handling is executed after auto-erase and auto-program complete. During auto-programming

R8C/32A Group 30. Flash Memory REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 512 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. FMR21, FMR22: Bits in FMR2 register Note: 1. Do not use a non-maskable interrupt while block 0 is being auto-erased because the fixed vector is allocated in block 0. Table 30.10 CPU Rewrite Mode Interrupts (2) Mode Erase/ Write Target Status

• Watchdog Timer
• Oscillation Stop Detection
• Voltage Monitor 2
• Voltage Monitor 1
• NMI (Note 1)
• Undefined Instruction
• I N T O I n s t r u c t i o n
• BRK Instruction
• Single Step (Note 1) EW0 Data flash During auto-erasure (suspend enabled) When an interrupt request is acknowledged, interrupt handling is executed. If the FMR22 bit is set to 1 (erase-suspend request enabled by interrupt request), the FMR21 bit is automatically set to 1 (erase-suspend request). The flash memory suspends auto-erasure after td(SR-SUS). If erase-suspend is required while the FMR22 bit is set to 0 (erase-suspend request disabled by interrupt request), set the FMR 21 bit to 1 during interrupt handling. The flash memory suspends auto-erasure after td(SR-SUS). While auto-erasure is being suspended, any block other than the block during auto- erasure execution can be read. Auto-erasure can be restarted by setting the FMR21 bit is set to 0 (erase restart). During auto-erasure (suspend disabled or FMR22 = 0) Interrupt handling is executed while auto-erasure or auto-programming is being performed. During auto-programming Program ROM During auto-erasure (suspend enabled) When an interrupt request is acknowledged, auto-erasure or auto-programming is forcibly stopped immediately and the flash memory is reset. Interrupt handling starts when the flash memory restarts after the fixed period. Since the block during auto-erasure or the address during auto-programming is forcibly stopped, the normal value may not be read. After the flash memory restarts, execute auto-erasure again and ensure it completes normally. The watchdog timer does not stop during the command operation, so interrupt requests may be generated. Initialize the watchdog timer regularly using the erase-suspend function. Not usable during auto-erasure or auto-programming. During auto-erasure (suspend disabled) During auto-programming EW1 Data flash During auto-erasure (suspend enabled) When an interrupt request is acknowledged, interrupt handling is executed. If the FMR22 bit is set to 1, the FMR21 bit is automatically set to 1. The flash memory suspends auto-erasure after td(SR-SUS). If erase-suspend is required while the FMR22 bit is set to 0, set the FMR 21 bit to 1 during interrupt handling. The flash memory suspends auto-programming after td(SR- SUS). While auto-erasure is being suspended, any block other than the block during auto- erasure execution can be read. Auto-erasure can be restarted by setting the FMR21 bit is set to 0. During auto-erasure (suspend disabled or FMR22 = 0) Interrupt handling is executed while auto-erasure or auto-programming is being performed. During auto-programming Program ROM During auto-erasure (suspend enabled) When an interrupt request is acknowledged, auto-erasure or auto-programming is forcibly stopped immediately and the flash memory is reset. Interrupt handling starts when the flash memory restarts after the fixed period. Since the block during auto-erasure or the address during auto-programming is forcibly stopped, the normal value may not be read. After the flash memory restarts, execute auto-erasure again and ensure it completes normally. The watchdog timer does not stop during the command operation, so interrupt requests may be generated. Initialize the watchdog timer regularly using the erase-suspend function. Not usable during auto-erasure or auto-programming. During auto-erasure (suspend disabled or FMR22 = 0) During auto-programming

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30.7.1.3 How to Access

To set one of the following bits to 1, first write 0 and then 1 immediately. Do not generate an interrupt between writing 0 and writing 1.

• The FMR01 bit or FMR02 bit in the FMR0 register
• The FMR13 bit in the FMR1 register
• The FMR20 bit, FMR22 bit, or FMR 27 bit in the FMR2 register To set one of the following bits to 0, first write 1 and then 0 immediately. Do not generate an interrupt between writing 1 and writing 0.
• The FMR14 bit, FMR15 bit, FMR16 bit, or FMR17 bit in the FMR1 register

30.7.1.4 Rewriting User ROM Area

In EW0 Mode, if the supply voltage drops while rewr iting any block in which a rewrite control program is stored, it may not be possible to rewrite the flash memory because the rewrite control program cannot be rewritten correctly. In this case, use standard serial I/O mode.

30.7.1.5 Programming

Do not write additions to the already programmed address.

30.7.1.6 Entering Stop Mode or Wait Mode

Do not enter stop mode or wait mode during erase-suspend. If the FST7 in the FST register is set to 0 (busy (during programming or erasure execution), do not enter to stop mode or wait mode.

30.7.1.7 Programming and Erasu re Voltage for Flash Memory

To perform programming and erasure, use VCC = 2.7 V to 5.5 V as th e supply voltage. Do not perform programming and erasure at less than 2.7 V .

R8C/32A Group 31. Reducing Power Consumption REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 514 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 31. Reducing Power Consumption

31.1 Overview

This chapter describes key points and processing methods for reducing power consumption.

31.2 Key Points and Processing Method s for Reducing Power Consumption

Key points for reducing power consumption are shown below. They should be referred to when designing a system or creating a program.

31.2.1 Voltage Detection Circuit

If voltage monitor 1 and comparator A1 are not used, set the VCA26 bit in the VCA2 register to 0 (voltage detection 1 circuit disabled). If voltage monitor 2 and comparator A2 are not used, set the VCA27 bit in the VCA2 register to 0 (voltage detection 2 circuit disabled). If the power-on reset and voltage monitor 0 reset are not used, set the VCA25 bit in the VCA2 register to 0 (voltage detection 0 circuit disabled).

31.2.2 Ports

Even after the MCU enters wait mode or stop mode, the states of the I/O ports are retained. Current flows into the output ports in the active state, and shoot-through current flows into the input ports in the high-impedance state. Unnecessary ports should be set to input and fixe d to a stable electric potential before the MCU enters wait mode or stop mode.

31.2.3 Clocks

Power consumption generally depends on the number of the operating clocks and th eir frequencies. The fewer the number of operating clocks or the lower their frequencies, the more power consumption decreases. Unnecessary clocks should be stopped accordingly. Stopping low-speed on-chip oscillator oscillation: CM14 bit in CM1 register Stopping high-speed on-chip oscillator oscillation: FRA00 bit in FRA0 register

31.2.4 Wait Mode, Stop Mode

Power consumption can be reduced in wait mode and stop mode. Refer to 9.7 Power Control for details.

31.2.5 Stopping Peripheral Function Clocks

If the peripheral function f1 , f2, f4, f8, and f32 clocks are not necessary in wait mode, set the CM02 bit in the CM0 register to 1 (peripheral function clock stops in wait mode). This will stop the f1, f2, f4, f8, and f32 clocks in wait mode.

31.2.6 Timers

If timer RA is not used, set the TCKCUT bit in the TRAMR register to 1 (count source cutoff). If timer RB is not used, set the TCKCUT bit in the TRBMR register to 1 (count source cutoff). If timer RC is not used, set the MSTTRC bit in the MSTCR register to 1 (standby).

31.2.7 A/D Converter

When the A/D converter is not used , power consumption can be reduced by setting the ADSTBY bit in the ADCON1 register to 0 (A/D operation stops (standby)) to shut off any analog circuit current flow.

31.2.8 Clock Synchronous Serial Interface

When the SSU or the I2C bus is not used, set the MSTIIC bit in the MSTCR register to 1 (standby).

R8C/32A Group 31. Reducing Power Consumption REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 515 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

31.2.9 Reducing Internal Power Consumption

When the MCU enters wait mode using low-speed clock mode or low-speed on-chip oscillator mode, internal power consumption can be reduced by using the VCA 20 bit in the VCA2 register. Figure 31.1 shows the Handling Procedure for Reducing Internal Power Consum ption Using VCA20 Bit. To enable reduced internal power consumption by the VCA20 bit, follow Figure 31.1 Handling Procedure for Reducing Internal Power Consumption Using VCA20 Bit. Figure 31.1 Handling Procedure for Reducing In ternal Power Consumption Using VCA20 Bit Notes: 1. Execute this routine to handle all interrupts generated in wait mode. However, this does not apply if it is not necessary to start the high-speed clock or high-speed on-chip oscillator during the i nterrupt routine. 2. Do not set the VCA20 bit to 0 with the instruction immediately after setting the VCA20 bit to 1. Also, do not do the opposit e. 3. When the VCA20 bit is set to 1, do not set the CM10 bit to 1 (stop mode). 4. When the MCU enters wait mode, follow 9.7.2 Wait Mode. Procedure for enabling reduced internal power consumption using VCA20 bit Enter low-speed clock mode or low-speed on-chip oscillator mode Stop XIN clock and high-speed on-chip oscillator clock VCA20 ← 1 (internal power low consumption enabled) (2, 3) Enter wait mode (4) VCA20 ← 0 (internal power low consumption disabled) (2) Start XIN clock or high-speed on-chip oscillator clock (Wait until XIN clock or high-speed on-chip oscillator clock oscillation stabilizes) Enter high-speed clock mode or high-speed on-chip oscillator mode In interrupt routine VCA20 ← 0 (internal power low consumption disabled) (2) (This is automatically set when exiting wait mode) Start XIN clock or high-speed on-chip oscillator clock Enter high-speed clock mode or high-speed on-chip oscillator mode Enter low-speed clock mode or low-speed on-chip oscillator mode Exit wait mode by interrupt Stop XIN clock and high-speed on-chip oscillator clock VCA20 ← 1 (internal power low consumption enabled) (2, 3) Interrupt handling completed Step (1) Step (2) Step (3) Step (4) Step (5) Step (6) Step (7) Step (8) Step (5) Step (6) Step (7) Step (8) (Wait until XIN clock or high-speed on-chip oscillator clock oscillation stabilizes) Step (1) Step (2) Step (3) If it is necessary to start the high-speed clock or high-speed on-chip oscillator during the interrupt routine, execute steps (6) to (7) in the routine. If the high-speed clock or high-speed on-chip oscillator starts during the interrupt routine, execute steps (1) to (3) at the end of the routine. (Note 1) Interrupt handling VCA20: Bit in VCA2 register

R8C/32A Group 31. Reducing Power Consumption REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 516 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

31.2.10 Stopping Flash Memory

In low-speed on-chip oscillator mode and low-speed clock mode, power consumption can be further reduced by stopping the flash memory using the FMSTP bit in the FMR0 register. Access to the flash memory is disabled by setting the FMSTP bit to 1 (flash memo ry stops). The FMSTP bit must be written to by a program transferred to RAM. When the MCU enters stop mode or wait mode while CPU rewrite mode is disabl ed, the power for the flash memory is automatically turned off. It is turned back on again after the MCU exit stop mode or wait mode. This eliminates the need to set the FMR0 register. Figure 31.2 shows the Handling Procedure Example for Reducing Power Consumption Using FMSTP Bit. Figure 31.2 Handling Procedure Example for Re ducing Power Consumption Using FMSTP Bit FMSTP bit setting program Transfer the FMSTP bit setting program to the RAM Jump to the FMSTP bit setting program (The subsequent processing is executed by the program in the RAM) After writing 0 to the FMR01 bit, write 1 (CPU rewrite mode enabled) Enter low-speed clock mode or low-speed on-chip oscillator mode Process in low-speed clock mode or low-speed on-chip oscillator mode Write 0 to the FMR01 bit (CPU rewrite mode disabled) Jump to the specified address in the flash memory Notes: 1. After setting the FMR01 bit to 1 (CPU rewrite mode enabled), set the FMSTP bit to 1 (flash memory stops). 2. Before switching the CPU clock source, make sure the designated clock is stable. 3. Insert a 60- µs wait time by a program. Do not access the flash memory during this wait time. Write 1 to the FMSTP bit (flash memory stops. low power consumption state) (1) Wait until the flash memory circuit stabilizes (60 µs) (3) Write 0 to the FMSTP bit (flash memory operates) Switch the clock source for the CPU clock (2) FMR01, FMSTP: Bits in FMR0 register Stop the high-speed on-chip oscillator

R8C/32A Group 31. Reducing Power Consumption REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 517 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

31.2.11 Low-Current-Cons umption Read Mode

In low-speed clock mode and low-speed on-chip oscill ator mode, the current consumption when reading the flash memory can be reduced by setting the FMR27 bit in the FMR2 register to 1 (enabled). Figure 31.3 shows the Handling Procedure Example of Low-Current-Consumption Read Mode. Figure 31.3 Handling Procedure Example of Low-Current-Consumption Read Mode

31.2.12 Others

Set the MSTTRD bit in the MSTCR register to 1. The power consumption of the peripheral functions can be reduced. Notes: 1. To set the FMR27 bit to 1, first write 0 and then write 1 immediately. After writing 0, do not generate an interrupt before writing 1. 2. In low-current-consumption read mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled). Handling procedure for enabling low-current-consumption read mode by FMR27 bit Step (1) Step (2) Step (3) Step (4) Step (5) Step (6) Step (7) Step (8) FMR27: Bit in FMR2 register Enter low-speed clock mode or low-speed on-chip oscillator mode Stop the high-speed on-chip oscillator clock FMR27 ← 1 (low-current-consumption read mode enabled) (1) Enter low-current-consumption read mode (2) FMR27 ← 0 (low-current-consumption read mode disabled) Start the high-speed on-chip oscillator clock (Wait until the high-speed on-chip oscillator clock oscillation stabilizes) Enter high-speed on-chip oscillator mode

R8C/32A Group 32. Electrical Characteristics REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 518 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 32. Electrical Characteristics Note: 1. For the register settings for each operation, refer to 7. I/O Ports and 9. Clock Generation Circuit. Table 32.1 Absolute Maximum Ratings Symbol Parameter Condition Rated Value Unit VCC/AVCC Supply voltage −0.3 to 6.5 V VI Input voltage P1_0 to P1_7, P3_3 to P3_5, P3_7, P4_5 to P4_7, MODE, RESET −0.3 to VCC + 0.3 V XIN, XOUT XIN-XOUT oscillation on (oscillation buffer ON) (1) −0.3 to 1.65 V XIN, XOUT XIN-XOUT oscillation off (oscillation buffer OFF) (1) −0.3 to VCC + 0.3 V XCIN XCIN-XCOUT oscillation on (oscillation buffer ON) (1) −0.3 to 1.65 V XCIN XCIN-XCOUT oscillation off (oscillation buffer OFF) (1) −0.3 to VCC + 0.3 V VO Output voltage P1_0 to P1_7, P3_3 to P3_5, P3_7, P4_5 to P4_7 −0.3 to VCC + 0.3 V XOUT XIN-XOUT oscillation on (oscillation buffer ON) (1) −0.3 to 1.65 V XOUT XIN-XOUT oscillation off (oscillation buffer OFF) (1) −0.3 to VCC + 0.3 V XCOUT XCIN-XCOUT oscillation on (oscillation buffer ON) (1) −0.3 to 1.65 V XCOUT XCIN-XCOUT oscillation off (oscillation buffer OFF) (1) −0.3 to VCC + 0.3 V Pd Power dissipation T opr = 25°CT B D m W Topr Operating ambient temperature −20 to 85 (N version) / −40 to 85 (D version) Tstg Storage temperature −65 to 150 °C

R8C/32A Group 32. Electrical Characteristics REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 519 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Notes: 1. V CC = 1.8 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified. 2. The average output current indicates the av erage value of current measured during 100 ms. Table 32.2 Recommended Operating Conditions Symbol Parameter Conditions Standard UnitMin. Typ. Max. VCC/AVCC Supply voltage 1.8 − 5.5 V VSS/AVSS Supply voltage − 0 − V VIH Input “H” voltage Input level switching function (I/O port) CMOS input Input level selection : 0.35 VCC 4.0 V ≤ VCC ≤ 5.5 V 0.45 VCC − VCC V 2.7 V ≤ VCC < 4.0 V 0.55 VCC − VCC V 1.8 V ≤ VCC < 2.7 V 0.65 VCC − VCC V Input level selection : 0.5 VCC 4.0 V ≤ VCC ≤ 5.5 V 0.6 VCC − VCC V 2.7 V ≤ VCC < 4.0 V 0.7 VCC − VCC V 1.8 V ≤ VCC < 2.7 V 0.8 VCC − VCC V Input level selection : 0.7 VCC 4.0 V ≤ VCC ≤ 5.5 V 0.85 VCC − VCC V 2.7 V ≤ VCC < 4.0 V 0.85 VCC − VCC V 1.8 V ≤ VCC < 2.7 V 0.85 VCC − VCC V VIL Input “L” voltage Input level switching function (I/O port) CMOS input Input level selection : 0.35 VCC 4.0 V ≤ VCC ≤ 5.5 V 0 − 0.2 VCC V 2.7 V ≤ VCC < 4.0 V 0 − 0.2 VCC V 1.8 V ≤ VCC < 2.7 V 0 − 0.2 VCC V Input level selection : 0.5 VCC 4.0 V ≤ VCC ≤ 5.5 V 0 − 0.4 VCC V 2.7 V ≤ VCC < 4.0 V 0 − 0.3 VCC V 1.8 V ≤ VCC < 2.7 V 0 − 0.2 VCC V Input level selection : 0.7 VCC 4.0 V ≤ VCC ≤ 5.5 V 0 − 0.55 VCC V 2.7 V ≤ VCC < 4.0 V 0 − 0.45 VCC V 1.8 V ≤ VCC < 2.7 V 0 − 0.35 VCC V IOH(sum) Peak sum output Sum of all pins IOH(peak) −− TBD mA IOH(sum) Average sum Sum of all pins IOH(avg) −− TBD mA IOH(peak) Peak output “H” current Drive capacity Low −− − 10 mA Drive capacity High −− − 40 mA IOH(avg) Average output “H” current Drive capacity Low −− − 5m A Drive capacity High −− − 20 mA IOL(sum) Peak sum output Sum of all pins IOL(peak) −− TBD mA IOL(sum) Average sum Sum of all pins IOL(avg) −− TBD mA IOL(peak) Peak output “L” current Drive capacity Low −− 10 mA Drive capacity High −− 40 mA IOL(avg) Average output “L” current Drive capacity Low −− 5m A Drive capacity High −− 20 mA f(XIN) XIN clock input oscillation frequency 3.0 V ≤ VCC ≤ 5.5 V 0 − 20 MHz 2.7 V ≤ VCC < 3.0 V 0 − 10 MHz 2.2 V ≤ VCC < 2.7 V 0 − 5M H z 1.8 V ≤ VCC < 2.2 V 0 − 2M H z f(XCIN) XCIN clock input oscillation frequency 1.8 V ≤ VCC ≤ 5.5 V − 32.768 50 kHz − fOCO40M operating When used as the count source for timer RC fOCO40M = 40MHz 2.7 − 5.5 V When used as the count source for fOCO-F fOCO40M = 40MHz 1.8 − 5.5 V fOCO-F fOCO-F frequency 3.0 V ≤ VCC ≤ 5.5 V 0 − 20 MHz 2.7 V ≤ VCC < 3.0 V 0 − 10 MHz 2.2 V ≤ VCC < 2.7 V 0 − 5M H z − fOCO-S operating voltage fOCO-S = 125kHz 1.8 − 5.5 V − System clock frequency 3.0 V ≤ VCC ≤ 5.5 V 0 − 20 MHz 2.7 V ≤ VCC < 3.0 V 0 − 10 MHz 2.2 V ≤ VCC < 2.7 V 0 − 5M H z 1.8 V ≤ VCC < 2.2 V 0 − 2M H z f(BCLK) CPU clock frequency 3.0 V ≤ VCC ≤ 5.5 V 0 − 20 MHz 2.7 V ≤ VCC < 3.0 V 0 − 10 MHz 2.2 V ≤ VCC < 2.7 V 0 − 5M H z 1.8 V ≤ VCC < 2.2 V 0 − 2M H z

R8C/32A Group 32. Electrical Characteristics REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 520 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 32.1 Ports P1, P3, P4 Timing Measurement Circuit P4 30pF

R8C/32A Group 32. Electrical Characteristics REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 521 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Notes: 1. V CC/AVCC = Vref = 2.2 to 5.5 V, VSS = 0V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified. 2. Set φAD frequency as follows: When AVCC = 4.0 to 5.5 V, 2 MHz ≤ φAD ≤ 20 MHz When AVCC = 3.2 to 4.0 V, 2 MHz ≤ φAD ≤ 16 MHz When AVCC = 3.0 to 3.2 V, 2 MHz ≤ φAD ≤ 10 MHz When AVCC = 2.2 to 3.0 V, 2 MHz ≤ φAD ≤ 5 MHz 3. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in 8-bit mode. Table 32.3 A/D Converter Characteristics (1) Symbol Parameter Conditions Standard UnitMin. Typ. Max. − Resolution V ref = AVCC −− 10 Bit INL Integral non-linearity error 10-bit mode V ref = AVCC = 5.0V AN8 to AN11 input −− ±3 LSB Vref = AVCC = 3.3V AN8 to AN11 input −− ±5 LSB Vref = AVCC = 3.0V AN8 to AN11 input −− ±5 LSB Vref = AVCC = 2.2V AN8 to AN11 input −− ±5 LSB 8-bit mode V ref = AVCC = 5.0V AN8 to AN11 input −− ±2 LSB Vref = AVCC = 3.3V AN8 to AN11 input −− ±2 LSB Vref = AVCC = 3.0V AN8 to AN11 input −− ±2 LSB Vref = AVCC = 2.2V AN8 to AN11 input −− ±2 LSB − Absolute accuracy 10-bit mode V ref = AVCC = 5.0V AN8 to AN11 input −− ±3 LSB Vref = AVCC = 3.3V AN8 to AN11 input −− ±5 LSB Vref = AVCC = 3.0V AN8 to AN11 input −− ±5 LSB Vref = AVCC = 2.2V AN8 to AN11 input −− ±5 LSB 8-bit mode V ref = AVCC = 5.0V AN8 to AN11 input −− ±2 LSB Vref = AVCC = 3.3V AN8 to AN11 input −− ±2 LSB Vref = AVCC = 3.0V AN8 to AN11 input −− ±2 LSB Vref = AVCC = 2.2V AN8 to AN11 input −− ±2 LSB − Tolerance level impedance − 3 − kΩ DNL Differential non-linearity error −− ±1 LSB − Offset error −− ±3 LSB − Gain error −− ±3 LSB RLADDER Ladder resistance V ref = AVCC 10 − 40 k Ω tCONV Conversion time 10-bit mode V ref = AVCC = 5.0V, φAD = 20 MHz 2.0 −− µ s 8-bit mode V ref = AVCC = 5.0V, φAD = 20 MHz 2.0 −− µ s tSAMP Sampling time 0.60 −− µ s Vref Reference voltage 2.2 − AVCC V VIA Analog input voltage (3) 0 − Vref V OCVREF On-chip reference voltage 1.24 1.34 1.44 V

R8C/32A Group 32. Electrical Characteristics REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 522 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Note: 1. V CC = 2.7 to 5.5 V, Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified. 2. When the digital filter is not selected. Note: 1. V CC = 2.7 to 5.5 V, Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified. 2. When the digital filter is not selected. Table 32.4 Comparator A Electrical Characteristics Symbol Parameter Condition Standard UnitMin. Typ. Max. LVREF External reference voltage input range 1.4 − VCC V LVCMP1, LVCMP2 External comparison voltage input range −0.3 − VCC + 0.3 V − Offset − TBD TBD mV − Comparator output delay time (2) − TBD TBD µs − Comparator operating current V CC = 5.0 V − TBD TBD µA Table 32.5 Comparator B Electrical Characteristics Symbol Parameter Condition Standard UnitMin. Typ. Max. Vref IVREF1, IVREF3 input reference voltage 0 − VCC − 1.4 V VI IVCMP1, IVCMP3 input voltage −0.3 − VCC + 0.3 V − Offset − TBD TBD mV td Comparator output delay time (2) VI = Vref ± 10 mV − TBD TBD µs ICMP Comparator operating current V CC = 5.0 V − TBD TBD µA

R8C/32A Group 32. Electrical Characteristics REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 523 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Notes: 1. V CC = 2.7 to 5.5 V at Topr = 0 to 60°C, unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. Endurance to guarantee all electrical c haracteristics after program and erase. (1 to Min. value can be guaranteed). 4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 5. If an error occurs during block erase, attempt to execute t he clear status register command, then execute the block erase command at least three times until the erase error does not occur. 6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 7. The data hold time includes time that the power supply is off or the clock is not supplied. 8. The erase sequence does not proceed unles s the interval of 20 ms or more is allowed from when an erase operation starts/restarts until the following suspend is requested. Table 32.6 Flash Memory (Program ROM) Electrical Characteristics Symbol Parameter Conditions Standard UnitMin. Typ. Max. − Program/erase endurance (2) 1,000 (3) −− times − Byte program time − 80 TBD µs − Block erase time − 0.3 TBD s td(SR-SUS) Time delay from suspend request until suspend −− 5+CPU clock × 3 cycles ms − Interval from erase start/restart until following suspend request (8) 0 −− µ s − Time from suspend until erase restart −− 30+CPU clock × 1 cycle µs − Program, erase voltage 2.7 − 5.5 V − Read voltage 1.8 − 5.5 V − Program, erase temperature 0 − 60 °C − Data hold time (7) Ambient temperature = 55°C2 0 −− year

R8C/32A Group 32. Electrical Characteristics REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 524 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Notes: 1. V CC = 2.7 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. Endurance to guarantee all electrical c haracteristics after program and erase. (1 to Min. value can be guaranteed). 4. Standard of block A to block D when program and erase enduranc e exceeds 1,000 times. Byte program time to 1,000 times is the same as that in program ROM. 5. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 6. If an error occurs during block erase, attempt to execute t he clear status register command, then execute the block erase command at least three times until the erase error does not occur. 7. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 8. −40°C for D version. 9. The data hold time includes time that the po wer supply is off or the clock is not supplied. 10. The erase sequence does not proceed unles s the interval of 3 ms or more is allowed from when an erase operation starts/restarts until the following suspend is requested. Figure 32.2 Time de lay until Suspend Table 32.7 Flash Memory (Data flash Block A to Block D) Electrical Characteristics (4) Symbol Parameter Conditions Standard UnitMin. Typ. Max. − Program/erase endurance (2) 10,000 (3) −− times − Byte program time (program/erase endurance ≤ 1,000 times) − 160 TBD µs − Byte program time (program/erase endurance > 1,000 times) − 300 −µ s − Block erase time (program/erase endurance ≤ 1,000 times) − 0.2 1 s − Block erase time (program/erase endurance > 1,000 times) − 0.3 1 s td(SR-SUS) Time delay from suspend request until suspend −− 5+CPU clock × 3 cycles ms − Interval from erase start/restart until following suspend request (10) 0 −− µ s − Time from suspend until erase restart −− 30+CPU clock × 1 cycle µs − Program, erase voltage 2.7 − 5.5 V − Read voltage 1.8 − 5.5 V − Program, erase temperature −20 (8) − 85 °C − Data hold time (9) Ambient temperature = 55 °C2 0 −− year FST6 bit Suspend request (FMR21 bit) Fixed time td(SR-SUS) Clock-dependent time Access restart FST6: Bit in FST register FMR21: Bit in FMR2 register

R8C/32A Group 32. Electrical Characteristics REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 525 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Notes: 1. The measurement condition is V CC = 1.8 V to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version). 2. Select the voltage detection level with bits VDSEL0 and VDSEL1 in the OFS register. 3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2 register to 0. Notes: 1. The measurement condition is V CC = 1.8 V to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version). 2. Select the voltage detection level with bits VD1S0 to VD1S3 in the VD1LS register. 3. Time until the voltage monitor 1 interrupt request is generated after the voltage passes V det1. 4. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2 register to 0. Table 32.8 Voltage Detection 0 Circuit Electrical Characteristics Symbol Parameter Condition Standard UnitMin. Typ. Max. Vdet0 Voltage detection level Vdet0_0 (2) At the falling of VCC 1.80 1.90 2.00 V Voltage detection level Vdet0_1 (2) At the falling of VCC 2.20 2.35 2.50 V Voltage detection level Vdet0_2 (2) At the falling of VCC 2.70 2.85 3.00 V Voltage detection level Vdet0_3 (2) At the falling of VCC 3.65 3.80 3.95 V − Voltage detection circuit self power consumption VCA25 = 1, V CC = 5.0 V − TBD −µ A td(E-A) Waiting time until voltage detection circuit operation starts (3) −− TBD µs Vccmin MCU operating voltage minimum value 2.2 −− V Table 32.9 Voltage Detection 1 Circuit Electrical Characteristics Symbol Parameter Condition Standard UnitMin. Typ. Max. Vdet1 Voltage detection level Vdet1_0 (2) At the falling of VCC 2.05 2.20 2.35 V Voltage detection level Vdet1_1 (2) At the falling of VCC 2.20 2.35 2.50 V Voltage detection level Vdet1_2 (2) At the falling of VCC 2.35 2.50 2.65 V Voltage detection level Vdet1_3 (2) At the falling of VCC 2.50 2.65 2.80 V Voltage detection level Vdet1_4 (2) At the falling of VCC 2.65 2.80 2.95 V Voltage detection level Vdet1_5 (2) At the falling of VCC 2.80 2.95 3.10 V Voltage detection level Vdet1_6 (2) At the falling of VCC 2.90 3.10 3.30 V Voltage detection level Vdet1_7 (2) At the falling of VCC 3.05 3.25 3.45 V Voltage detection level Vdet1_8 (2) At the falling of VCC 3.20 3.40 3.60 V Voltage detection level Vdet1_9 (2) At the falling of VCC 3.35 3.55 3.75 V Voltage detection level Vdet1_A (2) At the falling of VCC 3.50 3.70 3.90 V Voltage detection level Vdet1_B (2) At the falling of VCC 3.65 3.85 4.05 V Voltage detection level Vdet1_C (2) At the falling of VCC 3.80 4.00 4.20 V Voltage detection level Vdet1_D (2) At the falling of VCC 3.95 4.15 4.35 V Voltage detection level Vdet1_E (2) At the falling of VCC 4.10 4.30 4.50 V Voltage detection level Vdet1_F (2) At the falling of VCC 4.25 4.45 4.65 V − Voltage monitor 1 interrupt request generation time (3) − 40 −µ s − Voltage detection circuit self power consumption VCA26 = 1, V CC = 5.0 V − TBD −µ A td(E-A) Waiting time until voltage detection circuit operation starts (4) −− TBD µs

R8C/32A Group 32. Electrical Characteristics REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 526 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Notes: 1. The measurement condition is V CC = 1.8 V to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version). 2. The voltage detection level varies with detection targets. Se lect the level with the VCA24 bit in the VCA2 register. 3. Time until the voltage monitor 2 interrupt request is generated after the voltage passes V det2. 4. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2 register to 0. Notes: 1. The measurement condition is T opr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified. 2. This condition (external power V CC rise gradient) does not apply if VCC ≥ 1.0 V. 3. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS register to 0, the VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register to 1. 4. t w(por1) indicates the duration the external power V CC must be held below the effective voltage (V por1) to enable a power on reset. When turning on the power for the first time, maintain tw(por1) for 1 ms or more. Figure 32.3 Power-on Reset Circuit Electrical Characteristics Table 32.10 Voltage Detection 2 Circuit Electrical Characteristics Symbol Parameter Condition Standard UnitMin. Typ. Max. Vdet2 Voltage detection level Vdet2_0 (2) At the falling of VCC 3.80 4.00 4.20 V Voltage detection level Vdet2_EXT (2) At the falling of LVCMP2 1.24 1.34 1.44 V − Voltage monitor 2 interrupt request generation time (3) − 40 −µ s − Voltage detection circuit self power consumption VCA27 = 1, V CC = 5.0 V − TBD −µ A td(E-A) Waiting time until voltage detection circuit operation starts (4) −− TBD µs Table 32.11 Power-on Reset Circuit, Voltage Monitor 0 Reset Electrical Characteristics (3) Symbol Parameter Condition Standard UnitMin. Typ. Max. Vpor1 Power-on reset valid voltage (4) −− 1.0 V Vpor2 Power-on reset or voltage monitor 0 reset valid voltage 0 − Vdet0 V trth External power VCC rise gradient (2) 20 −− mV/msec Notes: 1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage range (1.8 V or above) during the sampling time. 2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit for details. 3. V det0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection Circuit for details. Vdet0 (3) Vpor1 Internal reset signal (“L” valid) tw(por1) Sampling time (1, 2) Vdet0 (3) fOCO-S × 32 1 fOCO-S × 32 Vpor2 1.8V External Power VCC trth trth

R8C/32A Group 32. Electrical Characteristics REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 527 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Notes: 1. V CC = 1.8 to 5.5 V, Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified. 2. This indicates the precision error for the frequency set to fOCO40M. 3. These values are not guaranteed. 4. This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in UART mode. Note: 1. V CC = 1.8 to 5.5 V, Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified. Notes: 1. The measurement condition is V CC = 1.8 to 5.5 V and Topr = 25°C. 2. Waiting time until the internal power s upply generation circuit stabilizes during power-on. 3. Time until system clock supply starts after the interrupt is acknowledged to exit stop mode. Table 32.12 High-speed On-Chip Oscillator Circuit Electrical Characteristics Symbol Parameter Condition Standard UnitMin. Typ. Max. fOCO40M High-speed on-chip o scillator frequency after reset VCC = 5.0 V, Topr = 25°C TBD (3) 40 TBD (3) MHz High-speed on-chip oscillator frequency when the FRA4 register correction value is written into the FRA1 register and the FRA5 register correction value into the FRA3 register (4) TBD (3) 36.864 TBD (3) MHz High-speed on-chip oscillator frequency when the FRA6 register correction value is written into the FRA1 register and the FRA7 register correction value into the FRA3 register TBD (3) 32 TBD (3) MHz High-speed on-chip oscillator frequency temperature • supply voltage dependence (2) VCC = 2.7 V to 5.5 V −20°C ≤ Topr ≤ 85°C TBD − TBD % VCC = 2.7 V to 5.5 V −40°C ≤ Topr ≤ 85°C TBD − TBD % VCC = 2.2 V to 5.5 V −20°C ≤ Topr ≤ 85°C TBD − TBD % VCC = 2.2 V to 5.5 V −40°C ≤ Topr ≤ 85°C TBD − TBD % VCC = 1.8 V to 5.5 V −20°C ≤ Topr ≤ 85°C TBD − TBD % VCC = 1.8 V to 5.5 V −40°C ≤ Topr ≤ 85°C TBD − TBD % − Oscillation stability time V CC = 5.0 V, Topr = 25°C − TBD TBD µs − Self power consumption at oscillation V CC = 5.0 V, Topr = 25°C − TBD −µ A Table 32.13 Low-speed On-Chip Oscillator Circuit Electrical Characteristics Symbol Parameter Condition Standard UnitMin. Typ. Max. fOCO-S Low-speed on-chip oscillator frequency 60 125 250 kHz − Oscillation stability time V CC = 5.0 V, Topr = 25°C − 10 100 µs − Self power consumption at oscillation V CC = 5.0 V, Topr = 25°C − 1 −µ A Table 32.14 Power Supply Circuit Timing Characteristics Symbol Parameter Condition Standard UnitMin. Typ. Max. td(P-R) Time for internal power supply stabilization during power-on(2) −− TBD µs td(R-S) STOP exit time(3) −− TBD µs

R8C/32A Group 32. Electrical Characteristics REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 528 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Notes: 1. V CC = 1.8 to 5.5 V, VSS = 0 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified. 2. 1t CYC = 1/f1(s) Table 32.15 Timing Requirements of Clock Synchronous Serial I/O with Chip Select (1) Symbol Parameter Conditions Standard UnitMin. Typ. Max. tSUCYC SSCK clock cycle time 4 −− tCYC (2) tHI SSCK clock “H” width 0.4 − 0.6 t SUCYC tLO SSCK clock “L” width 0.4 − 0.6 t SUCYC tRISE SSCK clock rising time Master −− 1 tCYC (2) Slave −− 1 µs tFALL SSCK clock falling time Master −− 1 tCYC (2) Slave −− 1 µs tSU SSO, SSI data input setup time 100 −− ns tH SSO, SSI data input hold time 1 −− tCYC (2) tLEAD SCS setup time Slave 1t CYC + 50 −− ns tLAG SCS hold time Slave 1t CYC + 50 −− ns tOD SSO, SSI data output delay time −− 1 tCYC (2) tSA SSI slave access time 2.7 V ≤ VCC ≤ 5.5 V −− 1.5tCYC + 100 ns 1.8 V ≤ VCC < 2.7 V −− 1.5tCYC + 200 ns tOR SSI slave out open time 2.7 V ≤ VCC ≤ 5.5 V −− 1.5tCYC + 100 ns 1.8 V ≤ VCC < 2.7 V −− 1.5tCYC + 200 ns

R8C/32A Group 32. Electrical Characteristics REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 529 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 32.4 I/O Timing of Clock Synchronous Serial I/O with Chip Select (Master) VIH or VOH VIH or VOH tHI tLO tHI tFALL tRISE tLO tSUCYC tOD tHtSU SCS (output) SSCK (output) (CPOS = 1) SSCK (output) (CPOS = 0) SSO (output) SSI (input) 4-Wire Bus Communication Mode, Master, CPHS = 1 VIH or VOH VIH or VOH tHI tLO tHI tFALL tRISE tLO tSUCYC tOD tHtSU SCS (output) SSCK (output) (CPOS = 1) SSCK (output) (CPOS = 0) SSO (output) SSI (input) 4-Wire Bus Communication Mode, Master, CPHS = 0 CPHS, CPOS: Bits in SSMR register

R8C/32A Group 32. Electrical Characteristics REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 530 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 32.5 I/O Timing of Clock Synchronous Serial I/O with Chip Select (Slave) VIH or VOH VIH or VOH SCS (input) SSCK (input) (CPOS = 1) SSCK (input) (CPOS = 0) SSO (input) SSI (output) 4-Wire Bus Communication Mode, Slave, CPHS = 1 VIH or VOH VIH or VOH tHI tLO tHI tFALL tRISE tLO tSUCYC tHtSU SCS (input) SSCK (input) (CPOS = 1) SSCK (input) (CPOS = 0) SSO (input) SSI (output) 4-Wire Bus Communication Mode, Slave, CPHS = 0 tOD tLEAD tSA tLAG tOR tHI tLO tHI tFALL tRISE tLO tSUCYC tHtSU tOD tLEAD tSA tLAG tOR CPHS, CPOS: Bits in SSMR register

R8C/32A Group 32. Electrical Characteristics REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 531 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 32.6 I/O Timing of Clock Synchronous Serial I/O with Chip Select (Clock Synchronous Communication Mode) VIH or VOH tHI tLO tSUCYC tOD tHtSU SSCK SSO (output) SSI (input) VIH or VOH

R8C/32A Group 32. Electrical Characteristics REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 532 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Notes: 1. V CC = 1.8 to 5.5 V, VSS = 0 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified. 2. 1t CYC = 1/f1(s) Figure 32.7 I/O Timing of I 2C bus Interface Table 32.16 Timing Requirements of I 2C bus Interface (1) Symbol Parameter Condition Standard UnitMin. Typ. Max. tSCL SCL input cycle time 12tCYC + 600 (2) −− ns tSCLH SCL input “H” width 3tCYC + 300 (2) −− ns tSCLL SCL input “L” width 5tCYC + 500 (2) −− ns tsf SCL, SDA input fall time −− 300 ns tSP SCL, SDA input spike pulse rejection time −− 1tCYC (2) ns tBUF SDA input bus-free time 5tCYC (2) −− ns tSTAH Start condition input hold time 3tCYC (2) −− ns tSTAS Retransmit start condition input setup time 3tCYC (2) −− ns tSTOP Stop condition input setup time 3tCYC (2) −− ns tSDAS Data input setup time 1tCYC + 20 (2) −− ns tSDAH Data input hold time 0 −− ns SDA tSTAH tSCLL tBUF VIH VIL tSCLH SCL tsrtsf tSDAHtSCL tSTAS tSP tSTOP tSDAS P(2) S(1) Sr(3) P(2) Notes: 1. Start condition 2. Stop condition 3. Retransmit start condition

R8C/32A Group 32. Electrical Characteristics REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 533 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Note: 1. V CC = 4.2 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), f(XIN) = 20 MHz, unless otherwise specified. Table 32.17 Electrical Characteristics (1) [V CC = 5 V] Symbol Parameter Condition Standard UnitMin. Typ. Max. VOH Output “H” voltage Drive capacity High I OH = −20 mA V CC − 2.0 − VCC V Drive capacity Low I OH = −5 mA V CC − 2.0 − VCC V VOL Output “L” voltage Drive capacity High I OL = 20 mA −− 2.0 V Drive capacity Low I OL = 5 mA −− 2.0 V VT+-VT- Hysteresis INT0, INT1, INT3, KI0, KI1, KI2, KI3, TRAIO, RXD0, CLK0, CLK2, SSI, SCL, SDA, SSO 0.1 0.5 − V RESET 0.1 1.0 − V IIH Input “H” current VI = 5 V −− 5.0 µA IIL Input “L” current VI = 0 V −− − 5.0 µA RPULLUP Pull-up resistance VI = 0 V 30 50 167 k Ω RfXIN Feedback resistance XIN − 1.0 − MΩ RfXCIN Feedback resistance XCIN − 18 − MΩ VRAM RAM hold voltage During stop mode 1.8 −− V

R8C/32A Group 32. Electrical Characteristics REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 534 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Table 32.18 Electrical Characteristics (2) [Vcc = 5 V] (Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.) Symbol Parameter Condition Standard UnitMin. Typ. Max. ICC Power supply current (VCC = 3.3 to 5.5 V) Single-chip mode, output pins are open, other pins are V SS High-speed clock mode XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division − 6.5 20 mA XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division − 5.3 16 mA XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division − 3.5 − mA XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 − 2.5 − mA XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 − 2.1 − mA XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 − 1.5 − mA High-speed on-chip oscillator mode XIN clock off High-speed on-chip oscillator on fOCO = 20 MHz Low-speed on-chip oscillator on = 125 kHz No division − 6.5 TBD mA XIN clock off High-speed on-chip oscillator on fOCO = 20 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 − 2.5 − mA Low-speed on-chip oscillator mode XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR27 = 1, VCA20 = 1 − 50 400 µA Low-speed clock mode XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz FMR27 = 1, VCA20 = 1 − 60 400 µA XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz Program operation on RAM Flash memory off, FMSTP = 1, VCA20 = 1 − 30 −µ A Wait mode XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 − 15 TBD µA XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 − 4T B D µA XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (peripheral clock off) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 − 3.5 −µ A Stop mode XIN clock off, Topr = 25°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 − 2.0 TBD µA XIN clock off, Topr = 85°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 − 5.0 −µ A

R8C/32A Group 32. Electrical Characteristics REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 537 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Note: 1. V CC =2.7 to 3.3 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), f(XIN) = 10 MHz, unless otherwise specified. Table 32.23 Electrical Characteristics (3) [V CC = 3 V] Symbol Parameter Condition Standard UnitMin. Typ. Max. VOH Output “H” voltage Drive capacity High I OH = −5 mA V CC − 0.5 − VCC V Drive capacity Low I OH = −1 mA V CC − 0.5 − VCC V VOL Output “L” voltage Drive capacity High I OL = 5 mA −− 0.5 V Drive capacity Low I OL = 1 mA −− 0.5 V VT+-VT- Hysteresis INT0, INT1, INT3, KI0, KI1, KI2, KI3, TRAIO, RXD0, CLK0, CLK2, SSI, SCL, SDA, SSO 0.1 0.3 − V RESET 0.1 0.4 − V IIH Input “H” current VI = 3 V −− 4.0 µA IIL Input “L” current VI = 0 V −− − 4.0 µA RPULLUP Pull-up resistance VI = 0 V 66 160 500 k Ω RfXIN Feedback resistance XIN − 3.0 − MΩ RfXCIN Feedback resistance XCIN − 18 − MΩ VRAM RAM hold voltage During stop mode 1.8 −− V

R8C/32A Group 32. Electrical Characteristics REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 538 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Table 32.24 Electrical Characteristics (4) [Vcc = 3 V] (Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.) Symbol Parameter Condition Standard UnitMin. Typ. Max. ICC Power supply current (VCC = 2.7 to 3.3 V) Single-chip mode, output pins are open, other pins are VSS High-speed clock mode XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division − 3.5 − mA XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 − 1.5 − mA High-speed on-chip oscillator mode XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz No division − 5.5 TBD mA XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 − 1.5 − mA Low-speed on-chip oscillator mode XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR27 = 1, VCA20 = 1 − 50 400 µA Low-speed clock mode XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz FMR27 = 1, VCA20 = 1 − 60 400 µA XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz Program operation on RAM Flash memory off, FMSTP = 1, VCA20 = 1 − 30 −µ A Wait mode XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 − 15 TBD µA XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 − 4T B D µA XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (peripheral clock off) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 − 3.5 −µ A Stop mode XIN clock off , Topr = 25°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 − 2.0 TBD µA XIN clock off, Topr = 85°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 − 5.0 −µ A

R8C/32A Group 32. Electrical Characteristics REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 541 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Note: 1. V CC = 1.8 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), f(XIN) = 5 MHz, unless otherwise specified. Table 32.29 Electrical Characteristics (5) [V CC = 2.2 V] Symbol Parameter Condition Standard UnitMin. Typ. Max. VOH Output “H” voltage Drive capacity High I OH = −2 mA V CC − 0.5 − VCC V Drive capacity Low I OH = −1 mA V CC − 0.5 − VCC V VOL Output “L” voltage Drive capacity High I OL = 2 mA −− 0.5 V Drive capacity Low I OL = 1 mA −− 0.5 V VT+-VT- Hysteresis INT0, INT1, INT3, KI0, KI1, KI2, KI3, TRAIO, RXD0, CLK0, CLK2, SSI, SCL, SDA, SSO 0.05 0.3 − V RESET 0.05 0.15 − V IIH Input “H” current VI = 1.8 V −− 4.0 µA IIL Input “L” current VI = 0 V −− − 4.0 µA RPULLUP Pull-up resistance VI = 0 V 100 200 600 k Ω RfXIN Feedback resistance XIN − 5 − MΩ RfXCIN Feedback resistance XCIN − 35 − MΩ VRAM RAM hold voltage During stop mode 1.8 −− V

R8C/32A Group 32. Electrical Characteristics REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 542 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Table 32.30 Electrical Characteristics (6) [Vcc = 2.2 V] (Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.) Symbol Parameter Condition Standard UnitMin. Typ. Max. ICC Power supply current (VCC = 1.8 to 2.7 V) Single-chip mode, output pins are open, other pins are VSS High-speed clock mode XIN = 5 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division − 2.2 − mA XIN = 5 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 − 0.8 − mA High-speed on-chip oscillator mode XIN clock off High-speed on-chip oscillator on fOCO = 5 MHz Low-speed on-chip oscillator on = 125 kHz No division − 4 − mA XIN clock off High-speed on-chip oscillator on fOCO = 5 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 − 1.7 − mA Low-speed on- chip oscillator mode XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR27 = 1, VCA20 = 1 − 50 300 µA Low-speed clock mode XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz FMR27 = 1, VCA20 = 1 − 60 350 µA XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz Program operation on RAM Flash memory off, FMSTP = 1, VCA20 = 1 − 30 −µ A Wait mode XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 − 15 TBD µA XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 − 4T B D µA XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (peripheral clock off) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 − 3.5 −µ A Stop mode XIN clock off , Topr = 25°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 − 2.0 TBD µA XIN clock off, Topr = 85°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 − 5.0 −µ A

R8C/32A Group 33. Usage Notes REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 545 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 33. Usage Notes

33.1 Notes on Clock Generation Circuit

33.1.1 Stop Mode

To enter stop mode, set the FMR01 bit in the FMR0 regi ster to 0 (CPU rewrite mode disabled) and then the CM10 bit in the CM1 register to 1 (stop mode). An instruction queue pre-reads 4 bytes from the instruction which sets the CM10 bit to 1 (stop mode) and the program stops. Insert at least four NOP instructions following the JM P.B instruction after the instruction which sets the CM10 bit to 1.

• Program example to enter stop mode BCLR 1,FMR0 ; CPU rewrite mode disabled BSET 0,PRCR ; Protect disabled FSET I ; Enable interrupt BSET 0,CM1 ; Stop mode JMP.B LABEL_001 LABEL_001: NOP NOP NOP NOP

33.1.2 Wait Mode

To enter wait mode with the WAIT instruction, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and then execute the WAIT instruction. An instruction queu e pre-reads 4 bytes from the WAIT instruction and the program stops. Insert at least four NOP instructions after the WAIT instruction.

• Program example to execute the WAIT instruction BCLR 1,FMR0 ; CPU rewrite mode disabled FSET I ; Enable interrupt WAIT ; Wait mode NOP NOP NOP NOP

33.1.3 Oscillation Stop Detection Function

Since the oscillation stop detection function cannot be used if the XIN clock frequency is below 2 MHz, set bits OCD1 to OCD0 to 00b.

33.1.4 Oscillation Circuit Constants

Consult the oscillator manufacturer to determine the optimal oscillation circuit constants for the user system. To use the MCU with supply voltage below VCC = 2.7 V , it is recommended to set the CM11 bit in the CM1 register to 1 (on-chip feedback resistor disabled) and connect the feedback resistor to the chip externally.

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33.2 Notes on Interrupts

33.2.1 Reading Address 00000h

Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At this time, the IR bit for the acknowledged interrupt is set to 0. If address 00000h is read by a program, the IR bit for the interrupt which has the highest priority among the enabled interrupts is set to 0. This may cause the interrupt to be cancel ed, or an unexpected interrupt to be generated.

33.2.2 SP Setting

Set a value in the SP before an interrupt is acknowledged. The SP is set to 0000h after a reset. If an interrupt is acknowledged before setting a value in the SP, the program may run out of control.

33.2.3 External Interrupt and Key Input Interrupt

Either the “L” level width or “H” level width shown in the Electrical Characteristic s is required for the signal input to pins INT0, INT1, INT3 and pins KI0 to KI3, regardless of the CPU clock. For details, refer to Table 32.22 (VCC = 5V), Table 32.28 (VCC = 3V), Table 32.34 (VCC = 2.2V) External Interrupt INTi (i = 0, 1, 3) Input, Key Input Interrupt KIi (i = 0 to 3).

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33.2.4 Changing Interrupt Sources

The IR bit in the interrupt control register may be se t to 1 (interrupt requested) when the interrupt source changes. To use an interrupt, set the IR bit to 0 (no interrupt requested) after changing interrupt sources. Changing interrupt sources as referred to here includes all factors that change the source, polarity, or timing of the interrupt assigned to a software interrupt number. Therefore, if a m ode change of a peripheral function involves the source, polarity, or timing of an interrupt, set the IR bit to 0 (no interrupt requested) after making these changes. Refer to the descriptions of the individual peripheral functions for related interrupts. Figure 33.1 shows a Procedure Example for Changing Interrupt Sources. Figure 33.1 Procedure Example for Changing Interrupt Sources Notes: 1. The above settings must be executed individually. Do not execute two or more settings simultaneously (using one instruction). 2. To prevent interrupt requests from being generated disable the peripheral function before changing the interrupt source. In this case, use the I flag if all maskable interrupts can be disabled. If all maskable interrupts cannot be disabled, use bits ILVL0 to ILVL2 for the interrupt whose source is to be changed. 3. Refer to 11.8.5 Rewriting Interrupt Control Register for the instructions to use and related notes. Interrupt source change Disable interrupts (2, 3) Set the IR bit to 0 (no interrupt request) using the MOV instruction (3) Change interrupt sources (including mode of peripheral function) Enable interrupts (2, 3) Change completed IR bit: The interrupt control register bit for the interrupt whose source is to be changed

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33.2.5 Rewriting Interr upt Control Register

(a) The contents of the interrupt control register can be rewritten only while no interrupt requests corresponding to that regist er are generated. If an interrupt reques t may be generated, disable the interrupt before rewriting the contents of the interrupt control register. (b) When rewriting the contents of the interrupt control register after disabling th e interrupt, be careful to choose appropriate instructions. Changing any bit other than the IR bit If an interrupt request corresponding to the register is generated while executing the instruction, the IR bit may not be set to 1 (interrupt requested), and the interrupt may be ignored. If this causes a problem, use one of the following instructions to rewrite the contents of the register: AND, OR, BCLR, and BSET. Changing the IR bit Depending on the instruction used, the IR bit may not be set to 0 (no interrupt requested). Use the MOV instruction to set the IR bit to 0. (c) When using the I flag to disable an interrupt, set the I flag as shown in the sample programs below. Refer to (b) regarding rewriting the contents of interrupt control registers using the sample programs. Examples 1 to 3 shows how to prevent the I flag from being set to 1 (interrupts enabled) before the contents of the interrupt control register are rewritten for the effects of the internal bus and the instruction queue buffer. Example 1: Use the NOP instructions to pause program until the interrupt control register is rewritten INT_SWITCH1: FCLR I ; Disable interrupts AND.B #00H,0056H ; Set the TRAIC register to 00h NOP ; NOP FSET I ; Enable interrupts Example 2: Use a dummy read to delay the FSET instruction INT_SWITCH2: FCLR I ; Disable interrupts AND.B #00H,0056H ; Set the TRAIC register to 00h MOV .W MEM,R0 ; Dummy read FSET I ; Enable interrupts Example 3: Use the POPC inst ruction to change the I flag INT_SWITCH3: PUSHC FLG FCLR I ; Disable interrupts AND.B #00H,0056H ; Set the TRAIC register to 00h POPC FLG ; Enable interrupts

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33.3 Notes on ID Code Areas

33.3.1 Setting Example of ID Code Areas

As the ID code areas are allocated in the flash memory (not in the SFRs), they cannot be rewritten by executing an instruction. Write appropriate values when creating a program. The following shows a setting example.

• To set 55h in all of the ID code areas .org 00FFDCH .lword dummy | (55000000h) ; UND .lword dummy | (55000000h) ; INTO .lword dummy ; BREAK .lword dummy | (55000000h) ; ADDRESS MATCH .lword dummy | (55000000h) ; SET SINGLE STEP .lword dummy | (55000000h) ; WDT .lword dummy | (55000000h) ; ADDRESS BREAK .lword dummy | (55000000h) ; RESERVE (Programming formats vary depending on the compiler. Check the compiler manual.)

33.4 Notes on Option Function Select Area

33.4.1 Setting Example of Op tion Function Select Area

As the option function select area is allocated in the flash memory (not in the SFRs), they cannot be rewritten by executing an instruction. Write appropriate values when creating a program. The following shows a setting example.

• To set FFh in the OFS register .org 00FFFCH .lword reset | (0FF000000h) ; RESET (Programming formats vary depending on the compiler. Check the compiler manual.)

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33.5 Notes on DTC

33.5.1 DTC activation source

• Do not generate any DTC activation sources before entering wait mode or during wait mode.
• Do not generate any DTC activation sources before entering stop mode or during stop mode.

33.5.2 DTCENi Registers (i = 0 to 3, 5, 6)

• Modify bits DTCENi0 to DTCENi1, and bits DT CENi3 to DTCENi7 only while an interrupt request corresponding to the bit is not generated.
• When the interrupt source flag in the status register for the peripheral function is 1, do not modify the corresponding activation source bit among bits DTCENi0 to DTCENi1, and bits DTCENi3 to DTCENi7.
• Do not access the DTCENi registers using DTC transfers.

33.5.3 Peripheral Modules

• Do not set the status register bit for the peripheral function to 0 using a DTC transfer.
• When the DTC activation source is I 2C bus/SSU receive data full, read the SSRDR register/the ICDRR register using a DTC transfer.
• When the DTC activation source is I2C bus/SSU transmit data empty, write to the SSTDR register/the ICDRT register using a DTC transfer.

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33.6 Notes on Timer RA

• Timer RA stops counting after a reset. Set the values in the timer RA and timer RA prescalers before the count starts.
• Even if the prescaler and timer RA are read out in 16-bit units, these register s are read 1 byte at a time by the MCU. Consequently, the timer value may be updated during the period when these two registers are being read.
• In pulse period measurement mode, bits TEDGF and TUNDF in the TRACR register can be set to 0 by writing 0 to these bits by a program. However, these bits re main unchanged if 1 is written. When using the READ- MODIFY-WRITE instruction for the TRACR register, the TEDGF or TUNDF bit may be set to 0 although these bits are set to 1 while the instruction is being executed. In this case, write 1 to the TEDGF or TUNDF bit which is not supposed to be set to 0 with the MOV instruction.
• When changing to pulse period measurement mode from another mode, the contents of bits TEDGF and TUNDF are undefined. Write 0 to bits TEDGF and TUNDF before the count starts.
• The TEDGF bit may be set to 1 by the first timer RA prescaler underflow generated after the count starts.
• When using the pulse period measurement mode, leave two or more periods of the timer RA prescaler immediately after the count starts, then set the TEDGF bit to 0.
• The TCSTF bit retains 0 (count stops) for 0 to 1 cycle of the count source after setting the TSTART bit to 1 (count starts) while the count is stopped. During this time, do not access regi sters associated with timer RA (1) other than the TCSTF bit. Timer RA starts counting at the first valid edge of the count source after The TCSTF bit is set to 1 (during count). The TCSTF bit remains 1 for 0 to 1 cycle of the count source after setting the TSTART bit to 0 (count stops) while the count is in progress. Timer RA counting is stopped when the TCSTF bit is set to 0. During this time, do not access registers associated with timer RA (1) other than the TCSTF bit. Note: 1. Registers associated with timer RA: TRACR, TRAIOC, TRAMR, TRAPRE, and TRA.
• When the TRAPRE register is continuously written during count operation (TCSTF bit is set to 1), allow three or more cycles of the count source clock for each write interval.
• When the TRA register is continuously written during count operation (TCSTF bit is set to 1), allow three or more cycles of the prescaler underflow for each write interval.

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33.7 Notes on Timer RB

• Timer RB stops counting after a reset. Set the values in the timer RB and timer RB prescalers before the count starts.
• Even if the prescaler and timer RB is read out in 16-bit units, these registers are read 1 byte at a time by the MCU. Consequently, the timer value may be updated during the period when these two registers are being read.
• In programmable one-shot generation mode and programma ble wait one-shot generation mode, when setting the TSTART bit in the TRBCR register to 0, 0 (stops counting) or setting the TOSSP bit in the TRBOCR register to 1 (stops one-shot), the timer reloads th e value of reload register and stops. Therefore, in programmable one-shot generation mode and programmable wait one-shot generation mode, read the timer count value before the timer stops.
• The TCSTF bit remains 0 (count stops) for 1 to 2 cycles of the count source after setting the TSTART bit to 1 (count starts) while the count is stopped. During this time, do not access registers associated with timer RB (1) other than the TCSTF bit. Timer RB starts counting at the first valid edge of the count source after the TCSTF bit is set to 1 (during count). The TCSTF bit remains 1 for 1 to 2 cycles of the count source after setting the TSTART bit to 0 (count stops) while the count is in progress. Timer RB counting is stopped when the TCSTF bit is set to 0. During this time, do not access registers associated with timer RB (1) other than the TCSTF bit. Note: 1. Registers associated with timer RB: TRBCR, TRBOCR, TRBIOC , TRBMR, TRBPRE, TRBSC, and TRBPR.
• If the TSTOP bit in the TRBCR register is set to 1 during timer operation, timer RB stops immediately.
• If 1 is written to the TOSST or TOSSP bit in the TRBO CR register, the value of the TOSSTF bit changes after one or two cycles of the count source have elapsed. If the TOSSP bit is written to 1 during the period between when the TOSST bit is written to 1 and when the TOSSTF bit is set to 1, the TOSSTF bit may be set to either 0 or 1 depending on the content state. Likewise, if the TOSST bit is written to 1 during the period between when the TOSSP bit is written to 1 and when the TOSSTF bit is set to 0, the TOSSTF bit may be set to either 0 or 1.

33.7.1 Timer Mode

To write to registers TRBPRE and TRBPR during count op eration (TCSTF bit in the TRBCR register is set to 1), note the following points:

• When the TRBPRE register is writte n continuously, allow three or more cycles of the count source for each write interval.
• When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for each write interval.

33.7.2 Programmable Waveform Generation Mode

To write to registers TRBPRE and TRBPR during count op eration (TCSTF bit in the TRBCR register is set to 1), note the following points:

• When the TRBPRE register is writte n continuously, allow three or more cycles of the count source for each write interval.
• When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for each write interval.

33.7.3 Programmable One-shot Generation Mode

To write to registers TRBPRE and TRBPR during count op eration (TCSTF bit in the TRBCR register is set to 1), note the following points:

• When the TRBPRE register is written continuously during count operation (TCSTF bit is set to 1), allow three or more cycles of the count source for each write interval.
• When the TRBPR register is written continuously during count operation (TCSTF bit is set to 1), allow three or more cycles of the prescaler underflow for each write interval.

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33.7.4 Programmable Wait One-shot Generation Mode

To write to registers TRBPRE and TRBPR during count op eration (TCSTF bit in the TRBCR register is set to 1), note the following points:

• When the TRBPRE register is writte n continuously, allow three or more cycles of the count source for each write interval.
• When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for each write interval.

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33.8 Notes on Timer RC

33.8.1 TRC Register

• The following note applies when the CCLR bit in the TRCCR1 register is set to 1 (clear TRC register at compare match with TRCGRA register). When using a program to write a valu e to the TRC register while the TSTART bit in the TRCMR register is set to 1 (count starts), ensure that the write does not overlap with the timing with which the TRC register is set to 0000h. If the timing of the write to the TRC register and the setting of the TRC register to 0000h coincide, the write value will not be written to the TRC register and the TRC register will be set to 0000h.
• Reading from the TRC register immedi ately after writing to it can result in the value previous to the write being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions. Program Example MOV .W #XXXXh, TRC ;Write JMP.B L1 ;JMP.B instruction L1: MOV .W TRC,DATA ;Read

33.8.2 TRCSR Register

Reading from the TRCSR register immediately after writin g to it can result in the value previous to the write being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions. Program Example MOV .B #XXh, TRCSR ;Write JMP.B L1 ;JMP.B instruction L1: MOV .B TRCSR,DATA ;Read

33.8.3 TRCCR1 Register

To set bits TCK2 to TCK0 in the TRCCR1 register to 111b (fOCO-F), set fOCO-F to the clock frequency higher than the CPU clock frequency.

33.8.4 Count Source Switching

• Stop the count before switching the count source. Switching procedure (1) Set the TSTART bit in the TRCMR register to 0 (count stops). (2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register.
• After switching the count source from fOCO40M to another clock, allow a minimum of two cycles of f1 to elapse after changing the clock setting before stopping fOCO40M. Switching procedure (1) Set the TSTART bit in the TRCMR register to 0 (count stops). (2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register. (3) Wait for a minimum of two cycles of f1. (4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator off).

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• After switching the count source from fOCO-F to fOCO40M, allow a minimum of two cycles of fOCO-F to elapse after changing the clock setting before stopping fOCO-F. Switching procedure (1) Set the TSTART bit in the TRCMR register to 0 (count stops). (2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register. (3) Wait for a minimum of two cycles of fOCO-F. (4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator off).
• After switching the count source from fOCO-F to a clock other than fOCO40M, allow a minimum of one cycle of fOCO-F + fOCO40M to elapse after changing the clock setting before stopping fOCO-F. Switching procedure (1) Set the TSTART bit in the TRCMR register to 0 (count stops). (2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register. (3) Wait for a minimum of one cycle of fOCO-F + fOCO40M. (4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator off).

33.8.5 Input Capture Function

• The pulse width of the input capture signal should be three cycles or more of the timer RC operation clock (refer to Table 19.1 Timer RC Operation Clock).
• The value of the TRC register is tr ansferred to the TRCGRj register one or two cycles of the timer RC operation clock after the input capture signal is input to the TRCIOj (j = A, B, C, or D) pin (when the digital filter function is not used).

33.8.6 TRCMR Regist er in PWM2 Mode

When the CSEL bit in the TRCCR2 register is set to 1 (count stops at compare match with the TRCGRA register), do not set the TRCMR register at compare match timing of registers TRC and TRCGRA.

33.8.7 Count Source fOCO40M

The count source fOCO40M can be used with supply voltage VCC = 2.7 to 5.5 V . For supply voltage other than that, do not set bits TCK2 to TCK0 in the TRCCR1 register to 110b (select fOCO40M as the count source).

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33.9 Notes on Timer RE

33.9.1 Starting and Stopping Count

Timer RE has the TSTART bit for instructing the count to start or stop, and the TCSTF bit, which indicates count start or stop. Bits TSTART and TCSTF are in the TRECR1 register. Timer RE starts counting and the TCSTF bit is set to 1 (count starts) when the TSTART bit is set to 1 (count starts). It takes up to 2 cycles of the count source until the TCSTF bit is set to 1 after setting the TSTART bit to 1. During this time, do not access registers associated with timer RE (1) other than the TCSTF bit. Also, timer RE stops counting when setting the TSTART bit to 0 (count stops) and the TCSTF bit is set to 0 (count stops). It takes the time for up to 2 cycles of the count source until the TCSTF bit is set to 0 after setting the TSTART bit to 0. During this time, do not access registers associated with timer RE other than the TCSTF bit. Note: 1. Registers associated with timer RE: TRESEC, TREMIN, TREHR, TREWK, TRECR1, TRECR2, and TRECSR.

33.9.2 Register Setting

Write to the following registers or bits when timer RE is stopped.

• Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2
• Bits H12_H24, PM, and INT in TRECR1 register
• Bits RCS0 to RCS3 in TRECSR register Timer RE is stopped when bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer RE stopped). Also, set all above-mentioned registers and bits (immedia tely before timer RE count starts) before setting the TRECR2 register. Figure 33.2 shows a Setting Example in Real-Time Clock Mode.

R8C/32A Group 33. Usage Notes REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 557 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Figure 33.2 Setting Example in Real-Time Clock Mode Stop timer RE operation TCSTF in TRECR1 = 0? TSTART in TRECR1 = 0 TRERST in TRECR1 = 1 TRERST in TRECR1 = 0 Setting of registers TRECSR, TRESEC, TREMIN, TREHR, TREWK, and bits H12_H24, PM, and INT in TRECR1 register Setting of TRECR2 TSTART in TRECR1 = 1 TCSTF in TRECR1 = 1? TREIC ← 00h (disable timer RE interrupt) Setting of TREIC (IR bit ← 0, select interrupt priority level) Timer RE register and control circuit reset Select clock output Select clock source Seconds, minutes, hours, days of week, operating mode Set a.m./p.m., interrupt timing Select interrupt source Start timer RE operation

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33.9.3 Time Reading Procedur e of Real-Time Clock Mode

In real-time clock mode, read registers TRESEC, TR EMIN, TREHR, and TREWK wh en time data is updated and read the PM bit in the TRECR1 register when the BSY bit is set to 0 (not while data is updated). Also, when reading several registers, an incorrect time will be r ead if data is updated before another register is read after reading any register. In order to prevent this, use the reading procedure shown below.

• Using an interrupt Read necessary contents of registers TRESEC, TR EMIN, TREHR, and TREWK and the PM bit in the TRECR1 register in the timer RE interrupt routine.
• Monitoring with a program 1 Monitor the IR bit in the TREIC register with a prog ram and read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register after the IR bit in the TREIC register is set to 1 (timer RE interrupt request generated).
• Monitoring with a program 2 (1) Monitor the BSY bit. (2) Monitor until the BSY bit is set to 0 after the BSY bi t is set to 1 (approximately 62.5 ms while the BSY bit is set to 1). (3) Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register after the BSY bit is set to 0.
• Using read results if they are the same value twice (1) Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register. (2) Read the same register as (1) and compare the contents. (3) Recognize as the correct value if the contents match. If the contents do not ma tch, repeat until the read contents match with the previous contents. Also, when reading several registers, read them as continuously as possible.

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33.10 Notes on Serial Interface (UART0)

• When reading data from the U0RB register either in clock synchronous serial I/O mode or in clock asynchronous serial I/O mode, always read data in 16-bit units. When the high-order byte of the U0RB register is read, bits PER and FER in the U0RB register and the RI bit in the U0C1 register are set to 0. To check receive errors, read the U0RB register and then use the read data. Program example to read the receive buffer register: MOV .W 00A6H,R0 ; Read the U0RB register
• When writing data to the U0TB register in clock asynch ronous serial I/O mode with 9-bit transfer data length, write data to the high-order byte first and then the low-order byte, in 8-bit units. Program example to write to the transmit buffer register: MOV .B #XXH,00A3H ; Write to the high-order byte of the U0TB register MOV .B #XXH,00A2H ; Write to the low-order byte of the U0TB register

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33.11 Notes on Serial Interface (UART2)

33.11.1 Clock Synchronous Serial I/O Mode

33.11.1.1 Transmission/Reception

When the RTS function is used with an external clock, the RTS2 pin outputs “L,” which informs the transmitting side that the MCU is re ady for a receive operation. The RTS2 pin outputs “H” when a receive operation starts. Therefore, the transmit timing and receive timing can be synchronized by connecting the RTS2 pin to the CTS2 pin of the transmitting side. The RTS function is disabled when an internal clock is selected.

33.11.1.2 Transmission

If an external clock is selected, the following conditions must be met while the external clock is held high when the CKPOL bit in the U2C0 register is set to 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock), or while the exte rnal clock is held low when the CKPOL bit is set to 1 (transmit data output at the rising edge and receive data input at the falling edge of the transfer clock).

• The TE bit in the U2C1 register = 1 (transmission enabled)
• The TI bit in the U2C1 register = 0 (data present in the U2TB register)
• If the CTS function is selected, input on the CTS2 pin = “L”

33.11.1.3 Reception

In clock synchronous serial I/O mode, the shift clock is generated by activating the transmitter. Set the UART2- associated registers for transmit ope ration even if the MCU is used for receive operation only. Dummy data is output from the TXD2 pin while receiving. When an internal clock is selected, the shift clock is ge nerated by setting the TE bit in the U2C1 register to 1 (transmission enabled) and placing dummy data in the U2TB register. When an external clock is selected, set the TE bit to 1 (transmission enabled), place dummy data in the U2TB register, and input an external clock to the CLK2 pin to generate the shift clock. If data is received consecutively, an overrun error occurs when the RE bit in the U2C1 register is set to 1 (data present in the U2RB register) and the next receive data is received in the UART2 receive register. Then, the OER bit in the U2RB register is set to 1 (overrun error). At this time, the U2RB register value is undefined. If an overrun error occurs, the IR bit in the S2RIC register remains unchanged. To receive data consecutively, set du mmy data in the low-order byte in the U2TB register per each receive operation. If an external clock is selected, the following conditions must be met while the external clock is held high when the CKPOL bit is set to 0, or while the external clock is held low when the CKPOL bit is set to 1.

• The RE bit in the U2C1 register = 1 (reception enabled)
• The TE bit in the U2C1 register = 1 (transmission enabled)
• The TI bit in the U2C1 register = 0 (data present in the U2TB register)

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33.11.2 Clock Asynchronous Serial I/O (UART) Mode

33.11.2.1 Transmission/Reception

When the RTS function is used with an external clock, the RTS2 pin outputs “L,” which informs the transmitting side that the MCU is re ady for a receive operation. The RTS2 pin outputs “H” when a receive operation starts. Therefore, the transmit timing and receive timing can be synchronized by connecting the RTS2 pin to the CTS2 pin of the transmitting side. The RTS function is disabled when an internal clock is selected.

33.11.2.2 Transmission

If an external clock is selected, the following conditions must be met while the external clock is held high when the CKPOL bit in the U2C0 register is set to 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock), or while the exte rnal clock is held low when the CKPOL bit is set to 1 (transmit data output at the rising edge and receive data input at the falling edge of the transfer clock).

• The TE bit in the U2C1 register = 1 (transmission enabled)
• The TI bit in the U2C1 register = 0 (data present in the U2TB register)
• If the CTS function is selected, input on the CTS2 pin = “L”

33.11.3 Special Mode 1 (I 2C Mode)

When generating start, stop, and rest art conditions, set the STSPSEL bit in the U2SMR4 register to 0 and wait for more than half cycle of the transfer clock before changing each condition generation bit (STAREQ, RSTAREQ, and STPREQ) from 0 to 1.

R8C/32A Group 33. Usage Notes REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 562 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

33.12 Notes on Synchronous Se rial Communication Unit

Set the IICSEL bit in the SSUIICSR register to 0 (select SSU function) to use the synchronous serial communication unit function.

33.13 Notes on I 2C bus Interface

To use the I 2C bus interface, set the IICSEL bit in the SSUIICSR register to 1 (I 2C bus interface function selected).

33.14 Notes on Hardware LIN

For the time-out processing of the head er and response fields, use another timer to measure the duration of time with a Synch Break detection interrupt as the starting point.

33.15 Notes on A/D Converter

• Write to the ADMOD register, the ADINSEL register, the ADCON0 register (other than ADST bit), the ADCON1 register, the OCVREFCR register when A/D conversion is stopped (before a trigger occurs).
• To use the A/D converter in repeat mode 0, repeat mode 1, or repeat sweep mode, select the frequency of the A/D converter operating clock φAD or more for the CPU clock during A/D conversion. Do not select fOCO-F as φAD.
• Connect 0.1 µF capacitor between the VREF pin and A VSS pin.
• Do not enter stop mode during A/D conversion.
• Do not enter wait mode during A/D conversion regardless of the state of the CM02 bit in the CM0 register (1: Peripheral function clock stops in wait mode or 0: Peripheral function clock does not stop in wait mode).
• Do not set the FMSTP bit in the FMR0 register to 1 (flash memory stops) during A/D conversion.

R8C/32A Group 33. Usage Notes REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 563 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

33.16 Notes on Flash Memory

33.16.1 CPU Rewrite Mode

33.16.1.1 Prohibited Instructions

The following instructions cannot be used while the program ROM area is being rewritten in EW0 mode because they reference data in the flash memory: UND, INTO, and BRK.

33.16.1.2 Non-Maskable Interrupts

Tables 33.1 and 33.2 show CPU Rewrite Mode Interrupts (1) and (2), respectively. FMR21, FMR22: Bits in FMR2 register Note: 1. Do not use a non-maskable interrupt while block 0 is being auto-erased because the fixed vector is allocated in block 0. Table 33.1 CPU Rewrite Mode Interrupts (1) Mode Erase/ Write Target Status Maskable Interrupt • Address Match

• Address Break (Note 1) EW0 Data flash During auto-erasure (suspend enabled) When an interrupt request is acknowledged, interrupt handling is executed. If the FMR22 bit is set to 1 (erase-suspend request enabled by interrupt request), the FMR21 bit is automatically set to 1 (erase-suspend request). The flash memory suspends auto-erasure after td(SR-SUS). If erase-suspend is required while the FMR22 bit is set to 0 (erase-suspend request disabled by interrupt request), set the FMR 21 bit to 1 during interrupt handling. The flash memory suspends auto-erasure after td(SR-SUS). While auto-erasure is being suspended, any block other than the block during auto- erasure execution can be read. Auto-erasure can be restarted by setting the FMR21 bit to 0 (erase restart). During auto-erasure (suspend disabled or FMR22 = 0) Interrupt handling is executed while auto-erasure or auto-programming is being performed. During auto-programming Program ROM During auto-erasure (suspend enabled) Usable by allocating a vector in RAM. Not usable during auto-erasure or auto-programming. During auto-erasure (suspend disabled) During auto-programming EW1 Data flash During auto-erasure (suspend enabled) When an interrupt request is acknowledged, interrupt handling is executed. If the FMR22 bit is set to 1, the FMR21 bit is automatically set to 1. The flash memory suspends auto-erasure after td(SR-SUS). If erase-suspend is required while the FMR22 bit is set to 0, set the FMR 21 bit to 1 during interrupt handling. The flash memory suspends auto-erasure after td(SR-SUS). While auto-erasure is being suspended, any block other than the block during auto- erasure execution can be read. Auto-erasure can be restarted by setting the FMR21 bit to 0. During auto-erasure (suspend disabled or FMR22 = 0) Interrupt handling is executed while auto-erasure or auto-programming is being performed. During auto-programming Program ROM During auto-erasure (suspend enabled) Auto-erasure suspends after td(SR-SUS) and interrupt handling is executed. Auto- erasure can be restarted by setting the FMR21 bit to 0 after interrupt handling completes. While auto-erasure is being suspended, any block other than the block during auto- erasure execution can be read. During auto-erasure (suspend disabled or FMR22 = 0) Auto-erasure and auto-programming have priority and interrupt requests are put on standby. Interrupt handling is executed after auto-erase and auto-program complete. During auto-programming

R8C/32A Group 33. Usage Notes REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 564 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. FMR21, FMR22: Bits in FMR2 register Note: 1. Do not use a non-maskable interrupt whil e block 0 is being auto-erased because the fixed vector is allocated in block 0. Table 33.2 CPU Rewrite Mode Interrupts (2) Mode Erase/ Write Target Status

• Watchdog Timer
• Oscillation Stop Detection
• Voltage Monitor 2
• Voltage Monitor 1
• NMI (Note 1)
• Undefined Instruction
• I N T O I n s t r u c t i o n
• BRK Instruction
• Single Step (Note 1) EW0 Data flash During auto-erasure (suspend enabled) When an interrupt request is acknowledged, interrupt handling is executed. If the FMR22 bit is set to 1 (erase-suspend request enabled by interrupt request), the FMR21 bit is automatically set to 1 (erase-suspend request). The flash memory suspends auto-erasure after td(SR-SUS). If erase-suspend is required while the FMR22 bit is set to 0 (erase-suspend request disabled by interrupt request), set the FMR 21 bit to 1 during interrupt handling. The flash memory suspends auto-erasure after td(SR-SUS). While auto-erasure is being suspended, any block other than the block during auto- erasure execution can be read. Auto-erasure can be restarted by setting the FMR21 bit is set to 0 (erase restart). During auto-erasure (suspend disabled or FMR22 = 0) Interrupt handling is executed while auto-erasure or auto-programming is being performed. During auto-programming Program ROM During auto-erasure (suspend enabled) When an interrupt request is acknowledged, auto-erasure or auto-programming is forcibly stopped immediately and the flash memory is reset. Interrupt handling starts when the flash memory restarts after the fixed period. Since the block during auto-erasure or the address during auto-programming is forcibly stopped, the normal value may not be read. After the flash memory restarts, execute auto-erasure again and ensure it completes normally. The watchdog timer does not stop during the command operation, so interrupt requests may be generated. Initialize the watchdog timer regularly using the erase-suspend function. Not usable during auto-erasure or auto-programming. During auto-erasure (suspend disabled) During auto-programming EW1 Data flash During auto-erasure (suspend enabled) When an interrupt request is acknowledged, interrupt handling is executed. If the FMR22 bit is set to 1, the FMR21 bit is automatically set to 1. The flash memory suspends auto-erasure after td(SR-SUS). If erase-suspend is required while the FMR22 bit is set to 0, set the FMR 21 bit to 1 during interrupt handling. The flash memory suspends auto-programming after td(SR-SUS). While auto-erasure is being suspended, any block other than the block during auto- erasure execution can be read. Auto-erasure can be restarted by setting the FMR21 bit is set to 0. During auto-erasure (suspend disabled or FMR22 = 0) Interrupt handling is executed while auto-erasure or auto-programming is being performed. During auto-programming Program ROM During auto-erasure (suspend enabled) When an interrupt request is acknowledged, auto-erasure or auto-programming is forcibly stopped immediately and the flash memory is reset. Interrupt handling starts when the flash memory restarts after the fixed period. Since the block during auto-erasure or the address during auto-programming is forcibly stopped, the normal value may not be read. After the flash memory restarts, execute auto-erasure again and ensure it completes normally. The watchdog timer does not stop during the command operation, so interrupt requests may be generated. Initialize the watchdog timer regularly using the erase-suspend function. Not usable during auto-erasure or auto-programming. During auto-erasure (suspend disabled or FMR22 = 0) During auto-programming

R8C/32A Group 33. Usage Notes REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 565 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

33.16.1.3 How to Access

To set one of the following bits to 1, first write 0 and then 1 immediately. Do not generate an interrupt between writing 0 and writing 1.

• The FMR01 bit or FMR02 bit in the FMR0 register
• The FMR13 bit in the FMR1 register
• The FMR20 bit, FMR22 bit, or FMR 27 bit in the FMR2 register To set one of the following bits to 0, first write 1 and then 0 immediately. Do not generate an interrupt between writing 1 and writing 0.
• The FMR14 bit, FMR15 bit, FMR16 bit, or FMR17 bit in the FMR1 register

33.16.1.4 Rewriting User ROM Area

In EW0 Mode, if the supply voltage drops while rewr iting any block in which a rewrite control program is stored, it may not be possible to rewrite the flash memory because the rewrite control program cannot be rewritten correctly. In this case, use standard serial I/O mode.

33.16.1.5 Programming

Do not write additions to the already programmed address.

33.16.1.6 Entering Stop Mode or Wait Mode

Do not enter stop mode or wait mode during erase-suspend. If the FST7 in the FST register is set to 0 (busy (during programming or erasure execution), do not enter to stop mode or wait mode.

33.16.1.7 Programming and Erasu re Voltage for Flash Memory

To perform programming and erasure, use VCC = 2.7 V to 5.5 V as th e supply voltage. Do not perform programming and erasure at less than 2.7 V .

R8C/32A Group 33. Usage Notes REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 566 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change.

33.17 Notes on Noise

33.17.1 Inserting a Bypass Capacitor between VCC and VSS Pins as a Countermeasure

against Noise and Latch-up Connect a bypass capacitor (at least 0.1 µF) using the shortest and thickest write possible.

33.17.2 Countermeasures against Noise Er ror of Port Control Registers

During rigorous noise testing or the like, external noise (mainly power supply system noise) can exceed the capacity of the MCU's internal noise control circuitry. In such cases the contents of the port related registers may be changed. As a firmware countermeasure, it is recommended that the port registers, port direc tion registers, and pull-up control registers be reset periodically. However, examin e the control processing fully before introducing the reset routine as conflicts may be created between the reset routine and interrupt routines.

R8C/32A Group 34. Notes on On-Chip Debugger REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 567 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 34. Notes on On-Chip Debugger When using the on-chip debugger to develop and debug programs for the R8C/32A Group, take note of the following: (1) Some of the user flash memory and RAM areas are used by the on-ship debugger. These areas cannot be accessed by the user. Refer to the on-chip debugger manual for which areas are used. (2) Do not set the address match interrupt (registers AIER 0, AIER1, RMAD0, and RMAD1 and fixed vector tables) in a user system. (3) Do not use the BRK instruction in a user system. (4) Debugging is available under the condition of supply voltage VCC = 1.8 to 5.5 V . Set the supply voltage to 2.7 V or above for rewriting the flash memory. Connecting and using the on-chip debugger has some special restrictions. Refer to the on-chip debugger manual for details.

R8C/32A Group Appendix 1. Package Dimensions REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 568 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Appendix 1. Package Dimensions Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of the Renesas Technology website. y Index mark1 10 1120 F c bpe A D E HE INCLUDE TRIM OFFSET. DIMENSION "*3" DOES NOT NOTE) DO NOT INCLUDE MOLD FLASH. Detail F A1A2 L 0.320.220.17bp Previous CodeJEITA Package Code RENESAS Code PLSP0020JB-A 20P2F-A MASS[Typ.] 0.1gP-LSSOP20-4.4x6.5-0.65 0.20.150.13 MaxNomMin Dimension in Millimeters Symbol Reference 6.66.56.4D 4.54.44.3E 1.15A2 6.66.46.2 1.45A 0.20.10 0.70.50.3L 10°0° c 0.65e 0.10y HE 0.53 0.77

R8C/32A Group Appendix 2. Connection Examples betw een Serial Writer and On-Chip Debugging Emulator REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 569 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Appendix 2. Connection Examples b etween Serial Writer and On-Chip Debugging Emulator Appendix Figure 2.1 shows a Connection Example with M16C Flash Starter (M3A-0806) and Appendix Figure 2.2 shows a Connection Example with E8a Emulator (R0E00008AKCE00). Appendix Figure 2.1 Connection Example with M16C Flash Starter (M3A-0806) Appendix Figure 2.2 Connection Example with E8a Emulator (R0E00008AKCE00) Note: 1. An oscillation circuit must be connected, even when operating with the on-chip oscillator clock. RXD 4

7 VSS

1 VCC

(M3A-0806) RXD TXD VSS VCC TXD RESET Connect oscillation circuit (1) MODE R8C/32A Group Note: 1. It is not necessary to connect an oscillation circuit when operating with the on-chip oscillator clock. MODE 4.7kΩ ±10% E8a emulator (R0E00008AKCE00) RESET12 VSS

7 MODE

circuit (1) 4.7kΩ or more Open collector buffer User logic R8C/32A Group

R8C/32A Group Appendix 3. Example of Oscillation Evaluation Circuit REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 570 of 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Appendix 3. Example of Osc illation Evaluation Circuit Appendix Figure 3.1 shows an Example of Oscillation Evaluation Circuit. Appendix Figure 3.1 Example of Oscillation Evaluation Circuit Connect oscillation circuit Note: 1. After reset, the XIN and XCIN clocks are stopped. Write a program to oscillate the XIN and XCIN clocks. VSS VCC RESET R8C/32A Group

REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 571 of 572 R8C/32A Group Index Under development Preliminary specification Specifications in this manual are tentative and subject to change. [ A ] [ C ] [ D ] [ F ] [ I ] [ K ] [ L ] [ M ] [ O ] [ P ] [ R ] [ S ] [ T ] Index

REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 572 of 572 R8C/32A Group Index Under development Preliminary specification Specifications in this manual are tentative and subject to change. [ U ] [ V ] [ W ]

REVISION HISTORY R8C/32A Group Hardware Manual Rev. Date

Description

0.10 Apr 01, 2008 − First Edition issued

R8C/32A Group Hardware ManualREVISION HISTORY

R8C/32A Group Hardware Manual Publication Date: Rev.0.10 Apr 01, 2008 Published by: Sales Strategic Planning Div. Renesas Technology Corp. © 2008. Renesas Technology Corp., All rights reserved. Printed in Japan

2-6-2, Ote-machi, Chiyoda-ku, Tokyo,100-0004, Japan R8C/32A Group Hardware Manual