R8C-10

R8C-10 RENESAS | Alldatasheet

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.60 Jan 27, 2006 page 1 of 25 REJ03B0035-0160 REJ03B0035-0160 Rev.1.60 Jan 27, 2006 1. Overview This MCU is built using the high-performance silicon gate CMOS process using a R8C/Tiny Series CPU core and is packaged in a 32-pin plastic molded LQFP. This MCU operates using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, it is capable of executing instructions at high speed.

1.1 Applications

Electric household appliance, office equipment, housing equipment (sensor, security), general industrial equipment, audio, etc.

Rev.1.60 Jan 27, 2006 page 2 of 25 REJ03B0035-0160 R8C/10 Group 1. Overview Table 1.1 Performance outline

1.2 Performance Overview

Table 1.1. lists the performance outline of this MCU. Item Performance CPU Number of basic instructions 89 instructions Minimum instruction execution time62.5 ns (f(XIN) = 16 MHZ, VCC = 3.0 to 5.5 V) 100 ns (f(XIN) = 10 MHZ, VCC = 2.7 to 5.5 V) Operating mode Single-chip Address space 1M bytes Memory capacity See Table 1.2 “Product List” Peripheral Port Input/Output: 22 (including LED drive port), Input: 2 function LED drive port I/O port: 8 Timer Timer X: 8 bits x 1 channel, Timer Y: 8 bits x 1 channel, Timer Z: 8 bits x 1 channel (Each timer equipped with 8-bit prescaler) Timer C: 16 bits x 1 channel (Input capture circuit) Serial interface •1 channel Clock synchronous, UART

1 channel UART A/D converter 10-bit A/D converter: 1 circuit, 8 channels Watchdog timer 15 bits x 1 (with prescaler) Interrupt Internal: 9 factors, External: 5 factors, Software: 4 factors, Priority level: 7 levels Clock generation circuit 2 circuits
Main clock generation circuit (Equipped with a built-in feedback resistor)
On-chip oscillator Oscillation stop detection functionMain clock oscillation stop detection function Electrical Supply voltage V CC = 3.0 to 5.5 V (f(XIN) = 16 MHZ) characteristics VCC = 2.7 to 5.5 V (f(XIN) = 10 MHZ) Power consumption Typ. 8mA (VCC = 5.0 V, (f(XIN) = 16MHZ) Typ. 5mA (VCC = 3.0 V, (f(XIN) = 10MHZ) Typ. 35µA (VCC = 3.0 V, Wait mode, Peripheral clock off) Typ. 0.7µA (VCC = 3.0 V, Stop mode) Flash memory Program/erase supply voltageVCC = 2.7 to 5.5 V Program/erase endurance 100 times Operating ambient temperature -20 to 85 °C -40 to 85 °C (D-version) Package 32-pin plastic mold LQFP

Rev.1.60 Jan 27, 2006 page 3 of 25 REJ03B0035-0160 R8C/10 Group 1. Overview

1.3 Block Diagram

Figure 1.1 shows this MCU block diagram. Figure 1.1 Block Diagram T i m e r X b i t s T i m e r Y b i t s T i m e r Z b i t s T i m e r C b i t s W a t c h d o g t i m e r b i t s M e m o r y R O M R 8 C / T i n y S e r i e s C P U c o r e I / O p o r t P o r t P 0 Port P1 P o r t P 3 M u l t i p l i e r System clock generator XI N - XO U T O n c h i p o s c i l l a t o r U A R T b i t s c h a n n e l Port P4 1 2 Pe r i p h e r a l f u n c t i o n s U A R T o r C l o c k s y n c h r o n o u s s e r i a l I O b i t s c h a n n e l A D c o n v e r t e r b i t s c h a n n e l s RAM NOTES: 1. ROM size depends on MCU type. 2. RAM size depends on MCU type. R 0 LR 0 H R1H R1L R 2 R 3 A 0 FB SB I S P USP INTB P C FLG T i m e r (2)

Rev.1.60 Jan 27, 2006 page 4 of 25 REJ03B0035-0160 R8C/10 Group 1. Overview

1.4 Product Information

Table 1.2 lists the product inforamation. Table 1.2 Product Information RAM capacityROM capacity Package type RemarksType No. As of January 2006 Flash memory versionR5F21102FP PLQP0032GB-A8K bytes 512 bytes PLQP0032GB-A12K bytes 768 bytes PLQP0032GB-A16K bytes 1K bytes R5F21103FP R5F21104FP R5F21102DFP PLQP0032GB-A8K bytes 512 bytes PLQP0032GB-A12K bytes 768 bytes PLQP0032GB-A16K bytes 1K bytes R5F21103DFP R5F21104DFP D version Figure 1.2 Type No., Memory Size, and Package Package type: FP : PLQP0032GB-A ROM capacity: 2 : 8 KBytes. 3 : 12 KBytes. 4 : 16 KBytes. Memory type: F: Flash memory version T y p e N o .R 5 F 2 11 04D F P R8C/10 group R8C/Tiny series Classification: D: Operating ambient temperature –40 °C to 85 °C No symbol: Operating ambient temperature –20 °C to 85 °C Renesas MCU Renesas semiconductors

Rev.1.60 Jan 27, 2006 page 5 of 25 REJ03B0035-0160 R8C/10 Group 1. Overview Figure 1.3 Pin Assignments (Top View) PIN CONFIGURATION (top view) 1 2 3 4 5 6 7 8 1 0 1 1 1 2 1 3 1 4 1 5 1 6 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 3 2 3 1 3 0 R 8 C / 1 0 G r o u pXI N / P 46 XO U T/ P 47 VS S R E S E T VC C C N VS S P 17/ I N T1/ C N T R 0 P 16/ C L K0 P15/RxD0 P 14/ T x D 0 P 37/ T x D 1 0/ R x D 1 P 30/ C N T R 0 P 33/ I N T3/ T C I N P 31/ T ZO U T P 32/ I N T2/ C N T R 1 I VC C A VS S A VC C / VR E F P03/AN4 P 02/ A N 5 P 01/ A N 6 P 00/ A N 7/T x D 1 P 06/ A N 1 P05/AN2 P 04/ A N 3 P45/INT0 P 10/ K I0 P 11/ K I1 P 12/ K I2 P 13/ K I3 P 07/ A N 0 M O D E NOTES: 1. P47 functions only as an input port. 2. When using On-chip debugger, do not use pins P00/AN7/TxD11 and P37/TxD10/RxD1. 3. Do not connect IVcc to Vcc.

1.5 Pin Assignment

Figure 1.3 shows the pin Assignments (top view).

Rev.1.60 Jan 27, 2006 page 6 of 25 REJ03B0035-0160 R8C/10 Group 1. Overview Signal name Pin name I/O type Power supply Vcc, I input Vss IVcc IVcc O Analog power AVcc, I supply input AVss Reset input RESET I CNVss CNVss I MODE MODE I Main clock input XIN I Main clock output XOUT O INT interrupt input INT0 to INT3 I Key input interrupt KI0 to KI3 I CNTR 0 O Timer Y CNTR 1 I/O Timer Z TZ OUT O Timer C TC IN I Serial interface CLK0 I/O RxD 0, RxD1 I TxD 0, TxD10,O TxD 11 Reference voltage VREF I input A/D converter AN 0 to AN7 I I/O port P0 0 to P07, I/O P10 to P17, P30 to P33, P37, P45 Input port P4 6, P47 I Function Apply 2.7 V to 5.5 V to the Vcc pin. Apply 0 V to the Vss pin. This pin is to stabilize internal power supply. Connect this pin to Vss via a capacitor (0.1 µF). Do not connect to Vcc. Power supply input pins for A/D converter. Connect the AVcc pin to Vcc. Connect the AVss pin to Vss. Connect a capacitor between pins AVcc and AVss. Input “L” on this pin resets the MCU. Connect this pin to Vss via a resistor. Connect this pin to Vcc via a resistor. These pins are provided for the main clock generat- ing circuit I/O. Connect a ceramic resonator or a crys- tal oscillator between the XIN and XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open.______ INT interrupt input pins. Key input interrupt pins. Timer X I/O pin Timer X output pin Timer Y I/O pin Timer Z output pin Timer C input pin Transfer clock I/O pin. Serial data input pins. Serial data output pins. Reference voltage input pin for A/D converter. Con- nect the VREF pin to Vcc. Analog input pins for A/D converter These are 8-bit CMOS I/O ports. Each port has an I/O select direction register, allowing each pin in that port to be directed for input or output individually. Any port set to input can select whether to use a pull- up resistor or not by program. 0 to P17 also function as LED drive ports. Port for input-only.

1.6 Pin Description

Table 1.3 shows the pin description Table 1.3 Pin description

R8C/10 Group 2. Central Processing Unit (CPU) Rev.1.60 Jan 27, 2006 page 7 of 25 REJ03B0035-0160 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. Two sets of register banks are provided.

2.1 Data Registers (R0, R1, R2 and R3)

R0 is a 16-bit register for transfer, arithmetic and logic operations. The same applies to R1 to R3. The R0 can be split into high-order bit (R0H) and low-order bit (R0L) to be used separately as 8-bit data registers. The same applies to R1H and R1L as R0H and R0L. R2 can be combined with R0 to be used as a 32-bit data register (R2R0). The same applies to R3R1 as R2R0. Data registers(1) Address registers(1) Frame base registers(1) Program counter Interrupt table register User stack pointer Interrupt stack pointer Static base register Flag register NOTES: 1. A register bank comprises t hese regi s te rs . T wo s e ts of regist er banks are provided R 0 H ( h i g h - o r d e r o f R 0 ) b 1 5 b 8 b7 b 0 R 3 I N T B H USP ISP SB CDZSBOIUIPL R 0 L ( h i g h - o r d e r o f R 0 ) R1H (high-order of R1)R1L (high-order of R1) R 2 b 3 1 R 3 A 1 A 0 F B b 1 9 I N T B L b 1 5 b 0 P C b 1 9 b 0 b15 b0 FLG b15 b0 b15 b0 b7 b8 Reserved bit Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved bit Processor interrupt priority level The 4-high order bits of INTB are INTBH and the 16-low bits of INTB are INTBL. Figure 2.1 CPU Register

R8C/10 Group 2. Central Processing Unit (CPU) Rev.1.60 Jan 27, 2006 page 8 of 25 REJ03B0035-0160

2.2 Address Registers (A0 and A1)

A0 is a 16-bit register for address register indirect addressing and address register relative address- ing. They also are used for transfer, arithmetic and logic operations. The same applies to A1 as A0. A0 can be combined with A0 to be used as a 32-bit address register (A1A0).

2.3 Frame Base Register (FB)

FB is a 16-bit register for FB relative addressing.

2.4 Interrupt Table Register (INTB)

INTB is a 20-bit register indicates the start address of an interrupt vector table.

2.5 Program Counter (PC)

PC, 20 bits wide, indicates the address of an instruction to be executed.

2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)

The stack pointer (SP), USP and ISP, are 16 bits wide each. The U flag of FLG is used to switch between USP and ISP.

2.7 Static Base Register (SB)

SB is a 16-bit register for SB relative addressing.

2.8 Flag Register (FLG)

FLG is a 11-bit register indicating the CPU state.

2.8.1 Carry Flag (C)

The C flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic logic unit.

2.8.2 Debug Flag (D)

The D flag is for debug only. Set to “0”.

2.8.3 Zero Flag (Z)

The Z flag is set to “1” when an arithmetic operation resulted in 0; otherwise, “0”.

2.8.4 Sign Flag (S)

The S flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, “0”.

2.8.5 Register Bank Select Flag (B)

The register bank 0 is selected when the B flag is “0”. The register bank 1 is selected when this flag is set to “1”.

2.8.6 Overflow Flag (O)

The O flag is set to “1” when the operation resulted in an overflow; otherwise, “0”.

2.8.7 Interrupt Enable Flag (I)

The I flag enables a maskable interrupt. An interrupt is disabled when the I flag is set to “0”, and are enabled when the I flag is set to “1”. The I flag is set to “0” when an interrupt request is acknowledged.

2.8.8 Stack Pointer Select Flag (U)

ISP is selected when the U flag is set to “0”, USP is selected when the U flag is set to “1”. The U flag is set to “0” when a hardware interrupt request is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed.

2.8.9 Processor Interrupt Priority Level (IPL)

IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has greater priority than IPL, the interrupt is enabled.

2.8.10 Reserved Bit

When write to this bit, set to “0”. When read, its content is indeterminate.

R8C/10 Group 4. Special Function Register (SFR) Rev.1.60 Jan 27, 2006 page 10 of 25 REJ03B0035-0160 Watchdog timer start register WDTS XX 16 W a t c h d o g t i m e r c o n t r o l r e g i s t e rW D C0 0 0 1 1 1 1 12 P r o c e s s o r m o d e r e g i s t e r 0P M 0X X X X0X 0 02 System clock control register 0 CM0 01101000 2 System clock control register 1 CM1 00100000 2 A d d r e s s m a t c h i n t e r r u p t e n a b l e r e g i s t e rA I E RX X X X X X 0 02 P r o t e c t r e g i s t e rP R C R0 0 X X X 0 0 02 P r o c e s s o r m o d e r e g i s t e r 1P M 10 0 X X X 0 X 02 N O T E S : B l a n k s p a c e s a r e r e s e r v e d N o a c c e s s i s a l l o w e d X U n d e f i n e d O s c i l l a t i o n s t o p d e t e c t i o n r e g i s t e rO C D0 0 0 0 0 1 0 02 INT0 input filter select register INT0F XXXXX000 2 0 0 0 01 C 1 D 1 C 1 D 1 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C 16 002D 16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C 16 003D 16 003E16 003F16 A d d r e s s R e g i s t e rS y m b o l A f t e r r e s e t A d d r e s s m a t c h i n t e r r u p t r e g i s t e r 0R M A D 00 01 X A d d r e s s m a t c h i n t e r r u p t r e g i s t e r 1R M A D 10 01 X W a t c h d o g t i m e r r e s e t r e g i s t e rW D T RX X1 4. Special Function Register (SFR) SFR(Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.4 list the SFR information Table 4.1 SFR Information(1)(1)

R8C/10 Group 4. Special Function Register (SFR) Rev.1.60 Jan 27, 2006 page 11 of 25 REJ03B0035-0160 UART0 transmit interrupt control register S0TIC XXXXX000 2 UART0 receive interrupt control register S0RIC XXXXX000 2 UART1 transmit interrupt control register S1TIC XXXXX000 2 UART1 receive interrupt control register S1RIC XXXXX000 2 Key input interrupt control register KUPIC XXXXX000 2 A D c o n v e r s i o n i n t e r r u p t c o n t r o l r e g i s t e rA D I CX X X X X 0 0 02 INT1 interrupt control register INT1IC XXXXX000 2 INT2 interrupt control register INT2IC XXXXX000 2 INT0 interrupt control register INT0IC XX00X000 2 INT3 interrupt control register INT3IC XXXXX000 2 NOTES : 1. Blank spaces are reserved. No access is allowed. X : Undefined 0 0 4 01 C 1 D 1 C 1 D 1 006016 006116 006216 006316 006416 006516 006616 006716 006816 006916 006A16 006B16 006C 16 006D 16 006E16 006F16 007016 007116 007216 007316 007416 007516 007616 007716 007816 007916 007A16 007B16 007C 16 007D 16 007E16 007F16 A d d r e s s R e g i s t e r Symbol A f t e r r e s e t Timer X interrupt control register TXIC XXXXX000 2 Timer Y interrupt control register TYIC XXXXX000 2 Timer Z interrupt control register TZIC XXXXX000 2 Timer C interrupt control register TCIC XXXXX000 2 Table 4.2 SFR Information(2)(1)

R8C/10 Group 4. Special Function Register (SFR) Rev.1.60 Jan 27, 2006 page 12 of 25 REJ03B0035-0160 0 0 8 01 C 1 D 1 C 1 D 1 0 0 A 01 A A A A A A A A A A A A C 1 A D 1 A A B B B B B B B B B B B B B C 1 B D 1 B B T i m e r X r e g i s t e rT XF F1 T i m e r Y s e c o n d a r y r e g i s t e rT Y S CF F1 E x t e r n a l i n p u t e n a b l e r e g i s t e rI N T E N0 01 P r e s c a l e r Y r e g i s t e rP R E YF F1 UART0 transmit/receive mode register U0MR 00 16 U A R T 0 t r a n s m i t b u f f e r r e g i s t e rU 0 T BX X1 X U A R T 0 r e c e i v e b u f f e r r e g i s t e r U 0 R BX X1 X UART1 transmit/receive mode register U1MR 00 16 UART1 transmit buffer register U1TB XX 16 XX 16 UART1 receive buffer register U1RB XX 16 XX 16 UART0 bit rate generator U0BRG XX 16 U A R T t r a n s m i t r e c e i v e c o n t r o l r e g i s t e r

0 U 0 C 00 0 0 0 1 0 0 02

U A R T t r a n s m i t r e c e i v e c o n t r o l r e g i s t e r

1 U 0 C 10 0 0 0 0 0 1 02

UART1 bit rate generator U1BRG XX 16 UART1 transmit/receive control register 0 U1C0 00001000 2 U A R T t r a n s m i t r e c e i v e c o n t r o l r e g i s t e r

1 U 1 C 10 0 0 0 0 0 1 02

UART transmit/receive control register 2 UCON 00 16 N O T E S : B l a n k s p a c e s a r e r e s e r v e d N o a c c e s s i s a l l o w e d X U n d e f i n e d A d d r e s s R e g i s t e rS y m b o l A f t e r r e s e t T i m e r Y , Z m o d e r e g i s t e rT Y Z M R0 01 Timer Y primary register TYPR FF 16 T i m e r Y , Z w a v e f o r m o u t p u t c o n t r o l r e g i s t e rP U M0 01 P r e s c a l e r Z r e g i s t e rP R E ZF F1 T i m e r Z s e c o n d a r y r e g i s t e rT Z S CF F1 T i m e r Z p r i m a r y r e g i s t e rT Z P RF F1 T i m e r Y , Z o u t p u t c o n t r o l r e g i s t e rT Y Z O C0 01 T i m e r X m o d e r e g i s t e rT X M R0 01 P r e s c a l e r X r e g i s t e rP R E XF F1 C o u n t s o u r c e s e t r e g i s t e rT C S S0 01 T i m e r C r e g i s t e rT C0 01 K e y i n p u t e n a b l e r e g i s t e rK I E N0 01 T i m e r C c o n t r o l r e g i s t e r 0T C C 00 01 Timer C control register 1 TCC1 00 16 Capture register TM0 00 16 0016 Table 4.3 SFR Information(3)(1)

R8C/10 Group 4. Special Function Register (SFR) Rev.1.60 Jan 27, 2006 page 13 of 25 REJ03B0035-0160 0 0 C 01 C C C C C C C C C C C C C 1 C D 1 C C D D D D D D D D D D D D D C 1 D D 1 D D 00E016 00E116 00E216 00E316 00E416 00E516 00E616 00E716 00E816 00E916 00EA 16 00EB 16 00EC 16 00ED 16 00EE 16 00EF 16 00F016 00F116 00F216 00F316 00F416 00F516 00F616 00F716 00F816 00F916 03FA 16 00FB 16 00FC 16 00FD 16 00FE 16 00FF16 01B316 01B416 01B516 01B616 01B716 NOTES: 1. Blank columns, 010016 to 01B216 and 01B816 to 02FF16 are all reserved. No access is allowed. X : Undefined A D r e g i s t e rA DX X X X X X X X2 X X X X X X X A D c o n t r o l r e g i s t e r 0A D C O N 00 0 0 0 0 X X X2 A D c o n t r o l r e g i s t e r 2A D C O N 20 01 A D c o n t r o l r e g i s t e r 1 A D C O N 10 01 P o r t P 0 r e g i s t e rP 0X X1 P o r t P 0 d i r e c t i o n r e g i s t e rP D 00 01 P o r t P 1 r e g i s t e rP 1X X1 Port P1 direction register PD1 00 16 P o r t P 3 r e g i s t e rP 3X X1 Port P3 direction register PD3 00 16 Port P4 register P4 XX 16 P o r t P 4 d i r e c t i o n r e g i s t e rP D 40 01 P u l l - u p c o n t r o l r e g i s t e r 0 P U R 00 0 X X 0 0 0 02 Port P1 drive capacity control register DRR 00 16 R e g i s t e r Symbol After resetA d d r e s s Pull-up control register 1 PUR1 XXXXXX0X 2 F l a s h m e m o r y c o n t r o l r e g i s t e r 1 F M R 10 1 0 0 X X 0 X2 F l a s h m e m o r y c o n t r o l r e g i s t e r 0 F M R 00 0 0 0 0 0 0 12 Flash memory control register 4 FMR4 01000000 2 Table 4.4 SFR Information(4)(1)

R8C/10 Group 5. Electrical Characteristics Rev.1.60 Jan 27, 2006 page 14 of 25 REJ03B0035-0160 5. Electrical Characteristics Table 5.1 Absolute Maximum Ratings Operating ambient temperature Parameter Unit Supply voltage Output voltageVO Pd Power dissipation Storage temperature Rated value V V Condition VCC Tstg Topr Symbol mW VCC =AV CC VAV CC V -0.3 to 6.5 -65 to 150 300 -20 to 85 / -40 to 85 (D version) C Topr=25 C Analog supply voltage VCC =AV CC -0.3 to 6.5 VI Input voltage -0.3 to VCC +0.3 -0.3 to VCC +0.3 C Table 5.2 Recommended Operating Conditions 2 . 75 . 5 Typ. M a x . UnitP a r a m e t e r VC C Supply voltage S y m b o l M i n S t a n d a r d Analog supply voltage VC C (3 )A V c c V 0Analog supply voltage Supply voltage VI H V s s A V s s 0 . 8 VC C V VVC C 0 . 2 VC C"L" input voltage " H " i n p u t v o l t a g e V f ( XI N ) M a i n c l o c k i n p u t o s c i l l a t i o n f r e q u e n c y V VIL 1 0 3 . 0 V ≤ V c c ≤ 5 . 5 V 2 . 7 V ≤ V c c < 3 . 0 V M H z M H z NOTES: 1. VCC = AVCC = 2.7 to 5.5V at Topr = -20 to 85 °C / -40 to 85 °C, unless otherwise specified. 2. The typical values when average output current is 100ms. 3. Hold Vcc=AVcc. IOH (sum) " H " p e a k a l l o u t p u t c u r r e n t s C o n d i t i o n s Sum of all pins' IOH (peak) -60.0 m A IOH (peak) "H" peak output current - 1 0 . 0 m A IOH (avg) " H " a v e r a g e o u t p u t c u r r e n t - 5 . 0m A IOL (sum) "L" peak all output currents Sum of all pins' IOL (peak) 60 mA IOL (peak) "L" peak output current Except P10 to P17 P10 to P17 10 mA Drive capacity HIGH Drive capacity LOW mA mA IO L a v g ) " L " a v e r a g e o u t p u t c u r r e n t Except P10 to P17 P10 to P17 Drive capacity HIGH Drive capacity LOW 1 5 m A m A mA 1 6

R8C/10 Group 5. Electrical Characteristics Rev.1.60 Jan 27, 2006 page 15 of 25 REJ03B0035-0160 Table 5.3 A/D Conversion Characteristics Standard M i n .T y p . M a x –R e s o l u t i o n BitVr e f = VC C 1 0 S y m b o lP a r a m e t e rM e a s u r i n g c o n d i t i o nU n i t LSB± 3 R L A D D E R tC O N V L a d d e r r e s i s t a n c e C o n v e r s i o n t i m e R e f e r e n c e v o l t a g e A n a l o g i n p u t v o l t a g e V VI A VR E F VC C ( Vref NOTES: 1. VCC =AV CC =2.7 to 5.5V at Topr = -20 to 85 °C / -40 to 85 °C, unless otherwise specified. 2. If fAD exceeds 10 MHz, divide the fAD and hold A/D operating clock frequency (ØAD) 10 MHz or below. 3. If the AVcc is less than 4.2V, divide the fAD and hold A/D operating clock frequency (ØAD) fAD /2 or below. 4. Hold Vcc=Vref. øAD=10 MHz, Vref=Vcc=5.0V VREF =VCC A b s o l u t e a c c u r a c y– 1 b i t m o d e 8 bit mode ø A D = 1 0 M H z , V r e f = V c c = 5 . 0 V ± 2 L S B b i t m o d e b i t m o d e øAD=10 MHz, Vref=Vcc=3.3V(3) ± 5L S B ø A D M H z V r e f V c c V(3 ) ± 2L S B 1 0 40 kΩ 10 bit mode 8 bit mode ø A D = 1 0 M H z , V r e f = V c c = 5 . 0 V ø A D = 1 0 M H z , V r e f = V c c = 5 . 0 V 3 . 3 2 . 8 µs µs V A D o p e r a t i n g c l o c k f r e q u e n c y(2 Without sample & hold With sample & hold 0 . 2 5 10 MHz 1.0 1 0 MHz Table 5.4 Flash Memory Version Electrical Characteristics B y t e p r o g r a m t i m e Block erase time P r o g r a m E r a s e v o l t a g e R e a d v o l t a g e µs P a r a m e t e r Standard M i n y p a x U n i t N O T E S : VC C A V c c t o V a t T o p r t o C u n l e s s o t h e r w i s e s p e c i f i e d T h e d a t a h o l d t i m e i n c l u d e s t i m e t h a t t h e p o w e r s u p p l y i s o f f o r t h e c l o c k i s n o t s u p p l i e d Measuring conditionS y m b o l Program, Erase temperature 2.7 2.7 400 s V V °C– Time delay from suspend request until erase suspend td(SR-ES) P r o g r a m e r a s e e n d u r a n c e 8 ms 100 t i m e s – D a t a h o l d t i m ) Ambient temperature=55 °C 20 year – E r a s e S u s p e n d R e q u e s t I n t e r v a l 10 ms Table 5.5 Power Circuit Timing Characteristics S y m b o l S t a n d a r d T y p . U n i tMeasuring condition M i n a x .Parameter 2000 N O T E S T h e m e a s u r i n g c o n d i t i o n i s V c c A V c c t o V a n d T o p r C T h i s s h o w s t h e w a i t i n g t i m e u n t i l t h e i n t e r n a l p o w e r s u p p l y g e n e r a t i n g c i r c u i t i s s t a b i l i z e d d u r i n g p o w e r i n g o n T h i s s h o w s t h e t i m e u n t i l B C L K s t a r t s f r o m t h e i n t e r r u p t a c k n o w l e d g e m e n t t o c a n c e l s t o p m o d e 1 5 0t d ( R - S ) S T O P r e l e a s e t i m e(3 µ st d ( P - R ) T i m e f o r i n t e r n a l p o w e r s u p p l y s t a b i l i z a t i o n d u r i n g p o w e r i n g o n(2 µ s

R8C/10 Group 5. Electrical Characteristics Rev.1.60 Jan 27, 2006 page 17 of 25 REJ03B0035-0160 Table 5.6 Electrical Characteristics (1) [Vcc=5V] Symbol VOH VOL "L" output voltage "H" output voltage Standard Typ. UnitMeasuring condition V V Min. Max. VCC -2.0 Parameter IOH =-5mA V NOTES: 1. Referenced to VCC =AV CC =4.2 to 5.5V at Topr = -20 to 85 °C / -40 to 85 °C, f(XIN)=20MHz unless otherwise specified. VCCExcept XOUT XOUT IOH =-200µA Drive capacity HIGH Drive capacity LOW VCC -0.3 VCC V IOH =-1 mA V CC -2.0 VCC -2.0IOH =-500µA V V VCC VCC Except P10 to P17, XOUT P10 to P17 Drive capacity HIGH Drive capacity LOW IOL = 5 mA IOL = 200 µA IOL = 15 mA IOL = 5 mA 2.0 0.45 V 2.0 V V Hysteresis "H" input currentIIH "L" input currentIIL VRAM RAM retention voltage VT+-VT- 0.2 V µA At stop mode 2.0 VI=5V VI=0V R fXIN Feedback resistance X IN M Ω R PULLUP Pull-up resistance 167 kΩ30 125 XOUT Drive capacity HIGH Drive capacity LOW IOL = 1 mA IOL =500µA 2.0 2.0 V INTo, INT1, INT2, INT3, KI0, KI1, KI2, KI3, CNTR0, CNTR1, TCIN, RxD 0, RxD1, P45 RESET 0.2 1.0 2.2 V V 5.0 -5.0 µA VI=0V 50 1.0 fRING On-chip oscillator frequency 40 250 kHz IOL = 200 µA 0.45 2.0 Drive capacity LOW V

R8C/10 Group 5. Electrical Characteristics Rev.1.60 Jan 27, 2006 page 18 of 25 REJ03B0035-0160 Table 5.7 Electrical Characteristics (2) [Vcc=5V] S y m b o l S t a n d a r d T y p . U n i tMeasuring condition M i n .M a x .Parameter N o division m A In single-chip mode, the output pins are open and other pins are V SS 8 1 4 XIN=16 MH z (square wave) m A H i g h - s p e e d m o d e IC C P o w e r s u p p l y c u r r e n t VC C = t o V N O T E S : T i m e r Y i s o p e r a t e d w i t h t i m e r m o d e R e f e r e n c e d t o VC C A VC C t o V a t T o p r t o C t o C f XI N ) M H z u n l e s s o t h e r w i s e s p e c i f i e d Wait mode µA µ A µ A m AMedium-speed mode On-chip oscillator mode Wait mode O n - c h i p o s c i l l a t o r o n = 1 2 5 k H z XIN=10 MH z (square wave) O n - c h i p o s c i l l a t o r o n = 1 2 5 k H z N o division XIN=16 MH z (square wave) O n - c h i p o s c i l l a t o r o n = 1 2 5 k H z D i v i s i o n b y 8 XIN=10 MH z (square wave) O n - c h i p o s c i l l a t o r o n = 1 2 5 k H z D i v i s i o n b y 8 2 mA M ain clock off O n - c h i p o s c i l l a t o r o n = 1 2 5 k H z M ain clock off O n - c h i p o s c i l l a t o r o n = 1 2 5 k H z Peripheral clock operation 4 0 M ain clock off O n - c h i p o s c i l l a t o r o n = 1 2 5 k H z Peripheral clock off Stop mode M a i n c l o c k o f f , T o p r = 2 5 ° C O n-chip oscillator off CM 10="1" Peripheral clock off 0 . 8 3 . 0 Division by 8 4 7 0 W h e n a W A I T i n s t r u c t i o n i s e x e c u t e d(1) When a WAIT instruction is executed(1) 9 0 0 7 6 µ A

R8C/10 Group 5. Electrical Characteristics Rev.1.60 Jan 27, 2006 page 19 of 25 REJ03B0035-0160 Timing requirements (Unless otherwise noted: VCC = 5V, VSS = 0V at Topr = 25 °C) [VCC =5V] Table 5.8 XIN input Table 5.9 CNTR0 input, CNTR1 input, INT2 input Table 5.10 TCIN input, INT3 input Table 5.11 Serial Interface Table 5.12 External interrupt INT0 input Symbol tC (XIN) tWH (XIN) tWL (XIN) Parameter XIN input cycle time XIN input HIGH pulse width XIN input LOW pulse width Min. 62.5 Max. Unit ns ns ns Standard Symbol tC (CNTR0 ) tWH (CNTR0 ) tWL (CNTR0 ) Parameter CNTR0 input cycle time CNTR0 input HIGH pulse width CNTR0 input LOW pulse width Min. 100 Max. Unit ns ns ns Standard Symbol tC (TCIN) tWH (TCIN) tWL (TCIN) Parameter TCIN input cycle time TCIN input HIGH pulse width TCIN input LOW pulse width Min. 400(1) 200(2) 200(2) Max. Unit ns ns ns Standard NOTES: 1. When using the Timer C capture function, adjust the cycle time above ( 1/ Timer C count source frequency x 3). 2. When using the Timer C capture function, adjust the pulse width above ( 1/ Timer C count source frequency x 1.5). NOTES: 1. When selecting the digital filter by the INT0 input filter select bit, use the INT0 input HIGH pulse width to the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard.________ ________ 2. When selecting the digital filter by the INT0 input filter select bit, use the INT0 input LOW pusle width to the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard. Symbol tC (CK ) tW (CKH ) tW (CKL ) td(C-Q ) th(C-Q ) tsu(D-C) th(C-D) Parameter CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width TxDi output delay time TxDi hold time RxDi input setup time RxDi input hold time Min. 200 100 100 Max. Unit ns ns ns ns ns ns ns Standard Symbol tW (INH) tW (INL) Parameter INT0 input LOW pulse width Min. 250(1) 250(2) Max. Unit ns ns Standard

R8C/10 Group 5. Electrical Characteristics Rev.1.60 Jan 27, 2006 page 20 of 25 REJ03B0035-0160 Figure 5.3 Vcc=5V timing diagram CLK i TxD i RxD i INTi tW(CKH) tc(CK) tW(CKL) th(C-Q) th(C-D)tsu(D-C)td(C-Q) tW(INL) tW(INH) XIN input tWH(XIN) tc(XIN) tWL(XIN) TCIN input tWH(TCIN) tc(TCIN) tWL(TCIN) CNTR0 input tWH(CNTR0) tc(CNTR0) tWL(CNTR0) VCC = 5V

R8C/10 Group 5. Electrical Characteristics Rev.1.60 Jan 27, 2006 page 21 of 25 REJ03B0035-0160 Table 5.13 Electrical Characteristics (3) [Vcc=3V] S y m b o l VO H VO L " L " o u t p u t v o l t a g e " H " o u t p u t v o l t a g e S t a n d a r d T y p . U n i tMeasuring condition V V V M i n .M a x . VC C -0 P a r a m e t e r IO H =-1m A V H y s t e r e s i s " H " i n p u t c u r r e n tII H " L " i n p u t c u r r e n tII L VR A M R A M r e t e n t i o n v o l t a g e VT -VT - 0 . 2 V µ A At stop mode 2 . 0 VI=3V R f X I N F e e d b a c k r e s i s t a n c e XI N M Ω R P U L L U P P u l l - u p r e s i s t a n c e kΩ66 125 N O T E S : R e f e r e n c e d t o VC C = A VC C =2 t o V a t T o p r t o C t o C f XI N ) M H z u n l e s s o t h e r w i s e s p e c i f i e d VC CE x c e p t XO U T XO U T D r i v e c a p a c i t y H I G H Drive capacity LOW IO H =-0 m AV CC -0.5 VC C -0 5IO H =-50 µ A V V VCC VC C E x c e p t P 10 t o P 17, XO U T P 10 t o P 17 XO U T D r i v e c a p a c i t y H I G H D r i v e c a p a c i t y L O W IO L= 1 m A IOL = 2 mA IO L= 1 m A 0 . 5 V0 . 5 0.5 VDrive capacity HIGH Drive capacity LOW IO L= 0 m A IO L= 5 0 µ A 0 . 5 0 . 5 V R E S E T 0.2 0 . 8 1 . 8 V 4. 0 -4. 0µ AVI= 0 V 160 3. 0 fR I N G O n - c h i p o s c i l l a t o r f r e q u e n c y 40 2 5 0 k H z VI= 0 V 5 0 0 INTo, INT1, INT2, INT3, KI0, KI1, KI2, KI3, CNTR0, CNTR1, TCIN, RxD 0, RxD1, P45

R8C/10 Group 5. Electrical Characteristics Rev.1.60 Jan 27, 2006 page 22 of 25 REJ03B0035-0160 Table 5.14 Electrical Characteristics (4) [Vcc=3V] S y m b o l S t a n d a r d T y p . U n i tM e a s u r i n g c o n d i t i o n M i n .M a x .Parameter N o d i v i s i o n m A I n s i n g l e - c h i p m o d e , t h e o u t p u t p i n s a r e o p e n a n d o t h e r p i n s a r e VS S 71 2 XI N = 1 6 M H z ( s q u a r e w a v e ) m A High-speed mode IC C P o w e r s u p p l y c u r r e n t VC C t o V 420 N O T E S : T i m e r Y i s o p e r a t e d w i t h t i m e r m o d e R e f e r e n c e d t o VC C = A VC C =2 t o V a t T o p r t o C t o C f XI N ) M H z u n l e s s o t h e r w i s e s p e c i f i e d W a i t m o d e µA µ A µA m AM e d i u m - s p e e d m o d e O n - c h i p o s c i l l a t o r m o d e W a i t m o d e O n-chip oscillator on=125 kHz XI N = 1 0 M H z ( s q u a r e w a v e ) O n-chip oscillator on=125 kHz N o division XI N = 1 6 M H z ( s q u a r e w a v e ) O n - c h i p o s c i l l a t o r o n = 1 2 5 k H z D i v i s i o n b y 8 2 . 5 XI N = 1 0 M H z ( s q u a r e w a v e ) O n-chip oscillator on=125 kHz D i v i s i o n b y 8 1 . 6 m A M a i n c l o c k o f f O n - c h i p o s c i l l a t o r o n = 1 2 5 k H z Division by 8 M ain clock off O n - c h i p o s c i l l a t o r o n = 1 2 5 k H z P e r i p h e r a l c l o c k o p e r a t i o n M ain clock off O n - c h i p o s c i l l a t o r o n = 1 2 5 k H z P e r i p h e r a l c l o c k o f f Stop mode M a i n c l o c k o f f , T o p r = 2 5 ° C O n - c h i p o s c i l l a t o r o f f C M 1 0 = " 1 " P e r i p h e r a l c l o c k o f f 0 . 73 . 0 3 7 3 5 W h e n a W A I T i n s t r u c t i o n i s e x e c u t e d(1) W h e n a W A I T i n s t r u c t i o n i s e x e c u t e d(1) 8 0 0 7 4 7 0 µ A

R8C/10 Group 5. Electrical Characteristics Rev.1.60 Jan 27, 2006 page 23 of 25 REJ03B0035-0160 Timing requirements (Unless otherwise noted: VCC = 3V, VSS = 0V at Topr = 25 °C) [VCC =3V] Table 5.15 XIN input Table 5.16 CNTR0 input, CNTR1 input, INT2 input Table 5.17 TCIN input, INT3 input Table 5.18 Serial Interface Table 5.19 External interrupt INT0 input Symbol tC (XIN) tWH (XIN) tWL (XIN) Parameter XIN input cycle time XIN input HIGH pulse width XIN input LOW pulse width Min. 100 Max. Unit ns ns ns Standard Symbol tC (CNTR0 ) tWH (CNTR0 ) tWL (CNTR0 ) Parameter CNTR0 input cycle time CNTR0 input HIGH pulse width CNTR0 input LOW pulse width Min. 300 120 120 Max. Unit ns ns ns Standard Symbol tC (TCIN) tWH (TCIN) tWL (TCIN) Parameter TCIN input cycle time TCIN input HIGH pulse width TCIN input LOW pulse width Min. 1200(1) 600(2) 600(2) Max. Unit ns ns ns Standard NOTES: 1. When using the Timer C capture function, adjust the cycle time above ( 1/ Timer C count source frequency x 3). 2. When using the Timer C capture function, adjust the pulse width above ( 1/ Timer C count source frequency x 1.5). NOTES: 1. When selecting the digital filter by the INT0 input filter select bit, use the INT0 input HIGH pulse width to the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard.________ ________ 2. When selecting the digital filter by the INT0 input filter select bit, use the INT0 input LOW pusle width to the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard. Symbol tC (CK ) tW (CKH ) tW (CKL ) td(C-Q ) th(C-Q ) tsu(D-C) th(C-D) Parameter CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width TxDi output delay time TxDi hold time RxDi input setup time RxDi input hold time Min. 300 150 150 Max. Unit ns ns ns ns ns ns ns Standard 160 Symbol tW (INH) tW (INL) Parameter INT0 input LOW pulse width Min. 380(1) 380(2) Max. Unit ns ns Standard

R8C/10 Group 5. Electrical Characteristics Rev.1.60 Jan 27, 2006 page 24 of 25 REJ03B0035-0160 Figure 5.4 Vcc=3V timing diagram CLK i TxD i RxD i INTi tW(CKH) tc(CK) tW(CKL) th(C-Q) th(C-D)tsu(D-C)td(C-Q) tW(INL) tW(INH) XIN input tWH(XIN) tc(XIN) tWL(XIN) TCIN input tWH(TCIN) tc(TCIN) tWL(TCIN) CNTR0 input tWH(CNTR0) tc(CNTR0) tWL(CNTR0) VCC = 3V

R8C/10 Group Package Dimensions Rev.1.60 Jan 27, 2006 page 25 of 25 REJ03B0035-0160 Package Dimensions DO NOT INCLUDE MOLD FLASH. NOTE) DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. y Index mark F 24 17 x bpe HE E D HD ZD ZE Detail F L A c A2A1 Previous CodeJEITA Package Code RENESAS Code PLQP0032GB-A 32P6U-A MASS[Typ.] 0.2gP-LQFP32-7x7-0.80 1.0 0.125 0.35 0.7 0.7 0.20 0.200.1450.09 0.420.370.32 MaxNomMin Dimension in Millimeters Symbol Reference 7.17.06.9D 7.17.06.9E 1.4A2 9.29.08.8 9.29.08.8 1.7A 0.20.10 0.70.50.3L x 8°0° c 0.8e 0.10y HD HE bp ZD ZE Terminal cross section bp c

REVISION HISTORY R8C/10 Group Datasheet Rev. Date Description Page Summary A-1 1.00 Jun. 19, 2003 First edition issued 1.10 Sep. 08, 2003 Table 1.1: Shortest instruction execution time and f(XIN) changed____________ Figure 1.3: Pin name changed from TXOUT to CNTR0____________ Table 1.3: Pin name changed from TXOUT to CNTR0 The value of Time C register after reset changed Chapter “5. Electrical Characteristics” added 1.20 Oct. 31, 2003 Table 1.1: Power consumption values added Table 1.3: Resistor value for CNVss and MODE deleted Table 5.2: Note 3 and Note 4 deleted t samp in Table 5.3 deleted Figure 5.1 added changed from “on 100kHz” to “125kHz”, X IN=5MHz deleted and XIN=10MHz added in high-speed mode and medium-speed mode, data added and modified Table 5.8 to Table 5.12 added Figure 5.2 added Table 5.13: Note 1, f (BCLK)=5 MHz changed to 10 MHz Table 5.14: on-chip oscillator changed from “on 100kHz” to “125kHz”, XIN=5MHz deleted and XIN=10MHz added in high-speed mode and medium-speed mode, data added and modified Table 5.15 to Table 5.19 added Figure 5.3 added 1.30 Dec 05, 2003 4 Table 1.2 : ** deleted 15 Table 5.4 revised

1.40 Sep 30, 2004 All pages Words standardized (on-chip oscillator, serial interface, A/D)

2 Table 1.1 revised 5 Figure 1.3, NOTES 3 added 6 Table 1.3 revised 10-13 One body sentence in chapter 4 added ; Titles 4.1 to 4.4 added 12 Table 4.3 revised ; Table 4.4 revised 14 Table 5.2 revised 15 Table 5.3 revised ; Table 5.4 revised 17 Table 5.6 revised 18 Table 5.7 revised 19 Table 5.8 revised ; Table 5.12 revised 21 Table 5.13 revised 22 Table 5.14 revised 23 Table 5.15 revised ; Table 5.17 revised ; Table 5.19 revised 5 Figure 1.3 package name revised 10 Table 4.1 revised

REVISION HISTORY R8C/10 Group Datasheet Rev. Date Description Page Summary A-2 1.50 Apr.27.2005 12 T able 4.3 revised 15 Table 5.3 partly revised Table 5.4 partly added Table 5.5 partly revised 17 Table 5.6 partly revised 21 Table 5.13 partly revised 1.60 Jan.27.2006 2 Table 1.1 Performance outline revised 3 Figure 1.1 Block diagram partly revised 4 1.4 Product Information, title of Table 1.2 “Product List” → “Product Informaton” revised Figure 1.2 Type No., Memory Size, and Package partly revised 6 Table 1.3 Pin description revised 7-8 2 Central Processing Unit (CPU) revised Figure 2.1 CPU register revised 10 Table 4.1 SFR Information(1) NOTES:1 revised 11 Table 4.2 SFR Information(2) NOTES:1 revised 12 Table 4.3 SFR Information(3); 008116: “Prescaler Y” → “Prescaler Y Register” 008216: “Timer Y Secondary” → “Timer Y Secondary Register” 008316: “Timer Y Primary” → “Timer Y Primary Register” 008516: “Prescaler Z” → “Prescaler Z Register” 008616: “Timer Z Secondary” → “Timer Z Secondary Register” 008716: “Timer Z Primary” → “Timer Z Primary Register” 008C 16: “Prescaler X” → “Prescaler X Register” revised NOTES:1 revised 13 Table 4.4 SFR Information(4) NOTES:1 revised 14 Table 5.2 Recommended Operating Conditions; NOTES: 1, 2, 3 revised 15 Table 5.3 A/D Conversion Characteristics; “A/D operation clock frequency” → “A/D operating clock frequency” revised NOTES: 1, 2, 3, 4 revised Table 5.4 Flash Memory (Program ROM) Electrical Characteristics; “Data retention duration” → “Data hold time” revised “Topr” → “Ambient temperature” revised NOTES: 2 added Measuring condition of byte program time and block erase time deleted 17 Table 5.6 Electrical Characteristics (1) [VCC =5V]; “P10 to P17 Except XOUT ” → “Except P10 to P17, XOUT ” revised 18 Table 5.7 Electrical Characteristics (2) [VCC =5V] NOTES: 1, 2 revised Measuring condition: Stop mode “Topr = 25 °C” 21 Table 5.13 Electrical Characteristics (3) [VCC =3V] “P10 to P17 Except XOUT ” → “Except P10 to P17, XOUT ” revised 22 Table 5.14 Electrical Characteristics (4) [VCC =3V] NOTES: 1, 2 revised Measuring condition: Stop mode “Topr = 25 °C”

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Description