R7F701644

RH850 RENESAS | Alldatasheet

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www.renesas.com All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Elect ronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp. website (http://www.renesas.com). User’s Manual Rev.1.10 Dec, 2018 RH850/F1KH, RH850/F1KM User’s Manual: Hardware Renesas microcontroller RH850 Family

1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operati on of semiconductor products and application examples. You are fully responsible for the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by you or third parties arising from the use of these circuits, software, or information. 2. Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims involving patents, copyrights, or other intellectual property ri ghts of third parties, by or arising from the use of Renesas Electronics products or technical information described in this document, including but not limited to, the product data, drawings, charts, programs, algorithm s, and application examples. 3. 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Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this docum ent or Renesas Electronics products. (Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its directly or indirectly controlled subsidiaries. (Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics. (Rev.4.0-1 November 2017 )

(1) Voltage application waveform at input pin: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). (2) Handling of unused input pins: Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to power supply or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) Precaution against ESD: A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. (4) Status before initialization: Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. (5) Power ON/OFF sequence: In the case of a device that uses different power supplies for the internal op eration and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. (6) Input of signal during power off state: Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device.

Readers This manual is intended for users who wish to understand the functions of the RH850/F1KH, RH850/F1KM and design application systems using the following RH850/F1KH, RH850/F1KM microcontrollers: Purpose This manual is intended to give users an understanding of the hardware functions of the RH850/F1KH, RH850/F1KM shown in the Organization below. Organization This manual is divided into two parts: Hardware (this manual) and Architecture (RH850G3KH User’s Manual: Software). How to read this manual It is assumed that the readers of this manual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. To understand the overall functions of the RH850/F1KH, RH850/F1KM. → Read this manual according to the Contents. To understand the details of an instruction function → See RH850G3KH User’s Manual: Software (R01US0165E) available separately. This RH850/F1KH, RH850/F1KM Hardware User’s Manual corresponds to Rev.1.10. The RH850/F1KH-D8 description relates to a revision level of Rev.1.00. The xxA section describes the functionality of RH850/F1KH-D8. The xxB section describes the functionality of RH850/F1KM-S4. The xxC section describes the functionality of RH850/F1KM-S1. The xxAB section describes the functionality of RH850/F1KH-D8 and RH850/F1KM-S4. The xxBC section describes the functionality of RH850/F1KM-S4 and RH850/F1KM-S1. The xxx section describes the functionality of all related products. Hardware Software Pin functions CPU function On-chip peripheral functions Flash memory programming Overview Processor Model Register Reference Exceptions and Interrupts Memory Management Instruction Reference Reset Appendix

Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: xxx (overscore over pin or signal name) Memory map address: Higher addresses on the top and lower addresses on the bottom Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information Numeric representation: Binary ... xxxx or xxxx B Decimal ... xxxx Hexadecimal ... xxxxH Prefix indicating power of 2 (address space, memory capacity): K (kilo): 210 = 1,024 M (mega): 220 = 1,0242 G (giga): 230 = 1,0243

Each register description includes register access, register address, and register value after a reset, a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meaning of the bit settings. The standard format for bit charts and tables are described below. (1) Access The register can be accessed in the bit unit indicated here. (2) Address This is the register address. For base address, see description of base address in each section. Access: This register can be read/written in 32-bit units. Address: <CSIGn_base> + 1010H Value after reset: 0000 0000H B i t 3 13 02 92 82 72 62 52 42 32 22 12 01 91 81 71 6 — — CSIGnPS[1:0] CSIGnDLS[3:0] — — — — — CSIGn DIR — CSIGn DAP V a l u e a f t e r r e s e t 0000000000000000 R / W RR R / W R / W R / W R / W R / W R / W RRRRR R / W R R / W B i t 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 V a l u e a f t e r r e s e t 0000000000000000 R / W RRRRRRRRRRRRRRRR Table 14.19 CSIGnCFG0 Register Contents (1/2) Bit Position Bit Name Function 31, 30 Reserved When read, the value after reset is returned. When writing to these bits, write the value after reset. 29, 28 CSIGnPS[1:0] Specifies parity. 27 to 24 CSIGnDLS [3:0] Specifies data length. 0: Data length is 16 bits 1: Data length is 1 bit 2: Data length is 2 bits ... 15: Data length is 15 bits CAUTION Do not set bits CSIGnCFG0.CSIGnDLS[3:0] for a value 1 to 6 when the extended data length function is disabled with bit CSIGnCTL1.CSIGnEDLE set to 0. It is forbidden to transmit two consecutive data with a data length of less than 7 bits. 23 to 19 Reserved When read, the value after reset is returned. When writing to these bits, write the value after reset. CSIGn PS1 CSIGn PS0 Transmission Reception 0 0 No parity transmitted No parity is waited for. 0 1 Add parity bit fixed at 0 Parity bit is waited for but not judged. 1 0 Add odd parity Odd parity bit is waited for. 1 1 Add even parity Even parity bit is waited for. (4) (5) (8) (1) (2) (3) (6) (7)

(3) Value after a reset (in hexadecimal notation) This is the value of all bits of the register after a reset. Values for bytes are given as numbers in the range from 0 to 9 and letters from A to F or as X where they are undefined. (4) Bit position This is the bit number. The bits are numbered from 31 to 0 for 32-bit registers, 15 to 0 for 16-bit registers, and 7 to 0 for 8- bit registers. (5) Bit name Bit name or field name is indicated. When clearly identifying the digits of a bit field is required, do so by using a form such as CSIGnDLS[3:0] above. Indicate reserved bits by using a dash (—). (6) Value after a reset (in binary notation) This is the bit values after a reset. (7) R/W This is the bit attribute of all bits of the register. (8) Function This is function of the bit. All trademarks and registered trademarks are the property of their respective owners. 0 : The value after a reset is 0. 1 : The value after a reset is 1. — : The value after a reset is undefined. R/W : The bit or field is readable and writable. R : The bit or field is readable. Note that all reserved bits are indicated as R. When written, the value specified in the bit chart or the value after a reset should be written. In case of writing to writable registers that also include non-reserved bits with the R-attribute, writing to the R-attribute bits will be ignored unless otherwise specified. W : This bit or field is writabl e. When read, the value is undefined. If a value is indicated in the bit chart, the value is returned.

3A.5.1 Synchronization of Store Instruction Completion and Subsequent Instruction Execution . 610

3BC.3.1 Synchronization of Store Instruction Completion and Subsequent Instruction Execution . 675

8.8.2.8 PDMAnDMyiCM — DMAC Channel Master Setting

(yi = 00 to 07, 10 to 17, 20 to 27, and 30 to 37 in RH850/F1KH-D8, yi = 00 to 07, 10 to 17, 20 to 27, and 30 to 37 in RH850/F1KM-S4,

8.10.2 DTFSEL_TAUD0/DTFSEL_TAUB0/DTFSEL_TAUB1 — DMA Trigger Factor Select

14.2.2.4 WUFMSK0/WUFMSK1/WUFMSK20/WUFMSK_ISO0 — Wake-Up Factor

18.3.4 MMCAnCE_ARG_CMD12 — MMCAn Argument Register for Automatically-Issued

18.3.10 MMCAnCE_RESP_CMD12 — MMCAn Response Register for Automatically-Issued

24.3.2.1 RCFDCnCFDCmNCFG — Channel Nominal Bit Rate Configuration Register

24.3.2.5 RCFDCnCFDCmDCFG — Channel Data Bit Rate Configuration Register

24.3.2.6 RCFDCnCFDCmFDCFG — Channel CAN FD Configuration Register

24.3.5.5 RCFDCnCFDRMFDSTSq — Receive Buffer CAN FD Status Register

24.3.5.6 RCFDCnCFDRMDFb_q — Receive Buffer Data Field Register

24.3.6.1 RCFDCnCFDRFCCx — Receive FIFO Buffer Configuration and Control Register

24.3.6.3 RCFDCnCFDRFPCTRx — Receive FIFO Buffer Pointer Control Register

24.3.6.5 RCFDCnCFDRFPTRx — Receive FIFO Buffer Access Pointer Register

24.3.6.6 RCFDCnCFDRFFDSTSx — Receive FIFO CAN FD Status Register

24.3.6.7 RCFDCnCFDRFDFd_x — Receive FIFO Buffer Access Data Field Register

24.3.7.1 RCFDCnCFDCFCCk — Transmit/receive FIFO Buffer Configuration and

24.3.7.2 RCFDCnCFDCFSTSk — Transmit/receive FIFO Buffer Status Register

24.3.7.3 RCFDCnCFDCFPCTRk — Transmit/receive FIFO Buffer Pointer Control

24.3.7.4 RCFDCnCFDCFIDk — Transmit/receive FIFO Buffer Access ID Register

24.3.7.5 RCFDCnCFDCFPTRk — Transmit/receive FIFO Buffer Access Pointer

24.3.7.6 RCFDCnCFDCFFDCSTSk — Transmit/receive FIFO CAN FD

24.3.7.7 RCFDCnCFDCFDFd_k — Transmit/receive FIFO Buffer Access Data Field

24.3.8.5 RCFDCnCFDCFRISTS — Transmit/receive FIFO Buffer Receive Interrupt

24.3.8.6 RCFDCnCFDCFTISTS — Transmit/receive FIFO Buffer Transmit Interrupt

24.3.10.5 RCFDCnCFDTMFDCTRp — Transmit Buffer CAN FD Configuration Register

24.3.10.6 RCFDCnCFDTMDFb_p — Transmit Buffer Data Field Register

24.3.10.7 RCFDCnCFDTMIECm — Transmit Buffer Interrupt Enable Configuration

24.3.11.1 RCFDCnCFDTMTRSTSm — Transmit Buffer Transmit Request Status

24.3.11.2 RCFDCnCFDTMTARSTSm — Transmit Buffer Transmit Abort Request

24.3.11.3 RCFDCnCFDTMTCSTSm — Transmit Buffer Transmit Complete Status

24.3.11.4 RCFDCnCFDTMTASTSm — Transmit Buffer Transmit Abort Status Register

24.3.12.1 RCFDCnCFDTXQCCm — Transmit Queue Configuration and Control

24.3.12.3 RCFDCnCFDTXQPCTRm — Transmit Queue Pointer Control Register

24.3.13.1 RCFDCnCFDTHLCCm — Transmit History Configuration and Control

24.3.13.3 RCFDCnCFDTHLPCTRm — Transmit History Pointer Control Register

25.2.7.12 FLXAnFRNMVm — FlexRay Network Management Vector Register m

25.2.9.7 FLXAnFRMBSCi — FlexRay Message Buffer Status Changed Register i

26.4.13.2 Rx-FIFO Read Error May Not be Flagged when Using FEMPTY_ND

26.4.13.3 When Trying to Release Non-Existing Timestamp FIFO Entry, New FIFO

26.4.13.6 ETNBnRIS0.FRFr may be lost when Data Processing Stops Close to or

26.4.13.8 Receive Frame Interrupt and Descriptor Interrupt may be issued before

31.3.4.2 TAUBnRDS — TAUBn Channel Reload Data Control Channel Select Register . 2820

31.6.4.1 Simultaneous Rewrite when the Master Channel (Re)Starts Counting

31.6.4.2 Simultaneous Rewrite at the Peak of a Triangular Wave of the Slave Channel

31.6.4.3 Simultaneous Rewrite when INTTAUBnIm is Generated on an Upper Channel

31.8.1 Interval Timer Mode, Judge Mode, Capture Mode, Count-Up/-Down Mode, and

31.10.1 Example of Combination of TAUBTTINm Input Pulse Interval Measurement Function

31.10.2 Example of Combination of TAUBTTINm Input Signal Width Measurement Function

31.10.3 Example of Combination of TAUBTTINm Input Position Detection Function

31.10.4 Example of Combination of TAUBTTINm Input Period Count Detection Function

and Overflow Interrupt Output Function (during TAUBTTINm Input Period Count

31.12.6.5 Operating Procedure for TAUBTTINm Input Pulse Interval Measurement

31.12.7.5 Operating Procedure for TAUBTTINm Input Signal Width Measurement

31.12.12.4 Operating Procedure for Overflow Interrupt Output Function (during

31.12.13 Overflow Interrupt Output Function (during TAUBTTINm Input Period Count

31.12.13.4 Operating Procedure for Overflow Interrupt Output Function (during

31.13.1.6 Operating Procedure for Simultaneous Rewrite Trigger Generation Function

32.3.4.2 TAUDnRDS — TAUDn Channel Reload Data Control Channel Select Register . 3042

32.6.4.1 Simultaneous Rewrite when the Master Channel (Re)starts Counting

32.6.4.2 Simultaneous Rewrite at the Peak of a Triangular Wave of Slave Channel

32.6.4.3 Simultaneous Rewrite when INTTAUDnIm is Generated on an Upper Channel

32.6.4.4 Simultaneous Rewrite when INTTAUDnIm is Generated on an Upper Channel

Specified by TAUDnRDC.TAUDnRDCm that in Turn is Triggered

32.7.3.2 Synchronous Channel Output Mode 1 with Non-Complementary Modulation

32.7.3.6 Synchronous Channel Output Mode 2 with Complementary Modulation Output . 3077

32.7.3.7 Synchronous Channel Output Mode 2 with Non-Complementary Modulation

32.8.1 Interval Timer Mode, Judge Mode, Capture Mode, Count-up/-down Mode, and

32.10.1 Combination of the TAUDTTINm Input Pulse Interval Measurement Function and

32.10.2 Combination of the TAUDTTINm Input Signal Width Measurement Function and

32.10.3 Combination of the TAUDTTINm Input Position Detection Function and the Interval

32.10.4 Combination of the TAUDTTINm Input Period Count Detection Function and

the Overflow Interrupt Output Function (at Detecting the TAUDTTINm

32.12.7.5 Operating Procedure for TAUDTTINm Input Pulse Interval Measurement

32.12.8.5 Operating Procedure for TAUDTTINm Input Signal Width Measurement

32.12.13.4 Operating Procedure for Overflow Interrupt Output Function (during

32.12.14 Overflow Interrupt Output Function (during TAUDTTINm Input Period Count

32.12.14.4 Operating Procedure for Overflow Interrupt Output Function (during

32.14.1.6 Operating Procedure for Simultaneous Rewrite Trigger Generation Function

32.14.2.5 Operating Procedure for Simultaneous Rewrite Trigger Generation Function

32.16.1.7 Operating Procedure for Non-Complementary Modulation Output Function

32.16.2.7 Operating Procedure for Non-Complementary Modulation Output Function

33.10.1 Combination of the TAUJTTINm Input Position Detection Function and the Interval

33.12.3.5 Operating Procedure for TAUJTTINm Input Pulse Interval Measurement

33.12.4.5 Operating Procedure for TAUJTTINm Input Signal Width Measurement

33.12.7.4 Operating Procedure for Overflow Interrupt Output Function (during

33.12.8 Overflow Interrupt Output Function (during TAUJTTINm Input Period Count Detection) 3439

33.12.8.4 Operating Procedure for Overflow Interrupt Output Function (during

35.6.4 Conflict between Overflow Occurrence and Clear Operation by Encoder Clear Input

35.6.5 Conflict between Underflow Occurrence and Clear Operation by Encoder Clear Input

35.6.10 Conflict between ENCAnLDE Function (Loading Counter Value) and Rewrite of

35.6.11 Conflict between ENCAnLDE Function (Loading Counter Value) and Clear Operation

35.6.12 Up-count after Conflict between ENCAnLDE Function (Loading Counter Value) and

35.6.15 Encoder Operation when Compare Match Clear Control is Enabled and

35.6.16 Encoder Operation when Compare Match Clear Control is Enabled and

35.6.18 Capture Operation Performed upon Clearing by ENCAnEC, ENCAnE0,

35.6.18.2 When the Timing of the ENCAnEC Input is Later than that of the ENCAnE1

Input during Up-count (When ENCAnACL = 1, ENCAnBCL = 0,

35.6.18.3 When the Timing of the ENCAnEC Input is the Same as that of the ENCAnE1

Input during Up-count (When ENCAnACL = 1, ENCAnBCL = 0,

35.6.18.4 When the Timing of the ENCAnEC Input is Earlier than that of the ENCAnE1

Input during Up-count (When ENCAnACL = 1, ENCAnBCL = 0,

35.6.18.5 When the Timing of the ENCAnEC Input is Later than that of the ENCAnE1

Input during Down-count (When ENCAnACL = 1, ENCAnBCL = 0,

36.6.3 Waveforms of A/D Converter Conversion Trigger Output Control Operation

36.7.3.1 PIC0ADTEN4nj — A/D Conversion Trigger Output Control Register 4nj

37.4.1 PWM Waveform Output by PWGA and Operation Waveform for A/D Conversion

37.4.1.2 Operation Waveform when Compare Buffer Register Simultaneous Rewrite

37.4.1.3 Operation Waveform when PWGAnTCBR Register Rewrite for PWGA

38.3.2.19 ADCAnMPXSTBTSELR0 to 4 — MPX Stabilization Time Selection Register

43.5.3 Restrictions when HS IntOSC is Used as the Main Clock Source Instead of MainOSC . 4179

43.5.4 Restrictions when the Writing of OCD_MD and Reset are Occur at the Same Time,

or Restrictions when the Writing of MTR (DBG_CTRLP) and

R01UH0684EJ0110 Rev.1.10 Page 95 of 4535 Dec 26, 2018 Section 1A Overview of RH850/F1KH-D8 1A.1 RH850/F1KH Product Features The features of the RH850/F1KH are described below. The RH850/F1KH is a 32-bit single-chip microcontroller with two G3KH CPU core. The key features of the F1KH are low power consumption, high computational processing power, and a wide variety of internal peripheral functions. To reduce supply current in a variety of applications, a wide range of power reducing measures are available. For example, there is a Low Power Sampler (LPS), that can poll signals input to the analog and digital input pins without CPU core interaction, and DeepSTOP mode in which the power supply to the most circuits of the microcontroller can be turned off.

Applications

The RH850/F1KH is ideal for automotive electronics, such as BCM (body control module), gateway, HVAC, lighting modules, and many other applications. RH850/F1KH, RH850/F1KM Renesas microcontroller R01UH0684EJ0110 Rev.1.10 Dec 26, 2018

RH850/F1KH, RH850/F1KM Section 1A Overview of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 96 of 4535 Dec 26, 2018 1A.2 RH850/F1KH Functions Table 1A.1 Overview of Product RH850/F1KH-D8 Product Name 176 Pins 233 Pins 324 Pins Memory See Table 1A.2, Product Lineup. External Memory Access Controller (MEMC) 23 bit Address Bus 24 bit Address Bus Serial Flash Memory I/F (SFMA) Bus width 4 bit Mode SDR Max. clock 40 MHz Memory Card I/F (MMCA) Bus width Not provided 8 bit Mode Backward-compatible Max. clock 20 MHz CPU CPU System G3KH (Dual Core) CPU frequency 240 MHz max. FPU Single-precision Protection Function Memory Protection Unit (MPU) Provided Internal Peripheral- device Guard (IPG) Provided Processor Element Guard (PEG) Provided DMA 64 channels Operating clock Main Oscillator (MainOSC) 8/16/20/24 MHz Low Speed Internal Oscillator (LS IntOSC) 240 kHz (typ.) High Speed Internal Oscillator (HS IntOSC) 8 MHz (typ.) PLL PLL0 (for CPU, with SSCG) Provided PLL1 (for CPU/Peripheral) Provided Sub Oscillator (SubOSC) 32.768 kHz I/O port 144 174 246 A/D converter ADCA0 Physical input channels Total 34 ch (12 bit resolution: 16 ch + 10 bit resolution: 18 ch) External multiplexer support for channel number extension Provided Channels with T&H Provided ADCA1 Physical input channels Total 24 ch (12 bit resolution: 16 ch + 10 bit resolution: 8 ch) Total 36 ch (12 bit resolution: 16 ch + 10 bit resolution: 20 ch) External multiplexer support for channel number extension Not provided Channels with T&H Not provided

RH850/F1KH, RH850/F1KM Section 1A Overview of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 97 of 4535 Dec 26, 2018 Table 1A.1 Overview of Product RH850/F1KH-D8 Product Name 176 Pins 233 Pins 324 Pins Timer Timer Array Unit D (TAUD) 1 unit (16 bit resolution timers × 16 channels /unit) Timer Array Unit B (TAUB) 2 units (16 bit resolution timers × 16 channels /unit) Timer Array Unit J (TAUJ) 4 units (32 bit resolution timers × 4 channels /unit) Operating System Timer (OSTM) 10 units Real-Time Clock (RTCA) 1 unit Encoder Timer (ENCA) 1 unit Window Watchdog Timer A (WDTA) 3 units Serial interfaces Clocked Serial Interface G (CSIG) 5 channels Clocked Serial Interface H (CSIH) 5 channels CAN Interface (RS-CANFD) 8 channels 12 channels LIN/UART Interface (RLIN3) 8 channels LIN Master Interface (RLIN2) 10 channels 12 channels 16 channels I2C Interface (RIIC) 2 channels Clock Extension Peripheral Interface (CXP1) Not provided Single Edge Nibble Transmission (RSENT) 2 channels FlexRay Interface (FLXA) 2 channel (A ch, B ch) Ethernet AVB (ETNB) 1 channel (MII) 2 channels (MII) External Interrupts Maskable 24 Non-maskable (NMI) 1 Other functions Clock Monitors (CLMA) For PLL0, PLL1, HS IntOSC, MainOSC Data CRC (DCRA) 4 channels Low-Voltage Indicator (LVI) Provided Power-On Clear (POC) Provided Core Voltage Monitors (CVM) Provided Error Correction Coding (ECC) For Code flash, Data flash, Local RAM, Retention RAM, Global RAM, CSIH, RS-CANFD, FLXA, ETNB For Code flash, Data flash, Local RAM, Retention RAM, Global RAM, CSIH, RS-CANFD, FLXA, ETNB, MMCA Low Power Sampler (LPS) Provided PWM Output/Diagnostic (PWM-Diag) 72 channels 80 channels 96 channels Motor Control 1 unit Key Return (KR) 8 channels CLOCK OUTPUT (FOUT) Provided RESET OUTPUT ( RESETOUT ) Provided Intelligent Cryptographic Unit Master D (ICUMD) Provided On-Chip debug (OCD) Provided Boundary Scan Provided

RH850/F1KH, RH850/F1KM Section 1A Overview of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 98 of 4535 Dec 26, 2018 Table 1A.1 Overview of Product RH850/F1KH-D8 Product Name 176 Pins 233 Pins 324 Pins Voltage supply Internal supply REG0VCC (for AWO) VPOC to 5.5 V REG1VCC (for ISO) VPOC to 3.6 V Input/output buffer supplies VPOC to 5.5 V A/D Converter supplies 3.0 to 5.5 V Package 176-pin LQFP 233-pin FPBGA 324-pin FPBGA

RH850/F1KH, RH850/F1KM Section 1A Overview of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 99 of 4535 Dec 26, 2018 1A.3 RH850/F1KH Product Lineup Table 1A.2 Product Lineup F1KH-D8 Memory Part Name Local RAM (LRAM) Global RAM (GRAM) Retention RAM (RRAM) Trace RAM Operating Temperature (Ta) Pin Count CPU Frequency Code Flash Data Flash CPU1 CPU2 –40°C to +105°C Package –40°C to +125°C Package 176 pins 240 MHz max.

6 MB 256 KB 160 KB 160 KB 512 KB 64 KB Not

8 MB 192 KB 192 KB 576 KB 32 KB R7F7017093AFP-C

max.

8 MB 192 KB 192 KB 576 KB 32 KB R7F7017113ABG-C

max.

8 MB 192 KB 192 KB 576 KB 32 KB R7F7017153ABG-C

RH850/F1KH, RH850/F1KM Section 1A Overview of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 100 of 4535 Dec 26, 2018 1A.4 RH850/F1KH Product Block Diagrams System control Flash interface Code flash (8 MB (max.)) Global RAM (576 KB (max.)) /Retention RAM (64 KB) DMA (64 ch) Local RAM (192 KB (max.)) Trace RAM*1 (32 KB) Debug CPU1 (PE1) SEG CPU core INTC1 MPU FPU IPIRSS MEV CPU2 (PE2) SEG CPU core INTC1 MPU FPU Local RAM (192 KB (max.)) System interconnect MainOSC LS IntOSC HS IntOSC SubOSC PLL0 PLL1 STBC CLMA (4 ch) CVM LVI POC LPS H-Bus P-Bus Peripheral Group 1 Flash controller DCRA (4 ch) Port RSENT (2 ch) ADCA0 RLIN3 (8 ch) RLIN2 (10 ch) RIIC (2 ch) KR (8 ch) PWM-Diag (72 ch) INTC2 DMA reg ICUMD WDTA (3 units) TAUD (1 unit) TAUB (2 units) TAUJ (4 units) RTCA (1 unit) ENCA (1 unit) Motor control ADCA1 ETNB reg OSTM (10 units) CSIH (5 ch) CSIG (5 ch) Data flash (256 KB (max.)) RS-CANFD (8 ch) FLXA (2 ch) Peripheral Group 5 Peripheral Group 4 Peripheral Group 3 Peripheral Group 2 ETNB (1 ch) MEMC SFMA IPG IPG Note 1. The trace RAM is only supported by products with 8 MB code flash memory. Figure 1A.1 Internal Block Diagram (RH850/F1KH-D8 176-Pin Version)

RH850/F1KH, RH850/F1KM Section 1A Overview of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 102 of 4535 Dec 26, 2018 System control Flash interface Code flash (8 MB (max.)) Global RAM (576 KB (max.)) /Retention RAM (64 KB) DMA (64ch) Local RAM (192 KB (max.)) Trace RAM*1 (32 KB) Debug CPU1 (PE1) SEG CPU core INTC1 MPU FPU IPIRSS MEV CPU2 (PE2) SEG CPU core INTC1 MPU FPU Local RAM (192 KB (max.)) System interconnect MainOSC LS IntOSC HS IntOSC SubOSC PLL0 PLL1 STBC CLMA (4 ch) CVM LVI POC LPS H-Bus P-Bus Peripheral Group 1 Flash controller DCRA (4 ch) Port RSENT (2 ch) ADCA0 RLIN3 (8 ch) RLIN2 (16 ch) RIIC (2 ch) KR (8 ch) PWM-Diag (96 ch) INTC2 DMA reg ICUMD WDTA (3 units) TAUD (1 unit) TAUB (2 units) TAUJ (4 units) RTCA (1 unit) ENCA (1 unit) Motor control ADCA1 ETNB reg OSTM (10 units) CSIH (5 ch) CSIG (5 ch) Data flash (256 KB (max.)) RS-CANFD (12 ch) FLXA (2 ch) Peripheral Group 5 Peripheral Group 4 Peripheral Group 3 Peripheral Group 2 ETNB (2 ch) MEMC SFMA IPG IPG MMCA Note 1. The trace RAM is only supported by products with 8 MB code flash memory. Figure 1A.4 Internal Block Diagram (RH850/F1KH-D8 324-Pin Version)

R01UH0684EJ0110 Rev.1.10 Page 103 of 4535 Dec 26, 2018 Section 1B Overview of RH850/F1KM-S4 1B.1 RH850/F1KM Product Features The features of the RH850/F1KM are described below. The RH850/F1KM is a 32-bit single-chip microcontroller with a G3KH CPU core. The key features of the F1KM are low power consumption, high computational processing power, and a wide variety of internal peripheral functions. To reduce supply current in a variety of applications, a wide range of power reducing measures are available. For example, there is a Low Power Sampler (LPS), that can poll signals input to the analog and digital input pins without CPU core interaction, and DeepSTOP mode in which the power supply to the most circuits of the microcontroller can be turned off. The RH850/F1KM is ideal for automotive electronics, such as BCM (body control module), gateway, HVAC, lighting modules, and many other applications. RH850/F1KH, RH850/F1KM Renesas microcontroller R01UH0684EJ0110 Rev.1.10 Dec 26, 2018

RH850/F1KH, RH850/F1KM Section 1B Overview of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 104 of 4535 Dec 26, 2018 1B.2 RH850/F1KM Functions Table 1B.1 Overview of Product Product Name RH850/F1KM-S4

100 Pins 144 Pins 176 Pins 233 Pins 272 Pins

Memory See Table 1B.2, Product Lineup. External Memory Access Controller (MEMC) Not provided 23 bit Address Bus 24 bit Address Bus Serial Flash Memory I/F (SFMA) Bus width Not provided 4 bit Mode SDR Max. clock 40 MHz CPU CPU System G3KH CPU frequency 240 MHz max. FPU Single-precision Protection Function Memory Protection Unit (MPU) Provided Internal Peripheral-device Guard (IPG) Provided Processor Element Guard (PEG) Provided DMA 32 channels Operating clock Main Oscillator (MainOSC) 8/16/20/24 MHz Low Speed Internal Oscillator (LS IntOSC) 240 kHz (typ.) High Speed Internal Oscillator (HS IntOSC) 8 MHz (typ.) PLL PLL0 (for CPU, with SSCG) Provided PLL1 (for CPU/Peripheral) Provided Sub Oscillator (SubOSC) Not provided 32.768 kHz I/O port 75 114 144 174 214 A/D converter ADCA0 Physical input channels Total 32 ch (12 bit resolution: 16 ch + 10 bit resolution: 16 ch) Total 34 ch (12 bit resolution: 16 ch + 10 bit resolution: 18 ch) External multiplexer support for channel number extension Provided Channels with T&H Provided

RH850/F1KH, RH850/F1KM Section 1B Overview of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 105 of 4535 Dec 26, 2018 Table 1B.1 Overview of Product Product Name RH850/F1KM-S4 (12 bit resolution: 8 ch + 10 bit resolution: 4 ch) Total 24 ch (12 bit resolution: 16 ch + 10 bit resolution: 8 ch) Total 36 ch (12 bit resolution: 16 ch + 10 bit resolution: 20 ch) External multiplexer support for channel number extension Not provided Channels with T&H Not provided Timer Timer Array Unit D (TAUD) 1 unit (16 bit resolution timers × 16 channels /unit) Timer Array Unit B (TAUB) 1 unit (16 bit resolution timers × 16 channels /unit) 2 units (16 bit resolution timers × 16 channels /unit) Timer Array Unit J (TAUJ) 4 units (32 bit resolution timers × 4 channels /unit) Operating System Timer (OSTM) 5 units Real-Time Clock (RTCA) 1 unit Encoder Timer (ENCA) 1 unit Window Watchdog Timer A (WDTA) 2 units Serial interfaces Clocked Serial Interface G (CSIG) 1 channel 2 channels 4 channels Clocked Serial Interface H (CSIH) 4 channels CAN Interface (RS-CANFD) 8 channels LIN/UART Interface (RLIN3) 3 channels 6 channels 8 channels LIN Master Interface (RLIN2) 3 channels 6 channels 10 channels 12 channels I2C Bus Interface (RIIC) 2 channels Clock Extension Peripheral Interface (CXP1) Not provided Single Edge Nibble Transmission (RSENT) 1 channel 2 channels FlexRay Interface (FLXA) 2 channel (A ch, B ch) Ethernet AVB (ETNB) Not provided 1 channel (MII) External Interrupts Maskable 14 24 Non-maskable (NMI) 1 Other functions Clock Monitors (CLMA) For PLL0, PLL1, HS IntOSC, MainOSC Data CRC (DCRA) 4 channels Low-Voltage Indicator (LVI) Provided Power-On Clear (POC) Provided Core Voltage Monitors (CVM) Provided Error Correction Coding (ECC) For Code flash, Data flash, Local RAM, Retention RAM, Global RAM, CSIH, RS-CANFD, FLXA For Code flash, Data flash, Local RAM, Retention RAM, Global RAM, CSIH, RS-CANFD, FLXA, ETNB

RH850/F1KH, RH850/F1KM Section 1B Overview of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 106 of 4535 Dec 26, 2018 Table 1B.1 Overview of Product Product Name RH850/F1KM-S4 Low Power Sampler (LPS) Provided PWM Output/Diagnostic (PWM-Diag) 44 channels 64 channels 72 channels 80 channels 96 channels Motor Control 1 unit Key Return (KR) 8 channels CLOCK OUTPUT (FOUT) Provided RESET OUTPUT ( RESETOUT ) Provided Intelligent Cryptographic Unit Master D (ICUMD) Provided On-Chip debug (OCD) Provided Boundary Scan Provided Voltage supply Internal supply VPOC to 5.5 V Input/output buffer supplies VPOC to 5.5 V A/D Converter supplies 3.0 to 5.5 V Package 100-pin LQFP 144-pin LQFP 176-pin LQFP 233-pin FPBGA 272-pin FPBGA

RH850/F1KH, RH850/F1KM Section 1B Overview of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 107 of 4535 Dec 26, 2018 1B.3 RH850/F1KM Product Lineup Table 1B.2 Product Lineup F1KM-S4 Memory Part Name Pin Count CPU Frequency Code Flash Data Flash Local RAM (LRAM) Global RAM (GRAM) Retention RAM (RRAM) Trace RAM Operating Temperature (Ta) –40°C to +105°C Package –40°C to +125°C Package 100 pins 240 MHz max. 3 MB 128 KB 192 KB 128 KB 64 KB Not available R7F7016443AFP-C LQFP

4 MB 256 KB 192KB 32 KB R7F7016453AFP-C

144 pins 240 MHz max. 3 MB 128 KB 192 KB 128 KB 64 KB Not available R7F7016463AFP-C LQFP

4 MB 256 KB 192KB 32 KB R7F7016473AFP-C

176 pins 240 MHz max. 3 MB 128 KB 192 KB 128 KB 64 KB Not available R7F7016483AFP-C LQFP

4 MB 256 KB 192KB 32 KB R7F7016493AFP-C

233 pins 240 MHz max. 3 MB 128 KB 192 KB 128 KB 64 KB Not available R7F7016503ABG-C FPBGA R7F7016504ABG-C FPBGA

4 MB 256 KB 192KB 32 KB R7F7016513ABG-C

272 pins 240 MHz max. 3 MB 128 KB 192 KB 128 KB 64 KB Not available R7F7016523ABG-C FPBGA R7F7016524ABG-C FPBGA

4 MB 256 KB 192KB 32 KB R7F7016533ABG-C

RH850/F1KH, RH850/F1KM Section 1B Overview of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 108 of 4535 Dec 26, 2018 1B.4 RH850/F1KM Product Block Diagrams P-Bus Peripheral Group 1 Peripheral Group 2 Peripheral Group 3 Peripheral Group 4 Peripheral Group 5 System interconnect H-Bus Local RAM (256 KB (max.)) Trace RAM*1 (32 KB) Debug Global RAM (192 KB (max.)) /Retention RAM (64 KB) DMA (32 ch) System control LVI CLMA (4 ch) LVI MainOSC LS IntOSC HS IntOSC PLL1 STBC CVM POC LPS Code flash (4 MB (max.)) OSTM (5 units) CSIH (4 ch) CSIG (1 ch) RS-CANFD (8 ch) WDTA (2 units) TAUD (1 unit) TAUB (1 unit) TAUJ (4 units) RTCA (1 unit) ENCA (1 unit) Motor control PWM-Diag (44 ch) INTC2 DMA reg ADCA0 RLIN3 (3 ch) RLIN2 (3 ch) RIIC (2 ch) KR (8 ch) Flash controller DCRA (4 ch) Port RSENT (1 ch) Data flash (128 KB (max.)) ICUMD PLL0 FLXA (2 ch) Flash interface INTC1 CPU1 (PE1) SEG CPU core MPU FPUIPG Note 1. The trace RAM is only supported by products with 4 MB code flash memory. Figure 1B.1 Internal Block Diagram (RH850/F1KM-S4 100-Pin Version)

RH850/F1KH, RH850/F1KM Section 1B Overview of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 109 of 4535 Dec 26, 2018 P-Bus Peripheral Group 1 Peripheral Group 2 Peripheral Group 3 Peripheral Group 4 Peripheral Group 5 System interconnect H-Bus Global RAM (192 KB (max.)) /Retention RAM (64 KB) DMA (32 ch) System control LVI CLMA (4 ch) LVI MainOSC LS IntOSC HS IntOSC PLL1 STBC CVM POC LPS Code flash (4 MB (max.)) OSTM (5 units) CSIH (4 ch) CSIG (2 ch) RS-CANFD (8 ch) WDTA (2 units) TAUD (1 unit) TAUB (1 unit) TAUJ (4 units) RTCA (1 unit) ENCA (1 unit) Motor control PWM-Diag (64 ch) INTC2 DMA reg ADCA0 RLIN3 (6 ch) RLIN2 (6 ch) RIIC (2 ch) KR (8 ch) Flash controller DCRA (4 ch) Port RSENT (2 ch) Data flash (128 KB (max.)) ICUMD PLL0 FLXA (2 ch) Flash interface SFMA ADCA1 SubOSC Local RAM (256 KB (max.)) Trace RAM*1 (32 KB) Debug INTC1 CPU1 (PE1) SEG CPU core MPU FPUIPG Note 1. The trace RAM is only supported by products with 4 MB code flash memory. Figure 1B.2 Internal Block Diagram (RH850/F1KM-S4 144-Pin Version)

RH850/F1KH, RH850/F1KM Section 1B Overview of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 110 of 4535 Dec 26, 2018 P-Bus Peripheral Group 1 Peripheral Group 2 Peripheral Group 3 Peripheral Group 4 Peripheral Group 5 System interconnect H-Bus Global RAM (192 KB (max.)) /Retention RAM (64 KB) DMA (32 ch) System control LVI CLMA (4 ch) LVI MainOSC LS IntOSC HS IntOSC PLL1 STBC CVM POC LPS Code flash (4 MB (max.)) OSTM (5 units) CSIH (4 ch) CSIG (4 ch) RS-CANFD (8 ch) WDTA (2 units) TAUD (1 unit) TAUB (2 unit) TAUJ (4 units) RTCA (1 unit) ENCA (1 unit) Motor control PWM-Diag (72 ch) INTC2 DMA reg ADCA0 RLIN3 (8 ch) RLIN2 (10 ch) RIIC (2 ch) KR (8 ch) Flash controller DCRA (4 ch) Port RSENT (2 ch) Data flash (128 KB (max.)) ICUMD PLL0 FLXA (2 ch) Flash interface SFMA ADCA1 SubOSC ETNB MEMC ETNB reg Local RAM (256 KB (max.)) Trace RAM*1 (32 KB) Debug INTC1 CPU1 (PE1) SEG CPU core MPU FPUIPG Note 1. The trace RAM is only supported by products with 4 MB code flash memory. Figure 1B.3 Internal Block Diagram (RH850/F1KM-S4 176-Pin Version)

RH850/F1KH, RH850/F1KM Section 1B Overview of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 111 of 4535 Dec 26, 2018 P-Bus Peripheral Group 1 Peripheral Group 2 Peripheral Group 3 Peripheral Group 4 Peripheral Group 5 System interconnect H-Bus Global RAM (192 KB (max.)) /Retention RAM (64 KB) DMA (32 ch) System control LVI CLMA (4 ch) LVI MainOSC LS IntOSC HS IntOSC PLL1 STBC CVM POC LPS Code flash (4 MB (max.)) OSTM (5 units) CSIH (4 ch) CSIG (4 ch) RS-CANFD (8 ch) WDTA (2 units) TAUD (1 unit) TAUB (2 unit) TAUJ (4 units) RTCA (1 unit) ENCA (1 unit) Motor control PWM-Diag (80 ch) INTC2 DMA reg ADCA0 RLIN3 (8 ch) RLIN2 (12 ch) RIIC (2 ch) KR (8 ch) Flash controller DCRA (4 ch) Port RSENT (2 ch) Data flash (128 KB (max.)) ICUMD PLL0 FLXA (2 ch) Flash interface SFMA ADCA1 SubOSC ETNB MEMC ETNB reg Local RAM (256 KB (max.)) Trace RAM*1 (32 KB) Debug INTC1 CPU1 (PE1) SEG CPU core MPU FPUIPG Note 1. The trace RAM is only supported by products with 4 MB code flash memory. Figure 1B.4 Internal Block Diagram (RH850/F1KM-S4 233-Pin Version)

RH850/F1KH, RH850/F1KM Section 1B Overview of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 112 of 4535 Dec 26, 2018 P-Bus Peripheral Group 1 Peripheral Group 2 Peripheral Group 3 Peripheral Group 4 Peripheral Group 5 System interconnect H-Bus Global RAM (192 KB (max.)) /Retention RAM (64 KB) DMA (32 ch) System control LVI CLMA (4 ch) LVI MainOSC LS IntOSC HS IntOSC PLL1 STBC CVM POC LPS Code flash (4 MB (max.)) OSTM (5 units) CSIH (4 ch) CSIG (4 ch) RS-CANFD (8 ch) WDTA (2 units) TAUD (1 unit) TAUB (2 unit) TAUJ (4 units) RTCA (1 unit) ENCA (1 unit) Motor control PWM-Diag (96 ch) INTC2 DMA reg ADCA0 RLIN3 (8 ch) RLIN2 (12 ch) RIIC (2 ch) KR (8 ch) Flash controller DCRA (4 ch) Port RSENT (2 ch) Data flash (128 KB (max.)) ICUMD PLL0 FLXA (2 ch) Flash interface SFMA ADCA1 SubOSC ETNB MEMC ETNB reg Local RAM (256 KB (max.)) Trace RAM*1 (32 KB) Debug INTC1 CPU1 (PE1) SEG CPU core MPU FPUIPG Note 1. The trace RAM is only supported by products with 4 MB code flash memory. Figure 1B.5 Internal Block Diagram (RH850/F1KM-S4 272-Pin Version)

R01UH0684EJ0110 Rev.1.10 Page 113 of 4535 Dec 26, 2018 Section 1C Overview of RH850/F1KM-S1 1C.1 RH850/F1KM Product Features The features of the RH850/F1KM are described below. The RH850/F1KM is a 32-bit single-chip microcontroller with a G3KH CPU core. The key features of the F1KM are low power consumption, high computational processing power, and a wide variety of internal peripheral functions. To reduce supply current in a variety of applications, a wide range of power reducing measures are available. For example, there is a Low Power Sampler (LPS), that can poll signals input to the analog and digital input pins without CPU core interaction, and DeepSTOP mode, in which the power supply to the most circuits of the microcontroller can be turned off. The RH850/F1KM is ideal for automotive electronics, such as BCM (body control module), gateway, HVAC, lighting modules, and many other applications. RH850/F1KH, RH850/F1KM Renesas microcontroller R01UH0684EJ0110 Rev.1.10 Dec 26, 2018

RH850/F1KH, RH850/F1KM Section 1C Overview of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 114 of 4535 Dec 26, 2018 1C.2 RH850/F1KM Functions Table 1C.1 Overview of Product Product Name RH850/F1KM-S1

48 Pins 64 Pins 80 Pins 100 Pins

Memory See Table 1C.2, Product Lineup. External Memory Access Controller (MEMC) Not provided CPU CPU System G3KH CPU frequency 120 MHz max FPU Single-Precision Protection Function Memory Protection Unit (MPU) Provided Internal Peripheral Guard (IPG) Provided Processor Element Guard (PEG) Provided DMA 16 channels Operating clock Main Oscillator (MainOSC) 8/16/20/24 MHz Low Speed Internal Oscillator (LS IntOSC) 240 kHz(typ.) High Speed Internal Oscillator (HS IntOSC) 8 MHz(typ.) PLL PLL0 (for CPU, with SSCG) Not provided PLL1 (for CPU/Peripheral) Provided Sub Oscillator (SubOSC) Not provided I/O port 33 49 65 81 A/D converter ADCA0 Physical input channels Total 12 ch Total 21 ch Total 25 ch Total 36 ch (12 bit resolution: 8 ch + 10 bit resolution: 4 ch) (12 bit resolution: 10 ch + 10 bit resolution: 11 ch) (12 bit resolution: 11 ch + 10 bit resolution: 14 ch) (12 bit resolution: 16 ch + 10 bit resolution: 20 ch) External multiplexer support for channel number extension Provided Channels with T&H 3 6 ADCA1 Physical input channels Not provided External multiplexer support for channel number extension Not provided Channels with T&H Not provided Timer Timer Array Unit D (TAUD) 1 unit (16 bit resolution timers × 16 channels /unit) Timer Array Unit B (TAUB) Not provided 1 unit (16 bit resolution timers × 16 channels /unit) Timer Array Unit J (TAUJ) 4 units (32 bit resolution timers × 4 channels /unit) Operating System Timer (OSTM) 1 unit Real-Time Clock (RTCA) 1 unit Encoder Timer (ENCA) 1 unit Window Watchdog Timer A (WDTA) 2 units

RH850/F1KH, RH850/F1KM Section 1C Overview of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 115 of 4535 Dec 26, 2018 Table 1C.1 Overview of Product Product Name RH850/F1KM-S1 Serial interfaces Clocked Serial Interface G (CSIG) 1 channel Clocked Serial Interface H (CSIH) 1 channel 3 channels 4 channels CAN Interface (RS-CANFD) 1 channel 3 channels 6 channels LIN/UART Interface (RLIN3) 1 channel 2 channels 3 channels 4 channels LIN Master Interface (RLIN2) 2 channels 3 channels I2C Bus Interface (RIIC) 2 channels Clock Extension Peripheral Interface (CXP1) Not provided Single Edge Nibble Transmission (RSENT) 2 channels External Interrupts Maskable 8 12 13 Non-maskable (NMI) 1 Other functions Clock Monitors (CLMA) For PLL1, HS IntOSC, MainOSC Data CRC (DCRA) 1 channel 4 channels Low-Voltage Indicator (LVI) Provided Power-On Clear (POC) Provided Core Voltage Monitors (CVM) Provided Error Correction Coding (ECC) For Code Flash, Data Flash, Local RAM, Retention RAM, CSIH, RS-CANFD Low Power Sampler (LPS) Provided PWM Output/Diagnostic (PWM-Diag) 13 channels 24 channels 48 channels Motor Control 1 unit Key Return (KR) 6 channels 8 channels CLOCK OUTPUT (FOUT) Provided RESET OUTPUT ( RESETOUT ) Not Provided Provided Intelligent Cryptographic Unit E (ICUSE) Provided Secure WDT (SWDT) Provided On-Chip debug (OCD) Provided Boundary Scan Provided Voltage supply Internal supply VPOC to 5.5 V Input/output buffer supplies VPOC to 5.5 V A/D Converter supplies 3.0 V to 5.5 V Package 48-pin LQFP 64-pin LQFP 80-pin LQFP 100-pin LQFP

RH850/F1KH, RH850/F1KM Section 1C Overview of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 116 of 4535 Dec 26, 2018 1C.3 RH850/F1KM Product Lineup Table 1C.2 Product Lineup F1KM-S1 Memory Part Name Pin Count CPU Frequency Code Flash Data Flash Local RAM (LRAM) Retention RAM (RRAM) Trace RAM Operating Temperature (Ta) –40°C to +105°C Package –40°C to +125°C Package 100 pins 120 MHz max.

1024 KB 64 KB 96 KB 32 KB 32 KB R7F7016843AFP-C

768 KB 64 KB Not

512 KB 32 KB Not

max.

1024 KB 64 KB 96 KB 32 KB 32 KB R7F7016873AFP-C

max.

1024 KB 64 KB 96 KB 32 KB 32 KB R7F7016903AFP-C

max.

1024 KB 64 KB 96 KB 32 KB 32 KB R7F7016933AFP-C

RH850/F1KH, RH850/F1KM Section 1C Overview of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 117 of 4535 Dec 26, 2018 1C.4 RH850/F1KM Product Block Diagrams P-Bus System control LVI Peripheral Group 1 Peripheral Group 2 Peripheral Group 3 Flash interface System interconnect DMA (16 ch) OSTM (1 unit) CSIH (1 ch) CSIG (1 ch) RS-CANFD (1 ch) WDTA (2 units) TAUD (1 unit) TAUJ (4 units) RTCA (1 unit) ENCA (1 unit) Motor control PWM-Diag (13 ch) INTC2 DMA reg Data flash (64 KB) ADCA0 RLIN3 (1 ch) RLIN2 (2 ch) RIIC (2 ch) KR (6 ch) Flash controller DCRA (1 ch) Port RSENT (2 ch) ICUSE CLMA (3 ch) LVI MainOSC LS IntOSC HS IntOSC PLL1 STBC CVM POC LPS Code flash (1 MB (max.)) Local RAM (96 KB (max.)) Trace RAM*1 (32 KB) Debug Retention RAM (32 KB) INTC1 CPU1 (PE1) SEG CPU core MPU FPUIPG Note 1. The trace RAM is only supported by products with 1 MB code flash memory. Figure 1C.1 Internal Block Diagram (RH850/F1KM-S1 48-Pin Version)

RH850/F1KH, RH850/F1KM Section 1C Overview of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 118 of 4535 Dec 26, 2018 P-Bus System control LVI Peripheral Group 1 Peripheral Group 2 Peripheral Group 3 Flash interface System interconnect DMA (16 ch) OSTM (1 unit) CSIH (1 ch) CSIG (1 ch) RS-CANFD (3 ch) WDTA (2 units) TAUD (1 unit) TAUJ (4 units) RTCA (1 unit) ENCA (1 unit) Motor control PWM-Diag (24 ch) INTC2 DMA reg Data flash (64 KB) ADCA0 RLIN3 (2 ch) RLIN2 (2 ch) RIIC (2 ch) KR (8 ch) Flash controller DCRA (1 ch) Port RSENT (2 ch) ICUSE CLMA (3 ch) LVI MainOSC LS IntOSC HS IntOSC PLL1 STBC CVM POC LPS Code flash (1 MB (max.)) Local RAM (96 KB (max.)) Trace RAM*1 (32 KB) Debug Retention RAM (32 KB) INTC1 CPU1 (PE1) SEG CPU core MPU FPUIPG Note 1. The trace RAM is only supported by products with 1 MB code flash memory. Figure 1C.2 Internal Block Diagram (RH850/F1KM-S1 64-Pin Version)

RH850/F1KH, RH850/F1KM Section 1C Overview of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 119 of 4535 Dec 26, 2018 P-Bus System control LVI Peripheral Group 1 Peripheral Group 2 Peripheral Group 3 Flash interface System interconnect DMA (16 ch) OSTM (1 unit) CSIH (3 ch) CSIG (1 ch) RS-CANFD (3 ch) WDTA (2 units) TAUD (1 unit) TAUB (1 unit) TAUJ (4 units) RTCA (1 unit) ENCA (1 unit) Motor control PWM-Diag (24 ch) INTC2 DMA reg Data flash (64 KB) ADCA0 RLIN3 (3 ch) RLIN2 (2 ch) RIIC (2 ch) KR (8 ch) Flash controller DCRA (4 ch) Port RSENT (2 ch) ICUSE CLMA (3 ch) LVI MainOSC LS IntOSC HS IntOSC PLL1 STBC CVM POC LPS Code flash (1 MB (max.)) Local RAM (96 KB (max.)) Trace RAM*1 (32 KB) Debug Retention RAM (32 KB) INTC1 CPU1 (PE1) SEG CPU core MPU FPUIPG Note 1. The trace RAM is only supported by products with 1 MB code flash memory. Figure 1C.3 Internal Block Diagram (RH850/F1KM-S1 80-Pin Version)

RH850/F1KH, RH850/F1KM Section 1C Overview of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 120 of 4535 Dec 26, 2018 P-Bus System control LVI Peripheral Group 1 Peripheral Group 2 Peripheral Group 3 Flash interface System interconnect DMA (16 ch) Local RAM (96 KB (max.)) Trace RAM*1 (32 KB) Debug OSTM (1 unit) CSIH (4 ch) CSIG (1 ch) RS-CANFD (6 ch) WDTA (2 units) TAUD (1 unit) TAUB (1 unit) TAUJ (4 units) RTCA (1 unit) ENCA (1 unit) Motor control PWM-Diag (48 ch) INTC2 DMA reg Data flash (64 KB) ADCA0 RLIN3 (4 ch) RLIN2 (3 ch) RIIC (2 ch) KR (8 ch) Flash controller DCRA (4 ch) Port RSENT (2 ch) ICUSE CLMA (3 ch) LVI MainOSC LS IntOSC HS IntOSC PLL1 STBC CVM POC LPS Code flash (1 MB (max.)) Retention RAM (32 KB) INTC1 CPU1 (PE1) SEG CPU core MPU FPUIPG Note 1. The trace RAM is only supported by products with 1 MB code flash memory. Figure 1C.4 Internal Block Diagram (RH850/F1KM-S1 100-Pin Version)

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 121 of 4535 Dec 26, 2018 Section 2A Pin Function of RH850/F1KH-D8 This section describes the pin and port functions. Section 2A.1, Pin Connection Diagram to Section 2A.5, Recommended Connection of Unused Pins describe the pin connections and respective pins. Section 2A.6, Features of RH850/F1KH Port to Section 2A.13, Description of Port Noise Filter & Edge/Level Detection describe the general port functions. 2A.1 Pin Connection Diagram P10_2 P10_1 P10_0 BVSS BVCC P12_2 P12_1 P12_0 P11_15 P11_7 P11_6 P11_5 P11_4 P11_3 P11_2 P11_1 P10_14 P10_13 P10_12 P10_11 P10_10 P10_9 P10_8 P10_7 P10_6 BVSS P18_7 P18_6 P18_5 P18_4 P18_3 P18_2 P18_1 P18_0 ISOVSS ISOVCL BVCC A1VSS A1VREF AP1_12 AP1_13 AP1_14 AP1_15 AP1_0 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 P10_3 1 132 AP1_1 P10_4 2 131 AP1_2 P10_5 3 130 AP1_3 BVCC 4 129 AP1_4 BVSS 5 128 AP1_5 P10_15 6 127 AP1_6 P11_0 7 126 AP1_7 P11_8 8 125 AP1_8 P11_9 9 124 AP1_9 P11_10 10 123 AP1_10 P11_11 11 122 AP1_11 P11_12 12 121 EVCC ISOVCL 13 120 P20_4 ISOVSS 14 119 P20_5 P12_3 15 118 P20_0 P12_4 16 117 P20_1 P12_5 17 116 P20_2 P0_0 18 115 P20_3 P0_1 19 114 REG1VCC P0_2 20 113 ISOVSS P0_3 21 112 P9_4 EVCC 22 111 P9_3 P0_4 23 110 P9_2 P0_5 24 109 P9_1 P0_6 25 108 P9_0 P0_11 26 107 EVSS P0_12 27 106 AP0_0 P0_13 28 105 AP0_1 P0_14 29 104 AP0_2 P1_0 30 103 AP0_3 P1_1 31 102 AP0_4 P1_2 32 101 AP0_5 P1_3 33 100 AP0_6 P1_12 34 99 AP0_7 P1_13 35 98 AP0_8 P2_6 36 97 AP0_9 EVSS 37 96 AP0_10 P8_2 38 95 AP0_11 P8_10 39 94 AP0_12 P8_11 40 93 AP0_13 P8_12 41 92 AP0_14 JP0_5 42 91 AP0_15 JP0_4 43 90 A0VREF JP0_3 44 89 A0VSS JP0_2 JP0_1 JP0_0 P2_1 P2_0 P1_11 P1_10 P1_9 P1_8 RESET EVCC XT1 IP0_0 AWOVSS AWOVCL REG0VCC FLMD0 P2_3 P2_2 JP0_6 P0_10 P0_9 P0_8 P0_7 EVSS ISOVSS ISOVCL P1_5 P1_4 P2_4 P2_5 P1_14 P1_15 P8_0 P8_1 P8_3 P8_4 P8_5 P8_6 P8_7 P8_8 P8_9 Figure 2A.1 Pin Connection Diagram (176-Pin LQFP)

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 123 of 4535 Dec 26, 2018 P24_5 P24_2 P24_3 P22_7 P12_1 P12_0 P22_11 P11_5 P11_4 P22_15 P11_1 P10_12 P10_10 P19_1 P19_0 P18_15 P10_4 P24_4 P24_1 P24_0 P13_1 P22_9 P22_12 P11_6 P22_14 P21_1 P10_14 P10_11 P10_8 P19_3 P18_7 P18_13 P22_6 P10_5 P10_3 P10_2 P22_8 P13_0 P22_10 P11_7 P22_13 P11_3 P10_13 P10_9 P10_7 P18_14 P18_12 P18_11 P22_4 P22_5 BVCC BVCC P10_1 P10_0 P12_2 P11_15 BVSS P11_2 BVCC BVSS P10_6 P19_2 P18_5 ISOVSS P11_8 P11_0 BVCC A1VSS AP1_2 AP1_4 AP1_7 P22_1 P11_9 BVCC A1VREF AP1_6 AP1_9 AP1_8 P11_11 P11_10 BVSS BVSS BVSS BVSS BVSS BVSS AP1_10 AP1_11 P20_6 P20_7 P11_12 P21_0 ISOVCL BVSS BVSS BVSS BVSS BVSS EVCC P20_8 P20_9 P20_4 P21_2 P21_3 ISOVSS BVSS BVSS BVSS BVSS EVSS EVSS P20_0 P20_5 P20_1 P13_5 P13_2 BVSS BVSS BVSS BVSS EVSS EVSS EVCC P20_2 P20_3 P20_10 P21_8 P13_3 P12_3 EVSS EVSS EVSS EVSS EVSS REG1VCC P20_11 P20_12 P20_15 P21_10 P13_4 P13_6 ISOVSS P20_13 P20_14 P23_10 P21_13 P13_7 P12_4 P9_4 P23_7 P23_8 P23_9 P21_14 P0_1 P0_2 JP0_2 JP0_1 P1_9 EVCC AWOVCL REG0VCC P0_9 ISOVSS ISOVCL P9_3 P23_6 P23_4 P23_5 P0_3 P0_6 P0_4 JP0_3 P2_1 P2_13 P3_0 FLMD0 JP0_6 P0_8 P0_7 P1_14 P9_2 P9_1 P23_2 P23_3 P0_11 P0_13 EVCC P2_0 P1_11 P2_14 IP0_0 P2_15 P2_3 P2_2 P1_5 P1_4 EVSS P9_0 P23_0 P23_1 P0_12 P0_14 P1_1 P1_10 P1_8 RESET XT1 AWOVSS X2 X1 P0_10 P2_4 A0VREF AP0_5 AP0_2 AP0_0 BVSS P24_6 P24_7 P10_15 P22_3 P22_2 P22_0 P21_4 P21_5 P21_6 P21_7 P21_9 P21_11 P21_12 P12_5 P0_0 P0_5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 P1_12 P1_3 P1_13 P2_7 P2_8 P2_11 P2_12 P2_9 P8_12 P8_2 P8_10 JP0_5 P8_11 JP0_4 JP0_0 P1_0 P1_2 P2_6 P2_10 EVSS P1_15 EVSS EVCC P3_7 P3_10 AP0_14 AP0_8 AP0_6 AP0_3 P8_1 P8_5 P3_1 P3_3 P3_6 P3_9 AP0_13 AP0_12 AP0_7 P8_0 P8_4 P8_7 P3_12 P8_8 P3_4 P3_8 AP0_11 AP0_9 P2_5 P8_3 P3_2 P3_11 P8_6 P8_9 P3_5 AP0_15 A0VSS A0VSS AP0_10 AP0_4 AP0_1 P18_6 P18_3 P18_9 P18_0 A1VSS P18_4 P18_8 P18_1 AP1_13 AP1_15 P18_10 P18_2 AP1_12 AP1_0 AP1_1 ISOVCL BVCC AP1_14 AP1_3 AP1_5 EVSS EVSS EVSS EVSS EVSS BVSS EVSS EVSS EVSS EVSS EVSS Top View A B C D E F G H J K L M N P R T U V W Y AA AB A B C D E F G H J K L M N P R T U V W Y AA AB Figure 2A.4 Pin Connection Diagram (324-Pin FPBGA)

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 124 of 4535 Dec 26, 2018 Table 2A.1 Pin Assignment 176-Pin LQFP Pin No. Pin Name

1 P10_3 / TAUD0I7 / TAUD0O7 / RIIC0SCL / KR0I1 / PWGA3O / ADCA0TRG1 / TAPA0VN / CSIH1SSI / MEMC0CLK /

2 P10_4 / TAUD0I9 / TAUD0O9 / RLIN21RX / CAN6TX / KR0I2 / ADCA0SEL0 / ADCA0TRG2 / TAPA0WP / CSIG0SSI /

PWGA53O / ETNB0RXD2 / MEMC0A22

3 P10_5 / TAUD0I11 / TAUD0O11 / CAN6RX / INTP6 / RLIN21TX / KR0I3 / ADCA0SEL1 / TAPA0WN / CSIG0RYI /

CSIG0RYO / ETNB0RXD3 / PWGA54O

4 BVCC

5 BVSS

6 P10_15 / CSIH3RYI / CSIH3RYO / PWGA24O / RLIN22RX / TAUB0I9 / TAUB0O9 / MEMC0RD

7 P11_0 / CSIH2RYI / CSIH2RYO / ADCA1TRG2 / PWGA25O / RLIN22TX / TAUB0I11 / TAUB0O11 / MEMC0WR

8 P11_8 / CSIG1SSI / RLIN35TX / PWGA48O / TAUB1I11 / TAUB1O11 / MEMC0CS0

9 P11_9 / CSIG1SO / RLIN35RX / INTP15 / PWGA49O / TAUB1I13 / TAUB1O13 / MEMC0CS1

10 P11_10 / CSIG1SC / PWGA50O / TAUB1I15 / TAUB1O15 / MEMC0CS2

11 P11_11 / CSIG1SI / RLIN25TX / PWGA51O / TAUB1I0 / TAUB1O0 / MEMC0CS3 / ETNB0RXDV

12 P11_12 / RLIN25RX / PWGA52O / TAUB1I2 / TAUB1O2 / MEMC0WAIT

13 ISOVCL

14 ISOVSS

15 P12_3 / RLIN27RX / PWGA68O / CSIG2SI / MEMC0BEN0 / TAUB1I6 / TAUB1O6

16 P12_4 / RLIN27TX / PWGA69O / CSIG2SC / ETNB0MDIO / MEMC0BEN1

17 P12_5 / PWGA70O / ETNB0MDC / CSIG2SO / TAUB1I4 / TAUB1O4

18 P0_0 / TAUD0I2 / TAUD0O2 / RLIN20RX / CAN0TX / PWGA10O / CSIH0SSI / DPO / TAUJ2I1 / TAUJ2O1

19 P0_1 / TAUD0I4 / TAUD0O4 / CAN0RX / INTP0 / RLIN20TX / PWGA11O / CSIH0SI / APO / TAUJ2I2 / TAUJ2O2

20 P0_2 / TAUD0I6 / TAUD0O6 / CAN1RX / INTP1 / RLIN30TX / PWGA12O / CSIH0SC / DPO / TAUJ2I3 / TAUJ2O3

21 P0_3 / TAUD0I8 / TAUD0O8 / RLIN30RX / INTP10 / CAN1TX / DPIN1 / PWGA13O / CSIH0SO / TAUJ1I0 / TAUJ1O0

22 EVCC

23 P0_4 / RLIN31RX / INTP11 / CAN2TX / PWGA10O / CSIH1SI / SELDP0 / DPIN8 / TAUB0I12 / TAUB0O12

24 P0_5 / CAN2RX / INTP2 / RLIN31TX / DPIN9 / SELDP1 / CSIH1SO / TAUB0I14 / TAUB0O14

25 P0_6 / INTP2 / DPIN10 / SELDP2 / CSIH1SC / PWGA35O

26 P0_11 / RIIC0SDA / DPIN12 / CSIH1CSS2 / TAUB0I8 / TAUB0O8 / RLIN26RX / PWGA34O

27 P0_12 / RIIC0SCL / DPIN13 / PWGA45O / TAUB0I10 / TAUB0O10 / CSIG0SI / RLIN26TX

28 P0_13 / RLIN32RX / INTP12 / PWGA46O / TAUB0I12 / TAUB0O12 / CSIG0SO / CAN5RX / INTP5

29 P0_14 / INTP17 / RLIN32TX / PWGA47O / TAUB0I14 / TAUB0O14 / CSIG0SC / CAN5TX

30 P1_0 / RLIN33RX / INTP13 / TAUJ2I0 / TAUJ2O0 / CSIG4SSI

31 P1_1 / INTP18 / RLIN33TX / CSIG4SC / TAUJ2I1 / TAUJ2O1

32 P1_2 / CAN3RX / INTP3 / DPIN19 / TAUJ2I2 / TAUJ2O2 / CSIG4SI

33 P1_3 / INTP19 / CAN3TX / DPIN23 / CSIG4SO / TAUJ2I3 / TAUJ2O3

34 P1_12 / CAN4RX / INTP4 / RLIN36TX

35 P1_13 / CAN4TX / RLIN36RX / INTP16

36 P2_6 / ADCA0SEL2 / CSIG4RYI / CSIG4RYO

37 EVSS

38 P8_2 / TAUJ0I0 / TAUJ0O0 / DPIN2 / CSIH0CSS0 / INTP6 / PWGA22O / RLIN37TX / ADCA0I4S

39 P8_10 / CSIH3CSS3 / DPIN14 / PWGA42O / RLIN37RX / INTP17 / ADCA0I17S

40 P8_11 / TAUJ1I2 / TAUJ1O2 / DPIN15 / PWGA43O / CSIH1CSS4 / RLIN25RX / ADCA0I18S

41 P8_12 / TAUJ1I3 / TAUJ1O3 / DPIN16 / PWGA44O / CSIH1CSS5 / INTP23 / RLIN25TX / ADCA0I19S

42 JP0_5 / NMI / RTCA0OUT / TAUJ0I3 / TAUJ0O3 / DCURDY / LPDCLKOUT

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 125 of 4535 Dec 26, 2018 Table 2A.1 Pin Assignment 176-Pin LQFP Pin No. Pin Name

43 JP0_4 / DCUTRST

44 JP0_3 / INTP3 / CSCXFOUT / TAUJ0I2 / TAUJ0O2 / DCUTMS

45 JP0_2 / INTP2 / TAUJ0I1 / TAUJ0O1 / FPCK / DCUTCK / LPDCLK

46 JP0_1 / INTP1 / TAUJ0I0 / TAUJ0O0 / FPDT / DCUTDO / LPDO

47 JP0_0 / INTP0 / TAUJ2I0 / TAUJ2O0 / FPDR / FPDT / DCUTDI / LPDI / LPDIO

48 P2_1 / RLIN27TX / CAN6TX

49 P2_0 / RLIN27RX / CAN6RX / INTP6

50 P1_11 / ADCA1TRG2 / RLIN24TX / DPIN22 / INTP14

51 P1_10 / RLIN24RX / DPIN21 / INTP22 / ADCA1TRG1

52 P1_9 / DPIN20 / INTP21

53 P1_8

54 RESET

55 EVCC

56 XT1

57 IP0_0 / XT2

58 AWOVSS

59 AWOVCL

60 REG0VCC

63 FLMD0

64 P2_3 / RLIN28TX / CSIH4CSS1

65 P2_2 / RLIN28RX / CSIH4CSS0

66 JP0_6 / EVTO

67 P0_10 / INTP3 / CSIH1CSS1 / DPIN11 / RLIN22TX / TAUB0I6 / TAUB0O6 / CAN4TX

68 P0_9 / INTP12 / CSIH1CSS0 / DPIN7 / RLIN22RX / TAUB0I4 / TAUB0O4 / CAN4RX / INTP4

69 P0_8 / INTP16 / RLIN21TX / DPIN6 / CSIH0CSS6 / CSIH1SSI / TAUB0I2 / TAUB0O2 / CAN3TX

70 P0_7 / RLIN21RX / DPIN5 / CSCXFOUT / CSIH1RYI / CSIH1RYO / TAUB0I0 / TAUB0O0 / CAN3RX / INTP3

71 EVSS

72 ISOVSS

73 ISOVCL

74 P1_5 / ADCA1TRG0 / RLIN35TX / DPIN17 / INTP20 / CSIH4SC

75 P1_4 / RLIN35RX / INTP15 / DPIN18 / CSIH4SI

76 P2_4 / RLIN29RX / ADCA0SEL0 / CSIH4SO

77 P2_5 / RLIN29TX / CSIH4SSI / ADCA0SEL1

78 P1_14 / RLIN23RX / CAN7RX / INTP9 / CSIH4RYI / CSIH4RYO

79 P1_15 / RLIN23TX / CAN7TX

80 P8_0 / TAUJ0I0 / TAUJ0O0 / DPIN2 / PWGA14O / INTP4 / CSIH0CSS0 / CAN6RX / INTP6 / RIIC1SDA / SENT0RX / ADCA0I0S

81 P8_1 / TAPA0ESO / TAUJ0O1 / DPIN0 / PWGA15O / INTP5 / CSIH1CSS3 / CAN6TX / RIIC1SCL / SENT0SPCO /

82 P8_3 / TAUJ0I1 / TAUJ0O1 / DPIN3 / CSIH0CSS1 / INTP7 / PWGA23O / CAN7TX / ADCA0I5S

83 P8_4 / TAUJ0I2 / TAUJ0O2 / DPIN4 / CSIH0CSS2 / INTP8 / PWGA36O / CAN7RX / INTP9 / ADCA0I6S

84 P8_5 / TAUJ0I3 / TAUJ0O3 / NMI / CSIH0CSS3 / INTP9 / PWGA37O / ADCA0I7S

85 P8_6 / NMI / CSIH0CSS4 / PWGA38O / RTCA0OUT / ADCA0I8S / RESETOUT

86 P8_7 / CSIH3CSS0 / PWGA39O / ADCA0SEL0 / RTCA0OUT / ADCA0I14S

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 126 of 4535 Dec 26, 2018 Table 2A.1 Pin Assignment 176-Pin LQFP Pin No. Pin Name

87 P8_8 / CSIH3CSS1 / PWGA40O / ADCA0SEL1 / RLIN34RX / INTP14 / ADCA0I15S

88 P8_9 / CSIH3CSS2 / PWGA41O / ADCA0SEL2 / RLIN34TX / ADCA0I16S

89 A0VSS

90 A0VREF

91 AP0_15 / ADCA0I15

92 AP0_14 / ADCA0I14

93 AP0_13 / ADCA0I13

94 AP0_12 / ADCA0I12

95 AP0_11 / ADCA0I11

96 AP0_10 / ADCA0I10

97 AP0_9 / ADCA0I9

98 AP0_8 / ADCA0I8

99 AP0_7 / ADCA0I7

100 AP0_6 / ADCA0I6

101 AP0_5 / ADCA0I5

102 AP0_4 / ADCA0I4

103 AP0_3 / ADCA0I3

104 AP0_2 / ADCA0I2

105 AP0_1 / ADCA0I1

106 AP0_0 / ADCA0I0

107 EVSS

108 P9_0 / NMI / PWGA8O / TAUD0I0 / TAUD0O0 / ADCA0TRG0 / CSIH2CSS0 / KR0I4 / TAUJ1I1 / TAUJ1O1 / SENT1RX / RIIC1SDA / ADCA0I2S

109 P9_1 / INTP11 / PWGA9O / TAUD0I2 / TAUD0O2 / KR0I5 / CSIH2CSS1 / TAUJ1I2 / TAUJ1O2 / SENT1SPCO /

110 P9_2 / KR0I6 / PWGA20O / TAPA0ESO / CSIH2CSS2 / ADCA0I9S

111 P9_3 / KR0I7 / PWGA21O / CSIH2CSS3 / TAUJ1I1 / TAUJ1O1 / INTP16 / ADCA0I10S

112 P9_4 / CSIH0CSS5 / PWGA33O / TAUJ1I0 / TAUJ1O0 / INTP17 / ADCA0I11S

113 ISOVSS

114 REG1VCC

115 P20_3 / CAN4TX / PWGA67O / RLIN29TX / CSIG3RYI / CSIG3RYO

116 P20_2 / CAN4RX / INTP4 / PWGA66O / RLIN29RX / CSIG3SC

117 P20_1 / RLIN26TX / PWGA65O / CAN6TX / CSIG3SO

118 P20_0 / RLIN26RX / PWGA64O / CAN6RX / INTP6 / CSIG3SI

119 P20_5 / RLIN23TX / INTP23 / PWGA60O / CAN7TX

120 P20_4 / RLIN23RX / INTP22 / PWGA59O / CAN7RX / INTP9 / CSIG3SSI

121 EVCC

122 AP1_11 / ADCA1I11

123 AP1_10 / ADCA1I10

124 AP1_9 / ADCA1I9

125 AP1_8 / ADCA1I8

126 AP1_7 / ADCA1I7

127 AP1_6 / ADCA1I6

128 AP1_5 / ADCA1I5

129 AP1_4 / ADCA1I4

130 AP1_3 / ADCA1I3

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 127 of 4535 Dec 26, 2018 Table 2A.1 Pin Assignment 176-Pin LQFP Pin No. Pin Name

131 AP1_2 / ADCA1I2

132 AP1_1 / ADCA1I1

133 AP1_0 / ADCA1I0

134 AP1_15 / ADCA1I15

135 AP1_14 / ADCA1I14

136 AP1_13 / ADCA1I13

137 AP1_12 / ADCA1I12

138 A1VREF

139 A1VSS

140 BVCC

141 ISOVCL

142 ISOVSS

143 P18_0 / CSIG1RYI / CSIG1RYO / ETNB0LINK / PWGA61O / TAUJ3I0 / TAUJ3O0 / ADCA1I0S

144 P18_1 / PWGA62O / ETNB0TXD0 / TAUJ3I1 / TAUJ3O1 / ADCA1I1S

145 P18_2 / PWGA63O / ETNB0TXD1 / TAUJ3I2 / TAUJ3O2 / ADCA1I2S

146 P18_3 / PWGA71O / ETNB0TXD2 / TAUJ3I3 / TAUJ3O3 / ADCA1I3S

147 P18_4 / CSIH1CSS4 / ETNB0TXD3 / ADCA1I4S

148 P18_5 / CSIH1CSS5 / ETNB0TXEN / ADCA1I5S

149 P18_6 / ADCA1I6S

150 P18_7 / ETNB0TXCLK / ADCA1I7S

151 BVSS

152 P10_6 / TAUD0I13 / TAUD0O13 / CSIG0SO / ENCA0TIN0 / ADCA0SEL2 / CAN1RX / INTP1 / MEMC0AD0 / RLIN24RX / MODE2

153 P10_7 / TAUD0I15 / TAUD0O15 / CSIG0SC / ENCA0TIN1 / PWGA4O / CAN1TX / MEMC0AD1 / RLIN24TX / TAUJ3I1 /

154 P10_8 / TAUD0I10 / TAUD0O10 / CSIG0SI / FLXA0TXDB / ENCA0EC / PWGA5O / MEMC0AD2 / TAUJ3I2 / TAUJ3O2 /

155 P10_9 / TAUD0I12 / TAUD0O12 / RLIN30RX / INTP10 / ENCA0E0 / PWGA6O / CSIH0RYI / CSIH0RYO / MEMC0AD3 /

156 P10_10 / TAUD0I14 / TAUD0O14 / RLIN30TX / ENCA0E1 / PWGA7O / CSIH0CSS1 / MEMC0AD4 / TAUJ3I3 / TAUJ3O3

157 P10_11 / PWGA16O / RLIN31RX / INTP11 / FLXA0TXENA / CSIH1CSS0 / TAUB0I1 / TAUB0O1 / MEMC0AD5

158 P10_12 / PWGA17O / FLXA0STPWT / RLIN31TX / CSIH1CSS1 / TAUB0I3 / TAUB0O3 / MEMC0AD6

159 P10_13 / CSIH0SSI / PWGA18O / RLIN32RX / INTP12 / FLXA0TXENB / TAUB0I5 / TAUB0O5 / MEMC0AD7 / CAN7TX

160 P10_14 / ADCA1TRG0 / PWGA19O / FLXA0RXDA / RLIN32TX / CSIH3SSI / TAUB0I7 / TAUB0O7 / MEMC0AD8 /

161 P11_1 / CSIH2SSI / FLXA0TXDA / RLIN20RX / CSIH0CSS7 / INTP20 / PWGA26O / TAUB0I13 / TAUB0O13 /

162 P11_2 / CSIH2SO / RLIN32RX / INTP12 / RLIN20TX / PWGA27O / TAUB0I15 / TAUB0O15 / MEMC0AD10 / SFMA0IO3

163 P11_3 / CSIH2SC / CAN3RX / INTP3 / PWGA28O / TAUB1I1 / TAUB1O1 / MEMC0AD11 / RLIN32TX / SFMA0IO2

164 P11_4 / CSIH2SI / CAN3TX / INTP21 / PWGA29O / TAUB1I3 / TAUB1O3 / MEMC0AD12 / SFMA0IO1

165 P11_5 / CAN5RX / INTP5 / RLIN33TX / PWGA30O / CSIH3SI / TAUB1I5 / TAUB1O5 / MEMC0AD13 / SFMA0IO0

166 P11_6 / RLIN33RX / INTP13 / CAN5TX / ADCA1TRG1 / PWGA31O / CSIH3SO / TAUB1I7 / TAUB1O7 / MEMC0AD14 /

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 128 of 4535 Dec 26, 2018 Table 2A.1 Pin Assignment 176-Pin LQFP Pin No. Pin Name

167 P11_7 / INTP5 / PWGA32O / CSIH3SC / TAUB1I9 / TAUB1O9 / MEMC0AD15 / SFMA0CLK

168 P11_15 / CAN2RX / INTP2 / CSIH2CSS4 / PWGA55O / TAUB1I8 / TAUB1O8 / MEMC0ASTB / ETNB0RXERR /

169 P12_0 / CAN2TX / PWGA56O / TAUB1I10 / TAUB1O10 / CSIG2SSI / MEMC0A16 / RLIN36RX / INTP16

170 P12_1 / RLIN34RX / INTP14 / CSIH2CSS5 / PWGA57O / TAUB1I12 / TAUB1O12 / MEMC0A17

171 P12_2 / INTP19 / RLIN34TX / PWGA58O / TAUB1I14 / TAUB1O14 / MEMC0A18 / CSIG2RYI / CSIG2RYO

172 BVCC

173 BVSS

174 P10_0 / TAUD0I1 / TAUD0O1 / CAN0RX / INTP0 / CSCXFOUT / PWGA0O / TAUJ1I3 / TAPA0UP / CSIH1SI /

MEMC0A19 / ETNB0RXCLK / TAUJ1O3

175 P10_1 / TAUD0I3 / TAUD0O3 / INTP18 / CAN0TX / PWGA1O / TAUJ3I0 / TAPA0UN / CSIH1SC / ETNB0RXD0 /

MEMC0A20 / TAUJ3O0 / MODE0

176 P10_2 / TAUD0I5 / TAUD0O5 / RIIC0SDA / KR0I0 / PWGA2O / ADCA0TRG0 / TAPA0VP / CSIH1SO / ETNB0RXD1 /

MEMC0A21 / RLIN37TX / MODE1

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 129 of 4535 Dec 26, 2018 Table 2A.2 Pin Assignment 233-Pin FPBGA Pin No. Pin Name A1 BVSS A2 P10_0 / TAUD0I1 / TAUD0O1 / CAN0RX / INTP0 / CSCXFOUT / PWGA0O / TAUJ1I3 / TAPA0UP / CSIH1SI / MEMC0A19 / ETNB0RXCLK / TAUJ1O3 A3 P12_2 / INTP19 / RLIN34TX / PWGA58O / TAUB1I14 / TAUB1O14 / MEMC0A18 / CSIG2RYI / CSIG2RYO A4 P11_5 / CAN5RX / INTP5 / RLIN33TX / PWGA30O / CSIH3SI / TAUB1I5 / TAUB1O5 / MEMC0AD13 / SFMA0IO0 A5 P11_1 / CSIH2SSI / FLXA0TXDA / RLIN20RX / CSIH0CSS7 / INTP20 / PWGA26O / TAUB0I13 / TAUB0O13 / MEMC0AD9 A6 P10_13 / CSIH0SSI / PWGA18O / RLIN32RX / INTP12 / FLXA0TXENB / TAUB0I5 / TAUB0O5 / MEMC0AD7 / CAN7TX A7 P10_10 / TAUD0I14 / TAUD0O14 / RLIN30TX / ENCA0E1 / PWGA7O / CSIH0CSS1 / MEMC0AD4 / TAUJ3I3 / TAUJ3O3 A8 P10_7 / TAUD0I15 / TAUD0O15 / CSIG0SC / ENCA0TIN1 / PWGA4O / CAN1TX / MEMC0AD1 / RLIN24TX / TAUJ3I1 / TAUJ3O1 A9 P10_6 / TAUD0I13 / TAUD0O13 / CSIG0SO / ENCA0TIN0 / ADCA0SEL2 / CAN1RX / INTP1 / MEMC0AD0 / RLIN24RX / MODE2 A10 P19_2 / ADCA1I18S A11 P18_15 / ADCA1I15S A12 P18_13 / ADCA1I13S A13 P18_6 / ADCA1I6S A14 P18_5 / CSIH1CSS5 / ETNB0TXEN / ADCA1I5S A15 P18_10 / ADCA1I10S A16 P18_8 / ADCA1I8S A17 A1VSS B1 P10_3 / TAUD0I7 / TAUD0O7 / RIIC0SCL / KR0I1 / PWGA3O / ADCA0TRG1 / TAPA0VN / CSIH1SSI / MEMC0CLK / RLIN37RX / INTP17 B2 P10_1 / TAUD0I3 / TAUD0O3 / INTP18 / CAN0TX / PWGA1O / TAUJ3I0 / TAPA0UN / CSIH1SC / ETNB0RXD0 / MEMC0A20 / TAUJ3O0 / MODE0 B3 P13_1 / MEMC0A20 B4 P12_0 / CAN2TX / PWGA56O / TAUB1I10 / TAUB1O10 / CSIG2SSI / MEMC0A16 / RLIN36RX / INTP16 B5 P11_4 / CSIH2SI / CAN3TX / INTP21 / PWGA29O / TAUB1I3 / TAUB1O3 / MEMC0AD12 / SFMA0IO1 B6 P11_3 / CSIH2SC / CAN3RX / INTP3 / PWGA28O / TAUB1I1 / TAUB1O1 / MEMC0AD11 / RLIN32TX / SFMA0IO2 B7 P10_14 / ADCA1TRG0 / PWGA19O / FLXA0RXDA / RLIN32TX / CSIH3SSI / TAUB0I7 / TAUB0O7 / MEMC0AD8 / CAN7RX / INTP9 B8 P10_9 / TAUD0I12 / TAUD0O12 / RLIN30RX / INTP10 / ENCA0E0 / PWGA6O / CSIH0RYI / CSIH0RYO / MEMC0AD3 / FLXA0RXDB B9 P19_3 / ADCA1I19S B10 P19_1 / ADCA1I17S B11 P18_7 / ETNB0TXCLK / ADCA1I7S B12 P18_11 / ADCA1I11S B13 P18_3 / PWGA71O / ETNB0TXD2 / TAUJ3I3 / TAUJ3O3 / ADCA1I3S B14 P18_2 / PWGA63O / ETNB0TXD1 / TAUJ3I2 / TAUJ3O2 / ADCA1I2S B15 P18_1 / PWGA62O / ETNB0TXD0 / TAUJ3I1 / TAUJ3O1 / ADCA1I1S B16 AP1_12 / ADCA1I12 B17 AP1_14 / ADCA1I14 C1 P10_15 / CSIH3RYI / CSIH3RYO / PWGA24O / RLIN22RX / TAUB0I9 / TAUB0O9 / MEMC0RD C2 P10_5 / TAUD0I11 / TAUD0O11 / CAN6RX / INTP6 / RLIN21TX / KR0I3 / ADCA0SEL1 / TAPA0WN / CSIG0RYI / CSIG0RYO / ETNB0RXD3 / PWGA54O

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 130 of 4535 Dec 26, 2018 Table 2A.2 Pin Assignment 233-Pin FPBGA Pin No. Pin Name C3 P10_2 / TAUD0I5 / TAUD0O5 / RIIC0SDA / KR0I0 / PWGA2O / ADCA0TRG0 / TAPA0VP / CSIH1SO / ETNB0RXD1 / MEMC0A21 / RLIN37TX / MODE1 C4 P13_0 / MEMC0A19 C5 P12_1 / RLIN34RX / INTP14 / CSIH2CSS5 / PWGA57O / TAUB1I12 / TAUB1O12 / MEMC0A17 C6 P11_7 / INTP5 / PWGA32O / CSIH3SC / TAUB1I9 / TAUB1O9 / MEMC0AD15 / SFMA0CLK C7 P11_2 / CSIH2SO / RLIN32RX / INTP12 / RLIN20TX / PWGA27O / TAUB0I15 / TAUB0O15 / MEMC0AD10 / SFMA0IO3 C8 P10_11 / PWGA16O / RLIN31RX / INTP11 / FLXA0TXENA / CSIH1CSS0 / TAUB0I1 / TAUB0O1 / MEMC0AD5 C9 P18_14 / ADCA1I14S C10 P19_0 / ADCA1I16S C11 P18_4 / CSIH1CSS4 / ETNB0TXD3 / ADCA1I4S C12 P18_12 / ADCA1I12S C13 P18_9 / ADCA1I9S C14 P18_0 / CSIG1RYI / CSIG1RYO / ETNB0LINK / PWGA61O / TAUJ3I0 / TAUJ3O0 / ADCA1I0S C15 AP1_13 / ADCA1I13 C16 AP1_15 / ADCA1I15 C17 AP1_0 / ADCA1I0 D1 P11_9 / CSIG1SO / RLIN35RX / INTP15 / PWGA49O / TAUB1I13 / TAUB1O13 / MEMC0CS1 D2 P11_0 / CSIH2RYI / CSIH2RYO / ADCA1TRG2 / PWGA25O / RLIN22TX / TAUB0I11 / TAUB0O11 / MEMC0WR D3 P10_4 / TAUD0I9 / TAUD0O9 / RLIN21RX / CAN6TX / KR0I2 / ADCA0SEL0 / ADCA0TRG2 / TAPA0WP / CSIG0SSI / PWGA53O / ETNB0RXD2 / MEMC0A22 D4 BVCC D5 P11_15 / CAN2RX / INTP2 / CSIH2CSS4 / PWGA55O / TAUB1I8 / TAUB1O8 / MEMC0ASTB / ETNB0RXERR / RLIN36TX D6 P11_6 / RLIN33RX / INTP13 / CAN5TX / ADCA1TRG1 / PWGA31O / CSIH3SO / TAUB1I7 / TAUB1O7 / MEMC0AD14 / SFMA0SSL D7 P10_12 / PWGA17O / FLXA0STPWT / RLIN31TX / CSIH1CSS1 / TAUB0I3 / TAUB0O3 / MEMC0AD6 D8 P10_8 / TAUD0I10 / TAUD0O10 / CSIG0SI / FLXA0TXDB / ENCA0EC / PWGA5O / MEMC0AD2 / TAUJ3I2 / TAUJ3O2 / FLMD1 D9 BVSS D10 BVCC D11 BVCC D12 ISOVSS D13 ISOVCL D14 A1VSS D15 AP1_1 / ADCA1I1 D16 AP1_2 / ADCA1I2 D17 AP1_3 / ADCA1I3 E1 P11_12 / RLIN25RX / PWGA52O / TAUB1I2 / TAUB1O2 / MEMC0WAIT E2 P11_10 / CSIG1SC / PWGA50O / TAUB1I15 / TAUB1O15 / MEMC0CS2 E3 P11_8 / CSIG1SSI / RLIN35TX / PWGA48O / TAUB1I11 / TAUB1O11 / MEMC0CS0 E4 BVCC E14 A1VREF E15 AP1_5 / ADCA1I5 E16 AP1_6 / ADCA1I6 E17 AP1_8 / ADCA1I8

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 131 of 4535 Dec 26, 2018 Table 2A.2 Pin Assignment 233-Pin FPBGA Pin No. Pin Name F1 P13_3 / ETNB0RXERR F2 P13_2 / ETNB0RXDV F3 P11_11 / CSIG1SI / RLIN25TX / PWGA51O / TAUB1I0 / TAUB1O0 / MEMC0CS3 / ETNB0RXDV F4 BVSS F14 AP1_4 / ADCA1I4 F15 AP1_7 / ADCA1I7 F16 AP1_9 / ADCA1I9 F17 P20_4 / RLIN23RX / INTP22 / PWGA59O / CAN7RX / INTP9 / CSIG3SSI G1 P12_3 / RLIN27RX / PWGA68O / CSIG2SI / MEMC0BEN0 / TAUB1I6 / TAUB1O6 G2 P13_4 G3 P13_5 / MEMC0A21 G4 ISOVCL G7 BVSS G8 BVSS G9 BVSS G10 BVSS G11 BVSS G14 AP1_10 / ADCA1I10 G15 AP1_11 / ADCA1I11 G16 P20_5 / RLIN23TX / INTP23 / PWGA60O / CAN7TX G17 P20_0 / RLIN26RX / PWGA64O / CAN6RX / INTP6 / CSIG3SI H1 P12_4 / RLIN27TX / PWGA69O / CSIG2SC / ETNB0MDIO / MEMC0BEN1 H2 P13_7 / PWGA73O H3 P13_6 / MEMC0A22 / PWGA72O H4 ISOVSS H7 BVSS H8 BVSS H9 BVSS H10 BVSS H11 EVSS H14 EVCC H15 P20_1 / RLIN26TX / PWGA65O / CAN6TX / CSIG3SO H16 P20_2 / CAN4RX / INTP4 / PWGA66O / RLIN29RX / CSIG3SC H17 P20_3 / CAN4TX / PWGA67O / RLIN29TX / CSIG3RYI / CSIG3RYO J1 P0_0 / TAUD0I2 / TAUD0O2 / RLIN20RX / CAN0TX / PWGA10O / CSIH0SSI / DPO / TAUJ2I1 / TAUJ2O1 J2 P0_1 / TAUD0I4 / TAUD0O4 / CAN0RX / INTP0 / RLIN20TX / PWGA11O / CSIH0SI / APO / TAUJ2I2 / TAUJ2O2 J3 P12_5 / PWGA70O / ETNB0MDC / CSIG2SO / TAUB1I4 / TAUB1O4 J4 P0_2 / TAUD0I6 / TAUD0O6 / CAN1RX / INTP1 / RLIN30TX / PWGA12O / CSIH0SC / DPO / TAUJ2I3 / TAUJ2O3 J7 BVSS J8 BVSS J9 BVSS J10 EVSS J11 EVSS J14 REG1VCC J15 P9_3 / KR0I7 / PWGA21O / CSIH2CSS3 / TAUJ1I1 / TAUJ1O1 / INTP16 / ADCA0I10S

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 132 of 4535 Dec 26, 2018 Table 2A.2 Pin Assignment 233-Pin FPBGA Pin No. Pin Name J16 P9_4 / CSIH0CSS5 / PWGA33O / TAUJ1I0 / TAUJ1O0 / INTP17 / ADCA0I11S J17 P9_2 / KR0I6 / PWGA20O / TAPA0ESO / CSIH2CSS2 / ADCA0I9S K1 P0_3 / TAUD0I8 / TAUD0O8 / RLIN30RX / INTP10 / CAN1TX / DPIN1 / PWGA13O / CSIH0SO / TAUJ1I0 / TAUJ1O0 K2 P0_5 / CAN2RX / INTP2 / RLIN31TX / DPIN9 / SELDP1 / CSIH1SO / TAUB0I14 / TAUB0O14 K3 P0_4 / RLIN31RX / INTP11 / CAN2TX / PWGA10O / CSIH1SI / SELDP0 / DPIN8 / TAUB0I12 / TAUB0O12 K4 EVCC K7 EVSS K8 EVSS K9 EVSS K10 EVSS K11 EVSS K14 ISOVSS K15 AP0_0 / ADCA0I0 K16 P9_0 / NMI / PWGA8O / TAUD0I0 / TAUD0O0 / ADCA0TRG0 / CSIH2CSS0 / KR0I4 / TAUJ1I1 / TAUJ1O1 / SENT1RX / RIIC1SDA / ADCA0I2S K17 P9_1 / INTP11 / PWGA9O / TAUD0I2 / TAUD0O2 / KR0I5 / CSIH2CSS1 / TAUJ1I2 / TAUJ1O2 / SENT1SPCO / RIIC1SCL / ADCA0I3S L1 P0_11 / RIIC0SDA / DPIN12 / CSIH1CSS2 / TAUB0I8 / TAUB0O8 / RLIN26RX / PWGA34O L2 P0_12 / RIIC0SCL / DPIN13 / PWGA45O / TAUB0I10 / TAUB0O10 / CSIG0SI / RLIN26TX L3 P0_6 / INTP2 / DPIN10 / SELDP2 / CSIH1SC / PWGA35O L4 P0_14 / INTP17 / RLIN32TX / PWGA47O / TAUB0I14 / TAUB0O14 / CSIG0SC / CAN5TX L7 EVSS L8 EVSS L9 EVSS L10 EVSS L11 EVSS L14 EVSS L15 AP0_4 / ADCA0I4 L16 AP0_2 / ADCA0I2 L17 AP0_1 / ADCA0I1 M1 P0_13 / RLIN32RX / INTP12 / PWGA46O / TAUB0I12 / TAUB0O12 / CSIG0SO / CAN5RX / INTP5 M2 P1_0 / RLIN33RX / INTP13 / TAUJ2I0 / TAUJ2O0 / CSIG4SSI M3 P2_9 / PWGA77O M4 P2_7 / RLIN210RX M14 A0VREF M15 AP0_8 / ADCA0I8 M16 AP0_5 / ADCA0I5 M17 AP0_3 / ADCA0I3 N1 P1_2 / CAN3RX / INTP3 / DPIN19 / TAUJ2I2 / TAUJ2O2 / CSIG4SI N2 P1_1 / INTP18 / RLIN33TX / CSIG4SC / TAUJ2I1 / TAUJ2O1 N3 P1_3 / INTP19 / CAN3TX / DPIN23 / CSIG4SO / TAUJ2I3 / TAUJ2O3 N4 P2_11 / PWGA79O N14 A0VSS N15 AP0_11 / ADCA0I11 N16 AP0_7 / ADCA0I7

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 133 of 4535 Dec 26, 2018 Table 2A.2 Pin Assignment 233-Pin FPBGA Pin No. Pin Name N17 AP0_6 / ADCA0I6 P1 P1_12 / CAN4RX / INTP4 / RLIN36TX P2 P1_13 / CAN4TX / RLIN36RX / INTP16 P3 P8_10 / CSIH3CSS3 / DPIN14 / PWGA42O / RLIN37RX / INTP17 / ADCA0I17S P4 P8_12 / TAUJ1I3 / TAUJ1O3 / DPIN16 / PWGA44O / CSIH1CSS5 / INTP23 / RLIN25TX / ADCA0I19S P5 JP0_1 / INTP1 / TAUJ0I0 / TAUJ0O0 / FPDT / DCUTDO / LPDO P6 P1_11 / ADCA1TRG2 / RLIN24TX / DPIN22 / INTP14 P7 P2_13 / RLIN211TX P8 P2_15 / PWGA75O P9 EVCC P10 REG0VCC P11 ISOVSS P12 ISOVCL P13 P8_6 / NMI / CSIH0CSS4 / PWGA38O / RTCA0OUT / ADCA0I8S / RESETOUT P14 P8_8 / CSIH3CSS1 / PWGA40O / ADCA0SEL1 / RLIN34RX / INTP14 / ADCA0I15S P15 AP0_13 / ADCA0I13 P16 AP0_10 / ADCA0I10 P17 AP0_9 / ADCA0I9 R1 P2_6 / ADCA0SEL2 / CSIG4RYI / CSIG4RYO R2 P2_10 / PWGA78O R3 JP0_4 / DCUTRST R4 JP0_3 / INTP3 / CSCXFOUT / TAUJ0I2 / TAUJ0O2 / DCUTMS R5 P2_1 / RLIN27TX / CAN6TX R6 P1_10 / RLIN24RX / DPIN21 / INTP22 / ADCA1TRG1 R7 P1_9 / DPIN20 / INTP21 R8 P3_0 / PWGA76O R9 FLMD0 R10 P0_9 / INTP12 / CSIH1CSS0 / DPIN7 / RLIN22RX / TAUB0I4 / TAUB0O4 / CAN4RX / INTP4 R11 P0_7 / RLIN21RX / DPIN5 / CSCXFOUT / CSIH1RYI / CSIH1RYO / TAUB0I0 / TAUB0O0 / CAN3RX / INTP3 R12 P2_5 / RLIN29TX / CSIH4SSI / ADCA0SEL1 R13 P1_15 / RLIN23TX / CAN7TX R14 P8_4 / TAUJ0I2 / TAUJ0O2 / DPIN4 / CSIH0CSS2 / INTP8 / PWGA36O / CAN7RX / INTP9 / ADCA0I6S R15 P8_7 / CSIH3CSS0 / PWGA39O / ADCA0SEL0 / RTCA0OUT / ADCA0I14S R16 AP0_14 / ADCA0I14 R17 AP0_12 / ADCA0I12 T1 P2_8 / RLIN210TX T2 P2_12 / RLIN211RX T3 P8_11 / TAUJ1I2 / TAUJ1O2 / DPIN15 / PWGA43O / CSIH1CSS4 / RLIN25RX / ADCA0I18S T4 JP0_2 / INTP2 / TAUJ0I1 / TAUJ0O1 / FPCK / DCUTCK / LPDCLK T5 P2_0 / RLIN27RX / CAN6RX / INTP6 T6 P2_14 / PWGA74O T7 IP0_0 / XT2 T8 AWOVCL T9 X1 T10 P2_2 / RLIN28RX / CSIH4CSS0

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 134 of 4535 Dec 26, 2018 Table 2A.2 Pin Assignment 233-Pin FPBGA Pin No. Pin Name T11 P0_10 / INTP3 / CSIH1CSS1 / DPIN11 / RLIN22TX / TAUB0I6 / TAUB0O6 / CAN4TX T12 P0_8 / INTP16 / RLIN21TX / DPIN6 / CSIH0CSS6 / CSIH1SSI / TAUB0I2 / TAUB0O2 / CAN3TX T13 P2_4 / RLIN29RX / ADCA0SEL0 / CSIH4SO T14 P8_1 / TAPA0ESO / TAUJ0O1 / DPIN0 / PWGA15O / INTP5 / CSIH1CSS3 / CAN6TX / RIIC1SCL / SENT0SPCO / ADCA0I1S T15 P8_5 / TAUJ0I3 / TAUJ0O3 / NMI / CSIH0CSS3 / INTP9 / PWGA37O / ADCA0I7S T16 P8_9 / CSIH3CSS2 / PWGA41O / ADCA0SEL2 / RLIN34TX / ADCA0I16S T17 AP0_15 / ADCA0I15 U1 EVSS U2 P8_2 / TAUJ0I0 / TAUJ0O0 / DPIN2 / CSIH0CSS0 / INTP6 / PWGA22O / RLIN37TX / ADCA0I4S U3 JP0_5 / NMI / RTCA0OUT / TAUJ0I3 / TAUJ0O3 / DCURDY / LPDCLKOUT U4 JP0_0 / INTP0 / TAUJ2I0 / TAUJ2O0 / FPDR / FPDT / DCUTDI / LPDI / LPDIO U5 P1_8 U6 RESET U7 XT1 U8 AWOVSS U9 X2 U10 P2_3 / RLIN28TX / CSIH4CSS1 U11 JP0_6 / EVTO U12 P1_5 / ADCA1TRG0 / RLIN35TX / DPIN17 / INTP20 / CSIH4SC U13 P1_4 / RLIN35RX / INTP15 / DPIN18 / CSIH4SI U14 P1_14 / RLIN23RX / CAN7RX / INTP9 / CSIH4RYI / CSIH4RYO U15 P8_0 / TAUJ0I0 / TAUJ0O0 / DPIN2 / PWGA14O / INTP4 / CSIH0CSS0 / CAN6RX / INTP6 / RIIC1SDA / SENT0RX / ADCA0I0S U16 P8_3 / TAUJ0I1 / TAUJ0O1 / DPIN3 / CSIH0CSS1 / INTP7 / PWGA23O / CAN7TX / ADCA0I5S U17 A0VSS Table 2A.3 Reserved

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 135 of 4535 Dec 26, 2018 Table 2A.4 Pin Assignment 324-Pin FPBGA Pin No. Pin Name A1 BVSS A2 P24_5 / CAN10RX / INTP20 A3 P24_2 / CAN9TX A4 P24_3 / CAN9RX / INTP19 A5 P22_7 / MMCA0CMD A6 P12_1 / RLIN34RX / INTP14 / CSIH2CSS5 / PWGA57O / TAUB1I12 / TAUB1O12 / MEMC0A17 A7 P12_0 / CAN2TX / PWGA56O / TAUB1I10 / TAUB1O10 / CSIG2SSI / MEMC0A16 / RLIN36RX / INTP16 A8 P22_11 / MMCA0DAT2 A9 P11_5 / CAN5RX / INTP5 / RLIN33TX / PWGA30O / CSIH3SI / TAUB1I5 / TAUB1O5 / MEMC0AD13 / SFMA0IO0 A10 P11_4 / CSIH2SI / CAN3TX / INTP21 / PWGA29O / TAUB1I3 / TAUB1O3 / MEMC0AD12 / SFMA0IO1 A11 P22_15 / MMCA0DAT6 A12 P11_1 / CSIH2SSI / FLXA0TXDA / RLIN20RX / CSIH0CSS7 / INTP20 / PWGA26O / TAUB0I13 / TAUB0O13 / MEMC0AD9 A13 P10_12 / PWGA17O / FLXA0STPWT / RLIN31TX / CSIH1CSS1 / TAUB0I3 / TAUB0O3 / MEMC0AD6 A14 P10_10 / TAUD0I14 / TAUD0O14 / RLIN30TX / ENCA0E1 / PWGA7O / CSIH0CSS1 / MEMC0AD4 / TAUJ3I3 / TAUJ3O3 A15 P19_1 / ADCA1I17S A16 P19_0 / ADCA1I16S A17 P18_15 / ADCA1I15S A18 P18_6 / PWGA95O / ADCA1I6S A19 P18_3 / PWGA71O / ETNB0TXD2 / TAUJ3I3 / TAUJ3O3 / ADCA1I3S A20 P18_9 / ADCA1I9S A21 P18_0 / CSIG1RYI / CSIG1RYO / ETNB0LINK / PWGA61O / TAUJ3I0 / TAUJ3O0 / ADCA1I0S A22 A1VSS B1 P24_6 / CAN11TX B2 P10_4 / TAUD0I9 / TAUD0O9 / RLIN21RX / CAN6TX / KR0I2 / ADCA0SEL0 / ADCA0TRG2 / TAPA0WP / CSIG0SSI / PWGA53O / ETNB0RXD2 / MEMC0A22 B3 P24_4 / CAN10TX B4 P24_1 / CAN8RX / INTP18 B5 P24_0 / CAN8TX B6 P13_1 / MEMC0A20 B7 P22_9 / MMCA0DAT0 B8 P22_12 / MMCA0DAT3 B9 P11_6 / RLIN33RX / INTP13 / CAN5TX / ADCA1TRG1 / PWGA31O / CSIH3SO / TAUB1I7 / TAUB1O7 / MEMC0AD14 / SFMA0SSL B10 P22_14 / MMCA0DAT5 B11 P21_1 / MMCA0DAT7 B12 P10_14 / ADCA1TRG0 / PWGA19O / FLXA0RXDA / RLIN32TX / CSIH3SSI / TAUB0I7 / TAUB0O7 / MEMC0AD8 / CAN7RX / INTP9 B13 P10_11 / PWGA16O / RLIN31RX / INTP11 / FLXA0TXENA / CSIH1CSS0 / TAUB0I1 / TAUB0O1 / MEMC0AD5 B14 P10_8 / TAUD0I10 / TAUD0O10 / CSIG0SI / FLXA0TXDB / ENCA0EC / PWGA5O / MEMC0AD2 / TAUJ3I2 / TAUJ3O2 / FLMD1 B15 P19_3 / ADCA1I19S B16 P18_7 / ETNB0TXCLK / ADCA1I7S B17 P18_13 / ADCA1I13S

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 136 of 4535 Dec 26, 2018 Table 2A.4 Pin Assignment 324-Pin FPBGA Pin No. Pin Name B18 P18_4 / CSIH1CSS4 / ETNB0TXD3 / ADCA1I4S B19 P18_8 / ADCA1I8S B20 P18_1 / PWGA62O / ETNB0TXD0 / TAUJ3I1 / TAUJ3O1 / ADCA1I1S B21 AP1_13 / ADCA1I13 B22 AP1_15 / ADCA1I15 C1 P24_7 / CAN11RX / INTP21 C2 P22_6 / ETNB1TXCLK C3 P10_5 / TAUD0I11 / TAUD0O11 / CAN6RX / INTP6 / RLIN21TX / KR0I3 / ADCA0SEL1 / TAPA0WN / CSIG0RYI / CSIG0RYO / ETNB0RXD3 / PWGA54O C4 P10_3 / TAUD0I7 / TAUD0O7 / RIIC0SCL / KR0I1 / PWGA3O / ADCA0TRG1 / TAPA0VN / CSIH1SSI / MEMC0CLK / RLIN37RX / INTP17 C5 P10_2 / TAUD0I5 / TAUD0O5 / RIIC0SDA / KR0I0 / PWGA2O / ADCA0TRG0 / TAPA0VP / CSIH1SO / ETNB0RXD1 / MEMC0A21 / RLIN37TX / MODE1 C6 P22_8 / MMCA0CLK C7 P13_0 / MEMC0A19 C8 P22_10 / MMCA0DAT1 C9 P11_7 / INTP5 / PWGA32O / CSIH3SC / TAUB1I9 / TAUB1O9 / MEMC0AD15 / SFMA0CLK C10 P22_13 / MMCA0DAT4 C11 P11_3 / CSIH2SC / CAN3RX / INTP3 / PWGA28O / TAUB1I1 / TAUB1O1 / MEMC0AD11 / RLIN32TX / SFMA0IO2 C12 P10_13 / CSIH0SSI / PWGA18O / RLIN32RX / INTP12 / FLXA0TXENB / TAUB0I5 / TAUB0O5 / MEMC0AD7 / CAN7TX C13 P10_9 / TAUD0I12 / TAUD0O12 / RLIN30RX / INTP10 / ENCA0E0 / PWGA6O / CSIH0RYI / CSIH0RYO / MEMC0AD3 / FLXA0RXDB C14 P10_7 / TAUD0I15 / TAUD0O15 / CSIG0SC / ENCA0TIN1 / PWGA4O / CAN1TX / MEMC0AD1 / RLIN24TX / TAUJ3I1 / TAUJ3O1 C15 P18_14 / ADCA1I14S C16 P18_12 / ADCA1I12S C17 P18_11 / ADCA1I11S C18 P18_10 / ADCA1I10S C19 P18_2 / PWGA63O / ETNB0TXD1 / TAUJ3I2 / TAUJ3O2 / ADCA1I2S C20 AP1_12 / ADCA1I12 C21 AP1_0 / ADCA1I0 C22 AP1_1 / ADCA1I1 D1 P10_15 / CSIH3RYI / CSIH3RYO / PWGA24O / RLIN22RX / TAUB0I9 / TAUB0O9 / MEMC0RD D2 P22_4 / ETNB1TXD0 D3 P22_5 / ETNB1TXEN D4 BVCC D5 BVCC D6 P10_1 / TAUD0I3 / TAUD0O3 / INTP18 / CAN0TX / PWGA1O / TAUJ3I0 / TAPA0UN / CSIH1SC / ETNB0RXD0 / MEMC0A20 / TAUJ3O0 / MODE0 D7 P10_0 / TAUD0I1 / TAUD0O1 / CAN0RX / INTP0 / CSCXFOUT / PWGA0O / TAUJ1I3 / TAPA0UP / CSIH1SI / MEMC0A19 / ETNB0RXCLK / TAUJ1O3 D8 P12_2 / INTP19 / RLIN34TX / PWGA58O / TAUB1I14 / TAUB1O14 / MEMC0A18 / CSIG2RYI / CSIG2RYO D9 P11_15 / CAN2RX / INTP2 / CSIH2CSS4 / PWGA55O / TAUB1I8 / TAUB1O8 / MEMC0ASTB / ETNB0RXERR / RLIN36TX D10 BVSS D11 P11_2 / CSIH2SO / RLIN32RX / INTP12 / RLIN20TX / PWGA27O / TAUB0I15 / TAUB0O15 / MEMC0AD10 / SFMA0IO3

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 137 of 4535 Dec 26, 2018 Table 2A.4 Pin Assignment 324-Pin FPBGA Pin No. Pin Name D12 BVCC D13 BVSS D14 P10_6 / TAUD0I13 / TAUD0O13 / CSIG0SO / ENCA0TIN0 / ADCA0SEL2 / CAN1RX / INTP1 / MEMC0AD0 / RLIN24RX / MODE2 D15 P19_2 / ADCA1I18S D16 P18_5 / CSIH1CSS5 / ETNB0TXEN / ADCA1I5S D17 ISOVSS D18 ISOVCL D19 BVCC D20 AP1_14 / ADCA1I14 D21 AP1_3 / ADCA1I3 D22 AP1_5 / ADCA1I5 E1 P22_3 / ETNB1TXD1 E2 P11_8 / CSIG1SSI / RLIN35TX / PWGA48O / TAUB1I11 / TAUB1O11 / MEMC0CS0 E3 P11_0 / CSIH2RYI / CSIH2RYO / ADCA1TRG2 / PWGA25O / RLIN22TX / TAUB0I11 / TAUB0O11 / MEMC0WR E4 BVCC E19 A1VSS E20 AP1_2 / ADCA1I2 E21 AP1_4 / ADCA1I4 E22 AP1_7 / ADCA1I7 F1 P22_2 / ETNB1TXD2 F2 P22_1 / ETNB1TXD3 F3 P11_9 / CSIG1SO / RLIN35RX / INTP15 / PWGA49O / TAUB1I13 / TAUB1O13 / MEMC0CS1 F4 BVCC F19 A1VREF F20 AP1_6 / ADCA1I6 F21 AP1_9 / ADCA1I9 F22 AP1_8 / ADCA1I8 G1 P22_0 / ETNB1RXCLK G2 P11_11 / CSIG1SI / RLIN25TX / PWGA51O / TAUB1I0 / TAUB1O0 / MEMC0CS3 / ETNB0RXDV G3 P11_10 / CSIG1SC / PWGA50O / TAUB1I15 / TAUB1O15 / MEMC0CS2 G4 BVSS G19 AP1_10 / ADCA1I10 G20 AP1_11 / ADCA1I11 G21 P20_6 / PWGA88O G22 P20_7 / PWGA89O H1 P21_4 / ETNB1RXD0 H2 P11_12 / RLIN25RX / PWGA52O / TAUB1I2 / TAUB1O2 / MEMC0WAIT H3 P21_0 / ETNB1RXDV H4 ISOVCL H19 EVCC H20 P20_8 / PWGA90O H21 P20_9 / PWGA91O H22 P20_4 / RLIN23RX / INTP22 / PWGA59O / CAN7RX / INTP9 / CSIG3SSI J1 P21_5 / ETNB1RXD3

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 138 of 4535 Dec 26, 2018 Table 2A.4 Pin Assignment 324-Pin FPBGA Pin No. Pin Name J2 P21_2 / ETNB1RXD2 J3 P21_3 / ETNB1RXD1 J4 ISOVSS J9 BVSS J10 BVSS J11 BVSS J12 BVSS J13 BVSS J14 BVSS J19 EVSS J20 P20_0 / RLIN26RX / PWGA64O / CAN6RX / INTP6 / CSIG3SI J21 P20_5 / RLIN23TX / INTP23 / PWGA60O / CAN7TX J22 P20_1 / RLIN26TX / PWGA65O / CAN6TX / CSIG3SO K1 P21_6 / ETNB1MDC K2 P13_5 / MEMC0A21 K3 P13_2 / ETNB0RXDV K4 BVSS K9 BVSS K10 BVSS K11 BVSS K12 BVSS K13 BVSS K14 EVSS K19 EVCC K20 P20_2 / CAN4RX / INTP4 / PWGA66O / RLIN29RX / CSIG3SC K21 P20_3 / CAN4TX / PWGA67O / RLIN29TX / CSIG3RYI / CSIG3RYO K22 P20_10 / PWGA92O L1 P21_7 / ETNB1MDIO L2 P21_8 / ETNB1RXERR L3 P13_3 / ETNB0RXERR L4 P12_3 / RLIN27RX / PWGA68O / CSIG2SI / MEMC0BEN0 / TAUB1I6 / TAUB1O6 L9 BVSS L10 BVSS L11 BVSS L12 BVSS L13 EVSS L14 EVSS L19 REG1VCC L20 P20_11 / PWGA93O L21 P20_12 / PWGA94O L22 P20_15 / RLIN214RX M1 P21_9 M2 P21_10 M3 P13_4 / ETNB1LINK M4 P13_6 / MEMC0A22 / PWGA72O

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 139 of 4535 Dec 26, 2018 Table 2A.4 Pin Assignment 324-Pin FPBGA Pin No. Pin Name M9 BVSS M10 BVSS M11 BVSS M12 EVSS M13 EVSS M14 EVSS M19 ISOVSS M20 P20_13 / RLIN215RX / PWGA95O M21 P20_14 / RLIN215TX M22 P23_10 / RLIN214TX N1 P21_11 / RLIN213RX N2 P21_13 / RLIN212RX N3 P13_7 / MEMC0A23 / PWGA73O N4 P12_4 / RLIN27TX / PWGA69O / CSIG2SC / ETNB0MDIO / MEMC0BEN1 N9 EVSS N10 EVSS N11 EVSS N12 EVSS N13 EVSS N14 EVSS N19 P9_4 / CSIH0CSS5 / PWGA33O / TAUJ1I0 / TAUJ1O0 / INTP17 / ADCA0I11S N20 P23_7 / CSIG4SI N21 P23_8 / CSIG4SC N22 P23_9 / CSIG4SSI P1 P21_12 / RLIN213TX P2 P21_14 / RLIN212TX P3 P0_1 / TAUD0I4 / TAUD0O4 / CAN0RX / INTP0 / RLIN20TX / PWGA11O / CSIH0SI / APO / TAUJ2I2 / TAUJ2O2 P4 P0_2 / TAUD0I6 / TAUD0O6 / CAN1RX / INTP1 / RLIN30TX / PWGA12O / CSIH0SC / DPO / TAUJ2I3 / TAUJ2O3 P9 EVSS P10 EVSS P11 EVSS P12 EVSS P13 EVSS P14 EVSS P19 P9_3 / KR0I7 / PWGA21O / CSIH2CSS3 / TAUJ1I1 / TAUJ1O1 / INTP16 / ADCA0I10S P20 P23_6 / CSIG4SO P21 P23_4 / CSIH4RYI / CSIH4RYO P22 P23_5 / CSIG4RYI / CSIG4RYO R1 P12_5 / PWGA70O / ETNB0MDC / CSIG2SO / TAUB1I4 / TAUB1O4 R2 P0_3 / TAUD0I8 / TAUD0O8 / RLIN30RX / INTP10 / CAN1TX / DPIN1 / PWGA13O / CSIH0SO / TAUJ1I0 / TAUJ1O0 R3 P0_6 / INTP2 / DPIN10 / SELDP2 / CSIH1SC / PWGA35O R4 P0_4 / RLIN31RX / INTP11 / CAN2TX / PWGA10O / CSIH1SI / SELDP0 / DPIN8 / TAUB0I12 / TAUB0O12 R19 P9_2 / KR0I6 / PWGA20O / TAPA0ESO / CSIH2CSS2 / ADCA0I9S

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 140 of 4535 Dec 26, 2018 Table 2A.4 Pin Assignment 324-Pin FPBGA Pin No. Pin Name R20 P9_1 / INTP11 / PWGA9O / TAUD0I2 / TAUD0O2 / KR0I5 / CSIH2CSS1 / TAUJ1I2 / TAUJ1O2 / SENT1SPCO / RIIC1SCL / ADCA0I3S R21 P23_2 / CSIH4SI R22 P23_3 / CSIH4SC T1 P0_0 / TAUD0I2 / TAUD0O2 / RLIN20RX / CAN0TX / PWGA10O / CSIH0SSI / DPO / TAUJ2I1 / TAUJ2O1 T2 P0_11 / RIIC0SDA / DPIN12 / CSIH1CSS2 / TAUB0I8 / TAUB0O8 / RLIN26RX / PWGA34O T3 P0_13 / RLIN32RX / INTP12 / PWGA46O / TAUB0I12 / TAUB0O12 / CSIG0SO / CAN5RX / INTP5 T4 EVCC T19 EVSS T20 P9_0 / NMI / PWGA8O / TAUD0I0 / TAUD0O0 / ADCA0TRG0 / CSIH2CSS0 / KR0I4 / TAUJ1I1 / TAUJ1O1 / SENT1RX / RIIC1SDA / ADCA0I2S T21 P23_0 / CSIH4SSI T22 P23_1 / CSIH4SO U1 P0_5 / CAN2RX / INTP2 / RLIN31TX / DPIN9 / SELDP1 / CSIH1SO / TAUB0I14 / TAUB0O14 U2 P0_12 / RIIC0SCL / DPIN13 / PWGA45O / TAUB0I10 / TAUB0O10 / CSIG0SI / RLIN26TX U3 P0_14 / INTP17 / RLIN32TX / PWGA47O / TAUB0I14 / TAUB0O14 / CSIG0SC / CAN5TX U4 P1_1 / INTP18 / RLIN33TX / CSIG4SC / TAUJ2I1 / TAUJ2O1 U19 A0VREF U20 AP0_5 / ADCA0I5 U21 AP0_2 / ADCA0I2 U22 AP0_0 / ADCA0I0 V1 P1_0 / RLIN33RX / INTP13 / TAUJ2I0 / TAUJ2O0 / CSIG4SSI V2 P1_12 / CAN4RX / INTP4 / RLIN36TX V3 P1_3 / INTP19 / CAN3TX / DPIN23 / CSIG4SO / TAUJ2I3 / TAUJ2O3 V4 P1_13 / CAN4TX / RLIN36RX / INTP16 V19 A0VSS V20 AP0_10 / ADCA0I10 V21 AP0_4 / ADCA0I4 V22 AP0_1 / ADCA0I1 W1 P1_2 / CAN3RX / INTP3 / DPIN19 / TAUJ2I2 / TAUJ2O2 / CSIG4SI W2 P2_7 / RLIN210RX W3 P2_8 / RLIN210TX W4 P2_11 / PWGA79O W5 JP0_2 / INTP2 / TAUJ0I1 / TAUJ0O1 / FPCK / DCUTCK / LPDCLK W6 JP0_1 / INTP1 / TAUJ0I0 / TAUJ0O0 / FPDT / DCUTDO / LPDO W7 P1_9 / DPIN20 / INTP21 W8 EVCC W9 AWOVCL W10 REG0VCC W11 P0_9 / INTP12 / CSIH1CSS0 / DPIN7 / RLIN22RX / TAUB0I4 / TAUB0O4 / CAN4RX / INTP4 W12 ISOVSS W13 ISOVCL W14 P1_15 / RLIN23TX / CAN7TX W15 EVSS W16 EVCC W17 P3_7 / CAN10RX / INTP20 / PWGA86O

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 141 of 4535 Dec 26, 2018 Table 2A.4 Pin Assignment 324-Pin FPBGA Pin No. Pin Name W18 P3_10 / CAN11TX W19 AP0_14 / ADCA0I14 W20 AP0_8 / ADCA0I8 W21 AP0_6 / ADCA0I6 W22 AP0_3 / ADCA0I3 Y1 P2_6 / ADCA0SEL2 / CSIG4RYI / CSIG4RYO Y2 P2_12 / RLIN211RX Y3 P2_9 / PWGA77O Y4 P8_12 / TAUJ1I3 / TAUJ1O3 / DPIN16 / PWGA44O / CSIH1CSS5 / INTP23 / RLIN25TX / ADCA0I19S Y5 JP0_3 / INTP3 / CSCXFOUT / TAUJ0I2 / TAUJ0O2 / DCUTMS Y6 P2_1 / RLIN27TX / CAN6TX Y7 P2_13 / RLIN211TX Y8 P3_0 / PWGA76O Y9 FLMD0 Y10 JP0_6 / EVTO Y11 P0_8 / INTP16 / RLIN21TX / DPIN6 / CSIH0CSS6 / CSIH1SSI / TAUB0I2 / TAUB0O2 / CAN3TX Y12 P0_7 / RLIN21RX / DPIN5 / CSCXFOUT / CSIH1RYI / CSIH1RYO / TAUB0I0 / TAUB0O0 / CAN3RX / INTP3 Y13 P1_14 / RLIN23RX / CAN7RX / INTP9 / CSIH4RYI / CSIH4RYO Y14 P8_1 / TAPA0ESO / TAUJ0O1 / DPIN0 / PWGA15O / INTP5 / CSIH1CSS3 / CAN6TX / RIIC1SCL / SENT0SPCO / ADCA0I1S Y15 P8_5 / TAUJ0I3 / TAUJ0O3 / NMI / CSIH0CSS3 / INTP9 / PWGA37O / ADCA0I7S Y16 P3_1 / PWGA80O Y17 P3_3 / CAN8RX / INTP18 / PWGA82O Y18 P3_6 / PWGA85O / CAN9TX Y19 P3_9 / CAN11RX / INTP21 Y20 AP0_13 / ADCA0I13 Y21 AP0_12 / ADCA0I12 Y22 AP0_7 / ADCA0I7 AA1 P2_10 / PWGA78O AA2 P8_2 / TAUJ0I0 / TAUJ0O0 / DPIN2 / CSIH0CSS0 / INTP6 / PWGA22O / RLIN37TX / ADCA0I4S AA3 P8_10 / CSIH3CSS3 / DPIN14 / PWGA42O / RLIN37RX / INTP17 / ADCA0I17S AA4 JP0_5 / NMI / RTCA0OUT / TAUJ0I3 / TAUJ0O3 / DCURDY / LPDCLKOUT AA5 P2_0 / RLIN27RX / CAN6RX / INTP6 AA6 P1_11 / ADCA1TRG2 / RLIN24TX / DPIN22 / INTP14 AA7 P2_14 / PWGA74O AA8 IP0_0 / XT2 AA9 P2_15 / PWGA75O AA10 P2_3 / RLIN28TX / CSIH4CSS1 AA11 P2_2 / RLIN28RX / CSIH4CSS0 AA12 P1_5 / ADCA1TRG0 / RLIN35TX / DPIN17 / INTP20 / CSIH4SC AA13 P1_4 / RLIN35RX / INTP15 / DPIN18 / CSIH4SI AA14 P8_0 / TAUJ0I0 / TAUJ0O0 / DPIN2 / PWGA14O / INTP4 / CSIH0CSS0 / CAN6RX / INTP6 / RIIC1SDA / SENT0RX / ADCA0I0S AA15 P8_4 / TAUJ0I2 / TAUJ0O2 / DPIN4 / CSIH0CSS2 / INTP8 / PWGA36O / CAN7RX / INTP9 / ADCA0I6S AA16 P8_7 / CSIH3CSS0 / PWGA39O / ADCA0SEL0 / RTCA0OUT / ADCA0I14S AA17 P3_12 / CSIH4CSS1

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 142 of 4535 Dec 26, 2018 Table 2A.4 Pin Assignment 324-Pin FPBGA Pin No. Pin Name AA18 P8_8 / CSIH3CSS1 / PWGA40O / ADCA0SEL1 / RLIN34RX / INTP14 / ADCA0I15S AA19 P3_4 / PWGA83O / CAN8TX AA20 P3_8 / PWGA87O / CAN10TX AA21 AP0_11 / ADCA0I11 AA22 AP0_9 / ADCA0I9 AB1 EVSS AB2 P8_11 / TAUJ1I2 / TAUJ1O2 / DPIN15 / PWGA43O / CSIH1CSS4 / RLIN25RX / ADCA0I18S AB3 JP0_4 / DCUTRST AB4 JP0_0 / INTP0 / TAUJ2I0 / TAUJ2O0 / FPDR / FPDT / DCUTDI / LPDI / LPDIO AB5 P1_10 / RLIN24RX / DPIN21 / INTP22 / ADCA1TRG1 AB6 P1_8 AB7 RESET AB8 XT1 AB9 AWOVSS AB10 X2 AB11 X1 AB12 P0_10 / INTP3 / CSIH1CSS1 / DPIN11 / RLIN22TX / TAUB0I6 / TAUB0O6 / CAN4TX AB13 P2_4 / RLIN29RX / ADCA0SEL0 / CSIH4SO AB14 P2_5 / RLIN29TX / CSIH4SSI / ADCA0SEL1 AB15 P8_3 / TAUJ0I1 / TAUJ0O1 / DPIN3 / CSIH0CSS1 / INTP7 / PWGA23O / CAN7TX / ADCA0I5S AB16 P3_2 / PWGA81O AB17 P3_11 / CSIH4CSS0 AB18 P8_6 / NMI / CSIH0CSS4 / PWGA38O / RTCA0OUT / ADCA0I8S / RESETOUT AB19 P8_9 / CSIH3CSS2 / PWGA41O / ADCA0SEL2 / RLIN34TX / ADCA0I16S AB20 P3_5 / CAN9RX / INTP19 / PWGA84O AB21 AP0_15 / ADCA0I15 AB22 A0VSS

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 143 of 4535 Dec 26, 2018 2A.2 Pin Description Table 2A.5 Pin Functions Pin Name No. of Pins IO Pin Function Unit 176 Pins 233 Pins 272 Pins 324 Pins AnVREF   —  — ADCAn voltage supply and reference voltage ADCAn n = 0, 1 n = 0, 1 — n = 0, 1 AnVSS   —  — ADCAn ground n = 0, 1 n = 0, 1 — n = 0, 1 ADCA0Im   —  I ADCA0 input channel m with 12-bit resolution m = 0 to 15 m = 0 to 15 — m = 0 to 15 ADCA1Im   —  I ADCA1 input channel m with 12-bit resolution m = 0 to 15 m = 0 to 15 — m = 0 to 15 ADCA0ImS   —  I ADCA0 input channel m with 10-bit resolution m = 0 to 11, 14 to 19 m = 0 to 11, 14 to 19 — m = 0 to 11, 14 to 19 ADCA1ImS   —  I ADCA1 input channel m with 10-bit resolution m = 0 to 7 m = 0 to 19 — m = 0 to 19 ADCA0SELy   —  O Selection pin y for ADCA0 input and external MPX y = 0 to 2 y = 0 to 2 — y = 0 to 2 ADCAnTRGy   —  I ADCAn external trigger pin y n = 0, 1 y = 0 to 2 n = 0, 1 y = 0 to 2 — n = 0, 1 y = 0 to 2 AP0_m   —  IO Analog port 0_m Port m = 0 to 15 m = 0 to 15 — m = 0 to 15 AP1_m   —  IO Analog port 1_m m = 0 to 15 m = 0 to 15 — m = 0 to 15 APO   —  O Port output signal for analog input LPS0 AWOVCL   —  — Voltage regulator for Always-On area (AWO area) capacitor connection Power AWOVSS   —  — Internal logic for Always-On area (AWO area) ground BVCC   —  — Port buffer voltage supply BVSS   —  — Port buffer ground CANzRX   —  I CANz receive data input RCFDCn z = 0 to 7 z = 0 to 7 — z = 0 to 11 CANzTX   —  O CANz transmit data output z = 0 to 7 z = 0 to 7 — z = 0 to 11 CSCXFOUT   —  O Clock output Clock CSIGnRYI   —  I CSIGn ready (1) / busy (0) input signal CSIGn n = 0 to 4 n = 0 to 4 — n = 0 to 4 CSIGnRYO   —  O CSIGn ready (1) / busy (0) output signal n = 0 to 4 n = 0 to 4 — n = 0 to 4 CSIGnSC   —  IO CSIGn serial clock signal n = 0 to 4 n = 0 to 4 — n = 0 to 4 CSIGnSI   —  I CSIGn serial data input n = 0 to 4 n = 0 to 4 — n = 0 to 4 CSIGnSO   —  O CSIGn serial data output n = 0 to 4 n = 0 to 4 — n = 0 to 4 CSIGnSSI   —  I CSIGn SS function control input signal n = 0 to 4 n = 0 to 4 — n = 0 to 4 CSIHnCSS0   —  O CSIHn serial peripheral chip select signal 0 CSIHn n = 0 to 4 n = 0 to 4 — n = 0 to 4 CSIHnCSS1   —  O CSIHn serial peripheral chip select signal 1 n = 0 to 4 n = 0 to 4 — n = 0 to 4

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 144 of 4535 Dec 26, 2018 Table 2A.5 Pin Functions Pin Name No. of Pins IO Pin Function Unit 176 Pins 233 Pins 272 Pins 324 Pins CSIHnCSS2   —  O CSIHn serial peripheral chip select signal 2 CSIHn n = 0 to 3 n = 0 to 3 — n = 0 to 3 CSIHnCSS3   —  O CSIHn serial peripheral chip select signal 3 n = 0 to 3 n = 0 to 3 — n = 0 to 3 CSIHnCSS4   —  O CSIHn serial peripheral chip select signal 4 n = 0 to 2 n = 0 to 2 — n = 0 to 2 CSIHnCSS5   —  O CSIHn serial peripheral chip select signal 5 n = 0 to 2 n = 0 to 2 — n = 0 to 2 CSIHnCSS6   —  O CSIHn serial peripheral chip select signal 6 n = 0 n = 0 — n = 0 CSIHnCSS7   —  O CSIHn serial peripheral chip select signal 7 n = 0 n = 0 — n = 0 CSIHnRYI   —  I CSIHn ready (1) / busy (0) input signal n = 0 to 4 n = 0 to 4 — n = 0 to 4 CSIHnRYO   —  O CSIHn ready (1) / busy (0) output signal n = 0 to 4 n = 0 to 4 — n = 0 to 4 CSIHnSC   —  IO CSIHn serial clock signal n = 0 to 4 n = 0 to 4 — n = 0 to 4 CSIHnSI   —  I CSIHn serial data input n = 0 to 4 n = 0 to 4 — n = 0 to 4 CSIHnSO   —  O CSIHn serial data output n = 0 to 4 n = 0 to 4 — n = 0 to 4 CSIHnSSI   —  I CSIHn slave select input signal n = 0 to 4 n = 0 to 4 — n = 0 to 4 DCURDY   —  O Debug ready OCD DCUTCK   —  I Debug clock DCUTDI   —  I Debug data input DCUTDO   —  O Debug data output DCUTMS   —  I Debug mode select DCUTRST   —  I Debug reset DPINm   —  I Digital port input m LPS0 m = 0 to 23 m = 0 to 23 — m = 0 to 23 DPO   —  O Port output signal for digital input ENCA0TINm   —  I ENCA0 capture trigger input m ENCAn m = 0, 1 m = 0, 1 — m = 0, 1 ENCA0E0   —  I ENCA0 encoder input 0 ENCA0E1   —  I ENCA0 encoder input 1 ENCA0EC   —  I ENCA0 encoder clear input ETNBnLINK   —  I PHY link status ETNBn n = 0 n = 0 — n = 0, 1 ETNBnMDC   —  O PHY management clock n = 0 n = 0 — n = 0, 1 ETNBnMDIO   —  IO Management transmit / receive data signal n = 0 n = 0 — n = 0, 1 ETNBnRXCLK   —  I MII receive clock n = 0 n = 0 — n = 0, 1 ETNBnRXD[3:0]   —  I MII receive data input n = 0 n = 0 — n = 0, 1 ETNBnRXDV   —  I MII receive data valid n = 0 n = 0 — n = 0, 1

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 145 of 4535 Dec 26, 2018 Table 2A.5 Pin Functions Pin Name No. of Pins IO Pin Function Unit 176 Pins 233 Pins 272 Pins 324 Pins ETNBnRXERR   —  I MII receive error ETNBn n = 0 n = 0 — n = 0, 1 ETNBnTXCLK   —  I MII transmit clock n = 0 n = 0 — n = 0, 1 ETNBnTXD[3:0]   —  O MII transmit data output n = 0 n = 0 — n = 0, 1 ETNBnTXEN   —  O MII transmit data enable n = 0 n = 0 — n = 0, 1 EVCC   —  — Port buffer voltage supply Power EVSS   —  — Port buffer ground EVTO   —  O Event output TEU_OUT FLMD0   —  I Operating mode select pin 0 Mode FLMD1   —  I Operating mode select pin 1 FLXA0RXDA   —  I FLXA0 channel A receive data input FLXAn FLXA0RXDB   —  I FLXA0 channel B receive data input FLXA0STPWT   —  I FLXA0 stop watch trigger input FLXA0TXDA   —  O FLXA0 channel A transmit data output FLXA0TXDB   —  O FLXA0 channel B transmit data output FLXA0TXENA   —  O FLXA0 channel A transmit enable FLXA0TXENB   —  O FLXA0 channel B transmit enable FPDR   —  I Serial Communication Interface RXD FLASH FPDT   —  O Serial Communication Interface TXD FPCK   —  I Serial Communication Interface clock INTPm   —  I External interrupt input m INTC m = 0 to 23 m = 0 to 23 — m = 0 to 23 IP0_0   —  I Input port 0_0 Port ISOVCL   —  — Voltage regulator for Isolated area (ISO area) capacitor connection Power ISOVSS   —  — Internal logic for Isolated area (ISO area) ground JP0_m   —  IO JTAG port 0_m JTAG m = 0 to 6 m = 0 to 6 — m = 0 to 6 KR0Im   —  I KR0 key input signal KRn m = 0 to 7 m = 0 to 7 — m = 0 to 7 LPDCLK   —  I LPD clock input (4-pin mode) LPD LPDCLKOUT   —  O LPD clock output (4-pin mode) LPDI   —  I LPD data input (4-pin mode) LPDIO   —  IO LPD data input / output (1-pin mode) LPDO   —  O LPD data output (4-pin mode) MEMC0Am   —  O MEMC0 address m MEMCn m = 16 to 22 m = 16 to 22 — m = 16 to 23 MEMC0ADm   —  IO MEMC0 address / data m m = 0 to 15 m = 0 to 15 — m = 0 to 15 MEMC0ASTB   —  O MEMC0 address strobe MEMC0BENm   —  O MEMC0 byte enable m m = 0, 1 m = 0, 1 — m = 0, 1 MEMC0CLK   —  O MEMC0 clock output MEMC0CSm   —  O MEMC0 chip select m m = 0 to 3 m = 0 to 3 — m = 0 to 3 MEMC0RD   —  O MEMC0 read strobe MEMC0WAIT   —  I MEMC0 wait input MEMC0WR   —  O MEMC0 write strobe

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 146 of 4535 Dec 26, 2018 Table 2A.5 Pin Functions Pin Name No. of Pins IO Pin Function Unit 176 Pins 233 Pins 272 Pins 324 Pins MMCA0CLK — — —  O MMCA Clock MMCAn MMCA0CMD — — —  IO MMCA Command / Response MMCA0DATm — — —  IO MMCA Data[7:0] m = 0 to 7 MODEm   —  I Sub operating mode select Mode m = 0 to 2 m = 0 to 2 — m = 0 to 2 NMI   —  I External non-maskable interrupt input INTC m = 0 to 14 m = 0 to 14 — m = 0 to 14 m = 0 to 5, 8 to 15 m = 0 to 5, 8 to 15 — m = 0 to 5, 8 to 15 m = 0 to 6 m = 0 to 15 — m = 0 to 15 P3_m  —  IO Port3_m m = 0 — m = 0 to 12 m = 0 to 12 m = 0 to 12 — m = 0 to 12 m = 0 to 4 m = 0 to 4 — m = 0 to 4 m = 0 to 15 m = 0 to 15 — m = 0 to 15 m = 0 to 12, m = 0 to 12, — m = 0 to 12, m = 0 to 5 m = 0 to 5 — m = 0 to 5 P13_m  —  IO Port 13_m m = 0 to 7 — m = 0 to 7 m = 0 to 7 m = 0 to 15 — m = 0 to 15 P19_m  —  IO Port19_m m = 0 to 3 — m = 0 to 3 m = 0 to 5 m = 0 to 5 — m = 0 to 15 P21_m ― ― —  IO Port21_m — m = 0 to 14 P22_m ― ― —  IO Port22_m — m = 0 to 15 P23_m ― ― ―  IO Port23_m m = 0 to 10 P24_m ― ― ―  IO Port24_m m = 0 to 7 PWGAnO   —  O PWGAn output signal PWGAn n = 0 to 71 n = 0 to 79 — n = 0 to 95 REGnVCC   —  — Voltage regulators voltage supply Power RESET   —  I External reset input Reset RESETOUT   —  O Reset output

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 147 of 4535 Dec 26, 2018 Table 2A.5 Pin Functions Pin Name No. of Pins IO Pin Function Unit 176 Pins 233 Pins 272 Pins 324 Pins RIICnSCL   —  IO RIICn serial clock RIICn n = 0, 1 n = 0, 1 — n = 0, 1 RIICnSDA   —  IO RIICn serial data n = 0, 1 n = 0, 1 — n = 0, 1 RLIN2mRX   —  I RLIN2m receive data input RLIN24n m = 0 to 9 m = 0 to 11 — m = 0 to 15 RLIN2mTX   —  O RLIN2m transmit data output m = 0 to 9 m = 0 to 11 — m = 0 to 15 RLIN3nRX   —  I RLIN3n receive data input RLIN3n n = 0 to 7 n = 0 to 7 — n = 0 to 7 RLIN3nTX   —  O RLIN3n transmit data output n = 0 to 7 n = 0 to 7 — n = 0 to 7 RTCA0OUT   —  O RTCA0 1Hz output RTCAn SELDPk   —  O External multiplexer select signal output k for the digital port LPS0 k = 0 to 2 k = 0 to 2 — k = 0 to 2 SENTnRX   —  I SENT receive data input RSENTn n = 0, 1 n = 0, 1 — n = 0, 1 SENTnSPCO   —  O SENT SPC Extension Output n = 0, 1 n = 0, 1 — n = 0, 1 SFMA0CLK   —  O SFMA0 clock SFMAn SFMA0IOm   —  IO SFMA0 master data input / output m = 0 to 3 m = 0 to 3 — m = 0 to 3 SFMA0SSL   —  O SFMA0 slave select TAPA0ESO   —  I Hi-Z control TAPAn TAPA0UN   —  O Motor control output U phase (negative) TAPA0UP   —  O Motor control output U phase (positive) TAPA0VN   —  O Motor control output V phase (negative) TAPA0VP   —  O Motor control output V phase (positive) TAPA0WN   —  O Motor control output W phase (negative) TAPA0WP   —  O Motor control output W phase (positive) TAUBnIm   —  I TAUBn channel input m TAUBn n = 0, 1 m = 0 to 15 n = 0, 1 m = 0 to 15 — n = 0, 1 m = 0 to 15 TAUBnOm   —  O TAUBn channel output m n = 0, 1 m = 0 to 15 n = 0, 1 m = 0 to 15 — n = 0, 1 m = 0 to 15 TAUD0Im   —  I TAUD0 channel input m TAUDn m = 0 to 15 m = 0 to 15 — m = 0 to 15 TAUD0Om   —  O TAUD0 channel output m m = 0 to 15 m = 0 to 15 — m = 0 to 15 TAUJnIm   —  I TAUJn channel input m TAUJn n = 0 to 3 m = 0 to 3 n = 0 to 3 m = 0 to 3 — n = 0 to 3 m = 0 to 3 TAUJnOm   —  O TAUJn channel output m n = 0 to 3 m = 0 to 3 n = 0 to 3 m = 0 to 3 — n = 0 to 3 m = 0 to 3 X1, X2   —  — Main OSC connections MOSC XT1, XT2   —  — Sub OSC connections SOSC

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 148 of 4535 Dec 26, 2018 CAUTION When pin functions for a peripheral module are allocated to multiple pins, use the pins from the same port group or nearby pins as the pins for a given channel.

• (e.g.) When RS-CANFD channel 0 is used: CAN0TX P0_0 P10_1 CAN0RX P0_1 P10_0 Use one of the following pin combinations: - P0_0 and P0_1, or - P10_0 and P10_1. The combinations of P0_0 and P10_0, and P0_1 and P10_1 are not allowed.
• (e.g.) When CSIH4 is used: CSIH4SC P1_5 P23_3 CSIH4S O P2_4 P23_1 CSIH4SI P1_4 P23_2 Use one of the following pin combinations: - P1_5, P2_4 and P1_4, or - P23_3, 23_1 and P23_2. The pin combinations of the following are not allowed: - P1_5, P2_4 and P23_2 - P1_5, P23_1 and P1_4 - P23_3, P2_4 and P23_2 - P1_5, P23_1 and P23_2 - P23_3, P2_4 and P1_4 - P23_3, P23_1 and P1_4.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 149 of 4535 Dec 26, 2018 2A.3 Pin Functions During and After Reset Table 2A.6 Pin Functions During and After Reset Pins During Reset After Reset JP0_0 High impedance JP0_0: Input Serial programming mode: FPDR, FPDT (1 wire UART) FPDR (2 wire UART) Nexus I/F: DCUTDI input LPD (4 pins): LPDI input LPD (1 pin): LPDIO input/output JP0_1 High impedance JP0_1: Input Serial programming mode: FPDT Nexus I/F: DCUTDO output LPD (4 pins): LPDO output LPD (1 pin): High impedance JP0_2 High impedance JP0_2: Input Serial programming mode: FPCK Nexus I/F: DCUTCK input LPD (4 pins): LPDCLK input LPD (1 pin): High impedance JP0_3 High impedance JP0_3: Input Serial programming mode: High impedance Nexus I/F: DCUTMS input LPD (4 pins): High impedance LPD (1 pin): High impedance JP0_4 Input*3,*5 JP0_4: Input Serial programming mode: High impedance Nexus I/F: DCUTRST input*1 LPD (4 pins): High impedance LPD (1 pin): High impedance JP0_5 High impedance JP0_5: Input Serial programming mode: High impedance Nexus I/F: DCURDY output LPD (4 pins): LPDCLKOUT output LPD (1 pin): High impedance JP0_6 High impedance JP0_6: Input Serial programming mode: High impedance Nexus I/F: EVTO output LPD (4 pins): High impedance LPD (1 pin): High impedance P8_6 Output*2,*4 Output (OPBT0.RESETOUTEN = 1)*2 High impedance (OPBT0.RESETOUTEN = 0)*2,*4 P0 to P3, P8 to P13, P18 to P24 (except P8_6, P10_1, P10_2, P10_6 and P10_8) High impedance High impedance P10_1 High impedance High impedance (FLMD0 = 0) High impedance (FLMD0 = 1, FLMD1 = 0) MODE0 input (FLMD0 = 1, FLMD1 = 1) P10_2 High impedance High impedance (FLMD0 = 0) High impedance (FLMD0 = 1, FLMD1 = 0) MODE1 input (FLMD0 = 1, FLMD1 = 1)

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 150 of 4535 Dec 26, 2018 Table 2A.6 Pin Functions During and After Reset Pins During Reset After Reset P10_6 High impedance High impedance (FLMD0 = 0) High impedance (FLMD0 = 1, FLMD1 = 0) High impedance (FLMD0 = 1, FLMD1 = 1, MODE0 = 0, MODE1 = 0) High impedance (FLMD0 = 1, FLMD1 = 1, MODE0 = 0, MODE1 = 1) High impedance (FLMD0 = 1, FLMD1 = 1, MODE0 = 1, MODE1 = 0) MODE2 input (FLMD0 = 1, FLMD1 = 1, MODE0 = 1, MODE1 = 1) P10_8 High impedance High impedance (FLMD0 = 0) FLMD1 input (FLMD0 = 1) FLMD0 Input Input RESET Input Input AP0, AP1 High impedance High impedance Note 1. When Nexus is enabled and no external device is connected, the level of the pin must always be fixed to low level. Note 2. RESETOUT is output. For details, see Section 2A.11, Port (Special I/O) Function Overview. Note 3. When the power is turned on or when RESET is low level, JP0_4 pin should be driven low level. Note 4. If OPBT0.RESETOUTEN = 0, P8_6 pin status has a possibility to become unstable (less than 15 μs) at the transition moment to reset status by internal reset factors. Note 5. When RESET is low level, on-chip pull-down resistor is connected to JP0_4.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 151 of 4535 Dec 26, 2018 2A.4 Port State in Standby Mode For the port state in standby mode, see Section 14.1.4, I/O Buffer Control. 2A.5 Recommended Connection of Unused Pins If the pins are not used, it is recommended to connect them as shown below. Table 2A.7 Recommended Connection of Unused Pins Pin Recommended Connection of Unused Pins A0VREF, A1VREF Connected to EVCC or BVCC A0VSS, A1VSS Connected to EVSS or BVSS RESET Connected to EVCC or BVCC via a resistor XT1 Connected to REGnVCC or AWOVSS via a resistor*2 (bit 0 of IPIBC0 = 1) Connected to AWOVSS (bit 0 of IPIBC0 = 0) X1 Connected to AWOVSS via a resistor X2 Open IP0_0 Connected to REGnVCC or AWOVSS via a resistor*2 (bit 0 of IPIBC0 = 1) Open (bit 0 of IPIBC0 = 0) JP0 (excluding JP0_4) P8 (excluding P8_6) P20 P23 Input: Open (when the PIBCn_m and PMCn_m bits are 0) Connected to EVCC or EVSS via a resistor (when the PIBCn_m or PMCn_m bits are 1) Output: Open P8_6 Input: Open (when the PIBCn_m and PMCn_m bits are 0) Connected to EVSS via a resistor (when the PIBCn_m or PMCn_m bits are 1) Output: Open JP0_4 Connected to EVSS via a resistor P10_1, P10_2, P10_6, P10_8 Input: Open (when the PIBCn_m and PMCn_m bits are 0) Connected to EVSS via a resistor (when the PIBCn_m or PMCn_m bits are 1) Output: Open

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 152 of 4535 Dec 26, 2018 Table 2A.7 Recommended Connection of Unused Pins Pin Recommended Connection of Unused Pins P10 (excluding P10_1, P10_2, P10_6, P10_8) P11 P12 P13 P18 P19 P21 P22 P24 Input: Open (when the PIBCn_m and PMCn_m bits are 0) Connected to BVCC or BVSS via a resistor (when the PIBCn_m or PMCn_m bits are 1) Output: Open AP0 Input: Open (when the PIBCn_m bit is 0) Connected to A0VREF or A0VSS via a resistor (when the PIBCn_m bit is 1) Output: Open AP1 Input: Open (when the PIBCn_m bit is 0) Connected to A1VREF or A1VSS via a resistor (when the PIBCn_m bit is 1) Output: Open Nexus/LPD I/F (JP0) DCUTDI/LPDI/LPDIO (JP0_0): Connected to EVCC via a resistor DCUTDO/LPDO (JP0_1): Open DCUTCK/LPDCLK (JP0_2): Open DCUTMS (JP0_3): Connected to EVCC via a resistor DCUTRST (JP0_4): Connected to EVSS via a resistor*1 DCURDY /LPDCLKOUT (JP0_5): Open EVTO (JP0_6): Open Note 1. For in case when a debugging interface is used, this pin should be connected to EVCC through resistor depending on the development tool made by a third party. Note 2. XT1 = IP0_0 (XT2) = REGnVCC or AWOVSS should be set. XT1 is connected to IP0_0 (XT2) through an internal resistor. Therefore, it is necessary to maintain equal voltage level in order not to make a current path.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 153 of 4535 Dec 26, 2018 2A.6 Features of RH850/F1KH Port 2A.6.1 Port Group The RH850/F1KH provides the following port groups, indicated by the numbers in the table below. Table 2A.8 Port Groups in RH850/F1KH-D8 No. of Pins Port Group RH850/F1KH-D8 176 pins Number 14 Name P0 to P2, P8 to P12, P18, P20, JP0, AP0,AP1, IP0 233 pins Number 17 Name P0 to P3, P8 to P13, P18 to P20, JP0, AP0, AP1, IP0 324 pins Number 21 Name P0 to P3, P8 to P13, P18 to P24, JP0, AP0, AP1, IP0 2A.6.2 Port Group Index n Throughout this section, the port groups are identified by using the index “n”. For example, the port mode control register of the Pn pin is PMCn (n = 0 to 3, 8 to 13, 18 to 24). 2A.6.3 Register Base Addresses Port and JTAG port base addresses are listed in the following table. Port and JTAG port register addresses are given as offsets from the base addresses. Table 2A.9 Register Base Addresses Base Address Name Base Address <PORTn_base> FFC1 0000H <JPORT0_base> FFC2 0000H 2A.6.4 Clock Supply The clock supply to ports is shown in the following table. Table 2A.10 Clock Supply Unit Name Unit Clock Name Supply Clock Name Port Register access clock CPUCLK_UL

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 154 of 4535 Dec 26, 2018 2A.7 Port Functions The microcontroller has various pins for input/output functions, known as ports. The ports are organized in port groups. The RH850/F1KH also has several control registers to enable pins to be used as other than general-purpose input/output pins. For a description of the terms pin, port, and port group, see Section 2A.7.2, Terms. 2A.7.1 Functional Overview

• All the port settings can be specified individually.
• The maximum number of bits (pins) in a port is 16.
• The output level of any pin can be set independently without affecting the other pins in the same port.
• Input buffers are enabled through registers settings.
• Pin level is read by dedicated port-pin-read register (PPR)
• All possible port functions are shown in the tables listed below. Table 2A.39, JTAG Port 0 (JP0), Table 2A.41, Port 0 (P0), Table 2A.43, Port 1 (P1), Table 2A.45, Port 2 (P2), Table 2A.47, Port 3 (P3), Table 2A.49, Port 8 (P8), Table 2A.51, Port 9 (P9), Table 2A.53, Port 10 (P10), Table 2A.55, Port 11 (P11), Table 2A.57, Port 12 (P12), Table 2A.59, Port 13 (P13), Table 2A.61, Port 18 (P18), Table 2A.63, Port 19 (P19), Table 2A.65, Port 20 (P20), Table 2A.67, Port 21 (P21), Table 2A.69, Port 22 (P22), Table 2A.71, Port 23 (P23), Table 2A.73, Port 24 (P24), Table 2A.75, Analog Port 0 (AP0), Table 2A.77, Analog Port 1 (AP1), Table 2A.79, Input Port 0 (IP0), and Section 2A.9.2, Pin Function Configuration. CAUTION Some input or output functions may be assigned to more than one port. Only activate a given function on a single pin. Do not activate a function on multiple pins at the same time. This also applies in cases where multiple peripheral functions are assigned to a single multiplexed function and only one of these functions is used. [Example] INTP0 is assigned to the following pins on this device. However, the INTP0 function should not be activated on more than one pin. After activating the function on one pin, do not activate it on another.
• JP0_0 (1st input alternative function)
• P0_1 (2nd, 3rd input alternative function)
• P10_0 (2nd input alternative function) In the above case, when the 1st input alternative function (INTP0) of JP0_0 is selected, using the 2nd input alternative function (CAN0RX/INTP0) of P0_1 only for the CAN signal is also prohibited.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 155 of 4535 Dec 26, 2018 2A.7.2 Terms The following terms are used in this section: Pin Denotes the physical pin. Every pin is denoted by a unique pin number. A pin can be used in several modes. Each pin is assigned a name that reflects its function, which is determined by the selected mode. Port group Denotes a group of pins. All the pins of a specific port group are controlled by the same port control register. Port mode and ports A pin in port mode works as a general-purpose input/output pin. It is then called “port”. The corresponding name is Pn_m. For example, P0_7 denotes port 7 of port group 0. It is referenced as “port P0_7”. Alternative mode In alternative mode, a pin can be used for various non-general-purpose input/output functions, such as the input/output pin of on-chip peripherals. The corresponding pin name depends on the selected function. For example, pin INTP0 denotes the pin for one of the external interrupt inputs. Note that two different names can refer to the same physical pin, for example P0_0 and INTP0. The different names indicate the function of the pin at that time. 2A.7.2.1 JTAG Ports The JTAG port groups are used for connecting a debugger for on-chip debugging. JTAG port group registers and bit names are prefixed by a “J”. For example, JP0 denotes JTAG port group 0, and JPM0.JPM0_m denotes the JPM0_m port mode bit of the JPM0 port mode register. NOTE In this section, the descriptions about all ports and their registers other than PFCAEn and PIPCn apply to the JTAG port unless otherwise specified.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 156 of 4535 Dec 26, 2018 2A.7.3 Overview of Pin Functions Pins can operate in three modes.

• Port mode (PMCn.PMCn_m bit = 0) A pin in port mode operates as a general-purpose input/output pin. The I/O mode is selected by setting the PMn.PMn_m bit.
• Software I/O control alternative mode (PMCn.PMCn_m bit = 1, PIPCn.PIPCn_m bit = 0) In this mode, the pins operate as alternative functions. The I/O mode is selected by setting the PMn.PMn_m bit.
• Direct I/O control alternative mode (PMCn.PMCn_m bit = 1, PIPCn.PIPCn_m bit = 1) In this mode, the pins operate as alternative functions. Unlike the software I/O control alternative mode, however, the I/O mode is directly controlled by the alternative function. An overview of the register settings is given in the tables below. Table 2A.11 Pin Function Configuration (Overview) Mode Bit I/O PMCn_m PMn_m PIPCn_m Port mode 0 0 X O 1*1 I Software I/O control alternative mode 1 0 0 O 1 0 I Direct I/O control alternative mode X 1 Controlled by the alternative function Note 1. The input buffer must be enabled (PIBCn_m bit = 1).
• Software I/O control alternative mode (PIPCn.PIPCn_m bit = 0) − Output (PMn_m bit = 0): Alternative output mode 1 to Alternative output mode 7 − Input (PMn_m bit = 1): Alternative input mode 1 to Alternative input mode 7
• Direct I/O control alternative mode (PIPCn.PIPCn_m bit = 1) − The I/O mode for Alternative output mode 1 to Alternative output mode 7 and Alternative input mode 1 to Alternative input mode 7 is directly selected by the alternative function.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 157 of 4535 Dec 26, 2018 Table 2A.12 Alternative Mode Selection Overview (PMCn.PMCn_m Bit = 1) Register Mode PIPC*1 PM*1 PFCAE PFCE PFC I/O Alternative output mode 1 (ALT-OUT1) 0 0 0 0 0 O Alternative input mode 1 (ALT-IN1) 1 I Alternative output mode 2 (ALT-OUT2) 0 1 O Alternative input mode 2 (ALT-IN2) 1 I Alternative output mode 3 (ALT-OUT3) 0 1 0 O Alternative input mode 3 (ALT-IN3) 1 I Alternative output mode 4 (ALT-OUT4) 0 1 O Alternative input mode 4 (ALT-IN4) 1 I Alternative output mode 5 (ALT-OUT5) 0 1 0 0 O Alternative input mode 5 (ALT-IN5) 1 I Alternative output mode 6 (ALT-OUT6) 0 1 O Alternative input mode 6 (ALT-IN6) 1 I Alternative output mode 7 (ALT-OUT7) 0 1 0 O Alternative input mode 7 (ALT-IN7) 1 I Other than the above Setting prohibited Note 1. If PIPCn.PIPCn_m = 1, the I/O direction is directly controlled by the peripheral (alternative) function and PM is ignored. If a pin is in alternative mode (PMCn.PMCn_m bit = 1), one of up to seven alternative functions can be selected for that pin by using the PFCn, PFCEn, and PFCAEn registers.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 158 of 4535 Dec 26, 2018 2A.7.4 Pin Data Input/Output The registers used for data input/output are described below. The location that is read via the PPRn register differs depending on the pin mode. 2A.7.4.1 Output Data In the port mode (PMCn.PMCn_m = 0), the value of the Pn.Pn_m is output from the Pn_m pin. 2A.7.4.2 Input Data When the PPRn register is read, either the value of the Pn_m pin, the value of the Pn.Pn_m, or the value output by the alternative function is returned. Which value is returned depends on the pin mode and setting of several control bits. The different PPRn read modes are shown in the table below. Table 2A.13 PPRn_m Read Values PMC n_m PM n_m PIBC n_m PIPC n_m PODC n_m Mode PPRn_m Read Value 0 1 0 X X Port input, input buffer disabled Pn.Pn_m bit

1 X Port input, input buffer enabled Pn_m pin

0 X 0 Port push-pull output Pn.Pn_m bit*1

1 Port open-drain output

1 1 X 0 X Software I/O control alternative input Pn_m pin 0 0 Software I/O control alternative push- pull output Output signal from the alternative function*1

1 Software I/O control alternative open-

X 1 0 Direct I/O control alternative input or push-pull output I/O port in alternative mode:

• Input: Pn_m pin
• Output: Output signal from the alternative function*1

1 Direct I/O control alternative input or

Note 1. When PBDCn_m = 1, the level of the Pn_m pin is returned by the PPRn_m bit. The control registers in the above table have the following effects:

• PMCn.PMCn_m bit This bit selects port mode (PMCn_m = 0) or alternative mode (PMCn_m = 1).
• PMn.PMn_m bit This bit selects input (PMn_m = 1) or output (PMn_m = 0) when the port mode (PMCn_m = 0) and software I/O control alternative mode (PMCn_m = 1, PIPCn_m = 0) have been selected.
• PIBCn.PIBCn_m bit This bit disables (PIBCn_m = 0) or enables (PIBCn_m = 1) the input buffer in input port mode (PMCn_m = 0 and PMn_m = 1). If the input buffer is disabled, PPRn_m reads the Pn.Pn_m bit; otherwise t he Pn_m pin level is returned.
• PIPCn.PIPCn_m bit This bit selects software I/O control alternative mode or direct I/O control alternative mode.
• PODCn.PODCn_m bit This bit selects push-pull output (PODCn_m = 0) or open-drain output (PODCn_m = 1).

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 159 of 4535 Dec 26, 2018

• PBDCn.PBDCn_m bit In output mode, when this bit is set to 1, the pin enters the bidirectional mode. In bidirectional mode, the level of the signal on a Pn_m pin can be read from PPRn.PPRn_m. CAUTION When using Pn_m as an alternative output function (PMCn.PMCn_m = 1, PMn.PMn_m = 0), the level of the Pn_m pin can be read at the PPRn.PPRn_m bit by enabling bidirectional mode (PBDCn.PBDCn_m = 1). Note, however, that the level of the Pn_m pin will be input to the alternative function that the Pn_m pin is being used as. 2A.7.4.3 Writing to the Pn Register The data to be output via port Pn_m in port mode (PMCn.PMCn_m bit = 0) is held in port register Pn. Pn data can be overwritten in two ways:
• By writing data directly to the Pn register. In this case, new data can be written directly to the Pn register.
• By performing an indirect bitwise operation (a “set”, “reset”, or “not” operation) on the Pn register. An indirect bitwise operation (“set”, “reset”, or “not”) can be performed on the Pn register by using the following two registers: − Port Set/Reset register PSRn If the PSRn.PSRn (m + 16) bit = 1, the value of the Pn.Pn_m bit is determined by the value of the PSRn.PSRn_m bit. In other words, the Pn_m bit can be set or reset without writing directly to the Pn register. − Port NOT register PNOTn By setting PNOTn.PNOTn_m to 1, the Pn.Pn_m bit can be inverted without writing directly to the Pn register. An indirect bitwise operation on the Pn register (“set”, “reset”, or “not”) has no effect on the bits that do not need to be updated, allowing you to overwrite only the bit or bits that need to be overwritten.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 160 of 4535 Dec 26, 2018 2A.8 Schematic View of Port Control The following figure is a schematic view of the port control functions. Peripheral bus (PBUS) PDSC PU PD PBDC PM PIBC PMC PIPC PODC PPR P PSR PNOT PPCMD PFC PFCE PFCAE PMSR PMCSR PPROTS PIS Internal IPs 1 2 3 ... 1 2 3 1 2 3 1 2 3 Internal IP data output Internal IP data output control Internal IP data input control Internal IP data input Output buffer control Pull-down control Pull-up control Input buffer control Input buffer control P N Output data control Input data control Alternative function selection PISA Open drain control Figure 2A.5 Schematic View of Port Control CAUTION Use documented alternative functions only. The behavior and performance are not guaranteed when undocumented alternative functions are selected.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 161 of 4535 Dec 26, 2018 2A.9 Port Group Configuration Registers This section starts with an overview of all configuration registers and then describes all registers in detail. The configuration registers are grouped as follows:

• Section 2A.9.2, Pin Function Configuration
• Section 2A.9.3, Pin Data Input/Output
• Section 2A.9.4, Configuration of Electrical Characteristics 2A.9.1 Overview The following registers are used for setting the individual pins of the port groups. For details on <PORTn_base> and <JPORT0_base>, see Section 2A.6.3, Register Base Addresses. Table 2A.14 Port Group Configuration Registers Module Name Register Name Symbol Address Pin function configuration PORT Port mode control register PMCn <PORTn_base> + 0400H + n × 4 JTAG JPMC0 <JPORT0_base> + 0040H PORT Port mode control set/reset register PMCSRn <PORTn_base> + 0900H + n × 4 JTAG JPMCSR0 <JPORT0_base> + 0090H PORT Port IP control register PIPCn <PORTn_base> + 4200H + n × 4 PORT Port mode register PMn <PORTn_base> + 0300H + n × 4 APMn <PORTn_base> + 03C8H + n × 4 JTAG JPM0 <JPORT0_base> + 0030H PORT Port mode set/reset register PMSRn <PORTn_base> + 0800H + n × 4 APMSRn <PORTn_base> + 08C8H + n × 4 JTAG JPMSR0 <JPORT0_base> + 0080H PORT Port input buffer control register PIBCn <PORTn_base> + 4000H + n × 4 APIBCn <PORTn_base> + 40C8H + n × 4 JTAG JPIBC0 <JPORT0_base> + 0400H PORT IPIBC0 <PORTn_base> + 40F0H PORT Port function control register PFCn <PORTn_base> + 0500H + n × 4 JTAG JPFC0 <JPORT0_base> + 0050H PORT Port function control expansion register PFCEn <PORTn_base> + 0600H + n × 4 JTAG JPFCE0 <JPORT0_base> + 0060H PORT Port function control additional expansion register PFCAEn <PORTn_base> + 0A00H + n × 4 Pin data input/output PORT Port bidirection control register PBDCn <PORTn_base> + 4100H + n × 4 APBDCn <PORTn_base> + 41C8H + n × 4 JTAG JPBDC0 <JPORT0_base> + 0410H PORT Port pin read register PPRn <PORTn_base> + 0200H + n × 4 APPRn <PORTn_base> + 02C8H + n × 4 JTAG JPPR0 <JPORT0_base> + 0020H PORT IPPR0 <PORTn_base> + 02F0H

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 162 of 4535 Dec 26, 2018 Table 2A.14 Port Group Configuration Registers Module Name Register Name Symbol Address Pin data input/output PORT Port register Pn <PORTn_base> + 0000H + n × 4 APn <PORTn_base> + 00C8H + n × 4 JTAG JP0 <JPORT0_base> + 0000H PORT Port NOT register PNOTn <PORTn_base> + 0700H + n × 4 APNOTn <PORTn_base> + 07C8H + n × 4 JTAG JPNOT0 <JPORT0_base> + 0070H PORT Port set/reset register PSRn <PORTn_base> + 0100H + n × 4 APSRn <PORTn_base> + 01C8H + n × 4 JTAG JPSR0 <JPORT0_base> + 0010H Configuration of electrical characteristics PORT Pull-up option register PUn <PORTn_base> + 4300H + n × 4 JTAG JPU0 <JPORT0_base> + 0430H PORT Pull-down option register PDn <PORTn_base> + 4400H + n × 4 JTAG JPD0 <JPORT0_base> + 0440H PORT Port drive strength control register PDSCn <PORTn_base> + 4600H + n × 4 JTAG JPDSC0 <JPORT0_base> + 0460H PORT Port open drain control register PODCn <PORTn_base> + 4500H + n × 4 JTAG JPODC0 <JPORT0_base> + 0450H PORT Port input buffer selection register PISn <PORTn_base> + 4700H + n × 4 JTAG JPIS0 <JPORT0_base> + 0470H PORT Port input buffer selection advanced register PISAn <PORTn_base> + 4A00H + n × 4 JTAG JPISA0 <JPORT0_base> + 04A0H Port register protection PORT Port protection command register PPCMDn <PORTn_base> + 4C00H + n × 4 JTAG JPPCMD0 <JPORT0_base> + 04C0H PORT Port protection status register PPROTSn <PORTn_base> + 4B00H + n × 4 JTAG JPPROTS0 <JPORT0_base> + 04B0H

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 163 of 4535 Dec 26, 2018 Index n In Table 2A.14, Port Group Configuration Registers, the index “n” in register symbols denotes the actual indices of the individual port groups. For example, PMCn generically indicates a port mode control register for port group n (Pn). The values for n differ according to the number of pins on the device in the way shown in Table 2A.15, Number of Pins on the Device, Name of Port Groups, and Values for “n” in Register Symbols . Table 2A.15 Number of Pins on the Device, Name of Port Groups, and Values for “n” in Register Symbols Number of Pins on the Device Port Groups Values for “n” 176 pins P0, P1, P2, P8, P9, P10, P11, P12, P18, P20 0,1,2,8,9,10,11,12,18,20 AP0, AP1 0, 1 233 pins P0, P1, P2, P3, P8, P9, P10, P11, P12, P13, P18, P19, P20 0,1,2,3,8,9,10,11,12,13,18,19,20 AP0, AP1 0, 1 324 pins P0, P1, P2, P3, P8, P9, P10, P11, P12, P13, P18, P19, P20, P21, P22, P23, P24 22,23,24 AP0, AP1 0, 1 JTAG port registers JTAG port registers are not explicitly described in the following register descriptions. All descriptions (except for those of the PFCAEn register and PIPCn register) apply to JTAG port registers. Note, however, that the JTAG port register base address differs from that of regular ports. Value after reset The values after reset depend on the ports. For the values after reset, see the register descriptions in t he following pages.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 164 of 4535 Dec 26, 2018 2A.9.2 Pin Function Configuration 2A.9.2.1 PMCn / JPMC0 — Port Mode Control Register This register specifies whether the individual pins of port group n are in port mode or in alternative mode. Access: PMCn: This register can be read or written in 16-bit units. JPMC0: This register can be read or written in 8-bit units. Address: PMCn: <PORTn_base> + 0400H + n × 4 (n = 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 18, 20, 21, 22, 23, 24) JPMC0: <JPORT0_base> + 0040H*1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PMC n_15 PMC n_14 PMC n_13 PMC n_12 PMC n_11 PMC n_10 PMC n_9 PMC n_8 PMC n_7 PMC n_6 PMC n_5 PMC n_4 PMC n_3 PMC n_2 PMC n_1 PMC n_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2A.10, Port (General I/O) Function Overview: Table 2A.40, Control Registers (JP0), Table 2A.42, Control Registers (P0), Table 2A.44, Control Registers (P1), Table 2A.46, Control Registers (P2), Table 2A.48, Control Registers (P3), Table 2A.50, Control Registers (P8), Table 2A.52, Control Registers (P9), Table 2A.54, Control Registers (P10), Table 2A.56, Control Registers (P11), Table 2A.58, Control Registers (P12), Table 2A.60, Control Registers (P13), Table 2A.62, Control Registers (P18), Table 2A.66, Control Registers (P20), Table 2A.68, Control Registers (P21), Table 2A.70, Control Registers (P22), Table 2A.72, Control Registers (P23), and Table 2A.74, Control Registers (P24). Table 2A.16 PMCn Register Contents Bit Position Bit Name Function 15 to 0 PMCn_[15:0] Specifies the operation mode of the corresponding pin. 0: Port mode 1: Alternative mode CAUTIONS 1. I/O is not controlled by only setting alternative mode (PMCn.PMCn_m bit = 1). If the alternative function requires direct I/O control, also set the PIPCn.PIPCn_m bit to 1. 2. If a port is to be used as an input pin in alternative mode, the signals from some pins will pass through a noise filter. These pins may require the setting of the FCLA0CTLm_<name>, DNFA<name>CTL and the DNFA<name>EN register. For details, see Section 2A.12, Noise Filter & Edge/Level Detector, and Section 2A.13, Description of Port Noise Filter & Edge/Level Detection. NOTE The control bits of the JTAG port mode control register (JPMC0) are JPMC0_[7:0].

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 165 of 4535 Dec 26, 2018 2A.9.2.2 PMCSRn / JPMCSR0 — Port Mode Control Set/Reset Register This register provides an alternative method to write data to the PMCn register. The upper 16 bits of PMCSRn act as a mask which specifies whether or not the value of PMCn.PMCn_m i s set by the corresponding bit in the lower 16 bits of PMCSRn. Access: PMCSRn: This register can be read or written in 32-bit units. Bits 31 to 16 are always read as 0000H. Reading bits 15 to 0 returns the value of register PMCn. JPMCSR0: This register can be read or written in 32-bit units. Bits 31 to 8 are always read as 000000H. Reading bits 7 to 0 returns the value of register JPMC0. Address: PMCSRn: <PORTn_base> + 0900H + n × 4 (n = 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 18, 20, 21, 22, 23, 24 ) JPMCSR0: <JPORT0_base> + 0090H*1 Value after reset: 0000 0000H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PMC SRn_31 PMC SRn_30 PMC SRn_29 PMC SRn_28 PMC SRn_27 PMC SRn_26 PMC SRn_25 PMC SRn_24 PMC SRn_23 PMC SRn_22 PMC SRn_21 PMC SRn_20 PMC SRn_19 PMC SRn_18 PMC SRn_17 PMC SRn_16 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PMC SRn_15 PMC SRn_14 PMC SRn_13 PMC SRn_12 PMC SRn_11 PMC SRn_10 PMC SRn_9 PMC SRn_8 PMC SRn_7 PMC SRn_6 PMC SRn_5 PMC SRn_4 PMC SRn_3 PMC SRn_2 PMC SRn_1 PMC SRn_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2A.10, Port (General I/O) Function Overview: Table 2A.40, Control Registers (JP0), Table 2A.42, Control Registers (P0), Table 2A.44, Control Registers (P1), Table 2A.46, Control Registers (P2), Table 2A.48, Control Registers (P3), Table 2A.50, Control Registers (P8), Table 2A.52, Control Registers (P9), Table 2A.54, Control Registers (P10), Table 2A.56, Control Registers (P11), Table 2A.58, Control Registers (P12), Table 2A.60, Control Registers (P13), Table 2A.62, Control Registers (P18), Table 2A.66, Control Registers (P20), Table 2A.68, Control Registers (P21), Table 2A.70, Control Registers (P22), Table 2A.72, Control Registers (P23), and Table 2A.74, Control Registers (P24). Table 2A.17 PMCSRn Register Contents Bit Position Bit Name Function 31 to 16 PMCSRn_ [31:16] Enable bits that specify whether the value of the corresponding lower bit PMCSRn_m (PMCSRn_[15:0]) is written to PMCn_m. 0: PMCn_m is not affected by PMCSRn_m. 1: PMCn_m is PMCSRn_m. Example: If PMCSRn.PMCSRn_31 = 1, the value of bit PMCSRn.PMCSRn_15 is written to bit PMCn.PMCn_15. 15 to 0 PMCSRn_ [15:0] Data bits that specify the value of PMCn_m if PMCSRn_m of the corresponding upper bit (PMCSRn_[31:16]) is 1. 0: PMCn_m is 0. 1: PMCn_m is 1. NOTE The control bits of the JTAG port mode control set/reset register (JPMCSR0) are JPMCSR0_[31:0].

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 166 of 4535 Dec 26, 2018 2A.9.2.3 PIPCn — Port IP Control Register This register specifies whether the I/O direction of the Pn_m pin is controlled by the port mode register PMn.PMn_m or by an alternative function. If the Pn_m pin is operated in alternative mode (PMCn.PMCn_m = 1) and the alternative function requires direct control of the I/O direction, then PIPCn.PIPCn_m must be set to 1 as well. This transfers I/O control to the alternative function and overrules the PMn.PMn_m setting. Regarding the alternative functions for which the PIPC register must be set, see Section 2A.11, Port (Special I/O) Function Overview. Access: This register can be read or written in 16-bit units. Address: PIPCn: <PORTn_base> + 4200H + n × 4 (n = 0, 1, 2, 10, 11, 12, 20, 21, 22, 23)*1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PIPC n_15 PIPC n_14 PIPC n_13 PIPC n_12 PIPC n_11 PIPC n_10 PIPC n_9 PIPC n_8 PIPC n_7 PIPC n_6 PIPC n_5 PIPC n_4 PIPC n_3 PIPC n_2 PIPC n_1 PIPC n_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2A.10, Port (General I/O) Function Overview: Table 2A.42, Control Registers (P0), Table 2A.44, Control Registers (P1), Table 2A.46, Control Registers (P2), Table 2A.54, Control Registers (P10), Table 2A.56, Control Registers (P11), Table 2A.58, Control Registers (P12), Table 2A.66, Control Registers (P20), Table 2A.68, Control Registers (P21), Table 2A.70, Control Registers (P22), and Table 2A.72, Control Registers (P23). Table 2A.18 PIPCn Register Contents Bit Position Bit Name Function 15 to 0 PIPCn_[15:0] Specifies the I/O mode. 0: I/O mode is selected by PMn.PMn_m (software I/O control). 1: I/O mode is selected by the peripheral function (direct I/O control).

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 167 of 4535 Dec 26, 2018 2A.9.2.4 PMn / APMn / JPM0 — Port Mode Register This register specifies whether the individual pins of the port group n are in input mode or in output mode. Access: PMn, APMn: These registers can be read or written in 16- bit units. JPM0: This register can be read or written in 8-bit units. Address: PMn: <PORTn_base> + 0300H + n × 4 (n = 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 18, 19, 20, 21, 22, 23, 24) APMn: <PORTn_base> + 03C8H + n × 4 (n = 0, 1) JPM0: <JPORT0_base> + 0030H*1 Value after reset: FFFFH*2 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PMn_ PMn_ PMn_ PMn_ PMn_ PMn_ PMn_ PMn_ PMn_ PMn_ PMn_ PMn_ PMn_ PMn_ PMn_ PMn_ Value after reset 1 1 1 1 1 1 1 1 1 1*3 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2A.10, Port (General I/O) Function Overview: Table 2A.40, Control Registers (JP0), Table 2A.42, Control Registers (P0), Table 2A.44, Control Registers (P1), Table 2A.46, Control Registers (P2), Table 2A.48, Control Registers (P3), Table 2A.50, Control Registers (P8), Table 2A.52, Control Registers (P9), Table 2A.54, Control Registers (P10), Table 2A.56, Control Registers (P11), Table 2A.58, Control Registers (P12), Table 2A.60, Control Registers (P13), Table 2A.62, Control Registers (P18), Table 2A.64, Control Registers (P19), Table 2A.66, Control Registers (P20), Table 2A.68, Control Registers (P21), Table 2A.70, Control Registers (P22), Table 2A.72, Control Registers (P23), Table 2A.74, Control Registers (P24), Table 2A.76, Control Registers (AP0), and Table 2A.78, Control Registers (AP1). Note 2. The PM8 register is as follows. When the OPBT0.RESETOUTEN = 1, the PM8 register is FFBFH. When the OPBT0.RESETOUTEN = 0, the PM8 register is FFFFH. Note 3. The PM8_6 bit is as follows. When the OPBT0.RESETOUTEN = 1, the PM8_6 bit is 0. When the OPBT0.RESETOUTEN = 0, the PM8_6 bit is 1. Table 2A.19 PMn Register Contents Bit Position Bit Name Function 15 to 0 PMn_[15:0] Specifies input/output mode of the corresponding pin. 0: Output mode (output enabled) 1: Input mode (output disabled) NOTES 1. To use a port in input port mode (PMCn.PMCn_m = 0 and PMn.PMn_m = 1), the input buffer must be enabled (PIBCn.PIBCn_m = 1). 2. By default, PMn.PMn_m specifies the I/O direction in port mode (PMCn.PMCn_m = 0) and alternative mode (PMCn.PMCn_m=1), since PIPCn.PIPCn_m = 0 after reset. 3. The control bits of the analog port register (APMn) are APMn_[15:0]. 4. The control bits of the JTAG port mode register (JPM0) are JPM0_[7:0].

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 168 of 4535 Dec 26, 2018 2A.9.2.5 PMSRn / APMSRn / JPMSR0 — Port Mode Set/Reset Register This register provides an alternative method to write data to the PMn register. The upper 16 bits of PMSRn act as a mask which specifies whether or not the value PMn.PMn_m is set by the corresponding bit in the lower 16 bits of PMSRn. Access: PMSRn, APMSRn: These registers can be read or written in 32- bit units. Bits 31 to 16 are always read as 0000H. Reading bits 15 to 0 returns the value of registers PMn and APMn. JPMSR0: This register can be read or written in 32-bit units. Bits 31 to 16 are always read as 0000H. Bits 15 to 8 are read as FFH. Reading bits 7 to 0 returns the value of register JPM0. Address: PMSRn: <PORTn_base> + 0800H + n × 4 (n = 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 18, 19, 20, 21, 22, 23, 24 ) APMSRn: <PORTn_base> + 08C8H + n × 4 (n = 0, 1) JPMSR0: <JPORT0_base> + 0080H*1 Value after reset: 0000 FFFFH*2 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PMSR n_31 PMSR n_30 PMSR n_29 PMSR n_28 PMSR n_27 PMSR n_26 PMSR n_25 PMSR n_24 PMSR n_23 PMSR n_22 PMSR n_21 PMSR n_20 PMSR n_19 PMSR n_18 PMSR n_17 PMSR n_16 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PMSR n_15 PMSR n_14 PMSR n_13 PMSR n_12 PMSR n_11 PMSR n_10 PMSR n_9 PMSR n_8 PMSR n_7 PMSR n_6 PMSR n_5 PMSR n_4 PMSR n_3 PMSR n_2 PMSR n_1 PMSR n_0 Value after reset 1 1 1 1 1 1 1 1 1 1*3 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2A.10, Port (General I/O) Function Overview: Table 2A.40, Control Registers (JP0), Table 2A.42, Control Registers (P0), Table 2A.44, Control Registers (P1), Table 2A.46, Control Registers (P2), Table 2A.48, Control Registers (P3), Table 2A.50, Control Registers (P8), Table 2A.52, Control Registers (P9), Table 2A.54, Control Registers (P10), Table 2A.56, Control Registers (P11), Table 2A.58, Control Registers (P12), Table 2A.60, Control Registers (P13), Table 2A.62, Control Registers (P18), Table 2A.64, Control Registers (P19), Table 2A.66, Control Registers (P20), Table 2A.68, Control Registers (P21), Table 2A.70, Control Registers (P22), Table 2A.72, Control Registers (P23), Table 2A.74, Control Registers (P24), Table 2A.76, Control Registers (AP0), and Table 2A.78, Control Registers (AP1). Note 2. The PMSR8 register is as follows. When the OPBT0.RESETOUTEN = 1, the PMSR8 register is 0000 FFBFH. When the OPBT0.RESETOUTEN = 0, the PMSR8 register is 0000 FFFFH. Note 3. The PMSR8_6 bit is as follows. When the OPBT0.RESETOUTEN = 1, the PMSR8_6 bit is 0. When the OPBT0.RESETOUTEN = 0, the PMSR8_6 bit is 1. Table 2A.20 PMSRn Register Contents Bit Position Bit Name Function 31 to 16 PMSRn_[31:16] Enable bits that specify whether the value of the corresponding lower bit PMSRn_m (PMSRn_[15:0]) is written to PMn_m. 0: PMn_m is not affected by PMSRn_m. 1: PMn_m is PMSRn_m. Example: If PMSRn.PMSRn_31 = 1, the value of bit PMSRn.PMSRn_15 is written to bit PMn.PMn_15. 15 to 0 PMSRn_[15:0] Data bits that specify the value of PMn_m if PMSRn_m of the corresponding upper bit (PMSRn_[31:16]) is 1. 0: PMn_m is 0. 1: PMn_m is 1.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 169 of 4535 Dec 26, 2018 NOTES 1. The control bits of the JTAG port mode set/reset register (JPMSR0) are JPMSR0_[31:0]. 2. The control bits of the analog port mode set/reset register (APMSRn) are APMSRn_[31:0].

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 170 of 4535 Dec 26, 2018 2A.9.2.6 PIBCn / APIBCn / JPIBC0 / IPIBC0 — Port Input Buffer Control Register In input port mode (PMCn.PMCn_m = 0 and PMn.PMn_m = 1), this register enables the port pin’s input buffer. Access: PIBCn, APIBCn, IPIBC0: These registers can be read or written in 16- bit units. JPIBC0: This register can be read or written in 8-bit units. Address: PIBCn: <PORTn_base> + 4000H + n × 4 (n = 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 18, 19, 20, 21, 22, 23, 24 ) APIBCn: <PORTn_base> + 40C8H+ n × 4 (n = 0, 1) JPIBC0: <JPORT0_base> + 0400H IPIBC0: <PORTn_base> + 40F0H*1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PIBC n_15 PIBC n_14 PIBC n_13 PIBC n_12 PIBC n_11 PIBC n_10 PIBC n_9 PIBC n_8 PIBC n_7 PIBC n_6 PIBC n_5 PIBC n_4 PIBC n_3 PIBC n_2 PIBC n_1 PIBC n_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2A.10, Port (General I/O) Function Overview: Table 2A.40, Control Registers (JP0), Table 2A.42, Control Registers (P0), Table 2A.44, Control Registers (P1), Table 2A.46, Control Registers (P2), Table 2A.48, Control Registers (P3), Table 2A.50, Control Registers (P8), Table 2A.52, Control Registers (P9), Table 2A.54, Control Registers (P10), Table 2A.56, Control Registers (P11), Table 2A.58, Control Registers (P12), Table 2A.60, Control Registers (P13), Table 2A.62, Control Registers (P18), Table 2A.64, Control Registers (P19), Table 2A.66, Control Registers (P20), Table 2A.68, Control Registers (P21), Table 2A.70, Control Registers (P22), Table 2A.72, Control Registers (P23), Table 2A.74, Control Registers (P24), Table 2A.76, Control Registers (AP0), Table 2A.78, Control Registers (AP1), and Table 2A.80, Control Registers (IP0). Table 2A.21 PIBCn Register Contents Bit Position Bit Name Function 15 to 0 PIBCn_[15:0] Enables/disables the input buffer. 0: Input buffer disabled 1: Input buffer enabled NOTES 1. When the input buffer is disabled, through current does not flow even when the pin level is Hi-Z. Thus the pin does not need to be fixed to a high or low level externally. 2. The control bits of the JTAG port input buffer control register (JPIBC0) are JPIBC0_[7:0]. CAUTION Settings in this register are overruled in bidirectional mode (PBDCn.PBDCn_m = 1).

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 171 of 4535 Dec 26, 2018 2A.9.2.7 PFCn / JPFC0 — Port Function Control Register This register, together with register PFCEn and PFCAEn, specifies an alternative function of the pins. Some alternative functions directly control the I/O of the Pn_m pin. For such alternative functions, PIPCn.PIPCn_m must be set to 1 and the I/O is selected by the peripheral function. For other alternative functions, input/output must be specified by PMn.PMn_m. Access: PFCn: This register can be read or written in 16-bit units. JPFC0: This register can be read or written in 8-bit units. Address: PFCn: <PORTn_base> + 0500H + n × 4 (n = 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 18, 20, 24) JPFC0: <JPORT0_base> + 0050H*1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PFC n_15 PFC n_14 PFC n_13 PFC n_12 PFC n_11 PFC n_10 PFC n_9 PFC n_8 PFC n_7 PFC n_6 PFC n_5 PFC n_4 PFC n_3 PFC n_2 PFC n_1 PFC n_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2A.10, Port (General I/O) Function Overview: Table 2A.40, Control Registers (JP0), Table 2A.42, Control Registers (P0), Table 2A.44, Control Registers (P1), Table 2A.46, Control Registers (P2), Table 2A.48, Control Registers (P3), Table 2A.50, Control Registers (P8), Table 2A.52, Control Registers (P9), Table 2A.54, Control Registers (P10), Table 2A.56, Control Registers (P11), Table 2A.58, Control Registers (P12), Table 2A.60, Control Registers (P13), Table 2A.62, Control Registers (P18), Table 2A.66, Control Registers (P20), and Table 2A.74, Control Registers (P24). Table 2A.22 PFCn Register Contents Bit Position Bit Name Function 15 to 0 PFCn_[15:0] Specifies the alternative function of the pin. For details, see Table 2A.25, Setting Alternative Functions. NOTE The control bits of the JTAG port function control register (JPFC0) are JPFC0_[7:0].

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 172 of 4535 Dec 26, 2018 2A.9.2.8 PFCEn / JPFCE0 — Port Function Control Expansion Register This register, together with register PFCn and PFCAEn, specifies an alternative function of the pins. Some alternative functions directly control the I/O of the Pn_m pin. For such alternative functions, PIPCn.PIPCn_m must be set to 1 and the I/O is specified by the peripheral function. For other alternative functions, input/output must be specified by PMn.PMn_m. Access: PFCEn: This register can be read or written in 16-bit units. JPFCE0: This register can be read or written in 8-bit units. Address: PFCEn: <PORTn_base> + 0600H + n × 4 (n = 0, 1, 2, 8, 9, 10, 11, 12, 18, 20) JPFCE0: <JPORT0_base> + 0060H*1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PFCE n_15 PFCE n_14 PFCE n_13 PFCE n_12 PFCE n_11 PFCE n_10 PFCEn PFCEn PFCEn PFCEn PFCEn PFCEn PFCEn PFCEn PFCEn PFCEn Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The effective bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2A.10, Port (General I/O) Function Overview: Table 2A.40, Control Registers (JP0), Table 2A.42, Control Registers (P0), Table 2A.44, Control Registers (P1), Table 2A.46, Control Registers (P2), Table 2A.50, Control Registers (P8), Table 2A.52, Control Registers (P9), Table 2A.54, Control Registers (P10), Table 2A.56, Control Registers (P11), Table 2A.58, Control Registers (P12), Table 2A.62, Control Registers (P18), and Table 2A.66, Control Registers (P20). Table 2A.23 PFCEn Register Contents Bit Position Bit Name Function 15 to 0 PFCEn_[15:0] Specifies the alternative function of the pin. For details, see Table 2A.25, Setting Alternative Functions.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 173 of 4535 Dec 26, 2018 2A.9.2.9 PFCAEn — Port Function Control Additional Expansion Register This register selects the alternative peripheral functions together with PFCEn, PFCn registers. Some alternative functions directly control the I/O of the Pn_m pin. For such alternative functions, PIPCn.PIPCn_m must be set to 1 and the I/O is specified by the peripheral function. For other alternative functions, input/output must be specified by PMn.PMn_m. Access: PFCAEn: This register can be read or written in 16-bit units. Address: PFCAEn: <PORTn_base> + 0A00H + n × 4 (n = 0, 1, 2, 8, 9, 10, 11, 12, 20)*1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PFCAE n_15 PFCAE n_14 PFCAE n_13 PFCAE n_12 PFCAE n_11 PFCAE n_10 PFCAE n_9 PFCAE n_8 PFCAE n_7 PFCAE n_6 PFCAE n_5 PFCAE n_4 PFCAE n_3 PFCAE n_2 PFCAE n_1 PFCAE n_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2A.10, Port (General I/O) Function Overview: Table 2A.42, Control Registers (P0), Table 2A.44, Control Registers (P1), Table 2A.46, Control Registers (P2), Table 2A.50, Control Registers (P8), Table 2A.52, Control Registers (P9), Table 2A.54, Control Registers (P10), Table 2A.56, Control Registers (P11), Table 2A.58, Control Registers (P12), and Table 2A.66, Control Registers (P20). Table 2A.24 PFCAEn Register Contents Bit Position Bit Name Function 15 to 0 PFCAEn_[15:0] Specifies the alternative function of the pin. For details, see Table 2A.25, Setting Alternative Functions. Table 2A.25 Setting Alternative Functions PFCAEn_m PFCEn_m PFCn_m PMn_m Function 0 0 0 1 Alternative input mode 1

0 Alternative output mode 1

1 1 Alternative input mode 2

0 Alternative output mode 2

1 0 1 Alternative input mode 3

0 Alternative output mode 3

1 1 Alternative input mode 4

0 Alternative output mode 4

0 1 Alternative input mode 5

0 Alternative output mode 5

1 1 Alternative input mode 6

0 Alternative output mode 6

1 0 1 Alternative input mode 7

0 Alternative output mode 7

1 X Setting prohibited

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 174 of 4535 Dec 26, 2018 CAUTION

• After selecting the alternative function by the PFCn_m, PFCEn_m, or PFCAEn_m bit, set the PMCn_m bit to “1”.
• With this product, the I/O of some functions is assigned to two or more pins, but a specific pin function can only be set to one pin at a time. Setting the same pin function to two or more pins at the same time is prohibited. For example, if the a/b/c pin is used as b, the b/d/e pin cannot be used as b. In this case, the b/d/e pin must be configured as a pin function other than b. NOTE Control Registers.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 175 of 4535 Dec 26, 2018 2A.9.3 Pin Data Input/Output 2A.9.3.1 PBDCn / APBDCn / JPBDC0 — Port Bidirection Control Register This register enables the input buffer in output mode and sets the port to bidirectional mode. In bidirectional mode, the level of the signal on a Pn_m pin can be read from PPRn.PPRn_m. Access: PBDCn, APBDCn: These registers can be read or written in 16- bit units. JPBDC0: This register can be read or written in 8-bit units. Address: PBDCn: <PORTn_base> + 4100H + n × 4 (n = 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 18, 19, 20, 21, 22, 23, 24 ) APBDCn: <PORTn_base> + 41C8H + n × 4 (n = 0, 1) JPBDC0: <JPORT0_base> + 0410H*1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PBDC n_15 PBDC n_14 PBDC n_13 PBDC n_12 PBDC n_11 PBDC n_10 PBDC n_9 PBDC n_8 PBDC n_7 PBDC n_6 PBDC n_5 PBDC n_4 PBDC n_3 PBDC n_2 PBDC n_1 PBDC n_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2A.10, Port (General I/O) Function Overview: Table 2A.40, Control Registers (JP0), Table 2A.42, Control Registers (P0), Table 2A.44, Control Registers (P1), Table 2A.46, Control Registers (P2), Table 2A.48, Control Registers (P3), Table 2A.50, Control Registers (P8), Table 2A.52, Control Registers (P9), Table 2A.54, Control Registers (P10), Table 2A.56, Control Registers (P11), Table 2A.58, Control Registers (P12), Table 2A.60, Control Registers (P13), Table 2A.62, Control Registers (P18), Table 2A.64, Control Registers (P19), Table 2A.66, Control Registers (P20), Table 2A.68, Control Registers (P21), Table 2A.70, Control Registers (P22), Table 2A.72, Control Registers (P23), Table 2A.74, Control Registers (P24), Table 2A.76, Control Registers (AP0), and Table 2A.78, Control Registers (AP1). Table 2A.26 PBDCn Register Contents Bit Position Bit Name Function 15 to 0 PBDCn[15:0] Enables/disables bidirectional mode of the corresponding pin. 0: Bidirectional mode disabled 1: Bidirectional mode enabled CAUTION

• When the Pn_m port is used for the alternative output function (PMCn.PMCn_m = 1, PMn.PMn_m = 0), the level of the Pn_m pin can be read from PPRn.PPRn_m by enabling the bidirectional mode (PBDCn.PBDCn_m = 1).
• However, output of that alternative output function is input to the alternative input function of the same pin (the alternative input function set by PFCn.PFCn_m, PFCEn.PFCEn_m, and PFCAEn.PFCAEn_m). If the alternative input function in question is being used by another pin, the alternative input function is not guaranteed. NOTE The control bits of the JTAG port bidirection control register (JPBDC0) are JPBDC0_[7:0].

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 176 of 4535 Dec 26, 2018 2A.9.3.2 PPRn / APPRn / JPPR0 / IPPR0 — Port Pin Read Register This register reflects the actual level of the Pn_m pin, whether it is the value of the Pn.Pn_m bit or the level of an alternative output function. Access: PPRn, APPRn, IPPR0: These registers are read-only registers that can be read in 16-bit units. JPPR0: This register is a read-only register that can be read in 8-bit units. Address: PPRn: <PORTn_base> + 0200H + n × 4 (n = 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 18, 19, 20, 21, 22, 23, 24 ) APPRn: <PORTn_base> + 02C8H + n × 4 (n = 0, 1) JPPR0: <JPORT0_base> + 0020H IPPR0: <PORTn_base> + 02F0H*1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PPR n_15 PPR n_14 PPR n_13 PPR n_12 PPR n_11 PPR n_10 PPR n_9 PPR n_8 PPR n_7 PPR n_6 PPR n_5 PPR n_4 PPR n_3 PPR n_2 PPR n_1 PPR n_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R R R R R R R R R R R R R R R R Note 1. The effective bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2A.10, Port (General I/O) Function Overview: Table 2A.40, Control Registers (JP0), Table 2A.42, Control Registers (P0), Table 2A.44, Control Registers (P1), Table 2A.46, Control Registers (P2), Table 2A.48, Control Registers (P3), Table 2A.50, Control Registers (P8), Table 2A.52, Control Registers (P9), Table 2A.54, Control Registers (P10), Table 2A.56, Control Registers (P11), Table 2A.58, Control Registers (P12), Table 2A.60, Control Registers (P13), Table 2A.62, Control Registers (P18), Table 2A.64, Control Registers (P19), Table 2A.66, Control Registers (P20), Table 2A.68, Control Registers (P21), Table 2A.70, Control Registers (P22), Table 2A.72, Control Registers (P23), Table 2A.74, Control Registers (P24), Table 2A.76, Control Registers (AP0), Table 2A.78, Control Registers (AP1), and Table 2A.80, Control Registers (IP0). Table 2A.27 PPRn Register Contents Bit Position Bit Name Function 15 to 0 PPRn_[15:0] The Pn_m Pin, Pn.Pn_m value or alternative function output. NOTES 1. For the read values of the PPRn register, see Section 2A.7.4, Pin Data Input/Output. 2. The control bits of the JTAG port pin read register (JPPR0) are JPPR0_[7:0].

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 177 of 4535 Dec 26, 2018 2A.9.3.3 Pn / APn / JP0 — Port Register This register holds the Pn.Pn_m data to be output via the related Pn_m port in output port mode (PMCn.PMCn_m = 0 and PMn.PMn_m = 0). Access: Pn, APn: These registers can be read or written in 16-bit units. JP0: This register can be read or written in 8-bit units. Address: Pn: <PORTn_base> + 0000H + n × 4 (n = 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 18, 19, 20, 21, 22, 23, 24 ) APn: <PORTn_base> + 00C8H + n × 4 (n = 0, 1) JP0: <JPORT0_base> + 0000H*1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Pn_15 Pn_14 Pn_13 Pn_12 Pn_11 Pn_10 Pn_9 Pn_8 Pn_7 Pn_6 Pn_5 Pn_4 Pn_3 Pn_2 Pn_1 Pn_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2A.10, Port (General I/O) Function Overview: Table 2A.40, Control Registers (JP0), Table 2A.42, Control Registers (P0), Table 2A.44, Control Registers (P1), Table 2A.46, Control Registers (P2), Table 2A.48, Control Registers (P3), Table 2A.50, Control Registers (P8), Table 2A.52, Control Registers (P9), Table 2A.54, Control Registers (P10), Table 2A.56, Control Registers (P11), Table 2A.58, Control Registers (P12), Table 2A.60, Control Registers (P13), Table 2A.62, Control Registers (P18), Table 2A.64, Control Registers (P19), Table 2A.66, Control Registers (P20), Table 2A.68, Control Registers (P21), Table 2A.70, Control Registers (P22), Table 2A.72, Control Registers (P23), Table 2A.74, Control Registers (P24), Table 2A.76, Control Registers (AP0), and Table 2A.78, Control Registers (AP1). Table 2A.28 Pn Register Contents Bit Position Bit Name Function 15 to 0 Pn_[15:0] Sets the output level of the Pn_m pin (m = 0 to 15). 0: Outputs low level 1: Outputs high level NOTE The control bits of the JTAG port register (JP0) are JP0_[7:0].

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 178 of 4535 Dec 26, 2018 2A.9.3.4 PNOTn / APNOTn / JPNOT0 — Port NOT Register This register allows the Pn_m bit of the port register Pn to be inverted without directly writing to Pn. Access: PNOTn, APNOTn: These registers are write-only registers that can be written in 16-bit units. When read, 0000H is returned. JPNOT0: This register is a write-only register that can be written in 8-bit units. When read, 00H is returned. Address: PNOTn: <PORTn_base> + 0700H + n × 4 (n = 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 18, 19, 20, 21, 22, 23, 24 ) APNOTn: <PORTn_base> + 07C8H + n × 4 (n = 0, 1) JPNOT0: <JPORT0_base> + 0070H*1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PNOT n_15 PNOT n_14 PNOT n_13 PNOT n_12 PNOT n_11 PNOT n_10 PNOT n_9 PNOT n_8 PNOT n_7 PNOT n_6 PNOT n_5 PNOT n_4 PNOT n_3 PNOT n_2 PNOT n_1 PNOT n_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W W W W W W W W W W W W W W W W W Note 1. The effective bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2A.10, Port (General I/O) Function Overview: Table 2A.40, Control Registers (JP0), Table 2A.42, Control Registers (P0), Table 2A.44, Control Registers (P1), Table 2A.46, Control Registers (P2), Table 2A.48, Control Registers (P3), Table 2A.50, Control Registers (P8), Table 2A.52, Control Registers (P9), Table 2A.54, Control Registers (P10), Table 2A.56, Control Registers (P11), Table 2A.58, Control Registers (P12), Table 2A.60, Control Registers (P13), Table 2A.62, Control Registers (P18), Table 2A.64, Control Registers (P19), Table 2A.66, Control Registers (P20), Table 2A.68, Control Registers (P21), Table 2A.70, Control Registers (P22), Table 2A.72, Control Registers (P23), Table 2A.74, Control Registers (P24), Table 2A.76, Control Registers (AP0), and Table 2A.78, Control Registers (AP1). Table 2A.29 PNOTn Register Contents Bit Position Bit Name Function 15 to 0 PNOTn_[15:0] Specifies if Pn.Pn_m is inverted. 0: Pn.Pn_m is not inverted (Pn_m → Pn_m) 1: Pn.Pn_m is inverted ( Pn_m → Pn_m) NOTE The control bits of the JTAG port NOT register are JPNOT0_[7:0].

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 179 of 4535 Dec 26, 2018 2A.9.3.5 PSRn / APSRn / JPSR0 — Port Set/Reset Register This register provides an alternative method to write data to the Pn register. The upper 16 bits of PSRn act as a mask which specifies whether or not the value Pn.Pn_m is set by the corresponding bit in the lower 16 bits of PSRn. Access: PSRn, APSRn: These registers can be read or written in 32-bit units. Bits 31 to 16 are always read as 0000H. Reading bits 15 to 0 returns the value of registers Pn and APn. JPSR0: This register can be read or written in 32-bit units. Bits 31 to 8 are always read as 000000H. Reading bits 7 to 0 returns the value of register JP0. Address: PSRn: <PORTn_base> + 0100H + n × 4 (n = 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 18, 19, 20, 21, 22, 23, 24) APSRn: <PORTn_base> + 01C8H + n × 4 (n = 0, 1) JPSR0: <JPORT0_base> + 0010H*1 Value after reset: 0000 0000H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PSR n_31 PSR n_30 PSR n_29 PSR n_28 PSR n_27 PSR n_26 PSR n_25 PSR n_24 PSR n_23 PSR n_22 PSR n_21 PSR n_20 PSR n_19 PSR n_18 PSR n_17 PSR n_16 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSR n_15 PSR n_14 PSR n_13 PSR n_12 PSR n_11 PSR n_10 PSR n_9 PSR n_8 PSR n_7 PSR n_6 PSR n_5 PSR n_4 PSR n_3 PSR n_2 PSR n_1 PSR n_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The effective bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2A.10, Port (General I/O) Function Overview: Table 2A.40, Control Registers (JP0), Table 2A.42, Control Registers (P0), Table 2A.44, Control Registers (P1), Table 2A.46, Control Registers (P2), Table 2A.48, Control Registers (P3), Table 2A.50, Control Registers (P8), Table 2A.52, Control Registers (P9), Table 2A.54, Control Registers (P10), Table 2A.56, Control Registers (P11), Table 2A.58, Control Registers (P12), Table 2A.60, Control Registers (P13), Table 2A.62, Control Registers (P18), Table 2A.64, Control Registers (P19), Table 2A.66, Control Registers (P20), Table 2A.68, Control Registers (P21), Table 2A.70, Control Registers (P22), Table 2A.72, Control Registers (P23), Table 2A.74, Control Registers (P24), Table 2A.76, Control Registers (AP0), and Table 2A.78, Control Registers (AP1). Table 2A.30 PSRn Register Contents Bit Position Bit Name Function 31 to 16 PSRn_[31:16] Specifies whether the value of the corresponding lower bit PSRn_m (PSRn_[15:0]) is written to Pn_m. 0: Pn_m is not affected by PSRn_m 1: Pn_m is PSRn_m Example: If PSRn.PSRn_31 = 1, the value of bit PSRn.PSRn_15 is written to bit Pn.Pn_15. 15 to 0 PSRn_[15:0] Specifies the Pn_m value if the corresponding upper bit (PSRn_[31:16]) PSRn_m is 1. 0: Pn_m = 0 1: Pn_m = 1 NOTE The control bits of the JTAG port set/reset register (JPSR0) are JPSR0_[31:0].

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 180 of 4535 Dec 26, 2018 2A.9.4 Configuration of Electrical Characteristics 2A.9.4.1 PUn / JPU0 — Pull-Up Option Register This register specifies whether an internal pull-up resistor is connected to an input pin. Access: PUn: This register can be read or written in 16-bit units. JPU0: This register can be read or written in 8-bit units. Address: PUn: <PORTn_base> + 4300H + n × 4 (n = 0, 1, 2, 3, 8, 9, 10, 11,12, 13, 18, 19, 20, 21, 22, 23, 24) JPU0: <JPORT0_base> + 0430H*1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PUn_15 PUn_14 PUn_13 PUn_12 PUn_11 PUn_10 PUn_9 PUn_8 PUn_7 PUn_6 PUn_5 PUn_4 PUn_3 PUn_2 PUn_1 PUn_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2A.10, Port (General I/O) Function Overview: Table 2A.40, Control Registers (JP0), Table 2A.42, Control Registers (P0), Table 2A.44, Control Registers (P1), Table 2A.46, Control Registers (P2), Table 2A.48, Control Registers (P3), Table 2A.50, Control Registers (P8), Table 2A.52, Control Registers (P9), Table 2A.54, Control Registers (P10), Table 2A.56, Control Registers (P11), Table 2A.58, Control Registers (P12), Table 2A.60, Control Registers (P13), Table 2A.62, Control Registers (P18), Table 2A.64, Control Registers (P19), Table 2A.66, Control Registers (P20), Table 2A.68, Control Registers (P21), Table 2A.70, Control Registers (P22), Table 2A.72, Control Registers (P23), and Table 2A.74, Control Registers (P24). Table 2A.31 PUn Register Contents Bit Position Bit Name Function 15 to 0 PUn_[15:0] Specifies whether an internal pull-up resistor is connected to the corresponding pin. 0: No internal pull-up resistor connected 1: An internal pull-up resistor connected NOTES 1. If a pin is configured such that both an internal pull-up resistor (PUn.PUn_m = 1) and pull-down resistor (PDn.PDn_m = 1) are connected, the pull-down resistor is automatically selected and the pull-up resistor is not connected. 2. The pull-up resistor has no effect when the pin is operated in output mode. 3. The control bits of the JTAG pull-up option register (JPU0) are JPU0_[7:0].

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 181 of 4535 Dec 26, 2018 2A.9.4.2 PDn / JPD0 — Pull-Down Option Register This register specifies whether to connect an internal pull-down resistor to an input pin. Access: PDn: This register can be read or written in 16-bit units. JPD0: This register can be read or written in 8-bit units. Address: PDn: <PORTn_base> + 4400H + n × 4 (n = 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 18, 19, 20, 21, 22, 23, 24 ) JPD0: <JPORT0_base> + 0440H*1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PDn_15 PDn_14 PDn_13 PDn_12 PDn_11 PDn_10 PDn_9 PDn_8 PDn_7 PDn_6 PDn_5 PDn_4 PDn_3 PDn_2 PDn_1 PDn_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2A.10, Port (General I/O) Function Overview: Table 2A.40, Control Registers (JP0), Table 2A.42, Control Registers (P0), Table 2A.44, Control Registers (P1), Table 2A.46, Control Registers (P2), Table 2A.48, Control Registers (P3), Table 2A.50, Control Registers (P8), Table 2A.52, Control Registers (P9), Table 2A.54, Control Registers (P10), Table 2A.56, Control Registers (P11), Table 2A.58, Control Registers (P12), Table 2A.60, Control Registers (P13), Table 2A.62, Control Registers (P18), Table 2A.64, Control Registers (P19), Table 2A.66, Control Registers (P20), Table 2A.68, Control Registers (P21), Table 2A.70, Control Registers (P22), Table 2A.72, Control Registers (P23), and Table 2A.74, Control Registers (P24). Table 2A.32 PDn Register Contents Bit Position Bit Name Function 15 to 0 PDn_[15:0] Specifies whether to connect an internal pull-down resistor to the corresponding pin. 0: No internal pull-down resistor connected 1: An internal pull-down resistor connected NOTES 1. If a pin is configured such that both an internal pull-up resistor (PUn.PUn_m = 1) and pull-down resistor (PDn.PDn_m = 1) are connected, the pull-down resistor is automatically selected and the pull-up resistor is not connected. 2. The internal pull-down resistor has no effect when the pin is operated in output mode. 3. The control bits of the JTAG pull-down option register (JPD0) are JPD0_[7:0].

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 182 of 4535 Dec 26, 2018 2A.9.4.3 PDSCn / JPDSC0 — Port Drive Strength Control Register This register specifies the output driver strength of the port pin. This function selects the fast mode (high drive strength) or slow mode (low drive strength) of the output buffer. The correct write sequence using the PPCMDn register is required in order to update this register. For details, see Section 5, Write-Protected Registers. Regarding the alternative functions for which the PDSC register needs to be set, see Section 2A.11.3.3, Output Buffer Control (PDSC). Access: PDSCn, JPDSC0: These registers can be read or written in 32- bit units. Address: PDSCn: <PORTn_base> + 4600H + n × 4 (n = 0, 1, 2, 3, 10, 11, 12, 13, 18, 19, 20, 21, 22, 23, 24) JPDSC0: <JPORT0_base> + 0460H*1 Value after reset: 0000 0000H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R R R R R R R R R R R R R R R R Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PDSC n_15 PDSC n_14 PDSC n_13 PDSC n_12 PDSC n_11 PDSC n_10 PDSC n_9 PDSC n_8 PDSC n_7 PDSC n_6 PDSC n_5 PDSC n_4 PDSC n_3 PDSC n_2 PDSC n_1 PDSC n_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The effective bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2A.10, Port (General I/O) Function Overview: Table 2A.40, Control Registers (JP0), Table 2A.42, Control Registers (P0), Table 2A.44, Control Registers (P1), Table 2A.46, Control Registers (P2), Table 2A.48, Control Registers (P3), Table 2A.54, Control Registers (P10), Table 2A.56, Control Registers (P11), Table 2A.58, Control Registers (P12), Table 2A.60, Control Registers (P13), Table 2A.62, Control Registers (P18), Table 2A.64, Control Registers (P19), Table 2A.66, Control Registers (P20), Table 2A.68, Control Registers (P21), Table 2A.70, Control Registers (P22), Table 2A.72, Control Registers (P23), and Table 2A.74, Control Registers (P24). Table 2A.33 PDSCn Register Contents Bit Position Bit Name Function 31 to 16 Reserved When read, the value after reset is returned. When writing, write the value after reset. 15 to 0 PDSCn_[15:0] Specifies the port drive strength of the output buffer of the port pin. 0: Lower drive strength (when the frequency output from the pin is 10 MHz or below) 1: High drive strength (when the frequency output from the pin is 40 MHz or less).

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 183 of 4535 Dec 26, 2018 2A.9.4.4 PODCn / JPODC0 — Port Open Drain Control Register This register selects push-pull or open-drain as output buffer function. The correct write sequence using the PPCMDn and JPPCMD0 registers is required in order to update this register. For details, see Section 5, Write -Protected Registers. Access: PODCn, JPODC0: These registers can be read or written in 32- bit units. Address: PODCn: <PORTn_base> + 4500H + n × 4 (n = 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 18, 19, 20, 21, 22, 23, 24 ) JPODC0: <JPORT0_base> + 0450H*1 Value after reset: 0000 0000H*2 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R R R R R R R R R R R R R R R R Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PODC n_15 PODC n_14 PODC n_13 PODC n_12 PODC n_11 PODC n_10 PODC n_9 PODC n_8 PODC n_7 PODC n_6 PODC n_5 PODC n_4 PODC n_3 PODC n_2 PODC n_1 PODC n_0 Value after reset 0 0 0 0 0 0 0 0 0 0*3 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2A.10, Port (General I/O) Function Overview: Table 2A.40, Control Registers (JP0), Table 2A.42, Control Registers (P0), Table 2A.44, Control Registers (P1), Table 2A.46, Control Registers (P2), Table 2A.48, Control Registers (P3), Table 2A.50, Control Registers (P8), Table 2A.52, Control Registers (P9), Table 2A.54, Control Registers (P10), Table 2A.56, Control Registers (P11), Table 2A.58, Control Registers (P12), Table 2A.60, Control Registers (P13), Table 2A.62, Control Registers (P18), Table 2A.64, Control Registers (P19), Table 2A.66, Control Registers (P20), Table 2A.68, Control Registers (P21), Table 2A.70, Control Registers (P22), Table 2A.72, Control Registers (P23), and Table 2A.74, Control Registers (P24). Note 2. The PODC8 register is as follows. When the OPBT0.RESETOUTEN = 1, the PODC8 register is 0000 0040H. When the OPBT0.RESETOUTEN = 0, the PODC8 register is 0000 0000H. Note 3. The PODC8_6 bit is as follows. When the OPBT0.RESETOUTEN = 1, the PODC8_6 bit is 1. When the OPBT0.RESETOUTEN = 0, the PODC8_6 bit is 0. Table 2A.34 PODCn Register Contents Bit Position Bit Name Function 31 to 16 Reserved When read, the value after reset is returned. When writing, write the value after reset. 15 to 0 PODCn_[15:0] Specifies the output buffer function. 0: Push-pull 1: Open-drain NOTE The control bits of the JTAG port open drain control register (JPODC0) are JPODC0_[31:0].

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 184 of 4535 Dec 26, 2018 2A.9.4.5 PISn/JPIS0 — Port Input Buffer Selection Register This register specifies the input buffer characteristics. Access: PISn: This register can be read or written in 16-bit units. JPIS0: This register can be read or written in 8-bit units. Address: PISn: <PORTn_base> + 4700H + n × 4 (n = 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 18, 19, 20, 21, 22, 23, 24) JPIS0: <JPORT0_base> + 0470H*1 Value after reset: FFFFH Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PIS n_15 PIS n_14 PIS n_13 PIS n_12 PIS n_11 PIS n_10 PIS n_9 PIS n_8 PIS n_7 PIS n_6 PIS n_5 PIS n_4 PIS n_3 PIS n_2 PIS n_1 PIS n_0 Value after reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2A.10, Port (General I/O) Function Overview: Table 2A.40, Control Registers (JP0), Table 2A.42, Control Registers (P0), Table 2A.44, Control Registers (P1), Table 2A.46, Control Registers (P2), Table 2A.48, Control Registers (P3), Table 2A.50, Control Registers (P8), Table 2A.52, Control Registers (P9), Table 2A.54, Control Registers (P10), Table 2A.56, Control Registers (P11), Table 2A.58, Control Registers (P12), Table 2A.60, Control Registers (P13), Table 2A.62, Control Registers (P18), Table 2A.64, Control Registers (P19), Table 2A.66, Control Registers (P20), Table 2A.68, Control Registers (P21), Table 2A.70, Control Registers (P22), Table 2A.72, Control Registers (P23), and Table 2A.74, Control Registers (P24). Table 2A.35 PISn Register Contents Bit Position Bit Name Function 15 to 0 PISn_[15:0] Specifies the input buffer Characteristics: 0: Type 1 (SHMT1) 1: Type 2 (SHMT4) NOTES 1. Details of the definition of type 1 and type 2 are given in Section 2A.11.3.2, Input Buffer Control (PISn/JPIS0, PISAn/JPISA0). For details, also see Section 47A, Electrical Characteristics of RH850/F1KH-D8 for input buffer characteristics. 2. The control bits of the JTAG port input buffer selection register (JPIS0) are JPIS0_[7:0].

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 185 of 4535 Dec 26, 2018 2A.9.4.6 PISAn / JPISA0 — Port Input Buffer Selection Advanced Register This register specifies the input buffer characteristics. Access: PISAn: This register can be read or written in 16-bit units. JPISA0: This register can be read or written in 8-bit units. Address: PISAn: <PORTn_base> + 4A00H + n × 4 (n = 10, 11, 12, 13, 18, 21, 22) JPISA0: <JPORT0_base> + 04A0H*1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PISA n_15 PISA n_14 PISA n_13 PISA n_12 PISA n_11 PISA n_10 PISA n_9 PISA n_8 PISA n_7 PISA n_6 PISA n_5 PISA n_4 PISA n_3 PISA n_2 PISA n_1 PISA n_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The effective bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2A.10, Port (General I/O) Function Overview: Table 2A.40, Control Registers (JP0), Table 2A.42, Control Registers (P0), Table 2A.54, Control Registers (P10), Table 2A.56, Control Registers (P11), Table 2A.58, Control Registers (P12), Table 2A.60, Control Registers (P13), Table 2A.62, Control Registers (P18), Table 2A.68, Control Registers (P21), and Table 2A.70, Control Registers (P22). Table 2A.36 PISAn Register Contents Bit Position Bit Name Function 15 to 0 PISA_[15:0] Specifies the input buffer characteristics: 0: Type 2 (SHMT4) 1: Type 5 (TTL) Table 2A.37 Port Input Selection Advanced Register Contents PISAn PISn Function 0 0 Type 1 input buffer is selected (SHMT1)

1 Type 2 input buffer is selected (SHMT4)

1 X Type 5 input buffer is selected (TTL)

Details of the definition of type 2 and type 5 are given in Section 2A.11.3.2, Input Buffer Control (PISn/JPIS0, PISAn/JPISA0). For details, also see Section 47A, Electrical Characteristics of RH850/F1KH-D8 for input buffer characteristics.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 186 of 4535 Dec 26, 2018 2A.9.5 Port Register Protection RH850/F1KH has Port Protection Command Register (PPCMDn) and Port Protection Status Register (PPROTSn) which implement the Port Protection Cluster Function. For details on the registers, see Section 5 , Write-Protected Registers. 2A.9.6 Flowchart Examples for Port Settings Examples of the port settings are shown in the flowchart below. CAUTION If the port is set to the PIPCn.PIPCn_m = 0 and alternative output mode, the port might briefly enter alternative input mode. This will occur between when the PMCn.PMCn_m bit is set to 1 and when the PMn.PMn_m bit is set to 0. If an interrupt-related signal is specified as an alternate function of the port, the mode will temporarily become the alternative input mode, so either disable the interrupt in question, or specify that the interrupt is ignored.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 187 of 4535 Dec 26, 2018 2A.9.6.1 Batch Setting An example of specifying batch port settings is shown in the flowchart below. Specify PIBCn.PIBCn_m bit = 0 Specify PBDCn.PBDCn_m bit = 0 Specify PMn.PMn_m bit = 1 Specify PMCn.PMCn_m bit = 0 Specify PIPCn.PIPCn_m bit = 0 Specify PIPCn.PIPCn_m bit Specify Pn.Pn_m bit Specify PMCn.PMCn_m bit Specify PMn.PMn_m bit Specify PIBCn.PIBCn_m bit Specify PFCn.PFCn_m, PFCEn.PFCEn_m, PFCAEn.PFCAEn_m bits Set port filters*1 Specify PDSCn.PDSCn_m, PODCn.PODCn_m, PBDCn.PBDCn_m, PUn.PUn_m, PDn.PDn_m, PISn.PISn_m bits PISAn.PISAn_m bits Port initialization: Set the initial port values. (The port is set to input mode and the input buffer is disabled.) Port settings: Set appropriate values. Alternative input mode is entered when the PIPCn.PIPCn_m bit is 0 and the PMCn.PMCn_m bit is 1. START Note 1. While PMC = 0, an interrupt may be triggered during the configuration of the port registers under the following conditions: For NMI, INTP7 and INTP8 interrupt requests:

• The port filter is set to low level detection.
• The port filter is set to rising edge or both edge detection and the PMC register is set to 1 while the input terminal is at high level. For INTP0-6 and INTP9-23 interrupt requests:
• The port filter is set to high level detection.
• The port filter is set to falling edge or both edges detection and the PMC register is set to 1 while the input terminal is at low level. In order to avoid the unintended interrupt occurrence, use the following configuration sequence: 1. Configure the PMC register. 2. Wait for the period of pulse rejection. 3. Configure the edge/level detection register. Figure 2A.6 Example of Port Settings (When Specified in Batch)

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 188 of 4535 Dec 26, 2018 2A.9.6.2 Individual Settings An example of specifying individual port settings is shown in the flowchart below. Specify PIBCn.PIBCn_m bit = 0 Specify PBDCn.PBDCn_m bit = 0 Specify PMn.PMn_m bit = 1 Specify PMCn.PMCn_m bit = 0 Specify PIPCn.PIPCn_m bit = 0 Specify PIBCn.PIBCn_m bit = 1 Specify Pn.Pn_m bit Specify PUn.PUn_m, PDn.PDn_m bits Set port filters Specify PDSCn.PDSCn_m, PODCn.PODCn_m, PBDCn.PBDCn_m bits Output mode Input mode Input or output? Specify PISn.PISn_m bits PISAn.PISAn_m bits Specify PMn.PMn_m bit = 0 Port initialization: Set the initial port values. (The port is set to input mode and the input buffer is disabled.) Port settings: Set appropriate values. START Figure 2A.7 Example of Port Settings (in Port Mode)

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 189 of 4535 Dec 26, 2018 (1) With IP Control Specify PIBCn.PIBCn_m bit = 0 Specify PBDCn.PBDCn_m bit = 0 Specify PMn.PMn_m bit = 1 Specify PMCn.PMCn_m bit = 0 Specify PIPCn.PIPCn_m bit = 0 Specify PIPCn.PIPCn_m bit = 1 Specify PMCn.PMCn_m bit = 1 Specify PISn.PISn_m bits PISAn.PISAn_m bits Set port filters Specify PUn.PUn_m, PDn.PDn_m bits Input function port settings: Set appropriate values. Alternative mode (with IP control) port settings: Set appropriate values. Output function port settings: Set appropriate values. Specify PFCn.PFCn_m, PFCEn.PFCEn_m, PFCAEn.PFCAEn_m bits Specify PDSCn.PDSCn_m, PODCn.PODCn_m, PBDCn.PBDCn_m bits Port initialization: Set the initial port values. (The port is set to input mode and the input buffer is disabled.) START Figure 2A.8 Example of Port Settings (in Alternative Mode)

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 190 of 4535 Dec 26, 2018 (2) Without IP Control Specify PIBCn.PIBCn_m bit = 0 Specify PBDCn.PBDCn_m bit = 0 Specify PMn.PMn_m bit = 1 Specify PMCn.PMCn_m bit = 0 Specify PIPCn.PIPCn_m bit = 0 Specify PUn.PUn_m, PDn.PDn_m bits Specify PFCn.PFCn_m, PFCEn.PFCEn_m, PFCAEn.PFCAEn_m bits Specify PDSCn.PDSCn_m, PODCn.PODCn_m, PBDCn.PBDCn_m bits Specify PISn.PISn_m bit PISAn.PISAn_m bits Specify PMn.PMn_m bit = 0Specify PMCn.PMCn_m bit = 1 Specify PFCn.PFCn_m, PFCEn.PFCEn_m, PFCAEn.PFCAEn_m bits Specify PMCn.PMCn_m bit = 1 Alternative input mode Set port filters*1 Output mode Input mode Input or output? Port initialization: Set the initial port values. (The port is set to input mode and the input buffer is disabled.) Port settings: Set appropriate values. START Note 1. While PMC = 0, an interrupt may be triggered during the configuration of the port registers under the following conditions: For NMI, INTP7 and INTP8 interrupt requests:

• The port filter is set to low level detection.
• The port filter is set to rising edge or both edge detection and the PMC register is set to 1 while the input terminal is at high level. For INTP0-6 and INTP9-23 interrupt requests:
• The port filter is set to high level detection.
• The port filter is set to falling edge or both edges detection and the PMC register is set to 1 while the input terminal is at low level. In order to avoid the unintended interrupt occurrence, use the following configuration sequence: 1. Configure the PMC register. 2. Wait for the period of pulse rejection. 3. Configure the edge/level detection register. Figure 2A.9 Example of Port Settings (in Alternative Mode)

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 191 of 4535 Dec 26, 2018 2A.10 Port (General I/O) Function Overview This section explains the port (general I/O) functions and all the functions assigned to the ports. See the following pages for details. In addition, whether the port mode is alternative mode or not can be selected by PMCn register setting. When PMCn.PMCn_m = 1, alternative functions are selected by the PFCn, PFCEn, and PFCAEn registers. Table 2A.38 Port Function Port Pin Name Size Direction Power Domain Special Alternative Function Device

176 Pins 233 Pins 272 Pins 324 Pins

JTAG Port 0 JP0_0 - 6 7 bits In/Out AWO JTAG, LPD   —  Port 0 P0_0 - 14 15 bits In/Out AWO   —  Port 1 P1_0 - 5, 8-15 14 bits In/Out AWO   —  Port 2 P2_0 - 6 7 bits In/Out AWO  — — — P2_0 - 15 16 bits —  —  Port 3 P3_0 1 bit In/Out AWO —  — — Port 8 P8_0 - 12 13 bits In/Out AWO ADCA0 (10-bit resolution) RESETOUT   —  Port 9 P9_0 - 4 5 bits In/Out ISO ADCA0 (10-bit resolution)   —  Port 10 P10_0 - 15 16 bits In/Out ISO   —  Port 11 P11_0 – 12, 15 14 bits In/Out ISO   —  Port 12 P12_0 - 5 6 bits In/Out ISO   —  Port 13 P13_0 - 7 8 bits In/Out ISO —  —  Port 18 P18_0 - 7 8 bits In/Out ISO ADCA1 (10-bit resolution)  — — — P18_0 - 15 16 bits —  —  Port 19 P19_0 - 3 4 bits In/Out ISO ADCA1 (10-bit resolution) —  —  Port 20 P20_0 - 5 6 bits In/Out ISO   — — P20_0 - 14 15 bits — — — — P20_0 - 15 16 bits — — —  Port 21 P21_0 – 4 5 bits In/Out ISO — — — — Port 22 P22_0 - 15 16 bits In/Out ISO — — —  Port 23 P23_0 - 10 11 bits In/Out ISO — — —  Port 24 P24_0 - 7 8 bits In/Out ISO — — —  Analog Port 0 AP0_0 - 15 16 bits In/Out AWO ADCA0 (12/10-bit resolution)   —  Analog Port 1 AP1_0 - 15 16 bits In/Out ISO ADCA1 (12/10-bit resolution)   —  Input Port 0 IP0_0 1 bit In AWO SOSC (XT2 pin)   — 

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 192 of 4535 Dec 26, 2018 2A.10.1 JTAG Port 0 (JP0) 2A.10.1.1 Alternative Function The following alternative functions are available when JTAG port 0 is configured as a general -purpose I/O port by setting OPJTAG[1:0] on the corresponding option byte to 00B. Table 2A.39 JTAG Port 0 (JP0) Port Mode (JPMC0_m = 0) Alternative Mode (JPMC0_m = 1) ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 176 Pins 233 Pins 272 Pins 324 Pins Input Output Input Output Input Output Input Output Input Output JP0_0*1 INTP0 TAUJ2I0 TAUJ2O0 FPDR FPDT DCUTDI/LPDI/LPDIO 47 U4 — AB4 JP0_1 INTP1 TAUJ0I0 TAUJ0O0 FPDT DCUTDO/LPDO 46 P5 — W6 JP0_2 INTP2 TAUJ0I1 TAUJ0O1 FPCK DCUTCK/LPDCLK 45 T4 — W5 JP0_3 INTP3 CSCXFOUT TAUJ0I2 TAUJ0O2 DCUTMS 44 R4 — Y5 JP0_4 DCUTRST 43 R3 — AB3 JP0_5 NMI RTCA0OUT TAUJ0I3 TAUJ0O3 DCURDY /LPDCLKOUT 42 U3 — AA4 JP0_6 EVTO 66 U11 — Y10 Note 1. In LPD (1 pin) mode, the JP0_0 output buffer state is Open-drain. CAUTION The behavior and performance are not guaranteed when alternative functions are not assigned to the register.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 193 of 4535 Dec 26, 2018 2A.10.1.2 Control Registers Table 2A.40 Control Registers (JP0) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 176 Pins 233 Pins 272 Pins 324 Pins JP0 JTAG port register 0 8 6-0 R/W 0000H 00H   —  JPSR0 JTAG port set/reset register 0 32 22-16, 6-0 R/W 0010H 0000 0000H   —  JPPR0 JTAG port pin read register 0 8 6-0 R 0020H 00H   —  JPM0 JTAG port mode register 0 8 6-0 R/W 0030H FFH   —  JPMC0 JTAG port mode control register 0 8 5, 3-0 R/W 0040H 00H   —  JPFC0 JTAG port function control register 0 8 5, 3-0 R/W 0050H 00H   —  JPFCE0 JTAG port function control expansion register 0 8 2-0 R/W 0060H 00H   —  JPNOT0 JTAG port NOT register 0 8 6-0 W 0070H 00H   —  JPMSR0 JTAG port mode set/reset register 0 32 22-16, 6-0 R/W 0080H 0000 FFFFH   —  JPMCSR0 JTAG port mode control set/reset register 0 32 21, 19-16, 5, 3-0 R/W 0090H 0000 0000H   —  JPIBC0 JTAG port input buffer control register 0 8 6-0 R/W 0400H 00H   —  JPBDC0 JTAG port bidirection control register 0 8 6-0 R/W 0410H 00H   —  JPU0 Pull-up option register 0 8 6-0 R/W 0430H 00H   —  JPD0 Pull-down option register 0 8 6-0 R/W 0440H 00H   —  JPODC0 JTAG port open drain control register 0 32 6-0 R/W 0450H 0000 0000H   —  JPDSC0 JTAG port drive strength control register 0 32 6, 5, 3-1 R/W 0460H 0000 0000H   —  JPIS0 JTAG port input buffer selection register 0 8 6, 5, 3-0 R/W 0470H FFH   —  JPISA0 JTAG port input buffer selection advanced register 0 8 3, 2, 0 R/W 04A0H 00H   —  JPPROTS0 JTAG port protection status register 0 32 0 R 04B0H 0000 0000H   —  JPPCMD0 JTAG port protection command register 0 32 7-0 W 04C0H xxxx xx00H   —  Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 194 of 4535 Dec 26, 2018 2A.10.2 Port 0 (P0) 2A.10.2.1 Alternative Function Table 2A.41 Port 0 (P0) Port Mode (PMC0_m = 0) Alternative Mode (PMC0_m =1) ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 176 Pins 233 Pins 272 Pins 324 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output P0_0 TAUD0I2 TAUD0O2 RLIN20RX CAN0TX PWGA10O CSIH0SSI DPO TAUJ2I1 TAUJ2O1 18 J1 — T1 P0_1 TAUD0I4 TAUD0O4 CAN0RX/ INTP0 RLIN20TX INTP0 PWGA11O CSIH0SI APO TAUJ2I2 TAUJ2O2 CAN0RX 19 J2 — P3 P0_2 TAUD0I6 TAUD0O6 CAN1RX/ INTP1 RLIN30TX PWGA12O CSIH0SC INTP1 DPO TAUJ2I3 TAUJ2O3 CAN1RX 20 J4 — P4 P0_3 TAUD0I8 TAUD0O8 RLIN30RX/ INTP10 CAN1TX DPIN1 PWGA13O CSIH0SO INTP10 TAUJ1I0 TAUJ1O0 RLIN30RX 21 K1 — R2 P0_4 RLIN31RX/ INTP11 CAN2TX INTP11 PWGA10O CSIH1SI SELDP0 DPIN8 TAUB0I1 TAUB0O RLIN31RX 23 K3 — R4 P0_5 CAN2RX/ INTP2 RLIN31TX DPIN9 SELDP1 CSIH1SO TAUB0I1 TAUB0O CAN2RX 24 K2 — U1 P0_6 INTP2 DPIN10 SELDP2 CSIH1SC PWGA35 O

25 L3 — R3

P0_7 RLIN21RX DPIN5 CSCXFOUT CSIH1RYI CSIH1RYO TAUB0I0 TAUB0O0 CAN3RX/ INTP3 CAN3RX 70 R11 — Y12 P0_8 INTP16 RLIN21TX DPIN6 CSIH0CSS6 CSIH1SSI TAUB0I2 TAUB0O2 CAN3TX 69 T12 — Y11 P0_9 INTP12 CSIH1CSS0 DPIN7 RLIN22RX TAUB0I4 TAUB0O4 CAN4RX/ INTP4 CAN4RX 68 R10 — W11 P0_10 INTP3 CSIH1CSS1 DPIN11 RLIN22TX TAUB0I6 TAUB0O6 CAN4TX 67 T11 — AB12 P0_11 RIIC0SDA DPIN12 CSIH1CSS2 TAUB0I8 TAUB0O8 RLIN26RX PWGA34O 26 L1 — T2 P0_12 RIIC0SCL DPIN13 PWGA45O TAUB0I10 TAUB0O10 CSIG0SI RLIN26TX 27 L2 — U2 P0_13 RLIN32RX/ INTP12 INTP12 PWGA46O TAUB0I12 TAUB0O12 CSIG0SO CAN5RX/ INTP5 RLIN32RX CAN5RX 28 M1 — T3 P0_14 INTP17 RLIN32TX PWGA47O TAUB0I14 TAUB0O14 CSIG0SC CAN5TX 29 L4 — U3 CAUTION The behavior and performance are not guaranteed when undocumented alternative functions are selected.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 195 of 4535 Dec 26, 2018 2A.10.2.2 Control Registers Table 2A.42 Control Registers (P0) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 176 Pins 233 Pins 272 Pins 324 Pins P0 Port register 0 16 14-0 R/W 0000H 0000H   —  PSR0 Port set/reset register 0 32 30-16, 14-0 R/W 0100H 0000 0000H   —  PPR0 Port pin read register 0 16 14-0 R 0200H 0000H   —  PM0 Port mode register 0 16 14-0 R/W 0300H FFFFH   —  PMC0 Port mode control register 0 16 14-0 R/W 0400H 0000H   —  PFC0 Port function control register 0 16 14-0 R/W 0500H 0000H   —  PFCE0 Port function control expansion register 0 16 14-0 R/W 0600H 0000H   —  PNOT0 Port NOT register 0 16 14-0 W 0700H 0000H   —  PMSR0 Port mode set/reset register 0 32 30-16, 14-0 R/W 0800H 0000 FFFFH   —  PMCSR0 Port mode control set/reset register 0 32 30-16, 14-0 R/W 0900H 0000 0000H   —  PFCAE0 Port function control additional expansion register 0 16 14, 13, 10-0 R/W 0A00H 0000H   —  PIBC0 Port input buffer control register 0 16 14-0 R/W 4000H 0000H   —  PBDC0 Port bidirection control register 0 16 14-0 R/W 4100H 0000H   —  PIPC0 Port IP control register 0 16 14, 13, 6, 5, 3, R/W 4200H 0000H   —  PU0 Pull-up option register 0 16 14-0 R/W 4300H 0000H   —  PD0 Pull-down option register 0 16 14-0 R/W 4400H 0000H   —  PODC0 Port open drain control register 0 32 14-0 R/W 4500H 0000 0000H   —  PDSC0 Port drive strength control register 0 32 14-0 R/W 4600H 0000 0000H   —  PIS0 Port input buffer selection register 0 16 14-0 R/W 4700H FFFFH   —  PPROTS0 Port protection status register 0 32 0 R 4B00H 0000 0000H   —  PPCMD0 Port protection command register 0 32 7-0 W 4C00H XXXX XX00H   —  Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 196 of 4535 Dec 26, 2018 2A.10.3 Port 1 (P1) 2A.10.3.1 Alternative Function Table 2A.43 Port 1 (P1) Port Mode (PMC1_m = 0) Alternative Mode (PMC1_m = 1) ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 176 Pins 233 Pins 272 Pins 324 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output P1_0 RLIN33RX/ INTP13 INTP13 TAUJ2I0 TAUJ2O0 CSIG4SSI RLIN33RX 30 M2 — V1 P1_1 INTP18 RLIN33TX CSIG4SC TAUJ2I1 TAUJ2O1 31 N2 — U4 P1_2 CAN3RX/ INTP3 INTP3 DPIN19 TAUJ2I2 TAUJ2O2 CSIG4SI CAN3RX 32 N1 — W1 P1_3 INTP19 CAN3TX DPIN23 CSIG4SO TAUJ2I3 TAUJ2O3 33 N3 — V3 P1_4 RLIN35RX/ INTP15 INTP15 DPIN18 CSIH4SI RLIN35RX 75 U13 — AA13 P1_5 ADCA1TR RLIN35TX DPIN17 INTP20 CSIH4SC 74 U12 — AA12 P1_8 53 U5 — AB6 P1_9 DPIN20 INTP21 52 R7 — W7 P1_10 RLIN24RX DPIN21 INTP22 ADCA1TR

51 R6 — AB5

P1_11 ADCA1TR RLIN24TX DPIN22 INTP14 50 P6 — AA6 P1_12 CAN4RX/ INTP4 INTP4 RLIN36TX CAN4RX 34 P1 — V2 P1_13 CAN4TX RLIN36RX/ INTP16 RLIN36RX 35 P2 — V4 P1_14 RLIN23RX CAN7RX/ INTP9 CSIH4RYI CSIH4RYO CAN7RX 78 U14 — Y13 P1_15 RLIN23TX CAN7TX 79 R13 — W14 CAUTION The behavior and performance are not guaranteed when undocumented alternative functions are selected.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 197 of 4535 Dec 26, 2018 2A.10.3.2 Control Registers Table 2A.44 Control Registers (P1) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 176 Pins 233 Pins 272 Pins 324 Pins P1 Port register 1 16 15-8, 5-0 R/W 0004H 0000H   —  PSR1 Port set/reset register 1 32 31-24, 21-16, 15-8, 5-0 R/W 0104H 0000 0000H   —  PPR1 Port pin read register 1 16 15-8, 5-0 R 0204H 0000H   —  PM1 Port mode register 1 16 15-8, 5-0 R/W 0304H FFFFH   —  PMC1 Port mode control register 1 16 15-9, 5-0 R/W 0404H 0000H   —  PFC1 Port function control register 1 16 15-9, 5-0 R/W 0504H 0000H   —  PFCE1 Port function control expansion register 16 14-9, 5-0 R/W 0604H 0000H   —  PNOT1 Port NOT register 1 16 15-8, 5-0 W 0704H 0000H   —  PMSR1 Port mode set/reset register 1 32 31-24, 21-16, 15-8, 5-0 R/W 0804H 0000 FFFFH   —  PMCSR1 Port mode control set/reset register 1 32 31-25, 21-16, 15-9, 5-0 R/W 0904H 0000 0000H   —  PFCAE1 Port function control additional expansion register 1 16 14-12, 4, 2, 0 R/W 0A04 H 0000H   —  PIBC1 Port input buffer control register 1 16 15-8, 5-0 R/W 4004H 0000H   —  PBDC1 Port bidirection control register 1 16 15-8, 5-0 R/W 4104H 0000H   —  PIPC1 Port IP control register 1 16 5,3,1 R/W 4204H 0000H   —  PU1 Pull-up option register 1 16 15-8, 5-0 R/W 4304H 0000H   —  PD1 Pull-down option register 1 16 15-8, 5-0 R/W 4404H 0000H   —  PODC1 Port open drain control register 1 32 15-8, 5-0 R/W 4504H 0000 0000H   —  PDSC1 Port drive strength control register 1 32 15-8, 5-0 R/W 4604H 0000 0000H   —  PIS1 Port input buffer selection register 1 16 15-8, 5-0 R/W 4704H FFFFH   —  PPROTS1 Port protection status register 1 32 0 R 4B04H 0000 0000H   —  PPCMD1 Port protection command register 1 32 7-0 W 4C04H xxxx xx00H   —  Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 198 of 4535 Dec 26, 2018 2A.10.4 Port 2 (P2) 2A.10.4.1 Alternative Function Table 2A.45 Port 2 (P2) Port Mode (PMC2_m =0) Alternative Mode (PMC2_m =1) ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 176 Pins 233 Pins 272 Pins 324 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output P2_0 RLIN27RX CAN6RX/ INTP6 CAN6RX 49 T5 — AA5 P2_1 RLIN27TX CAN6TX 48 R5 — Y6 P2_2 RLIN28RX CSIH4CSS0 65 T10 — AA11 P2_3 RLIN28TX CSIH4CSS1 64 U10 — AA10 P2_4 RLIN29RX ADCA0SEL0 CSIH4SO 76 T13 — AB13 P2_5 RLIN29TX CSIH4SSI ADCA0SEL1 77 R12 — AB14 P2_6 ADCA0SEL2 CSIG4RYI CSIG4RYO 36 R1 — Y1 P2_7 RLIN210RX — M4 — W2 P2_8 RLIN210TX — T1 — W3 P2_9 PWGA77O — M3 — Y3 P2_10 PWGA78O — R2 — AA1 P2_11 PWGA79O — N4 — W4 P2_12 RLIN211RX — T2 — Y2 P2_13 RLIN211TX — P7 — Y7 P2_14 PWGA74O — T6 — AA7 P2_15 PWGA75O — P8 — AA9 CAUTION The behavior and performance are not guaranteed when undocumented alternative functions are selected.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 199 of 4535 Dec 26, 2018 2A.10.4.2 Control Registers Table 2A.46 Control Registers (P2) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 176 Pins 233 Pins 272 Pins 324 Pins P2 Port register 2 16 6-0 R/W 0008H 0000H  — — — 15-0 —  —  PSR2 Port set/reset register 2 32 22-16, 6-0 R/W 0108H 0000 0000H  — — — PPR2 Port pin read register 2 16 6-0 R 0208H 0000H  — — — 15-0 —  —  PM2 Port mode register 2 16 6-0 R/W 0308H FFFFH  — — — 15-0 —  —  PMC2 Port mode control register 2 16 6-0 R/W 0408H 0000H  — — — 15-0 —  —  PFC2 Port function control register 2 16 6-3, 1, 0 R/W 0508H 0000H   —  PFCE2 Port function control expansion register 2 16 4, 0 R/W 0608H 0000H   —  PNOT2 Port NOT register 2 16 6-0 W 0708H 0000H  — — — 15-0 —  —  PMSR2 Port mode set/reset register 2 32 22-16, 6-0 R/W 0808H 0000 FFFFH  — — — PMCSR2 Port mode control set/reset register 2 32 22-16, 6-0 R/W 0908H 0000 0000H  — — — PFCAE2 Port function control additional expansion register 2 16 0 R/W 0A08H 0000H   —  PIBC2 Port input buffer control register 2 16 6-0 R/W 4008H 0000H  — — — 15-0 —  —  PBDC2 Port bidirection control register 2 16 6-0 R/W 4108H 0000H  — — — 15-0 —  —  PIPC2 Port IP control register 2 16 4 R/W 4208H 0000H   —  PU2 Pull-up option register 2 16 6-0 R/W 4308H 0000H  — — — 15-0 —  —  PD2 Pull-down option register 2 16 6-0 R/W 4408H 0000H  — — — 15-0 —  —  PODC2 Port open drain control register 2 32 6-0 R/W 4508H 0000 0000H  — — — 15-0 —  —  PDSC2 Port drive strength control register 2 32 6-0 R/W 4608H 0000 0000H  — — — 15-0 —  —  PIS2 Port input buffer selection register 2 16 6-0 R/W 4708H FFFFH  — — — 15-0 —  —  PPROTS2 Port protection status register 2 32 0 R 4B08H 0000 0000H   —  PPCMD2 Port protection command register 2 32 7-0 W 4C08H xxxx xx00H   —  Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 200 of 4535 Dec 26, 2018 2A.10.5 Port 3 (P3) 2A.10.5.1 Alternative Function Table 2A.47 Port 3 (P3) Port Mode (PMC3_m =0) Alternative Mode (PMC3_m =1) ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 176 Pins 233 Pins 272 Pins 324 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output P3_0 PWGA76O — R8 — Y8 P3_1 PWGA80O — — — Y16 P3_2 PWGA81O — — — AB16 P3_3 CAN8RX/ INTP18 PWGA82O CAN8RX — — — Y17 P3_4 PWGA83O CAN8TX — — — AA19 P3_5 CAN9RX/ INTP19 PWGA84O CAN9RX — — — AB20 P3_6 PWGA85O CAN9TX — — — Y18 P3_7 CAN10RX/ INTP20 PWGA86O CAN10RX — — — W17 P3_8 PWGA87O CAN10TX — — — AA20 P3_9 CAN11RX/ INTP21 CAN11RX — — — Y19 P3_10 CAN11TX — — — W18 P3_11 CSIH4CSS0 — — — AB17 P3_12 CSIH4CSS1 — — — AA17 CAUTION The behavior and performance are not guaranteed when undocumented alternative functions are selected.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 201 of 4535 Dec 26, 2018 2A.10.5.2 Control Registers Table 2A.48 Control Registers (P3) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 176 Pins 233 Pins 272 Pins 324 Pins P3 Port register 3 16 0 R/W 000CH 0000H —  — — 10-0 — — — — 12-0 — — —  PSR3 Port set/reset register 3 32 16, 0 R/W 010CH 0000 0000H —  — — PPR3 Port pin read register 3 16 0 R 020CH 0000H —  — — 10-0 — — — — 12-0 — — —  PM3 Port mode register 3 16 0 R/W 030CH FFFFH —  — — 10-0 — — — — 12-0 — — —  PMC3 Port mode control register 3 16 0 R/W 040CH 0000H —  — — 10-0 — — — — 12-0 — — —  PFC3 Port function control register 3 16 9-3 R/W 050CH 0000H — — —  PNOT3 Port NOT register 3 16 0 W 070CH 0000H —  — — 10-0 — — — — 12-0 — — —  PMSR3 Port mode set/reset register 3 32 16, 0 R/W 080CH 0000 FFFFH —  — — PMCSR3 Port mode control set/reset register 3 32 16, 0 R/W 090CH 0000 0000H —  — — PIBC3 Port input buffer control register 3 16 0 R/W 400CH 0000H —  — — 10-0 — — — — 12-0 — — —  PBDC3 Port bidirection control register 3 16 0 R/W 410CH 0000H —  — — 10-0 — — — — 12-0 — — —  PU3 Pull-up option register 3 16 0 R/W 430CH 0000H —  — — 10-0 — — — — 12-0 — — —  PD3 Pull-down option register 3 16 0 R/W 440CH 0000H —  — — 10-0 — — — — 12-0 — — —  PODC3 Port open drain control register 3 32 0 R/W 450CH 0000 0000H —  — — 10-0 — — — — 12-0 — — —  PDSC3 Port drive strength control register 3 32 0 R/W 460CH 0000 0000H —  — — 10-0 — — — — 12-0 — — —  PIS3 Port input buffer selection register 3 16 0 R/W 470CH FFFFH —  — — 10-0 — — — — 12-0 — — —  PPROTS3 Port protection status register 3 32 0 R 4B0CH 0000 0000H —  —  PPCMD3 Port protection command register 3 32 7-0 W 4C0CH 0000 0000H —  — 

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 202 of 4535 Dec 26, 2018 Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 203 of 4535 Dec 26, 2018 2A.10.6 Port 8 (P8) 2A.10.6.1 Alternative Function Table 2A.49 Port 8 (P8) Port Mode (PMC8_m = 0) Alternative Mode (PMC8_m = 1) ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 176 Pins 233 Pins 272 Pins 324 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output P8_0 TAUJ0I0 TAUJ0O0 DPIN2 PWGA14O INTP4 CSIH0CSS0 CAN6RX/ INTP6 RIIC1SDA SENT0RX CAN6RX ADCA0I0S 80 U15 — AA14 P8_1 TAPA0ESO TAUJ0O1 DPIN0 PWGA15O INTP5 CSIH1CSS3 CAN6TX RIIC1SCL SENT0SP CO ADCA0I1S 81 T14 — Y14 P8_2 TAUJ0I0 TAUJ0O0 DPIN2 CSIH0CSS0 INTP6 PWGA22O RLIN37TX ADCA0I4S 38 U2 — AA2 P8_3 TAUJ0I1 TAUJ0O1 DPIN3 CSIH0CSS1 INTP7 PWGA23O CAN7TX ADCA0I5S 82 U16 — AB15 P8_4 TAUJ0I2 TAUJ0O2 DPIN4 CSIH0CSS2 INTP8 PWGA36O CAN7RX/ INTP9 CAN7RX ADCA0I6S 83 R14 — AA15 P8_5 TAUJ0I3 TAUJ0O3 NMI CSIH0CSS3 INTP9 PWGA37O ADCA0I7S 84 T15 — Y15 P8_6 NMI CSIH0CSS4 PWGA38O RTCA0OUT ADCA0I8S RESETOUT 85 P13 — AB18 P8_7 CSIH3CSS0 PWGA39O ADCA0SEL0 RTCA0OUT ADCA0I14S 86 R15 — AA16 P8_8 CSIH3CSS1 PWGA40O ADCA0SEL1 RLIN34RX/ INTP14 RLIN34RX ADCA0I15S 87 P14 — AA18 P8_9 CSIH3CSS2 PWGA41O ADCA0SEL2 RLIN34TX ADCA0I16S 88 T16 — AB19 P8_10 CSIH3CSS3 DPIN14 PWGA42O RLIN37RX/ INTP17 RLIN37RX ADCA0I17S 39 P3 — AA3 P8_11 TAUJ1I2 TAUJ1O2 DPIN15 PWGA43O CSIH1CSS4 RLIN25RX ADCA0I18S 40 T3 — AB2 P8_12 TAUJ1I3 TAUJ1O3 DPIN16 PWGA44O CSIH1CSS5 INTP23 RLIN25TX ADCA0I19S 41 P4 — Y4 CAUTIONS 1. The behavior and performance are not guaranteed when undocumented alternative functions are selected. 2. Use ADC functions with their initial settings. For details, see Table 2A.50, Control Registers (P8). 3. When the RESETOUT function is selected for the P8_6 pin, the output on the pin is at the low level during a reset and after release from the reset state. For details, see Section 2A.11.1.1, P8_6: RESETOUT .

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 204 of 4535 Dec 26, 2018 2A.10.6.2 Control Registers Table 2A.50 Control Registers (P8) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 176 Pins 233 Pins 272 Pins 324 Pins P8 Port register 8 16 12-0 R/W 0020H 0000H   —  PSR8 Port set/reset register 8 32 28-16, 12-0 R/W 0120H 0000 0000H   —  PPR8 Port pin read register 8 16 12-0 R 0220H 0000H   —  PM8 Port mode register 8 16 12-0 R/W 0320H FFBFH   —  PMC8 Port mode control register 8 16 12-0 R/W 0420H 0000H   —  PFC8 Port function control register 8 16 12-0 R/W 0520H 0000H   —  PFCE8 Port function control expansion register 8 16 12-0 R/W 0620H 0000H   —  PNOT8 Port NOT register 8 16 12-0 W 0720H 0000H   —  PMSR8 Port mode set/reset register 8 32 28-16, 12-0 R/W 0820H 0000 FFBFH   —  PMCSR8 Port mode control set/reset register 8 32 28-16, 12-0 R/W 0920 H 0000 0000H   —  PFCAE8 Port function control additional expansion register 8 16 10, 8, 4, 1, 0 R/W 0A20 H 0000H   —  PIBC8 Port input buffer control register 16 12-0 R/W 4020H 0000H   —  PBDC8 Port bidirection control register 8 16 12-0 R/W 4120H 0000H   —  PU8 Pull-up option register 8 16 12-0 R/W 4320H 0000H   —  PD8 Pull-down option register 8 16 12-0 R/W 4420H 0000H   —  PODC8 Port open drain control register 8 32 12-0 R/W 4520H 0000 0040H   —  PIS8 Port input buffer selection register 8 32 12-0 R/W 4720 H FFFFH   —  PPROTS8 Port protection status register 8 32 0 R 4B20H 0000 0000H   —  PPCMD8 Port protection command register 8 32 7-0 W 4C20 H xxxx xx00H   —  Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset. CAUTION P8_6 drives a low level after any kind of reset release, until it is later configured differently by register settings. For details, see Section 2A.11.1.1, P8_6: RESETOUT .

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 205 of 4535 Dec 26, 2018 2A.10.7 Port 9 (P9) 2A.10.7.1 Alternative Function Table 2A.51 Port 9 (P9) Port Mode (PMC9_m = 0) Alternative Mode (PMC9_m = 1) ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 176 Pins 233 Pins 272 Pins 324 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output P9_0 NMI PWGA8O TAUD0I0 TAUD0O0 ADCA0TRG0 CSIH2CSS0 KR0I4 TAUJ1I1 TAUJ1O1 SENT1RX RIIC1SDA ADCA0I2S 108 K16 — T20 P9_1 INTP11 PWGA9O TAUD0I2 TAUD0O2 KR0I5 CSIH2CSS1 TAUJ1I2 TAUJ1O2 SENT1SP CO RIIC1SCL ADCA0I3S 109 K17 — R20 P9_2 KR0I6 PWGA20O TAPA0ESO CSIH2CSS2 ADCA0I9S 110 J17 — R19 P9_3 KR0I7 PWGA21O CSIH2CSS3 TAUJ1I1 TAUJ1O1 INTP16 ADCA0I10S 111 J15 — P19 P9_4 CSIH0CSS5 PWGA33O TAUJ1I0 TAUJ1O0 INTP17 ADCA0I11S 112 J16 — N19 CAUTIONS 1. The behavior and performance are not guaranteed when undocumented alternative functions are selected. 2. Use ADC functions with their initial settings. For details, see Table 2A.52, Control Registers (P9).

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 206 of 4535 Dec 26, 2018 2A.10.7.2 Control Registers Table 2A.52 Control Registers (P9) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 176 Pins 233 Pins 272 Pins 324 Pins P9 Port register 9 16 4-0 R/W 0024H 0000H   —  PSR9 Port set/reset register 9 32 20-16, 4-0 R/W 0124H 0000 0000H   —  PPR9 Port pin read register 9 16 4-0 R 0224H 0000H   —  PM9 Port mode register 9 16 4-0 R/W 0324H FFFFH   —  PMC9 Port mode control register 9 16 4-0 R/W 0424H 0000H   —  PFC9 Port function control register 9 16 4-0 R/W 0524H 0000H   —  PFCE9 Port function control expansion register 9 16 4, 3, 1, 0 R/W 0624H 0000H   —  PNOT9 Port NOT register 9 16 4-0 W 0724H 0000H   —  PMSR9 Port mode set/reset register 9 32 20-16, 4-0 R/W 0824H 0000 FFFFH   —  PMCSR9 Port mode control set/reset register 9 32 20-16, 4-0 R/W 0924 H 0000 0000H   —  PFCAE9 Port function control additional expansion register 9 16 1, 0 R/W 0A24H 0000H   —  PIBC9 Port input buffer control register 16 4-0 R/W 4024H 0000H   —  PBDC9 Port bidirection control register 9 16 4-0 R/W 4124H 0000H   —  PU9 Pull-up option register 9 16 4-0 R/W 4324H 0000H   —  PD9 Pull-down option register 9 16 4-0 R/W 4424H 0000H   —  PODC9 Port open drain control register 32 4-0 R/W 4524H 0000 0000H   —  PIS9 Port input buffer selection register 9 16 4-0 R/W 4724 H FFFFH   —  PPROTS9 Port protection status register 9 32 0 R 4B24H 0000 0000H   —  PPCMD9 Port protection command register 9 32 7-0 W 4C24 H xxxx xx00H   —  Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 207 of 4535 Dec 26, 2018 2A.10.8 Port 10 (P10) 2A.10.8.1 Alternative Function Table 2A.53 Port 10 (P10) Port Mode (PMC10_ m = 0) Alternative Mode (PMC10_m = 1) ADC Special Functio n PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 176 Pins 233 Pins 272 Pins 324 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output P10_0 TAUD0I1 TAUD0O1 CAN0RX/ INTP0 CSCXFOUT PWGA0O TAUJ1I3 TAPA0UP CSIH1SI MEMC0A19 ETNB0RXCLK TAUJ1O3 CAN0RX 174 A2 — D7 P10_1 TAUD0I3 TAUD0O3 INTP18 CAN0TX PWGA1O TAUJ3I0 TAPA0UN CSIH1SC ETNB0RXD0 MEMC0A20 TAUJ3O0 MODE0 175 B2 — D6 P10_2 TAUD0I5 TAUD0O5 RIIC0SDA KR0I0 PWGA2O ADCA0TRG0 TAPA0VP CSIH1SO ETNB0RXD1 MEMC0A21 RLIN37TX MODE1 176 C3 — C5 P10_3 TAUD0I7 TAUD0O7 RIIC0SCL KR0I1 PWGA3O ADCA0TRG1 TAPA0VN CSIH1SSI MEMC0CLK RLIN37RX/ INTP17 RLIN37RX 1 B1 — C4 P10_4 TAUD0I9 TAUD0O9 RLIN21RX CAN6TX KR0I2 ADCA0SEL0 ADCA0TRG2 TAPA0WP CSIG0SSI PWGA53O ETNB0RXD2 MEMC0A22 2 D3 — B2 P10_5 TAUD0I11 TAUD0O11 CAN6RX/ INTP6 RLIN21TX KR0I3 ADCA0SEL1 TAPA0WN CSIG0RYI CSIG0RYO ETNB0RXD3 PWGA54O CAN6RX 3 C2 — C3 P10_6 TAUD0I13 TAUD0O13 CSIG0SO ENCA0TIN0 ADCA0SEL2 CAN1RX /INTP1 MEMC0AD0 RLIN24RX CAN1RX MODE2 152 A9 — D14 P10_7 TAUD0I15 TAUD0O15 CSIG0SC ENCA0TIN1 PWGA4O CAN1TX MEMC0AD1 RLIN24TX TAUJ3I1 TAUJ3O1 153 A8 — C14 P10_8 TAUD0I10 TAUD0O10 CSIG0SI FLXA0TXDB ENCA0EC PWGA5O MEMC0AD2 TAUJ3I2 TAUJ3O2 FLMD1 154 D8 — B14 P10_9 TAUD0I12 TAUD0O12 RLIN30RX/ INTP10 ENCA0E0 PWGA6O CSIH0RYI CSIH0RYO MEMC0AD3 FLXA0RXDB RLIN30RX 155 B8 — C13 P10_10 TAUD0I14 TAUD0O14 RLIN30TX ENCA0E1 PWGA7O CSIH0CSS1 MEMC0AD4 TAUJ3I3 TAUJ3O3 156 A7 — A14 P10_11 PWGA16O RLIN31RX/ INTP11 FLXA0TXEN A CSIH1CSS0 TAUB0I1 TAUB0O1 MEMC0AD5 RLIN31RX 157 C8 — B13 P10_12 PWGA17O FLXA0STPW T RLIN31TX CSIH1CSS1 TAUB0I3 TAUB0O3 MEMC0AD6 158 D7 — A13 P10_13 CSIH0SSI PWGA18O RLIN32RX/ INTP12 FLXA0TXEN B TAUB0I5 TAUB0O5 MEMC0AD7 CAN7TX RLIN32RX 159 A6 — C12 P10_14 ADCA1TRG0 PWGA19O FLXA0RXDA RLIN32TX CSIH3SSI TAUB0I7 TAUB0O7 MEMC0AD8 CAN7RX/ INTP9 CAN7RX 160 B7 — B12 P10_15 CSIH3RYI CSIH3RYO PWGA24O RLIN22RX TAUB0I9 TAUB0O9 MEMC0RD 6 C1 — D1 CAUTION The behavior and performance are not guaranteed when undocumented alternative functions are selected.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 208 of 4535 Dec 26, 2018 2A.10.8.2 Control Registers Table 2A.54 Control Registers (P10) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 176 Pins 233 Pins 272 Pins 324 Pins P10 Port register 10 16 15-0 R/W 0028H 0000H   —  PSR10 Port set/reset register 10 32 31-16, 15-0 R/W 0128H 0000 0000H   —  PPR10 Port pin read register 10 16 15-0 R 0228H 0000H   —  PM10 Port mode register 10 16 15-0 R/W 0328H FFFFH   —  PMC10 Port mode control register 10 16 15-0 R/W 0428H 0000H   —  PFC10 Port function control register 10 16 15-0 R/W 0528H 0000H   —  PFCE10 Port function control expansion register 10 16 15-0 R/W 0628H 0000H   —  PNOT10 Port NOT register 10 16 15-0 W 0728H 0000H   —  PMSR10 Port mode set/reset register 10 32 31-16, 15-0 R/W 0828H 0000 FFFFH   —  PMCSR10 Port mode control set/reset register 10 32 31-16, 15-0 R/W 0928H 0000 0000H   —  PFCAE10 Port function control additional expansion register 10 16 15-0 R/W 0A28H 0000H   —  PIBC10 Port input buffer control register 10 16 15-0 R/W 4028H 0000H   —  PBDC10 Port bidirection control register 10 16 15-0 R/W 4128H 0000H   —  PIPC10 Port IP control register 10 16 14-0 R/W 4228H 0000H   —  PU10 Pull-up option register 10 16 15-0 R/W 4328H 0000H   —  PD10 Pull-down option register 10 16 15-0 R/W 4428H 0000H   —  PODC10 Port open drain control register 10 32 15-0 R/W 4528H 0000 0000H   —  PDSC10 Port drive strength control register 10 32 15-0 R/W 4628H 0000 0000H   —  PIS10 Port input buffer selection register 10 16 15-0 R/W 4728H FFFFH   —  PISA10 Port input buffer selection advanced register 10 16 5, 4, 2-0 R/W 4A28H 0000H   —  PPROTS10 Port protection status register 10 32 0 R 4B28H 0000 0000H   —  PPCMD10 Port protection command register 10 32 7-0 W 4C28H xxxx xx00H   —  Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 209 of 4535 Dec 26, 2018 2A.10.9 Port 11 (P11) 2A.10.9.1 Alternative Function Table 2A.55 Port 11 (P11) Port mode (PMC11_m = 0) Alternative Mode (PMC11_m = 1) ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 176 Pins 233 Pins 272 Pins 324 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output P11_0 CSIH2RYI CSIH2R YO ADCA1TRG PWGA25O RLIN22TX TAUB0I11 TAUB0O11 MEMC0WR

7 D2 — E3

P11_1 CSIH2SSI FLXA0T XDA RLIN20RX CSIH0CSS7 INTP20 PWGA26O TAUB0I13 TAUB0O13 MEMC0AD9 161 A5 — A12 P11_2 CSIH2S O RLIN32RX/ INTP12 RLIN20TX PWGA27O TAUB0I15 TAUB0O15 MEMC0AD10 SFMA0IO3 RLIN32RX 162 C7 — D11 P11_3 CSIH2SC CAN3RX/ INTP3 PWGA28O TAUB1I1 TAUB1O1 MEMC0AD11 RLIN32TX SFMA0IO2 CAN3RX 163 B6 — C11 P11_4 CSIH2SI CAN3TX INTP21 PWGA29O TAUB1I3 TAUB1O3 MEMC0AD12 SFMA0IO1 164 B5 — A10 P11_5 CAN5RX/ INTP5 RLIN33T X PWGA30O CSIH3SI TAUB1I5 TAUB1O5 MEMC0AD13 SFMA0IO0 CAN5RX 165 A4 — A9 P11_6 RLIN33RX/ INTP13 CAN5TX ADCA1TRG PWGA31O CSIH3SO TAUB1I7 TAUB1O7 MEMC0AD14 SFMA0SSL RLIN33RX 166 D6 — B9 P11_7 INTP5 PWGA32O CSIH3SC TAUB1I9 TAUB1O9 MEMC0AD15 SFMA0CLK 167 C6 — C9 P11_8 CSIG1SSI RLIN35T X PWGA48O TAUB1I11 TAUB1O1 MEMC0CS0

8 E3 — E2

P11_9 CSIG1S O RLIN35RX/ INTP15 PWGA49O TAUB1I13 TAUB1O1 MEMC0CS1 RLIN35RX 9 D1 — F3 P11_10 CSIG1SC PWGA50O TAUB1I15 TAUB1O1 MEMC0CS2

10 E2 — G3

P11_11 CSIG1SI RLIN25T X PWGA51O TAUB1I0 TAUB1O0 MEMC0CS3 ETNB0R XDV

11 F3 — G2

P11_12 RLIN25RX PWGA52O TAUB1I2 TAUB1O2 MEMC0WAIT 12 E1 — H2 P11_15 CAN2RX/ INTP2 CSIH2C SS4 PWGA55O TAUB1I8 TAUB1O8 MEMC0ASTB ETNB0R XERR RLIN36TX CAN2RX 168 D5 — D9 CAUTION The behavior and performance are not guaranteed when undocumented alternative functions are selected.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 210 of 4535 Dec 26, 2018 2A.10.9.2 Control Registers Table 2A.56 Control Registers (P11) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 176 Pins 233 Pins 272 Pins 324 Pins P11 Port register 11 16 15, 12-0 R/W 002CH 0000H   —  PSR11 Port set/reset register 11 32 31, 28-16, 15, 12-0 R/W 012CH 0000 0000H   —  PPR11 Port pin read register 11 16 15, 12-0 R 022CH 0000H   —  PM11 Port mode register 11 16 15, 12-0 R/W 032CH FFFFH   —  PMC11 Port mode control register 11 16 15, 12-0 R/W 042CH 0000H   —  PFC11 Port function control register 11 16 15, 12-0 R/W 052CH 0000H   —  PFCE11 Port function control expansion register 11 16 15, 12-0 R/W 062CH 0000H   —  PNOT11 Port NOT register 11 16 15, 12-0 W 072CH 0000H   —  PMSR11 Port mode set/reset register 11 32 31, 28-16, 15, 12-0 R/W 082CH 0000 FFFFH   —  PMCSR11 Port mode control set/reset register 11 32 31, 28-16, 15, 12-0 R/W 092CH 0000 0000H   —  PFCAE11 Port function control additional expansion register 11 16 15, 11, 9, 7-0 R/W 0A2CH 0000H   —  PIBC11 Port input buffer control register 11 16 15, 12-0 R/W 402CH 0000H   —  PBDC11 Port bidirection control register 11 16 15, 12-0 R/W 412CH 0000H   —  PIPC11 Port IP control register 11 16 10, 9, 7-1 R/W 422CH 0000H   —  PU11 Pull-up option register 11 16 15, 12-0 R/W 432CH 0000H   —  PD11 Pull-down option register 11 16 15, 12-0 R/W 442CH 0000H   —  PODC11 Port open drain control register 11 32 15, 12-0 R/W 452CH 0000 0000H   —  PDSC11 Port drive strength control register 11 32 15, 12-0 R/W 462CH 0000 0000H   —  PIS11 Port input buffer selection register 11 16 15, 12-0 R/W 472CH FFFFH   —  PISA11 Port input buffer selection advanced register 11 16 15, 12-10 R/W 4A2C H 0000H   —  PPROTS11 Port protection status register 11 32 0 R 4B2CH 0000 0000H   —  PPCMD11 Port protection command register 11 32 7-0 W 4C2CH xxxx xx00H   —  Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 211 of 4535 Dec 26, 2018 2A.10.10 Port 12 (P12) 2A.10.10.1 Alternative Function Table 2A.57 Port 12 (P12) Port Mode (PMC12_m =0) Alternative Mode (PMC12_m =1) ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 176 Pins 233 Pins 272 Pins 324 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output P12_0 CAN2TX PWGA56O TAUB1I10 TAUB1O10 CSIG2SSI MEMC0A RLIN36RX/ INTP16 RLIN36RX 169 B4 — A7 P12_1 RLIN34RX/ INTP14 CSIH2CSS PWGA57O TAUB1I12 TAUB1O12 MEMC0A RLIN34RX 170 C5 — A6 P12_2 INTP19 RLIN34TX PWGA58O TAUB1I14 TAUB1O14 MEMC0A CSIG2RYI CSIG2RYO 171 A3 — D8 P12_3 RLIN27RX PWGA68O CSIG2SI MEMC0BEN0 TAUB1I6 TAUB1O

15 G1 — L4

P12_4 RLIN27TX PWGA69O CSIG2SC ETNB0MDIO MEMC0BEN1 16 H1 — N4 P12_5 PWGA70O ETNB0MD C CSIG2SO TAUB1I4 TAUB1O4 17 J3 — R1 CAUTION The behavior and performance are not guaranteed when undocumented alternative functions are selected.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev .1.10 Page 212 of 4535 Dec 26, 2018 2A.10.10.2 Control Registers Table 2A.58 Control Registers (P12) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 176 Pins 233 Pins 272 Pins 324 Pins P12 Port register 12 16 5-0 R/W 0030H 0000H   —  PSR12 Port set/reset register 12 32 21-16, 5-0 R/W 0130H 0000 0000H   —  PPR12 Port pin read register 12 16 5-0 R 0230H 0000H   —  PM12 Port mode register 12 16 5-0 R/W 0330H FFFFH   —  PMC12 Port mode control register 12 16 5-0 R/W 0430H 0000H   —  PFC12 Port function control register 12 16 5-0 R/W 0530H 0000H   —  PFCE12 Port function control expansion register 12 16 5-0 R/W 0630H 0000H   —  PNOT12 Port NOT register 12 16 5-0 W 0730H 0000H   —  PMSR12 Port mode set/reset register 12 32 21-16, 5-0 R/W 0830H 0000 FFFFH   —  PMCSR12 Port mode control set/reset register 12 32 21-16, 5-0 R/W 0930H 0000 0000H   —  PFCAE12 Port function control expansion register 12 16 4, 2-0 R/W 0A30H 0000H   —  PIBC12 Port input buffer control register 12 16 5-0 R/W 4030H 0000H   —  PBDC12 Port bidirection control register 12 16 5-0 R/W 4130H 0000H   —  PIPC12 Port IP control register 12 16 5, 4 R/W 4230H 0000H   —  PU12 Pull-up option register 12 16 5-0 R/W 4330H 0000H   —  PD12 Pull-down option register 12 16 5-0 R/W 4430H 0000H   —  PODC12 Port open drain control register 12 32 5-0 R/W 4530H 0000 0000H   —  PDSC12 Port drive strength control register 12 32 5-0 R/W 4630H 0000 0000H   —  PIS12 Port input buffer selection register 12 16 5-0 R/W 4730H FFFFH   —  PISA12 Port input buffer selection advanced register 12 16 4 R/W 4A30H 0000H   —  PPROTS12 Port protection status register 12 32 0 R 4B30H 0000 0000H   —  PPCMD12 Port protection command register 12 32 7-0 W 4C30H xxxx xx00H   —  Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 213 of 4535 Dec 26, 2018 2A.10.11 Port 13 (P13) 2A.10.11.1 Alternative Function Table 2A.59 Port 13 (P13) Port Mode (PMC13_m =0) Alternative Mode (PMC13_m =1) ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 176 Pins 233 Pins 272 Pins 324 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output P13_0 MEMC0A19 — C4 — C7 P13_1 MEMC0A20 — B3 — B6 P13_2 ETNB0RXD V — F2 — K3 P13_3 ETNB0RXE RR — F1 — L3 P13_4 — G2 — — ETNB1LINK — — — M3 P13_5 MEMC0A21 — G3 — K2 P13_6 MEMC0A22 PWGA72O — H3 — M4 P13_7 PWGA73O — H2 — — MEMC0A23 PWGA73O — — — N3 CAUTION The behavior and performance are not guaranteed when undocumented alternative functions are selected.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 214 of 4535 Dec 26, 2018 2A.10.11.2 Control Registers Table 2A.60 Control Registers (P13) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 176 Pins 233 Pins 272 Pins 324 Pins P13 Port register 13 16 7-0 R/W 0034H 0000H —  —  PSR13 Port set/reset register 13 32 23-16, 7-0 R/W 0134H 0000 0000H —  —  PPR13 Port pin read register 13 16 7-0 R 0234H 0000H —  —  PM13 Port mode register 13 16 7-0 R/W 0334H FFFFH —  —  PMC13 Port mode control register 13 16 7-5, 3-0 R/W 0434H 0000H —  — — 7-0 — — —  PFC13 Port function control register 13 16 7, 6 R/W 0534H 0000H —  —  PNOT13 Port NOT register 13 16 7-0 W 0734H 0000H —  —  PMSR13 Port mode set/reset register 13 32 23-16, 7-0 R/W 0834H 0000 FFFFH —  —  PMCSR13 Port mode control set/reset register 13 32 23-21, 19-16, 7-5, 3-0 R/W 0934H 0000 0000H —  — — 23-16, 7-0 — — —  PIBC13 Port input buffer control register 13 16 7-0 R/W 4034H 0000H —  —  PBDC13 Port bidirection control register 13 16 7-0 R/W 4134H 0000H —  —  PU13 Pull-up option register 13 16 7-0 R/W 4334H 0000H —  —  PD13 Pull-down option register 13 16 7-0 R/W 4434H 0000H —  —  PODC13 Port open drain control register 13 32 7-0 R/W 4534H 0000 0000H —  —  PDSC13 Port drive strength control register 13 32 7-0 R/W 4634H 0000 0000H —  —  PIS13 Port input buffer selection register 13 16 7-0 R/W 4734H FFFFH —  —  PISA13 Port input buffer selection advanced register 13 16 5, 3, 2 R/W 4A34H 0000H —  — — 5-2 — — —  PPROTS13 Port protection status register 13 32 0 R 4B34H 0000 0000H —  —  PPCMD13 Port protection command register 13 32 7-0 W 4C34H 0000 0000H —  —  Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 215 of 4535 Dec 26, 2018 2A.10.12 Port 18 (P18) 2A.10.12.1 Alternative Function Table 2A.61 Port 18 (P18) Port Mode (PMC18_m = 0) Alternative Mode (PMC18_m = 1) ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 176 Pins 233 Pins 272 Pins 324 Pins Input Output Input Output Input Output Input Output Input Output P18_0 CSIG1RYI CSIG1RYO ETNB0LINK PWGA61O TAUJ3I0 TAUJ3O0 ADCA1I0S 143 C14 — A21 P18_1 PWGA62O ETNB0TXD0 TAUJ3I1 TAUJ3O1 ADCA1I1S 144 B15 — B20 P18_2 PWGA63O ETNB0TXD1 TAUJ3I2 TAUJ3O2 ADCA1I2S 145 B14 — C19 P18_3 PWGA71O ETNB0TXD2 TAUJ3I3 TAUJ3O3 ADCA1I3S 146 B13 — A19 P18_4 CSIH1CSS4 ETNB0TXD3 ADCA1I4S 147 C11 — B18 P18_5 CSIH1CSS5 ETNB0TXEN ADCA1I5S 148 A14 — D16 P18_6 ADCA1I6S 149 A13 — — PWGA95O ADCA1I6S — — — A18 P18_7 ETNB0TXCLK ADCA1I7S 150 B11 — B16 P18_8 ADCA1I8S — A16 — B19 P18_9 ADCA1I9S — C13 — A20 P18_10 ADCA1I10S — A15 — C18 P18_11 ADCA1I11S — B12 — C17 P18_12 ADCA1I12S — C12 — C16 P18_13 ADCA1I13S — A12 — B17 P18_14 ADCA1I14S — C9 — C15 P18_15 ADCA1I15S — A11 — A17 CAUTIONS 1. The behavior and performance are not guaranteed when undocumented alternative functions are selected. 2. Use ADC functions with their initial settings. For details, see Table 2A.62, Control Registers (P18).

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 216 of 4535 Dec 26, 2018 2A.10.12.2 Control Registers Table 2A.62 Control Registers (P18) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 176 Pins 233 Pins 272 Pins 324 Pins P18 Port register 18 16 7-0 R/W 0048H 0000H  — — — 15-0 —  —  PSR18 Port set/reset register 18 32 23-16, 7-0 R/W 0148H 0000 0000H  — — — PPR18 Port pin read register 18 16 7-0 R 0248H 0000H  — — — 15-0 —  —  PM18 Port mode register 18 16 7-0 R/W 0348H FFFFH  — — — 15-0 —  —  PMC18 Port mode control register 18 16 7, 5-0 R/W 0448H 0000H   — — 7-0 — — —  PFC18 Port function control register 18 16 5-0 R/W 0548H 0000H   —  PFCE18 Port function control expansion register 18 16 3-0 R/W 0648H 0000H   —  PNOT18 Port NOT register 18 16 7-0 W 0748H 0000H  — — — 15-0 —  —  PMSR18 Port mode set/reset register 18 32 23-16, 7-0 R/W 0848H 0000 FFFFH  — — — PMCSR18 Port mode control set/reset register 18 32 23, 21-16, 7, 5- R/W 0948H 0000 0000H   — — 23-16, 7-0 — — —  PIBC18 Port input buffer control register 18 16 7-0 R/W 4048H 0000H  — — — 15-0 —  —  PBDC18 Port bidirection control register 18 16 7-0 R/W 4148H 0000H  — — — 15-0 —  —  PU18 Pull-up option register 18 16 7-0 R/W 4348H 0000H  — — — 15-0 —  —  PD18 Pull-down option register 18 16 7-0 R/W 4448H 0000H  — — — 15-0 —  —  PODC18 Port open drain control register 18 32 7-0 R/W 4548H 0000 0000H  — — — 15-0 —  —  PDSC18 Port drive strength control register 18 32 7-0 R/W 4648H 0000 0000H  — — — 15-0 —  —  PIS18 Port input buffer selection register 18 16 7-0 R/W 4748H FFFFH  — — — 15-0 —  —  PISA18 Port protection status register 18 16 7, 0 R/W 4A48H 0000H  — — — 9-7, 0 —  —  PPROTS1 Port protection status register 18 32 0 R 4B48H 0000 0000H   —  PPCMD18 Port protection command register 18 32 7-0 W 4C48H xxxx xx00H   —  Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 217 of 4535 Dec 26, 2018 2A.10.13 Port 19 (P19) 2A.10.13.1 Alternative Function Table 2A.63 Port 19 (P19) Port Mode Alternative Mode ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 176 Pins 233 Pins 272 Pins 324 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output P19_0 ADCA1I16S — C10 — A16 P19_1 ADCA1I17S — B10 — A15 P19_2 ADCA1I18S — A10 — D15 P19_3 ADCA1I19S — B9 — B15 CAUTIONS 1. The behavior and performance are not guaranteed when undocumented alternative functions are selected. 2. Use ADC functions with their initial settings. For details, see Table 2A.64, Control Registers (P19).

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 218 of 4535 Dec 26, 2018 2A.10.13.2 Control Registers Table 2A.64 Control Registers (P19) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 176 Pins 233 Pins 272 Pins 324 Pins P19 Port register 19 16 3-0 R/W 004CH 0000H —  —  PSR19 Port set/reset register 19 32 19-16, 3-0 R/W 014CH 0000 0000H —  —  PPR19 Port pin read register 19 16 3-0 R 024CH 0000H —  —  PM19 Port mode register 19 16 3-0 R/W 034CH FFFFH —  —  PNOT19 Port NOT register 19 16 3-0 W 074CH 0000H —  —  PMSR19 Port mode set/reset register 19 32 19-16, 3-0 R/W 084CH 0000 FFFFH —  —  PIBC19 Port input buffer control register 19 16 3-0 R/W 404CH 0000H —  —  PBDC19 Port bidirection control register 19 16 3-0 R/W 414CH 0000H —  —  PU19 Pull-up option register 19 16 3-0 R/W 434CH 0000H —  —  PD19 Pull-down option register 19 16 3-0 R/W 444CH 0000H —  —  PODC19 Port open drain control register 19 32 3-0 R/W 454CH 0000 0000H —  —  PDSC19 Port drive strength control register 19 32 3-0 R/W 464CH 0000 0000H —  —  PIS19 Port input buffer selection register 19 16 3-0 R/W 474CH FFFFH —  —  PPROTS19 Port protection status register 19 32 0 R 4B4CH 0000 0000H —  —  PPCMD19 Port protection command register 19 32 7-0 W 4C4CH 0000 0000H —  —  Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 219 of 4535 Dec 26, 2018 2A.10.14 Port 20 (P20) 2A.10.14.1 Alternative Function Table 2A.65 Port 20 (P20) Port Mode (PMC20_m =0) Alternative Mode (PMC20_m = 1) ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 176 Pins 233 Pins 272 Pins 324 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output P20_0 RLIN26RX PWGA64O CAN6RX/ INTP6 CSIG3SI CAN6RX 118 G17 — J20 P20_1 RLIN26TX PWGA65O CAN6TX CSIG3SO 117 H15 — J22 P20_2 CAN4RX/ INTP4 PWGA66O RLIN29RX CSIG3SC CAN4RX 116 H16 — K20 P20_3 CAN4TX PWGA67O RLIN29TX CSIG3RYI CSIG3RYO 115 H17 — K21 P20_4 RLIN23RX INTP22 PWGA59O CAN7RX/ INTP9 CSIG3SSI CAN7RX 120 F17 — H22 P20_5 RLIN23TX INTP23 PWGA60O CAN7TX 119 G16 — J21 P20_6 PWGA88O — — — G21 P20_7 PWGA89O — — — G22 P20_8 PWGA90O — — — H20 P20_9 PWGA91O — — — H21 P20_10 PWGA92O — — — K22 P20_11 PWGA93O — — — L20 P20_12 PWGA94O — — — L21 RLIN215RX PWGA95O — — — M20 RLIN215TX — — — M21 P20_15 RLIN214RX — — — L22 CAUTION The behavior and performance are not guaranteed when undocumented alternative functions are selected.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 220 of 4535 Dec 26, 2018 2A.10.14.2 Control Registers Table 2A.66 Control Registers (P20) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 176 Pins 233 Pins 272 Pins 324 Pins P20 Port register 20 16 5-0 R/W 0050H 0000H   — — 14-0 — — — — 15-0 — — —  PSR20 Port set/reset register 20 32 21-16, 5-0 R/W 0150H 0000 0000H   — — PPR20 Port pin read register 20 16 5-0 R 0250H 0000H   — — 14-0 — — — — 15-0 — — —  PM20 Port mode register 20 16 5-0 R/W 0350H FFFFH   — — 14-0 — — — — 15-0 — — —  PMC20 Port mode control register 20 16 5-0 R/W 0450H 0000H   — — 13-0 — — — — 15-0 — — —  PFC20 Port function control register 20 16 5-0 R/W 0550H 0000H   —  PFCE20 Port function control expansion register 20 16 5-0 R/W 0650H 0000H   —  PNOT20 Port NOT register 20 16 5-0 W 0750H 0000H   — — 14-0 — — — — 15-0 — — —  PMSR20 Port mode set/reset register 20 32 21-16, 5-0 R/W 0850H 0000 FFFFH   — — PMCSR20 Port mode control set/reset register 20 32 21-16, 5-0 R/W 0950H 0000 0000H   — — PFCAE20 Port function control additional expansion register 20 16 4, 2, 0 R/W 0A50H 0000H   —  PIBC20 Port input buffer control register 20 16 5-0 R/W 4050H 0000H   — — 14-0 — — — — 15-0 — — —  PBDC20 Port bidirection control register 20 16 5-0 R/W 4150H 0000H   — — 14-0 — — — — 15-0 — — —  PIPC20 Port IP control register 20 16 2, 1 R/W 4250H 0000H   —  PU20 Pull-up option register 20 16 5-0 R/W 4350H 0000H   — — 14-0 — — — — 15-0 — — —  PD20 Pull-down option register 20 16 5-0 R/W 4450H 0000H   — — 14-0 — — — — 15-0 — — —  PODC20 Port open drain control register 20 32 5-0 R/W 4550H 0000 0000H   — — 14-0 — — — — 15-0 — — — 

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 221 of 4535 Dec 26, 2018 Table 2A.66 Control Registers (P20) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 176 Pins 233 Pins 272 Pins 324 Pins PDSC20 Port drive strength control register 20 32 5-0 R/W 4650H 0000 0000H   — — 14-0 — — — — 15-0 — — —  PIS20 Port input buffer selection register 20 16 5-0 R/W 4750H FFFFH   — — 14-0 — — — — 15-0 — — —  PPROTS20 Port protection status register 20 32 0 R 4B50H 0000 0000H   —  PPCMD20 Port protection command register 20 32 7-0 W 4C50H xxxx xx00H   —  Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 222 of 4535 Dec 26, 2018 2A.10.15 Port 21 (P21) 2A.10.15.1 Alternative Function Table 2A.67 Port 21 (P21) Port Mode (PMC21_m =0) Alternative Mode (PMC21_m = 1) ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 176 Pins 233 Pins 272 Pins 324 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output ETNB1RXDV — — — H3 MMCA0DAT7 — — — B11 ETNB1RXD2 — — — J2 ETNB1RXD1 — — — J3 ETNB1RXD0 — — — H1 P21_5 ETNB1RXD3 — — — J1 P21_6 ETNB1MDC — — — K1 P21_7 ETNB1MDIO — — — L1 P21_8 ETNB1RXERR — — — L2 P21_9 — — — M1 P21_10 — — — M2 P21_11 RLIN213RX — — — N1 P21_12 RLIN213TX — — — P1 P21_13 RLIN212RX — — — N2 P21_14 RLIN212TX — — — P2 CAUTION The behavior and performance are not guaranteed when undocumented alternative functions are selected.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 223 of 4535 Dec 26, 2018 2A.10.15.2 Control Registers Table 2A.68 Control Registers (P21) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 176 Pins 233 Pins 272 Pins 324 Pins P21 Port register 21 16 4-0 R/W 0054H 0000H — — — — 14-0 — — —  PSR21 Port set/reset register 21 32 20-16, 4-0 R/W 0154H 0000 0000H — — — — PPR21 Port pin read register 21 16 4-0 R 0254H 0000H — — — — 14-0 — — —  PM21 Port mode register 21 16 4-0 R/W 0354H FFFFH — — — — 14-0 — — —  PMC21 Port mode control register 21 16 14-11, 8-0 R/W 0454H 0000H — — —  PNOT21 Port NOT register 21 16 4-0 W 0754H 0000H — — — — 14-0 — — —  PMSR21 Port mode set/reset register 21 32 20-16, 4-0 R/W 0854H 0000 FFFFH — — — — PMCSR21 Port mode control set/reset register 32 30-27, 24- 16, 14-11, 8- R/W 0954H 0000 0000H — — —  PIBC21 Port input buffer control register 21 16 4-0 R/W 4054H 0000H — — — — 14-0 — — —  PBDC21 Port bidirection control register 21 16 4-0 R/W 4154H 0000H — — — — 14-0 — — —  PIPC21 Port IP control register 21 16 7, 1 R/W 4254H 0000H — — —  PU21 Pull-up option register 21 16 4-0 R/W 4354H 0000H — — — — 14-0 — — —  PD21 Pull-down option register 21 16 4-0 R/W 4454H 0000H — — — — 14-0 — — —  PODC21 Port open drain control register 21 32 4-0 R/W 4554H 0000 0000H — — — — 14-0 — — —  PDSC21 Port drive strength control register 21 32 14-0 R/W 4654H 0000 0000H — — —  PIS21 Port input buffer selection register 21 16 4-0 R/W 4754H FFFFH — — — — 14-0 — — —  PISA21 Port input buffer selection advanced register 21 16 10-7, 5-2, 0 R/W 4A54 H 0000H — — —  PPROTS21 Port protection status register 21 32 0 R 4B54H 0000 0000H — — —  PPCMD21 Port protection command register 21 32 7-0 W 4C54H 0000 0000H — — —  Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 224 of 4535 Dec 26, 2018 2A.10.16 Port 22 (P22) 2A.10.16.1 Alternative Function Table 2A.69 Port 22 (P22) Port Mode (PMC22_m =0) Alternative Mode (PMC22_m = 1) ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 176 Pins 233 Pins 272 Pins 324 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output ETNB1RXCLK — — — G1 ETNB1TXD3 — — — F2 ETNB1TXD2 — — — F1 ETNB1TXD1 — — — E1 ETNB1TXD0 — — — D2 ETNB1TXEN — — — D3 ETNB1TXCLK — — — C2 MMCA0CMD — — — A5 MMCA0CLK — — — C6 MMCA0DAT0 — — — B7 MMCA0DAT1 — — — C8 MMCA0DAT2 — — — A8 MMCA0DAT3 — — — B8 MMCA0DAT4 — — — C10

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 225 of 4535 Dec 26, 2018 Table 2A.69 Port 22 (P22) Port Mode (PMC22_m =0) Alternative Mode (PMC22_m = 1) ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 176 Pins 233 Pins 272 Pins 324 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output MMCA0DAT5 — — — B10 MMCA0DAT6 — — — A11 CAUTION The behavior and performance are not guaranteed when undocumented alternative functions are selected.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 226 of 4535 Dec 26, 2018 2A.10.16.2 Control Registers Table 2A.70 Control Registers (P22) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 176 Pins 233 Pins 272 Pins 324 Pins P22 Port register 22 16 15-0 R/W 0058H 0000H — — —  PSR22 Port set/reset register 22 32 31-16, 15-0 R/W 0158H 0000 0000H — — —  PPR22 Port pin read register 22 16 15-0 R 0258H 0000H — — —  PM22 Port mode register 22 16 15-0 R/W 0358H FFFFH — — —  PMC22 Port mode control register 22 16 15-0 R/W 0458H 0000H — — —  PNOT22 Port NOT register 22 16 15-0 W 0758H 0000H — — —  PMSR22 Port mode set/reset register 22 32 31-16, 15-0 R/W 0858H 0000 FFFFH — — —  PMCSR22 Port mode control set/reset register 22 32 31-16, 15-0 R/W 0958H 0000 0000H — — —  PIBC22 Port input buffer control register 22 16 15-0 R/W 4058H 0000H — — —  PBDC22 Port bidirection control register 22 16 15-0 R/W 4158H 0000H — — —  PIPC22 Port IP control register 22 16 15-9, 7 R/W 4258H 0000H — — —  PU22 Pull-up option register 22 16 15-0 R/W 4358H 0000H — — —  PD22 Pull-down option register 22 16 15-0 R/W 4458H 0000H — — —  PODC22 Port open drain control register 22 32 15-0 R/W 4558H 0000 0000H — — —  PDSC22 Port drive strength control register 22 32 15-0 R/W 4658H 0000 0000H — — —  PIS22 Port input buffer selection register 22 16 15-0 R/W 4758H FFFFH — — —  PISA22 Port input buffer selection advanced register 22 16 6, 0 R/W 4A58H 0000H — — —  PPROTS22 Port protection status register 22 32 0 R 4B58H 0000 0000H — — —  PPCMD22 Port protection command register 22 32 7-0 W 4C58H 0000 0000H — — —  Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 227 of 4535 Dec 26, 2018 2A.10.17 Port 23 (P23) 2A.10.17.1 Alternative Function Table 2A.71 Port 23 (P23) Port Mode (PMC23_m =0) Alternative Mode (PMC23_m = 1) ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 176 Pins 233 Pins 272 Pins 324 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output P23_0 CSIH4SSI — — — T21 P23_1 CSIH4SO — — — T22 P23_2 CSIH4SI — — — R21 P23_3 CSIH4SC — — — R22 P23_4 CSIH4RYI CSIH4RYO — — — P21 P23_5 CSIG4RYI CSIG4RYO — — — P22 P23_6 CSIG4SO — — — P20 P23_7 CSIG4SI — — — N20 P23_8 CSIG4SC — — — N21 P23_9 CSIG4SSI — — — N22 P23_10 RLIN214TX — — — M22 CAUTION The behavior and performance are not guaranteed when undocumented alternative functions are selected.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 228 of 4535 Dec 26, 2018 2A.10.17.2 Control Registers Table 2A.72 Control Registers (P23) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 176 Pins 233 Pins 272 Pins 324 Pins P23 Port register 23 16 10-0 R/W 005CH 0000H — — —  PSR23 Port set/reset register 23 32 26-16, 10-0 R/W 015CH 0000 0000H — — —  PPR23 Port pin read register 23 16 10-0 R 025CH 0000H — — —  PM23 Port mode register 23 16 10-0 R/W 035CH FFFFH — — —  PMC23 Port mode control register 23 16 10-0 R/W 045CH 0000H — — —  PNOT23 Port NOT register 23 16 10-0 W 075CH 0000H — — —  PMSR23 Port mode set/reset register 23 32 26-16, 10-0 R/W 085CH 0000 FFFFH — — —  PMCSR23 Port mode control set/reset register 23 32 26-16, 10-0 R/W 095CH 0000 0000H — — —  PIBC23 Port input buffer control register 23 16 10-0 R/W 405CH 0000H — — —  PBDC23 Port bidirection control register 23 16 10-0 R/W 415CH 0000H — — —  PIPC23 Port IP control register 23 16 8, 6, 3, 1 R/W 425CH 0000H — — —  PU23 Pull-up option register 23 16 10-0 R/W 435CH 0000H — — —  PD23 Pull-down option register 23 16 10-0 R/W 445CH 0000H — — —  PODC23 Port open drain control register 23 32 10-0 R/W 455CH 0000 0000H — — —  PDSC23 Port drive strength control register 23 32 10-0 R/W 465CH 0000 0000H — — —  PIS23 Port input buffer selection register 23 16 10-0 R/W 475CH FFFFH — — —  PPROTS23 Port protection status register 23 32 0 R 4B5CH 0000 0000H — — —  PPCMD23 Port protection command register 23 32 7-0 W 4C5CH 0000 0000H — — —  Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 229 of 4535 Dec 26, 2018 2A.10.18 Port 24 (P24) 2A.10.18.1 Alternative Function Table 2A.73 Port 24 (P24) Port Mode (PMC24_m =0) Alternative Mode (PMC24_m = 1) ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 176 Pins 233 Pins 272 Pins 324 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output P24_0 CAN8TX — — — B5 P24_1 CAN8RX/ INTP18 CAN8RX — — — B4 P24_2 CAN9TX — — — A3 P24_3 CAN9RX/ INTP19 CAN9RX — — — A4 P24_4 CAN10TX — — — B3 P24_5 CAN10RX/ INTP20 CAN10RX — — — A2 P24_6 CAN11TX — — — B1 P24_7 CAN11RX/ INTP21 CAN11RX — — — C1 CAUTION The behavior and performance are not guaranteed when undocumented alternative functions are selected.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 230 of 4535 Dec 26, 2018 2A.10.18.2 Control Registers Table 2A.74 Control Registers (P24) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 176 Pins 233 Pins 272 Pins 324 Pins P24 Port register 24 16 7-0 R/W 0060H 0000H — — —  PSR24 Port set/reset register 24 32 23-16, 7-0 R/W 0160H 0000 0000H — — —  PPR24 Port pin read register 24 16 7-0 R 0260H 0000H — — —  PM24 Port mode register 24 16 7-0 R/W 0360H FFFFH — — —  PMC24 Port mode control register 24 16 7-0 R/W 0460H 0000H — — —  PFC24 Port function control register 24 16 7, 5, 3, 1 R/W 0560H 0000H — — —  PNOT24 Port NOT register 24 16 7-0 W 0760H 0000H — — —  PMSR24 Port mode set/reset register 24 32 23-16, 7-0 R/W 0860H 0000 FFFFH — — —  PMCSR24 Port mode control set/reset register 24 32 23-16, 7-0 R/W 0960H 0000 0000H — — —  PIBC24 Port input buffer control register 24 16 7-0 R/W 4060H 0000H — — —  PBDC24 Port bidirection control register 24 16 7-0 R/W 4160H 0000H — — —  PU24 Pull-up option register 24 16 7-0 R/W 4360H 0000H — — —  PD24 Pull-down option register 24 16 7-0 R/W 4460H 0000H — — —  PODC24 Port open drain control register 24 32 7-0 R/W 4560H 0000 0000H — — —  PDSC24 Port drive strength control register 24 32 7-0 R/W 4660H 0000 0000H — — —  PIS24 Port input buffer selection register 24 16 7-0 R/W 4760H FFFFH — — —  PPROTS24 Port protection status register 24 32 0 R 4B60H 0000 0000H — — —  PPCMD24 Port protection command register 24 32 7-0 W 4C60H 0000 0000H — — —  Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 231 of 4535 Dec 26, 2018 2A.10.19 Analog Port 0 (AP0) 2A.10.19.1 Alternative Function Table 2A.75 Analog Port 0 (AP0) Port Mode Alternative Mode ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 176 Pins 233 Pins 272 Pins 324 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output AP0_0 ADCA0I0 106 K15 — U22 AP0_1 ADCA0I1 105 L17 — V22 AP0_2 ADCA0I2 104 L16 — U21 AP0_3 ADCA0I3 103 M17 — W22 AP0_4 ADCA0I4 102 L15 — V21 AP0_5 ADCA0I5 101 M16 — U20 AP0_6 ADCA0I6 100 N17 — W21 AP0_7 ADCA0I7 99 N16 — Y22 AP0_8 ADCA0I8 98 M15 — W20 AP0_9 ADCA0I9 97 P17 — AA22 AP0_10 ADCA0I10 96 P16 — V20 AP0_11 ADCA0I11 95 N15 — AA21 AP0_12 ADCA0I12 94 R17 — Y21 AP0_13 ADCA0I13 93 P15 — Y20 AP0_14 ADCA0I14 92 R16 — W19 AP0_15 ADCA0I15 91 T17 — AB21 CAUTION Use ADC functions with their initial settings. For details, see Table 2A.76, Control Registers (AP0).

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 232 of 4535 Dec 26, 2018 2A.10.19.2 Control Registers Table 2A.76 Control Registers (AP0) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 176 Pins 233 Pins 272 Pins 324 Pins AP0 Analog port register 0 16 15-0 R/W 00C8H 0000H   —  APSR0 Analog port set/reset register 0 32 31-16, 15-0 R/W 01C8H 0000 0000H   —  APPR0 Analog port pin read register 0 16 15-0 R 02C8H 0000H   —  APM0 Analog port mode register 0 16 15-0 R/W 03C8H FFFFH   —  APNOT0 Analog port NOT register 0 16 15-0 W 07C8H 0000H   —  APMSR0 Analog port mode set/reset register 0 32 31-16, 15-0 R/W 08C8H 0000 FFFFH   —  APIBC0 Analog port input buffer control register 0 16 15-0 R/W 40C8H 0000H   —  APBDC0 Analog port bidirection control register 0 16 15-0 R/W 41C8H 0000H   —  Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 233 of 4535 Dec 26, 2018 2A.10.20 Analog Port 1 (AP1) 2A.10.20.1 Alternative Function Table 2A.77 Analog Port 1 (AP1) Port Mode Alternative Mode ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 176 Pins 233 Pins 272 Pins 324 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output AP1_0 ADCA1I0 133 C17 — C21 AP1_1 ADCA1I1 132 D15 — C22 AP1_2 ADCA1I2 131 D16 — E20 AP1_3 ADCA1I3 130 D17 — D21 AP1_4 ADCA1I4 129 F14 — E21 AP1_5 ADCA1I5 128 E15 — D22 AP1_6 ADCA1I6 127 E16 — F20 AP1_7 ADCA1I7 126 F15 — E22 AP1_8 ADCA1I8 125 E17 — F22 AP1_9 ADCA1I9 124 F16 — F21 AP1_10 ADCA1I10 123 G14 — G19 AP1_11 ADCA1I11 122 G15 — G20 AP1_12 ADCA1I12 137 B16 — C20 AP1_13 ADCA1I13 136 C15 — B21 AP1_14 ADCA1I14 135 B17 — D20 AP1_15 ADCA1I15 134 C16 — B22 CAUTION Use ADC functions with their initial settings. For details, see Table 2A.78, Control Registers (AP1).

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 234 of 4535 Dec 26, 2018 2A.10.20.2 Control Registers Table 2A.78 Control Registers (AP1) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 176 Pins 233 Pins 272 Pins 324 Pins AP1 Analog port register 1 16 15-0 R/W 00CCH 0000H   —  APSR1 Analog port set/reset register 1 32 31-16, 15-0 R/W 01CCH 0000 0000H   —  APPR1 Analog port pin read register 1 16 15-0 R 02CCH 0000H   —  APM1 Analog port mode register 1 16 15-0 R/W 03CCH FFFFH   —  APNOT1 Analog port NOT register 1 16 15-0 W 07CCH 0000H   —  APMSR1 Analog port mode Set/reset register 1 32 31-16, 15-0 R/W 08CCH 0000 FFFFH   —  APIBC1 Analog port input buffer control register 1 16 15-0 R/W 40CCH 0000H   —  APBDC1 Analog port bidirection control register 1 16 15-0 R/W 41CCH 0000H   —  Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 235 of 4535 Dec 26, 2018 2A.10.21 Input Port 0 (IP0) 2A.10.21.1 Alternative Function Table 2A.79 Input Port 0 (IP0) Port Mode Alternative Mode ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 176 Pins 233 Pins 272 Pins 324 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output IP0_0 XT2 57 T7 — AA8

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 236 of 4535 Dec 26, 2018 2A.10.21.2 Control Registers Table 2A.80 Control Registers (IP0) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 176 Pins 233 Pins 272 Pins 324 Pins IPPR0 Input port pin read register 0 16 0 R 02F0H 0000H   —  IPIBC0 Port input buffer control register 0 16 0 R/W 40F0H 0000H   —  Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset. CAUTION When the IP0_0/XT2 pin is used as an input port, set the IPIBC0.0 bit to 1 and stop the SOSC operation. For details on the settings for SOSC operations, see Section 12AB.4.2.7, SOSCE — SubOSC Enable Register. When the IP0_0/XT2 pin is used for the SubOSC (SOSC) not as an input port, set the IPIBC0.0 bit to 0.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 237 of 4535 Dec 26, 2018 2A.11 Port (Special I/O) Function Overview This section describes the port (special I/O) functions. 2A.11.1 Special I/O after Reset The special port function after reset is deasserted is shown below. 2A.11.1.1 P8_6: RESETOUT The P8_6 pin ( RESETOUT signal) changes PM8.PM8_6 and PODC8.PODC8_6 registers value after reset by OPBT0.RESETOUTEN setting. The P8_6 pin outputs a low level while a reset is asserted, and pin status of after the reset is different. (Case 1): OPBT0.RESETOUTEN = 1

• P8.P8_6 = 0: Outputs low level
• PM8.PM8_6 = 0: Output mode
• PODC8.PODC8_6 = 1: Open-drain (Case 2): OPBT0.RESETOUTEN = 0
• P8.P8_6 = 0: Outputs low level
• PM8.PM8_6 = 1: Input mode
• PODC8.PODC8_6 = 0: Push-pull For detail of OPBT0.RESETOUTEN register, see Section 44.9.2, OPBT0 — Option Byte 0, also see Section 9A.1.3, Reset Output ( RESETOUT ).

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 238 of 4535 Dec 26, 2018 When the P8_6 pin setting is updated with another value, the pin operates by new setting. EVCC/ REG0VCC/ REG1VCC RESET Flash Operation P8_6 RESETOUT RESETOUT enable P8_6 was set to1. General purpose I/O P8_6 is changed to Low output by resets. RESETOUT enable Execution of user program started. Transferred data (OPBT0.RESETOUTEN=1) Reset is asserted Flash sequence Flash sequence RESETOUT Figure 2A.10 P8_6 Pin ( RESETOUT Signal) Operation While a Reset is asserted and released: (Case 1) OPBT0.RESETOUTEN setting is 1

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 239 of 4535 Dec 26, 2018 EVCC/ REG0VCC/ REG1VCC RESET Flash Operation Flash sequence P8_6 RESETOUT RESETOUT disable P8_6 was set to1. General purpose I/O P8_6 is changed to Hi-z by resets. Execution of user program started. Reset is asserted. Flash sequence RESETOUT disable Hi-z Hi-z Transferred data (OPBT0.RESETOUTEN=0) (*1) General purpose I/O P8_6 was set to1. RESETOUT Power lowered POC RESET is asserted. P8_6 is changed to Low output by resets. Note 1. When a reset except POC reset occurs with RESETOUT disable (OPBT0.RESETOUTEN = 0), P8_6 pin ( RESETOUT signal) will be changed to Hi-z. Figure 2A.11 P8_6 Pin ( RESETOUT Signal) Operation While a Reset is asserted and released: (Case 2) OPBT0.RESETOUTEN setting is 0

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 240 of 4535 Dec 26, 2018 2A.11.1.2 JP0_0 to JP0_6: Debug Interface If the OPJTAG[1:0] setting is the combination below, the pins of the JTAG port group can be used as a debug interface after reset release. Table 2A.81 Debug Interface OPJTAG1 OPJTAG0 Mode JP0_0 JP0_1 JP0_2 JP0_3 JP0_4 JP0_5 JP0_6 1 1 Nexus I/F DCUTDI input DCUTDO output DCUTCK input DCUTMS input DCUTRST input DCURDY output EVTO output 0 1 LPD (4 pins) LPDI input LPDO output LPDCLK input Port/ alternative function Port/ alternative function LPDCLK OUT output Port/ alternative function 1 0 LPD (1 pin) LPDIO input/output Port/ alternative function Port/ alternative function Port/ alternative function Port/ alternative function Port/ alternative function Port/ alternative function NOTE For the OPJTAG [1:0] settings, see Section 44.9.2, OPBT0 — Option Byte 0. 2A.11.1.3 FPDR(JP0_0), FPDT(JP0_1), FPCK(JP0_2): Flash Programmer These pins are used for connecting a flash programmer. See Flash Programmer's Manual for details. 2A.11.1.4 Mode Pins The FLMD0 pin in combination with the P10_8: FLMD1 pin can select serial programming mode. The FLMD0 pin in combination with the P10_8: FLMD1, the P10_2: MODE1 and the P10_1: MODE0 pins can select boundary scan mode. The FLMD0 pin in combination with the P10_8: FLMD1, the P10_6: MODE2, the P10_2: MODE1 and the P10_1: MODE0 pins can select user boot mode. For details on the mode selection, see Section 6, Operating Mode. 2A.11.1.5 IP0_0: XT2 This pin is the SubOSC (SOSC) input pin. When the IPIBC0_0 bit = 1, the IP0_0/XT2 pin is used as an input port. If you make this setting, stop SOSC operation at the same time.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 241 of 4535 Dec 26, 2018 2A.11.2 A/D Input Alternative I/O The following ports are permanently connected to A/D input functions. (However, an analog input to the A/D is controlled by the A/D module.) Table 2A.82 A/D Input Alternative Pins Port A/D Input Device

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 242 of 4535 Dec 26, 2018 Table 2A.82 A/D Input Alternative Pins Port A/D Input Device

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 243 of 4535 Dec 26, 2018 2A.11.3 Special I/O Control 2A.11.3.1 Direct I/O Control (PIPC) Some alternative functions take over the input and output control of the ports. The following table lists all alternative functions where PIPCn.PIPCn_m must be set to 1. For details, see Section 2A.9.2.3, PIPCn — Port IP Control Register. Table 2A.83 Alternative Modes that Require Setting PIPCn.PIPCn_m = 1 Function Alternative functions Name Port Name Power Supply Area Control Reference Section MEMC MEMC0AD0 P10_6 ISO Section 16 MEMC0AD1 P10_7 ISO MEMC0AD2 P10_8 ISO MEMC0AD3 P10_9 ISO MEMC0AD4 P10_10 ISO MEMC0AD5 P10_11 ISO MEMC0AD6 P10_12 ISO MEMC0AD7 P10_13 ISO MEMC0AD8 P10_14 ISO MEMC0AD9 P11_1 ISO MEMC0AD10 P11_2 ISO MEMC0AD11 P11_3 ISO MEMC0AD12 P11_4 ISO MEMC0AD13 P11_5 ISO MEMC0AD14 P11_6 ISO MEMC0AD15 P11_7 ISO TAPA TAPA0UP P10_0 ISO U phase Hi-Z control Section 36 TAPA0UN P10_1 ISO TAPA0VP P10_2 ISO V phase Hi-Z control TAPA0VN P10_3 ISO TAPA0WP P10_4 ISO W phase Hi-Z control TAPA0WN P10_5 ISO CSIG CSIG0SO P0_13 AWO Serial data output control signal Section 19 P10_6 ISO CSIG0SC P0_14 AWO Master (1) / slave (0) mode signal P10_7 ISO CSIG1SO P11_9 ISO Serial data output control signal CSIG1SC P11_10 ISO Master (1) / slave (0) mode signal CSIG2SO P12_5 ISO Serial data output control signal CSIG2SC P12_4 ISO Master (1) / slave (0) mode signal CSIG3SO P20_1 ISO Serial data output control signal CSIG3SC P20_2 ISO Master (1) / slave (0) mode signal CSIG4SO P1_3 AWO Serial data output control signal P23_6 ISO CSIG4SC P1_1 AWO Master (1) / slave (0) mode signal P23_8 ISO

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 244 of 4535 Dec 26, 2018 Table 2A.83 Alternative Modes that Require Setting PIPCn.PIPCn_m = 1 Function Alternative functions Name Port Name Power Supply Area Control Reference Section CSIH CSIH0SO P0_3 AWO Serial data output control signal Section 20 CSIH0SC P0_2 AWO Master (1) / slave (0) mode signal CSIH1SO P0_5 AWO Serial data output control signal P10_2 ISO CSIH1SC P0_6 AWO Master (1) / slave (0) mode signal P10_1 ISO CSIH2SO P11_2 ISO Serial data output control signal CSIH2SC P11_3 ISO Master (1) / slave (0) mode signal CSIH3SO P11_6 ISO Serial data output control signal CSIH3SC P11_7 ISO Master (1) / slave (0) mode signal CSIH4SO P2_4 AWO Serial data output control signal P23_1 ISO CSIH4SC P1_5 AWO Master (1) / slave (0) mode signal P23_3 ISO SFMA SFMA0IO0 P11_5 ISO SPIch.0 MOSI0_IO00 output enable Section 17 SFMA0IO1 P11_4 ISO SPIch.0 MOSI0_IO10 output enable SFMA0IO2 P11_3 ISO SPIch.0 IO20 output enable SFMA0IO3 P11_2 ISO SPIch.0 IO30 output enable ETNB ETNB0MDIO P12_4 ISO MDIO output enable Section 26 ETNB1MDIO P21_7 ISO MDIO output enable MMCA MMCA0CMD P22_7 ISO MMCA0CMD output enable Section 18 MMCA0DAT0 P22_9 ISO MMCA0DAT0 output enable MMCA0DAT1 P22_10 ISO MMCA0DAT1 output enable MMCA0DAT2 P22_11 ISO MMCA0DAT2 output enable MMCA0DAT3 P22_12 ISO MMCA0DAT3 output enable MMCA0DAT4 P22_13 ISO MMCA0DAT4 output enable MMCA0DAT5 P22_14 ISO MMCA0DAT5 output enable MMCA0DAT6 P22_15 ISO MMCA0DAT6 output enable MMCA0DAT7 P21_1 ISO MMCA0DAT7 output enable

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 245 of 4535 Dec 26, 2018 2A.11.3.2 Input Buffer Control (PISn/JPIS0, PISAn/JPISA0) The port input buffer characteristics (Type 1 or Type 2) of this device can be selected using the PISn/PISAn/JPIS0 register. The applicable pins are shown in the following table. The JTAG port input buffer characteristics (Type 1/2 or Type 5) of this device can be selected using the JPISA0 register. The applicable pins are shown in Table 2A.85, JTAG Port Input Buffer Characteristics Selection. Table 2A.84 Port Input Buffer Characteristics Selection Port Name Input Buffer Selection Device Type 1 (PISn_m = 0 & PISAn_m = 0) Type 2 (PISn_m = 1 & PISAn_m = 0) Type 5 (PISAn_m = 1) 176 Pins 233 Pins 272 Pins 324 Pins

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 246 of 4535 Dec 26, 2018 Table 2A.84 Port Input Buffer Characteristics Selection Port Name Input Buffer Selection Device Type 1 (PISn_m = 0 & PISAn_m = 0) Type 2 (PISn_m = 1 & PISAn_m = 0) Type 5 (PISAn_m = 1) 176 Pins 233 Pins 272 Pins 324 Pins P10_0 SHMT1 SHMT4 TTL   —  P10_1 SHMT1 SHMT4 TTL   — 

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 247 of 4535 Dec 26, 2018 Table 2A.84 Port Input Buffer Characteristics Selection Port Name Input Buffer Selection Device Type 1 (PISn_m = 0 & PISAn_m = 0) Type 2 (PISn_m = 1 & PISAn_m = 0) Type 5 (PISAn_m = 1) 176 Pins 233 Pins 272 Pins 324 Pins P10_2 SHMT1 SHMT4 TTL   —  P10_4 SHMT1 SHMT4 TTL   —  P10_5 SHMT1 SHMT4 TTL   —  P11_10 SHMT1 SHMT4 TTL   —  P11_11 SHMT1 SHMT4 TTL   —  P11_12 SHMT1 SHMT4 TTL   —  P11_15 SHMT1 SHMT4 TTL   —  P12_4 SHMT1 SHMT4 TTL   —  P13_2 SHMT1 SHMT4 TTL —  —  P13_3 SHMT1 SHMT4 TTL —  — 

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 248 of 4535 Dec 26, 2018 Table 2A.84 Port Input Buffer Characteristics Selection Port Name Input Buffer Selection Device Type 1 (PISn_m = 0 & PISAn_m = 0) Type 2 (PISn_m = 1 & PISAn_m = 0) Type 5 (PISAn_m = 1) 176 Pins 233 Pins 272 Pins 324 Pins TTL — — —  P13_5 SHMT1 SHMT4 TTL —  —  P18_0 SHMT1 SHMT4 TTL   —  P18_7 SHMT1 SHMT4 TTL   —  P18_8 SHMT1 SHMT4 TTL —  —  P18_9 SHMT1 SHMT4 TTL —  — 

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 249 of 4535 Dec 26, 2018 Table 2A.84 Port Input Buffer Characteristics Selection Port Name Input Buffer Selection Device Type 1 (PISn_m = 0 & PISAn_m = 0) Type 2 (PISn_m = 1 & PISAn_m = 0) Type 5 (PISAn_m = 1) 176 Pins 233 Pins 272 Pins 324 Pins TTL — — —  TTL — — —  TTL — — —  TTL — — —  P21_5 SHMT1 SHMT4 TTL — — —  P21_7 SHMT1 SHMT4 TTL — — —  P21_8 SHMT1 SHMT4 TTL — — —  P21_9 SHMT1 SHMT4 TTL — — —  P21_10 SHMT1 SHMT4 TTL — — —  TTL — — —  TTL — — — 

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 250 of 4535 Dec 26, 2018 Table 2A.84 Port Input Buffer Characteristics Selection Port Name Input Buffer Selection Device Type 1 (PISn_m = 0 & PISAn_m = 0) Type 2 (PISn_m = 1 & PISAn_m = 0) Type 5 (PISAn_m = 1) 176 Pins 233 Pins 272 Pins 324 Pins

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 251 of 4535 Dec 26, 2018 Table 2A.85 JTAG Port Input Buffer Characteristics Selection Port Name Input Buffer Selection Devices Type 1 (JPIS0_m = 0 & JPISA0_m = 0) Type 2 (JPIS0_m = 1 & JPISA0_m = 0) Type 5 (JPISA0_m = 1) 176 Pins 233 Pins 272 Pins 324 Pins Note 1. TTL is selected for Boundary scan mode without JPISA0 register setting. Note 2. TTL is selected for Nexus in normal operating mode without JPISA0 register setting. Note 3. TTL is selected for LPD (4 pins) in normal operating mode without JPISA0 register setting. Note 4. TTL is selected for LPD (1 pin) in normal operating mode without JPISA0 register setting. NOTES 1. For the SHMT1, SHMT4 and TTL pin characteristics, see Section 47A, Electrical Characteristics of RH850/F1KH-D8. 2. For the input buffer after reset, Type 2 (SHMT4) is selected.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 252 of 4535 Dec 26, 2018 2A.11.3.3 Output Buffer Control (PDSC) The port output driver strength (slow mode/fast mode) can be selected using the PDSCn register. The applicable pins are shown in the following table. Only slow mode is supported for ports other than those listed below. Table 2A.86 Output Buffer Characteristics Selection Port Name Output Drive Strength Selection Device Slow Mode (PDSCn_m = 0) Fast Mode (PDSCn_m = 1) 176 Pins 233 Pins 272 Pins 324 Pins JP0_1 10 MHz 40 MHz   —  JP0_2 10 MHz 40 MHz   —  JP0_3 10 MHz 40 MHz   —  JP0_5 10 MHz 40 MHz   —  JP0_6 10 MHz 40 MHz   —  P0_0 10 MHz 40 MHz   —  P0_1 10 MHz 40 MHz   —  P0_4 10 MHz 40 MHz   —  P0_7 10 MHz 40 MHz   —  P0_8 10 MHz 40 MHz   —  P0_9 10 MHz 40 MHz   —  P0_10 10 MHz 40 MHz   —  P0_11 10 MHz 40 MHz   —  P0_12 10 MHz 40 MHz   —  P0_13 10 MHz 40 MHz   —  P0_14 10 MHz 40 MHz   —  P1_0 10 MHz 40 MHz   —  P1_1 10 MHz 40 MHz   —  P1_2 10 MHz 40 MHz   —  P1_3 10 MHz 40 MHz   —  P1_4 10 MHz 40 MHz   —  P1_8 10 MHz 40 MHz   —  P1_9 10 MHz 40 MHz   —  P1_10 10 MHz 40 MHz   —  P1_11 10 MHz 40 MHz   —  P1_12 10 MHz 40 MHz   —  P1_13 10 MHz 40 MHz   —  P1_14 10 MHz 40 MHz   —  P1_15 10 MHz 40 MHz   —  P2_0 10 MHz 40 MHz   —  P2_1 10 MHz 40 MHz   —  P2_2 10 MHz 40 MHz   —  P2_3 10 MHz 40 MHz   —  P2_5 10 MHz 40 MHz   — 

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 253 of 4535 Dec 26, 2018 Table 2A.86 Output Buffer Characteristics Selection Port Name Output Drive Strength Selection Device Slow Mode (PDSCn_m = 0) Fast Mode (PDSCn_m = 1) 176 Pins 233 Pins 272 Pins 324 Pins P2_6 10 MHz 40 MHz   —  P2_7 10 MHz 40 MHz ―  —  P2_8 10 MHz 40 MHz ―  —  P2_9 10 MHz 40 MHz ―  —  P2_10 10 MHz 40 MHz ―  —  P2_11 10 MHz 40 MHz ―  —  P2_12 10 MHz 40 MHz ―  —  P2_13 10 MHz 40 MHz ―  —  P2_14 10 MHz 40 MHz ―  —  P2_15 10 MHz 40 MHz ―  —  P3_0 10 MHz 40 MHz ―  —  P3_1 10 MHz 40 MHz ― ― —  P3_2 10 MHz 40 MHz ― ― —  P3_3 10 MHz 40 MHz ― ― —  P3_4 10 MHz 40 MHz ― ― —  P3_5 10 MHz 40 MHz ― ― —  P3_6 10 MHz 40 MHz ― ― —  P3_7 10 MHz 40 MHz ― ― —  P3_8 10 MHz 40 MHz ― ― —  P3_9 10 MHz 40 MHz ― ― —  P3_10 10 MHz 40 MHz ― ― —  P3_11 10 MHz 40 MHz ― ― ―  P3_12 10 MHz 40 MHz ― ― ―  P10_0 10 MHz 40 MHz   —  P10_3 10 MHz 40 MHz   —  P10_4 10 MHz 40 MHz   —  P10_5 10 MHz 40 MHz   —  P10_6 10 MHz 40 MHz   —  P10_7 10 MHz 40 MHz   —  P10_8 10 MHz 40 MHz   —  P10_9 10 MHz 40 MHz   —  P10_10 10 MHz 40 MHz   —  P10_11 10 MHz 40 MHz   —  P10_12 10 MHz 40 MHz   —  P10_13 10 MHz 40 MHz   —  P10_14 10 MHz 40 MHz   —  P10_15 10 MHz 40 MHz   —  P11_0 10 MHz 40 MHz   —  P11_1 10 MHz 40 MHz   — 

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 254 of 4535 Dec 26, 2018 Table 2A.86 Output Buffer Characteristics Selection Port Name Output Drive Strength Selection Device Slow Mode (PDSCn_m = 0) Fast Mode (PDSCn_m = 1) 176 Pins 233 Pins 272 Pins 324 Pins P11_4 10 MHz 40 MHz   —  P11_5 10 MHz 40 MHz   —  P11_8 10 MHz 40 MHz   —  P11_9 10 MHz 40 MHz   —  P11_10 10 MHz 40 MHz   —  P11_11 10 MHz 40 MHz   —  P11_12 10 MHz 40 MHz   —  P11_15 10 MHz 40 MHz   —  P12_0 10 MHz 40 MHz   —  P12_1 10 MHz 40 MHz   —  P12_2 10 MHz 40 MHz   —  P12_3 10 MHz 40 MHz   —  P12_4 10 MHz 40 MHz   —  P12_5 10 MHz 40 MHz   —  P13_0 10 MHz 40 MHz ―  —  P13_1 10 MHz 40 MHz ―  —  P13_2 10 MHz 40 MHz ―  —  P13_3 10 MHz 40 MHz ―  —  P13_4 10 MHz 40 MHz ―  —  P13_5 10 MHz 40 MHz ―  —  P13_6 10 MHz 40 MHz ―  —  P13_7 10 MHz 40 MHz ―  —  P18_0 10 MHz 40 MHz   —  P18_1 10 MHz 40 MHz   —  P18_2 10 MHz 40 MHz   —  P18_3 10 MHz 40 MHz   —  P18_4 10 MHz 40 MHz   —  P18_5 10 MHz 40 MHz   —  P18_6 10 MHz 40 MHz   —  P18_7 10 MHz 40 MHz   —  P18_8 10 MHz 40 MHz ―  —  P18_9 10 MHz 40 MHz ―  —  P18_10 10 MHz 40 MHz ―  —  P18_11 10 MHz 40 MHz ―  —  P18_12 10 MHz 40 MHz ―  —  P18_13 10 MHz 40 MHz ―  —  P18_14 10 MHz 40 MHz ―  —  P18_15 10 MHz 40 MHz ―  —  P19_0 10 MHz 40 MHz ―  —  P19_1 10 MHz 40 MHz ―  —  P19_2 10 MHz 40 MHz ―  — 

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 255 of 4535 Dec 26, 2018 Table 2A.86 Output Buffer Characteristics Selection Port Name Output Drive Strength Selection Device Slow Mode (PDSCn_m = 0) Fast Mode (PDSCn_m = 1) 176 Pins 233 Pins 272 Pins 324 Pins P19_3 10 MHz 40 MHz ―  —  P20_0 10 MHz 40 MHz   —  P20_1 10 MHz 40 MHz   —  P20_2 10 MHz 40 MHz   —  P20_3 10 MHz 40 MHz   —  P20_4 10 MHz 40 MHz   —  P20_5 10 MHz 40 MHz   —  P20_6 10 MHz 40 MHz ― ― —  P20_7 10 MHz 40 MHz ― ― —  P20_8 10 MHz 40 MHz ― ― —  P20_9 10 MHz 40 MHz ― ― —  P20_10 10 MHz 40 MHz ― ― —  P20_11 10 MHz 40 MHz ― ― —  P20_12 10 MHz 40 MHz ― ― —  P20_13 10 MHz 40 MHz ― ― —  P20_14 10 MHz 40 MHz ― ― —  P20_15 10 MHz 40 MHz ― ― ―  P21_0 10 MHz 40 MHz ― ― ―  P21_1 10 MHz 40 MHz ― ― ―  P21_2 10 MHz 40 MHz ― ― ―  P21_3 10 MHz 40 MHz ― ― ―  P21_4 10 MHz 40 MHz ― ― ―  P21_5 10 MHz 40 MHz ― ― ―  P21_6 10 MHz 40 MHz ― ― ―  P21_7 10 MHz 40 MHz ― ― ―  P21_8 10 MHz 40 MHz ― ― ―  P21_9 10 MHz 40 MHz ― ― ―  P21_10 10 MHz 40 MHz ― ― ―  P21_11 10 MHz 40 MHz ― ― ―  P21_12 10 MHz 40 MHz ― ― ―  P21_13 10 MHz 40 MHz ― ― ―  P21_14 10 MHz 40 MHz ― ― ―  P22_0 10 MHz 40 MHz ― ― ―  P22_1 10 MHz 40 MHz ― ― ―  P22_2 10 MHz 40 MHz ― ― ―  P22_3 10 MHz 40 MHz ― ― ―  P22_4 10 MHz 40 MHz ― ― ―  P22_5 10 MHz 40 MHz ― ― ―  P22_6 10 MHz 40 MHz ― ― ―  P22_7 10 MHz 40 MHz ― ― ―  P22_8 10 MHz 40 MHz ― ― ―  P22_9 10 MHz 40 MHz ― ― ―  P22_10 10 MHz 40 MHz ― ― ― 

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 256 of 4535 Dec 26, 2018 Table 2A.86 Output Buffer Characteristics Selection Port Name Output Drive Strength Selection Device Slow Mode (PDSCn_m = 0) Fast Mode (PDSCn_m = 1) 176 Pins 233 Pins 272 Pins 324 Pins P22_11 10 MHz 40 MHz ― ― ―  P22_12 10 MHz 40 MHz ― ― ―  P22_13 10 MHz 40 MHz ― ― ―  P22_14 10 MHz 40 MHz ― ― ―  P22_15 10 MHz 40 MHz ― ― ―  P23_0 10 MHz 40 MHz ― ― ―  P23_2 10 MHz 40 MHz ― ― ―  P23_4 10 MHz 40 MHz ― ― ―  P23_5 10 MHz 40 MHz ― ― ―  P23_6 10 MHz 40 MHz ― ― ―  P23_7 10 MHz 40 MHz ― ― ―  P23_8 10 MHz 40 MHz ― ― ―  P23_9 10 MHz 40 MHz ― ― ―  P23_10 10 MHz 40 MHz ― ― ―  P24_0 10 MHz 40 MHz ― ― ―  P24_1 10 MHz 40 MHz ― ― ―  P24_2 10 MHz 40 MHz ― ― ―  P24_3 10 MHz 40 MHz ― ― ―  P24_4 10 MHz 40 MHz ― ― ―  P24_5 10 MHz 40 MHz ― ― ―  P24_6 10 MHz 40 MHz ― ― ―  P24_7 10 MHz 40 MHz ― ― ―  Note 1. Supports Cload: 100 pF (The load capacitance of CSIH0 is 100 pF.) Note 2. Supports Cload: 50 pF (The load capacitance of CSIH1 to CSIH4 are 50 pF.) Note 3. In some of the functions, Fast mode or Slow mode is specified. For details, see Section 47A.5, AC Characteristics.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 257 of 4535 Dec 26, 2018 2A.12 Noise Filter & Edge/Level Detector The input signals at some pins are passed through a filter to remove noise and glitches. The RH850/F1KH supports both analog and digital filters. It also supports the function for edge and level detection after the signals have passed through a filter. The first part of this section provides an overview of port input pins that are equipped with a filter and the filter type, noise filter & edge/level detection control registers and control bits, and register addresses. For details on the digital/analog filter function and noise filter & edge/level detection control registers, see Section 2A.13, Description of Port Noise Filter & Edge/Level Detection. NOTE In this section, <name> in the noise filter control register represents the peripheral function connected to a filter. 2A.12.1 Port Filter Assignment A list of the input pins that incorporate an analog or digital filter is provided below. 2A.12.1.1 Input Pins that Incorporate Analog Filter Type A The input pins of analog filter type A incorporate an analog filter and edge/level detection functio n. Edge/level detection is controlled by the following registers.

• Filter control register FCLA0CTLm_<name> (m = 0 to 7) A dedicated FCLA0CTLm_<name> register is provided for each pin in a port that incorporates an analog filter. Table 2A.87 Input Pins that Incorporate Analog Filter Type A Module Name Input Pin FCLA0CTL Register Configuration Device Register Address 176 Pins 233 Pins 272 Pins 324 Pins FCLA0 NMI FCLA0CTL0_NMI FFC3 4000H   —  INTP0 FCLA0CTL0_INTPL FFC3 4020H   —  INTP1 FCLA0CTL1_INTPL FFC3 4024H   —  INTP2 FCLA0CTL2_INTPL FFC3 4028H   —  INTP3 FCLA0CTL3_INTPL FFC3 402CH   —  INTP4 FCLA0CTL4_INTPL FFC3 4030H   —  INTP5 FCLA0CTL5_INTPL FFC3 4034H   —  INTP6 FCLA0CTL6_INTPL FFC3 4038H   —  INTP7 FCLA0CTL7_INTPL FFC3 403CH   —  INTP8 FCLA0CTL0_INTPH FFC3 4040H   —  INTP9 FCLA0CTL1_INTPH FFC3 4044H   —  INTP10 FCLA0CTL2_INTPH FFC3 4048H   —  INTP11 FCLA0CTL3_INTPH FFC3 404CH   —  INTP12 FCLA0CTL4_INTPH FFC3 4050H   —  INTP13 FCLA0CTL5_INTPH FFC3 4054H   —  INTP14 FCLA0CTL6_INTPH FFC3 4058H   —  INTP15 FCLA0CTL7_INTPH FFC3 405CH   —  INTP16 FCLA0CTL0_INTPU FFC3 40A0H   —  INTP17 FCLA0CTL1_INTPU FFC3 40A4H   — 

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 258 of 4535 Dec 26, 2018 Table 2A.87 Input Pins that Incorporate Analog Filter Type A Module Name Input Pin FCLA0CTL Register Configuration Device Register Address 176 Pins 233 Pins 272 Pins 324 Pins FCLA0 INTP18 FCLA0CTL2_INTPU FFC3 40A8H   —  INTP19 FCLA0CTL3_INTPU FFC3 40ACH   —  INTP20 FCLA0CTL4_INTPU FFC3 40B0H   —  INTP21 FCLA0CTL5_INTPU FFC3 40B4H   —  INTP22 FCLA0CTL6_INTPU FFC3 40B8H   —  INTP23 FCLA0CTL7_INTPU FFC3 40BCH   —  2A.12.1.2 Input Pins that Incorporate Analog Filter Type B The input pins of analog filter type B incorporate an analog filter. Edge/level detection is controlled by the registers for individual peripheral functions. Table 2A.88 Input Pins that Incorporate Analog Filter Type B Input Pin Edge/Level Detection Device TAUJ0I0 Edge detection*1   —  TAUJ0I1 Edge detection*1   —  TAUJ0I2 Edge detection*1   —  TAUJ0I3 Edge detection*1   —  TAUJ1I0 Edge detection*1   —  TAUJ1I1 Edge detection*1   —  TAUJ1I2 Edge detection*1   —  TAUJ1I3 Edge detection*1   —  TAUJ2I0 Edge detection*1   —  TAUJ2I1 Edge detection*1   —  TAUJ2I2 Edge detection*1   —  TAUJ2I3 Edge detection*1   —  TAUJ3I0 Edge detection*1   —  TAUJ3I1 Edge detection*1   —  TAUJ3I2 Edge detection*1   —  TAUJ3I3 Edge detection*1   —  TAPA0ESO Edge detection*2   —  KR0I0 Low level detection   —  KR0I1 Low level detection   —  KR0I2 Low level detection   —  KR0I3 Low level detection   —  KR0I4 Low level detection   —  KR0I5 Low level detection   —  KR0I6 Low level detection   —  KR0I7 Low level detection   —  Note 2. For details on edge detection for TAPA, see Section 36.3.2, TAPAnCTL0 — TAPA Control Register 0.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 259 of 4535 Dec 26, 2018 2A.12.1.3 Input Pins that Incorporate Analog Filter Type C The input pins of analog filter type C only incorporate an analog filter function. Table 2A.89 Input Pins that Incorporate Analog Filter Type C Input Pin FLMD0 FLMD1 MODE0 MODE1 MODE2 RESET DCUTRST

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 260 of 4535 Dec 26, 2018 2A.12.1.4 Input Pins that Incorporate Digital Filter Type D The input pins of digital filter type D incorporate a digital filter and edge detection function. The digital filter and edge detection are controlled by the following registers.

• Filter control register FCLA0CTLm_<name> (m = 0 to 2) Each port with a digital filter has a special FCLA0CTLm_<name> register.
• Digital noise elimination control register DNFA<name>CTL Each DNFA<name>CTL control register controls digital filter processing for three input signals per group.
• Digital noise elimination enable register DNFA<name>EN The setting of the DNFA<name>ENL[2:0] bits in DNFA<name>EN enables or disables digital noise elimination for three input signals per group. Table 2A.90 Input Pins that Incorporate Digital Filter Type D Input Pin Device Digital Noise Elimination Control Register Digital Noise Elimination Enable Register Filter Control Register 176 Pins 233 Pins 272 Pins 324 Pins Control Register Address Control Register Control Bit Address Control Register Address ADCA0TRG0   —  DNFAADCTL0CTL FFC3 00A0H DNFAADCTL0EN (DNFAADCTL0ENL) DNFAADCTL0ENL0 FFC3 00A4H (FFC3 00ACH) FCLA0CTL0 _ADC0 FFC3 4060H ADCA0TRG1   —  DNFAADCTL0ENL1 FCLA0CTL1 _ADC0 FFC3 4064H ADCA0TRG2   —  DNFAADCTL0ENL2 FCLA0CTL2 _ADC0 FFC3 4068 H ADCA1TRG0   —  DNFAADCTL1CTL FFC3 00C0H DNFAADCTL1EN (DNFAADCTL1ENL) DNFAADCTL1ENL0 FFC3 00C4H (FFC3 00CCH) FCLA0CTL0 _ADC1 FFC3 4080H ADCA1TRG1   —  DNFAADCTL1ENL1 FCLA0CTL1 _ADC1 FFC3 4084H ADCA1TRG2   —  DNFAADCTL1ENL2 FCLA0CTL2 _ADC1 FFC3 4088H

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 261 of 4535 Dec 26, 2018 2A.12.1.5 Input Pins that Incorporate Digital Filter Type E The input pins of digital filter type E incorporate a digital filter. The digital filter is controlled by the follow ing registers. Edge detection is controlled by the registers for individual peripheral functions.

• Digital noise elimination control register DNFA<name>CTL Each DNFA<name>CTL control register controls digital filter processing for up to 16 input signals per group.
• Digital noise elimination enable register DNFA<name>EN The setting of the DNFA<name>ENL[7:0] and DNFA<name>ENH[7:0] bits in DNFA<name>EN enables or disables digital noise elimination for up to 16 input signals per group. Table 2A.91 Input Pins that Incorporate Digital Filter Type E Input Pin Devises Digital Noise Elimination Control Register Digital Noise Elimination Enable Register Edge Detection 176 Pins 233 Pins 272 Pins 324 Pins Control Register Address Control Register Control Bit Address Register Name TAUD0I0   —  DNFATAUD0ICTL FFC3 0000H DNFATAUD0IEN (DNFATAUD0IENH/ DNFATAUD0IENL) DNFATAUD0IENL0 FFC3 0004H (FFC3 0008H/ FFC3 000CH) TAUD0I1   —  DNFATAUD0IENL1 TAUD0I2   —  DNFATAUD0IENL2 TAUD0I3   —  DNFATAUD0IENL3 TAUD0I4   —  DNFATAUD0IENL4 TAUD0I5   —  DNFATAUD0IENL5 TAUD0I6   —  DNFATAUD0IENL6 TAUD0I7   —  DNFATAUD0IENL7 TAUD0I8   —  DNFATAUD0IENH0 TAUD0I9   —  DNFATAUD0IENH1 TAUD0I10   —  DNFATAUD0IENH2 TAUD0I11   —  DNFATAUD0IENH3 TAUD0I12   —  DNFATAUD0IENH4 TAUD0I13   —  DNFATAUD0IENH5 TAUD0I14   —  DNFATAUD0IENH6 TAUD0I15   —  DNFATAUD0IENH7 TAUB0I0   —  DNFATAUB0ICTL FFC3 0020H DNFATAUB0IEN (DNFATAUB0IENH/ DNFATAUB0IENL) DNFATAUB0IENL0 FFC3 0024H (FFC3 0028H/ FFC3 002CH) TAUB0I1   —  DNFATAUB0IENL1 TAUB0I2   —  DNFATAUB0IENL2 TAUB0I3   —  DNFATAUB0IENL3 TAUB0I4   —  DNFATAUB0IENL4 TAUB0I5   —  DNFATAUB0IENL5 TAUB0I6   —  DNFATAUB0IENL6 TAUB0I7   —  DNFATAUB0IENL7 TAUB0I8   —  DNFATAUB0IENH0 TAUB0I9   —  DNFATAUB0IENH1 TAUB0I10   —  DNFATAUB0IENH2 TAUB0I11   —  DNFATAUB0IENH3 TAUB0I12   —  DNFATAUB0IENH4 TAUB0I13   —  DNFATAUB0IENH5 TAUB0I14   —  DNFATAUB0IENH6 TAUB0I15   —  DNFATAUB0IENH7

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 262 of 4535 Dec 26, 2018 Table 2A.91 Input Pins that Incorporate Digital Filter Type E Input Pin Devises Digital Noise Elimination Control Register Digital Noise Elimination Enable Register Edge Detection 176 Pins 233 Pins 272 Pins 324 Pins Control Register Address Control Register Control Bit Address Register Name TAUB1I0   —  DNFATAUB1ICTL FFC3 0040H DNFATAUB1IEN (DNFATAUB1IENH/ DNFATAUB1IENL) DNFATAUB1IENL0 FFC3 0044H (FFC3 0048H/ FFC3 004CH) TAUB1I1   —  DNFATAUB1IENL1 TAUB1I2   —  DNFATAUB1IENL2 TAUB1I3   —  DNFATAUB1IENL3 TAUB1I4   —  DNFATAUB1IENL4 TAUB1I5   —  DNFATAUB1IENL5 TAUB1I6   —  DNFATAUB1IENL6 TAUB1I7   —  DNFATAUB1IENL7 TAUB1I8   —  DNFATAUB1IENH0 TAUB1I9   —  DNFATAUB1IENH1 TAUB1I10   —  DNFATAUB1IENH2 TAUB1I11   —  DNFATAUB1IENH3 TAUB1I12   —  DNFATAUB1IENH4 TAUB1I13   —  DNFATAUB1IENH5 TAUB1I14   —  DNFATAUB1IENH6 TAUB1I15   —  DNFATAUB1IENH7 ENCA0TIN0   —  DNFAENCA0ICTL FFC3 0060H DNFAENCA0IEN (DNFAENCA0IENL) DNFAENCA0IENL0 FFC3 0064H (FFC3 006CH) ENCA0TIN1   —  DNFAENCA0IENL1 ENCA0E0   —  DNFAENCA0IENL2 ENCA0E1   —  DNFAENCA0IENL3 ENCA0EC   —  DNFAENCA0IENL4 SENT0RX   —  DNFASENTICTL FFC3 00E0H DNFASENTIEN (DNFASENTIENL) DNFASENTIENL0 FFC3 00E4H (FFC3 00ECH) —*4 SENT1RX   —  DNFASENTIENL1 Note 3. For the setting for ENCA edge detection, see Section 35.3.3, ENCAnIOC0 — ENCAn I/O Control Register 0. Note 4. RSENT does not have the edge detection.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 263 of 4535 Dec 26, 2018 2A.12.2 Clock Supply for Port Filters The following table shows the clock supply for each filter type in each port domain. Table 2A.92 Clock Supply for Port Filters Peripheral Function Port Domain*1 Filter Type Filter Clock Setting Register Source Clock Selection Clock Selection ADCA0 Always-On area (AWO area) Digital filter type D DNFATCKI CKSC_AADCAS_CTL CKSC_AADCAD_CTL ADCA1 Isolated area (ISO area) Digital filter type D DNFATCKI CKSC_IADCAS_CTL CKSC_IADCAD_CTL TAUD0 Isolated area (ISO area) Digital filter type E DNFATCKI CKSC_IPERI1S_CTL — TAUB0 Isolated area (ISO area) Digital filter type E DNFATCKI CKSC_IPERI2S_CTL — TAUB1 Isolated area (ISO area) Digital filter type E DNFATCKI CKSC_IPERI2S_CTL — ENCA0 Isolated area (ISO area) Digital filter type E DNFATCKI CKSC_IPERI1S_CTL — SENTn Isolated area (ISO area) Digital filter type E DNFATCKI CKSC_IPERI2S_CTL — Note 1. Power Domain NOTE For the Setting Register, see Section 12AB.4.3, Clock Selector Control Register.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 264 of 4535 Dec 26, 2018 2A.13 Description of Port Noise Filter & Edge/Level Detection External signals pass through different types of filters according to the use of each external input signal. NOTE In this section, <name> in the noise filter control register represents the peripheral function connected to a filter. 2A.13.1 Overview 2A.13.1.1 Analog Filter Types Analog filters have fixed characteristics.

• Type A: An analog filter with edge detection or level detection. Used for external interrupt signals.
• Type B: An analog filter Edge detection is performed by each peripheral function. Used for the timer input signals, asynchronous Hi -Z control input signals, and key return input signals.
• Type C: An analog filter only Used for the external RESET input and mode signals. 2A.13.1.2 Digital Filter Types The digital filter characteristics can be adjusted to suit the application.
• Type D: A digital filter with edge detection. Used for the A/D converter external trigger pin.
• Type E: A digital filter. Edge detection is performed by each peripheral function. Used for the timer input signals and encoder input signals.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 265 of 4535 Dec 26, 2018 2A.13.2 Analog Filters 2A.13.2.1 Analog Filter Characteristic See Section 47A, Electrical Characteristics of RH850/F1KH-D8 for the input conditions for signals input to pins that incorporate an analog filter. 2A.13.2.2 Analog Filter Control Registers A dedicated FCLA0CTLm_<name> register or control register in the peripheral macro is provided for input pins that incorporate an analog filter. The assignment of the input signals to the control registers and their addresses are given in Table 2A.87, Input Pins that Incorporate Analog Filter Type A. 2A.13.2.3 Analog Filter in Standby Mode Analog filters for the function of waking-up from the DeepSTOP mode are located in the Always-On area (AWO area). Analog filters in the Always-On area (AWO area) always operate. The analog filter in standby mode and its wake-up capability depend on the filter types. See the description of the analog filter types below. (1) Analog Filter Type A A block diagram of analog filter type A is shown below. Analog filter FCLA0CTLm_<name>.FCLA0INTLm_<name> EMCLK Input signal INTC Level detector Edge detector Figure 2A.12 Block Diagram of Analog Filter Type A

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 266 of 4535 Dec 26, 2018 After passing an external signal through the filter to eliminate noise and glitches, an output signal is generated according to whether an event is detected; that is whether a specified level is detected or whether a change in the level (an edge) occurs. Whether a level or an edge is detected is selected by the control bit FCLA0CTLm_<name >.FCLA0INTLm_<name>.

• FCLA0INTLm_<name> bit = 0: Edge detection Whether a rising or falling edge is detected can be specified by setting the FCLA0CTLm_<name>.FCLA0INTRm_<name> and FCLA0CTLm_<name>.FCLA0INTFm_<name> bits.
• FCLA0INTLm_<name> bit = 1: Level detection The detection of a high level or low level can be specified by setting FCLA0CTLm_<name>.FCLA0INTRm_<name> bit. The table below summarizes the detection conditions of the analog filter. Table 2A.93 Analog Filter Event Detection Conditions FCLA0INTLm_<name> FCLA0INTFm_<name> FCLA0INTRm_<name> Edge Detection Level Detection 0 0 0 No edge detected Disabled 0 1 Rising edge 1 0 Falling edge 1 1 Rising and falling edges

1 X 0 Disabled Low level

Analog filter type A in Standby mode The output signal of an analog filter type A can always be used as a standby mode wake- up signal. (2) Analog filter type B A block diagram of analog filter type B is shown below. Analog filterInput signal Edge detection Peripheral function Figure 2A.13 Block Diagram of Analog Filter Type B Analog filter type B in Standby mode The output signal of an analog filter type B can always be used as a standby mode wake- up signal.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 267 of 4535 Dec 26, 2018 (3) Analog filter type C A block diagram of analog filter type C is shown below. Peripheral functionAnalog filterInput signal Figure 2A.14 Block Diagram of Analog Filter Type C The generated signals are always input signals that have passed through an analog filter. Analog filter type C in Standby mode Pins equipped with type C analog filters in this product do not support the input of event signals to trigger wake -up from standby.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 268 of 4535 Dec 26, 2018 2A.13.3 Digital Filters 2A.13.3.1 Digital Filter Characteristic The digital filters allow the filter characteristics to be adjusted accordingly to the needs of the application. The input signal is sampled with the sampling frequency fs. If a specified number of successive samples yield the same (high or low) level, the signal level is judged as valid and the filter output signal is set accordingly. If an external signal level change is detected within the specified number of samples (same level samples), the signal level is judged as noise and the filter output signal does not change. The length of an external signal pulse to be judged as noise depends on the sampling frequency and the specified number of same level samples. Both parameters can be specified:

• DNFA<name>CTL.DNFA<name>PRS[2:0] select the sampling frequency based on fs = fDNFATCKI / 2DNFA<name>PRS[2:0] where fDNFATCKI is the frequency of the DNFATCKI clock.
• DNFA<name>CTL.DNFA<name>NFSTS[1:0] determines the number of same level samples, “s”, (2 to 5): s = DNFA<name>NFSTS[1:0] + 2 External signal pulses shorter than the following are suppressed at all times. s ×1/fs External signal pulses longer than the following are always judged as valid and are passed on to the filter output. (s + 1) × 1/fs External signal pulses in the following range may be suppressed or judged as valid. s × 1/fs to (s + 1) × 1/fs The filter operation is illustrated in the figure below with DNFA<name>NFSTS[1:0] = 01B, i.e. s = 3 same level samples. Input signal Sampling points Digital filter output fs Figure 2A.15 Digital Filter Function

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 269 of 4535 Dec 26, 2018 2A.13.3.2 Digital Filter Groups The input signals processed through digital filters are ordered in groups of up to 16 signals. The digital filter characteristics, specified by DNFA<name>CTL.DNFA<name>PRS[2:0] and DNFA<name>NFSTS[1:0] apply to the signals. However, the digital filter for each signal can be enabled or disabled separately by DNFA<name>EN.DNFA<name>ENLm (m = 0 to 7) and DNFA<name>EN.DNFA<name>ENHm (m = 0 to 7). CAUTIONS 1. When the output signal from the digital filter is input to an alternative function, allow at least the following interval to elapse after the digital filter is enabled (DNFA<name>EN.DNFA<name>ENLm (m = 0 to 7) = 1 and DNFA<name>EN.DNFA<name>ENHm (m = 0 to 7) = 1) for the port pin to switch to the alternative function. s = DNFA<name>NFSTS[1:0] + 2 s × 1/fs + 2 × 1/fDNFATCKI 2. When a digital filter’s output signal is used as an interrupt signal, only enable the digital filter (DNFA<name>EN.DNFA<name>ENLm (m = 0 to 7) = 1 and DNFA<name>EN.DNFA<name>ENHm (m = 0 to 7) = 1) while interrupts are disabled. Furthermore, only enable interrupts after enabling the digital filter, waiting for the time below to elapse, and then clearing the interrupt request flag. s × 1/fs + 3 × 1/fDNFATCKI 2A.13.3.3 Digital Filters in Standby Mode Digital filters for the function of waking-up from the DeepSTOP mode are located in the Always-On area (AWO area). Digital filters on the Always-On area (AWO area) are always operating. Digital noise elimination requires the clock supply DNFATCKI to operate. Pins equipped with digital filters in this product do not support the input of event signals to trigger wake-up from standby.

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 270 of 4535 Dec 26, 2018 2A.13.3.4 Digital Filter Control Registers For each group consisting of up to 16 digital filters, the digital noise elimination control register DNFA< name>CTL and digital noise elimination enable register DNFA<name>EN are used to set all the filters in the same group (<name> = peripheral function group). The DNFA<name>CTL register specifies the characteristics of the digital noise elimination filter for the digital filter of <name>. The DNFA<name>EN register enables/disables each filter by setting the corresponding bit in DNFA<name>EN.DNFA<name>ENLm (m = 0 to 7) and DNFA<name>EN.DNFA<name>ENHm (m = 0 to 7). The edge detection setup is done via the filter dedicated control register and the registers for individual peripheral functions. The FCLA0CTLm_ADCn registers are ordered in groups of 3 registers with the same index n. The register index n is in 0 or 1. The assignment of the input signals to the control registers and their addresses are given in Table 2A.90, Input Pins that Incorporate Digital Filter Type D and Table 2A.91, Input Pins that Incorporate Digital Filter Type E in Section 2A.12.1, Port Filter Assignment. CAUTION Do not change any control register settings while the corresponding digital filter is enabled by DNFA<name>EN.DNFA<name>ENLm (m = 0 to 7) = 1 and DNFA<name>EN.DNFA<name>ENHm (m = 0 to 7) = 1. Otherwise an unintended filter output may be generated. (1) Digital filter type D A block diagram of digital filter type D is shown below. Digital filter Peripheral function Prescaler fs Input signal DNFATCKI 1Edge detector “L” DNFA<name>EN.DNFA<name>ENLm Figure 2A.16 Block Diagram of Digital Filter Type D The generated signal depends on the register setting, as shown in the following table. Table 2A.94 Output Options for Digital Filter Type D DNFA<name>EN.DNFA<name>ENLm Signals Output to Peripheral Functions

0 Fixed to low level

1 Input signal passed through filter

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 271 of 4535 Dec 26, 2018 (2) Digital filter type E A block diagram of digital filter type E is shown below. Digital filter Edge detection Prescaler Input signal DNFATCKI DNFA<name>EN.DNFA<name>ENLm and DNFA<name>EN.DNFA<name>ENHm “L” Peripheral function fs Figure 2A.17 Block Diagram of Digital Filter Type E The generated signal depends on the register setting, as shown in the following table. Table 2A.95 Output Options for Digital Filter Type E DNFA<name>EN.DNFA<name>ENLm and DNFA<name>EN.DNFA<name>ENHm Signals Output to Peripheral Functions 2A.13.4 Filter Control Registers The analog and digital filters are controlled and operated by the following registers: Table 2A.96 List of Filter Registers Module Name Register Name Symbol Address FCLA0 Filter control register m FCLA0CTLm_<name> The addresses are shown in the tables in Section 2A.12.1, Port Filter Assignment. DNF Digital noise elimination control register DNFA<name>CTL Digital noise elimination enable register DNFA<name>EN Digital noise elimination enable H register DNFA<name>ENH Digital noise elimination enable L register DNFA<name>ENL

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 272 of 4535 Dec 26, 2018 2A.13.4.1 FCLA0CTLm_<name> — Filter Control Register This register controls the analog and digital filter operation. Access: This register can be read or written in 8-bit units. Address: The allocation of input signals to FCLA0CTLm_<name> registers and the address of each register are shown in the tables in Section 2A.12.1, Port Filter Assignment. Value after reset: 00H Bit 7 6 5 4 3 2 1 0 _<name> FCLA0INTFm _<name> FCLA0INTRm _<name> Value after reset 0 0 0 0 0 0 0 0 R/W R R R R R R/W R/W R/W Table 2A.97 FCLA0CTLm_<name> Register Contents Bit Position Bit Name Function 7 to 3 Reserved When read, the value after reset is returned. When writing, write the value after reset.

2 FCLA0INTLm

_<name> Detection Mode Selection 0: Edge detection 1: Level detection NOTE: This bit is only valid for analog filter type A.

1 FCLA0INTFm

_<name>

• In level detection mode (FCLA0INTLm_<name> = 1): This bit has no effect.
• In edge detection mode (FCLA0INTLm_<name> = 0): Falling edge detection control 0: Falling edge detection disabled 1: Falling edge detection enabled NOTE: This bit is only valid for analog filter type A and digital filter type D. However, digital filter type D is placed in edge detection mode.

0 FCLA0INTRm

_<name>

• In level detection mode (FCLA0INTLm_<name> = 1): Detected level selection 0: Low level detection 1: High level detection
• In edge detection mode (FCLA0INTLm_<name> = 0): Rising edge detection control 0: Rising edge detection disabled 1: Rising edge detection enabled NOTE: This bit is only valid for analog filter type A and digital filter type D. However, digital filter type D is placed in edge detection mode. CAUTION Digital filter type D: Always set bit 2 to "0".

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 273 of 4535 Dec 26, 2018 2A.13.4.2 DNFA<name>CTL — Digital Noise Elimination Control Register This register is used to specify the filter characteristics of the digital noise elimination filter. NOTE This register is only valid for digital filter type D and digital filter type E. Access: This register can be read or written in 8-bit units. Address: For the correspondence between the DNFA<name>CTL register and input signals, and the addresses of individual registers, see Table 2A.90, Input Pins that Incorporate Digital Filter Type D and Table 2A.91, Input Pins that Incorporate Digital Filter Type E in Section 2A.12.1, Port Filter Assignment. Value after reset: 00H Bit 7 6 5 4 3 2 1 0 — DNFA<name>NFSTS[1:0] — — DNFA<name>PRS[2:0] Value after reset 0 0 0 0 0 0 0 0 R/W R R/W R/W R R R/W R/W R/W Table 2A.98 DNFA<name>CTL Register Contents Bit Position Bit Name Function 7 Reserved When read, the value after reset is returned. When writing, write the value after reset. 6, 5 DNFA<name> NFSTS[1:0] The DNFA<name>NFSTS[1:0] bits specify the number of samples used to judge whether an external signal pulse is valid. DNFA<name>NFSTS[1:0] Number of Samples 00B 2 01B 3 10B 4 11B 5 4, 3 Reserved When read, the value after reset is returned. When writing, write the value after reset. 2 to 0 DNFA<name> PRS[2:0] Digital filter sampling clock selection DNFA<name>PRS[2:0] Sampling Clock Frequency 000B DNFATCKI/1 001B DNFATCKI/2 010B DNFATCKI/4 011B DNFATCKI/8 100B DNFATCKI/16 101B DNFATCKI/32 110B DNFATCKI/64 111B DNFATCKI/128

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 274 of 4535 Dec 26, 2018 2A.13.4.3 DNFA<name>EN — Digital Noise Elimination Enable Register This register enables and disables digital noise elimination for a specified input signal. NOTE This register is only valid for digital filter type D and digital filter type E. Access: This register can be read or written in 16-bit units. The upper- and lower-order bytes (DNFA<name>ENH[7:0] and DNFA<name>ENL[7:0]) are accessible in 8- or 1-bit units respectively by setting DNFA<name>ENH. and DNFA<name>ENL. Address: For the correspondence between the DNFA<name>EN register and input signals, and the addresses of individual registers, see Table 2A.90, Input Pins that Incorporate Digital Filter Type D and Table 2A.91, Input Pins that Incorporate Digital Filter Type E in Section 2A.12.1, Port Filter Assignment. Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DNFA <name> ENH7 DNFA <name> ENH6 DNFA <name> ENH5 DNFA <name> ENH4 DNFA <name> ENH3 DNFA <name> ENH2 DNFA <name> ENH1 DNFA <name> ENH0 DNFA <name> ENL7 DNFA <name> ENL6 DNFA <name> ENL5 DNFA <name> ENL4 DNFA <name> ENL3 DNFA <name> ENL2 DNFA <name> ENL1 DNFA <name> ENL0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Table 2A.99 DNFA<name>EN Register Contents Bit Position Bit Name Function 15 to 0 DNFA<name> ENH[7:0] DNFA<name> ENL[7:0] Digital Noise Elimination Enable/Disable Control 0: Fixed to low level 1: Input signal passed through filter

RH850/F1KH, RH850/F1KM Section 2A Pin Function of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 275 of 4535 Dec 26, 2018 2A.13.4.4 DNFA<name>ENH – Digital Noise Elimination Enable H Register Setting in this register correspond to those of the 8 upper-order bits of the DNFA<name>EN register. NOTE This register is only valid for digital filter type E. Access: This register can be read or written in 8-bit or 1-bit units. Address: For the correspondence between the DNFA<name>ENH register and input signals, and the addresses of individual registers, see Table 2A.91, Input Pins that Incorporate Digital Filter Type E in Section 2A.12.1, Port Filter Assignment. Value after reset: 00H Bit 7 6 5 4 3 2 1 0 DNFA<name> ENH7 DNFA<name> ENH6 DNFA<name> ENH5 DNFA<name> ENH4 DNFA<name> ENH3 DNFA<name> ENH2 DNFA<name> ENH1 DNFA<name> ENH0 Value after reset 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W For details of the respective bit functions, see Section 2A.13.4.3, DNFA<name>EN — Digital Noise Elimination Enable Register. 2A.13.4.5 DNFA<name>ENL – Digital Noise Elimination Enable L Register Setting in this register correspond to those of the 8 lower-order bits of the DNFA<name>EN register. NOTE This register is only valid for digital filter type D and digital filter type E. Access: This register can be read or written in 8-bit or 1-bit units. Address: For the correspondence between the DNFA<name>ENL register and input signals, and the addresses of individual registers, see Table 2A.90, Input Pins that Incorporate Digital Filter Type D and Table 2A.91, Input Pins that Incorporate Digital Filter Type E in Section 2A.12.1, Port Filter Assignment. Value after reset: 00H Bit 7 6 5 4 3 2 1 0 DNFA <name> ENL7 DNFA <name> ENL6 DNFA <name> ENL5 DNFA <name> ENL4 DNFA <name> ENL3 DNFA <name> ENL2 DNFA <name> ENL1 DNFA <name> ENL0 Value after reset 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W For details of the respective bit functions, see Section 2A.13.4.3, DNFA<name>EN — Digital Noise Elimination Enable Register.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 276 of 4535 Dec 26, 2018 Section 2B Pin Function of RH850/F1KM-S4 This section describes the pin and port functions. Section 2B.1, Pin Connection Diagram to Section 2B.5, Recommended Connection of Unused Pins describe the pin connections and respective pins. Section 2B.6, Features of RH850/F1KM Port to Section 2B.13, Description of Port Noise Filter & Edge/Level Detection describe the general port functions. 2B.1 Pin Connection Diagram JP0_2 JP0_1 JP0_0 RESET EVCC AWOVSS AWOVCL REGVCC FLMD0 P0_10 P0_9 P0_8 P0_7 EVSS ISOVSS ISOVCL P8_3 P8_4 P8_5 P8_6 P8_7 P8_8 P8_9 REGVCC ISOVSS P9_4 P9_3 P9_2 P9_1 P9_0 AP0_0 AP0_1 AP0_2 AP0_3 AP0_4 AP0_5 AP0_6 AP0_7 AP0_8 AP0_9 AP0_10 AP0_11 AP0_12 AP0_13 AP0_14 AP0_15 A0VREF A0VSS 100 P10_2 P10_1 P10_0 EVSS EVCC P11_7 P11_6 P11_5 P11_4 P11_3 P11_2 P11_1 P10_14 P10_13 P10_12 P10_11 P10_10 P10_9 P10_8 P10_7 P10_6 EVSS ISOVSS ISOVCL EVCC P10_3 P10_4 P10_5 ISOVCL ISOVSS P0_0 P0_1 P0_2 P0_3 EVCC P0_4 P0_5 P0_6 P0_11 P0_12 P0_13 P0_14 EVSS P8_2 P8_10 P8_11 P8_12 JP0_5 JP0_4 JP0_3 Figure 2B.1 Pin Connection Diagram (100-Pin LQFP)

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 277 of 4535 Dec 26, 2018 JP0_2 JP0_1 JP0_0 P1_11 P1_10 P1_9 P1_8 RESET EVCC XT1 IP0_0 AWOVSS AWOVCL REGVCC FLMD0 JP0_6 P0_10 P0_9 P0_8 P0_7 EVSS ISOVSS ISOVCL P1_5 P1_4 P8_0 P8_1 P8_3 P8_4 P8_5 P8_6 P8_7 P8_8 P8_9 AP1_1 AP1_2 AP1_3 AP1_4 AP1_5 AP1_6 AP1_7 EVCC P20_4 P20_5 REGVCC ISOVSS P9_4 P9_3 P9_2 P9_1 P9_0 EVSS AP0_0 AP0_1 AP0_2 AP0_3 AP0_4 AP0_5 AP0_6 AP0_7 AP0_8 AP0_9 AP0_10 AP0_11 AP0_12 AP0_13 AP0_14 AP0_15 A0VREF A0VSS 108 107 106 105 104 103 102 101 100 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 P10_2 P10_1 P10_0 BVSS BVCC P12_2 P12_1 P12_0 P11_15 P11_7 P11_6 P11_5 P11_4 P11 P11_2 P11_1 P10_14 P10_13 P10_12 P10_11 P10_10 P10_9 P10_8 P10_7 P10_6 BVSS P18_3 P18_2 P18_1 P18_0 ISOVSS ISOVCL BVCC A1VSS A1VREF AP1_0 P10_3 P10_4 P10_5 P10_15 P11_0 P11_8 P11_9 P11_10 P11_11 P11_12 ISOVCL ISOVSS P0_0 P0_1 P0_2 P0_3 EVCC P0_4 P0_5 P0_6 P0_11 P0_12 P0_13 P0_14 P1_0 P1_1 P1_2 P1_3 EVSS P8_2 P8_10 P8_11 P8_12 JP0_5 JP0_4 JP0_3 Figure 2B.2 Pin Connection Diagram (144-Pin LQFP)

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 278 of 4535 Dec 26, 2018 JP0_2 JP0_1 JP0_0 P2_1 P2_0 P1_11 P1_10 P1_9 P1_8 RESET EVCC XT1 IP0_0 AWOVSS AWOVCL REGVCC FLMD0 P2_3 P2_2 JP0_6 P0_10 P0_9 P0_8 P0_7 EVSS ISOVSS ISOVCL P1_5 P1_4 P2_4 P2_5 P1_14 P1_15 P8_0 P8_1 P8_3 P8_4 P8_5 P8_6 P8_7 P8_8 P8_9 AP1_1 AP1_2 AP1_3 AP1_4 AP1_5 AP1_6 AP1_7 AP1_8 AP1_9 AP1_10 AP1_11 EVCC P20_4 P20_5 P20_0 P20_1 P20_2 P20_3 REGVCC ISOVSS P9_4 P9_3 P9_2 P9_1 P9_0 EVSS AP0_0 AP0_1 AP0_2 AP0_3 AP0_4 AP0_5 AP0_6 AP0_7 AP0_8 AP0_9 AP0_10 AP0_11 AP0_12 AP0_13 AP0_14 AP0_15 A0VREF A0VSS 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 P10_2 P10_1 P10_0 BVSS BVCC P12_2 P12_1 P12_0 P11_15 P11_7 P11_6 P11_5 P11_4 P11_3 P11_2 P11_1 P10_14 P10_13 P10_12 P10_11 P10_10 P10_9 P10_8 P10_7 P10_6 BVSS P18_7 P18_6 P18_5 P18_4 P18_3 P18_2 P18_1 P18_0 ISOVSS ISOVCL BVCC A1VSS A1VREF AP1_12 AP1_13 AP1_14 AP1_15 AP1_0 P10_3 P10_4 P10_5 BVCC BVSS P10_15 P11_0 P11_8 P11_9 P11_10 P11_11 P11_12 ISOVCL ISOVSS P12_3 P12_4 P12_5 P0_0 P0_1 P0_2 P0_3 EVCC P0_4 P0_5 P0_6 P0_11 P0_12 P0_13 P0_14 P1_0 P1_1 P1_2 P1_3 P1_12 P1_13 P2_6 EVSS P8_2 P8_10 P8_11 P8_12 JP0_5 JP0_4 JP 0_3 Figure 2B.3 Pin Connection Diagram (176-Pin LQFP)

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 279 of 4535 Dec 26, 2018 P10_0 P12_2 P11_5 P11_1 P10_13 P10_10 P10_7 P10_6 P19_2 P18_15 P18_13 P18_6 P18_5 P18_10 P18_8 A1VSS P10_1 P13_1 P12_0 P11_4 P11_3 P10_14 P10_9 P19_3 P19_1 P18_7 P18_11 P18_3 P18_2 P18_1 AP1_12 AP1_14 P10_5 P10_2 P13_0 P12_1 P11_7 P11_2 P10_11 P18_14 P19_0 P18_4 P18_12 P18_9 P18_0 AP1_13 AP1_15 AP1_0 P11_0 P10_4 BVCC P11_15 P11_6 P10_12 P10_8 BVSS BVCC BVCC ISOVSS ISOVCL A1VSS AP1_1 AP1_2 AP1_3 P11_10 P11_8 BVCC A1VREF AP1_5 AP1_6 AP1_8 P13_2 P11_11 BVSS AP1_4 AP1_7 AP1_9 P20_4 P13_4 P13_5 ISOVCL BVSS BVSS BVSS BVSS BVSS AP1_10 AP1_11 P20_5 P20_0 P13_7 P13_6 ISOVSS BVSS BVSS BVSS BVSS EVSS EVCC P20_1 P20_2 P20_3 P0_1 P12_5 P0_2 BVSS BVSS BVSS EVSS EVSS REGVCC P9_3 P9_4 P9_2 P0_5 P0_4 EVCC EVSS EVSS EVSS EVSS EVSS ISOVSS AP0_0 P9_0 P9_1 P0_12 P0_6 P0_14 EVSS EVSS EVSS EVSS EVSS EVSS AP0_4 AP0_2 AP0_1 P1_0 P2_9 P2_7 A0VREF AP0_8 AP0_5 AP0_3 P1_1 P1_3 P2_11 A0VSS AP0_11 AP0_7 AP0_6 P1_13 P8_10 P8_12 JP0_1 P1_11 P2_13 P2_15 EVCC REGVCC ISOVSS ISOVCL P8_6 P8_8 AP0_13 AP0_10 AP0_9 P2_10 JP0_4 JP0_3 P2_1 P1_10 P1_9 P3_0 FLMD0 P0_9 P0_7 P2_5 P1_15 P8_4 P8_7 AP0_14 AP0_12 P2_12 P8_11 JP0_2 P2_0 P2_14 IP0_0 AWOVCL X1 P2_2 P0_10 P0_8 P2_4 P8_1 P8_5 P8_9 AP0_15 P8_2 JP0_5 JP0_0 P1_8 RESET XT1 AWOVSS X2 P2_3 JP0_6 P1_5 P1_4 P1_14 P8_0 P8_3 A0VSS BVSS P10_3 P10_15 P11_9 P11_12 P13_3 P12_3 P12_4 P0_0 P0_3 P0_11 P0_13 P1_2 P1_12 P2_6 P2_8 EVSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 A B C D E F G H J K L M N P R T U A B C D E F G H J K L M N P R T U Top View Figure 2B.4 Pin Connection Diagram (233-Pin FPBGA)

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 280 of 4535 Dec 26, 2018 P22_7 P13_1 P22_9 P11_15 P22_12 P22_13 P22_15 P11_1 P10_12 P10_10 P10_6 P19_3 P19_0 P18_14 P18_6 P18_3 P10_3 P10_1 P22_8 P12_1 P22_11 P11_5 P11_4 P21_1 P10_14 P10_8 P19_2 P19_1 P18_7 P18_13 P18_4 P18_2 P22_5 P10_2 P10_0 P12_2 P22_10 P11_6 P22_14 P11_3 P10_13 P10_7 P10_9 P18_15 P18_12 P18_11 P18_10 P18_8 P22_3 P10_5 BVCC BVCC P13_0 P12_0 P11_7 P11_2 BVSS P10_11 BVCC BVSS P18_5 ISOVSS ISOVCL BVCC P11_8 P10_4 BVCC A1VSS AP1_4 AP1_5 AP1_6 P22_1 P11_9 BVCC A1VREF AP1_7 AP1_9 AP1_10 P11_11 P11_10 BVSS BVSS BVSS BVSS BVSS AP1_8 AP1_11 P20_6 P20_7 P11_12 P21_0 ISOVCL BVSS BVSS BVSS EVSS EVCC P20_8 P20_9 P20_4 P21_3 P21_2 ISOVSS BVSS EVSS EVSS EVSS EVSS P20_5 P20_0 P20_1 P13_6 P13_2 BVSS EVSS EVSS EVSS EVSS EVCC P20_3 P20_10 P20_2 P12_5 P0_3 P13_5 REGVCC P20_13 P20_12 P20_11 P0_1 P0_6 P13_7 ISOVSS P9_3 P9_4 P20_14 P0_5 P12_4 P0_2 EVSS P9_0 P9_1 P9_2 P0_12 P0_14 EVCC JP0_2 P1_9 EVCC AWOVCL REGVCC P0_9 ISOVSS ISOVCL P1_15 AP0_6 AP0_3 AP0_1 AP0_0 P1_1 P2_6 P1_3 JP0_0 P1_11 P2_13 P3_0 FLMD0 P0_8 P0_7 P2_5 P8_1 A0VREF AP0_7 AP0_4 AP0_2 P1_12 P2_8 P2_9 P2_0 P2_14 P2_15 IP0_0 P2_3 P2_2 JP0_6 P1_4 P2_4 A0VSS AP0_10 AP0_8 AP0_5 P1_10 P1_8 RESET XT1 AWOVSS X2 X1 P0_10 P1_5 BVSS P22_6 P22_4 P10_15 P11_0 P22_2 P22_0 P21_4 P13_3 P13_4 P12_3 P0_0 P0_4 P0_11 P0_13 P1_0 P2_7 P2_11 P8_12 P2_12 P8_10 JP0_3 P8_2 JP0_5 JP0_1 P8_11 JP0_4 P2_1 P1_2 P1_13 P2_10 EVSS EVSS EVCC P3_7 P3_10 AP0_13 AP0_11 AP0_9 P3_1 P8_7 P3_3 P3_6 P3_9 AP0_14 AP0_12 P8_0 P8_4 P3_2 P8_8 P3_4 P3_8 AP0_15 P1_14 P8_3 P8_5 P8_6 P8_9 P3_5 A0VSS P18_9 P18_0 A1VSS P18_1 AP1_12 AP1_13 AP1_14 AP1_15 AP1_0 AP1_1 AP1_2 AP1_3 Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A B C D E F G H J K L M N P R T U V W Y A B C D E F G H J K L M N P R T U V W Y Figure 2B.5 Pin Connection Diagram (272-Pin FPBGA)

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 281 of 4535 Dec 26, 2018 Table 2B.1 Pin Assignment 100-Pin LQFP Pin No. Pin Name

1 P10_3 / TAUD0I7 / TAUD0O7 / RIIC0SCL / KR0I1 / PWGA3O / ADCA0TRG1 / CSIH1SSI / TAPA0VN

2 P10_4 / TAUD0I9 / TAUD0O9 / RLIN21RX / CAN6TX / KR0I2 / ADCA0TRG2 / CSIG0SSI / ADCA0SEL0 / TAPA0WP

3 P10_5 / TAUD0I11 / TAUD0O11 / CAN6RX / INTP6 / RLIN21TX / KR0I3 / CSIG0RYI / CSIG0RYO / ADCA0SEL1 /

4 ISOVCL

5 ISOVSS

6 P0_0 / TAUD0I2 / TAUD0O2 / RLIN20RX / CAN0TX / PWGA10O / CSIH0SSI / DPO / TAUJ2I1 / TAUJ2O1

7 P0_1 / TAUD0I4 / TAUD0O4 / CAN0RX / INTP0 / RLIN20TX / PWGA11O / CSIH0SI / APO / TAUJ2I2 / TAUJ2O2

8 P0_2 / TAUD0I6 / TAUD0O6 / CAN1RX / INTP1 / RLIN30TX / PWGA12O / CSIH0SC / DPO / TAUJ2I3 / TAUJ2O3

9 P0_3 / TAUD0I8 / TAUD0O8 / RLIN30RX / INTP10 / CAN1TX / DPIN1 / PWGA13O / CSIH0SO / TAUJ1I0 / TAUJ1O0

10 EVCC

11 P0_4 / RLIN31RX / INTP11 / CAN2TX / PWGA10O / CSIH1SI / SELDP0 / DPIN8 / TAUB0I12 / TAUB0O12

12 P0_5 / CAN2RX / INTP2 / RLIN31TX / DPIN9 / SELDP1 / CSIH1SO / TAUB0I14 / TAUB0O14

13 P0_6 / INTP2 / DPIN10 / SELDP2 / CSIH1SC / PWGA35O

14 P0_11 / RIIC0SDA / DPIN12 / CSIH1CSS2 / TAUB0I8 / TAUB0O8 / PWGA34O

15 P0_12 / RIIC0SCL / DPIN13 / PWGA45O / TAUB0I10 / TAUB0O10 / CSIG0SI

16 P0_13 / INTP12 / PWGA46O / TAUB0I12 / TAUB0O12 / CSIG0SO / CAN5RX / INTP5 / RLIN32RX

17 P0_14 / PWGA47O / TAUB0I14 / TAUB0O14 / CSIG0SC / CAN5TX / RLIN32TX

18 EVSS

19 P8_2 / TAUJ0I0 / TAUJ0O0 / DPIN2 / CSIH0CSS0 / INTP6 / PWGA22O / ADCA0I4S

20 P8_10 / DPIN14 / PWGA42O / ADCA0I17S / CSIH3CSS3

21 P8_11 / TAUJ1I2 / TAUJ1O2 / DPIN15 / PWGA43O / ADCA0I18S / CSIH1CSS4

22 P8_12 / TAUJ1I3 / TAUJ1O3 / DPIN16 / PWGA44O / ADCA0I19S / CSIH1CSS5

23 JP0_5 / NMI / TAUJ0I3 / TAUJ0O3 / DCURDY / LPDCLKOUT / RTCA0OUT

24 JP0_4 / DCUTRST

25 JP0_3 / INTP3 / TAUJ0I2 / TAUJ0O2 / DCUTMS / CSCXFOUT

26 JP0_2 / INTP2 / TAUJ0I1 / TAUJ0O1 / FPCK / DCUTCK / LPDCLK

27 JP0_1 / INTP1 / TAUJ0I0 / TAUJ0O0 / FPDT / DCUTDO / LPDO

28 JP0_0 / INTP0 / FPDR / FPDT / DCUTDI / LPDI/ LPDIO / TAUJ2I0 / TAUJ2O0

29 RESET

30 EVCC

31 AWOVSS

32 AWOVCL

33 REGVCC

36 FLMD0

37 P0_10 / INTP3 / CSIH1CSS1 / DPIN11 / RLIN22TX / TAUB0I6 / TAUB0O6 / CAN4TX

38 P0_9 / INTP12 / CSIH1CSS0 / DPIN7 / RLIN22RX / TAUB0I4 / TAUB0O4 / CAN4RX / INTP4

39 P0_8 / RLIN21TX / DPIN6 / CSIH1SSI / TAUB0I2 / TAUB0O2 / CAN3TX / CSIH0CSS6

40 P0_7 / RLIN21RX / DPIN5 / CSCXFOUT / CSIH1RYI / CSIH1RYO / TAUB0I0 / TAUB0O0 / CAN3RX / INTP3

41 EVSS

42 ISOVSS

43 ISOVCL

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 282 of 4535 Dec 26, 2018 Table 2B.1 Pin Assignment 100-Pin LQFP Pin No. Pin Name

44 P8_3 / TAUJ0I1 / TAUJ0O1 / DPIN3 / CSIH0CSS1 / INTP7 / PWGA23O / CAN7TX / ADCA0I5S

45 P8_4 / TAUJ0I2 / TAUJ0O2 / DPIN4 / CSIH0CSS2 / INTP8 / PWGA36O / CAN7RX / INTP9 / ADCA0I6S

46 P8_5 / TAUJ0I3 / TAUJ0O3 / NMI / CSIH0CSS3 / PWGA37O / ADCA0I7S / INTP9

47 P8_6 / NMI / CSIH0CSS4 / PWGA38O / RTCA0OUT / ADCA0I8S / RESETOUT

48 P8_7 / PWGA39O / ADCA0SEL0 / RTCA0OUT / ADCA0I14S / CSIH3CSS0

49 P8_8 / PWGA40O / ADCA0SEL1 / ADCA0I15S / CSIH3CSS1

50 P8_9 / PWGA41O / ADCA0SEL2 / ADCA0I16S / CSIH3CSS2

51 A0VSS

52 A0VREF

53 AP0_15 / ADCA0I15

54 AP0_14 / ADCA0I14

55 AP0_13 / ADCA0I13

56 AP0_12 / ADCA0I12

57 AP0_11 / ADCA0I11

58 AP0_10 / ADCA0I10

59 AP0_9 / ADCA0I9

60 AP0_8 / ADCA0I8

61 AP0_7 / ADCA0I7

62 AP0_6 / ADCA0I6

63 AP0_5 / ADCA0I5

64 AP0_4 / ADCA0I4

65 AP0_3 / ADCA0I3

66 AP0_2 / ADCA0I2

67 AP0_1 / ADCA0I1

68 AP0_0 / ADCA0I0

69 P9_0 / NMI / PWGA8O / TAUD0I0 / TAUD0O0 / ADCA0TRG0 / CSIH2CSS0 / KR0I4 / TAUJ1I1 / TAUJ1O1 / SENT1RX / RIIC1SDA / ADCA0I2S

70 P9_1 / INTP11 / PWGA9O / TAUD0I2 / TAUD0O2 / KR0I5 / CSIH2CSS1 / TAUJ1I2 / TAUJ1O2 / SENT1SPCO /

71 P9_2 / KR0I6 / PWGA20O / TAPA0ESO / CSIH2CSS2 / ADCA0I9S

72 P9_3 / KR0I7 / PWGA21O / CSIH2CSS3 / TAUJ1I1 / TAUJ1O1 / ADCA0I10S

73 P9_4 / CSIH0CSS5 / PWGA33O / TAUJ1I0 / TAUJ1O0 / ADCA0I11S

74 ISOVSS

75 REGVCC

76 EVCC

77 ISOVCL

78 ISOVSS

79 EVSS

80 P10_6 / TAUD0I13 / TAUD0O13 / CSIG0SO / ENCA0TIN0 / ADCA0SEL2 / CAN1RX / INTP1 / MODE2

81 P10_7 / TAUD0I15 / TAUD0O15 / CSIG0SC / ENCA0TIN1 / PWGA4O / CAN1TX / TAUJ3I1 / TAUJ3O1

82 P10_8 / TAUD0I10 / TAUD0O10 / CSIG0SI / FLXA0TXDB / ENCA0EC / PWGA5O / TAUJ3I2 / TAUJ3O2 / FLMD1

83 P10_9 / TAUD0I12 / TAUD0O12 / RLIN30RX / INTP10 / ENCA0E0 / PWGA6O / CSIH0RYI / CSIH0RYO / FLXA0RXDB

84 P10_10 / TAUD0I14 / TAUD0O14 / RLIN30TX / ENCA0E1 / PWGA7O / CSIH0CSS1 / TAUJ3I3 / TAUJ3O3

85 P10_11 / PWGA16O / RLIN31RX / INTP11 / FLXA0TXENA / CSIH1CSS0 / TAUB0I1 / TAUB0O1

86 P10_12 / PWGA17O / FLXA0STPWT / RLIN31TX / CSIH1CSS1 / TAUB0I3 / TAUB0O3

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 283 of 4535 Dec 26, 2018 Table 2B.1 Pin Assignment 100-Pin LQFP Pin No. Pin Name

87 P10_13 / CSIH0SSI / PWGA18O / INTP12 / FLXA0TXENB / TAUB0I5 / TAUB0O5 / CAN7TX / RLIN32RX

88 P10_14 / PWGA19O / FLXA0RXDA / TAUB0I7 / TAUB0O7 / CAN7RX / INTP9 / RLIN32TX / CSIH3SSI

89 P11_1 / CSIH2SSI / FLXA0TXDA / RLIN20RX / PWGA26O / TAUB0I13 / TAUB0O13 / CSIH0CSS7

90 P11_2 / CSIH2SO / INTP12 / RLIN20TX / PWGA27O / TAUB0I15 / TAUB0O15 / RLIN32RX

91 P11_3 / CSIH2SC / CAN3RX / INTP3 / PWGA28O / RLIN32TX

92 P11_4 / CSIH2SI / CAN3TX / PWGA29O

93 P11_5 / CAN5RX / INTP5 / PWGA30O / CSIH3SI

94 P11_6 / INTP13 / CAN5TX / PWGA31O / CSIH3SO

95 P11_7 / INTP5 / PWGA32O / CSIH3SC

96 EVCC

97 EVSS

98 P10_0 / TAUD0I1 / TAUD0O1 / CAN0RX / INTP0 / PWGA0O / CSIH1SI / CSCXFOUT / TAUJ1I3 / TAUJ1O3 / TAPA0UP

99 P10_1 / TAUD0I3 / TAUD0O3 / CAN0TX / PWGA1O / CSIH1SC / MODE0 / TAUJ3I0 / TAUJ3O0 / TAPA0UN

100 P10_2 / TAUD0I5 / TAUD0O5 / RIIC0SDA / KR0I0 / PWGA2O / ADCA0TRG0 / CSIH1SO / MODE1 / TAPA0VP

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 284 of 4535 Dec 26, 2018 Table 2B.2 Pin Assignment 144-Pin LQFP Pin No. Pin Name

1 P10_3 / TAUD0I7 / TAUD0O7 / RIIC0SCL / KR0I1 / PWGA3O / ADCA0TRG1 / TAPA0VN / CSIH1SSI

4 P10_15 / CSIH3RYI / CSIH3RYO / PWGA24O / RLIN22RX / TAUB0I9 / TAUB0O9

5 P11_0 / CSIH2RYI / CSIH2RYO / ADCA1TRG2 / PWGA25O / RLIN22TX / TAUB0I11 / TAUB0O11

6 P11_8 / CSIG1SSI / RLIN35TX / PWGA48O

7 P11_9 / CSIG1SO / RLIN35RX / INTP15 / PWGA49O

8 P11_10 / CSIG1SC / PWGA50O

9 P11_11 / CSIG1SI / RLIN25TX / PWGA51O

10 P11_12 / RLIN25RX / PWGA52O

11 ISOVCL

12 ISOVSS

13 P0_0 / TAUD0I2 / TAUD0O2 / RLIN20RX / CAN0TX / PWGA10O / CSIH0SSI / DPO / TAUJ2I1 / TAUJ2O1

14 P0_1 / TAUD0I4 / TAUD0O4 / CAN0RX / INTP0 / RLIN20TX / PWGA11O / CSIH0SI / APO / TAUJ2I2 / TAUJ2O2

15 P0_2 / TAUD0I6 / TAUD0O6 / CAN1RX / INTP1 / RLIN30TX / PWGA12O / CSIH0SC / DPO / TAUJ2I3 / TAUJ2O3

16 P0_3 / TAUD0I8 / TAUD0O8 / RLIN30RX / INTP10 / CAN1TX / DPIN1 / PWGA13O / CSIH0SO / TAUJ1I0 / TAUJ1O0

17 EVCC

18 P0_4 / RLIN31RX / INTP11 / CAN2TX / PWGA10O / CSIH1SI / SELDP0 /DPIN8 / TAUB0I12 / TAUB0O12

19 P0_5 / CAN2RX / INTP2 / RLIN31TX / DPIN9 / SELDP1 / CSIH1SO / TAUB0I14 / TAUB0O14

20 P0_6 / INTP2 / DPIN10 / SELDP2 / CSIH1SC / PWGA35O

21 P0_11 / RIIC0SDA / DPIN12 / CSIH1CSS2 / TAUB0I8 / TAUB0O8 / PWGA34O

22 P0_12 / RIIC0SCL / DPIN13 / PWGA45O / TAUB0I10 / TAUB0O10 / CSIG0SI

23 P0_13 / RLIN32RX / INTP12 / PWGA46O / TAUB0I12 / TAUB0O12 / CSIG0SO / CAN5RX / INTP5

24 P0_14 / INTP17 / RLIN32TX / PWGA47O / TAUB0I14 / TAUB0O14 / CSIG0SC / CAN5TX

25 P1_0 / RLIN33RX / INTP13 / TAUJ2I0 / TAUJ2O0

26 P1_1 / INTP18 / RLIN33TX / TAUJ2I1 / TAUJ2O1

27 P1_2 / CAN3RX / INTP3 / DPIN19 / TAUJ2I2 / TAUJ2O2

28 P1_3 / INTP19 / CAN3TX / DPIN23 / TAUJ2I3 / TAUJ2O3

29 EVSS

30 P8_2 / TAUJ0I0 / TAUJ0O0 / DPIN2 / CSIH0CSS0 / INTP6 / PWGA22O / ADCA0I4S

31 P8_10 / CSIH3CSS3 / DPIN14 / PWGA42O / ADCA0I17S

32 P8_11 / TAUJ1I2 / TAUJ1O2 / DPIN15 / PWGA43O / CSIH1CSS4 / RLIN25RX / ADCA0I18S

33 P8_12 / TAUJ1I3 / TAUJ1O3 / DPIN16 / PWGA44O / CSIH1CSS5 / INTP23 / RLIN25TX / ADCA0I19S

34 JP0_5 / NMI / RTCA0OUT / TAUJ0I3 / TAUJ0O3 / DCURDY / LPDCLKOUT

35 JP0_4 / DCUTRST

36 JP0_3 / INTP3 / CSCXFOUT / TAUJ0I2 / TAUJ0O2 / DCUTMS

37 JP0_2 / INTP2 / TAUJ0I1 / TAUJ0O1 / FPCK / DCUTCK / LPDCLK

38 JP0_1 / INTP1 /TAUJ0I0 / TAUJ0O0 / FPDT / DCUTDO / LPDO

39 JP0_0 / INTP0 / FPDR / FPDT / DCUTDI / LPDI / LPDIO / TAUJ2I0 / TAUJ2O0

40 P1_11 / ADCA1TRG2 / RLIN24TX / DPIN22 / INTP14

41 P1_10 / RLIN24RX / DPIN21 / INTP22 / ADCA1TRG1

42 P1_9 / DPIN20 / INTP21

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 285 of 4535 Dec 26, 2018 Table 2B.2 Pin Assignment 144-Pin LQFP Pin No. Pin Name

43 P1_8

44 RESET

45 EVCC

46 XT1

47 IP0_0 / XT2

48 AWOVSS

49 AWOVCL

50 REGVCC

53 FLMD0

54 JP0_6 / EVTO

55 P0_10 / INTP3 / CSIH1CSS1 / DPIN11 / RLIN22TX / TAUB0I6 / TAUB0O6 / CAN4TX

56 P0_9 / INTP12 / CSIH1CSS0 / DPIN7 / RLIN22RX / TAUB0I4 / TAUB0O4 / CAN4RX / INTP4

57 P0_8/ INTP16 / RLIN21TX / DPIN6 / CSIH0CSS6 / CSIH1SSI / TAUB0I2 / TAUB0O2 / CAN3TX

58 P0_7 / RLIN21RX / DPIN5 / CSCXFOUT / CSIH1RYI / CSIH1RYO / TAUB0I0 / TAUB0O0 / CAN3RX / INTP3

59 EVSS

60 ISOVSS

61 ISOVCL

62 P1_5 / ADCA1TRG0 / RLIN35TX / DPIN17 / INTP20

63 P1_4 / RLIN35RX / INTP15 / DPIN18

64 P8_0 / TAUJ0I0 / TAUJ0O0 / DPIN2 / PWGA14O / INTP4 / CSIH0CSS0 / CAN6RX / INTP6 / ADCA0I0S / RIIC1SDA / SENT0RX

65 P8_1 / TAPA0ESO / TAUJ0O1 / DPIN0 / PWGA15O / INTP5 / CSIH1CSS3 / CAN6TX / ADCA0I1S / RIIC1SCL /

66 P8_3 / TAUJ0I1 / TAUJ0O1 / DPIN3 / CSIH0CSS1 / INTP7 / PWGA23O / CAN7TX / ADCA0I5S

67 P8_4 / TAUJ0I2 / TAUJ0O2 / DPIN4 / CSIH0CSS2 / INTP8 / PWGA36O / CAN7RX / INTP9 / ADCA0I6S

68 P8_5 / TAUJ0I3 / TAUJ0O3 / NMI / CSIH0CSS3 / INTP9 / PWGA37O / ADCA0I7S

69 P8_6 / NMI / CSIH0CSS4 / PWGA38O / RTCA0OUT / ADCA0I8S / RESETOUT

70 P8_7 / CSIH3CSS0 / PWGA39O / ADCA0SEL0 / RTCA0OUT / ADCA0I14S

71 P8_8 / CSIH3CSS1 / PWGA40O / ADCA0SEL1 / RLIN34RX / INTP14 / ADCA0I15S

72 P8_9 / CSIH3CSS2 / PWGA41O / ADCA0SEL2 / RLIN34TX / ADCA0I16S

73 A0VSS

74 A0VREF

75 AP0_15 / ADCA0I15

76 AP0_14 / ADCA0I14

77 AP0_13 / ADCA0I13

78 AP0_12 / ADCA0I12

79 AP0_11 / ADCA0I11

80 AP0_10 / ADCA0I10

81 AP0_9 / ADCA0I9

82 AP0_8 / ADCA0I8

83 AP0_7 / ADCA0I7

84 AP0_6 / ADCA0I6

85 AP0_5 / ADCA0I5

86 AP0_4 / ADCA0I4

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 286 of 4535 Dec 26, 2018 Table 2B.2 Pin Assignment 144-Pin LQFP Pin No. Pin Name

87 AP0_3 / ADCA0I3

88 AP0_2 / ADCA0I2

89 AP0_1 / ADCA0I1

90 AP0_0 / ADCA0I0

91 EVSS

92 P9_0 / NMI / PWGA8O / TAUD0I0 / TAUD0O0 / ADCA0TRG0 / CSIH2CSS0 / KR0I4 / ADCA0I2S / TAUJ1I1 / TAUJ1O1 / SENT1RX / RIIC1SDA

93 P9_1 / INTP11 / PWGA9O / TAUD0I2 / TAUD0O2 / KR0I5 / CSIH2CSS1 / ADCA0I3S / TAUJ1I2 / TAUJ1O2 /

94 P9_2 / KR0I6 / PWGA20O / TAPA0ESO / CSIH2CSS2 / ADCA0I9S

95 P9_3 / KR0I7 / PWGA21O / CSIH2CSS3 / TAUJ1I1 / TAUJ1O1 / INTP16 / ADCA0I10S

96 P9_4 / CSIH0CSS5 / PWGA33O / TAUJ1I0 / TAUJ1O0 / INTP17 / ADCA0I11S

97 ISOVSS

98 REGVCC

99 P20_5 / RLIN23TX / INTP23 / PWGA60O / CAN7TX

100 P20_4 / RLIN23RX / INTP22 / PWGA59O / CAN7RX / INTP9

101 EVCC

102 AP1_7 / ADCA1I7

103 AP1_6 / ADCA1I6

104 AP1_5 / ADCA1I5

105 AP1_4 / ADCA1I4

106 AP1_3 / ADCA1I3

107 AP1_2 / ADCA1I2

108 AP1_1 / ADCA1I1

109 AP1_0 / ADCA1I0

110 A1VREF

111 A1VSS

112 BVCC

113 ISOVCL

114 ISOVSS

115 P18_0 / CSIG1RYI / CSIG1RYO / PWGA61O / ADCA1I0S / TAUJ3I0 / TAUJ3O0

116 P18_1 / PWGA62O / ADCA1I1S / TAUJ3I1 / TAUJ3O1

117 P18_2 / PWGA63O / ADCA1I2S / TAUJ3I2 / TAUJ3O2

118 P18_3 / ADCA1I3S / TAUJ3I3 / TAUJ3O3

119 BVSS

120 P10_6 / TAUD0I13 / TAUD0O13 / CSIG0SO / ENCA0TIN0 / ADCA0SEL2 / CAN1RX /INTP1 / RLIN24RX / MODE2

121 P10_7 / TAUD0I15 / TAUD0O15 / CSIG0SC / ENCA0TIN1 / PWGA4O / CAN1TX / RLIN24TX / TAUJ3I1 / TAUJ3O1

122 P10_8 / TAUD0I10 / TAUD0O10 / CSIG0SI / FLXA0TXDB / ENCA0EC / PWGA5O / FLMD1 / TAUJ3I2 / TAUJ3O2

123 P10_9 / TAUD0I12 / TAUD0O12 / RLIN30RX / INTP10 / ENCA0E0 / PWGA6O / CSIH0RYI / CSIH0RYO / FLXA0RXDB

124 P10_10 / TAUD0I14 / TAUD0O14 / RLIN30TX / ENCA0E1 / PWGA7O / CSIH0CSS1 / TAUJ3I3 / TAUJ3O3

125 P10_11 / PWGA16O / RLIN31RX / INTP11 / FLXA0TXENA / CSIH1CSS0 / TAUB0I1 / TAUB0O1

126 P10_12 / PWGA17O / FLXA0STPWT / RLIN31TX / CSIH1CSS1 / TAUB0I3 / TAUB0O3

127 P10_13 / CSIH0SSI / PWGA18O / RLIN32RX / INTP12 / FLXA0TXENB / TAUB0I5 / TAUB0O5 / CAN7TX

128 P10_14 / ADCA1TRG0 / PWGA19O / FLXA0RXDA / RLIN32TX / CSIH3SSI / TAUB0I7 / TAUB0O7 / CAN7RX / INTP9

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 287 of 4535 Dec 26, 2018 Table 2B.2 Pin Assignment 144-Pin LQFP Pin No. Pin Name

129 P11_1 / CSIH2SSI / FLXA0TXDA / RLIN20RX / CSIH0CSS7 / INTP20 / PWGA26O / TAUB0I13 / TAUB0O13

130 P11_2 / CSIH2SO / RLIN32RX / INTP12 / RLIN20TX / PWGA27O / TAUB0I15 / TAUB0O15 / SFMA0IO3

131 P11_3 / CSIH2SC / CAN3RX / INTP3 / PWGA28O / RLIN32TX / SFMA0IO2

132 P11_4 / CSIH2SI / CAN3TX / INTP21 / PWGA29O / SFMA0IO1

133 P11_5 / CAN5RX / INTP5 / RLIN33TX / PWGA30O / CSIH3SI / SFMA0IO0

134 P11_6 / RLIN33RX / INTP13 / CAN5TX / ADCA1TRG1 / PWGA31O / CSIH3SO / SFMA0SSL

135 P11_7 / INTP5 / PWGA32O / CSIH3SC / SFMA0CLK

136 P11_15 / CAN2RX / INTP2 / CSIH2CSS4 / PWGA55O

137 P12_0 / CAN2TX / PWGA56O

138 P12_1 / RLIN34RX / INTP14 / CSIH2CSS5 / PWGA57O

139 P12_2 / INTP19 / RLIN34TX / PWGA58O

141 BVSS

142 P10_0 / TAUD0I1 / TAUD0O1 / CAN0RX /INTP0 / CSCXFOUT / PWGA0O / TAPA0UP / CSIH1SI / TAUJ1I3 / TAUJ1O3

143 P10_1 / TAUD0I3 / TAUD0O3 / INTP18 / CAN0TX / PWGA1O / TAPA0UN / CSIH1SC / MODE0 / TAUJ3I0 / TAUJ3O0

144 P10_2 / TAUD0I5 / TAUD0O5 / RIIC0SDA / KR0I0 / PWGA2O / ADCA0TRG0 / TAPA0VP / CSIH1SO / MODE1

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 288 of 4535 Dec 26, 2018 Table 2B.3 Pin Assignment 176-Pin LQFP Pin No. Pin Name PWGA53O / ETNB0RXD2 / MEMC0A22 CSIG0RYO / ETNB0RXD3 / PWGA54O

23 P0_4 / RLIN31RX / INTP11 / CAN2TX / PWGA10O / CSIH1SI / SELDP0 /DPIN8 / TAUB0I12 / TAUB0O12

30 P1_0 / RLIN33RX / INTP13 / TAUJ2I0 / TAUJ2O0

31 P1_1 / INTP18 / RLIN33TX / TAUJ2I1 / TAUJ2O1

32 P1_2 / CAN3RX / INTP3 / DPIN19 / TAUJ2I2 / TAUJ2O2

33 P1_3 / INTP19 / CAN3TX / DPIN23 / TAUJ2I3 / TAUJ2O3

36 P2_6 / ADCA0SEL2

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 289 of 4535 Dec 26, 2018 Table 2B.3 Pin Assignment 176-Pin LQFP Pin No. Pin Name

46 JP0_1 / INTP1 /TAUJ0I0 / TAUJ0O0 / FPDT / DCUTDO / LPDO

47 JP0_0 / INTP0 / FPDR / FPDT / DCUTDI / LPDI / LPDIO / TAUJ2I0 / TAUJ2O0

49 P2_0 / RLIN27RX / INTP6 / CAN6RX

60 REGVCC

64 P2_3 / RLIN28TX

65 P2_2 / RLIN28RX

69 P0_8/ INTP16 / RLIN21TX / DPIN6 / CSIH0CSS6 / CSIH1SSI / TAUB0I2 / TAUB0O2 / CAN3TX

74 P1_5 / ADCA1TRG0 / RLIN35TX / DPIN17 / INTP20

75 P1_4 / RLIN35RX / INTP15 / DPIN18

76 P2_4 / RLIN29RX / ADCA0SEL0

77 P2_5 / RLIN29TX / ADCA0SEL1

78 P1_14 / RLIN23RX / CAN7RX / INTP9

80 P8_0 / TAUJ0I0 / TAUJ0O0 / DPIN2 / PWGA14O / INTP4 / CSIH0CSS0 / CAN6RX / INTP6 / ADCA0I0S / RIIC1SDA / SENT0RX

81 P8_1 / TAPA0ESO / TAUJ0O1 / DPIN0 / PWGA15O / INTP5 / CSIH1CSS3 / CAN6TX / ADCA0I1S / RIIC1SCL /

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 290 of 4535 Dec 26, 2018 Table 2B.3 Pin Assignment 176-Pin LQFP Pin No. Pin Name 108 P9_0 / NMI / PWGA8O / TAUD0I0 / TAUD0O0 / ADCA0TRG0 / CSIH2CSS0 / KR0I4 / ADCA0I2S / TAUJ1I1 / TAUJ1O1 / SENT1RX / RIIC1SDA

109 P9_1 / INTP11 / PWGA9O / TAUD0I2 / TAUD0O2 / KR0I5 / CSIH2CSS1 / ADCA0I3S / TAUJ1I2 / TAUJ1O2 /

114 REGVCC

118 P20_0 / RLIN26RX / PWGA64O / INTP6 / CAN6RX / CSIG3SI

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 291 of 4535 Dec 26, 2018 Table 2B.3 Pin Assignment 176-Pin LQFP Pin No. Pin Name

143 P18_0 / CSIG1RYI / CSIG1RYO / ETNB0LINK / PWGA61O / ADCA1I0S / TAUJ3I0 / TAUJ3O0

144 P18_1 / PWGA62O / ETNB0TXD0 / ADCA1I1S / TAUJ3I1 / TAUJ3O1

145 P18_2 / PWGA63O / ETNB0TXD1 / ADCA1I2S / TAUJ3I2 / TAUJ3O2

146 P18_3 / PWGA71O / ETNB0TXD2 / ADCA1I3S / TAUJ3I3 / TAUJ3O3

152 P10_6 / TAUD0I13 / TAUD0O13 / CSIG0SO / ENCA0TIN0 / ADCA0SEL2 / CAN1RX /INTP1 / MEMC0AD0 / RLIN24RX /

154 P10_8 / TAUD0I10 / TAUD0O10 / CSIG0SI / FLXA0TXDB / ENCA0EC / PWGA5O / MEMC0AD2 / FLMD1 / TAUJ3I2 /

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 292 of 4535 Dec 26, 2018 Table 2B.3 Pin Assignment 176-Pin LQFP Pin No. Pin Name

174 P10_0 / TAUD0I1 / TAUD0O1 / CAN0RX /INTP0 / CSCXFOUT / PWGA0O / TAPA0UP / CSIH1SI / MEMC0A19 /

ETNB0RXCLK / TAUJ1I3 / TAUJ1O3

175 P10_1 / TAUD0I3 / TAUD0O3 / INTP18 / CAN0TX / PWGA1O / TAPA0UN / CSIH1SC / ETNB0RXD0 / MEMC0A20 /

MEMC0A21 / RLIN37TX / MODE1

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 293 of 4535 Dec 26, 2018 Table 2B.4 Pin Assignment 233-Pin FPBGA Pin No. Pin Name A1 BVSS A2 P10_0 / TAUD0I1 / TAUD0O1 / CAN0RX / INTP0 / CSCXFOUT / PWGA0O / TAPA0UP / CSIH1SI / MEMC0A19 / ETNB0RXCLK / TAUJ1I3 / TAUJ1O3 A3 P12_2 / INTP19 / RLIN34TX / PWGA58O / TAUB1I14 / TAUB1O14 / MEMC0A18 / CSIG2RYI / CSIG2RYO A4 P11_5 / CAN5RX / INTP5 / RLIN33TX / PWGA30O / CSIH3SI / TAUB1I5 / TAUB1O5 / MEMC0AD13 / SFMA0IO0 A5 P11_1 / CSIH2SSI / FLXA0TXDA / RLIN20RX / CSIH0CSS7 / INTP20 / PWGA26O / TAUB0I13 / TAUB0O13 / MEMC0AD9 A6 P10_13 / CSIH0SSI / PWGA18O / RLIN32RX / INTP12 / FLXA0TXENB / TAUB0I5 / TAUB0O5 / MEMC0AD7 / CAN7TX A7 P10_10 / TAUD0I14 / TAUD0O14 / RLIN30TX / ENCA0E1 / PWGA7O / CSIH0CSS1 / MEMC0AD4 / TAUJ3I3 / TAUJ3O3 A8 P10_7 / TAUD0I15 / TAUD0O15 / CSIG0SC / ENCA0TIN1 / PWGA4O / CAN1TX / MEMC0AD1 / RLIN24TX / TAUJ3I1 / TAUJ3O1 A9 P10_6 / TAUD0I13 / TAUD0O13 / CSIG0SO / ENCA0TIN0 / ADCA0SEL2 / CAN1RX / INTP1 / MEMC0AD0 / RLIN24RX / MODE2 A10 P19_2 / ADCA1I18S A11 P18_15 / ADCA1I15S A12 P18_13 / ADCA1I13S A13 P18_6 / ADCA1I6S A14 P18_5 / CSIH1CSS5 / ETNB0TXEN / ADCA1I5S A15 P18_10 / ADCA1I10S A16 P18_8 / ADCA1I8S A17 A1VSS B1 P10_3 / TAUD0I7 / TAUD0O7 / RIIC0SCL / KR0I1 / PWGA3O / ADCA0TRG1 / TAPA0VN / CSIH1SSI / MEMC0CLK / RLIN37RX / INTP17 B2 P10_1 / TAUD0I3 / TAUD0O3 / INTP18 / CAN0TX / PWGA1O / TAPA0UN / CSIH1SC / ETNB0RXD0 / MEMC0A20 / MODE0 / TAUJ3I0 / TAUJ3O0 B3 P13_1 / MEMC0A20 B4 P12_0 / CAN2TX / PWGA56O / TAUB1I10 / TAUB1O10 / CSIG2SSI / MEMC0A16 / RLIN36RX / INTP16 B5 P11_4 / CSIH2SI / CAN3TX / INTP21 / PWGA29O / TAUB1I3 / TAUB1O3 / MEMC0AD12 / SFMA0IO1 B6 P11_3 / CSIH2SC / CAN3RX / INTP3 / PWGA28O / TAUB1I1 / TAUB1O1 / MEMC0AD11 / RLIN32TX / SFMA0IO2 B7 P10_14 / ADCA1TRG0 / PWGA19O / FLXA0RXDA / RLIN32TX / CSIH3SSI / TAUB0I7 / TAUB0O7 / MEMC0AD8 / CAN7RX / INTP9 B8 P10_9 / TAUD0I12 / TAUD0O12 / RLIN30RX / INTP10 / ENCA0E0 / PWGA6O / CSIH0RYI / CSIH0RYO / MEMC0AD3 / FLXA0RXDB B9 P19_3 / ADCA1I19S B10 P19_1 / ADCA1I17S B11 P18_7 / ETNB0TXCLK / ADCA1I7S B12 P18_11 / ADCA1I11S B13 P18_3 / PWGA71O / ETNB0TXD2 / ADCA1I3S / TAUJ3I3 / TAUJ3O3 B14 P18_2 / PWGA63O / ETNB0TXD1 / ADCA1I2S / TAUJ3I2 / TAUJ3O2 B15 P18_1 / PWGA62O / ETNB0TXD0 / ADCA1I1S / TAUJ3I1 / TAUJ3O1 B16 AP1_12 / ADCA1I12 B17 AP1_14 / ADCA1I14 C1 P10_15 / CSIH3RYI / CSIH3RYO / PWGA24O / RLIN22RX / TAUB0I9 / TAUB0O9 / MEMC0RD C2 P10_5 / TAUD0I11 / TAUD0O11 / CAN6RX / INTP6 / RLIN21TX / KR0I3 / ADCA0SEL1 / TAPA0WN / CSIG0RYI / CSIG0RYO / ETNB0RXD3 / PWGA54O

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 294 of 4535 Dec 26, 2018 Table 2B.4 Pin Assignment 233-Pin FPBGA Pin No. Pin Name C3 P10_2 / TAUD0I5 / TAUD0O5 / RIIC0SDA / KR0I0 / PWGA2O / ADCA0TRG0 / TAPA0VP / CSIH1SO / ETNB0RXD1 / MEMC0A21 / RLIN37TX / MODE1 C4 P13_0 / MEMC0A19 C5 P12_1 / RLIN34RX / INTP14 / CSIH2CSS5 / PWGA57O / TAUB1I12 / TAUB1O12 / MEMC0A17 C6 P11_7 / INTP5 / PWGA32O / CSIH3SC / TAUB1I9 / TAUB1O9 / MEMC0AD15 / SFMA0CLK C7 P11_2 / CSIH2SO / RLIN32RX / INTP12 / RLIN20TX / PWGA27O / TAUB0I15 / TAUB0O15 / MEMC0AD10 / SFMA0IO3 C8 P10_11 / PWGA16O / RLIN31RX / INTP11 / FLXA0TXENA / CSIH1CSS0 / TAUB0I1 / TAUB0O1 / MEMC0AD5 C9 P18_14 / ADCA1I14S C10 P19_0 / ADCA1I16S C11 P18_4 / CSIH1CSS4 / ETNB0TXD3 / ADCA1I4S C12 P18_12 / ADCA1I12S C13 P18_9 / ADCA1I9S C14 P18_0 / CSIG1RYI / CSIG1RYO / ETNB0LINK / PWGA61O / ADCA1I0S / TAUJ3I0 / TAUJ3O0 C15 AP1_13 / ADCA1I13 C16 AP1_15 / ADCA1I15 C17 AP1_0 / ADCA1I0 D1 P11_9 / CSIG1SO / RLIN35RX / INTP15 / PWGA49O / TAUB1I13 / TAUB1O13 / MEMC0CS1 D2 P11_0 / CSIH2RYI / CSIH2RYO / ADCA1TRG2 / PWGA25O / RLIN22TX / TAUB0I11 / TAUB0O11 / MEMC0WR D3 P10_4 / TAUD0I9 / TAUD0O9 / RLIN21RX / CAN6TX / KR0I2 / ADCA0SEL0 / ADCA0TRG2 / TAPA0WP / CSIG0SSI / PWGA53O / ETNB0RXD2 / MEMC0A22 D4 BVCC D5 P11_15 / CAN2RX / INTP2 / CSIH2CSS4 / PWGA55O / TAUB1I8 / TAUB1O8 / MEMC0ASTB / ETNB0RXERR / RLIN36TX D6 P11_6 / RLIN33RX / INTP13 / CAN5TX / ADCA1TRG1 / PWGA31O / CSIH3SO / TAUB1I7 / TAUB1O7 / MEMC0AD14 / SFMA0SSL D7 P10_12 / PWGA17O / FLXA0STPWT / RLIN31TX / CSIH1CSS1 / TAUB0I3 / TAUB0O3 / MEMC0AD6 D8 P10_8 / TAUD0I10 / TAUD0O10 / CSIG0SI / FLXA0TXDB / ENCA0EC / PWGA5O / MEMC0AD2 / FLMD1 / TAUJ3I2 / TAUJ3O2 D9 BVSS D10 BVCC D11 BVCC D12 ISOVSS D13 ISOVCL D14 A1VSS D15 AP1_1 / ADCA1I1 D16 AP1_2 / ADCA1I2 D17 AP1_3 / ADCA1I3 E1 P11_12 / RLIN25RX / PWGA52O / TAUB1I2 / TAUB1O2 / MEMC0WAIT E2 P11_10 / CSIG1SC / PWGA50O / TAUB1I15 / TAUB1O15 / MEMC0CS2 E3 P11_8 / CSIG1SSI / RLIN35TX / PWGA48O / TAUB1I11 / TAUB1O11 / MEMC0CS0 E4 BVCC E14 A1VREF E15 AP1_5 / ADCA1I5 E16 AP1_6 / ADCA1I6 E17 AP1_8 / ADCA1I8

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 295 of 4535 Dec 26, 2018 Table 2B.4 Pin Assignment 233-Pin FPBGA Pin No. Pin Name F1 P13_3 / ETNB0RXERR F2 P13_2 / ETNB0RXDV F3 P11_11 / CSIG1SI / RLIN25TX / PWGA51O / TAUB1I0 / TAUB1O0 / MEMC0CS3 / ETNB0RXDV F4 BVSS F14 AP1_4 / ADCA1I4 F15 AP1_7 / ADCA1I7 F16 AP1_9 / ADCA1I9 F17 P20_4 / RLIN23RX / INTP22 / PWGA59O / CAN7RX / INTP9 / CSIG3SSI G1 P12_3 / RLIN27RX / PWGA68O / CSIG2SI / MEMC0BEN0 / TAUB1I6 / TAUB1O6 G2 P13_4 G3 P13_5 / MEMC0A21 G4 ISOVCL G7 BVSS G8 BVSS G9 BVSS G10 BVSS G11 BVSS G14 AP1_10 / ADCA1I10 G15 AP1_11 / ADCA1I11 G16 P20_5 / RLIN23TX / INTP23 / PWGA60O / CAN7TX G17 P20_0 / RLIN26RX / PWGA64O / CAN6RX / INTP6 / CSIG3SI H1 P12_4 / RLIN27TX / PWGA69O / CSIG2SC / ETNB0MDIO / MEMC0BEN1 H2 P13_7 / PWGA73O H3 P13_6 / MEMC0A22 / PWGA72O H4 ISOVSS H7 BVSS H8 BVSS H9 BVSS H10 BVSS H11 EVSS H14 EVCC H15 P20_1 / RLIN26TX / PWGA65O / CAN6TX / CSIG3SO H16 P20_2 / CAN4RX / INTP4 / PWGA66O / RLIN29RX / CSIG3SC H17 P20_3 / CAN4TX / PWGA67O / RLIN29TX / CSIG3RYI / CSIG3RYO J1 P0_0 / TAUD0I2 / TAUD0O2 / RLIN20RX / CAN0TX / PWGA10O / CSIH0SSI / DPO / TAUJ2I1 / TAUJ2O1 J2 P0_1 / TAUD0I4 / TAUD0O4 / CAN0RX / INTP0 / RLIN20TX / PWGA11O / CSIH0SI / APO / TAUJ2I2 / TAUJ2O2 J3 P12_5 / PWGA70O / ETNB0MDC / CSIG2SO / TAUB1I4 / TAUB1O4 J4 P0_2 / TAUD0I6 / TAUD0O6 / CAN1RX / INTP1 / RLIN30TX / PWGA12O / CSIH0SC / DPO / TAUJ2I3 / TAUJ2O3 J7 BVSS J8 BVSS J9 BVSS J10 EVSS J11 EVSS J14 REGVCC J15 P9_3 / KR0I7 / PWGA21O / CSIH2CSS3 / TAUJ1I1 / TAUJ1O1 / INTP16 / ADCA0I10S

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 296 of 4535 Dec 26, 2018 Table 2B.4 Pin Assignment 233-Pin FPBGA Pin No. Pin Name J16 P9_4 / CSIH0CSS5 / PWGA33O / TAUJ1I0 / TAUJ1O0 / INTP17 / ADCA0I11S J17 P9_2 / KR0I6 / PWGA20O / TAPA0ESO / CSIH2CSS2 / ADCA0I9S K1 P0_3 / TAUD0I8 / TAUD0O8 / RLIN30RX / INTP10 / CAN1TX / DPIN1 / PWGA13O / CSIH0SO / TAUJ1I0 / TAUJ1O0 K2 P0_5 / CAN2RX / INTP2 / RLIN31TX / DPIN9 / SELDP1 / CSIH1SO / TAUB0I14 / TAUB0O14 K3 P0_4 / RLIN31RX / INTP11 / CAN2TX / PWGA10O / CSIH1SI / SELDP0 / DPIN8 / TAUB0I12 / TAUB0O12 K4 EVCC K7 EVSS K8 EVSS K9 EVSS K10 EVSS K11 EVSS K14 ISOVSS K15 AP0_0 / ADCA0I0 K16 P9_0 / NMI / PWGA8O / TAUD0I0 / TAUD0O0 / ADCA0TRG0 / CSIH2CSS0 / KR0I4 / ADCA0I2S / TAUJ1I1 / TAUJ1O1 / SENT1RX / RIIC1SDA K17 P9_1 / INTP11 / PWGA9O / TAUD0I2 / TAUD0O2 / KR0I5 / CSIH2CSS1 / ADCA0I3S / TAUJ1I2 / TAUJ1O2 / SENT1SPCO / RIIC1SCL L1 P0_11 / RIIC0SDA / DPIN12 / CSIH1CSS2 / TAUB0I8 / TAUB0O8 / RLIN26RX / PWGA34O L2 P0_12 / RIIC0SCL / DPIN13 / PWGA45O / TAUB0I10 / TAUB0O10 / CSIG0SI / RLIN26TX L3 P0_6 / INTP2 / DPIN10 / SELDP2 / CSIH1SC / PWGA35O L4 P0_14 / INTP17 / RLIN32TX / PWGA47O / TAUB0I14 / TAUB0O14 / CSIG0SC / CAN5TX L7 EVSS L8 EVSS L9 EVSS L10 EVSS L11 EVSS L14 EVSS L15 AP0_4 / ADCA0I4 L16 AP0_2 / ADCA0I2 L17 AP0_1 / ADCA0I1 M1 P0_13 / RLIN32RX / INTP12 / PWGA46O / TAUB0I12 / TAUB0O12 / CSIG0SO / CAN5RX / INTP5 M2 P1_0 / RLIN33RX / INTP13 / TAUJ2I0 / TAUJ2O0 M3 P2_9 / PWGA77O M4 P2_7 / RLIN210RX M14 A0VREF M15 AP0_8 / ADCA0I8 M16 AP0_5 / ADCA0I5 M17 AP0_3 / ADCA0I3 N1 P1_2 / CAN3RX / INTP3 / DPIN19 / TAUJ2I2 / TAUJ2O2 N2 P1_1 / INTP18 / RLIN33TX / TAUJ2I1 / TAUJ2O1 N3 P1_3 / INTP19 / CAN3TX / DPIN23 / TAUJ2I3 / TAUJ2O3 N4 P2_11 / PWGA79O N14 A0VSS N15 AP0_11 / ADCA0I11 N16 AP0_7 / ADCA0I7

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 297 of 4535 Dec 26, 2018 Table 2B.4 Pin Assignment 233-Pin FPBGA Pin No. Pin Name N17 AP0_6 / ADCA0I6 P1 P1_12 / CAN4RX / INTP4 / RLIN36TX P2 P1_13 / CAN4TX / RLIN36RX / INTP16 P3 P8_10 / CSIH3CSS3 / DPIN14 / PWGA42O / RLIN37RX / INTP17 / ADCA0I17S P4 P8_12 / TAUJ1I3 / TAUJ1O3 / DPIN16 / PWGA44O / CSIH1CSS5 / INTP23 / RLIN25TX / ADCA0I19S P5 JP0_1 / INTP1 / TAUJ0I0 / TAUJ0O0 / FPDT / DCUTDO / LPDO P6 P1_11 / ADCA1TRG2 / RLIN24TX / DPIN22 / INTP14 P7 P2_13 / RLIN211TX P8 P2_15 / PWGA75O P9 EVCC P10 REGVCC P11 ISOVSS P12 ISOVCL P13 P8_6 / NMI / CSIH0CSS4 / PWGA38O / RTCA0OUT / ADCA0I8S / RESETOUT P14 P8_8 / CSIH3CSS1 / PWGA40O / ADCA0SEL1 / RLIN34RX / INTP14 / ADCA0I15S P15 AP0_13 / ADCA0I13 P16 AP0_10 / ADCA0I10 P17 AP0_9 / ADCA0I9 R1 P2_6 / ADCA0SEL2 R2 P2_10 / PWGA78O R3 JP0_4 / DCUTRST R4 JP0_3 / INTP3 / CSCXFOUT / TAUJ0I2 / TAUJ0O2 / DCUTMS R5 P2_1 / RLIN27TX / CAN6TX R6 P1_10 / RLIN24RX / DPIN21 / INTP22 / ADCA1TRG1 R7 P1_9 / DPIN20 / INTP21 R8 P3_0 / PWGA76O R9 FLMD0 R10 P0_9 / INTP12 / CSIH1CSS0 / DPIN7 / RLIN22RX / TAUB0I4 / TAUB0O4 / CAN4RX / INTP4 R11 P0_7 / RLIN21RX / DPIN5 / CSCXFOUT / CSIH1RYI / CSIH1RYO / TAUB0I0 / TAUB0O0 / CAN3RX / INTP3 R12 P2_5 / RLIN29TX / ADCA0SEL1 R13 P1_15 / RLIN23TX / CAN7TX R14 P8_4 / TAUJ0I2 / TAUJ0O2 / DPIN4 / CSIH0CSS2 / INTP8 / PWGA36O / CAN7RX / INTP9 / ADCA0I6S R15 P8_7 / CSIH3CSS0 / PWGA39O / ADCA0SEL0 / RTCA0OUT / ADCA0I14S R16 AP0_14 / ADCA0I14 R17 AP0_12 / ADCA0I12 T1 P2_8 / RLIN210TX T2 P2_12 / RLIN211RX T3 P8_11 / TAUJ1I2 / TAUJ1O2 / DPIN15 / PWGA43O / CSIH1CSS4 / RLIN25RX / ADCA0I18S T4 JP0_2 / INTP2 / TAUJ0I1 / TAUJ0O1 / FPCK / DCUTCK / LPDCLK T5 P2_0 / RLIN27RX / CAN6RX / INTP6 T6 P2_14 / PWGA74O T7 IP0_0 / XT2 T8 AWOVCL T9 X1 T10 P2_2 / RLIN28RX

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 298 of 4535 Dec 26, 2018 Table 2B.4 Pin Assignment 233-Pin FPBGA Pin No. Pin Name T11 P0_10 / INTP3 / CSIH1CSS1 / DPIN11 / RLIN22TX / TAUB0I6 / TAUB0O6 / CAN4TX T12 P0_8 / INTP16 / RLIN21TX / DPIN6 / CSIH0CSS6 / CSIH1SSI / TAUB0I2 / TAUB0O2 / CAN3TX T13 P2_4 / RLIN29RX / ADCA0SEL0 T14 P8_1 / TAPA0ESO / TAUJ0O1 / DPIN0 / PWGA15O / INTP5 / CSIH1CSS3 / CAN6TX / ADCA0I1S / RIIC1SCL / SENT0SPCO T15 P8_5 / TAUJ0I3 / TAUJ0O3 / NMI / CSIH0CSS3 / INTP9 / PWGA37O / ADCA0I7S T16 P8_9 / CSIH3CSS2 / PWGA41O / ADCA0SEL2 / RLIN34TX / ADCA0I16S T17 AP0_15 / ADCA0I15 U1 EVSS U2 P8_2 / TAUJ0I0 / TAUJ0O0 / DPIN2 / CSIH0CSS0 / INTP6 / PWGA22O / RLIN37TX / ADCA0I4S U3 JP0_5 / NMI / RTCA0OUT / TAUJ0I3 / TAUJ0O3 / DCURDY / LPDCLKOUT U4 JP0_0 / INTP0 / FPDR / FPDT / DCUTDI / LPDI / LPDIO / TAUJ2I0 / TAUJ2O0 U5 P1_8 U6 RESET U7 XT1 U8 AWOVSS U9 X2 U10 P2_3 / RLIN28TX U11 JP0_6 / EVTO U12 P1_5 / ADCA1TRG0 / RLIN35TX / DPIN17 / INTP20 U13 P1_4 / RLIN35RX / INTP15 / DPIN18 U14 P1_14 / RLIN23RX / CAN7RX / INTP9 U15 P8_0 / TAUJ0I0 / TAUJ0O0 / DPIN2 / PWGA14O / INTP4 / CSIH0CSS0 / CAN6RX / INTP6 / ADCA0I0S / RIIC1SDA / SENT0RX U16 P8_3 / TAUJ0I1 / TAUJ0O1 / DPIN3 /CSIH0CSS1 / INTP7/ PWGA23O / CAN7TX / ADCA0I5S U17 A0VSS

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 299 of 4535 Dec 26, 2018 Table 2B.5 Pin Assignment 272-Pin FPBGA Pin No. Pin Name A1 BVSS A2 P22_7 A3 P13_1 / MEMC0A20 A4 P22_9 A5 P11_15 / CAN2RX / INTP2 / CSIH2CSS4 / PWGA55O / TAUB1I8 / TAUB1O8 / MEMC0ASTB / ETNB0RXERR / RLIN36TX A6 P22_12 A7 P22_13 A8 P22_15 A9 P11_1 / CSIH2SSI / FLXA0TXDA / RLIN20RX / CSIH0CSS7 / INTP20 / PWGA26O / TAUB0I13 / TAUB0O13 / MEMC0AD9 A10 P10_12 / PWGA17O / FLXA0STPWT / RLIN31TX / CSIH1CSS1 / TAUB0I3 / TAUB0O3 / MEMC0AD6 A11 P10_10 / TAUD0I14 / TAUD0O14 / RLIN30TX / ENCA0E1 / PWGA7O / CSIH0CSS1 / MEMC0AD4 / TAUJ3I3 / TAUJ3O3 A12 P10_6 / TAUD0I13 / TAUD0O13 / CSIG0SO / ENCA0TIN0 / ADCA0SEL2 / CAN1RX / INTP1 / MEMC0AD0 / RLIN24RX / MODE2 A13 P19_3 / ADCA1I19S A14 P19_0 / ADCA1I16S A15 P18_14 / ADCA1I14S A16 P18_6 / ADCA1I6S A17 P18_3 / PWGA71O / ETNB0TXD2 / ADCA1I3S / TAUJ3I3 / TAUJ3O3 A18 P18_9 / ADCA1I9S A19 P18_0 / CSIG1RYI / CSIG1RYO / ETNB0LINK / PWGA61O / ADCA1I0S / TAUJ3I0 / TAUJ3O0 A20 A1VSS B1 P22_6 B2 P10_3 / TAUD0I7 / TAUD0O7 / RIIC0SCL / KR0I1 / PWGA3O / ADCA0TRG1 / TAPA0VN / CSIH1SSI / MEMC0CLK / RLIN37RX / INTP17 B3 P10_1 / TAUD0I3 / TAUD0O3 / INTP18 / CAN0TX / PWGA1O / TAPA0UN / CSIH1SC / ETNB0RXD0 / MEMC0A20 / MODE0 / TAUJ3I0 / TAUJ3O0 B4 P22_8 B5 P12_1 / RLIN34RX / INTP14 / CSIH2CSS5 / PWGA57O / TAUB1I12 / TAUB1O12 / MEMC0A17 B6 P22_11 B7 P11_5 / CAN5RX / INTP5 / RLIN33TX / PWGA30O / CSIH3SI / TAUB1I5 / TAUB1O5 / MEMC0AD13 / SFMA0IO0 B8 P11_4 / CSIH2SI / CAN3TX / INTP21 / PWGA29O / TAUB1I3 / TAUB1O3 / MEMC0AD12 / SFMA0IO1 B9 P21_1 B10 P10_14 / ADCA1TRG0 / PWGA19O / FLXA0RXDA / RLIN32TX / CSIH3SSI / TAUB0I7 / TAUB0O7 / MEMC0AD8 / CAN7RX / INTP9 B11 P10_8 / TAUD0I10 / TAUD0O10 / CSIG0SI / FLXA0TXDB / ENCA0EC / PWGA5O / MEMC0AD2 / FLMD1 / TAUJ3I2 / TAUJ3O2 B12 P19_2 / ADCA1I18S B13 P19_1 / ADCA1I17S B14 P18_7 / ETNB0TXCLK / ADCA1I7S B15 P18_13 / ADCA1I13S B16 P18_4 / CSIH1CSS4 / ETNB0TXD3 / ADCA1I4S B17 P18_2 / PWGA63O / ETNB0TXD1 / ADCA1I2S / TAUJ3I2 / TAUJ3O2 B18 P18_1 / PWGA62O / ETNB0TXD0 / ADCA1I1S / TAUJ3I1 / TAUJ3O1 B19 AP1_12 / ADCA1I12

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 300 of 4535 Dec 26, 2018 Table 2B.5 Pin Assignment 272-Pin FPBGA Pin No. Pin Name B20 AP1_13 / ADCA1I13 C1 P22_4 C2 P22_5 C3 P10_2 / TAUD0I5 / TAUD0O5 / RIIC0SDA / KR0I0 / PWGA2O / ADCA0TRG0 / TAPA0VP / CSIH1SO / ETNB0RXD1 / MEMC0A21 / RLIN37TX / MODE1 C4 P10_0 / TAUD0I1 / TAUD0O1 / CAN0RX / INTP0 / CSCXFOUT / PWGA0O / TAPA0UP / CSIH1SI / MEMC0A19 / ETNB0RXCLK / TAUJ1I3 / TAUJ1O3 C5 P12_2 / INTP19 / RLIN34TX / PWGA58O / TAUB1I14 / TAUB1O14 / MEMC0A18 / CSIG2RYI / CSIG2RYO C6 P22_10 C7 P11_6 / RLIN33RX / INTP13 / CAN5TX / ADCA1TRG1 / PWGA31O / CSIH3SO / TAUB1I7 / TAUB1O7 / MEMC0AD14 / SFMA0SSL C8 P22_14 C9 P11_3 / CSIH2SC / CAN3RX / INTP3 / PWGA28O / TAUB1I1 / TAUB1O1 / MEMC0AD11 / RLIN32TX / SFMA0IO2 C10 P10_13 / CSIH0SSI / PWGA18O / RLIN32RX / INTP12 / FLXA0TXENB / TAUB0I5 / TAUB0O5 / MEMC0AD7 / CAN7TX C11 P10_7 / TAUD0I15 / TAUD0O15 / CSIG0SC / ENCA0TIN1 / PWGA4O / CAN1TX / MEMC0AD1 / RLIN24TX / TAUJ3I1 / TAUJ3O1 C12 P10_9 / TAUD0I12 / TAUD0O12 / RLIN30RX / INTP10 / ENCA0E0 / PWGA6O / CSIH0RYI / CSIH0RYO / MEMC0AD3 / FLXA0RXDB C13 P18_15 / ADCA1I15S C14 P18_12 / ADCA1I12S C15 P18_11 / ADCA1I11S C16 P18_10 / ADCA1I10S C17 P18_8 / ADCA1I8S C18 AP1_14 / ADCA1I14 C19 AP1_15 / ADCA1I15 C20 AP1_0 / ADCA1I0 D1 P10_15 / CSIH3RYI / CSIH3RYO / PWGA24O / RLIN22RX / TAUB0I9 / TAUB0O9 / MEMC0RD D2 P22_3 D3 P10_5 / TAUD0I11 / TAUD0O11 / CAN6RX / INTP6 / RLIN21TX / KR0I3 / ADCA0SEL1 / TAPA0WN / CSIG0RYI / CSIG0RYO / ETNB0RXD3 / PWGA54O D4 BVCC D5 BVCC D6 P13_0 / MEMC0A19 D7 P12_0 / CAN2TX / PWGA56O / TAUB1I10 / TAUB1O10 / CSIG2SSI / MEMC0A16 / RLIN36RX / INTP16 D8 P11_7 / INTP5 / PWGA32O / CSIH3SC / TAUB1I9 / TAUB1O9 / MEMC0AD15 / SFMA0CLK D9 P11_2 / CSIH2SO / RLIN32RX / INTP12 / RLIN20TX / PWGA27O / TAUB0I15 / TAUB0O15 / MEMC0AD10 / SFMA0IO3 D10 BVSS D11 P10_11 / PWGA16O / RLIN31RX / INTP11 / FLXA0TXENA / CSIH1CSS0 / TAUB0I1 / TAUB0O1 / MEMC0AD5 D12 BVCC D13 BVSS D14 P18_5 / CSIH1CSS5 / ETNB0TXEN / ADCA1I5S D15 ISOVSS D16 ISOVCL D17 BVCC

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 301 of 4535 Dec 26, 2018 Table 2B.5 Pin Assignment 272-Pin FPBGA Pin No. Pin Name D18 AP1_1 / ADCA1I1 D19 AP1_2 / ADCA1I2 D20 AP1_3 / ADCA1I3 E1 P11_0 / CSIH2RYI / CSIH2RYO / ADCA1TRG2 / PWGA25O / RLIN22TX / TAUB0I11 / TAUB0O11 / MEMC0WR E2 P11_8 / CSIG1SSI / RLIN35TX / PWGA48O / TAUB1I11 / TAUB1O11 / MEMC0CS0 E3 P10_4 / TAUD0I9 / TAUD0O9 / RLIN21RX / CAN6TX / KR0I2 / ADCA0SEL0 / ADCA0TRG2 / TAPA0WP / CSIG0SSI / PWGA53O / ETNB0RXD2 / MEMC0A22 E4 BVCC E17 A1VSS E18 AP1_4 / ADCA1I4 E19 AP1_5 / ADCA1I5 E20 AP1_6 / ADCA1I6 F1 P22_2 F2 P22_1 F3 P11_9 / CSIG1SO / RLIN35RX / INTP15 / PWGA49O / TAUB1I13 / TAUB1O13 / MEMC0CS1 F4 BVCC F17 A1VREF F18 AP1_7 / ADCA1I7 F19 AP1_9 / ADCA1I9 F20 AP1_10 / ADCA1I10 G1 P22_0 G2 P11_11 / CSIG1SI / RLIN25TX / PWGA51O / TAUB1I0 / TAUB1O0 / MEMC0CS3 / ETNB0RXDV G3 P11_10 / CSIG1SC / PWGA50O / TAUB1I15 / TAUB1O15 / MEMC0CS2 G4 BVSS G17 AP1_8 / ADCA1I8 G18 AP1_11 / ADCA1I11 G19 P20_6 / PWGA88O G20 P20_7 / PWGA89O H1 P21_4 H2 P11_12 / RLIN25RX / PWGA52O / TAUB1I2 / TAUB1O2 / MEMC0WAIT H3 P21_0 H4 ISOVCL H17 EVCC H18 P20_8 / PWGA90O H19 P20_9 / PWGA91O H20 P20_4 / RLIN23RX / INTP22 / PWGA59O / CAN7RX / INTP9 / CSIG3SSI J1 P13_3 / ETNB0RXERR J2 P21_3 J3 P21_2 J4 ISOVSS J9 BVSS J10 BVSS J11 BVSS J12 BVSS J17 EVSS J18 P20_5 / RLIN23TX / INTP23 / PWGA60O / CAN7TX

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 302 of 4535 Dec 26, 2018 Table 2B.5 Pin Assignment 272-Pin FPBGA Pin No. Pin Name J19 P20_0 / RLIN26RX / PWGA64O / CAN6RX / INTP6 / CSIG3SI J20 P20_1 / RLIN26TX / PWGA65O / CAN6TX / CSIG3SO K1 P13_4 K2 P13_6 / MEMC0A22 / PWGA72O K3 P13_2 / ETNB0RXDV K4 BVSS K9 BVSS K10 BVSS K11 BVSS K12 EVSS K17 EVCC K18 P20_3 / CAN4TX / PWGA67O / RLIN29TX / CSIG3RYI / CSIG3RYO K19 P20_10 / PWGA92O K20 P20_2 / CAN4RX / INTP4 / PWGA66O / RLIN29RX / CSIG3SC L1 P12_3 / RLIN27RX / PWGA68O / CSIG2SI / MEMC0BEN0 / TAUB1I6 / TAUB1O6 L2 P12_5 / PWGA70O / ETNB0MDC / CSIG2SO / TAUB1I4 / TAUB1O4 L3 P0_3 / TAUD0I8 / TAUD0O8 / RLIN30RX / INTP10 / CAN1TX / DPIN1 / PWGA13O / CSIH0SO / TAUJ1I0 / TAUJ1O0 L4 P13_5 / MEMC0A21 L9 BVSS L10 EVSS L11 EVSS L12 EVSS L17 REGVCC L18 P20_13 / PWGA95O L19 P20_12 / PWGA94O L20 P20_11 / PWGA93O M1 P0_0 / TAUD0I2 / TAUD0O2 / RLIN20RX / CAN0TX / PWGA10O / CSIH0SSI / DPO / TAUJ2I1 / TAUJ2O1 M2 P0_1 / TAUD0I4 / TAUD0O4 / CAN0RX / INTP0 / RLIN20TX / PWGA11O / CSIH0SI / APO / TAUJ2I2 / TAUJ2O2 M3 P0_6 / INTP2 / DPIN10 / SELDP2 / CSIH1SC / PWGA35O M4 P13_7 / MEMC0A23 / PWGA73O M9 EVSS M10 EVSS M11 EVSS M12 EVSS M17 ISOVSS M18 P9_3 / KR0I7 / PWGA21O / CSIH2CSS3 / TAUJ1I1 / TAUJ1O1 / INTP16 / ADCA0I10S M19 P9_4 / CSIH0CSS5 / PWGA33O / TAUJ1I0 / TAUJ1O0 / INTP17 / ADCA0I11S M20 P20_14 N1 P0_4 / RLIN31RX / INTP11 / CAN2TX / PWGA10O / CSIH1SI / SELDP0 / DPIN8 / TAUB0I12 / TAUB0O12 N2 P0_5 / CAN2RX / INTP2 / RLIN31TX / DPIN9 / SELDP1 / CSIH1SO / TAUB0I14 / TAUB0O14 N3 P12_4 / RLIN27TX / PWGA69O / CSIG2SC / ETNB0MDIO / MEMC0BEN1 N4 P0_2 / TAUD0I6 / TAUD0O6 / CAN1RX / INTP1 / RLIN30TX / PWGA12O / CSIH0SC / DPO / TAUJ2I3 / TAUJ2O3 N17 EVSS

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 303 of 4535 Dec 26, 2018 Table 2B.5 Pin Assignment 272-Pin FPBGA Pin No. Pin Name N18 P9_0 / NMI / PWGA8O / TAUD0I0 / TAUD0O0 / ADCA0TRG0 / CSIH2CSS0 / KR0I4 / ADCA0I2S / TAUJ1I1 / TAUJ1O1 / SENT1RX / RIIC1SDA N19 P9_1 / INTP11 / PWGA9O / TAUD0I2 / TAUD0O2 / KR0I5 / CSIH2CSS1 / ADCA0I3S / TAUJ1I2 / TAUJ1O2 / SENT1SPCO / RIIC1SCL N20 P9_2 / KR0I6 / PWGA20O / TAPA0ESO / CSIH2CSS2 / ADCA0I9S P1 P0_11 / RIIC0SDA / DPIN12 / CSIH1CSS2 / TAUB0I8 / TAUB0O8 / RLIN26RX / PWGA34O P2 P0_12 / RIIC0SCL / DPIN13 / PWGA45O / TAUB0I10 / TAUB0O10 / CSIG0SI / RLIN26TX P3 P0_14 / INTP17 / RLIN32TX / PWGA47O / TAUB0I14 / TAUB0O14 / CSIG0SC / CAN5TX P4 EVCC P17 AP0_6 / ADCA0I6 P18 AP0_3 / ADCA0I3 P19 AP0_1 / ADCA0I1 P20 AP0_0 / ADCA0I0 R1 P0_13 / RLIN32RX / INTP12 / PWGA46O / TAUB0I12 / TAUB0O12 / CSIG0SO / CAN5RX / INTP5 R2 P1_1 / INTP18 / RLIN33TX / TAUJ2I1 / TAUJ2O1 R3 P2_6 / ADCA0SEL2 R4 P1_3 / INTP19 / CAN3TX / DPIN23 / TAUJ2I3 / TAUJ2O3 R17 A0VREF R18 AP0_7 / ADCA0I7 R19 AP0_4 / ADCA0I4 R20 AP0_2 / ADCA0I2 T1 P1_0 / RLIN33RX / INTP13 / TAUJ2I0 / TAUJ2O0 T2 P1_12 / CAN4RX / INTP4 / RLIN36TX T3 P2_8 / RLIN210TX T4 P2_9 / PWGA77O T17 A0VSS T18 AP0_10 / ADCA0I10 T19 AP0_8 / ADCA0I8 T20 AP0_5 / ADCA0I5 U1 P1_2 / CAN3RX / INTP3 / DPIN19 / TAUJ2I2 / TAUJ2O2 U2 P2_7 / RLIN210RX U3 P2_11 / PWGA79O U4 P8_12 / TAUJ1I3 / TAUJ1O3 / DPIN16 / PWGA44O / CSIH1CSS5 / INTP23 / RLIN25TX / ADCA0I19S U5 JP0_2 / INTP2 / TAUJ0I1 / TAUJ0O1 / FPCK / DCUTCK / LPDCLK U6 P1_9 / DPIN20 / INTP21 U7 EVCC U8 AWOVCL U9 REGVCC U10 P0_9 / INTP12 / CSIH1CSS0 / DPIN7 / RLIN22RX / TAUB0I4 / TAUB0O4 / CAN4RX / INTP4 U11 ISOVSS U12 ISOVCL U13 P1_15 / RLIN23TX / CAN7TX U14 EVSS U15 EVCC U16 P3_7 / PWGA86O U17 P3_10

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 304 of 4535 Dec 26, 2018 Table 2B.5 Pin Assignment 272-Pin FPBGA Pin No. Pin Name U18 AP0_13 / ADCA0I13 U19 AP0_11 / ADCA0I11 U20 AP0_9 / ADCA0I9 V1 P1_13 / CAN4TX / RLIN36RX / INTP16 V2 P2_12 / RLIN211RX V3 P8_10 / CSIH3CSS3 / DPIN14 / PWGA42O / RLIN37RX / INTP17 / ADCA0I17S V4 JP0_3 / INTP3 / CSCXFOUT / TAUJ0I2 / TAUJ0O2 / DCUTMS V5 JP0_0 / INTP0 / FPDR / FPDT / DCUTDI / LPDI / LPDIO / TAUJ2I0 / TAUJ2O0 V6 P1_11 / ADCA1TRG2 / RLIN24TX / DPIN22 / INTP14 V7 P2_13 / RLIN211TX V8 P3_0 / PWGA76O V9 FLMD0 V10 P0_8 / INTP16 / RLIN21TX / DPIN6 / CSIH0CSS6 / CSIH1SSI / TAUB0I2 / TAUB0O2 / CAN3TX V11 P0_7 / RLIN21RX / DPIN5 / CSCXFOUT / CSIH1RYI / CSIH1RYO / TAUB0I0 / TAUB0O0 / CAN3RX / INTP3 V12 P2_5 / RLIN29TX / ADCA0SEL1 V13 P8_1 / TAPA0ESO / TAUJ0O1 / DPIN0 / PWGA15O / INTP5 / CSIH1CSS3 / CAN6TX / ADCA0I1S / RIIC1SCL / SENT0SPCO V14 P3_1 / PWGA80O V15 P8_7 / CSIH3CSS0 / PWGA39O / ADCA0SEL0 / RTCA0OUT / ADCA0I14S V16 P3_3 / PWGA82O V17 P3_6 / PWGA85O V18 P3_9 V19 AP0_14 / ADCA0I14 V20 AP0_12 / ADCA0I12 W1 P2_10 / PWGA78O W2 P8_2 / TAUJ0I0 / TAUJ0O0 / DPIN2 / CSIH0CSS0 / INTP6 / PWGA22O / RLIN37TX / ADCA0I4S W3 JP0_5 / NMI / RTCA0OUT / TAUJ0I3 / TAUJ0O3 / DCURDY / LPDCLKOUT W4 JP0_1 / INTP1 / TAUJ0I0 / TAUJ0O0 / FPDT / DCUTDO / LPDO W5 P2_0 / RLIN27RX / CAN6RX / INTP6 W6 P2_14 / PWGA74O W7 P2_15 / PWGA75O W8 IP0_0 / XT2 W9 P2_3 / RLIN28TX W10 P2_2 / RLIN28RX W11 JP0_6 / EVTO W12 P1_4 / RLIN35RX / INTP15 / DPIN18 W13 P2_4 / RLIN29RX / ADCA0SEL0 W14 P8_0 / TAUJ0I0 / TAUJ0O0 / DPIN2 / PWGA14O / INTP4 / CSIH0CSS0 / CAN6RX / INTP6 / ADCA0I0S / RIIC1SDA / SENT0RX W15 P8_4 / TAUJ0I2 / TAUJ0O2 / DPIN4 / CSIH0CSS2 / INTP8 / PWGA36O / CAN7RX / INTP9 / ADCA0I6S W16 P3_2 / PWGA81O W17 P8_8 / CSIH3CSS1 / PWGA40O / ADCA0SEL1 / RLIN34RX / INTP14 / ADCA0I15S W18 P3_4 / PWGA83O W19 P3_8 / PWGA87O W20 AP0_15 / ADCA0I15 Y1 EVSS

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 305 of 4535 Dec 26, 2018 Table 2B.5 Pin Assignment 272-Pin FPBGA Pin No. Pin Name Y2 P8_11 / TAUJ1I2 / TAUJ1O2 / DPIN15 / PWGA43O / CSIH1CSS4 / RLIN25RX / ADCA0I18S Y3 JP0_4 / DCUTRST Y4 P2_1 / RLIN27TX / CAN6TX Y5 P1_10 / RLIN24RX / DPIN21 / INTP22 / ADCA1TRG1 Y6 P1_8 Y7 RESET Y8 XT1 Y9 AWOVSS Y10 X2 Y11 X1 Y12 P0_10 / INTP3 / CSIH1CSS1 / DPIN11 / RLIN22TX / TAUB0I6 / TAUB0O6 / CAN4TX Y13 P1_5 / ADCA1TRG0 / RLIN35TX / DPIN17 / INTP20 Y14 P1_14 / RLIN23RX / CAN7RX / INTP9 Y15 P8_3 / TAUJ0I1 / TAUJ0O1 / DPIN3 / CSIH0CSS1 / INTP7 / PWGA23O / CAN7TX / ADCA0I5S Y16 P8_5 / TAUJ0I3 / TAUJ0O3 / NMI / CSIH0CSS3 / INTP9 / PWGA37O / ADCA0I7S Y17 P8_6 / NMI / CSIH0CSS4 / PWGA38O / RTCA0OUT / ADCA0I8S / RESETOUT Y18 P8_9 / CSIH3CSS2 / PWGA41O / ADCA0SEL2 / RLIN34TX / ADCA0I16S Y19 P3_5 / PWGA84O Y20 A0VSS

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 306 of 4535 Dec 26, 2018 2B.2 Pin Description Table 2B.6 Pin Functions Pin Name No. of Pins IO Pin Function Unit 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins AnVREF      — ADCAn voltage supply and reference voltage ADCAn n = 0 n = 0, 1 n = 0, 1 n = 0, 1 n = 0, 1 AnVSS      — ADCAn ground n = 0 n = 0, 1 n = 0, 1 n = 0, 1 n = 0, 1 ADCA0Im      I ADCA0 input channel m with 12-bit resolution m = 0 to 15 m = 0 to 15 m = 0 to 15 m = 0 to 15 m = 0 to 15 ADCA1Im —     I ADCA1 input channel m with 12-bit resolution m = 0 to 7 m = 0 to 15 m = 0 to 15 m = 0 to 15 ADCA0ImS      I ADCA0 input channel m with 10-bit resolution m = 2 to 11, 14 to 19 m = 0 to 11, 14 to 19 m = 0 to 11, 14 to 19 m = 0 to 11, 14 to 19 m = 0 to 11, 14 to 19 ADCA1ImS —     I ADCA1 input channel m with 10-bit resolution m = 0 to 3 m = 0 to 7 m = 0 to 19 m = 0 to 19 ADCA0SELy      O Selection pin y for ADCA0 input and external MPX y = 0 to 2 y = 0 to 2 y = 0 to 2 y = 0 to 2 y = 0 to 2 ADCAnTRGy      I ADCAn external trigger pin y n = 0, y = 0 to 2 n = 0, 1, y = 0 to 2 n = 0, 1, y = 0 to 2 n = 0, 1, y = 0 to 2 n = 0, 1, y = 0 to 2 AP0_m      IO Analog port 0_m Port m = 0 to 15 m = 0 to 15 m = 0 to 15 m = 0 to 15 m = 0 to 15 m = 0 to 7 m = 0 to 15 m = 0 to 15 m = 0 to 15 APO      O Port output signal for analog input LPS0 AWOVCL      — Voltage regulator for Always-On area (AWO area) capacitor connection Power AWOVSS      — Internal logic for Always-On area (AWO area) ground BVCC —     — Port buffer voltage supply BVSS —     — Port buffer ground CANzRX      I CANz receive data input RCFDCn z = 0 to 7 z = 0 to 7 z = 0 to 7 z = 0 to 7 z = 0 to 7 CANzTX      O CANz transmit data output z = 0 to 7 z = 0 to 7 z = 0 to 7 z = 0 to 7 z = 0 to 7 CSCXFOUT      O Clock output Clock CSIGnRYI      I CSIGn ready (1) / busy (0) input signal CSIGn n = 0 n = 0, 1 n = 0 to 3 n = 0 to 3 n = 0 to 3 CSIGnRYO      O CSIGn ready (1) / busy (0) output signal n = 0 n = 0, 1 n = 0 to 3 n = 0 to 3 n = 0 to 3 CSIGnSC      IO CSIGn serial clock signal n = 0 n = 0, 1 n = 0 to 3 n = 0 to 3 n = 0 to 3 CSIGnSI      I CSIGn serial data input n = 0 n = 0, 1 n = 0 to 3 n = 0 to 3 n = 0 to 3 CSIGnSO      O CSIGn serial data output n = 0 n = 0, 1 n = 0 to 3 n = 0 to 3 n = 0 to 3 CSIGnSSI      I CSIGn SS function control input signal n = 0 n = 0, 1 n = 0 to 3 n = 0 to 3 n = 0 to 3 CSIHnCSS0      O CSIHn serial peripheral chip select signal 0 CSIHn n = 0 to 3 n = 0 to 3 n = 0 to 3 n = 0 to 3 n = 0 to 3 CSIHnCSS1      O CSIHn serial peripheral chip select signal 1 n = 0 to 3 n = 0 to 3 n = 0 to 3 n = 0 to 3 n = 0 to 3

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 307 of 4535 Dec 26, 2018 Table 2B.6 Pin Functions Pin Name No. of Pins IO Pin Function Unit 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins CSIHnCSS2      O CSIHn serial peripheral chip select signal 2 CSIHn n = 0 to 3 n = 0 to 3 n = 0 to 3 n = 0 to 3 n = 0 to 3 CSIHnCSS3      O CSIHn serial peripheral chip select signal 3 n = 0, 2, 3 n = 0 to 3 n = 0 to 3 n = 0 to 3 n = 0 to 3 CSIHnCSS4      O CSIHn serial peripheral chip select signal 4 n = 0, 1 n = 0 to 2 n = 0 to 2 n = 0 to 2 n = 0 to 2 CSIHnCSS5      O CSIHn serial peripheral chip select signal 5 n = 0, 1 n = 0 to 2 n = 0 to 2 n = 0 to 2 n = 0 to 2 CSIHnCSS6      O CSIHn serial peripheral chip select signal 6 n = 0 n = 0 n = 0 n = 0 n = 0 CSIHnCSS7      O CSIHn serial peripheral chip select signal 7 n = 0 n = 0 n = 0 n = 0 n = 0 CSIHnRYI      I CSIHn ready (1) / busy (0) input signal n = 0, 1 n = 0 to 3 n = 0 to 3 n = 0 to 3 n = 0 to 3 CSIHnRYO      O CSIHn ready (1) / busy (0) output signal n = 0, 1 n = 0 to 3 n = 0 to 3 n = 0 to 3 n = 0 to 3 CSIHnSC      IO CSIHn serial clock signal n = 0 to 3 n = 0 to 3 n = 0 to 3 n = 0 to 3 n = 0 to 3 CSIHnSI      I CSIHn serial data input n = 0 to 3 n = 0 to 3 n = 0 to 3 n = 0 to 3 n = 0 to 3 CSIHnSO      O CSIHn serial data output n = 0 to 3 n = 0 to 3 n = 0 to 3 n = 0 to 3 n = 0 to 3 CSIHnSSI      I CSIHn slave select input signal n = 0 to 3 n = 0 to 3 n = 0 to 3 n = 0 to 3 n = 0 to 3 DCURDY      O Debug ready OCD DCUTCK      I Debug clock DCUTDI      I Debug data input DCUTDO      O Debug data output DCUTMS      I Debug mode select DCUTRST      I Debug reset OCD DPINm      I Digital port input m LPS0 m = 1 to 16 m = 0 to 23 m = 0 to 23 m = 0 to 23 m = 0 to 23 DPO      O Port output signal for digital input ENCA0TINm      I ENCA0 capture trigger input m ENCAn m = 0, 1 m = 0, 1 m = 0, 1 m = 0, 1 m = 0, 1 ENCA0E0      I ENCA0 encoder input 0 ENCA0E1      I ENCA0 encoder input 1 ENCA0EC      I ENCA0 encoder clear input ETNB0LINK — ―    I PHY link status ETNBn ETNB0MDC — ―    O PHY management clock ETNB0MDIO — ―    IO Management transmit / receive data signal ETNB0RXCLK — ―    I MII receive clock ETNB0RXD[3:0] — ―    I MII receive data input ETNB0RXDV — ―    I MII receive data valid ETNB0RXERR — ―    I MII receive error

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 308 of 4535 Dec 26, 2018 Table 2B.6 Pin Functions Pin Name No. of Pins IO Pin Function Unit 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins ETNB0TXCLK — ―    I MII transmit clock ETNBn ETNB0TXD[3:0] — ―    O MII transmit data output ETNB0TXEN — ―    O MII transmit data enable EVCC      — Port buffer voltage supply Power EVSS      — Port buffer ground EVTO —     O Event output TEU_OUT FLMD0      I Operating mode select pin 0 Mode FLMD1      I Operating mode select pin 1 FLXA0RXDA      I FLXA0 channel A receive data input FLXAn FLXA0RXDB      I FLXA0 channel B receive data input FLXA0STPWT      I FLXA0 stop watch trigger input FLXA0TXDA      O FLXA0 channel A transmit data output FLXA0TXDB      O FLXA0 channel B transmit data output FLXA0TXENA      O FLXA0 channel A transmit enable FLXA0TXENB      O FLXA0 channel B transmit enable FPDR      I Serial Communication Interface RXD FLASH FPDT      O Serial Communication Interface TXD FPCK      I Serial Communication Interface clock INTPm      I External interrupt input m INTC m = 0 to 13 m = 0 to 23 m = 0 to 23 m = 0 to 23 m = 0 to 23 IP0_0 —     I Input port 0_0 Port ISOVCL      — Voltage regulator for Isolated area (ISO area) capacitor connection Power ISOVSS      — Internal logic for Isolated area (ISO area) ground JP0_m      IO JTAG port 0_m JTAG m = 0 to 5 m = 0 to 6 m = 0 to 6 m = 0 to 6 m = 0 to 6 KR0Im      I KR0 key input signal KRn m = 0 to 7 m = 0 to 7 m = 0 to 7 m = 0 to 7 m = 0 to 7 LPDCLK      I LPD clock input (4-pin mode) LPD LPDCLKOUT      O LPD clock output (4-pin mode) LPDI      I LPD data input (4-pin mode) LPDIO      IO LPD data input / output (1-pin mode) LPDO      O LPD data output (4-pin mode) MEMC0Am — —    O MEMC0 address m MEMCn m = 16 to 22 m = 16 to 22 m = 16 to 23 MEMC0ADm — —    IO MEMC0 address / data m m = 0 to 15 m = 0 to 15 m = 0 to 15 MEMC0ASTB — —    O MEMC0 address strobe MEMC0BENm — —    O MEMC0 byte enable m m = 0, 1 m = 0, 1 m = 0, 1 MEMC0CLK — —    O MEMC0 clock output MEMC0CSm — —    O MEMC0 chip select m m = 0 to 3 m = 0 to 3 m = 0 to 3 MEMC0RD — —    O MEMC0 read strobe MEMC0WAIT — —    I MEMC0 wait input MEMC0WR — —    O MEMC0 write strobe MODEm      I Sub operating mode select Mode m = 0 to 2 m = 0 to 2 m = 0 to 2 m = 0 to 2 m = 0 to 2 NMI      I External non-maskable interrupt input INTC

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 309 of 4535 Dec 26, 2018 Table 2B.6 Pin Functions Pin Name No. of Pins IO Pin Function Unit 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins m = 0 to 14 m = 0 to 14 m = 0 to 14 m = 0 to 14 m = 0 to 14 m = 0 to 5, 8 to 11 m = 0 to 5, 8 to 15 m = 0 to 5, 8 to 15 m = 0 to 5, 8 to 15 m = 0 to 6 m = 0 to 15 m = 0 to 15 m = 0 m = 0 to 10 m = 2 to 12 m = 0 to 12 m = 0 to 12 m = 0 to 12 m = 0 to 12 m = 0 to 4 m = 0 to 4 m = 0 to 4 m = 0 to 4 m = 0 to 4 m = 0 to 14 m = 0 to 15 m = 0 to 15 m = 0 to 15 m = 0 to 15 m = 1 to 7 m = 0 to 12, m = 0 to 12, m = 0 to 12, m = 0 to 12, m = 0 to 2 m = 0 to 5 m = 0 to 5 m = 0 to 5 m = 0 to 7 m = 0 to 7 m = 0 to 3 m = 0 to 7 m = 0 to 15 m = 0 to 15 m = 0 to 3 m = 0 to 3 m = 4, 5 m = 0 to 5 m = 0 to 5 m = 0 to 14 m = 0 to 4 m = 0 to 15 PWGAnO      O PWGAn output signal PWGAn n = 0 to 13, 16 to 23, 26 to 47 n = 0 to 63 n = 0 to 71 n = 0 to 79 n = 0 to 95 REGVCC      — Voltage regulators voltage supply Power RESET      I External reset input Reset RESETOUT      O Reset output RIICnSCL      IO RIICn serial clock RIICn n = 0, 1 n = 0, 1 n = 0, 1 n = 0, 1 n = 0, 1 RIICnSDA      IO RIICn serial data n = 0, 1 n = 0, 1 n = 0, 1 n = 0, 1 n = 0, 1 RLIN2mRX      I RLIN2m receive data input RLIN24n m = 0 to 2 m = 0 to 5 m = 0 to 9 m = 0 to 11 m = 0 to 11 RLIN2mTX      O RLIN2m transmit data output m = 0 to 2 m = 0 to 5 m = 0 to 9 m = 0 to 11 m = 0 to 11 RLIN3nRX      I RLIN3n receive data input RLIN3n n = 0 to 2 n = 0 to 5 n = 0 to 7 n = 0 to 7 n = 0 to 7 RLIN3nTX      O RLIN3n transmit data output n = 0 to 2 n = 0 to 5 n = 0 to 7 n = 0 to 7 n = 0 to 7 RTCA0OUT      O RTCA0 1Hz output RTCAn

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 310 of 4535 Dec 26, 2018 Table 2B.6 Pin Functions Pin Name No. of Pins IO Pin Function Unit 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins SELDPk      O External multiplexer select signal output k for the digital port LPS0 k = 0 to 2 k = 0 to 2 k = 0 to 2 k = 0 to 2 k = 0 to 2 SENTnRX      I SENT receive data input RSENTn n = 1 n = 0 to 1 n = 0 to 1 n = 0 to 1 n = 0 to 1 SENTnSPCO      O SENT SPC Extension Output n = 1 n = 0 to 1 n = 0 to 1 n = 0 to 1 n = 0 to 1 SFMA0CLK ―     O SFMA0 clock SFMAn SFMA0IOm ―     IO SFMA0 master data input / output m = 0 to 3 m = 0 to 3 m = 0 to 3 m = 0 to 3 SFMA0SSL ―     O SFMA0 slave select TAPA0ESO      I Hi-Z control TAPAn TAPA0UN      O Motor control output U phase (negative) TAPA0UP      O Motor control output U phase (positive) TAPA0VN      O Motor control output V phase (negative) TAPA0VP      O Motor control output V phase (positive) TAPA0WN      O Motor control output W phase (negative) TAPA0WP      O Motor control output W phase (positive) TAUBnIm      I TAUBn channel input m TAUBn n = 0, m = 0 to 8, 10, 12 to 15 n = 0, m = 0 to 15 n = 0, 1, m = 0 to 15 n = 0, 1, m = 0 to 15 n = 0, 1, m = 0 to 15 TAUBnOm      O TAUBn channel output m n = 0, m = 0 to 8, 10, 12 to 15 n = 0, m = 0 to 15 n = 0, 1, m = 0 to 15 n = 0, 1, m = 0 to 15 n = 0, 1, m = 0 to 15 TAUD0Im      I TAUD0 channel input m TAUDn m = 0 to 15 m = 0 to 15 m = 0 to 15 m = 0 to 15 m = 0 to 15 TAUD0Om      O TAUD0 channel output m m = 0 to 15 m = 0 to 15 m = 0 to 15 m = 0 to 15 m = 0 to 15 TAUJnIm      I TAUJn channel input m TAUJn n = 0 to 3, m = 0 to 3 n = 0 to 3, m = 0 to 3 n = 0 to 3, m = 0 to 3 n = 0 to 3, m = 0 to 3 n = 0 to 3, m = 0 to 3 TAUJnOm      O TAUJn channel output m n = 0 to 3, m = 0 to 3 n = 0 to 3, m = 0 to 3 n = 0 to 3, m = 0 to 3 n = 0 to 3, m = 0 to 3 n = 0 to 3, m = 0 to 3 X1, X2      — Main OSC connections MOSC XT1, XT2 ―     — Sub OSC connections SOSC CAUTION When pin functions for a peripheral module are allocated to multiple pins, use the pins from the same port group or nearby pins as the pins for a given channel.

• (e.g.) When RS-CANFD channel 0 is used: CAN0TX P0_0 P10_1 CAN0RX P0_1 P10_0 Use one of the following pin combinations: - P0_0 and P0_1, or - P10_0 and P10_1. The combinations of P0_0 and P10_0, and P0_1 and P10_1 are not allowed.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 311 of 4535 Dec 26, 2018 2B.3 Pin Functions During and After Reset Table 2B.7 Pin Functions During and After Reset Pins During Reset After Reset JP0_0 High impedance JP0_0: Input Serial programming mode: FPDR, FPDT (1 wire UART) FPDR (2 wire UART) Nexus I/F: DCUTDI input LPD (4 pins): LPDI input LPD (1 pin): LPDIO input/output JP0_1 High impedance JP0_1: Input Serial programming mode: FPDT Nexus I/F: DCUTDO output LPD (4 pins): LPDO output LPD (1 pin): High impedance JP0_2 High impedance JP0_2: Input Serial programming mode: FPCK Nexus I/F: DCUTCK input LPD (4 pins): LPDCLK input LPD (1 pin): High impedance JP0_3 High impedance JP0_3: Input Serial programming mode: High impedance Nexus I/F: DCUTMS input LPD (4 pins): High impedance LPD (1 pin): High impedance JP0_4 Input*3,*5 JP0_4: Input Serial programming mode: High impedance Nexus I/F: DCUTRST input*1 LPD (4 pins): High impedance LPD (1 pin): High impedance JP0_5 High impedance JP0_5: Input Serial programming mode: High impedance Nexus I/F: DCURDY output LPD (4 pins): LPDCLKOUT output LPD (1 pin): High impedance JP0_6 High impedance JP0_6: Input Serial programming mode: High impedance Nexus I/F: EVTO output LPD (4 pins): High impedance LPD (1 pin): High impedance P8_6 Output*2,*4 Output (OPBT0.RESETOUTEN = 1)*2 High impedance (OPBT0.RESETOUTEN = 0)*2,*4 P0 to P3, P8 to P13, P18 to P22 (except P8_6, P10_1, P10_2, P10_6 and P10_8) High impedance High impedance P10_1 High impedance High impedance (FLMD0 = 0) High impedance (FLMD0 = 1, FLMD1 = 0) MODE0 input (FLMD0 = 1, FLMD1 = 1) P10_2 High impedance High impedance (FLMD0 = 0) High impedance (FLMD0 = 1, FLMD1 = 0) MODE1 input (FLMD0 = 1, FLMD1 = 1)

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 312 of 4535 Dec 26, 2018 Table 2B.7 Pin Functions During and After Reset Pins During Reset After Reset P10_6 High impedance High impedance (FLMD0 = 0) High impedance (FLMD0 = 1, FLMD1 = 0) High impedance (FLMD0 = 1, FLMD1 = 1, MODE0 = 0, MODE1 = 0) High impedance (FLMD0 = 1, FLMD1 = 1, MODE0 = 0, MODE1 = 1) High impedance (FLMD0 = 1, FLMD1 = 1, MODE0 = 1, MODE1 = 0) MODE2 input (FLMD0 = 1, FLMD1 = 1, MODE0 = 1, MODE1 = 1) P10_8 High impedance High impedance (FLMD0 = 0) FLMD1 input (FLMD0 = 1) FLMD0 Input Input RESET Input Input AP0, AP1 High impedance High impedance Note 1. When Nexus is enabled and no external device is connected, the level of the pin must always be fixed to low level. Note 2. RESETOUT is output. For details, see Section 2B.11, Port (Special I/O) Function Overview. Note 3. When the power is turned on or when RESET is low level, JP0_4 pin should be driven low level. Note 4. If OPBT0.RESETOUTEN = 0, P8_6 pin status has a possibility to become unstable (less than 15 μs) at the transition moment to reset status by internal reset factors. Note 5. When RESET is low level, on-chip pull-down resistor is connected to JP0_4.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 313 of 4535 Dec 26, 2018 2B.4 Port State in Standby Mode For the port state in standby mode, see Section 14.1.4, I/O Buffer Control. 2B.5 Recommended Connection of Unused Pins If the pins are not used, it is recommended to connect them as shown below. Table 2B.8 Recommended Connection of Unused Pins Pin Recommended Connection of Unused Pins A0VREF, A1VREF*1 [Excluding 100-Pin LQFP] Connected to EVCC or BVCC [100-Pin LQFP] Connected to EVCC A0VSS, A1VSS*1 [Excluding 100-Pin LQFP] Connected to EVSS or BVSS [100-Pin LQFP] Connected to EVSS RESET [Excluding 100-Pin LQFP] Connected to EVCC or BVCC via a resistor [100-Pin LQFP] Connected to EVCC via a resistor XT1 Connected to REGVCC or AWOVSS via a resistor*3 (bit 0 of IPIBC0 = 1) Connected to AWOVSS (bit 0 of IPIBC0 = 0) X1 Connected to AWOVSS via a resistor X2 Open IP0_0 Connected to REGVCC or AWOVSS via a resistor*3 (bit 0 of IPIBC0 = 1) Open (bit 0 of IPIBC0 = 0) JP0 (excluding JP0_4) P8 (excluding P8_6) P20 Input: Open (when the PIBCn_m and PMCn_m bits are 0) Connected to EVCC or EVSS via a resistor (when the PIBCn_m or PMCn_m bits are 1) Output: Open P8_6 Input: Open (when the PIBCn_m and PMCn_m bits are 0) Connected to EVSS via a resistor (when the PIBCn_m or PMCn_m bits are 1) Output: Open JP0_4 Connected to EVSS via a resistor P10_1, P10_2, P10_6, P10_8 Input: Open (when the PIBCn_m and PMCn_m bits are 0) Connected to EVSS via a resistor (when the PIBCn_m or PMCn_m bits are 1) Output: Open

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 314 of 4535 Dec 26, 2018 Table 2B.8 Recommended Connection of Unused Pins Pin Recommended Connection of Unused Pins P10 (excluding P10_1, P10_2, P10_6, P10_8) P11 P12 P13 P18 P19 P21 P22 [Excluding 100-Pin LQFP] Input: Open (when the PIBCn_m and PMCn_m bits are 0) Connected to BVCC or BVSS via a resistor (when the PIBCn_m or PMCn_m bits are 1) Output: Open [100-Pin LQFP] Input: Open (when the PIBCn_m and PMCn_m bits are 0) Connected to EVCC or EVSS via a resistor (when the PIBCn_m or PMCn_m bits are 1) Output: Open AP0 Input: Open (when the PIBCn_m bit is 0) Connected to A0VREF or A0VSS via a resistor (when the PIBCn_m bit is 1) Output: Open AP1 Input: Open (when the PIBCn_m bit is 0) Connected to A1VREF or A1VSS via a resistor (when the PIBCn_m bit is 1) Output: Open Nexus/LPD I/F (JP0) DCUTDI/LPDI/LPDIO (JP0_0): Connected to EVCC via a resistor DCUTDO/LPDO (JP0_1): Open DCUTCK/LPDCLK (JP0_2): Open DCUTMS (JP0_3): Connected to EVCC via a resistor DCUTRST (JP0_4): Connected to EVSS via a resistor*2 DCURDY /LPDCLKOUT (JP0_5):Open EVTO (JP0_6): Open*1 Note 1. Only available for 272-pin, 233-pin, 176-pin and 144-pin devices Note 2. For in case when a debugging interface is used, this pin should be connected to EVCC through resistor depending on the development tool made by a third party. Note 3. XT1 = IP0_0 (XT2) = REGVCC or AWOVSS should be set. XT1 is connected to IP0_0 (XT2) through an internal resistor. Therefore, it is necessary to maintain equal voltage level in order not to make a current path.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 315 of 4535 Dec 26, 2018 2B.6 Features of RH850/F1KM Port 2B.6.1 Port Group The RH850/F1KM provides the following port groups, indicated by the numbers in the table below. Table 2B.9 Port Groups in RH850/F1KM-S4 No. of Pins Port Group RH850/F1KM-S4 100 pins Number 7 Name P0, P8 to P11, JP0, AP0 144 pins Number 13 Name P0, P1, P8 to P12, P18, P20, JP0, AP0, AP1, IP0 176 pins Number 14 Name P0 to P2, P8 to P12, P18, P20, JP0, AP0, AP1, IP0 233 pins Number 17 Name P0 to P3, P8 to P13, P18 to P20, JP0, AP0, AP1, IP0 272 pins Number 19 Name P0 to P3, P8 to P13, P18 to P22, JP0, AP0, AP1, IP0 2B.6.2 Port Group Index n Throughout this section, the port groups are identified by using the index “n”. For example, the port mode control register of the Pn pin is PMCn (n = 0 to 3, 8 to 13, 18 to 22). 2B.6.3 Register Base Addresses Port and JTAG port base addresses are listed in the following table. Port and JTAG port register addresses are given as offsets from the base addresses. Table 2B.10 Register Base Addresses Base Address Name Base Address <PORTn_base> FFC1 0000H <JPORT0_base> FFC2 0000H 2B.6.4 Clock Supply The clock supply to ports is shown in the following table. Table 2B.11 Clock Supply Unit Name Unit Clock Name Supply Clock Name Port Register access clock CPUCLK_UL

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 316 of 4535 Dec 26, 2018 2B.7 Port Functions This product has various pins for input/output ports. The ports are organized in port groups. The RH850/F1KM also has several control registers to enable pins to be used as other than general-purpose input/output pins. For a description of the terms pin, port, and port group, see Section 2B.7.2, Terms 2B.7.1 Functional Overview

• All the port settings can be specified individually.
• The maximum number of bits (pins) in a port is 16.
• The output level of any pin can be set independently without affecting the other pins in the same port.
• Input buffers are enabled through registers settings.
• Pin level is read by dedicated port-pin-read register (PPR)
• All possible port functions are shown in the tables listed below. Table 2B.40, JTAG Port 0 (JP0), Table 2B.42, Port 0 (P0), Table 2B.44, Port 1 (P1), Table 2B.46, Port 2 (P2), Table 2B.48, Port 3 (P3), Table 2B.50, Port 8 (P8), Table 2B.52, Port 9 (P9), Table 2B.54, Port 10 (P10), Table 2B.56, Port 11 (P11), Table 2B.58, Port 12 (P12), Table 2B.60, Port 13 (P13), Table 2B.62, Port 18 (P18), Table 2B.64, Port 19 (P19), Table 2B.66, Port 20 (P20), Table 2B.68, Port 21 (P21), Table 2B.70, Port 22 (P22), Table 2B.72, Analog Port 0 (AP0), Table 2B.74, Analog Port 1 (AP1), Table 2B.76, Input Port 0 (IP0), and Section 2B.9.2, Pin Function Configuration. CAUTION Some input or output functions may be assigned to more than one port. Only activate a given function on a single pin. Do not activate a function on multiple pins at the same time. This also applies in cases where multiple peripheral functions are assigned to a single multiplexed function and only one of these functions is used. [Example] INTP0 is assigned to the following pins on this device. However, the INTP0 function should not be activated on more than one pin. After activating the function on one pin, do not activate it on another.
• JP0_0 (1st input alternative function)
• P0_1 (2nd, 3rd input alternative function)
• P10_0 (2nd input alternative function) In the above case, when the 1st input alternative function (INTP0) of JP0_0 is selected, using the 2nd input alternative function (CAN0RX/INTP0) of P0_1 only for the CAN signal is also prohibited.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 317 of 4535 Dec 26, 2018 2B.7.2 Terms The following terms are used in this section: Pin Denotes the physical pin. Every pin is denoted by a unique pin number. A pin can be used in several modes. Each pin is assigned a name that reflects its function, which is determined by the selected mode. Port group Denotes a group of pins. All the pins of a specific port group are controlled by the same port control register. Port mode and ports A pin in port mode works as a general-purpose input/output pin. It is then called “port”. The corresponding name is Pn_m. For example, P0_7 denotes port 7 of port group 0. It i s referenced as “port P0_7”. Alternative mode In alternative mode, a pin can be used for various non-general-purpose input/output functions, such as the input/output pin of on-chip peripherals. The corresponding pin name depends on the selected function. For example, pin INTP0 denotes the pin for one of the external interrupt inputs. Note that two different names can refer to the same physical pin, for example P0_0 and INTP0. The different names indicate the function of the pin at that time. 2B.7.2.1 JTAG Ports The JTAG port groups are used for connecting a debugger for on-chip debugging. JTAG port group registers and bit names are prefixed by a “J”. For example, JP0 denotes JTAG port group 0, and JPM0.JPM0_m denotes the JPM0_m port mode bit of the JPM0 port mode register. NOTE In this section, the descriptions about all ports and their registers other than PFCAEn and PIPCn apply to the JTAG port unless otherwise specified.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 318 of 4535 Dec 26, 2018 2B.7.3 Overview of Pin Functions Pins can operate in three modes.

• Port mode (PMCn.PMCn_m bit = 0) A pin in port mode operates as a general-purpose input/output pin. The I/O mode is selected by setting the PMn.PMn_m bit.
• Software I/O control alternative mode (PMCn.PMCn_m bit = 1, PIPCn.PIPCn_m bit = 0) In this mode, the pins operate as alternative functions. The I/O mode is selected by setting the PMn.PMn_m bit.
• Direct I/O control alternative mode (PMCn.PMCn_m bit = 1, PIPCn.PIPCn_m bit = 1) In this mode, the pins operate as alternative functions. Unlike the software I/O control alternative mode, however, the I/O mode is directly controlled by the alternative function. An overview of the register settings is given in the tables below. Table 2B.12 Pin Function Configuration (Overview) Bit Mode PMCn_m PMn_m PIPCn_m I/O Port mode 0 0 X O 1*1 I Software I/O control alternative mode 1 0 0 O 1 0 I Direct I/O control alternative mode X 1 Controlled by the alternative function Note 1. The input buffer must be enabled (PIBCn_m bit = 1).
• Software I/O control alternative mode (PIPCn.PIPCn_m bit = 0) − Output (PMn_m bit = 0): Alternative output mode 1 to Alternative output mode 7 − Input (PMn_m bit = 1): Alternative input mode 1 to Alternative input mode 7
• Direct I/O control alternative mode (PIPCn.PIPCn_m bit = 1) − The I/O mode for Alternative output mode 1 to Alternative output mode 7 and Alternative input mode 1 to Alternative input mode 7 is directly selected by the alternative function.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 319 of 4535 Dec 26, 2018 Table 2B.13 Alternative Mode Selection Overview (PMCn.PMCn_m Bit = 1) Register Mode PIPC*1 PM*1 PFCAE PFCE PFC I/O Alternative output mode 1 (ALT-OUT1) 0 0 0 0 0 O Alternative input mode 1 (ALT-IN1) 1 I Alternative output mode 2 (ALT-OUT2) 0 1 O Alternative input mode 2 (ALT-IN2) 1 I Alternative output mode 3 (ALT-OUT3) 0 1 0 O Alternative input mode 3 (ALT-IN3) 1 I Alternative output mode 4 (ALT-OUT4) 0 1 O Alternative input mode 4 (ALT-IN4) 1 I Alternative output mode 5 (ALT-OUT5) 0 1 0 0 O Alternative input mode 5 (ALT-IN5) 1 I Alternative output mode 6 (ALT-OUT6) 0 1 O Alternative input mode 6 (ALT-IN6) 1 I Alternative output mode 7 (ALT-OUT7) 0 1 0 O Alternative input mode 7 (ALT-IN7) 1 I Other than the above Setting prohibited Note 1. If PIPCn.PIPCn_m = 1, the I/O direction is directly controlled by the peripheral (alternative) function and PM is ignored. If a pin is in alternative mode (PMCn.PMCn_m bit = 1), one of up to seven alternative functions can be selected for that pin by using the PFCn, PFCEn, and PFCAEn registers.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 320 of 4535 Dec 26, 2018 2B.7.4 Pin Data Input/Output The registers used for data input/output are described below. The location that is read via the PPRn register differs depending on the pin mode. 2B.7.4.1 Output Data In the port mode (PMCn.PMCn_m bit = 0), the value of the Pn.Pn_m bit is output from the Pn_m pin. 2B.7.4.2 Input Data When the PPRn register is read, either the value of the Pn_m pin, the value of the Pn.Pn_m bit, or the value output by the alternative function is returned. Which value is returned depends on the pin mode and setting of several control bits. The different PPRn read modes are shown in the table below. Table 2B.14 PPRn_m Read Values PMC n_m PM n_m PIBC n_m PIPC n_m PODC n_m Mode PPRn_m Read Value 0 1 0 X X Port input, input buffer disabled Pn.Pn_m bit 0 X 0 Port push-pull output Pn.Pn_m bit*1 1 1 X 0 X Software I/O control alternative input Pn_m pin 0 0 Software I/O control alternative push- pull output Output signal from the alternative function*1 X 1 0 Direct I/O control alternative input or push-pull output I/O port in alternative mode:

• Input: Pn_m pin
• Output: Output signal from the alternative function*1

Note 1. When PBDCn_m = 1, the level of the Pn_m pin is returned by the PPRn_m bit. The control registers in the above table have the following effects:

• PMCn.PMCn_m bit This bit selects port mode (PMCn_m = 0) or alternative mode (PMCn_m = 1).
• PMn.PMn_m bit This bit selects input (PMn_m = 1) or output (PMn_m = 0) when the port mode (PMCn_m = 0) and software I/O control alternative mode (PMCn_m = 1, PIPCn_m = 0) have been selected.
• PIBCn.PIBCn_m bit This bit disables (PIBCn_m = 0) or enables (PIBCn_m = 1) the input buffer in input port mode (PMCn_m = 0 and PMn_m = 1). If the input buffer is disabled, PPRn_m reads the Pn.Pn_m bit; otherwise the Pn_m pin level is returned.
• PIPCn.PIPCn_m bit This bit selects software I/O control alternative mode or direct I/O control alternative mode.
• PODCn.PODCn_m bit This bit selects push-pull output (PODCn_m = 0) or open-drain output (PODCn_m = 1).

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 321 of 4535 Dec 26, 2018

• PBDCn.PBDCn_m bit In output mode, when this bit is set to 1, the pin enters the bidirectional mode. In bidirectional mode, the level of the signal on a Pn_m pin can be read from PPRn.PPRn_m. CAUTION When using Pn_m as an alternative output function (PMCn.PMCn_m bit = 1, PMn.PMn_m bit = 0), the level of the Pn_m pin can be read at the PPRn.PPRn_m bit by enabling bidirectional mode (PBDCn.PBDCn_m bit = 1). Note, however, that the level of the Pn_m pin will be input to the alternative function that the Pn_m pin is being used as. 2B.7.4.3 Writing to the Pn Register The data to be output via port Pn_m in port mode (PMCn.PMCn_m bit = 0) is held in port register Pn. Pn data can be overwritten in two ways:
• By writing data directly to the Pn register. In this case, new data can be written directly to the Pn register.
• By performing an indirect bitwise operation (a “set”, “reset”, or “not” operation) on the Pn register. An indirect bitwise operation (“set”, “reset”, or “not”) can be performed on the Pn register by using the following two registers: − Port Set/Reset register PSRn If the PSRn.PSRn (m + 16) bit = 1, the value of the Pn.Pn_m bit is determined by the value of the PSRn.PSRn_m bit. In other words, the Pn_m bit can be set or reset without writing directly to the Pn register. − Port NOT register PNOTn By setting PNOTn.PNOTn_m bit to 1, the Pn.Pn_m bit can be inverted without writing directly to the Pn register. An indirect bitwise operation on the Pn register (“set”, “reset”, or “not”) has no effect on the bits that do not need to be updated, allowing you to overwrite only the bit or bits that need to be overwritten.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 322 of 4535 Dec 26, 2018 2B.8 Schematic View of Port Control The following figure is a schematic view of the port control functions. Peripheral bus (PBUS) PDSC PU PD PBDC PM PIBC PMC PIPC PODC PPR P PSR PNOT PPCMD PFC PFCE PFCAE PMSR PMCSR PPROTS PIS Internal IPs 1 2 3 ... 1 2 3 1 2 3 1 2 3 Internal IP data output Internal IP data output control Internal IP data input control Internal IP data input Output buffer control Pull-down control Pull-up control Input buffer control Input buffer control P N Output data control Input data control Alternative function selection PISA Open drain control Figure 2B.6 Schematic View of Port Control CAUTION Use documented alternative functions only. The behavior and performance are not guaranteed when undocumented alternative functions are selected.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 323 of 4535 Dec 26, 2018 2B.9 Port Group Configuration Registers This section starts with an overview of all configuration registers and then describes all registers in detail. The configuration registers are grouped as follows:

• Section 2B.9.2, Pin Function Configuration
• Section 2B.9.3, Pin Data Input/Output
• Section 2B.9.4, Configuration of Electrical Characteristics 2B.9.1 Overview The following registers are used for setting the individual pins of the port groups. For details on <PORTn_base> and <JPORT0_base>, see Section 2B.6.3, Register Base Addresses. Table 2B.15 Port Group Configuration Registers Module Name Register Name Symbol Address Pin function configuration PORT Port mode control register PMCn <PORTn_base> + 0400H + n × 4 JTAG JPMC0 <JPORT0_base> + 0040H PORT Port mode control set/reset register PMCSRn <PORTn_base> + 0900H + n × 4 JTAG JPMCSR0 <JPORT0_base> + 0090H PORT Port IP control register PIPCn <PORTn_base> + 4200H + n × 4 PORT Port mode register PMn <PORTn_base> + 0300H + n × 4 APMn <PORTn_base> + 03C8H + n × 4 JTAG JPM0 <JPORT0_base> + 0030H PORT Port mode set/reset register PMSRn <PORTn_base> + 0800H + n × 4 APMSRn <PORTn_base> + 08C8H + n × 4 JTAG JPMSR0 <JPORT0_base> + 0080H PORT Port input buffer control register PIBCn <PORTn_base> + 4000H + n × 4 APIBCn <PORTn_base> + 40C8H + n × 4 JTAG JPIBC0 <JPORT0_base> + 0400H PORT IPIBC0 <PORTn_base> + 40F0H PORT Port function control register PFCn <PORTn_base> + 0500H + n × 4 JTAG JPFC0 <JPORT0_base> + 0050H PORT Port function control expansion register PFCEn <PORTn_base> + 0600H + n × 4 JTAG JPFCE0 <JPORT0_base> + 0060H PORT Port function control additional expansion register PFCAEn <PORTn_base> + 0A00H + n × 4 Pin data input/output PORT Port bidirection control register PBDCn <PORTn_base> + 4100H + n × 4 APBDCn <PORTn_base> + 41C8H + n × 4 JTAG JPBDC0 <JPORT0_base> + 0410H PORT Port pin read register PPRn <PORTn_base> + 0200H + n × 4 APPRn <PORTn_base> + 02C8H + n × 4 JTAG JPPR0 <JPORT0_base> + 0020H PORT IPPR0 <PORTn_base> + 02F0H

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 324 of 4535 Dec 26, 2018 Table 2B.15 Port Group Configuration Registers Module Name Register Name Symbol Address Pin data input/output PORT Port register Pn <PORTn_base> + 0000H + n × 4 APn <PORTn_base> + 00C8H + n × 4 JTAG JP0 <JPORT0_base> + 0000H PORT Port NOT register PNOTn <PORTn_base> + 0700H + n × 4 APNOTn <PORTn_base> + 07C8H + n × 4 JTAG JPNOT0 <JPORT0_base> + 0070H PORT Port set/reset register PSRn <PORTn_base> + 0100H + n × 4 APSRn <PORTn_base> + 01C8H + n × 4 JTAG JPSR0 <JPORT0_base> + 0010H Configuration of electrical characteristics PORT Pull-up option register PUn <PORTn_base> + 4300H + n × 4 JTAG JPU0 <JPORT0_base> + 0430H PORT Pull-down option register PDn <PORTn_base> + 4400H + n × 4 JTAG JPD0 <JPORT0_base> + 0440H PORT Port drive strength control register PDSCn <PORTn_base> + 4600H + n × 4 JTAG JPDSC0 <JPORT0_base> + 0460H PORT Port open drain control register PODCn <PORTn_base> + 4500H + n × 4 JTAG JPODC0 <JPORT0_base> + 0450H PORT Port input buffer selection register PISn <PORTn_base> + 4700H + n × 4 JTAG JPIS0 <JPORT0_base> + 0470H PORT Port input buffer selection advanced register PISAn <PORTn_base> + 4A00H + n × 4 JTAG JPISA0 <JPORT0_base> + 04A0H Port register protection PORT Port protection command register PPCMDn <PORTn_base> + 4C00H + n × 4 JTAG JPPCMD0 <JPORT0_base> + 04C0H PORT Port protection status register PPROTSn <PORTn_base> + 4B00H + n × 4 JTAG JPPROTS0 <JPORT0_base> + 04B0H

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 325 of 4535 Dec 26, 2018 Index n In Table 2B.15, Port Group Configuration Registers, the index “n” in register symbols denotes the actual indices of the individual port groups. For example, PMCn generically indicates a port mode control register for port group n (Pn). The values for n differ according to the number of pins on the device in the way shown in Table 2B.16, Number of Pins on the Device, Name of Port Groups, and Values for “n” in Register Symbols . Table 2B.16 Number of Pins on the Device, Name of Port Groups, and Values for “n” in Register Symbols Number of Pins on the Device Port Groups Values for “n” 100 pins P0, P8, P9, P10, P11 0, 8, 9, 10, 11 AP0 0 144 pins P0, P1, P8, P9, P10, P11, P12, P18, P20 0, 1, 8, 9, 10, 11, 12, 18, 20 AP0, AP1 0, 1 176 pins P0, P1, P2, P8, P9, P10, P11, P12, P18, P20 0, 1, 2, 8, 9, 10, 11, 12, 18, 20 AP0, AP1 0, 1 233 pins P0, P1, P2, P3, P8, P9, P10, P11, P12, P13, P18, P19, P20 AP0, AP1 0, 1 272 pins P0, P1, P2, P3, P8, P9, P10, P11, P12, P13, P18, P19, P20, P21, P22 AP0, AP1 0, 1 JTAG port registers JTAG port registers are not explicitly described in the following register descriptions. All descriptions (except for those of the PFCAEn register and PIPCn register) apply to JTAG port registers. Note, however, that the JTAG port register base address differs from that of regular ports. Value after reset The values after reset depend on the ports. For the values after reset, see the register descriptions in the following pages.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 326 of 4535 Dec 26, 2018 2B.9.2 Pin Function Configuration 2B.9.2.1 PMCn / JPMC0 — Port Mode Control Register This register specifies whether the individual pins of port group n are in port mode or in alternative mode. Access: PMCn: This register can be read or written in 16-bit units. JPMC0: This register can be read or written in 8-bit units. Address: PMCn: <PORTn_base> + 0400H + n × 4 (n = 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 18, 20) JPMC0: <JPORT0_base> + 0040H*1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PMC n_15 PMC n_14 PMC n_13 PMC n_12 PMC n_11 PMC n_10 PMC n_9 PMC n_8 PMC n_7 PMC n_6 PMC n_5 PMC n_4 PMC n_3 PMC n_2 PMC n_1 PMC n_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2B.10, Port (General I/O) Function Overview: Table 2B.41, Control Registers (JP0), Table 2B.43, Control Registers (P0), Table 2B.45, Control Registers (P1), Table 2B.47, Control Registers (P2), Table 2B.49, Control Registers (P3), Table 2B.51, Control Registers (P8), Table 2B.53, Control Registers (P9), Table 2B.55, Control Registers (P10), Table 2B.57, Control Registers (P11), Table 2B.59, Control Registers (P12), Table 2B.61, Control Registers (P13), Table 2B.63, Control Registers (P18), and Table 2B.67, Control Registers (P20). Table 2B.17 PMCn Register Contents Bit Position Bit Name Function 15 to 0 PMCn_[15:0] Specifies the operation mode of the corresponding pin. 0: Port mode 1: Alternative mode CAUTIONS 1. I/O is not controlled by only setting alternative mode (PMCn.PMCn_m bit = 1). If the alternative function requires direct I/O control, also set the PIPCn.PIPCn_m bit to 1. 2. If a port is to be used as an input pin in alternative mode, the signals from some pins will pass through a noise filter. These pins may require the setting of the FCLA0CTLm_<name>, DNFA<name>CTL and the DNFA<name>EN register. For details, see Section 2B.12, Noise Filter & Edge/Level Detector, and Section 2B.13, Description of Port Noise Filter & Edge/Level Detection. NOTE The control bits of the JTAG port mode control register (JPMC0) are JPMC0_[7:0].

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 327 of 4535 Dec 26, 2018 2B.9.2.2 PMCSRn / JPMCSR0 — Port Mode Control Set/Reset Register This register provides an alternative method to write data to the PMCn register. The upper 16 bits of PMCSRn act as a mask which specifies whether or not the value of PMCn.PMCn_m is set by the corresponding bit in the lower 16 bits of PMCSRn. Access: PMCSRn: This register can be read or written in 32-bit units. Bits 31 to 16 are always read as 0000H. Reading bits 15 to 0 returns the value of register PMCn. JPMCSR0: This register can be read or written in 32-bit units. Bits 31 to 8 are always read as 000000H. Reading bits 7 to 0 returns the value of register JPMC0. Address: PMCSRn: <PORTn_base> + 0900H + n × 4 (n = 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 18, 20) JPMCSR0: <JPORT0_base> + 0090H*1 Value after reset: 0000 0000H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PMC SRn_31 PMC SRn_30 PMC SRn_29 PMC SRn_28 PMC SRn_27 PMC SRn_26 PMC SRn_25 PMC SRn_24 PMC SRn_23 PMC SRn_22 PMC SRn_21 PMC SRn_20 PMC SRn_19 PMC SRn_18 PMC SRn_17 PMC SRn_16 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PMC SRn_15 PMC SRn_14 PMC SRn_13 PMC SRn_12 PMC SRn_11 PMC SRn_10 PMC SRn_9 PMC SRn_8 PMC SRn_7 PMC SRn_6 PMC SRn_5 PMC SRn_4 PMC SRn_3 PMC SRn_2 PMC SRn_1 PMC SRn_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2B.10, Port (General I/O) Function Overview: Table 2B.41, Control Registers (JP0), Table 2B.43, Control Registers (P0), Table 2B.45, Control Registers (P1), Table 2B.47, Control Registers (P2), Table 2B.49, Control Registers (P3), Table 2B.51, Control Registers (P8), Table 2B.53, Control Registers (P9), Table 2B.55, Control Registers (P10), Table 2B.57, Control Registers (P11), Table 2B.59, Control Registers (P12), Table 2B.61, Control Registers (P13), Table 2B.63, Control Registers (P18), and Table 2B.67, Control Registers (P20). Table 2B.18 PMCSRn Register Contents Bit Position Bit Name Function 31 to 16 PMCSRn_[31:16] Enable bits that specify whether the value of the corresponding lower bit PMCSRn_m (PMCSRn_[15:0]) is written to PMCn_m. 0: PMCn_m is not affected by PMCSRn_m. 1: PMCn_m is PMCSRn_m. Example: If PMCSRn.PMCSRn_31 = 1, the value of bit PMCSRn.PMCSRn_15 is written to bit PMCn.PMCn_15. 15 to 0 PMCSRn_[15:0] Data bits that specify the value of PMCn_m if PMCSRn_m of the corresponding upper bit (PMCSRn_[31:16]) is 1. 0: PMCn_m is 0. 1: PMCn_m is 1. NOTE The control bits of the JTAG port mode control set/reset register (JPMCSR0) are JPMCSR0_[31:0].

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 328 of 4535 Dec 26, 2018 2B.9.2.3 PIPCn — Port IP Control Register This register specifies whether the I/O direction of the Pn_m pin is controlled by the port mode register PMn.PMn_m or by an alternative function. If the Pn_m pin is operated in alternative mode (PMCn.PMCn_m = 1) and the alternative function requires direct control of the I/O direction, then PIPCn.PIPCn_m must be set to 1 as well. This transfers I/O control to the alternative function and overrules the PMn.PMn_m setting. Regarding the alternative functions for which the PIPC register must be set, see Section 2B.11, Port (Special I/O) Function Overview. Access: This register can be read or written in 16-bit units. Address: PIPCn: <PORTn_base> + 4200H + n × 4 (n = 0, 10, 11, 12, 20)*1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PIPC n_15 PIPC n_14 PIPC n_13 PIPC n_12 PIPC n_11 PIPC n_10 PIPC n_9 PIPC n_8 PIPC n_7 PIPC n_6 PIPC n_5 PIPC n_4 PIPC n_3 PIPC n_2 PIPC n_1 PIPC n_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2B.10, Port (General I/O) Function Overview: Table 2B.43, Control Registers (P0), Table 2B.55, Control Registers (P10), Table 2B.57, Control Registers (P11), and Table 2B.59, Control Registers (P12). Table 2B.19 PIPCn Register Contents Bit Position Bit Name Function 15 to 0 PIPCn_[15:0] Specifies the I/O mode. 0: I/O mode is selected by PMn.PMn_m (software I/O control). 1: I/O mode is selected by the peripheral function (direct I/O control).

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 329 of 4535 Dec 26, 2018 2B.9.2.4 PMn / APMn / JPM0 — Port Mode Register This register specifies whether the individual pins of the port group n are in input mode or in output mode. Access: PMn, APMn: These registers can be read or written in 16-bit units. JPM0: This register can be read or written in 8-bit units. Address: PMn: <PORTn_base> + 0300H + n × 4 (n = 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 18, 19, 20, 21, 22) APMn: <PORTn_base> + 03C8H + n × 4 (n = 0, 1) JPM0: <JPORT0_base> + 0030H*1 Value after reset: FFFFH*2 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PMn_15 PMn_14 PMn_13 PMn_12 PMn_11 PMn_10 PMn_9 PMn_8 PMn_7 PMn_6 PMn_5 PMn_4 PMn_3 PMn_2 PMn_1 PMn_0 Value after reset 1 1 1 1 1 1 1 1 1 1*3 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2B.10, Port (General I/O) Function Overview: Table 2B.41, Control Registers (JP0), Table 2B.43, Control Registers (P0), Table 2B.45, Control Registers (P1), Table 2B.47, Control Registers (P2), Table 2B.49, Control Registers (P3), Table 2B.51, Control Registers (P8), Table 2B.53, Control Registers (P9), Table 2B.55, Control Registers (P10), Table 2B.57, Control Registers (P11), Table 2B.59, Control Registers (P12), Table 2B.61, Control Registers (P13), Table 2B.63, Control Registers (P18), Table 2B.65, Control Registers (P19), Table 2B.67, Control Registers (P20), Table 2B.69, Control Registers (P21), Table 2B.71, Control Registers (P22), Table 2B.73, Control Registers (AP0), and Table 2B.75, Control Registers (AP1). Note 2. The PM8 register is as follows. When the OPBT0.RESETOUTEN = 1, the PM8 register is FFBFH. When the OPBT0.RESETOUTEN = 0, the PM8 register is FFFFH. Note 3. The PM8_6 bit is as follows. When the OPBT0.RESETOUTEN = 1, the PM8_6 bit is 0. When the OPBT0.RESETOUTEN = 0, the PM8_6 bit is 1. Table 2B.20 PMn Register Contents Bit Position Bit Name Function 15 to 0 PMn_[15:0] Specifies input/output mode of the corresponding pin. 0: Output mode (output enabled) 1: Input mode (output disabled) NOTES 1. To use a port in input port mode (PMCn.PMCn_m = 0 and PMn.PMn_m = 1), the input buffer must be enabled (PIBCn.PIBCn_m = 1). 2. By default, PMn.PMn_m specifies the I/O direction in port mode (PMCn.PMCn_m = 0) and alternative mode (PMCn.PMCn_m = 1), since PIPCn.PIPCn_m = 0 after reset. 3. The control bits of the analog port register (APMn) are APMn_[15:0]. 4. The control bits of the JTAG port mode register (JPM0) are JPM0_[7:0].

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 330 of 4535 Dec 26, 2018 2B.9.2.5 PMSRn / APMSRn / JPMSR0 — Port Mode Set/Reset Register This register provides an alternative method to write data to the PMn register. The upper 16 bits of PMSRn act as a mask which specifies whether or not the value PMn.PMn_m is set by the corresponding bit in the lower 16 bits of PMSRn. Access: PMSRn, APMSRn: These registers can be read or written in 32- bit units. Bits 31 to 16 are always read as 0000H. Reading bits 15 to 0 returns the value of registers PMn and APMn. JPMSR0: This register can be read or written in 32-bit units. Bits 31 to 16 are always read as 0000H. Bits 15 to 8 are read as FFH. Reading bits 7 to 0 returns the value of register JPM0. Address: PMSRn: <PORTn_base> + 0800H + n × 4 (n = 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 18, 19, 20, 21, 22) APMSRn: <PORTn_base> + 08C8H + n × 4 (n = 0, 1) JPMSR0: <JPORT0_base> + 0080H*1 Value after reset: 0000 FFFFH*2 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PMSR n_31 PMSR n_30 PMSR n_29 PMSR n_28 PMSR n_27 PMSR n_26 PMSR n_25 PMSR n_24 PMSR n_23 PMSR n_22 PMSR n_21 PMSR n_20 PMSR n_19 PMSR n_18 PMSR n_17 PMSR n_16 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PMSR n_15 PMSR n_14 PMSR n_13 PMSR n_12 PMSR n_11 PMSR n_10 PMSR n_9 PMSR n_8 PMSR n_7 PMSR n_6 PMSR n_5 PMSR n_4 PMSR n_3 PMSR n_2 PMSR n_1 PMSR n_0 Value after reset 1 1 1 1 1 1 1 1 1 1*3 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2B.10, Port (General I/O) Function Overview: Table 2B.41, Control Registers (JP0), Table 2B.43, Control Registers (P0), Table 2B.45, Control Registers (P1), Table 2B.47, Control Registers (P2), Table 2B.49, Control Registers (P3), Table 2B.51, Control Registers (P8), Table 2B.53, Control Registers (P9), Table 2B.55, Control Registers (P10), Table 2B.57, Control Registers (P11), Table 2B.59, Control Registers (P12), Table 2B.61, Control Registers (P13), Table 2B.63, Control Registers (P18), Table 2B.65, Control Registers (P19), Table 2B.67, Control Registers (P20), Table 2B.69, Control Registers (P21), Table 2B.71, Control Registers (P22), Table 2B.73, Control Registers (AP0), and Table 2B.75, Control Registers (AP1). Note 2. The PMSR8 register is as follows. When the OPBT0.RESETOUTEN = 1, the PMSR8 register is 0000 FFBFH. When the OPBT0.RESETOUTEN = 0, the PMSR8 register is 0000 FFFFH. Note 3. The PMSR8_6 bit is as follows. When the OPBT0.RESETOUTEN = 1, the PMSR8_6 bit is 0. When the OPBT0.RESETOUTEN = 0, the PMSR8_6 bit is 1. Table 2B.21 PMSRn Register Contents Bit Position Bit Name Function 31 to 16 PMSRn_[31:16] Enable bits that specify whether the value of the corresponding lower bit PMSRn_m (PMSRn_[15:0]) is written to PMn_m. 0: PMn_m is not affected by PMSRn_m. 1: PMn_m is PMSRn_m. Example: If PMSRn.PMSRn_31 = 1, the value of bit PMSRn.PMSRn_15 is written to bit PMn.PMn_15. 15 to 0 PMSRn_[15:0] Data bits that specify the value of PMn_m if PMSRn_m of the corresponding upper bit (PMSRn_[31:16]) is 1. 0: PMn_m is 0. 1: PMn_m is 1.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 331 of 4535 Dec 26, 2018 NOTES 1. The control bits of the JTAG port mode set/reset register (JPMSR0) are JPMSR0_[31:0]. 2. The control bits of the analog port mode set/reset register (APMSRn) are APMSRn_[31:0]. 2B.9.2.6 PIBCn / APIBCn / JPIBC0 / IPIBC0 — Port Input Buffer Control Register In input port mode (PMCn.PMCn_m = 0 and PMn.PMn_m = 1), this register enables the port pin’s input buffer. Access: PIBCn, APIBCn, IPIBC0: These registers can be read or written in 16- bit units. JPIBC0: This register can be read or written in 8-bit units. Address: PIBCn: <PORTn_base> + 4000H + n × 4 (n = 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 18, 19, 20, 21, 22) APIBCn: <PORTn_base> + 40C8H+ n × 4 (n = 0, 1) JPIBC0: <JPORT0_base> + 0400H IPIBC0: <PORTn_base> + 40F0H*1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PIBC n_15 PIBC n_14 PIBC n_13 PIBC n_12 PIBC n_11 PIBC n_10 PIBC n_9 PIBC n_8 PIBC n_7 PIBC n_6 PIBC n_5 PIBC n_4 PIBC n_3 PIBC n_2 PIBC n_1 PIBC n_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2B.10, Port (General I/O) Function Overview: Table 2B.41, Control Registers (JP0), Table 2B.43, Control Registers (P0), Table 2B.45, Control Registers (P1), Table 2B.47, Control Registers (P2), Table 2B.49, Control Registers (P3), Table 2B.51, Control Registers (P8), Table 2B.53, Control Registers (P9), Table 2B.55, Control Registers (P10), Table 2B.57, Control Registers (P11), Table 2B.59, Control Registers (P12), Table 2B.61, Control Registers (P13), Table 2B.63, Control Registers (P18), Table 2B.65, Control Registers (P19), Table 2B.67, Control Registers (P20), Table 2B.69, Control Registers (P21), Table 2B.71, Control Registers (P22), Table 2B.73, Control Registers (AP0), Table 2B.75, Control Registers (AP1) and Table 2B.77, Control Registers (IP0). Table 2B.22 PIBCn Register Contents Bit Position Bit Name Function 15 to 0 PIBCn_[15:0] Enables/disables the input buffer. 0: Input buffer disabled 1: Input buffer enabled NOTES 1. When the input buffer is disabled, through current does not flow even when the pin level is Hi-Z. Thus the pin does not need to be fixed to a high or low level externally. 2. The control bits of the JTAG port input buffer control register (JPIBC0) are JPIBC0_[7:0]. CAUTION Settings in this register are overruled in bidirectional mode (PBDCn.PBDCn_m = 1).

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 332 of 4535 Dec 26, 2018 2B.9.2.7 PFCn / JPFC0 — Port Function Control Register This register, together with register PFCEn and PFCAEn, specifies an alternative function of the pins. Some alternative functions directly control the I/O of the Pn_m pin. For such alternative functions, PIPCn.PIPCn_m must be set to 1 and the I/O is selected by the peripheral function. For other alternative functions, input/output must be specified by PMn.PMn_m. Access: PFCn: This register can be read or written in 16-bit units. JPFC0: This register can be read or written in 8-bit units. Address: PFCn: <PORTn_base> + 0500H + n × 4 (n = 0, 1, 2, 8, 9, 10, 11, 12, 13, 18, 20) JPFC0: <JPORT0_base> + 0050H*1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PFC n_15 PFC n_14 PFC n_13 PFC n_12 PFC n_11 PFC n_10 PFC n_9 PFC n_8 PFC n_7 PFC n_6 PFC n_5 PFC n_4 PFC n_3 PFC n_2 PFC n_1 PFC n_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2B.10, Port (General I/O) Function Overview: Table 2B.41, Control Registers (JP0), Table 2B.43, Control Registers (P0), Table 2B.45, Control Registers (P1), Table 2B.47, Control Registers (P2), Table 2B.51, Control Registers (P8), Table 2B.53, Control Registers (P9), Table 2B.55, Control Registers (P10), Table 2B.57, Control Registers (P11), Table 2B.59, Control Registers (P12), Table 2B.61, Control Registers (P13), Table 2B.63, Control Registers (P18), and Table 2B.67, Control Registers (P20). Table 2B.23 PFCn Register Contents Bit Position Bit Name Function 15 to 0 PFCn_[15:0] Specifies the alternative function of the pin. For details, see Table 2B.26, Setting Alternative Functions. NOTE The control bits of the JTAG port function control register (JPFC0) are JPFC0_[7:0].

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 333 of 4535 Dec 26, 2018 2B.9.2.8 PFCEn / JPFCE0 — Port Function Control Expansion Register This register, together with register PFCn and PFCAEn, specifies an alternative function of the pins. Some alternative functions directly control the I/O of the Pn_m pin. For such alternative functions, PIPCn.PIPCn_m must be set to 1 and the I/O is specified by the peripheral function. For other alternative functions, input/output must be specified by PMn.PMn_m. Access: PFCEn: This register can be read or written in 16-bit units. JPFCE0: This register can be read or written in 8-bit units. Address: PFCEn: <PORTn_base> + 0600H + n × 4 (n = 0, 1, 2, 8, 9, 10, 11, 12, 18, 20) JPFCE0: <JPORT0_base> + 0060H*1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PFCE n_15 PFCE n_14 PFCE n_13 PFCE n_12 PFCE n_11 PFCE n_10 PFCEn PFCEn PFCEn PFCEn PFCEn PFCEn PFCEn PFCEn PFCEn PFCEn Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2B.10, Port (General I/O) Function Overview: Table 2B.41, Control Registers (JP0), Table 2B.43, Control Registers (P0), Table 2B.45, Control Registers (P1), Table 2B.47, Control Registers (P2), Table 2B.51, Control Registers (P8), Table 2B.53, Control Registers (P9), Table 2B.55, Control Registers (P10), Table 2B.57, Control Registers (P11), Table 2B.59, Control Registers (P12), Table 2B.63, Control Registers (P18), and Table 2B.67, Control Registers (P20). Table 2B.24 PFCEn Register Contents Bit Position Bit Name Function 15 to 0 PFCEn_[15:0] Specifies the alternative function of the pin. For details, see Table 2B.26, Setting Alternative Functions.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 334 of 4535 Dec 26, 2018 2B.9.2.9 PFCAEn — Port Function Control Additional Expansion Register This register selects the alternative peripheral functions together with PFCEn, PFCn registers. Some alternative functions directly control the I/O of the Pn_m pin. For such alternative functions, PIPCn.PIPCn_m must be set to 1 and the I/O is specified by the peripheral function. For other alternative functions, input/output must be specified by PMn.PMn_m. Access: PFCAEn: This register can be read or written in 16-bit units. Address: PFCAEn: <PORTn_base> + 0A00H + n × 4 (n = 0, 1, 2, 8, 9, 10, 11, 12, 20)*1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PFCAE n_15 PFCAE n_14 PFCAE n_13 PFCAE n_12 PFCAE n_11 PFCAE n_10 PFCAE n_9 PFCAE n_8 PFCAE n_7 PFCAE n_6 PFCAE n_5 PFCAE n_4 PFCAE n_3 PFCAE n_2 PFCAE n_1 PFCAE n_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2B.10, Port (General I/O) Function Overview: Table 2B.43, Control Registers (P0), Table 2B.45, Control Registers (P1), Table 2B.47, Control Registers (P2), Table 2B.51, Control Registers (P8), Table 2B.53, Control Registers (P9), Table 2B.55, Control Registers (P10), Table 2B.57, Control Registers (P11), Table 2B.59, Control Registers (P12), and Table 2B.67, Control Registers (P20). Table 2B.25 PFCAEn Register Contents Bit Position Bit Name Function 15 to 0 PFCAEn_[15:0] Specifies the alternative function of the pin. For details, see Table 2B.26, Setting Alternative Functions. Table 2B.26 Setting Alternative Functions PFCAEn_m PFCEn_m PFCn_m PMn_m Function 0 0 0 1 Alternative input mode 1 1 1 Alternative input mode 2 1 0 1 Alternative input mode 3 1 1 Alternative input mode 4 1 0 0 1 Alternative input mode 5 1 1 Alternative input mode 6 1 0 1 Alternative input mode 7

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 335 of 4535 Dec 26, 2018 CAUTION

• After selecting the alternative function by the PFCn_m, PFCEn_m, or PFCAEn_m bit, set the PMCn_m bit to “1”.
• With this product, the I/O of some functions is assigned to two or more pins, but a specific pin function can only be set to one pin at a time. Setting the same pin function to two or more pins at the same time is prohibited. For example, if the a/b/c pin is used as b, the b/d/e pin cannot be used as b. In this case, the b/d/e pin must be configured as a pin function other than b. NOTE Control Registers.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 336 of 4535 Dec 26, 2018 2B.9.3 Pin Data Input/Output 2B.9.3.1 PBDCn / APBDCn / JPBDC0 — Port Bidirection Control Register This register enables the input buffer in output mode and sets the port to bidirectional mode. In bidirectional mode, the level of the signal on a Pn_m pin can be read from PPRn.PPRn_m. Access: PBDCn, APBDCn: These registers can be read or written in 16- bit units. JPBDC0: This register can be read or written in 8-bit units. Address: PBDCn: <PORTn_base> + 4100H + n × 4 (n = 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 18, 19, 20, 21, 22) APBDCn: <PORTn_base> + 41C8H + n × 4 (n = 0, 1) JPBDC0: <JPORT0_base> + 0410H*1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PBDC n_15 PBDC n_14 PBDC n_13 PBDC n_12 PBDC n_11 PBDC n_10 PBDC n_9 PBDC n_8 PBDC n_7 PBDC n_6 PBDC n_5 PBDC n_4 PBDC n_3 PBDC n_2 PBDC n_1 PBDC n_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2B.10, Port (General I/O) Function Overview: Table 2B.41, Control Registers (JP0), Table 2B.43, Control Registers (P0), Table 2B.45, Control Registers (P1), Table 2B.47, Control Registers (P2), Table 2B.49, Control Registers (P3), Table 2B.51, Control Registers (P8), Table 2B.53, Control Registers (P9), Table 2B.55, Control Registers (P10), Table 2B.57, Control Registers (P11), Table 2B.59, Control Registers (P12), Table 2B.61, Control Registers (P13), Table 2B.63, Control Registers (P18), Table 2B.65, Control Registers (P19), Table 2B.67, Control Registers (P20), Table 2B.69, Control Registers (P21), Table 2B.71, Control Registers (P22), Table 2B.73, Control Registers (AP0), and Table 2B.75, Control Registers (AP1). Table 2B.27 PBDCn Register Contents Bit Position Bit Name Function 15 to 0 PBDCn[15:0] Enables/disables bidirectional mode of the corresponding pin. 0: Bidirectional mode disabled 1: Bidirectional mode enabled CAUTION

• When the Pn_m port is used for the alternative output function (PMCn.PMCn_m = 1, PMn.PMn_m = 0), the level of the Pn_m pin can be read from PPRn.PPRn_m by enabling the bidirectional mode (PBDCn.PBDCn_m = 1).
• However, output of that alternative output function is input to the alternative input function of the same pin (the alternative input function set by PFCn.PFCn_m, PFCEn.PFCEn_m, and PFCAEn.PFCAEn_m). If the alternative input function in question is being used by another pin, the alternative input function is not guaranteed. NOTE The control bits of the JTAG port bidirection control register (JPBDC0) are JPBDC0_[7:0].

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 337 of 4535 Dec 26, 2018 2B.9.3.2 PPRn / APPRn / JPPR0 / IPPR0 — Port Pin Read Register This register reflects the actual level of the Pn_m pin, whether it is the value of the Pn.Pn_m bit o r the level of an alternative output function. Access: PPRn, APPRn, IPPR0: These registers are read-only registers that can be read in 16-bit units. JPPR0: This register is a read-only register that can be read in 8-bit units. Address: PPRn: <PORTn_base> + 0200H + n × 4 (n = 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 18, 19, 20, 21, 22) APPRn: <PORTn_base> + 02C8H + n × 4 (n = 0, 1) JPPR0: <JPORT0_base> + 0020H IPPR0: <PORTn_base> + 02F0H*1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PPR n_15 PPR n_14 PPR n_13 PPR n_12 PPR n_11 PPR n_10 PPR n_9 PPR n_8 PPR n_7 PPR n_6 PPR n_5 PPR n_4 PPR n_3 PPR n_2 PPR n_1 PPR n_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R R R R R R R R R R R R R R R R Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2B.10, Port (General I/O) Function Overview: Table 2B.41, Control Registers (JP0), Table 2B.43, Control Registers (P0), Table 2B.45, Control Registers (P1), Table 2B.47, Control Registers (P2), Table 2B.49, Control Registers (P3), Table 2B.51, Control Registers (P8), Table 2B.53, Control Registers (P9), Table 2B.55, Control Registers (P10), Table 2B.57, Control Registers (P11), Table 2B.59, Control Registers (P12), Table 2B.61, Control Registers (P13), Table 2B.63, Control Registers (P18), Table 2B.65, Control Registers (P19), Table 2B.67, Control Registers (P20), Table 2B.69, Control Registers (P21), Table 2B.71, Control Registers (P22), Table 2B.73, Control Registers (AP0), Table 2B.75, Control Registers (AP1) and Table 2B.77, Control Registers (IP0). Table 2B.28 PPRn Register Contents Bit Position Bit Name Function 15 to 0 PPRn_[15:0] The Pn_m Pin, Pn.Pn_m value or alternative function output. NOTES 1. For the read values of the PPRn register, see Section 2B.7.4, Pin Data Input/Output. 2. The control bits of the JTAG port pin read register (JPPR0) are JPPR0_[7:0].

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 338 of 4535 Dec 26, 2018 2B.9.3.3 Pn / APn / JP0 — Port Register This register holds the Pn.Pn_m data to be output via the related Pn_m port in output port mode (PMCn.PMCn_m = 0 and PMn.PMn_m = 0). Access: Pn, APn: These registers can be read or written in 16-bit units. JP0: This register can be read or written in 8-bit units. Address: Pn: <PORTn_base> + 0000H + n × 4 (n = 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 18, 19, 20, 21, 22) APn: <PORTn_base> + 00C8H + n × 4 (n = 0, 1) JP0: <JPORT0_base> + 0000H*1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Pn_15 Pn_14 Pn_13 Pn_12 Pn_11 Pn_10 Pn_9 Pn_8 Pn_7 Pn_6 Pn_5 Pn_4 Pn_3 Pn_2 Pn_1 Pn_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2B.10, Port (General I/O) Function Overview: Table 2B.41, Control Registers (JP0), Table 2B.43, Control Registers (P0), Table 2B.45, Control Registers (P1), Table 2B.47, Control Registers (P2), Table 2B.49, Control Registers (P3), Table 2B.51, Control Registers (P8), Table 2B.53, Control Registers (P9), Table 2B.55, Control Registers (P10), Table 2B.57, Control Registers (P11), Table 2B.59, Control Registers (P12), Table 2B.61, Control Registers (P13), Table 2B.63, Control Registers (P18), Table 2B.65, Control Registers (P19), Table 2B.67, Control Registers (P20), Table 2B.69, Control Registers (P21), Table 2B.71, Control Registers (P22), Table 2B.73, Control Registers (AP0), and Table 2B.75, Control Registers (AP1). Table 2B.29 Pn Register Contents Bit Position Bit Name Function 15 to 0 Pn_[15:0] Sets the output level of the Pn_m pin (m = 0 to 15). 0: Outputs low level 1: Outputs high level NOTE The control bits of the JTAG port register (JP0) are JP0_[7:0].

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 339 of 4535 Dec 26, 2018 2B.9.3.4 PNOTn / APNOTn / JPNOT0 — Port NOT Register This register allows the Pn_m bit of the port register Pn to be inverted without directly writing to Pn. Access: PNOTn, APNOTn: These registers are write-only registers that can be written in 16-bit units. When read, 0000H is returned. JPNOT0: This register is a write-only register that can be written in 8-bit units. When read, 00H is returned. Address: PNOTn: <PORTn_base> + 0700H + n × 4 (n = 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 18, 19, 20, 21, 22) APNOTn: <PORTn_base> + 07C8H + n × 4 (n = 0, 1) JPNOT0: <JPORT0_base> + 0070H*1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PNOT n_15 PNOT n_14 PNOT n_13 PNOT n_12 PNOT n_11 PNOT n_10 PNOT n_9 PNOT n_8 PNOT n_7 PNOT n_6 PNOT n_5 PNOT n_4 PNOT n_3 PNOT n_2 PNOT n_1 PNOT n_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W W W W W W W W W W W W W W W W W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2B.10, Port (General I/O) Function Overview: Table 2B.41, Control Registers (JP0), Table 2B.43, Control Registers (P0), Table 2B.45, Control Registers (P1), Table 2B.47, Control Registers (P2), Table 2B.49, Control Registers (P3), Table 2B.51, Control Registers (P8), Table 2B.53, Control Registers (P9), Table 2B.55, Control Registers (P10), Table 2B.57, Control Registers (P11), Table 2B.59, Control Registers (P12), Table 2B.61, Control Registers (P13), Table 2B.63, Control Registers (P18), Table 2B.65, Control Registers (P19), Table 2B.67, Control Registers (P20), Table 2B.69, Control Registers (P21), Table 2B.71, Control Registers (P22), Table 2B.73, Control Registers (AP0), and Table 2B.75, Control Registers (AP1). Table 2B.30 PNOTn Register Contents Bit Position Bit Name Function 15 to 0 PNOTn_[15:0] Specifies if Pn.Pn_m is inverted. 0: Pn.Pn_m is not inverted (Pn_m → Pn_m) 1: Pn.Pn_m is inverted ( Pn_m → Pn_m) NOTE The control bits of the JTAG port NOT register are JPNOT0_[7:0].

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 340 of 4535 Dec 26, 2018 2B.9.3.5 PSRn / APSRn / JPSR0 — Port Set/Reset Register This register provides an alternative method to write data to the Pn register. The upper 16 bits of PSRn act as a mask which specifies whether or not the value Pn.Pn_m is set by the corresponding bit in the lower 16 bits of PSRn. Access: PSRn, APSRn: These registers can be read or written in 32-bit units. Bits 31 to 16 are always read as 0000H. Reading bits 15 to 0 returns the value of registers Pn and APn. JPSR0: This register can be read or written in 32-bit units. Bits 31 to 8 are always read as 000000H. Reading bits 7 to 0 returns the value of register JP0. Address: PSRn: <PORTn_base> + 0100H + n × 4 (n = 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 18, 19, 20, 21, 22) APSRn: <PORTn_base> + 01C8H + n × 4 (n = 0, 1) JPSR0: <JPORT0_base> + 0010H*1 Value after reset: 0000 0000H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PSR n_31 PSR n_30 PSR n_29 PSR n_28 PSR n_27 PSR n_26 PSR n_25 PSR n_24 PSR n_23 PSR n_22 PSR n_21 PSR n_20 PSR n_19 PSR n_18 PSR n_17 PSR n_16 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSR n_15 PSR n_14 PSR n_13 PSR n_12 PSR n_11 PSR n_10 PSR n_9 PSR n_8 PSR n_7 PSR n_6 PSR n_5 PSR n_4 PSR n_3 PSR n_2 PSR n_1 PSR n_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2B.10, Port (General I/O) Function Overview: Table 2B.41, Control Registers (JP0), Table 2B.43, Control Registers (P0), Table 2B.45, Control Registers (P1), Table 2B.47, Control Registers (P2), Table 2B.49, Control Registers (P3), Table 2B.51, Control Registers (P8), Table 2B.53, Control Registers (P9), Table 2B.55, Control Registers (P10), Table 2B.57, Control Registers (P11), Table 2B.59, Control Registers (P12), Table 2B.61, Control Registers (P13), Table 2B.63, Control Registers (P18), Table 2B.65, Control Registers (P19), Table 2B.67, Control Registers (P20), Table 2B.69, Control Registers (P21), Table 2B.71, Control Registers (P22), Table 2B.73, Control Registers (AP0), and Table 2B.75, Control Registers (AP1). Table 2B.31 PSRn Register Contents Bit Position Bit Name Function 31 to 16 PSRn_[31:16] Specifies whether the value of the corresponding lower bit PSRn_m (PSRn_[15:0]) is written to Pn_m. 0: Pn_m is not affected by PSRn_m 1: Pn_m is PSRn_m Example: If PSRn.PSRn_31 = 1, the value of bit PSRn.PSRn_15 is written to bit Pn.Pn_15. 15 to 0 PSRn_[15:0] Specifies the Pn_m value if the corresponding upper bit (PSRn_[31:16]) PSRn_m is 1. 0: Pn_m = 0 1: Pn_m = 1 NOTE The control bits of the JTAG port set/reset register (JPSR0) are JPSR0_[31:0].

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 341 of 4535 Dec 26, 2018 2B.9.4 Configuration of Electrical Characteristics 2B.9.4.1 PUn / JPU0 — Pull-Up Option Register This register specifies whether an internal pull-up resistor is connected to an input pin. Access: PUn: This register can be read or written in 16-bit units. JPU0: This register can be read or written in 8-bit units. Address: PUn: <PORTn_base> + 4300H + n × 4 (n = 0, 1, 2, 3, 8, 9, 10, 11,12, 13, 18, 19, 20, 21, 22) JPU0: <JPORT0_base> + 0430H*1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PUn_15 PUn_14 PUn_13 PUn_12 PUn_11 PUn_10 PUn_9 PUn_8 PUn_7 PUn_6 PUn_5 PUn_4 PUn_3 PUn_2 PUn_1 PUn_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2B.10, Port (General I/O) Function Overview: Table 2B.41, Control Registers (JP0), Table 2B.43, Control Registers (P0), Table 2B.45, Control Registers (P1), Table 2B.47, Control Registers (P2), Table 2B.49, Control Registers (P3), Table 2B.51, Control Registers (P8), Table 2B.53, Control Registers (P9), Table 2B.55, Control Registers (P10), Table 2B.57, Control Registers (P11), Table 2B.59, Control Registers (P12), Table 2B.61, Control Registers (P13), Table 2B.63, Control Registers (P18), Table 2B.65, Control Registers (P19), Table 2B.67, Control Registers (P20), Table 2B.69, Control Registers (P21), and Table 2B.71, Control Registers (P22). Table 2B.32 PUn Register Contents Bit Position Bit Name Function 15 to 0 PUn_[15:0] Specifies whether an internal pull-up resistor is connected to the corresponding pin. 0: No internal pull-up resistor connected 1: An internal pull-up resistor connected NOTES 1. If a pin is configured such that both an internal pull-up resistor (PUn.PUn_m = 1) and pull-down resistor (PDn.PDn_m = 1) are connected, the pull-down resistor is automatically selected and the pull-up resistor is not connected. 2. The pull-up resistor has no effect when the pin is operated in output mode. 3. The control bits of the JTAG pull-up option register (JPU0) are JPU0_[7:0].

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 342 of 4535 Dec 26, 2018 2B.9.4.2 PDn / JPD0 — Pull-Down Option Register This register specifies whether to connect an internal pull-down resistor to an input pin. Access: PDn: This register can be read or written in 16-bit units. JPD0: This register can be read or written in 8-bit units. Address: PDn: <PORTn_base> + 4400H + n × 4 (n = 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 18, 19, 20, 21, 22) JPD0: <JPORT0_base> + 0440H*1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PDn_15 PDn_14 PDn_13 PDn_12 PDn_11 PDn_10 PDn_9 PDn_8 PDn_7 PDn_6 PDn_5 PDn_4 PDn_3 PDn_2 PDn_1 PDn_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2B.10, Port (General I/O) Function Overview: Table 2B.41, Control Registers (JP0), Table 2B.43, Control Registers (P0), Table 2B.45, Control Registers (P1), Table 2B.47, Control Registers (P2), Table 2B.49, Control Registers (P3), Table 2B.51, Control Registers (P8), Table 2B.53, Control Registers (P9), Table 2B.55, Control Registers (P10), Table 2B.57, Control Registers (P11), Table 2B.59, Control Registers (P12), Table 2B.61, Control Registers (P13), Table 2B.63, Control Registers (P18), Table 2B.65, Control Registers (P19), Table 2B.67, Control Registers (P20), Table 2B.69, Control Registers (P21), and Table 2B.71, Control Registers (P22). Table 2B.33 PDn Register Contents Bit Position Bit Name Function 15 to 0 PDn_[15:0] Specifies whether to connect an internal pull-down resistor to the corresponding pin. 0: No internal pull-down resistor connected 1: An internal pull-down resistor connected NOTES 1. If a pin is configured such that both an internal pull-up resistor (PUn.PUn_m = 1) and pull-down resistor (PDn.PDn_m = 1) are connected, the pull-down resistor is automatically selected and the pull-up resistor is not connected. 2. The internal pull-down resistor has no effect when the pin is operated in output mode. 3. The control bits of the JTAG pull-down option register (JPD0) are JPD0_[7:0].

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 343 of 4535 Dec 26, 2018 2B.9.4.3 PDSCn / JPDSC0 — Port Drive Strength Control Register This register specifies the output driver strength of the port pin. This function selects the fast mode (high drive strength) or slow mode (low drive strength) of the output buffer. The correct write sequence using the PPCMDn and JPPCMD0 registers is required in order to update this register. For details, see Section 5, Write-Protected Registers. Regarding the alternative functions for which the PDSC register needs to be set, see Section 2B.11.3.3, Output Buffer Control (PDSC). Access: PDSCn, JPDSC0: These registers can be read or written in 32- bit units. Address: PDSCn: <PORTn_base> + 4600H + n × 4 (n = 0, 1, 2, 3, 10, 11, 12, 13, 18, 19, 20) JPDSC0: <JPORT0_base> + 0460H*1 Value after reset: 0000 0000H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R R R R R R R R R R R R R R R R Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PDSC n_15 PDSC n_14 PDSC n_13 PDSC n_12 PDSC n_11 PDSC n_10 PDSC n_9 PDSC n_8 PDSC n_7 PDSC n_6 PDSC n_5 PDSC n_4 PDSC n_3 PDSC n_2 PDSC n_1 PDSC n_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2B.10, Port (General I/O) Function Overview: Table 2B.41, Control Registers (JP0), Table 2B.43, Control Registers (P0), Table 2B.45, Control Registers (P1), Table 2B.47, Control Registers (P2), Table 2B.49, Control Registers (P3), Table 2B.51, Control Registers (P8), Table 2B.53, Control Registers (P9), Table 2B.55, Control Registers (P10), Table 2B.57, Control Registers (P11), Table 2B.59, Control Registers (P12), Table 2B.61, Control Registers (P13), Table 2B.63, Control Registers (P18), Table 2B.65, Control Registers (P19), and Table 2B.67, Control Registers (P20). Table 2B.34 PDSCn Register Contents Bit Position Bit Name Function 31 to 16 Reserved When read, the value after reset is returned. When writing, write the value after reset. 15 to 0 PDSCn_[15:0] Specifies the port drive strength of the output buffer of the port pin. 0: Lower drive strength (when the frequency output from the pin is 10 MHz or below) 1: High drive strength (when the frequency output from the pin is 40 MHz or less).

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 344 of 4535 Dec 26, 2018 2B.9.4.4 PODCn / JPODC0 — Port Open Drain Control Register This register selects push-pull or open-drain as output buffer function. The correct write sequence using the PPCMDn and JPPCMD0 registers is required in order to update this register. For details, see Section 5, Write- Protected Registers. Access: PODCn, JPODC0: These registers can be read or written in 32-bit units. Address: PODCn: <PORTn_base> + 4500H + n × 4 (n = 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 18, 19, 20, 21, 22) JPODC0: <JPORT0_base> + 0450H*1 Value after reset: 0000 0000H*2 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R R R R R R R R R R R R R R R R Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PODC n_15 PODC n_14 PODC n_13 PODC n_12 PODC n_11 PODC n_10 PODC n_9 PODC n_8 PODC n_7 PODC n_6 PODC n_5 PODC n_4 PODC n_3 PODC n_2 PODC n_1 PODC n_0 Value after reset 0 0 0 0 0 0 0 0 0 0*3 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2B.10, Port (General I/O) Function Overview: Table 2B.41, Control Registers (JP0), Table 2B.43, Control Registers (P0), Table 2B.45, Control Registers (P1), Table 2B.47, Control Registers (P2), Table 2B.49, Control Registers (P3), Table 2B.51, Control Registers (P8), Table 2B.53, Control Registers (P9), Table 2B.55, Control Registers (P10), Table 2B.57, Control Registers (P11), Table 2B.59, Control Registers (P12), Table 2B.61, Control Registers (P13), Table 2B.63, Control Registers (P18), Table 2B.65, Control Registers (P19), Table 2B.67, Control Registers (P20), Table 2B.69, Control Registers (P21), and Table 2B.71, Control Registers (P22). Note 2. The PODC8 register is as follows. When the OPBT0.RESETOUTEN = 1, the PODC8 register is 0000 0040H. When the OPBT0.RESETOUTEN = 0, the PODC8 register is 0000 0000H. Note 3. The PODC8_6 bit is as follows. When the OPBT0.RESETOUTEN = 1, the PODC8_6 bit is 1. When the OPBT0.RESETOUTEN = 0, the PODC8_6 bit is 0. Table 2B.35 PODCn Register Contents Bit Position Bit Name Function 31 to 16 Reserved When read, the value after reset is returned. When writing, write the value after reset. 15 to 0 PODCn_[15:0] Specifies the output buffer function. 0: Push-pull 1: Open-drain NOTE The control bits of the JTAG port open drain control register (JPODC0) are JPODC0_[31:0].

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 345 of 4535 Dec 26, 2018 2B.9.4.5 PISn/JPIS0 — Port Input Buffer Selection Register This register specifies the input buffer characteristics. Access: PISn: This register can be read or written in 16-bit units. JPIS0: This register can be read or written in 8-bit units. Address: PISn: <PORTn_base> + 4700H + n × 4 (n = 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 18, 19, 20, 21, 22) JPIS0: <JPORT0_base> + 0470H*1 Value after reset: FFFFH Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PIS n_15 PIS n_14 PIS n_13 PIS n_12 PIS n_11 PIS n_10 PIS n_9 PIS n_8 PIS n_7 PIS n_6 PIS n_5 PIS n_4 PIS n_3 PIS n_2 PIS n_1 PIS n_0 Value after reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2B.10, Port (General I/O) Function Overview: Table 2B.41, Control Registers (JP0), Table 2B.43, Control Registers (P0), Table 2B.45, Control Registers (P1), Table 2B.47, Control Registers (P2), Table 2B.49, Control Registers (P3), Table 2B.51, Control Registers (P8), Table 2B.53, Control Registers (P9), Table 2B.55, Control Registers (P10), Table 2B.57, Control Registers (P11), Table 2B.59, Control Registers (P12), Table 2B.61, Control Registers (P13), Table 2B.63, Control Registers (P18), Table 2B.65, Control Registers (P19), Table 2B.67, Control Registers (P20), Table 2B.69, Control Registers (P21), and Table 2B.71, Control Registers (P22). Table 2B.36 PISn Register Contents Bit Position Bit Name Function 15 to 0 PISn_[15:0] Specifies the input buffer Characteristics: 0: Type 1 (SHMT1) 1: Type 2 (SHMT4) NOTES 1. Details of the definition of type 1 and type 2 are given in Section 2B.11.3.2, Input Buffer Control (PISn/JPIS0, PISAn/JPISA0). For details, also see Section 47B, Electrical Characteristics of RH850/F1KM-S4 for input buffer characteristics. 2. The control bits of the JTAG port input buffer selection register (JPIS0) are JPIS0_[7:0].

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 346 of 4535 Dec 26, 2018 2B.9.4.6 PISAn / JPISA0 — Port Input Buffer Selection Advanced Register This register specifies the input buffer characteristics. Access: PISAn: This register can be read or written in 16-bit units. JPISA0: This register can be read or written in 8-bit units. Address: PISAn: <PORTn_base> + 4A00H + n × 4 (n = 10, 11, 12, 13, 18) JPISA0: <JPORT0_base> + 04A0H*1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PISA n_15 PISA n_14 PISA n_13 PISA n_12 PISA n_11 PISA n_10 PISA n_9 PISA n_8 PISA n_7 PISA n_6 PISA n_5 PISA n_4 PISA n_3 PISA n_2 PISA n_1 PISA n_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2B.10, Port (General I/O) Function Overview: Table 2B.41, Control Registers (JP0), Table 2B.55, Control Registers (P10), Table 2B.57, Control Registers (P11), Table 2B.59, Control Registers (P12), Table 2B.61, Control Registers (P13), and Table 2B.63, Control Registers (P18). Table 2B.37 PISAn Register Contents Bit Position Bit Name Function 15 to 0 PISA_[15:0] Specifies the input buffer characteristics: 0: Type 2 (SHMT4) 1: Type 5 (TTL) Table 2B.38 Port Input Selection Advanced Register Contents PISAn PISn Function 0 0 Type 1 input buffer is selected (SHMT1) Details of the definition of type 2 and type 5 are given in Section 2B.11.3.2, Input Buffer Control (PISn/JPIS0, PISAn/JPISA0). For details, also see Section 47B, Electrical Characteristics of RH850/F1KM-S4 for input buffer characteristics.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 347 of 4535 Dec 26, 2018 2B.9.5 Port Register Protection RH850/F1KM has Port Protection Command Registers (PPCMDn) and Port Protection Status Registers (PPROTSn ) which implement the Port Protection Cluster Function. For details on the registers, see Section 5, Write -Protected Registers. 2B.9.6 Flowchart Examples for Port Settings Examples of the port settings are shown in the flowchart below. CAUTION If the port is set to the PIPCn.PIPCn_m = 0 and alternative output mode, the port might briefly enter alternative input mode. This will occur between when the PMCn.PMCn_m bit is set to 1 and when the PMn.PMn_m bit is set to 0. If an interrupt-related signal is specified as an alternate function of the port, the mode will temporarily become the alternative input mode, so either disable the interrupt in question, or specify that the interrupt is ignored.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 348 of 4535 Dec 26, 2018 2B.9.6.1 Batch Setting An example of specifying batch port settings is shown in the flowchart below. Specify PIBCn.PIBCn_m bit = 0 Specify PBDCn.PBDCn_m bit = 0 Specify PMn.PMn_m bit = 1 Specify PMCn.PMCn_m bit = 0 Specify PIPCn.PIPCn_m bit = 0 Specify PIPCn.PIPCn_m bit Specify Pn.Pn_m bit Specify PMCn.PMCn_m bit Specify PMn.PMn_m bit Specify PIBCn.PIBCn_m bit Specify PFCn.PFCn_m, PFCEn.PFCEn_m, PFCAEn.PFCAEn_m bits Set port filters*1 Specify PDSCn.PDSCn_m, PODCn.PODCn_m, PBDCn.PBDCn_m, PUn.PUn_m, PDn.PDn_m, PISn.PISn_m bits PISAn.PISAn_m bits Port initialization: Set the initial port values. (The port is set to input mode and the input buffer is disabled.) Port settings: Set appropriate values. Alternative input mode is entered when the PIPCn.PIPCn_m bit is 0 and the PMCn.PMCn_m bit is 1. START Note 1. While PMC = 0, an interrupt may be triggered during the configuration of the port registers under the following conditions: For NMI, INTP7 and INTP8 interrupt requests:

• The port filter is set to low level detection.
• The port filter is set to rising edge or both edge detection and the PMC register is set to 1 while the input terminal is at high level. For INTP0-6 and INTP9-23 interrupt requests:
• The port filter is set to high level detection.
• The port filter is set to falling edge or both edges detection and the PMC register is set to 1 while the input terminal is at low level. In order to avoid the unintended interrupt occurrence, use the following configuration sequence: 1. Configure the PMC register. 2. Wait for the period of pulse rejection. 3. Configure the edge/level detection register. Figure 2B.7 Example of Port Settings (When Specified in Batch)

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 349 of 4535 Dec 26, 2018 2B.9.6.2 Individual Settings An example of specifying individual port settings is shown in the flowchart below. Specify PIBCn.PIBCn_m bit = 0 Specify PBDCn.PBDCn_m bit = 0 Specify PMn.PMn_m bit = 1 Specify PMCn.PMCn_m bit = 0 Specify PIPCn.PIPCn_m bit = 0 Specify PIBCn.PIBCn_m bit = 1 Specify Pn.Pn_m bit Specify PUn.PUn_m, PDn.PDn_m bits Set port filters Specify PDSCn.PDSCn_m, PODCn.PODCn_m, PBDCn.PBDCn_m bits Output mode Input mode Input or output? Specify PISn.PISn_m bits PISAn.PISAn_m bits Specify PMn.PMn_m bit = 0 Port initialization: Set the initial port values. (The port is set to input mode and the input buffer is disabled.) Port settings: Set appropriate values. START Figure 2B.8 Example of Port Settings (in Port Mode)

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 350 of 4535 Dec 26, 2018 (1) With IP Control Specify PIBCn.PIBCn_m bit = 0 Specify PBDCn.PBDCn_m bit = 0 Specify PMn.PMn_m bit = 1 Specify PMCn.PMCn_m bit = 0 Specify PIPCn.PIPCn_m bit = 0 Specify PIPCn.PIPCn_m bit = 1 Specify PMCn.PMCn_m bit = 1 Specify PISn.PISn_m bits PISAn.PISAn_m bits Set port filters Specify PUn.PUn_m, PDn.PDn_m bits Input function port settings: Set appropriate values. Alternative mode (with IP control) port settings: Set appropriate values. Output function port settings: Set appropriate values. Specify PFCn.PFCn_m, PFCEn.PFCEn_m, PFCAEn.PFCAEn_m bits Specify PDSCn.PDSCn_m, PODCn.PODCn_m, PBDCn.PBDCn_m bits Port initialization: Set the initial port values. (The port is set to input mode and the input buffer is disabled.) START Figure 2B.9 Example of Port Settings (in Alternative Mode)

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 351 of 4535 Dec 26, 2018 (2) Without IP Control Specify PIBCn.PIBCn_m bit = 0 Specify PBDCn.PBDCn_m bit = 0 Specify PMn.PMn_m bit = 1 Specify PMCn.PMCn_m bit = 0 Specify PIPCn.PIPCn_m bit = 0 Specify PUn.PUn_m, PDn.PDn_m bits Specify PFCn.PFCn_m, PFCEn.PFCEn_m, PFCAEn.PFCAEn_m bits Specify PDSCn.PDSCn_m, PODCn.PODCn_m, PBDCn.PBDCn_m bits Specify PISn.PISn_m bit PISAn.PISAn_m bits Specify PMn.PMn_m bit = 0Specify PMCn.PMCn_m bit = 1 Specify PFCn.PFCn_m, PFCEn.PFCEn_m, PFCAEn.PFCAEn_m bits Specify PMCn.PMCn_m bit = 1 Alternative input mode Set port filters*1 Output mode Input mode Input or output? Port initialization: Set the initial port values. (The port is set to input mode and the input buffer is disabled.) Port settings: Set appropriate values. START Note 1. While PMC = 0, an interrupt may be triggered during the configuration of the port registers under the following conditions: For NMI, INTP7 and INTP8 interrupt requests:

• The port filter is set to low level detection.
• The port filter is set to rising edge or both edge detection and the PMC register is set to 1 while the input terminal is at high level. For INTP0-6 and INTP9-23 interrupt requests:
• The port filter is set to high level detection.
• The port filter is set to falling edge or both edges detection and the PMC register is set to 1 while the input terminal is at low level. In order to avoid the unintended interrupt occurrence, use the following configuration sequence: 1. Configure the PMC register. 2. Wait for the period of pulse rejection. 3. Configure the edge/level detection register. Figure 2B.10 Example of Port Settings (in Alternative Mode)

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 352 of 4535 Dec 26, 2018 2B.10 Port (General I/O) Function Overview This section explains the port (general I/O) functions and all the functions assigned to the ports. See the following pages for details. In addition, whether the port mode is alternative mode or not can be selected by PMCn register setting. When PMCn.PMCn_m = 1, alternative functions are selected by the PFCn, PFCEn, and PFCAEn registers. Table 2B.39 Port Function Port Pin Name Size Direction Power Domain Special Alternative Function Device JTAG Port 0 JP0_0 - 5 6 bits In/Out AWO JTAG, LPD  — — — — Port 0 P0_0 - 14 15 bits In/Out AWO      Port 1 P1_0 - 5, 8-11 10 bits In/Out AWO —  — — — Port 2 P2_0 - 6 7 bits In/Out AWO — —  — — Port 3 P3_0 1 bit In/Out AWO — — —  — Port 8 P8_2 - 12 11 bits In/Out AWO ADCA0 (10-bit resolution) RESETOUT Port 9 P9_0 - 4 5 bits In/Out ISO ADCA0 (10-bit resolution)      Port 10 P10_0 - 14 15 bits In/Out ISO  — — — — Port 11 P11_1 - 7 7 bits In/Out ISO  — — — — P11_0 - 12, 15 14 bits —     Port 12 P12_0 - 2 3 bits In/Out ISO —  — — — Port 13 P13_0 - 7 8 bits In/Out ISO — — —   Port 18 P18_0 - 3 4 bits In/Out ISO ADCA1 (10-bit resolution) —  — — — Port 19 P19_0 - 3 4 bits In/Out ISO ADCA1 (10-bit resolution) — — —   Port 20 P20_4 - 5 2 bits In/Out ISO —  — — — Port 21 P21_0 - 4 5 bits In/Out ISO — — — —  Port 22 P22_0 - 15 16 bits In/Out ISO — — — —  Analog Port 0 AP0_0 - 15 16 bits In/Out AWO ADCA0 (12/10-bit resolution) Analog Port 1 AP1_0 - 7 8 bits In/Out ISO ADCA1 (12/10-bit resolution) AP1_0 - 15 16 bits ADCA1 (12/10-bit resolution) Input Port 0 IP0_0 1 bit In AWO SOSC (XT2 pin) —    

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 353 of 4535 Dec 26, 2018 2B.10.1 JTAG Port 0 (JP0) 2B.10.1.1 Alternative Function The following alternative functions are available when JTAG port 0 is c onfigured as a general-purpose I/O port by setting OPJTAG[1:0] on the corresponding option byte to 00B. Table 2B.40 JTAG Port 0 (JP0) Port Mode (JPMC0_m = Alternative Mode (JPMC0_m = 1) ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins Input Output Input Output Input Output Input Output Input Output JP0_0*1 INTP0 TAUJ2I0 TAUJ2O0 FPDR FPDT DCUTDI/LPDI/LPDIO 28 39 47 U4 V5 JP0_1 INTP1 TAUJ0I0 TAUJ0O0 FPDT DCUTDO/LPDO 27 38 46 P5 W4 JP0_2 INTP2 TAUJ0I1 TAUJ0O1 FPCK DCUTCK/LPDCLK 26 37 45 T4 U5 JP0_3 INTP3 CSCXFOUT TAUJ0I2 TAUJ0O2 DCUTMS 25 36 44 R4 V4 JP0_4 DCUTRST 24 35 43 R3 Y3 JP0_5 NMI RTCA0OUT TAUJ0I3 TAUJ0O3 DCURDY /LPDCLKOUT 23 34 42 U3 W3 JP0_6 EVTO — 54 66 U11 W11 Note 1. In LPD (1 pin) mode, the JP0_0 output buffer state is Open-drain. CAUTION The behavior and performance are not guaranteed when alternative functions are not assigned to the register.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 354 of 4535 Dec 26, 2018 2B.10.1.2 Control Registers Table 2B.41 Control Registers (JP0) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins JP0 JTAG port register 0 8 5-0 R/W 0000H 00H  — — — — JPSR0 JTAG port set/reset register 0 32 21-16, 5-0 R/W 0010H 0000 0000H  — — — — JPPR0 JTAG port pin read register 0 8 5-0 R 0020H 00H  — — — — JPM0 JTAG port mode register 0 8 5-0 R/W 0030H FFH  — — — — JPMC0 JTAG port mode control register 0 8 5, 3-0 R/W 0040H 00H      JPFC0 JTAG port function control register 0 8 5, 3-0 R/W 0050H 00H      JPFCE0 JTAG port function control expansion register 0 8 2-0 R/W 0060H 00H      JPNOT0 JTAG port NOT register 0 8 5-0 W 0070H 00H  — — — — JPMSR0 JTAG port mode set/reset register 0 32 21-16, 5-0 R/W 0080H 0000 FFFFH  — — — — JPMCSR0 JTAG port mode control set/reset register 32 21, 19-16, 5, 3-0 R/W 0090H 0000 0000H      JPIBC0 JTAG port input buffer control register 0 8 5-0 R/W 0400H 00H  — — — — JPBDC0 JTAG port bidirection control register 0 8 5-0 R/W 0410H 00H  — — — — JPU0 Pull-up option register 0 8 5-0 R/W 0430H 00H  — — — — JPD0 Pull-down option register 0 8 5-0 R/W 0440H 00H  — — — — JPODC0 JTAG port open drain control register 0 32 5-0 R/W 0450H 0000 0000H  — — — — JPDSC0 JTAG port drive strength control register 32 5, 3-1 R/W 0460H 0000 0000H  — — — — JPIS0 JTAG port input buffer selection register 0 8 5, 3-0 R/W 0470H FFH  — — — — JPISA0 JTAG port input buffer selection advanced register 0 8 3, 2, 0 R/W 04A0H 00H      JPPROTS0 JTAG port protection status register 0 32 0 R 04B0H 0000 0000H      JPPCMD0 JTAG port protection command register 0 32 7-0 W 04C0H xxxx xx00H      Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 355 of 4535 Dec 26, 2018 2B.10.2 Port 0 (P0) 2B.10.2.1 Alternative Function Table 2B.42 Port 0 (P0) Port Mode (PMC0_m = Alternative Mode (PMC0_m =1) ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output P0_0 TAUD0I2 TAUD0O2 RLIN20RX CAN0TX PWGA10O CSIH0SSI DPO TAUJ2I1 TAUJ2O1 6 13 18 J1 M1 P0_1 TAUD0I4 TAUD0O4 CAN0RX/ INTP0 RLIN20TX INTP0 PWGA11O CSIH0SI APO TAUJ2I2 TAUJ2O2 CAN0RX 7 14 19 J2 M2 P0_2 TAUD0I6 TAUD0O6 CAN1RX/ INTP1 RLIN30TX PWGA12O CSIH0SC INTP1 DPO TAUJ2I3 TAUJ2O3 CAN1RX 8 15 20 J4 N4 P0_3 TAUD0I8 TAUD0O8 RLIN30RX/ INTP10 CAN1TX DPIN1 PWGA13O CSIH0SO INTP10 TAUJ1I0 TAUJ1O0 RLIN30RX 9 16 21 K1 L3 P0_4 RLIN31RX/ INTP11 CAN2TX INTP11 PWGA10O CSIH1SI SELDP0 DPIN8 TAUB0I12 TAUB0O12 RLIN31RX 11 18 23 K3 N1 P0_5 CAN2RX/ INTP2 RLIN31TX DPIN9 SELDP1 CSIH1SO TAUB0I14 TAUB0O14 CAN2RX 12 19 24 K2 N2 P0_6 INTP2 DPIN10 SELDP2 CSIH1SC PWGA35O 13 20 25 L3 M3 P0_7 RLIN21RX DPIN5 CSCXFOUT CSIH1RYI CSIH1RYO TAUB0I0 TAUB0O0 CAN3RX/ INTP3 CAN3RX 40 58 70 R11 V11 P0_8 INTP16 RLIN21TX DPIN6 CSIH0CSS6 CSIH1SSI TAUB0I2 TAUB0O2 CAN3TX — 57 69 T12 V10 RLIN21TX DPIN6 CSIH0CSS6 CSIH1SSI TAUB0I2 TAUB0O2 CAN3TX 39 — — — — P0_9 INTP12 CSIH1CSS0 DPIN7 RLIN22RX TAUB0I4 TAUB0O4 CAN4RX/ INTP4 CAN4RX 38 56 68 R10 U10 P0_10 INTP3 CSIH1CSS1 DPIN11 RLIN22TX TAUB0I6 TAUB0O6 CAN4TX 37 55 67 T11 Y12 P0_11 RIIC0SDA DPIN12 CSIH1CSS2 TAUB0I8 TAUB0O8 RLIN26RX PWGA34O — — 26 L1 P1 RIIC0SDA DPIN12 CSIH1CSS2 TAUB0I8 TAUB0O8 PWGA34O 14 21 — — — P0_12 RIIC0SCL DPIN13 PWGA45O TAUB0I10 TAUB0O10 CSIG0SI RLIN26TX — — 27 L2 P2 RIIC0SCL DPIN13 PWGA45O TAUB0I10 TAUB0O10 CSIG0SI 15 22 — — — P0_13 RLIN32RX/ INTP12 INTP12 PWGA46O TAUB0I12 TAUB0O12 CSIG0SO CAN5RX/ INTP5 RLIN32RX CAN5RX 16 23 28 M1 R1 P0_14 INTP17 RLIN32TX PWGA47O TAUB0I14 TAUB0O14 CSIG0SC CAN5TX — 24 29 L4 P3 RLIN32TX PWGA47O TAUB0I14 TAUB0O14 CSIG0SC CAN5TX 17 — — — —

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 356 of 4535 Dec 26, 2018 CAUTION The behavior and performance are not guaranteed when undocumented alternative functions are selected.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 357 of 4535 Dec 26, 2018 2B.10.2.2 Control Registers Table 2B.43 Control Registers (P0) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins P0 Port register 0 16 14-0 R/W 0000H 0000H      PSR0 Port set/reset register 0 32 30-16, 14-0 R/W 0100H 0000 0000H      PPR0 Port pin read register 0 16 14-0 R 0200H 0000H      PM0 Port mode register 0 16 14-0 R/W 0300H FFFFH      PMC0 Port mode control register 0 16 14-0 R/W 0400H 0000H      PFC0 Port function control register 0 16 14-0 R/W 0500H 0000H      PFCE0 Port function control expansion register 0 16 14-0 R/W 0600H 0000H      PNOT0 Port NOT register 0 16 14-0 W 0700H 0000H      PMSR0 Port mode set/reset register 0 32 30-16, 14-0 R/W 0800H 0000 FFFFH      PMCSR0 Port mode control set/reset register 0 32 30-16, 14-0 R/W 0900H 0000 0000H      PFCAE0 Port function control additional expansion register 0 16 14, 13, 10-0 R/W 0A00H 0000H      PIBC0 Port input buffer control register 0 16 14-0 R/W 4000H 0000H      PBDC0 Port bidirection control register 0 16 14-0 R/W 4100H 0000H      PIPC0 Port IP control register 0 16 14, 13, 6, 5, 3, 2 R/W 4200H 0000H      PU0 Pull-up option register 0 16 14-0 R/W 4300H 0000H      PD0 Pull-down option register 0 16 14-0 R/W 4400H 0000H      PODC0 Port open drain control register 0 32 14-0 R/W 4500H 0000 0000H      PDSC0 Port drive strength control register 0 32 14-0 R/W 4600H 0000 0000H      PIS0 Port input buffer selection register 0 16 14-0 R/W 4700H FFFFH      PPROTS0 Port protection status register 0 32 0 R 4B00H 0000 0000H      PPCMD0 Port protection command register 0 32 7-0 W 4C00H XXXX XX00H      Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 358 of 4535 Dec 26, 2018 2B.10.3 Port 1 (P1) 2B.10.3.1 Alternative Function Table 2B.44 Port 1 (P1) Port Mode (PMC1_m = 0) Alternative Mode (PMC1_m = 1) ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output P1_0 RLIN33RX/ INTP13 INTP13 TAUJ2I0 TAUJ2O0 RLIN33RX — 25 30 M2 T1 P1_1 INTP18 RLIN33TX TAUJ2I1 TAUJ2O1 — 26 31 N2 R2 P1_2 CAN3RX/ INTP3 INTP3 DPIN19 TAUJ2I2 TAUJ2O2 CAN3RX — 27 32 N1 U1 P1_3 INTP19 CAN3TX DPIN23 TAUJ2I3 TAUJ2O3 — 28 33 N3 R4 P1_4 RLIN35RX/ INTP15 INTP15 DPIN18 RLIN35RX — 63 75 U13 W12 P1_5 ADCA1TRG0 RLIN35TX DPIN17 INTP20 — 62 74 U12 Y13 P1_8 — 43 53 U5 Y6 P1_9 DPIN20 INTP21 — 42 52 R7 U6 P1_10 RLIN24RX DPIN21 INTP22 ADCA1TRG1 — 41 51 R6 Y5 P1_11 ADCA1TRG2 RLIN24TX DPIN22 INTP14 — 40 50 P6 V6 P1_12 CAN4RX/ INTP4 INTP4 RLIN36TX CAN4RX — — 34 P1 T2 P1_13 CAN4TX RLIN36RX /INTP16 RLIN36RX — — 35 P2 V1 P1_14 RLIN23RX CAN7RX /INTP9 CAN7RX — — 78 U14 Y14 P1_15 RLIN23TX CAN7TX — — 79 R13 U13 CAUTION The behavior and performance are not guaranteed when undocumented alternative functions are selected.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 359 of 4535 Dec 26, 2018 2B.10.3.2 Control Registers Table 2B.45 Control Registers (P1) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins P1 Port register 1 16 11-8, 5-0 R/W 0004H 0000H —  — — — PSR1 Port set/reset register 1 32 27-24, 21-16, 11-8, 5-0 R/W 0104H 0000 0000H —  — — — 31-24, 21-16, 15-8, 5-0 PPR1 Port pin read register 1 16 11-8, 5-0 R 0204H 0000H —  — — — PM1 Port mode register 1 16 11-8, 5-0 R/W 0304H FFFFH —  — — — PMC1 Port mode control register 1 16 11-9, 5-0 R/W 0404H 0000H —  — — — PFC1 Port function control register 1 16 11-9, 5-0 R/W 0504H 0000H —  — — — PFCE1 Port function control expansion register 1 16 11-9, 5-0 R/W 0604H 0000H —  — — — PNOT1 Port NOT register 1 16 11-8, 5-0 W 0704H 0000H —  — — — PMSR1 Port mode set/reset register 1 32 27-24, 21-16, 11-8, 5-0 R/W 0804H 0000 FFFFH —  — — — 31-24, 21-16, 15-8, 5-0 PMCSR1 Port mode control set/reset register 1 32 27-25, 21-16, 11-9, 5-0 R/W 0904H 0000 0000H —  — — — 31-25, 21-16, 15-9, 5-0 PFCAE1 Port function control additional expansion register 1 16 4, 2, 0 R/W 0A04 PIBC1 Port input buffer control register 1 16 11-8, 5-0 R/W 4004H 0000H —  — — — PBDC1 Port bidirection control register 1 16 11-8, 5-0 R/W 4104H 0000H —  — — — PU1 Pull-up option register 1 16 11-8, 5-0 R/W 4304H 0000H —  — — — PD1 Pull-down option register 1 16 11-8, 5-0 R/W 4404H 0000H —  — — — PODC1 Port open drain control register 1 32 11-8, 5-0 R/W 4504H 0000 0000H —  — — — PDSC1 Port drive strength control register 1 32 11-8, 5-0 R/W 4604H 0000 0000H —  — — — PIS1 Port input buffer selection register 1 16 11-8, 5-0 R/W 4704H FFFFH —  — — — PPROTS1 Port protection status register 1 32 0 R 4B04H 0000 0000H —     PPCMD1 Port protection command register 1 32 7-0 W 4C04H xxxx xx00H —     Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 360 of 4535 Dec 26, 2018 2B.10.4 Port 2 (P2) 2B.10.4.1 Alternative Function Table 2B.46 Port 2 (P2) CAUTION The behavior and performance are not guaranteed when undocumented alternative functions are selected. Port Mode (PMC2_m =0) Alternative Mode (PMC2_m =1) ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output P2_0 RLIN27RX CAN6RX/ INTP6 CAN6RX — — 49 T5 W5 P2_1 RLIN27TX CAN6TX — — 48 R5 Y4 P2_2 RLIN28RX — — 65 T10 W10 P2_3 RLIN28TX — — 64 U10 W9 P2_4 RLIN29RX ADCA0SEL0 — — 76 T13 W13 P2_5 RLIN29TX ADCA0SEL1 — — 77 R12 V12 P2_6 ADCA0SEL2 — — 36 R1 R3 P2_7 RLIN210RX — — — M4 U2 P2_8 RLIN210TX — — — T1 T3 P2_9 PWGA77O — — — M3 T4 P2_10 PWGA78O — — — R2 W1 P2_11 PWGA79O — — — N4 U3 P2_12 RLIN211RX — — — T2 V2 P2_13 RLIN211TX — — — P7 V7 P2_14 PWGA74O — — — T6 W6 P2_15 PWGA75O — — — P8 W7

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 361 of 4535 Dec 26, 2018 2B.10.4.2 Control Registers Table 2B.47 Control Registers (P2) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins P2 Port register 2 16 6-0 R/W 0008H 0000H — —  — — PSR2 Port set/reset register 2 32 22-16, 6-0 R/W 0108H 0000 0000H — —  — — PPR2 Port pin read register 2 16 6-0 R 0208H 0000H — —  — — PM2 Port mode register 2 16 6-0 R/W 0308H FFFFH — —  — — PMC2 Port mode control register 2 16 6-0 R/W 0408H 0000H — —  — — PFC2 Port function control register 2 16 5, 4, 1, 0 R/W 0508H 0000H — —    PFCE2 Port function control expansion register 2 16 0 R/W 0608H 0000H — —    PNOT2 Port NOT register 2 16 6-0 W 0708H 0000H — —  — — PMSR2 Port mode set/reset register 2 32 22-16, 6-0 R/W 0808H 0000 FFFFH — —  — — PMCSR2 Port mode control set/reset register 32 22-16, 6-0 R/W 0908H 0000 0000H — —  — — PFCAE2 Port function control additional expansion register 2 16 0 R/W 0A08H 0000H — —    PIBC2 Port input buffer control register 2 16 6-0 R/W 4008H 0000H — —  — — PBDC2 Port bidirection control register 2 16 6-0 R/W 4108H 0000H — —  — — PU2 Pull-up option register 2 16 6-0 R/W 4308H 0000H — —  — — PD2 Pull-down option register 2 16 6-0 R/W 4408H 0000H — —  — — PODC2 Port open drain control register 2 32 6-0 R/W 4508H 0000 0000H — —  — — PDSC2 Port drive strength control register 2 32 6-0 R/W 4608H 0000 0000H — —  — — PIS2 Port input buffer selection register 2 16 6-0 R/W 4708H FFFFH — —  — — PPROTS2 Port protection status register 2 32 0 R 4B08H 0000 0000H — —    PPCMD2 Port protection command register 2 32 7-0 W 4C08H xxxx xx00H — —    Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 362 of 4535 Dec 26, 2018 2B.10.5 Port 3 (P3) 2B.10.5.1 Alternative Function Table 2B.48 Port 3 (P3) Port Mode (PMC3_m =0) Alternative Mode (PMC3_m =1) ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output P3_0 PWGA76O — — — R8 V8 CAUTION The behavior and performance are not guaranteed when undocumented alternative functions are selected.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 363 of 4535 Dec 26, 2018 2B.10.5.2 Control Registers Table 2B.49 Control Registers (P3) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins P3 Port register 3 16 0 R/W 000CH 0000H — — —  — PSR3 Port set/reset register 3 32 16, 0 R/W 010CH 0000 0000H — — —  — PPR3 Port pin read register 3 16 0 R 020CH 0000H — — —  — PM3 Port mode register 3 16 0 R/W 030CH FFFFH — — —  — PMC3 Port mode control register 3 16 0 R/W 040CH 0000H — — —  — PNOT3 Port NOT register 3 16 0 W 070CH 0000H — — —  — PMSR3 Port mode set/reset register 3 32 16, 0 R/W 080CH 0000 FFFFH — — —  — PMCSR3 Port mode control set/reset register 3 32 16, 0 R/W 090CH 0000 0000H — — —  — PIBC3 Port input buffer control register 3 16 0 R/W 400CH 0000H — — —  — PBDC3 Port bidirection control register 3 16 0 R/W 410CH 0000H — — —  — PU3 Pull-up option register 3 16 0 R/W 430CH 0000H — — —  — PD3 Pull-down option register 3 16 0 R/W 440CH 0000H — — —  — PODC3 Port open drain control register 3 32 0 R/W 450CH 0000 0000H — — —  — PDSC3 Port drive strength control register 3 32 0 R/W 460CH 0000 0000H — — —  — PIS3 Port input buffer selection register 3 16 0 R/W 470CH FFFFH — — —  — PPROTS3 Port protection status register 3 32 0 R 4B0CH 0000 0000H — — —   PPCMD3 Port protection command register 3 32 7-0 W 4C0CH 0000 0000H — — —   Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 364 of 4535 Dec 26, 2018 2B.10.6 Port 8 (P8) 2B.10.6.1 Alternative Function Table 2B.50 Port 8 (P8) Port Mode (PMC8_m = 0) Alternative Mode (PMC8_m = 1) ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output P8_0 TAUJ0I0 TAUJ0O0 DPIN2 PWGA14O INTP4 CSIH0CSS0 CAN6RX/ INTP6 RIIC1SDA SENT0RX CAN6RX ADCA0I0S — 64 80 U15 W14 P8_1 TAPA0ESO TAUJ0O1 DPIN0 PWGA15O INTP5 CSIH1CSS3 CAN6TX RIIC1SCL SENT0SPCO ADCA0I1S — 65 81 T14 V13 P8_2 TAUJ0I0 TAUJ0O0 DPIN2 CSIH0CSS0 INTP6 PWGA22O RLIN37TX ADCA0I4S — — 38 U2 W2 TAUJ0I0 TAUJ0O0 DPIN2 CSIH0CSS0 INTP6 PWGA22O ADCA0I4S 19 30 — — — P8_3 TAUJ0I1 TAUJ0O1 DPIN3 CSIH0CSS1 INTP7 PWGA23O CAN7TX ADCA0I5S 44 66 82 U16 Y15 P8_4 TAUJ0I2 TAUJ0O2 DPIN4 CSIH0CSS2 INTP8 PWGA36O CAN7RX/ INTP9 CAN7RX ADCA0I6S 45 67 83 R14 W15 P8_5 TAUJ0I3 TAUJ0O3 NMI CSIH0CSS3 INTP9 PWGA37O ADCA0I7S 46 68 84 T15 Y16 P8_6 NMI CSIH0CSS4 PWGA38O RTCA0OUT ADCA0I8S RESETOUT 47 69 85 P13 Y17 P8_7 CSIH3CSS0 PWGA39O ADCA0SEL0 RTCA0OUT ADCA0I14S 48 70 86 R15 V15 P8_8 CSIH3CSS1 PWGA40O ADCA0SEL1 RLIN34RX /INTP14 RLIN34RX ADCA0I15S — 71 87 P14 W17 CSIH3CSS1 PWGA40O ADCA0SEL1 ADCA0I15S 49 — — — — P8_9 CSIH3CSS2 PWGA41O ADCA0SEL2 RLIN34TX ADCA0I16S — 72 88 T16 Y18 CSIH3CSS2 PWGA41O ADCA0SEL2 ADCA0I16S 50 — — — — P8_10 CSIH3CSS3 DPIN14 PWGA42O RLIN37RX /INTP17 RLIN37RX ADCA0I17S — — 39 P3 V3 CSIH3CSS3 DPIN14 PWGA42O ADCA0I17S 20 31 — — — P8_11 TAUJ1I2 TAUJ1O2 DPIN15 PWGA43O CSIH1CSS4 RLIN25RX ADCA0I18S — 32 40 T3 Y2 TAUJ1I2 TAUJ1O2 DPIN15 PWGA43O CSIH1CSS4 ADCA0I18S 21 — — — — P8_12 TAUJ1I3 TAUJ1O3 DPIN16 PWGA44O CSIH1CSS5 INTP23 RLIN25TX ADCA0I19S — 33 41 P4 U4 TAUJ1I3 TAUJ1O3 DPIN16 PWGA44O CSIH1CSS5 ADCA0I19S 22 — — — —

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 365 of 4535 Dec 26, 2018 CAUTIONS 1. The behavior and performance are not guaranteed when undocumented alternative functions are selected. 2. Use ADC functions with their initial settings. For details, see Table 2B.51, Control Registers (P8). 3. When the RESETOUT function is selected for the P8_6 pin, the output on the pin is at the low level during a reset and after release from the reset state. For details, see Section 2B.11.1.1, P8_6: RESETOUT .

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 366 of 4535 Dec 26, 2018 2B.10.6.2 Control Registers Table 2B.51 Control Registers (P8) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins P8 Port register 8 16 12-2 R/W 0020H 0000H  — — — — PSR8 Port set/reset register 8 32 28-18, 12-2 R/W 0120H 0000 0000H  — — — — PPR8 Port pin read register 8 16 12-2 R 0220H 0000H  — — — — PM8 Port mode register 8 16 12-2 R/W 0320H FFBFH  — — — — PMC8 Port mode control register 8 16 12-2 R/W 0420H 0000H  — — — — PFC8 Port function control register 8 16 12-2 R/W 0520H 0000H  — — — — PFCE8 Port function control expansion register 8 16 12, 11, 9-2 R/W 0620H 0000H  — — — — PNOT8 Port NOT register 8 16 12-2 W 0720H 0000H  — — — — PMSR8 Port mode set/reset register 8 32 28-18, 12-2 R/W 0820H 0000 FFBFH  — — — — PMCSR8 Port mode control set/reset register 8 32 28-18, 12-2 R/W 0920 PFCAE8 Port function control additional expansion register 8 16 4 R/W 0A20 PIBC8 Port input buffer control register 16 12-2 R/W 4020 PBDC8 Port bidirection control register 8 16 12-2 R/W 4120H 0000H  — — — — PU8 Pull-up option register 8 16 12-2 R/W 4320H 0000H  — — — — PD8 Pull-down option register 8 16 12-2 R/W 4420H 0000H  — — — — PODC8 Port open drain control register 8 32 12-2 R/W 4520H 0000 0040H  — — — — PIS8 Port input buffer selection register 8 16 12-2 R/W 4720H FFFFH  — — — — PPROTS8 Port protection status register 8 32 0 R 4B20H 0000 0000H      PPCMD8 Port protection command register 8 32 7-0 W 4C20H xxxx xx00H      Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset. CAUTION P8_6 drives a low level after any kind of reset release, until it is later configured differently by register settings. For details, see Section 2B.11.1.1, P8_6: RESETOUT .

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 367 of 4535 Dec 26, 2018 2B.10.7 Port 9 (P9) 2B.10.7.1 Alternative Function Table 2B.52 Port 9 (P9) Port Mode (PMC9_m = 0) Alternative Mode (PMC9_m = 1) ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output P9_0 NMI PWGA8O TAUD0I0 TAUD0O0 ADCA0TRG0 CSIH2CSS0 KR0I4 TAUJ1I1 TAUJ1O1 SENT1RX RIIC1SDA ADCA0I2S 69 92 108 K16 N18 P9_1 INTP11 PWGA9O TAUD0I2 TAUD0O2 KR0I5 CSIH2CSS1 TAUJ1I2 TAUJ1O2 SENT1SPCO RIIC1SCL ADCA0I3S 70 93 109 K17 N19 P9_2 KR0I6 PWGA20O TAPA0ESO CSIH2CSS2 ADCA0I9S 71 94 110 J17 N20 P9_3 KR0I7 PWGA21O CSIH2CSS3 TAUJ1I1 TAUJ1O1 INTP16 ADCA0I10S — 95 111 J15 M18 KR0I7 PWGA21O CSIH2CSS3 TAUJ1I1 TAUJ1O1 ADCA0I10S 72 — — — — P9_4 CSIH0CSS5 PWGA33O TAUJ1I0 TAUJ1O0 INTP17 ADCA0I11S — 96 112 J16 M19 CSIH0CSS5 PWGA33O TAUJ1I0 TAUJ1O0 ADCA0I11S 73 — — — — CAUTIONS 1. The behavior and performance are not guaranteed when undocumented alternative functions are selected. 2. Use ADC functions with their initial settings. For details, see Table 2B.53, Control Registers (P9).

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 368 of 4535 Dec 26, 2018 2B.10.7.2 Control Registers Table 2B.53 Control Registers (P9) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins P9 Port register 9 16 4-0 R/W 0024H 0000H      PSR9 Port set/reset register 9 32 20-16, 4-0 R/W 0124H 0000 0000H      PPR9 Port pin read register 9 16 4-0 R 0224H 0000H      PM9 Port mode register 9 16 4-0 R/W 0324H FFFFH      PMC9 Port mode control register 9 16 4-0 R/W 0424H 0000H      PFC9 Port function control register 9 16 4-0 R/W 0524H 0000H      PFCE9 Port function control expansion register 9 16 4, 3, 1, 0 R/W 0624H 0000H      PNOT9 Port NOT register 9 16 4-0 W 0724H 0000H      PMSR9 Port mode set/reset register 9 32 20-16, 4-0 R/W 0824H 0000 FFFFH      PMCSR9 Port mode control set/reset register 9 32 20-16, 4-0 R/W 0924H 0000 0000H      PFCAE9 Port function control additional expansion register 9 16 1, 0 R/W 0A24H 0000H      PIBC9 Port input buffer control register 9 16 4-0 R/W 4024H 0000H      PBDC9 Port bidirection control register 9 16 4-0 R/W 4124H 0000H      PU9 Pull-up option register 9 16 4-0 R/W 4324H 0000H      PD9 Pull-down option register 9 16 4-0 R/W 4424H 0000H      PODC9 Port open drain control register 9 32 4-0 R/W 4524H 0000 0000H      PIS9 Port input buffer selection register 9 16 4-0 R/W 4724H FFFFH      PPROTS9 Port protection status register 9 32 0 R 4B24H 0000 0000H      PPCMD9 Port protection command register 9 32 7-0 W 4C24H xxxx xx00H      Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 369 of 4535 Dec 26, 2018 2B.10.8 Port 10 (P10) 2B.10.8.1 Alternative Function Table 2B.54 Port 10 (P10) Port Mode (PMC10_m = 0) Alternative Mode (PMC10_m = 1) ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output P10_0 TAUD0I1 TAUD0O1 CAN0RX/ INTP0 CSCXFO UT PWGA0O TAUJ1I3 TAPA0UP CSIH1SI MEMC0A19 ETNB0RXC LK TAUJ1O3 CAN0RX — — 174 A2 C4 TAUD0I1 TAUD0O1 CAN0RX/ INTP0 CSCXFO UT PWGA0O TAUJ1I3 TAPA0UP CSIH1SI TAUJ1O3 CAN0RX 98 142 — — — P10_1 TAUD0I3 TAUD0O3 INTP18 CAN0TX PWGA1O TAUJ3I0 TAPA0UN CSIH1SC ETNB0RXD MEMC0A20 TAUJ3O0 MODE0 — — 175 B2 B3 TAUD0I3 TAUD0O3 INTP18 CAN0TX PWGA1O TAUJ3I0 TAPA0UN CSIH1SC TAUJ3O0 MODE0 — 143 — — — TAUD0I3 TAUD0O3 CAN0TX PWGA1O TAUJ3I0 TAPA0UN CSIH1SC TAUJ3O0 MODE0 99 — — — — P10_2 TAUD0I5 TAUD0O5 RIIC0SDA KR0I0 PWGA2O ADCA0TR TAPA0VP CSIH1SO ETNB0RXD MEMC0A21 RLIN37TX MODE1 — — 176 C3 C3 TAUD0I5 TAUD0O5 RIIC0SDA KR0I0 PWGA2O ADCA0TR TAPA0VP CSIH1SO MODE1 100 144 — — — P10_3 TAUD0I7 TAUD0O7 RIIC0SCL KR0I1 PWGA3O ADCA0TR TAPA0VN CSIH1SSI MEMC0CLK RLIN37RX/ INTP17 RLIN37RX — — 1 B1 B2 TAUD0I7 TAUD0O7 RIIC0SCL KR0I1 PWGA3O ADCA0TR TAPA0VN CSIH1SSI 1 1 — — — P10_4 TAUD0I9 TAUD0O9 RLIN21RX CAN6TX KR0I2 ADCA0SE ADCA0TR TAPA0WP CSIG0SSI PWGA53O ETNB0RXD MEMC0A22 — — 2 D3 E3 TAUD0I9 TAUD0O9 RLIN21RX CAN6TX KR0I2 ADCA0SE ADCA0TR TAPA0WP CSIG0SSI PWGA53O — 2 — — — TAUD0I9 TAUD0O9 RLIN21RX CAN6TX KR0I2 ADCA0SE ADCA0TR TAPA0WP CSIG0SSI 2 — — — — P10_5 TAUD0I11 TAUD0O11 CAN6RX/ INTP6 RLIN21T X KR0I3 ADCA0SE TAPA0WN CSIG0RYI CSIG0RYO ETNB0RXD PWGA54O CAN6RX — — 3 C2 D3 TAUD0I11 TAUD0O11 CAN6RX/ INTP6 RLIN21T X KR0I3 ADCA0SE TAPA0WN CSIG0RYI CSIG0RYO PWGA54O CAN6RX — 3 — — — TAUD0I11 TAUD0O11 CAN6RX/ INTP6 RLIN21T X KR0I3 ADCA0SE TAPA0WN CSIG0RYI CSIG0RYO CAN6RX 3 — — — — P10_6 TAUD0I13 TAUD0O13 CSIG0S O ENCA0TIN ADCA0SE CAN1RX /INTP1 MEMC0AD0 RLIN24RX CAN1RX MODE2 — — 152 A9 A12 TAUD0I13 TAUD0O13 CSIG0S O ENCA0TIN ADCA0SE CAN1RX /INTP1 RLIN24RX CAN1RX MODE2 — 120 — — — TAUD0I13 TAUD0O13 CSIG0S O ENCA0TIN ADCA0SE CAN1RX /INTP1 CAN1RX MODE2 80 — — — —

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 370 of 4535 Dec 26, 2018 Table 2B.54 Port 10 (P10) Port Mode (PMC10_m = 0) Alternative Mode (PMC10_m = 1) ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output P10_7 TAUD0I15 TAUD0O15 CSIG0SC ENCA0TIN PWGA4O CAN1TX MEMC0AD1 RLIN24TX TAUJ3I1 TAUJ3O1 — — 153 A8 C11 TAUD0I15 TAUD0O15 CSIG0SC ENCA0TIN PWGA4O CAN1TX RLIN24TX TAUJ3I1 TAUJ3O1 — 121 — — — TAUD0I15 TAUD0O15 CSIG0SC ENCA0TIN PWGA4O CAN1TX TAUJ3I1 TAUJ3O1 81 — — — — P10_8 TAUD0I10 TAUD0O10 CSIG0SI FLXA0TX DB ENCA0EC PWGA5O MEMC0AD2 TAUJ3I2 TAUJ3O2 FLMD1 — — 154 D8 B11 TAUD0I10 TAUD0O10 CSIG0SI FLXA0TX DB ENCA0EC PWGA5O TAUJ3I2 TAUJ3O2 FLMD1 82 122 — — — P10_9 TAUD0I12 TAUD0O12 RLIN30RX /INTP10 ENCA0E0 PWGA6O CSIH0RYI CSIH0RY O MEMC0AD3 FLXA0RXD B RLIN30RX — — 155 B8 C12 TAUD0I12 TAUD0O12 RLIN30RX /INTP10 ENCA0E0 PWGA6O CSIH0RYI CSIH0RY O FLXA0RXD B RLIN30RX 83 123 — — — P10_10 TAUD0I14 TAUD0O14 RLIN30T X ENCA0E1 PWGA7O CSIH0CSS MEMC0AD4 TAUJ3I3 TAUJ3O3 — — 156 A7 A11 TAUD0I14 TAUD0O14 RLIN30T X ENCA0E1 PWGA7O CSIH0CSS TAUJ3I3 TAUJ3O3 84 124 — — — P10_11 PWGA16O RLIN31RX /INTP11 FLXA0TX ENA CSIH1CS TAUB0I1 TAUB0O1 MEMC0AD5 RLIN31RX — — 157 C8 D11 PWGA16O RLIN31RX /INTP11 FLXA0TX ENA CSIH1CS TAUB0I1 TAUB0O1 RLIN31RX 85 125 — — — P10_12 PWGA17O FLXA0STP WT RLIN31T X CSIH1CS TAUB0I3 TAUB0O3 MEMC0AD6 — — 158 D7 A10 PWGA17O FLXA0STP WT RLIN31T X CSIH1CS TAUB0I3 TAUB0O3 86 126 — — — P10_13 CSIH0SSI PWGA18O RLIN32RX /INTP12 FLXA0TX ENB TAUB0I5 TAUB0O5 MEMC0AD7 CAN7TX RLIN32RX — — 159 A6 C10 CSIH0SSI PWGA18O RLIN32RX /INTP12 FLXA0TX ENB TAUB0I5 TAUB0O5 CAN7TX RLIN32RX 87 127 — — —

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 371 of 4535 Dec 26, 2018 Table 2B.54 Port 10 (P10) Port Mode (PMC10_m = 0) Alternative Mode (PMC10_m = 1) ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output P10_14 ADCA1TRG PWGA19O FLXA0RXD A RLIN32T X CSIH3SSI TAUB0I7 TAUB0O7 MEMC0AD8 CAN7RX/ INTP9 CAN7RX — — 160 B7 B10 ADCA1TRG PWGA19O FLXA0RXD A RLIN32T X CSIH3SSI TAUB0I7 TAUB0O7 CAN7RX/ INTP9 CAN7RX — 128 — — — PWGA19O FLXA0RXD A RLIN32T X CSIH3SSI TAUB0I7 TAUB0O7 CAN7RX/ INTP9 CAN7RX 88 — — — — P10_15 CSIH3RYI CSIH3RYO PWGA24 O RLIN22RX TAUB0I9 TAUB0O9 MEMC0RD — — 6 C1 D1 CSIH3RYI CSIH3RYO PWGA24 O RLIN22RX TAUB0I9 TAUB0O9 — 4 — — — CAUTION The behavior and performance are not guaranteed when undocumented alternative functions are selected.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 372 of 4535 Dec 26, 2018 2B.10.8.2 Control Registers Table 2B.55 Control Registers (P10) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins P10 Port register 10 16 14-0 R/W 0028H 0000H  — — — — 15-0 R/W 0028H 0000H —     PSR10 Port set/reset register 10 32 30-16, 14-0 R/W 0128H 0000 0000H  — — — — 31-16, 15-0 R/W 0128H 0000 0000H —     PPR10 Port pin read register 10 16 14-0 R 0228H 0000H  — — — — 15-0 R 0228H 0000H —     PM10 Port mode register 10 16 14-0 R/W 0328H FFFFH  — — — — 15-0 R/W 0328H FFFFH —     PMC10 Port mode control register 10 16 14-0 R/W 0428H 0000H  — — — — 15-0 R/W 0428H 0000H —     PFC10 Port function control register 10 16 14-0 R/W 0528H 0000H  — — — — 15-0 R/W 0528H 0000H —     PFCE10 Port function control expansion register 10 16 14-0 R/W 0628H 0000H  — — — — 15-0 R/W 0628H 0000H —     PNOT10 Port NOT register 10 16 14-0 W 0728H 0000H  — — — — 15-0 W 0728H 0000H —     PMSR10 Port mode set/reset register 10 32 30-16, 14-0 R/W 0828H 0000 FFFFH  — — — — 31-16, 15-0 R/W 0828H 0000 FFFFH —     PMCSR10 Port mode control set/reset register 10 32 30-16, 14-0 R/W 0928H 0000 0000H  — — — — 31-16, 15-0 R/W 0928H 0000 0000H —     PFCAE10 Port function control additional expansion register 10 16 14-0 R/W 0A28H 0000H   — — — PIBC10 Port input buffer control register 10 16 14-0 R/W 4028H 0000H  — — — — 15-0 R/W 4028H 0000H —     PBDC10 Port bidirection control register 10 16 14-0 R/W 4128H 0000H  — — — — 15-0 R/W 4128H 0000H —     PIPC10 Port IP control register 10 16 7-0 R/W 4228H 0000H   — — — PU10 Pull-up option register 10 16 14-0 R/W 4328H 0000H  — — — — 15-0 R/W 4328H 0000H —     PD10 Pull-down option register 10 16 14-0 R/W 4428H 0000H  — — — — 15-0 R/W 4428H 0000H —     PODC10 Port open drain control register 10 32 14-0 R/W 4528H 0000 0000H  — — — — 15-0 R/W 4528H 0000 0000H —     PDSC10 Port drive strength control register 10 32 14-0 R/W 4628H 0000 0000H  — — — — 15-0 R/W 4628H 0000 0000H —     PIS10 Port input buffer selection register 10 16 14-0 R/W 4728H FFFFH  — — — — 15-0 R/W 4728H FFFFH —     PISA10 Port input buffer selection advanced register 10 16 5, 4, 2-0 R/W 4A28 PPROTS10 Port protection status register 10 32 0 R 4B28H 0000 0000H      PPCMD10 Port protection command register 10 32 7-0 W 4C28H xxxx xx00H      Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset..

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 373 of 4535 Dec 26, 2018 2B.10.9 Port 11 (P11) 2B.10.9.1 Alternative Function Table 2B.56 Port 11 (P11) Port mode (PMC11_m = 0) Alternative Mode (PMC11_m = 1) ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output P11_0 CSIH2RYI CSIH2RY O ADCA1TR PWGA25O RLIN22TX TAUB0I11 TAUB0O11 MEMC0WR — — 7 D2 E1 CSIH2RYI CSIH2RY O ADCA1TR PWGA25O RLIN22TX TAUB0I11 TAUB0O11 — 5 — — — P11_1 CSIH2SSI FLXA0TX DA RLIN20RX CSIH0CS INTP20 PWGA26O TAUB0I13 TAUB0O13 MEMC0AD9 — — 161 A5 A9 CSIH2SSI FLXA0TX DA RLIN20RX CSIH0CS INTP20 PWGA26O TAUB0I13 TAUB0O13 — 129 — — — CSIH2SSI FLXA0TX DA RLIN20RX CSIH0CS PWGA26O TAUB0I13 TAUB0O13 89 — — — — P11_2 CSIH2SO RLIN32RX /INTP12 RLIN20TX PWGA27O TAUB0I15 TAUB0O15 MEMC0AD10 SFMA0IO3 RLIN32RX — — 162 C7 D9 CSIH2SO RLIN32RX /INTP12 RLIN20TX PWGA27O TAUB0I15 TAUB0O15 SFMA0IO3 RLIN32RX — 130 — — — CSIH2SO RLIN32RX /INTP12 RLIN20TX PWGA27O TAUB0I15 TAUB0O15 RLIN32RX 90 — — — — P11_3 CSIH2SC CAN3RX /INTP3 PWGA28O TAUB1I1 TAUB1O1 MEMC0AD11 RLIN32TX SFMA0IO2 CAN3RX — — 163 B6 C9 CSIH2SC CAN3RX /INTP3 PWGA28O RLIN32TX SFMA0IO2 CAN3RX — 131 — — — CSIH2SC CAN3RX /INTP3 PWGA28O RLIN32TX CAN3RX 91 — — — — P11_4 CSIH2SI CAN3TX INTP21 PWGA29O TAUB1I3 TAUB1O3 MEMC0AD12 SFMA0IO1 — — 164 B5 B8 CSIH2SI CAN3TX INTP21 PWGA29O SFMA0IO1 — 132 — — — CSIH2SI CAN3TX PWGA29O 92 — — — — P11_5 CAN5RX/ INTP5 RLIN33TX PWGA30O CSIH3SI TAUB1I5 TAUB1O5 MEMC0AD13 SFMA0IO0 CAN5RX — — 165 A4 B7 CAN5RX/ INTP5 RLIN33TX PWGA30O CSIH3SI SFMA0IO0 CAN5RX — 133 — — — CAN5RX/ INTP5 PWGA30O CSIH3SI CAN5RX 93 — — — —

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 374 of 4535 Dec 26, 2018 Table 2B.56 Port 11 (P11) Port mode (PMC11_m = 0) Alternative Mode (PMC11_m = 1) ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output P11_6 RLIN33RX /INTP13 CAN5TX ADCA1TR PWGA31O CSIH3SO TAUB1I7 TAUB1O7 MEMC0AD14 SFMA0SS L RLIN33RX — — 166 D6 C7 RLIN33RX /INTP13 CAN5TX ADCA1TR PWGA31O CSIH3SO SFMA0SS L RLIN33RX — 134 — — — INTP13 CAN5TX PWGA31O CSIH3SO 94 — — — — P11_7 INTP5 PWGA32O CSIH3SC TAUB1I9 TAUB1O9 MEMC0AD15 SFMA0CL K — — 167 C6 D8 INTP5 PWGA32O CSIH3SC SFMA0CL K — 135 — — — INTP5 PWGA32O CSIH3SC 95 — — — — P11_8 CSIG1SSI RLIN35TX PWGA48O TAUB1I11 TAUB1O11 MEMC0CS0 — — 8 E3 E2 CSIG1SSI RLIN35TX PWGA48O — 6 — — — P11_9 CSIG1SO RLIN35RX /INTP15 PWGA49O TAUB1I13 TAUB1O13 MEMC0CS1 RLIN35RX — — 9 D1 F3 CSIG1SO RLIN35RX /INTP15 PWGA49O RLIN35RX — 7 — — — P11_10 CSIG1SC PWGA50O TAUB1I15 TAUB1O15 MEMC0CS2 — — 10 E2 G3 CSIG1SC PWGA50O — 8 — — — P11_11 CSIG1SI RLIN25TX PWGA51O TAUB1I0 TAUB1O0 MEMC0CS3 ETNB0 RXDV — — 11 F3 G2 CSIG1SI RLIN25TX PWGA51O — 9 — — — P11_12 RLIN25RX PWGA52O TAUB1I2 TAUB1O2 MEMC0WAIT — — 12 E1 H2 RLIN25RX PWGA52O — 10 — — — P11_15 CAN2RX /INTP2 CSIH2CS PWGA55O TAUB1I8 TAUB1O8 MEMC0ASTB ETNB0 RXERR RLIN36TX CAN2RX — — 168 D5 A5 CAN2RX /INTP2 CSIH2CS PWGA55O CAN2RX — 136 — — — CAUTION The behavior and performance are not guaranteed when undocumented alternative functions are selected.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 375 of 4535 Dec 26, 2018 2B.10.9.2 Control Registers Table 2B.57 Control Registers (P11) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins P11 Port register 11 16 7-1 R/W 002CH 0000H  — — — — PSR11 Port set/reset register 11 32 23-17, 7-1 R/W 012CH 0000 0000H  — — — — PPR11 Port pin read register 11 16 7-1 R 022CH 0000H  — — — — PM11 Port mode register 11 16 7-1 R/W 032CH FFFFH  — — — — PMC11 Port mode control register 11 16 7-1 R/W 042CH 0000H  — — — — PFC11 Port function control register 11 16 7-1 R/W 052CH 0000H  — — — — PFCE11 Port function control expansion register 11 16 7-5, 3-1 R/W 062CH 0000H  — — — — PNOT11 Port NOT register 11 16 7-1 W 072CH 0000H  — — — — PMSR11 Port mode set/reset register 11 32 23-17, 7-1 R/W 082CH 0000 FFFFH  — — — — PMCSR11 Port mode control set/reset register 11 32 23-17, 7-1 R/W 092CH 0000 0000H  — — — — PFCAE11 Port function control additional expansion register 11 16 5, 3, 2 R/W 0A2CH 0000H  — — — — PIBC11 Port input buffer control register 11 16 7-1 R/W 402CH 0000H  — — — — PBDC11 Port bidirection control register 11 16 7-1 R/W 412CH 0000H  — — — — PIPC11 Port IP control register 11 16 7, 6, 3, 2 R/W 422CH 0000H  — — — — PU11 Pull-up option register 11 16 7-1 R/W 432CH 0000H  — — — — PD11 Pull-down option register 11 16 7-1 R/W 442CH 0000H  — — — — PODC11 Port open drain control register 11 32 7-1 R/W 452CH 0000 0000H  — — — — PDSC11 Port drive strength control register 11 32 7-1 R/W 462CH 0000 0000H  — — — — PIS11 Port input buffer selection register 11 16 7-1 R/W 472CH FFFFH  — — — — PISA11 Port input buffer selection advanced register 11 16 15, 12-10 R/W 4A2CH 0000H — —    PPROTS11 Port protection status register 11 32 0 R 4B2CH 0000 0000H      PPCMD11 Port protection command register 11 32 7-0 W 4C2CH xxxx xx00H      Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 376 of 4535 Dec 26, 2018 2B.10.10 Port 12 (P12) 2B.10.10.1 Alternative Function Table 2B.58 Port 12 (P12) Port Mode (PMC12_m =0) Alternative Mode (PMC12_m =1) ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output P12_0 CAN2TX PWGA56O TAUB1I10 TAUB1O10 CSIG2SSI MEMC0A16 RLIN36RX/INTP16 RLIN36RX — — 169 B4 D7 CAN2TX PWGA56O — 137 — — — P12_1 RLIN34RX/ INTP14 CSIH2CSS5 PWGA57O TAUB1I12 TAUB1O12 MEMC0A17 RLIN34RX — — 170 C5 B5 RLIN34RX/ INTP14 CSIH2CSS5 PWGA57O RLIN34RX — 138 — — — P12_2 INTP19 RLIN34TX PWGA58O TAUB1I14 TAUB1O14 MEMC0A18 CSIG2RYI CSIG2RYO — — 171 A3 C5 INTP19 RLIN34TX PWGA58O — 139 — — — P12_3 RLIN27RX PWGA68O CSIG2SI MEMC0BEN0 TAUB1I6 TAUB1O6 — — 15 G1 L1 P12_4 RLIN27TX PWGA69O CSIG2SC ETNB0MDIO MEMC0BEN1 — — 16 H1 N3 P12_5 PWGA70O ETNB0MDC CSIG2SO TAUB1I4 TAUB1O4 — — 17 J3 L2 CAUTION The behavior and performance are not guaranteed when undocumented alternative functions are selected.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 377 of 4535 Dec 26, 2018 2B.10.10.2 Control Registers Table 2B.59 Control Registers (P12) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins P12 Port register 12 16 2-0 R/W 0030H 0000H —  — — — PSR12 Port set/reset register 12 32 18-16, 2-0 R/W 0130H 0000 0000H —  — — — PPR12 Port pin read register 12 16 2-0 R 0230H 0000H —  — — — PM12 Port mode register 12 16 2-0 R/W 0330H FFFFH —  — — — PMC12 Port mode control register 12 16 2-0 R/W 0430H 0000H —  — — — PFC12 Port function control register 12 16 2-0 R/W 0530H 0000H —  — — — PFCE12 Port function control expansion register 12 16 1 R/W 0630H 0000H —  — — — PNOT12 Port NOT register 12 16 2-0 W 0730H 0000H —  — — — PMSR12 Port mode set/reset register 12 32 18-16, 2-0 R/W 0830H 0000 FFFFH —  — — — PMCSR12 Port mode control set/reset register 12 32 18-16, 2-0 R/W 0930H 0000 0000H —  — — — PFCAE12 Port function control expansion register 12 16 1 R/W 0A30H 0000H —  — — — PIBC12 Port input buffer control register 12 16 2-0 R/W 4030H 0000H —  — — — PBDC12 Port bidirection control register 12 16 2-0 R/W 4130H 0000H —  — — — PIPC12 Port IP control register 12 16 5, 4 R/W 4230H 0000H — —    PU12 Pull-up option register 12 16 2-0 R/W 4330H 0000H —  — — — PD12 Pull-down option register 12 16 2-0 R/W 4430H 0000H —  — — — PODC12 Port open drain control register 12 32 2-0 R/W 4530H 0000 0000H —  — — — PDSC12 Port drive strength control register 12 32 2-0 R/W 4630H 0000 0000H —  — — — PIS12 Port input buffer selection register 12 16 2-0 R/W 4730H FFFFH —  — — — PISA12 Port input buffer selection advanced register 12 16 4 R/W 4A30H 0000H — —    PPROTS12 Port protection status register 12 32 0 R 4B30H 0000 0000H —     PPCMD12 Port protection command register 12 32 7-0 W 4C30H xxxx xx00H —     Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 378 of 4535 Dec 26, 2018 2B.10.11 Port 13 (P13) 2B.10.11.1 Alternative Function Table 2B.60 Port 13 (P13) Port Mode (PMC13_m =0) Alternative Mode (PMC13_m =1) ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output P13_0 MEMC0A19 — — — C4 D6 P13_1 MEMC0A20 — — — B3 A3 P13_2 ETNB0RXDV — — — F2 K3 P13_3 ETNB0RXERR — — — F1 J1 P13_4 — — — G2 K1 P13_5 MEMC0A21 — — — G3 L4 P13_6 MEMC0A22 PWGA72O — — — H3 K2 P13_7 MEMC0A23 PWGA73O — — — — M4 PWGA73O — — — H2 — CAUTION The behavior and performance are not guaranteed when undocumented alternative functions are selected.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 379 of 4535 Dec 26, 2018 2B.10.11.2 Control Registers Table 2B.61 Control Registers (P13) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins P13 Port register 13 16 7-0 R/W 0034H 0000H — — —   PSR13 Port set/reset register 13 32 23-16, 7-0 R/W 0134H 0000 0000H — — —   PPR13 Port pin read register 13 16 7-0 R 0234H 0000H — — —   PM13 Port mode register 13 16 7-0 R/W 0334H FFFFH — — —   PMC13 Port mode control register 13 16 7-5, 3-0 R/W 0434H 0000H — — —   PFC13 Port function control register 13 16 7, 6 R/W 0534H 0000H — — —   PNOT13 Port NOT register 13 16 7-0 W 0734H 0000H — — —   PMSR13 Port mode set/reset register 13 32 23-16, 7-0 R/W 0834H 0000 FFFFH — — —   PMCSR13 Port mode control set/reset register 13 32 23-21, 19-16, 7-5, 3-0 R/W 0934H 0000 0000H — — —   PIBC13 Port input buffer control register 13 16 7-0 R/W 4034H 0000H — — —   PBDC13 Port bidirection control register 13 16 7-0 R/W 4134H 0000H — — —   PU13 Pull-up option register 13 16 7-0 R/W 4334H 0000H — — —   PD13 Pull-down option register 13 16 7-0 R/W 4434H 0000H — — —   PODC13 Port open drain control register 13 32 7-0 R/W 4534H 0000 0000H — — —   PDSC13 Port drive strength control register 13 32 7-0 R/W 4634H 0000 0000H — — —   PIS13 Port input buffer selection register 13 16 7-0 R/W 4734H FFFFH — — —   PISA13 Port input buffer selection advanced register 13 16 5, 3, 2 R/W 4A34H 0000H — — —   PPROTS13 Port protection status register 13 32 0 R 4B34H 0000 0000H — — —   PPCMD13 Port protection command register 13 32 7-0 W 4C34H 0000 0000H — — —   Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 380 of 4535 Dec 26, 2018 2B.10.12 Port 18 (P18) 2B.10.12.1 Alternative Function Table 2B.62 Port 18 (P18) Port Mode (PMC18_m = 0) Alternative Mode (PMC18_m = 1) ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output P18_0 CSIG1RYI CSIG1RYO ETNB0LINK PWGA61O TAUJ3I0 TAUJ3O0 ADCA1I0S — — 143 C14 A19 CSIG1RYI CSIG1RYO PWGA61O TAUJ3I0 TAUJ3O0 ADCA1I0S — 115 — — — P18_1 PWGA62O ETNB0TXD0 TAUJ3I1 TAUJ3O1 ADCA1I1S — — 144 B15 B18 PWGA62O TAUJ3I1 TAUJ3O1 ADCA1I1S — 116 — — — P18_2 PWGA63O ETNB0TXD1 TAUJ3I2 TAUJ3O2 ADCA1I2S — — 145 B14 B17 PWGA63O TAUJ3I2 TAUJ3O2 ADCA1I2S — 117 — — — P18_3 PWGA71O ETNB0TXD2 TAUJ3I3 TAUJ3O3 ADCA1I3S — — 146 B13 A17 TAUJ3I3 TAUJ3O3 ADCA1I3S — 118 — — — P18_4 CSIH1CSS4 ETNB0TXD3 ADCA1I4S — — 147 C11 B16 P18_5 CSIH1CSS5 ETNB0TXEN ADCA1I5S — — 148 A14 D14 P18_6 ADCA1I6S — — 149 A13 A16 P18_7 ETNB0TXCLK ADCA1I7S — — 150 B11 B14 P18_8 ADCA1I8S — — — A16 C17 P18_9 ADCA1I9S — — — C13 A18 P18_10 ADCA1I10S — — — A15 C16 P18_11 ADCA1I11S — — — B12 C15 P18_12 ADCA1I12S — — — C12 C14 P18_13 ADCA1I13S — — — A12 B15 P18_14 ADCA1I14S — — — C9 A15 P18_15 ADCA1I15S — — — A11 C13 CAUTIONS 1. The behavior and performance are not guaranteed when undocumented alternative functions are selected. 2. Use ADC functions with their initial settings. For details, see Table 2B.63, Control Registers (P18).

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 381 of 4535 Dec 26, 2018 2B.10.12.2 Control Registers Table 2B.63 Control Registers (P18) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins P18 Port register 18 16 3-0 R/W 0048H 0000H —  — — — PSR18 Port set/reset register 18 32 19-16, 3-0 R/W 0148H 0000 0000H —  — — — PPR18 Port pin read register 18 16 3-0 R 0248H 0000H —  — — — PM18 Port mode register 18 16 3-0 R/W 0348H FFFFH —  — — — PMC18 Port mode control register 18 16 3-0 R/W 0448H 0000H —  — — — PFC18 Port function control register 18 16 3-0 R/W 0548H 0000H —  — — — PFCE18 Port function control expansion register 18 16 3-0 R/W 0648H 0000H —     PNOT18 Port NOT register 18 16 3-0 W 0748H 0000H —  — — — PMSR18 Port mode set/reset register 18 32 19-16, 3-0 R/W 0848H 0000 FFFFH —  — — — PMCSR18 Port mode control set/reset register 18 32 18-16, 3-0 R/W 0948H 0000 0000H —  — — — PIBC18 Port input buffer control register 18 16 3-0 R/W 4048H 0000H —  — — — PBDC18 Port bidirection control register 18 16 3-0 R/W 4148H 0000H —  — — — PU18 Pull-up option register 18 16 3-0 R/W 4348H 0000H —  — — — PD18 Pull-down option register 18 16 3-0 R/W 4448H 0000H —  — — — PODC18 Port open drain control register 18 32 3-0 R/W 4548H 0000 0000H —  — — — PDSC18 Port drive strength control register 18 32 3-0 R/W 4648H 0000 0000H —  — — — PIS18 Port input buffer selection register 18 16 3-0 R/W 4748H FFFFH —  — — —

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 382 of 4535 Dec 26, 2018 Table 2B.63 Control Registers (P18) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins PISA18 Port input buffer selection advanced register 18 16 7, 0 R/W 4A48H 0000H — —  — — PPROTS18 Port protection status register 18 32 0 R 4B48H 0000 0000H —     PPCMD18 Port protection command register 18 32 7-0 W 4C48H xxxx xx00H —     Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 383 of 4535 Dec 26, 2018 2B.10.13 Port 19 (P19) 2B.10.13.1 Alternative Function Table 2B.64 Port 19 (P19) Port Mode (PMC19_m =0) Alternative Mode (PMC19_m =1) ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output P19_0 ADCA1I16S — — — C10 A14 P19_1 ADCA1I17S — — — B10 B13 P19_2 ADCA1I18S — — — A10 B12 P19_3 ADCA1I19S — — — B9 A13 CAUTION 1. The behavior and performance are not guaranteed when undocumented alternative functions are selected. 2. Use ADC functions with their initial settings. For details, see Table 2B.65, Control Registers (P19).

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 384 of 4535 Dec 26, 2018 2B.10.13.2 Control Registers Table 2B.65 Control Registers (P19) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins P19 Port register 19 16 3-0 R/W 004CH 0000H — — —   PSR19 Port set/reset register 19 32 19-16, 3-0 R/W 014CH 0000 0000H — — —   PPR19 Port pin read register 19 16 3-0 R 024CH 0000H — — —   PM19 Port mode register 19 16 3-0 R/W 034CH FFFFH — — —   PNOT19 Port NOT register 19 16 3-0 W 074CH 0000H — — —   PMSR19 Port mode set/reset register 19 32 19-16, 3-0 R/W 084CH 0000 FFFFH — — —   PIBC19 Port input buffer control register 19 16 3-0 R/W 404CH 0000H — — —   PBDC19 Port bidirection control register 19 16 3-0 R/W 414CH 0000H — — —   PU19 Pull-up option register 19 16 3-0 R/W 434CH 0000H — — —   PD19 Pull-down option register 19 16 3-0 R/W 444CH 0000H — — —   PODC19 Port open drain control register 19 32 3-0 R/W 454CH 0000 0000H — — —   PDSC19 Port drive strength control register 19 32 3-0 R/W 464CH 0000 0000H — — —   PIS19 Port input buffer selection register 19 16 3-0 R/W 474CH FFFFH — — —   PPROTS19 Port protection status register 19 32 0 R 4B4CH 0000 0000H — — —   PPCMD19 Port protection command register 19 32 7-0 W 4C4CH 0000 0000H — — —   Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 385 of 4535 Dec 26, 2018 2B.10.14 Port 20 (P20) 2B.10.14.1 Alternative Function Table 2B.66 Port 20 (P20) Port Mode (PMC20_m =0) Alternative Mode (PMC20_m = 1) ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output P20_0 RLIN26RX PWGA64O CAN6RX/ INTP6 CSIG3SI CAN6RX — — 118 G17 J19 P20_1 RLIN26TX PWGA65O CAN6TX CSIG3SO — — 117 H15 J20 P20_2 CAN4RX/ INTP4 PWGA66O RLIN29RX CSIG3SC CAN4RX — — 116 H16 K20 P20_3 CAN4TX PWGA67O RLIN29TX CSIG3RYI CSIG3RYO — — 115 H17 K18 P20_4 RLIN23RX INTP22 PWGA59O CAN7RX/ INTP9 CSIG3SSI CAN7RX — — 120 F17 H20 RLIN23RX INTP22 PWGA59O CAN7RX/ INTP9 CAN7RX — 100 — — — P20_5 RLIN23TX INTP23 PWGA60O CAN7TX — 99 119 G16 J18 P20_6 PWGA88O — — — — G19 P20_7 PWGA89O — — — — G20 P20_8 PWGA90O — — — — H18 P20_9 PWGA91O — — — — H19 P20_10 PWGA92O — — — — K19 P20_11 PWGA93O — — — — L20 P20_12 PWGA94O — — — — L19 P20_13 PWGA95O — — — — L18 CAUTION The behavior and performance are not guaranteed when undocumented alternative functions are selected.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 386 of 4535 Dec 26, 2018 2B.10.14.2 Control Registers Table 2B.67 Control Registers (P20) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins P20 Port register 20 16 5, 4 R/W 0050H 0000H —  — — — PSR20 Port set/reset register 20 32 21-20, 5, 4 R/W 0150H 0000 0000H —  — — — PPR20 Port pin read register 20 16 5, 4 R 0250H 0000H —  — — — PM20 Port mode register 20 16 5, 4 R/W 0350H FFFFH —  — — — PMC20 Port mode control register 20 16 5, 4 R/W 0450H 0000H —  — — — PFC20 Port function control register 20 16 5, 4 R/W 0550H 0000H —  — — — PFCE20 Port function control expansion register 20 16 5, 4 R/W 0650H 0000H —  — — — PNOT20 Port NOT register 20 16 5, 4 W 0750H 0000H —  — — — PMSR20 Port mode set/reset register 20 32 21, 20, 5, 4 R/W 0850H 0000 FFFFH —  — — — PMCSR20 Port mode control set/reset register 20 32 21, 20, 5, 4 R/W 0950H 0000 0000H —  — — — PFCAE20 Port function control additional expansion register 20 16 4 R/W 0A50H 0000H —  — — — PIBC20 Port input buffer control register 20 16 5, 4 R/W 4050H 0000H —  — — — PBDC20 Port bidirection control register 20 16 5, 4 R/W 4150H 0000H —  — — — PIPC20 Port IP control register 20 16 2, 1 R/W 4250H 0000H — —    PU20 Pull-up option register 20 16 5, 4 R/W 4350H 0000H —  — — — PD20 Pull-down option register 20 16 5, 4 R/W 4450H 0000H —  — — — PODC20 Port open drain control register 20 32 5, 4 R/W 4550H 0000 0000H —  — — —

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 387 of 4535 Dec 26, 2018 Table 2B.67 Control Registers (P20) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins PDSC20 Port drive strength control register 20 32 5, 4 R/W 4650H 0000 0000H —  — — — PIS20 Port input buffer selection register 20 16 5, 4 R/W 4750H FFFFH —  — — — PPROTS20 Port protection status register 20 32 0 R 4B50H 0000 0000H —     PPCMD20 Port protection command register 20 32 7-0 W 4C50H xxxx xx00H —     Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 388 of 4535 Dec 26, 2018 2B.10.15 Port 21 (P21) 2B.10.15.1 Alternative Function Table 2B.68 Port 21 (P21) Port Mode (PMC21_m =0) Alternative Mode (PMC21_m = 1) ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output CAUTION The behavior and performance are not guaranteed when undocumented alternative functions are selected.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 389 of 4535 Dec 26, 2018 2B.10.15.2 Control Registers Table 2B.69 Control Registers (P21) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins P21 Port register 21 16 4-0 R/W 0054H 0000H — — — —  PSR21 Port set/reset register 21 32 20-16, 4-0 R/W 0154H 0000 0000H — — — —  PPR21 Port pin read register 21 16 4-0 R 0254H 0000H — — — —  PM21 Port mode register 21 16 4-0 R/W 0354H FFFFH — — — —  PNOT21 Port NOT register 21 16 4-0 W 0754H 0000H — — — —  PMSR21 Port mode set/reset register 21 32 20-16, 4-0 R/W 0854H 0000 FFFFH — — — —  PIBC21 Port input buffer control register 21 16 4-0 R/W 4054H 0000H — — — —  PBDC21 Port bidirection control register 21 16 4-0 R/W 4154H 0000H — — — —  PU21 Pull-up option register 21 16 4-0 R/W 4354H 0000H — — — —  PD21 Pull-down option register 21 16 4-0 R/W 4454H 0000H — — — —  PODC21 Port open drain control register 21 32 4-0 R/W 4554H 0000 0000H — — — —  PIS21 Port input buffer selection register 21 16 4-0 R/W 4754H FFFFH — — — —  PPROTS21 Port protection status register 21 32 0 R 4B54H 0000 0000H — — — —  PPCMD21 Port protection command register 21 32 7-0 W 4C54H 0000 0000H — — — —  Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 390 of 4535 Dec 26, 2018 2B.10.16 Port 22 (P22) 2B.10.16.1 Alternative Function Table 2B.70 Port 22 (P22) Port Mode (PMC22_m =0) Alternative Mode (PMC22_m = 1) ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output CAUTION The behavior and performance are not guaranteed when undocumented alternative functions are selected.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 391 of 4535 Dec 26, 2018 2B.10.16.2 Control Registers Table 2B.71 Control Registers (P22) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins P22 Port register 22 16 15-0 R/W 0058H 0000H — — — —  PSR22 Port set/reset register 22 32 31-16, 15-0 R/W 0158H 0000 0000H — — — —  PPR22 Port pin read register 22 16 15-0 R 0258H 0000H — — — —  PM22 Port mode register 22 16 15-0 R/W 0358H FFFFH — — — —  PNOT22 Port NOT register 22 16 15-0 W 0758H 0000H — — — —  PMSR22 Port mode set/reset register 22 32 31-16, 15-0 R/W 0858H 0000 FFFFH — — — —  PIBC22 Port input buffer control register 22 16 15-0 R/W 4058H 0000H — — — —  PBDC22 Port bidirection control register 22 16 15-0 R/W 4158H 0000H — — — —  PU22 Pull-up option register 22 16 15-0 R/W 4358H 0000H — — — —  PD22 Pull-down option register 22 16 15-0 R/W 4458H 0000H — — — —  PODC22 Port open drain control register 22 32 15-0 R/W 4558H 0000 0000H — — — —  PIS22 Port input buffer selection register 22 16 15-0 R/W 4758H FFFFH — — — —  PPROTS22 Port protection status register 22 32 0 R 4B58H 0000 0000H — — — —  PPCMD22 Port protection command register 22 32 7-0 W 4C58H 0000 0000H — — — —  Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 392 of 4535 Dec 26, 2018 2B.10.17 Analog Port 0 (AP0) 2B.10.17.1 Alternative Function Table 2B.72 Analog Port 0 (AP0) Port Mode Alternative Mode ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output AP0_0 ADCA0I0 68 90 106 K15 P20 AP0_1 ADCA0I1 67 89 105 L17 P19 AP0_2 ADCA0I2 66 88 104 L16 R20 AP0_3 ADCA0I3 65 87 103 M17 P18 AP0_4 ADCA0I4 64 86 102 L15 R19 AP0_5 ADCA0I5 63 85 101 M16 T20 AP0_6 ADCA0I6 62 84 100 N17 P17 AP0_7 ADCA0I7 61 83 99 N16 R18 AP0_8 ADCA0I8 60 82 98 M15 T19 AP0_9 ADCA0I9 59 81 97 P17 U20 AP0_10 ADCA0I10 58 80 96 P16 T18 AP0_11 ADCA0I11 57 79 95 N15 U19 AP0_12 ADCA0I12 56 78 94 R17 V20 AP0_13 ADCA0I13 55 77 93 P15 U18 AP0_14 ADCA0I14 54 76 92 R16 V19 AP0_15 ADCA0I15 53 75 91 T17 W20 CAUTION Use ADC functions with their initial settings. For details, see Table 2B.73, Control Registers (AP0).

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 393 of 4535 Dec 26, 2018 2B.10.17.2 Control Registers Table 2B.73 Control Registers (AP0) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins AP0 Analog port register 0 16 15-0 R/W 00C8H 0000H      APSR0 Analog port set/reset register 0 32 31-16, 15-0 R/W 01C8H 0000 0000H      APPR0 Analog port pin read register 0 16 15-0 R 02C8H 0000H      APM0 Analog port mode register 0 16 15-0 R/W 03C8H FFFFH      APNOT0 Analog port NOT register 0 16 15-0 W 07C8H 0000H      APMSR0 Analog port mode set/reset register 0 32 31-16, 15-0 R/W 08C8H 0000 FFFFH      APIBC0 Analog port input buffer control register 0 16 15-0 R/W 40C8H 0000H      APBDC0 Analog port bidirection control register 0 16 15-0 R/W 41C8H 0000H      Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 394 of 4535 Dec 26, 2018 2B.10.18 Analog Port 1 (AP1) 2B.10.18.1 Alternative Function Table 2B.74 Analog Port 1 (AP1) Port Mode Alternative Mode ADC Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output AP1_0 ADCA1I0 — 109 133 C17 C20 AP1_1 ADCA1I1 — 108 132 D15 D18 AP1_2 ADCA1I2 — 107 131 D16 D19 AP1_3 ADCA1I3 — 106 130 D17 D20 AP1_4 ADCA1I4 — 105 129 F14 E18 AP1_5 ADCA1I5 — 104 128 E15 E19 AP1_6 ADCA1I6 — 103 127 E16 E20 AP1_7 ADCA1I7 — 102 126 F15 F18 AP1_8 ADCA1I8 — — 125 E17 G17 AP1_9 ADCA1I9 — — 124 F16 F19 AP1_10 ADCA1I10 — — 123 G14 F20 AP1_11 ADCA1I11 — — 122 G15 G18 AP1_12 ADCA1I12 — — 137 B16 B19 AP1_13 ADCA1I13 — — 136 C15 B20 AP1_14 ADCA1I14 — — 135 B17 C18 AP1_15 ADCA1I15 — — 134 C16 C19 CAUTION Use ADC functions with their initial settings. For details, see Table 2B.75, Control Registers (AP1).

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 395 of 4535 Dec 26, 2018 2B.10.18.2 Control Registers Table 2B.75 Control Registers (AP1) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins AP1 Analog port register 1 16 7-0 R/W 00CCH 0000H —  — — — APSR1 Analog port set/reset register 1 32 23-16, 7-0 R/W 01CCH 0000 0000H —  — — — APPR1 Analog port pin read register 1 16 7-0 R 02CCH 0000H —  — — — APM1 Analog port mode register 1 16 7-0 R/W 03CCH FFFFH —  — — — APNOT1 Analog port NOT register 1 16 7-0 W 07CCH 0000H —  — — — APMSR1 Analog port mode Set/reset register 1 32 23-16, 7-0 R/W 08CCH 0000 FFFFH —  — — — APIBC1 Analog port input buffer control register 1 16 7-0 R/W 40CCH 0000H —  — — — APBDC1 Analog port bidirection control register 1 16 7-0 R/W 41CCH 0000H —  — — — Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 396 of 4535 Dec 26, 2018 2B.10.19 Input Port 0 (IP0) 2B.10.19.1 Alternative Function Table 2B.76 Input Port 0 (IP0) Port Mode Alternative Mode Special Function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output IP0_0 XT2 — 47 57 T7 W8

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 397 of 4535 Dec 26, 2018 2B.10.19.2 Control Registers Table 2B.77 Control Registers (IP0) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins IPPR0 Input port pin read register 0 16 0 R 02F0H 0000H —     IPIBC0 Port input buffer control register 0 16 0 R/W 40F0H 0000H —     Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset CAUTION When the IP0_0/XT2 pin is used as an input port, set the IPIBC0.0 bit to 1 and stop the SOSC operation. For details on the settings for SOSC operations, see Section 12AB.4.2.7, SOSCE — SubOSC Enable Register. When the IP0_0/XT2 pin is used for the SubOSC (SOSC) not as an input port, set the IPIBC0.0 bit to 0.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 398 of 4535 Dec 26, 2018 2B.11 Port (Special I/O) Function Overview This section describes the port (special I/O) functions. 2B.11.1 Special I/O after Reset The special port function after reset is deasserted is shown below. 2B.11.1.1 P8_6: RESETOUT The P8_6 pin ( RESETOUT signal) changes PM8.PM8_6 and PODC8.PODC8_6 registers value after reset by OPBT0.RESETOUTEN setting. The P8_6 pin outputs a low level while a reset is asserted, and pin status of after the reset is different. (Case 1): OPBT0.RESETOUTEN = 1

• P8.P8_6 = 0: Outputs low level
• PM8.PM8_6 = 0: Output mode
• PODC8.PODC8_6 = 1: Open-drain (Case 2): OPBT0.RESETOUTEN = 0
• P8.P8_6 = 0: Outputs low level
• PM8.PM8_6 = 1: Input mode
• PODC8.PODC8_6 = 0: Push-pull For detail of OPBT0.RESETOUTEN register, see Section 44.9.2, OPBT0 — Option Byte 0, also see Section 9BC.1.3, Reset Output ( RESETOUT ).

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 399 of 4535 Dec 26, 2018 When the P8_6 pin setting is updated with another value, the pin operates by new setting. EVCC/ REGVCC RESET Flash Operation P8_6 RESETOUT RESETOUT enable P8_6 was set to1. General purpose I/O P8_6 is changed to Low output by resets. RESETOUT enable Execution of user program started. Transferred data (OPBT0.RESETOUTEN=1) Reset is asserted Flash sequence Flash sequence RESETOUT Figure 2B.11 P8_6 Pin ( RESETOUT Signal) Operation While a Reset is asserted and released: (Case 1) OPBT0.RESETOUTEN setting is 1

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 400 of 4535 Dec 26, 2018 EVCC/ REGVCC RESET Flash Operation Flash sequence P8_6 RESETOUT RESETOUT disable P8_6 was set to1. General purpose I/O P8_6 is changed to Hi-z by resets. Execution of user program started. Reset is asserted. Flash sequence RESETOUT disable Hi-z Hi-z Transferred data (OPBT0.RESETOUTEN=0) (*1) General purpose I/O P8_6 was set to1. RESETOUT Power lowered POC RESET is asserted. P8_6 is changed to Low output by resets. Note 1. When a reset except POC reset occurs with RESETOUT disable (OPBT0.RESETOUTEN = 0), P8_6 pin ( RESETOUT signal) will be changed to Hi-z. Figure 2B.12 P8_6 Pin ( RESETOUT Signal) Operation While a Reset is asserted and released: (Case 2) OPBT0.RESETOUTEN setting is 0

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 401 of 4535 Dec 26, 2018 2B.11.1.2 JP0_0 to JP0_6: Debug Interface If the OPJTAG[1:0] setting is the combination below, the pins of the JTAG port group can be used as a debug interface after reset release. Table 2B.78 Debug Interface OPJTAG1 OPJTAG0 Mode JP0_0 JP0_1 JP0_2 JP0_3 JP0_4 JP0_5 JP0_6 1 1 Nexus I/F DCUTDI input DCUTDO output DCUTCK input DCUTMS input DCUTRST input DCURDY output EVTO output 0 1 LPD (4 pins) LPDI input LPDO output LPDCLK input Port/ alternative function Port/ alternative function LPDCLK OUT output Port/ alternative function 1 0 LPD (1 pin) LPDIO input/output Port/ alternative function Port/ alternative function Port/ alternative function Port/ alternative function Port/ alternative function Port/ alternative function NOTE For the OPJTAG[1:0] settings, see Section 44.9.2, OPBT0 — Option Byte 0. 2B.11.1.3 FPDR(JP0_0), FPDT(JP0_1), FPCK(JP0_2): Flash Programmer These pins are used for connecting a flash programmer. See Flash Programmer's Manual for details. 2B.11.1.4 Mode Pins The FLMD0 pin in combination with the P10_8: FLMD1 pin can select serial programming mode. The FLMD0 pin in combination with the P10_8: FLMD1, the P10_2: MODE1 and the P10_1: MODE0 pins can select boundary scan mode. The FLMD0 pin in combination with the P10_8: FLMD1, the P10_6: MODE2, the P10_2: MODE1 and the P10_1: MODE0 pins can select user boot mode. For details on the mode selection, see Section 6, Operating Mode. 2B.11.1.5 IP0_0: XT2 This pin is the SubOSC (SOSC) input pin. When the IPIBC0_0 bit = 1, the IP0_0/XT2 pin is used as an input port. If you make this setting, stop SOSC operation at the same time.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 402 of 4535 Dec 26, 2018 2B.11.2 A/D Input Alternative I/O The following ports are permanently connected to A/D input functions. (However, an analog input to the A/D is controlled by the A/D module.) Table 2B.79 A/D Input Alternative Pins Device Port A/D Input 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 403 of 4535 Dec 26, 2018 Table 2B.79 A/D Input Alternative Pins Device Port A/D Input 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 404 of 4535 Dec 26, 2018 2B.11.3 Special I/O Control 2B.11.3.1 Direct I/O Control (PIPC) Some alternative functions take over the input and output control of the ports. The following table lists all alternative functions where PIPCn.PIPCn_m must be set to 1. For details, see Section 2B.9.2.3, PIPCn — Port IP Control Register. Table 2B.80 Alternative Modes that Require Setting PIPCn.PIPCn_m = 1 Function Alternative functions Name Port Name Power Supply Area Control Reference Section MEMC MEMC0AD0 P10_6 ISO Section 16 MEMC0AD1 P10_7 ISO MEMC0AD2 P10_8 ISO MEMC0AD3 P10_9 ISO MEMC0AD4 P10_10 ISO MEMC0AD5 P10_11 ISO MEMC0AD6 P10_12 ISO MEMC0AD7 P10_13 ISO MEMC0AD8 P10_14 ISO MEMC0AD9 P11_1 ISO MEMC0AD10 P11_2 ISO MEMC0AD11 P11_3 ISO MEMC0AD12 P11_4 ISO MEMC0AD13 P11_5 ISO MEMC0AD14 P11_6 ISO MEMC0AD15 P11_7 ISO TAPA TAPA0UP P10_0 ISO U phase Hi-Z control Section 36 TAPA0UN P10_1 ISO TAPA0VP P10_2 ISO V phase Hi-Z control TAPA0VN P10_3 ISO TAPA0WP P10_4 ISO W phase Hi-Z control TAPA0WN P10_5 ISO CSIG CSIG0SO P0_13 AWO Serial data output control signal Section 19 P10_6 ISO CSIG0SC P0_14 AWO Master (1) / slave (0) mode signal P10_7 ISO CSIG1SO P11_9 ISO Serial data output control signal CSIG1SC P11_10 ISO Master (1) / slave (0) mode signal CSIG2SO P12_5 ISO Serial data output control signal CSIG2SC P12_4 ISO Master (1) / slave (0) mode signal CSIG3SO P20_1 ISO Serial data output control signal CSIG3SC P20_2 ISO Master (1) / slave (0) mode signal

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 405 of 4535 Dec 26, 2018 Table 2B.80 Alternative Modes that Require Setting PIPCn.PIPCn_m = 1 Function Alternative functions Name Port Name Power Supply Area Control Reference Section CSIH CSIH0SO P0_3 AWO Serial data output control signal Section 20 CSIH0SC P0_2 AWO Master (1) / slave (0) mode signal CSIH1SO P0_5 AWO Serial data output control signal P10_2 ISO CSIH1SC P0_6 AWO Master (1) / slave (0) mode signal P10_1 ISO CSIH2SO P11_2 ISO Serial data output control signal CSIH2SC P11_3 ISO Master (1) / slave (0) mode signal CSIH3SO P11_6 ISO Serial data output control signal CSIH3SC P11_7 ISO Master (1) / slave (0) mode signal SFMA SFMA0IO0 P11_5 ISO SPIch.0 MOSI0_IO00 output enable Section 17 SFMA0IO1 P11_4 ISO SPIch.0 MOSI0_IO10 output enable SFMA0IO2 P11_3 ISO SPIch.0 IO20 output enable SFMA0IO3 P11_2 ISO SPIch.0 IO30 output enable ETNB ETNB0MDIO P12_4 ISO MDIO output enable Section 26

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 406 of 4535 Dec 26, 2018 2B.11.3.2 Input Buffer Control (PISn/JPIS0, PISAn/JPISA0) The port input buffer characteristics (Type 1 or Type 2) of this device can be selected using the PISn/PISAn/JPIS0 register. The applicable pins are shown in the following table. The JTAG port input buffer characteristics (Type 1/2 or Type 5) of this device can be selected using the JPISA0 register. The applicable pins are shown in Table 2B.82, JTAG Port Input Buffer Characteristics Selection. Table 2B.81 Port Input Buffer Characteristics Selection Input Buffer Selection Device Port Name Type 1 (PISn_m = 0 & PISAn_m = 0) Type 2 (PISn_m = 1 & PISAn_m = 0) Type 5 (PISAn_m = 1) 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 407 of 4535 Dec 26, 2018 Table 2B.81 Port Input Buffer Characteristics Selection Input Buffer Selection Device Port Name Type 1 (PISn_m = 0 & PISAn_m = 0) Type 2 (PISn_m = 1 & PISAn_m = 0) Type 5 (PISAn_m = 1) 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins SHMT1 SHMT4 TTL — —    SHMT1 SHMT4 TTL — —   

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 408 of 4535 Dec 26, 2018 Table 2B.81 Port Input Buffer Characteristics Selection Input Buffer Selection Device Port Name Type 1 (PISn_m = 0 & PISAn_m = 0) Type 2 (PISn_m = 1 & PISAn_m = 0) Type 5 (PISAn_m = 1) 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins SHMT1 SHMT4 TTL — —    SHMT1 SHMT4 TTL — —    SHMT1 SHMT4 TTL — —    SHMT1 SHMT4 TTL — —    SHMT1 SHMT4 TTL — —    SHMT1 SHMT4 TTL — —    SHMT1 SHMT4 TTL — —    P12_4 SHMT1 SHMT4 TTL — —   

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 409 of 4535 Dec 26, 2018 Table 2B.81 Port Input Buffer Characteristics Selection Input Buffer Selection Device Port Name Type 1 (PISn_m = 0 & PISAn_m = 0) Type 2 (PISn_m = 1 & PISAn_m = 0) Type 5 (PISAn_m = 1) 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins P13_2 SHMT1 SHMT4 TTL — — —   P13_3 SHMT1 SHMT4 TTL — — —   P13_5 SHMT1 SHMT4 TTL — — —   SHMT1 SHMT4 TTL — —    P18_7 SHMT1 SHMT4 TTL — —    P18_8 SHMT1 SHMT4 TTL — — —   P18_9 SHMT1 SHMT4 TTL — — —  

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 410 of 4535 Dec 26, 2018 Table 2B.81 Port Input Buffer Characteristics Selection Input Buffer Selection Device Port Name Type 1 (PISn_m = 0 & PISAn_m = 0) Type 2 (PISn_m = 1 & PISAn_m = 0) Type 5 (PISAn_m = 1) 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins Table 2B.82 JTAG Port Input Buffer Characteristics Selection Input Buffer Selection Devices Port Name Type 1 (JPIS0_m = 0 & JPISA0_m = 0) Type 2 (JPIS0_m = 1 & JPISA0_m = 0) Type 5 (JPISA0_m = 1) 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins Note 1. TTL is selected for Boundary scan mode without JPISA0 register setting. Note 2. TTL is selected for Nexus in normal operating mode without JPISA0 register setting. Note 3. TTL is selected for LPD (4 pins) in normal operating mode without JPISA0 register setting. Note 4. TTL is selected for LPD (1 pin) in normal operating mode without JPISA0 register setting. NOTES 1. For the SHMT1, SHMT4 and TTL pin characteristics, see Section 47B, Electrical Characteristics of RH850/F1KM-S4. 2. For the input buffer after reset, Type 2 (SHMT4) is selected.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 411 of 4535 Dec 26, 2018 2B.11.3.3 Output Buffer Control (PDSC) The port output driver strength (slow mode/fast mode) can be selected using the PDSCn register. The applicable pins are shown in the following table. Only slow mode is supported for ports other than those listed below. Table 2B.83 Output Buffer Characteristics Selection Output Drive Strength Selection Device Port Name Slow Mode (PDSCn_m = 0) Fast Mode (PDSCn_m = 1) 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 412 of 4535 Dec 26, 2018 Table 2B.83 Output Buffer Characteristics Selection Output Drive Strength Selection Device Port Name Slow Mode (PDSCn_m = 0) Fast Mode (PDSCn_m = 1) 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins P10_10 10 MHz 40 MHz      P10_11 10 MHz 40 MHz      P10_12 10 MHz 40 MHz      P10_13 10 MHz 40 MHz      P10_14 10 MHz 40 MHz      P10_15 10 MHz 40 MHz —    

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 413 of 4535 Dec 26, 2018 Table 2B.83 Output Buffer Characteristics Selection Output Drive Strength Selection Device Port Name Slow Mode (PDSCn_m = 0) Fast Mode (PDSCn_m = 1) 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins P11_10 10 MHz 40 MHz ―     P11_11 10 MHz 40 MHz ―     P11_12 10 MHz 40 MHz ―     P11_15 10 MHz 40 MHz ―     P18_10 10 MHz 40 MHz ― ― ―   P18_11 10 MHz 40 MHz ― ― ―   P18_12 10 MHz 40 MHz ― ― ―   P18_13 10 MHz 40 MHz ― ― ―   P18_14 10 MHz 40 MHz ― ― ―   P18_15 10 MHz 40 MHz ― ― ―  

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 414 of 4535 Dec 26, 2018 Table 2B.83 Output Buffer Characteristics Selection Output Drive Strength Selection Device Port Name Slow Mode (PDSCn_m = 0) Fast Mode (PDSCn_m = 1) 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins P20_10 10 MHz 40 MHz ― ― ― ―  P20_11 10 MHz 40 MHz ― ― ― ―  P20_12 10 MHz 40 MHz ― ― ― ―  P20_13 10 MHz 40 MHz ― ― ― ―  P20_14 10 MHz 40 MHz ― ― ― ―  Note 1. Supports Cload: 100 pF (The load capacitance of CSIH0 is 100 pF.) Note 2. Supports Cload: 50 pF (The load capacitance of CSIH1 to CSIH3 are 50 pF.) Note 3. In some of the functions, Fast mode or Slow mode is specified. For details, see Section 47B.5, AC Characteristics.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 415 of 4535 Dec 26, 2018 2B.12 Noise Filter & Edge/Level Detector The input signals at some pins are passed through a filter to remove noise and glitches. The RH850/F1KM supports both analog and digital filters. It also supports the function for edge and level detection after the signals have passed t hrough a filter. The first part of this section provides an overview of port input pins that are equipped with a filter and the filter type, noise filter & edge/level detection control registers and control bits, and register addresses. For details on the digital/analog filter function and noise filter & edge/level detection control registers, see Section 2B.13, Description of Port Noise Filter & Edge/Level Detection. NOTE In this section, <name> in the noise filter control register represents the peripheral function connected to a filter. 2B.12.1 Port Filter Assignment A list of the input pins that incorporate an analog or digital filter is provided below. 2B.12.1.1 Input Pins that Incorporate Analog Filter Type A The input pins of analog filter type A incorporate an analog filter and edge/level detection function. Edge/level detection is controlled by the following registers.

• Filter control register FCLA0CTLm_<name> (m = 0 to 7) A dedicated FCLA0CTLm_<name> register is provided for each pin in a port that incorporates an analog filter. Table 2B.84 Input Pins that Incorporate Analog Filter Type A FCLA0CTL Register Configuration Device Module Name Input Pin Register Address 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins FCLA0 NMI FCLA0CTL0_NMI FFC3 4000H      INTP0 FCLA0CTL0_INTPL FFC3 4020H      INTP1 FCLA0CTL1_INTPL FFC3 4024H      INTP2 FCLA0CTL2_INTPL FFC3 4028H      INTP3 FCLA0CTL3_INTPL FFC3 402CH      INTP4 FCLA0CTL4_INTPL FFC3 4030H      INTP5 FCLA0CTL5_INTPL FFC3 4034H      INTP6 FCLA0CTL6_INTPL FFC3 4038H      INTP7 FCLA0CTL7_INTPL FFC3 403CH      INTP8 FCLA0CTL0_INTPH FFC3 4040H      INTP9 FCLA0CTL1_INTPH FFC3 4044H      INTP10 FCLA0CTL2_INTPH FFC3 4048H      INTP11 FCLA0CTL3_INTPH FFC3 404CH      INTP12 FCLA0CTL4_INTPH FFC3 4050H      INTP13 FCLA0CTL5_INTPH FFC3 4054H      INTP14 FCLA0CTL6_INTPH FFC3 4058H ―     INTP15 FCLA0CTL7_INTPH FFC3 405CH ―     INTP16 FCLA0CTL0_INTPU FFC3 40A0H ―     INTP17 FCLA0CTL1_INTPU FFC3 40A4H ―     INTP18 FCLA0CTL2_INTPU FFC3 40A8H ―     INTP19 FCLA0CTL3_INTPU FFC3 40ACH ―    

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 416 of 4535 Dec 26, 2018 Table 2B.84 Input Pins that Incorporate Analog Filter Type A FCLA0CTL Register Configuration Device Module Name Input Pin Register Address 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins FCLA0 INTP20 FCLA0CTL4_INTPU FFC3 40B0H ―     INTP21 FCLA0CTL5_INTPU FFC3 40B4H ―     INTP22 FCLA0CTL6_INTPU FFC3 40B8H ―     INTP23 FCLA0CTL7_INTPU FFC3 40BCH ―     2B.12.1.2 Input Pins that Incorporate Analog Filter Type B The input pins of analog filter type B incorporate an analog filter. Edge/level detection is controlled by the registers for individual peripheral functions. Table 2B.85 Input Pins that Incorporate Analog Filter Type B Device Input Pin Edge/Level Detection 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins TAUJ0I0 Edge detection*1      TAUJ0I1 Edge detection*1      TAUJ0I2 Edge detection*1      TAUJ0I3 Edge detection*1      TAUJ1I0 Edge detection*1      TAUJ1I1 Edge detection*1      TAUJ1I2 Edge detection*1      TAUJ1I3 Edge detection*1      TAUJ2I0 Edge detection*1      TAUJ2I1 Edge detection*1      TAUJ2I2 Edge detection*1      TAUJ2I3 Edge detection*1      TAUJ3I0 Edge detection*1      TAUJ3I1 Edge detection*1      TAUJ3I2 Edge detection*1      TAUJ3I3 Edge detection*1      TAPA0ESO Edge detection*2 ―     KR0I0 Low level detection      KR0I1 Low level detection      KR0I2 Low level detection      KR0I3 Low level detection      KR0I4 Low level detection      KR0I5 Low level detection      KR0I6 Low level detection      KR0I7 Low level detection      Note 2. For details on edge detection for TAPA, see Section 36.3.2, TAPAnCTL0 — TAPA Control Register 0.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 417 of 4535 Dec 26, 2018 2B.12.1.3 Input Pins that Incorporate Analog Filter Type C The input pins of analog filter type C only incorporate an analog filter function. Table 2B.86 Input Pins that Incorporate Analog Filter Type C Input Pin FLMD0 FLMD1 MODE0 MODE1 MODE2 RESET DCUTRST

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 418 of 4535 Dec 26, 2018 2B.12.1.4 Input Pins that Incorporate Digital Filter Type D The input pins of digital filter type D incorporate a digital filter and edge detection function. The digital filter and edge detection are controlled by the following registers.

• Filter control register FCLA0CTLm_<name> (m = 0 to 2) Each port with a digital filter has a special FCLA0CTLm_<name> register.
• Digital noise elimination control register DNFA<name>CTL Each DNFA<name>CTL control register controls digital filter processing for three input signals per group.
• Digital noise elimination enable register DNFA<name>EN The setting of the DNFA<name>ENL[2:0] bits in DNFA<name>EN enables or disables digital noise elimination for three input signals per group. Table 2B.87 Input Pins that Incorporate Digital Filter Type D Input Pin Device Digital Noise Elimination Control Register Digital Noise Elimination Enable Register Filter Control Register 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins Control Register Address Control Register Control Bit Address Control Register Address ADCA0TRG0      DNFAADCTL0CTL FFC3 00A0H DNFAADCTL0 EN (DNFAADCTL0 ENL) DNFAADCTL0ENL0 FFC3 00A4H (FFC3 00ACH) FCLA0CTL0 _ADC0 FFC3 4060H ADCA0TRG1      DNFAADCTL0ENL1 FCLA0CTL1 _ADC0 FFC3 4064H ADCA0TRG2      DNFAADCTL0ENL2 FCLA0CTL2 _ADC0 FFC3 4068H ADCA1TRG0 ―     DNFAADCTL1CTL FFC3 00C0H DNFAADCTL1 EN (DNFAADCTL1 ENL) DNFAADCTL1ENL0 FFC3 00C4 H (FFC3 00CCH) FCLA0CTL0 _ADC1 FFC3 4080H ADCA1TRG1 ―     DNFAADCTL1ENL1 FCLA0CTL1 _ADC1 FFC3 4084 H ADCA1TRG2 ―     DNFAADCTL1ENL2 FCLA0CTL2 _ADC1 FFC3 4088 H

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 419 of 4535 Dec 26, 2018 2B.12.1.5 Input Pins that Incorporate Digital Filter Type E The input pins of digital filter type E incorporate a digital filter. The digital filter is controlled by the following registers. Edge detection is controlled by the registers for individual peripheral functions.

• Digital noise elimination control register DNFA<name>CTL Each DNFA<name>CTL control register controls digital filter processing for up to 16 input signals per group.
• Digital noise elimination enable register DNFA<name>EN The setting of the DNFA<name>ENL[7:0] and DNFA<name>ENH[7:0] bits in DNFA<name>EN enables or disables digital noise elimination for up to 16 input signals per group. Table 2B.88 Input Pins that Incorporate Digital Filter Type E Devises Digital Noise Elimination Control Register Digital Noise Elimination Enable Register Edge Detection Input Pin 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins Control Register Address Control Register Control Bit Address Register Name TAUD0I0      DNFATAUD0I CTL FFC3 0000H DNFATAUD0IE N (DNFATAUD0IE NH/ DNFATAUD0IE NL) DNFATAUD0IENL0 FFC3 0004H (FFC3 0008H/ FFC3 000CH) TAUD0I1      DNFATAUD0IENL1 TAUD0I2      DNFATAUD0IENL2 TAUD0I3      DNFATAUD0IENL3 TAUD0I4      DNFATAUD0IENL4 TAUD0I5      DNFATAUD0IENL5 TAUD0I6      DNFATAUD0IENL6 TAUD0I7      DNFATAUD0IENL7 TAUD0I8      DNFATAUD0IENH0 TAUD0I9      DNFATAUD0IENH1 TAUD0I10      DNFATAUD0IENH2 TAUD0I11      DNFATAUD0IENH3 TAUD0I12      DNFATAUD0IENH4 TAUD0I13      DNFATAUD0IENH5 TAUD0I14      DNFATAUD0IENH6 TAUD0I15      DNFATAUD0IENH7 TAUB0I0      DNFATAUB0I CTL FFC3 0020H DNFATAUB0IE N (DNFATAUB0IE NH/ DNFATAUB0IE NL) DNFATAUB0IENL0 FFC3 0024H (FFC3 0028H/ FFC3 002CH) TAUB0I1      DNFATAUB0IENL1 TAUB0I2      DNFATAUB0IENL2 TAUB0I3      DNFATAUB0IENL3 TAUB0I4      DNFATAUB0IENL4 TAUB0I5      DNFATAUB0IENL5 TAUB0I6      DNFATAUB0IENL6 TAUB0I7      DNFATAUB0IENL7 TAUB0I8      DNFATAUB0IENH0 TAUB0I9 —     DNFATAUB0IENH1 TAUB0I10      DNFATAUB0IENH2 TAUB0I11 —     DNFATAUB0IENH3 TAUB0I12      DNFATAUB0IENH4 TAUB0I13      DNFATAUB0IENH5 TAUB0I14      DNFATAUB0IENH6 TAUB0I15      DNFATAUB0IENH7

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 420 of 4535 Dec 26, 2018 Table 2B.88 Input Pins that Incorporate Digital Filter Type E Devises Digital Noise Elimination Control Register Digital Noise Elimination Enable Register Edge Detection Input Pin 100 Pins 144 Pins 176 Pins 233 Pins 272 Pins Control Register Address Control Register Control Bit Address Register Name TAUB1I0 — —    DNFATAUB1I CTL FFC3 0040H DNFATAUB1IE N (DNFATAUB1IE NH/ DNFATAUB1IE NL) DNFATAUB1IENL0 FFC3 0044H (FFC3 0048H/ FFC3 004CH) TAUB1I1 — —    DNFATAUB1IENL1 TAUB1I2 — —    DNFATAUB1IENL2 TAUB1I3 — —    DNFATAUB1IENL3 TAUB1I4 — —    DNFATAUB1IENL4 TAUB1I5 — —    DNFATAUB1IENL5 TAUB1I6 — —    DNFATAUB1IENL6 TAUB1I7 — —    DNFATAUB1IENL7 TAUB1I8 — —    DNFATAUB1IENH0 TAUB1I9 — —    DNFATAUB1IENH1 TAUB1I10 — —    DNFATAUB1IENH2 TAUB1I11 — —    DNFATAUB1IENH3 TAUB1I12 — —    DNFATAUB1IENH4 TAUB1I13 — —    DNFATAUB1IENH5 TAUB1I14 — —    DNFATAUB1IENH6 TAUB1I15 — —    DNFATAUB1IENH7 ENCA0TIN0      DNFAENCA0I CTL FFC3 0060H DNFAENCA0IE N (DNFAENCA0IE NL) DNFAENCA0IENL0 FFC3 0064 H (FFC3 006CH) ENCA0TIN1      DNFAENCA0IENL1 ENCA0E0      DNFAENCA0IENL2 ENCA0E1      DNFAENCA0IENL3 ENCA0EC      DNFAENCA0IENL4 SENT0RX —     DNFASENTIC TL FFC3 00E0H DNFASENTIEN (DNFASENTIEN DNFASENTIENL0 FFC3 00E4H (FFC3 00ECH) —*4 SENT1RX      DNFASENTIENL1 Note 3. For the setting for ENCA edge detection, see Section 35.3.3, ENCAnIOC0 — ENCAn I/O Control Register 0. Note 4. RSENT does not have the edge detection.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 421 of 4535 Dec 26, 2018 2B.12.2 Clock Supply for Port Filters The following table shows the clock supply for each filter type in each port domain. Table 2B.89 Clock Supply for Port Filters Setting Register Peripheral Function Port Domain*1 Filter Type Filter Clock Source Clock Selection Clock Selection ADCA0 Always-On area (AWO area) Digital filter type D DNFATCKI CKSC_AADCAS_CTL CKSC_AADCAD_CTL ADCA1 Isolated area (ISO area) Digital filter type D DNFATCKI CKSC_IADCAS_CTL CKSC_IADCAD_CTL TAUD0 Isolated area (ISO area) Digital filter type E DNFATCKI CKSC_IPERI1S_CTL — TAUB0 Isolated area (ISO area) Digital filter type E DNFATCKI CKSC_IPERI2S_CTL — TAUB1 Isolated area (ISO area) Digital filter type E DNFATCKI CKSC_IPERI2S_CTL — ENCA0 Isolated area (ISO area) Digital filter type E DNFATCKI CKSC_IPERI1S_CTL — RSENTn Isolated area (ISO area) Digital filter type E DNFATCKI CKSC_IPERI2S_CTL — Note 1. Power Domain NOTE For the Setting Register, see Section 12AB.4.3, Clock Selector Control Register.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 422 of 4535 Dec 26, 2018 2B.13 Description of Port Noise Filter & Edge/Level Detection External signals pass through different types of filters according to the use of each external input signal. NOTE In this section, <name> in the noise filter control register represents the peripheral function connected to a filter. 2B.13.1 Overview 2B.13.1.1 Analog Filter Types Analog filters have fixed characteristics.

• Type A: An analog filter with edge detection or level detection. Used for external interrupt signals.
• Type B: An analog filter Edge detection is performed by each peripheral function. Used for the timer input signals, asynchronous Hi -Z control input signals, and key return input signals.
• Type C: An analog filter only Used for the external RESET input and mode signals. 2B.13.1.2 Digital Filter Types The digital filter characteristics can be adjusted to suit the application.
• Type D: A digital filter with edge detection. Used for the A/D converter external trigger pin.
• Type E: A digital filter. Edge detection is performed by each peripheral function. Used for the timer input signals and encoder input signals.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 423 of 4535 Dec 26, 2018 2B.13.2 Analog Filters 2B.13.2.1 Analog Filter Characteristic See Section 47B, Electrical Characteristics of RH850/F1KM-S4 for the input conditions for signals input to pins that incorporate an analog filter. 2B.13.2.2 Analog Filter Control Registers A dedicated FCLA0CTLm_<name> register or control register in the peripheral macro is provided for input pins that incorporate an analog filter. The assignment of the input signals to the control registers and their addresses are given in Table 2B.84, Input Pins that Incorporate Analog Filter Type A. 2B.13.2.3 Analog Filter in Standby Mode Analog filters for the function of waking-up from the DeepSTOP mode are located in the Always-On area (AWO area). Analog filters in the Always-On area (AWO area) always operate. The analog filter in standby mode and its wake-up capability depend on the filter types. See the description of the analog filter types below. (1) Analog Filter Type A A block diagram of analog filter type A is shown below. Analog filter FCLA0CTLm_<name>.FCLA0INTLm_<name> EMCLK Input signal INTC Level detector Edge detector Figure 2B.13 Block Diagram of Analog Filter Type A

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 424 of 4535 Dec 26, 2018 After passing an external signal through the filter to eliminate noise and glitches, an output signal is generated according to whether an event is detected; that is whether a specified level is detected or whether a change in the level (an edge) occurs. Whether a level or an edge is detected is selected by the control bit FCLA0CTLm_<name>.FCLA0INTLm_<name>.

• FCLA0INTLm_<name> bit = 0: Edge detection Whether a rising or falling edge is detected can be specified by setting the FCLA0CTLm_<name>.FCLA0INTRm_<name> and FCLA0CTLm_<name>.FCLA0INTFm_<name> bits.
• FCLA0INTLm_<name> bit = 1: Level detection The detection of a high level or low level can be specified by setting FCLA0CTLm_<name>.FCLA0INTRm_<name> bit. The table below summarizes the detection conditions of the analog filter. Table 2B.90 Analog Filter Event Detection Conditions FCLA0INTLm_<name> FCLA0INTFm_<name> FCLA0INTRm_<name> Edge Detection Level Detection 0 0 0 No edge detected Disabled 0 1 Rising edge 1 0 Falling edge 1 1 Rising and falling edges

Analog filter type A in Standby mode The output signal of an analog filter type A can always be used as a standby mode wake- up signal. (2) Analog filter type B A block diagram of analog filter type B is shown below. Analog filterInput signal Edge detection Peripheral function Figure 2B.14 Block Diagram of Analog Filter Type B Analog filter type B in Standby mode The output signal of an analog filter type B can always be used as a standby mode wake- up signal.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 425 of 4535 Dec 26, 2018 (3) Analog filter type C A block diagram of analog filter type C is shown below. Peripheral functionAnalog filterInput signal Figure 2B.15 Block Diagram of Analog Filter Type C The generated signals are always input signals that have passed through an analog filter. Analog filter type C in Standby mode Pins equipped with type C analog filters in this product do not support the input of event signals to trigger wake -up from standby.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 426 of 4535 Dec 26, 2018 2B.13.3 Digital Filters 2B.13.3.1 Digital Filter Characteristic The digital filters allow the filter characteristics to be adjusted accordingly to the needs of the application. The input signal is sampled with the sampling frequency fs. If a specified number of successive samples yield the same (high or low) level, the signal level is judged as valid and the filter output signal is set accordingly. If an external signal level change is detected within the specified number of samples (same level samples), the signal level is judged as noise and the filter output signal does not change. The length of an external signal pulse to be judged as noise depends on the sampling frequency and the specified number of same level samples. Both parameters can be specified:

• DNFA<name>CTL.DNFA<name>PRS[2:0] select the sampling frequency based on fs = fDNFATCKI / 2DNFA<name>PRS[2:0] where fDNFATCKI is the frequency of the DNFATCKI clock.
• DNFA<name>CTL.DNFA<name>NFSTS[1:0] determines the number of same level samples, “s”, (2 to 5): s = DNFA<name>NFSTS[1:0] + 2 External signal pulses shorter than the following are suppressed at all times. s ×1/fs External signal pulses longer than the following are always judged as valid and are passed on to the filter output. (s + 1) × 1/fs External signal pulses in the following range may be suppressed or judged as valid. s × 1/fs to (s + 1) × 1/fs The filter operation is illustrated in the figure below with DNFA<name>NFSTS[1:0] = 01B, i.e. s = 3 same level samples. Input signal Sampling points Digital filter output fs Figure 2B.16 Digital Filter Function

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 427 of 4535 Dec 26, 2018 2B.13.3.2 Digital Filter Groups The input signals processed through digital filters are ordered in groups of up to 16 signals. The digital filter characteristics, specified by DNFA<name>CTL.DNFA<name>PRS[2:0] and DNFA<name>NFSTS[1:0] apply to the signals. However, the digital filter for each signal can be enabled or disabled separately by DNFA<name>EN.DNFA<name>ENLm (m = 0 to 7) and DNFA<name>EN.DNFA<name>ENHm (m = 0 to 7). CAUTIONS 1. When the output signal from the digital filter is input to an alternative function, allow at least the following interval to elapse after the digital filter is enabled (DNFA<name>EN.DNFA<name>ENLm (m = 0 to 7) = 1 and DNFA<name>EN.DNFA<name>ENHm (m = 0 to 7) = 1) for the port pin to switch to the alternative function. s = DNFA<name>NFSTS[1:0] + 2 s × 1/fs + 2 × 1/fDNFATCKI 2. When a digital filterʼs output signal is used as an interrupt signal, only enable the digital filter (DNFA<name>EN.DNFA<name>ENLm (m = 0 to 7) = 1 and DNFA<name>EN.DNFA<name>ENHm (m = 0 to 7) = 1) while interrupts are disabled. Furthermore, only enable interrupts after enabling the digital filter, waiting for the time below to elapse, and then clearing the interrupt request flag. s × 1/fs + 3 × 1/fDNFATCKI 2B.13.3.3 Digital Filters in Standby Mode Digital filters for the function of waking-up from the DeepSTOP mode are located in the Always-On area (AWO area). Digital filters on the Always-On area (AWO area) are always operating. Digital noise elimination requires the clock supply DNFATCKI to operate. Pins equipped with digital filters in this product do not support the input of event signals to trigger wake -up from standby.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 428 of 4535 Dec 26, 2018 2B.13.3.4 Digital Filter Control Registers For each group consisting of up to 16 digital filters, the digital noise elimination control register DNFA< name>CTL and digital noise elimination enable register DNFA<name>EN are used to set all the filters in the same group (<name> = peripheral function group). The DNFA<name>CTL register specifies the characteristics of the digital noise elimination filter for the digital filter of <name>. The DNFA<name>EN register enables/disables each filter by setting the corresponding bit in DNFA<name>EN.DNFA<name>ENLm (m = 0 to 7) and DNFA<name>EN.DNFA<name>ENHm (m = 0 to 7). The edge detection setup is done via the filter dedicated control register and the registers for individual peripheral functions. The FCLA0CTLm_ADCn registers are ordered in groups of 3 registers with the same index n. The register index n is in 0 or 1. The assignment of the input signals to the control registers and their addresses are give n in Table 2B.87, Input Pins that Incorporate Digital Filter Type D and Table 2B.88, Input Pins that Incorporate Digital Filter Type E in Section 2B.12.1, Port Filter Assignment. CAUTION Do not change any control register settings while the corresponding digital filter is enabled by DNFA<name>EN.DNFA<name>ENLm (m = 0 to 7) = 1 and DNFA<name>EN.DNFA<name>ENHm (m = 0 to 7) = 1. Otherwise an unintended filter output may be generated. (1) Digital filter type D A block diagram of digital filter type D is shown below. Digital filter Peripheral function Prescaler fs Input signal DNFATCKI 1Edge detector “L” DNFA<name>EN.DNFA<name>ENLm Figure 2B.17 Block Diagram of Digital Filter Type D The generated signal depends on the register setting, as shown in the following table. Table 2B.91 Output Options for Digital Filter Type D DNFA<name>EN.DNFA<name>ENLm Signals Output to Peripheral Functions

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 429 of 4535 Dec 26, 2018 (2) Digital filter type E A block diagram of digital filter type E is shown below. Digital filter Edge detection Prescaler Input signal DNFATCKI DNFA<name>EN.DNFA<name>ENLm and DNFA<name>EN.DNFA<name>ENHm “L” Peripheral function fs Figure 2B.18 Block Diagram of Digital Filter Type E The generated signal depends on the register setting, as shown in the following table. Table 2B.92 Output Options for Digital Filter Type E DNFA<name>EN.DNFA<name>ENLm and DNFA<name>EN.DNFA<name>ENHm Signals Output to Peripheral Functions 2B.13.4 Filter Control Registers The analog and digital filters are controlled and operated by the following registers: Table 2B.93 List of Filter Registers Module Name Register Name Symbol Address FCLA0 Filter control register m FCLA0CTLm_<name> The addresses are shown in the tables in Section 2B.12.1, Port Filter Assignment. DNF Digital noise elimination control register DNFA<name>CTL Digital noise elimination enable register DNFA<name>EN Digital noise elimination enable H register DNFA<name>ENH Digital noise elimination enable L register DNFA<name>ENL

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 430 of 4535 Dec 26, 2018 2B.13.4.1 FCLA0CTLm_<name> — Filter Control Register This register controls the analog and digital filter operation. Access: This register can be read or written in 8-bit units. Address: The allocation of input signals to FCLA0CTLm_<name> registers and the address of each register are shown in the tables in Section 2B.12.1, Port Filter Assignment. Value after reset: 00H Bit 7 6 5 4 3 2 1 0 _<name> FCLA0INTFm _<name> FCLA0INTRm _<name> Value after reset 0 0 0 0 0 0 0 0 R/W R R R R R R/W R/W R/W Table 2B.94 FCLA0CTLm_<name> Register Contents Bit Position Bit Name Function 7 to 3 Reserved When read, the value after reset is returned. When writing, write the value after reset. _<name> Detection Mode Selection 0: Edge detection 1: Level detection NOTE: This bit is only valid for analog filter type A. _<name>

• In level detection mode (FCLA0INTLm_<name> = 1): This bit has no effect.
• In edge detection mode (FCLA0INTLm_<name> = 0): Falling edge detection control 0: Falling edge detection disabled 1: Falling edge detection enabled NOTE: This bit is only valid for analog filter type A and digital filter type D. However, digital filter type D is placed in edge detection mode.

_<name>

• In level detection mode (FCLA0INTLm_<name> = 1): Detected level selection 0: Low level detection 1: High level detection
• In edge detection mode (FCLA0INTLm_<name> = 0): Rising edge detection control 0: Rising edge detection disabled 1: Rising edge detection enabled NOTE: This bit is only valid for analog filter type A and digital filter type D. However, digital filter type D is placed in edge detection mode. CAUTION Digital filter type D: Always set bit 2 to “0”.

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 431 of 4535 Dec 26, 2018 2B.13.4.2 DNFA<name>CTL — Digital Noise Elimination Control Register This register is used to specify the filter characteristics of the digital noise elimination filter. NOTE This register is only valid for digital filter type D and digital filter type E. Access: This register can be read or written in 8-bit units. Address: For the correspondence between the DNFA<name>CTL register and input signals, and the addresses of individual registers, see Table 2B.87, Input Pins that Incorporate Digital Filter Type D and Table 2B.88, Input Pins that Incorporate Digital Filter Type E in Section 2B.12.1, Port Filter Assignment. Value after reset: 00H Bit 7 6 5 4 3 2 1 0 — DNFA<name>NFSTS[1:0] — — DNFA<name>PRS[2:0] Value after reset 0 0 0 0 0 0 0 0 R/W R R/W R/W R R R/W R/W R/W Table 2B.95 DNFA<name>CTL Register Contents Bit Position Bit Name Function 7 Reserved When read, the value after reset is returned. When writing, write the value after reset. 6, 5 DNFA<name> NFSTS[1:0] The DNFA<name>NFSTS[1:0] bits specify the number of samples used to judge whether an external signal pulse is valid. DNFA<name>NFSTS[1:0] Number of Samples 00B 2 01B 3 10B 4 11B 5 4, 3 Reserved When read, the value after reset is returned. When writing, write the value after reset. 2 to 0 DNFA<name> PRS[2:0] Digital filter sampling clock selection DNFA<name>PRS[2:0] Sampling Clock Frequency 000B DNFATCKI/1 001B DNFATCKI/2 010B DNFATCKI/4 011B DNFATCKI/8 100B DNFATCKI/16 101B DNFATCKI/32 110B DNFATCKI/64 111B DNFATCKI/128

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 432 of 4535 Dec 26, 2018 2B.13.4.3 DNFA<name>EN — Digital Noise Elimination Enable Register This register enables and disables digital noise elimination for a specified input signal. NOTE This register is only valid for digital filter type D and digital filter type E. Access: This register can be read or written in 16-bit units. The upper- and lower-order bytes (DNFA<name>ENH[7:0] and DNFA<name>ENL[7:0]) are accessible in 8- or 1-bit units respectively by setting DNFA<name>ENH. and DNFA<name>ENL. Address: For the correspondence between the DNFA<name>EN register and input signals, and the addresses of individual registers, see Table 2B.87, Input Pins that Incorporate Digital Filter Type D and Table 2B.88, Input Pins that Incorporate Digital Filter Type E in Section 2B.12.1, Port Filter Assignment. Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DNFA <name> ENH7 DNFA <name> ENH6 DNFA <name> ENH5 DNFA <name> ENH4 DNFA <name> ENH3 DNFA <name> ENH2 DNFA <name> ENH1 DNFA <name> ENH0 DNFA <name> ENL7 DNFA <name> ENL6 DNFA <name> ENL5 DNFA <name> ENL4 DNFA <name> ENL3 DNFA <name> ENL2 DNFA <name> ENL1 DNFA <name> ENL0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Table 2B.96 DNFA<name>EN Register Contents Bit Position Bit Name Function 15 to 0 DNFA<name> ENH[7:0] DNFA<name> ENL[7:0] Digital Noise Elimination Enable/Disable Control 0: Fixed to low level 1: Input signal passed through filter

RH850/F1KH, RH850/F1KM Section 2B Pin Function of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 433 of 4535 Dec 26, 2018 2B.13.4.4 DNFA<name>ENH – Digital Noise Elimination Enable H Register Setting in this register correspond to those of the 8 upper-order bits of the DNFA<name>EN register. NOTE This register is only valid for digital filter type E. Access: This register can be read or written in 8-bit or 1-bit units. Address: For the correspondence between the DNFA<name>ENH register and input signals, and the addresses of individual registers, see Table 2B.88, Input Pins that Incorporate Digital Filter Type E in Section 2B.12.1, Port Filter Assignment. Value after reset: 00H Bit 7 6 5 4 3 2 1 0 DNFA<name> ENH7 DNFA<name> ENH6 DNFA<name> ENH5 DNFA<name> ENH4 DNFA<name> ENH3 DNFA<name> ENH2 DNFA<name> ENH1 DNFA<name> ENH0 Value after reset 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W For details of the respective bit functions, see Section 2B.13.4.3, DNFA<name>EN — Digital Noise Elimination Enable Register. 2B.13.4.5 DNFA<name>ENL – Digital Noise Elimination Enable L Register Setting in this register correspond to those of the 8 lower-order bits of the DNFA<name>EN register. NOTE This register is only valid for digital filter type D and digital filter type E. Access: This register can be read or written in 8-bit or 1-bit units. Address: For the correspondence between the DNFA<name>ENL register and input signals, and the addresses of individual registers, see Table 2B.87, Input Pins that Incorporate Digital Filter Type D and Table 2B.88, Input Pins that Incorporate Digital Filter Type E in Section 2B.12.1, Port Filter Assignment. Value after reset: 00H Bit 7 6 5 4 3 2 1 0 DNFA<name> ENL7 DNFA<name> ENL6 DNFA<name> ENL5 DNFA<name> ENL4 DNFA<name> ENL3 DNFA<name> ENL2 DNFA<name> ENL1 DNFA<name> ENL0 Value after reset 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W For details of the respective bit functions, see Section 2B.13.4.3, DNFA<name>EN — Digital Noise Elimination Enable Register.

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 434 of 4535 Dec 26, 2018 Section 2C Pin Function of RH850/F1KM-S1 This section describes the pin and port functions. Section 2C.1, Pin Connection Diagram to Section 2C.5, Recommended Connection of Unused Pins describe the pin connections and respective pins. Section 2C.6, Features of RH850/F1KM Port to Section 2C.13, Description of Port Noise Filter & Edge/Level Detection describe the general port functions. 2C.1 Pin Connection Diagram JP0_2 JP0_1 JP0_0 RESET AWOVSS AWOVCL REGVCC FLMD0 P8_0 P8_1 P9_1 P9_0 AP0_0 AP0_1 AP0_2 AP0_3 AP0_4 AP0_5 AP0_6 AP0_7 A0VREF A0VSS P10_2 P10_1 P10_0 EVSS EVCC P10_10 P10_9 P10_8 P10_7 P10_6 ISOVSS ISOVCL P10_3 P10_4 P10_5 P0_0 P0_1 P0_2 P0_3 EVCC EVSS JP0_5 JP0_4 JP0_3 Figure 2C.1 Pin Connection Diagram (48-Pin LQFP)

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 436 of 4535 Dec 26, 2018 JP0_2 JP0_1 JP0_0 RESET EVCC AWOVSS AWOVCL REGVCC FLMD0 P0_10 P0_9 P0_8 P0_7 EVSS P8_0 P8_1 P8_3 P8_4 P8_5 P8_6 P8_7 P8_8 P8_9 P9_6 P9_5 P9_4 P9_3 P9_2 P9_1 P9_0 AP0_0 AP0_1 AP0_2 AP0_3 AP0_4 AP0_5 AP0_6 AP0_7 AP0_8 AP0_9 AP0_10 AP0_11 AP0_12 AP0_13 AP0_14 AP0_15 A0VREF A0VSS 100 P10_2 P10_1 P10_0 EVSS EVCC P11_7 P11_6 P11_5 P11_4 P11_3 P11_2 P11_1 P10_14 P10_13 P10_12 P10_11 P10_10 P10_9 P10_8 P10_7 P10_6 EVSS ISOVSS ISOVCL EVCC P10_3 P10_4 P10_5 P10_15 P11_0 P0_0 P0_1 P0_2 P0_3 EVCC P0_4 P0_5 P0_6 P0_11 P0_12 P0_13 P0_14 EVSS P8_2 P8_10 P8_11 P8_12 JP0_5 JP0_4 JP0_3 Figure 2C.4 Pin Connection Diagram (100-Pin LQFP)

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 437 of 4535 Dec 26, 2018 Table 2C.1 Pin Assignment 48-Pin LQFP Pin No. Pin Name

1 P10_3 / TAUD0I7 / TAUD0O7 / RIIC0SCL / KR0I1 / PWGA3O / ADCA0TRG1 / TAPA0VN

2 P10_4 / TAUD0I9 / TAUD0O9 / RLIN21RX / KR0I2 / ADCA0SEL0 / ADCA0TRG2 / TAPA0WP / CSIG0SSI

3 P10_5 / TAUD0I11 / TAUD0O11 / RLIN21TX / KR0I3 / ADCA0SEL1 / TAPA0WN / CSIG0RYI / CSIG0RYO

4 P0_0 / TAUD0I2 / TAUD0O2 / RLIN20RX / CAN0TX / PWGA10O / CSIH0SSI / DPO / TAUJ2I1 / TAUJ2O1

5 P0_1 / TAUD0I4 / TAUD0O4 / CAN0RX / INTP0 / RLIN20TX / PWGA11O / CSIH0SI / APO / TAUJ2I2 / TAUJ2O2

6 P0_2 / TAUD0I6 / TAUD0O6 / INTP1 / RLIN30TX / PWGA12O / CSIH0SC / DPO / TAUJ2I3 / TAUJ2O3

7 P0_3 / TAUD0I8 / TAUD0O8 / RLIN30RX / INTP10 / DPIN1 / CSIH0SO / TAUJ1I0 / TAUJ1O0

8 EVCC

9 EVSS

10 JP0_5 / NMI / RTCA0OUT / TAUJ0I3 / TAUJ0O3 / DCURDY / LPDCLKOUT

11 JP0_4 / DCUTRST

12 JP0_3 / INTP3 / CSCXFOUT / TAUJ0I2 / TAUJ0O2 / DCUTMS

13 JP0_2 / INTP2 / TAUJ0I1 / TAUJ0O1 / FPCK / DCUTCK / LPDCLK

14 JP0_1 / INTP1 / TAUJ0I0 / TAUJ0O0 / FPDT / DCUTDO / LPDO

15 JP0_0 / INTP0 / FPDR / FPDT / TAUJ2I0 / TAUJ2O0 / DCUTDI / LPDI/ LPDIO

16 RESET

17 AWOVSS

18 AWOVCL

19 REGVCC

22 FLMD0

23 P8_0 / TAUJ0I0 / TAUJ0O0 / DPIN2 / INTP4 / CSIH0CSS0 / SENT0RX / ADCA0I0S / RIIC1SDA

24 P8_1 / TAPA0ESO / TAUJ0O1 / DPIN0 / INTP5 / SENT0SPCO / ADCA0I1S / RIIC1SCL

25 A0VSS

26 A0VREF

27 AP0_7 / ADCA0I7

28 AP0_6 / ADCA0I6

29 AP0_5 / ADCA0I5

30 AP0_4 / ADCA0I4

31 AP0_3 / ADCA0I3

32 AP0_2 / ADCA0I2

33 AP0_1 / ADCA0I1

34 AP0_0 / ADCA0I0

35 P9_0 / NMI / PWGA8O / TAUD0I0 / TAUD0O0 / ADCA0TRG0 / KR0I4 / TAUJ1I1 / TAUJ1O1 / SENT1RX / ADCA0I2S / RIIC1SDA 36 P9_1 / INTP11 / PWGA9O / TAUD0I2 / TAUD0O2 / KR0I5 / TAUJ1I2 / TAUJ1O2 / SENT1SPCO / ADCA0I3S / RIIC1SCL

37 ISOVCL

38 ISOVSS

39 P10_6 / TAUD0I13 / TAUD0O13 / CSIG0SO / ENCA0TIN0 / ADCA0SEL2 / MODE2

40 P10_7 / TAUD0I15 / TAUD0O15 / CSIG0SC / ENCA0TIN1 / PWGA4O / TAUJ3I1 / TAUJ3O1

41 P10_8 / TAUD0I10 / TAUD0O10 / CSIG0SI / ENCA0EC / PWGA5O / TAUJ3I2 / TAUJ3O2 / FLMD1

42 P10_9 / TAUD0I12 / TAUD0O12 / RLIN30RX / INTP10 / ENCA0E0 / PWGA6O / CSIH0RYI / CSIH0RYO

43 P10_10 / TAUD0I14 / TAUD0O14 / RLIN30TX / ENCA0E1 / PWGA7O / CSIH0CSS1 / TAUJ3I3 / TAUJ3O3

44 EVCC

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 438 of 4535 Dec 26, 2018 Table 2C.1 Pin Assignment 48-Pin LQFP Pin No. Pin Name

45 EVSS

46 P10_0 / TAUD0I1 / TAUD0O1 / CAN0RX / INTP0 / CSCXFOUT / PWGA0O / TAUJ1I3 / TAPA0UP / TAUJ1O3

47 P10_1 / TAUD0I3 / TAUD0O3 / CAN0TX / PWGA1O / TAUJ3I0 / TAPA0UN / TAUJ3O0 / MODE0

48 P10_2 / TAUD0I5 / TAUD0O5 / RIIC0SDA / KR0I0 / PWGA2O / ADCA0TRG0 / TAPA0VP /MODE1

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 439 of 4535 Dec 26, 2018 Table 2C.2 Pin Assignment 64-Pin LQFP Pin No. Pin Name

6 P0_2 / TAUD0I6 / TAUD0O6 / CAN1RX / INTP1 / RLIN30TX / PWGA12O / CSIH0SC / DPO / TAUJ2I3 / TAUJ2O3

7 P0_3 / TAUD0I8 / TAUD0O8 / RLIN30RX / INTP10 / CAN1TX / DPIN1 / PWGA13O / CSIH0SO / TAUJ1I0 / TAUJ1O0

9 P0_4 / RLIN31RX / INTP11 / CAN2TX / PWGA10O / SELDP0 / DPIN8

10 P0_5 / CAN2RX / INTP2 / RLIN31TX / DPIN9 / SELDP1

11 P0_6 / INTP2 / DPIN10 / SELDP2

12 EVSS

13 P8_2 / TAUJ0I0 / TAUJ0O0 / DPIN2 / CSIH0CSS0 / PWGA22O / ADCA0I4S

14 JP0_5 / NMI / RTCA0OUT / TAUJ0I3 / TAUJ0O3 / DCURDY / LPDCLKOUT

15 JP0_4 / DCUTRST

16 JP0_3 / INTP3 / CSCXFOUT / TAUJ0I2 / TAUJ0O2 / DCUTMS

17 JP0_2 / INTP2 / TAUJ0I1 / TAUJ0O1 / FPCK / DCUTCK / LPDCLK

18 JP0_1 / INTP1 / TAUJ0I0 / TAUJ0O0 / FPDT / DCUTDO / LPDO

19 JP0_0 / INTP0 / FPDR / FPDT / TAUJ2I0 / TAUJ2O0 / DCUTDI / LPDI/ LPDIO

20 RESET

21 AWOVSS

22 AWOVCL

23 REGVCC

26 FLMD0

27 P8_0 / TAUJ0I0 / TAUJ0O0 / DPIN2 / PWGA14O / INTP4 / CSIH0CSS0 / SENT0RX / ADCA0I0S / RIIC1SDA

28 P8_1 / TAPA0ESO / TAUJ0O1 / DPIN0 / PWGA15O / INTP5 / SENT0SPCO / ADCA0I1S / RIIC1SCL

29 P8_3 / TAUJ0I1 / TAUJ0O1 / DPIN3 / CSIH0CSS1 / PWGA23O / ADCA0I5S

30 P8_4 / TAUJ0I2 / TAUJ0O2 / DPIN4 / CSIH0CSS2 / ADCA0I6S

31 P8_5 / TAUJ0I3 / TAUJ0O3 / NMI / CSIH0CSS3 / ADCA0I7S

32 P8_6 / NMI / RTCA0OUT / ADCA0I8S / RESETOUT

33 A0VSS

34 A0VREF

35 AP0_9 / ADCA0I9

36 AP0_8 / ADCA0I8

37 AP0_7 / ADCA0I7

38 AP0_6 / ADCA0I6

39 AP0_5 / ADCA0I5

40 AP0_4 / ADCA0I4

41 AP0_3 / ADCA0I3

42 AP0_2 / ADCA0I2

43 AP0_1 / ADCA0I1

44 AP0_0 / ADCA0I0

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 440 of 4535 Dec 26, 2018 Table 2C.2 Pin Assignment 64-Pin LQFP Pin No. Pin Name 45 P9_0 / NMI / PWGA8O / TAUD0I0 / TAUD0O0 / ADCA0TRG0 / KR0I4 / TAUJ1I1 / TAUJ1O1 / SENT1RX / ADCA0I2S / RIIC1SDA 46 P9_1 / INTP11 / PWGA9O / TAUD0I2 / TAUD0O2 / KR0I5 / TAUJ1I2 / TAUJ1O2 / SENT1SPCO / ADCA0I3S / RIIC1SCL

47 P9_2 / KR0I6 / PWGA20O / TAPA0ESO / ADCA0I9S

48 P9_3 / KR0I7 / PWGA21O / TAUJ1I1 / TAUJ1O1 / ADCA0I10S

49 ISOVCL

50 ISOVSS

51 P10_6 / TAUD0I13 / TAUD0O13 / CSIG0SO / ENCA0TIN0 / ADCA0SEL2 / CAN1RX / INTP1 / MODE2

52 P10_7 / TAUD0I15 / TAUD0O15 / CSIG0SC / ENCA0TIN1 / PWGA4O / CAN1TX / TAUJ3I1 / TAUJ3O1

53 P10_8 / TAUD0I10 / TAUD0O10 / CSIG0SI / ENCA0EC / PWGA5O / TAUJ3I2 / TAUJ3O2 / FLMD1

54 P10_9 / TAUD0I12 / TAUD0O12 / RLIN30RX / INTP10 / ENCA0E0 / PWGA6O / CSIH0RYI / CSIH0RYO

55 P10_10 / TAUD0I14 / TAUD0O14 / RLIN30TX / ENCA0E1 / PWGA7O / CSIH0CSS1 / TAUJ3I3 / TAUJ3O3

56 P10_11 / PWGA16O / RLIN31RX / INTP11

57 P10_12 / PWGA17O / RLIN31TX

58 P10_13 / CSIH0SSI / PWGA18O

59 P10_14 / PWGA19O

60 EVCC

61 EVSS

62 P10_0 / TAUD0I1 / TAUD0O1 / CAN0RX / INTP0 / CSCXFOUT / PWGA0O / TAUJ1I3 / TAPA0UP / TAUJ1O3

63 P10_1 / TAUD0I3 / TAUD0O3 / CAN0TX / PWGA1O / TAUJ3I0 / TAPA0UN / TAUJ3O0 / MODE0

64 P10_2 / TAUD0I5 / TAUD0O5 / RIIC0SDA / KR0I0 / PWGA2O / ADCA0TRG0 / TAPA0VP /MODE1

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 441 of 4535 Dec 26, 2018 Table 2C.3 Pin Assignment 80-Pin LQFP Pin No. Pin Name

4 P10_15 / TAUB0I9 / TAUB0O9

5 P11_0 / CSIH2RYI / CSIH2RYO / TAUB0I11 / TAUB0O11

13 P0_6 / INTP2 / DPIN10 / SELDP2 / CSIH1SC

14 P0_11 / RIIC0SDA / CSIH1CSS2 / TAUB0I8 / TAUB0O8

15 P0_12 / RIIC0SCL / TAUB0I10 / TAUB0O10 / CSIG0SI

16 EVSS

17 P8_2 / TAUJ0I0 / TAUJ0O0 / DPIN2 / CSIH0CSS0 / INTP6 / PWGA22O / ADCA0I4S

18 JP0_5 / NMI / RTCA0OUT / TAUJ0I3 / TAUJ0O3 / DCURDY / LPDCLKOUT

19 JP0_4 / DCUTRST

20 JP0_3 / INTP3 / CSCXFOUT / TAUJ0I2 / TAUJ0O2 / DCUTMS

21 JP0_2 / INTP2 / TAUJ0I1 / TAUJ0O1 / FPCK / DCUTCK / LPDCLK

22 JP0_1 / INTP1 / TAUJ0I0 / TAUJ0O0 / FPDT / DCUTDO / LPDO

23 JP0_0 / INTP0 / FPDR / FPDT / TAUJ2I0 / TAUJ2O0 / DCUTDI / LPDI/ LPDIO

24 RESET

25 AWOVSS

26 AWOVCL

27 REGVCC

30 FLMD0

31 P0_10 / INTP3 / CSIH1CSS1 / DPIN11 / TAUB0I6 / TAUB0O6

32 P0_9 / INTP12 / CSIH1CSS0 / DPIN7 / TAUB0I4 / TAUB0O4

33 P0_8 / RLIN21TX / DPIN6 / CSIH0CSS6 / CSIH1SSI / TAUB0I2 / TAUB0O2

34 P0_7 / RLIN21RX / DPIN5 / CSCXFOUT / CSIH1RYI / CSIH1RYO / TAUB0I0 / TAUB0O0

35 P8_0 / TAUJ0I0 / TAUJ0O0 / DPIN2 / PWGA14O / INTP4 / CSIH0CSS0 / SENT0RX / ADCA0I0S / RIIC1SDA

36 P8_1 / TAPA0ESO / TAUJ0O1 / DPIN0 / PWGA15O / INTP5 / CSIH1CSS3 / SENT0SPCO / ADCA0I1S / RIIC1SCL

37 P8_3 / TAUJ0I1 / TAUJ0O1 / DPIN3 / CSIH0CSS1 / INTP7 / PWGA23O / ADCA0I5S

38 P8_4 / TAUJ0I2 / TAUJ0O2 / DPIN4 / CSIH0CSS2 / INTP8 / ADCA0I6S

39 P8_5 / TAUJ0I3 / TAUJ0O3 / NMI / CSIH0CSS3 / ADCA0I7S

40 P8_6 / NMI / CSIH0CSS4 / RTCA0OUT / ADCA0I8S / RESETOUT

41 A0VSS

42 A0VREF

43 AP0_10 / ADCA0I10

44 AP0_9 / ADCA0I9

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 442 of 4535 Dec 26, 2018 Table 2C.3 Pin Assignment 80-Pin LQFP Pin No. Pin Name

45 AP0_8 / ADCA0I8

46 AP0_7 / ADCA0I7

47 AP0_6 / ADCA0I6

48 AP0_5 / ADCA0I5

49 AP0_4 / ADCA0I4

50 AP0_3 / ADCA0I3

51 AP0_2 / ADCA0I2

52 AP0_1 / ADCA0I1

53 AP0_0 / ADCA0I0

54 P9_0 / NMI / PWGA8O / TAUD0I0 / TAUD0O0 / ADCA0TRG0 / CSIH2CSS0 / KR0I4 / TAUJ1I1 / TAUJ1O1 / SENT1RX / ADCA0I2S / RIIC1SDA

55 P9_1 / INTP11 / PWGA9O / TAUD0I2 / TAUD0O2 / KR0I5 / CSIH2CSS1 / TAUJ1I2 / TAUJ1O2 / SENT1SPCO /

56 P9_2 / KR0I6 / PWGA20O / TAPA0ESO / CSIH2CSS2 / ADCA0I9S

57 P9_3 / KR0I7 / PWGA21O / CSIH2CSS3 / TAUJ1I1 / TAUJ1O1 / ADCA0I10S

58 P9_4 / CSIH0CSS5 / TAUJ1I0 / TAUJ1O0 / ADCA0I11S

59 P9_5 / CSIH0CSS6 / TAUJ1I1 / TAUJ1O1 / ADCA0I12S

60 P9_6 / CSIH0CSS7 / ADCA0I13S

62 ISOVSS

63 P10_6 / TAUD0I13 / TAUD0O13 / CSIG0SO / ENCA0TIN0 / ADCA0SEL2 / CAN1RX / INTP1 / MODE2

64 P10_7 / TAUD0I15 / TAUD0O15 / CSIG0SC / ENCA0TIN1 / PWGA4O / CAN1TX / TAUJ3I1 / TAUJ3O1

65 P10_8 / TAUD0I10 / TAUD0O10 / CSIG0SI / ENCA0EC / PWGA5O / TAUJ3I2 / TAUJ3O2 / FLMD1

66 P10_9 / TAUD0I12 / TAUD0O12 / RLIN30RX / INTP10 / ENCA0E0 / PWGA6O / CSIH0RYI / CSIH0RYO

67 P10_10 / TAUD0I14 / TAUD0O14 / RLIN30TX / ENCA0E1 / PWGA7O / CSIH0CSS1 / TAUJ3I3 / TAUJ3O3

68 P10_11 / PWGA16O / RLIN31RX / INTP11 / CSIH1CSS0 / TAUB0I1 / TAUB0O1

69 P10_12 / PWGA17O / RLIN31TX / CSIH1CSS1 / TAUB0I3 / TAUB0O3

70 P10_13 / CSIH0SSI / PWGA18O / RLIN32RX / INTP12 / TAUB0I5 / TAUB0O5

71 P10_14 / PWGA19O / RLIN32TX / TAUB0I7 / TAUB0O7

72 P11_1 / CSIH2SSI / RLIN20RX / CSIH0CSS7 / TAUB0I13 / TAUB0O13

73 P11_2 / CSIH2SO / RLIN32RX / INTP12 / RLIN20TX / TAUB0I15 / TAUB0O15

74 P11_3 / CSIH2SC / RLIN32TX

75 P11_4 / CSIH2SI

77 EVSS

78 P10_0 / TAUD0I1 / TAUD0O1 / CAN0RX / INTP0 / CSCXFOUT / PWGA0O / TAUJ1I3 / TAPA0UP / CSIH1SI / TAUJ1O3

79 P10_1 / TAUD0I3 / TAUD0O3 / CAN0TX / PWGA1O / TAUJ3I0 / TAPA0UN / CSIH1SC / TAUJ3O0 / MODE0

80 P10_2 / TAUD0I5 / TAUD0O5 / RIIC0SDA / KR0I0 / PWGA2O / ADCA0TRG0 / TAPA0VP / CSIH1SO / MODE1

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 443 of 4535 Dec 26, 2018 Table 2C.4 Pin Assignment 100-Pin LQFP Pin No. Pin Name

5 P11_0 / CSIH2RYI / CSIH2RYO / PWGA25O / RLIN22TX / TAUB0I11 / TAUB0O11

16 P0_13 / RLIN32RX / INTP12 / PWGA46O / TAUB0I12 / TAUB0O12 / CSIG0SO / CAN5RX / INTP5

17 P0_14 / RLIN32TX / PWGA47O / TAUB0I14 / TAUB0O14 / CSIG0SC / CAN5TX

20 P8_10 / CSIH3CSS3 / DPIN14 / PWGA42O / ADCA0I17S

21 P8_11 / TAUJ1I2 / TAUJ1O2 / DPIN15 / PWGA43O / CSIH1CSS4 / ADCA0I18S

22 P8_12 / TAUJ1I3 / TAUJ1O3 / DPIN16 / PWGA44O / CSIH1CSS5 / ADCA0I19S

23 JP0_5 / NMI / RTCA0OUT / TAUJ0I3 / TAUJ0O3 / DCURDY / LPDCLKOUT

25 JP0_3 / INTP3 / CSCXFOUT / TAUJ0I2 / TAUJ0O2 / DCUTMS

28 JP0_0 / INTP0 / FPDR / FPDT / TAUJ2I0 / TAUJ2O0 / DCUTDI / LPDI/ LPDIO

39 P0_8 / RLIN21TX / DPIN6 / CSIH0CSS6 / CSIH1SSI / TAUB0I2 / TAUB0O2 / CAN3TX

42 P8_0 / TAUJ0I0 / TAUJ0O0 / DPIN2 / PWGA14O / INTP4 / CSIH0CSS0 / SENT0RX / ADCA0I0S / RIIC1SDA

43 P8_1 / TAPA0ESO / TAUJ0O1 / DPIN0 / PWGA15O / INTP5 / CSIH1CSS3 / SENT0SPCO / ADCA0I1S / RIIC1SCL

44 P8_3 / TAUJ0I1 / TAUJ0O1 / DPIN3 / CSIH0CSS1 / INTP7 / PWGA23O / ADCA0I5S

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 444 of 4535 Dec 26, 2018 Table 2C.4 Pin Assignment 100-Pin LQFP Pin No. Pin Name

45 P8_4 / TAUJ0I2 / TAUJ0O2 / DPIN4 / CSIH0CSS2 / INTP8 / PWGA36O / ADCA0I6S

46 P8_5 / TAUJ0I3 / TAUJ0O3 / NMI / CSIH0CSS3 / PWGA37O / ADCA0I7S

48 P8_7 / CSIH3CSS0 / PWGA39O / ADCA0SEL0 / RTCA0OUT / ADCA0I14S

49 P8_8 / CSIH3CSS1 / PWGA40O / ADCA0SEL1 / ADCA0I15S

50 P8_9 / CSIH3CSS2 / PWGA41O / ADCA0SEL2 / ADCA0I16S

69 P9_0 / NMI / PWGA8O / TAUD0I0 / TAUD0O0 / ADCA0TRG0 / CSIH2CSS0 / KR0I4 / TAUJ1I1 / TAUJ1O1 / SENT1RX / ADCA0I2S / RIIC1SDA

74 P9_5 / CSIH0CSS6 / PWGA34O / TAUJ1I1 / TAUJ1O1 / ADCA0I12S

75 P9_6 / CSIH0CSS7 / PWGA35O / ADCA0I13S

82 P10_8 / TAUD0I10 / TAUD0O10 / CSIG0SI / ENCA0EC / PWGA5O / TAUJ3I2 / TAUJ3O2 / FLMD1

83 P10_9 / TAUD0I12 / TAUD0O12 / RLIN30RX / INTP10 / ENCA0E0 / PWGA6O / CSIH0RYI / CSIH0RYO

85 P10_11 / PWGA16O / RLIN31RX / INTP11 / CSIH1CSS0 / TAUB0I1 / TAUB0O1

86 P10_12 / PWGA17O / RLIN31TX / CSIH1CSS1 / TAUB0I3 / TAUB0O3

87 P10_13 / CSIH0SSI / PWGA18O / RLIN32RX / INTP12 / TAUB0I5 / TAUB0O5

88 P10_14 / PWGA19O / RLIN32TX / CSIH3SSI / TAUB0I7 / TAUB0O7

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 445 of 4535 Dec 26, 2018 Table 2C.4 Pin Assignment 100-Pin LQFP Pin No. Pin Name

89 P11_1 / CSIH2SSI / RLIN20RX / CSIH0CSS7 / PWGA26O / TAUB0I13 / TAUB0O13

90 P11_2 / CSIH2SO / RLIN32RX / INTP12 / RLIN20TX / PWGA27O / TAUB0I15 / TAUB0O15

93 P11_5 / CAN5RX / INTP5 / RLIN33TX / PWGA30O / CSIH3SI

94 P11_6 / RLIN33RX / INTP13 / CAN5TX / PWGA31O / CSIH3SO

98 P10_0 / TAUD0I1 / TAUD0O1 / CAN0RX / INTP0 / CSCXFOUT / PWGA0O / TAUJ1I3 / TAPA0UP / CSIH1SI / TAUJ1O3

99 P10_1 / TAUD0I3 / TAUD0O3 / CAN0TX / PWGA1O / TAUJ3I0 / TAPA0UN / CSIH1SC / TAUJ3O0 / MODE0

100 P10_2 / TAUD0I5 / TAUD0O5 / RIIC0SDA / KR0I0 / PWGA2O / ADCA0TRG0 / TAPA0VP / CSIH1SO / MODE1

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 446 of 4535 Dec 26, 2018 2C.2 Pin Description Table 2C.5 Pin Functions No. of Pins Pin Name 48 Pins 64 Pins 80 Pins 100 Pins IO Pin Function Unit A0VREF     — ADCAn voltage supply and reference voltage ADCAn A0VSS     — ADCAn ground ADCA0Im     I ADCA0 input channel m with 12-bit resolution m = 0 to 7 m = 0 to 9 m = 0 to 10 m = 0 to 15 ADCA0ImS     I ADCA0 input channel m with 10-bit resolution m = 0 to 3 m = 0 to 10 m = 0 to 13 m = 0 to 19 ADCA0SELy     O External MPX selection pin y for ADCA0 input y = 0 to 2 y = 0 to 2 y = 0 to 2 y = 0 to 2 ADCA0TRGy     I ADCA0 external trigger pin y y = 0 to 2 y = 0 to 2 y = 0 to 2 y = 0 to 2 AP0_m     IO Analog port 0_m Port m = 0 to 7 m = 0 to 9 m = 0 to 10 m = 0 to 15 APO     O Port output signal for analog input LPS0 AWOVCL     — Voltage regulator for Always-On area (AWO area) capacitor connection Power AWOVSS     — Internal logic for Always-On area (AWO area) ground CANzRX     I CANz receive data input RCFDCn z = 0 z = 0 to 2 z = 0 to 2 z = 0 to 5 CANzTX     O CANz transmit data output z = 0 z = 0 to 2 z = 0 to 2 z = 0 to 5 CSCXFOUT     O Clock output Clock CSIG0RYI     I CSIGn ready (1) / busy (0) input signal CSIGn CSIG0RYO     O CSIGn ready (1) / busy (0) output signal CSIG0SC     IO CSIGn serial clock signal CSIG0SI     I CSIGn serial data input CSIG0SO     O CSIGn serial data output CSIG0SSI     I CSIGn SS function control input signal CSIHnCSS0     O CSIHn serial peripheral chip select signal 0 CSIHn n = 0 n = 0 n = 0 to 2 n = 0 to 3 CSIHnCSS1     O CSIHn serial peripheral chip select signal 1 n = 0 n = 0 n = 0 to 2 n = 0 to 3 CSIHnCSS2 —    O CSIHn serial peripheral chip select signal 2 n = 0 n = 0 to 2 n = 0 to 3 CSIHnCSS3 —    O CSIHn serial peripheral chip select signal 3 n = 0 n = 0 to 2 n = 0 to 3 CSIHnCSS4 — —   O CSIHn serial peripheral chip select signal 4 n = 0 n = 0, 1 CSIHnCSS5 — —   O CSIHn serial peripheral chip select signal 5 n = 0 n = 0, 1 CSIHnCSS6 — —   O CSIHn serial peripheral chip select signal 6 n = 0 n = 0 CSIHnCSS7 — —   O CSIHn serial peripheral chip select signal 7 n = 0 n = 0 CSIHnRYI     I CSIHn ready (1) / busy (0) input signal n = 0 n = 0 n = 0 to 2 n = 0 to 3 CSIHnRYO     O CSIHn ready (1) / busy (0) output signal n = 0 n = 0 n = 0 to 2 n = 0 to 3 CSIHnSC     IO CSIHn serial clock signal n = 0 n = 0 n = 0 to 2 n = 0 to 3

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 447 of 4535 Dec 26, 2018 Table 2C.5 Pin Functions No. of Pins Pin Name 48 Pins 64 Pins 80 Pins 100 Pins IO Pin Function Unit CSIHnSI     I CSIHn serial data input CSIHn n = 0 n = 0 n = 0 to 2 n = 0 to 3 CSIHnSO     O CSIHn serial data output n = 0 n = 0 n = 0 to 2 n = 0 to 3 CSIHnSSI     I CSIHn slave select input signal n = 0 n = 0 n = 0 to 2 n = 0 to 3 DCURDY     O Debug ready OCD DCUTCK     I Debug clock DCUTDI     I Debug data input DCUTDO     O Debug data output DCUTMS     I Debug mode select DCUTRST     I Debug reset DPINm     I Digital port input m LPS0 m = 0 to 2 m = 0 to 4, 8 to 10 m = 0 to 11 m = 0 to 16 DPO     O Port output signal for digital input ENCA0TINm     I ENCA0 capture trigger input m ENCAn m = 0, 1 m = 0, 1 m = 0, 1 m = 0, 1 ENCA0EC     I ENCA0 encoder clear input ENCA0E0     I ENCA0 encoder input 0 ENCA0E1     I ENCA0 encoder input 1 EVCC     — Port buffer voltage supply Power EVSS     — Port buffer ground FLMD0     I Operating mode select pin 0 Mode FLMD1     I Operating mode select pin 1 FPDR     I Serial Communication Interface RXD FLASH FPDT     O Serial Communication Interface TXD FPCK     I Serial Communication Interface clock INTPm     I External interrupt input m INTC m = 0 to 5, 10, 11 m = 0 to 5, 10, 11 m = 0 to 8, 10 to 12 m = 0 to 8, 10 to 13 ISOVCL     — Voltage regulator for Isolated area (ISO area) capacitor connection Power ISOVSS     — Internal logic for Isolated area (ISO area) ground JP0_m     IO JTAG port 0_m JTAG m = 0 to 5 m = 0 to 5 m = 0 to 5 m = 0 to 5 KR0Im     I KR0 key input signal KRn m = 0 to 5 m = 0 to 7 m = 0 to 7 m = 0 to 7 LPDCLK     I LPD clock input (4-pin mode) LPD LPDCLKOUT     O LPD clock output (4-pin mode) LPDI     I LPD data input (4-pin mode) LPDIO     IO LPD data input / output (1-pin mode) LPDO     O LPD data output (4-pin mode) MODEm     I Sub operating mode select (Boundary scan) Mode m = 0 to 2 m = 0 to 2 m = 0 to 2 m = 0 to 2 NMI     I External non-maskable interrupt input INTC m = 0 to 3 m = 0 to 6 m = 0 to 12 m = 0 to 14 m = 0 to 1 m = 0 to 6 m = 0 to 6 m = 0 to 12 m = 0 to 1 m = 0 to 3 m = 0 to 6 m = 0 to 6

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 448 of 4535 Dec 26, 2018 Table 2C.5 Pin Functions No. of Pins Pin Name 48 Pins 64 Pins 80 Pins 100 Pins IO Pin Function Unit P10_m     IO Port 10_m Port m = 0 to 10 m = 0 to 14 m = 0 to 15 m = 0 to 15 m = 0 to 4 m = 0 to 7 PWGAnO     O PWGAn output signal PWGAn n = 0 to 12 n = 0 to 23 m =0 to 23 n = 0 to 47 REGVCC     — Voltage regulators voltage supply Power RESET     I External reset input Reset RESETOUT —    O Reset output RIICnSCL     IO RIICn serial clock RIICn n = 0 to 1 n = 0 to 1 n = 0 to 1 n = 0 to 1 RIICnSDA     IO RIICn serial data n = 0 to 1 n = 0 to 1 n = 0 to 1 n = 0 to 1 RLIN2mRX     I RLIN2m receive data input RLIN24n m = 0 to 1 m = 0 to 1 m = 0 to 1 m = 0 to 2 RLIN2mTX     O RLIN2m transmit data output m = 0 to 1 m = 0 to 1 m = 0 to 1 m = 0 to 2 RLIN3nRX     I RLIN3n receive data input RLIN3n n = 0 n = 0 to 1 n = 0 to 2 n = 0 to 3 RLIN3nTX     O RLIN3n transmit data output n = 0 n = 0 to 1 n = 0 to 2 n = 0 to 3 SENTnRX     I SENT data input RSENTn n = 0 to 1 n = 0 to 1 n = 0 to 1 n = 0 to 1 SENTnSPCO     O SENT SPC extension output n = 0 to 1 n = 0 to 1 n = 0 to 1 n = 0 to 1 RTCA0OUT     O RTCA0 1Hz output RTCAn SELDPk —    O External multiplexer selection output signal k for digital port LPS0 k = 0 to 2 k = 0 to 2 k = 0 to 2 TAPA0ESO     I Hi-Z control TAPAn TAPA0UN     O Motor control output U phase (negative) TAPA0UP     O Motor control output U phase (positive) TAPA0VN     O Motor control output V phase (negative) TAPA0VP     O Motor control output V phase (positive) TAPA0WN     O Motor control output W phase (negative) TAPA0WP     O Motor control output W phase (positive) TAUD0Im     I TAUD0 channel input m TAUDn m = 0 to 15 m = 0 to 15 m = 0 to 15 m = 0 to 15 TAUD0Om     O TAUD0 channel output m m = 0 to 15 m = 0 to 15 m = 0 to 15 m = 0 to 15 TAUB0Im — —   I TAUBn channel input m TAUBn m = 0 to 15 m = 0 to 15 TAUB0Om — —   O TAUBn channel output m m = 0 to 15 m = 0 to 15

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 449 of 4535 Dec 26, 2018 Table 2C.5 Pin Functions No. of Pins Pin Name 48 Pins 64 Pins 80 Pins 100 Pins IO Pin Function Unit TAUJnIm     I TAUJn channel input m TAUJn n = 0 to 3 m = 0 to 3 n = 0 to 3 m = 0 to 3 n = 0 to 3 m = 0 to 3 n = 0 to 3 m = 0 to 3 TAUJnOm     O TAUJn channel output m n = 0 to 3 m = 0 to 3 n = 0 to 3 m = 0 to 3 n = 0 to 3 m = 0 to 3 n = 0 to 3 m = 0 to 3 X1, X2     — MainOSC connections MOSC CAUTION When pin functions for a peripheral module are allocated to multiple pins, use the pins from the same port group or nearby pins as the pins for a given channel.

• (e.g.) When RS-CANFD channel 0 is used: CAN0TX P0_0 P10_1 CAN0RX P0_1 P10_0 Use one of the following pin combinations: - P0_0 and P0_1, or - P10_0 and P10_1. The combinations of P0_0 and P10_0, and P0_1 and P10_1 are not allowed.

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 450 of 4535 Dec 26, 2018 2C.3 Pin Functions During and After Reset Table 2C.6 Pin Functions During and After Reset Pins During Reset After Reset JP0_0 High impedance JP0_0: Input Serial programming mode: FPDR, FPDT (1 wire UART) FPDR (2 wire UART) Nexus I/F: DCUTDI input LPD (4 pins): LPDI input LPD (1 pin): LPDIO input/output JP0_1 High impedance JP0_1: Input Serial programming mode: FPDT Nexus I/F: DCUTDO output LPD (4 pins): LPDO output LPD (1 pin): High impedance JP0_2 High impedance JP0_2: Input Serial programming mode: FPCK Nexus I/F: DCUTCK input LPD (4 pins): LPDCLK input LPD (1 pin): High impedance JP0_3 High impedance JP0_3: Input Serial programming mode: High impedance Nexus I/F: DCUTMS input LPD (4 pins): High impedance LPD (1 pin): High impedance JP0_4 Input*3,*5 JP0_4: Input Serial programming mode: High impedance Nexus I/F: DCUTRST input*1 LPD (4 pins): High impedance LPD (1 pin): High impedance JP0_5 High impedance JP0_5: Input Serial programming mode: High impedance Nexus I/F: DCURDY output LPD (4 pins): LPDCLKOUT output LPD (1 pin): High impedance P8_6 Output*2 *4 Output (OPBT0.RESETOUTEN = 1)*2 High impedance (OPBT0.RESETOUTEN = 0)*2, *4 P0, P8 to 11 (except P8_6, P10_1, P10_2, P10_6 and P10_8) High impedance High impedance P10_1 High impedance High impedance (FLMD0 = 0) High impedance (FLMD0 = 1, FLMD1 = 0) MODE0 input (FLMD0 = 1, FLMD1 = 1) P10_2 High impedance High impedance (FLMD0 = 0) High impedance (FLMD0 = 1, FLMD1 = 0) MODE1 input (FLMD0 = 1, FLMD1 = 1) P10_6 High impedance High impedance (FLMD0 = 0) High impedance (FLMD0 = 1, FLMD1 = 0) High impedance (FLMD0 = 1, FLMD1 = 1, MODE0 = 0, MODE1 = 0) High impedance (FLMD0 = 1, FLMD1 = 1, MODE0 = 0, MODE1 = 1) High impedance (FLMD0 = 1, FLMD1 = 1, MODE0 = 1, MODE1 = 0) MODE2 input (FLMD0 = 1, FLMD1 = 1, MODE0 = 1, MODE1 = 1) P10_8 High impedance High impedance (FLMD0 = 0) FLMD1 input (FLMD0 = 1) FLMD0 Input Input RESET Input Input AP0 High impedance High impedance

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 451 of 4535 Dec 26, 2018 Note 1. When Nexus is enabled and no external device is connected, the level of the pin must always be fixed to low level. Note 2. RESETOUT is output. For details, see Section 2C.11, Port (Special I/O) Function Overview. Note 3. When the power is turned on or when RESET is low level, JP0_4 pin should be driven low level. Note 4. If OPBT0.RESETOUTEN = 0, P8_6 pin status has a possibility to become unstable (less than 15 μs) at the transition moment to reset status by internal reset factors. Note 5. When RESET is low level, on-chip pull-down resistor is connected to JP0_4.

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 452 of 4535 Dec 26, 2018 2C.4 Port State in Standby Mode For the port state in standby mode, see Section 14.1.4, I/O Buffer Control. 2C.5 Recommended Connection of Unused Pins If the pins are not used, it is recommended to connect them as shown below. Table 2C.7 Recommended Connection of Unused Pins Pin Recommended Connection of Unused Pins A0VREF Connected to EVCC A0VSS Connected to EVSS RESET Connected to EVCC via a resistor X1 Connected to AWOVSS via a resistor X2 Open JP0 (excluding JP0_4) P8 (excluding P8_6) Input: Open (when the PIBCn_m and PMCn_m bits are 0) Connected to EVCC or EVSS via a resistor (when the PIBCn_m or PMCn_m bits are 1) Output: Open P8_6 Input: Open (when the PIBCn_m and PMCn_m bits are 0) Connected to EVSS via a resistor (when the PIBCn_m or PMCn_m bits are 1) Output: Open JP0_4 Connected to EVSS via a resistor P10 (excluding P10_1, P10_2, P10_6, P10_8) P11 Input: Open (when the PIBCn_m and PMCn_m bits are 0) Connected to EVCC or EVSS via a resistor (when the PIBCn_m or PMCn_m bits are 1) Output: Open P10_1, P10_2, P10_6, P10_8 Input: Open (when the PIBCn_m and PMCn_m bits are 0) Connected to EVSS via a resistor (when the PIBCn_m or PMCn_m bits are 1) Output: Open AP0 Input: Open (when the PIBCn_m bit is 0) Connected to A0VREF or A0VSS via a resistor (when the PIBCn_m bit is 1) Output: Open Nexus/LPD I/F (JP0) DCUTDI/LPDI/LPDIO (JP0_0): Connected to EVCC via a resistor DCUTDO/LPDO (JP0_1): Open DCUTCK/LPDCLK (JP0_2): Open DCUTMS (JP0_3): Connected to EVCC via a resistor DCUTRST (JP0_4): Connected to EVSS via a resistor*1 DCURDY /LPDCLKOUT (JP0_5): Open Note 1. For in case when a debugging interface is used, this pin should be connected to EVCC through resistor depending on the development tool made by a third party.

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 453 of 4535 Dec 26, 2018 2C.6 Features of RH850/F1KM Port 2C.6.1 Port Group The RH850/F1KM provides the following port groups, indicated by the numbers in the table below. Table 2C.8 Port Groups in RH850/F1KM-S1 No. of Pins Port Group RH850/F1KM-S1 48 pins Number 6 Name P0, P8 to P10, JP0, AP0 64 pins Number 6 Name P0, P8 to P10, JP0, AP0 80 pins Number 7 Name P0, P8 to P11, JP0, AP0 100 pins Number 7 Name P0, P8 to P11, JP0, AP0 2C.6.2 Port Group Index n Throughout this section, the port groups are identified by using the index “n”. For example, the port mode control register of the Pn pin is PMCn (n = 0, and 8 to 11). 2C.6.3 Register Base Addresses Port and JTAG port base addresses are listed in the following table. Port and JTAG port register addresses are given as offsets from the base addresses. Table 2C.9 Register Base Addresses Base Address Name Base Address <PORTn_base> FFC1 0000H <JPORT0_base> FFC2 0000H 2C.6.4 Clock Supply The clock supply to ports is shown in the following table. Table 2C.10 Clock Supply Unit Name Unit Clock Name Supply Clock Name Port Register access clock CPUCLK_UL

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 454 of 4535 Dec 26, 2018 2C.7 Port Functions This product has various pins for input/output ports. The ports are organized in port groups. The RH850/F1KM also has several control registers to enable pins to be used as other than general -purpose input/output pins. For a description of the terms pin, port, and port group, see Section 2C.7.2, Terms. 2C.7.1 Functional Overview

• All the port settings can be specified individually.
• The maximum number of bits (pins) in a port is 16.
• The output level of any pin can be set independently without affecting the other pins in the same port.
• Input buffers are enabled through registers settings.
• Pin level is read by dedicated port-pin-read register (PPR)
• All possible port functions are shown in the tables listed below. Table 2C.39, JTAG Port 0 (JP0), Table 2C.41, Port 0 (P0), Table 2C.43, Port 8 (P8), Table 2C.45, Port 9 (P9), Table 2C.47, Port 10 (P10), Table 2C.49, Port 11 (P11), Table 2C.51, Analog Port 0 (AP0) and Section 2C.9.2, Pin Function Configuration. CAUTION Some input or output functions may be assigned to more than one port. Only activate a given function on a single pin. Do not activate a function on multiple pins at the same time. This also applies in cases where multiple peripheral functions are assigned to a single multiplexed function and only one of these functions is used. [Example] INTP0 is assigned to the following pins on this device. However, the INTP0 function should not be activated on more than one pin. After activating the function on one pin, do not activate it on another.
• JP0_0 (1st input alternative function)
• P0_1 (2nd, 3rd input alternative function)
• P10_0 (2nd input alternative function) In the above case, when the 1st input alternative function (INTP0) of JP0_0 is selected, using the 2nd input alternative function (CAN0RX/INTP0) of P0_1 only for the CAN signal is also prohibited.

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 455 of 4535 Dec 26, 2018 2C.7.2 Terms The following terms are used in this section: Pin Denotes the physical pin. Every pin is denoted by a unique pin number. A pin can be used in several modes. Each pin is assigned a name that reflects its function, which is determined by the selected mode. Port group Denotes a group of pins. All the pins of a specific port group are controlled by the same port control register. Port mode and ports A pin in port mode works as a general-purpose input/output pin. It is then called “port”. The corresponding name is Pn_m. For example, P0_7 denotes port 7 of port group 0. It is refere nced as “port P0_7”. Alternative mode In alternative mode, a pin can be used for various non-general-purpose input/output functions, such as the input/output pin of on-chip peripherals. The corresponding pin name depends on the selected function. For example, pin INTP0 denotes the pin for one of the external interrupt inputs. Note that two different names can refer to the same physical pin, for example P0_0 and INTP0. The different names indicate the function of the pin at that time. 2C.7.2.1 JTAG Ports The JTAG port groups are used for connecting a debugger for on-chip debugging. JTAG port group registers and bit names are prefixed by a “J”. For example, JP0 denotes JTAG port group 0, and JPM0.JPM0_m denotes the JPM0_m port mode bit of the JPM0 port mode register. NOTE In this section, the descriptions about all ports and their registers other than PFCAEn and PIPCn apply to the JTAG port unless otherwise specified.

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 456 of 4535 Dec 26, 2018 2C.7.3 Overview of Pin Functions Pins can operate in three modes.

• Port mode (PMCn.PMCn_m bit = 0) A pin in port mode operates as a general-purpose input/output pin. The I/O mode is selected by setting the PMn.PMn_m bit.
• Software I/O control alternative mode (PMCn.PMCn_m bit = 1, PIPCn.PIPCn_m bit = 0) In this mode, the pins operate as alternative functions. The I/O mode is selected by setting the PMn.PMn_m bit.
• Direct I/O control alternative mode (PMCn.PMCn_m bit = 1, PIPCn.PIPCn_m bit = 1) In this mode, the pins operate as alternative functions. Unlike the software I/O control alternative mode, however, the I/O mode is directly controlled by the alternative function. An overview of the register settings is given in the tables below. Table 2C.11 Pin Function Configuration (Overview) Bit Mode PMCn_m PMn_m PIPCn_m I/O Port mode 0 0 X O 1*1 I Software I/O control alternative mode 1 0 0 O 1 0 I Direct I/O control alternative mode X 1 Controlled by the alternative function Note 1. The input buffer must be enabled (PIBCn_m bit = 1).
• Software I/O control alternative mode (PIPCn.PIPCn_m bit = 0) − Output (PMn_m bit = 0): Alternative output mode 1 to Alternative output mode 7 − Input (PMn_m bit = 1): Alternative input mode 1 to Alternative input mode 7
• Direct I/O control alternative mode (PIPCn.PIPCn_m bit = 1) − The I/O mode for Alternative output mode 1 to Alternative output mode 7 and Alternative input mode 1 to Alternative input mode 7 is directly selected by the alternative function.

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 457 of 4535 Dec 26, 2018 Table 2C.12 Alternative Mode Selection Overview (PMCn.PMCn_m Bit = 1) Register Mode PIPC*1 PM*1 PFCAE PFCE PFC I/O Alternative output mode 1 (ALT-OUT1) 0 0 0 0 0 O Alternative input mode 1 (ALT-IN1) 1 I Alternative output mode 2 (ALT-OUT2) 0 1 O Alternative input mode 2 (ALT-IN2) 1 I Alternative output mode 3 (ALT-OUT3) 0 1 0 O Alternative input mode 3 (ALT-IN3) 1 I Alternative output mode 4 (ALT-OUT4) 0 1 O Alternative input mode 4 (ALT-IN4) 1 I Alternative output mode 5 (ALT-OUT5) 0 1 0 0 O Alternative input mode 5 (ALT-IN5) 1 I Alternative output mode 6 (ALT-OUT6) 0 1 O Alternative input mode 6 (ALT-IN6) 1 I Alternative output mode 7 (ALT-OUT7) 0 1 0 O Alternative input mode 7 (ALT-IN7) 1 I Other than the above Setting prohibited Note 1. If PIPCn.PIPCn_m bit = 1, the I/O direction is directly controlled by the peripheral (alternative) function and PM is ignored. If a pin is in alternative mode (PMCn.PMCn_m bit = 1), one of up to seven alternative functions can be selected for that pin by using the PFCn, PFCEn, and PFCAEn registers.

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 458 of 4535 Dec 26, 2018 2C.7.4 Pin Data Input/Output The registers used for data input/output are described below. The location that is read via the PPRn register differs depending on the pin mode. 2C.7.4.1 Output Data In the port mode (PMCn.PMCn_m bit = 0), the value of the Pn.Pn_m bit is output from the Pn_m pin. 2C.7.4.2 Input Data When the PPRn register is read, either the value of the Pn_m pin, the value of the Pn.Pn_m bit, or the value output by the alternative function is returned. Which value is returned depends on the pin mode and setting of several control bits. The different PPRn read modes are shown in the table below. Table 2C.13 PPRn_m Read Values PMC n_m PM n_m PIBC n_m PIPC n_m PODC n_m Mode PPRn_m Read Value 0 1 0 X X Port input, input buffer disabled Pn.Pn_m bit 0 X 0 Port push-pull output Pn.Pn_m bit*1 1 1 X 0 X Software I/O control alternative input Pn_m pin 0 0 Software I/O control alternative push- pull output Output signal from the alternative function*1 X 1 0 Direct I/O control alternative input or push-pull output I/O port in alternative mode:

• Input: Pn_m pin
• Output: Output signal from the alternative function*1 Note 1. When PBDCn_m = 1, the level of the Pn_m pin is returned by the PPRn_m bit. The control registers in the above table have the following effects:
• PMCn.PMCn_m bit This bit selects port mode (PMCn_m = 0) or alternative mode (PMCn_m = 1).
• PMn.PMn_m bit This bit selects input (PMn_m = 1) or output (PMn_m = 0) when the port mode (PMCn_m = 0) and software I/O control alternative mode (PMCn_m = 1, PIPCn_m = 0) have been selected.
• PIBCn.PIBCn_m bit This bit disables (PIBCn_m = 0) or enables (PIBCn_m = 1) the input buffer in input port mode (PMCn_m = 0 and PMn_m = 1). If the input buffer is disabled, PPRn_m reads the Pn.Pn_m bit; otherwise the Pn_m pin level is returned.
• PIPCn.PIPCn_m bit This bit selects software I/O control alternative mode or direct I/O control alternative mode.

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 459 of 4535 Dec 26, 2018

• PODCn.PODCn_m bit This bit selects push-pull output (PODCn_m = 0) or open-drain output (PODCn_m = 1).
• PBDCn.PBDCn_m bit In output mode, when this bit is set to 1, the pin enters the bidirectional mode. In bidirectional mode, the level of the signal on a Pn_m pin can be read from PPRn.PPRn_m. CAUTION When using Pn_m as an alternative output function (PMCn.PMCn_m bit = 1, PMn.PMn_m bit = 0), the level of the Pn_m pin can be read at the PPRn.PPRn_m bit by enabling bidirectional mode (PBDCn.PBDCn_m bit = 1). Note, however, that the level of the Pn_m pin will be input to the alternative input function that the Pn_m pin is being used as. 2C.7.4.3 Writing to the Pn Register The data to be output via port Pn_m in port mode (PMCn.PMCn_m bit = 0) is held in port register Pn. Pn data can be overwritten in two ways:
• By writing data directly to the Pn register. In this case, new data can be written directly to the Pn register.
• By performing an indirect bitwise operation (a “set”, “reset”, or “not” operation) on the Pn register. An indirect bitwise operation (“set”, “reset”, or “not”) can be performed on the Pn register by using the following two registers: − Port Set/Reset register PSRn If the PSRn.PSRn (m + 16) bit = 1, the value of the Pn.Pn_m bit is determined by the value of the PSRn.PSRn_m bit. In other words, the Pn_m bit can be set or reset without writing directly to the Pn register. − Port NOT register PNOTn By setting PNOTn.PNOTn_m bit to 1, the Pn.Pn_m bit can be inverted without writing directly to the Pn register. An indirect bitwise operation on the Pn register (“set”, “reset”, or “not”) has no effect on the bits that do not need to be updated, allowing you to overwrite only the bit or bits that need to be overwritten.

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 460 of 4535 Dec 26, 2018 2C.8 Schematic View of Port Control The following figure is a schematic view of the port control functions. Peripheral bus (PBUS) PDSC PU PD PBDC PM PIBC PMC PIPC PODC PPR P PSR PNOT PPCMD PFC PFCE PFCAE PMSR PMCSR PPROTS PIS Internal IPs 1 2 3 ... 1 2 3 1 2 3 1 2 3 Internal IP data output Internal IP data output control Internal IP data input control Internal IP data input Output buffer control Pull-down control Pull-up control Input buffer control Input buffer control P N Output data control Input data control Alternative function selection PISA*1 Open drain control Note 1. There is no PISAn register in RH850/F1KM-S1. Figure 2C.5 Schematic View of Port Control CAUTION Use documented alternative functions only. The behavior and performance are not guaranteed when undocumented alternative functions are selected.

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 461 of 4535 Dec 26, 2018 2C.9 Port Group Configuration Registers This section starts with an overview of all configuration registers and then describes all registers in detail. The configuration registers are grouped as follows:

• Section 2C.9.2, Pin Function Configuration
• Section 2C.9.3, Pin Data Input/Output
• Section 2C.9.4, Configuration of Electrical Characteristics 2C.9.1 Overview The following registers are used for setting the individual pins of the port groups. For details on <PORTn_base> and <JPORT0_base>, see Section 2C.6.3, Register Base Addresses. Table 2C.14 Port Group Configuration Registers Module Name Register Name Symbol Address Pin function configuration PORT Port mode control register PMCn <PORTn_base> + 0400H + n × 4 JTAG JPMC0 <JPORT0_base> + 0040H PORT Port mode control set/reset register PMCSRn <PORTn_base> + 0900H + n × 4 JTAG JPMCSR0 <JPORT0_base> + 0090H PORT Port IP control register PIPCn <PORTn_base> + 4200H + n × 4 PORT Port mode register PMn <PORTn_base> + 0300H + n × 4 APMn <PORTn_base> + 03C8H + n × 4 JTAG JPM0 <JPORT0_base> + 0030H PORT Port mode set/reset register PMSRn <PORTn_base> + 0800H + n × 4 APMSRn <PORTn_base> + 08C8H + n × 4 JTAG JPMSR0 <JPORT0_base> + 0080H PORT Port input buffer control register PIBCn <PORTn_base> + 4000H + n × 4 APIBCn <PORTn_base> + 40C8H + n × 4 JTAG JPIBC0 <JPORT0_base> + 0400H PORT Port function control register PFCn <PORTn_base> + 0500H + n × 4 JTAG JPFC0 <JPORT0_base> + 0050H PORT Port function control expansion register PFCEn <PORTn_base> + 0600H + n × 4 JTAG JPFCE0 <JPORT0_base> + 0060H PORT Port function control additional expansion register PFCAEn <PORTn_base> + 0A00H + n × 4 Pin data input/output PORT Port bidirection control register PBDCn <PORTn_base> + 4100H + n × 4 APBDCn <PORTn_base> + 41C8H + n × 4 JTAG JPBDC0 <JPORT0_base> + 0410H PORT Port pin read register PPRn <PORTn_base> + 0200H + n × 4 APPRn <PORTn_base> + 02C8H + n × 4 JTAG JPPR0 <JPORT0_base> + 0020H PORT Port register Pn <PORTn_base> + 0000H + n × 4 APn <PORTn_base> + 00C8H + n × 4 JTAG JP0 <JPORT0_base> + 0000H

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 462 of 4535 Dec 26, 2018 Table 2C.14 Port Group Configuration Registers Module Name Register Name Symbol Address Pin data input/output PORT Port NOT register PNOTn <PORTn_base> + 0700H + n × 4 APNOTn <PORTn_base> + 07C8H + n × 4 JTAG JPNOT0 <JPORT0_base> + 0070H PORT Port set/reset register PSRn <PORTn_base> + 0100H + n × 4 APSRn <PORTn_base> + 01C8H + n × 4 JTAG JPSR0 <JPORT0_base> + 0010H Configuration of electrical characteristics PORT Pull-up option register PUn <PORTn_base> + 4300H + n × 4 JTAG JPU0 <JPORT0_base> + 0430H PORT Pull-down option register PDn <PORTn_base> + 4400H + n × 4 JTAG JPD0 <JPORT0_base> + 0440H PORT Port drive strength control register PDSCn <PORTn_base> + 4600H + n × 4 JTAG JPDSC0 <JPORT0_base> + 0460H PORT Port open drain control register PODCn <PORTn_base> + 4500H + n × 4 JTAG JPODC0 <JPORT0_base> + 0450H PORT Port input buffer selection register PISn <PORTn_base> + 4700H + n × 4 JTAG JPIS0 <JPORT0_base> + 0470H JTAG Port input buffer selection advanced register JPISA0 <JPORT0_base> + 04A0H Port register protection PORT Port protection command register PPCMDn <PORTn_base> + 4C00H + n × 4 JTAG JPPCMD0 <JPORT0_base> + 04C0H PORT Port protection status register PPROTSn <PORTn_base> + 4B00H + n × 4 JTAG JPPROTS0 <JPORT0_base> + 04B0H Index n In Table 2C.14, Port Group Configuration Registers, the index “n” in register symbols denotes the actual indices of the individual port groups. For example, PMCn generically indicates a port mode control register for port group n (Pn). The values for n differ according to the number of pins on the device in the way shown in Table 2C.15, Number of Pins on the Device, Name of Port Groups, and Values for “n” in Register Symbols . Table 2C.15 Number of Pins on the Device, Name of Port Groups, and Values for “n” in Register Symbols Number of Pins on the Device Port Groups Values for “n” 48 pins P0, P8, P9, P10 0, 8, 9, 10 AP0 0 64 pins P0, P8, P9, P10 0, 8, 9, 10 AP0 0 80 pins P0, P8, P9, P10, P11 0, 8, 9, 10, 11 AP0 0 100 pins P0, P8, P9, P10, P11 0, 8, 9, 10, 11 AP0 0

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 463 of 4535 Dec 26, 2018 JTAG port registers JTAG port registers are not explicitly described in the following register descriptions. All descriptions (except for those of the PFCAEn register and PIPCn register) apply to JTAG port registers. Note, however, that the JTAG port register base address differs from that of regular ports. Value after reset The values after reset depend on the ports. For the values after reset, see the register descriptions in the following pages.

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 464 of 4535 Dec 26, 2018 2C.9.2 Pin Function Configuration 2C.9.2.1 PMCn / JPMC0 — Port Mode Control Register This register specifies whether the individual pins of port group n are in port mode or in alternative mode. Access: PMCn: This register can be read or written in 16-bit units. JPMC0: This register can be read or written in 8-bit units. Address: PMCn: <PORTn_base> + 0400H + n × 4 (n = 0, 8, 9, 10, 11) JPMC0: <JPORT0_base> + 0040H*1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PMC n_15 PMC n_14 PMC n_13 PMC n_12 PMC n_11 PMC n_10 PMC n_9 PMC n_8 PMC n_7 PMC n_6 PMC n_5 PMC n_4 PMC n_3 PMC n_2 PMC n_1 PMC n_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2C.10, Port (General I/O) Function Overview: Table 2C.40, Control Registers (JP0), Table 2C.42, Control Registers (P0), Table 2C.44, Control Registers (P8), Table 2C.46, Control Registers (P9), Table 2C.48, Control Registers (P10), and Table 2C.50, Control Registers (P11). Table 2C.16 PMCn Register Contents Bit Position Bit Name Function 15 to 0 PMCn_[15:0] Specifies the operation mode of the corresponding pin. 0: Port mode 1: Alternative mode CAUTIONS 1. I/O is not controlled by only setting alternative mode (PMCn.PMCn_m bit = 1). If the alternative function requires direct I/O control, also set the PIPCn.PIPCn_m bit to 1. 2. If a port is to be used as an input pin in alternative mode, the signals from some pins will pass through a noise filter. These pins may require the setting of the FCLA0CTLm_<name>, DNFA<name>CTL and the DNFA<name>EN register. For details, see Section 2C.12, Noise Filter & Edge/Level Detector, and Section 2C.13, Description of Port Noise Filter & Edge/Level Detection. NOTE The control bits of the JTAG port mode control register (JPMC0) are JPMC0_[7:0].

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 465 of 4535 Dec 26, 2018 2C.9.2.2 PMCSRn / JPMCSR0 — Port Mode Control Set/Reset Register This register provides an alternative method to write data to the PMCn register. The upper 16 bits of PMCSRn act as a mask which specifies whether or not the value of PMCn.PMCn_m is set by the corresponding bit in the lower 16 bits of PMCSRn. Access: PMCSRn: This register can be read or written in 32-bit units. Bits 31 to 16 are always read as 0000H. Reading bits 15 to 0 returns the value of register PMCn. JPMCSR0: This register can be read or written in 32-bit units. Bits 31 to 8 are always read as 000000H. Reading bits 7 to 0 returns the value of register JPMC0. Address: PMCSRn: <PORTn_base> + 0900H + n × 4 (n = 0, 8, 9, 10, 11) JPMCSR0: <JPORT0_base> + 0090H*1 Value after reset: 0000 0000H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PMC SRn_31 PMC SRn_30 PMC SRn_29 PMC SRn_28 PMC SRn_27 PMC SRn_26 PMC SRn_25 PMC SRn_24 PMC SRn_23 PMC SRn_22 PMC SRn_21 PMC SRn_20 PMC SRn_19 PMC SRn_18 PMC SRn_17 PMC SRn_16 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PMC SRn_15 PMC SRn_14 PMC SRn_13 PMC SRn_12 PMC SRn_11 PMC SRn_10 PMC SRn_9 PMC SRn_8 PMC SRn_7 PMC SRn_6 PMC SRn_5 PMC SRn_4 PMC SRn_3 PMC SRn_2 PMC SRn_1 PMC SRn_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2C.10, Port (General I/O) Function Overview: Table 2C.40, Control Registers (JP0), Table 2C.42, Control Registers (P0), Table 2C.44, Control Registers (P8), Table 2C.46, Control Registers (P9), Table 2C.48, Control Registers (P10), and Table 2C.50, Control Registers (P11). Table 2C.17 PMCSRn Register Contents Bit Position Bit Name Function 31 to 16 PMCSRn_[31:16] Enable bits that specify whether the value of the corresponding lower bit PMCSRn_m (PMCSRn_[15:0]) is written to PMCn_m. 0: PMCn_m is not affected by PMCSRn_m. 1: PMCn_m is PMCSRn_m. Example: If PMCSRn.PMCSRn_31 = 1, the value of bit PMCSRn.PMCSRn_15 is written to bit PMCn.PMCn_15. 15 to 0 PMCSRn_[15:0] Data bits that specify the value of PMCn_m if PMCSRn_m of the corresponding upper bit (PMCSRn_[31:16]) is 1. 0: PMCn_m is 0. 1: PMCn_m is 1. NOTE The control bits of the JTAG port mode control set/reset register (JPMCSR0) are JPMCSR0_[31:0].

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 466 of 4535 Dec 26, 2018 2C.9.2.3 PIPCn — Port IP Control Register This register specifies whether the I/O direction of the Pn_m pin is controlled by the port mode register PMn.PMn_m or by an alternative function. If the Pn_m pin is operated in alternative mode (PMCn.PMCn_m = 1) and the alternative function requires direct control of the I/O direction, then PIPCn.PIPCn_m must be set to 1 as well. This transfers I/O control to the alternative function and overrules the PMn.PMn_m setting. Regarding the alternative functions for which the PIPC register must be set, see Section 2C.11, Port (Special I/O) Function Overview. Access: This register can be read or written in 16-bit units. Address: PIPCn: <PORTn_base> + 4200H + n × 4 (n = 0, 10, 11) *1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PIPC n_15 PIPC n_14 PIPC n_13 PIPC n_12 PIPC n_11 PIPC n_10 PIPC n_9 PIPC n_8 PIPC n_7 PIPC n_6 PIPC n_5 PIPC n_4 PIPC n_3 PIPC n_2 PIPC n_1 PIPC n_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2C.10, Port (General I/O) Function Overview: Table 2C.42, Control Registers (P0), Table 2C.48, Control Registers (P10), and Table 2C.50, Control Registers (P11). Table 2C.18 PIPCn Register Contents Bit Position Bit Name Function 15 to 0 PIPCn_[15:0] Specifies the I/O mode. 0: I/O mode is selected by PMn.PMn_m (software I/O control). 1: I/O mode is selected by the peripheral function (direct I/O control).

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 467 of 4535 Dec 26, 2018 2C.9.2.4 PMn / APMn / JPM0 — Port Mode Register This register specifies whether the individual pins of the port group n are in input mode or in output mode. Access: PMn, APMn: These registers can be read or written in 16- bit units. JPM0: This register can be read or written in 8-bit units. Address: PMn: <PORTn_base> + 0300H + n × 4 (n = 0, 8, 9, 10, 11) APMn: <PORTn_base> + 03C8H (n = 0) JPM0: <JPORT0_base> + 0030H*1 Value after reset: FFFFH*2 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PMn_15 PMn_14 PMn_13 PMn_12 PMn_11 PMn_10 PMn_9 PMn_8 PMn_7 PMn_6 PMn_5 PMn_4 PMn_3 PMn_2 PMn_1 PMn_0 Value after reset 1 1 1 1 1 1 1 1 1 1*3 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2C.10, Port (General I/O) Function Overview: Table 2C.40, Control Registers (JP0), Table 2C.42, Control Registers (P0), Table 2C.44, Control Registers (P8), Table 2C.46, Control Registers (P9), Table 2C.48, Control Registers (P10), Table 2C.50, Control Registers (P11) and Table 2C.52, Control Registers (AP0). Note 2. The PM8 register is as follows. When the OPBT0.RESETOUTEN = 1, the PM8 register is FFBFH. When the OPBT0.RESETOUTEN = 0, the PM8 register is FFFFH. Note 3. The PM8_6 bit is as follows. When the OPBT0.RESETOUTEN = 1, the PM8_6 bit is 0. When the OPBT0.RESETOUTEN = 0, the PM8_6 bit is 1. Table 2C.19 PMn Register Contents Bit Position Bit Name Function 15 to 0 PMn_[15:0] Specifies input/output mode of the corresponding pin. 0: Output mode (output enabled) 1: Input mode (output disabled) NOTES 1. To use a port in input port mode (PMCn.PMCn_m = 0 and PMn.PMn_m = 1), the input buffer must be enabled (PIBCn.PIBCn_m = 1). 2. By default, PMn.PMn_m specifies the I/O direction in port mode (PMCn.PMCn_m = 0) and alternative mode (PMCn.PMCn_m=1), since PIPCn.PIPCn_m = 0 (I/O mode is controlled by PMn.PMn_m) after reset. 3. The control bits of the analog port register (APMn) are APMn_[15:0]. 4. The control bits of the JTAG port mode register (JPM0) are JPM0_[7:0].

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 468 of 4535 Dec 26, 2018 2C.9.2.5 PMSRn / APMSRn / JPMSR0 — Port Mode Set/Reset Register This register provides an alternative method to write data to the PMn register. The upper 16 bits of PMSRn act as a mask which specifies whether or not the value PMn.PMn_m is set by the corresponding bit in the lower 16 bits of PMSRn. Access: PMSRn, APMSRn: These registers can be read or written in 32- bit units. Bits 31 to 16 are always read as 0000H. Reading bits 15 to 0 returns the value of registers PMn and APMn. JPMSR0: This register can be read or written in 32-bit units. Bits 31 to 16 are always read as 0000H. Bits 15 to 8 are read as FFH. Reading bits 7 to 0 returns the value of register JPM0. Address: PMSRn: <PORTn_base> + 0800H + n × 4 (n = 0, 8, 9, 10, 11) APMSRn: <PORTn_base> + 08C8H (n = 0) JPMSR0: <JPORT0_base> + 0080H*1 Value after reset: 0000 FFFFH*2 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PMSR n_31 PMSR n_30 PMSR n_29 PMSR n_28 PMSR n_27 PMSR n_26 PMSR n_25 PMSR n_24 PMSR n_23 PMSR n_22 PMSR n_21 PMSR n_20 PMSR n_19 PMSR n_18 PMSR n_17 PMSR n_16 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PMSR n_15 PMSR n_14 PMSR n_13 PMSR n_12 PMSR n_11 PMSR n_10 PMSR n_9 PMSR n_8 PMSR n_7 PMSR n_6 PMSR n_5 PMSR n_4 PMSR n_3 PMSR n_2 PMSR n_1 PMSR n_0 Value after reset 1 1 1 1 1 1 1 1 1 1*3 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2C.10, Port (General I/O) Function Overview: Table 2C.40, Control Registers (JP0), Table 2C.42, Control Registers (P0), Table 2C.44, Control Registers (P8), Table 2C.46, Control Registers (P9), Table 2C.48, Control Registers (P10), Table 2C.50, Control Registers (P11) and Table 2C.52, Control Registers (AP0). Note 2. The PMSR8 register is as follows. When the OPBT0.RESETOUTEN = 1, the PMSR8 register is 0000 FFBFH. When the OPBT0.RESETOUTEN = 0, the PMSR8 register is 0000 FFFFH. Note 3. The PMSR8_6 bit is as follows. When the OPBT0.RESETOUTEN = 1, the PMSR8_6 bit is 0. When the OPBT0.RESETOUTEN = 0, the PMSR8_6 bit is 1. Table 2C.20 PMSRn Register Contents Bit Position Bit Name Function 31 to 16 PMSRn_[31:16] Enable bits that specify whether the value of the corresponding lower bit PMSRn_m (PMSRn_[15:0]) is written to PMn_m. 0: PMn_m is not affected by PMSRn_m. 1: PMn_m is PMSRn_m. Example: If PMSRn.PMSRn_31 = 1, the value of bit PMSRn.PMSRn_15 is written to bit PMn.PMn_15. 15 to 0 PMSRn_[15:0] Data bits that specify the value of PMn_m if PMSRn_m of the corresponding upper bit (PMSRn_[31:16]) is 1. 0: PMn_m is 0. 1: PMn_m is 1.

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 469 of 4535 Dec 26, 2018 NOTES 1. The control bits of the JTAG port mode set/reset register (JPMSR0) are JPMSR0_[31:0]. 2. The control bits of the analog port mode set/reset register (APMSRn) are APMSRn_[31:0].

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 470 of 4535 Dec 26, 2018 2C.9.2.6 PIBCn / APIBCn / JPIBC0 — Port Input Buffer Control Register In input port mode (PMCn.PMCn_m = 0 and PMn.PMn_m = 1), this register enables the port pin’s input buffer. Access: PIBCn, APIBCn: These registers can be read or written in 16 -bit units. JPIBC0: This register can be read or written in 8-bit units. Address: PIBCn: <PORTn_base> + 4000H + n × 4 (n = 0, 8, 9, 10, 11) APIBCn: <PORTn_base> + 40C8H (n = 0) JPIBC0: <JPORT0_base> + 0400H*1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PIBC n_15 PIBC n_14 PIBC n_13 PIBC n_12 PIBC n_11 PIBC n_10 PIBC n_9 PIBC n_8 PIBC n_7 PIBC n_6 PIBC n_5 PIBC n_4 PIBC n_3 PIBC n_2 PIBC n_1 PIBC n_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2C.10, Port (General I/O) Function Overview: Table 2C.40, Control Registers (JP0), Table 2C.42, Control Registers (P0), Table 2C.44, Control Registers (P8), Table 2C.46, Control Registers (P9), Table 2C.48, Control Registers (P10), Table 2C.50, Control Registers (P11) and Table 2C.52, Control Registers (AP0). Table 2C.21 PIBCn Register Contents Bit Position Bit Name Function 15 to 0 PIBCn_[15:0] Enables/disables the input buffer. 0: Input buffer disabled 1: Input buffer enabled NOTES 1. When the input buffer is disabled, through current does not flow even when the pin level is Hi-Z. Thus the pin does not need to be fixed to a high or low level externally. 2. The control bits of the JTAG port input buffer control register (JPIBC0) are JPIBC0_[7:0]. CAUTION Settings in this register are overruled in bidirectional mode (PBDCn.PBDCn_m = 1).

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 471 of 4535 Dec 26, 2018 2C.9.2.7 PFCn / JPFC0 — Port Function Control Register This register, together with register PFCEn and PFCAEn, specifies an alternative function of the pins. Some alternative functions directly control the I/O of the Pn_m pin. For such alternative functions, PIPCn.PIPCn_m must be set to 1 and the I/O is selected by the peripheral function. For other alternative functions, input/output must be specified by PMn.PMn_m. Access: PFCn: This register can be read or written in 16-bit units. JPFC0: This register can be read or written in 8-bit units. Address: PFCn: <PORTn_base> + 0500H + n × 4 (n = 0, 8, 9, 10, 11) JPFC0: <JPORT0_base> + 0050H*1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PFC n_15 PFC n_14 PFC n_13 PFC n_12 PFC n_11 PFC n_10 PFC n_9 PFC n_8 PFC n_7 PFC n_6 PFC n_5 PFC n_4 PFC n_3 PFC n_2 PFC n_1 PFC n_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2C.10, Port (General I/O) Function Overview: Table 2C.40, Control Registers (JP0), Table 2C.42, Control Registers (P0), Table 2C.44, Control Registers (P8), Table 2C.46, Control Registers (P9), Table 2C.48, Control Registers (P10), and Table 2C.50, Control Registers (P11). Table 2C.22 PFCn Register Contents Bit Position Bit Name Function 15 to 0 PFCn_[15:0] Specifies the alternative function of the pin. For details, see Table 2C.25, Setting Alternative Functions. NOTE The control bits of the JTAG port function control register (JPFC0) are JPFC0_[7:0].

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 472 of 4535 Dec 26, 2018 2C.9.2.8 PFCEn / JPFCE0 — Port Function Control Expansion Register This register, together with register PFCn and PFCAEn, specifies an alternative function of the pins. Some alternative functions directly control the I/O of the Pn_m pin. For such alternative functions, PIPCn.PIPCn_m must be set to 1 and the I/O is specified by the peripheral function. For other alternative functions, input/output must be specified by PMn.PMn_m. Access: PFCEn: This register can be read or written in 16-bit units. JPFCE0: This register can be read or written in 8-bit units. Address: PFCEn: <PORTn_base> + 0600H + n × 4 (n = 0, 8, 9, 10, 11) JPFCE0: <JPORT0_base> + 0060H*1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PFCE n_15 PFCE n_14 PFCE n_13 PFCE n_12 PFCE n_11 PFCE n_10 PFCE n_9 PFCE n_8 PFCE n_7 PFCE n_6 PFCE n_5 PFCE n_4 PFCE n_3 PFCE n_2 PFCE n_1 PFCE n_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2C.10, Port (General I/O) Function Overview: Table 2C.40, Control Registers (JP0), Table 2C.42, Control Registers (P0), Table 2C.44, Control Registers (P8), Table 2C.46, Control Registers (P9), Table 2C.48, Control Registers (P10), and Table 2C.50, Control Registers (P11). Table 2C.23 PFCEn Register Contents Bit Position Bit Name Function 15 to 0 PFCEn_[15:0] Specifies the alternative function of the pin. For details, see Table 2C.25, Setting Alternative Functions. NOTE The control bits of the JTAG port function control register (JPFCE0) are JPFCE0_[7:0].

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 473 of 4535 Dec 26, 2018 2C.9.2.9 PFCAEn — Port Function Control Additional Expansion Register This register selects the alternative peripheral functions together with PFCEn, PFCn registers. Some alternative functions directly control the I/O of the Pn_m pin. For such alternative functions, PIPCn.PIPCn_m must be set to 1 and the I/O is specified by the peripheral function. For other alternative functions, input/output must be specified by PMn.PMn_m. Access: PFCAEn: This register can be read or written in 16-bit units. Address: PFCAEn: <PORTn_base> + 0A00H + n × 4 (n = 0, 8, 9, 10, 11)*1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PFCAE n_15 PFCAE n_14 PFCAE n_13 PFCAE n_12 PFCAE n_11 PFCAE n_10 PFCAE n_9 PFCAE n_8 PFCAE n_7 PFCAE n_6 PFCAE n_5 PFCAE n_4 PFCAE n_3 PFCAE n_2 PFCAE n_1 PFCAE n_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2C.10, Port (General I/O) Function Overview: Table 2C.42, Control Registers (P0), Table 2C.44, Control Registers (P8), Table 2C.46, Control Registers (P9), Table 2C.48, Control Registers (P10), and Table 2C.50, Control Registers (P11). Table 2C.24 PFCAEn Register Contents Bit Position Bit Name Function 15 to 0 PFCAEn_[15:0] Specifies the alternative function of the pin. For details, see Table 2C.25, Setting Alternative Functions. Table 2C.25 Setting Alternative Functions PFCAEn_m PFCEn_m PFCn_m PMn_m Function 0 0 0 1 Alternative input mode 1 1 1 Alternative input mode 2 1 0 1 Alternative input mode 3 1 1 Alternative input mode 4 1 0 0 1 Alternative input mode 5 1 1 Alternative input mode 6 1 0 1 Alternative input mode 7

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 474 of 4535 Dec 26, 2018 CAUTION

• After selecting the alternative function by the PFCn_m, PFCEn_m, or PFCAEn_m bit, set the PMCn_m bit to “1”.
• With this product, the I/O of some functions is assigned to two or more pins, but a specific pin function can only be set to one pin at a time. Setting the same pin function to two or more pins at the same time is prohibited. For example, if the a/b/c pin is used as b, the b/d/e pin cannot be used as b. In this case, the b/d/e pin must be configured as a pin function other than b. NOTE For more details on the assignment of each function, see Sections 2C.10.1, JTAG Port 0 (JP0) to 2C.10.7, Analog Port 0 (AP0).

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 475 of 4535 Dec 26, 2018 2C.9.3 Pin Data Input/Output 2C.9.3.1 PBDCn / APBDCn / JPBDC0 — Port Bidirection Control Register This register enables the input buffer in output mode and sets the port to bidirectional mode. In bidirectional mode, the level of the signal on a Pn_m pin can be read from PPRn.PPRn_m. Access: PBDCn, APBDCn: These registers can be read or written in 16- bit units. JPBDC0: This register can be read or written in 8-bit units. Address: PBDCn: <PORTn_base> + 4100H + n × 4 (n = 0, 8, 9, 10, 11) APBDCn: <PORTn_base> + 41C8H (n = 0) JPBDC0: <JPORT0_base> + 0410H*1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PBDC n_15 PBDC n_14 PBDC n_13 PBDC n_12 PBDC n_11 PBDC n_10 PBDC n_9 PBDC n_8 PBDC n_7 PBDC n_6 PBDC n_5 PBDC n_4 PBDC n_3 PBDC n_2 PBDC n_1 PBDC n_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2C.10, Port (General I/O) Function Overview: Table 2C.40, Control Registers (JP0), Table 2C.42, Control Registers (P0), Table 2C.44, Control Registers (P8), Table 2C.46, Control Registers (P9), Table 2C.48, Control Registers (P10), Table 2C.50, Control Registers (P11) and Table 2C.52, Control Registers (AP0). Table 2C.26 PBDCn Register Contents Bit Position Bit Name Function 15 to 0 PBDCn[15:0] Enables/disables bidirectional mode of the corresponding pin. 0: Bidirectional mode disabled 1: Bidirectional mode enabled CAUTION When the Pn_m port is used for the alternative output function (PMCn.PMCn_m = 1, PMn.PMn_m = 0), the level of the Pn_m pin can be read from PPRn.PPRn_m by enabling the bidirectional mode (PBDCn.PBDCn_m = 1). However, output of that alternative output function is input to the alternative input function of the same pin (the alternative input function set by PFCn.PFCn_m, PFCEn.PFCEn_m, and PFCAEn.PFCAEn_m). If the alternative input function in question is being used by another pin, the alternative input function is not guaranteed. NOTE The control bits of the JTAG port bidirection control register (JPBDC0) are JPBDC0_[7:0].

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 476 of 4535 Dec 26, 2018 2C.9.3.2 PPRn / APPRn / JPPR0 — Port Pin Read Register This register reflects the actual level of the Pn_m pin, whether it is the value of the Pn.Pn_m bit or the level of an alternative output function. Access: PPRn, APPRn: These registers are read-only registers that can be read in 16-bit units. JPPR0: This register is a read-only register that can be read in 8-bit units. Address: PPRn: <PORTn_base> + 0200H + n × 4 (n = 0, 8, 9, 10, 11) APPRn: <PORTn_base> + 02C8H (n = 0) JPPR0: <JPORT0_base> + 0020H*1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PPR n_15 PPR n_14 PPR n_13 PPR n_12 PPR n_11 PPR n_10 PPR n_9 PPR n_8 PPR n_7 PPR n_6 PPR n_5 PPR n_4 PPR n_3 PPR n_2 PPR n_1 PPR n_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R R R R R R R R R R R R R R R R Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2C.10, Port (General I/O) Function Overview: Table 2C.40, Control Registers (JP0), Table 2C.42, Control Registers (P0), Table 2C.44, Control Registers (P8), Table 2C.46, Control Registers (P9), Table 2C.48, Control Registers (P10), Table 2C.50, Control Registers (P11) and Table 2C.52, Control Registers (AP0). Table 2C.27 PPRn Register Contents Bit Position Bit Name Function 15 to 0 PPRn_[15:0] The Pn_m Pin, Pn.Pn_m value or alternative function output. NOTES 1. For the read values of the PPRn register, see Section 2C.7.4, Pin Data Input/Output. 2. The control bits of the JTAG port pin read register (JPPR0) are JPPR0_[7:0].

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 477 of 4535 Dec 26, 2018 2C.9.3.3 Pn / APn / JP0 — Port Register This register holds the Pn.Pn_m data to be output via the related Pn_m port in output port mode (PMCn.PMCn_m = 0 and PMn.PMn_m = 0). Access: Pn, APn: These registers can be read or written in 16-bit units. JP0: This register can be read or written in 8-bit units. Address: Pn: <PORTn_base> + 0000H + n × 4 (n = 0, 8, 9, 10, 11) APn: <PORTn_base> + 00C8H (n = 0) JP0: <JPORT0_base> + 0000H*1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Pn_15 Pn_14 Pn_13 Pn_12 Pn_11 Pn_10 Pn_9 Pn_8 Pn_7 Pn_6 Pn_5 Pn_4 Pn_3 Pn_2 Pn_1 Pn_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2C.10, Port (General I/O) Function Overview: Table 2C.40, Control Registers (JP0), Table 2C.42, Control Registers (P0), Table 2C.44, Control Registers (P8), Table 2C.46, Control Registers (P9), Table 2C.48, Control Registers (P10), Table 2C.50, Control Registers (P11) and Table 2C.52, Control Registers (AP0). Table 2C.28 Pn Register Contents Bit Position Bit Name Function 15 to 0 Pn_[15:0] Sets the output level of the Pn_m pin (m = 0 to 15). 0: Outputs low level 1: Outputs high level NOTE The control bits of the JTAG port register (JP0) are JP0_[7:0].

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 478 of 4535 Dec 26, 2018 2C.9.3.4 PNOTn / APNOTn / JPNOT0 — Port NOT Register This register allows the Pn_m bit of the port register Pn to be inverted without directly writing to Pn. Access: PNOTn, APNOTn: These registers are write-only registers that can be written in 16-bit units. When read, 0000H is returned. JPNOT0: This register is a write-only register that can be written in 8-bit units. When read, 00H is returned. Address: PNOTn: <PORTn_base> + 0700H + n × 4 (n = 0,8, 9, 10, 11) APNOTn: <PORTn_base> + 07C8H (n = 0) JPNOT0: <JPORT0_base> + 0070H*1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PNOT n_15 PNOT n_14 PNOT n_13 PNOT n_12 PNOT n_11 PNOT n_10 PNOT n_9 PNOT n_8 PNOT n_7 PNOT n_6 PNOT n_5 PNOT n_4 PNOT n_3 PNOT n_2 PNOT n_1 PNOT n_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W W W W W W W W W W W W W W W W W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2C.10, Port (General I/O) Function Overview: Table 2C.40, Control Registers (JP0), Table 2C.42, Control Registers (P0), Table 2C.44, Control Registers (P8), Table 2C.46, Control Registers (P9), Table 2C.48, Control Registers (P10), Table 2C.50, Control Registers (P11) and Table 2C.52, Control Registers (AP0). Table 2C.29 PNOTn Register Contents Bit Position Bit Name Function 15 to 0 PNOTn_[15:0] Specifies if Pn.Pn_m is inverted. 0: Pn.Pn_m is not inverted (Pn_m → Pn_m) 1: Pn.Pn_m is inverted ( Pn_m → Pn_m) NOTE The control bits of the JTAG port NOT register are JPNOT0_[7:0].

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 479 of 4535 Dec 26, 2018 2C.9.3.5 PSRn / APSRn / JPSR0 — Port Set/Reset Register This register provides an alternative method to write data to the Pn register. The upper 16 bits of PSRn act as a mask which specifies whether or not the value Pn.Pn_m is set by the corresponding bit in the lower 16 bits of PSRn. Access: PSRn, APSRn: These registers can be read or written in 32-bit units. Bits 31 to 16 are always read as 0000H. Reading bits 15 to 0 returns the value of registers Pn and APn. JPSR0: This register can be read or written in 32-bit units. Bits 31 to 8 are always read as 000000H. Reading bits 7 to 0 returns the value of register JP0. Address: PSRn: <PORTn_base> + 0100H + n × 4 (n = 0, 8, 9, 10, 11) APSRn: <PORTn_base> + 01C8H (n = 0) JPSR0: <JPORT0_base> + 0010H*1 Value after reset: 0000 0000H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PSR n_31 PSR n_30 PSR n_29 PSR n_28 PSR n_27 PSR n_26 PSR n_25 PSR n_24 PSR n_23 PSR n_22 PSR n_21 PSR n_20 PSR n_19 PSR n_18 PSR n_17 PSR n_16 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSR n_15 PSR n_14 PSR n_13 PSR n_12 PSR n_11 PSR n_10 PSR n_9 PSR n_8 PSR n_7 PSR n_6 PSR n_5 PSR n_4 PSR n_3 PSR n_2 PSR n_1 PSR n_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2C.10, Port (General I/O) Function Overview: Table 2C.40, Control Registers (JP0), Table 2C.42, Control Registers (P0), Table 2C.44, Control Registers (P8), Table 2C.46, Control Registers (P9), Table 2C.48, Control Registers (P10), Table 2C.50, Control Registers (P11) and Table 2C.52, Control Registers (AP0). Table 2C.30 PSRn Register Contents Bit Position Bit Name Function 31 to 16 PSRn_[31:16] Specifies whether the value of the corresponding lower bit PSRn_m (PSRn_[15:0]) is written to Pn_m. 0: Pn_m is not affected by PSRn_m 1: Pn_m is PSRn_m Example: If PSRn.PSRn_31 = 1, the value of bit PSRn.PSRn_15 is written to bit Pn.Pn_15. 15 to 0 PSRn_[15:0] Specifies the Pn_m value if the corresponding upper bit (PSRn_[31:16]) PSRn_m is 1. 0: Pn_m = 0 1: Pn_m = 1 NOTE The control bits of the JTAG port set/reset register (JPSR0) are JPSR0_[31:0].

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 480 of 4535 Dec 26, 2018 2C.9.4 Configuration of Electrical Characteristics 2C.9.4.1 PUn / JPU0 — Pull-Up Option Register This register specifies whether an internal pull-up resistor is connected to an input pin. Access: PUn: This register can be read or written in 16-bit units. JPU0: This register can be read or written in 8-bit units. Address: PUn: <PORTn_base> + 4300H + n × 4 (n = 0, 8, 9, 10, 11) JPU0: <JPORT0_base> + 0430H*1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PUn_15 PUn_14 PUn_13 PUn_12 PUn_11 PUn_10 PUn_9 PUn_8 PUn_7 PUn_6 PUn_5 PUn_4 PUn_3 PUn_2 PUn_1 PUn_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2C.10, Port (General I/O) Function Overview: Table 2C.40, Control Registers (JP0), Table 2C.42, Control Registers (P0), Table 2C.44, Control Registers (P8), Table 2C.46, Control Registers (P9), Table 2C.48, Control Registers (P10), and Table 2C.50, Control Registers (P11). Table 2C.31 PUn Register Contents Bit Position Bit Name Function 15 to 0 PUn_[15:0] Specifies whether an internal pull-up resistor is connected to the corresponding pin. 0: No internal pull-up resistor connected 1: An internal pull-up resistor connected NOTES 1. If a pin is configured such that both an internal pull-up resistor (PUn.PUn_m = 1) and pull-down resistor (PDn.PDn_m = 1) are connected, the pull-down resistor is automatically selected and the pull-up resistor is not connected. 2. The pull-up resistor has no effect when the pin is operated in output mode. 3. The control bits of the JTAG pull-up option register (JPU0) are JPU0_[7:0].

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 481 of 4535 Dec 26, 2018 2C.9.4.2 PDn / JPD0 — Pull-Down Option Register This register specifies whether to connect an internal pull-down resistor to an input pin. Access: PDn: This register can be read or written in 16-bit units. JPD0: This register can be read or written in 8-bit units. Address: PDn: <PORTn_base> + 4400H + n × 4 (n = 0, 8, 9, 10, 11) JPD0: <JPORT0_base> + 0440H*1 Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PDn_15 PDn_14 PDn_13 PDn_12 PDn_11 PDn_10 PDn_9 PDn_8 PDn_7 PDn_6 PDn_5 PDn_4 PDn_3 PDn_2 PDn_1 PDn_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2C.10, Port (General I/O) Function Overview: Table 2C.40, Control Registers (JP0), Table 2C.42, Control Registers (P0), Table 2C.44, Control Registers (P8), Table 2C.46, Control Registers (P9), Table 2C.48, Control Registers (P10), and Table 2C.50, Control Registers (P11). Table 2C.32 PDn Register Contents Bit Position Bit Name Function 15 to 0 PDn_[15:0] Specifies whether to connect an internal pull-down resistor to the corresponding pin. 0: No internal pull-down resistor connected 1: An internal pull-down resistor connected NOTES 1. If a pin is configured such that both an internal pull-up resistor (PUn.PUn_m = 1) and pull-down resistor (PDn.PDn_m = 1) are connected, the pull-down resistor is automatically selected and the pull-up resistor is not connected. 2. The internal pull-down resistor has no effect when the pin is operated in output mode. 3. The control bits of the JTAG pull-down option register (JPD0) are JPD0_[7:0].

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 482 of 4535 Dec 26, 2018 2C.9.4.3 PDSCn / JPDSC0 — Port Drive Strength Control Register This register specifies the output driver strength of the port pin. This function selects the fast mode (high drive strength) or slow mode (low drive strength) of the output buffer. The correct write sequence using the PPCMDn and JPPCMD0 registers is required in order to update this register. For details, see Section 5, Write-Protected Registers. Regarding the alternative functions for which the PDSC register needs to be set, see Section 2C.11.3.3, Output Buffer Control (PDSC). Access: PDSCn, JPDSC0: These registers can be read or written in 32- bit units. Address: PDSCn: <PORTn_base> + 4600H + n × 4 (n = 0, 10, 11) JPDSC0: <JPORT0_base> + 0460H*1 Value after reset: 0000 0000H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R R R R R R R R R R R R R R R R Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PDSC n_15 PDSC n_14 PDSC n_13 PDSC n_12 PDSC n_11 PDSC n_10 PDSC n_9 PDSC n_8 PDSC n_7 PDSC n_6 PDSC n_5 PDSC n_4 PDSC n_3 PDSC n_2 PDSC n_1 PDSC n_0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2C.10, Port (General I/O) Function Overview: Table 2C.40, Control Registers (JP0), Table 2C.42, Control Registers (P0), Table 2C.48, Control Registers (P10), and Table 2C.50, Control Registers (P11). Table 2C.33 PDSCn Register Contents Bit Position Bit Name Function 31 to 16 Reserved When read, the value after reset is returned. When writing, write the value after reset. 15 to 0 PDSCn_[15:0] Specifies the port drive strength of the output buffer of the port pin. 0: Lower drive strength (when the frequency output from the pin is 10 MHz or below) 1: High drive strength (when the frequency output from the pin is 40 MHz or less). NOTE The control bits of the JTAG port drive strength control register (JPDSC0) are JPDSC0_[31:0].

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 483 of 4535 Dec 26, 2018 2C.9.4.4 PODCn / JPODC0 — Port Open Drain Control Register This register selects push-pull or open-drain as output buffer function. The correct write sequence using the PPCMDn and JPPCMD0 registers is required in order to update this register. For details, see Section 5, Write- Protected Registers. Access: PODCn, JPODC0: These registers can be read or written in 32- bit units. Address: PODCn: <PORTn_base> + 4500H + n × 4 (n = 0, 8, 9, 10, 11) JPODC0: <JPORT0_base> + 0450H*1 Value after reset: 0000 0000H*2 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R R R R R R R R R R R R R R R R Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PODC n_15 PODC n_14 PODC n_13 PODC n_12 PODC n_11 PODC n_10 PODC n_9 PODC n_8 PODC n_7 PODC n_6 PODC n_5 PODC n_4 PODC n_3 PODC n_2 PODC n_1 PODC n_0 Value after reset 0 0 0 0 0 0 0 0 0 0*3 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2C.10, Port (General I/O) Function Overview: Table 2C.40, Control Registers (JP0), Table 2C.42, Control Registers (P0), Table 2C.44, Control Registers (P8), Table 2C.46, Control Registers (P9), Table 2C.48, Control Registers (P10), and Table 2C.50, Control Registers (P11). Note 2. The PODC8 register is as follows. When the OPBT0.RESETOUTEN = 1, the PODC8 register is 0000 0040H. When the OPBT0.RESETOUTEN = 0, the PODC8 register is 0000 0000H. Note 3. The PODC8_6 bit is as follows. When the OPBT0.RESETOUTEN = 1, the PODC8_6 bit is 1. When the OPBT0.RESETOUTEN = 0, the PODC8_6 bit is 0. Table 2C.34 PODCn Register Contents Bit Position Bit Name Function 31 to 16 Reserved When read, the value after reset is returned. When writing, write the value after reset. 15 to 0 PODCn_[15:0] Specifies the output buffer function. 0: Push-pull 1: Open-drain NOTE The control bits of the JTAG port open drain control register (JPODC0) are JPODC0_[31:0].

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 484 of 4535 Dec 26, 2018 2C.9.4.5 PISn/JPIS0 — Port Input Buffer Selection Register This register specifies the input buffer characteristics. Access: PISn: This register can be read or written in 16-bit units. JPIS0: This register can be read or written in 8-bit units. Address: PISn: <PORTn_base> + 4700H + n × 4 (n = 0, 8, 9, 10, 11) JPIS0: <JPORT0_base> + 0470H*1 Value after reset: FFFFH Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PIS n_15 PIS n_14 PIS n_13 PIS n_12 PIS n_11 PIS n_10 PISn_9 PISn_8 PISn_7 PISn_6 PISn_5 PISn_4 PISn_3 PISn_2 PISn_1 PISn_0 Value after reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2C.10, Port (General I/O) Function Overview: Table 2C.40, Control Registers (JP0), Table 2C.42, Control Registers (P0), Table 2C.44, Control Registers (P8), Table 2C.46, Control Registers (P9), Table 2C.48, Control Registers (P10), and Table 2C.50, Control Registers (P11). Table 2C.35 PISn Register Contents Bit Position Bit Name Function 15 to 0 PISn_[15:0] Specifies the input buffer Characteristics: 0: Type 1 (SHMT1) 1: Type 2 (SHMT4) NOTES 1. Details of the definition of type 1 and type 2 are given in Section 2C.11.3.2, Input Buffer Control (PISn/JPIS0, JPISA0). For details, also see Section 47C, Electrical Characteristics of RH850/F1KM-S1 for input buffer characteristics. 2. The control bits of the JTAG port input buffer selection register (JPIS0) are JPIS0_[7:0]

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 485 of 4535 Dec 26, 2018 2C.9.4.6 JPISA0 — Port Input Buffer Selection Advanced Register This register specifies the input buffer characteristics. Access: JPISA0: This register can be read or written in 8-bit units. Address: JPISA0: <JPORT0_base> + 04A0H*1 Value after reset: 00H Bit 7 6 5 4 3 2 1 0 Value after reset 0 0 0 0 0 0 0 0 R/W R R R R R/W R/W R R/W Note 1. The valid bit positions (value for the index m) vary depending on the number of pins for each device. See the following tables in Section 2C.10, Port (General I/O) Function Overview: Table 2C.40, Control Registers (JP0). Table 2C.36 JPISA0 Register Contents Bit Position Bit Name Function 7 to 4, 1 Reserved When read, the value after reset is returned. When writing, write the value after reset. 3, 2, 0 JPISA0_[3, 2, 0] Specifies the input buffer characteristics: 0: Type 2 (SHMT4) 1: Type 5 (TTL) Table 2C.37 JTAG Port Input Selection Advanced Register Contents JPISA0 JPIS0 Function 0 0 Type 1 input buffer is selected (SHMT1) Details of the definition of type 2 and type 5 are given in Section 2C.11.3.2, Input Buffer Control (PISn/JPIS0, JPISA0). For details, also see Section 47C, Electrical Characteristics of RH850/F1KM-S1 for input buffer characteristics.

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 486 of 4535 Dec 26, 2018 2C.9.5 Port Register Protection RH850/F1KM has Port Protection Command Registers (PPCMDn) and Port Protection Status Registers (PPROTSn) which implement the Port Protection Cluster Function. For details on the registers, see Section 5, Write -Protected Registers. 2C.9.6 Flowchart Examples for Port Settings Examples of the port settings are shown in the flowchart below. CAUTION If the port is set to the PIPCn.PIPCn_m bit = 0 and alternative output mode, the port might briefly enter alternative input mode. This will occur between when the PMCn.PMCn_m bit is set to 1 and when the PMn.PMn_m bit is set to 0. If an interrupt- related signal is specified as an alternate function of the port, the mode will temporarily become the alternative input mode, so either disable the interrupt in question, or specify that the interrupt is ignored.

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 487 of 4535 Dec 26, 2018 2C.9.6.1 Batch Setting An example of specifying batch port group settings is shown in the flowchart below. Specify PIBCn.PIBCn_m bit = 0 Specify PBDCn.PBDCn_m bit = 0 Specify PMn.PMn_m bit = 1 Specify PMCn.PMCn_m bit = 0 Specify PIPCn.PIPCn_m bit = 0 Specify PIPCn.PIPCn_m bit Specify Pn.Pn_m bit Specify PMCn.PMCn_m bit Specify PMn.PMn_m bit Specify PIBCn.PIBCn_m bit Specify PFCn.PFCn_m, PFCEn.PFCEn_m, PFCAEn.PFCAEn_m bits Set port filters*2 Specify PDSCn.PDSCn_m, PODCn.PODCn_m, PBDCn.PBDCn_m, PUn.PUn_m, PDn.PDn_m, PISn.PISn_m bits PISAn.PISAn_m bits*1 Port initialization: Set the initial port values. (The port is set to input mode and the input buffer is disabled.) Port settings: Set appropriate values. Alternative input mode is entered when the PIPCn.PIPCn_m bit is 0 and the PMCn.PMCn_m bit is START Note 1. There is no PISAn.PISAn_m bit in RH850/F1KM-S1. Note 2. While PMC = 0, an interrupt may be triggered during the configuration of the port registers under the following conditions: For NMI, INTP7 and INTP8 interrupt requests:

• The port filter is set to low level detection.
• The port filter is set to rising edge or both edge detection and the PMC register is set to 1 while the input terminal is at high level. For INTP0-5 and INTP10-12 interrupt requests:
• The port filter is set to high level detection.
• The port filter is set to falling edge or both edges detection and the PMC register is set to 1 while the input terminal is at low level. In order to avoid the unintended interrupt occurrence, use the following configuration sequence: 1. Configure the PMC register. 2. Wait for the period of pulse rejection. 3. Configure the edge/level detection register. Figure 2C.6 Example of Port Settings (When Specified in Batch)

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 488 of 4535 Dec 26, 2018 2C.9.6.2 Individual Settings An example of specifying individual port settings is shown in the flowchart below. Specify PIBCn.PIBCn_m bit = 0 Specify PBDCn.PBDCn_m bit = 0 Specify PMn.PMn_m bit = 1 Specify PMCn.PMCn_m bit = 0 Specify PIPCn.PIPCn_m bit = 0 Specify PIBCn.PIBCn_m bit = 1 Specify Pn.Pn_m bit Specify PUn.PUn_m, PDn.PDn_m bits Set port filters Specify PDSCn.PDSCn_m, PODCn.PODCn_m, PBDCn.PBDCn_m bits Output mode Input mode Input or output? Specify PISn.PISn_m bits PISAn.PISAn_m bits *1 Specify PMn.PMn_m bit = 0 Port initialization: Set the initial port values. (The port is set to input mode and the input buffer is disabled.) Port settings: Set appropriate values. START Note 1. There is no PISAn.PISAn_m bit in RH850/F1KM-S1. Figure 2C.7 Example of Port Settings (in Port Mode)

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 489 of 4535 Dec 26, 2018 (1) With IP Control Specify PIBCn.PIBCn_m bit = 0 Specify PBDCn.PBDCn_m bit = 0 Specify PMn.PMn_m bit = 1 Specify PMCn.PMCn_m bit = 0 Specify PIPCn.PIPCn_m bit = 0 Specify PIPCn.PIPCn_m bit = 1 Specify PMCn.PMCn_m bit = 1 Specify PISn.PISn_m bits PISAn.PISAn_m bits*1 Set port filters Specify PUn.PUn_m, PDn.PDn_m bits Input function port settings: Set appropriate values. Alternative mode (with IP control) port settings: Set appropriate values. Output function port settings: Set appropriate values. Specify PFCn.PFCn_m, PFCEn.PFCEn_m, PFCAEn.PFCAEn_m bits Specify PDSCn.PDSCn_m, PODCn.PODCn_m, PBDCn.PBDCn_m bits Port initialization: Set the initial port values. (The port is set to input mode and the input buffer is disabled.) START Note 1. There is no PISAn.PISAn_m bit in RH850/F1KM-S1. Figure 2C.8 Example of Port Settings (in Alternative Mode)

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 490 of 4535 Dec 26, 2018 (2) Without IP Control Specify PIBCn.PIBCn_m bit = 0 Specify PBDCn.PBDCn_m bit = 0 Specify PMn.PMn_m bit = 1 Specify PMCn.PMCn_m bit = 0 Specify PIPCn.PIPCn_m bit = 0 Specify PUn.PUn_m, PDn.PDn_m bits Specify PFCn.PFCn_m, PFCEn.PFCEn_m, PFCAEn.PFCAEn_m bits Specify PDSCn.PDSCn_m, PODCn.PODCn_m, PBDCn.PBDCn_m bits Specify PISn.PISn_m bit PISAn.PISAn_m bits *1 Specify PMn.PMn_m bit = 0Specify PMCn.PMCn_m bit = 1 Specify PFCn.PFCn_m, PFCEn.PFCEn_m, PFCAEn.PFCAEn_m bits Specify PMCn.PMCn_m bit = 1 Alternative input mode Set port filters*2 Output mode Input mode Input or output? Port initialization: Set the initial port values. (The port is set to input mode and the input buffer is disabled.) Port settings: Set appropriate values. START Note 1. There is no PISAn.PISAn_m bit in RH850/F1KM-S1. Note 2. While PMC = 0, an interrupt may be triggered during the configuration of the port registers under the following conditions: For NMI, INTP7 and INTP8 interrupt requests:

• The port filter is set to low level detection.
• The port filter is set to rising edge or both edge detection and the PMC register is set to 1 while the input terminal is at high level. For INTP0-5 and INTP10-12 interrupt requests:
• The port filter is set to high level detection.
• The port filter is set to falling edge or both edges detection and the PMC register is set to 1 while the input terminal is at low level. In order to avoid the unintended interrupt occurrence, use the following configuration sequence: 1. Configure the PMC register. 2. Wait for the period of pulse rejection. 3. Configure the edge/level detection register. Figure 2C.9 Example of Port Settings (in Alternative Mode)

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 491 of 4535 Dec 26, 2018 2C.10 Port (General I/O) Function Overview This section explains the port (general I/O) functions and all the functions assigned to the ports. See the following pages for details. In addition, whether the port mode is alternative mode or not can be selected by PMCn register setting. When PMCn.PMCn_m = 1, alternative functions are selected by the PFCn, PFCEn, and P FCAEn registers. Table 2C.38 Port Function Device Port Pin Name Size Direction Power Domain Special Alternative Function 48 Pins 64 Pins 80 Pins 100 Pins JTAG Port 0 JP0_0 - 5 6 bits In/Out AWO JTAG, LPD     Port 0 P0_0 - 3 4 bits In/Out AWO  — — — P0_0 - 12 13 bits — —  — P0_0 - 14 15 bits — — —  Port 8 P8_0 - 1 2 bits In/Out AWO ADCA0 (10-bit resolution)  — — — P8_0 - 12 13 bits — — —  P8_6 1 bit In/Out AWO RESETOUT —    Port 9 P9_0 - 1 2 bits In/Out ISO ADCA0 (10-bit resolution)  — — — Port 10 P10_0 - 10 11 bits In/Out ISO  — — — P10_0 - 14 15 bits —  — — P10_0 - 15 16 bits — —   Port 11 P11_0 - 4 5 bits In/Out ISO — —  — Analog Port 0 AP0_0 - 7 8 bits In/Out AWO ADCA0 (12/10-bit resolution)  — — — AP0_0 - 15 16 bits — — — 

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 492 of 4535 Dec 26, 2018 2C.10.1 JTAG Port 0 (JP0) 2C.10.1.1 Alternative Function The following alternative functions are available when JTAG port 0 is configured as a general -purpose I/O port by setting OPJTAG[1:0] on the corresponding option byte to 00B. Table 2C.39 JTAG Port 0 (JP0) Port Mode (JPMC 0_m = 0) Alternative Mode (JPMC0_m = 1) ADC Special function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 48 Pins Pins Pins 100 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output JP0_0*1 INTP0 TAUJ2I0 TAUJ2O0 FPDR FPDT DCUTDI/ LPDI/ LPDIO 15 19 23 28 JP0_1 INTP1 TAUJ0I0 TAUJ0O0 FPDT DCUTDO/ LPDO 14 18 22 27 JP0_2 INTP2 TAUJ0I1 TAUJ0O1 FPCK DCUTCK/ LPDCLK 13 17 21 26 JP0_3 INTP3 CSCXFOUT TAUJ0I2 TAUJ0O2 DCUTMS 12 16 20 25 JP0_4 DCUTRST 11 15 19 24 JP0_5 NMI RTCA0OUT TAUJ0I3 TAUJ0O3 DCURDY / LPDCLKOUT 10 14 18 23 Note 1. In LPD (1 pin) mode, the JP0_0 output buffer state is Open-drain. CAUTION The behavior and performance are not guaranteed when alternative functions are not assigned to the register.

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 493 of 4535 Dec 26, 2018 2C.10.1.2 Control Registers Table 2C.40 Control Registers (JP0) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 48 Pins 64 Pins 80 Pins 100 Pins JP0 JTAG port register 0 8 5-0 R/W 0000H 00H     JPSR0 JTAG port set/reset register 0 32 21-16, 5-0 R/W 0010H 0000 0000H     JPPR0 JTAG port pin read register 0 8 5-0 R 0020H 00H     JPM0 JTAG port mode register 0 8 5-0 R/W 0030H FFH     JPMC0 JTAG port mode control register 0 8 5, 3-0 R/W 0040H 00H     JPFC0 JTAG port function control register 0 8 5, 3-0 R/W 0050H 00H     JPFCE0 JTAG port function control expansion register 0 8 2-0 R/W 0060H 00H     JPNOT0 JTAG port NOT register 0 8 5-0 W 0070H 00H     JPMSR0 JTAG port mode set/reset register 0 32 21-16, 5-0 R/W 0080H 0000 FFFFH     JPMCSR0 JTAG port mode control set/reset register 0 32 21, 19-16, 5, 3-0 R/W 0090H 0000 0000H     JPIBC0 JTAG port input buffer control register 0 8 5-0 R/W 0400H 00H     JPBDC0 JTAG port bidirection control register 0 8 5-0 R/W 0410H 00H     JPU0 Pull-up option register 0 8 5-0 R/W 0430H 00H     JPD0 Pull-down option register 0 8 5-0 R/W 0440H 00H     JPODC0 JTAG port open drain control register 0 32 5-0 R/W 0450H 0000 0000H     JPDSC0 JTAG port drive strength control register 0 32 5, 3-1 R/W 0460H 0000 0000H     JPIS0 JTAG port input buffer selection register 0 8 5, 3-0 R/W 0470H FFH     JPISA0 JTAG port input buffer selection advanced register 0 8 3, 2, 0 R/W 04A0H 00H     JPPROTS0 JTAG port protection status register 0 32 0 R 04B0H 0000 0000H     JPPCMD0 JTAG port protection command register 0 32 7-0 W 04C0H xxxx xx00H     Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 494 of 4535 Dec 26, 2018 2C.10.2 Port 0 (P0) 2C.10.2.1 Alternative Function Table 2C.41 Port 0 (P0) Port Mode (PMC0_ m = 0) Alternative Mode (PMC0_m = 1) ADC Special function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 48 Pins Pins Pins 100 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output P0_0 TAUD0I2 TAUD0O2 RLIN20RX CAN0TX PWGA10O CSIH0SSI DPO TAUJ2I1 TAUJ2O1 4 4 6 6 P0_1 TAUD0I4 TAUD0O4 CAN0RX/ INTP0 RLIN20TX INTP0 PWGA11O CSIH0SI APO TAUJ2I2 TAUJ2O2 CAN0RX 5 5 7 7 P0_2 TAUD0I6 TAUD0O6 RLIN30TX PWGA12O CSIH0SC INTP1 DPO TAUJ2I3 TAUJ2O3 6 — — — TAUD0I6 TAUD0O6 CAN1RX/ INTP1 RLIN30TX PWGA12O CSIH0SC INTP1 DPO TAUJ2I3 TAUJ2O3 CAN1RX — 6 8 8 P0_3 TAUD0I8 TAUD0O8 RLIN30RX/ INTP10 DPIN1 CSIH0SO INTP10 TAUJ1I0 TAUJ1O0 RLIN30RX 7 — — — TAUD0I8 TAUD0O8 RLIN30RX/ INTP10 CAN1TX DPIN1 PWGA13O CSIH0SO INTP10 TAUJ1I0 TAUJ1O0 RLIN30RX — 7 9 9 P0_4 RLIN31RX/ INTP11 CAN2TX INTP11 PWGA10O SELDP0 DPIN8 RLIN31RX — 9 — — RLIN31RX/ INTP11 CAN2TX INTP11 PWGA10O CSIH1SI SELDP0 DPIN8 TAUB0I12 TAUB0O12 RLIN31RX — — 11 11 P0_5 CAN2RX/ INTP2 RLIN31TX DPIN9 SELDP1 CAN2RX — 10 — — CAN2RX/ INTP2 RLIN31TX DPIN9 SELDP1 CSIH1SO TAUB0I14 TAUB0O14 CAN2RX — — 12 12 P0_6 INTP2 DPIN10 SELDP2 — 11 — — INTP2 DPIN10 SELDP2 CSIH1SC — — 13 — INTP2 DPIN10 SELDP2 CSIH1SC PWGA35O — — — 13 P0_7 RLIN21RX DPIN5 CSCXFOUT CSIH1RYI CSIH1RYO TAUB0I0 TAUB0O0 — — 34 — RLIN21RX DPIN5 CSCXFOUT CSIH1RYI CSIH1RYO TAUB0I0 TAUB0O0 CAN3RX/ INTP3 CAN3RX — — — 40 P0_8 RLIN21TX DPIN6 CSIH0CSS6 CSIH1SSI TAUB0I2 TAUB0O2 — — 33 — RLIN21TX DPIN6 CSIH0CSS6 CSIH1SSI TAUB0I2 TAUB0O2 CAN3TX — — — 39

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 495 of 4535 Dec 26, 2018 Table 2C.41 Port 0 (P0) Port Mode (PMC 0_m = 0) Alternative Mode (PMC0_m = 1) AD C Special function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 48 Pins Pins Pins 100 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output P0_9 INTP12 CSIH1CSS0 DPIN7 TAUB0I4 TAUB0O4 — — 32 — INTP12 CSIH1CSS0 DPIN7 RLIN22RX TAUB0I4 TAUB0O4 CAN4RX/ INTP4 CAN4RX — — — 38 P0_10 INTP3 CSIH1CSS1 DPIN11 TAUB0I6 TAUB0O6 — — 31 — INTP3 CSIH1CSS1 DPIN11 RLIN22TX TAUB0I6 TAUB0O6 CAN4TX — — — 37 P0_11 RIIC0SDA CSIH1CSS2 TAUB0I8 TAUB0O8 — — 14 — RIIC0SDA DPIN12 CSIH1CSS2 TAUB0I8 TAUB0O8 PWGA34O — — — 14 P0_12 RIIC0SCL TAUB0I10 TAUB0O10 CSIG0SI — — 15 — RIIC0SCL DPIN13 PWGA45O TAUB0I10 TAUB0O10 CSIG0SI — — — 15 P0_13 RLIN32RX/ INTP12 INTP12 PWGA46O TAUB0I12 TAUB0O12 CSIG0SO CAN5RX/ INTP5 RLIN32RX CAN5RX — — — 16 P0_14 RLIN32TX PWGA47O TAUB0I14 TAUB0O14 CSIG0SC CAN5TX — — — 17 CAUTION The behavior and performance are not guaranteed when alternative functions are not assigned to the register.

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 496 of 4535 Dec 26, 2018 2C.10.2.2 Control Registers Table 2C.42 Control Registers (P0) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 48 Pins 64 Pins 80 Pins 100 Pins P0 Port register 0 16 3-0 R/W 0000H 0000H  ― ― ― 6-0 ―  ― ― 12-0 ― ―  ― 14-0 ― ― ―  PSR0 Port set/reset register 0 32 19-16, 3-0 R/W 0100H 0000 0000H  ― ― ― 22-16, 6-0 ―  ― ― PPR0 Port pin read register 0 16 3-0 R 0200H 0000H  ― ― ― 6-0 ―  ― ― 12-0 ― ―  ― 14-0 ― ― ―  PM0 Port mode register 0 16 3-0 R/W 0300H FFFFH  ― ― ― 6-0 ―  ― ― 12-0 ― ―  ― 14-0 ― ― ―  PMC0 Port mode control register 0 16 3-0 R/W 0400H 0000H  ― ― ― 6-0 ―  ― ― 12-0 ― ―  ― 14-0 ― ― ―  PFC0 Port function control register 0 16 3-0 R/W 0500H 0000H  ― ― ― 6-0 ―  ― ― 12-0 ― ―  ― 14-0 ― ― ―  PFCE0 Port function control expansion register 0 16 3-0 R/W 0600H 0000H  ― ― ― 5-0 ―  ― ― 12-0 ― ―  ― 14-0 ― ― ―  PNOT0 Port NOT register 0 16 3-0 W 0700H 0000H  ― ― ― 6-0 ―  ― ― 12-0 ― ―  ― 14-0 ― ― ―  PMSR0 Port mode set/reset register 0 32 19-16, 3-0 R/W 0800H 0000 FFFFH  ― ― ― 22-16, 6-0 ―  ― ― PMCSR0 Port mode control set/reset register 0 32 19-16, 3-0 R/W 0900H 0000 0000H  ― ― ― 22-16, 6-0 ―  ― ― PFCAE0 Port function control additional expansion register 0 16 3-0 R/W 0A00H 0000H  ― ― ― 5-0 ―   ― PIBC0 Port input buffer control register 0 16 3-0 R/W 4000H 0000H  ― ― ― 6-0 ―  ― ― 12-0 ― ―  ― 14-0 ― ― ― 

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 497 of 4535 Dec 26, 2018 Table 2C.42 Control Registers (P0) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 48 Pins 64 Pins 80 Pins 100 Pins PBDC0 Port bidirection control register 0 16 3-0 R/W 4100H 0000H  ― ― ― 6-0 ―  ― ― 12-0 ― ―  ― 14-0 ― ― ―  PIPC0 Port IP control register 0 16 3, 2 R/W 4200H 0000H  ― ― ― 6, 5, 3, 2 ―   ― PU0 Pull-up option register 0 16 3-0 R/W 4300H 0000H  ― ― ― 6-0 ―  ― ― 12-0 ― ―  ― 14-0 ― ― ―  PD0 Pull-down option register 0 16 3-0 R/W 4400H 0000H  ― ― ― 6-0 ―  ― ― 12-0 ― ―  ― 14-0 ― ― ―  PODC0 Port open drain control register 0 32 3-0 R/W 4500H 0000 0000H  ― ― ― 6-0 ―  ― ― 12-0 ― ―  ― 14-0 ― ― ―  PDSC0 Port drive strength control register 0 32 3-0 R/W 4600H 0000 0000H  ― ― ― 6-0 ―  ― ― 12-0 ― ―  ― 14-0 ― ― ―  PIS0 Port input buffer selection register 0 16 3-0 R/W 4700H FFFFH  ― ― ― 6-0 ―  ― ― 12-0 ― ―  ― 14-0 ― ― ―  PPROTS0 Port protection status register 0 32 0 R 4B00H 0000 0000H     PPCMD0 Port protection command register 0 32 7-0 W 4C00H XXXX XX00H     Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 498 of 4535 Dec 26, 2018 2C.10.3 Port 8 (P8) 2C.10.3.1 Alternative Function Table 2C.43 Port 8 (P8) Port Mode (PMC8_m = Alternative Mode (PMC8_m = 1) ADC Special function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 48 Pins Pins Pins 100 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output P8_0 TAUJ0I0 TAUJ0O0 DPIN2 INTP4 CSIH0CSS0 RIIC1SDA SENT0RX ADCA0I0S 23 — — — TAUJ0I0 TAUJ0O0 DPIN2 PWGA14O INTP4 CSIH0CSS0 RIIC1SDA SENT0RX ADCA0I0S — 27 35 42 P8_1 TAPA0ESO TAUJ0O1 DPIN0 INTP5 RIIC1SCL SENT0SPCO ADCA0I1S 24 — — — TAPA0ESO TAUJ0O1 DPIN0 PWGA15O INTP5 RIIC1SCL SENT0SPCO ADCA0I1S — 28 — — TAPA0ESO TAUJ0O1 DPIN0 PWGA15O INTP5 CSIH1CSS3 RIIC1SCL SENT0SPCO ADCA0I1S — — 36 43 P8_2 TAUJ0I0 TAUJ0O0 DPIN2 CSIH0CSS0 PWGA22O ADCA0I4S — 13 — — TAUJ0I0 TAUJ0O0 DPIN2 CSIH0CSS0 INTP6 PWGA22O ADCA0I4S — — 17 19 P8_3 TAUJ0I1 TAUJ0O1 DPIN3 CSIH0CSS1 PWGA23O ADCA0I5S — 29 — — TAUJ0I1 TAUJ0O1 DPIN3 CSIH0CSS1 INTP7 PWGA23O ADCA0I5S — — 37 44 P8_4 TAUJ0I2 TAUJ0O2 DPIN4 CSIH0CSS2 ADCA0I6S — 30 — — TAUJ0I2 TAUJ0O2 DPIN4 CSIH0CSS2 INTP8 ADCA0I6S — — 38 — TAUJ0I2 TAUJ0O2 DPIN4 CSIH0CSS2 INTP8 PWGA36O ADCA0I6S — — — 45 P8_5 TAUJ0I3 TAUJ0O3 NMI CSIH0CSS3 ADCA0I7S — 31 39 — TAUJ0I3 TAUJ0O3 NMI CSIH0CSS3 PWGA37O ADCA0I7S — — — 46 P8_6 NMI RTCA0OUT ADCA0I8S RESETOUT — 32 — — NMI CSIH0CSS4 RTCA0OUT ADCA0I8S RESETOUT — — 40 — NMI CSIH0CSS4 PWGA38O RTCA0OUT ADCA0I8S RESETOUT — — — 47 P8_7 CSIH3CSS0 PWGA39O ADCA0SEL0 RTCA0OUT ADCA0I14S — — — 48 P8_8 CSIH3CSS1 PWGA40O ADCA0SEL1 ADCA0I15S — — — 49 P8_9 CSIH3CSS2 PWGA41O ADCA0SEL2 ADCA0I16S — — — 50 P8_10 CSIH3CSS3 DPIN14 PWGA42O ADCA0I17S — — — 20 P8_11 TAUJ1I2 TAUJ1O2 DPIN15 PWGA43O CSIH1CSS4 ADCA0I18S — — — 21 P8_12 TAUJ1I3 TAUJ1O3 DPIN16 PWGA44O CSIH1CSS5 ADCA0I19S — — — 22

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 499 of 4535 Dec 26, 2018 CAUTIONS 1. The behavior and performance are not guaranteed when alternative functions are not assigned to the register. 2. Use ADC functions with their initial settings. For details, see Table 2C.44, Control Registers (P8). 3. When the RESETOUT function is selected for the P8_6 pin, the P8_6 pin outputs a low-level as the RESETOUT signal while a reset is asserted and continues to output

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 500 of 4535 Dec 26, 2018 2C.10.3.2 Control Registers Table 2C.44 Control Registers (P8) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 48 Pins 64 Pins 80 Pins 100 Pins P8 Port register 8 16 1,0 R/W 0020H 0000H  — — — 6-0 —   — 12-0 — — —  PSR8 Port set/reset register 8 32 17,16,1,0 R/W 0120H 0000 0000H  — — — 22-16, 6-0 —   — 28-16,12-0 — — —  PPR8 Port pin read register 8 16 1,0 R 0220H 0000H  — — — 6-0 —   — 12-0 — — —  PM8 Port mode register 8 16 1,0 R/W 0320H FFBFH  — — — 6-0 —   — 12-0 — — —  PMC8 Port mode control register 8 16 1,0 R/W 0420H 0000H  — — — 6-0 —   — 12-0 — — —  PFC8 Port function control register 8 16 1,0 R/W 0520H 0000H  — — — 5-0 —   — 12-0 — — —  PFCE8 Port function control expansion register 8 16 1,0 R/W 0620H 0000H  — — — 6, 3-0 —  — — 6, 4-0 — —  — PNOT8 Port NOT register 8 16 1,0 W 0720H 0000H  — — — 6-0 —   — 12-0 — — —  PMSR8 Port mode set/reset register 8 32 17,16,1,0 R/W 0820H 0000 FFBFH  — — — 22-16, 6-0 —   — 28-16,12-0 — — —  PMCSR8 Port mode control set/reset register 8 32 17,16,1,0 R/W 0920H 0000 0000H  — — — 22-16, 6-0 —   — 28-16,12-0 — — —  PFCAE8 Port function control additional expansion register 8 16 1,0 R/W 0A20H 0000H     PIBC8 Port input buffer control register 8 16 1,0 R/W 4020H 0000H  — — — 6-0 —   — 12-0 — — —  PBDC8 Port bidirection control register 8 16 1,0 R/W 4120H 0000H  — — — 6-0 —   — 12-0 — — —  PU8 Pull-up option register 8 16 1,0 R/W 4320H 0000H  — — — 6-0 —   — 12-0 — — —  PD8 Pull-down option register 8 16 1,0 R/W 4420H 0000H  — — — 6-0 —   — 12-0 — — —  PODC8 Port open drain control register 8 32 1,0 R/W 4520H 0000 0040H  — — — 6-0 —   — 12-0 — — — 

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 501 of 4535 Dec 26, 2018 Table 2C.44 Control Registers (P8) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 48 Pins 64 Pins 80 Pins 100 Pins PIS8 Port input buffer selection register 8 16 1,0 R/W 4720H FFFFH  — — — 6-0 —   — 12-0 — — —  PPROTS8 Port protection status register 8 32 0 R 4B20H 0000 0000H     PPCMD8 Port protection command register 8 32 7-0 W 4C20H xxxx xx00H     Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset. CAUTION P8_6 drives a low level after any kind of reset release, until it is later configured differently by register settings. For details, see Section 2C.11.1.1, P8_6: RESETOUT .

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 502 of 4535 Dec 26, 2018 2C.10.4 Port 9 (P9) 2C.10.4.1 Alternative Function Table 2C.45 Port 9 (P9) Port Mode (PMC9_m = 0) Alternative Mode (PMC9_m = 1) ADC Special function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative Pins Pins Pins 100 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output P9_0 NMI PWGA8O TAUD0I0 TAUD0O0 ADCA0TRG0 KR0I4 TAUJ1I1 TAUJ1O1 SENT1RX RIIC1SDA ADCA0I2S 35 45 — — NMI PWGA8O TAUD0I0 TAUD0O0 ADCA0TRG0 CSIH2CSS0 KR0I4 TAUJ1I1 TAUJ1O1 SENT1RX RIIC1SDA ADCA0I2S — — 54 69 P9_1 INTP11 PWGA9O TAUD0I2 TAUD0O2 KR0I5 TAUJ1I2 TAUJ1O2 SENT1SPCO RIIC1SCL ADCA0I3S 36 46 — — INTP11 PWGA9O TAUD0I2 TAUD0O2 KR0I5 CSIH2CSS1 TAUJ1I2 TAUJ1O2 SENT1SPCO RIIC1SCL ADCA0I3S — — 55 70 P9_2 KR0I6 PWGA20O TAPA0ESO ADCA0I9S — 47 — — KR0I6 PWGA20O TAPA0ESO CSIH2CSS2 ADCA0I9S — — 56 71 P9_3 KR0I7 PWGA21O TAUJ1I1 TAUJ1O1 ADCA0I10S — 48 — — KR0I7 PWGA21O CSIH2CSS3 TAUJ1I1 TAUJ1O1 ADCA0I10S — — 57 72 P9_4 CSIH0CSS5 TAUJ1I0 TAUJ1O0 ADCA0I11S — — 58 — CSIH0CSS5 PWGA33O TAUJ1I0 TAUJ1O0 ADCA0I11S — — — 73 P9_5 CSIH0CSS6 TAUJ1I1 TAUJ1O1 ADCA0I12S — — 59 — CSIH0CSS6 PWGA34O TAUJ1I1 TAUJ1O1 ADCA0I12S — — — 74 P9_6 CSIH0CSS7 ADCA0I13S — — 60 — CSIH0CSS7 PWGA35O ADCA0I13S — — — 75 CAUTIONS 1. The behavior and performance are not guaranteed when alternative functions are not assigned to the register. 2. Use ADC functions with their initial settings. For details, see Table 2C.46, Control Registers (P9).

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 503 of 4535 Dec 26, 2018 2C.10.4.2 Control Registers Table 2C.46 Control Registers (P9) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 48 Pins 64 Pins 80 Pins 100 Pins P9 Port register 9 16 1, 0 R/W 0024H 0000H  — — — 3-0 —  — — 6-0 — —   PSR9 Port set/reset register 9 32 17, 16, 1, 0 R/W 0124H 0000 0000H  — — — 19-16, 3-0 —  — — 22-16, 6-0 — —   PPR9 Port pin read register 9 16 1, 0 R 0224H 0000H  — — — 3-0 —  — — 6-0 — —   PM9 Port mode register 9 16 1, 0 R/W 0324H FFFFH  — — — 3-0 —  — — 6-0 — —   PMC9 Port mode control register 9 16 1, 0 R/W 0424H 0000H  — — — 3-0 —  — — 6-0 — —   PFC9 Port function control register 9 16 1, 0 R/W 0524H 0000H  — — — 2-0 —  — — 3-0 — —  — 6-0 — — —  PFCE9 Port function control expansion register 16 1, 0 R/W 0624H 0000H  — — — 3, 1, 0 —  — — 5-3, 1, 0 — —   PNOT9 Port NOT register 9 16 1, 0 W 0724H 0000H  — — — 3-0 —  — — 6-0 — —   PMSR9 Port mode set/reset register 9 32 17, 16, 1, 0 R/W 0824H 0000 FFFFH  — — — 19-16, 3-0 —  — — 22-16, 6-0 — —   PMCSR9 Port mode control set/reset register 9 32 17, 16, 1, 0 R/W 0924H 0000 0000H  — — — 19-16, 3-0 —  — — 22-16, 6-0 — —   PFCAE9 Port function control additional expansion register 9 16 1, 0 R/W 0A24H 0000H     PIBC9 Port input buffer control register 9 16 1, 0 R/W 4024H 0000H  — — — 3-0 —  — — 6-0 — —   PBDC9 Port bidirection control register 9 16 1, 0 R/W 4124H 0000H  — — — 3-0 —  — — 6-0 — —   PU9 Pull-up option register 9 16 1, 0 R/W 4324H 0000H  — — — 3-0 —  — — 6-0 — —   PD9 Pull-down option register 9 16 1, 0 R/W 4424H 0000H  — — — 3-0 —  — — 6-0 — —   PODC9 Port open drain control register 9 32 1, 0 R/W 4524H 0000 0000H  — — — 3-0 —  — — 6-0 — —  

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 504 of 4535 Dec 26, 2018 Table 2C.46 Control Registers (P9) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 48 Pins 64 Pins 80 Pins 100 Pins PIS9 Port input buffer selection register 9 16 1, 0 R/W 4724H FFFFH  — — — 3-0 —  — — 6-0 — —   PPROTS9 Port protection status register 9 32 0 R 4B24H 0000 0000H     PPCMD9 Port protection command register 9 32 7-0 W 4C24H xxxx xx00H     Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 505 of 4535 Dec 26, 2018 2C.10.5 Port 10 (P10) 2C.10.5.1 Alternative Function Table 2C.47 Port 10 (P10) Port Mode (PMC10_ m = 0) Alternative Mode (PMC10_m = 1) ADC Special function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 48 Pins Pins Pins 100 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output P10_0 TAUD0I1 TAUD0O1 CAN0RX/ INTP0 CSCXFOUT PWGA0O TAUJ1I3 TAPA0UP TAUJ1O3 CAN0RX 46 62 — — TAUD0I1 TAUD0O1 CAN0RX/ INTP0 CSCXFOUT PWGA0O TAUJ1I3 TAPA0UP CSIH1SI TAUJ1O3 CAN0RX — — 78 98 P10_1 TAUD0I3 TAUD0O3 CAN0TX PWGA1O TAUJ3I0 TAPA0UN TAUJ3O0 MODE0 47 63 — — TAUD0I3 TAUD0O3 CAN0TX PWGA1O TAUJ3I0 TAPA0UN CSIH1SC TAUJ3O0 MODE0 — — 79 99 P10_2 TAUD0I5 TAUD0O5 RIIC0SDA KR0I0 PWGA2O ADCA0TRG0 TAPA0VP MODE1 48 64 — — TAUD0I5 TAUD0O5 RIIC0SDA KR0I0 PWGA2O ADCA0TRG0 TAPA0VP CSIH1SO MODE1 — — 80 100 P10_3 TAUD0I7 TAUD0O7 RIIC0SCL KR0I1 PWGA3O ADCA0TRG1 TAPA0VN 1 1 — — TAUD0I7 TAUD0O7 RIIC0SCL KR0I1 PWGA3O ADCA0TRG1 TAPA0VN CSIH1SSI — — 1 1 P10_4 TAUD0I9 TAUD0O9 RLIN21RX KR0I2 ADCA0SEL0 ADCA0TRG2 TAPA0WP CSIG0SSI 2 2 2 2 P10_5 TAUD0I11 TAUD0O11 RLIN21TX KR0I3 ADCA0SEL1 TAPA0WN CSIG0RYI CSIG0RYO 3 3 3 3 P10_6 TAUD0I13 TAUD0O13 CSIG0SO ENCA0TIN0 ADCA0SEL2 MODE2 39 — — — TAUD0I13 TAUD0O13 CSIG0SO ENCA0TIN0 ADCA0SEL2 CAN1RX/ INTP1 CAN1RX MODE2 — 51 63 80 P10_7 TAUD0I15 TAUD0O15 CSIG0SC ENCA0TIN1 PWGA4O TAUJ3I1 TAUJ3O1 40 — — — TAUD0I15 TAUD0O15 CSIG0SC ENCA0TIN1 PWGA4O CAN1TX TAUJ3I1 TAUJ3O1 — 52 64 81 P10_8 TAUD0I10 TAUD0O10 CSIG0SI ENCA0EC PWGA5O TAUJ3I2 TAUJ3O2 FLMD1 41 53 65 82 P10_9 TAUD0I12 TAUD0O12 RLIN30RX/ INTP10 ENCA0E0 PWGA6O CSIH0RYI CSIH0RYO RLIN30RX 42 54 66 83 P10_10 TAUD0I14 TAUD0O14 RLIN30TX ENCA0E1 PWGA7O CSIH0CSS1 TAUJ3I3 TAUJ3O3 43 55 67 84 P10_11 PWGA16O RLIN31RX/ INTP11 RLIN31RX — 56 — — PWGA16O RLIN31RX/ INTP11 CSIH1CSS0 TAUB0I1 TAUB0O1 RLIN31RX — — 68 85

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 506 of 4535 Dec 26, 2018 Table 2C.47 Port 10 (P10) Port Mode (PMC10_ m = 0) Alternative Mode (PMC10_m = 1) ADC Special function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 48 Pins Pins Pins 100 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output P10_12 PWGA17O RLIN31TX — 57 — — PWGA17O RLIN31TX CSIH1CSS1 TAUB0I3 TAUB0O3 — — 69 86 P10_13 CSIH0SSI PWGA18O — 58 — — CSIH0SSI PWGA18O RLIN32RX/ INTP12 TAUB0I5 TAUB0O5 RLIN32RX — — 70 87 P10_14 PWGA19O — 59 — — PWGA19O RLIN32TX TAUB0I7 TAUB0O7 — — 71 — PWGA19O RLIN32TX CSIH3SSI TAUB0I7 TAUB0O7 — — — 88 P10_15 TAUB0I9 TAUB0O9 — — 4 — CSIH3RYI CSIH3RYO PWGA24O RLIN22RX TAUB0I9 TAUB0O9 — — — 4 CAUTION The behavior and performance are not guaranteed when alternative functions are not assigned to the register.

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 507 of 4535 Dec 26, 2018 2C.10.5.2 Control Registers Table 2C.48 Control Registers (P10) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 48 Pins 64 Pins 80 Pins 176 Pins P10 Port register 10 16 10-0 R/W 0028H 0000H  — — — 14-0 —  — — 15-0 — —   PSR10 Port set/reset register 10 32 26-16, 10-0 R/W 0128H 0000 0000H  — — — PPR10 Port pin read register 10 16 10-0 R 0228H 0000H  — — — 14-0 —  — — 15-0 — —   PM10 Port mode register 10 16 10-0 R/W 0328H FFFFH  — — — 14-0 —  — — 15-0 — —   PMC10 Port mode control register 10 16 10-0 R/W 0428H 0000H  — — — 14-0 —  — — 15-0 — —   PFC10 Port function control register 10 16 10-0 R/W 0528H 0000H  — — — 12-0 —  — — 15-0 — —   PFCE10 Port function control expansion register 10 16 10-0 R/W 0628H 0000H  — — — 11-0 —  — — 15-0 — —   PNOT10 Port NOT register 10 16 10-0 W 0728H 0000H  — — — 14-0 —  — — 15-0 — —   PMSR10 Port mode set/reset register 10 32 26-16, 10-0 R/W 0828H 0000 FFFFH  — — — PMCSR10 Port mode control set/reset register 10 32 26-16, 10-0 R/W 0928H 0000 0000H  — — — PFCAE10 Port function control additional expansion register 10 16 10-7, 5, 4, 1, 0 R/W 0A28H 0000H  — — — 11-4, 1, 0 —  — — 13, 11-0 — —   PIBC10 Port input buffer control register 10 16 10-0 R/W 4028H 0000H  — — — 14-0 —  — — 15-0 — —   PBDC10 Port bidirection control register 10 16 10-0 R/W 4128H 0000H  — — — 14-0 —  — — 15-0 — —   PIPC10 Port IP control register 10 16 7-0 R/W 4228H 0000H     PU10 Pull-up option register 10 16 10-0 R/W 4328H 0000H  — — — 14-0 —  — — 15-0 — —   PD10 Pull-down option register 10 16 10-0 R/W 4428H 0000H  — — — 14-0 —  — — 15-0 — —   PODC10 Port open drain control register 10 32 10-0 R/W 4528H 0000 0000H  — — — 14-0 —  — — 15-0 — —  

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 508 of 4535 Dec 26, 2018 Table 2C.48 Control Registers (P10) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 48 Pins 64 Pins 80 Pins 176 Pins PDSC10 Port drive strength control register 10 32 10-0 R/W 4628H 0000 0000H  — — — 14-0 —  — — 15-0 — —   PIS10 Port input buffer selection register 10 16 10-0 R/W 4728H FFFFH  — — — 14-0 —  — — 15-0 — —   PPROTS10 Port protection status register 10 32 0 R 4B28H 0000 0000H     PPCMD10 Port protection command register 10 32 7-0 W 4C28H xxxx xx00H     Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 509 of 4535 Dec 26, 2018 2C.10.6 Port 11 (P11) 2C.10.6.1 Alternative Function Table 2C.49 Port 11 (P11) Port Mode (PMC11_m = 0) Alternative Mode (PMC11_m = 1) ADC Special function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative 48 Pins Pins Pins 100 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output P11_0 CSIH2RYI CSIH2RYO TAUB0I11 TAUB0O11 — — 5 — CSIH2RYI CSIH2RYO PWGA25O RLIN22TX TAUB0I11 TAUB0O11 — — — 5 P11_1 CSIH2SSI RLIN20RX CSIH0CSS7 TAUB0I13 TAUB0O13 — — 72 — CSIH2SSI RLIN20RX CSIH0CSS7 PWGA26O TAUB0I13 TAUB0O13 — — — 89 P11_2 CSIH2SO RLIN32RX/ INTP12 RLIN20TX TAUB0I15 TAUB0O15 RLIN32RX — — 73 — CSIH2SO RLIN32RX/ INTP12 RLIN20TX PWGA27O TAUB0I15 TAUB0O15 RLIN32RX — — — 90 P11_3 CSIH2SC RLIN32TX — — 74 — CSIH2SC CAN3RX/ INTP3 PWGA28O RLIN32TX CAN3RX — — — 91 P11_4 CSIH2SI — — 75 — CSIH2SI CAN3TX PWGA29O — — — 92 P11_5 CAN5RX/ INTP5 RLIN33TX PWGA30O CSIH3SI CAN5RX — — — 93 P11_6 RLIN33RX/ INTP13 CAN5TX PWGA31O CSIH3SO RLIN33RX — — — 94 P11_7 INTP5 PWGA32O CSIH3SC — — — 95 CAUTION The behavior and performance are not guaranteed when alternative functions are not assigned to the register.

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 510 of 4535 Dec 26, 2018 2C.10.6.2 Control Registers Table 2C.50 Control Registers (P11) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 48 Pins 64 Pins 80 Pins 100 Pins P11 Port register 11 16 4-0 R/W 002CH 0000H — —  — 7-0 — — —  PSR11 Port set/reset register 11 32 20-16, 4-0 R/W 012CH 0000 0000H — —  — 23-16, 7-0 — — —  PPR11 Port pin read register 11 16 4-0 R 022CH 0000H — —  — 7-0 — — —  PM11 Port mode register 11 16 4-0 R/W 032CH FFFFH — —  — 7-0 — — —  PMC11 Port mode control register 11 16 4-0 R/W 042CH 0000H — —  — 7-0 — — —  PFC11 Port function control register 11 16 2-0 R/W 052CH 0000H — —  — 7-0 — — —  PFCE11 Port function control expansion register 16 3-0 R/W 062CH 0000H — —  — 7-5, 3-0 — — —  PNOT11 Port NOT register 11 16 4-0 W 072CH 0000H — —  — 7-0 — — —  PMSR11 Port mode set/reset register 11 32 20-16, 4-0 R/W 082CH 0000 FFFFH — —  — 23-16, 7-0 — — —  PMCSR11 Port mode control set/reset register 11 32 20-16, 4-0 R/W 092CH 0000 0000H — —  — 23-16, 7-0 — — —  PFCAE11 Port function control additional expansion register 11 16 3, 2 R/W 0A2CH 0000H — —  — 6, 5, 3, 2 — — —  PIBC11 Port input buffer control register 11 16 4-0 R/W 402CH 0000H — —  — 7-0 — — —  PBDC11 Port bidirection control register 11 16 4-0 R/W 412CH 0000H — —  — 7-0 — — —  PIPC11 Port IP control register 11 16 3, 2 R/W 422CH 0000H — —  — 7, 6, 3, 2 — — —  PU11 Pull-up option register 11 16 4-0 R/W 432CH 0000H — —  — 7-0 — — —  PD11 Pull-down option register 11 16 4-0 R/W 442CH 0000H — —  — 7-0 — — —  PODC11 Port open drain control register 11 32 4-0 R/W 452CH 0000 0000H — —  — 7-0 — — —  PDSC11 Port drive strength control register 11 32 4-0 R/W 462CH 0000 0000H — —  — 7-0 — — —  PIS11 Port input buffer selection register 11 16 4-0 R/W 472CH FFFFH — —  — 7-0 — — —  PPROTS11 Port protection status register 11 32 0 R 4B2CH 0000 0000H — —   PPCMD11 Port protection command register 11 32 7-0 W 4C2CH xxxx xx00H — —   Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 511 of 4535 Dec 26, 2018 2C.10.7 Analog Port 0 (AP0) 2C.10.7.1 Alternative Function Table 2C.51 Analog Port 0 (AP0) Port Mode Alternative Mode ADC Special function PKG No. 1st Alternative 2nd Alternative 3rd Alternative 4th Alternative 5th Alternative 6th Alternative 7th Alternative Pins Pins Pins 100 Pins Input Output Input Output Input Output Input Output Input Output Input Output Input Output AP0_0 ADCA0I0 34 44 53 68 AP0_1 ADCA0I1 33 43 52 67 AP0_2 ADCA0I2 32 42 51 66 AP0_3 ADCA0I3 31 41 50 65 AP0_4 ADCA0I4 30 40 49 64 AP0_5 ADCA0I5 29 39 48 63 AP0_6 ADCA0I6 28 38 47 62 AP0_7 ADCA0I7 27 37 46 61 AP0_8 ADCA0I8 — 36 45 60 AP0_9 ADCA0I9 — 35 44 59 AP0_10 ADCA0I10 — — 43 58 AP0_11 ADCA0I11 — — — 57 AP0_12 ADCA0I12 — — — 56 AP0_13 ADCA0I13 — — — 55 AP0_14 ADCA0I14 — — — 54 AP0_15 ADCA0I15 — — — 53 CAUTION Use ADC functions with their initial settings. For details, see Table 2C.52, Control Registers (AP0).

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 512 of 4535 Dec 26, 2018 2C.10.7.2 Control Registers Table 2C.52 Control Registers (AP0) Register Function Register Size Effective Bit Offset Address Value after Reset Device Position R/W*1 48 Pins 64 Pins 80 Pins 100 Pins AP0 Analog port register 0 16 7-0 R/W 00C8H 0000H  — — — 9-0 —  — — 10-0 — —  — 15-0 — — —  APSR0 Analog port set/reset register 0 32 23-16, 7-0 R/W 01C8H 0000 0000H  — — — 25-16, 9-0 —  — — APPR0 Analog port pin read register 0 16 7-0 R 02C8H 0000H  — — — 9-0 —  — — 10-0 — —  — 15-0 — — —  APM0 Analog port mode register 0 16 7-0 R/W 03C8H FFFFH  — — — 9-0 —  — — 10-0 — —  — 15-0 — — —  APNOT0 Analog port NOT register 0 16 7-0 W 07C8H 0000H  — — — 9-0 —  — — 10-0 — —  — 15-0 — — —  APMSR0 Analog port mode set/reset register 0 32 23-16, 7-0 R/W 08C8H 0000 FFFFH  — — — 25-16, 9-0 —  — — APIBC0 Analog port input buffer control register 0 16 7-0 R/W 40C8H 0000H  — — — 9-0 —  — — 10-0 — —  — 15-0 — — —  APBDC0 Analog port bidirection control register 0 16 7-0 R/W 41C8H 0000H  — — — 9-0 —  — — 10-0 — —  — 15-0 — — —  Note 1. The unused bits are read-only (R). When read, the value after reset is returned. When writing to unused bits, write the value after reset.

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 513 of 4535 Dec 26, 2018 2C.11 Port (Special I/O) Function Overview This section describes the port (special I/O) functions. 2C.11.1 Special I/O after Reset The special port function after reset is deasserted is shown below. 2C.11.1.1 P8_6: RESETOUT The P8_6 pin ( RESETOUT signal) changes PM8.PM8_6 and PODC8.PODC8_6 registers value after reset by OPBT0.RESETOUTEN setting. The P8_6 pin outputs a low level while a reset is asserted, and pin status of after the reset is different. (Case 1): OPBT0.RESETOUTEN = 1

• P8.P8_6 = 0: Outputs low level
• PM8.PM8_6 = 0: Output mode
• PODC8.PODC8_6 = 1: Open-drain (Case 2): OPBT0.RESETOUTEN = 0
• P8.P8_6 = 0: Outputs low level
• PM8.PM8_6 = 1: Input mode
• PODC8.PODC8_6 = 0: Push-pull For detail of OPBT0.RESETOUTEN register, see Section 44.9.2, OPBT0 — Option Byte 0, also see Section 9BC.1.3, Reset Output ( RESETOUT ).

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 514 of 4535 Dec 26, 2018 When the P8_6 pin setting is updated with another value, the pin operates by new setting. EVCC/ REGVCC RESET Flash Operation P8_6 RESETOUT RESETOUT enable P8_6 was set to1. General purpose I/O P8_6 is changed to Low output by resets. RESETOUT enable Execution of user program started. Transferred data (OPBT0.RESETOUTEN = 1) Reset is asserted Flash sequence Flash sequence RESETOUT Figure 2C.10 P8_6 Pin ( RESETOUT Signal) Operation While a Reset is asserted and released: (Case 1) OPBT0.RESETOUTEN setting is 1

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 515 of 4535 Dec 26, 2018 EVCC/ REGVCC RESET Flash Operation Flash sequence P8_6 RESETOUT RESETOUT disable P8_6 was set to1. General purpose I/O P8_6 is changed to Hi-z by resets. Execution of user program started. Reset is asserted. Flash sequence RESETOUT disable Hi-z Hi-z Transferred data (OPBT0.RESETOUTEN=0) (*1) General purpose I/O P8_6 was set to1. RESETOUT Power lowered POC RESET is asserted. P8_6 is changed to Low output by resets. Note 1. When a reset except POC reset occurs with RESETOUT disable (OPBT0.RESETOUTEN = 0), P8_6 pin ( RESETOUT signal) will be changed to Hi-z. Figure 2C.11 P8_6 Pin ( RESETOUT Signal) Operation While a Reset is asserted and released: (Case 2) OPBT0.RESETOUTEN setting is 0

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 516 of 4535 Dec 26, 2018 2C.11.1.2 JP0_0 to JP0_5: Debug Interface If the OPJTAG[1:0] setting is the combination below, the pins of the JTAG port group can be used as a debug interface after reset release. Table 2C.53 Debug Interface OPJTAG1 OPJTAG0 Mode JP0_0 JP0_1 JP0_2 JP0_3 JP0_4 JP0_5 1 1 Nexus I/F DCUTDI input DCUTDO output DCUTCK input DCUTMS input DCUTRST input DCURDY output 0 1 LPD (4 pins) LPDI input LPDO output LPDCLK input Port/ alternative function Port/ alternative function LPDCLK OUT output 1 0 LPD (1 pin) LPDIO input/output Port/ alternative function Port/ alternative function Port/ alternative function Port/ alternative function Port/ alternative function NOTE For the OPJTAG[1:0] settings, see Section 44.9.2, OPBT0 — Option Byte 0. 2C.11.1.3 FPDR(JP0_0), FPDT(JP0_1), FPCK(JP0_2): Flash Programmer These pins are used for connecting a flash programmer. See Flash Programmerʼs Manual for details. 2C.11.1.4 Mode Pins The FLMD0 pin in combination with the P10_8: FLMD1 pin can select serial programming mode. The FLMD0 pin in combination with the P10_8: FLMD1, the P10_2: MODE1 and the P10_1: MODE0 pins can select boundary scan mode. The FLMD0 pin in combination with the P10_8: FLMD1, the P10_6: MODE2, the P10_2: MODE1 and the P10_1: MODE0 pins can select user boot mode. For details on the mode selection, see Section 6, Operating Mode.

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 517 of 4535 Dec 26, 2018 2C.11.2 A/D Input Alternative I/O The following ports are permanently connected to A/D input functions. (However, an analog input to the A/D is controlled by the A/D module.) Table 2C.54 A/D Input Alternative Pins Device Port A/D Input 48 Pins 64 Pins 80 Pins 100 Pins

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 518 of 4535 Dec 26, 2018 2C.11.3 Special I/O Control 2C.11.3.1 Direct I/O Control (PIPC) Some alternative functions take over the input and output control of the ports. The following table lists all alternative functions where PIPCn.PIPCn_m must be set to 1. For details, see Section 2C.9.2.3, PIPCn — Port IP Control Register. Table 2C.55 Alternative Modes that Require Setting PIPCn.PIPCn_m = 1 Function Alternative Functions Name Port Name Power Supply Area Control Reference Section TAPA TAPA0UP P10_0 ISO U phase Hi-Z control Section 36 TAPA0UN P10_1 ISO TAPA0VP P10_2 ISO V phase Hi-Z control TAPA0VN P10_3 ISO TAPA0WP P10_4 ISO W phase Hi-Z control TAPA0WN P10_5 ISO CSIG CSIG0SO P0_13 AWO Serial data output control signal Section 19 P10_6 ISO CSIG0SC P0_14 AWO Master (1) / slave (0) mode signal P10_7 ISO CSIH CSIH0SO P0_3 AWO Serial data output control signal Section 20 CSIH0SC P0_2 AWO Master (1) / slave (0) mode signal CSIH1SO P0_5 AWO Serial data output control signal P10_2 ISO CSIH1SC P0_6 AWO Master (1) / slave (0) mode signal P10_1 ISO CSIH2SO P11_2 ISO Serial data output control signal CSIH2SC P11_3 ISO Master (1) / slave (0) mode signal CSIH3SO P11_6 ISO Serial data output control signal CSIH3SC P11_7 ISO Master (1) / slave (0) mode signal

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 519 of 4535 Dec 26, 2018 2C.11.3.2 Input Buffer Control (PISn/JPIS0, JPISA0) The port input buffer characteristics (Type 1 or Type 2) of this device can be selected using the PISn/ JPIS0 register. The applicable pins are shown in the following table. The JTAG port input buffer characteristics (Type 1/2 or Type 5) of this device can be selected using the JPISA0 register. The applicable pins are shown in Table 2C.57, JTAG Port Input Buffer Characteristics Selection. Table 2C.56 Port Input Buffer Characteristics Selection Input Buffer Selection Device Port Name Type 1 (PISn_m = 0) Type 2 (PISn_m = 1) 48 Pins 64 Pins 80 Pins 100 Pins P0_10 SHMT1 SHMT4 — —   P0_11 SHMT1 SHMT4 — —   P0_12 SHMT1 SHMT4 — —   P0_13 SHMT1 SHMT4 — — —  P0_14 SHMT1 SHMT4 — — —  P8_10 SHMT1 SHMT4 — — —  P8_11 SHMT1 SHMT4 — — —  P8_12 SHMT1 SHMT4 — — —  P10_0 SHMT1 SHMT4     P10_1 SHMT1 SHMT4    

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 520 of 4535 Dec 26, 2018 Table 2C.56 Port Input Buffer Characteristics Selection Input Buffer Selection Device Port Name Type 1 (PISn_m = 0) Type 2 (PISn_m = 1) 48 Pins 64 Pins 80 Pins 100 Pins P10_2 SHMT1 SHMT4     P10_3 SHMT1 SHMT4     P10_4 SHMT1 SHMT4     P10_5 SHMT1 SHMT4     P10_6 SHMT1 SHMT4     P10_7 SHMT1 SHMT4     P10_8 SHMT1 SHMT4     P10_9 SHMT1 SHMT4     P10_10 SHMT1 SHMT4     P10_11 SHMT1 SHMT4 —    P10_12 SHMT1 SHMT4 —    P10_13 SHMT1 SHMT4 —    P10_14 SHMT1 SHMT4 —    P10_15 SHMT1 SHMT4 — —   P11_0 SHMT1 SHMT4 — —   P11_1 SHMT1 SHMT4 — —   P11_2 SHMT1 SHMT4 — —   P11_3 SHMT1 SHMT4 — —   P11_4 SHMT1 SHMT4 — —   P11_5 SHMT1 SHMT4 — — —  P11_6 SHMT1 SHMT4 — — —  P11_7 SHMT1 SHMT4 — — —  Table 2C.57 JTAG Port Input Buffer Characteristics Selection Input Buffer Selection Devices Port Name Type 1 (JPIS0_m = 0 & JPISA0_m = 0) Type 2 (JPIS0_m = 1 & JPISA0_m = 0) Type 5 (JPISA0_m = 1) 48 Pins 64 Pins 80 Pins 100 Pins Note 1. TTL is selected for Boundary scan mode without JPISA0 register setting. Note 2. TTL is selected for Nexus in normal operating mode without JPISA0 register setting. Note 3. TTL is selected for LPD (4 pins) in normal operating mode without JPISA0 register setting. Note 4. TTL is selected for LPD (1 pin) in normal operating mode without JPISA0 register setting. NOTES 1. For the SHMT1, SHMT4, and TTL pin characteristics, see Section 47C, Electrical Characteristics of RH850/F1KM-S1. 2. For the input buffer after reset, Type 2 (SHMT4) is selected.

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 521 of 4535 Dec 26, 2018 2C.11.3.3 Output Buffer Control (PDSC) The port output driver strength (slow mode/fast mode) can be selected using the PDSCn register. The applicable pins are shown in the following table. Only slow mode is supported for ports other than those listed bel ow. Table 2C.58 Output Buffer Characteristics Selection Output Drive Strength Selection Device Port Name Slow Mode (PDSCn_m = 0) Fast Mode (PDSCn_m = 1) 48 Pins 64 Pins 80 Pins 100 Pins JP0_1 10 MHz 40 MHz     JP0_2 10 MHz 40 MHz     JP0_3 10 MHz 40 MHz     JP0_5 10 MHz 40 MHz     P0_0 10 MHz 40 MHz     P0_1 10 MHz 40 MHz     P0_4 10 MHz 40 MHz —    P0_7 10 MHz 40 MHz — —   P0_8 10 MHz 40 MHz — —   P0_9 10 MHz 40 MHz — —   P0_10 10 MHz 40 MHz — —   P0_11 10 MHz 40 MHz — —   P0_12 10 MHz 40 MHz — —   P0_13 10 MHz 40 MHz — — —  P0_14 10 MHz 40 MHz — — —  P10_0 10 MHz 40 MHz     P10_3 10 MHz 40 MHz     P10_4 10 MHz 40 MHz     P10_5 10 MHz 40 MHz     P10_6 10 MHz 40 MHz     P10_7 10 MHz 40 MHz     P10_8 10 MHz 40 MHz     P10_9 10 MHz 40 MHz     P10_10 10 MHz 40 MHz     P10_11 10 MHz 40 MHz —    P10_12 10 MHz 40 MHz —    P10_13 10 MHz 40 MHz —    P10_14 10 MHz 40 MHz —    P10_15 10 MHz 40 MHz — —   P11_0 10 MHz 40 MHz — —   P11_1 10 MHz 40 MHz — —  

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 522 of 4535 Dec 26, 2018 Table 2C.58 Output Buffer Characteristics Selection Output Drive Strength Selection Device Port Name Slow Mode (PDSCn_m = 0) Fast Mode (PDSCn_m = 1) 48 Pins 64 Pins 80 Pins 100 Pins P11_4 10 MHz 40 MHz — —   P11_5 10 MHz 40 MHz — — —  Note 1. Supports Cload: 100 pF (The load capacitance of CSIH0 is 100 pF.) Note 2. Supports Cload: 50 pF (The load capacitance of CSIH1 to CSIH3 are 50 pF.) Note 3. In some of the functions, Fast mode or Slow mode is specified. For details, see Section 47C.5, AC Characteristics.

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 523 of 4535 Dec 26, 2018 2C.12 Noise Filter & Edge/Level Detector The input signals at some pins are passed through a filter to remove noise and glitches. The RH850/F1KM supports both analog and digital filters. It also supports the function for edge and level detection after the signals have passed through a filter. The first part of this section provides an overview of port input pins that are equipped with a filter and the filter type, noise filter & edge/level detection control registers and control bits, and register addresses. For details on the digital/analog filter function and noise filter & edge/level detection control registers, see Section 2C.13, Description of Port Noise Filter & Edge/Level Detection. NOTE In this section, <name> in the noise filter control register represents the peripheral function connected to a filter. 2C.12.1 Port Filter Assignment A list of the input pins that incorporate an analog or digital filter is provided below. 2C.12.1.1 Input Pins that Incorporate Analog Filter Type A The input pins of analog filter type A incorporate an analog filter and edge/level det ection function. Edge/level detection is controlled by the following registers. Filter control register FCLA0CTLm_<name> (m = 0 to 7) A dedicated FCLA0CTLm_<name> register is provided for each pin in a port that incorporates an analog filter. Table 2C.59 Input Pins that Incorporate Analog Filter Type A FCLA0CTL Register Configuration Device Module Name Input Pin Register Address 48 Pins 64 Pins 80 Pins 100 Pins FCLA0 NMI FCLA0CTL0_NMI FFC3 4000H     INTP0 FCLA0CTL0_INTPL FFC3 4020H     INTP1 FCLA0CTL1_INTPL FFC3 4024H     INTP2 FCLA0CTL2_INTPL FFC3 4028H     INTP3 FCLA0CTL3_INTPL FFC3 402CH     INTP4 FCLA0CTL4_INTPL FFC3 4030H     INTP5 FCLA0CTL5_INTPL FFC3 4034H     INTP6 FCLA0CTL6_INTPL FFC3 4038H — —   INTP7 FCLA0CTL7_INTPL FFC3 403CH — —   INTP8 FCLA0CTL0_INTPH FFC3 4040H — —   INTP10 FCLA0CTL2_INTPH FFC3 4048H     INTP11 FCLA0CTL3_INTPH FFC3 404CH     INTP12 FCLA0CTL4_INTPH FFC3 4050H — —   INTP13 FCLA0CTL5_INTPH FFC3 4054H — — — 

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 524 of 4535 Dec 26, 2018 2C.12.1.2 Input Pins that Incorporate Analog Filter Type B The input pins of analog filter type B incorporate an analog filter. Edge/level detection is controlled by the registers for individual peripheral functions. Table 2C.60 Input Pins that Incorporate Analog Filter Type B Device Input Pin Edge/Level Detection 48 Pins 64 Pins 80 Pins 100 Pins TAUJ0I0 Edge detection*1     TAUJ0I1 Edge detection*1     TAUJ0I2 Edge detection*1     TAUJ0I3 Edge detection*1     TAUJ1I0 Edge detection*1     TAUJ1I1 Edge detection*1     TAUJ1I2 Edge detection*1     TAUJ1I3 Edge detection*1     TAUJ2I0 Edge detection*1     TAUJ2I1 Edge detection*1     TAUJ2I2 Edge detection*1     TAUJ2I3 Edge detection*1     TAUJ3I0 Edge detection*1     TAUJ3I1 Edge detection*1     TAUJ3I2 Edge detection*1     TAUJ3I3 Edge detection*1     TAPA0ESO Edge detection*2     KR0I0 Low level detection     KR0I1 Low level detection     KR0I2 Low level detection     KR0I3 Low level detection     KR0I4 Low level detection     KR0I5 Low level detection     KR0I6 Low level detection —    KR0I7 Low level detection —    Note 2. For details on edge detection for TAPA, see Section 36.3.2, TAPAnCTL0 — TAPA Control Register 0.

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 525 of 4535 Dec 26, 2018 2C.12.1.3 Input Pins that Incorporate Analog Filter Type C The input pins of analog filter type C only incorporate an analog filter function. Table 2C.61 Input Pins that Incorporate Analog Filter Type C Input Pin FLMD0 FLMD1 MODE0 MODE1 MODE2 RESET DCUTRST

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 526 of 4535 Dec 26, 2018 2C.12.1.4 Input Pins that Incorporate Digital Filter Type D The input pins of digital filter type D incorporate a digital filter and edge detection function. The digital filter and edge detection are controlled by the following registers.

• Filter control register FCLA0CTLm_<name> (m = 0 to 2) Each port with a digital filter has a special FCLA0CTLm_<name> register.
• Digital noise elimination control register DNFA<name>CTL Each DNFA<name>CTL control register controls digital filter processing for three input signals per group.
• Digital noise elimination enable register DNFA<name>EN The setting of the DNFA<name>ENL[2:0] bits in DNFA<name>EN enables or disables digital noise elimination for three input signals per group. Table 2C.62 Input Pins that Incorporate Digital Filter Type D Device Digital Noise Elimination Control Register Digital Noise Elimination Enable Register Filter Control Register Input Pin 48 Pins 64 Pins 80 Pins 100 Pins Control Register Address Control Register Control Bit Address Control Register Address ADCA0TRG0     DNFAADCTL0CTL FFC3 00A0H DNFAADCTL0EN (DNFAADCTL0ENL) DNFAADCTL0 ENL0 FFC3 00A4H (FFC3 00ACH) FCLA0CTL0 _ADC0 FFC3 4060 H ADCA0TRG1     DNFAADCTL0 ENL1 FCLA0CTL1 _ADC0 FFC3 4064 H ADCA0TRG2     DNFAADCTL0 ENL2 FCLA0CTL2 _ADC0 FFC3 4068 H

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 527 of 4535 Dec 26, 2018 2C.12.1.5 Input Pins that Incorporate Digital Filter Type E The input pins of digital filter type E incorporate a digital filter. The digital filter is controlled by the following registers. Edge detection is controlled by the registers for individual peripheral functions.

• Digital noise elimination control register DNFA<name>CTL Each DNFA<name>CTL control register controls digital filter processing for up to 16 input signals per group.
• Digital noise elimination enable register DNFA<name>EN The setting of the DNFA<name>ENL[7:0] and DNFA<name>ENH[7:0] bits in DNFA<name>EN enables or disables digital noise elimination for up to 16 input signals per group. Table 2C.63 Input Pins that Incorporate Digital Filter Type E Devises Digital Noise Elimination Control Register Digital Noise Elimination Enable Register Edge Detection Input Pin 48 Pins 64 Pins 80 Pins 100 Pins Control Register Address Control Register Control Bit Address Register Name TAUD0I0     DNFA TAUD0ICTL FFC3 0000H DNFATAUD0IEN (DNFA TAUD0IENH / DNFA TAUD0IENL) DNFATAUD0IENL0 FFC3 0004H (FFC3 0008H/ FFC3 000CH) TAUD0I1     DNFATAUD0IENL1 TAUD0I2     DNFATAUD0IENL2 TAUD0I3     DNFATAUD0IENL3 TAUD0I4     DNFATAUD0IENL4 TAUD0I5     DNFATAUD0IENL5 TAUD0I6     DNFATAUD0IENL6 TAUD0I7     DNFATAUD0IENL7 TAUD0I8     DNFATAUD0IENH0 TAUD0I9     DNFATAUD0IENH1 TAUD0I10     DNFATAUD0IENH2 TAUD0I11     DNFATAUD0IENH3 TAUD0I12     DNFATAUD0IENH4 TAUD0I13     DNFATAUD0IENH5 TAUD0I14     DNFATAUD0IENH6 TAUD0I15     DNFATAUD0IENH7 TAUB0I0 — —   DNFA TAUB0ICTL FFC3 0020H DNFATAUB0IEN (DNFA TAUB0IENH/ DNFA TAUB0IENL) DNFATAUB0IENL0 FFC3 0024 H (FFC3 0028H/ FFC3 002CH) TAUB0I1 — —   DNFATAUB0IENL1 TAUB0I2 — —   DNFATAUB0IENL2 TAUB0I3 — —   DNFATAUB0IENL3 TAUB0I4 — —   DNFATAUB0IENL4 TAUB0I5 — —   DNFATAUB0IENL5 TAUB0I6 — —   DNFATAUB0IENL6 TAUB0I7 — —   DNFATAUB0IENL7 TAUB0I8 — —   DNFATAUB0IENH0 TAUB0I9 — —   DNFATAUB0IENH1 TAUB0I10 — —   DNFATAUB0IENH2 TAUB0I11 — —   DNFATAUB0IENH3 TAUB0I12 — —   DNFATAUB0IENH4 TAUB0I13 — —   DNFATAUB0IENH5 TAUB0I14 — —   DNFATAUB0IENH6 TAUB0I15 — —   DNFATAUB0IENH7 ENCA0TIN0     DNFA ENCA0ICTL FFC3 0060H DNFAENCA0IEN (DNFA ENCA0IENL) DNFAENCA0IENL0 FFC3 0064H (FFC3 006CH) ENCA0TIN1     DNFAENCA0IENL1 ENCA0E0     DNFAENCA0IENL2 ENCA0E1     DNFAENCA0IENL3 ENCA0EC     DNFAENCA0IENL4

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 528 of 4535 Dec 26, 2018 Table 2C.63 Input Pins that Incorporate Digital Filter Type E Devises Digital Noise Elimination Control Register Digital Noise Elimination Enable Register Edge Detection Input Pin 48 Pins 64 Pins 80 Pins 100 Pins Control Register Address Control Register Control Bit Address Register Name SENT0RX     DNFA SENTICTL FFC3 00E0H DNFASENTIEN (DNFA SENTIENL) DNFASENTIENL0 FFC3 00E4H (FFC3 00ECH） —*4 SENT1RX     DNFASENTIENL1 Note 3. For the setting for ENCA edge detection, see Section 35.3.3, ENCAnIOC0 — ENCAn I/O Control Register 0. Note 4. RSENT does not have the edge detection.

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 529 of 4535 Dec 26, 2018 2C.12.2 Clock Supply for Port Filters The following table shows the clock supply for each filter type in each port domain. Table 2C.64 Clock Supply for Port Filters Setting Register Peripheral Function Port Domain*1 Filter Type Filter Clock Source Clock Selection Clock Selection ADCA0 Always-On area (AWO area) Digital filter type D DNFATCKI CKSC_AADCAS_CTL CKSC_AADCAD_CTL TAUD0 Isolated area (ISO area) Digital filter type E DNFATCKI CKSC_IPERI1S_CTL — TAUB0 Isolated area (ISO area) Digital filter type E DNFATCKI CKSC_IPERI2S_CTL — ENCA0 Isolated area (ISO area) Digital filter type E DNFATCKI CKSC_IPERI1S_CTL — RSENTn Isolated area (ISO area) Digital filter type E DNFATCKI CKSC_IPERI2S_CTL — Note 1. Power Domain NOTE For the Setting Register, see Section 12C.4.3, Clock Selector Control Register.

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 530 of 4535 Dec 26, 2018 2C.13 Description of Port Noise Filter & Edge/Level Detection External signals pass through different types of filters according to the use of each external input signal. NOTE In this section, <name> in the noise filter control register represents the peripheral function connected to a filter. 2C.13.1 Overview 2C.13.1.1 Analog Filter Types Analog filters have fixed characteristics.

• Type A: An analog filter with edge detection or level detection. Used for external interrupt signals.
• Type B: An analog filter Edge detection is performed by each peripheral function. Used for the timer input signals, asynchronous Hi -Z control input signals, and key return input signals.
• Type C: An analog filter only Used for the external RESET input and mode signals. 2C.13.1.2 Digital Filter Types The digital filter characteristics can be adjusted to suit the application.
• Type D: A digital filter with edge detection. Used for the A/D converter external trigger pin.
• Type E: A digital filter. Edge detection is performed by each peripheral function. Used for the timer in put signals and encoder input signals.

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 531 of 4535 Dec 26, 2018 2C.13.2 Analog Filters 2C.13.2.1 Analog Filter Characteristic See Section 47C, Electrical Characteristics of RH850/F1KM-S1 for the input conditions for signals input to pins that incorporate an analog filter. 2C.13.2.2 Analog Filter Control Registers A dedicated FCLA0CTLm_<name> register or control register in the peripheral macro is provided for input pins that incorporate an analog filter. The assignment of the input signals to the control registers and their addresses are given in Table 2C.59, Input Pins that Incorporate Analog Filter Type A. 2C.13.2.3 Analog Filter in Standby Mode Analog filters for the function of waking-up from the DeepSTOP mode are located in the Always-On area (AWO area). Analog filters in the Always-On area (AWO area) always operate. The analog filter in standby mode and its wake-up capability depend on the filter types. See the description of the analog filter types below. (1) Analog Filter Type A A block diagram of analog filter type A is shown below. Analog filter FCLA0CTLm_<name>.FCLA0INTLm_<name> EMCLK Input signal INTC Level detector Edge detector Figure 2C.12 Block Diagram of Analog Filter Type A After passing an external signal through the filter to eliminate noise and glitches, an output signal is generated according to whether an event is detected; that is whether a specified level is detected or whether a change in the level (an edge) occurs. Whether a level or an edge is detected is selected by the control bit FCLA0CTLm_<name>.FCLA0INTLm_<name>.

• FCLA0INTLm_<name> bit = 0: Edge detection Whether a rising or falling edge is detected can be specified by setting the FCLA0CTLm_<name>.FCLA0INTRm_<name> and FCLA0CTLm_<name>.FCLA0INTFm_<name> bits.

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 532 of 4535 Dec 26, 2018

• FCLA0INTLm_<name> bit = 1: Level detection The detection of a high level or low level can be specified by setting FCLA0CTLm_<name>.FCLA0INTRm_<name> bit. The table below summarizes the detection conditions of the analog filter. Table 2C.65 Analog Filter Event Detection Conditions FCLA0INTLm_<name> FCLA0INTFm_<name> FCLA0INTRm_<name> Edge Detection Level Detection 0 0 0 No edge detected Disabled 0 1 Rising edge 1 0 Falling edge 1 1 Rising and falling edges

Analog filter type A in Standby mode The output signal of an analog filter type A can always be used as a standby mode wake- up signal. (2) Analog filter type B A block diagram of analog filter type B is shown below. Analog filterInput signal Edge detection Peripheral function Figure 2C.13 Block Diagram of Analog Filter Type B Analog filter type B in Standby mode The output signal of an analog filter type B can always be used as a standby mode wake- up signal.

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 533 of 4535 Dec 26, 2018 (3) Analog filter type C A block diagram of analog filter type C is shown below. Peripheral functionAnalog filterInput signal Figure 2C.14 Block Diagram of Analog Filter Type C The generated signals are always input signals that have passed through an analog filter. Analog filter type C in Standby mode Pins equipped with type C analog filters in this product do not support the input of event signals to trigger wake -up from standby.

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 534 of 4535 Dec 26, 2018 2C.13.3 Digital Filters 2C.13.3.1 Digital Filter Characteristic The digital filters allow the filter characteristics to be adjusted accordingly to the needs of the application. The input signal is sampled with the sampling frequency fs. If a specified number of successive samples yield the same (high or low) level, the signal level is judged as valid and the filter output signal is set accordingly. If an external signal level change is detected within the specified number of samples (same level samples), the signal level is judged as noise and the filter output signal does not change. The length of an external signal pulse to be judged as noise depends on the sampling frequency and the specified number of same level samples. Both parameters can be specified:

• DNFA<name>CTL.DNFA<name>PRS[2:0] select the sampling frequency based on fs = fDNFATCKI / 2DNFA<name>PRS[2:0] where fDNFATCKI is the frequency of the DNFATCKI clock.
• DNFA<name>CTL.DNFA<name>NFSTS[1:0] determines the number of same level samples, “s”, (2 to 5): s = DNFA<name>NFSTS[1:0] + 2 External signal pulses shorter than the following are suppressed at all times. s ×1/fs External signal pulses longer than the following are always judged as valid and are passed on to the filter output. (s + 1) × 1/fs External signal pulses in the following range may be suppressed or judged as valid. s × 1/fs to (s + 1) × 1/fs The filter operation is illustrated in the figure below with DNFA<name>NFSTS[1:0] = 01B, i.e. s = 3 same level samples. Input signal Sampling points Digital filter output fs Figure 2C.15 Digital Filter Function

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 535 of 4535 Dec 26, 2018 2C.13.3.2 Digital Filter Groups The input signals processed through digital filters are ordered in groups of up to 16 signals. The digital filter characteristics, specified by DNFA<name>CTL.DNFA<name>PRS[2:0] and DNFA<name>NFSTS[1:0] apply to the signals. However, the digital filter for each signal can be enabled or disabled separately by DNFA<name>EN.DNFA<name>ENLm (m = 0 to 7) and DNFA<name>EN.DNFA<name>ENHm (m = 0 to 7). CAUTIONS 1. When the output signal from the digital filter is input to an alternative function, allow at least the following interval to elapse after the digital filter is enabled (DNFA<name>EN.DNFA<name>ENLm (m = 0 to 7) = 1 and DNFA<name>EN.DNFA<name>ENHm (m = 0 to 7) = 1) for the port pin to switch to the alternative function. s = DNFA<name>NFSTS[1:0] + 2 s × 1/fs + 2 × 1/fDNFATCKI 2. When a digital filter's output signal is used as an interrupt signal, only enable the digital filter (DNFA<name>EN.DNFA<name>ENLm (m = 0 to 7) = 1 and DNFA<name>EN.DNFA<name>ENHm (m = 0 to 7) = 1) while interrupts are disabled. Furthermore, only enable interrupts after enabling the digital filter, waiting for the time below to elapse, and then clearing the interrupt request flag. s × 1/fs + 3 × 1/fDNFATCKI 2C.13.3.3 Digital Filters in Standby Mode Digital filters for the function of waking-up from the DeepSTOP mode are located in the Always-On area (AWO area). Digital filters on the Always-On area (AWO area) are always operating. Digital noise elimination requires the clock supply DNFATCKI to operate. Pins equipped with digital filters in this product do not support the input of event signals to trigger wake -up from standby.

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 536 of 4535 Dec 26, 2018 2C.13.3.4 Digital Filter Control Registers For each group consisting of up to 16 digital filters, the digital noise elimination control register DNFA< name>CTL and digital noise elimination enable register DNFA<name>EN are used to set all the filters in the same group (<name> = peripheral function group). The DNFA<name>CTL register specifies the characteristics of the digital noise elimination filter for the digital filter of <name>. The DNFA<name>EN register enables/disables each filter by setting the corresponding bit in DNFA<name>EN.DNFA<name>ENLm (m = 0 to 7) and DNFA<name>EN.DNFA<name>ENHm (m = 0 to 7). The edge detection setup is done via the filter dedicated control register and the registers for individual peripheral functions. The FCLA0CTLm_ADCn registers are ordered in groups of 3 registers with the same index n. The register index n is in 0 or 1. The assignment of the input signals to the control registers and their addresses are given in Table 2C.62, Input Pins that Incorporate Digital Filter Type D and Table 2C.63, Input Pins that Incorporate Digital Filter Type E in Section 2C.12.1, Port Filter Assignment. CAUTION Do not change any control register settings while the corresponding digital filter is enabled by DNFA<name>EN.DNFA<name>ENLm (m = 0 to 7) = 1 and DNFA<name>EN.DNFA<name>ENHm (m = 0 to 7) = 1. Otherwise an unintended filter output may be generated. (1) Digital filter type D A block diagram of digital filter type D is shown below. Digital filter Peripheral function Prescaler fs Input signal DNFATCKI 1Edge detector “L” DNFA<name>EN.DNFA<name>ENLm Figure 2C.16 Block Diagram of Digital Filter Type D The generated signal depends on the register setting, as shown in the following table. Table 2C.66 Output Options for Digital Filter Type D DNFA<name>EN.DNFA<name>ENLm Signals Output to Peripheral Functions

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 537 of 4535 Dec 26, 2018 (2) Digital filter type E A block diagram of digital filter type E is shown below. Digital filter Edge detection Prescaler Input signal DNFATCKI DNFA<name>EN.DNFA<name>ENLm and DNFA<name>EN.DNFA<name>ENHm “L” Peripheral function fs Figure 2C.17 Block Diagram of Digital Filter Type E The generated signal depends on the register setting, as shown in the following table. Table 2C.67 Output Options for Digital Filter Type E DNFA<name>EN.DNFA<name>ENLm and DNFA<name>EN.DNFA<name>ENHm Signals Output to Peripheral Functions 2C.13.4 Filter Control Registers The analog and digital filters are controlled and operated by the following registers: Table 2C.68 List of Filter Registers Module Name Register Name Symbol Address FCLA0 Filter control register m FCLA0CTLm_<name> The addresses are shown in the tables in Section 2C.12.1, Port Filter Assignment. DNF Digital noise elimination control register DNFA<name>CTL Digital noise elimination enable register DNFA<name>EN Digital noise elimination enable H register DNFA<name>ENH Digital noise elimination enable L register DNFA<name>ENL

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 538 of 4535 Dec 26, 2018 2C.13.4.1 FCLA0CTLm_<name> — Filter Control Register This register controls the analog and digital filter operation. Access: This register can be read or written in 8-bit units. Address: The allocation of input signals to FCLA0CTLm_<name> registers and the address of each register are shown in the tables in Section 2C.12.1, Port Filter Assignment. Value after reset: 00H Bit 7 6 5 4 3 2 1 0 _<name> FCLA0INTFm _<name> FCLA0INTRm _<name> Value after reset 0 0 0 0 0 0 0 0 R/W R R R R R R/W R/W R/W Table 2C.69 FCLA0CTLm_<name> Register Contents Bit Position Bit Name Function 7 to 3 Reserved When read, the value after reset is returned. When writing, write the value after reset.

2 FCLA0INTLm_

<name> Detection Mode Selection 0: Edge detection 1: Level detection NOTE: This bit is only valid for analog filter type A.

1 FCLA0INTFm_

<name>

• In level detection mode (FCLA0INTLm_<name> = 1): This bit has no effect.
• In edge detection mode (FCLA0INTLm_<name> = 0): Falling edge detection control 0: Falling edge detection disabled 1: Falling edge detection enabled NOTE: This bit is only valid for analog filter type A and digital filter type D. However, digital filter type D is placed in edge detection mode.

0 FCLA0INTRm_

<name>

• In level detection mode (FCLA0INTLm_<name> = 1): Detected level selection 0: Low level detection 1: High level detection
• In edge detection mode (FCLA0INTLm_<name> = 0): Rising edge detection control 0: Rising edge detection disabled 1: Rising edge detection enabled NOTE: This bit is only valid for analog filter type A and digital filter type D. However, digital filter type D is placed in edge detection mode. CAUTION Digital filter type D: Always set bit 2 to “0”.

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 539 of 4535 Dec 26, 2018 2C.13.4.2 DNFA<name>CTL — Digital Noise Elimination Control Register This register is used to specify the filter characteristics of the digital noise elimination filter. NOTE This register is only valid for digital filter type D and digital filter type E. Access: This register can be read or written in 8-bit units. Address: For the correspondence between the DNFA<name>CTL register and input signals, and the addresses of individual registers, see Table 2C.62, Input Pins that Incorporate Digital Filter Type D and Table 2C.63, Input Pins that Incorporate Digital Filter Type E in Section 2C.12.1, Port Filter Assignment. Value after reset: 00H Bit 7 6 5 4 3 2 1 0 — DNFA<name>NFSTS[1:0] — — DNFA<name>PRS[2:0] Value after reset 0 0 0 0 0 0 0 0 R/W R R/W R/W R R R/W R/W R/W Table 2C.70 DNFA<name>CTL Register Contents Bit Position Bit Name Function 7 Reserved When read, the value after reset is returned. When writing, write the value after reset. 6, 5 DNFA<name> NFSTS[1:0] The DNFA<name>NFSTS[1:0] bits specify the number of samples used to judge whether an external signal pulse is valid. DNFA<name>NFSTS[1:0] Number of Samples 00B 2 01B 3 10B 4 11B 5 4, 3 Reserved When read, the value after reset is returned. When writing, write the value after reset. 2 to 0 DNFA<name> PRS[2:0] Digital filter sampling clock selection DNFA<name>PRS[2:0] Sampling Clock Frequency 000B DNFATCKI/1 001B DNFATCKI/2 010B DNFATCKI/4 011B DNFATCKI/8 100B DNFATCKI/16 101B DNFATCKI/32 110B DNFATCKI/64 111B DNFATCKI/128

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 540 of 4535 Dec 26, 2018 2C.13.4.3 DNFA<name>EN — Digital Noise Elimination Enable Register This register enables and disables digital noise elimination for a specified input signal. NOTE This register is only valid for digital filter type D and digital filter type E. Access: This register can be read or written in 16-bit units. The upper- and lower-order bytes (DNFA<name>ENH[7:0] and DNFA<name>ENL[7:0]) are accessible in 8- or 1-bit units respectively by setting DNFA<name>ENH. and DNFA<name>ENL. Address: For the correspondence between the DNFA<name>EN register and input signals, and the addresses of individual registers, see Table 2C.62, Input Pins that Incorporate Digital Filter Type D and Table 2C.63, Input Pins that Incorporate Digital Filter Type E in Section 2C.12.1, Port Filter Assignment. Value after reset: 0000H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DNFA <name> ENH7 DNFA <name> ENH6 DNFA <name> ENH5 DNFA <name> ENH4 DNFA <name> ENH3 DNFA <name> ENH2 DNFA <name> ENH1 DNFA <name> ENH0 DNFA <name> ENL7 DNFA <name> ENL6 DNFA <name> ENL5 DNFA <name> ENL4 DNFA <name> ENL3 DNFA <name> ENL2 DNFA <name> ENL1 DNFA <name> ENL0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Table 2C.71 DNFA<name>EN Register Contents Bit Position Bit Name Function 15 to 0 DNFA<name> ENH[7:0] DNFA<name> ENL[7:0] Digital Noise Elimination Enable/Disable Control 0: Fixed to low level 1: Input signal passed through filter

RH850/F1KH, RH850/F1KM Section 2C Pin Function of RH850/F1KM-S1 R01UH0684EJ0110 Rev.1.10 Page 541 of 4535 Dec 26, 2018 2C.13.4.4 DNFA<name>ENH — Digital Noise Elimination Enable H Register Setting in this register correspond to those of the 8 upper-order bits of the DNFA<name>EN register. NOTE This register is only valid for digital filter type E. Access: This register can be read or written in 8-bit or 1-bit units. Address: For the correspondence between the DNFA<name>ENH register and input signals, and the addresses of individual registers, see Table 2C.63, Input Pins that Incorporate Digital Filter Type E in Section 2C.12.1, Port Filter Assignment. Value after reset: 00H Bit 7 6 5 4 3 2 1 0 DNFA<name> ENH7 DNFA<name> ENH6 DNFA<name> ENH5 DNFA<name> ENH4 DNFA<name> ENH3 DNFA<name> ENH2 DNFA<name> ENH1 DNFA<name> ENH0 Value after reset 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W For details of the respective bit functions, see Section 2C.13.4.3, DNFA<name>EN — Digital Noise Elimination Enable Register. 2C.13.4.5 DNFA<name>ENL — Digital Noise Elimination Enable L Register Setting in this register correspond to those of the 8 lower-order bits of the DNFA<name>EN register. NOTE This register is only valid for digital filter type D and digital filter type E. Access: This register can be read or written in 8-bit or 1-bit units. Address: For the correspondence between the DNFA<name>ENL register and input signals, and the addresses of individual registers, see Table 2C.62, Input Pins that Incorporate Digital Filter Type D and Table 2C.63, Input Pins that Incorporate Digital Filter Type E in Section 2C.12.1, Port Filter Assignment. Value after reset: 00H Bit 7 6 5 4 3 2 1 0 DNFA<name> ENL7 DNFA<name> ENL6 DNFA<name> ENL5 DNFA<name> ENL4 DNFA<name> ENL3 DNFA<name> ENL2 DNFA<name> ENL1 DNFA<name> ENL0 Value after reset 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W For details of the respective bit functions, see Section 2C.13.4.3, DNFA<name>EN — Digital Noise Elimination Enable Register.

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 543 of 4535 Dec 26, 2018 CPU1 (PE1) The RH850G3KH2.0 Core is used as the main CPU. CPU2 (PE2) The RH850G3KH2.0 Core is used as an enhanced performance CPU. Local RAM Each CPU has a high-speed accessible RAM Global RAM The global RAM is a large-capacity RAM for data sharing among CPUs and with DMA. Retention RAM The retention RAM is used to retain values in DeepSTOP mode. Since the continuous global RAM area is assigned for the retention RAM, the retention RAM can also serve as a global RAM for sharing data with the DMA. Code flash The code flash memory is included for program storage. It is connected with CPU1 and CPU2 via the flash interface. Data flash The data flash memory can be rewritten by the CPUs. It has a greater write endurance than the code flash memory. P-Bus and H-Bus The P-Bus connects the peripheral IPs. The P-Bus is divided into five peripheral groups, 1 to 5. INTC1, INTC2 There are two interrupt controllers, INTC1 and INTC2. INTC1 is an interrupt controller exclusive to each CPU. INTC2 is a common interrupt controller that CPU1 and CPU2 share. The PE to which an interrupt request is bound can be specified by a register setting. DMA The DMA transfer module (PDMA) is included. Slave guard The slave guard is a function to prevent unauthorized access from the specific bus master, and consists of the following guard structures: (1) PE guard (PEG) The PE guard is a function to prevent unauthorized access to the resources (local RAM) in the PE from an external master. After reset is released, access from other than the own PE is prohibited. (2) Internal Peripheral Guard (IPG) The PE with system interconnects supports “Internal Peripheral Guard” (IPG) that protects the registers of peripherals against invalid accesses. (3) Global RAM guard (GRG) The global RAM guard is a function to prevent unauthorized access to the global RAM and retention RAM from

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 544 of 4535 Dec 26, 2018 an external master. The global RAM is in the unprotected state (accessible from all bus master) after reset is released. For details, see Section 40A, Functional Safety of RH850/F1KH-D8. (4) Peripheral guard (PBG / HBG) The peripheral guard is a function to prevent unauthorized access to peripherals. The control registers in the peripheral circuits are protected against illegal accesses. For details, see Section 40A, Functional Safety of RH850/F1KH-D8.

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 545 of 4535 Dec 26, 2018 3A.2 CPU 3A.2.1 Core Functions 3A.2.1.1 Features Table 3A.1, Features of the RH850G3KH2.0 Core lists features of the RH850G3KH2.0 core. Table 3A.1 Features of the RH850G3KH2.0 Core Item Feature CPU ● Advanced 32-bit architecture for embedded control

• 32-bit internal data bus
• Thirty-two 32-bit general-purpose registers – RISC-type instruction set – Long-/short-format load/store instructions – Three-operand instructions – Instruction set based on C language
• CPU operating modes – User mode and supervisor mode
• Address space: 4-Gbyte linear address space for both data and instructions Coprocessor ● Floating-point operation coprocessor (FPU) – Supports single precision (32 bits) – Supports data types and exceptions conforming to IEEE754. – Rounding mode: Neighborhood, 0 direction, +∞ direction, and −∞ direction – Handling of denormalized numbers: Rounding down to 0 or exception notification to conform to IEEE754 Exception/Interrupt ● 16 interrupt priority levels settable for each channel
• Vector selection method selectable according to performance request or memory usage – Direct branching exception vectors – Indirect branching exception vectors referring to the address table
• Supports the high-speed save/return processing of the context by the dedicated instructions (PUSHSP and POPSP) at the generation of an interrupt Memory management ● Memory protection function (MPU): 16 areas settable Cache ● No cache memory is equipped.

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 546 of 4535 Dec 26, 2018 3A.2.1.2 Register Set This subsection explains the program registers and system registers incorporated in this CPU. (1) Program Registers Program registers include the general-purpose registers (r0 to r31) and program counter (PC). Table 3A.2 Program Registers Program Register Name Function Description General-purpose registers r0 Zero register Always retains “0” r1 Assembler reserved register Used as working register for generating addresses r2 Register for address and data variables (used when the real-time OS used does not use this register) r3 Stack pointer (SP) Used for generating a stack frame when a function is called r4 Global pointer (GP) Used for accessing a global variable in the data area r5 Text pointer (TP) Used as a register that indicates the start of the text area (area where program code is placed) r6 to r29 Register for address and data variables r30 Element pointer (EP) Used as a base pointer for generating addresses when accessing memory r31 Link pointer (LP) Used when the compiler calls a function Program counter PC Retains instruction addresses during execution of programs NOTE For further descriptions of r1, r3 to r5, and r31 used by the assembler and/or C compiler, see the specification of each software development environment.

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 547 of 4535 Dec 26, 2018 (a) General-Purpose Registers A total of 32 general-purpose registers (r0 to r31) are provided. All of these registers can be used for either data variables or address variables. Of the general-purpose registers, r0 to r5, r30, and r31 are assumed to be used for special purposes in software development environments, so it is necessary to note the following when using them. 1. r0, r3, r30 These registers are implicitly used by instructions. r0 is a register that always retains “0”. It is used for operations that use 0 and addressing with base address being 0. r3 is implicitly used by the PREPARE, DISPOSE, PUSHSP, and POPSP instructions. r30 is used as a base pointer when the SLD or SST instruction accesses memory. 2. r1, r4, r5, r31 These registers are implicitly used by the assembler and C compiler. When using these registers, register contents must first be saved so they are not lost and can be restored after the registers are used. 3. r2 This register might be used by a real-time OS in some cases. If the real-time OS that is being used does not use r2, r2 can be used as a register for address variables or data variables. (b) PC — Program Counter The PC retains the address of the instruction being executed. Bit 0 is fixed to 0, and branching to an odd number address is disabled. 31 0 Value after reset *1 PC PC31 to PC0 Table 3A.3 PC Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 1 PC31 to PC1 These bits indicate the address of the instruction being executed. R/W *1 0 PC0 This bit is fixed to 0. Branching to an odd number address is disabled. R/W 0 Note 1. The value after reset differs depending on the setting value of the reset vector. For details, see (q) RBASE — Reset Vector Base Address Register.

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 548 of 4535 Dec 26, 2018 (2) Basic System Registers The basic system registers are used to control CPU status and to retain exception information. System registers are read from or written to by using the LDSR and STSR instructions and specifying the system register number, which is made up of a register number and a selection ID. Table 3A.4 Basic System Registers Register No. (regID, selID) Symbol Function Access Permission SR0, 0 EIPC Status save registers when acknowledging EI level exception SV SR1, 0 EIPSW Status save registers when acknowledging EI level exception SV SR2, 0 FEPC Status save registers when acknowledging FE level exception SV SR3, 0 FEPSW Status save registers when acknowledging FE level exception SV SR5, 0 PSW Program status word *1 SR6, 0 FPSR (Refer to FPU function registers.) CU and SV SR7, 0 FPEPC (Refer to FPU function registers.) CU and SV SR8, 0 FPST (Refer to FPU function registers.) CU SR9, 0 FPCC (Refer to FPU function registers.) CU SR10, 0 FPCFG (Refer to FPU function registers.) CU SR11, 0 FPEC (Refer to FPU function registers.) CU and SV SR13, 0 EIIC EI level exception source register SV SR14, 0 FEIC FE level exception source register SV SR16, 0 CTPC CALLT execution status save register UM SR17, 0 CTPSW CALLT execution status save register UM SR20, 0 CTBP CALLT base pointer register UM SR28, 0 EIWR EI level exception working register SV SR29, 0 FEWR FE level exception working register SV SR0, 1 MCFG0 Machine configuration register SV SR2, 1 RBASE Reset vector base address register SV SR3, 1 EBASE Exception handler vector address register SV SR4, 1 INTBP Base address register of the interrupt handler address table SV SR5, 1 MCTL CPU control SV SR6, 1 PID Processor ID register SV SR11, 1 SCCFG SYSCALL operation setting register SV SR12, 1 SCBP SYSCALL base pointer register SV SR0, 2 HTCFG0 Thread configuration register SV SR6, 2 MEA Memory error address register SV SR7, 2 ASID Address space ID register SV SR8, 2 MEI Memory error information register SV Note 1. The access permission differs depending on the bit.

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 549 of 4535 Dec 26, 2018 (a) EIPC — Status Save Register when Acknowledging EI Level Exception When an EI level exception is acknowledged, the address of the instruction that was being executed when the EI level exception occurred, or of the next instruction, is saved to the EIPC register (see “Types of Exceptions” in Software Manual). Because there is only one pair of EI level exception status save registers, when processing multiple exceptions, the contents of these registers must be saved by a program. Be sure to set an even-numbered address to the EIPC register. An odd-numbered address cannot be specified. 31 0 Value after reset Undefined EIPC EIPC31 to EIPC0 Table 3A.5 EIPC Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 1 EIPC31 to EIPC1 These bits indicate the PC saved when an EI level exception is acknowledged. R/W Undefined 0 EIPC0 This bit indicates the PC saved when an EI level exception is acknowledged. Always set this bit to 0. Even if it is set to 1, the value transferred to the PC when the EIRET instruction is executed is 0. R/W Undefined

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 550 of 4535 Dec 26, 2018 (b) EIPSW — Status Save Register when Acknowledging EI Level Exception When an EI level exception is acknowledged, the current PSW setting is saved to the EIPSW register. Because there is only one pair of EI level exception status save registers, when processing multiple exceptions, the contents of these registers must be saved by a program. 31 30 29 17 16 15 14 8 7 6 5 4 3 2 1 0 U M C U E B V N P E P I D S A T C Y O V S Z Value after reset 0000 0020H EIPSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3A.6 EIPSW Register Contents Bit Position Bit Name Function R/W Value after Reset 31 — (Reserved for future expansion. Be sure to set to 0.) R 0 30 UM This bit stores the PSW.UM bit setting when an EI level exception is acknowledged. R/W 0 29 to 17 — (Reserved for future expansion. Be sure to set to 0.) R 0 16 CU This bit stores the PSW.CU field setting when an EI level exception is acknowledged. R/W 0 15 EBV This bit stores the PSW.EBV bit setting when an EI level exception is acknowledged. R/W 0 14 to 8 — (Reserved for future expansion. Be sure to set to 0.) R 0 7 NP This bit stores the PSW.NP bit setting when an EI level exception is acknowledged. R/W 0 6 EP This bit stores the PSW.EP bit setting when an EI level exception is acknowledged. R/W 0 5 ID This bit stores the PSW.ID bit setting when an EI level exception is acknowledged. R/W 1 4 SAT This bit stores the PSW.SAT bit setting when an EI level exception is acknowledged. R/W 0 3 CY This bit stores the PSW.CY bit setting when an EI level exception is acknowledged. R/W 0 2 OV This bit stores the PSW.OV bit setting when an EI level exception is acknowledged. R/W 0 1 S This bit stores the PSW.S bit setting when an EI level exception is acknowledged. R/W 0 0 Z This bit stores the PSW.Z bit setting when an EI level exception is acknowledged. R/W 0

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 551 of 4535 Dec 26, 2018 (c) FEPC — Status Save Register when Acknowledging FE Level Exception When an FE level exception is acknowledged, the address of the instruction that was being executed when the FE level exception occurred, or of the next instruction, is saved to the FEPC register (see “Types of Exceptions” in Software Manual). Because there is only one pair of FE level exception status save registers, when processing multiple exceptions, the contents of these registers must be saved by a program. Be sure to set an even-numbered address to the FEPC register. An odd-numbered address cannot be specified. 31 0 Value after reset Undefined FEPC FEPC31 to FEPC0 Table 3A.7 FEPC Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 1 FEPC31 to FEPC1 These bits indicate the PC saved when an FE level exception is acknowledged. R/W Undefined 0 FEPC0 This bit indicates the PC saved when an FE level exception is acknowledged. Always set this bit to 0. Even if it is set to 1, the value transferred to the PC when the FERET instruction is executed is 0. R/W Undefined

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 552 of 4535 Dec 26, 2018 (d) FEPSW — Status Save Register when Acknowledging FE Level Exception When an FE level exception is acknowledged, the current PSW setting is saved to the FEPSW register. Because there is only one pair of FE level exception status save registers, when processing multiple exceptions, the contents of these registers must be saved by a program. 31 30 29 17 16 15 14 8 7 6 5 4 3 2 1 0 U M C U E B V N P E P I D S A T C Y O V S Z Value after reset 0000 0020H FEPSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3A.8 FEPSW Register Contents Bit Position Bit Name Function R/W Value after Reset 31 — (Reserved for future expansion. Be sure to set to 0.) R 0 30 UM This bit stores the PSW.UM bit setting when an FE level exception is acknowledged. R/W 0 29 to 17 — (Reserved for future expansion. Be sure to set to 0.) R 0 16 CU This bit stores the PSW.CU field setting when an FE level exception is acknowledged. R/W 0 15 EBV This bit stores the PSW.EBV bit setting when an FE level exception is acknowledged. R/W 0 14 to 8 — (Reserved for future expansion. Be sure to set to 0.) R 0 7 NP This bit stores the PSW.NP bit setting when an FE level exception is acknowledged. R/W 0 6 EP This bit stores the PSW.EP bit setting when an FE level exception is acknowledged. R/W 0 5 ID This bit stores the PSW.ID bit setting when an FE level exception is acknowledged. R/W 1 4 SAT This bit stores the PSW.SAT bit setting when an FE level exception is acknowledged. R/W 0 3 CY This bit stores the PSW.CY bit setting when an FE level exception is acknowledged. R/W 0 2 OV This bit stores the PSW.OV bit setting when an FE level exception is acknowledged. R/W 0 1 S This bit stores the PSW.S bit setting when an FE level exception is acknowledged. R/W 0 0 Z This bit stores the PSW.Z bit setting when an FE level exception is acknowledged. R/W 0

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 553 of 4535 Dec 26, 2018 (e) PSW — Program Status Word PSW (program status word) is a set of flags that indicate the program status (instruction execution result) and bits that indicate the operation status of the CPU (flags are bits in the PSW that are referenced by conditional instructions (Bcond, CMOV, etc.)). CAUTIONS 1. When the LDSR instruction is used to change the contents of bit7 to 0 in this register, the changed contents become valid immediately after completion of the LDSR instruction execution. See “APPENDIX A. Hazard Resolution Procedure for System Registers” in Software Manual when the content of the other bits in this register is changed. 2. The access permission for the PSW register differs depending on the bit. All bits can be read, but some bits can only be written under certain conditions. See Table 3A.9, Access Permission for PSW Register for the access permission for each bit. Table 3A.9 Access Permission for PSW Register Bit Access Permission when Reading Access Permission when Writing

30 UM UM SV*1

16 CU UM SV*1

15 EBV UM SV*1

7 NP UM SV*1

6 EP UM SV*1

5 ID UM SV*1

4 SAT UM UM

3 CY UM UM

2 OV UM UM

1 S UM UM

0 Z UM UM

Note 1. The access permission for the whole PSW register is UM, so the PIE exception does not occur even if the register is written by using an LDSR instruction when PSW.UM is 1. In this case, writing is ignored. 31 30 29 17 16 15 14 8 7 6 5 4 3 2 1 0 U M C U E B V N P E P I D S A T C Y O V S Z Value after reset 0000 0020H PSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3A.10 PSW Register Contents Bit Position Bit Name Function R/W Value after Reset 31 — (Reserved for future expansion. Be sure to set to 0.) R 0

30 UM This bit indicates that the CPU is in user mode (in UM mode)

0: Supervisor mode 1: User mode R/W 0 29 to 17 — (Reserved for future expansion. Be sure to set to 0.) R 0 16 CU This bit indicates the coprocessor use permissions. When the bit corresponding to the coprocessor is 0, a coprocessor unusable exception occurs if an instruction for the coprocessor is executed or a coprocessor resource (system register) is accessed. CU bit 16: FPU R/W 0

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 554 of 4535 Dec 26, 2018 Table 3A.10 PSW Register Contents Bit Position Bit Name Function R/W Value after Reset 15 EBV This bit indicates the reset vector and exception vector operation. See the description on RBASE ((q) RBASE — Reset Vector Base Address Register) and EBASE ((r) EBASE — Exception Handler Vector Address Register) in this section. R/W 0 14 to 8 — (Reserved for future expansion. Be sure to set to 0.) R 0 7 NP This bit disables the acknowledgement of FE level exception. When an FE level exception is acknowledged, this bit is set to 1 to disable the acknowledgement of EI level and FE level exceptions. As for the exceptions which the NP bit disables the acknowledgment, see Table 7A.1, List of Exception Sources. 0: The acknowledgement of FE level exception is enabled. 1: The acknowledgement of FE level exception is disabled. R/W 0

6 EP This bit indicates that an exception other than an interrupt controlled by the

interrupt controller is being serviced. It is set to 1 when the corresponding exception occurs. This bit does not affect acknowledging an exception request even when it is set to 1. 0: An exception other than an interrupt is not being serviced. 1: An exception other than an interrupt is being serviced. R/W 0 5 ID This bit disables the acknowledgement of EI level exception. When an EI level or FE level exception is acknowledged, this bit is set to 1 to disable the acknowledgement of EI level exception. As for the exceptions which the ID bit disables the acknowledgment, see Table 7A.1, List of Exception Sources. This bit is also used to disable EI level exceptions from being acknowledged as a critical section while an ordinary program or interrupt is being serviced. It is set to 1 when the DI instruction is executed, and cleared to 0 when the EI instruction is executed. The change of the ID bit by the EI or ID instruction will be enabled from the next instruction. 0: EI level exception is not being processed or the section is not a critical section (after execution of EI instruction). 1: EI level exception is being processed or the section is a critical section (after execution of DI instruction). R/W 1

4 SAT*1 This bit indicates that the operation result is saturated because the operation

result of a saturated operation instruction has overflowed. This is a cumulative flag, so when the operation result of the saturated operation instruction becomes saturated, this bit is set to 1, but it is not cleared to 0 when the operation result for a subsequent instruction is not saturated. This bit is cleared to 0 by the LDSR instruction. This bit is neither set to 1 nor cleared to 0 when an arithmetic operation instruction is executed. 0: Not saturated 1: Saturated R/W 0

3 CY This bit indicates whether a carry or borrow has occurred in the operation

result. 0: Carry and borrow have not occurred. 1: Carry or borrow has occurred. R/W 0

2 OV*1 This bit indicates whether or not an overflow has occurred during an

operation. 0: Overflow has not occurred. 1: Overflow has occurred. R/W 0 1 S*1 This bit indicates whether or not the result of an operation is negative. 0: Result of operation is positive or 0. 1: Result of operation is negative. R/W 0 0 Z This bit indicates whether or not the result of an operation is 0. 0: Result of operation is not 0. 1: Result of operation is 0. R/W 0 Note 1. The operation result of the saturation processing is determined in accordance with the contents of the OV flag and S flag during a saturated operation. The SAT flag is set to 1 only when the OV flag is set to 1 in a saturated operation.

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 555 of 4535 Dec 26, 2018 Flag Status Operation Result after Saturation Processing Operation Result Status SAT OV S Exceeded positive maximum value 1 1 0 7FFF FFFFH Exceeded negative maximum value 1 1 1 8000 0000H Positive (maximum value not exceeded) Value prior to operation is retained. 0 0 Operation result itself Negative (maximum value not exceeded) 1 (f) EIIC — EI Level Exception Source Register The EIIC register retains the source of any EI level exception that occurs. The value retained in this register is an exception source code corresponding to a specific exception source. 31 0 Value after reset 0000 0000H EIIC EIIC31 to EIIC0 Table 3A.11 EIIC Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 0 EIIC31 to EIIC0 These bits store the exception source code when an EI level exception is acknowledged. The EIIC15 to EIIC0 field stores the lower 16 bits of the exception source code. The EIIC31 to EIIC16 field stores detailed exception source codes defined individually for each exception. If there is no particular definition of a function related to the exception, these bits are set to 0. R/W 0 (g) FEIC — FE Level Exception Source Register The FEIC register retains the source of any FE level exception that occurs. The value retained in this register is an exception source code corresponding to a specific exception source. 31 0 Value after reset 0000 0000H FEIC FEIC31 to FEIC0 Table 3A.12 FEIC Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 0 FEIC31 to FEIC0 These bits store the exception source code when an FE level exception is acknowledged. The FEIC15 to FEIC0 field stores the lower 16 bits of the exception source code. The FEIC31 to FEIC16 field stores detailed exception source codes defined individually for each exception. If there is no particular definition of a function related to the exception, these bits are set to 0. R/W 0

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 556 of 4535 Dec 26, 2018 (h) CTPC — Status Save Register when Executing CALLT Instruction When a CALLT instruction is executed, the address of the next instruction after the CALLT instruction is saved to CTPC. Be sure to set an even-numbered address to the CTPC register. An odd-numbered address cannot be specified. 31 0 Value after reset Undefined CTPC CTPC31 to CTPC0 Table 3A.13 CTPC Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 1 CTPC31 to CTPC1 These bits indicate the PC of the instruction after the CALLT instruction. R/W Undefined 0 CTPC0 This bit indicates the PC of the instruction after the CALLT instruction. Always set this bit to 0. Even if it is set to 1, the value transferred to the PC when the CTRET instruction is executed is 0. R/W Undefined (i) CTPSW — Status Save Register when Executing CALLT Instruction When a CALLT instruction is executed, some of the PSW (program status word) settings are saved to CTPSW. 31 5 4 3 2 1 0 S A T C Y O V Value after reset 0000 0000H CTPSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 S Z Table 3A.14 CTPSW Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 5 — (Reserved for future expansion. Be sure to set to 0.) R 0 4 SAT This bit stores the PSW.SAT bit setting when the CALLT instruction is executed. R/W 0 3 CY This bit stores the PSW.CY bit setting when the CALLT instruction is executed. R/W 0 2 OV This bit stores the PSW.OV bit setting when the CALLT instruction is executed. R/W 0 1 S This bit stores the PSW.S bit setting when the CALLT instruction is executed. R/W 0 0 Z This bit stores the PSW.Z bit setting when the CALLT instruction is executed. R/W 0

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 557 of 4535 Dec 26, 2018 (j) CTBP — CALLT Base Pointer Register The CTBP register is used to specify table addresses of the CALLT instruction and generate target addresses. Be sure to set the CTBP register to a halfword address. 31 0 Value after reset Undefined CTBP CTBP31 to CTBP0 Table 3A.15 CTBP Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 1 CTBP31 to CTBP1 These bits indicate the base pointer address of the CALLT instruction. These bits indicate the start address of the table used by the CALLT instruction. R/W Undefined 0 CTBP0 This bit indicates the base pointer address of the CALLT instruction. This bit indicates the start address of the table used by the CALLT instruction. Always set this bit to 0. R 0 (k) ASID — Address Space ID Register This register indicates the address space ID. This is used to identify the address space provided by the memory management function. 31 10 9 0 Value after reset Undefined ASID 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASID Table 3A.16 ASID Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 10 — (Reserved for future expansion. Be sure to set to 0.) R 0 9 to 0 ASID These bits indicate the address space ID. R/W Undefined (l) EIWR — EI Level Exception Working Register The EIWR register is used as a working register when an EI level exception has occurred. 31 0 Value after reset Undefined EIWR EIWR31 to EIWR0 Table 3A.17 EIWR Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 0 EIWR31 to EIWR0 These bits constitute a working register that can be used for any purpose during the servicing of an EI level exception. This register can be used to temporarily save the values of general-purpose registers, etc. R/W Undefined

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 558 of 4535 Dec 26, 2018 (m) FEWR — FE Level Exception Working Register The FEWR register is used as a working register when an FE level exception has occurred. 31 0 Value after reset Undefined FEWR FEWR31 to FEWR0 Table 3A.18 FEWR Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 0 FEWR31 to FEWR0 These bits constitute a working register that can be used for any purpose during the servicing of an FE level exception. This register can be used to temporarily save the values of general-purpose registers, etc. R/W Undefined (n) HTCFG0 — Thread Configuration Register 31 19 18 17 16 15 14 0 Value after reset *1 HTCFG0 0 0 0 0 0 0 0 0 0 0 0 0 0 PEID 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3A.19 HTCFG0 Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 19 — (Reserved for future expansion. Be sure to set to 0.) R 0 18 to 16 PEID These bits indicate the processor element number. R *2 15 — (Reserved for future expansion. Be sure to set to 1.) R 1 14 to 0 — (Reserved for future expansion. Be sure to set to 0.) R 0 Note 1. The value after reset is 0001 8000H for CPU1 (PE1) and 0002 8000H for CPU2 (PE2). Note 2. The value after reset is 001B for CPU1 (PE1) and 010B for CPU2 (PE2). (o) MEA — Memory Error Address Register 31 0 Value after reset Undefined MEA MEA Table 3A.20 MEA Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 0 MEA These bits store the violation address when an MAE (misaligned) or MPU occurs. R/W Undefined

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 559 of 4535 Dec 26, 2018 (p) MEI — Memory Error Information Register This register is used to store information about the instruction that caused a misaligned (MAE) or memory protection (MDP) exception when such an exception occurred. This information is used during emulation. 31 21 20 16 15 11 10 9 8 7 6 5 1 0 R W Value after reset Undefined MEI 0 0 0 0 0 0 0 0 0 0 0 REG 0 0 0 0 0 DS 0 0 ITYPE Table 3A.21 MEI Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 21 — (Reserved for future expansion. Be sure to set to 0.) R 0 20 to 16 REG These bits indicate the number of the source or destination register accessed by the instruction that caused the exception. For details, see Table 3A.22, Instructions Causing Exceptions and Values of MEI Register. R/W Undefined 15 to 11 — (Reserved for future expansion. Be sure to set to 0.) R 0 10, 9 DS These bits indicate the data type of the instruction that caused the exception.*1 0: Byte (8 bits) 1: Halfword (16 bits) 2: Word (32 bits) 3: Double-word (64 bits) For details, see Table 3A.22, Instructions Causing Exceptions and Values of MEI Register. R/W Undefined

8 U This bit indicates the sign extension method of the instruction that caused the

exception. 0: Signed 1: Unsigned For details, see Table 3A.22, Instructions Causing Exceptions and Values of MEI Register. R/W Undefined 7, 6 — (Reserved for future expansion. Be sure to set to 0.) R 0 5 to 1 ITYPE These bits indicate the instruction that caused the exception. For details, see Table 3A.22, Instructions Causing Exceptions and Values of MEI Register. R/W Undefined

0 RW This bit indicates whether the operation of the instruction that caused the

exception was read (Load-memory) or write (Store-memory). 0: Read (Load-memory) 1: Write (Store-memory) For details, see Table 3A.22, Instructions Causing Exceptions and Values of MEI Register. R/W Undefined Note 1. Even if the data is divided and access is made several times due to the specifications of the hardware, the original data type indicated by the instruction is stored. Table 3A.22 Instructions Causing Exceptions and Values of MEI Register Instruction REG DS U RW ITYPE SLD.B dst 0 (byte) 0 (signed) 0 (read) 00000B SLD.BU dst 0 (byte) 1 (unsigned) 0 (read) 00000B SLD.H dst 1 (halfword) 0 (signed) 0 (read) 00000B SLD.HU dst 1 (halfword) 1 (unsigned) 0 (read) 00000B SLD.W dst 2 (word) 0 (signed) 0 (read) 00000B SST.B src 0 (byte) 0 (signed) 1 (write) 00000B SST.H src 1 (halfword) 0 (signed) 1 (write) 00000B

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 560 of 4535 Dec 26, 2018 Table 3A.22 Instructions Causing Exceptions and Values of MEI Register Instruction REG DS U RW ITYPE SST.W src 2 (word) 0 (signed) 1 (write) 00000B LD.B (disp16) dst 0 (byte) 0 (signed) 0 (read) 00001B LD.BU (disp16) dst 0 (byte) 1 (unsigned) 0 (read) 00001B LD.H (disp16) dst 1 (halfword) 0 (signed) 0 (read) 00001B LD.HU (disp16) dst 1 (halfword) 1 (unsigned) 0 (read) 00001B LD.W (disp16) dst 2 (word) 0 (signed) 0 (read) 00001B ST.B (disp16) src 0 (byte) 0 (signed) 1 (write) 00001B ST.H (disp16) src 1 (halfword) 0 (signed) 1 (write) 00001B ST.W (disp16) src 2 (word) 0 (signed) 1 (write) 00001B LD.B (disp23) dst 0 (byte) 0 (signed) 0 (read) 00010B LD.BU (disp23) dst 0 (byte) 1 (unsigned) 0 (read) 00010B LD.H (disp23) dst 1 (halfword) 0 (signed) 0 (read) 00010B LD.HU (disp23) dst 1 (halfword) 1 (unsigned) 0 (read) 00010B LD.W (disp23) dst 2 (word) 0 (signed) 0 (read) 00010B ST.B (disp23) src 0 (byte) 0 (signed) 1 (write) 00010B ST.H (disp23) src 1 (halfword) 0 (signed) 1 (write) 00010B ST.W (disp23) src 2 (word) 0 (signed) 1 (write) 00010B LD.DW (disp23) dst 3 (double-word) 0 (signed) 0 (read) 00010B ST.DW (disp23) src 3 (double-word) 0 (signed) 1 (write) 00010B LDL.W dst 2 (word) 0 (signed) 0 (read) 00111B STC.W src 2 (word) 0 (signed) 1 (write) 00111B CAXI dst 2 (word) 0 (signed) 0 (read)/1 (write) 01000B SET1 — 0 (byte) 0 (signed) 0 (read)/1 (write) 01001B CLR1 — 0 (byte) 0 (signed) 0 (read)/1 (write) 01001B NOT1 — 0 (byte) 0 (signed) 0 (read)/1 (write) 01001B TST1 — 0 (byte) 0 (signed) 0 (read) 01001B PREPARE — 2 (word) 0 (signed) 1 (write) 01100B DISPOSE — 2 (word) 0 (signed) 0 (read) 01100B PUSHSP — 2 (word) 0 (signed) 1 (write) 01101B POPSP — 2 (word) 0 (signed) 0 (read) 01101B SWITCH — 1 (halfword) 0 (signed) 0 (read) 10000B CALLT — 1 (halfword) 1 (unsigned) 0 (read) 10001B SYSCALL — 2 (word) 0 (signed) 0 (read) 10010B Interrupt (table reference)*1 — 2 (word) 0 (signed) 0 (read) 10101B Note 1. When reading the interrupt vector by using the table reference method. NOTE dst: destination register number, src: source register number

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 561 of 4535 Dec 26, 2018 (q) RBASE — Reset Vector Base Address Register This register indicates the reset vector address when there is a reset. If the PSW.EBV bit is 0, this vector address is also used as the exception vector address. 31 9 8 1 0 RINT Value after reset *1 RBASE RBASE31 to RBASE9 0 0 0 0 0 0 0 0 Table 3A.23 RBASE Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 9 RBASE31 to RBASE9 These bits indicate the reset vector when there is a reset. When PSW.EBV = 0, this address is also used as the exception vector. For RBASE8 to RBASE0, 0 is used implicitly. R CPU1: 0000 0000 0000 0000 0000 000 B CPU2: 0000 0000 1000 0000 0000 000 B*1 8 to 1 — (Reserved for future expansion. Be sure to set to 0.) R 0

0 RINT When the RINT bit is set, the exception handler address for interrupt servicing

is reduced. See Section 7A.10.1, Direct Vector Method. This bit is valid when PSW.EBV = 0. R 0 Note 1. The value depends on the reset vector. The values set at shipment are shown in the table. When the reset vector is modified, the address will be changed. (r) EBASE — Exception Handler Vector Address Register This register indicates the exception handler vector address. This register is valid when the PSW.EBV bit is 1. 31 9 8 1 0 RINT Value after reset Undefined EBASE EBASE31 to EBASE9 0 0 0 0 0 0 0 0 Table 3A.24 EBASE Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 9 EBASE31 to EBASE9 The exception handler routine address is changed to the address resulting from adding the offset address of each exception to the base address specified for this register. For EBASE8 to EBASE0, 0 is used implicitly. R/W Undefined 8 to 1 — (Reserved for future expansion. Be sure to set to 0.) R 0 is reduced. See Section 7A.10.1, Direct Vector Method. R/W Undefined

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 562 of 4535 Dec 26, 2018 (s) INTBP — Base Address Register of the Interrupt Handler Address Table This register indicates the base address of the address table when the table reference method is selected as the interrupt handler address selection method. 31 9 8 0 Value after reset Undefined INTBP INTBP31 to INTBP9 0 0 0 0 0 0 0 0 0 Table 3A.25 INTBP Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 9 INTBP31 to INTBP9 These bits indicate the base pointer address for an interrupt when the table reference method is used. The value indicated by these bits is the first address in the table used to determine the exception handler when the interrupt specified by the table reference method (EIINT0 to EIINT511) is acknowledged. For INTBP8 to INTBP0, 0 is used implicitly. R/W Undefined 8 to 0 — (Reserved for future expansion. Be sure to set to 0.) R 0 (t) PID — Processor ID Register The PID register retains a processor identifier that is unique to the CPU. The PID register is a read-only register. 31 0 Value after reset 0500 03A8H PID PID Table 3A.26 PID Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 24 PID Architecture Identifier This identifier indicates the architecture of the processor. R 05H 23 to 8 Function Identifier This identifier indicates the functions of the processor. These bits indicate whether or not functions defined per bit are implemented (1: implemented, 0: not implemented). Bits 23 to 11: Reserved Bit 10: Double-precision floating-point operation function Bit 9: Single-precision floating-point operation function Bit 8: Memory protection function (MPU) R 0003H 7 to 0 Version Identifier This identifier indicates the version of the processor. R A8H

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 563 of 4535 Dec 26, 2018 (u) SCCFG — SYSCALL Operation Setting Register This register is used to specify operations related to the SYSCALL instruction. Be sure to set an appropriate value to this register before using the SYSCALL instruction. 31 8 7 0 Value after reset Undefined SCCFG 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIZE Table 3A.27 SCCFG Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 8 — (Reserved for future expansion. Be sure to set to 0.) R 0 7 to 0 SIZE These bits specify the maximum number of entries of a table that the SYSCALL instruction references. The maximum number of entries the SYSCALL instruction references is 1 if SIZE is 0, and 256 if SIZE is 255. By setting the maximum number of entries appropriately in accordance with the number of functions branched by the SYSCALL instruction, the memory area can be effectively used. If vectors exceeding the maximum number of entries are specified for the SYSCALL instruction, the first entry is selected. Place an error processing routine at the first entry. R/W Undefined (v) SCBP — SYSCALL Base Pointer Register The SCBP register is used to specify a table address of the SYSCALL instruction and generate a target address. Be sure to set an appropriate value to this register before using the SYSCALL instruction. Be sure to set a word address to the SCBP register. 31 0 Value after reset Undefined SCBP SCBP31 to SCBP0 Table 3A.28 SCBP Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 2 SCBP31 to SCBP2 These bits indicate the base pointer address of the SYSCALL instruction. These bits indicate the start address of the table used by the SYSCALL instruction. R/W Undefined 1, 0 SCBP1, SCBP0 These bits indicate the base pointer address of the SYSCALL instruction. These bits indicate the start address of the table used by the SYSCALL instruction. Always set these bits to 0. R 0

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 564 of 4535 Dec 26, 2018 (w) MCFG0 — Machine Configuration Register This register indicates the CPU configuration. 31 18 17 16 15 3 2 1 0 Value after reset *1 MCFG0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPID 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Table 3A.29 MCFG0 Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 18 — (Reserved for future expansion. Be sure to set to 0.) R 0 17, 16 SPID These bits indicate the system protection number. R/W *2 15 to 3 — (Reserved for future expansion. Be sure to set to 0.) R 0 2 — (Reserved for future expansion. Be sure to set to 1.) R 1 1, 0 — (Reserved for future expansion. Be sure to set to 0.) R 0 Note 1. The value after reset is 0001 0004H for CPU1 (PE1) and 0002 0004H for CPU2 (PE2). Note 2. The value after reset is 01B for CPU1 (PE1) and 10B for CPU2 (PE2). (x) MCTL — Machine Control Register This register is used to control the CPU. 31 2 1 0 M A U I C Value after reset 8000 0002H MCTL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3A.30 MCTL Register Contents Bit Position Bit Name Function R/W Value after Reset 31 — (Reserved for future expansion. Be sure to set to 1.) R 1 30 to 2 — (Reserved for future expansion. Be sure to set to 0.) R 0 1 MA This bit is used to control the misaligned access. 0: In the event of a misaligned access, an exception is always generated.*1 1: The correct operation is controlled by hardware.*2 R/W 1 0 UIC This bit is used to control the interrupt enable/disable operation in user mode. When this bit is set to 1, executing the EI/DI instruction in user mode becomes possible. R/W 0 Note 1. Excluding LD.DW, and ST.DW for word boundary allocation. Note 2. Exception still occurs in case of LD.DW or ST.DW for misaligned access except word boundary allocation.

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 565 of 4535 Dec 26, 2018 (3) Interrupt Function Registers Table 3A.31 Interrupt Function System Registers Register No. (regID, selID) Symbol Function Access Permission SR7, 1 FPIPR FPI exception interrupt priority setting register SV SR10, 2 ISPR Priority of interrupt being serviced register SV SR11, 2 PMR Interrupt priority masking register SV SR12, 2 ICSR Interrupt control status register SV SR13, 2 INTCFG Interrupt function setting register SV

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 566 of 4535 Dec 26, 2018 (a) FPIPR — FPI Exception Interrupt Priority Setting Register This register is used to set the interrupt priority of FPI exception. 31 5 4 0 Value after reset 0000 0000H FPIPR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FPIPR Table 3A.32 FPIPR Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 5 — (Reserved for future expansion. Be sure to set to 0.) R 0 4 to 0 FPIPR These bits are used to specify the interrupt priority of floating-point operation exceptions (imprecise) (FPI). Specify values from 0 to 16. Specifying 17 or greater is prohibited. FPI exceptions are handled using the specified interrupt priority. If an FPI exception occurs at the same time as an interrupt that has the same priority, the FPI exception is prioritized. NOTE: A set value of more than 16 is treated as 16. R/W 0

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 567 of 4535 Dec 26, 2018 (b) ISPR — Priority of Interrupt being Serviced Register This register retains the priority of the EIINTn interrupt being serviced by the CPU. This priority value is then used to perform priority ceiling processing when multiple interrupts occur. 31 16 15 0 Value after reset 0000 0000H ISPR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISP15 to ISP0 Table 3A.33 ISPR Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 16 — (Reserved for future expansion. Be sure to set to 0.) R 0 15 to 0 ISP15 to ISP0 These bits indicate the acknowledgment status of an EIINTn interrupt with a priority that corresponds to the relevant bit position. 0: An interrupt request for an interrupt whose priority corresponds to the relevant bit position has not been acknowledged. 1: An interrupt request for an interrupt whose priority corresponds to the relevant bit position is being serviced by the CPU core. The bit positions correspond to the following priority levels. Bit Priority

0 Priority 0 (highest)

1 Priority 1

14 Priority 14

15 Priority 15 (lowest)

When an interrupt request (EIINTn) is acknowledged, the bit corresponding to the acknowledged interrupt request is automatically set to 1. If PSW.EP is 0 when the EIRET instruction is executed, the bit with the highest priority among the ISP15 to ISP0 bits that are set to 1 (0 is the highest priority) is cleared to 0.* While a bit in this register is set to 1, same or lower priority interrupts (EIINTn) and FPI exceptions*2 are masked. Priority level judgment is therefore not performed when the system is determining whether to acknowledge an exception, meaning that exceptions will not be acknowledged. When performing software-based priority control using the PMR register, be sure to clear this register by using the INTCFG.ISPC bit. 3 0 Note 1. Interrupt acknowledgment and auto-updating of values when the EIRET instruction is executed are disabled by setting (1) to the INTCFG.ISPC bit. It is recommended to enable auto-updating of values, so in normal cases, the INTCFG.ISPC bit should be cleared to 0. Note 2. Since FPI exceptions have the same level of priority as EIINTn interrupts, they are affected by interrupts in the same way as the ISPR. The priority of FPI exceptions is set by the FPIPR register. Note 3. This is R or R/W, depending on the setting of the INTCFG.ISPC bit. It is recommended to use this register as a read-only (R) register.

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 568 of 4535 Dec 26, 2018 (c) PMR — Interrupt Priority Masking Register This register is used to mask the specified interrupt priority. 31 16 15 0 Value after reset 0000 0000H PMR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PM15 to PM0 Table 3A.34 PMR Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 16 — (Reserved for future expansion. Be sure to set to 0.) R 0 15 to 0 PM15 to PM0 These bits mask an interrupt request with a priority level that corresponds to the relevant bit position. 0: Servicing of an interrupt with a priority that corresponds to the relevant bit position is enabled. 1: Servicing of an interrupt with a priority that corresponds to the relevant bit position is disabled. The bit positions correspond to the following priority levels: Bit Priority

15 Priority 15 and priority 16 (lowest)

While a bit in this register is set to 1, interrupts (EIINTn) and FPI exceptions*1 with the priority corresponding to that bit are masked. Priority level judgment is therefore not performed when the system is determining whether to acknowledge an exception, meaning that exceptions will not be acknowledged*2. R/W 0 Note 1. Since FPI exceptions are specified as the same level of priority as that of interrupts (EIINTn), it is affected by the PMR like interrupts. The priority of FPI exceptions is set by the FPIPR register. Note 2. Specify the masks by setting the bits to 1 in order from the lowest-priority bit. For example, FF00H can be set, but F0F0H or 00FFH cannot. (d) ICSR — Interrupt Control Status Register This register indicates the interrupt control status in the CPU. 31 2 1 0 PMFP PMEI Value after reset 0000 0000H ICSR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3A.35 ICSR Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 2 — (Reserved for future expansion. Be sure to set to 0.) R 0

1 PMFP This bit indicates that an FPI exception with the priority level masked by the

PMR register exists. R 0

0 PMEI This bit indicates that an interrupt (EIINTn) with the priority level masked by

the PMR register exists. R 0

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 569 of 4535 Dec 26, 2018 (e) INTCFG — Interrupt Function Setting Register This register is used to specify settings related to the CPU’s internal interrupt function. 31 1 0 ISPC Value after reset 0000 0000H INTCFG 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3A.36 INTCFG Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 1 — (Reserved for future expansion. Be sure to set to 0.) R 0 0 ISPC This bit specifies how the ISPR register is updated. 0: The ISPR register is automatically updated. Updates triggered by the program (via execution of LDSR instruction) are ignored. 1: The ISPR register is not automatically updated. Updates triggered by the program (via execution of LDSR instruction) are performed. If this bit is cleared to 0, the bits of the ISPR register are automatically set to 1 when an interrupt (EIINTn) is acknowledged, and cleared to 0 when the EIRET instruction is executed. In this case, updating by the program (via execution of an LDSR instruction) is ignored. If this bit is set to 1, the bits of the ISPR register are not updated by the acknowledgement of an interrupt (EIINTn) or by execution of the EIRET instruction. In this case, the bits can be updated by an LDSR instruction executed by the program. In normal cases, the ISPC bit should be cleared to 0. When performing software-based control of interrupt priorities, however, set this bit (1) and perform priority control by using the PMR register. R/W 0

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 570 of 4535 Dec 26, 2018 (4) FPU Function Registers The FPU uses the CPU general-purpose registers (r0 to r31). There are no register files used only for floating-point operations. The RH850/F1KH supports single-precision floating-point instruction and thirty-two 32-bit registers can be specified. These registers correspond to general-purpose registers r0 to r31. The FPU can use the following system registers to control floating-point operation Table 3A.37 FPU System Registers Register No. (regID, selID) Symbol Function Access Permission SR6, 0 FPSR Floating-point operation setting/status register CU and SV SR7, 0 FPEPC Floating-point exception program counter register CU and SV SR8, 0 FPST Floating-point operation status register CU SR9, 0 FPCC Floating-point operation comparison result register CU SR10, 0 FPCFG Floating-point operation configuration register CU SR11, 0 FPEC Floating-point exception control register CU and SV

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 571 of 4535 Dec 26, 2018 (a) FPSR — Floating-point Operation Setting/Status Register This register indicates the execution status of floating-point operations and any exceptions that occur. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0 F N I F P E M F S Value after reset See below FPSR 0 RM 0 E V Z O U I V Z O U I V Z O U I *1 *2 *3 Note 1. Cause bits (XC) Note 2. Enable bits(XE) Note 3. Preservation bits (XP) Table 3A.38 FPSR Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 24 CC[7:0] These are the CC (condition) bits. They store the results of floating-point comparison instructions. The CC7 to CC0 bits are not affected by any instructions except the comparison instruction and LDSR instruction. 0: Comparison result is false 1: Comparison result is true R/W Undefined 23 FN This bit enables flush-to-nearest mode. When the FN bit is set to 1, if the rounding mode is RN and the operation result is a subnormal number, the number is flushed to the nearest number. R/W 0

22 IF This bit accumulates and indicates information about the flushing of input

operands. R/W 0 21 PEM This bit specifies whether to handle an exception as a precise exception. If the PEM bit is 1, exceptions that are caused by the execution of a floating-point operation instruction are handled as precise exceptions. R/W 0 20 — (Reserved for future expansion. Be sure to set to 0.) R 0 19, 18 RM These are the rounding mode control bits. The RM bits define the rounding mode that the FPU uses for all floating-point instructions. RM Bits Mnemonic Description 19 18 0 0 RN Rounds the result to the nearest representable value. If the value is exactly in-between the two nearest representable values, the result is rounded toward the value whose least significant bit is 0. 0 1 RZ Rounds the result toward 0. The result is the nearest to the value that does not exceed the absolute value of the result with infinite accuracy. 1 0 RP Rounds the result toward +∞. The result is nearest to a value greater than the accurate result with infinite accuracy. 1 1 RM Rounds the result toward −∞. The result is nearest to a value less than the accurate result with infinite accuracy. R/W 00

17 FS This bit enables values that cannot be normalized (subnormal numbers) to be

flushed. If the FS bit is set, input operands and operation results that are subnormal numbers are flushed without causing an unimplemented operation exception (E). An input operand that is a subnormal number is flushed to 0 with the same sign. Operation results that are subnormal numbers either become 0 or the minimum normalized number, depending on the rounding mode. Operation Result that is a Subnormal Number Rounding Mode and Value after Flushing RN*1 RZ RP RM Positive +0 +0 +2Emin +0 Negative −0 −0 −0 −2Emin Note 1. If the rounding mode is RN and the FPSR.FN bit is set to 1, flushing will occur in the direction of higher accuracy. R/W 1 16 — (Reserved for future expansion. Be sure to set to 0.) R 0 15 to 10 XC (E, V, Z, O, U, I) These are the cause bits. R/W Undefined

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 572 of 4535 Dec 26, 2018 Table 3A.38 FPSR Register Contents Bit Position Bit Name Function R/W Value after Reset 9 to 5 XE (V, Z, O, U, I) These are the enable bits. R/W 0 4 to 0 XP (V, Z, O, U, I) These are the preservation bits. R/W Undefined (b) FPEPC — Floating-point Exception Program Counter Register When an exception that is enabled by an enable bit occurs, the program counter (PC) of the instruction that caused the exception is stored. 31 0 Value after reset Undefined FPEPC FPEPC31 to FPEPC0 Table 3A.39 FPEPC Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 1 FPEPC31 to FPEPC1 These bits store the program counter (PC) of the floating-point instruction that caused the exception when a floating-point operation exception that is enabled by an enable bit occurs. R/W Undefined

0 FPEPC0 This bit stores the program counter (PC) of the floating-point instruction that

caused the exception when a floating-point operation exception that is enabled by an enable bit occurs. Always set this bit to 0. R 0 (c) FPST — Floating-point Operation Status Register This register reflects the contents of the FPSR register bits related to the operation status. 31 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I F Value after reset Undefined FPST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E V Z O U I 0 0 V Z O U I *1 *2 Note 1. Cause bits (XC) Note 2. Preservation bits (XP) Table 3A.40 FPST Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 14 — (Reserved for future expansion. Be sure to set to 0.) R 0 13 to 8 XC (E, V, Z, O, U, I) These are cause bits. Values written to these bits are reflected in FPSR.XC bits. R/W Undefined 7, 6 — (Reserved for future expansion. Be sure to set to 0.) R 0

5 IF This bit accumulates and indicates information about the flushing of input

operands. R/W 0 4 to 0 XP (V, Z, O, U, I) These are preservation bits. Values written to these bits are reflected in FPSR.XP bits. R/W Undefined

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 573 of 4535 Dec 26, 2018 (d) FPCC — Floating-point Operation Comparison Result Register This register reflects the contents of the FPSR.CC[7:0] bits. 31 8 7 6 5 4 3 2 1 0 CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0 Value after reset Undefined FPCC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3A.41 FPCC Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 8 — (Reserved for future expansion. Be sure to set to 0.) R 0 7 to 0 CC[7:0] These are CC (condition) bits. They store the result of a floating-point comparison instruction. The CC[7:0] bits are not affected by any instructions except the comparison instruction and LDSR instruction. Values written to these bits are reflected in the CC[7:0] bits of FPSR. 0: Comparison result is false 1: Comparison result is true R/W Undefined (e) FPCFG — Floating-point Operation Configuration Register This register reflects the contents of the FPSR register bits related to the operation settings. 31 10 9 8 7 5 4 3 2 1 0 Value after reset 0000 0000H FPCFG 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RM 0 0 0 V Z O U I Note 1. Enable bits (XE) Table 3A.42 FPCFG Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 10 — (Reserved for future expansion. Be sure to set to 0.) R 0 9, 8 RM These are rounding mode control bits. The RM bits define the rounding mode that the FPU uses for all floating-point instructions. Values written to these bits are reflected in RM bits of FPSR. RM Bits Mnemonic Description 9 8 0 0 RN Rounds the result to the nearest representable value. If the value is exactly in-between the two nearest representable values, the result is rounded toward the value whose least significant bit is 0. 0 1 RZ Rounds the result toward 0. The result is the nearest to the value that does not exceed the absolute value of the result with infinite accuracy. 1 0 RP Rounds the result toward +∞. The result is nearest to a value greater than the accurate result with infinite accuracy. 1 1 RM Rounds the result toward −∞. The result is nearest to a value less than the accurate result with infinite accuracy. R/W 0 7 to 5 — (Reserved for future expansion. Be sure to set to 0.) R 0 4 to 0 XE (V, Z, O, U, I) These are the enable bits. R/W 0

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 574 of 4535 Dec 26, 2018 (f) FPEC — Floating-point Exception Control Register This register controls the floating-point operation exception. 31 1 0 FPIVD Value after reset 0000 0000H FPEC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3A.43 FPEC Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 1 — (Reserved for future expansion. Be sure to set to 0.) R 0 0 FPIVD*1 This bit indicates the status of reporting the FPI exception. If this bit is set to 1, the FPI exception is reported to the CPU but is not acknowledged. It is automatically cleared to 0 when the CPU acknowledges the FPI exception. While this bit is set to 1, all the floating-point instructions are invalidated. Report of the FPI exception can be canceled by clearing (0) this bit by the LDSR instruction while it is set to 1. When report of the FPI exception is canceled, the CPU does not acknowledge the FPI exception. 0: FPI exception is not reported. 1: FPI exception is reported. R/W 0 Note 1. The FPIVD bit can only be cleared to 0 by the write operation of the LDSR instruction. It cannot be set to 1.

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 575 of 4535 Dec 26, 2018 (5) MPU Function Registers Table 3A.44 MPU Function System Registers Register No. (regID, selID) Symbol Function Access Permission SR0, 5 MPM Memory protection operation mode setting SV SR1, 5 MPRC MPU region control SV SR4, 5 MPBRGN MPU base region number SV SR5, 5 MPTRGN MPU end region number SV SR8, 5 MCA Memory protection setting check address SV SR9, 5 MCS Memory protection setting check size SV SR10, 5 MCC Memory protection setting check command SV SR11, 5 MCR Memory protection setting check result SV SR0, 6 MPLA0 Protection area lower limit address SV SR1, 6 MPUA0 Protection area upper limit address SV SR2, 6 MPAT0 Protection area attribute SV SR4, 6 MPLA1 Protection area lower limit address SV SR5, 6 MPUA1 Protection area upper limit address SV SR6, 6 MPAT1 Protection area attribute SV SR8, 6 MPLA2 Protection area lower limit address SV SR9, 6 MPUA2 Protection area upper limit address SV SR10, 6 MPAT2 Protection area attribute SV SR12, 6 MPLA3 Protection area lower limit address SV SR13, 6 MPUA3 Protection area upper limit address SV SR14, 6 MPAT3 Protection area attribute SV SR16, 6 MPLA4 Protection area lower limit address SV SR17, 6 MPUA4 Protection area upper limit address SV SR18, 6 MPAT4 Protection area attribute SV SR20, 6 MPLA5 Protection area lower limit address SV SR21, 6 MPUA5 Protection area upper limit address SV SR22, 6 MPAT5 Protection area attribute SV SR24, 6 MPLA6 Protection area lower limit address SV SR25, 6 MPUA6 Protection area upper limit address SV SR26, 6 MPAT6 Protection area attribute SV SR28, 6 MPLA7 Protection area lower limit address SV SR29, 6 MPUA7 Protection area upper limit address SV SR30, 6 MPAT7 Protection area attribute SV SR0, 7 MPLA8 Protection area lower limit address SV SR1, 7 MPUA8 Protection area upper limit address SV SR2, 7 MPAT8 Protection area attribute SV SR4, 7 MPLA9 Protection area lower limit address SV SR5, 7 MPUA9 Protection area upper limit address SV SR6, 7 MPAT9 Protection area attribute SV SR8, 7 MPLA10 Protection area lower limit address SV SR9, 7 MPUA10 Protection area upper limit address SV SR10, 7 MPAT10 Protection area attribute SV SR12, 7 MPLA11 Protection area lower limit address SV SR13, 7 MPUA11 Protection area upper limit address SV

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 576 of 4535 Dec 26, 2018 Table 3A.44 MPU Function System Registers Register No. (regID, selID) Symbol Function Access Permission SR14, 7 MPAT11 Protection area attribute SV SR16, 7 MPLA12 Protection area lower limit address SV SR17, 7 MPUA12 Protection area upper limit address SV SR18, 7 MPAT12 Protection area attribute SV SR20, 7 MPLA13 Protection area lower limit address SV SR21, 7 MPUA13 Protection area upper limit address SV SR22, 7 MPAT13 Protection area attribute SV SR24, 7 MPLA14 Protection area lower limit address SV SR25, 7 MPUA14 Protection area upper limit address SV SR26, 7 MPAT14 Protection area attribute SV SR28, 7 MPLA15 Protection area lower limit address SV SR29, 7 MPUA15 Protection area upper limit address SV SR30, 7 MPAT15 Protection area attribute SV

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 577 of 4535 Dec 26, 2018 (a) MPM — Memory Protection Operation Mode Register The memory protection mode register is used to define the basic operating state of the memory protection function. 31 2 1 0 S V P M P E Value after reset 0000 0000H MPM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3A.45 MPM Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 2 — (Reserved for future expansion. Be sure to set to 0.) R 0 1 SVP In SV mode (when PSW.UM = 0), this bit is used to specify whether to restrict access according to the SX, SW, and SR bits of the MPAT register for each protection area.*1 0: As usual, implicitly enable all access in SV mode. 1: Restrict access according to the SX, SW, and SR bits even in SV mode.*2 R/W 0 0 MPE This bit is used to specify whether to enable or disable the MPU function. 0: Disable 1: Enable R/W 0 Note 1. If the SVP bit is set to 1, access will be restricted in accordance with the setting for each protection area, even in SV mode. Therefore, specify the protection area beforehand so that the access from the program which set the SVP bit is not restricted. Note 2. If access is restricted in SV mode, execution of MDP exceptions or the MIP exception handling itself might not be possible depending on the settings. Be careful to specify settings so that access by the exception handler and to the memory area necessary for exception handling is permitted. (b) MPRC — MPU Region Control Register 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E E E E E E E E E E E E E E E E Value after reset 0000 0000H MPRC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3A.46 MPRC Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 16 — (Reserved for future expansion. Be sure to set to 0.) R 0 15 to 0 E15 to E0 These are the enable bits for each protection area. Bit En is a copy of bit MPATn.E (where n = 15 to 0). R/W 0

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 578 of 4535 Dec 26, 2018 (c) MPBRGN — MPU Base Region Register This register indicates the minimum usable MPU area number. 31 5 4 0 Value after reset 0000 0000H MPBRGN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPBRGN Table 3A.47 MPBRGN Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 5 — (Reserved for future expansion. Be sure to set to 0.) R 0 4 to 0 MPBRGN These bits indicate the smallest number of an MPU area. These bits always indicate 0. R 0 (d) MPTRGN — MPU End Region Register This register indicates the maximum usable MPU area number + 1. 31 5 4 0 Value after reset 0000 0010H MPTRGN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPTRGN Table 3A.48 MPTRGN Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 5 — (Reserved for future expansion. Be sure to set to 0.) R 0 4 to 0 MPTRGN These bits indicate the largest number of an MPU area + 1. These bits indicate the maximum number of MPU areas incorporated into the hardware. R 10000B (e) MCA — Memory Protection Setting Check Address Register This register is used to specify the base address of the area for which a memory protection setting check is to be performed. 31 0 Value after reset Undefined MCA MCA31 to MCA0 Table 3A.49 MCA Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 0 MCA31 to MCA0 These bits are used to specify the start address of the memory area that is subject to a memory protection setting check in bytes. R/W Undefined

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 579 of 4535 Dec 26, 2018 (f) MCS — Memory Protection Setting Check Size Register This register is used to specify the size of the area for which a memory protection setting check is to be performed. 31 0 Value after reset Undefined MCS MCS31 to MCS0 Table 3A.50 MCS Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 0 MCS31 to MCS0 These bits are used to specify the size of the memory area that is subject to a memory protection setting check and the size of the target area in bytes. Because the specified size is assumed to represent an unsigned integer, it is not possible to check an area in the direction in which the address value decreases relative to the MCA register value. Do not specify 0000 0000 H for the MCS register. R/W Undefined (g) MCC — Memory Protection Setting Check Command Register This register is used to specify the base address of the area where memory protection settings are checked. 31 0 Value after reset 0000 0000H MCC MCC31 to MCC0 Table 3A.51 MCC Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 0 MCC31 to MCC0 When any value is written to the MCC register, a memory protection setting check starts. By setting up the MCA/MCS register and then writing to the MCC register, results are stored in MCR. Because the check is started by any written value, a check can be started by using r0 as the source register without using any unnecessary registers. Note that, for the check, the results are applied according to each area setting regardless of the state of the PSW.UM bit. When the MCC register is read, value 0000 0000 H is always returned. R/W 0

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 580 of 4535 Dec 26, 2018 (h) MCR — Memory Protection Setting Check Result Register This register is used to store the results of a memory protection setting check. Be sure to clear bits 31 to 9, 7 and 6. 31 9 8 7 6 5 4 3 2 1 0 O V S X E S W E S R E U X E U W E U R E Value after reset Undefined MCR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3A.52 MCR Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 9 — (Reserved for future expansion. Be sure to set to 0.) R 0

8 OV If the specified area includes 0000 0000H or 7FFF FFFFH, 1 is stored in this

bit. In other cases, 0 is stored in this bit. R/W Undefined 7, 6 — (Reserved for future expansion. Be sure to set to 0.) R 0

5 SXE If the specified area is contained within one of the protection areas and

execution is permitted for that area in supervisor mode, 1 is stored in this bit. In other cases, 0 is stored in this bit. R/W Undefined

4 SWE If the specified area is contained within one of the protection areas and writing

to that area is permitted in supervisor mode, 1 is stored in this bit. In other cases, 0 is stored in this bit. R/W Undefined

3 SRE If the specified area is contained within one of the protection areas and

reading from that area is permitted in supervisor mode, 1 is stored in this bit. In other cases, 0 is stored in this bit. R/W Undefined

2 UXE If the specified area is contained within one of the protection areas and

execution is permitted for that area in user mode, 1 is stored in this bit. In other cases, 0 is stored in this bit. R/W Undefined

1 UWE If the specified area is contained within one of the protection areas and writing

to that area is permitted in user mode, 1 is stored in this bit. In other cases, 0 is stored in this bit. R/W Undefined

0 URE If the specified area is contained within one of the protection areas and

reading from that area is permitted in user mode, 1 is stored in this bit. In other cases, 0 is stored in this bit. R/W Undefined (i) MPLAn — Protection Area Lower Limit Address Register These registers indicate the lower limit address of area n (where n = 0 to 15). 31 2 1 0 Value after reset Undefined MPLAn MPLAn 0 0 Table 3A.53 MPLAn Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 2 MPLA31 to MPLA2 These bits indicate the lower limit address of area n. For MPLA1 and MPLA0, 0 is used implicitly. R/W Undefined 1, 0 — (Reserved for future expansion. Be sure to set to 0.) R 0

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 581 of 4535 Dec 26, 2018 (j) MPUAn — Protection Area Upper Limit Address Register These registers indicate the upper limit address of area n (where n = 0 to 15). 31 2 1 0 Value after reset Undefined MPUAn MPUAn 0 0 Table 3A.54 MPUAn Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 2 MPUA31 to MPUA2 These bits indicate the upper limit address of area n. For MPUAn.MPUA1 and MPUA0, 1 is used implicitly. R/W Undefined 1, 0 — (Reserved for future expansion. Be sure to set to 0.) R 0

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 582 of 4535 Dec 26, 2018 (k) MPATn — Protection Area Attribute Register These registers indicate the attributes of area n (where n = 0 to 15). 31 26 25 16 15 8 7 6 5 4 3 2 1 0 S X S W S R U X U W U R Value after reset Undefined MPATn 0 0 0 0 0 0 ASID 0 0 0 0 0 0 0 0 E G Table 3A.55 MPATn Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 26 — (Reserved for future expansion. Be sure to set to 0.) R 0 25 to 16 ASID These bits indicate the ASID value to be used as the area match condition. R/W Undefined 15 to 8 — (Reserved for future expansion. Be sure to set to 0.) R 0 7 E This bit indicates whether area n is enabled or disabled. 0: Area n is disabled. 1: Area n is enabled. R/W 0 6 G 0: Areas match only if ASIDs are equal. 1: Areas match even if ASIDs are not equal. If this bit is 0, MPATn.ASID = ASID.ASID is used as the area match condition. If this bit is 1, areas may match even if the values of MPATn.ASID and ASID.ASID are not equal. R/W Undefined 5 SX This bit indicates the execution privilege for the supervisor mode.*1 0: Execution is disabled. 1: Execution is enabled. R/W Undefined 4 SW This bit indicates whether writing is enabled in the supervisor mode.*1 0: Writing is disabled. 1: Writing is enabled. R/W Undefined 3 SR This bit indicates whether writing is enabled in the supervisor mode.*1 0: Reading is disabled. 1: Reading is enabled. R/W Undefined 2 UX This bit indicates the execution privilege for the user mode. 0: Execution is disabled. 1: Execution is enabled. R/W Undefined 1 UW This bit indicates whether writing is enabled in the user mode. 0: Writing is disabled. 1: Writing is enabled. R/W Undefined 0 UR This bit indicates whether writing is enabled in the user mode. 0: Reading is disabled. 1: Reading is enabled. R/W Undefined Note 1. If access is restricted in SV mode, execution of MDP exceptions or the MIP exception handling itself might not be possible depending on the settings. Be careful to specify settings so that access by the exception handler and to the memory area necessary for exception handling is permitted.

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 583 of 4535 Dec 26, 2018 (6) Cache Operation Function Registers The RH850/F1KH does not include a cache operation function, so all the following registers return a value of 0 when read, and writing to these registers is ignored. Table 3A.56 Cache Operation Function Registers Register No. (regID, selID) Symbol Function Access Permission SR12, 4 BWERRL Not implemented. A value of 0 is returned when read and writing is ignored. SV SR13, 4 BWERRH SV SR14, 4 BRERRL SV SR15, 4 BRERRH SV SR16, 4 ICTAGL SV SR17, 4 ICTAGH SV SR18, 4 ICDATL SV SR19, 4 ICDATH SV SR20, 4 DCTAGL SV SR21, 4 DCTAGH SV SR22, 4 DCDATL SV SR23, 4 DCDATH SV SR24, 4 ICCTRL SV SR25, 4 DCCTRL SV SR26, 4 ICCFG SV SR27, 4 DCCFG SV SR28, 4 ICERR SV SR29, 4 DCERR SV 3A.2.1.3 Instruction See “Instruction” in Software Manual. A snooze instruction halts operation of the CPU1/2 core for 32 clocks.

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 585 of 4535 Dec 26, 2018 3A.2.2.3 Registers for Buffer Control (1) List of Buffer Control Registers Table 3A.57 Buffer Control Register (Base Address: FFC5 B000H) Module Name Address Offset Size (Byte) Register Name Abbreviation Right R/W Operable Bit Value after Reset 1 8 16 32 FBUF_CTRL +000H 4 Flash buffer clear control register FBUFCCTL — R/W —    0000 0000H (2) Register Sets Access: FBUFCCTL register can be read or written in 32-bit units. FBUFCCTLL register can be read or written in 16-bit units. FBUFCCTLLL register can be read or written in 8-bit units. Address: FBUFCCTL: FFC5 B000H FBUFCCTLL: FFC5 B000H FBUFCCTLLL: FFC5 B000H 31 1 0 FBUFCLR Value after reset 0000 0000H FBUFCCTL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3A.58 FBUFCCTL Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 1 Reserved When read, the value after reset is returned. When writing, write the value after reset. R 0 0 FBUFCLR Buffer clear bits. To clear buffers, write 1 to this bit and then write 0. 0: Buffers are valid 1: Buffers are invalid (cleared) R/W 0 Please do following procedures when you want to clear the buffers. Step 1: Write 0 to FBUFCCTL.FBUFCLR Step 2: Write 1 to FBUFCCTL.FBUFCLR Step 3: Write 0 to FBUFCCTL.FBUFCLR Step 4: Read the FBUFCCTL register (dummy read) Step 5: Execute the SYNCP instruction Step 6: Execute the SYNCI instruction If you do not do Step 3 after Step 2, the buffers are kept invalid during FBUFCCTL.FBUFCLR = 1.

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 586 of 4535 Dec 26, 2018 3A.2.3 Inter-Processor Interrupts Four registers (IPIR_CHn) are provided for communicating four channels of interrupts between the CPUs (PEs). IPIR_CH0 to IPIR_CH3 are assigned to CH0 to CH3 of user interrupts (EIINT). An interrupt for specific PEs (including own PE) can be requested by manipulating the bits corresponding to each PE. 3A.2.3.1 Inter-Processor Interrupt Control Registers These registers are located in the CPU Peripheral. Table 3A.59 List of Registers Module Name Address Register Name Symbol R/W Access Size Value after Reset 1 8 16 32 IPIRSS FFFE EC80H Inter-PE interrupt register 0 IPIR_CH0 R/W —    0000 0000H FFFE EC84H Inter-PE interrupt register 1 IPIR_CH1 R/W —    0000 0000H FFFE EC88H Inter-PE interrupt register 2 IPIR_CH2 R/W —    0000 0000H FFFE EC8CH Inter-PE interrupt register 3 IPIR_CH3 R/W —    0000 0000H

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 587 of 4535 Dec 26, 2018 (1) IPIR_CHn — Inter-PE Interrupt Register n (n = 0 to 3) Access: IPIR_CHn can be read or written in 32-bit units. IPIR_CHnL can be read or written in 16-bit units. IPIR_CHnLL can be read or written in 8-bit units. Address: IPIR_CHn: FFFE EC80H + n × 4H IPIR_CHnL: FFFE EC80H + n × 4H IPIR_CHnLL: FFFE EC80H + n × 4H Value after reset: 0000 0000H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R R R R R R R R R R R R R R R R Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R R R R R R R R R R R R R R R/W R/W Table 3A.60 IPIR_CHn Registers Contents Bit Position Bit Name Function 31 to 2 Reserved When read, the value after reset is returned. When writing, write the value after reset.

1 PE2 Inter-PE Interrupt Request to PE2

Writing 1 to this bit enables an interrupt request to PE2. This bit is automatically cleared to 0 when the interrupt request has been notified. 0: Inter-PE interrupt request output is not specified or an interrupt request is not being output. 1: Interrupt request output is specified or an interrupt request is being output.

0 PE1 Inter-PE Interrupt Request to PE1

Writing 1 to this bit enables an interrupt request to PE1. This bit is automatically cleared to 0 when the interrupt request has been notified. 0: Inter-PE interrupt request output is not specified or an interrupt request is not being output. 1: Interrupt request output is specified or an interrupt request is being output.

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 588 of 4535 Dec 26, 2018 3A.2.4 Reliability Functions 3A.2.4.1 PE Guard Function (PEG) (1) Overview of the PEG Function The PEG is a constituent of the slave guard system to prevent unauthorized access to the resources in the CPU (PE) from an external master. This function protects access to the local RAM in the PE. In the initial state after a reset, access by masters other than own PE is disabled. Setting the registers listed in (3) List of PEG Protection Setting Registers enables access by masters other than own PE. (1) Detecting PE guard violation If an external master makes an unauthorized access to the resource area in a PE for which PE guard is set, the access is detected as a PE guard violation. (2) Blocking unauthorized access When a PE guard violation is detected, unauthorized access to the internal resources of the PE are blocked to prevent unauthorized modification of the contents of PE resources. (3) Notifying occurrence of violation An error response to an unauthorized access is sent to the request source of external master. When DMA Controller makes an unauthorized access, meanwhile, a DMA transfer error is detected. A PE guard violation is notified as INTGUARD interrupt request which is a source of FEINT. (2) Protection Made by SPID

• Setting PEG Protection − Up to four areas can be set depending on the local RAM address of the own PE. − The area range is specified by the base address and the mask bit (4 kbytes to 4 Gbytes). − “Read enable” and “write enable” can be set for each area. − “Enable” or “disable” can be selected based on the system protection identifier (SPID) for each area.
• Procedure for permitting access by using the system protection identifier (SPID) 1. Is the area subject to access is the local RAM area? If so, go to step 2. 2. Is the area subject to access is within the range of valid areas 0, 1, 2, or 3? If so, go to step 3. Otherwise, return an error response. 3. Are all the conditions below for the relevant area satisfied? If so, permit access. − The system protection identifier (SPID) is enabled. − Required operations (read/write) are enabled. Otherwise, return an error response.

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 589 of 4535 Dec 26, 2018 (3) List of PEG Protection Setting Registers Specify the necessary settings in the registers below to protect PE resources from unauthorized access by an external master.

• Whether to permit access to the local RAM in the PE can be specified. Table 3A.61 PEG Registers (Base Address: FFFE E600H) Module Name Address Offset Size (Byte) Register Name Abbreviation Right R/W Operable Bit Value after Reset 1 8 16 32 PEG +00CH 4 PEG SPID control register PEGSP — R/W —    0000 0000H +080H 4 PEG area 0 mask setting register PEGG0MK — R/W —    0000 0000H +084H 4 PEG area 0 base setting register PEGG0BA — R/W —    0000 0000H +090H 4 PEG area 1 mask setting register PEGG1MK — R/W —    0000 0000H +094H 4 PEG area 1 base setting register PEGG1BA — R/W —    0000 0000H +0A0H 4 PEG area 2 mask setting register PEGG2MK — R/W —    0000 0000H +0A4H 4 PEG area 2 base setting register PEGG2BA — R/W —    0000 0000H +0B0H 4 PEG area 3 mask setting register PEGG3MK — R/W —    0000 0000H +0B4H 4 PEG area 3 base setting register PEGG3BA — R/W —    0000 0000H

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 590 of 4535 Dec 26, 2018 (4) Register Set (a) PEGSP — PEG SPID Control Register Access: PEGSP register can be read or written in 32-bit units. PEGSPL register can be read or written in 16-bit units. PEGSPLL register can be read or written in 8-bit units. Address: PEGSP: FFFE E60CH PEGSPL: FFFE E60CH PEGSPLL: FFFE E60CH Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R R R R R R R R R R R R R R R R Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R R R R R R R R R R R R R R R R/W Table 3A.62 PEGSP Register Contents Bit Position Bit Name Function 31 to 1 Reserved When read, the value after reset is returned. When writing, write the value after reset. 0 SPEN Access permission to external master with specified SPID. 0: Not permit. 1: Permit.

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 591 of 4535 Dec 26, 2018 (b) PEGGnMK — PEG Area n Mask Setting Register (n = 0 to 3) The PEGGnMK register defines which bits of PEGGnBA.GnBASE are compared with the access address. If bit PEGGnMK.GnMASK[m] is cleared, bit PEGGnBA.GnBASE[m] is compared with bit m of the access address. Access: PEGGnMK register can be read or written in 32-bit units. PEGGnMKL, PEGGnMKH registers can be read or written in 16-bit units. PEGGnMKLH, PEGGnMKHL, PEGGnMKHH registers can be read or written in 8-bit units. Address: PEGGnMK: FFFE E680H + (10H × n) PEGGnMKL: FFFE E680H + (10H × n), PEGGnMKH: FFFE E682H + (10H × n) PEGGnMKLH: FFFE E681H + (10H × n), PEGGnMKHL: FFFE E682H + (10H × n), PEGGnMKHH: FFFE E683H + (10H × n) Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GnMASK Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R R R R R R R R R R R R Table 3A.63 PEGGnMK Register Contents Bit Position Bit Name Function 31 to 12 GnMASK 0: Target bits are compared when determining the PE guard area. 1: Target bits are not compared when determining the PE guard area. 11 to 0 Reserved When read, the value after reset is returned. When writing, write the value after reset. NOTE When you write to the PEGGnMK register, the corresponding GnEN bit in the PEGGnBA register is cleared automatically.

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 592 of 4535 Dec 26, 2018 (c) PEGGnBA — PEG Area n Base Setting Register (n = 0 to 3) In combination with the PEGGnMK register, this register specifies a range or ranges within PE guard protection area n. Setting the GnEN bit to 1 validates the access enable conditions specified by this register and the PEGGnMK register. Access: PEGGnBA register can be read or written in 32-bit units. PEGGnBAL, PEGGnBAH registers can be read or written in 16-bit units. PEGGnBALL, PEGGnBALH, PEGGnBAHL, PEGGnBAHH registers can be read or written in 8-bit units. Address: PEGGnBA: FFFE E684H + (10H × n) PEGGnBAL: FFFE E684H + (10H × n), PEGGnBAH: FFFE E686H + (10H × n) PEGGnBALL FFFE E684H + (10H × n), PEGGnBALH FFFE E685H + (10H × n), PEGGnBAHL: FFFE E686H + (10H × n), PEGGnBAHH: FFFE E687H + (10H × n) Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GnBASE Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GnBASE — — — — GnSP3 GnSP2 GnSP1 GnSP0 — GnWR GnRD GnEN Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R R R R R/W R/W R/W R/W R R/W R/W R/W Table 3A.64 PEGGnBA Register Contents Bit Position Bit Name Function 31 to 12 GnBASE Base address that specifies the range of PE guard protection area n. 11 to 8 Reserved When read, the value after reset is returned. When writing, write the value after reset. 7 GnSP3 Access permission setting from SPID = 3 external master to PE guard protection area n. 0: Not permit. 1: Permit.

6 GnSP2 Access permission setting from SPID = 2 (CPU2*1) external master to PE guard protection

area n. 0: Not permit. 1: Permit.

5 GnSP1 Access permission setting from SPID = 1 (CPU1*1) external master to PE guard protection

area n. 0: Not permit. 1: Permit.

4 GnSP0 Access permission setting from SPID = 0 (peripheral device connected to H-BUS) external

master to PE guard protection area n. 0: Not permit. 1: Permit. 3 Reserved When read, the value after reset is returned. When writing, write the value after reset. 2 GnWR Write access permission to PE guard protection area n. 0: Write access is disabled. 1: Write access is enabled.

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 593 of 4535 Dec 26, 2018 Table 3A.64 PEGGnBA Register Contents Bit Position Bit Name Function 1 GnRD Read access permission to PE guard protection area n. 0: Read access is disabled. 1: Read access is enabled.

0 GnEN Enables or Disables the setting for the access enable conditions to PE guard protection area

0: Settings for access enable conditions are disabled. 1: Settings for access enable conditions are enabled. Note 1. Setting value of MCFG0.SPID NOTE When you write to the PEGGnMK register, the corresponding GnEN bit in the PEGGnBA register is cleared automatically.

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 594 of 4535 Dec 26, 2018 3A.2.4.2 PE’s Internal Peripheral Device Protection Function (IPG) (1) Overview of the IPG Function The IPG is a function to prevent unauthorized accesses to peripheral devices from the CPU core equipped with the IPG. The IPG achieves the following functions. The IPG covers accesses to the SEG, the PEG, the IPIR, the MEV, the INTC1 and P-Bus. (a) Detecting Violation of Peripheral Device Protection If the CPU makes an unauthorized access to an area (peripheral device) for which peripheral device protection is set, the access is detected as “violation of peripheral device protection”. (b) Storing Unauthorized Access Information When a violation of peripheral device protection is detected, the unauthorized-access information is stored in the IPG’s internal register. (c) Blocking Unauthorized Accesses When a violation of peripheral device protection is detected, unauthorized accesses to peripheral devices are blocked to prevent contents of peripheral devices from being modified illegally. (d) Notifying Violation When a violation of peripheral device protection is detected, a request for generating an exception is made to ask the CPU to stop the processing. NOTE Even if a request for generating an exception is immediately sent to the CPU in step (d) Notifying Violation above, a subsequent access issued (before receiving a request from the IPG) by the CPU that does not know an occurrence of violation may illegally modify contents of peripheral devices. (Accesses after a violation has occurred result in unauthorized accesses.) (2) IPG Function

• This function invalidates accesses according to their attributes (including address, transfer type, and access right).
• After an access right violation is detected until the error flag (described later) is cleared by writing by the software, subsequent accesses are invalidated. However, invalidation is applied only to accesses from the CPU and is not applied to accesses from outside the CPU core. Invalidation is performed independently of addresses.
• When a request for accessing different peripheral devices simultaneously is made due to misalignment or double- word access, the access is executed when all such accesses are enabled. (3) IPG Protection Setting Registers for Illegal Users To protect peripheral devices from unauthorized accesses by programs in user mode, necessary settings are required for the registers listed below.
• Accesses in user mode are to be detected.

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 595 of 4535 Dec 26, 2018 Table 3A.65 IPG Registers (Base Address: FFFE E000H) Module Name Address Offset Size (Byte) Register Name Abbreviation Right*1 R/W Operable Bit Value after Reset 1 8 16 32 IPG +002H 2 Peripheral device protection violation access information register IPGECRUM SV R/W —   — Undefined (retained) +008H 4 Peripheral device protection violation access address register IPGADRUM SV R/W —    Undefined (retained) +00DH 1 Peripheral device protection enable register IPGENUM SV R/W —  — — 00 H +020H 1 Peripheral device protection setting register 0 IPGPMTUM0 SV R/W —  — — 00 H +022H 1 Peripheral device protection setting register 2 IPGPMTUM2 SV R/W —  — — 00H +023H 1 Peripheral device protection setting register 3 IPGPMTUM3 SV R/W —  — — 00H +024H 1 Peripheral device protection setting register 4 IPGPMTUM4 SV R/W —  — — 00 H Note 1. Registers for which “SV” is described are accessible by accesses with SV right (UM = 0).

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 596 of 4535 Dec 26, 2018 (4) Register Set (a) IPGECRUM — Peripheral Device Protection Violation Access Information Register Access: IPGECRUM register can be read or written in 16-bit units. IPGECRUML register can be read or written in 8-bit units. Address: IPGECRUM: FFFE E002H IPGECRUML: FFFE E002H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Value after reset 0 0 0 0 0 0 0 0 0 — — — — — — — R/W R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W Table 3A.66 IPGECRUM Register Contents Bit Position Bit Name Function 15 to 7 Reserved These bits are always read as 0. The write value should always be 0.

6 WD This bit is set to 1 when a violation occurred in read word, instruction fetch read access, write

word, CAXI, LDL or STC. In other cases, this bit is cleared to 0. 5 HW This bit is set to 1 when a violation occurred in read halfword or write haflword. In other cases, this bit is cleared to 0. 4 BY This bit is set to 1 when a violation occurred in read byte, write byte or bit operation. In other cases, this bit is cleared to 0. 3 EX This bit is set to 1 when a violation occurred in an instruction fetch read access. In other cases, this bit is cleared to 0.

2 WR This bit is set to 1 when a violation occurred in a write access, bit operation, or execution of

the CAXI instruction. In other cases, this bit is cleared to 0. 1 RD This bit is set to 1 when a violation occurred in a read access, bit operation, or execution of the CAXI instruction. In other cases, this bit is cleared to 0.

0 VD This bit is set to 1 when a violation of peripheral device protection is detected by a program

with the relevant right. Even if another violation of peripheral device protection is detected while this bit is 1, data of this IPGECRUM register and the IPGADRUM register is not updated and is retained. NOTE When the IRE bit value of the IPGENUM register (described later) is 0 and violation of peripheral device protection by a program operating in user mode is an instruction fetch read access, no bit of this register is updated.

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 597 of 4535 Dec 26, 2018 (b) IPGADRUM — Peripheral Device Protection Violation Access Address Register Access: IPGADRUM register can be read or written in 32-bit units. IPGADRUML, IPGADRUMH registers can be read or written in 16-bit units. IPGADRUMLL, IPGADRUMLH, IPGADRUMHL, IPGADRUMHH registers can be read or written in 8-bit units. Address: IPGADRUM: FFFE E008H IPGADRUML: FFFE E008H, IPGADRUMH: FFFE E00AH IPGADRUMLL: FFFE E008H, IPGADRUMLH: FFFE E009H, IPGADRUMHL: FFFE E00AH, IPGADRUMHH: FFFE E00BH Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EADR[31:16] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EADR[15:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Table 3A.67 IPGADRUM Register Contents Bit Position Bit Name Function 31 to 0 EADR These bits store the address of the access in which a violation occurred. NOTE When the IRE bit value of the IPGENUM register (described later) is 0 and violation of peripheral device protection by a program operating in user mode is an instruction fetch read access, no bit of this register is updated.

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 598 of 4535 Dec 26, 2018 (c) IPGENUM — Peripheral Device Protection Enable Register Access: IPGENUM register can be read or written in 8-bit units. Address: IPGENUM: FFFE E00DH Bit 7 6 5 4 3 2 1 0 Value after reset 0 0 0 0 0 0 0 0 R/W R R R R R R R/W R/W Table 3A.68 IPGENUM Register Contents Bit Position Bit Name Function 7 to 2 Reserved These bits are always read as 0. The write value should always be 0.

1 IRE This bit sets whether to store the access information in the peripheral device protection

violation access address register and the peripheral device protection violation access information register when a violation of peripheral device protection occurred in an instruction fetch access. 0: Instruction fetch access information is not stored. (value after reset) 1: Instruction fetch access information is stored. CAUTION: If you do not want to detect speculative instruction fetches (no instruction is executed in some cases), clear this bit to 0.

0 E This bit enables or disables the peripheral devices protection function against accesses by the

relevant access right. 0: The peripheral device protection function is disabled. (Value after reset) 1: The peripheral device protection function is enabled. (d) IPGPMTUM0 — Peripheral Device Protection Setting Register 0 Access: IPGPMTUM0 register can be read or written in 8-bit units. Address: IPGPMTUM0: FFFE E020H Bit 7 6 5 4 3 2 1 0 Value after reset 0 0 0 0 0 0 0 0 R/W R R/W R/W R/W R R R R Table 3A.69 IPGPMTUM0 Register Contents Bit Position Bit Name Function 7 Reserved These bits are always read as 0. The write value should always be 0. 6 X1 This bit sets whether to enable instruction fetch read access to P-Bus. 0: Instruction fetch read access to P-Bus is treated as violation. (Value after reset) 1: Instruction fetch read access to P-Bus is not restricted. 5 W1 This bit sets whether to enable write access to P-Bus. 0: Write access to P-Bus is treated as violation. (Value after reset) 1: Write access to P-Bus is not restricted. 4 R1 This bit sets whether to enable read access to P-Bus. 0: Read access to P-Bus is treated as violation. (Value after reset) 1: Read access to P-Bus is not restricted. 3 to 0 Reserved These bits are always read as 0. The write value should always be 0.

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 599 of 4535 Dec 26, 2018 (e) IPGPMTUM2 — Peripheral Device Protection Setting Register 2 Access: IPGPMTUM2 register can be read or written in 8-bit units. Address: IPGPMTUM2: FFFE E022H Bit 7 6 5 4 3 2 1 0 — — W1 R1 — — W0 R0 Value after reset 0 0 0 0 0 0 0 0 R/W R R R/W R/W R R R/W R/W Table 3A.70 IPGPMTUM2 Register Contents Bit Position Bit Name Function 7, 6 Reserved These bits are always read as 0. The write value should always be 0. 5 W1 This bit sets whether to enable write access to G0MEVm/IPIR_CHn. 0: Write access to G0MEVm/IPIR_CHn is treated as violation. (Value after reset) 1: Write access to G0MEVm/IPIR_CHn is not restricted. 4 R1 This bit sets whether to enable read access to G0MEVm/IPIR_CHn. 0: Read access to G0MEVm/IPIR_CHn is treated as violation. (Value after reset) 1: Read access to G0MEVm/IPIR_CHn is not restricted. 3, 2 Reserved These bits are always read as 0. The write value should always be 0. 1 W0 This bit sets whether to enable write access to INTC1. 0: Write access to INTC1 is treated as violation. (Value after reset) 1: Write access to INTC1 is not restricted 0 R0 This bit sets whether to enable read access to INTC1. 0: Read access to INTC1 is treated as violation. (Value after reset) 1: Read access to INTC1 is not restricted. (f) IPGPMTUM3 — Peripheral Device Protection Setting Register 3 Access: IPGPMTUM3 register can be read or written in 8-bit units. Address: IPGPMTUM3: FFFE E023H Bit 7 6 5 4 3 2 1 0 Value after reset 0 0 0 0 0 0 0 0 R/W R R R/W R/W R R R R Table 3A.71 IPGPMTUM3 Register Contents Bit Position Bit Name Function 7, 6 Reserved These bits are always read as 0. The write value should always be 0. 5 W1 This bit sets whether to enable write access to SysErrGen. 0: Write access to SysErrGen is treated as violation. (Value after reset) 1: Write access to SysErrGen is not restricted. 4 R1 This bit sets whether to enable read access to SysErrGen. 0: Read access to SysErrGen is treated as violation. (Value after reset) 1: Read access to SysErrGen is not restricted 3 to 0 Reserved These bits are always read as 0. The write value should always be 0.

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 600 of 4535 Dec 26, 2018 (g) IPGPMTUM4 — Peripheral Device Protection Setting Register 4 Access: IPGPMTUM4 register can be read or written in 8-bit units. Address: IPGPMTUM4: FFFE E024H Bit 7 6 5 4 3 2 1 0 Value after reset 0 0 0 0 0 0 0 0 R/W R R R R R R R/W R/W Table 3A.72 IPGPMTUM4 Register Contents Bit Position Bit Name Function 7 to 2 Reserved These bits are always read as 0. The write value should always be 0. 1 W0 This bit sets whether to enable write access to its own PEG. 0: Write access to its own PEG is treated as violation. (Value after reset) 1: Write access to its own PEG is not restricted. 0 R0 This bit sets whether to enable read access to its own PEG. 0: Read access to its own PEG is treated as violation. (Value after reset) 1: Read access to its own PEG is not restricted

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 601 of 4535 Dec 26, 2018 3A.2.4.3 System Error Generator Function (SEG) SEG (SysErrGen) controls interrupt notification and recording after a system error occurred by a data access. Multiple error occurrence inputs are categorized according to error factor, and are processed sequentially from the highest-priority error factor, generating an FE-level exception (SYSERR). The bit position of the SEGFLAG register becomes the error factor priority. Error factors of lower bits take precedence over error factors of upper bits. Error address information is recorded only once regardless of error frequency. The error with the highest priority among the error factors is valid when errors occur simultaneously. Recorded error address information is not overwritten by subsequent errors. (1) List of SEG Function Control Registers Table 3A.73 SEG Register (Base Address: FFFE E980H) Module Name Address Offset Size (Byte) Register Name Abbreviation Right*1 R/W Operable Bit Value after Reset 1 8 16 32 SEG +00H 2 SEG error control register SEGCONT SV R/W — —  — 0000H +02H 2 SEG error flag register SEGFLAG SV R/W — —  — 0000H +08H 4 SEG error address information register SEGADDR SV R/W — — —  Undefined (retained) Note 1. Registers for which “SV” is described are writable with the SV right (UM = 0). Attempting to write, if these conditions do not hold, leads to a SYSERR exception with setting VCIF flag. No restriction is provided for read accesses.

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 602 of 4535 Dec 26, 2018 (2) Register Set (a) SEGCONT — SEG Error Control Register This register is used to enable (= 1) or disable (= 0) notification of SysErr request in response to error flags that store the error occurrence status for each factor. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R R R R R R/W R/W R/W R R/W R R/W R R R R Table 3A.74 SEGCONT Register Contents Bit Position Bit Name Function 15 to 11 Reserved When read, the value after reset is returned. When writing, write the value after reset.

10 VCSE This bit enables notification of an error response detected inside system interconnect:

• Error response from external bus masters in write access
• Illegal response to local RAM or peripherals or Flash from optional master in access (except instruction fetch from CPU). And illegal response to optional slave from external AHB master in access. 9 APIE This bit enables notification of an error response from peripherals. The error notification includes the following cases:
• Error response from peripherals in write access
• PBG error in write access 8 IPGE This bit enables notification of IPG illegal access detection. 7 Reserved When read, the value after reset is returned. When writing, write the value after reset.

6 TCME This bit enables notification of an error during data access to its own local RAM from PE

master. The error notification includes the following cases:

• ECC uncorrectable error (DED or SED & SECDIS=1)
• Detection of an access to RAM unimplemented area 5 Reserved When read, the value after reset is returned. When writing, write the value after reset.

4 VCIE This bit enables notification of an error response during access to CPU peripherals, P-Bus

(read access), global RAM, retention RAM, other PE local RAM, H-Bus and CodeFlash by PE. The error notification includes the following cases:

• IPG error from CPU peripherals and P-Bus
• Error response from H-Bus peripherals
• PBG error / HBG error from P-Bus and H-Bus
• GRG error from global RAM and retention RAM
• PEG error from other PE local RAM
• ECC uncorrectable error from CodeFlash, global RAM, retention RAM and other PE local RAM (DED or SED & SECDIS = 1) This bit enables notification of an error response when accessing to a part of access prohibited areas in address map. 3 to 0 Reserved When read, the value after reset is returned. When writing, write the value after reset.

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 603 of 4535 Dec 26, 2018 (b) SEGFLAG — SEG Error Flag Register This register indicates error flags that store error occurrence status of each factors. The flags are set to 1 by an error occurrence input. The flags are not automatically cleared to 0. Both setting and clearing of each flag are supported in writing to the register. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R R R R R R/W R/W R/W R R/W R R/W R R R R Table 3A.75 SEGFLAG Register Contents Bit Position Bit Name Function 15 to 11 Reserved When read, the value after reset is returned. When writing, write the value after reset.

10 VCSF Flag corresponding to bit 10 of the SEGCONT register

9 APIF Flag corresponding to bit 9 of the SEGCONT register

8 IPGF Flag corresponding to bit 8 of the SEGCONT register

7 Reserved When read, the value after reset is returned. When writing, write the value after reset.

6 TCMF Flag corresponding to bit 6 of the SEGCONT register

5 Reserved When read, the value after reset is returned. When writing, write the value after reset.

4 VCIF Flag corresponding to bit 4 of the SEGCONT register

3 to 0 Reserved When read, the value after reset is returned. When writing, write the value after reset. NOTE An error may lead to setting of multiple error flags in SEG. For example, if an IPG error occurs at peripheral registers read, both IPGF bit and VCIF bit in SEGFLAG are set.

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 604 of 4535 Dec 26, 2018 (c) SEGADDR — Error Address Information Register Address information (one record) which is notified with error occurrence is stored in the register. The register is not updated while one or more bits in SEGFLAG register are set. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address[31:16] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address[15:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Table 3A.76 SEGADDR Register Contents Bit Position Bit Name Function 31 to 0 Address These bits store the error address information. CAUTIONS 1. SEGADDR stores error address information in case of an error occurrence related to VCIF bit or TCMF bit in SEGFLAG register. SEGADDR register stores all 0 data in case of an error occurrence related to VCSF bit, APIF bit or IPGF bit in SEGFLAG register. 2. In case of an error occurrence related to TCMF bit in SEGFLAG register, bit[18:0] of the error address are stored in SEGADDR[18:0] and SEGADDR[31:19] are filled with 0.

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 605 of 4535 Dec 26, 2018 (3) SEG Function (a) SEG Function: SYSERR Request Notification by Error Flag

• Setting an error flag takes precedence over clearing the same flag. − A simultaneous clearing operation is ignored.
• Priority of error factors − The bit position of each flags in SEGFLAG register which error notification is enabled by SEGCONT register becomes the error factor priority. Error factors of lower bits take precedence over error factors of upper bits. Notification is made from the highest-priority error factor. − The bit position of error factors is reported as a “SysErr factor code.”
• Conditions for starting SysErr request notification − Even if a flag which error notification is disabled by SEGCONT register is set to 1, notification is not made. − Notification is made immediately after a flag which error notification is enabled by SEGCONT register is set to − After clearing of a flag, notification is made if an other flag which error notification is enabled by SEGCONT register remains set.
• Finishing notification at a SysErr acknowledgement − Even after notification is finished, the flag is not cleared automatically. − Notification is not made until setting or clearing the flag again. − If an error flag that is prioritized higher than the error factor is set prior to an acknowledgement, the notification information may be replaced with a higher prioritized SysErr factor code. (b) SEG Function: Recording Error Address Information
• When an error which error notification is enabled by SEGCONT register occurs, the error address is retained in the SEGADDR register. − No information is retained by setting or clearing an error flag in SEGFLAG register. − When multiple error occurrence inputs are present simultaneously, information other than the prioritized error factor is not retained.
• While a flag which error notification is enabled by SEGCONT register is set to 1, overwrite to the SEGADDR register is inhibited. − If error occurrence input continues, information of subsequent error factors is not retained. − To reset the inhibition of overwrite to the register, clear either SEGCONT or SEGFLAG register (or both of them). (c) Supplementary Notes on SYSERR Exception
• Even when a SYSERR exception occurs, the value of the PSW.EBV bit is held, and the base address of the exception handler does not switch.

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 606 of 4535 Dec 26, 2018 3A.3 Inter-CPU Functions 3A.3.1 Processor Element Identifier The PEID, processor element ID number, can be read from the PEID field in the HTCFG0 register. Which CPU core is executing a specific program can be checked by referring to the PEID. The following shows the PEID of this product. CPU Core PEID CPU1 (PE1) 001B CPU2 (PE2) 010B 3A.3.2 Inter-Processor Interrupt Function Each CPU has the IPIR register as a peripheral function. Setting of the IPIR register enables an EI-level interrupt request from a PE to another PE. For details, see Section 3A.2.3, Inter-Processor Interrupts. 3A.3.3 Exclusive Control The local RAM, global RAM, retention RAM, and exclusive control registers (G0MEVm; m = 0 to 31) are available as a resource for exclusive control. Atomic operation instructions LDL/STC, CAXI, SET1, CLR1, and NOT1 can be executed on the local RAM, global RAM, and retention RAM. CAXI, SET1, CLR1, and NOT1 can be executed on the exclusive control registers (G0MEVm). Note that the LD and ST instructions can also access these resources, but the access is not atomic. 3A.3.3.1 Exclusive Control Register (G0MEVm; m = 0 to 31) This register supports exclusive control for variable shared between PEs (common resources). (MEV: Mutual Exclusion Variable Register)

• Thirty-two 32-bit G0MEVm registers are included.
• G0MEVm can be accessed in 8-, 16-, or 32-bit units.
• Access from CPU1 (PE1) and CPU2 (PE2) can be made.
• Atomic operation instructions CAXI, SET1, CLR1, and NOT1 can be executed. CPU1 (PE1) and CPU2 (PE2) each have an independent access path for G0MEVm registers. Therefore, when CPU1 (PE1) and CPU2 (PE2) each access different G0MEVm registers, they do not need to wait for access. When they access the same G0MEVm register, however, waiting for access is required. Table 3A.77 List of Registers Module Name Address*1 Register Name Symbol R/W Access Size Value after Reset 1 8 16 32 MEV +00H Exclusive control register 0 G0MEV0 R/W —    0000 0000H +04H Exclusive control register 1 G0MEV1 R/W —    0000 0000H +08H Exclusive control register 2 G0MEV2 R/W —    0000 0000H : : : : : : : : : +7CH Exclusive control register 31 G0MEV31 R/W —    0000 0000H Note 1. Base address: FFFE EC00H

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 607 of 4535 Dec 26, 2018 (1) G0MEVm — Exclusive Control Register m (m = 0 to 31) Access: G0MEVm can be read or written in 32-bit units. G0MEVmL and G0MEVmH can be read or written in 16-bit units. G0MEVmLL, G0MEVmLH, G0MEVmHL, G0MEVmHH can be read or written in 8-bit units. Address: G0MEVm: FFFE EC00H + m × 4H, G0MEVmL: FFFE EC00H + m × 4H, G0MEVmH: FFFE EC00H + m × 4H + 2H, G0MEVmLL: FFFE EC00H + m × 4H, G0MEVmLH: FFFE EC00H + m × 4H + 1H, G0MEVmHL: FFFE EC00H + m × 4H + 2H, G0MEVmHH: FFFE EC00H + m × 4H + 3H Value after reset: 0000 0000H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 G0MEVm[31:16] Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 G0MEVm[15:0] Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Table 3A.78 G0MEVm Registers Contents Bit Position Bit Name Function 31 to 0 G0MEVm[31:0] These bits set the value for exclusive control.

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 608 of 4535 Dec 26, 2018 The LDL.W and STC.W instructions can be used to perform atomic read-modify-write operations for accurate processing in the updating of memory in multicore systems. The LDL.W and STC.W instructions operate as follows.

• Link generation: The CPU is capable of generating links to both the local RAM and global RAM (including the retention RAM). Executing the LDL.W instruction on the target RAM for the operation leads to the link flag being set and a link being generated in response to reading by the instruction. Two link flag systems are provided, one each for the following two areas of RAM. (1) The local RAM for the given processor (2) The global RAM (including the retention RAM)
• Success in storing: After a link has been generated, storing will only proceed in response to executing an STC.W instruction corresponding to the generated link.
• Failure in storing: If a link is lost, storing does not proceed even when an STC.W instruction for the corresponding address is processed. Storing also does not proceed when an STC.W instruction that does not correspond to the link is processed.
• Condition for successful storing: If the following condition is met, the STC.W instruction is judged to be for the address corresponding to the link. − The address for the LDL.W instruction which generated the link matches that for the STC.W instruction.
• Loss of the link: If any of the following occurs, the link flag is cleared and the link is lost.
• Any of the following processing by the CPU for which the link was generated: − Execution of a STC.W instruction. The corresponding link (for (1) or (2) above) will be lost irrespective of the success or failure of storing. − Occurrence of an exception or the CPU executing an instruction to return from an exception processing routine (FERET or EIRET). The link flags for both areas of RAM are cleared. − Successive execution of LDL.W instructions for a location with the same link flags. The link generated in − response to the preceding LDL.W instruction will be lost. Do not execute such processing − Execution of a storing operation other than an STC.W instruction for the address generating the link. Do not execute such processing.
• Access as described below by another bus master: Any storing operation, including execution of an STC.W instruction for the address generating the link. The corresponding link will be lost. Success of the STC.W instruction means that the LDL.W and STC.W instructions have realized an atomic read-modify- write operation.

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 609 of 4535 Dec 26, 2018 3A.4 CPU2 Boot Up Operation After reset is released, CPU1 starts to fetch instruction. Initial condition of CPU2 is decided by option byte setting and its boot up condition can be set and confirmed by BOOTCTRL register. (1) List of Register Table 3A.79 BOOTCTRL Register (Base Address: FFC5 8000H) Module Name Address Offset Size (Byte) Register Name Abbreviation Right R/W Operable Bit Value after Reset 1 8 16 32 — +00H 4 BOOTCTRL register BOOTCTRL — R/W — — —  0000 0006H or 0000 0002H (2) BOOTCTRL — Boot Control Register This register is used to control the start-up of CPU2. By setting bit to “1”, CPU2 starts its pipeline operation. When the value of CPU2EN is “1”, it cannot be overwritten to “0” excluding reset. Access: BOOTCTRL register can be read or written in 32-bit units. Address: FFC5 8000H Value after reset: The value after reset depends on the option byte setting. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R R R R R R R R R R R R R R R R Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EN — — Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0/1*1 1 0 R/W R R R R R R R R R R R R R R/W R R Note 1. The setting of the option byte OPBT0.PE2BOOTEN is reflected. For details on the option byte, see Section 44.9, Option Bytes. Table 3A.80 BOOTCTRL Register Contents Bit Position Bit Name Function 31 to 3 Reserved When read, the value after reset is returned. When writing, write the value after reset.

2 CPU2EN CPU2 operation setting

0: Invalid boot up of CPU2. 1: Valid boot up of CPU2. When the value of PE2EN (option byte) is “0”, it cannot be overwritten to “1”. 1, 0 Reserved When read, the value after reset is returned. When writing, write the value after reset.

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 610 of 4535 Dec 26, 2018 3A.5 Notes 3A.5.1 Synchronization of Store Instruction Completion and Subsequent Instruction Execution When a control register is updated by a store instruction, there is a time lag after the CPU executes the store instruction and before the control register is actually updated. Therefore, if the updated content of the control register is to be used by the instruction following the store instruction, the appropriate synchronization is required. How to perform synchronization processing is shown below. For the procedures to synchronize updating system registers by LDSR instruction and the subsequent instruction execution, see APPENDIX A, Hazard Resolution Procedure for System Registers in the RH850G3KH User’s Manual: Software. When the updated results in the control registers are to be used by the subsequent instruction: Example 1: An interrupt is enabled by execution of an EI instruction after an interrupt request is cleared by access from the control register in the INTC2 and the peripheral circuits. Proceed as follows in this case. (1) Execute the store instruction to update a control register (ST.W, etc.). (2) Perform a dummy read of the above control register (LD.W, etc.). (3) Execute SYNCP. (4) Execute the subsequent instruction (EI). In case of RH850/F1KH, SYNCM instruction has the same effects as above-mentioned (2) and (3). (Excludes RCFDCn, RCFDCn ECC register access.) Example 2: When you must wait until a control register (control register A) has been completely updated before accessing another control register (control register B), execute similar processing. For example, different peripheral functions are linked, or the interrupt mask for INTC is cleared after the peripheral function is set. Note that this processing is not required if the control registers A and B belong to the same peripheral group. (1) Execute the store instruction to update the control register A (ST.W, etc.). (2) Perform a dummy read of the above control register (LD.W, etc.). (3) Execute SYNCP. (4) Execute the store instruction to access the control register B (ST.W, LD.W, etc.). In case of RH850/F1KH, SYNCM instruction has the same effects as above-mentioned (2) and (3). (Excludes RCFDCn, RCFDCn ECC register access.) The similar processing is also required when starting to access a memory or control register to be protected is started after a safety function (such as some kind of memory protection and ECC) has been completely set up.

RH850/F1KH, RH850/F1KM Section 3A CPU System of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 611 of 4535 Dec 26, 2018 When the updated results of the control register or memory to be used in the instruction fetch of the subsequent instruction: (a) In case of writing the instructions to the RAM before jumping to the RAM to execute instructions from the RAM, take the following procedure. (1) Execute the store instruction to update a memory (ST.W, etc.). (2) Perform a dummy read of the above memory (LD.W, etc.). (3) Execute SYNCP. (4) Execute SYNCI. (5) Execute the subsequent instruction (branch instruction, etc.). (b) In case of updating control registers for memory protection and ECC functions before jumping to the memory to be controlled by the registers, take the following procedure. (1) Execute the store instruction to update a control register (ST.W, etc.). (2) Perform a dummy read of the control register (LD.W, etc.). (3) Execute SYNCP. (4) Execute SYNCI. (5) Execute the subsequent instruction (branch instruction, etc.). When switching the code flash memory area: In this case, see Section 10, Usage Notes, (7) Updating the BFASELR register in the RH850/F1KH, F1KM, F1K Flash Memory User’s Manual: Hardware Interface. 3A.5.2 Ensure Coherency after Rewriting the Code Flash The CPU1 is equipped with the buffer for the code flash area as described in Section 3A.2.2, Buffers for Code Flash. Therefore, clear the buffer to ensure coherency after rewriting the code flash by self-programming. 3A.5.3 Access to Registers by Using Bit-Manipulation Instructions Writing bit-manipulation instructions consists of read-modify-write processing in 8-bit units. Thus, access by a bit- manipulation instruction is only possible for registers for which reading and writing in 8-bit units is possible. If a register includes multiple flag bits, the read-modify-write operation may lead to the clearing of flags that were not actually targets for clearing. 3A.5.4 Caution of Prefetching There is a possibility that the reading of the memory occurs by pre-fetch from the area where instruction codes do not exist. Secure more than 40-byte initialized area after the area where instruction codes are stored. 3A.5.5 Overwriting Context upon Acceptance of Multiple Exceptions Acceptance of an exception depends on the type of exception source, regardless of the states of the ID and NP bits in the PSW register. When multiple exceptions are generated, the contents of the system register which hold the context information are overwritten. For the conditions for acceptance and whether correct return or recovery is possible for each exception source, see the List of Exception Sources in the RH850G3KH User’s Manual: Software.

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 614 of 4535 Dec 26, 2018 Retention RAM RH850/F1KM-S4: The retention RAM is used to retain values in DeepSTOP mode. Since the continuous global RAM area is assigned for the retention RAM, the retention RAM can also serve as a global RAM for sharing data with the DMA. RH850/F1KM-S1: The retention RAM is used to retain values in DeepSTOP mode. Since the continuous local RAM area is assigned for the retention RAM, the retention RAM can also serve as a local RAM for sharing data with the DMA. Code flash The code flash memory is included for program storage. It is connected with CPU1 via the flash interface. Data flash The data flash memory can be rewritten by the CPU1. It has a greater write endurance than the code flash memory. P-Bus and H-Bus (RH850/F1KM-S4) The P-Bus connects the peripheral IPs. The P-Bus is divided into five peripheral groups, 1 to 5. P-Bus (RH850/F1KM-S1) The P-Bus connects the peripheral IPs. The P-Bus is divided into three peripheral groups, 1 to 3. INTC1, INTC2 There are two interrupt controllers, INTC1 and INTC2. DMA The DMA transfer module (PDMA) is included. Slave guard The slave guard is a function to prevent unauthorized access from the specific bus master, and consists of the following guard structures: (1) PE guard (PEG) The PE guard is a function to prevent unauthorized access to the resources (local RAM) in the PE from an external master. After reset is released, access from other than the own PE is prohibited. (2) Internal Peripheral Guard (IPG) The PE with system interconnects supports “Internal Peripheral Guard” (IPG) that protects the registers of peripherals against invalid accesses. (3) Global RAM guard (GRG) (RH850/F1KM-S4) The global RAM guard is a function to prevent unauthorized access to the global RAM and retention RAM from an external master. The global RAM is in the unprotected state (accessible from all bus master) after reset is released. For details, see Section 40B, Functional Safety of RH850/F1KM-S4. (4) Peripheral guard (PBG / HBG (RH850/F1KM-S4)) The peripheral guard is a function to prevent unauthorized access to peripherals. The control registers in the peripheral circuits are protected against illegal accesses. For details, see Section 40B, Functional Safety of RH850/F1KM-S4 and Section 40C, Functional Safety of RH850/F1KM-S1.

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 615 of 4535 Dec 26, 2018 3BC.2 CPU 3BC.2.1 Core Functions 3BC.2.1.1 Features Table 3BC.1, Features of the RH850G3KH2.0 Core lists features of the RH850G3KH2.0 core. Table 3BC.1 Features of the RH850G3KH2.0 Core Item Feature CPU ● Advanced 32-bit architecture for embedded control

• 32-bit internal data bus
• Thirty-two 32-bit general-purpose registers – RISC-type instruction set – Long-/short-format load/store instructions – Three-operand instructions – Instruction set based on C language
• CPU operating modes – User mode and supervisor mode
• Address space: 4-Gbyte linear address space for both data and instructions Coprocessor ● Floating-point operation coprocessor (FPU) – Supports single precision (32 bits) – Supports data types and exceptions conforming to IEEE754. – Rounding mode: Neighborhood, 0 direction, +∞ direction, and −∞ direction – Handling of denormalized numbers: Rounding down to 0 or exception notification to conform to IEEE754 Exception/Interrupt ● 16 interrupt priority levels settable for each channel
• Vector selection method selectable according to performance request or memory usage – Direct branching exception vectors – Indirect branching exception vectors referring to the address table
• Supports the high-speed save/return processing of the context by the dedicated instructions (PUSHSP and POPSP) at the generation of an interrupt Memory management ● Memory protection function (MPU): 16 areas settable Cache ● No cache memory is equipped.

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 616 of 4535 Dec 26, 2018 3BC.2.1.2 Register Set This subsection explains the program registers and system registers incorporated in this CPU. (1) Program Registers Program registers include the general-purpose registers (r0 to r31) and program counter (PC). Table 3BC.2 Program Registers Program Register Name Function Description General-purpose registers r0 Zero register Always retains “0” r1 Assembler reserved register Used as working register for generating addresses r2 Register for address and data variables (used when the real-time OS used does not use this register) r3 Stack pointer (SP) Used for generating a stack frame when a function is called r4 Global pointer (GP) Used for accessing a global variable in the data area r5 Text pointer (TP) Used as a register that indicates the start of the text area (area where program code is placed) r6 to r29 Register for address and data variables r30 Element pointer (EP) Used as a base pointer for generating addresses when accessing memory r31 Link pointer (LP) Used when the compiler calls a function Program counter PC Retains instruction addresses during execution of programs NOTE For further descriptions of r1, r3 to r5, and r31 used by the assembler and/or C compiler, see the specification of each software development environment.

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 617 of 4535 Dec 26, 2018 (a) General-Purpose Registers A total of 32 general-purpose registers (r0 to r31) are provided. All of these registers can be used for either data variables or address variables. Of the general-purpose registers, r0 to r5, r30, and r31 are assumed to be used for special purposes in software development environments, so it is necessary to note the following when using them. 1. r0, r3, r30 These registers are implicitly used by instructions. r0 is a register that always retains “0”. It is used for operations that use 0 and addressing with base address being 0. r3 is implicitly used by the PREPARE, DISPOSE, PUSHSP, and POPSP instructions. r30 is used as a base pointer when the SLD or SST instruction accesses memory. 2. r1, r4, r5, r31 These registers are implicitly used by the assembler and C compiler. When using these registers, register contents must first be saved so they are not lost and can be restored after the registers are used. 3. r2 This register might be used by a real-time OS in some cases. If the real-time OS that is being used does not use r2, r2 can be used as a register for address variables or data variables. (b) PC — Program Counter The PC retains the address of the instruction being executed. Bit 0 is fixed to 0, and branching to an odd number address is disabled. 31 0 Value after reset *1 PC PC31 to PC0 Table 3BC.3 PC Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 1 PC31 to PC1 These bits indicate the address of the instruction being executed. R/W *1 0 PC0 This bit is fixed to 0. Branching to an odd number address is disabled. R/W 0 Note 1. The value after reset differs depending on the setting value of the reset vector. For details, see (q) RBASE — Reset Vector Base Address Register.

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 618 of 4535 Dec 26, 2018 (2) Basic System Registers The basic system registers are used to control CPU status and to retain exception information. System registers are read from or written to by using the LDSR and STSR instructions and specifying the system register number, which is made up of a register number and a selection ID. Table 3BC.4 Basic System Registers Register No. (regID, selID) Symbol Function Access Permission SR0, 0 EIPC Status save registers when acknowledging EI level exception SV SR1, 0 EIPSW Status save registers when acknowledging EI level exception SV SR2, 0 FEPC Status save registers when acknowledging FE level exception SV SR3, 0 FEPSW Status save registers when acknowledging FE level exception SV SR5, 0 PSW Program status word *1 SR6, 0 FPSR (Refer to FPU function registers.) CU and SV SR7, 0 FPEPC (Refer to FPU function registers.) CU and SV SR8, 0 FPST (Refer to FPU function registers.) CU SR9, 0 FPCC (Refer to FPU function registers.) CU SR10, 0 FPCFG (Refer to FPU function registers.) CU SR11, 0 FPEC (Refer to FPU function registers.) CU and SV SR13, 0 EIIC EI level exception source register SV SR14, 0 FEIC FE level exception source register SV SR16, 0 CTPC CALLT execution status save register UM SR17, 0 CTPSW CALLT execution status save register UM SR20, 0 CTBP CALLT base pointer register UM SR28, 0 EIWR EI level exception working register SV SR29, 0 FEWR FE level exception working register SV SR0, 1 MCFG0 Machine configuration register SV SR2, 1 RBASE Reset vector base address register SV SR3, 1 EBASE Exception handler vector address register SV SR4, 1 INTBP Base address register of the interrupt handler address table SV SR5, 1 MCTL CPU control SV SR6, 1 PID Processor ID register SV SR11, 1 SCCFG SYSCALL operation setting register SV SR12, 1 SCBP SYSCALL base pointer register SV SR0, 2 HTCFG0 Thread configuration register SV SR6, 2 MEA Memory error address register SV SR7, 2 ASID Address space ID register SV SR8, 2 MEI Memory error information register SV Note 1. The access permission differs depending on the bit.

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 619 of 4535 Dec 26, 2018 (a) EIPC — Status Save Register when Acknowledging EI Level Exception When an EI level exception is acknowledged, the address of the instruction that was being executed when the EI level exception occurred, or of the next instruction, is saved to the EIPC register (see “Types of Exceptions” in Software Manual). Because there is only one pair of EI level exception status save registers, when processing multiple exceptions, the contents of these registers must be saved by a program. Be sure to set an even-numbered address to the EIPC register. An odd-numbered address cannot be specified. 31 0 Value after reset Undefined EIPC EIPC31 to EIPC0 Table 3BC.5 EIPC Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 1 EIPC31 to EIPC1 These bits indicate the PC saved when an EI level exception is acknowledged. R/W Undefined 0 EIPC0 This bit indicates the PC saved when an EI level exception is acknowledged. Always set this bit to 0. Even if it is set to 1, the value transferred to the PC when the EIRET instruction is executed is 0. R/W Undefined

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 620 of 4535 Dec 26, 2018 (b) EIPSW — Status Save Register when Acknowledging EI Level Exception When an EI level exception is acknowledged, the current PSW setting is saved to the EIPSW register. Because there is only one pair of EI level exception status save registers, when processing multiple exceptions, the contents of these registers must be saved by a program. 31 30 29 17 16 15 14 8 7 6 5 4 3 2 1 0 U M C U E B V N P E P I D S A T C Y O V S Z Value after reset 0000 0020H EIPSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3BC.6 EIPSW Register Contents Bit Position Bit Name Function R/W Value after Reset 31 — (Reserved for future expansion. Be sure to set to 0.) R 0 30 UM This bit stores the PSW.UM bit setting when an EI level exception is acknowledged. R/W 0 29 to 17 — (Reserved for future expansion. Be sure to set to 0.) R 0 16 CU This bit stores the PSW.CU field setting when an EI level exception is acknowledged. R/W 0 15 EBV This bit stores the PSW.EBV bit setting when an EI level exception is acknowledged. R/W 0 14 to 8 — (Reserved for future expansion. Be sure to set to 0.) R 0 7 NP This bit stores the PSW.NP bit setting when an EI level exception is acknowledged. R/W 0 6 EP This bit stores the PSW.EP bit setting when an EI level exception is acknowledged. R/W 0 5 ID This bit stores the PSW.ID bit setting when an EI level exception is acknowledged. R/W 1 4 SAT This bit stores the PSW.SAT bit setting when an EI level exception is acknowledged. R/W 0 3 CY This bit stores the PSW.CY bit setting when an EI level exception is acknowledged. R/W 0 2 OV This bit stores the PSW.OV bit setting when an EI level exception is acknowledged. R/W 0 1 S This bit stores the PSW.S bit setting when an EI level exception is acknowledged. R/W 0 0 Z This bit stores the PSW.Z bit setting when an EI level exception is acknowledged. R/W 0

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 621 of 4535 Dec 26, 2018 (c) FEPC — Status Save Register when Acknowledging FE Level Exception When an FE level exception is acknowledged, the address of the instruction that was being executed when the FE level exception occurred, or of the next instruction, is saved to the FEPC register (see “Types of Exceptions” in Software Manual). Because there is only one pair of FE level exception status save registers, when processing multiple exceptions, the contents of these registers must be saved by a program. Be sure to set an even-numbered address to the FEPC register. An odd-numbered address cannot be specified. 31 0 Value after reset Undefined FEPC FEPC31 to FEPC0 Table 3BC.7 FEPC Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 1 FEPC31 to FEPC1 These bits indicate the PC saved when an FE level exception is acknowledged. R/W Undefined 0 FEPC0 This bit indicates the PC saved when an FE level exception is acknowledged. Always set this bit to 0. Even if it is set to 1, the value transferred to the PC when the FERET instruction is executed is 0. R/W Undefined

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 622 of 4535 Dec 26, 2018 (d) FEPSW — Status Save Register when Acknowledging FE Level Exception When an FE level exception is acknowledged, the current PSW setting is saved to the FEPSW register. Because there is only one pair of FE level exception status save registers, when processing multiple exceptions, the contents of these registers must be saved by a program. 31 30 29 17 16 15 14 8 7 6 5 4 3 2 1 0 U M C U E B V N P E P I D S A T C Y O V S Z Value after reset 0000 0020H FEPSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3BC.8 FEPSW Register Contents Bit Position Bit Name Function R/W Value after Reset 31 — (Reserved for future expansion. Be sure to set to 0.) R 0 30 UM This bit stores the PSW.UM bit setting when an FE level exception is acknowledged. R/W 0 29 to 17 — (Reserved for future expansion. Be sure to set to 0.) R 0 16 CU This bit stores the PSW.CU field setting when an FE level exception is acknowledged. R/W 0 15 EBV This bit stores the PSW.EBV bit setting when an FE level exception is acknowledged. R/W 0 14 to 8 — (Reserved for future expansion. Be sure to set to 0.) R 0 7 NP This bit stores the PSW.NP bit setting when an FE level exception is acknowledged. R/W 0 6 EP This bit stores the PSW.EP bit setting when an FE level exception is acknowledged. R/W 0 5 ID This bit stores the PSW.ID bit setting when an FE level exception is acknowledged. R/W 1 4 SAT This bit stores the PSW.SAT bit setting when an FE level exception is acknowledged. R/W 0 3 CY This bit stores the PSW.CY bit setting when an FE level exception is acknowledged. R/W 0 2 OV This bit stores the PSW.OV bit setting when an FE level exception is acknowledged. R/W 0 1 S This bit stores the PSW.S bit setting when an FE level exception is acknowledged. R/W 0 0 Z This bit stores the PSW.Z bit setting when an FE level exception is acknowledged. R/W 0

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 623 of 4535 Dec 26, 2018 (e) PSW — Program Status Word PSW (program status word) is a set of flags that indicate the program status (instruction execution result) and bits that indicate the operation status of the CPU (flags are bits in the PSW that are referenced by conditional instructions (Bcond, CMOV, etc.)). CAUTIONS 1. When the LDSR instruction is used to change the contents of bit7 to 0 in this register, the changed contents become valid immediately after completion of the LDSR instruction execution. See “APPENDIX A. Hazard Resolution Procedure for System Registers” in Software Manual when the content of the other bits in this register is changed. 2. The access permission for the PSW register differs depending on the bit. All bits can be read, but some bits can only be written under certain conditions. See Table 3BC.9, Access Permission for PSW Register for the access permission for each bit. Table 3BC.9 Access Permission for PSW Register Bit Access Permission when Reading Access Permission when Writing Note 1. The access permission for the whole PSW register is UM, so the PIE exception does not occur even if the register is written by using an LDSR instruction when PSW.UM is 1. In this case, writing is ignored. 31 30 29 17 16 15 14 8 7 6 5 4 3 2 1 0 U M C U E B V N P E P I D S A T C Y O V S Z Value after reset 0000 0020H PSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3BC.10 PSW Register Contents Bit Position Bit Name Function R/W Value after Reset 31 — (Reserved for future expansion. Be sure to set to 0.) R 0 0: Supervisor mode 1: User mode R/W 0 29 to 17 — (Reserved for future expansion. Be sure to set to 0.) R 0 16 CU This bit indicates the coprocessor use permissions. When the bit corresponding to the coprocessor is 0, a coprocessor unusable exception occurs if an instruction for the coprocessor is executed or a coprocessor resource (system register) is accessed. CU bit 16: FPU R/W 0

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 624 of 4535 Dec 26, 2018 Table 3BC.10 PSW Register Contents Bit Position Bit Name Function R/W Value after Reset 15 EBV This bit indicates the reset vector and exception vector operation. See the description on RBASE ((q) RBASE — Reset Vector Base Address Register) and EBASE ((r) EBASE — Exception Handler Vector Address Register) in this section. R/W 0 14 to 8 — (Reserved for future expansion. Be sure to set to 0.) R 0 7 NP This bit disables the acknowledgement of FE level exception. When an FE level exception is acknowledged, this bit is set to 1 to disable the acknowledgement of EI level and FE level exceptions. As for the exceptions which the NP bit disables the acknowledgment, see Table 7BC.1, List of Exception Sources. 0: The acknowledgement of FE level exception is enabled. 1: The acknowledgement of FE level exception is disabled. R/W 0 interrupt controller is being serviced. It is set to 1 when the corresponding exception occurs. This bit does not affect acknowledging an exception request even when it is set to 1. 0: An exception other than an interrupt is not being serviced. 1: An exception other than an interrupt is being serviced. R/W 0 5 ID This bit disables the acknowledgement of EI level exception. When an EI level or FE level exception is acknowledged, this bit is set to 1 to disable the acknowledgement of EI level exception. As for the exceptions which the ID bit disables the acknowledgment, see Table 7BC.1, List of Exception Sources. This bit is also used to disable EI level exceptions from being acknowledged as a critical section while an ordinary program or interrupt is being serviced. It is set to 1 when the DI instruction is executed, and cleared to 0 when the EI instruction is executed. The change of the ID bit by the EI or ID instruction will be enabled from the next instruction. 0: EI level exception is not being processed or the section is not a critical section (after execution of EI instruction). 1: EI level exception is being processed or the section is a critical section (after execution of DI instruction). R/W 1 result of a saturated operation instruction has overflowed. This is a cumulative flag, so when the operation result of the saturated operation instruction becomes saturated, this bit is set to 1, but it is not cleared to 0 when the operation result for a subsequent instruction is not saturated. This bit is cleared to 0 by the LDSR instruction. This bit is neither set to 1 nor cleared to 0 when an arithmetic operation instruction is executed. 0: Not saturated 1: Saturated R/W 0 result. 0: Carry and borrow have not occurred. 1: Carry or borrow has occurred. R/W 0 operation. 0: Overflow has not occurred. 1: Overflow has occurred. R/W 0 1 S*1 This bit indicates whether or not the result of an operation is negative. 0: Result of operation is positive or 0. 1: Result of operation is negative. R/W 0 0 Z This bit indicates whether or not the result of an operation is 0. 0: Result of operation is not 0. 1: Result of operation is 0. R/W 0 Note 1. The operation result of the saturation processing is determined in accordance with the contents of the OV flag and S flag during a saturated operation. The SAT flag is set to 1 only when the OV flag is set to 1 in a saturated operation.

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 625 of 4535 Dec 26, 2018 Flag Status Operation Result after Saturation Processing Operation Result Status SAT OV S Exceeded positive maximum value 1 1 0 7FFF FFFFH Exceeded negative maximum value 1 1 1 8000 0000H Positive (maximum value not exceeded) Value prior to operation is retained. 0 0 Operation result itself Negative (maximum value not exceeded) 1 (f) EIIC — EI Level Exception Source Register The EIIC register retains the source of any EI level exception that occurs. The value retained in this register is an exception source code corresponding to a specific exception source. 31 0 Value after reset 0000 0000H EIIC EIIC31 to EIIC0 Table 3BC.11 EIIC Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 0 EIIC31 to EIIC0 These bits store the exception source code when an EI level exception is acknowledged. The EIIC15 to EIIC0 field stores the lower 16 bits of the exception source code. The EIIC31 to EIIC16 field stores detailed exception source codes defined individually for each exception. If there is no particular definition of a function related to the exception, these bits are set to 0. R/W 0 (g) FEIC — FE Level Exception Source Register The FEIC register retains the source of any FE level exception that occurs. The value retained in this register is an exception source code corresponding to a specific exception source. 31 0 Value after reset 0000 0000H FEIC FEIC31 to FEIC0 Table 3BC.12 FEIC Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 0 FEIC31 to FEIC0 These bits store the exception source code when an FE level exception is acknowledged. The FEIC15 to FEIC0 field stores the lower 16 bits of the exception source code. The FEIC31 to FEIC16 field stores detailed exception source codes defined individually for each exception. If there is no particular definition of a function related to the exception, these bits are set to 0. R/W 0

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 626 of 4535 Dec 26, 2018 (h) CTPC — Status Save Register when Executing CALLT Instruction When a CALLT instruction is executed, the address of the next instruction after the CALLT instruction is saved to CTPC. Be sure to set an even-numbered address to the CTPC register. An odd-numbered address cannot be specified. 31 0 Value after reset Undefined CTPC CTPC31 to CTPC0 Table 3BC.13 CTPC Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 1 CTPC31 to CTPC1 These bits indicate the PC of the instruction after the CALLT instruction. R/W Undefined 0 CTPC0 This bit indicates the PC of the instruction after the CALLT instruction. Always set this bit to 0. Even if it is set to 1, the value transferred to the PC when the CTRET instruction is executed is 0. R/W Undefined (i) CTPSW — Status Save Register when Executing CALLT Instruction When a CALLT instruction is executed, some of the PSW (program status word) settings are saved to CTPSW. 31 5 4 3 2 1 0 S A T C Y O V Value after reset 0000 0000H CTPSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 S Z Table 3BC.14 CTPSW Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 5 — (Reserved for future expansion. Be sure to set to 0.) R 0 4 SAT This bit stores the PSW.SAT bit setting when the CALLT instruction is executed. R/W 0 3 CY This bit stores the PSW.CY bit setting when the CALLT instruction is executed. R/W 0 2 OV This bit stores the PSW.OV bit setting when the CALLT instruction is executed. R/W 0 1 S This bit stores the PSW.S bit setting when the CALLT instruction is executed. R/W 0 0 Z This bit stores the PSW.Z bit setting when the CALLT instruction is executed. R/W 0

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 627 of 4535 Dec 26, 2018 (j) CTBP — CALLT Base Pointer Register The CTBP register is used to specify table addresses of the CALLT instruction and generate target addresses. Be sure to set the CTBP register to a halfword address. 31 0 Value after reset Undefined CTBP CTBP31 to CTBP0 Table 3BC.15 CTBP Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 1 CTBP31 to CTBP1 These bits indicate the base pointer address of the CALLT instruction. These bits indicate the start address of the table used by the CALLT instruction. R/W Undefined 0 CTBP0 This bit indicates the base pointer address of the CALLT instruction. This bit indicates the start address of the table used by the CALLT instruction. Always set this bit to 0. R 0 (k) ASID — Address Space ID Register This register indicates the address space ID. This is used to identify the address space provided by the memory management function. 31 10 9 0 Value after reset Undefined ASID 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASID Table 3BC.16 ASID Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 10 — (Reserved for future expansion. Be sure to set to 0.) R 0 9 to 0 ASID These bits indicate the address space ID. R/W Undefined (l) EIWR — EI Level Exception Working Register The EIWR register is used as a working register when an EI level exception has occurred. 31 0 Value after reset Undefined EIWR EIWR31 to EIWR0 Table 3BC.17 EIWR Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 0 EIWR31 to EIWR0 These bits constitute a working register that can be used for any purpose during the servicing of an EI level exception. This register can be used to temporarily save the values of general-purpose registers, etc. R/W Undefined

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 628 of 4535 Dec 26, 2018 (m) FEWR — FE Level Exception Working Register The FEWR register is used as a working register when an FE level exception has occurred. 31 0 Value after reset Undefined FEWR FEWR31 to FEWR0 Table 3BC.18 FEWR Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 0 FEWR31 to FEWR0 These bits constitute a working register that can be used for any purpose during the servicing of an FE level exception. This register can be used to temporarily save the values of general-purpose registers, etc. R/W Undefined (n) HTCFG0 — Thread Configuration Register 31 19 18 17 16 15 14 0 Value after reset 0001 8000H HTCFG0 0 0 0 0 0 0 0 0 0 0 0 0 0 PEID 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3BC.19 HTCFG0 Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 19 — (Reserved for future expansion. Be sure to set to 0.) R 0 18 to 16 PEID These bits indicate the processor element number. R 001B 15 — (Reserved for future expansion. Be sure to set to 1.) R 1 14 to 0 — (Reserved for future expansion. Be sure to set to 0.) R 0 (o) MEA — Memory Error Address Register 31 0 Value after reset Undefined MEA MEA Table 3BC.20 MEA Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 0 MEA These bits store the violation address when an MAE (misaligned) or MPU occurs. R/W Undefined

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 629 of 4535 Dec 26, 2018 (p) MEI — Memory Error Information Register This register is used to store information about the instruction that caused a misaligned (MAE) or memory protection (MDP) exception when such an exception occurred. This information is used during emulation. 31 21 20 16 15 11 10 9 8 7 6 5 1 0 R W Value after reset Undefined MEI 0 0 0 0 0 0 0 0 0 0 0 REG 0 0 0 0 0 DS 0 0 ITYPE Table 3BC.21 MEI Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 21 — (Reserved for future expansion. Be sure to set to 0.) R 0 20 to 16 REG These bits indicate the number of the source or destination register accessed by the instruction that caused the exception. For details, see Table 3BC.22, Instructions Causing Exceptions and Values of MEI Register. R/W Undefined 15 to 11 — (Reserved for future expansion. Be sure to set to 0.) R 0 10, 9 DS These bits indicate the data type of the instruction that caused the exception.*1 0: Byte (8 bits) 1: Halfword (16 bits) 2: Word (32 bits) 3: Double-word (64 bits) For details, see Table 3BC.22, Instructions Causing Exceptions and Values of MEI Register. R/W Undefined exception. 0: Signed 1: Unsigned For details, see Table 3BC.22, Instructions Causing Exceptions and Values of MEI Register. R/W Undefined 7, 6 — (Reserved for future expansion. Be sure to set to 0.) R 0 5 to 1 ITYPE These bits indicate the instruction that caused the exception. For details, see Table 3BC.22, Instructions Causing Exceptions and Values of MEI Register. R/W Undefined exception was read (Load-memory) or write (Store-memory). 0: Read (Load-memory) 1: Write (Store-memory) For details, see Table 3BC.22, Instructions Causing Exceptions and Values of MEI Register. R/W Undefined Note 1. Even if the data is divided and access is made several times due to the specifications of the hardware, the original data type indicated by the instruction is stored. Table 3BC.22 Instructions Causing Exceptions and Values of MEI Register Instruction REG DS U RW ITYPE SLD.B dst 0 (byte) 0 (signed) 0 (read) 00000B SLD.BU dst 0 (byte) 1 (unsigned) 0 (read) 00000B SLD.H dst 1 (halfword) 0 (signed) 0 (read) 00000B SLD.HU dst 1 (halfword) 1 (unsigned) 0 (read) 00000B SLD.W dst 2 (word) 0 (signed) 0 (read) 00000B SST.B src 0 (byte) 0 (signed) 1 (write) 00000B SST.H src 1 (halfword) 0 (signed) 1 (write) 00000B

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 630 of 4535 Dec 26, 2018 Table 3BC.22 Instructions Causing Exceptions and Values of MEI Register Instruction REG DS U RW ITYPE SST.W src 2 (word) 0 (signed) 1 (write) 00000B LD.B (disp16) dst 0 (byte) 0 (signed) 0 (read) 00001B LD.BU (disp16) dst 0 (byte) 1 (unsigned) 0 (read) 00001B LD.H (disp16) dst 1 (halfword) 0 (signed) 0 (read) 00001B LD.HU (disp16) dst 1 (halfword) 1 (unsigned) 0 (read) 00001B LD.W (disp16) dst 2 (word) 0 (signed) 0 (read) 00001B ST.B (disp16) src 0 (byte) 0 (signed) 1 (write) 00001B ST.H (disp16) src 1 (halfword) 0 (signed) 1 (write) 00001B ST.W (disp16) src 2 (word) 0 (signed) 1 (write) 00001B LD.B (disp23) dst 0 (byte) 0 (signed) 0 (read) 00010B LD.BU (disp23) dst 0 (byte) 1 (unsigned) 0 (read) 00010B LD.H (disp23) dst 1 (halfword) 0 (signed) 0 (read) 00010B LD.HU (disp23) dst 1 (halfword) 1 (unsigned) 0 (read) 00010B LD.W (disp23) dst 2 (word) 0 (signed) 0 (read) 00010B ST.B (disp23) src 0 (byte) 0 (signed) 1 (write) 00010B ST.H (disp23) src 1 (halfword) 0 (signed) 1 (write) 00010B ST.W (disp23) src 2 (word) 0 (signed) 1 (write) 00010B LD.DW (disp23) dst 3 (double-word) 0 (signed) 0 (read) 00010B ST.DW (disp23) src 3 (double-word) 0 (signed) 1 (write) 00010B LDL.W dst 2 (word) 0 (signed) 0 (read) 00111B STC.W src 2 (word) 0 (signed) 1 (write) 00111B CAXI dst 2 (word) 0 (signed) 0 (read)/1 (write) 01000B SET1 — 0 (byte) 0 (signed) 0 (read)/1 (write) 01001B CLR1 — 0 (byte) 0 (signed) 0 (read)/1 (write) 01001B NOT1 — 0 (byte) 0 (signed) 0 (read)/1 (write) 01001B TST1 — 0 (byte) 0 (signed) 0 (read) 01001B PREPARE — 2 (word) 0 (signed) 1 (write) 01100B DISPOSE — 2 (word) 0 (signed) 0 (read) 01100B PUSHSP — 2 (word) 0 (signed) 1 (write) 01101B POPSP — 2 (word) 0 (signed) 0 (read) 01101B SWITCH — 1 (halfword) 0 (signed) 0 (read) 10000B CALLT — 1 (halfword) 1 (unsigned) 0 (read) 10001B SYSCALL — 2 (word) 0 (signed) 0 (read) 10010B Interrupt (table reference)*1 — 2 (word) 0 (signed) 0 (read) 10101B Note 1. When reading the interrupt vector by using the table reference method. NOTE dst: destination register number, src: source register number

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 631 of 4535 Dec 26, 2018 (q) RBASE — Reset Vector Base Address Register This register indicates the reset vector address when there is a reset. If the PSW.EBV bit is 0, this vector address is also used as the exception vector address. 31 9 8 1 0 RINT Value after reset *1 RBASE RBASE31 to RBASE9 0 0 0 0 0 0 0 0 Table 3BC.23 RBASE Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 9 RBASE31 to RBASE9 These bits indicate the reset vector when there is a reset. When PSW.EBV = 0, this address is also used as the exception vector. For RBASE8 to RBASE0, 0 is used implicitly. R 0000 0000 0000 0000 0000 000 B*1 8 to 1 — (Reserved for future expansion. Be sure to set to 0.) R 0 is reduced. See Section 7BC.10.1, Direct Vector Method. This bit is valid when PSW.EBV = 0. R 0 Note 1. The value depends on the reset vector. The values set at shipment are shown in the table. When the reset vector is modified, the address will be changed. (r) EBASE — Exception Handler Vector Address Register This register indicates the exception handler vector address. This register is valid when the PSW.EBV bit is 1. 31 9 8 1 0 RINT Value after reset Undefined EBASE EBASE31 to EBASE9 0 0 0 0 0 0 0 0 Table 3BC.24 EBASE Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 9 EBASE31 to EBASE9 The exception handler routine address is changed to the address resulting from adding the offset address of each exception to the base address specified for this register. For EBASE8 to EBASE0, 0 is used implicitly. R/W Undefined 8 to 1 — (Reserved for future expansion. Be sure to set to 0.) R 0 is reduced. See Section 7BC.10.1, Direct Vector Method. R/W Undefined

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 632 of 4535 Dec 26, 2018 (s) INTBP — Base Address Register of the Interrupt Handler Address Table This register indicates the base address of the address table when the table reference method is selected as the interrupt handler address selection method. 31 9 8 0 Value after reset Undefined INTBP INTBP31 to INTBP9 0 0 0 0 0 0 0 0 0 Table 3BC.25 INTBP Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 9 INTBP31 to INTBP9 These bits indicate the base pointer address for an interrupt when the table reference method is used. The value indicated by these bits is the first address in the table used to determine the exception handler when the interrupt specified by the table reference method (EIINT0 to EIINT511) is acknowledged. For INTBP8 to INTBP0, 0 is used implicitly. R/W Undefined 8 to 0 — (Reserved for future expansion. Be sure to set to 0.) R 0 (t) PID — Processor ID Register The PID register retains a processor identifier that is unique to the CPU. The PID register is a read-only register. 31 0 Value after reset 0500 03A8H PID PID Table 3BC.26 PID Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 24 PID Architecture Identifier This identifier indicates the architecture of the processor. R 05H 23 to 8 Function Identifier This identifier indicates the functions of the processor. These bits indicate whether or not functions defined per bit are implemented (1: implemented, 0: not implemented). Bits 23 to 11: Reserved Bit 10: Double-precision floating-point operation function Bit 9: Single-precision floating-point operation function Bit 8: Memory protection function (MPU) R 0003H 7 to 0 Version Identifier This identifier indicates the version of the processor. R A8H

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 633 of 4535 Dec 26, 2018 (u) SCCFG — SYSCALL Operation Setting Register This register is used to specify operations related to the SYSCALL instruction. Be sure to set an appropriate value to this register before using the SYSCALL instruction. 31 8 7 0 Value after reset Undefined SCCFG 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIZE Table 3BC.27 SCCFG Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 8 — (Reserved for future expansion. Be sure to set to 0.) R 0 7 to 0 SIZE These bits specify the maximum number of entries of a table that the SYSCALL instruction references. The maximum number of entries the SYSCALL instruction references is 1 if SIZE is 0, and 256 if SIZE is 255. By setting the maximum number of entries appropriately in accordance with the number of functions branched by the SYSCALL instruction, the memory area can be effectively used. If vectors exceeding the maximum number of entries are specified for the SYSCALL instruction, the first entry is selected. Place an error processing routine at the first entry. R/W Undefined (v) SCBP — SYSCALL Base Pointer Register The SCBP register is used to specify a table address of the SYSCALL instruction and generate a target address. Be sure to set an appropriate value to this register before using the SYSCALL instruction. Be sure to set a word address to the SCBP register. 31 0 Value after reset Undefined SCBP SCBP31 to SCBP0 Table 3BC.28 SCBP Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 2 SCBP31 to SCBP2 These bits indicate the base pointer address of the SYSCALL instruction. These bits indicate the start address of the table used by the SYSCALL instruction. R/W Undefined 1, 0 SCBP1, SCBP0 These bits indicate the base pointer address of the SYSCALL instruction. These bits indicate the start address of the table used by the SYSCALL instruction. Always set these bits to 0. R 0

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 634 of 4535 Dec 26, 2018 (w) MCFG0 — Machine Configuration Register This register indicates the CPU configuration. 31 18 17 16 15 3 2 1 0 Value after reset 0001 0004H MCFG0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPID 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Table 3BC.29 MCFG0 Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 18 — (Reserved for future expansion. Be sure to set to 0.) R 0 17, 16 SPID These bits indicate the system protection number. R/W 01B 15 to 3 — (Reserved for future expansion. Be sure to set to 0.) R 0 2 — (Reserved for future expansion. Be sure to set to 1.) R 1 1, 0 — (Reserved for future expansion. Be sure to set to 0.) R 0 (x) MCTL — Machine Control Register This register is used to control the CPU. 31 2 1 0 M A U I C Value after reset 8000 0002H MCTL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3BC.30 MCTL Register Contents Bit Position Bit Name Function R/W Value after Reset 31 — (Reserved for future expansion. Be sure to set to 1.) R 1 30 to 2 — (Reserved for future expansion. Be sure to set to 0.) R 0 1 MA This bit is used to control the misaligned access. 0: In the event of a misaligned access, an exception is always generated.*1 1: The correct operation is controlled by hardware.*2 R/W 1 0 UIC This bit is used to control the interrupt enable/disable operation in user mode. When this bit is set to 1, executing the EI/DI instruction in user mode becomes possible. R/W 0 Note 1. Excluding LD.DW, and ST.DW for word boundary allocation. Note 2. Exception still occurs in case of LD.DW or ST.DW for misaligned access except word boundary allocation.

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 635 of 4535 Dec 26, 2018 (3) Interrupt Function Registers Table 3BC.31 Interrupt Function System Registers Register No. (regID, selID) Symbol Function Access Permission SR7, 1 FPIPR FPI exception interrupt priority setting register SV SR10, 2 ISPR Priority of interrupt being serviced register SV SR11, 2 PMR Interrupt priority masking register SV SR12, 2 ICSR Interrupt control status register SV SR13, 2 INTCFG Interrupt function setting register SV

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 636 of 4535 Dec 26, 2018 (a) FPIPR — FPI Exception Interrupt Priority Setting Register This register is used to set the interrupt priority of FPI exception. 31 5 4 0 Value after reset 0000 0000H FPIPR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FPIPR Table 3BC.32 FPIPR Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 5 — (Reserved for future expansion. Be sure to set to 0.) R 0 4 to 0 FPIPR These bits are used to specify the interrupt priority of floating-point operation exceptions (imprecise) (FPI). Specify values from 0 to 16. Specifying 17 or greater is prohibited. FPI exceptions are handled using the specified interrupt priority. If an FPI exception occurs at the same time as an interrupt that has the same priority, the FPI exception is prioritized. NOTE: A set value of more than 16 is treated as 16. R/W 0

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 637 of 4535 Dec 26, 2018 (b) ISPR — Priority of Interrupt being Serviced Register This register retains the priority of the EIINTn interrupt being serviced by the CPU. This priority value is then used to perform priority ceiling processing when multiple interrupts occur. 31 16 15 0 Value after reset 0000 0000H ISPR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISP15 to ISP0 Table 3BC.33 ISPR Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 16 — (Reserved for future expansion. Be sure to set to 0.) R 0 15 to 0 ISP15 to ISP0 These bits indicate the acknowledgment status of an EIINTn interrupt with a priority that corresponds to the relevant bit position. 0: An interrupt request for an interrupt whose priority corresponds to the relevant bit position has not been acknowledged. 1: An interrupt request for an interrupt whose priority corresponds to the relevant bit position is being serviced by the CPU core. The bit positions correspond to the following priority levels. Bit Priority When an interrupt request (EIINTn) is acknowledged, the bit corresponding to the acknowledged interrupt request is automatically set to 1. If PSW.EP is 0 when the EIRET instruction is executed, the bit with the highest priority among the ISP15 to ISP0 bits that are set to 1 (0 is the highest priority) is cleared to 0.* While a bit in this register is set to 1, same or lower priority interrupts (EIINTn) and FPI exceptions*2 are masked. Priority level judgment is therefore not performed when the system is determining whether to acknowledge an exception, meaning that exceptions will not be acknowledged. When performing software-based priority control using the PMR register, be sure to clear this register by using the INTCFG.ISPC bit. 3 0 Note 1. Interrupt acknowledgment and auto-updating of values when the EIRET instruction is executed are disabled by setting (1) to the INTCFG.ISPC bit. It is recommended to enable auto-updating of values, so in normal cases, the INTCFG.ISPC bit should be cleared to 0. Note 2. Since FPI exceptions have the same level of priority as EIINTn interrupts, they are affected by interrupts in the same way as the ISPR. The priority of FPI exceptions is set by the FPIPR register. Note 3. This is R or R/W, depending on the setting of the INTCFG.ISPC bit. It is recommended to use this register as a read-only (R) register.

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 638 of 4535 Dec 26, 2018 (c) PMR — Interrupt Priority Masking Register This register is used to mask the specified interrupt priority. 31 16 15 0 Value after reset 0000 0000H PMR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PM15 to PM0 Table 3BC.34 PMR Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 16 — (Reserved for future expansion. Be sure to set to 0.) R 0 15 to 0 PM15 to PM0 These bits mask an interrupt request with a priority level that corresponds to the relevant bit position. 0: Servicing of an interrupt with a priority that corresponds to the relevant bit position is enabled. 1: Servicing of an interrupt with a priority that corresponds to the relevant bit position is disabled. The bit positions correspond to the following priority levels: Bit Priority While a bit in this register is set to 1, interrupts (EIINTn) and FPI exceptions*1 with the priority corresponding to that bit are masked. Priority level judgment is therefore not performed when the system is determining whether to acknowledge an exception, meaning that exceptions will not be acknowledged*2. R/W 0 Note 1. Since FPI exceptions are specified as the same level of priority as that of interrupts (EIINTn), it is affected by the PMR like interrupts. The priority of FPI exceptions is set by the FPIPR register. Note 2. Specify the masks by setting the bits to 1 in order from the lowest-priority bit. For example, FF00H can be set, but F0F0H or 00FFH cannot. (d) ICSR — Interrupt Control Status Register This register indicates the interrupt control status in the CPU. 31 2 1 0 PMFP PMEI Value after reset 0000 0000H ICSR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3BC.35 ICSR Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 2 — (Reserved for future expansion. Be sure to set to 0.) R 0 PMR register exists. R 0 the PMR register exists. R 0

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 639 of 4535 Dec 26, 2018 (e) INTCFG — Interrupt Function Setting Register This register is used to specify settings related to the CPU’s internal interrupt function. 31 1 0 ISPC Value after reset 0000 0000H INTCFG 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3BC.36 INTCFG Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 1 — (Reserved for future expansion. Be sure to set to 0.) R 0 0 ISPC This bit specifies how the ISPR register is updated. 0: The ISPR register is automatically updated. Updates triggered by the program (via execution of LDSR instruction) are ignored. 1: The ISPR register is not automatically updated. Updates triggered by the program (via execution of LDSR instruction) are performed. If this bit is cleared to 0, the bits of the ISPR register are automatically set to 1 when an interrupt (EIINTn) is acknowledged, and cleared to 0 when the EIRET instruction is executed. In this case, updating by the program (via execution of an LDSR instruction) is ignored. If this bit is set to 1, the bits of the ISPR register are not updated by the acknowledgement of an interrupt (EIINTn) or by execution of the EIRET instruction. In this case, the bits can be updated by an LDSR instruction executed by the program. In normal cases, the ISPC bit should be cleared to 0. When performing software-based control of interrupt priorities, however, set this bit (1) and perform priority control by using the PMR register. R/W 0

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 640 of 4535 Dec 26, 2018 (4) FPU Function Registers The FPU uses the CPU general-purpose registers (r0 to r31). There are no register files used only for floating-point operations. The RH850/F1KM supports single-precision floating-point instruction and thirty-two 32-bit registers can be specified. These registers correspond to general-purpose registers r0 to r31. The FPU can use the following system registers to control floating-point operation Table 3BC.37 FPU System Registers Register No. (regID, selID) Symbol Function Access Permission SR6, 0 FPSR Floating-point operation setting/status register CU and SV SR7, 0 FPEPC Floating-point exception program counter register CU and SV SR8, 0 FPST Floating-point operation status register CU SR9, 0 FPCC Floating-point operation comparison result register CU SR10, 0 FPCFG Floating-point operation configuration register CU SR11, 0 FPEC Floating-point exception control register CU and SV

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 641 of 4535 Dec 26, 2018 (a) FPSR — Floating-point Operation Setting/Status Register This register indicates the execution status of floating-point operations and any exceptions that occur. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0 F N I F P E M F S Value after reset See below FPSR 0 RM 0 E V Z O U I V Z O U I V Z O U I *1 *2 *3 Note 1. Cause bits (XC) Note 2. Enable bits(XE) Note 3. Preservation bits (XP) Table 3BC.38 FPSR Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 24 CC[7:0] These are the CC (condition) bits. They store the results of floating-point comparison instructions. The CC7 to CC0 bits are not affected by any instructions except the comparison instruction and LDSR instruction. 0: Comparison result is false 1: Comparison result is true R/W Undefined 23 FN This bit enables flush-to-nearest mode. When the FN bit is set to 1, if the rounding mode is RN and the operation result is a subnormal number, the number is flushed to the nearest number. R/W 0 operands. R/W 0 21 PEM This bit specifies whether to handle an exception as a precise exception. If the PEM bit is 1, exceptions that are caused by the execution of a floating-point operation instruction are handled as precise exceptions. R/W 0 20 — (Reserved for future expansion. Be sure to set to 0.) R 0 19, 18 RM These are the rounding mode control bits. The RM bits define the rounding mode that the FPU uses for all floating-point instructions. RM Bits Mnemonic Description 19 18 0 0 RN Rounds the result to the nearest representable value. If the value is exactly in-between the two nearest representable values, the result is rounded toward the value whose least significant bit is 0. 0 1 RZ Rounds the result toward 0. The result is the nearest to the value that does not exceed the absolute value of the result with infinite accuracy. 1 0 RP Rounds the result toward +∞. The result is nearest to a value greater than the accurate result with infinite accuracy. 1 1 RM Rounds the result toward −∞. The result is nearest to a value less than the accurate result with infinite accuracy. R/W 00 flushed. If the FS bit is set, input operands and operation results that are subnormal numbers are flushed without causing an unimplemented operation exception (E). An input operand that is a subnormal number is flushed to 0 with the same sign. Operation results that are subnormal numbers either become 0 or the minimum normalized number, depending on the rounding mode. Operation Result that is a Subnormal Number Rounding Mode and Value after Flushing RN*1 RZ RP RM Positive +0 +0 +2Emin +0 Negative −0 −0 −0 −2Emin Note 1. If the rounding mode is RN and the FPSR.FN bit is set to 1, flushing will occur in the direction of higher accuracy. R/W 1 16 — (Reserved for future expansion. Be sure to set to 0.) R 0 15 to 10 XC (E, V, Z, O, U, I) These are the cause bits. R/W Undefined

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 642 of 4535 Dec 26, 2018 Table 3BC.38 FPSR Register Contents Bit Position Bit Name Function R/W Value after Reset 9 to 5 XE (V, Z, O, U, I) These are the enable bits. R/W 0 4 to 0 XP (V, Z, O, U, I) These are the preservation bits. R/W Undefined (b) FPEPC — Floating-point Exception Program Counter Register When an exception that is enabled by an enable bit occurs, the program counter (PC) of the instruction that caused the exception is stored. 31 0 Value after reset Undefined FPEPC FPEPC31 to FPEPC0 Table 3BC.39 FPEPC Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 1 FPEPC31 to FPEPC1 These bits store the program counter (PC) of the floating-point instruction that caused the exception when a floating-point operation exception that is enabled by an enable bit occurs. R/W Undefined caused the exception when a floating-point operation exception that is enabled by an enable bit occurs. Always set this bit to 0. R 0 (c) FPST — Floating-point Operation Status Register This register reflects the contents of the FPSR register bits related to the operation status. 31 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I F Value after reset Undefined FPST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E V Z O U I 0 0 V Z O U I *1 *2 Note 1. Cause bits (XC) Note 2. Preservation bits (XP) Table 3BC.40 FPST Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 14 — (Reserved for future expansion. Be sure to set to 0.) R 0 13 to 8 XC (E, V, Z, O, U, I) These are cause bits. Values written to these bits are reflected in FPSR.XC bits. R/W Undefined 7, 6 — (Reserved for future expansion. Be sure to set to 0.) R 0 operands. R/W 0 4 to 0 XP (V, Z, O, U, I) These are preservation bits. Values written to these bits are reflected in FPSR.XP bits. R/W Undefined

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 643 of 4535 Dec 26, 2018 (d) FPCC — Floating-point Operation Comparison Result Register This register reflects the contents of the FPSR.CC[7:0] bits. 31 8 7 6 5 4 3 2 1 0 CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0 Value after reset Undefined FPCC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3BC.41 FPCC Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 8 — (Reserved for future expansion. Be sure to set to 0.) R 0 7 to 0 CC[7:0] These are CC (condition) bits. They store the result of a floating-point comparison instruction. The CC[7:0] bits are not affected by any instructions except the comparison instruction and LDSR instruction. Values written to these bits are reflected in the CC[7:0] bits of FPSR. 0: Comparison result is false 1: Comparison result is true R/W Undefined (e) FPCFG — Floating-point Operation Configuration Register This register reflects the contents of the FPSR register bits related to the operation settings. 31 10 9 8 7 5 4 3 2 1 0 Value after reset 0000 0000H FPCFG 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RM 0 0 0 V Z O U I Note 1. Enable bits (XE) Table 3BC.42 FPCFG Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 10 — (Reserved for future expansion. Be sure to set to 0.) R 0 9, 8 RM These are rounding mode control bits. The RM bits define the rounding mode that the FPU uses for all floating-point instructions. Values written to these bits are reflected in RM bits of FPSR. RM Bits Mnemonic Description 9 8 0 0 RN Rounds the result to the nearest representable value. If the value is exactly in-between the two nearest representable values, the result is rounded toward the value whose least significant bit is 0. 0 1 RZ Rounds the result toward 0. The result is the nearest to the value that does not exceed the absolute value of the result with infinite accuracy. 1 0 RP Rounds the result toward +∞. The result is nearest to a value greater than the accurate result with infinite accuracy. 1 1 RM Rounds the result toward −∞. The result is nearest to a value less than the accurate result with infinite accuracy. R/W 0 7 to 5 — (Reserved for future expansion. Be sure to set to 0.) R 0 4 to 0 XE (V, Z, O, U, I) These are the enable bits. R/W 0

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 644 of 4535 Dec 26, 2018 (f) FPEC — Floating-point Exception Control Register This register controls the floating-point operation exception. 31 1 0 FPIVD Value after reset 0000 0000H FPEC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3BC.43 FPEC Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 1 — (Reserved for future expansion. Be sure to set to 0.) R 0 0 FPIVD*1 This bit indicates the status of reporting the FPI exception. If this bit is set to 1, the FPI exception is reported to the CPU but is not acknowledged. It is automatically cleared to 0 when the CPU acknowledges the FPI exception. While this bit is set to 1, all the floating-point instructions are invalidated. Report of the FPI exception can be canceled by clearing (0) this bit by the LDSR instruction while it is set to 1. When report of the FPI exception is canceled, the CPU does not acknowledge the FPI exception. 0: FPI exception is not reported. 1: FPI exception is reported. R/W 0 Note 1. The FPIVD bit can only be cleared to 0 by the write operation of the LDSR instruction. It cannot be set to 1.

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 645 of 4535 Dec 26, 2018 (5) MPU Function Registers Table 3BC.44 MPU Function System Registers Register No. (regID, selID) Symbol Function Access Permission SR0, 5 MPM Memory protection operation mode setting SV SR1, 5 MPRC MPU region control SV SR4, 5 MPBRGN MPU base region number SV SR5, 5 MPTRGN MPU end region number SV SR8, 5 MCA Memory protection setting check address SV SR9, 5 MCS Memory protection setting check size SV SR10, 5 MCC Memory protection setting check command SV SR11, 5 MCR Memory protection setting check result SV SR0, 6 MPLA0 Protection area lower limit address SV SR1, 6 MPUA0 Protection area upper limit address SV SR2, 6 MPAT0 Protection area attribute SV SR4, 6 MPLA1 Protection area lower limit address SV SR5, 6 MPUA1 Protection area upper limit address SV SR6, 6 MPAT1 Protection area attribute SV SR8, 6 MPLA2 Protection area lower limit address SV SR9, 6 MPUA2 Protection area upper limit address SV SR10, 6 MPAT2 Protection area attribute SV SR12, 6 MPLA3 Protection area lower limit address SV SR13, 6 MPUA3 Protection area upper limit address SV SR14, 6 MPAT3 Protection area attribute SV SR16, 6 MPLA4 Protection area lower limit address SV SR17, 6 MPUA4 Protection area upper limit address SV SR18, 6 MPAT4 Protection area attribute SV SR20, 6 MPLA5 Protection area lower limit address SV SR21, 6 MPUA5 Protection area upper limit address SV SR22, 6 MPAT5 Protection area attribute SV SR24, 6 MPLA6 Protection area lower limit address SV SR25, 6 MPUA6 Protection area upper limit address SV SR26, 6 MPAT6 Protection area attribute SV SR28, 6 MPLA7 Protection area lower limit address SV SR29, 6 MPUA7 Protection area upper limit address SV SR30, 6 MPAT7 Protection area attribute SV SR0, 7 MPLA8 Protection area lower limit address SV SR1, 7 MPUA8 Protection area upper limit address SV SR2, 7 MPAT8 Protection area attribute SV SR4, 7 MPLA9 Protection area lower limit address SV SR5, 7 MPUA9 Protection area upper limit address SV SR6, 7 MPAT9 Protection area attribute SV SR8, 7 MPLA10 Protection area lower limit address SV SR9, 7 MPUA10 Protection area upper limit address SV SR10, 7 MPAT10 Protection area attribute SV SR12, 7 MPLA11 Protection area lower limit address SV SR13, 7 MPUA11 Protection area upper limit address SV

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 646 of 4535 Dec 26, 2018 Table 3BC.44 MPU Function System Registers Register No. (regID, selID) Symbol Function Access Permission SR14, 7 MPAT11 Protection area attribute SV SR16, 7 MPLA12 Protection area lower limit address SV SR17, 7 MPUA12 Protection area upper limit address SV SR18, 7 MPAT12 Protection area attribute SV SR20, 7 MPLA13 Protection area lower limit address SV SR21, 7 MPUA13 Protection area upper limit address SV SR22, 7 MPAT13 Protection area attribute SV SR24, 7 MPLA14 Protection area lower limit address SV SR25, 7 MPUA14 Protection area upper limit address SV SR26, 7 MPAT14 Protection area attribute SV SR28, 7 MPLA15 Protection area lower limit address SV SR29, 7 MPUA15 Protection area upper limit address SV SR30, 7 MPAT15 Protection area attribute SV

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 647 of 4535 Dec 26, 2018 (a) MPM — Memory Protection Operation Mode Register The memory protection mode register is used to define the basic operating state of the memory protection function. 31 2 1 0 S V P M P E Value after reset 0000 0000H MPM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3BC.45 MPM Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 2 — (Reserved for future expansion. Be sure to set to 0.) R 0 1 SVP In SV mode (when PSW.UM = 0), this bit is used to specify whether to restrict access according to the SX, SW, and SR bits of the MPAT register for each protection area.*1 0: As usual, implicitly enable all access in SV mode. 1: Restrict access according to the SX, SW, and SR bits even in SV mode.*2 R/W 0 0 MPE This bit is used to specify whether to enable or disable the MPU function. 0: Disable 1: Enable R/W 0 Note 1. If the SVP bit is set to 1, access will be restricted in accordance with the setting for each protection area, even in SV mode. Therefore, specify the protection area beforehand so that the access from the program which set the SVP bit is not restricted. Note 2. If access is restricted in SV mode, execution of MDP exceptions or the MIP exception handling itself might not be possible depending on the settings. Be careful to specify settings so that access by the exception handler and to the memory area necessary for exception handling is permitted. (b) MPRC — MPU Region Control Register 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E E E E E E E E E E E E E E E E Value after reset 0000 0000H MPRC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3BC.46 MPRC Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 16 — (Reserved for future expansion. Be sure to set to 0.) R 0 15 to 0 E15 to E0 These are the enable bits for each protection area. Bit En is a copy of bit MPATn.E (where n = 15 to 0). R/W 0

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 648 of 4535 Dec 26, 2018 (c) MPBRGN — MPU Base Region Register This register indicates the minimum usable MPU area number. 31 5 4 0 Value after reset 0000 0000H MPBRGN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPBRGN Table 3BC.47 MPBRGN Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 5 — (Reserved for future expansion. Be sure to set to 0.) R 0 4 to 0 MPBRGN These bits indicate the smallest number of an MPU area. These bits always indicate 0. R 0 (d) MPTRGN — MPU End Region Register This register indicates the maximum usable MPU area number + 1. 31 5 4 0 Value after reset 0000 0010H MPTRGN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPTRGN Table 3BC.48 MPTRGN Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 5 — (Reserved for future expansion. Be sure to set to 0.) R 0 4 to 0 MPTRGN These bits indicate the largest number of an MPU area + 1. These bits indicate the maximum number of MPU areas incorporated into the hardware. R 10000B (e) MCA — Memory Protection Setting Check Address Register This register is used to specify the base address of the area for which a memory protection setting check is to be performed. 31 0 Value after reset Undefined MCA MCA31 to MCA0 Table 3BC.49 MCA Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 0 MCA31 to MCA0 These bits are used to specify the start address of the memory area that is subject to a memory protection setting check in bytes. R/W Undefined

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 649 of 4535 Dec 26, 2018 (f) MCS — Memory Protection Setting Check Size Register This register is used to specify the size of the area for which a memory protection setting check is to be performed. 31 0 Value after reset Undefined MCS MCS31 to MCS0 Table 3BC.50 MCS Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 0 MCS31 to MCS0 These bits are used to specify the size of the memory area that is subject to a memory protection setting check and the size of the target area in bytes. Because the specified size is assumed to represent an unsigned integer, it is not possible to check an area in the direction in which the address value decreases relative to the MCA register value. Do not specify 0000 0000 H for the MCS register. R/W Undefined (g) MCC — Memory Protection Setting Check Command Register This register is used to specify the base address of the area where memory protection settings are checked. 31 0 Value after reset 0000 0000H MCC MCC31 to MCC0 Table 3BC.51 MCC Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 0 MCC31 to MCC0 When any value is written to the MCC register, a memory protection setting check starts. By setting up the MCA/MCS register and then writing to the MCC register, results are stored in MCR. Because the check is started by any written value, a check can be started by using r0 as the source register without using any unnecessary registers. Note that, for the check, the results are applied according to each area setting regardless of the state of the PSW.UM bit. When the MCC register is read, value 0000 0000 H is always returned. R/W 0

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 650 of 4535 Dec 26, 2018 (h) MCR — Memory Protection Setting Check Result Register This register is used to store the results of a memory protection setting check. Be sure to clear bits 31 to 9, 7 and 6. 31 9 8 7 6 5 4 3 2 1 0 O V S X E S W E S R E U X E U W E U R E Value after reset Undefined MCR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3BC.52 MCR Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 9 — (Reserved for future expansion. Be sure to set to 0.) R 0 bit. In other cases, 0 is stored in this bit. R/W Undefined 7, 6 — (Reserved for future expansion. Be sure to set to 0.) R 0 execution is permitted for that area in supervisor mode, 1 is stored in this bit. In other cases, 0 is stored in this bit. R/W Undefined to that area is permitted in supervisor mode, 1 is stored in this bit. In other cases, 0 is stored in this bit. R/W Undefined reading from that area is permitted in supervisor mode, 1 is stored in this bit. In other cases, 0 is stored in this bit. R/W Undefined execution is permitted for that area in user mode, 1 is stored in this bit. In other cases, 0 is stored in this bit. R/W Undefined to that area is permitted in user mode, 1 is stored in this bit. In other cases, 0 is stored in this bit. R/W Undefined reading from that area is permitted in user mode, 1 is stored in this bit. In other cases, 0 is stored in this bit. R/W Undefined (i) MPLAn — Protection Area Lower Limit Address Register These registers indicate the lower limit address of area n (where n = 0 to 15). 31 2 1 0 Value after reset Undefined MPLAn MPLAn 0 0 Table 3BC.53 MPLAn Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 2 MPLA31 to MPLA2 These bits indicate the lower limit address of area n. For MPLA1 and MPLA0, 0 is used implicitly. R/W Undefined 1, 0 — (Reserved for future expansion. Be sure to set to 0.) R 0

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 651 of 4535 Dec 26, 2018 (j) MPUAn — Protection Area Upper Limit Address Register These registers indicate the upper limit address of area n (where n = 0 to 15). 31 2 1 0 Value after reset Undefined MPUAn MPUAn 0 0 Table 3BC.54 MPUAn Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 2 MPUA31 to MPUA2 These bits indicate the upper limit address of area n. For MPUAn.MPUA1 and MPUA0, 1 is used implicitly. R/W Undefined 1, 0 — (Reserved for future expansion. Be sure to set to 0.) R 0

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 652 of 4535 Dec 26, 2018 (k) MPATn — Protection Area Attribute Register These registers indicate the attributes of area n (where n = 0 to 15). 31 26 25 16 15 8 7 6 5 4 3 2 1 0 S X S W S R U X U W U R Value after reset Undefined MPATn 0 0 0 0 0 0 ASID 0 0 0 0 0 0 0 0 E G Table 3BC.55 MPATn Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 26 — (Reserved for future expansion. Be sure to set to 0.) R 0 25 to 16 ASID These bits indicate the ASID value to be used as the area match condition. R/W Undefined 15 to 8 — (Reserved for future expansion. Be sure to set to 0.) R 0 7 E This bit indicates whether area n is enabled or disabled. 0: Area n is disabled. 1: Area n is enabled. R/W 0 6 G 0: Areas match only if ASIDs are equal. 1: Areas match even if ASIDs are not equal. If this bit is 0, MPATn.ASID = ASID.ASID is used as the area match condition. If this bit is 1, areas may match even if the values of MPATn.ASID and ASID.ASID are not equal. R/W Undefined 5 SX This bit indicates the execution privilege for the supervisor mode.*1 0: Execution is disabled. 1: Execution is enabled. R/W Undefined 4 SW This bit indicates whether writing is enabled in the supervisor mode.*1 0: Writing is disabled. 1: Writing is enabled. R/W Undefined 3 SR This bit indicates whether writing is enabled in the supervisor mode.*1 0: Reading is disabled. 1: Reading is enabled. R/W Undefined 2 UX This bit indicates the execution privilege for the user mode. 0: Execution is disabled. 1: Execution is enabled. R/W Undefined 1 UW This bit indicates whether writing is enabled in the user mode. 0: Writing is disabled. 1: Writing is enabled. R/W Undefined 0 UR This bit indicates whether writing is enabled in the user mode. 0: Reading is disabled. 1: Reading is enabled. R/W Undefined Note 1. If access is restricted in SV mode, execution of MDP exceptions or the MIP exception handling itself might not be possible depending on the settings. Be careful to specify settings so that access by the exception handler and to the memory area necessary for exception handling is permitted.

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 653 of 4535 Dec 26, 2018 (6) Cache Operation Function Registers The RH850/F1KM does not include a cache operation function, so all the following registers return a value of 0 when read, and writing to these registers is ignored. Table 3BC.56 Cache Operation Function Registers Register No. (regID, selID) Symbol Function Access Permission SR12, 4 BWERRL Not implemented. A value of 0 is returned when read and writing is ignored. SV SR13, 4 BWERRH SV SR14, 4 BRERRL SV SR15, 4 BRERRH SV SR16, 4 ICTAGL SV SR17, 4 ICTAGH SV SR18, 4 ICDATL SV SR19, 4 ICDATH SV SR20, 4 DCTAGL SV SR21, 4 DCTAGH SV SR22, 4 DCDATL SV SR23, 4 DCDATH SV SR24, 4 ICCTRL SV SR25, 4 DCCTRL SV SR26, 4 ICCFG SV SR27, 4 DCCFG SV SR28, 4 ICERR SV SR29, 4 DCERR SV 3BC.2.1.3 Instruction See “Instruction” in Software Manual. A snooze instruction halts operation of the CPU core for 32 clocks.

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 655 of 4535 Dec 26, 2018 3BC.2.2.3 Registers for Buffer Control (1) List of Buffer Control Registers Table 3BC.57 Buffer Control Register (Base Address: FFC5 B000H) Module Name Address Offset Size (Byte) Register Name Abbreviation Right R/W Operable Bit Value after Reset 1 8 16 32 FBUF_CTRL +000H 4 Flash buffer clear control register FBUFCCTL — R/W —    0000 0000H (2) Register Sets Access: FBUFCCTL register can be read or written in 32-bit units. FBUFCCTLL register can be read or written in 16-bit units. FBUFCCTLLL register can be read or written in 8-bit units. Address: FBUFCCTL: FFC5 B000H FBUFCCTLL: FFC5 B000H FBUFCCTLLL: FFC5 B000H 31 1 0 FBUFCLR Value after reset 0000 0000H FBUFCCTL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3BC.58 FBUFCCTL Register Contents Bit Position Bit Name Function R/W Value after Reset 31 to 1 Reserved When read, the value after reset is returned. When writing, write the value after reset. R 0 0 FBUFCLR Buffer clear bits. To clear buffers, write 1 to this bit and then write 0. 0: Buffers are valid 1: Buffers are invalid (cleared) R/W 0 Please do following procedures when you want to clear the buffers. Step 1: Write 0 to FBUFCCTL.FBUFCLR Step 2: Write 1 to FBUFCCTL.FBUFCLR Step 3: Write 0 to FBUFCCTL.FBUFCLR Step 4: Read the FBUFCCTL register (dummy read) Step 5: Execute the SYNCP instruction Step 6: Execute the SYNCI instruction If you do not do Step 3 after Step 2, the buffers are kept invalid during FBUFCCTL.FBUFCLR = 1.

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 656 of 4535 Dec 26, 2018 3BC.2.3 Reliability Functions 3BC.2.3.1 PE Guard Function (PEG) (1) Overview of the PEG Function The PEG is a constituent of the slave guard system to prevent unauthorized access to the resources in the CPU (PE) from an external master. This function protects access to the local RAM*1 in the PE. In the initial state after a reset, access by masters other than own PE is disabled. Setting the registers listed in (3) List of PEG Protection Setting Registers enables access by masters other than own PE. Note 1. It is the local RAM and the retention RAM in RH850/F1KM-S1. (1) Detecting PE guard violation If an external master makes an unauthorized access to the resource area in a PE for which PE guard is set, the access is detected as a PE guard violation. (2) Blocking unauthorized access When a PE guard violation is detected, unauthorized access to the internal resources of the PE are blocked to prevent unauthorized modification of the contents of PE resources. (3) Notifying occurrence of violation An error response to an unauthorized access is sent to the request source of external master. When DMA Controller makes an unauthorized access, meanwhile, a DMA transfer error is detected. A PE guard violation is notified as INTGUARD interrupt request which is a source of FEINT. (2) Protection Made by SPID

• Setting PEG Protection − Up to four areas can be set depending on the local RAM address*1 of the own PE. − The area range is specified by the base address and the mask bit (4 kbytes to 4 Gbytes). − “Read enable” and “write enable” can be set for each area. − “Enable” or “disable” can be selected based on the system protection identifier (SPID) for each area. Note 1. It is the local RAM address and the retention RAM address in RH850/F1KM-S1.
• Procedure for permitting access by using the system protection identifier (SPID) 1. Is the area subject to access is the local RAM area*1? If so, go to step 2. 2. Is the area subject to access is within the range of valid areas 0, 1, 2, or 3? If so, go to step 3. Otherwise, return an error response. 3. Are all the conditions below for the relevant area satisfied? If so, permit access. − The system protection identifier (SPID) is enabled. − Required operations (read/write) are enabled. Otherwise, return an error response. Note 1. It is the local RAM area and the retention RAM area in RH850/F1KM-S1.

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 657 of 4535 Dec 26, 2018 (3) List of PEG Protection Setting Registers Specify the necessary settings in the registers below to protect PE resources from unauthorized access by an external master.

• Whether to permit access to the local RAM*1 in the PE can be specified. Note 1. It is local RAM and retention RAM in RH850/F1KM-S1. Table 3BC.59 PEG Registers (Base Address: FFFE E600H) Module Name Address Offset Size (Byte) Register Name Abbreviation Right R/W Operable Bit Value after Reset 1 8 16 32 PEG +00CH 4 PEG SPID control register PEGSP — R/W —    0000 0000H +080H 4 PEG area 0 mask setting register PEGG0MK — R/W —    0000 0000H +084H 4 PEG area 0 base setting register PEGG0BA — R/W —    0000 0000H +090H 4 PEG area 1 mask setting register PEGG1MK — R/W —    0000 0000H +094H 4 PEG area 1 base setting register PEGG1BA — R/W —    0000 0000H +0A0H 4 PEG area 2 mask setting register PEGG2MK — R/W —    0000 0000H +0A4H 4 PEG area 2 base setting register PEGG2BA — R/W —    0000 0000H +0B0H 4 PEG area 3 mask setting register PEGG3MK — R/W —    0000 0000H +0B4H 4 PEG area 3 base setting register PEGG3BA — R/W —    0000 0000H

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 658 of 4535 Dec 26, 2018 (4) Register Set (a) PEGSP — PEG SPID Control Register Access: PEGSP register can be read or written in 32-bit units. PEGSPL register can be read or written in 16-bit units. PEGSPLL register can be read or written in 8-bit units. Address: PEGSP: FFFE E60CH PEGSPL: FFFE E60CH PEGSPLL: FFFE E60CH Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R R R R R R R R R R R R R R R R Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R R R R R R R R R R R R R R R R/W Table 3BC.60 PEGSP Register Contents Bit Position Bit Name Function 31 to 1 Reserved When read, the value after reset is returned. When writing, write the value after reset. 0 SPEN Access permission to external master with specified SPID. 0: Not permit. 1: Permit.

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 659 of 4535 Dec 26, 2018 (b) PEGGnMK — PEG Area n Mask Setting Register (n = 0 to 3) The PEGGnMK register defines which bits of PEGGnBA.GnBASE are compared with the access address. If bit PEGGnMK.GnMASK[m] is cleared, bit PEGGnBA.GnBASE[m] is compared with bit m of the access address. Access: PEGGnMK register can be read or written in 32-bit units. PEGGnMKL, PEGGnMKH registers can be read or written in 16-bit units. PEGGnMKLH, PEGGnMKHL, PEGGnMKHH registers can be read or written in 8-bit units. Address: PEGGnMK: FFFE E680H + (10H × n) PEGGnMKL: FFFE E680H + (10H × n), PEGGnMKH: FFFE E682H + (10H × n) PEGGnMKLH: FFFE E681H + (10H × n), PEGGnMKHL: FFFE E682H + (10H × n), PEGGnMKHH: FFFE E683H + (10H × n) Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GnMASK Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R R R R R R R R R R R R Table 3BC.61 PEGGnMK Register Contents Bit Position Bit Name Function 31 to 12 GnMASK 0: Target bits are compared when determining the PE guard area. 1: Target bits are not compared when determining the PE guard area. 11 to 0 Reserved When read, the value after reset is returned. When writing, write the value after reset. NOTE When you write to the PEGGnMK register, the corresponding GnEN bit in the PEGGnBA register is cleared automatically.

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 660 of 4535 Dec 26, 2018 (c) PEGGnBA — PEG Area n Base Setting Register (n = 0 to 3) In combination with the PEGGnMK register, this register specifies a range or ranges within PE guard protection area n. Setting the GnEN bit to 1 validates the access enable conditions specified by this register and the PEGGnMK register. Access: PEGGnBA register can be read or written in 32-bit units. PEGGnBAL, PEGGnBAH registers can be read or written in 16-bit units. PEGGnBALL, PEGGnBALH, PEGGnBAHL, PEGGnBAHH registers can be read or written in 8-bit units. Address: PEGGnBA: FFFE E684H + (10H × n) PEGGnBAL: FFFE E684H + (10H × n), PEGGnBAH: FFFE E686H + (10H × n) PEGGnBALL FFFE E684H + (10H × n), PEGGnBALH FFFE E685H + (10H × n), PEGGnBAHL: FFFE E686H + (10H × n), PEGGnBAHH: FFFE E687H + (10H × n) Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GnBASE Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GnBASE — — — — GnSP3 GnSP2 GnSP1 GnSP0 — GnWR GnRD GnEN Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R R R R R/W R/W R/W R/W R R/W R/W R/W Table 3BC.62 PEGGnBA Register Contents Bit Position Bit Name Function 31 to 12 GnBASE Base address that specifies the range of PE guard protection area n. 11 to 8 Reserved When read, the value after reset is returned. When writing, write the value after reset. 7 GnSP3 Access permission setting from SPID = 3 external master to PE guard protection area n. 0: Not permit. 1: Permit. 6 GnSP2 Access permission setting from SPID = 2 external master to PE guard protection area n. 0: Not permit. 1: Permit. area n. 0: Not permit. 1: Permit.

4 GnSP0 Access permission setting from SPID = 0 (peripheral device connected to H-BUS*2) external

master to PE guard protection area n. 0: Not permit. 1: Permit. 3 Reserved When read, the value after reset is returned. When writing, write the value after reset. 2 GnWR Write access permission to PE guard protection area n. 0: Write access is disabled. 1: Write access is enabled.

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 661 of 4535 Dec 26, 2018 Table 3BC.62 PEGGnBA Register Contents Bit Position Bit Name Function 1 GnRD Read access permission to PE guard protection area n. 0: Read access is disabled. 1: Read access is enabled. 0: Settings for access enable conditions are disabled. 1: Settings for access enable conditions are enabled. Note 1. Setting value of MCFG0.SPID Note 2. H-BUS is only supported by RH850/F1KM-S4. NOTE When you write to the PEGGnMK register, the corresponding GnEN bit in the PEGGnBA register is cleared automatically.

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 662 of 4535 Dec 26, 2018 3BC.2.3.2 PE’s Internal Peripheral Device Protection Function (IPG) (1) Overview of the IPG Function The IPG is a function to prevent unauthorized accesses to peripheral devices from the CPU core equipped with the IPG. The IPG achieves the following functions. The IPG covers accesses to the SEG, the PEG, the INTC1 and P-Bus. (a) Detecting Violation of Peripheral Device Protection If the CPU makes an unauthorized access to an area (peripheral device) for which peripheral device protection is set, the access is detected as “violation of peripheral device protection”. (b) Storing Unauthorized Access Information When a violation of peripheral device protection is detected, the unauthorized-access information is stored in the IPG’s internal register. (c) Blocking Unauthorized Accesses When a violation of peripheral device protection is detected, unauthorized accesses to peripheral devices are blocked to prevent contents of peripheral devices from being modified illegally. (d) Notifying Violation When a violation of peripheral device protection is detected, a request for generating an exception is made to ask the CPU to stop the processing. NOTE Even if a request for generating an exception is immediately sent to the CPU in step (d) Notifying Violation above, a subsequent access issued (before receiving a request from the IPG) by the CPU that does not know an occurrence of violation may illegally modify contents of peripheral devices. (Accesses after a violation has occurred result in unauthorized accesses.) (2) IPG Function

• This function invalidates accesses according to their attributes (including address, transfer type, and access right).
• After an access right violation is detected until the error flag (described later) is cleared by writing by the software, subsequent accesses are invalidated. However, invalidation is applied only to accesses from the CPU and is not applied to accesses from outside the CPU core. Invalidation is performed independently of addresses.
• When a request for accessing different peripheral devices simultaneously is made due to misalignment or double- word access, the access is executed when all such accesses are enabled. (3) IPG Protection Setting Registers for Illegal Users To protect peripheral devices from unauthorized accesses by programs in user mode, necessary settings are required for the registers listed below.
• Accesses in user mode are to be detected.

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 663 of 4535 Dec 26, 2018 Table 3BC.63 IPG Registers (Base Address: FFFE E000H) Module Name Address Offset Size (Byte) Register Name Abbreviation Right*1 R/W Operable Bit Value after Reset 1 8 16 32 IPG +002H 2 Peripheral device protection violation access information register IPGECRUM SV R/W —   — Undefined (retained) +008H 4 Peripheral device protection violation access address register IPGADRUM SV R/W —    Undefined (retained) +00DH 1 Peripheral device protection enable register IPGENUM SV R/W —  — — 00 H +020H 1 Peripheral device protection setting register 0 IPGPMTUM0 SV R/W —  — — 00 H +022H 1 Peripheral device protection setting register 2 IPGPMTUM2 SV R/W —  — — 00H +023H 1 Peripheral device protection setting register 3 IPGPMTUM3 SV R/W —  — — 00H +024H 1 Peripheral device protection setting register 4 IPGPMTUM4 SV R/W —  — — 00 H Note 1. Registers for which “SV” is described are accessible by accesses with SV right (UM = 0).

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 664 of 4535 Dec 26, 2018 (4) Register Set (a) IPGECRUM — Peripheral Device Protection Violation Access Information Register Access: IPGECRUM register can be read or written in 16-bit units. IPGECRUML register can be read or written in 8-bit units. Address: IPGECRUM: FFFE E002H IPGECRUML: FFFE E002H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Value after reset 0 0 0 0 0 0 0 0 0 — — — — — — — R/W R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W Table 3BC.64 IPGECRUM Register Contents Bit Position Bit Name Function 15 to 7 Reserved These bits are always read as 0. The write value should always be 0. word, CAXI, LDL or STC. In other cases, this bit is cleared to 0. 5 HW This bit is set to 1 when a violation occurred in read halfword or write haflword. In other cases, this bit is cleared to 0. 4 BY This bit is set to 1 when a violation occurred in read byte, write byte or bit operation. In other cases, this bit is cleared to 0. 3 EX This bit is set to 1 when a violation occurred in an instruction fetch read access. In other cases, this bit is cleared to 0. the CAXI instruction. In other cases, this bit is cleared to 0. 1 RD This bit is set to 1 when a violation occurred in a read access, bit operation, or execution of the CAXI instruction. In other cases, this bit is cleared to 0. with the relevant right. Even if another violation of peripheral device protection is detected while this bit is 1, data of this IPGECRUM register and the IPGADRUM register is not updated and is retained. NOTE When the IRE bit value of the IPGENUM register (described later) is 0 and violation of peripheral device protection by a program operating in user mode is an instruction fetch read access, no bit of this register is updated.

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 665 of 4535 Dec 26, 2018 (b) IPGADRUM — Peripheral Device Protection Violation Access Address Register Access: IPGADRUM register can be read or written in 32-bit units. IPGADRUML, IPGADRUMH registers can be read or written in 16-bit units. IPGADRUMLL, IPGADRUMLH, IPGADRUMHL, IPGADRUMHH registers can be read or written in 8-bit units. Address: IPGADRUM: FFFE E008H IPGADRUML: FFFE E008H, IPGADRUMH: FFFE E00AH IPGADRUMLL: FFFE E008H, IPGADRUMLH: FFFE E009H, IPGADRUMHL: FFFE E00AH, IPGADRUMHH: FFFE E00BH Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EADR[31:16] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EADR[15:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Table 3BC.65 IPGADRUM Register Contents Bit Position Bit Name Function 31 to 0 EADR These bits store the address of the access in which a violation occurred. NOTE When the IRE bit value of the IPGENUM register (described later) is 0 and violation of peripheral device protection by a program operating in user mode is an instruction fetch read access, no bit of this register is updated.

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 666 of 4535 Dec 26, 2018 (c) IPGENUM — Peripheral Device Protection Enable Register Access: IPGENUM register can be read or written in 8-bit units. Address: IPGENUM: FFFE E00DH Bit 7 6 5 4 3 2 1 0 Value after reset 0 0 0 0 0 0 0 0 R/W R R R R R R R/W R/W Table 3BC.66 IPGENUM Register Contents Bit Position Bit Name Function 7 to 2 Reserved These bits are always read as 0. The write value should always be 0. violation access address register and the peripheral device protection violation access information register when a violation of peripheral device protection occurred in an instruction fetch access. 0: Instruction fetch access information is not stored. (value after reset) 1: Instruction fetch access information is stored. CAUTION: If you do not want to detect speculative instruction fetches (no instruction is executed in some cases), clear this bit to 0. relevant access right. 0: The peripheral device protection function is disabled. (Value after reset) 1: The peripheral device protection function is enabled. (d) IPGPMTUM0 — Peripheral Device Protection Setting Register 0 Access: IPGPMTUM0 register can be read or written in 8-bit units. Address: IPGPMTUM0: FFFE E020H Bit 7 6 5 4 3 2 1 0 Value after reset 0 0 0 0 0 0 0 0 R/W R R/W R/W R/W R R R R Table 3BC.67 IPGPMTUM0 Register Contents Bit Position Bit Name Function 7 Reserved These bits are always read as 0. The write value should always be 0. 6 X1 This bit sets whether to enable instruction fetch read access to P-Bus. 0: Instruction fetch read access to P-Bus is treated as violation. (Value after reset) 1: Instruction fetch read access to P-Bus is not restricted. 5 W1 This bit sets whether to enable write access to P-Bus. 0: Write access to P-Bus is treated as violation. (Value after reset) 1: Write access to P-Bus is not restricted. 4 R1 This bit sets whether to enable read access to P-Bus. 0: Read access to P-Bus is treated as violation. (Value after reset) 1: Read access to P-Bus is not restricted. 3 to 0 Reserved These bits are always read as 0. The write value should always be 0.

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 667 of 4535 Dec 26, 2018 (e) IPGPMTUM2 — Peripheral Device Protection Setting Register 2 Access: IPGPMTUM2 register can be read or written in 8-bit units. Address: IPGPMTUM2: FFFE E022H Bit 7 6 5 4 3 2 1 0 Value after reset 0 0 0 0 0 0 0 0 R/W R R R R R R R/W R/W Table 3BC.68 IPGPMTUM2 Register Contents Bit Position Bit Name Function 7 to 2 Reserved These bits are always read as 0. The write value should always be 0. 1 W0 This bit sets whether to enable write access to INTC1. 0: Write access to INTC1 is treated as violation. (Value after reset) 1: Write access to INTC1 is not restricted 0 R0 This bit sets whether to enable read access to INTC1. 0: Read access to INTC1 is treated as violation. (Value after reset) 1: Read access to INTC1 is not restricted. (f) IPGPMTUM3 — Peripheral Device Protection Setting Register 3 Access: IPGPMTUM3 register can be read or written in 8-bit units. Address: IPGPMTUM3: FFFE E023H Bit 7 6 5 4 3 2 1 0 Value after reset 0 0 0 0 0 0 0 0 R/W R R R/W R/W R R R R Table 3BC.69 IPGPMTUM3 Register Contents Bit Position Bit Name Function 7 to 6 Reserved These bits are always read as 0. The write value should always be 0. 5 W1 This bit sets whether to enable write access to SysErrGen. 0: Write access to SysErrGen is treated as violation. (Value after reset) 1: Write access to SysErrGen is not restricted. 4 R1 This bit sets whether to enable read access to SysErrGen. 0: Read access to SysErrGen is treated as violation. (Value after reset) 1: Read access to SysErrGen is not restricted 3 to 0 Reserved These bits are always read as 0. The write value should always be 0.

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 668 of 4535 Dec 26, 2018 (g) IPGPMTUM4 — Peripheral Device Protection Setting Register 4 Access: IPGPMTUM4 register can be read or written in 8-bit units. Address: IPGPMTUM4: FFFE E024H Bit 7 6 5 4 3 2 1 0 Value after reset 0 0 0 0 0 0 0 0 R/W R R R R R R R/W R/W Table 3BC.70 IPGPMTUM4 Register Contents Bit Position Bit Name Function 7 to 2 Reserved These bits are always read as 0. The write value should always be 0. 1 W0 This bit sets whether to enable write access to its own PEG. 0: Write access to its own PEG is treated as violation. (Value after reset) 1: Write access to its own PEG is not restricted. 0 R0 This bit sets whether to enable read access to its own PEG. 0: Read access to its own PEG is treated as violation. (Value after reset) 1: Read access to its own PEG is not restricted

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 669 of 4535 Dec 26, 2018 3BC.2.3.3 System Error Generator Function (SEG) SEG (SysErrGen) controls interrupt notification and recording after a system error occurred by a data access. Multiple error occurrence inputs are categorized according to error factor, and are processed sequentially from the highest-priority error factor, generating an FE-level exception (SYSERR). The bit position of the SEGFLAG register becomes the error factor priority. Error factors of lower bits take precedence over error factors of upper bits. Error address information is recorded only once regardless of error frequency. The error with the highest priority among the error factors is valid when errors occur simultaneously. Recorded error address information is not overwritten by subsequent errors. (1) List of SEG Function Control Registers Table 3BC.71 SEG Register (Base Address: FFFE E980H) Module Name Address Offset Size (Byte) Register Name Abbreviation Right*1 R/W Operable Bit Value after Reset 1 8 16 32 SEG +00H 2 SEG error control register SEGCONT SV R/W — —  — 0000H +02H 2 SEG error flag register SEGFLAG SV R/W — —  — 0000H +08H 4 SEG error address information register SEGADDR SV R/W — — —  Undefined (retained) Note 1. Registers for which “SV” is described are writable with the SV right (UM = 0). Attempting to write, if these conditions do not hold, leads to a SYSERR exception with setting VCIF flag. No restriction is provided for read accesses.

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 670 of 4535 Dec 26, 2018 (2) Register Set (a) SEGCONT — SEG Error Control Register This register is used to enable (= 1) or disable (= 0) notification of SysErr request in response to error flags that store the error occurrence status for each factor. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R R R R R R/W R/W R/W R R/W R R/W R R R R Table 3BC.72 SEGCONT Register Contents Bit Position Bit Name Function 15 to 11 Reserved When read, the value after reset is returned. When writing, write the value after reset.

• Error response from external bus masters in write access
• Illegal response to local RAM or peripherals or Flash from optional master in access (except instruction fetch from CPU). And illegal response to optional slave from external AHB master in access. 9 APIE This bit enables notification of an error response from peripherals. The error notification includes the following cases:
• Error response from peripherals in write access
• PBG error in write access 8 IPGE This bit enables notification of IPG illegal access detection. 7 Reserved When read, the value after reset is returned. When writing, write the value after reset.

6 TCME This bit enables notification of an error during data access to its own local RAM*1 from PE

master. The error notification includes the following cases:

• ECC uncorrectable error (DED or SED & SECDIS=1)
• Detection of an access to RAM unimplemented area 5 Reserved When read, the value after reset is returned. When writing, write the value after reset.

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 671 of 4535 Dec 26, 2018 Table 3BC.72 SEGCONT Register Contents Bit Position Bit Name Function

4 VCIE RH850/F1KM-S4:

This bit enables notification of an error response during access to CPU peripherals, P-Bus (read access), global RAM, retention RAM, H-Bus and CodeFlash by PE. The error notification includes the following cases:

• IPG error from CPU peripherals and P-Bus
• Error response from H-Bus peripherals
• PBG error / HBG error from P-Bus and H-Bus
• GRG error from global RAM and retention RAM
• ECC uncorrectable error from CodeFlash, global RAM and retention RAM (DED or SED & SECDIS = 1) This bit enables notification of an error response when accessing to a part of access prohibited areas in address map. RH850/F1KM-S1: This bit enables notification of an error response during access to CPU peripherals, P-Bus (read access), global RAM and CodeFlash by PE. The error notification includes the following cases:
• IPG error from CPU peripherals and P-Bus
• PBG error from P-Bus
• ECC uncorrectable error from CodeFlash (DED or SED & SECDIS = 1) This bit enables notification of an error response when accessing to a part of access prohibited areas in address map. 3 to 0 Reserved When read, the value after reset is returned. When writing, write the value after reset. Note 1. It is local RAM and retention RAM in RH850/F1KM-S1.

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 672 of 4535 Dec 26, 2018 (b) SEGFLAG — SEG Error Flag Register This register indicates error flags that store error occurrence status of each factors. The flags are set to 1 by an error occurrence input. The flags are not automatically cleared to 0. Both setting and clearing of each flag are supported in writing to the register. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R R R R R R/W R/W R/W R R/W R R/W R R R R Table 3BC.73 SEGFLAG Register Contents Bit Position Bit Name Function 15 to 11 Reserved When read, the value after reset is returned. When writing, write the value after reset. 7 Reserved When read, the value after reset is returned. When writing, write the value after reset. 5 Reserved When read, the value after reset is returned. When writing, write the value after reset. 3 to 0 Reserved When read, the value after reset is returned. When writing, write the value after reset. NOTE An error may lead to setting of multiple error flags in SEG. For example, if an IPG error occurs at peripheral registers read, both IPGF bit and VCIF bit in SEGFLAG are set.

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 673 of 4535 Dec 26, 2018 (c) SEGADDR — Error Address Information Register Address information (one record) which is notified with error occurrence is stored in the register. The register is not updated while one or more bits in SEGFLAG register are set. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address[31:16] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address[15:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Table 3BC.74 SEGADDR Register Contents Bit Position Bit Name Function 31 to 0 Address These bits store the error address information. CAUTIONS 1. SEGADDR stores error address information in case of an error occurrence related to VCIF bit or TCMF bit in SEGFLAG register. SEGADDR register stores all 0 data in case of an error occurrence related to VCSF bit, APIF bit or IPGF bit in SEGFLAG register. 2. In case of an error occurrence related to TCMF bit in SEGFLAG register, bit[18:0] of the error address are stored in SEGADDR[18:0] and SEGADDR[31:19] are filled with 0.

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 674 of 4535 Dec 26, 2018 (3) SEG Function (a) SEG Function: SYSERR Request Notification by Error Flag

• Setting an error flag takes precedence over clearing the same flag. − A simultaneous clearing operation is ignored.
• Priority of error factors − The bit position of each flags in SEGFLAG register which error notification is enabled by SEGCONT register becomes the error factor priority. Error factors of lower bits take precedence over error factors of upper bits. Notification is made from the highest-priority error factor. − The bit position of error factors is reported as a “SysErr factor code.”
• Conditions for starting SysErr request notification − Even if a flag which error notification is disabled by SEGCONT register is set to 1, notification is not made. − Notification is made immediately after a flag which error notification is enabled by SEGCONT register is set to − After clearing of a flag, notification is made if an other flag which error notification is enabled by SEGCONT register remains set.
• Finishing notification at a SysErr acknowledgement − Even after notification is finished, the flag is not cleared automatically. − Notification is not made until setting or clearing the flag again. − If an error flag that is prioritized higher than the error factor is set prior to an acknowledgement, the notification information may be replaced with a higher prioritized SysErr factor code. (b) SEG Function: Recording Error Address Information
• When an error which error notification is enabled by SEGCONT register occurs, the error address is retained in the SEGADDR register. − No information is retained by setting or clearing an error flag in SEGFLAG register. − When multiple error occurrence inputs are present simultaneously, information other than the prioritized error factor is not retained.
• While a flag which error notification is enabled by SEGCONT register is set to 1, overwrite to the SEGADDR register is inhibited. − If error occurrence input continues, information of subsequent error factors is not retained. − To reset the inhibition of overwrite to the register, clear either SEGCONT or SEGFLAG register (or both of them). (c) Supplementary Notes on SYSERR Exception
• Even when a SYSERR exception occurs, the value of the PSW.EBV bit is held, and the base address of the exception handler does not switch.

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 675 of 4535 Dec 26, 2018 3BC.3 Notes 3BC.3.1 Synchronization of Store Instruction Completion and Subsequent Instruction Execution When a control register is updated by a store instruction, there is a time lag after the CPU executes the store instruction and before the control register is actually updated. Therefore, if the updated content of the control register is to be used by the instruction following the store instruction, the appropriate synchronization is required. How to perform synchronization processing is shown below. For the procedures to synchronize updating system registers by LDSR instruction and the subsequent instruction execution, see APPENDIX A, Hazard Resolution Procedure for System Registers in the RH850G3KH User’s Manual: Software. When the updated results in the control registers are to be used by the subsequent instruction: Example 1: An interrupt is enabled by execution of an EI instruction after an interrupt request is cleared by access from the control register in the INTC2 and the peripheral circuits. Proceed as follows in this case. (1) Execute the store instruction to update a control register (ST.W, etc.). (2) Perform a dummy read of the above control register (LD.W, etc.). (3) Execute SYNCP. (4) Execute the subsequent instruction (EI). In case of RH850/F1KM, SYNCM instruction has the same effects as above-mentioned (2) and (3). (Excludes RCFDCn, RCFDCn ECC register access.) Example 2: When you must wait until a control register (control register A) has been completely updated before accessing another control register (control register B), execute similar processing. For example, different peripheral functions are linked, or the interrupt mask for INTC is cleared after the peripheral function is set. Note that this processing is not required if the control registers A and B belong to the same peripheral group. (1) Execute the store instruction to update the control register A (ST.W, etc.). (2) Perform a dummy read of the above control register (LD.W, etc.). (3) Execute SYNCP. (4) Execute the store instruction to access the control register B (ST.W, LD.W, etc.). In case of RH850/F1KM, SYNCM instruction has the same effects as above-mentioned (2) and (3). (Excludes RCFDCn, RCFDCn ECC register access.) The similar processing is also required when starting to access a memory or control register to be protected is started after a safety function (such as some kind of memory protection and ECC) has been completely set up.

RH850/F1KH, RH850/F1KM Section 3BC CPU System of RH850/F1KM R01UH0684EJ0110 Rev.1.10 Page 676 of 4535 Dec 26, 2018 When the updated results of the control register or memory to be used in the instruction fetch of the subsequent instruction: (a) In case of writing the instructions to the RAM before jumping to the RAM to execute instructions from the RAM, take the following procedure. (1) Execute the store instruction to update a memory (ST.W, etc.). (2) Perform a dummy read of the above memory (LD.W, etc.). (3) Execute SYNCP. (4) Execute SYNCI. (5) Execute the subsequent instruction (branch instruction, etc.). (b) In case of updating control registers for memory protection and ECC functions before jumping to the memory to be controlled by the registers, take the following procedure. (1) Execute the store instruction to update a control register (ST.W, etc.). (2) Perform a dummy read of the control register (LD.W, etc.). (3) Execute SYNCP. (4) Execute SYNCI. (5) Execute the subsequent instruction (branch instruction, etc.). When switching the code flash memory area: In this case, see Section 10, Usage Notes, (7) Updating the BFASELR register in the RH850/F1KH, F1KM, F1K Flash Memory User’s Manual: Hardware Interface. 3BC.3.2 Ensure Coherency after Rewriting the Code Flash The CPU1 is equipped with the buffer for the code flash area as described in Section 3BC.2.2, Buffers for Code Flash. Therefore, clear the buffer to ensure coherency after rewriting the code flash by self-programming. 3BC.3.3 Access to Registers by Using Bit-Manipulation Instructions Writing bit-manipulation instructions consists of read-modify-write processing in 8-bit units. Thus, access by a bit- manipulation instruction is only possible for registers for which reading and writing in 8-bit units is possible. If a register includes multiple flag bits, the read-modify-write operation may lead to the clearing of flags that were not actually targets for clearing. 3BC.3.4 Caution of Prefetching There is a possibility that the reading of the memory occurs by pre-fetch from the area where instruction codes do not exist. Secure more than 40-byte initialized area after the area where instruction codes are stored. 3BC.3.5 Overwriting Context upon Acceptance of Multiple Exceptions Acceptance of an exception depends on the type of exception source, regardless of the states of the ID and NP bits in the PSW register. When multiple exceptions are generated, the contents of the system register which hold the context information are overwritten. For the conditions for acceptance and whether correct return or recovery is possible for each exception source, see the List of Exception Sources in the RH850G3KH User’s Manual: Software.

RH850/F1KH, RH850/F1KM Section 4A Address Space of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 677 of 4535 Dec 26, 2018 Section 4A Address Space of RH850/F1KH-D8 4A.1 Address Space Table 4A.1, Address Space (8-MB 176/233/324-Pin Product) to Table 4A.2, Address Space (6-MB 176/233/324-Pin Product) show the address space of the RH850/F1KH. CAUTION Do not access an address with which no register is mapped in the on-chip I/O register space. In addition, do not access any access prohibited area specified in Table 4A.1, Address Space (8-MB 176/233/324-Pin Product) to Table 4A.2, Address Space (6-MB 176/233/324-Pin Product). If such an address is accessed, operation is not guaranteed. NOTE The Local RAM is accessible through the following three address areas in the address space. CPU1 area: Address area accessible from CPU1, CPU2, DMA, FlexRay and ETNB. CPU2 area: Address area accessible from CPU1, CPU2, DMA, FlexRay and ETNB. Self area: Mirrored address area, accessible only from CPU (CPU1, CPU2) to refer the CPU’s self resource. Table 4A.1 Address Space (8-MB 176/233/324-Pin Product) Address Address Space Type Size 0000 0000H to 003F FFFFH Code Flash (bank A) 4 MB 0040 0000H to 007F FFFFH Access prohibited area 0080 0000H to 00BF FFFFH Code Flash (bank B) 4 MB 00C0 0000H to 00FF FFFFH Access prohibited area 0100 0000H to 0100 7FFFH Code Flash (Extended user area) 32 KB 0100 8000H to 1001 FFFFH Access prohibited area 1002 0000H to 1002 1FFFH FlexRay Interface (FLXA) 8 KB 1002 2000H to 1002 FFFFH Access prohibited area 1003 0000H to 1003 03FFH External Memory Access Controller (MEMC) 1 KB 1003 0400H to 1003 FFFFH Access prohibited area 1004 0000H to 1004 0FFFH Serial Flash Memory Interface (SFMA) 4 KB 1004 1000H to 1FFF FFFFH Access prohibited area 2000 0000H to 20FF FFFFH External Memory Area(CS0) 16 MB*4 2100 0000H to 21FF FFFFH Access prohibited area 2200 0000H to 22FF FFFFH External Memory Area(CS1) 16 MB*4 2300 0000H to 23FF FFFFH Access prohibited area 2400 0000H to 24FF FFFFH External Memory Area(CS2) 16 MB*4 2500 0000H to 27FF FFFFH Access prohibited area 2800 0000H to 28FF FFFFH External Memory Area(CS3) 16 MB*4 2900 0000H to 2FFF FFFFH Access prohibited area 3000 0000H to 33FF FFFFH External Serial Flash Memory Area 64 MB 3400 0000H to FE9C FFFFH Access prohibited area FE9D 0000H to FE9F FFFFH Local RAM (CPU2 area) 192 KB*1 FEA0 0000H to FEBC FFFFH Access prohibited area FEBD 0000H to FEBF FFFFH Local RAM (CPU1 area) 192 KB*1

RH850/F1KH, RH850/F1KM Section 4A Address Space of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 678 of 4535 Dec 26, 2018 Table 4A.1 Address Space (8-MB 176/233/324-Pin Product) Address Address Space Type Size FEC0 0000H to FEDC FFFFH Access prohibited area FEDD 0000H to FEDF FFFFH Local RAM (self area) 192 KB*1 FEE0 0000H to FEEB 7FFFH Access prohibited area FEEB 8000H to FEEF FFFFH Global RAM A 288 KB*2 FEF0 0000H to FEF0 FFFFH Retention RAM 64 KB FEF1 0000H to FEFB 7FFFH Access prohibited area FEFB 8000H to FEFF FFFFH Global RAM B 288 KB*2 FF00 0000H to FF1F FFFFH Access prohibited area FF20 0000H to FF23 FFFFH Data flash 256 KB*3 FF24 0000H to FF9F FFFFH Access prohibited area FFA0 0000H to FFFD FFFFH On-chip peripheral I/O area 6 MB - 128 KB FFFE 0000H to FFFE DFFFH Access prohibited area FFFE E000H to FFFE FFFFH On-chip peripheral I/O area (self area) 8 KB FFFF 0000H to FFFF 4FFFH Access prohibited area FFFF 5000H to FFFF FFFFH On-chip peripheral I/O area 44 KB Note 1. 160 KB in products of CPU frequency 160 MHz max.: For detail, see Section 45, RAM. Note 2. 256 KB in products of CPU frequency 160 MHz max.: For detail, see Section 45, RAM. Note 3. 96 KB in products of CPU frequency 160 MHz max.: For detail, see Section 44, Flash Memory. Note 4. 8 MB in 176/233-pin products: For details, see Section 16, External Memory Access Controller (MEMC).

RH850/F1KH, RH850/F1KM Section 4A Address Space of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 679 of 4535 Dec 26, 2018 Table 4A.2 Address Space (6-MB 176/233/324-Pin Product) Address Address Space Type Size 0000 0000H to 002F FFFFH Code Flash (bank A) 3 MB 0030 0000H to 007F FFFFH Access prohibited area 0080 0000H to 00AF FFFFH Code Flash (bank B) 3 MB 00B0 0000H to 00FF FFFFH Access prohibited area 0100 0000H to 0100 7FFFH Code Flash (Extended user area) 32 KB 0100 8000H to 1001 FFFFH Access prohibited area 1002 0000H to 1002 1FFFH FlexRay Interface (FLXA) 8 KB 1002 2000H to 1002 FFFFH Access prohibited area 1003 0000H to 1003 03FFH External Memory Access Controller (MEMC) 1 KB 1003 0400H to 1003 FFFFH Access prohibited area 1004 0000H to 1004 0FFFH Serial Flash Memory Interface (SFMA) 4 KB 1004 1000H to 1FFF FFFFH Access prohibited area 2000 0000H to 20FF FFFFH External Memory Area (CS0) 16 MB*4 2100 0000H to 21FF FFFFH Access prohibited area 2200 0000H to 22FF FFFFH External Memory Area (CS1) 16 MB*4 2300 0000H to 23FF FFFFH Access prohibited area 2400 0000H to 24FF FFFFH External Memory Area (CS2) 16 MB*4 2500 0000H to 27FF FFFFH Access prohibited area 2800 0000H to 28FF FFFFH External Memory Area (CS3) 16 MB*4 2900 0000H to 2FFF FFFFH Access prohibited area 3000 0000H to 33FF FFFFH External Serial Flash Memory Area 64 MB 3400 0000H to FE9D 7FFFH Access prohibited area FE9D 8000H to FE9F FFFFH Local RAM (CPU2 area) 160 KB*1 FEA0 0000H to FEBD 7FFFH Access prohibited area FEBD 8000H to FEBF FFFFH Local RAM (CPU1 area) 160 KB*1 FEC0 0000H to FEDD 7FFFH Access prohibited area FEDD 8000H to FEDF FFFFH Local RAM (self area) 160 KB*1 FEE0 0000H to FEEB FFFFH Access prohibited area FEEC 0000H to FEEF FFFFH Global RAM A 256 KB*2 FEF0 0000H to FEF0 FFFFH Retention RAM 64 KB FEF1 0000H to FEFB FFFFH Access prohibited area FEFC 0000H to FEFF FFFFH Global RAM B 256 KB*2 FF00 0000H to FF1F FFFFH Access prohibited area FF20 0000H to FF23 FFFFH Data flash 256 KB*3 FF24 0000H to FF9F FFFFH Access prohibited area FFA0 0000H to FFFD FFFFH On-chip peripheral I/O area 6 MB - 128 KB FFFE 0000H to FFFE DFFFH Access prohibited area FFFE E000H to FFFE FFFFH On-chip peripheral I/O area (self area) 8 KB FFFF 0000H to FFFF 4FFFH Access prohibited area FFFF 5000H to FFFF FFFFH On-chip peripheral I/O area 44 KB Note 1. 160 KB in products of CPU frequency 160 MHz max.: For detail, see Section 45, RAM. Note 2. 48 KB in products of CPU frequency 160 MHz max.: For detail, see Section 45, RAM. Note 3. 96 KB in products of CPU frequency 160 MHz max.: For detail, see Section 44, Flash Memory. Note 4. 8 MB in 176/233-pin products: For details, see Section 16, External Memory Access Controller (MEMC).

RH850/F1KH, RH850/F1KM Section 4A Address Space of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 680 of 4535 Dec 26, 2018 4A.2 Address Space Viewed from Each Bus Master Table 4A.3, Address Space Viewed from Each Bus Master (8-MB Product) shows address spaces viewed from each bus master. 4A.2.1 Space in which Instructions can be Fetched Instructions of the CPU can be fetched from the Code flash, local RAM, global RAM, and retention RAM. 4A.2.2 Data Space Accessible by CPU1 See Table 4A.3, Address Space Viewed from Each Bus Master (8-MB Product) for the spaces accessible from the CPU1. 4A.2.3 Data Space Accessible by CPU2 See Table 4A.3, Address Space Viewed from Each Bus Master (8-MB Product) for the spaces accessible from the CPU2. 4A.2.4 Data Space Accessible by DMA See Table 4A.3, Address Space Viewed from Each Bus Master (8-MB Product) for the spaces accessible from the DMA. 4A.2.5 Data Space Accessible by Flexray See Table 4A.3, Address Space Viewed from Each Bus Master (8-MB Product) for the spaces accessible from the Flexray. 4A.2.6 Data Space Accessible by ETNB See Table 4A.3, Address Space Viewed from Each Bus Master (8-MB Product) for the spaces accessible from the ETNB.

RH850/F1KH, RH850/F1KM Section 4A Address Space of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 681 of 4535 Dec 26, 2018 4A.2.7 Data Space Accessible by Each Bus Master See Table 4A.3, Address Space Viewed from Each Bus Master (8-MB Product) for the spaces accessible from Each Bus Master. Table 4A.3 Address Space Viewed from Each Bus Master (8-MB Product) Address Resource From CPU1 From CPU2 From DMA From FlexRay From ETNB 0000 0000H to 003F FFFFH Code Flash (bank A)    0040 0000H to 007F FFFFH Access prohibited area 0080 0000H to 00BF FFFFH Code Flash (bank B)    00C0 0000H to 00FF FFFFH Access prohibited area 0100 0000H to 0100 7FFFH Code Flash (Extended user area)    0100 8000H to 1001 FFFFH Access prohibited area 1002 0000H to 1002 1FFFH FlexRay Interface (FLXA)    1002 2000H to 1002 FFFFH Access prohibited area 1003 0000H to 1003 03FFH External Memory Access Controller (MEMC)    1003 0400H to 1003 FFFFH Access prohibited area 1004 0000H to 1004 0FFFH Serial Flash Memory Interface (SFMA)    1004 1000H to 1FFF FFFFH Access prohibited area 2000 0000H to 20FF FFFFH External Memory Area (CS0)    2100 0000H to 21FF FFFFH Access prohibited area 2200 0000H to 22FF FFFFH External Memory Area (CS1)    2300 0000H to 23FF FFFFH Access prohibited area 2400 0000H to 24FF FFFFH External Memory Area (CS2)    2500 0000H to 27FF FFFFH Access prohibited area 2800 0000H to 28FF FFFFH External Memory Area (CS3)    2900 0000H to 2FFF FFFFH Access prohibited area 3000 0000H to 33FF FFFFH External Serial Flash Memory Area    3400 0000H to FE9C FFFFH Access prohibited area FE9D 0000H to FE9F FFFFH Local RAM (CPU2 area)      FEA0 0000H to FEBC FFFFH Access prohibited area FEBD 0000H to FEBF FFFFH Local RAM (CPU1 area)      FEC0 0000H to FEDC FFFFH Access prohibited area FEDD 0000H to FEDF FFFFH Local RAM (self area)   FEE0 0000H to FEEB 7FFFH Access prohibited area FEEB 8000H to FEEF FFFFH Global RAM A      FEF0 0000H to FEF0 FFFFH Retention RAM      FEF1 0000H to FEFB 7FFFH Access prohibited area FEFB 8000H to FEFF FFFFH Global RAM B      FF00 0000H to FF1F FFFFH Access prohibited area FF20 0000H to FF23 FFFFH Data flash    FF24 0000H to FF9F FFFFH Access prohibited area FFA0 0000H to FFFD FFFFH On-chip peripheral I/O area    FFFE 0000H to FFFE DFFFH Access prohibited area FFFE E000H to FFFE FFFFH On-chip peripheral I/O area (self area)   FFFF 0000H to FFFF 4FFFH Access prohibited area FFFF 5000H to FFFF FFFFH On-chip peripheral I/O area   

RH850/F1KH, RH850/F1KM Section 4A Address Space of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 682 of 4535 Dec 26, 2018 Note: The following color coding is used in the map above. Fetch and data access available Data access available Access prohibited

RH850/F1KH, RH850/F1KM Section 4A Address Space of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 683 of 4535 Dec 26, 2018 4A.3 Peripheral I/O Address Map Table 4A.4, Peripheral I/O Address Map shows peripheral I/O address map. Table 4A.4 Peripheral I/O Address Map Address Peripheral Group Peripheral I/O FF00 0000H to FF1F FFFFH — Access prohibited area FF20 0000H to FF23 FFFFH 4 Data Flash FF24 0000H to FF9F FFFFH — Access prohibited area FFA0 0000H to FFA0 001FH 1 FLMD FFA0 0020H to FFA0 0FFFH — Access prohibited area FFA0 1000H to FFA0 103FH — Access prohibited area FFA0 1040H to FFA0 1FFFH — Access prohibited area FFA0 2000H to FFA0 201FH — Access prohibited area FFA0 2020H to FFA0 7FFFH — Access prohibited area FFA0 8000H to FFA0 801FH — Access prohibited area FFA0 8020H to FFA0 FFFFH — Access prohibited area FFA1 0000H to FFA1 1FFFH 1 FPSYS (Register) FFA1 2000H to FFA1 FFFFH — Access prohibited area FFA2 0000H to FFA2 FFFFH 1 FACI command-issuing area FFA3 0000H to FFBF FFFFH — Access prohibited area FFC0 0000H to FFC0 000FH 1 FENMI (ECON_NMI) FFC0 0010H to FFC0 00FFH — Access prohibited area FFC0 0100H to FFC0 010FH 1 FEINT (ECON_FEINT) FFC0 0110H to FFC0 0FFFH — Access prohibited area FFC0 1000H to FFC0 1003H 1 SELB_INTC (SL_INTC) FFC0 1004H to FFC0 1FFFH — Access prohibited area FFC0 2000H to FFC0 200FH 1 SELB_DMAC (SL_DMAC) FFC0 2010H to FFC0 2FFFH — Access prohibited area FFC0 3000H to FFC0 300FH 1 GRZF FFC0 3010H to FFC0 FFFFH — Access prohibited area FFC1 0000H to FFC1 FFFFH 1 PORTn FFC2 0000H to FFC2 FFFFH 1 PORT (JTAG) FFC3 0000H to FFC3 000FH 1 DNFA_TAUD0 (DNF) FFC3 0010H to FFC3 001FH — Access prohibited area FFC3 0020H to FFC3 002FH 1 DNFA_TAUB0 (DNF) FFC3 0030H to FFC3 003FH — Access prohibited area FFC3 0040H to FFC3 004FH 1 DNFA_TAUB1 (DNF) FFC3 0050H to FFC3 005FH — Access prohibited area FFC3 0060H to FFC3 006FH 1 DNFA_ENCA0 (DNF) FFC3 0070H to FFC3 009FH — Access prohibited area FFC3 00A0H to FFC3 00AFH 1 DNFA_ADCA0 (DNF) FFC3 00B0H to FFC3 00BFH — Access prohibited area FFC3 00C0H to FFC3 00CFH 1 DNFA_ADCA1 (DNF) FFC3 00D0H to FFC3 00DFH — Access prohibited area FFC3 00E0H to FFC3 00EFH 1 DNFA_SENT (DNF) FFC3 00F0H to FFC3 00FFH — Access prohibited area

RH850/F1KH, RH850/F1KM Section 4A Address Space of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 684 of 4535 Dec 26, 2018 Table 4A.4 Peripheral I/O Address Map Address Peripheral Group Peripheral I/O FFC3 0100H to FFC3 010FH — Access prohibited area FFC3 0110H to FFC3 3FFFH — Access prohibited area FFC3 4000H to FFC3 401FH 1 FCLA_NMI (FCLA0) FFC3 4020H to FFC3 403FH 1 FCLA_INTPL (FCLA0) FFC3 4040H to FFC3 405FH 1 FCLA_INTPH (FCLA0) FFC3 4060H to FFC3 407FH 1 FCLA_ADCA0 (FCLA0) FFC3 4080H to FFC3 409FH 1 FCLA_ADCA1 (FCLA0) FFC3 40A0H to FFC3 40BFH 1 FCLA_INTPU (FCLA0) FFC3 40C0H to FFC3 FFFFH — Access prohibited area FFC4 0000H to FFC4 004FH 1 P-Bus guard (PBG10) FFC4 0050H to FFC4 00FFH — Access prohibited area FFC4 0100H to FFC4 014FH 1 P-Bus guard (PBG11) FFC4 0150H to FFC4 03FFH — Access prohibited area FFC4 0400H to FFC4 044FH 1 P-Bus guard (PBG12) FFC4 0450H to FFC4 04FFH — Access prohibited area FFC4 0500H to FFC4 054FH 1 P-Bus guard (PBG13) FFC4 0550H to FFC4 05FFH — Access prohibited area FFC4 0600H to FFC4 064FH 1 P-Bus guard (PBG14) FFC4 0650H to FFC4 8FFFH — Access prohibited area FFC4 9000H to FFC4 907FH 2 Global RAM Guard Bank A (MGDGR) FFC4 9080H to FFC4 91FFH — Access prohibited area FFC4 9200H to FFC4 927FH 2 Global RAM Guard Bank B (MGDGR) FFC4 9280H to FFC4 BFFFH — Access prohibited area FFC4 C000H to FFC4 C00FH 2 P-Bus guard (PBGC0) FFC4 C010H to FFC4 C10FH — Access prohibited area FFC4 C110H to FFC4 C13FH 2 P-Bus guard (PBGC1) FFC4 C140H to FFC4 C7FFH — Access prohibited area FFC4 C800H to FFC4 C80FH 2 ERRSLV (PBGC0) FFC4 C810H to FFC4 C8FFH — Access prohibited area FFC4 C900H to FFC4 C90FH 2 ERRSLV (PBGC1) FFC4 C910H to FFC5 7FFFH — Access prohibited area FFC5 8000H to FFC5 803FH 2 BOOTCTRL FFC5 8040H to FFC5 97FFH — Access prohibited area FFC5 9800H to FFC5 981FH 4 EEPRDCYCL (DCIB) FFC5 9820H to FFC5 9BFFH — Access prohibited area FFC5 9C00H to FFC5 9C4FH 4 P-Bus guard (PBG40) FFC5 9C50H to FFC5 AFFFH — Access prohibited area FFC5 B000H to FFC5 B003H 2 FBUFCCTL (FBUF_CTRL) FFC5 B004H to FFC6 21FFH — Access prohibited area FFC6 2200H to FFC6 23FFH 2 Code Flash ECC (CFECC_VCI) FFC6 2400H to FFC6 25FFH 2 Code Flash ECC (CFECC_CPU1) FFC6 2600H to FFC6 29FFH — Access prohibited area FFC6 2A00H to FFC6 2A3FH 4 Data Flash ECC (DFECC) FFC6 2A40H to FFC6 3FFFH — Access prohibited area

RH850/F1KH, RH850/F1KM Section 4A Address Space of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 685 of 4535 Dec 26, 2018 Table 4A.4 Peripheral I/O Address Map Address Peripheral Group Peripheral I/O FFC6 4000H to FFC6 403FH 2 Global RAM ECC Bank A (GRECC) FFC6 4040H to FFC6 41FFH — Access prohibited area FFC6 4200H to FFC6 423FH 2 Global RAM ECC Bank B (GRECC) FFC6 4240H to FFC6 4FFFH — Access prohibited area FFC6 5000H to FFC6 501FH 2 Local RAM ECC TEST PE1 (LRTST) FFC6 5020H to FFC6 53FFH — Access prohibited area FFC6 5400H to FFC6 547FH 2 Local RAM ECC PE1 (LRECC) FFC6 5480H to FFC6 55FFH — Access prohibited area FFC6 5600H to FFC6 567FH 2 Local RAM ECC PE2 (LRECC) FFC6 5680H to FFC7 00FFH — Access prohibited area FFC7 0100H to FFC7 011FH 3 ECCCSIH0 FFC7 0120H to FFC7 01FFH — Access prohibited area FFC7 0200H to FFC7 021FH 3 ECCCSIH1 FFC7 0220H to FFC7 02FFH — Access prohibited area FFC7 0300H to FFC7 031FH 3 ECCCSIH2 FFC7 0320H to FFC7 03FFH — Access prohibited area FFC7 0400H to FFC7 041FH 3 ECCCSIH3 FFC7 0420H to FFC7 04FFH — Access prohibited area FFC7 0500H to FFC7 051FH 3 ECCCSIH4 FFC7 0520H to FFC7 12FFH — Access prohibited area FFC7 1300H to FFC7 131FH 5 ECCCFD0MB FFC7 1320H to FFC7 13FFH — Access prohibited area FFC7 1400H to FFC7 141FH 5 ECCCFD0AFL0 FFC7 1420H to FFC7 14FFH — Access prohibited area FFC7 1500H to FFC7 151FH 5 ECCCFD0AFL1 FFC7 1520H to FFC7 17FFH — Access prohibited area FFC7 1800H to FFC7 184FH 5 P-Bus guard (PBG60) FFC7 1850H to FFC7 18FFH — Access prohibited area FFC7 1900H to FFC7 194FH 5 P-Bus guard (PBG61) FFC7 1950H to FFC7 19FFH — Access prohibited area FFC7 1A00H to FFC7 1A1FH 5 ECCCFD1MB FFC7 1A20H to FFC7 1AFFH — Access prohibited area FFC7 1B00H to FFC7 1B1FH 5 ECCCFD1AFL0 FFC7 1B20H to FFC7 1BFFH — Access prohibited area FFC7 1C00H to FFC7 1C1FH 5 ECCCFD1AFL1 FFC7 1C20H to FFC7 30FFH — Access prohibited area FFC7 3100H to FFC7 311FH 3 ECCFLXA0 FFC7 3120H to FFC7 31FFH — Access prohibited area FFC7 3200H to FFC7 321FH 3 ECCFLXA0T0 FFC7 3220H to FFC7 32FFH — Access prohibited area FFC7 3300H to FFC7 331FH 3 ECCFLXA0T1 FFC7 3320H to FFC7 40FFH — Access prohibited area FFC7 4100H to FFC7 411FH 3 ECCETNB0TX FFC7 4120H to FFC7 41FFH — Access prohibited area

RH850/F1KH, RH850/F1KM Section 4A Address Space of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 686 of 4535 Dec 26, 2018 Table 4A.4 Peripheral I/O Address Map Address Peripheral Group Peripheral I/O FFC7 4200H to FFC7 421FH 3 ECCETNB0RX FFC7 4220H to FFC7 42FFH — Access prohibited area FFC7 4300H to FFC7 431FH 3 ECCETNB1TX FFC7 4320H to FFC7 43FFH — Access prohibited area FFC7 4400H to FFC7 441FH 3 ECCETNB1RX FFC7 4420H to FFC7 7FFFH — Access prohibited area FFC7 8000H to FFC7 8003H 1 SELB READ TEST (SL_READTEST) FFC7 8004H to FFC9 FFFFH — Access prohibited area FFCA 0000H to FFCA 007FH 1 RIIC0 FFCA 0080H to FFCA 00FFH 1 RIIC1 FFCA 0100H to FFCC FFFFH — Access prohibited area FFCD 0000H to FFCD 01FFH 1 PRDNAME/CHIPID (SCDS) FFCD 0200H to FFCD FFFFH — Access prohibited area FFCE 0000H to FFCE 007FH 1 RLN240 FFCE 0080H to FFCE 00FFH 1 RLN241 FFCE 0100H to FFCE 017FH 1 RLN242 FFCE 0180H to FFCE 01FFH 1 RLN243 FFCE 0200H to FFCE 1FFFH — Access prohibited area FFCE 2000H to FFCE 203FH 1 RLN30 FFCE 2040H to FFCE 207FH 1 RLN31 FFCE 2080H to FFCE 20BFH 1 RLN32 FFCE 20C0H to FFCE 20FFH 1 RLN33 FFCE 2100H to FFCE 213FH 1 RLN34 FFCE 2140H to FFCE 217FH 1 RLN35 FFCE 2180H to FFCE 21BFH 1 RLN36 FFCE 21C0H to FFCE 21FFH 1 RLN37 FFCE 2200H to FFCE FFFFH — Access prohibited area FFCF 0000H to FFCF 007FH 1 RSENT0 FFCF 0080H to FFCF 00FFH — Access prohibited area FFCF 0100H to FFCF 017FH 1 RSENT1 FFCF 0180H to FFCF FFFFH — Access prohibited area FFD0 0000H to FFD1 FFFFH 5 RCFDC0 FFD2 0000H to FFD3 FFFFH 5 RCFDC1 FFD4 0000H to FFD6 CFFFH — Access prohibited area FFD6 D000H to FFD6 D7FFH 3 ADCA1 FFD6 D800H to FFD6 DFFFH — Access prohibited area FFD6 E000H to FFD6 E7FFH 3 ETNB0 FFD6 E800H to FFD6 EFFFH 3 ETNB1 FFD6 F000H to FFD6 FFFFH — Access prohibited area FFD7 0000H to FFD7 003FH 3 OSTM0 FFD7 0040H to FFD7 00FFH — Access prohibited area FFD7 0100H to FFD7 013FH 3 OSTM1 FFD7 0140H to FFD7 01FFH — Access prohibited area FFD7 0200H to FFD7 023FH 3 OSTM2 FFD7 0240H to FFD7 02FFH — Access prohibited area

RH850/F1KH, RH850/F1KM Section 4A Address Space of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 687 of 4535 Dec 26, 2018 Table 4A.4 Peripheral I/O Address Map Address Peripheral Group Peripheral I/O FFD7 0300H to FFD7 033FH 3 OSTM3 FFD7 0340H to FFD7 03FFH — Access prohibited area FFD7 0400H to FFD7 043FH 3 OSTM4 FFD7 0440H to FFD7 0FFFH — Access prohibited area FFD7 1000H to FFD7 103FH 3 OSTM5 FFD7 1040H to FFD7 10FFH — Access prohibited area FFD7 1100H to FFD7 113FH 3 OSTM6 FFD7 1140H to FFD7 11FFH — Access prohibited area FFD7 1200H to FFD7 123FH 3 OSTM7 FFD7 1240H to FFD7 12FFH — Access prohibited area FFD7 1300H to FFD7 133FH 3 OSTM8 FFD7 1340H to FFD7 13FFH — Access prohibited area FFD7 1400H to FFD7 143FH 3 OSTM9 FFD7 1440H to FFD7 FFFFH — Access prohibited area FFD8 0000H to FFD8 001FH 3 CSIH0 (CSIH0CTL0-2, CSIH0STR0, CSIH0STCR0, CSIH0EMU) FFD8 0020H to FFD8 0FFFH — Access prohibited area FFD8 1000H to FFD8 107FH 3 CSIH0 (CSIH0 registers other than above) FFD8 1080H to FFD8 1FFFH — Access prohibited area FFD8 2000H to FFD8 201FH 3 CSIH1 (CSIH1CTL0-2, CSIH1STR0, CSIH1STCR0, CSIH1EMU) FFD8 2020H to FFD8 2FFFH — Access prohibited area FFD8 3000H to FFD8 307FH 3 CSIH1 (CSIH1 registers other than above) FFD8 3080H to FFD8 3FFFH — Access prohibited area FFD8 4000H to FFD8 401FH 3 CSIH2 (CSIH2CTL0-2, CSIH2STR0, CSIH2STCR0, CSIH2EMU) FFD8 4020H to FFD8 4FFFH — Access prohibited area FFD8 5000H to FFD8 507FH 3 CSIH2 (CSIH2 registers other than above) FFD8 5080H to FFD8 5FFFH — Access prohibited area FFD8 6000H to FFD8 601FH 3 CSIH3 (CSIH3CTL0-2, CSIH3STR0, CSIH3STCR0, CSIH3EMU) FFD8 6020H to FFD8 6FFFH — Access prohibited area FFD8 7000H to FFD8 707FH 3 CSIH3 (CSIH3 registers other than above) FFD8 7080H to FFD8 7FFFH — Access prohibited area FFD8 8000H to FFD8 801FH 3 CSIG0 (CSIG0CTL0-2, CSIG0STR0, CSIG0STCR0, CSIG0EMU) FFD8 8020H to FFD8 8FFFH — Access prohibited area FFD8 9000H to FFD8 901FH 3 CSIG0 (CSIG0 registers other than above) FFD8 9020H to FFD8 9FFFH — Access prohibited area FFD8 A000H to FFD8 A01FH 3 CSIG1 (CSIG1CTL0-2, CSIG1STR0, CSIG1STCR0, CSIG1EMU) FFD8 A020H to FFD8 AFFFH — Access prohibited area FFD8 B000H to FFD8 B01FH 3 CSIG1 (CSIG1 registers other than above) FFD8 B020H to FFD8 BFFFH — Access prohibited area FFD8 C000H to FFD8 C01FH 3 CSIG2 (CSIG2CTL0-2, CSIG2STR0, CSIG2STCR0, CSIG2EMU) FFD8 C020H to FFD8 CFFFH — Access prohibited area FFD8 D000H to FFD8 D01FH 3 CSIG2 (CSIG2 registers other than above) FFD8 D020H to FFD8 DFFFH — Access prohibited area FFD8 E000H to FFD8 E01FH 3 CSIG3 (CSIG3CTL0-2, CSIG3STR0, CSIG3STCR0, CSIG3EMU) FFD8 E020H to FFD8 EFFFH — Access prohibited area FFD8 F000H to FFD8 F01FH 3 CSIG3 (CSIG3 registers other than above)

RH850/F1KH, RH850/F1KM Section 4A Address Space of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 688 of 4535 Dec 26, 2018 Table 4A.4 Peripheral I/O Address Map Address Peripheral Group Peripheral I/O FFD8 F020H to FFD8 FFFFH — Access prohibited area FFD9 0000H to FFD9 001FH 3 CSIH4 (CSIH4CTL0-2, CSIH4STR0, CSIH4STCR0, CSIH4EMU) FFD9 0020H to FFD9 0FFFH — Access prohibited area FFD9 1000H to FFD9 107FH 3 CSIH4 (CSIH4 registers other than above) FFD9 1080H to FFD9 1FFFH — Access prohibited area FFD9 2000H to FFD9 201FH 3 CSIG4 (CSIG4CTL0-2, CSIG4STR0, CSIG4STCR0, CSIG4EMU) FFD9 2020H to FFD9 2FFFH — Access prohibited area FFD9 3000H to FFD9 301FH 3 CSIG4 (CSIG4 registers other than above) FFD9 3020H to FFDC FFFFH — Access prohibited area FFDD 0000H to FFDD 00FFH 2 PIC0 FFDD 0100H to FFDD CFFFH — Access prohibited area FFDD D000H to FFDD D04FH 2 P-Bus guard (PBG20) FFDD D050H to FFDD D0FFH — Access prohibited area FFDD D100H to FFDD D14FH 2 P-Bus guard (PBG21) FFDD D150H to FFE1 FFFFH — Access prohibited area FFE2 0000H to FFE2 03FFH 2 TAUD0 FFE2 0400H to FFE2 3FFFH — Access prohibited area FFE2 4000H to FFE2 4003H 2 SELB_TAUD0 (SL_TAUD0) FFE2 4004H to FFE2 FFFFH — Access prohibited area FFE3 0000H to FFE3 03FFH 2 TAUB0 FFE3 0400H to FFE3 0FFFH — Access prohibited area FFE3 1000H to FFE3 13FFH 2 TAUB1 FFE3 1400H to FFE3 1FFFH — Access prohibited area FFE3 2000H to FFE3 2003H 2 SELB_TAUB0 (SL_TAUB0) FFE3 2004H to FFE3 2FFFH — Access prohibited area FFE3 3000H to FFE3 3003H 2 SELB_TAUB1 (SL_TAUB1) FFE3 3004H to FFE4 FFFFH — Access prohibited area FFE5 0000H to FFE5 00FFH 2 TAUJ0 FFE5 0100H to FFE5 01FFH 2 TAUJ2 FFE5 0200H to FFE5 0FFFH — Access prohibited area FFE5 1000H to FFE5 10FFH 2 TAUJ1 FFE5 1100H to FFE5 11FFH 2 TAUJ3 FFE5 1200H to FFE5 3FFFH — Access prohibited area FFE5 4000H to FFE5 4003H 2 SELB_TAUJ0 (SL_TAUJ0) FFE5 4004H to FFE5 4007H 2 SELB_TAUJ2 (SL_TAUJ2) FFE5 4008H to FFE6 FFFFH — Access prohibited area FFE7 0000H to FFE7 03FFH 2 PWSA0 FFE7 0400H to FFE7 0FFFH — Access prohibited area FFE7 1000H to FFE7 27FFH 2 PWGAn FFE7 2800H to FFE7 281FH 2 PWBA0 FFE7 2820H to FFE7 2FFFH — Access prohibited area FFE7 3000H to FFE7 301FH 2 SLPWG FFE7 3020H to FFE7 30FFH — Access prohibited area FFE7 3100H to FFE7 315FH 2 PWGA_INTF FFE7 3160H to FFE7 7FFFH — Access prohibited area

RH850/F1KH, RH850/F1KM Section 4A Address Space of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 689 of 4535 Dec 26, 2018 Table 4A.4 Peripheral I/O Address Map Address Peripheral Group Peripheral I/O FFE7 8000H to FFE7 807FH 2 RTCA0 FFE7 8080H to FFE7 FFFFH — Access prohibited area FFE8 0000H to FFE8 007FH 2 ENCA0 FFE8 0080H to FFE8 FFFFH — Access prohibited area FFE9 0000H to FFE9 003FH 2 TAPA0 FFE9 0040H to FFEC FFFFH — Access prohibited area FFED 0000H to FFED 000FH 2 WDTA0 FFED 0010H to FFED 0FFFH — Access prohibited area FFED 1000H to FFED 100FH 2 WDTA1 FFED 1010H to FFED 1FFFH — Access prohibited area FFED 2000H to FFED 200FH 2 WDTA2 FFED 2010H to FFED 8FFFH — Access prohibited area FFED 9000H to FFED 907FH 2 MMCA0 FFED 9080H to FFED 9FFFH — Access prohibited area FFED A000H to FFED A01FH 2 ECCMMCA0A FFED A020H to FFED A0FFH — Access prohibited area FFED A100H to FFED A11FH 2 ECCMMCA0B FFED A120H to FFF1 FFFFH — Access prohibited area FFF2 0000H to FFF2 07FFH 1 ADCA0 FFF2 0800H to FFF6 FFFFH — Access prohibited area FFF7 0000H to FFF7 003FH 1 DCRA0 FFF7 0040H to FFF7 0FFFH — Access prohibited area FFF7 1000H to FFF7 103FH 1 DCRA1 FFF7 1040H to FFF7 1FFFH — Access prohibited area FFF7 2000H to FFF7 203FH 1 DCRA2 FFF7 2040H to FFF7 2FFFH — Access prohibited area FFF7 3000H to FFF7 303FH 1 DCRA3 FFF7 3040H to FFF7 7FFFH — Access prohibited area FFF7 8000H to FFF7 8003H 1 KR0 FFF7 8004H to FFF7 FFFFH — Access prohibited area FFF8 0000H to FFF8 000FH 1 Write protected register (WPROTR) FFF8 0010H to FFF8 00FFH — Access prohibited area FFF8 0100H to FFF8 011FH 1 STBC0 FFF8 0120H to FFF8 03FFH — Access prohibited area FFF8 0400H to FFF8 040FH 1 STBC_WUF0 FFF8 0410H to FFF8 041FH 1 STBC_WUF1 FFF8 0420H to FFF8 051FH — Access prohibited area FFF8 0520H to FFF8 052FH 1 STBC_WUF20 FFF8 0530H to FFF8 075FH — Access prohibited area FFF8 0760H to FFF8 0AFFH 1 Reset controller / Supply voltage monitor (LVI,VLVI) FFF8 0B00H to FFF8 0FFFH 1 STBC_IOHOLD FFF8 1000H to FFF8 2FFFH 1 Clock controller (CLKCTL) FFF8 3000H to FFF8 307FH 1 LPS0 FFF8 3080H to FFF8 30FFH — Access prohibited area FFF8 3100H to FFF8 3207H 1 CVM (SVM)

RH850/F1KH, RH850/F1KM Section 4A Address Space of RH850/F1KH-D8 R01UH0684EJ0110 Rev.1.10 Page 690 of 4535 Dec 26, 2018 Table 4A.4 Peripheral I/O Address Map Address Peripheral Group Peripheral I/O FFF8 3208H to FFF8 3603H — Access prohibited area FFF8 3604H to FFF8 7FFFH — Access prohibited area FFF8 8000H to FFF8 800FH 1 Write protected register (WPROTR) FFF8 8010H to FFF8 810FH — Access prohibited area FFF8 8110H to FFF8 811FH 1 STBC_WUFISO FFF8 8120H to FFF8 BFFFH 1 Clock controller (CLKCTL) FFF8 C000H to FFF8 CFFFH 1 CLMA0, CLMA FFF8 D000H to FFF8 DFFFH 1 CLMA1 FFF8 E000H to FFF8 EFFFH 1 CLMA2 FFF8 F000H to FFF8 FFFFH 1 CLMA3 FFF9 0000H to FFF9 004FH 1 P-Bus guard (PBG50) FFF9 0050H to FFF9 3FFFH — Access prohibited area FFF9 4000H to FFF9 404FH 3 P-Bus guard (PBG30) FFF9 4050H to FFF9 40FFH — Access prohibited area FFF9 4100H to FFF9 414FH 3 P-Bus guard (PBG31) FFF9 4150H to FFF9 41FFH — Access prohibited area FFF9 4200H to FFF9 424FH 3 P-Bus guard (PBG32) FFF9 4250H to FFF9 42FFH — Access prohibited area FFF9 4300H to FFF9 434FH 3 P-Bus guard (PBG33) FFF9 4350H to FFF9 BFFFH — Access prohibited area FFF9 C000H to FFF9 C04FH 3 H-Bus guard (HBG00) FFF9 C050H to FFF9 C0FFH — Access prohibited area FFF9 C100H to FFF9 C14FH 3 H-Bus guard (HBG01) FFF9 C150H to FFF9 C1FFH — Access prohibited area FFF9 C200H to FFF9 C24FH 3 H-Bus guard (HBG02) FFF9 C250H to FFFE DFFFH — Access prohibited area FFFE E000H to FFFE E03FH CPU local peripheral IPG FFFE E040H to FFFE E5FFH Access prohibited area FFFE E600H to FFFE E6FFH PEG FFFE E700H to FFFE E97FH Access prohibited area FFFE E980H to FFFE E98FH SEG FFFE E990H to FFFE E9FFH Access prohibited area FFFE EA00H to FFFE EBFFH INTC1 FFFE EC00H to FFFE EC7FH MEV FFFE EC80H to FFFE EC8FH IPIRSS FFFE EC90H to FFFF 7FFFH — Access prohibited area FFFF 8000H to FFFF 8FFFH 2 PDMA0 FFFF 9000H to FFFF 9FFFH 2 PDMA1 FFFF A000H to FFFF AFFFH — Access prohibited area FFFF B000H to FFFF BFFFH 2 INTC2 FFFF C000H to FFFF FFFFH — Access prohibited area

RH850/F1KH, RH850/F1KM Section 4B Address Space of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 691 of 4535 Dec 26, 2018 Section 4B Address Space of RH850/F1KM-S4 4B.1 Address Space Table 4B.1, Address Space (4-MB 176/233/272-Pin Product) to Table 4B.6, Address Space (3-MB 100- Pin Product) show the address space of the RH850/F1KM. CAUTION Do not access an address with which no register is mapped in the on-chip I/O register space. In addition, do not access any access prohibited area specified in Table 4B.1, Address Space (4-MB 176/233/272-Pin Product) to Table 4B.6, Address Space (3-MB 100-Pin Product). If such an address is accessed, operation is not guaranteed. NOTE The Local RAM is accessible through the following two address areas in the address space. CPU1 area: Address area accessible from CPU, DMA, FlexRay and ETNB. Self area: Mirrored address area, accessible only from CPU to refer the CPU’s self resource. Table 4B.1 Address Space (4-MB 176/233/272-Pin Product) Address Address Space Type Size 0000 0000H to 003F FFFFH Code Flash 4 MB 0040 0000H to 00FF FFFFH Access prohibited area 0100 0000H to 0100 7FFFH Code Flash (Extended user area) 32 KB 0100 8000H to 1001 FFFFH Access prohibited area 1002 0000H to 1002 1FFFH FlexRay Interface (FLXA) 8 KB 1002 2000H to 1002 FFFFH Access prohibited area 1003 0000H to 1003 03FFH External Memory Access Controller (MEMC) 1 KB 1003 0400H to 1003 FFFFH Access prohibited area 1004 0000H to 1004 0FFFH Serial Flash Memory Interface (SFMA) 4 KB 1004 1000H to 1FFF FFFFH Access prohibited area 2000 0000H to 20FF FFFFH External Memory Area (CS0) 16 MB*4 2100 0000H to 21FF FFFFH Access prohibited area 2200 0000H to 22FF FFFFH External Memory Area (CS1) 16 MB*4 2300 0000H to 23FF FFFFH Access prohibited area 2400 0000H to 24FF FFFFH External Memory Area (CS2) 16 MB*4 2500 0000H to 27FF FFFFH Access prohibited area 2800 0000H to 28FF FFFFH External Memory Area (CS3) 16 MB*4 2900 0000H to 2FFF FFFFH Access prohibited area 3000 0000H to 33FF FFFFH External Serial Flash Memory Area 64 MB 3400 0000H to FEBB FFFFH Access prohibited area FEBC 0000H to FEBF FFFFH Local RAM (CPU1 area) 256 KB*1 FEC0 0000H to FEDB FFFFH Access prohibited area FEDC 0000H to FEDF FFFFH Local RAM (self area) 256 KB*1 FEE0 0000H to FEEE 7FFFH Access prohibited area FEEE 8000H to FEEF FFFFH Global RAM A 96 KB*2 FEF0 0000H to FEF0 FFFFH Retention RAM 64 KB FEF1 0000H to FEFE 7FFFH Access prohibited area

RH850/F1KH, RH850/F1KM Section 4B Address Space of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 692 of 4535 Dec 26, 2018 Table 4B.1 Address Space (4-MB 176/233/272-Pin Product) Address Address Space Type Size FEFE 8000H to FEFF FFFFH Global RAM B 96 KB*2 FF00 0000H to FF1F FFFFH Access prohibited area FF20 0000H to FF21 FFFFH Data flash 128 KB*3 FF22 0000H to FF9F FFFFH Access prohibited area FFA0 0000H to FFFD FFFFH On-chip peripheral I/O area 6 MB - 128 KB FFFE 0000H to FFFE DFFFH Access prohibited area FFFE E000H to FFFE FFFFH On-chip peripheral I/O area (self area) 8 KB FFFF 0000H to FFFF 4FFFH Access prohibited area FFFF 5000H to FFFF FFFFH On-chip peripheral I/O area 44 KB Note 1. 192 KB in products of CPU frequency 160 MHz max.: For detail, see Section 45, RAM. Note 2. 64 KB in products of CPU frequency 160 MHz max.: For detail, see Section 45, RAM. Note 3. 96 KB in products of CPU frequency 160 MHz max.: For detail, see Section 44, Flash Memory. Note 4. 8 MB in 176/233-pin products: For details, see Section 16, External Memory Access Controller (MEMC).

RH850/F1KH, RH850/F1KM Section 4B Address Space of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 693 of 4535 Dec 26, 2018 Table 4B.2 Address Space (4-MB 144-Pin Product) Address Address Space Type Size 0000 0000H to 003F FFFFH Code Flash 4 MB 0040 0000H to 00FF FFFFH Access prohibited area 0100 0000H to 0100 7FFFH Code Flash (Extended user area) 32 KB 0100 8000H to 1001 FFFFH Access prohibited area 1002 0000H to 1002 1FFFH FlexRay Interface (FLXA) 8 KB 1002 2000H to 1003 FFFFH Access prohibited area 1004 0000H to 1004 0FFFH Serial Flash Memory Interface (SFMA) 4 KB 1004 1000H to 2FFF FFFFH Access prohibited area 3000 0000H to 33FF FFFFH External Serial Flash Memory Area 64 MB 3400 0000H to FEBB FFFFH Access prohibited area FEBC 0000H to FEBF FFFFH Local RAM (CPU1 area) 256 KB*1 FEC0 0000H to FEDB FFFFH Access prohibited area FEDC 0000H to FEDF FFFFH Local RAM (self area) 256 KB*1 FEE0 0000H to FEEE 7FFFH Access prohibited area FEEE 8000H to FEEF FFFFH Global RAM A 96 KB*2 FEF0 0000H to FEF0 FFFFH Retention RAM 64 KB FEF1 0000H to FEFE 7FFFH Access prohibited area FEFE 8000H to FEFF FFFFH Global RAM B 96 KB*2 FF00 0000H to FF1F FFFFH Access prohibited area FF20 0000H to FF21 FFFFH Data flash 128 KB*3 FF22 0000H to FF9F FFFFH Access prohibited area FFA0 0000H to FFFD FFFFH On-chip peripheral I/O area 6 MB - 128 KB FFFE 0000H to FFFE DFFFH Access prohibited area FFFE E000H to FFFE FFFFH On-chip peripheral I/O area (self area) 8 KB FFFF 0000H to FFFF 4FFFH Access prohibited area FFFF 5000H to FFFF FFFFH On-chip peripheral I/O area 44 KB Note 1. 192 KB in products of CPU frequency 160 MHz max.: For detail, see Section 45, RAM. Note 2. 64 KB in products of CPU frequency 160 MHz max.: For detail, see Section 45, RAM. Note 3. 96 KB in products of CPU frequency 160 MHz max.: For detail, see Section 44, Flash Memory.

RH850/F1KH, RH850/F1KM Section 4B Address Space of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 694 of 4535 Dec 26, 2018 Table 4B.3 Address Space (4-MB 100-Pin Product) Address Address Space Type Size 0000 0000H to 003F FFFFH Code Flash 4 MB 0040 0000H to 00FF FFFFH Access prohibited area 0100 0000H to 0100 7FFFH Code Flash (Extended user area) 32 KB 0100 8000H to 1001 FFFFH Access prohibited area 1002 0000H to 1002 1FFFH FlexRay Interface (FLXA) 8 KB 1002 2000H to FEBB FFFFH Access prohibited area FEBC 0000H to FEBF FFFFH Local RAM (CPU1 area) 256 KB*1 FEC0 0000H to FEDB FFFFH Access prohibited area FEDC 0000H to FEDF FFFFH Local RAM (self area) 256 KB*1 FEE0 0000H to FEEE 7FFFH Access prohibited area FEEE 8000H to FEEF FFFFH Global RAM A 96 KB*2 FEF0 0000H to FEF0 FFFFH Retention RAM 64 KB FEF1 0000H to FEFE 7FFFH Access prohibited area FEFE 8000H to FEFF FFFFH Global RAM B 96 KB*2 FF00 0000H to FF1F FFFFH Access prohibited area FF20 0000H to FF21 FFFFH Data flash 128 KB*3 FF22 0000H to FF9F FFFFH Access prohibited area FFA0 0000H to FFFD FFFFH On-chip peripheral I/O area 6 MB - 128 KB FFFE 0000H to FFFE DFFFH Access prohibited area FFFE E000H to FFFE FFFFH On-chip peripheral I/O area (self area) 8 KB FFFF 0000H to FFFF 4FFFH Access prohibited area FFFF 5000H to FFFF FFFFH On-chip peripheral I/O area 44 KB Note 1. 192 KB in products of CPU frequency 160 MHz max.: For detail, see Section 45, RAM. Note 2. 64 KB in products of CPU frequency 160 MHz max.: For detail, see Section 45, RAM. Note 3. 96 KB in products of CPU frequency 160 MHz max.: For detail, see Section 44, Flash Memory.

RH850/F1KH, RH850/F1KM Section 4B Address Space of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 695 of 4535 Dec 26, 2018 Table 4B.4 Address Space (3-MB 176/233/272-Pin Product) Address Address Space Type Size 0000 0000H to 002F FFFFH Code Flash 3 MB 0030 0000H to 00FF FFFFH Access prohibited area 0100 0000H to 0100 7FFFH Code Flash (Extended user area) 32 KB 0100 8000H to 1001 FFFFH Access prohibited area 1002 0000H to 1002 1FFFH FlexRay Interface (FLXA) 8 KB 1002 2000H to 1002 FFFFH Access prohibited area 1003 0000H to 1003 03FFH External Memory Access Controller (MEMC) 1 KB 1003 0400H to 1003 FFFFH Access prohibited area 1004 0000H to 1004 0FFFH Serial Flash Memory Interface (SFMA) 4 KB 1004 1000H to 1FFF FFFFH Access prohibited area 2000 0000H to 20FF FFFFH External Memory Area (CS0) 16 MB*4 2100 0000H to 21FF FFFFH Access prohibited area 2200 0000H to 22FF FFFFH External Memory Area (CS1) 16 MB*4 2300 0000H to 23FF FFFFH Access prohibited area 2400 0000H to 24FF FFFFH External Memory Area (CS2) 16 MB*4 2500 0000H to 27FF FFFFH Access prohibited area 2800 0000H to 28FF FFFFH External Memory Area (CS3) 16 MB*4 2900 0000H to 2FFF FFFFH Access prohibited area 3000 0000H to 33FF FFFFH External Serial Flash Memory Area 64 MB 3400 0000H to FEBC FFFFH Access prohibited area FEBD 0000H to FEBF FFFFH Local RAM (CPU1 area) 192 KB*1 FEC0 0000H to FEDC FFFFH Access prohibited area FEDD 0000H to FEDF FFFFH Local RAM (self area) 192 KB*1 FEE0 0000H to FEEE FFFFH Access prohibited area FEEF 0000H to FEEF FFFFH Global RAM A 64 KB*2 FEF0 0000H to FEF0 FFFFH Retention RAM 64 KB FEF1 0000H to FEFE FFFFH Access prohibited area FEFF 0000H to FEFF FFFFH Global RAM B 64 KB*2 FF00 0000H to FF1F FFFFH Access prohibited area FF20 0000H to FF21 FFFFH Data flash 128 KB*3 FF22 0000H to FF9F FFFFH Access prohibited area FFA0 0000H to FFFD FFFFH On-chip peripheral I/O area 6 MB - 128 KB FFFE 0000H to FFFE DFFFH Access prohibited area FFFE E000H to FFFE FFFFH On-chip peripheral I/O area (self area) 8 KB FFFF 0000H to FFFF 4FFFH Access prohibited area FFFF 5000H to FFFF FFFFH On-chip peripheral I/O area 44 KB Note 1. 160 KB in products of CPU frequency 160 MHz max.: For detail, see Section 45, RAM. Note 2. 48 KB in products of CPU frequency 160 MHz max.: For detail, see Section 45, RAM. Note 3. 96 KB in products of CPU frequency 160 MHz max.: For detail, see Section 44, Flash Memory. Note 4. 8 MB in 176/233-pin products: For details, see Section 16, External Memory Access Controller (MEMC).

RH850/F1KH, RH850/F1KM Section 4B Address Space of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 696 of 4535 Dec 26, 2018 Table 4B.5 Address Space (3-MB 144-Pin Product) Address Address Space Type Size 0000 0000H to 002F FFFFH Code Flash 3 MB 0030 0000H to 00FF FFFFH Access prohibited area 0100 0000H to 0100 7FFFH Code Flash (Extended user area) 32 KB 0100 8000H to 1001 FFFFH Access prohibited area 1002 0000H to 1002 1FFFH FlexRay Interface (FLXA) 8 KB 1002 2000H to 1003 FFFFH Access prohibited area 1004 0000H to 1004 0FFFH Serial Flash Memory Interface (SFMA) 4 KB 1004 1000H to 2FFF FFFFH Access prohibited area 3000 0000H to 33FF FFFFH External Serial Flash Memory Area 64 MB 3400 0000H to FEBC FFFFH Access prohibited area FEBD 0000H to FEBF FFFFH Local RAM (CPU1 area) 192 KB*1 FEC0 0000H to FEDC FFFFH Access prohibited area FEDD 0000H to FEDF FFFFH Local RAM (self area) 192 KB*1 FEE0 0000H to FEEE FFFFH Access prohibited area FEEF 0000H to FEEF FFFFH Global RAM A 64 KB*2 FEF0 0000H to FEF0 FFFFH Retention RAM 64 KB FEF1 0000H to FEFE FFFFH Access prohibited area FEFF 0000H to FEFF FFFFH Global RAM B 64 KB*2 FF00 0000H to FF1F FFFFH Access prohibited area FF20 0000H to FF21 FFFFH Data flash 128 KB*3 FF22 0000H to FF9F FFFFH Access prohibited area FFA0 0000H to FFFD FFFFH On-chip peripheral I/O area 6 MB - 128 KB FFFE 0000H to FFFE DFFFH Access prohibited area FFFE E000H to FFFE FFFFH On-chip peripheral I/O area (self area) 8 KB FFFF 0000H to FFFF 4FFFH Access prohibited area FFFF 5000H to FFFF FFFFH On-chip peripheral I/O area 44 KB Note 1. 160 KB in products of CPU frequency 160 MHz max.: For detail, see Section 45, RAM. Note 2. 48 KB in products of CPU frequency 160 MHz max.: For detail, see Section 45, RAM. Note 3. 96 KB in products of CPU frequency 160 MHz max.: For detail, see Section 44, Flash Memory.

RH850/F1KH, RH850/F1KM Section 4B Address Space of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 697 of 4535 Dec 26, 2018 Table 4B.6 Address Space (3-MB 100-Pin Product) Address Address Space Type Size 0000 0000H to 002F FFFFH Code Flash 3 MB 0030 0000H to 00FF FFFFH Access prohibited area 0100 0000H to 0100 7FFFH Code Flash (Extended user area) 32 KB 0100 8000H to 1001 FFFFH Access prohibited area 1002 0000H to 1002 1FFFH FlexRay Interface (FLXA) 8 KB 1002 2000H to FEBC FFFFH Access prohibited area FEBD 0000H to FEBF FFFFH Local RAM (CPU1 area) 192 KB*1 FEC0 0000H to FEDC FFFFH Access prohibited area FEDD 0000H to FEDF FFFFH Local RAM (self area) 192 KB*1 FEE0 0000H to FEEE FFFFH Access prohibited area FEEF 0000H to FEEF FFFFH Global RAM A 64 KB*2 FEF0 0000H to FEF0 FFFFH Retention RAM 64 KB FEF1 0000H to FEFE FFFFH Access prohibited area FEFF 0000H to FEFF FFFFH Global RAM B 64 KB*2 FF00 0000H to FF1F FFFFH Access prohibited area FF20 0000H to FF21 FFFFH Data flash 128 KB*3 FF22 0000H to FF9F FFFFH Access prohibited area FFA0 0000H to FFFD FFFFH On-chip peripheral I/O area 6 MB - 128 KB FFFE 0000H to FFFE DFFFH Access prohibited area FFFE E000H to FFFE FFFFH On-chip peripheral I/O area (self area) 8 KB FFFF 0000H to FFFF 4FFFH Access prohibited area FFFF 5000H to FFFF FFFFH On-chip peripheral I/O area 44 KB Note 1. 160 KB in products of CPU frequency 160 MHz max.: For detail, see Section 45, RAM. Note 2. 48 KB in products of CPU frequency 160 MHz max.: For detail, see Section 45, RAM. Note 3. 96 KB in products of CPU frequency 160 MHz max.: For detail, see Section 44, Flash Memory.

RH850/F1KH, RH850/F1KM Section 4B Address Space of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 698 of 4535 Dec 26, 2018 4B.2 Address Space Viewed from Each Bus Master Table 4B.7, Address Space Viewed from Each Bus Master (4-MB Product) shows address spaces viewed from each bus master. 4B.2.1 Space in which Instructions can be Fetched Instructions of the CPU can be fetched from the Code flash, local RAM, global RAM, and retention RAM. 4B.2.2 Data Space Accessible by CPU See Table 4B.7, Address Space Viewed from Each Bus Master (4-MB Product) for the spaces accessible from the CPU. 4B.2.3 Data Space Accessible by DMA See Table 4B.7, Address Space Viewed from Each Bus Master (4-MB Product) for the spaces accessible from the DMA. 4B.2.4 Data Space Accessible by Flexray See Table 4B.7, Address Space Viewed from Each Bus Master (4-MB Product) for the spaces accessible from the Flexray. 4B.2.5 Data Space Accessible by ETNB See Table 4B.7, Address Space Viewed from Each Bus Master (4-MB Product) for the spaces accessible from the ETNB.

RH850/F1KH, RH850/F1KM Section 4B Address Space of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 699 of 4535 Dec 26, 2018 4B.2.6 Data Space Accessible by Each Bus Master See Table 4B.7, Address Space Viewed from Each Bus Master (4-MB Product) for the spaces accessible from Each Bus Master. Table 4B.7 Address Space Viewed from Each Bus Master (4-MB Product) Address Resource From CPU From DMA From FlexRay From ETNB 0000 0000H to 003F FFFFH Code Flash   0040 0000H to 00FF FFFFH Access prohibited area 0100 0000H to 0100 7FFFH Code Flash (Extended user area)   0100 8000H to 1001 FFFFH Access prohibited area 1002 0000H to 1002 1FFFH FlexRay Interface (FLXA)   1002 2000H to 1002 FFFFH Access prohibited area 1003 0000H to 1003 03FFH External Memory Access Controller (MEMC)   1003 0400H to 1003 FFFFH Access prohibited area 1004 0000H to 1004 0FFFH Serial Flash Memory Interface (SFMA)   1004 1000H to 1FFF FFFFH Access prohibited area 2000 0000H to 20FF FFFFH External Memory Area (CS0)   2100 0000H to 21FF FFFFH Access prohibited area 2200 0000H to 22FF FFFFH External Memory Area (CS1)   2300 0000H to 23FF FFFFH Access prohibited area 2400 0000H to 24FF FFFFH External Memory Area (CS2)   2500 0000H to 27FF FFFFH Access prohibited area 2800 0000H to 28FF FFFFH External Memory Area (CS3)   2900 0000H to 2FFF FFFFH Access prohibited area 3000 0000H to 33FF FFFFH External Serial Flash Memory Area   3400 0000H to FEBB FFFFH Access prohibited area FEBC 0000H to FEBF FFFFH Local RAM (CPU1 area)     FEC0 0000H to FEDB FFFFH Access prohibited area FEDC 0000H to FEDF FFFFH Local RAM (self area)  FEE0 0000H to FEEE 7FFFH Access prohibited area FEEE 8000H to FEEF FFFFH Global RAM A     FEF0 0000H to FEF0 FFFFH Retention RAM     FEF1 0000H to FEFE 7FFFH Access prohibited area FEFE 8000H to FEFF FFFFH Global RAM B     FF00 0000H to FF1F FFFFH Access prohibited area FF20 0000H to FF21 FFFFH Data flash   FF22 0000H to FF9F FFFFH Access prohibited area FFA0 0000H to FFFD FFFFH On-chip peripheral I/O area   FFFE 0000H to FFFE DFFFH Access prohibited area FFFE E000H to FFFE FFFFH On-chip peripheral I/O area (self area)  FFFF 0000H to FFFF 4FFFH Access prohibited area FFFF 5000H to FFFF FFFFH On-chip peripheral I/O area   Note: The following color coding is used in the map above. Fetch and data access available Data access available Access prohibited

RH850/F1KH, RH850/F1KM Section 4B Address Space of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 700 of 4535 Dec 26, 2018 4B.3 Peripheral I/O Address Map Table 4B.8, Peripheral I/O Address Map shows peripheral I/O address map. Table 4B.8 Peripheral I/O Address Map Address Peripheral Group Peripheral I/O FF00 0000H to FF1F FFFFH — Access prohibited area FF20 0000H to FF21 FFFFH 4 Data Flash FF22 0000H to FF9F FFFFH — Access prohibited area FFA0 0000H to FFA0 001FH 1 FLMD FFA0 0020H to FFA0 0FFFH — Access prohibited area FFA0 1000H to FFA0 103FH — Access prohibited area FFA0 1040H to FFA0 1FFFH — Access prohibited area FFA0 2000H to FFA0 201FH — Access prohibited area FFA0 2020H to FFA0 FFFFH — Access prohibited area FFA1 0000H to FFA1 1FFFH 1 Flash controller FFA1 2000H to FFA1 FFFFH — Access prohibited area FFA2 0000H to FFA2 FFFFH 1 FACI command-issuing area FFA3 0000H to FFBF FFFFH — Access prohibited area FFC0 0000H to FFC0 000FH 1 FENMI (ECON_NMI) FFC0 0010H to FFC0 00FFH — Access prohibited area FFC0 0100H to FFC0 010FH 1 FEINT (ECON_FEINT) FFC0 0110H to FFC0 0FFFH — Access prohibited area FFC0 1000H to FFC0 1003H 1 SELB_INTC (SL_INTC) FFC0 1004H to FFC0 1FFFH — Access prohibited area FFC0 2000H to FFC0 200FH 1 SELB_DMAC (SL_DMAC) FFC0 2010H to FFC0 2FFFH — Access prohibited area FFC0 3000H to FFC0 300FH 1 GRZF FFC0 3010H to FFC0 FFFFH — Access prohibited area FFC1 0000H to FFC1 4CCFH 1 PORT FFC1 4CD0H to FFC1 FFFFH — Access prohibited area FFC2 0000H to FFC2 04CFH 1 PORT(JTAG) FFC2 04D0H to FFC2 FFFFH — Access prohibited area FFC3 0000H to FFC3 000FH 1 DNFA_TAUD0 (DNF) FFC3 0010H to FFC3 001FH — Access prohibited area FFC3 0020H to FFC3 002FH 1 DNFA_TAUB0 (DNF) FFC3 0030H to FFC3 003FH — Access prohibited area FFC3 0040H to FFC3 004FH 1 DNFA_TAUB1 (DNF) FFC3 0050H to FFC3 005FH — Access prohibited area FFC3 0060H to FFC3 006FH 1 DNFA_ENCA0 (DNF) FFC3 0070H to FFC3 009FH — Access prohibited area FFC3 00A0H to FFC3 00AFH 1 DNFA_ADCA0 (DNF) FFC3 00B0H to FFC3 00BFH — Access prohibited area FFC3 00C0H to FFC3 00CFH 1 DNFA_ADCA1 (DNF) FFC3 00D0H to FFC3 00DFH — Access prohibited area

RH850/F1KH, RH850/F1KM Section 4B Address Space of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 701 of 4535 Dec 26, 2018 Table 4B.8 Peripheral I/O Address Map Address Peripheral Group Peripheral I/O FFC3 00E0H to FFC3 00EFH 1 DNFA_SENT (DNF) FFC3 00F0H to FFC3 00FFH — Access prohibited area FFC3 0100H to FFC3 010FH — Access prohibited area FFC3 0110H to FFC3 3FFFH — Access prohibited area FFC3 4000H to FFC3 401FH 1 FCLA_NMI (FCLA0) FFC3 4020H to FFC3 403FH 1 FCLA_INTPL (FCLA0) FFC3 4040H to FFC3 405FH 1 FCLA_INTPH (FCLA0) FFC3 4060H to FFC3 407FH 1 FCLA_ADCA0 (FCLA0) FFC3 4080H to FFC3 409FH 1 FCLA_ADCA1 (FCLA0) FFC3 40A0H to FFC3 40BFH 1 FCLA_INTPU (FCLA0) FFC3 40C0H to FFC3 FFFFH — Access prohibited area FFC4 0000H to FFC4 004FH 1 P-Bus guard (PBG10) FFC4 0050H to FFC4 00FFH — Access prohibited area FFC4 0100H to FFC4 014FH 1 P-Bus guard (PBG11) FFC4 0150H to FFC4 03FFH — Access prohibited area FFC4 0400H to FFC4 044FH 1 P-Bus guard (PBG12) FFC4 0450H to FFC4 04FFH — Access prohibited area FFC4 0500H to FFC4 054FH 1 P-Bus guard (PBG13) FFC4 0550H to FFC4 8FFFH — Access prohibited area FFC4 9000H to FFC4 907FH 2 Global RAM Guard Bank A (MGDGR) FFC4 9080H to FFC4 91FFH — Access prohibited area FFC4 9200H to FFC4 927FH 2 Global RAM Guard Bank B (MGDGR) FFC4 9280H to FFC4 BFFFH — Access prohibited area FFC4 C000H to FFC4 C00FH 2 P-Bus guard (PBGC0) FFC4 C010H to FFC4 C10FH — Access prohibited area FFC4 C110H to FFC4 C13FH 2 P-Bus guard (PBGC1) FFC4 C140H to FFC4 C7FFH — Access prohibited area FFC4 C800H to FFC4 C80FH 2 ERRSLV (PBGC0) FFC4 C810H to FFC4 C8FFH — Access prohibited area FFC4 C900H to FFC4 C90FH 2 ERRSLV (PBGC1) FFC4 C910H to FFC5 97FFH — Access prohibited area FFC5 9800H to FFC5 981FH 4 EEPRDCYCL (DCIB) FFC5 9820H to FFC5 9BFFH — Access prohibited area FFC5 9C00H to FFC5 9C4FH 4 P-Bus guard (PBG40) FFC5 9C50H to FFC5 AFFFH — Access prohibited area FFC5 B000H to FFC5 B003H 2 FBUFCCTL (FBUF_CTRL) FFC5 B004H to FFC6 21FFH — Access prohibited area FFC6 2200H to FFC6 23FFH 2 Code Flash ECC (CFECC_VCI) FFC6 2400H to FFC6 25FFH 2 Code Flash ECC (CFECC_CPU1) FFC6 2600H to FFC6 29FFH — Access prohibited area FFC6 2A00H to FFC6 2A3FH 4 Data Flash ECC (DFECC)

RH850/F1KH, RH850/F1KM Section 4B Address Space of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 702 of 4535 Dec 26, 2018 Table 4B.8 Peripheral I/O Address Map Address Peripheral Group Peripheral I/O FFC6 2A40H to FFC6 3FFFH — Access prohibited area FFC6 4000H to FFC6 403FH 2 Global RAM ECC Bank A (GRECC) FFC6 4040H to FFC6 41FFH — Access prohibited area FFC6 4200H to FFC6 423FH 2 Global RAM ECC Bank B (GRECC) FFC6 4240H to FFC6 4FFFH — Access prohibited area FFC6 5000H to FFC6 501FH 2 Local RAM ECC TEST PE1 (LRTST) FFC6 5020H to FFC6 53FFH — Access prohibited area FFC6 5400H to FFC6 547FH 2 Local RAM ECC PE1 (LRECC) FFC6 5480H to FFC7 00FFH — Access prohibited area FFC7 0100H to FFC7 011FH 3 ECCCSIH0 FFC7 0120H to FFC7 01FFH — Access prohibited area FFC7 0200H to FFC7 021FH 3 ECCCSIH1 FFC7 0220H to FFC7 02FFH — Access prohibited area FFC7 0300H to FFC7 031FH 3 ECCCSIH2 FFC7 0320H to FFC7 03FFH — Access prohibited area FFC7 0400H to FFC7 041FH 3 ECCCSIH3 FFC7 0420H to FFC7 12FFH — Access prohibited area FFC7 1300H to FFC7 131FH 5 ECCCFD0MB FFC7 1320H to FFC7 13FFH — Access prohibited area FFC7 1400H to FFC7 141FH 5 ECCCFD0AFL0 FFC7 1420H to FFC7 14FFH — Access prohibited area FFC7 1500H to FFC7 151FH 5 ECCCFD0AFL1 FFC7 1520H to FFC7 17FFH — Access prohibited area FFC7 1800H to FFC7 184FH 5 P-Bus guard (PBG60) FFC7 1850H to FFC7 30FFH — Access prohibited area FFC7 3100H to FFC7 311FH 3 ECCFLXA0 FFC7 3120H to FFC7 31FFH — Access prohibited area FFC7 3200H to FFC7 321FH 3 ECCFLXA0T0 FFC7 3220H to FFC7 32FFH — Access prohibited area FFC7 3300H to FFC7 331FH 3 ECCFLXA0T1 FFC7 3320H to FFC7 40FFH — Access prohibited area FFC7 4100H to FFC7 411FH 3 ECCETNB0TX FFC7 4120H to FFC7 41FFH — Access prohibited area FFC7 4200H to FFC7 421FH 3 ECCETNB0RX FFC7 4220H to FFC7 7FFFH — Access prohibited area FFC7 8000H to FFC7 8003H 1 SELB READ TEST (SL_READTEST) FFC7 8004H to FFC9 FFFFH — Access prohibited area FFCA 0000H to FFCA 007FH 1 RIIC0 FFCA 0080H to FFCA 00FFH 1 RIIC1 FFCA 0100H to FFCC FFFFH — Access prohibited area FFCD 0000H to FFCD 01FFH 1 PRDNAME/CHIPID (SCDS) FFCD 0200H to FFCD FFFFH — Access prohibited area FFCE 0000H to FFCE 007FH 1 RLN240 FFCE 0080H to FFCE 00FFH 1 RLN241 FFCE 0100H to FFCE 017FH 1 RLN242

RH850/F1KH, RH850/F1KM Section 4B Address Space of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 703 of 4535 Dec 26, 2018 Table 4B.8 Peripheral I/O Address Map Address Peripheral Group Peripheral I/O FFCE 0180H to FFCE 1FFFH — Access prohibited area FFCE 2000H to FFCE 203FH 1 RLN30 FFCE 2040H to FFCE 207FH 1 RLN31 FFCE 2080H to FFCE 20BFH 1 RLN32 FFCE 20C0H to FFCE 20FFH 1 RLN33 FFCE 2100H to FFCE 213FH 1 RLN34 FFCE 2140H to FFCE 217FH 1 RLN35 FFCE 2180H to FFCE 21BFH 1 RLN36 FFCE 21C0H to FFCE 21FFH 1 RLN37 FFCE 2200H to FFCE FFFFH — Access prohibited area FFCF 0000H to FFCF 007FH 1 RSENT0 FFCF 0080H to FFCF 00FFH — Access prohibited area FFCF 0100H to FFCF 017FH 1 RSENT1 FFCF 0180H to FFCF FFFFH — Access prohibited area FFD0 0000H to FFD1 FFFFH 5 RCFDC0 FFD2 0000H to FFD6 CFFFH — Access prohibited area FFD6 D000H to FFD6 D7FFH 3 ADCA1 FFD6 D800H to FFD6 DFFFH — Access prohibited area FFD6 E000H to FFD6 E7FFH 3 ETNB0 FFD6 E800H to FFD6 FFFFH — Access prohibited area FFD7 0000H to FFD7 003FH 3 OSTM0 FFD7 0040H to FFD7 00FFH — Access prohibited area FFD7 0100H to FFD7 013FH 3 OSTM1 FFD7 0140H to FFD7 01FFH — Access prohibited area FFD7 0200H to FFD7 023FH 3 OSTM2 FFD7 0240H to FFD7 02FFH — Access prohibited area FFD7 0300H to FFD7 033FH 3 OSTM3 FFD7 0340H to FFD7 03FFH — Access prohibited area FFD7 0400H to FFD7 043FH 3 OSTM4 FFD7 0440H to FFD7 FFFFH — Access prohibited area FFD8 0000H to FFD8 001FH 3 CSIH0 (CSIH0CTL0-2, CSIH0STR0, CSIH0STCR0, CSIH0EMU) FFD8 0020H to FFD8 0FFFH — Access prohibited area FFD8 1000H to FFD8 107FH 3 CSIH0 (CSIH0 registers other than above) FFD8 1080H to FFD8 1FFFH — Access prohibited area FFD8 2000H to FFD8 201FH 3 CSIH1 (CSIH1CTL0-2, CSIH1STR0, CSIH1STCR0, CSIH1EMU) FFD8 2020H to FFD8 2FFFH — Access prohibited area FFD8 3000H to FFD8 307FH 3 CSIH1 (CSIH1 registers other than above) FFD8 3080H to FFD8 3FFFH — Access prohibited area FFD8 4000H to FFD8 401FH 3 CSIH2 (CSIH2CTL0-2, CSIH2STR0, CSIH2STCR0, CSIH2EMU) FFD8 4020H to FFD8 4FFFH — Access prohibited area FFD8 5000H to FFD8 507FH 3 CSIH2 (CSIH2 registers other than above) FFD8 5080H to FFD8 5FFFH — Access prohibited area FFD8 6000H to FFD8 601FH 3 CSIH3 (CSIH3CTL0-2, CSIH3STR0, CSIH3STCR0, CSIH3EMU) FFD8 6020H to FFD8 6FFFH — Access prohibited area FFD8 7000H to FFD8 707FH 3 CSIH3 (CSIH3 registers other than above)

RH850/F1KH, RH850/F1KM Section 4B Address Space of RH850/F1KM-S4 R01UH0684EJ0110 Rev.1.10 Page 704 of 4535 Dec 26, 2018 Table 4B.8 Peripheral I/O Address Map Address Peripheral Group Peripheral I/O FFD8 7080H to FFD8 7FFFH — Access prohibited area FFD8 8000H to FFD8 801FH 3 CSIG0 (CSIG0CTL0-2, CSIG0STR0, CSIG0STCR0, CSIG0EMU) FFD8 8020H to FFD8 8FFFH — Access prohibited area FFD8 9000H to FFD8 901FH 3 CSIG0 (CSIG0 registers other than above) FFD8 9020H to FFD8 9FFFH — Access prohibited area FFD8 A000H to FFD8 A01FH 3 CSIG1 (CSIG1CTL0-2, CSIG1STR0, CSIG1STCR0, CSIG1EMU) FFD8 A020H to FFD8 AFFFH — Access prohibited area FFD8 B000H to FFD8 B01FH 3 CSIG1 (CSIG1 registers other than above) FFD8 B020H to FFD8 BFFFH — Access prohibited area FFD8 C000H to FFD8 C01FH 3 CSIG2 (CSIG2CTL0-2, CSIG2STR0, CSIG2STCR0, CSIG2EMU) FFD8 C020H to FFD8 CFFFH — Access prohibited area FFD8 D000H to FFD8 D01FH 3 CSIG2 (CSIG2 registers other than above) FFD8 D020H to FFD8 DFFFH — Access prohibited area FFD8 E000H to FFD8 E01FH 3 CSIG3 (CSIG3CTL0-2, CSIG3STR0, CSIG3STCR0, CSIG3EMU) FFD8 E020H to FFD8 EFFFH — Access prohibited area FFD8 F000H to FFD8 F01FH 3 CSIG3 (CSIG3 registers other than above) FFD8 F020H to FFDC FFFFH — Access prohibited area FFDD 0000H to FFDD 00FFH 2 PIC0 FFDD 0100H to FFDD CFFFH — Access prohibited area FFDD D000H to FFDD D04FH 2 P-Bus guard (PBG20) FFDD D050H to FFDD D0FFH — Access prohibited area FFDD D100H to FFDD D14FH 2 P-Bus guard (PBG21) FFDD D150H to FFE1 FFFFH — Access prohibited area FFE2 0000H to FFE2 03FFH 2 TAUD0 FFE2 0400H to FFE2 3FFFH — Access prohibited area FFE2 4000H to FFE2 4003H 2 SELB_TAUD0 (SL_TAUD0) FFE2 4004H to FFE2 FFFFH — Access prohibited area FFE3 0000H to FFE3 03FFH 2 TAUB0 FFE3 0400H to FFE3 0FFFH — Access prohibited area FFE3 1000H to FFE3 13FFH 2 TAUB1 FFE3 1400H to FFE3 1FFFH — Access prohibited area FFE3 2000H to FFE3 2003H 2 SELB_TAUB0 (SL_TAUB0) FFE3 2004H to FFE3 2FFFH — Access prohibited area FFE3 3000H to FFE3 3003H 2 SELB_TAUB1 (SL_TAUB1) FFE3 3004H to FFE4 FFFFH — Access prohibited area FFE5 0000H to FFE5 00FFH 2 TAUJ0 FFE5 0100H to FFE5 01FFH 2 TAUJ2 FFE5 0200H to FFE5 0FFFH — Access prohibited area FFE5 1000H to FFE5 10FFH 2 TAUJ1 FFE5 1100H to FFE5 11FFH 2 TAUJ3 FFE5 1200H to FFE5 3FFFH — Access prohibited area FFE5 4000H to FFE5 4003H 2 SELB_TAUJ0 (SL_TAUJ0) FFE5 4004H to FFE5 4007H 2 SELB_TAUJ2 (SL_TAUJ2) FFE5 4008H to FFE6 FFFFH — Access prohibited area FFE7 0000H to FFE7 03FFH 2 PWSA0

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