Microcontroller

R7F123FMG4AFB-C

Renesas Technology Corp

RENESAS MCU Rev.1.20 Dec 31, 2025

Manufacturer: Renesas Technology Corp

Document: 210 Pages / 3Mb

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Document overview

Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
PDF pages: 210

Technical content

The RL78/F23, F24 microcontrollers are ideal for realizing future highly reliable smart actuators and sensors, as well as low-end body ECUs. RL78/F23, F24 products are designed accordi ng to ISO 26262 and support functional safety (FuSa) up to ASIL B. They support up to the EVITA-Light security standard or more. An AES crypto module can handle key lengths of up to 256 bits and supports secure boot a nd authentication. To further boost the calculation performance for BLDC (FOC) motor control and DC/DC control systems, RL78/F23, F24 is equipped with the unique application accelerator IP to offload complex trigonometric and arithmetic processing. Please refer to the User's Manual: Hardware (R01UH0944EJ) for product details. R01DS0446EJ0120 Rev.1.20 Page 1 of 207 Dec 31, 2025 R01DS0446EJ0120 Rev.1.20 Dec 31, 2025 RL78/F23, F24 RENESAS MCU Datasheet 1. OVERVIEW

1.1 Features

 Minimum instruction execution time can be changed from high speed (0.025 µs: @ 40 MHz operation with high-speed on-chip oscillator clock or PLL clock) to ultra low-speed (66.6 µs: @ 15 kHz operation with low-speed on-chip oscillator clock)  General-purpose register: 8 bits × 32 registers (8 bits × 8 registers × 4 banks)  ROM: 128 KB / 256 KB  RAM: 12 KB / 24 KB  Data flash memory: 8 KB / 16 KB  High-speed on-chip oscillator clock Selectable from 40 MHz (Typ.), 32 MHz (Typ.), 20 MHz (Typ.), 16 MHz (Typ.), 8 MHz (Typ.), 4 MHz (Typ.), and 2 MHz (Typ.) (Selectable from 80 MHz (Typ.) and 64 MHz (Typ.) when using Timer RDe and RS-CANFD lite Note 1 )  Low-speed on-chip oscillator clock: 15 kHz × 2 ch (one for WWDT and one for CPU and peripherals other than WWDT)  On-chip PLL  On-chip single-power-supply flash memory (with prohibition of block erase/writing function)  Self-programming (with boot swap function/flash shield window function)  On-chip debug function  On-chip power-on-reset (POR) circuit and voltage detector (LVD)  On-chip watchdog timer (operable with the dedicated low-speed on-chip oscillator clock)  Multiply/divide/multiply & accumulate instructions are supported 16 bits × 16 bits = 32 bits (Unsigned or signed) 32 bits ÷ 32 bits = 32 bits (Unsigned) 16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed)  On-chip BCD adjustment  I/O ports: 28 to 92 (including one input-only pin)  Timer - 16-bit timer array unit: 12 channels / 16 channels - 16-bit timer RDe: 2 channels (with PWMOPA and Dithering / Gate function) - 16-bit timer RJ: 1 channel - Watchdog timer: 1 channel - Real-time clock: 1 channel  12-bit resolution A/D converter: 10 to 31 channels  Application accelerator unit  Serial interface - CSI - UART/UART (LIN-bus supported) - LIN module (master/slave supported) - I2C/simplified I2C - CAN interface (RS-CANFD lite) Note 2  DTC (Max. 44 sources)  ELC (Max. 26 channels for event link source, Max. 10 channels for event link destination) Note 2  8-bit D/A converter Note 2  On-chip comparator: 1 unit (input pin: 4 channels) Note 2  On-chip key interrupt function  On-chip clock output/buzzer output controller  Functional safety (CRC calculation, Clock monitor, AD test, etc.)  ASIL level: ASIL-B  Security functions (Secur e boot, Crypto engine (AES- 128, 192, 256), Random Number Generator (TRNG))  Power supply voltage: VDD = 2.7 to 5.5 V  Operating ambient temperature: TA = −40°C to 105°C (Grade-3) TA = −40°C to 125°C (Grade-4) TA = −40°C to 150°C (Grade-5) RL78/F23, F24 Block Diagram (Outline) Notes 1. fIH cannot be used as a RS-CANFD lite communication clock. 2. Only available in the RL78/F24. 3. FOC: Field Oriented Control (BLDC motor vector control method)

Applications

General automotive electrical applications (motor control, door control, headlight contro l, etc.), motorcycle engine control. System Data Transfer Controller (DTC) (ELC) Clock Monitor PLL (80 MHz) Internal Oscillator 15 kHz Internal Oscillator 80 MHz Internal Oscillator 20 MHz Ext. Sub Oscillator 32.7 kHz Ext. Interrupt Key Return Power On Reset (POR) Low Voltage Detector (LVD) On-Chip Debug (Hot plug-in, Live debug) 16-bit CPU RL78 Core MUL / MAC / DIV instructions Memory Code Flash RAM Data Flash Generic Timers Enhanced Timer RD Real Time Clock (RTC)Timer Array Unit Timer RJ Dithering Function Safety + Security ISO 26262 ASIL B Evita-Light Interface CAN FD LIN/UART Serial Array Unit (CSI, UART, Simplified I2C) Multi-master I2C Accelerator SIN. COS, Clarke/Park transformation , PI control , 32-bit Multiplier Analog 12-bit ADC (with dedicated S&H) 8-bit DAC Comparator Note 2 Note 2 Note 2 F23: 8 KB/ F24: 16 KB F23: 12 KB/ F24: 24 KB F23: 128 KB/ F24: 256 KB Note 3 FOC Assist Function 40 MHz, 2.7 V to 5.5 V Ta = -40 to +150 ℃ (Grade-5)Note 2Event Link Controller

RL78/F23, F24 1. OVERVIEW R01DS0446EJ0120 Rev.1.20 Page 2 of 207 Dec 31, 2025

1.2 Product Lineup

Table 1-1. RL78/F23, F24 Lineup (Grade-3) Operating Temperature (TA) Code Flash / Data Flash / RAM Code Flash / Data Flash / RAM 128KB / 8KB / 12KB 256KB / 16KB / 24KB −40°C to 105°C HWQFN 32 R7F123FBG3ANP-C R7F124FBJ3ANP-C LFQFP

48 R7F123FGG3AFB-C R7F124FGJ3AFB-C

64 R7F123FLG3AFB-C R7F124FLJ3AFB-C

80 R7F123FMG3AFB-C R7F124FMJ3AFB-C

100 ‒ R7F124FPJ3AFB-C Table 1-2. RL78/F23, F24 Lineup (Grade-4) Operating Temperature (TA) Code Flash / Data Flash / RAM Code Flash / Data Flash / RAM 128KB / 8KB / 12KB 256KB / 16KB / 24KB −40°C to 125°C HWQFN 32 R7F123FBG4ANP-C R7F124FBJ4ANP-C LFQFP

48 R7F123FGG4AFB-C R7F124FGJ4AFB-C

64 R7F123FLG4AFB-C R7F124FLJ4AFB-C

80 R7F123FMG4AFB-C R7F124FMJ4AFB-C

100 ‒ R7F124FPJ4AFB-C Table 1-3. RL78/F23, F24 Lineup (Grade-5) Note Operating Temperature (TA) Code Flash / Data Flash / RAM Code Flash / Data Flash / RAM 128KB / 8KB / 12KB 256KB / 16KB / 24KB −40°C to 150°C HWQFN 32 R7F123FBG5ANP-C R7F124FBJ5ANP-C LFQFP

48 R7F123FGG5AFB-C R7F124FGJ5AFB-C

64 R7F123FLG5AFB-C R7F124FLJ5AFB-C

80 R7F123FMG5AFB-C R7F124FMJ5AFB-C

100 ‒ R7F124FPJ5AFB-C Note To order grade-5 specification, pl ease provide the order code and the application temperature mission profile for verification to Renesas Support. <R> <R> <R> <R> <R> <R>

RL78/F23, F24 1. OVERVIEW R01DS0446EJ0120 Rev.1.20 Page 3 of 207 Dec 31, 2025

1.3 Function Overview

1.3.1 RL78/F24 Functions List

Table 1-4. RL78/F24 Functions List (1/2) Function Items Series Name R7F124FPJ R7F124FM J R7F124FLJ R7F124FGJ R7F124FBJ Pin Count 100 pins 80 pins 64 pins 48 pins 32 pins Code flash 256 KB Data flash 16 KB RAM 24 KB Supply voltage range 2.7 V to 5.5 V Maximum operation frequency 40 MHz System clock Main system clock oscillator Crystal / ceramic / square wave 2 to 20 MHz (operating at 2.7 V to 5.5 V) High-speed on-chip oscillator Normal high accuracy 40 MHz (typ.) Low-speed on-chip oscillator For low-speed operation 15 kHz (typ.) Subsystem clock oscillator 32.768 kHz Note 6 None PLL Yes Clock for peripherals Low-speed on-chip oscillator For peripherals other than WDT 15 kHz (typ.) For WDT 15 kHz (typ.) POR When power supply is rising 1.56 V (typ.) When power supply is falling 1.55 V (typ.) LVD V DD voltage detection When power supply is rising 2.81 V (typ.) to 4.74 V (typ.) (in 6 steps) When power supply is falling 2.75 V (typ.) to 4.64 V (typ.) (in 6 steps) Functional safety Note 7 WWDT (window watchdog timer) Yes Flash memory fast CRC operation function Yes General purpose CRC operation Yes Flash memory ECC function Yes RAM 1-bit error correction function Yes RAM 2-bit error detection function Yes RS-CANFD lite RAM 1-bit error correction function Yes RS-CANFD lite RAM 2-bit error detection function Yes Invalid memory access detection function Yes Frequency detection function Yes Clock monitor function Yes Stack pointer monitor function Yes A/D test function Yes I/O ports Input/Outpu t CMOS 86 ch 68 ch 52 ch 38 ch 25 ch Output CMOS 1 ch None Input Shared with oscillator pins 4 ch Note 6 2 ch Input only 1ch Power supply pins For internal circuits VDD, VSS, REGC For I/O ports EVDD0, EVSS0 EVDD1, EVSS1 EVDD0, EVSS0 None For analog circuits (AD, DA, COMP) V DD, VSS (AVREFP, AVREFM for AD) Multiply/divide and multiply- accumulate functions Multiply 16 bits × 16 bits (signed) 16 bits × 16 bits (unsigned) Divide 32 bits ÷ 32 bits (unsigned) Multiply-accumulate 16 bits × 16 bits + 32 bits (signed) 16 bits × 16 bits + 32 bits (unsigned) Arithmetic instructions (extended instruction set) Yes Vectored interrupt sources External 16 ch Notes 4, 5 16 ch Notes 4, 5 15 ch Notes 3, 5 14 ch Note 2 10 ch Note 1 Internal 53 ch Note 4 53 ch Note 4 53 ch Note 3 53 ch Note 2 53 ch Note 1 Key return detection 8 ch 6 ch DTC 44 sources 43 sources Timer TAU 16 bits (8 ch × 2) RTC 1 ch Timer RJ 16 bits × 1 Timer RDe 16 bits × 2 (with PWMOPA and dithering / gate function) (Notes are listed on the next page.)

RL78/F23, F24 1. OVERVIEW R01DS0446EJ0120 Rev.1.20 Page 4 of 207 Dec 31, 2025 Table 1-4. RL78/F24 Functions List (2/2) Function Items Series Name R7F124FPJ R7F124FMJ R7F124FLJ R7F124FGJ R7F124FBJ Pin Count 100 pins 80 pins 64 pins 48 pins 32 pins Serial I/F CSI / simplified I 2C / UART 4 ch / 4 ch / 2 ch 3 ch / 3 ch / 2 ch SPI Yes Multimaster I2C 1 ch LIN/UART module (RLIN3) 2 ch CAN interface (RS-CANFD lite) 1 ch A/D converter 12 bit High speed 16 ch 16 ch 16 ch 13 ch 8 ch Normal speed 15 ch 9 ch 8 ch 6 ch 2 ch Internal 1 ch (Internal reference voltage) D/A converter 8-bit 1 ch Comparator 1 unit (input 4 ch) ELC Link source: 26 ch Link destination: 10 ch PCLBUZ 1 ch None Application accelerator unit Yes Self-programming Yes On-chip debug Trace Yes Hot plug-in Yes Option byte Yes Security functions AESEA ECB/CBC mode and CMAC (AES-128, 192, 256) Random number generator (TRNG) Yes Notes 1. The following pairs of internal and external sources are each counted as a single source in this number: INTP4 and INTSPM, INTP5 and INTCMP0. 2. The following pairs of internal and external sources are each counted as a single source in this number: INTP4 and INTSPM, INTP5 and INTCMP0, INTP6 and INTTM11H, INTP7 and INTTM13H, INTP8 and INTRTC, INTP9 and INTTM01H. 3. The following pairs of internal and external sources are each counted as a single source in this number: INTP4 and INTSPM, INTP5 and INTCMP0, INTP6 and INTTM11H, INTP7 and INTTM13H, INTP8 and INTRTC, INTP9 and INTTM01H, INTP10 and INTTM03H. 4. The following pairs of internal and external sources are each counted as a single source in this number: INTP4 and INTSPM, INTP5 and INTCMP0, INTP6 and INTTM11H, INTP7 and INTTM13H, INTP8 and INTRTC, INTP9 and INTTM01H, INTP10 and INTTM03H, INTP13 and INTCLM. 5. Both sources in the following pairs are counted as a single source in this number: INTP11 and INTLIN0WUP, INTP12 and INTLIN1WUP. 6. Do not use the XT1 and XT2 pin functions in grade-5 products. 7. These functions are provided but they are not Safety Mechanism. ・Illegal instruction execution detection function ・SFR/RAM guard function ・I/O port output signal level detection function

RL78/F23, F24 1. OVERVIEW R01DS0446EJ0120 Rev.1.20 Page 5 of 207 Dec 31, 2025

1.3.2 RL78/F23 Functions List

Table 1-5. RL78/F23 Functions List (1/2) Function Items Series Name R7F123FMG R7F123FLG R7F123FGG R7F123FBG Pin Count 80 pins 64 pins 48 pins 32 pins Code flash 128 KB Data flash 8 KB RAM 12 KB Supply voltage range 2.7 V to 5.5 V Maximum operation frequency 40 MHz System clock Main system clock oscillator Crystal / ceramic / square wave 2 to 20 MHz (operating at 2.7 V to 5.5 V) High-speed on-chip oscillator Normal high accuracy 40 MHz (typ.) Low-speed on-chip oscillator For low-speed operation 15 kHz (typ.) Subsystem clock oscillator 32.768 kHz Note 6 None PLL Yes Clock for peripherals Low-speed on-chip oscillator For peripherals other than WDT 15 kHz (typ.) For WDT 15 kHz (typ.) POR When power supply is rising 1.56 V (typ.) When power supply is falling 1.55 V (typ.) LVD V DD voltage detection When power supply is rising 2.81 V (typ.) to 4.74 V (typ.) (in 6 steps) When power supply is falling 2.75 V (typ.) to 4.64 V (typ.) (in 6 steps) Functional safety Note 7 WWDT (window watchdog timer) Yes Flash memory fast CRC operation function Yes General purpose CRC operation Yes Flash memory ECC function Yes RAM 1-bit error correction function Yes RAM 2-bit error detection function Yes Invalid memory access detection function Yes Frequency detection function Yes Clock monitor function Yes Stack pointer monitor function Yes A/D test function Yes I/O ports Input/Outpu t CMOS 68 ch 52 ch 38 ch 25 ch Output CMOS 1 ch None Input Shared with oscillator pins 4ch Note 6 2 ch Input only 1 ch Power supply pins For internal circuits VDD, VSS, REGC For I/O ports EV DD0, EVSS0 None For analog circuits (AD) V DD, VSS (AVREFP, AVREFM for AD) Multiply/divide and multiply- accumulate functions Multiply 16 bits × 16 bits (signed) 16 bits × 16 bits (unsigned) Divide 32 bits ÷ 32 bits (unsigned) Multiply-accumulate 16 bits × 16 bits + 32 bits (signed) 16 bits × 16 bits + 32 bits (unsigned) Arithmetic instructions (extended instruction set) Yes Vectored interrupt sources External 15 ch Note 4, 5 14 ch Note3, 5 12 ch Note 2 8 ch Note 1 Internal 38 ch Note 4 38 ch Note 3 38 ch Note 2 38 ch Note 1 Key return detection 8 ch 6 ch DTC 36 sources 35 sources Timer TAU 16 bits (8 ch + 4 ch) RTC 1 ch Timer RJ 16 bits × 1 Timer RDe 16 bits × 2 (with PWMOPA and dithering / gate function) (Notes are listed on the next page.)

RL78/F23, F24 1. OVERVIEW R01DS0446EJ0120 Rev.1.20 Page 6 of 207 Dec 31, 2025 Table 1-5. RL78/F23 Functions List (2/2) Function Items Series Name R7F123FMG R7F 123FLG R7F123FGG R7F123FBG Pin Count 80 pins 64 pins 48 pins 32 pins Serial I/F CSI/simplified I 2C /UART 4 ch / 4 ch / 2 ch 3 ch / 3 ch / 2 ch SPI Yes Multimaster I2C 1 ch LIN/UART module (RLIN3) 1 ch CAN interface (RS-CANFD lite) None A/D converter 12 bit High Speed 16 ch 16 ch 13 ch 8 ch Normal Speed 9 ch 8 ch 6 ch 2 ch Internal 1 ch (Internal reference voltage) D/A converter 8-bit None Comparator None ELC None PCLBUZ 1 ch None Application accelerator unit Yes Self-programming Yes On-chip debug Trace Yes Hot plug-in Yes Option byte Yes Security Functions AESEA ECB/CBC mode and CMAC (AES-128, 192, 256) Random Number Generator (TRNG) Yes Notes 1. The following pairs of internal and external sources are each counted as a single source in this number: INTP4 and INTSPM. 2. The following pairs of internal and external sources are each counted as a single source in this number: INTP4 and INTSPM, INTP6 and INTTM11H, INTP7 and INTTM13H, INTP8 and INTRTC, INTP9 and INTTM01H. 3. The following pairs of internal and external sources are each counted as a single source in this number: INTP4 and INTSPM, INTP6 and INTTM11H, INTP7 and INTTM13H, INTP8 and INTRTC, INTP9 and INTTM01H, INTP10 and INTTM03H. 4. The following pairs of internal and external sources are each counted as a single source in this number: INTP4 and INTSPM, INTP6 and INTTM11H, INTP7 and INTTM13H, INTP8 and INTRTC, INTP9 and INTTM01H, INTP10 and INTTM03H, INTP13 and INTCLM. 5. INTP11 and INTLIN0WUP are counted as a single source bec ause using them at the same time is not possible. 6. Do not use the XT1 and XT2 pin functions in grade-5 products. 7. These functions are provided but they are not Safety Mechanism. ・Illegal instruction execution detection function ・SFR/RAM guard function ・I/O port output signal level detection function

RL78/F23, F24 1. OVERVIEW R01DS0446EJ0120 Rev.1.20 Page 7 of 207 Dec 31, 2025

1.4 Block Diagram

1.4.1 RL78/F24: Block Diagram of R7F124FPJ 100-pin Products

Figure 1-1. Block Diagram of RL78/F24 100-pin Product Caution Do not use the XT1 and XT2 pin functions in Grade-5 products. TAU0 (8ch) RESOUT REGC WWDT Clock Generator Reset Generator Low-speed OCO (for WDT) Sub OSC CLM PLL POR/ LVD Low-speed OCO High-speed OCO Voltage REGULATOR CRC Main OSC RESET ELC CODE FLASH DATA FLASH OCD BCD AAU INT DTC RAM AESEA TRNG PORT0 PORT1 PORT3 PORT4 PORT5 PORT6 PORT8 PORT9 PORT10 PORT12 PORT13 PORT14 PORT15 8 PCL/BUZ KEY RETURN (8ch) Exte rnal INT (14ch) RTC 12-bit ADC (31ch) Comparator 0 (1unit) IICA0 (1ch) STANDBY ch00 ch01 TRJ TRDe (2ch) ch0 SAU0 (2ch) UART0 CSI00 CSI01 IIC00 IIC01 TI00 TO00 TI01 TO01 ch02TI02 TO02 ch03TI03 TO03 ch04TI04 TO04 ch05TI05 TO05 ch06TI06 TO06 ch07TI07 TO07 TAU1 (8ch) ch10 ch11 TI10 TO10 TI11 TO11 ch12TI12 TO12 ch13TI13 TO13 ch14TI14 TO14 ch15TI15 TO15 ch16TI16 TO16 ch17TI17 TO17 CAN (1ch) LIN0 (1ch) LIN1 (1ch) 8-bit DAC (1ch) P00-P03 P10-P17 P30-P34 P40-P47 P50-P57 P60-P67 PORT7 8 P70-P77 P80-P87 P90-P97 P100-P107 P120, P125-P127 P130 P137 P140 P121-P1244 P150-P157 ANI0-ANI30 AVREFP AVREFM KR0-KR7 ANO0 VCOUT0 IVCMP00 IVCMP01 IVCMP02 IVREF0/IVCMP03 TRJO0 TRJIO0 TRDIOA0/TRDCLK0 TRDIOB0 TRDIOC0 TRDIOD0 TRD0RES TRDIOA1 TRDIOB1 TRDIOC1 TRDIOD1 TRD1RES ch1 CRXD0 CTXD0 LRXD0 LTXD0 LRXD1 LTXD1 RXD0 TXD0 SCK00 SI00 SO00 SSI00 SCK01 SI01 SO01 SSI01 SCL00 SDA00 SCL01 SDA01 SCLA0 SDAA0 SNZOUT0-SNZOUT7 STOPST RTC1HZ INTP0-INTP13 PCLBUZ0 SAU1 (2ch) UART1 CSI10 CSI11 IIC10 IIC11 RXD1 TXD1 SCK10 SI10 SO10 SSI10 SCK11 SI11 SO11 SSI11 SCL10 SDA10 SCL11 SDA11 RL78 CPU CORE Multiplier, Divider and Multiply- Accumulator TOOL0 TOOL0 TXD TOOL0 RXD XT1 XT2/EX CLKS X2/EXCLK

RL78/F23, F24 1. OVERVIEW R01DS0446EJ0120 Rev.1.20 Page 8 of 207 Dec 31, 2025

1.4.2 RL78/F24: Block Diagram of R7F124FMJ 80-pin Products

Figure 1-2. Block Diagram of RL78/F24 80-pin Product Caution Do not use the XT1 and XT2 pin functions in Grade-5 products. TAU0 (8ch) RESOUT REGC WWDT Clock Generator Reset Generator Low-speed OCO (for WDT) Sub OSC CLM PLL POR/ LVD Low-speed OCO High-speed OCO Voltage REGULATOR CRC Main OSC RESET ELC CODE FLASH DATA FLASH OCD BCD AAU INT DTC RAM AESEA TRNG PORT0 PORT1 PORT3 PORT4 PORT5 PORT6 PORT8 PORT9 PORT12 PORT13 PORT14 PCL/BUZ KEY RETURN (8ch) Exte rnal INT (14ch) RTC 12-bit ADC (25ch) Comparator 0 (1unit) IICA0 (1ch) STANDBY ch00 ch01 TRJ TRDe (2ch) ch0 SAU0 (2ch) UART0 CSI00 CSI01 IIC00 IIC01 TI00 TO00 TI01 TO01 ch02TI02 TO02 ch03TI03 TO03 ch04TI04 TO04 ch05TI05 TO05 ch06TI06 TO06 ch07TI07 TO07 TAU1 (8ch) ch10 ch11 TI10 TO10 TI11 TO11 ch12TI12 TO12 ch13TI13 TO13 ch14TI14 TO14 ch15TI15 TO15 ch16TI16 TO16 ch17TI17 TO17 CAN (1ch) LIN0 (1ch) LIN1 (1ch) 8-bit DAC (1ch) P00-P02 P10-P17 P30-P34 P40-P47 P50-P57 P60-P67 PORT7 8 P70-P77 P80-P87 P90-P97 P120, P125, P126 P130 P137 P140 P121-P1244

25 ANI0-ANI17, ANI24-ANI30

SAU1 (2ch) UART1 CSI10 CSI11 IIC10 IIC11 RXD1 TXD1 SCK10 SI10 SO10 SSI10 SCK11 SI11 SO11 SSI11 SCL10 SDA10 SCL11 SDA11 RL78 CPU CORE Multiplier, Divider and Multiply- Accumulator TOOL0 TOOL0 TXD TOOL0 RXD XT1 XT2/EXCLKS X2/EXCLK

RL78/F23, F24 1. OVERVIEW R01DS0446EJ0120 Rev.1.20 Page 9 of 207 Dec 31, 2025

1.4.3 RL78/F24: Block Diagram of R7F124FLJ 64-pin Products

Figure 1-3. Block Diagram of RL78/F24 64-pin Product Caution Do not use the XT1 and XT2 pin functions in Grade-5 products. TAU0 (8ch) RESOUT REGC WWDT Clock Generator Reset Generator Low-speed OCO (for WDT) Sub OSC CLM PLL POR/ LVD Low-speed OCO High-speed OCO Voltage REGULATOR CRC Main OSC RESET ELC CODE FLASH DATA FLASH OCD BCD AAU INT DTC RAM AESEA TRNG PORT0 PORT1 PORT3 PORT4 PORT5 PORT6 PORT8 PORT9 PORT12 PORT13 PORT14 PCL/BUZ KEY RETURN (8ch) Exte rnal INT (13ch) RTC 12-bit ADC (24ch) Comparator 0 (1unit) IICA0 (1ch) STANDBY ch00 ch01 TRJ TRDe (2ch) ch0 SAU0 (2ch) UART0 CSI00 CSI01 IIC00 IIC01 TI00 TO00 TI01 TO01 ch02TI02 TO02 ch03TI03 TO03 ch04TI04 TO04 ch05TI05 TO05 ch06TI06 TO06 ch07TI07 TO07 TAU1 (8ch) ch10 ch11 TI10 TO10 TI11 TO11 ch12TI12 TO12 ch13TI13 TO13 ch14TI14 TO14 ch15TI15 TO15 ch16TI16 TO16 ch17TI17 TO17 CAN (1ch) LIN0 (1ch) LIN1 (1ch) 8-bit DAC (1ch) TOOL0 TOOL0 TXD TOOL0 RXD P00 P10-P17 P30-P34 P40-P43 P50-P53 P60-P63 PORT7 8 P70-P77 P80-P87 P90-P96 P120, P125 P130 P137 P140 P121-P1244

24 ANI0-ANI16, ANI24-ANI30

RL78/F23, F24 1. OVERVIEW R01DS0446EJ0120 Rev.1.20 Page 10 of 207 Dec 31, 2025

1.4.4 RL78/F24: Block Diagram of R7F124FGJ 48-pin Products

Figure 1-4. Block Diagram of RL78/F24 48-pin Product Caution Do not use the XT1 and XT2 pin functions in Grade-5 products. TAU0 (8ch) RESOUT REGC WWDT Clock Generator Reset Generator Low-speed OCO (for WDT) Sub OSC CLM PLL POR/ LVD Low-speed OCO High-speed OCO Voltage REGULATOR CRC Main OSC RESET ELC CODE FLASH DATA FLASH OCD BCD AAU INT DTC RAM AESEA TRNG PORT0 PORT1 PORT3 PORT4 PORT6 PORT8 PORT9 PORT12 PORT13 PORT14 PCL/BUZ KEY RETURN (8ch) Exte rnal INT (10ch) RTC 12-bit ADC (19ch) Comparator 0 (1unit) IICA0 (1ch) STANDBY ch00 ch01 TRJ TRDe (2ch) ch0 SAU0 (2ch) UART0 CSI00 CSI01 IIC00 IIC01 TI00 TO00 TI01 TO01 ch02TI02 TO02 ch03TI03 TO03 ch04TI04 TO04 ch05TI05 TO05 ch06TI06 TO06 ch07TI07 TO07 TAU1 (8ch) ch10 ch11 TI10 TO10 TI11 TO11 ch12TI12 TO12 ch13TI13 TO13 ch14TI14 TO14 ch15TI15 TO15 ch16TI16 TO16 ch17TI17 TO17 CAN (1ch) LIN0 (1ch) LIN1 (1ch) 8-bit DAC (1ch) P00 P10-P17 P30-P34 P40, P41 P60-P63 PORT7 4 P70-P73 P80-P87 P90-P92 P120, P125 P130 P137 P140 P121-P1244

19 ANI0-ANI12, ANI24-ANI29

SAU1 (2ch) UART1 CSI10 CSI11 IIC10 IIC11 RXD1 TXD1 SCK10 SI10 SO10 SCK11 SI11 SO11 SSI11 SCL10 SDA10 SCL11 SDA11 RL78 CPU CORE Multiplier, Divider and Multiply- Accumulator TOOL0 TOOL0 TXD TOOL0 RXD XT1 XT2/EXCLKS X2/EXCLK

RL78/F23, F24 1. OVERVIEW R01DS0446EJ0120 Rev.1.20 Page 11 of 207 Dec 31, 2025

1.4.5 RL78/F24: Block Diagram of R7F124FBJ 32-pin Products

Figure 1-5. Block Diagram of RL78/F24 32-pin Product TAU1 (8ch) TAU0 (8ch) REGC WWDT Clock Generator Reset Generator Low-speed OCO (for WDT) CLM PLL POR/ LVD Low-speed OCO High-speed OCO Voltage REGULATOR CRC Main OSC X1 X2/EXCLK RESET ELC CODE FLASH DATA FLASH OCD BCD AAU INT DTC RAM AESEA TRNG PORT1 PORT3 PORT4 PORT6 PORT8 PORT12 PORT13 KEY RETURN (6ch) External INT (6ch) RTC 12-bit ADC (10ch) Comparator 0 (1unit) IICA0 (1ch) STANDBY ch00 ch01 TRJ TRDe (2ch) ch0 SAU0 (2ch) UART0 CSI00 CSI01 IIC00 IIC01 TI00 TO00 TI01 TO01 ch02TI02 TO02 ch03TI03 TO03 ch04TI04 TO04 ch05TI05 TO05 ch06TI06 TO06 ch07TI07 TO07 ch10 ch11 TI10 TO10 TI11 TO11 ch12TI12 TO12 ch13TI13 TO13 CAN (1ch) LIN0 (1ch) LIN1 (1ch) 8-bit DAC (1ch) P10-P17 P30, P33, P34 P40, P41 P60-P63 P80-P85 P120, P125 P137 P121, P1222

10 ANI0-ANI7, ANI24, ANI25

SAU1 (2ch) UART1 CSI10 IIC10 RXD1 TXD1 SCK10 SI10 SO10 SCL10 SDA10 RL78 CPU CORE Multiplier, Divider and Multiply- Accumulator TOOL0 TOOL0 TXD TOOL0 RXD ch14 ch15 ch16 ch17

RL78/F23, F24 1. OVERVIEW R01DS0446EJ0120 Rev.1.20 Page 12 of 207 Dec 31, 2025

1.4.6 RL78/F23: Block Diagram of R7F123FMG 80-pin Products

Figure 1-6. Block Diagram of RL78/F23 80-pin Product Caution Do not use the XT1 and XT2 pin functions in Grade-5 products. TAU0 (8ch) REGC WWDT Clock Generator Reset Generator Low-speed OCO (for WDT) CLM PLL POR/ LVD Low-speed OCO High-speed OCO Voltage REGULATOR CRC Main OSC RESET CODE FLASH DATA FLASH OCD BCD AAU INT DTC RAM AESEA TRNG PORT1 PORT3 PORT4 PORT5 PORT6 PORT8 PORT9 PORT12 PORT13 PORT14 PCL/BUZ KEY RETURN (8ch) External INT (16ch) RTC 12-bit ADC (25ch) IICA0 (1ch) STANDBY ch00 ch01 TRJ TRDe (2ch) ch0 SAU0 (2ch) UART0 CSI00 CSI01 IIC00 IIC01 TI00 TO00 TI01 TO01 ch02TI02 TO02 ch03TI03 TO03 ch04TI04 TO04 ch05TI05 TO05 ch06TI06 TO06 ch07TI07 TO07 TAU1 (4ch) ch10 ch11 TI10 TO10 TI11 TO11 ch12TI12 TO12 ch13TI13 TO13 LIN0 (1ch) P10-P17 P30-P34 P40-P47 P50-P57 P60-P67 PORT7 8 P70-P77 P80-P87 P90-P97 P12 0, P12 5, P12 6 P130 P137 P140 P121-P1244 Multiplier, Divider and Multiply- Accumulator TOOL0 TOOL0 TXD TOOL0 RXD PORT0 3 P00-P02 Sub OSC XT1 XT2/EXCLKS X2/EXCLK RESOUT SAU1 (2ch) UART1 CSI10 CSI11 IIC10 IIC11 RXD1 TXD1 SCK10 SI10 SO10 SSI10 SCK11 SI11 SO11 SSI11 SCL10 SDA10 SCL11 SDA11

RL78/F23, F24 1. OVERVIEW R01DS0446EJ0120 Rev.1.20 Page 13 of 207 Dec 31, 2025

1.4.7 RL78/F23: Block Diagram of R7F123FLG 64-pin Products

Figure 1-7. Block Diagram of RL78/F23 64-pin Product Caution Do not use the XT1 and XT2 pin functions in Grade-5 products. TAU0 (8ch) REGC WWDT Clock Generator Reset Generator Low-speed OCO (for WDT) CLM PLL POR/ LVD Low-speed OCO High-speed OCO Voltage REGULATOR CRC Main OSC RESET CODE FLASH DATA FLASH OCD BCD AAU INT DTC RAM AESEA TRNG PORT1 PORT3 PORT4 PORT5 PORT6 PORT8 PORT9 PORT12 PORT13 PORT14 PCL/BUZ KEY RETURN (8ch) External INT (13ch) RTC 12-bit ADC (24ch) IICA0 (1ch) STANDBY ch00 ch01 TRJ TRDe (2ch) ch0 SAU0 (2ch) UART0 CSI00 CSI01 IIC00 IIC01 TI00 TO00 TI01 TO01 ch02TI02 TO02 ch03TI03 TO03 ch04TI04 TO04 ch05TI05 TO05 ch06TI06 TO06 ch07TI07 TO07 TAU1 (4ch) ch10 ch11 TI10 TO10 TI11 TO11 ch12TI12 TO12 ch13TI13 TO13 LIN0 (1ch) P10-P17 P30-P34 P40-P43 P50-P53 P60-P63 PORT7 8 P70-P77 P80-P87 P90-P96 P120, P125 P130 P137 P140 P121-P1244 Multiplier, Divider and Multiply- Accumulator TOOL0 TOOL0 TXD TOOL0 RXD PORT0 P00 Sub OSC RESOUT SAU1 (2ch) UART1 CSI10 CSI11 IIC10 IIC11 RXD1 TXD1 SCK10 SI10 SO10 SSI10 SCK11 SI11 SO11 SSI11 SCL10 SDA10 SCL11 SDA11 XT1 XT2/EXCLKS X2/EXCLK

RL78/F23, F24 1. OVERVIEW R01DS0446EJ0120 Rev.1.20 Page 14 of 207 Dec 31, 2025

1.4.8 RL78/F23: Block Diagram of R7F123FGG 48-pin Products

Figure 1-8. Block Diagram of RL78/F23 48-pin Product Caution Do not use the XT1 and XT2 pin functions in Grade-5 products. TAU0 (8ch) REGC WWDT Clock Generator Reset Generator Low-speed OCO (for WDT) CLM PLL POR/ LVD Low-speed OCO High-speed OCO Voltage REGULATOR CRC Main OSC RESET CODE FLASH DATA FLASH OCD BCD AAU INT DTC RAM AESEA TRNG PORT1 PORT3 PORT4 PORT6 PORT8 PORT9 PORT12 PORT13 PORT14 PCL/BUZ KEY RETURN (8ch) External INT (10ch) RTC 12-bit ADC (19ch) IICA0 (1ch) STANDBY ch00 ch01 TRJ TRDe (2ch) ch0 SAU0 (2ch) UART0 CSI00 CSI01 IIC00 IIC01 TI00 TO00 TI01 TO01 ch02TI02 TO02 ch03TI03 TO03 ch04TI04 TO04 ch05TI05 TO05 ch06TI06 TO06 ch07TI07 TO07 TAU1 (4ch) ch10 ch11 TI10 TO10 TI11 TO11 ch12TI12 TO12 ch13TI13 TO13 LIN0 (1ch) P10-P17 P30-P34 P40, P41 P60-P63 PORT7 4 P70-P73 P80-P87 P90-P92 P120, P125 P130 P137 P140 P121-P1244 Multiplier, Divider and Multiply- Accumulator TOOL0 TOOL0 TXD TOOL0 RXD PORT0 P00 Sub OSC RESOUT SAU1 (2ch) UART1 CSI11 IIC10 IIC11 RXD1 TXD1 SCK11 SI11 SO11 SSI11 SCL10 SDA10 SCL11 SDA11 CSI10 SCK10 SI10 SO10 XT1 XT2/EXCLKS X2/EXCLK

RL78/F23, F24 1. OVERVIEW R01DS0446EJ0120 Rev.1.20 Page 15 of 207 Dec 31, 2025

1.4.9 RL78/F23: Block Diagram of R7F123FBG 32-pin Products

Figure 1-9. Block Diagram of RL78/F23 32-pin Product TAU0 (8ch) REGC WWDT Clock Generator Reset Generator Low-speed OCO (for WDT) CLM PLL POR/ LVD Low-speed OCO High-speed OCO Voltage REGULATOR CRC Main OSC RESET CODE FLASH DATA FLASH OCD BCD AAU INT DTC RAM AESEA TRNG PORT1 PORT3 PORT4 PORT6 PORT8 PORT12 PORT13 KEY RETURN (6ch) Exte rnal INT (6ch) RTC 12-bit ADC (10ch) IICA0 (1ch) STANDBY ch00 ch01 TRJ TRDe (2ch) ch0 SAU0 (2ch) UART0 CSI00 CSI01 IIC00 IIC01 TI00 TO00 TI01 TO01 ch02TI02 TO02 ch03TI03 TO03 ch04TI04 TO04 ch05TI05 TO05 ch06TI06 TO06 ch07TI07 TO07 TAU1 (4ch) ch10 ch11 TI10 TO10 TI11 TO11 ch12TI12 TO12 ch13TI13 TO13 LIN0 (1ch) P10-P17 P30, P33, P34 P40, P41 P60-P63 P80-P85 P120, P125 P137 P121, P1222 Multiplier, Divider and Multiply- Accumulator TOOL0 TOOL0 TXD TOOL0 RXD X1 X2/EXCLK SAU1 (2ch) UART1 CSI10 IIC10 RXD1 TXD1 SCK10 SI10 SO10 SCL10 SDA10

RL78/F23, F24 1. OVERVIEW R01DS0446EJ0120 Rev.1.20 Page 16 of 207 Dec 31, 2025

1.5 Pin Configurations

1.5.1 RL78/F24 Pin Configuration for 100-pin Products

RL78/F24: 100-pin Plastic QFP (Fine Pitch) (14 × 14) Figure 1-10. RL78/F24 Pin Configuration for 100-pin Products Caution Do not use the XT1 and XT2 pin functions in grade-5 products. Remark Functions in parentheses in the above figure can be assigned via settings in t he peripheral I/O redirection registers (PIORx). Only the STOPST function of P52 can be assi gned via settings in the STOP status output control register (STPSTC). 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 76 50 77 49 78 48 79 47 80 46 81 45 82 44 83 43 84 42 85 41 86 40 87 39 88 38 89 37 90 36 91 35 92 34 93 33 94 32 95 31 96 30 97 29 98 28 99 27 100 26 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 92 02 12 22 32 42 5 EVDD0 P60 / (TO01) / (SCK00) / (SCL00) P61 / (TO02) / (SI00) / (SDA00) / (RXD0) P123 / XT1 P137 / INTP0 P122 / X2 / EXCLK P121 / X1 REGC VSS P43 / (LRXD0) P42 / (LTXD0) P41 / VCOUT0 / TI10 / TO10 / TRJIO0 / TRD0RES / (SI10) / (RXD1) / SNZOUT2 P126 / (TI01) / (TO01) P65 / (TI16) / (TO16) / (SNZOUT2) P01 / (TI04) / (TO04) P64 / (TI14) / (TO14) / (SNZOUT3) P125 / ANI24 / TI03 / TO03 / TRDIOB0 / SSI01 / (LRXD1) / INTP1 / SNZOUT1 P63 / (TO07) / (SSI00) / SDAA0 P40 / TOOL0 RESET P124 / XT2 / EXCLKS P120 / ANI25 / TI07 / TO07 / TRDIOD0 / SO01 / (SCK10) / (LTXD1) / INTP4 P62 / (TO03) / (SO00) / (TXD0) / SCLA0 P153 / (SCK11) P152 / (SI11) P151 / (SO11) P150 / (SSI11) P47 / INTP13 EVSS0 VDD P103 / ANI21 P154 / (SNZOUT7) P97 / ANI17 (QFP) P157 / (SNZOUT4) P100 / ANI18 P156 / (SNZOUT5) P101 / ANI19 P00 / (TI05) / (TO05) / INTP9 P102 / ANI20 P155 / (SNZOUT6) P93 / ANI13 100pin P76 / (SCK10) / KR6 P94 / ANI14 P77 / (SSI10) / INTP12 / KR7 P95 / ANI15 P130 / RESOUT P96 / ANI16 P140 / TRD1RES / PCLBUZ0 P87 / ANI9 RL78/F24 P73 / ANI29 / SSI11 / (CRXD0) / SNZOUT7 / KR3 P90 / ANI10 EVSS1 P91 / ANI11 P74 / ANI30 / (SO10) / (TXD1) / KR4 P92 / ANI12 P75 / (SI10) / (RXD1) / KR5 P84 / ANI4 / IVCMP02 P70 / ANI26 / TI15 / TO15 / SI11 / SDA11 / INTP8 / SNZOUT4 / KR0 P85 / ANI5 / IVREF0 / IVCMP03 P71 / ANI27 / TI17 / TO17 / SCK11 / SCL11 / INTP6 / SNZOUT5 / KR1 P86 / ANI8 P72 / ANI28 / SO11 / (CTXD0) / SNZOUT6 / KR2 P17 / TI00 / TO00 / TRDIOB1 / SCK00 / SCL00 / INTP3 P81 / ANI1 P30 / TI01 / TO01 / TRDIOD1 / SSI00 / INTP2 / SNZOUT0 P82 / ANI2 / IVCMP00 P32 / TI16 / TO16 / (SO11) / INTP7 P83 / ANI3 / IVCMP01 P03 / (RTC1HZ) P51 / (SO01) / INTP11 P50 / (SSI01) / (INTP3) P31 / TI14 / TO14 / (INTP2) / STOPS T P15 / TI05 / TO05 / TRDIOA1 / (TRDIOA0) / (TRDCLK0) / SO00 / TXD0 / RTC1HZ / TOOLTXD EV DD1 P16 / TI02 / TO02 / TRDIOC1 / SI00 / SDA00 / RXD0 / TOOLRXD P11 / TI12 / TO12 / (TRDIOB0) / SI10 / SDA10 / RXD1 / CRXD0 / LRXD1 P12 / TI11 / TO11 / (TRDIOD0) / SO10 / TXD1 / INTP5 / SNZOUT3 P13 / TI04 / TO04 / TRDIOA0 / TRDCLK0 / SI01 / SDA01 / LTXD0 P14 / TI06 / TO06 / TRDIOC0 / SCK01 / SCL01 / LRXD0 P53 / (SI01) / INTP10 P52 / (SCK01) / (STOPST) P107 / (LRXD1) P57 / (TI17) / (TO17) / (SNZOUT0) P56 / (TI15) / (TO15) / (SNZOUT1) P54 / (TI11) / (TO11) / SSI10 P10 / TI13 / TO13 / TRJO0 / SCK10 / SCL10 / CTXD0 / LTXD1 P80 / ANI0 / ANO0 P34 / AV REFM / ANI7 P33 / AVREFP / ANI6 P104 / ANI22 P105 / ANI23 P106 / (LTXD1) <R>

RL78/F23, F24 1. OVERVIEW R01DS0446EJ0120 Rev.1.20 Page 17 of 207 Dec 31, 2025

1.5.2 RL78/F24 Pin Configuration for 80-pin Products

RL78/F24: 80-pin Plastic QFP (Fine Pitch) (12 × 12) Figure 1-11. RL78/F24 Pin Configuration for 80-pin Products Caution Do not use the XT1 and XT2 pin functions in grade-5 products. Remark Functions in parentheses in the above figure can be assigned via settings in t he peripheral I/O redirection registers (PIORx). Only the STOPST function of P52 can be assi gned via settings in the STOP status output control register (STPSTC). 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 40 62 39 63 38 64 37 65 36 66 35 67 34 68 33 69 32 70 31 71 30 72 29 73 28 74 27 75 26 76 25 77 24 78 23 79 22 80 21 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 EVSS0 VDD P137 / INTP0 P122 / X2 / EXCLK P121 / X1 REGC VSS P62 / (TO03) / (SO00) / (TXD0) / SCLA0 P125 / ANI24 / TI03 / TO03 / TRDIOB0 / SSI01 / (LRXD1) / INTP1 / SNZOUT1 P60 / (TO01) / (SCK00) / (SCL00) P120 / ANI25 / TI07 / TO07 / TRDIOD0 / SO01 / (SCK10) / (LTXD1) / INTP4 P47 / INTP13 P43 / (LRXD0) P42 / (LTXD0) P41 / VCOUT0 / TI10 / TO10 / TRJIO0 / TRD0RES / (SI10) / (RXD1) / SNZOUT2 EV DD0 P40 / TOOL0 RESET P124 / XT2 / EXCLKS P123 / XT1 P01 / (TI04) / (TO04) P61 / (TO02) / (SI00) / (SDA00) / (RXD0) P93 / ANI13 P00 / (TI05) / (TO05) / INTP9 P94 / ANI14 (QFP) P95 / ANI15 P66 / (TI00) / (TO00) P96 / ANI16 P65 / (TI16) / (TO16) / (SNZOUT2) P97 / ANI17 P64 / (TI14) / (TO14) / (SNZOUT3) P02 / (TI06) / (TO06) P63 / (TO07) / (SSI00) / SDAA0 P90 / ANI10 80pin P77 / (SSI10) / INTP12 / KR7 P91 / ANI11 P130 / RESOUT P92 / ANI12 P140 / TRD1RES / PCLBUZ0 P82 / ANI2 / IVCMP00 P71 / ANI27 / TI17 / TO17 / SCK11 / SCL11 / INTP6 / SNZOUT5 / KR1 P83 / ANI3 / IVCMP01 P72 / ANI28 / SO11 / (CTXD0) / SNZOUT6 / KR2 P84 / ANI4 / IVCMP02 RL78/F24 P73 / ANI29 / SSI11 / (CRXD0) / SNZOUT7 / KR3 P85 / ANI5 / IVREF0 / IVCMP03 P74 / ANI30 / (SO10) / (TXD1) / KR4 P86 / ANI8 P75 / (SI10) / (RXD1) / KR5 P87 / ANI9 P76 / (SCK10) / KR6 P17 / TI00 / TO00 / TRDIOB1 / SCK00 / SCL00 / INTP3 P30 / TI01 / TO01 / TRDIOD1 / SSI00 / INTP2 / SNZOUT0 P80 / ANI0 / ANO0 P32 / TI16 / TO16 / (SO11) / INTP7 P81 / ANI1 P70 / ANI26 / TI15 / TO15 / SI11 / SDA11 / INTP8 / SNZOUT4 / KR0 P52 / (SCK01) / (STOPST) P51 / (SO01) / INTP11 P50 / (SSI01) / (INTP3) P31 / TI14 / TO14 / (INTP2) / STOPST P15 / TI05 / TO05 / TRDIOA1 / (TRDIOA0) / (TRDCLK0) / SO00 / TXD0 / RTC1HZ / TOOLTXD P16 / TI02 / TO02 / TRDIOC1 / SI00 / SDA00 / RXD0 / TOOLRXD P10 / TI13 / TO13 / TRJO0 / SCK10 / SCL10 / CTXD0 / LTXD1 P11 / TI12 / TO12 / (TRDIOB0) / SI10 / SDA10 / RXD1 / CRXD0 / LRXD1 P12 / TI11 / TO11 / (TRDIOD0) / SO10 / TXD1 / INTP5 / SNZOUT3 P13 / TI04 / TO04 / TRDIOA0 / TRDCLK0 / SI01 / SDA01 / LTXD0 P14 / TI06 / TO06 / TRDIOC0 / SCK01 / SCL01 / LRXD0 P53 / (SI01) / INTP10 P34 / AV REFM / ANI7 P33 / AVREFP / ANI6 P57 / (TI17) / (TO17) / (SNZOUT0) P56 / (TI15) / (TO15) / (SNZOUT1) P54 / (TI11) / (TO11) / SSI10 <R>

RL78/F23, F24 1. OVERVIEW R01DS0446EJ0120 Rev.1.20 Page 18 of 207 Dec 31, 2025

1.5.3 RL78/F23 Pin Configuration for 80-pin Products

RL78/F23: 80-pin Plastic QFP (Fine Pitch) (12 × 12) Figure 1-12. RL78/F23 Pin Configuration for 80-pin Products Caution Do not use the XT1 and XT2 pin functions in grade-5 products. Remark Functions in parentheses in the above figure can be assigned via settings in t he peripheral I/O redirection registers (PIORx). Only the STOPST function of P52 can be assi gned via settings in the STOP status output control register (STPSTC). 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 40 62 39 63 38 64 37 65 36 66 35 67 34 68 33 69 32 70 31 71 30 72 29 73 28 74 27 75 26 76 25 77 24 78 23 79 22 80 21 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 92 0 P14 / TI06 / TO06 / TRDIOC0 / SCK01 / SCL01 / LRXD0 P53 / (SI01) / INTP10 P34 / AVREFM / ANI7 P33 / AVREFP / ANI6 P57 / (SNZOUT0) P56 / (SNZOUT1) P54 / (TI11) / (TO11) / SSI10 P17 / TI00 / TO00 / TRDIOB1 / SCK00 / SCL00 / INTP3 P30 / TI01 / TO01 / TRDIOD1 / SSI00 / INTP2 / SNZOUT0 P80 / ANI0 P32 / (SO11) / INTP7 P81 / ANI1 P70 / ANI26 / SI11 / SDA11 / INTP8 / SNZOUT4 / KR0 P52 / (SCK01) / (STOPST) P51 / (SO01) / INTP11 P50 / (SSI01) / (INTP3) P31 / (INTP2) / STOPST P15 / TI05 / TO05 / TRDIOA1 / (TRDIOA0) / (TRDCLK0) / SO00 / TXD0 / RTC1HZ / TOOLTXD P16 / TI02 / TO02 / TRDIOC1 / SI00 / SDA00 / RXD0 / TOOLRXD P10 / TI13 / TO13 / TRJO0 / SCK10 / SCL10 P11 / TI12 / TO12 / (TRDIOB0) / SI10 / SDA10 / RXD1 P12 / TI11 / TO11 / (TRDIOD0) / SO10 / TXD1 / INTP5 / SNZOUT3 P13 / TI04 / TO04 / TRDIOA0 / TRDCLK0 / SI01 / SDA01 / LTXD0 P82 / ANI2 P71 / ANI27 / SCK11 / SCL11 / INTP6 / SNZOUT5 / KR1 P83 / ANI3 P72 / ANI28 / SO11 / SNZOUT6 / KR2 P84 / ANI4 RL78/F23 P73 / ANI29 / SSI11 / SNZOUT7 / KR3 P85 / ANI5 P74 / ANI30 / (SO10) / (TXD1) / KR4 P86 / ANI8 P75 / (SI10) / (RXD1) / KR5 P87 / ANI9 P76 / (SCK10) / KR6 P90 / ANI10 80pin P77 / (SSI10) / INTP12 / KR7 P91 / ANI11 P130 / RESOUT P92 / ANI12 P140 / TRD1RES / PCLBUZ0 P01 / (TI04) / (TO04) P61 / (TO02) / (SI00) / (SDA00) / (RXD0) P93 / ANI13 P00 / (TI05) / (TO05) / INTP9 P94 / ANI14 (QFP) P95 / ANI15 P66 / (TI00) / (TO00) P96 / ANI16 P65 / (SNZOUT2) P97 / ANI17 P64 / (SNZOUT3) P02 / (TI06) / (TO06) P63 / (TO07) / (SSI00) / SDAA0 P126 / (TI01) / (TO01) P62 / (TO03) / (SO00) / (TXD0) / SCLA0 P125 / ANI24 / TI03 / TO03 / TRDIOB0 / SSI01 / INTP1 / SNZOUT1 P60 / (TO01) / (SCK00) / (SCL00) P120 / ANI25 / TI07 / TO07 / TRDIOD0 / SO01 / (SCK10) / INTP4 P47 / INTP13 P43 / (LRXD0) P42 / (LTXD0) P41 / TI10 / TO10 / TRJIO0 / TRD0RES / (SI10) / (RXD1) / SNZOUT2 EVDD0 P40 / TOOL0 RESET P124 / XT2 / EXCLKS P123 / XT1 EVSS0 VDD P137 / INTP0 P122 / X2 / EXCLK P121 / X1 REGC VSS <R>

RL78/F23, F24 1. OVERVIEW R01DS0446EJ0120 Rev.1.20 Page 19 of 207 Dec 31, 2025

1.5.4 RL78/F24 Pin Configuration for 64-pin Products

RL78/F24: 64-pin Plastic QFP (Fine Pitch) (10 × 10) Figure 1-13. RL78/F24 Pin Configuration for 64-pin Products Caution Do no use the XT1 and XT2 pin functions in grade-5 products. Remark Functions in parentheses in the above figure can be assigned via settings in t he peripheral I/O redirection registers (PIORx). Only the STOPST function of P52 can be assi gned via settings in the STOP status output control register (STPSTC). 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 32 50 31 51 30 52 29 53 28 54 27 55 26 56 25 57 24 58 23 59 22 60 21 61 20 62 19 63 18 64 17 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 P32 / TI16 / TO16 / (SO11) / INTP7 P14 / TI06 / TO06 / TRDIOC0 / SCK01 / SCL01 / LRXD0 P53 / (SI01) / INTP10 P52 / (SCK01) / (STOPST) P51 / (SO01) / INTP11 P50 / (SSI01) / (INTP3) P31 / TI14 / TO14 / (INTP2) / STOPS T P15 / TI05 / TO05 / TRDIOA1 / (TRDIOA0) / (TRDCLK0) / SO00 / TXD0 / RTC1HZ / TOOLTXD P16 / TI02 / TO02 / TRDIOC1 / SI00 / SDA00 / RXD0 / TOOLRXD P17 / TI00 / TO00 / TRDIOB1 / SCK00 / SCL00 / INTP3 P30 / TI01 / TO01 / TRDIOD1 / SSI00 / INTP2 / SNZOUT0 P70 / ANI26 / TI15 / TO15 / SI11 / SDA11 / INTP8 / SNZOUT4 / KR0 P82 / ANI2 / IVCMP00 RL78/F24 P71 / ANI27 / TI17 / TO17 / SCK11 / SCL11 / INTP6 / SNZOUT5 / KR1 P83 / ANI3 / IVCMP01 P72 / ANI28 / SO11 / (CTXD0) / SNZOUT6 / KR2 P84 / ANI4 / IVCMP02 P73 / ANI29 / SSI11 / (CRXD0) / SNZOUT7 / KR3 P85 / ANI5 / IVREF0 / IVCMP03 P74 / ANI30 / (SO10) / (TXD1) / KR4 P80 / ANI0 / ANO0 P34 / AVREFM / ANI7 P33 / AVREFP / ANI6 P86 / ANI8 64pin P91 / ANI11 / (KR2) P81 / ANI1 P10 / TI13 / TO13 / TRJO0 / SCK10 / SCL10 / CTXD0 / LTXD1 P11 / TI12 / TO12 / (TRDIOB0) / SI10 / SDA10 / RXD1 / CRXD0 / LRXD1 P12 / TI11 / TO11 / (TRDIOD0) / SO10 / TXD1 / INTP5 / SNZOUT3 P13 / TI04 / TO04 / TRDIOA0 / TRDCLK0 / SI01 / SDA01 / LTXD0 P75 / (SI10) / (RXD1) / KR5 P87 / ANI9 / (KR0) P76 / (SCK10) / KR6 P90 / ANI10 / (KR1) P77 / (SSI10) / INTP12 / KR7 P92 / ANI12 / (KR3) (QFP) P140 / TRD1RES / PCLBUZ0 P93 / ANI13 / (KR4) P00 / (TI05) / (TO05) / INTP9 P94 / ANI14 / (KR5) P63 / (TO07) / (SSI00) / SDAA0 P95 / ANI15 / (KR6) P62 / (TO03) / (SO00) / (TXD0) / SCLA0 P137 / INTP0 P130 / RESOUT P122 / X2 / EXCLK P121 / X1 REGC P96 / ANI16 / (KR7) P61 / (TO02) / (SI00) / (SDA00) / (RXD0) P125 / ANI24 / TI03 / TO03 / TRDIOB0 / SSI01 / (LRXD1) / INTP1 / SNZOUT1 P60 / (TO01) / (SCK00) / (SCL00) P120 / ANI25 / TI07 / TO07 / TRDIOD0 / SO01 / (SCK10) / (LTXD1) / INTP4 P43 / (LRXD0) P42 / (LTXD0) P41 / VCOUT0 / TI10 / TO10 / TRJIO0 / TRD0RES / (SI10) / (RXD1) / SNZOUT2 P40 / TOOL0 RESET VSS EVSS0 VDD EVDD0 P124 / XT2 / EXCLKS P123 / XT1 <R>

RL78/F23, F24 1. OVERVIEW R01DS0446EJ0120 Rev.1.20 Page 20 of 207 Dec 31, 2025

1.5.5 RL78/F23 Pin Configuration for 64-pin Products

RL78/F23: 64-pin Plastic QFP (Fine Pitch) (10 × 10) Figure 1-14. RL78/F23 Pin Configuration for 64-pin Products Caution Do not use the XT1 and XT2 pin functions in grade-5 products. Remark Functions in parentheses in the above figure can be assigned via settings in t he peripheral I/O redirection registers (PIORx). Only the STOPST function of P52 can be assi gned via settings in the STOP status output control register (STPSTC). 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 32 50 31 51 30 52 29 53 28 54 27 55 26 56 25 57 24 58 23 59 22 60 21 61 20 62 19 63 18 64 17 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 6 P32 / (SO11) / INTP7 P14 / TI06 / TO06 / TRDIOC0 / SCK01 / SCL01 / LRXD0 P53 / (SI01) / INTP10 P52 / (SCK01) / (STOPST) P51 / (SO01) / INTP11 P50 / (SSI01) / (INTP3) P31 / (INTP2) / STOPST P15 / TI05 / TO05 / TRDIOA1 / (TRDIOA0) / (TRDCLK0) / SO00 / TXD0 / RTC1HZ / TOOLTXD P16 / TI02 / TO02 / TRDIOC1 / SI00 / SDA00 / RXD0 / TOOLRXD P17 / TI00 / TO00 / TRDIOB1 / SCK00 / SCL00 / INTP3 P30 / TI01 / TO01 / TRDIOD1 / SSI00 / INTP2 / SNZOUT0 P70 / ANI26 / SI11 / SDA11 / INTP8 / SNZOUT4 / KR0 P82 / ANI2 RL78/F23 P71 / ANI27 / SCK11 / SCL11 / INTP6 / SNZOUT5 / KR1 P83 / ANI3 P72 / ANI28 / SO11 / SNZOUT6 / KR2 P84 / ANI4 P73 / ANI29 / SSI11 / SNZOUT7 / KR3 P85 / ANI5 P74 / ANI30 / (SO10) / (TXD1) / KR4 P80 / ANI0 P34 / AVREFM / ANI7 P33 / AVREFP / ANI6 P86 / ANI8 64pin P91 / ANI11 / (KR2) P81 / ANI1 P10 / TI13 / TO13 / TRJO0 / SCK10 / SCL10 P11 / TI12 / TO12 / (TRDIOB0) / SI10 / SDA10 / RXD1 P12 / TI11 / TO11 / (TRDIOD0) / SO10 / TXD1 / INTP5 / SNZOUT3 P13 / TI04 / TO04 / TRDIOA0 / TRDCLK0 / SI01 / SDA01 / LTXD0 P75 / (SI10) / (RXD1) / KR5 P87 / ANI9 / (KR0) P76 / (SCK10) / KR6 P90 / ANI10 / (KR1) P77 / (SSI10) / INTP12 / KR7 P92 / ANI12 / (KR3) (QFP) P140 / TRD1RES / PCLBUZ0 P93 / ANI13 / (KR4) P00 / (TI05) / (TO05) / INTP9 P94 / ANI14 / (KR5) P63 / (TO07) / (SSI00) / SDAA0 P95 / ANI15 / (KR6) P62 / (TO03) / (SO00) / (TXD0) / SCLA0 P137 / INTP0 P130 / RESOUT P122 / X2 / EXCLK P121 / X1 REGC P96 / ANI16 / (KR7) P61 / (TO02) / (SI00) / (SDA00) / (RXD0) P125 / ANI24 / TI03 / TO03 / TRDIOB0 / SSI01 / INTP1 / SNZOUT1 P60 / (TO01) / (SCK00) / (SCL00) P120 / ANI25 / TI07 / TO07 / TRDIOD0 / SO01 / (SCK10) / INTP4 P43 / (LRXD0) P42 / (LTXD0) P41 / TI10 / TO10 / TRJIO0 / TRD0RES / (SI10) / (RXD1) / SNZOUT2 P40 / TOOL0 RESET VSS EVSS0 VDD EVDD0 P124 / XT2 / EXCLKS P123 / XT1 <R>

RL78/F23, F24 1. OVERVIEW R01DS0446EJ0120 Rev.1.20 Page 21 of 207 Dec 31, 2025

1.5.6 RL78/F24 Pin Configuration for 48-pin Products

RL78/F24: 48-pin Plastic QFP Figure 1-15. RL78/F24 Pin Configuration for 48-pin Products Caution Do not use the XT1 and XT2 pin functions in grade-5 products. Remark Functions in parentheses in the above figure can be assigned via settings in t he peripheral I/O redirection registers (PIORx). 36 35 34 33 32 31 30 29 28 27 26 25 37 24 38 23 39 22 40 21 41 20 42 19 43 18 44 17 45 16 46 15 47 14 48 13 123456789 1 0 1 1 1 2 P30 / TI01 / TO01 / TRDIOD1 / SSI00 / INTP2 / SNZOUT0 P34 / AVREFM / ANI7 P33 / AVREFP / ANI6 P10 / TI13 / TO13 / TRJO0 / SCK10 / SCL10 / CTXD0 / LTXD1 P11 / TI12 / TO12 / (TRDIOB0) / SI10 / SDA10 / RXD1 / CRXD0 / LRXD1 P12 / TI11 / TO11 / (TRDIOD0) / SO10 / TXD1 / INTP5 / SNZOUT3 P13 / TI04 / TO04 / TRDIOA0 / TRDCLK0 / SI01 / SDA01 / LTXD0 P14 / TI06 / TO06 / TRDIOC0 / SCK01 / SCL01 / LRXD0 P31 / TI14 / TO14 / (INTP2) / STOPST P15 / TI05 / TO05 / TRDIOA1 / (TRDIOA0) / (TRDCLK0) / SO00 / TXD0 / RTC1HZ / TOOLTXD P16 / TI02 / TO02 / TRDIOC1 / SI00 / SDA00 / RXD0 / TOOLRXD P17 / TI00 / TO00 / TRDIOB1 / SCK00 / SCL00 / INTP3 P80 / ANI0 / ANO0 P32 / TI16 / TO16 / (SO11) / INTP7 P81 / ANI1 RL78/F24 P70 / ANI26 / TI15 / TO15 / SI11 / SDA11 / INTP8 / SNZOUT4 / KR0 P82 / ANI2 / IVCMP00 P71 / ANI27 / TI17 / TO17 / SCK11 / SCL11 / INTP6 / SNZOUT5 / KR1 P83 / ANI3 / IVCMP01 / (KR0) P72 / ANI28 / SO11 / (CTXD0) / SNZOUT6 / KR2 P84 / ANI4 / IVCMP02 / (KR1) 48pin P73 / ANI29 / SSI11 / (CRXD0) / SNZOUT7 / KR3 P85 / ANI5 / IVREF0 / IVCMP03 / (KR2) P130 / RESOU T P86 / ANI8 / (KR3) P140 / TRD1RES / PCLBUZ0 P87 / ANI9 / (KR4) (QFP) P00 / (TI05) / (TO05) / INTP9 P90 / ANI10 / (KR5) P63 / (TO07) / (SSI00) / SDAA0 P91 / ANI11 / (KR6) P62 / (TO03) / (SO00) / (TXD0) / SCLA0 VDD P92 / ANI12 / (KR7) P61 / (TO02) / (SI00) / (SDA00) / (RXD0) P125 / ANI24 / TI03 / TO03 / TRDIOB0 / SSI01 / (LRXD1) / INTP1 / SNZOUT1 P60 / (TO01) / (SCK00) / (SCL00) P120 / ANI25 / TI07 / TO07 / TRDIOD0 / SO01 / (SCK10) / (LTXD1) / INTP4 P41 / VCOUT0 / TI10 / TO10 / TRJIO0 / TRD0RES / (SI10) / (RXD1) / SNZOUT2 P40 / TOOL0 RESET P124 / XT2 / EXCLKS P123 / XT1 P137 / INTP0 P122 / X2 / EXCLK P121 / X1 REGC VSS <R>

RL78/F23, F24 1. OVERVIEW R01DS0446EJ0120 Rev.1.20 Page 22 of 207 Dec 31, 2025

1.5.7 RL78/F23 Pin Configuration for 48-pin Products

RL78/F23: 48-pin Plastic QFP Figure 1-16. RL78/F23 Pin Configuration for 48-pin Products Caution Do not use the XT1 and XT2 pin functions in grade-5 products. Remark Functions in parentheses in the above figure can be assigned via settings in t he peripheral I/O redirection registers (PIORx). 36 35 34 33 32 31 30 29 28 27 26 25 37 24 38 23 39 22 40 21 41 20 42 19 43 18 44 17 45 16 46 15 47 14 48 13 123456789 1 0 1 1 1 2 P30 / TI01 / TO01 / TRDIOD1 / SSI00 / INTP2 / SNZOUT0 P34 / AVREFM / ANI7 P33 / AVREFP / ANI6 P10 / TI13 / TO13 / TRJO0 / SCK10 / SCL10 P11 / TI12 / TO12 / (TRDIOB0) / SI10 / SDA10 / RXD1 P12 / TI11 / TO11 / (TRDIOD0) / SO10 / TXD1 / INTP5 / SNZOUT3 P13 / TI04 / TO04 / TRDIOA0 / TRDCLK0 / SI01 / SDA01 / LTXD0 P14 / TI06 / TO06 / TRDIOC0 / SCK01 / SCL01 / LRXD0 P31 / (INTP2) / STOPST P15 / TI05 / TO05 / TRDIOA1 / (TRDIOA0) / (TRDCLK0) / SO00 / TXD0 / RTC1HZ / TOOLTXD P16 / TI02 / TO02 / TRDIOC1 / SI00 / SDA00 / RXD0 / TOOLRXD P17 / TI00 / TO00 / TRDIOB1 / SCK00 / SCL00 / INTP3 P80 / ANI0 P32 / (SO11) / INTP7 P81 / ANI1 RL78/F23 P70 / ANI26 / SI11 / SDA11 / INTP8 / SNZOUT4 / KR0 P82 / ANI2 P71 / ANI27 / SCK11 / SCL11 / INTP6 / SNZOUT5 / KR1 P83 / ANI3 / (KR0) P72 / ANI28 / SO11 / SNZOUT6 / KR2 P84 / ANI4 / (KR1) 48pin P73 / ANI29 / SSI11 / SNZOUT7 / KR3 P85 / ANI5 / (KR2) P130 / RESOUT P86 / ANI8 / (KR3) P140 / TRD1RES / PCLBUZ0 P87 / ANI9 / (KR4) (QFP) P00 / (TI05) / (TO05) / INTP9 P90 / ANI10 / (KR5) P63 / (TO07) / (SSI00) / SDAA0 P91 / ANI11 / (KR6) P62 / (TO03) / (SO00) / (TXD0) / SCLA0 VDD P92 / ANI12 / (KR7) P61 / (TO02) / (SI00) / (SDA00) / (RXD0) P125 / ANI24 / TI03 / TO03 / TRDIOB0 / SSI01 / INTP1 / SNZOUT1 P60 / (TO01) / (SCK00) / (SCL00) P120 / ANI25 / TI07 / TO07 / TRDIOD0 / SO01 / (SCK10) / INTP4 P41 / TI10 / TO10 / TRJIO0 / TRD0RES / (SI10) / (RXD1) / SNZOUT2 P40 / TOOL0 RESET P124 / XT2 / EXCLKS P123 / XT1 P137 / INTP0 P122 / X2 / EXCLK P121 / X1 REGC VSS <R>

RL78/F23, F24 1. OVERVIEW R01DS0446EJ0120 Rev.1.20 Page 23 of 207 Dec 31, 2025

1.5.8 RL78/F24 Pin Configuration for 32-pin Products

RL78/F24: 32-pin Plastic QFN Figure 1-17. RL78/F24 Pin Configuration for 32-pin Products Remark Functions in parentheses in the above figure can be assigned via settings in t he peripheral I/O redirection registers (PIORx). 24 23 22 21 20 19 18 17 25 16 26 15 27 14 28 13 29 12 30 11 31 10 32 9 12345678 P15 / TI05 / TO05 / TRDIOA1 / (TRDIOA0) / (TRDCLK0) / SO00 / TXD0 / RTC1HZ / TOOLTXD P16 / TI02 / TO02 / TRDIOC1 / SI00 / SDA00 / RXD0 / TOOLRXD P34 / AVREFM / ANI7 P17 / TI00 / TO00 / TRDIOB1 / SCK00 / SCL00 / INTP3 P80 / ANI0 / ANO0 / (KR0) RL78/F24 P30 / TI01 / TO01 / TRDIOD1 / SSI00 / INTP2 / SNZOUT0 P81 / ANI1 / (KR1) P63 / (TO07) / (SSI00) / SDAA0 P33 / AVREFP / ANI6 P10 / TI13 / TO13 / TRJO0 / SCK10 / SCL10 / CTXD0 / LTXD1 P11 / TI12 / TO12 / (TRDIOB0) / SI10 / SDA10 / RXD1 / CRXD0 / LRXD1 P12 / TI11 / TO11 / (TRDIOD0) / SO10 / TXD1 / INTP5 / SNZOUT3 P13 / TI04 / TO04 / TRDIOA0 / TRDCLK0 / SI01 / SDA01 / LTXD0 P14 / TI06 / TO06 / TRDIOC0 / SCK01 / SCL01 / LRXD0 P84 / ANI4 / IVCMP02 / (KR4) (QFN) P60 / (TO01) / (SCK00) / (SCL00) P85 / ANI5 / IVREF0 / IVCMP03 / (KR5) VDD P82 / ANI2 / IVCMP00 / (KR2) 32pin P62 / (TO03) / (SO00) / (TXD0) / SCLA0 P83 / ANI3 / IVCMP01 / (KR3) P61 / (TO02) / (SI00) / (SDA00) / (RXD0) P125 / ANI24 / TI03 / TO03 / TRDIOB0 / SSI01 / (LRXD1) / INTP1 / SNZOUT1 VSS P120 / ANI25 / TI07 / TO07 / TRDIOD0 / SO01 / (SCK10) / (LTXD1) / INTP4 P41 / VCOUT0 / TI10 / TO10 / TRJIO0 / TRD0RES / (SI10) / (RXD1) / SNZOUT2 P40 / TOOL0 RESET P137 / INTP0 P122 / X2 / EXCLK P121 / X1 REGC <R>

RL78/F23, F24 1. OVERVIEW R01DS0446EJ0120 Rev.1.20 Page 24 of 207 Dec 31, 2025

1.5.9 RL78/F23 Pin Configuration for 32-pin Products

RL78/F23: 32-pin Plastic QFN Figure 1-18. RL78/F23 Pin Configuration for 32-pin Products Remark Functions in parentheses in the above figure can be assigned via settings in t he peripheral I/O redirection registers (PIORx). 24 23 22 21 20 19 18 17 25 16 26 15 27 14 28 13 29 12 30 11 31 10 32 9 12345678 P15 / TI05 / TO05 / TRDIOA1 / (TRDIOA0) / (TRDCLK0) / SO00 / TXD0 / RTC1HZ / TOOLTXD P16 / TI02 / TO02 / TRDIOC1 / SI00 / SDA00 / RXD0 / TOOLRXD P34 / AVREFM / ANI7 P17 / TI00 / TO00 / TRDIOB1 / SCK00 / SCL00 / INTP3 P80 / ANI0 / (KR0) RL78/F23 P30 / TI01 / TO01 / TRDIOD1 / SSI00 / INTP2 / SNZOUT0 P81 / ANI1 / (KR1) P63 / (TO07) / (SSI00) / SDAA0 P33 / AVREFP / ANI6 P10 / TI13 / TO13 / TRJO0 / SCK10 / SCL10 P11 / TI12 / TO12 / (TRDIOB0) / SI10 / SDA10 / RXD1 P12 / TI11 / TO11 / (TRDIOD0) / SO10 / TXD1 / INTP5 / SNZOUT3 P13 / TI04 / TO04 / TRDIOA0 / TRDCLK0 / SI01 / SDA01 / LTXD0 P14 / TI06 / TO06 / TRDIOC0 / SCK01 / SCL01 / LRXD0 P84 / ANI4 / (KR4) (QFN) P60 / (TO01) / (SCK00) / (SCL00) P85 / ANI5 / (KR5) VDD P82 / ANI2 / (KR2) 32pin P62 / (TO03) / (SO00) / (TXD0) / SCLA0 P83 / ANI3 / (KR3) P61 / (TO02) / (SI00) / (SDA00) / (RXD0) P125 / ANI24 / TI03 / TO03 / TRDIOB0 / SSI01 / INTP1 / SNZOUT1 VSS P120 / ANI25 / TI07 / TO07 / TRDIOD0 / SO01 / (SCK10) / INTP4 P41 / TI10 / TO10 / TRJIO0 / TRD0RES / (SI10) / (RXD1) / SNZOUT2 P40 / TOOL0 RESET P137 / INTP0 P122 / X2 / EXCLK P121 / X1 REGC <R>

RL78/F23, F24 2. PIN FUNCTIONS R01DS0446EJ0120 Rev.1.20 Page 25 of 207 Dec 31, 2025 2. PIN FUNCTIONS

2.1 Pin Function List

Pin I/O buffer power suppli es depend on the product. Table 2-1 shows the relationship between these power supplies and the pins. EVDD indicates EVDD0 and EVDD1. Table 2-1. Pin I/O Buffer Power Supplies (1) 32-pin, and 48-pin products Power Supply Corresponding Pins VDD All pins (2) 64-pin products Power Supply Corresponding Pins EVDD0 • Port pins other than P33, P34, P80 to P87, P90 to P96, P121 to P124, and P137 VDD • P33, P34, P80 to P87, P90 to P96, P121 to P124, and P137

Pins other than port pins (3) 80-pin products Power Supply Corresponding Pins EVDD0 • Port pins other than P33, P34, P80 to P87, P90 to P97, P121 to P124, and P137 VDD • P33, P34, P80 to P87, P90 to P97, P121 to P124, and P137
Pins other than port pins (4) 100-pin products Power Supply Corresponding Pins EVDD0, EVDD1 • Port pins other than P33, P34, P80 to P87, P90 to P97, P100 to P105, P121 to P124, and P137 VDD • P33, P34, P80 to P87, P90 to P97, P100 to P105, P121 to P124, and P137
Pins other than port pins This subchapter describes the 100-pin products of RL78/F24 and the 80-pin products of RL78/F23 as examples.

RL78/F23, F24 2. PIN FUNCTIONS R01DS0446EJ0120 Rev.1.20 Page 26 of 207 Dec 31, 2025

2.1.1 RL78/F24 100-pin Products

(1/2) Function Name I/O Function After Reset Alternate Function P00 I/O Port 0 Use of an on-chip pull-up resistor can be specified by a software setting. Input port (TI05)/(TO05)/INTP9 P01 (TI04)/(TO04) P02 (TI06)/(TO06) P03 (RTC1HZ) P10 I/O Port 1 Input of P10, P11, P13, P14, P16, and P17 can be set to TTL input buffer. Use of an on-chip pull-up resistor can be specified by a software setting. Output from P10 to P17 can be set to N-ch open-drain output. For input to P10, P11, P13, P14, P16, and P17, the threshold level can be specified. Input port TI13/TO13/TRJO0/SCK10/SCL10/ LTXD1/CTXD0 P11 TI12/TO12/(TRDIOB0)/SI10/ SDA10/RXD1/LRXD1/CRXD0 P12 TI11/TO11/(TRDIOD0)/INTP5/ SO10/TXD1/SNZOUT3 P13 TI04/TO04/TRDIOA0/TRDCLK0/ SI01/SDA01/LTXD0 P14 TI06/TO06/TRDIOC0/SCK01/ SCL01/LRXD0 P15 TI05/TO05/TRDIOA1/(TRDIOA0)/ (TRDCLK0)/SO00/TXD0/ TOOLTXD/RTC1HZ P16 TI02/TO02/TRDIOC1/SI00/ SDA00/RXD0/TOOLRXD P17 TI00/TO00/TRDIOB1/SCK00/ SCL00/INTP3 P30 I/O Port 3 Input of P30 can be set to TTL input buffer. P33 and P34 can be set to analog input. Output from P32 can be set to N-ch open-drain output. For input to P30 to P32, use of an on-chip pull-up resistor can be specified by a software setting. For input to P30, the threshold level can be specified. Input port TI01/TO01/TRDIOD1/SSI00/ INTP2/SNZOUT0 P31 TI14/TO14/STOPST/(INTP2) P32 TI16/TO16/(SO11)/INTP7 P33 Analog input port AVREFP/ANI6 P34 AVREFM/ANI7 P40 I/O Port 4 Use of an on-chip pull-up resistor can be specified by a software setting. For input to P41 and P43, the threshold level can be specified. Input port TOOL0 P41 TI10/TO10/TRJIO0/TRD0RES/ (SI10)/(RXD1)/VCOUT0/SNZOUT2 P42 (LTXD0) P43 (LRXD0) P44 (TI07)/(TO07) P45 (TI10)/(TO10) P46 (TI12)/(TO12) P47 INTP13 P50 I/O Port 5 Input of P54 can be set to TTL input buffer. Use of an on-chip pull-up resistor can be specified by a software setting. For input to P50 and P52 to P54, the threshold level can be specified. Input port (SSI01)/(INTP3) P51 (SO01)/INTP11 P52 (SCK01)/(STOPST) P53 (SI01)/INTP10 P54 (TI11)/(TO11)/SSI10 P55 (TI13)/(TO13) P56 (TI15)/(TO15)/(SNZOUT1) P57 (TI17)/(TO17)/(SNZOUT0) P60 I/O Port 6 Input of P62 and P63 can be set to TTL input buffer. Use of an on-chip pull-up resistor can be specified by a software setting. Output from P60 to P63 can be set to N-ch open-drain output. For input to P60 to P63, the threshold level can be specified. Input port (TO01)/(SCK00)/(SCL00) P61 (TO02)/(SI00)/(SDA00)/(RXD0) P62 (TO03)/(SO00)/(TXD0)/SCLA0 P63 (TO07)/(SSI00)/SDAA0 P64 (TI14)/(TO14)/(SNZOUT3) P65 (TI16)/(TO16)/(SNZOUT2) P66 (TI00)/(TO00) P67 (TI02)/(TO02) Remark Functions in parentheses in the ab ove table can be assigned via settings in the peripheral I/O redirection registers (PIORx). Only the STOPST function of P52 can be assi gned via settings in the STOP status output control register (STPSTC).

RL78/F23, F24 2. PIN FUNCTIONS R01DS0446EJ0120 Rev.1.20 Page 27 of 207 Dec 31, 2025 (2/2) Function Name I/O Function After Reset Alternate Function P70 I/O Port 7 Input of P70, P71, and P73 can be set to TTL input buffer. P70 to P74 can be set to analog input. Use of an on-chip pull-up resistor can be specified by a software setting. Output from P70 to P72 can be set to N-ch open-drain output. For input to P70, P71, P73, and P75 to P77, the threshold level can be specified. Analog input port ANI26/KR0/TI15/TO15/INTP8/ SI11/SDA11/SNZOUT4 P71 ANI27/KR1/TI17/TO17/INTP6/ SCK11/SCL11/SNZOUT5 P72 ANI28/KR2/(CTXD0)/SO11/ SNZOUT6 P73 ANI29/KR3/(CRXD0)/SSI11/ SNZOUT7 P74 ANI30/KR4/(SO10)/(TXD1) P75 Input port KR5/(SI10)/(RXD1) P76 KR6/(SCK10) P77 KR7/(SSI10)/INTP12 P80 I/O Port 8 P80 to P87 can be set to analog input. Analog input port ANI0/ANO0 P81 ANI1 P82 ANI2/IVCMP00 P83 ANI3/IVCMP01 P84 ANI4/IVCMP02 P85 ANI5/IVCMP03/IVREF0 P86 ANI8 P87 ANI9 P90 I/O Port 9 P90 to P97 can be set to analog input. Analog input port ANI10 P91 ANI11 P92 ANI12 P93 ANI13 P94 ANI14 P95 ANI15 P96 ANI16 P97 ANI17 P100 I/O Port 10 P100 to P105 can be set to analog input. For P106 and P107, use of an on-chip pull-up resistor can be specified by a software setting. For input to P107, the threshold level can be specified. Analog input port ANI18 P101 ANI19 P102 ANI20 P103 ANI21 P104 ANI22 P105 ANI23 P106 Input port (LTXD1) P107 (LRXD1) P120 I/O Port 12 Input of P125 can be set to TTL input buffer. P120 and P125 can be set to analog input. For P120 and P125 to P127, use of an on-chip pull-up resistor can be specified by a software setting. Output from P120 can be set to N-ch open-drain output. For input to P120 and P125, the threshold level can be specified. Analog input port ANI25/TI07/TO07/TRDIOD0/ SO01/(SCK10)/(LTXD1)/INTP4 P121 Input Input port X1 P122 X2/EXCLK P123 XT1 P124 XT2/EXCLKS P125 I/O Analog input port ANI24/TI03/TO03/TRDIOB0/ SSI01/(LRXD1)/INTP1/SNZOUT1 P126 Input port (TI01)/(TO01) P127 (TI03)/(TO03) P130 Output Port 13 Output port RESOUT P137 Input Input port INTP0 P140 I/O Port 14 Use of an on-chip pull-up resistor can be specified by a software setting. Input port TRD1RES/PCLBUZ0 P150 I/O Port 15 Use of an on-chip pull-up resistor can be specified by a software setting. For input to P150, P152, and P153, the threshold level can be specified. Input port (SSI11) P151 (SO11) P152 (SI11) P153 (SCK11) P154 (SNZOUT7) P155 (SNZOUT6) P156 (SNZOUT5) P157 (SNZOUT4) Remark Functions in parentheses in the ab ove table can be assigned via settings in the peripheral I/O redirection registers (PIORx).

RL78/F23, F24 2. PIN FUNCTIONS R01DS0446EJ0120 Rev.1.20 Page 28 of 207 Dec 31, 2025

2.1.2 RL78/F23 80-pin Products

(1/2) Function Name I/O Function After Reset Alternate Function P00 I/O Port 0 Use of an on-chip pull-up resistor can be specified by a software setting. Input port (TI05)/(TO05)/INTP9 P01 (TI04)/(TO04) P02 (TI06)/(TO06) P10 I/O Port 1 Input of P10, P11, P13, P14, P16, and P17 can be set to TTL input buffer. Use of an on-chip pull-up resistor can be specified by a software setting. Output from P10 to P17 can be set to N-ch open-drain output. For input to P10, P11, P13, P14, P16, and P17, the threshold level can be specified. Input port TI13/TO13/TRJO0/SCK10/SCL10 P11 TI12/TO12/(TRDIOB0)/SI10/ SDA10/RXD1 P12 TI11/TO11/(TRDIOD0)/INTP5/ SO10/TXD1/SNZOUT3 P13 TI04/TO04/TRDIOA0/TRDCLK0/ SI01/SDA01/LTXD0 P14 TI06/TO06/TRDIOC0/SCK01/ SCL01/LRXD0 P15 TI05/TO05/TRDIOA1/(TRDIOA0)/ (TRDCLK0)/SO00/TXD0/ TOOLTXD/RTC1HZ P16 TI02/TO02/TRDIOC1/SI00/ SDA00/RXD0/TOOLRXD P17 TI00/TO00/TRDIOB1/SCK00/ SCL00/INTP3 P30 I/O Port 3 Input of P30 can be set to TTL input buffer. P33 and P34 can be set to analog input. Output from P32 can be set to N-ch open-drain output. For input to P30 to P32, use of an on-chip pull-up resistor can be specified by a software setting. For input to P30, the threshold level can be specified. Input port TI01/TO01/TRDIOD1/SSI00/ INTP2/SNZOUT0 P31 STOPST/(INTP2) P32 (SO11)/INTP7 P33 Analog input port AVREFP/ANI6 P34 AVREFM/ANI7 P40 I/O Port 4 Use of an on-chip pull-up resistor can be specified by a software setting. For input to P41 and P43, the threshold level can be specified. Input port TOOL0 P41 TI10/TO10/TRJIO0/TRD0RES/ (SI10)/(RXD1)/SNZOUT2 P42 (LTXD0) P43 (LRXD0) P44 (TI07)/(TO07) P45 (TI10)/(TO10) P46 (TI12)/(TO12) P47 INTP13 P50 I/O Port 5 Use of an on-chip pull-up resistor can be specified by a software setting. For input to P50 and P52 to P54, the threshold level can be specified. Input of P54 can be set to TTL input buffer. Input port (SSI01)/(INTP3) P51 (SO01)/INTP11 P52 (SCK01)/(STOPST) P53 (SI01)/INTP10 P54 (TI11)/(TO11)/SSI10 P55 (TI13)/(TO13) P56 (SNZOUT1) P57 (SNZOUT0) P60 I/O Port 6 Input of P62 and P63 can be set to TTL input buffer. Use of an on-chip pull-up resistor can be specified by a software setting. Output from P60 to P63 can be set to N-ch open-drain output. For input to P60 to P63, the threshold level can be specified. Input port (TO01)/(SCK00)/(SCL00) P61 (TO02)/(SI00)/(SDA00)/(RXD0) P62 (TO03)/(SO00)/(TXD0)/SCLA0 P63 (TO07)/(SSI00)/SDAA0 P64 (SNZOUT3) P65 (SNZOUT2) P66 (TI00)/(TO00) P67 (TI02)/(TO02) Remark Functions in parentheses in the ab ove table can be assigned via settings in the peripheral I/O redirection registers (PIORx). Only the STOPST function of P52 can be assi gned via settings in the STOP status output control register (STPSTC).

RL78/F23, F24 2. PIN FUNCTIONS R01DS0446EJ0120 Rev.1.20 Page 29 of 207 Dec 31, 2025 (2/2) Function Name I/O Function After Reset Alternate Function P70 I/O Port 7 Input of P70, P71, and P73 can be set to TTL input buffer. P70 to P74 can be set to analog input. Use of an on-chip pull-up resistor can be specified by a software setting. Output from P70 to P72 can be set to N-ch open-drain output. For input to P70, P71, P73, and P75 to P77, the threshold level can be specified. Analog input port ANI26/KR0/INTP8/SI11/SDA11/ SNZOUT4 P71 ANI27/KR1/INTP6/SCK11/SCL11/ SNZOUT5 P72 ANI28/KR2/SO11/SNZOUT6 P73 ANI29/KR3/SSI11/SNZOUT7 P74 ANI30/KR4/(SO10)/(TXD1) P75 Input port KR5/(SI10)/(RXD1) P76 KR6/(SCK10) P77 KR7/(SSI10)/INTP12 P80 I/O Port 8 P80 to P87 can be set to analog input. Analog input port ANI0 P81 ANI1 P82 ANI2 P83 ANI3 P84 ANI4 P85 ANI5 P86 ANI8 P87 ANI9 P90 I/O Port 9 P90 to P97 can be set to analog input. Analog input port ANI10 P91 ANI11 P92 ANI12 P93 ANI13 P94 ANI14 P95 ANI15 P96 ANI16 P97 ANI17 P120 I/O Port 12 Input of P125 can be set to TTL input buffer. P120 and P125 can be set to analog input. For P120, P125, and P126, use of an on-chip pull-up resistor can be specified by a software setting. Output from P120 can be set to N-ch open-drain output. For input to P120 and P125, the threshold level can be specified. Analog input port ANI25/TI07/TO07/TRDIOD0/ SO01/(SCK10)/INTP4 P121 Input Input port X1 P122 X2/EXCLK P123 XT1 P124 XT2/EXCLKS P125 I/O Analog input port ANI24/TI03/TO03/TRDIOB0/ SSI01/INTP1/SNZOUT1 P126 Input port (TI01)/(TO01) P130 Output Port 13 Output port RESOUT P137 Input Input port INTP0 P140 I/O Port 14 Use of an on-chip pull-up resistor can be specified by a software setting. Input port TRD1RES/PCLBUZ0 Remark Functions in parentheses in the ab ove table can be assigned via settings in the peripheral I/O redirection registers (PIORx).

RL78/F23, F24 2. PIN FUNCTIONS R01DS0446EJ0120 Rev.1.20 Page 30 of 207 Dec 31, 2025

2.1.3 Pins for Each Product (pins other than port pins)

This subchapter shows the pins other than the ports shown in Table 2-2 and Table 2-3 for each product. “√ ” indicates the pin that is provided in the product and “⎯” indicates the pin that is not provided. Table 2-2. List of RL78/F24 Pins Other than Port Pins (1/5) Pin Function I/O Function Pin Count 100-pin 80-pin 64-pin 48-pin 32-pin ANI0 Input A/D converter analog input (high-speed) √ √ √ √ √ ANI16 Input A/D converter analog input (normal-speed) √ √ √ ⎯ ⎯ IVCMP00 Input Comparator analog voltage input √ √ √ √ √ IVREF0 Input Comparator reference voltage input √ √ √ √ √

RL78/F23, F24 2. PIN FUNCTIONS R01DS0446EJ0120 Rev.1.20 Page 31 of 207 Dec 31, 2025 Table 2-2. List of RL78/F24 Pins Other than Port Pins (2/5) Pin Function I/O Function Pin Count 100-pin 80-pin 64-pin 48-pin 32-pin KR0 Input Key interrupt input √ √ √ √ √ ANO0 Output D/A converter output √ √ √ √ √ VCOUT0 Output Comparator output √ √ √ √ √ TI00 Input 16-bit timer 00 input √ √ √ √ √ TI01 Input 16-bit timer 01 input (8-bit mode available) √ √ √ √ √ TI02 Input 16-bit timer 02 input √ √ √ √ √ TI03 Input 16-bit timer 03 input (8-bit mode available) √ √ √ √ √ TI04 Input 16-bit timer 04 input √ √ √ √ √ TI05 Input 16-bit timer 05 input √ √ √ √ √ TI06 Input 16-bit timer 06 input √ √ √ √ √ TI07 Input 16-bit timer 07 input √ √ √ √ √ TI10 Input 16-bit timer 10 input √ √ √ √ √ TI11 Input 16-bit timer 11 input (8-bit mode available) √ √ √ √ √ TI12 Input 16-bit timer 12 input √ √ √ √ √ TI13 Input 16-bit timer 13 input (8-bit mode available) √ √ √ √ √ TI14 Input 16-bit timer 14 input √ √ √ √ ⎯ TI15 Input 16-bit timer 15 input √ √ √ √ ⎯ TI16 Input 16-bit timer 16 input √ √ √ √ ⎯ TI17 Input 16-bit timer 17 input √ √ √ √ ⎯ TO00 Output 16-bit timer 00 output √ √ √ √ √ TO01 Output 16-bit timer 01 output (8-bit mode available) √ √ √ √ √ TO02 Output 16-bit timer 02 output √ √ √ √ √ TO03 Output 16-bit timer 03 output (8-bit mode available) √ √ √ √ √ TO04 Output 16-bit timer 04 output √ √ √ √ √ TO05 Output 16-bit timer 05 output √ √ √ √ √ TO06 Output 16-bit timer 06 output √ √ √ √ √ TO07 Output 16-bit timer 07 output √ √ √ √ √ TO10 Output 16-bit timer 10 output √ √ √ √ √ TO11 Output 16-bit timer 11 output (8-bit mode available) √ √ √ √ √ TO12 Output 16-bit timer 12 output √ √ √ √ √ TO13 Output 16-bit timer 13 output (8-bit mode available) √ √ √ √ √ TO14 Output 16-bit timer 14 output √ √ √ √ ⎯ TO15 Output 16-bit timer 15 output √ √ √ √ ⎯ TO16 Output 16-bit timer 16 output √ √ √ √ ⎯ TO17 Output 16-bit timer 17 output √ √ √ √ ⎯

RL78/F23, F24 2. PIN FUNCTIONS R01DS0446EJ0120 Rev.1.20 Page 32 of 207 Dec 31, 2025 Table 2-2. List of RL78/F24 Pins Other than Port Pins (3/5) Pin Function I/O Function Pin Count 100-pin 80-pin 64-pin 48-pin 32-pin TRJIO0 I/O Timer RJ input/output √ √ √ √ √ TRJO0 Output Timer RJ output √ √ √ √ √ TRDCLK0 Input Timer RDe external clock input √ √ √ √ √ TRDIOA0 I/O Timer RDe0 input/output √ √ √ √ √ TRDIOA1 I/O Timer RDe1 input/output √ √ √ √ √ TRD0RES Input Timer RDe0 external timer counter clear trigger input √ √ √ √ √ TRD1RES Input Timer RDe1 external timer counter clear trigger input √ √ √ √ ⎯ RXD0 Input Serial data input to UART0 √ √ √ √ √ RXD1 Input Serial data input to UART1 √ √ √ √ √ TXD0 Output Serial data output from UART0 √ √ √ √ √ TXD1 Output Serial data output from UART1 √ √ √ √ √ SCLA0 I/O Clock input/output for IICA0 √ √ √ √ √ SCL00 Output Clock output from simplified I 2C √ √ √ √ √ SDAA0 I/O Serial data input/output for IICA0 √ √ √ √ √ SDA00 I/O Serial data input/output for simplified I 2C √ √ √ √ √ SCK00 I/O Clock input/output for CSI00 √ √ √ √ √ SCK01 I/O Clock input/output for CSI01 √ √ √ √ √ SCK10 I/O Clock input/output for CSI10 √ √ √ √ √ SCK11 I/O Clock input/output for CSI11 √ √ √ √ ⎯ SI00 Input Serial data input to CSI00 √ √ √ √ √ SI01 Input Serial data input to CSI01 √ √ √ √ √ SI10 Input Serial data input to CSI10 √ √ √ √ √ SI11 Input Serial data input to CSI11 √ √ √ √ ⎯ SO00 Output Serial data output from CSI00 √ √ √ √ √ SO01 Output Serial data output from CSI01 √ √ √ √ √ SO10 Output Serial data output from CSI10 √ √ √ √ √ SO11 Output Serial data output from CSI11 √ √ √ √ ⎯ SSI00 Input Slave select input to CSI00 (SPI00) √ √ √ √ √ SSI01 Input Slave select input to CSI01 (SPI01) √ √ √ √ √ SSI10 Input Slave select input to CSI10 (SPI10) √ √ √ ⎯ ⎯ SSI11 Input Slave select input to CSI11 (SPI11) √ √ √ √ ⎯

RL78/F23, F24 2. PIN FUNCTIONS R01DS0446EJ0120 Rev.1.20 Page 33 of 207 Dec 31, 2025 Table 2-2. List of RL78/F24 Pins Other than Port Pins (4/5) Pin Function I/O Function Pin Count 100-pin 80-pin 64-pin 48-pin 32-pin CRXD0 Input Serial data input to CAN √ √ √ √ √ CTXD0 Output Serial data output from CAN √ √ √ √ √ LRXD0 Input Serial data input to LIN √ √ √ √ √ LTXD0 Output Serial data output from LIN √ √ √ √ √ INTP0 Input External interrupt input √ √ √ √ √ PCLBUZ0 Output Clock output/buzzer output 0 √ √ √ √ ⎯ RESOUT Output Reset output √ √ √ √ ⎯ STOPST Output STOP status output √ √ √ √ ⎯ SNZOUT0 Output SNOOZE status output √ √ √ √ √ RTC1HZ Output Real-time clock correction clock (1 Hz) output √ √ √ √ √

RL78/F23, F24 2. PIN FUNCTIONS R01DS0446EJ0120 Rev.1.20 Page 34 of 207 Dec 31, 2025 Table 2-2. List of RL78/F24 Pins Other than Port Pins (5/5) Pin Function I/O Function Pin Count 100-pin 80-pin 64-pin 48-pin 32-pin EXCLK Input External clock input for main system clock √ √ √ √ √ EXCLKS Input External clock input for subsystem clock √ √ √ √ ⎯ X1 ⎯ Resonator connection for main system clock √ √ √ √ √ XT1 Note ⎯ Resonator connection for subsystem clock √ √ √ √ ⎯ RESET Input External reset input √ √ √ √ √ REGC ⎯ Regulator output stabilizatio n capacitance connection for internal operation. Connect to V SS via the capacitor (0.47 to 1 μF). VDD ⎯ Positive power supply for the P33, P34, P80 to P87, P90 to P97, P100 to P105, P121 to P124, P137, and RESET pins EVDD0 ⎯ Positive power supply for the pins that are not connected to VDD √ √ √ ⎯ ⎯ AVREFP Input A/D converter reference voltage (+ side) input √ √ √ √ √ AVREFM Input A/D converter reference voltage (- side) input √ √ √ √ √ VSS ⎯ Ground potential for the P33, P34, P80 to P87, P90 to P97, P100 to P105, P121 to P124, P137, and RESET pins EVSS0 ⎯ Ground potential for the pins that are not connected to V SS √ √ √ ⎯ ⎯ TOOLRXD Input UART reception pin for the external device connection used during flash memory programming TOOLTXD Output UART transmission pin for the external device connection used during flash memory programming TOOL0 I/O Data input/output for flash memory programmer/debugger √ √ √ √ √ Note Do not use the XT1 and XT2 pin functions in grade-5 products.

RL78/F23, F24 2. PIN FUNCTIONS R01DS0446EJ0120 Rev.1.20 Page 35 of 207 Dec 31, 2025 Table 2-3. List of RL78/F23 Pins Other than Port Pins (1/5) Pin Function I/O Function Pin Count 80-pin 64-pin 48-pin 32-pin ANI0 Input A/D converter analog input (high-speed) √ √ √ √ ANI1 Input √ √ √ √ ANI2 Input √ √ √ √ ANI3 Input √ √ √ √ ANI4 Input √ √ √ √ ANI5 Input √ √ √ √ ANI6 Input √ √ √ √ ANI7 Input √ √ √ √ ANI8 Input √ √ √ ⎯ ANI9 Input √ √ √ ⎯ ANI10 Input √ √ √ ⎯ ANI11 Input √ √ √ ⎯ ANI12 Input √ √ √ ⎯ ANI13 Input √ √ ⎯ ⎯ ANI14 Input √ √ ⎯ ⎯ ANI15 Input √ √ ⎯ ⎯ ANI16 Input A/D converter analog input (normal-speed) √ √ ⎯ ⎯ ANI17 Input √ ⎯ ⎯ ⎯ ANI24 Input √ √ √ √ ANI25 Input √ √ √ √ ANI26 Input √ √ √ ⎯ ANI27 Input √ √ √ ⎯ ANI28 Input √ √ √ ⎯ ANI29 Input √ √ √ ⎯ ANI30 Input √ √ ⎯ ⎯ KR0 Input Key interrupt input √ √ √ √ KR1 Input √ √ √ √ KR2 Input √ √ √ √ KR3 Input √ √ √ √ KR4 Input √ √ √ √ KR5 Input √ √ √ √ KR6 Input √ √ √ ⎯ KR7 Input √ √ √ ⎯

RL78/F23, F24 2. PIN FUNCTIONS R01DS0446EJ0120 Rev.1.20 Page 36 of 207 Dec 31, 2025 Table 2-3. List of RL78/F23 Pins Other than Port Pins (2/5) Pin Function I/O Function Pin Count 80-pin 64-pin 48-pin 32-pin TI00 Input 16-bit timer 00 input √ √ √ √ TI01 Input 16-bit timer 01 input (8-bit mode available) √ √ √ √ TI02 Input 16-bit timer 02 input √ √ √ √ TI03 Input 16-bit timer 03 input (8-bit mode available) √ √ √ √ TI04 Input 16-bit timer 04 input √ √ √ √ TI05 Input 16-bit timer 05 input √ √ √ √ TI06 Input 16-bit timer 06 input √ √ √ √ TI07 Input 16-bit timer 07 input √ √ √ √ TI10 Input 16-bit timer 10 input √ √ √ √ TI11 Input 16-bit timer 11 input (8-bit mode available) √ √ √ √ TI12 Input 16-bit timer 12 input √ √ √ √ TI13 Input 16-bit timer 13 input (8-bit mode available) √ √ √ √ TO00 Output 16-bit timer 00 output √ √ √ √ TO01 Output 16-bit timer 01 output (8-bit mode available) √ √ √ √ TO02 Output 16-bit timer 02 output √ √ √ √ TO03 Output 16-bit timer 03 output (8-bit mode available) √ √ √ √ TO04 Output 16-bit timer 04 output √ √ √ √ TO05 Output 16-bit timer 05 output √ √ √ √ TO06 Output 16-bit timer 06 output √ √ √ √ TO07 Output 16-bit timer 07 output √ √ √ √ TO10 Output 16-bit timer 10 output √ √ √ √ TO11 Output 16-bit timer 11 output (8-bit mode available) √ √ √ √ TO12 Output 16-bit timer 12 output √ √ √ √ TO13 Output 16-bit timer 13 output (8-bit mode available) √ √ √ √ TRJIO0 I/O Timer RJ input/output √ √ √ √ TRJO0 Output Timer RJ output √ √ √ √ TRDCLK0 Input Timer RDe external clock input √ √ √ √ TRDIOA0 I/O Timer RDe0 input/output √ √ √ √ TRDIOB0 I/O √ √ √ √ TRDIOC0 I/O √ √ √ √ TRDIOD0 I/O √ √ √ √ TRDIOA1 I/O Timer RDe1 input/output √ √ √ √ TRDIOB1 I/O √ √ √ √ TRDIOC1 I/O √ √ √ √ TRDIOD1 I/O √ √ √ √ TRD0RES Input Timer RDe0 external timer counter clear trigger input √ √ √ √ TRD1RES Input Timer RDe1 external timer counter clear trigger input √ √ √ ⎯

RL78/F23, F24 2. PIN FUNCTIONS R01DS0446EJ0120 Rev.1.20 Page 37 of 207 Dec 31, 2025 Table 2-3. List of RL78/F23 Pins Other than Port Pins (3/5) Pin Function I/O Function Pin Count 80-pin 64-pin 48-pin 32-pin RXD0 Input Serial data input to UART0 √ √ √ √ RXD1 Input Serial data input to UART1 √ √ √ √ TXD0 Output Serial data output from UART0 √ √ √ √ TXD1 Output Serial data output from UART1 √ √ √ √ SCLA0 I/O Clock input/output for IICA0 √ √ √ √ SCL00 Output Clock output from simplified I 2C √ √ √ √ SCL01 Output √ √ √ √ SCL10 Output √ √ √ √ SCL11 Output √ √ √ ⎯ SDAA0 I/O Serial data input/output for IICA0 √ √ √ √ SDA00 I/O Serial data input/output for simplified I 2C √ √ √ √ SDA01 I/O √ √ √ √ SDA10 I/O √ √ √ √ SDA11 I/O √ √ √ ⎯ SCK00 I/O Clock input/output for CSI00 √ √ √ √ SCK01 I/O Clock input/output for CSI01 √ √ √ √ SCK10 I/O Clock input/output for CSI10 √ √ √ √ SCK11 I/O Clock input/output for CSI11 √ √ √ ⎯ SI00 Input Serial data input to CSI00 √ √ √ √ SI01 Input Serial data input to CSI01 √ √ √ √ SI10 Input Serial data input to CSI10 √ √ √ √ SI11 Input Serial data input to CSI11 √ √ √ ⎯ SO00 Output Serial data output from CSI00 √ √ √ √ SO01 Output Serial data output from CSI01 √ √ √ √ SO10 Output Serial data output from CSI10 √ √ √ √ SO11 Output Serial data output from CSI11 √ √ √ ⎯ SSI00 Input Slave select input to CSI00 (SPI00) √ √ √ √ SSI01 Input Slave select input to CSI01 (SPI01) √ √ √ √ SSI10 Input Slave select input to CSI10 (SPI10) √ √ ⎯ ⎯ SSI11 Input Slave select input to CSI11 (SPI11) √ √ √ ⎯ LRXD0 Input Serial data input to LIN √ √ √ √ LTXD0 Output Serial data output from LIN √ √ √ √

RL78/F23, F24 2. PIN FUNCTIONS R01DS0446EJ0120 Rev.1.20 Page 38 of 207 Dec 31, 2025 Table 2-3. List of RL78/F23 Pins Other than Port Pins (4/5) Pin Function I/O Function Pin Count 80-pin 64-pin 48-pin 32-pin INTP0 Input External interrupt input √ √ √ √ INTP1 Input √ √ √ √ INTP2 Input √ √ √ √ INTP3 Input √ √ √ √ INTP4 Input √ √ √ √ INTP5 Input √ √ √ √ INTP6 Input √ √ √ ⎯ INTP7 Input √ √ √ ⎯ INTP8 Input √ √ √ ⎯ INTP9 Input √ √ √ ⎯ INTP10 Input √ √ ⎯ ⎯ INTP11 Input √ √ ⎯ ⎯ INTP12 Input √ √ ⎯ ⎯ INTP13 Input √ ⎯ ⎯ ⎯ PCLBUZ0 Output Clock output/buzzer output 0 √ √ √ ⎯ RESOUT Output Reset output √ √ √ ⎯ STOPST Output STOP status output √ √ √ ⎯ SNZOUT0 Output SNOOZE status output √ √ √ √ SNZOUT1 Output √ √ √ √ SNZOUT2 Output √ √ √ √ SNZOUT3 Output √ √ √ √ SNZOUT4 Output √ √ √ ⎯ SNZOUT5 Output √ √ √ ⎯ SNZOUT6 Output √ √ √ ⎯ SNZOUT7 Output √ √ √ ⎯ RTC1HZ Output Real-time clock correction clock (1 Hz) output √ √ √ √

RL78/F23, F24 2. PIN FUNCTIONS R01DS0446EJ0120 Rev.1.20 Page 39 of 207 Dec 31, 2025 Table 2-3. List of RL78/F23 Pins Other than Port Pins (5/5) Pin Function I/O Function Pin Count 80-pin 64-pin 48-pin 32-pin EXCLK Input External clock input for main system clock √ √ √ √ EXCLKS Input External clock input for subsystem clock √ √ √ ⎯ X1 ⎯ Resonator connection for main system clock √ √ √ √ XT1 Note ⎯ Resonator connection for subsystem clock √ √ √ ⎯ RESET Input External reset input √ √ √ √ REGC ⎯ Regulator output stabilizat ion capacitance connection for internal operation. Connect to VSS via the capacitor (0.47 to 1 μF). √ √ √ √ VDD ⎯ Positive power supply for the P33, P34, P80 to P87, P90 to P97, P121 to P124, P137, and RESET pins √ √ √ √ EVDD0 ⎯ Positive power supply for the pins that are not connected to VDD √ √ ⎯ ⎯ AVREFP Input A/D converter reference voltage (+ side) input √ √ √ √ AVREFM Input A/D converter reference voltage (- side) input √ √ √ √ VSS ⎯ Ground potential for the P33, P34, P80 to P87, P90 to P97, P121 to P124, P137, and RESET pins √ √ √ √ EVSS0 ⎯ Ground potential for the pins that are not connected to VSS √ √ ⎯ ⎯ TOOLRXD Input UART reception pin fo r the external device connection used during flash memory programming √ √ √ √ TOOLTXD Output UART transmission pi n for the external device connection used during flash memory programming √ √ √ √ TOOL0 I/O Data input/output for flash memory programmer/debugger √ √ √ √ Note Do not use the XT1 and XT2 pin functions in grade-5 products.

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 40 of 207 Dec 31, 2025 3. ELECTRICAL SPECIFICATIONS (GRADE 3) Cautions 1. RL78/F23 and RL78/F24 have an on-chip debug function, which is provided for development and evaluation. Do not use the on-ch ip debug function in products designate d for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. 2. With products not provided with an EV DD0, EVDD1, EVSS0, or EVSS1 pin, replace EVDD0 and EVDD1 with VDD, or replace EVSS0 and EVSS1 with VSS. 3. The pins mounted depending on the product. For details, refer to 1.5 Pin Configurations and 2.1 Pin Function List.

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 41 of 207 Dec 31, 2025

3.1 Absolute Maximum Ratings

(1/3) Parameter Symbol Conditions Ratings Unit Supply voltage V DD -0.5 to +6.5 V EVDD0, EVDD1 EV DD0 = EVDD1 = VDD -0.5 to +6.5 V VSS -0.5 to +0.3 V EVSS0, EVSS1 EV SS0 = EVSS1 -0.5 to +0.3 V REGC pin input voltage V IREGC REGC -0.3 to +2.8 and -0.3 to VDD + 0.3 Note 1 V Input voltage V I1 P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P140, P150 to P157 -0.3 to EV DD0 + 0.3 and -0.3 to VDD + 0.3 Note 2 V VI2 P33, P34, P80 to P87, P90 to P97, P100 to P105, P121 to P124, P137, RESET -0.3 to VDD + 0.3 Note 2 V Output voltage V O1 P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P130, P140, P150 to P157 -0.3 to EV DD0 + 0.3 and -0.3 to VDD + 0.3 Note 2 V VO2 P33, P34, P80 to P87, P90 to P97, P100 to P105 -0.3 to V DD + 0.3 V Analog input voltage V AI1 ANI24 to ANI30 -0.3 to EV DD0+ 0.3 and -0.3 to AVREF(+) + 0.3 Notes 2, 3 V VAI2 ANI0 to ANI23 -0.3 to V DD + 0.3 and -0.3 to AVREF(+) + 0.3 Notes 2, 3 V Notes 1. Connect the REGC pin to VSS via a capacitor (0.47 to 1 µF). This value regulates the absolute maximum rating of the REGC pin. Do not use this pin with voltage applied to it. 2. Must be 6.5 V or lower. 3. For pins to be used in A/D conversion, the voltage should not exceed the value AVREF (+) + 0.3. Caution Product quality may suffer if the absolute m aximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, t he characteristics of alternate-function pins are the same as those of the port pins.

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 42 of 207 Dec 31, 2025 (2/3) Parameter Symbol Conditions Ratings Unit Output current, high I OH1 Per pin P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P130, P140, P150 to P157 -40 mA Total of all pins -170 mA P01, P02, P40 to P47, P120, P125 to P127, P150 to P153 -70 mA P00, P03, P10 to P17, P30 to P32, P50 to P57, P60 to P67, P70 to P77, P106, P107, P130, P140, P154 to P157 -100 mA IOH2 Per pin P33, P34, P80 to P87, P90 to P97, P100 to P105 -0.5 mA Total of all pins -2 mA Output current, low I OL1 Per pin P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P130, P140, P150 to P157 40 mA Total of all pins 170 mA P01, P02, P40 to P47, P120, P125 to P127, P150 to P153 70 mA P00, P03, P10 to P17, P30 to P32, P50 to P57, P60 to P67, P70 to P77, P106, P107, P130, P140, P154 to P157 100 mA IOL2 Per pin P33, P34, P80 to P87, P90 to P97, P100 to P105 1 mA Total of all pins 5 mA Caution Product quality may suffer if the absolute m aximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, t he characteristics of alternate-function pins are the same as those of the port pins.

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 43 of 207 Dec 31, 2025 (3/3) Parameter Symbol Conditions Ratings Unit Positive injected current I > VDD) Note IINJP Per pin P00 to P03, P10 to P17, P30 to P32, P41 to P47, P50 to P57, P60 to P67, P75 to P77, P106, P107, P126, P127, P140, P150 to P157 5 mA P70 to P74, P80 to P87, P90 to P97, P100 to P105, P120, P125 2 mA Negative injected current I < VSS) Note IINJN Per pin P00 to P03, P10 to P17, P30 to P32, P41 to P47, P50 to P57, P60 to P67, P75 to P77, P106, P107, P126, P127, P140, P150 to P157 -5 mA P70 to P74, P80 to P87, P90 to P97, P100 to P105, P120, P125 -0.5 mA Sum of all positive injected currents Note ΣIINJP Total of all pins P00 to P03, P10 to P17, P30 to P32, P41 to P47, P50 to P57, P60 to P67, P75 to P77, P106, P107, P126, P127, P140, P150 to P157 40 mA P70 to P74, P80 to P87, P90 to P97, P100 to P105, P120, P125 10 mA Sum of all negative injected currents Note ΣIINJN Total of all pins P00 to P03, P10 to P17, P30 to P32, P41 to P47, P50 to P57, P60 to P67, P75 to P77, P106, P107, P126, P127, P140, P150 to P157 -40 mA P70 to P74, P80 to P87, P90 to P97, P100 to P105, P120, P125 -2 mA Total of all injected currents Note Σ|IINJP| + Σ|IINJN| Total of all pins P00 to P03, P10 to P17, P30 to P32, P41 to P47, P50 to P57, P60 to P67, P75 to P77, P106, P107, P126, P127, P140, P150 to P157 40 mA P70 to P74, P80 to P87, P90 to P97, P100 to P105, P120, P125 10 mA Operating ambient temperature TA In normal operation mode -40 to +105 °C In flash memory programming mode Storage temperature T stg -65 to +150 °C Note Conditions: 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V Caution Product quality may suffer if the absolute m aximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. 2. V I :This is the input voltage level to the port pins.

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 44 of 207 Dec 31, 2025

3.2 Oscillator Characteristics

3.2.1 Main System Clock Oscillator Characteristics

(TA = -40 to +105°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit Ceramic resonator/ Crystal resonator X1 clock oscillation frequency (fx) 2.7 V ≤ VDD ≤ 5.5 V 2.0 20.0 MHz Cautions 1. When using the X1 oscilla tor, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance.  Keep the wiring length as short as possible.  Do not cross the wiring with the other signal lines.  Do not route the wiring near a signal line through which a high fluctuating current flows.  Always make the ground point of the oscillator capacitor the same potential as VSS.  Do not ground the capacitor to a ground pattern through which a high current flows.  Do not fetch signals from the oscillator. 2. Customers are requested to consult the resonato r manufacturer to select an appropriate resonator and to determine the proper osc illation constant. Customers are also requested to adequately evaluate the oscillation on their system. Determine the X1 clock oscillation stabilization time using the oscillation stabilization time of the oscillation stabilization time counter status register (OSTC) and the oscillation stabilizati on time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. Rd X2X1VSS C1 C2

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 45 of 207 Dec 31, 2025

3.2.2 On-chip Oscillator Characteristics

(TA = -40 to +105°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Oscillators Symbol Conditions MIN. TYP. MAX. Unit High-speed on-chip oscillator clock frequency Note fIH 2 80 MHz High-speed on-chip oscillator clock frequency accuracy – -2.0 +2.0 % Low-speed on-chip oscillator clock frequency fIL, fWDT 15 kHz Low-speed on-chip oscillator clock frequency accuracy – -15 +15 % Note High-speed on-chip oscillator frequency is selected with bits 0 to 4 of the option byte (000C2H/040C2H) and bits 0 to 2 of the HOCODIV register.

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 46 of 207 Dec 31, 2025

3.2.3 Subsystem Clock Oscillator Characteristics

(TA = -40 to +105°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Resonator Recommended Circuit Item C onditions MIN. TYP. MAX. Unit Crystal resonator Cautions 1. When using the XT1 oscilla tor, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance.  Keep the wiring length as short as possible.  Do not cross the wiring with the other signal lines.  Do not route the wiring near a signal line through which a high fluctuating current flows.  Always make the ground point of the oscillator capacitor the same potential as VSS.  Do not ground the capacitor to a ground pattern through which a high current flows.  Do not fetch signals from the oscillator. 2. The XT1 oscillator is designed as a low-amplitude circuit for reducing power consumption and thus required to be adequately evaluated on the system. Customers are requested to consult the resonator manufacturer to select an appropriate resonator and to determine the proper oscillation constant. Rd XT2XT1VSS C3 C4

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 47 of 207 Dec 31, 2025

3.2.4 PLL Circuit Characteristics

(TA = -40 to +105°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Resonator Symbol Conditions MIN. TYP. MAX. Unit PLL input enable clock frequency Note 1 fPLLI f MAIN: 4.0 MHz FMAINDIV[1:0] = 00B 3.92 4.0 4.08 MHz fMAIN: 8.0 MHz FMAINDIV[1:0] = 00B 7.84 8.0 8.16 MHz fMAIN: 16.0 MHz FMAINDIV[1:0] = 10B 7.84 8.0 8.16 MHz fMAIN: 20.0 MHz FMAINDIV[1:0] = 11B 4.90 5.0 5.10 MHz PLL output frequency (center value) f PLL f MAIN: 20 MHz, PLLMULA = 0, PLLMUL = 1 PLLDIV0 = 0, FPLLDIV = 0, PLLDIV1 = 0 fPLLI × 16/2 MHz PLLDIV0 = 0, FPLLDIV = 1, PLLDIV1 = 1 fPLLI × 16 MHz fMAIN: 4 MHz, PLLMULA = 1, PLLMUL = 1 PLLDIV0 = 0, FPLLDIV = 0, PLLDIV1 = 0 fPLLI × 20/2 MHz PLLDIV0 = 0, FPLLDIV = 1, PLLDIV1 = 1 fPLLI × 20 MHz fMAIN: 8 MHz or 16 MHz, PLLMULA = 0, PLLMUL = 0 PLLDIV0 = 1, FPLLDIV = 0, PLLDIV1 = 0 fPLLI × 12/4 MHz PLLDIV0 = 0, FPLLDIV = 0, PLLDIV1 = 1 fPLLI × 12/2 MHz fMAIN: 8 MHz or 16 MHz, PLLMULA = 0, PLLMUL = 1 PLLDIV0 = 1, FPLLDIV = 0, PLLDIV1 = 0 fPLLI × 16/4 MHz PLLDIV0 = 0, FPLLDIV = 0, PLLDIV1 = 1 fPLLI × 16/2 MHz fMAIN: 8 MHz or 16 MHz, PLLMULA = 1, PLLMUL = 0 PLLDIV0 = 0, FPLLDIV = 0, PLLDIV1 = 0 fPLLI × 10/2 MHz PLLDIV0 = 0, FPLLDIV = 1, PLLDIV1 = 1 fPLLI × 10 MHz Long-term jitter Note 2 t LJ term = 1 μs -1 +1 ns term = 10 μs -1 +1 ns term = 20 μs -2 +2 ns Notes 1. If the high-speed on-chip oscillator clock is to be sele cted as the PLL input clock, the minimum and maximum values will reflect the range of accuracy of the oscillation frequency by the high-speed on-chip oscillator clock. 2. Guaranteed by design, but not tested before shipment. Remark f MAIN: Main system clock frequency.

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 48 of 207 Dec 31, 2025

3.3 DC Characteristics

3.3.1 Pin Characteristics

For the relationship between the port pins shown in the following tables and the products, refer to 2. PIN FUNCTIONS. (TA = -40 to +105°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/6) Items Symbol Conditions MIN. TYP. MAX. Unit Output current, high Note 1 I OH1 Per pin for P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P130, P140, P150 to P157

4.0 V ≤ EV

DD0 ≤ 5.5 V -5.0 mA 2.7 V ≤ EVDD0 < 4.0 V -3.0 mA Per pin for P10, P12, P14, P30, P120, P140 (special slew rate) DD0 ≤ 5.5 V -0.6 mA 2.7 V ≤ EVDD0 < 4.0 V -0.2 mA Total of P01, P02, P40 to P47, P120, P125 to P127, P150 to P153 (for duty factors ≤ 70% Note 2) 4.0 V ≤ EVDD0 ≤ 5.5 V -20.0 mA 2.7 V ≤ EVDD0 < 4.0 V -10.0 mA Total of P00, P03, P10 to P17, P30 to P32, P50 to P57, P60 to P67, P70 to P77, P106, P107, P130, P140, P154 to P157 (for duty factors ≤ 70% Note 2) 4.0 V ≤ EVDD0 ≤ 5.5 V -30.0 mA 2.7 V ≤ EVDD0 < 4.0 V -19.0 mA Total of all pins (for duty factors ≤ 70% Note 2) 4.0 V ≤ EVDD0 ≤ 5.5 V -50.0 mA 2.7 V ≤ EVDD0 < 4.0 V -29.0 mA IOH2 Per pin for P33, P34, P80 to P87, P90 to P97, P100 to P105

2.7 V ≤ V

DD ≤ 5.5 V -0.1 mA Total of all pins (for duty factors ≤ 70% Note 2) 2.7 V ≤ VDD ≤ 5.5 V -2.0 mA Notes 1. Value of current at which the device operation is guaranteed even if the current flows from pins EV DD0, EVDD1 and VDD to an output pin. 2. These output current values are obtai ned under the condition that the du ty factor is no greater than 70%. The output current values when the duty factor is changed to a value greater than 70% can be calculated from the following expression (when the duty factor is changed to n%).

Total output current of pins (I OH × 0.7) / (n × 0.01) <Example> Where n = 80% and I OH = -10.0 mA Total output current of pins = (-10.0 × 0.7) / (80 × 0.01) ≈ -8.7 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maxi mum rating must not flow into one pin. Caution P10 to P17, P32, P60 to P63, P70 to P72, a nd P120 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, t he characteristics of alternate-function pins are the same as those of the port pins.

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 49 of 207 Dec 31, 2025 (TA = -40 to +105°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/6) Items Symbol Conditions MIN. TYP. MAX. Unit Output current, low Note 1 I OL1 Per pin for P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P130, P140, P150 to P157 DD0 ≤ 5.5 V 8.5 mA 2.7 V ≤ EVDD0 < 4.0 V 4.0 mA Per pin for P10, P12, P14, P30, P120, P140 (special slew rate) DD0 ≤ 5.5 V 0.59 mA 2.7 V ≤ EVDD0 < 4.0 V 0.07 mA Total of P01, P02, P40 to P47, P120, P125 to P127, P150 to P153 (for duty factors ≤ 70% Note 2) 4.0 V ≤ EVDD0 ≤ 5.5 V 20.0 mA 2.7 V ≤ EVDD0 < 4.0 V 15.0 mA Total of P00, P03, P10 to P17, P30 to P32, P50 to P57, P60 to P67, P70 to P77, P106, P107, P130, P140, P154 to P157 (for duty factors ≤ 70% Note 2) 4.0 V ≤ EVDD0 ≤ 5.5 V 45.0 mA 2.7 V ≤ EVDD0 < 4.0 V 35.0 mA Total of all pins (for duty factors ≤ 70% Note 2) 4.0 V ≤ EVDD0 ≤ 5.5 V 65.0 mA 2.7 V ≤ EVDD0 < 4.0 V 50.0 mA IOL2 Per pin for P33, P34, P80 to P87, P90 to P97, P100 to P105 DD ≤ 5.5 V 0.4 mA Total of all pins (for duty factors ≤ 70% Note 2) 2.7 V ≤ VDD ≤ 5.5 V 5.0 mA Notes 1. Value of current at which the device operation is guaranteed even if the current flows to the EVSS0, EVSS1 and VSS pins from an output pin. 2. These output current values are obtai ned under the condition that the du ty factor is no greater than 70%. The output current values when the duty factor is changed to a value greater than 70% can be calculated from the following expression (when the duty factor is changed to n%).

Total output current of pins (I OL × 0.7) / (n × 0.01) <Example> Where n = 80% and I OL = 10.0 mA Total output current of pins = (10.0 × 0.7) / (80 × 0.01) ≈ 8.7 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maxi mum rating must not flow into one pin. Remark Unless specified otherwise, t he characteristics of alternate-function pins are the same as those of the port pins.

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 50 of 207 Dec 31, 2025 (TA = -40 to +105°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (3/6) Items Symbol Conditions MIN. TYP. MAX. Unit Input voltage, high V IH1 P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P140, P150 to P157 (Schmitt 1 mode) DD0 ≤ 5.5 V 0.65 EVDD0 EV DD0 Note V 2.7 V ≤ EVDD0 < 4.0 V 0.7 EVDD0 EV DD0 Note V VIH2 P10, P11, P13, P14, P16, P17, P30, P41, P43, P50, P52 to P54, P60 to P63, P70, P71, P73, P75 to P77, P107, P120, P125, P150, P152, P153 (Schmitt 3 mode) DD0 ≤ 5.5 V 0.8 EVDD0 EV DD0 Note V 2.7 V ≤ EVDD0 < 4.0 V 0.85 EVDD0 EV DD0 Note V VIH3 P10, P11, P13, P14, P16, P17, P30, P54, P62, P63, P70, P71, P73, P125 (TTL mode) DD0 ≤ 5.5 V 2.2 EV DD0 Note V 2.7 V ≤ EVDD0 < 4.0 V 2.0 EV DD0 Note V VIH4 P33, P34, P80 to P87, P90 to P97, P100 to P105, P137 (fixed to Schmitt 3 mode)

4.0 V ≤ V

DD ≤ 5.5 V 0.8 VDD V DD V 2.7 V ≤ VDD < 4.0 V 0.85 VDD V DD V VIH5 RESET (fixed to Schmitt 1 mode) 4.0 V ≤ VDD ≤ 5.5 V 0.65 VDD V DD V 2.7 V ≤ VDD < 4.0 V 0.7 VDD V DD V VIH6 P121 to P124, EXCLK, EXCLKS (fixed to Schmitt 2 mode) DD ≤ 5.5 V 0.8 VDD V DD V 2.7 V ≤ VDD < 4.0 V 0.8 VDD V DD V Note The maximum value of V IH of the pins P10 to P17, P32, P60 to P63, P70 to P72, and P120 is EV DD0, even in N-ch open-drain mode. Remark Unless specified otherwise, t he characteristics of alternate-function pins are the same as those of the port pins.

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 51 of 207 Dec 31, 2025 (TA = -40 to +105°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (4/6) Items Symbol Conditions MIN. TYP. MAX. Unit Input voltage, low V IL1 P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P140, P150 to P157 (Schmitt 1 mode) DD0 ≤ 5.5 V 0 0.35 EV DD0 V 2.7 V ≤ EVDD0 < 4.0 V 0 0.3 EV DD0 V VIL2 P10, P11, P13, P14, P16, P17, P30, P41, P43, P50, P52 to P54, P60 to P63, P70, P71, P73, P75 to P77, P107, P120, P125, P150, P152, P153 (Schmitt 3 mode) DD0 ≤ 5.5 V 0 0.5 EV DD0 V 2.7 V ≤ EVDD0 < 4.0 V 0 0.4 EV DD0 V VIL3 P10, P11, P13, P14, P16, P17, P30, P54, P62, P63, P70, P71, P73, P125 (TTL mode) DD0 ≤ 5.5 V 0 0.8 V 2.7 V ≤ EVDD0 < 4.0 V 0 0.5 V VIL4 P33, P34, P80 to P87, P90 to P97, P100 to P105, P137 (fixed to Schmitt 3 mode) DD ≤ 5.5 V 0 0.5 V DD V 2.7 V ≤ VDD < 4.0 V 0 0.4 V DD V VIL5 RESET (fixed to Schmitt 1 mode) 4.0 V ≤ VDD ≤ 5.5 V 0 0.35 V DD V 2.7 V ≤ VDD < 4.0 V 0 0.3 V DD V VIL6 P121 to P124, EXCLK, EXCLKS (fixed to Schmitt 2 mode) DD ≤ 5.5 V 0 0.2 V DD V 2.7 V ≤ VDD < 4.0 V 0 0.2 V DD V Remark Unless specified otherwise, t he characteristics of alternate-function pins are the same as those of the port pins.

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 52 of 207 Dec 31, 2025 (TA = -40 to +105°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (5/6) Items Symbol Conditions MIN. TYP. MAX. Unit Output voltage, high V OH1 P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P130, P140, P150 to P157 (normal slew rate) DD0 ≤ 5.5 V, IOH1 = -5.0 mA EVDD0 - 0.9 V 2.7 V ≤ EVDD0 ≤ 5.5 V, IOH1 = -3.0 mA EVDD0 - 0.7 V 2.7 V ≤ EVDD0 ≤ 5.5 V, IOH1 = -1.0 mA EVDD0 - 0.5 V VOH2 P33, P34, P80 to P87, P90 to P97, P100 to P105 2.7 V ≤ VDD ≤ 5.5 V IOH2 = -100 µA VDD - 0.5 V VOH3 P10, P12, P14, P30, P120, P140 (special slew rate) DD0 ≤ 5.5 V, IOH3 = -0.6 mA EVDD0 - 0.8 V 2.7 V ≤ EVDD0 ≤ 5.5 V, IOH3 = -0.2 mA EVDD0 - 0.5 V Output voltage, low V OL1 P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P130, P140, P150 to P157 (normal slew rate) DD0 ≤ 5.5 V, IOL1 = 8.5 mA 0.7 V 4.0 V ≤ EVDD0 ≤ 5.5 V, IOL1 = 4.0 mA 0.4 V 2.7 V ≤ EVDD0 ≤ 5.5 V, IOL1 = 4.0 mA 0.7 V 2.7 V ≤ EVDD0 ≤ 5.5 V, IOL1 = 1.5 mA 0.4 V VOL2 P33, P34, P80 to P87, P90 to P97, P100 to P105 2.7 V ≤ VDD ≤ 5.5 V IOL2 = 400 µA 0.4 V VOL3 P10, P12, P14, P30, P120, P140 (special slew rate) DD0 ≤ 5.5 V, IOL3 = 0.6 mA 0.8 V 2.7 V ≤ EVDD0 ≤ 5.5 V, IOL3 = 0.07 mA 0.5 V Caution P10 to P17, P32, P60 to P63, P70 to P72, a nd P120 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, t he characteristics of alternate-function pins are the same as those of the port pins.

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 53 of 207 Dec 31, 2025 (TA = -40 to +105°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (6/6) Items Symbol Conditions MIN. TYP. MAX. Unit Input leakage current, high ILIH1 P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P140, P150 to P157 V I = EVDD0 1 µA ILIH2 P33, P34, P80 to P87, P90 to P97, P100 to P105, P137, RESET V I = VDD 1 µA ILIH3 P121 to P124 (X1, X2, XT1, XT2, EXCLK, EXCLKS) VI = VDD In input port or external clock input 1 µA In resonator connection 10 µA Input leakage current, low ILIL1 P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P140, P150 to P157 V I = EVSS0 -1 µA ILIL2 P33, P34, P80 to P87, P90 to P97, P100 to P105, P137, RESET V I = VSS -1 µA ILIL3 P121 to P124 (X1, X2, XT1, XT2, EXCLK, EXCLKS) VI = VSS In input port or external clock input -1 µA In resonator connection -10 µA Positive injected current Notes 1, 4 IINJPRMS P00 to P03, P10 to P17, P30 to P32, P41 to P47, P50 to P57, P60 to P67, P75 to P77, P106, P107, P126, P127, P140, P150 to P157 Per pin, V I > EVDD0 0.4 mA Total of all pins, VI > EVDD0 4 mA P70 to P74, P80, P83 to P87 Note 2, P90 to P97, P100 to P105, P120, P125 Per pin, V I > VDD 0.15 mA Total of all pins, VI > VDD 1 mA P81 to P84 Note 3 Total of all pins, V I > VDD 0.15 mA On-chip pull-up resistance RU P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P140, P150 to P157 V I = EVSS0, in input port 10 20 100 kΩ Notes 1. These specifications are not te sted on sorting and are specified based on the device characterization. 2. For RL78/F24 product: P80, P86, P87 3. For RL78/F23 product: P81, P82 4. For RL78/F24 product, P85/ANI07/IV REF0 does not guarantee the electric al characteristics when a positive injection current is generated even if it is within the above specifications. Caution P10 to P17, P32, P60 to P63, P70 to P72, a nd P120 do not output high level in N-ch open-drain mode. Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. 2. VI :This is the input voltage level to the port pins.

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 54 of 207 Dec 31, 2025

3.3.2 Supply Current Characteristics

(1) RL78/F24 (TA = -40 to +105°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2) Items Symbol Conditions MIN. TYP. MAX. Unit Supply current Note 1 IDD1 Operating mode Normal operation Note 2 High-speed on- chip oscillator clock operation f IH = 80 MHz f CLK = 40 MHz Notes 3, 4 10.8 20.0 mA fIH = 40 MHz f CLK = fIH Notes 3, 4 10.1 18.3 mA fIH = 2 MHz f CLK = fIH Notes 3, 4 1.7 3.1 mA Resonator operation fMX = 20 MHz f CLK = fMX Notes 3, 5 5.6 10.3 mA fMX = 2 MHz f CLK = fMX Notes 3, 5 1.5 2.8 mA Resonator operation (PLL operation) (PLL input clock = f MX) fPLL = 80 MHz, fMX = 20 MHz fCLK = 40 MHz Notes 3, 6 10.6 20.0 mA fPLL = 40 MHz, fMX = 20 MHz fCLK = 40 MHz Notes 3, 6 10.2 18.3 mA fPLL = 40 MHz, fMX = 4 MHz fCLK = 40 MHz Notes 3, 6 9.9 17.8 mA Subsystem clock operation fSUB = 32.768 kHz fCLK = fSUB Note 7 7.6 250 µA Low-speed on- chip oscillator clock operation f IL = 15 kHz f CLK = fIL Note 8 4.2 250 µA Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0, VSS, or EVSS0. However, not including the current flowing into the I/O buffer and on- chip pull-up/pull-down resistors. 2. Current drawn when all the CP U instructions are executed. 3. The values below the MAX. column include the peripheral operation current (except for background operation (BGO)). However, the LVD circuit, A/D converter, D/A converter, and comparator are stopped. 4. When high-speed system clock, subsyst em clock, PLL clock, and low-speed on-chip oscillator clock are stopped. 5. When subsystem clock, PLL clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped. 6. When subsystem clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped. 7. When high-speed system clock, PLL cl ock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator are stopped, and with setting of ADSLP = 1. 8. When high-speed system clock, subsystem clock, PLL cl ock, and high-speed on-chip oscillator clock are stopped, and with setting of ADSLP = 1. Remarks 1. f MX: High-speed system clock frequency 2. f SUB: Subsystem clock frequency 3. f PLL: PLL clock frequency 4. f IH: High-speed on-chip oscillator clock frequency 5. f IL: Low-speed on-chip oscillator clock frequency 6. fCLK: CPU/peripheral hardware clock frequency

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 55 of 207 Dec 31, 2025 (TA = -40 to +105°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2) Items Symbol Conditions MIN. TYP. MAX. Unit Supply current Notes 1, 3 IDD2 HALT mode Note 2 High-speed on-chip oscillator clock operation f IH = 80 MHz f CLK = 40 MHz Note 5 3.4 12.0 mA fIH = 40 MHz f CLK = fIH Note 5 2.8 10.5 mA fIH = 2 MHz f CLK = fIH Note 5 0.5 1.8 mA Resonator operation f MX = 20 MHz f CLK = fMX Note 6 1.5 6.5 mA fMX = 2 MHz f CLK = fMX Note 6 0.3 1.8 mA Resonator operation (PLL operation) (PLL input clock = f MX) fPLL = 80 MHz, fMX = 20 MHz fCLK = 40 MHz Note 7 3.2 12.0 mA fPLL = 40 MHz, fMX = 20 MHz fCLK = 40 MHz Note 7 2.9 10.5 mA fPLL = 40 MHz, fMX = 4 MHz fCLK = 40 MHz Note 7 2.6 10.0 mA Subsystem clock operation fSUB = 32.768 kHz fCLK = fSUB Note 8 0.8 140 µA Low-speed on-chip oscillator clock operation f IL = 15 kHz f CLK = fIL Note 9 0.8 140 µA IDD3 STOP mode Note 4 TA = +25°C 0.6 µA TA = +50°C 10 TA = +70°C 25 TA = +105°C 115 ISNOZ SNOOZE mode DTC operation 7.0 mA Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0, VSS, or EVSS0. However, not including the current flowing into the I/O buffer and on- chip pull-up/pull-down resistors. 2. When HALT mode is entered during fetch from the flash memory. 3. The values below the MAX. column include the pe ripheral operation current and STOP leakage current. However, the watchdog timer, LVD circuit, A/D converter, D/A converter, and comparator are stopped. 4. When high-speed system clock, subsystem clock, PLL cl ock, high-speed on-chip oscillator clock, and low- speed on-chip oscillator clock are stopped. 5. When high-speed system clock, subsyst em clock, PLL clock, and low-speed on-chip oscillator clock are stopped. 6. When subsystem clock, PLL clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped. 7. When subsystem clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped. 8. When high-speed system clock, PLL cl ock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped, and with setting of ADSLP = 1. 9. When high-speed system clock, subsystem clock, PLL cl ock, and high-speed on-chip oscillator clock are stopped, and with setting of ADSLP = 1. Remarks 1. f MX: High-speed system clock frequency 2. fSUB: Subsystem clock frequency 3. fPLL: PLL clock frequency 4. fIH: High-speed on-chip oscillator clock frequency 5. fIL: Low-speed on-chip oscillator clock frequency 6. fCLK: CPU/peripheral hardware clock frequency

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 56 of 207 Dec 31, 2025 (TA = -40 to +105°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Window watchdog timer operating current IWDT Notes 1, 2 f WDT = 15 kHz 0.3 µA A/D converter operating current I ADC Note 3 When conversion at maximum speed AVREFP = VDD = 5.0 V 1.3 1.7 mA When internal reference voltage is selected Note 5 75.0 µA AVREFP current I ADREF Note 7 AV REFP = 5.0 V 65.0 µA Sample-and-hold circuit operating current IADSH Note 8 0.8 1.2 mA LVD operating current I LVD Note 4 0.08 µA D/A converter operating current I DAC 0.8 1.5 mA Comparator operating current I CMP 50.0 µA BGO operating current I BGO Note 6 2.5 12.2 mA Notes 1. When the high-speed on-chip oscillator clock and high-speed system clock are stopped. 2. Current flowing only to the watchdog timer (including the operation current of the 15 kHz on-chip oscillator). The current value is the sum of IDD1, IDD2, or IDD3 and IWDT when the watchdog timer operates in STOP mode. 3. Current flowing only to the A/D converte r. The current value is the sum of I DD1 or IDD2 and IADC when the A/D converter operates in operation mode or HALT mode. 4. Current flowing only to the LVD circuit. The current value is the sum of IDD1, IDD2, or IDD3 and ILVD when the LVD circuit operates in operation mode, HALT mode, or STOP mode. 5. Operating current that increases when the internal reference voltage is selected. This current flows even when conversion is stopped. 6. Current increased by the BGO operation. The current value is the sum of I DD1 or IDD2 and IBGO when the BGO operates in operation mode or HALT mode. 7. Operating current that increases when the AV REFP is selected. This current flows even when conversion is stopped. 8. Operating current that increases when the sample-and-hol d circuit is used. This current flows for each analog input channel.

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 57 of 207 Dec 31, 2025 (2) RL78/F23 (TA = -40 to +105°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2) Items Symbol Conditions MIN. TYP. MAX. Unit Supply current Note 1 IDD1 Operating mode Normal operation Note 2 High-speed on- chip oscillator clock operation f IH = 80 MHz f CLK = 40 MHz Notes 3, 4 9.7 17.0 mA fIH = 40 MHz f CLK = fIH Notes 3, 4 9.0 15.5 mA fIH = 2 MHz f CLK = fIH Notes 3, 4 1.6 2.8 mA Resonator operation fMX = 20 MHz f CLK = fMX Notes 3, 5 5.0 9.0 mA fMX = 2 MHz f CLK = fMX Notes 3, 5 1.4 2.6 mA Resonator operation (PLL operation) (PLL input clock = f MX) fPLL = 80 MHz, fMX = 20 MHz fCLK = 40 MHz Notes 3, 6 9.2 17.0 mA fPLL = 40 MHz, fMX = 20 MHz fCLK = 40 MHz Notes 3, 6 9.0 15.5 mA fPLL = 40 MHz, fMX = 4 MHz fCLK = 40 MHz Notes 3, 6 8.6 15.0 mA Subsystem clock operation fSUB = 32.768 kHz fCLK = fSUB Note 7 6.5 100 µA Low-speed on- chip oscillator clock operation f IL = 15 kHz f CLK = fIL Note 8 3.3 100 µA Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0, VSS, or EVSS0. However, not including the current flowing into the I/O buffer and on- chip pull-up/pull-down resistors. 2. Current drawn when all the CP U instructions are executed. 3. The values below the MAX. column include the peripheral operation current (except for background operation (BGO)). However, the LVD circuit and A/D converter are stopped. 4. When high-speed system clock, subsyst em clock, PLL clock, and low-speed on-chip oscillator clock are stopped. 5. When subsystem clock, PLL clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped. 6. When subsystem clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped. 7. When high-speed system clock, PLL cl ock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator are stopped, and with setting of ADSLP = 1. 8. When high-speed system clock, subsystem clock, PLL cl ock, and high-speed on-chip oscillator clock are stopped, and with setting of ADSLP = 1. Remarks 1. f MX: High-speed system clock frequency 2. f SUB: Subsystem clock frequency 3. f PLL: PLL clock frequency 4. f IH: High-speed on-chip oscillator clock frequency 5. f IL: Low-speed on-chip oscillator clock frequency 6. fCLK: CPU/peripheral hardware clock frequency

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 58 of 207 Dec 31, 2025 (TA = -40 to +105°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2) Items Symbol Conditions MIN. TYP. MAX. Unit Supply current Notes 1, 3 IDD2 HALT mode Note 2 High-speed on-chip oscillator clock operation f IH = 80 MHz f CLK = 40 MHz Note 5 3.4 11.0 mA fIH = 40 MHz f CLK = fIH Note 5 2.8 9.5 mA fIH = 2 MHz f CLK = fIH Note 5 0.5 1.5 mA Resonator operation f MX = 20 MHz f CLK = fMX Note 6 1.5 5.5 mA fMX = 2 MHz f CLK = fMX Note 6 0.3 1.5 mA Resonator operation (PLL operation) (PLL input clock = fMX) fPLL = 80 MHz, fMX = 20 MHz fCLK = 40 MHz Note 7 3.1 11.0 mA fPLL = 40 MHz, fMX = 20 MHz fCLK = 40 MHz Note 7 2.8 9.5 mA fPLL = 40 MHz, fMX = 4 MHz fCLK = 40 MHz Note 7 2.5 9.0 mA Subsystem clock operation fSUB = 32.768 kHz fCLK = fSUB Note 8 0.7 66 µA Low-speed on-chip oscillator clock operation f IL = 15 kHz f CLK = fIL Note 9 0.7 66 µA IDD3 STOP mode Note 4 TA = +25°C 0.5 µA TA = +50°C 4.5 TA = +70°C 9.0 TA = +105°C 51 ISNOZ SNOOZE mode DTC operation 6.0 mA Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0, VSS, or EVSS0. However, not including the current flowing into the I/O buffer and on- chip pull-up/pull-down resistors. 2. When HALT mode is entered during fetch from the flash memory. 3. The values below the MAX. column include the pe ripheral operation current and STOP leakage current. However, the watchdog timer, LVD circuit, and A/D converter are stopped. 4. When high-speed system clock, subsystem clock, PLL cl ock, high-speed on-chip oscillator clock, and low- speed on-chip oscillator clock are stopped. 5. When high-speed system clock, subsyst em clock, PLL clock, and low-speed on-chip oscillator clock are stopped. 6. When subsystem clock, PLL clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped. 7. When subsystem clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped. 8. When high-speed system clock, PLL cl ock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped, and with setting of ADSLP = 1. 9. When high-speed system clock, subsystem clock, PLL cl ock, and high-speed on-chip oscillator clock are stopped, and with setting of ADSLP = 1. Remarks 1. f MX: High-speed system clock frequency 2. fSUB: Subsystem clock frequency 3. fPLL: PLL clock frequency 4. fIH: High-speed on-chip oscillator clock frequency 5. fIL: Low-speed on-chip oscillator clock frequency 6. fCLK: CPU/peripheral hardware clock frequency

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 59 of 207 Dec 31, 2025 (TA = -40 to +105°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Window watchdog timer operating current IWDT Notes 1, 2 f WDT = 15 kHz 0.3 µA A/D converter operating current IADC Note 3 When conversion at maximum speed AVREFP = VDD = 5.0 V 1.3 1.7 mA When internal reference voltage is selected Note 5 75.0 µA AVREFP current I ADREF Note 7 AV REFP = 5.0 V 65.0 µA Sample-and-hold circuit operating current IADSH Note 8 0.8 1.2 mA LVD operating current I LVD Note 4 0.08 µA BGO operating current I BGO Note 6 2.5 12.2 mA Notes 1. When the high-speed on-chip oscillator clock and high-speed system clock are stopped. 2. Current flowing only to the watchdog timer (including t he operation current of the 15 kHz on-chip oscillator). The current value is the sum of IDD1, IDD2, or IDD3 and IWDT when the watchdog timer operates in STOP mode. 3. Current flowing only to the A/D converte r. The current value is the sum of I DD1 or IDD2 and IADC when the A/D converter operates in operation mode or HALT mode. 4. Current flowing only to the LVD circuit. The current value is the sum of IDD1, IDD2, or IDD3 and ILVD when the LVD circuit operates in operation mode, HALT mode, or STOP mode. 5. Operating current that increases when the internal reference voltage is selected. This current flows even when conversion is stopped. 6. Current increased by the BGO operation. The current value is the sum of I DD1 or IDD2 and IBGO when the BGO operates in operation mode or HALT mode. 7. Operating current that increases when the AV REFP is selected. This current flows even when conversion is stopped. 8. Operating current that increases when the sample-and-hol d circuit is used. This current flows for each analog input channel.

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 60 of 207 Dec 31, 2025

3.4 AC Characteristics

3.4.1 Basic Operation

(TA = -40 to +105°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Instruction cycle (minimum instruction execution time) TCY High-speed on-chip oscillator clock operation 0.025 0.5 µs High-speed system clock operation 0.05 0.5 µs PLL clock operation 0.025 0.5 µs Subsystem clock operation 28.5 30.5 34.5 µs Low-speed on-chip oscillator clock operation 66.6 µs In self programming mode 0.025 0.5 µs CPU/peripheral hardware clock frequency fCLK 0.025 66.6 µs External system clock frequency fEX 2.0 20.0 MHz fEXS 29 35 kHz External system clock input high-level width, low-level width t EXH, tEXL 24 ns tEXHS, tEXLS 13.7 µs TI00 to TI07, TI10 to TI17 input high-level width, low- level width t TIH, tTIL 1/f MCK+10 ns TO00 to TO07, TO10 to TO17, TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1, TRJIO0, TRJO0 output frequency f TO Normal slew rate, C = 30 pF 4.0 V ≤ EVDD0 ≤ 5.5 V 16 MHz 2.7 V ≤ EVDD0 < 4.0 V 8 MHz TO01, TO06, TO07, TO11, TO13, TRDIOC0, TRDIOD0, TRDIOD1, TRJO0 only, Special slew rate, C = 30 pF

2 MHz

PCLBUZ0 output frequency f PCL Normal slew rate C = 30 pF 4.0 V ≤ EVDD0 ≤ 5.5 V 16 MHz 2.7 V ≤ EVDD0 < 4.0 V 8 MHz Special slew rate C = 30 pF Timer RJ input cycle t C TRJIO0 100 ns Timer RJ input high-level width, low-level width tTJIH, tTJIL TRJIO0 40 ns Timer RDe input high-level, low-level width tTDIH, tTDIL TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1, TRDCLK0, TRD0RES, TRD1RES 3/f TRD ns Timer RDe pulse output forced cutoff signal low-level width tTDSIL P137/INTP0 2 MHz < fCLK ≤ 40 MHz 1 µs fCLK ≤ 2 MHz 1/fCLK + 1 µs Caution Excluding the error in oscillation frequency accuracy. Remarks 1. f MCK: Timer array unit operation clock frequency 2. fTRD: Timer RDe operation clock frequency

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 61 of 207 Dec 31, 2025 (TA = -40 to +105°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2) Notes 1. Pins RESET, INTP0 to INTP3, INTP12, and INTP13 have noise filters for transient levels lasting less than 100 ns. 2. T A = +25°C, EVDD0 = 5.0 V AC Timing Test Points Test pointsVIH VIL VIH VIL Parameter Symbol Conditions MIN. TYP. MAX. Unit Interrupt input high-level width, low-level width tINTH, tINTL INTP0 to INTP13 Note 1 1 µs KR0 to KR7 key interrupt input low-level width tKR 250 ns RESET low-level width t RSL Note 1 10 µs Port output rise time, port output fall time tRO, tFO P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P130, P140, P150 to P157 (normal slew rate) C = 30 pF DD0 ≤ 5.5 V 25 ns 2.7 V ≤ EVDD0 < 4.0 V 55 ns P10, P12, P14, P30, P120, P140 (special slew rate) C = 30 pF DD0 ≤ 5.5 V 25 Note 2 60 ns 2.7 V ≤ EVDD0 < 4.0 V 100 ns

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 62 of 207 Dec 31, 2025 External System Clock Timing EXCLK EXCLKS TI/TO Timing TI00 to TI07, TI10 to TI17, TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1, TRDCLK0, TRD0RES, TRD1RES TO00 to TO07, TO10 to TO17, TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1, TRJIO0, TRJO0 TRJIO0 P137/INTP0 1/f EX t EXL t EX H 0.8 VDD (MIN.) 0.2 VDD (MAX.) 1/f EX S t EXLS t EXHS 0.8 VDD (MIN.) 0.2 VDD (MAX.) t TIL, t TDIL t TIH, t TDIH 1/f TO t TJIL t TJIH t TDSIL

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 63 of 207 Dec 31, 2025 Interrupt Request Input Timing INTP0 to INTP13 Key Interrupt Input Timing KR0 to KR7 RESET Input Timing RESET Output Rising and Falling Timing Output pin t INTL t INTH t KR t RSL t RO t FO

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 64 of 207 Dec 31, 2025

3.5 Peripheral Functions Characteristics

3.5.1 RAM can be written to Serial Array Unit

(1) During communication at same pot ential (UART mode) (dedicated baud rate generator output) (TA = -40 to +105°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate – f MCK/6 bps fCLK = 40 MHz, fMCK = fCLK Normal slew rate 6.6 Mbps Special slew rate 2 Mbps UART mode connection diagram (during communication at same potential) UART mode bit width (during communication at same potential) (reference) Caution Select the normal input buffer for the RXD0 pi n and RXD1 pin and normal output mode for the TXD0 pin and TXD1 pin. Remark fMCK: Serial array unit operation clock frequency User's deviceRL78 microcontroller TXD0, TXD1 RXD0, RXD1 RX TX Baud rate error tolerance 1/Transfer rate High-/low-bit width TXD0, TXD1 RXD0, RXD1

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 65 of 207 Dec 31, 2025 (2) During communication at same potential (CSI mode) (master mode, SCKp … internal clock output, normal slew rate) (TA = -40 to +105°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKp cycle time t KCY1 100 Note 5 ns SCKp high-level width, low-level width t KH1, tKL1 4.0 V ≤ EVDD0 ≤ 5.5 V tKCY1/2 – 12 ns 2.7 V ≤ EVDD0 < 4.0 V tKCY1/2 – 18 ns SIp setup time (to SCKp↑) Note 1 tSIK1 4.0 V ≤ EVDD0 ≤ 5.5 V 33 ns 2.7 V ≤ EVDD0 < 4.0 V 44 ns SIp hold time (from SCKp↑) Note 2 tKSI1 30 ns Delay time from SCKp↓ to SOp output Note 3 tKSO1 C = 30 pF Note 4 30 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The Slp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0 or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp ↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SCKp and SOp output lines. 5. t KCY1 ≥ 4/fMCK must also be satisfied. Caution Select the normal input buffer for the SIp pin and normal output mode for the SOp pin and SCKp pin. Remark p: CSIp (p = 00, 01, 10, 11), m: Unit m (m = 0, 1), n: Channel n (n = 0, 1) <R>

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 66 of 207 Dec 31, 2025 (3) During communication at same potential (CSI mode) (master mode, SCKp … internal clock output, special slew rate) (TA = -40 to +105°C, 4.0 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKp cycle time t KCY1 500 Note 5 ns SCKp high-level width, low-level width t KH1, tKL1 t KCY1/2 – 60 ns SIp setup time (to SCKp↑) Note 1 tSIK1 120 ns SIp hold time (from SCKp↑) Note 2 tKSI1 80 ns Delay time from SCKp↓ to SOp output Note 3 tKSO1 C = 30 pF Note 4 90 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The Slp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0 or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp ↓” when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp ↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SCKp and SOp output lines. 5. t KCY1 ≥ 4/fMCK must also be satisfied. Caution Select the normal input buffer for the SIp pin and normal output mode and special slew rate for the SOp pin and SCKp pin. Remark p: CSIp (p = 00, 01, 10, 11), m: Unit m (m = 0, 1), n: Channel n (n = 0, 1) <R>

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 67 of 207 Dec 31, 2025 (4) During communication at same potential (CSI mode) (s lave mode, SCKp … external clock input, normal slew rate) (TA = -40 to +105°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKp cycle time t KCY2 32 MHz < fMCK 10/fMCK ns fMCK ≤ 32 MHz 8/fMCK ns SCKp high-level width, low-level width tKH2, tKL2 t KCY2/2 ns SIp setup time (to SCKp↑) Note 1 tSIK2 1/f MCK + 20 ns SIp hold time (from SCKp↑) Note 2 tKSI2 1/f MCK + 31 ns Delay time from SCKp↓ to SOp output Note 3 tKSO2 C = 30 pF Note 4 4.0 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V 2/f MCK + 44 ns 2.7 V ≤ VDD = EVDD0 = EVDD1 < 4.0 V 2/f MCK + 57 ns SSIp setup time t SSIK DAP = 0 120 ns DAP = 1 1/f MCK + 120 ns SSIp hold time t KSSI DAP = 0 1/f MCK + 120 ns DAP = 1 120 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The Slp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0 or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp ↓” when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp ↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp, S CKp and SSIp pins and normal output mode for the SOp pin. Remarks 1. p: CSIp (p = 00, 01, 10, 11), m: Unit m (m = 0, 1), n: Channel n (n = 0, 1) 2. f MCK: Serial array unit operation clock frequency

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 68 of 207 Dec 31, 2025 (5) During communication at same potential (CSI mode) (sla ve mode, SCKp … external clock input, special slew rate) (TA = -40 to +105°C, 4.0 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKp cycle time t KCY2 20 MHz < fMCK 10/fMCK ns

10 MHz < fMCK ≤ 20 MHz 8/fMCK ns

fMCK ≤ 10 MHz 6/fMCK ns SCKp high-level width, low-level width t KH2, tKL2 t KCY2/2 ns SIp setup time (to SCKp↑) Note1 tSIK2 1/f MCK + 50 ns SIp hold time (from SCKp↑) Note 2 tKSI2 1/f MCK + 50 ns Delay time from SCKp↓ to SOp output Note 3 tKSO2 C = 30 pF Note 4 2/f MCK + 80 ns SSIp setup time t SSIK DAP = 0 120 ns DAP = 1 1/f MCK + 120 ns SSIp hold time t KSSI DAP = 0 1/f MCK + 120 ns DAP = 1 120 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The Slp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0 or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp ↓” when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp ↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp, SCKp and SSIp pins and normal output mode and special slew rate for the SOp pin. Remarks 1. p: CSIp (p = 00, 01, 10, 11), m: Unit m (m = 0, 1), n: Channel n (n = 0, 1) 2. f MCK: Serial array unit operation clock frequency

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 69 of 207 Dec 31, 2025 CSI mode connection diagram (during communication at same potential) CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1) Remark p: CSIp (p = 00, 01, 10, 11), m: Unit m (m = 0, 1), n: Channel n (n = 0, 1) RL78 microcontroller SCKp SSIp User's device SCK SOp SIp SO SI <Master> RL78 microcontroller SCKp SSIp User's device SCK SOp SIp SO SI <Slave> SSO t KCY2 t KL2 t KH2 Input data Output data t SI K2 t KSI2 t KSO2 t KSSI t SSIK SCKp SIp SOp SSIp

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 70 of 207 Dec 31, 2025 CSI mode serial transfer timing (during communication at same potential) (When DAPmn= 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0) Remark p: CSIp (p = 00, 01, 10, 11), m: Unit m (m = 0, 1), n: Channel n (n = 0, 1) t KCY1, 2 t KH1, 2 t KL1, 2 Input data Output data t SI K1, 2 t KSI1, 2 t KSO1, 2 t KSSI t SSIK SCKp SIp SOp SSIp

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 71 of 207 Dec 31, 2025 (6) During communication at same potential (simplified I 2C mode) (SDAr: N-ch open-drain output (EVDD tolerance) mode, SCLr: normal output mode) (TA = -40 to +105°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCLr clock frequency f SCL 1000 Note kHz Hold time when SCLr = “L” t LOW 475 ns Hold time when SCLr = “H” t HIGH 475 ns Data setup time (reception) t SU:DAT 1/f MCK + 85 ns Data hold time (transmission) t HD:DAT Cb = 50 pF, Rb = 2.7 kΩ 0 305 ns Note f CLK ≤ fMCK/4 must also be satisfied. Simplified I2C mode connection diagram (during communication at same potential) Simplified I2C mode serial transfer timing (during communication at same potential) Caution Select the normal input buffer and N-ch open-drain output mode for the SDAr pin and normal output mode for the SCLr pin. Remarks 1. R b [ Ω]: Communication line (SDAr) pull-up resistance, C b [F]: Communication line (SCLr, SDAr) load capacitance 3. f MCK: Serial array unit operation clock frequency User's deviceRL78 microcontroller SDAr SCLr SDA SCL VDD Rb 1/f SCL t LO W t HIGH SCLr SDAr t HD:DAT t SU:DAT

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 72 of 207 Dec 31, 2025 (7) During communication at same potential (simplified I 2C mode) (SDAr and SCLr: N-ch open-drain output (EVDD tolerance) mode) (TA = -40 to +105°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. MAX. Unit SCLr clock frequency f SCL 400 Note kHz Hold time when SCLr = “L” t LOW 4.0 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 1.7 kΩ 1300 ns 2.7 V ≤ VDD < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ Hold time when SCLr = “H” t HIGH 4.0 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 1.7 kΩ 600 ns 2.7 V ≤ VDD < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ Data setup time (reception) t SU:DAT 4.0 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 1.7 kΩ 1/fMCK + 120 ns 2.7 V ≤ VDD < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ 1/fMCK + 270 ns Data hold time (transmission) t HD:DAT 4.0 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 1.7 kΩ 0 300 ns 2.7 V ≤ VDD < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ Note f CLK ≤ fMCK/4 must also be satisfied. Simplified I2C mode connection diagram (during communication at same potential) Caution Select the normal input buffer and N-ch open-drain output mode for the SDAr pin and SCLr pin. Remarks 1. R b [Ω]: Communication line (SDAr, SCLr) pull-up resistance, Cb [F]: Communication line (SDAr, SCLr) load capacitance, Vb [V]: Communication line voltage 3. f MCK: Serial array unit operation clock frequency User's deviceRL78 microcontroller SDAr SCLr SDA SCL Vb Rb Vb Rb

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 73 of 207 Dec 31, 2025 Simplified I2C mode serial transfer timing (during communication at same potential) Remark r: IICr (r = 00, 01, 10, 11) 1/f SCL t LO W t HIGH SCLr SDAr t HD:DAT t SU:DAT

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 74 of 207 Dec 31, 2025 (8) Communication at different potential (UART mode) (T XD output buffer: N-ch open-drain, RXD input buffer: TTL) (TA = -40 to +105°C, 4.0 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate – Reception 2.7 V ≤ Vb ≤ EVDD0, VIH = 2.2 V, VIL = 0.8 V f MCK/6 bps Theoretical value of the maximum transfer rate Note (Cb = 30 pF)

5.3 Mbps

Transmission 2.7 V ≤ Vb ≤ EVDD0, VOH = 2.2 V, VOL = 0.8 V Smaller number of the values given by fMCK/6 and expression 1 is applicable. bps Theoretical value of the maximum transfer rate Note (Cb = 30 pF) Normal slew rate Note Expression 1: Maximum transfer rate = 1 / [{ -Cb × Rb × ln (1 - 2.2/Vb) } × 3] UART mode connection diagram (during communication at different potential) User's deviceRL78 microcontroller TXD0, TXD1 RXD0, RXD1 RX TX Vb Rb

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 75 of 207 Dec 31, 2025 UART mode bit width (during communication at different potential) (reference) Caution Select the TTL input buffer for the RXD0 pin and RXD1 pin and N-ch open-drain output mode for the TXD0 pin and TXD1 pin. Remarks 1. R b [Ω]: Communication line (TXD) pull-up resistance, Cb [F]: Communication line (TXD) load capacitance, Vb [V]: Communication line voltage 2. f MCK: Serial array unit operation clock frequency TXD0, TXD1 RXD0, RXD1 Baud rate error tolerance 1/Transfer rate High-/low-bit width Baud rate error tolerance 1/Transfer rate High-bit width Low-bit width

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 76 of 207 Dec 31, 2025 (9) During communication at different potential (3-V supply system) (CSI mode) (master mode, SCKp … internal clock output, normal slew rate) (TA = -40 to +105°C, 4.0 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKp cycle time t KCY1 2.7 V ≤ Vb ≤ EVDD0, Cb = 30 pF, Rb = 1.4 kΩ

400 Note3 ns

SCKp high-level width t KH1 2.7 V ≤ Vb ≤ EVDD0, Cb = 30 pF, Rb = 1.4 kΩ tKCY1/2 - 75 ns SCKp low-level width t KL1 2.7 V ≤ Vb ≤ EVDD0, Cb = 30 pF, Rb = 1.4 kΩ tKCY1/2 - 20 ns SIp setup time (to SCKp↑) Note 1 tSIK1 2.7 V ≤ Vb ≤ EVDD0, Cb = 30 pF, Rb = 1.4 kΩ 150 ns SIp setup time (to SCKp↓) Note 2 tSIK1 2.7 V ≤ Vb ≤ EVDD0, Cb = 30 pF, Rb = 1.4 kΩ 70 ns SIp hold time (from SCKp↑) Note 1 tKSI1 2.7 V ≤ Vb ≤ EVDD0, Cb = 30 pF, Rb = 1.4 kΩ 30 ns SIp hold time (from SCKp↓) Note 2 tKSI1 2.7 V ≤ Vb ≤ EVDD0, Cb = 30 pF, Rb = 1.4 kΩ 30 ns Delay time from SCKp↓ to SOp output Note1 tKSO1 2.7 V ≤ Vb ≤ EVDD0, Cb = 30 pF, Rb = 1.4 kΩ 120 ns Delay time from SCKp↑ to SOp output Note2 tKSO1 2.7 V ≤ Vb ≤ EVDD0, Cb = 30 pF, Rb = 1.4 kΩ 40 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. 2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. tKCY1 ≥ 4/fMCK must also be satisfied. CSI mode connection diagram (during communication at different potential) Caution Select the TTL input buffer for the SIp pin and N-ch open-drain output mode for the SOp pin and SCKp pin. Remarks 1. Rb [Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb [F]: Communication line (SOp, SCKp) load capacitance, Vb [V]: Communication line voltage 2. p: CSIp (p = 00, 01, 10, 11), m: Unit m (m = 0, 1), n: Channel n (n = 0, 1) 3. AC characteristics of the serial array unit during communication at different potential in CSI mode are measured with the VIH and VIL below: User's deviceRL78 microcontroller SCKp SSIp SCK SI Vb Rb Vb Rb SOp SIp SO <Master> <R>

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 77 of 207 Dec 31, 2025 CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1) CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn= 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0) Remark p: CSIp (p = 00, 01, 10, 11), m: Unit m (m = 0, 1), n: Channel n (n = 0, 1) t KCY1 t KL1 t KH1 Input data Output data t SI K1 t KSI1 t KSO1 SCKp SIp SOp t KCY1 t KH1 t KL1 Input data Output data t SI K1 t KSI1 t KSO1 SCKp SIp SOp

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 78 of 207 Dec 31, 2025 (10) During communication at different potential (3-V supply system) (CSI mode) (slave mode, SCKp … external clock input, normal slew rate) (TA = -40 to +105°C, 4.0 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKp cycle time t KCY2 2.7 V ≤ Vb ≤ VDD 32 MHz < fMCK 18/f MCK ns

24 MHz < fMCK ≤ 32 MHz 14/fMCK ns

20 MHz < fMCK ≤ 24 MHz 12/fMCK ns

8 MHz < fMCK ≤ 20 MHz 10/fMCK ns

4 MHz < fMCK ≤ 8 MHz 8/fMCK ns

fMCK ≤ 4 MHz 6/fMCK ns SCKp high-level width, low-level width tKH2, tKL2 2.7 V ≤ Vb ≤ VDD tKCY2/2 - 20 ns SIp setup time (to SCKp↑) Note 1 tSIK2 90 ns SIp hold time (from SCKp↑) Note 2 tKSI2 1/f MCK + 50 ns Delay time from SCKp↓ to SOp output Note 3 tKSO2 2.7 V ≤ Vb ≤ VDD, Cb = 30 pF, Rb = 1.4 kΩ 2/f MCK + 120 ns SSIp setup time t SSIK DAP = 0 120 ns DAP = 1 1/f MCK + 120 ns SSIp hold time t KSSI DAP = 0 1/f MCK + 120 ns DAP = 1 120 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The Slp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0 or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp ↓” when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp ↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 79 of 207 Dec 31, 2025 CSI mode connection diagram (during communication at different potential) Caution Select the TTL input buffer for the SIp, SCKp and SSIp pins and N-ch open-drain output mode for the SOp pin. Remarks 1. R b [Ω]: Communication line (SOp) pull-up resistance, Cb [F]: Communication line (SOp) load capacitance, Vb [V]: Communication line voltage 2. p: CSIp (p = 00, 01, 10, 11), m: Unit m (m = 0, 1), n: Channel n (n = 0, 1) 3. AC characteristics of the serial array unit during communication at different potential in CSI mode are measured with the VIH and VIL below: User's device RL78 microcontroller SCKp SSIp SCK SI Vb Rb SOp SIp SO ＜Slave＞ SSO

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 80 of 207 Dec 31, 2025 CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1) CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn= 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0) Remark p: CSIp (p = 00, 01, 10, 11), m: Unit m (m = 0, 1), n: Channel n (n = 0, 1) t KCY2 t KL2 t KH2 Input data Output data t SI K2 t KSI2 t KSO2 t KSSI t SSIK SCKp SIp SOp SSIp t KCY2 t KH2 t KL2 Input data t SI K2 t KSI2 t KSSI t SSIK SCKp SIp SSIp Output data t KSO2 SOp

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 81 of 207 Dec 31, 2025 (11) During communication at different pot ential (3-V supply system) (simplified I2C mode) (SDAr: TTL input buffer mode or N-ch open-drain output (EVDD tolerance) mode, SCLr: N-ch open-drain output (EVDD tolerance) mode) (TA = -40 to +105°C, 4.0 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. MAX. Unit SCLr clock frequency f SCL 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 1.4 kΩ

400 Note kHz

Hold time when SCLr = “L” t LOW 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 1.4 kΩ 1200 ns Hold time when SCLr = “H” t HIGH 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 1.4 kΩ 600 ns Data setup time (reception) t SU:DAT 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 1.4 kΩ 135 + 1/fMCK ns Data hold time (transmission) t HD:DAT 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 1.4 kΩ 0 140 ns Note fSCL ≤ fMCK/4 must also be satisfied. Simplified I2C mode connection diagram (during communication at different potential) Simplified I2C mode serial transfer timing (during communication at different potential) Caution Select the TTL input buffer and the N-ch open-drain output mode for the SDAr pin and N-ch open-drain output mode for the SCLr pin. Remarks 1. R b [Ω]: Communication line (SDAr, SCLr) pull-up resistance, Cb [F]: Communication line (SDAr, SCLr) load capacitance, Vb [V]: Communication line voltage 2. f MCK: Serial array unit operation clock frequency User's device RL78 microcontroller SDAr SCLr SDA SCL Vb Rb Vb Rb 1/f SCL t LO W t HIGH SCLr SDAr t HD:DAT t SU:DAT

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3.5.2 Serial Interface IICA

(TA = -40 to +105°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions Normal M ode Fast Mode Fast Mode Plus Unit SCLA0 clock frequency f SCL Fast mode plus:

10 MHz ≤ fMCK

Fast mode:

3.5 MHz ≤ fMCK

Normal mode:

1 MHz ≤ fMCK

Setup time of restart condition Note 1 t SU:STA 4.7 0.6 0.26 µs Hold time t HD:STA 4.0 0.6 0.26 µs Hold time when SCLA0 = “L” t LOW 4.7 1.3 0.5 µs Hold time when SCLA0 = “H” t HIGH 4.0 0.6 0.26 µs Data setup time (reception) t SU:DAT 250 100 50 ns Data hold time (transmission) Note 2 t HD:DAT 0 3.45 0 0.9 0 µs Setup time of stop condition t SU:STO 4.0 0.6 0.26 µs Bus-free time t BUF 4.7 1.3 0.5 µs Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected. 2. The maximum value (MAX.) of t HD:DAT is during normal transfer and a wa it state is inserted in the ACK (acknowledge) timing. Remark The maximum value of C b (communication line capacitance) and the value of R b (communication line pull-up resistor) at that time in each mode are as follows. Standard mode: C b = 400 pF, Rb = 2.7 kΩ Fast mode: C b = 320 pF, Rb = 1.1 kΩ Fast mode plus: C b = 120 pF, Rb = 1.1 kΩ IICA serial transfer timing t LO W SCLA0 SDAA0 Stop condition t R t HD:DAT t HD:STA t HIGH t F t SU:DAT t SU:STA t HD:STA t SU:STO Start condition Restart condition Stop condition t BUF <R> <R> <R>

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3.5.3 On-chip Debug (UART)

(TA = -40 to +105°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate – 115.2 k 1 M bps

3.5.4 LIN/UART Module (RLIN3) UART Mode

(TA = -40 to +105°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate – Operation mode, HALT mode LIN communication clock source (fCLK or fMX): 4 to 40 MHz 4000 kbps SNOOZE mode LIN communication clock source (f CLK): 2 to 40 MHz 9.6

3.5.5 CAN-FD Communication Interface (RS-CANFD lite) Timing

(TA = -40 to +105°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate – Classical CAN mode 1 Mbps CAN-FD mode Data bit rate 5 Mbps CAN-FD mode Nominal bit rate 1 Mbps Internal delay time Note t NODE 50 ns Note t NODE = Internal input delay time (tINPUT) + Internal output delay time (tOUTPUT) Image of Internal delay RL78/F24 CAN controller CTXD0 CRXD0 Internal output delay time （t OUTPUT） Internal input delay time （t INPUT）

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3.6 Analog Characteristics

3.6.1 A/D Converter Characteristics

Classification of A/D converter characteristics Reference Input channel Reference voltage (+) = AVREFP Reference voltage (-) = AVREFM Reference voltage (+) = VDD Reference voltage (-) = VSS ANI0 to ANI5,ANI8 to ANI30 3.6.1 (1) 3.6.1 (2) ANI6,ANI7 － 3.6.1 (2) Internal reference voltage (+) 3.6.1 (1) 3.6.1 (2) (1) When Reference voltage (+) = AV REFP, Reference voltage (-) = AVREFM = 0 V, target ANI pin: ANI0 to ANI5, ANI8 to ANI30, Internal reference voltage (+). (TA = -40 to +105 °C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = AV REFP, Reference voltage (-) = AVREFM = 0 V) (1/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 12 bit Overall error Note 1 ABS ANI0 to ANI5, ANI8 to ANI23 Note 2, [4.5 V ≤ AVREFP = VDD ≤ 5.5 V] ±5.0 LSB ANI0 to ANI5, ANI8 to ANI23 Note 2, [2.7 V ≤ AVREFP = VDD < 4.5 V] ±5.0 LSB ANI1, ANI2 Note 3, [4.5 V ≤ AVREFP = VDD ≤ 5.5 V] [0.25 V ≤ VAIN ≤ VDD - 0.25 V] ±6.0 LSB ANI1, ANI2 Note 3, [2.7 V ≤ AVREFP = VDD < 4.5 V] [0.25 V ≤ VAIN ≤ VDD - 0.25 V] ±8.0 LSB ANI24 to ANI30, [4.5 V ≤ AVREFP = VDD ≤ 5.5 V] ±11.0 LSB ANI24 to ANI30, [2.7 V ≤ AVREFP = VDD < 4.5 V] ±13.0 LSB Integral linearity error Note 1 INL ANI0 to ANI5, ANI8 to ANI23, [AV REFP = VDD] ±3.0 LSB ANI24 to ANI30, [AVREFP = VDD] ±7.0 LSB Differential linearity error Note 1 DNL ANI0 to ANI5, ANI8 to ANI23, [AV REFP = VDD] ±1.5 LSB ANI24 to ANI30, [AVREFP = VDD] ±3.5 LSB Zero-scale error Note 1 ZSE ANI0 to ANI5, ANI8 to ANI23 Note 2, [AVREFP = VDD] ±4.5 LSB ANI24 to ANI30, [AVREFP = VDD] ±8.5 LSB Full-scale error Note 1 FSE ANI0 to ANI5, ANI8 to ANI23 Note 2, [AVREFP = VDD] ±4.5 LSB ANI24 to ANI30, [AVREFP = VDD] ±8.5 LSB (Notes are at the end of this table.)

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 85 of 207 Dec 31, 2025 Parameter Symbol Conditions MIN. TYP. MAX. Unit Reference voltage (+) AV REFP 2.7 V DD V Analog input voltage V AIN ANI0 to ANI5, ANI8 to ANI30 0 AV REFP V Analog input slew rate SR 0.4 V/µs Operation clock f AD 2 40 MHz Conversion time Note 4 (per 1 channel) tCONV ADCLK = 40 MHz, input impedance ≤ 0.5 kΩ ANI0 to ANI5, ANI8 to ANI15 Note 2 1.125 µs ANI16 to ANI30 1.8 µs ANI1, ANI2 Note 3 2.1 µs Notes 1. Excludes quantization error (±1/2 LSB). 2. In case that dedicated sample & hold circuit is not used. 3. In case that dedicated sample & hold circuit is used. 4. The A/D conversion processing time (tCONV) consists of sampling time and time for conversion by successive approximation. (2/2)

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 86 of 207 Dec 31, 2025 (2) When Reference voltage (+) = V DD, Reference voltage (-) = VSS, target ANI pin: ANI0 to ANI30, Internal reference voltage (+). (TA = -40 to +105 °C, 2.7 V ≤ EVDD0 = EV DD1 = V DD ≤ 5.5 V, V SS = EV SS0 = EV SS1 = 0 V, Reference voltage (+) = V DD, Reference voltage (-) = VSS) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 12 bit Overall error Note 1 ABS ANI0 to ANI23 Note 2, [4.5 V ≤ VDD ≤ 5.5 V] ±13.0 LSB ANI0 to ANI23 Note 2, [2.7 V ≤ VDD < 4.5 V] ±15.0 LSB ANI1, ANI2 Note 3, [4.5 V ≤ VDD ≤ 5.5 V], [0.25 V ≤ VAIN ≤ VDD - 0.25 V] ±14.0 LSB ANI1, ANI2 Note 3, [2.7 V ≤ VDD < 4.5 V], [0.25 V ≤ VAIN ≤ VDD - 0.25 V] ±16.0 LSB ANI24 to ANI30, [4.5 V ≤ VDD ≤ 5.5 V] ±19.0 LSB ANI24 to ANI30, [2.7 V ≤ VDD < 4.5 V] ±21.0 LSB Integral linearity error Note 1 INL ANI0 to ANI23 ±7.0 LSB ANI24 to ANI30 ±9.0 LSB Differential linearity error Note 1 DNL ANI0 to ANI23 ±3.5 LSB ANI24 to ANI30 ±5.5 LSB Zero-scale error Note 1 ZSE ANI0 to ANI23 Note 2 ±14.5 LSB ANI24 to ANI30 ±18.5 LSB Full-scale error Note 1 FSE ANI0 to ANI23 Note 2 ±14.5 LSB ANI24 to ANI30 ±18.5 LSB Analog input voltage V AIN ANI0 to ANI30 0 V DD V Analog input slew rate SR 0.4 V/µs Operation clock f AD 2 40 MHz Conversion time Note 4 (per 1 channel) tCONV ADCLK = 40 MHz, input impedance ≤ 0.5 kΩ ANI0 to ANI15 Note 2 1.125 µs ANI16 to ANI30 1.8 µs ANI1, ANI2 Note 3 2.1 µs Notes 1. Excludes quantization error (±1/2 LSB). 2. In case that dedicated sample & hold circuit is not used. 3. In case that dedicated sample & hold circuit is used. 4. The A/D conversion processing time (tCONV) consists of sampling time and time for conversion by successive approximation.

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3.6.2 D/A Converter Characteristics

(TA = -40 to +105°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 8 bit Overall error AINL Rload = 4 MΩ 2.7 V ≤ VDD ≤ 5.5 V ±2.5 LSB Rload = 8 MΩ 2.7 V ≤ VDD ≤ 5.5 V ±2.5 LSB Settling time t SET Cload = 20 pF 2.7 V ≤ VDD ≤ 5.5 V 3 µs

3.6.3 Comparator Characteristics

(TA = -40 to +105°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input offset voltage V IOCMP ±5 ±40 mV Input voltage range V ICMP 0 V DD V Response time t CR, tCF Input amplitude ±100 mV 70 200 ns Stabilization wait time during input channel switching Note 1 tWAIT Input amplitude ±100 mV 300 ns Operation stabilization wait time Note 2 t CMP 3.3 V ≤ VDD ≤ 5.5 V 1 µs 2.7 V ≤ VDD < 3.3 V 3 µs Notes 1. Period of time from when the comparator input channel is switched until the comparator is switched to output. 2. Period of time from when the com parator operation is enabled (HCMPON bit in CMPCTL is set to 1) until the comparator satisfies the DC/AC characteristics.

3.6.4 POR Circuit Characteristics

A = -40 to +105°C, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage Note 1 V POR Power supply rise time 1.48 1.56 1.62 V VPDR Power supply fall time 1.47 1.55 1.61 V Minimum pulse width Note 2 T PW 300 µs Detection delay time T PD 350 µs Notes 1. This indicates the POR circuit characteristics, and no rmal operation is not guarante ed under the condition of less than lower limit operation voltage (2.7 V). 2. Minimum time required for a POR reset when V DD exceeds below VPDR. Supply voltage (V DD) TPW V PO R V PDR

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3.6.5 LVD Circuit Characteristics

(1) LVD detection voltage of interrupt mode or reset mode (TA = -40 to +105°C, VPDR ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage Supply voltage level V LVD0 Power supply rise time 4.62 4.74 4.84 V Power supply fall time 4.52 4.64 4.74 V VLVD1 Power supply rise time 4.50 4.62 4.72 V Power supply fall time 4.40 4.52 4.62 V VLVD2 Power supply rise time 4.30 4.42 4.51 V Power supply fall time 4.21 4.32 4.41 V VLVD3 Power supply rise time 3.13 3.22 3.29 V Power supply fall time 3.07 3.15 3.22 V VLVD4 Power supply rise time 2.95 3.02 3.09 V Power supply fall time 2.89 2.96 3.02 V VLVD5 Power supply rise time 2.74 2.81 2.87 V Power supply fall time 2.68 Note 2.75 2.81 V Minimum pulse width t LW 300 µs Detection delay time t LD 300 µs Note The minimum value exceeds below the lower limit operation voltage (2.7 V), however, in reset mode, normal operation (same behavior when VDD = 2.7 V) is possible until a reset is effected at the power supply falling time. (2) LVD detection voltage of interrupt and reset mode (TA = -40 to +105°C, VPDR ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Interrupt and reset mode VLVD5 VPOC2, VPOC1, VPOC0 = 0, 0, 1 Note 1, falling reset voltage: 2.75 V 2.68 Note 2 2.75 2.81 V VLVD2 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 4.30 4.42 4.51 V Falling interrupt voltage 4.21 4.32 4.41 V VLVD5 VPOC2, VPOC1, VPOC0 = 0, 1, 0 Note 1, falling reset voltage: 2.75 V 2.68 Note 2 2.75 2.81 V VLVD1 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 4.50 4.62 4.72 V Falling interrupt voltage 4.40 4.52 4.62 V VLVD5 VPOC2, VPOC1, VPOC0 = 0, 1, 1 Note 1, falling reset voltage: 2.75 V 2.68 Note 2 2.75 2.81 V VLVD3 LVIS1, LVIS0 = 0, 1 Rising release reset voltage 3.13 3.22 3.29 V Falling interrupt voltage 3.07 3.15 3.22 V VLVD0 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 4.62 4.74 4.84 V Falling interrupt voltage 4.52 4.64 4.74 V Notes 1. These values indicate setting values of option bytes. 2. The minimum value exceeds below the lower limit operat ion voltage (2.7 V), however, in reset mode, normal operation (same behavior when VDD = 2.7 V) is possible until a reset is effected at the power supply falling time.

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3.7 Power Supply Voltage Rising Time

(TA = -40 to +105°C, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Maximum power supply voltage rising slope Svrmax 0 V → VDD (VPOC2 = 0 or 1 Note 2) 50 Note 3 V/ms Minimum power supply voltage rising slope Note 1 Svrmin 0 V → 2.7 V 6.5 V/ms Notes 1. The minimum power supply voltage rising slope is applied only under the following condition. When the voltage detection (LVD) circuit is not used (VPO C2 = 1) and an external reset circuit is not used or when a reset is not effected until VDD = 2.7 V. 2. These values indicate setting values of option bytes. 3. If the power supply drops below V PDR and a POR reset is effected, this sp ecification is also applied when the power supply is recovered without dropping to 0 V.

3.8 Regulator Output Voltage Characteristics

A = -40 to +105°C, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit REGC output voltage Note V OREGC C = 0.47 to 1 µF 2.0 2.1 2.2 V Note Other than the following conditions are applicable.  In STOP mode.  When the high-speed system clock (f MX), the high-speed on-chip oscillator clock (fIH), and PLL clock (fPLL) are stopped during CPU operation with the subsystem/low-speed on-chip oscillator clock select clock (fSL).  When the hifh-speed system clock (f MX), the high-speed on-chip oscillator clock (fIH), and PLL clock (fPLL) are stopped during the HALT mode when t he CPU operation with the subsyste m/low-speed on-chip oscillator clock select (fSL) has been set.

3.9 RAM Data Retention Characteristics

A = -40 to +105°C, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention supply voltage V DDDR 1.47 Note 5.5 V Note This depends on the POR detection voltage. For a falling voltage, data in RAM are retained until the voltage reaches the level that triggers a POR reset but not once it reaches the level at which a POR reset is generated. Standby release signal (interrupt request) RAM data retention STOP instruction execution STOP mode Operation mode VDDDR VDD

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3.10 Flash Memory Programming Characteristics

(TA = -40 to +105°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit System clock frequency f CLK 2 40 MHz Number of code flash rewrites Notes 1, 2, 3 C erwr Retained for 20 years TA = +85°C Note 4 1,000 Times Number of data flash rewrites Notes 1, 2, 3 Retained for 20 years TA = +85°C Note 4 10,000 Retained for 5 years TA = +85°C Note 4 100,000 Erase time T erasa Block erase 5 ms Write time T wrwa 1 word write 10 µs Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The starting point of the retaining years are after the erase. 2. When using flash memory programmer and Renesas Electronics self programming code. 3. These are the characteristics of t he flash memory and the results obtained from reliability testing by Renesas Electronics Corporation. 4. The average temperatur e for data retention. (1) Code flash memory processing time (TA = -40 to +105°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Item f CLK = 2 MHz f CLK = 4 MHz f CLK = 8 MHz f CLK = 16 MHz Unit Blank checking time 4 bytes – 29.0 – 22.0 – 19.0 – 17.0 µs 1 KB – 800.0 – 405.0 – 245.0 – 145.0 µs Internal verify time 4 bytes – 350.0 – 175.0 – 90.0 – 45.0 µs 1 KB – 19.0 – 9.5 – 5.0 – 2.5 ms Item f CLK = 20 MHz f CLK = 32 MHz f CLK = 40 MHz Unit Blank checking time 4 bytes – 17.0 – 16.0 – 16.0 µs 1 KB – 145.0 – 135.0 – 135.0 µs Internal verify time 4 bytes – 35.0 – 22.0 – 18.0 µs 1 KB – 2.0 – 1.2 – 1.0 ms Caution The listed values do not include the time until the operations of the flash memory start following execution of an instruction by software.

RL78/F23, F24 3. ELECTRICAL SPECIFICATIONS (GRADE 3) R01DS0446EJ0120 Rev.1.20 Page 91 of 207 Dec 31, 2025 (2) Data flash memory processing time (TA = -40 to +105°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Item f CLK = 2 MHz f CLK = 4 MHz f CLK = 8 MHz f CLK = 16 MHz Unit Blank checking time 1 byte – 29.0 – 22.0 – 19.0 – 17.0 µs 1 KB – 3.1 – 1.6 – 0.95 – 0.55 ms Internal verify time 1 byte – 350.0 – 175.0 – 90.0 – 45.0 µs 1 KB – 76.0 – 38.0 – 19.0 – 9.5 ms Item f CLK = 20 MHz f CLK = 32 MHz f CLK = 40 MHz Unit Blank checking time 1 byte – 17.0 – 16.0 – 16.0 µs 1 KB – 0.55 – 0.5 – 0.5 ms Internal verify time 1 byte – 35.0 – 22.0 – 18.0 µs 1 KB – 7.5 – 4.7 – 3.8 ms Caution The listed values do not include the time until the operations of the flash memory start following execution of an instruction by software.

3.11 Dedicated Flash Memory Programmer Communication (UART)

A = -40 to +105°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate – During serial programming 115.2 k 1 M bps

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3.12 Timing of Entry to Flash Memory Programming Modes

(TA = -40 to +105°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Time to complete the communication for the initial setting after the external reset is released t SUINIT POR and LVD reset must be released before the external reset is released. 100 ms Time to release the external reset after the TOOL0 pin is set to the low level tSU POR and LVD reset must be released before the external reset is released. 10 µs Time to hold the TOOL0 pin at the low level after the external reset is released (excluding the processing time of the firmware to control the flash memory) t HD POR and LVD reset must be released before the external reset is released. 1 ms <1> The low level is input to the TOOL0 pin. <2> The external reset is released (POR and LVD reset must be released before the external reset is released.). <3> The TOOL0 pin is set to the high level. <4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting. Remarks 1. tSUINIT: Communication for the initial setting must be comple ted within 100 ms after the external reset is released during this period. 2. t SU: Time to release the extern al reset after the TOOL0 pin is set to the low level 3. t HD: Time to hold the TOOL0 pin at the low level afte r the external reset is released (excluding the processing time of the firmware to control the flash memory) RESET t SU 1 ms + t HD processing time 00H reception (TOOLRXD, TOOLTXD mode) t SUINIT

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 93 of 207 Dec 31, 2025 4. ELECTRICAL SPECIFICATIONS (GRADE 4) Cautions 1. RL78/F23 and RL78/F24 have an on-chip debug function, which is provided for development and evaluation. Do not use the on-ch ip debug function in products designate d for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. 2. With products not provided with an EV DD0, EVDD1, EVSS0, or EVSS1 pin, replace EVDD0 and EVDD1 with VDD, or replace EVSS0 and EVSS1 with VSS. 3. The pins mounted depending on the product. For details, refer to 1.5 Pin Configurations and 2.1 Pin Function List.

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 94 of 207 Dec 31, 2025

4.1 Absolute Maximum Ratings

(1/3) Parameter Symbol Conditions Ratings Unit Supply voltage V DD -0.5 to +6.5 V EVDD0, EVDD1 EV DD0 = EVDD1 = VDD -0.5 to +6.5 V VSS -0.5 to +0.3 V EVSS0, EVSS1 EV SS0 = EVSS1 -0.5 to +0.3 V REGC pin input voltage V IREGC REGC -0.3 to +2.8 and -0.3 to VDD+0.3 Note 1 V Input voltage V I1 P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P140, P150 to P157 -0.3 to EV DD0 + 0.3 and -0.3 to VDD + 0.3 Note 2 V VI2 P33, P34, P80 to P87, P90 to P97, P100 to P105, P121 to P124, P137, RESET -0.3 to VDD + 0.3 Note 2 V Output voltage V O1 P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P130, P140, P150 to P157 -0.3 to EV DD0 + 0.3 and -0.3 to VDD+ 0.3 Note 2 V VO2 P33, P34, P80 to P87, P90 to P97, P100 to P105 -0.3 to V DD + 0.3 V Analog input voltage V AI1 ANI24 to ANI30 -0.3 to EV DD0 + 0.3 and -0.3 to AVREF(+) + 0.3 Notes 2, 3 V VAI2 ANI0 to ANI23 -0.3 to V DD + 0.3 and -0.3 to AVREF(+) + 0.3 Notes 2, 3 V Notes 1. Connect the REGC pin to VSS via a capacitor (0.47 to 1 µF). This value regulates the absolute maximum rating of the REGC pin. Do not use this pin with voltage applied to it. 2. Must be 6.5 V or lower. 3. For pins to be used in A/D conversion, the voltage should not exceed the value AVREF(+) + 0.3. Caution Product quality may suffer if the absolute m aximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, t he characteristics of alternate-function pins are the same as those of the port pins.

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 95 of 207 Dec 31, 2025 (2/3) Parameter Symbol Conditions Ratings Unit Output current, high I OH1 Per pin P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P130, P140, P150 to P157 -40 mA Total of all pins -170 mA P01, P02, P40 to P47, P120, P125 to P127, P150 to P153 -70 mA P00, P03, P10 to P17, P30 to P32, P50 to P57, P60 to P67, P70 to P77, P106, P107, P130, P140, P154 to P157 -100 mA IOH2 Per pin P33, P34, P80 to P87, P90 to P97, P100 to P105 -0.5 mA Total of all pins -2 mA Output current, low I OL1 Per pin P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P130, P140, P150 to P157 40 mA Total of all pins 170 mA P01, P02, P40 to P47, P120, P125 to P127, P150 to P153 70 mA P00, P03, P10 to P17, P30 to P32, P50 to P57, P60 to P67, P70 to P77, P106, P107, P130, P140, P154 to P157 100 mA IOL2 Per pin P33, P34, P80 to P87, P90 to P97, P100 to P105 1 mA Total of all pins 5 mA Caution Product quality may suffer if the absolute m aximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, t he characteristics of alternate-function pins are the same as those of the port pins.

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 96 of 207 Dec 31, 2025 (3/3) Parameter Symbol Conditions Ratings Unit Positive injected current (VI > VDD) Note IINJP Per pin P00 to P03, P10 to P17, P30 to P32, P41 to P47, P50 to P57, P60 to P67, P75 to P77, P106, P107, P126, P127, P140, P150 to P157 5 mA P70 to P74, P80 to P87, P90 to P97, P100 to P105, P120, P125 2 mA Negative injected current I < VSS) Note IINJN Per pin P00 to P03, P10 to P17, P30 to P32, P41 to P47, P50 to P57, P60 to P67, P75 to P77, P106, P107, P126, P127, P140, P150 to P157 -5 mA P70 to P74, P80 to P87, P90 to P97, P100 to P105, P120, P125 -0.5 mA Sum of all positive injected currents Note ΣIINJP Total of all pins P00 to P03, P10 to P17, P30 to P32, P41 to P47, P50 to P57, P60 to P67, P75 to P77, P106, P107, P126, P127, P140, P150 to P157 40 mA P70 to P74, P80 to P87, P90 to P97, P100 to P105, P120, P125 10 mA Sum of all negative injected currents Note ΣIINJN Total of all pins P00 to P03, P10 to P17, P30 to P32, P41 to P47, P50 to P57, P60 to P67, P75 to P77, P106, P107, P126, P127, P140, P150 to P157 -40 mA P70 to P74, P80 to P87, P90 to P97, P100 to P105, P120, P125 -2 mA Total of all injected currents Note Σ|IINJP| + Σ|IINJN| Total of all pins P00 to P03, P10 to P17, P30 to P32, P41 to P47, P50 to P57, P60 to P67, P75 to P77, P106, P107, P126, P127, P140, P150 to P157 40 mA P70 to P74, P80 to P87, P90 to P97, P100 to P105, P120, P125 10 mA Operating ambient temperature TA In normal operation mode -40 to +125 °C In flash memory programming mode Storage temperature T stg -65 to +150 °C Note Conditions: 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V Caution Product quality may suffer if the absolute m aximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remarks 1 . Unless specified otherwise, the char acteristics of alternate-function pins are the same as those of the port pins. 2. V I :This is the input voltage level to the port pins.

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 97 of 207 Dec 31, 2025

4.2 Oscillator Characteristics

4.2.1 Main System Clock Oscillator Characteristics

(TA = -40 to +125°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit Ceramic resonator/ Crystal resonator X1 clock oscillation frequency (fx) 2.7 V ≤ VDD ≤ 5.5 V 2.0 20.0 MHz Cautions 1. When using the X1 oscilla tor, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance.  Keep the wiring length as short as possible.  Do not cross the wiring with the other signal lines.  Do not route the wiring near a signal line through which a high fluctuating current flows.  Always make the ground point of the oscillator capacitor the same potential as VSS.  Do not ground the capacitor to a ground pattern through which a high current flows.  Do not fetch signals from the oscillator. 2. Customers are requested to consult the resonato r manufacturer to select an appropriate resonator and to determine the proper osc illation constant. Customers are also requested to adequately evaluate the oscillation on their system. Determine the X1 clock oscillation stabilization time using the oscillation stabilization time of the oscillation stabilization time counter status register (OSTC) and the oscillation stabilizati on time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. Rd X2X1VSS C1 C2

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 98 of 207 Dec 31, 2025

4.2.2 On-chip Oscillator Characteristics

(TA = -40 to +125°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Oscillators Symbol Conditions MIN. TYP. MAX. Unit High-speed on-chip oscillator clock frequency Note fIH 2 80 MHz High-speed on-chip oscillator clock frequency accuracy – -2.0 +2.0 % Low-speed on-chip oscillator clock frequency fIL, fWDT 15 kHz Low-speed on-chip oscillator clock frequency accuracy – -15 +15 % Note High-speed on-chip oscillator frequency is selected with bits 0 to 4 of the option byte (000C2H/040C2H) and bits 0 to 2 of the HOCODIV register.

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 99 of 207 Dec 31, 2025

4.2.3 Subsystem Clock Oscillator Characteristics

(TA = -40 to +125°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Resonator Recommended Circuit Item C onditions MIN. TYP. MAX. Unit Crystal resonator Cautions 1. When using the XT1 oscilla tor, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance.  Keep the wiring length as short as possible.  Do not cross the wiring with the other signal lines.  Do not route the wiring near a signal line through which a high fluctuating current flows.  Always make the ground point of the oscillator capacitor the same potential as VSS.  Do not ground the capacitor to a ground pattern through which a high current flows.  Do not fetch signals from the oscillator. 2. The XT1 oscillator is designed as a low-amplitude circuit for reducing power consumption and thus required to be adequately evaluated on the system. Customers are requested to consult the resonator manufacturer to select an appropriate resonator and to determine the proper oscillation constant. Rd XT2XT1VSS C3 C4

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 100 of 207 Dec 31, 2025

4.2.4 PLL Circuit Characteristics

(TA = -40 to +125°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Resonator Symbol Conditions MIN. TYP. MAX. Unit PLL input enable clock frequency Note 1 fPLLI f MAIN: 4.0 MHz FMAINDIV[1:0] = 00B 3.92 4.0 4.08 MHz fMAIN: 8.0 MHz FMAINDIV[1:0] = 00B 7.84 8.0 8.16 MHz fMAIN: 16.0 MHz FMAINDIV[1:0] = 10B 7.84 8.0 8.16 MHz fMAIN: 20.0 MHz FMAINDIV[1:0] = 11B 4.90 5.0 5.10 MHz PLL output frequency (center value) f PLL f MAIN: 20 MHz, PLLMULA=0, PLLMUL=1 PLLDIV0 = 0, FPLLDIV = 0, PLLDIV1 = 0 fPLLI × 16/2 MHz PLLDIV0 = 0, FPLLDIV = 1, PLLDIV1 = 1 fPLLI × 16 MHz fMAIN: 4 MHz, PLLMULA=1, PLLMUL=1 PLLDIV0 = 0, FPLLDIV = 0, PLLDIV1 = 0 fPLLI × 20/2 MHz PLLDIV0 = 0, FPLLDIV = 1, PLLDIV1 = 1 fPLLI × 20 MHz fMAIN: 8 MHz or 16 MHz, PLLMULA = 0, PLLMUL = 0 PLLDIV0 = 1, FPLLDIV = 0, PLLDIV1 = 0 fPLLI × 12/4 MHz PLLDIV0 = 0, FPLLDIV = 0, PLLDIV1 = 1 fPLLI × 12/2 MHz fMAIN: 8 MHz or 16 MHz, PLLMULA = 0, PLLMUL = 1 PLLDIV0 = 1, FPLLDIV = 0, PLLDIV1 = 0 fPLLI × 16/4 MHz PLLDIV0 = 0, FPLLDIV = 0, PLLDIV1 = 1 fPLLI × 16/2 MHz fMAIN: 8 MHz or 16 MHz, PLLMULA = 1, PLLMUL = 0 PLLDIV0 = 0, FPLLDIV = 0, PLLDIV1 = 0 fPLLI × 10/2 MHz PLLDIV0 = 0, FPLLDIV = 1, PLLDIV1 = 1 fPLLI × 10 MHz Long-term jitter Note 2 t LJ term = 1 μs -1 +1 ns term = 10 μs -1 +1 ns term = 20 μs -2 +2 ns Notes 1. If the high-speed on-chip oscillator clock is to be sele cted as the PLL input clock, the minimum and maximum values will reflect the range of accuracy of the oscillation frequency by the high-speed on-chip oscillator clock. 2. Guaranteed by design, but not tested before shipment. Remark f MAIN : Main system clock frequency.

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4.3 DC Characteristics

4.3.1 Pin Characteristics

For the relationship between the port pins shown in the following tables and the products, refer to 2. PIN FUNCTIONS. (TA = -40 to +125°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/6) Items Symbol Conditions MIN. TYP. MAX. Unit Output current, high Note 1 I OH1 Per pin for P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P130, P140, P150 to P157 DD0 ≤ 5.5 V -5.0 mA 2.7 V ≤ EVDD0 < 4.0 V -3.0 mA Per pin for P10, P12, P14, P30, P120, P140 (special slew rate) DD0 ≤ 5.5 V -0.6 mA 2.7 V ≤ EVDD0 < 4.0 V -0.2 mA Total of P01, P02, P40 to P47, P120, P125 to P127, P150 to P153 (for duty factors ≤ 70% Note 2) 4.0 V ≤ EVDD0 ≤ 5.5 V -20.0 mA 2.7 V ≤ EVDD0 < 4.0 V -10.0 mA Total of P00, P03, P10 to P17, P30 to P32, P50 to P57, P60 to P67, P70 to P77, P106, P107, P130, P140, P154 to P157 (for duty factors ≤ 70% Note 2) 4.0 V ≤ EVDD0 ≤ 5.5 V -30.0 mA 2.7 V ≤ EVDD0 < 4.0 V -19.0 mA Total of all pins (for duty factors ≤ 70% Note 2) 4.0 V ≤ EVDD0 ≤ 5.5 V -42.0 mA 2.7 V ≤ EVDD0 < 4.0 V -29.0 mA IOH2 Per pin for P33, P34, P80 to P87, P90 to P97, P100 to P105 DD ≤ 5.5 V -0.1 mA Total of all pins (for duty factors ≤ 70% Note 2) 2.7 V ≤ VDD ≤ 5.5 V -2.0 mA Notes 1. Value of current at which the dev ice operation is guaranteed even if the current flows from pins EV DD0, EVDD1 and VDD to an output pin. 2. These output current values are obtai ned under the condition that the du ty factor is no greater than 70%. The output current values when the duty factor is changed to a value greater than 70% can be calculated from the following expression (when the duty factor is changed to n%).

Total output current of pins (I OH × 0.7) / (n × 0.01) <Example> Where n = 80% and I OH = -10.0 mA Total output current of pins = (-10.0 × 0.7) / (80 × 0.01) ≈ -8.7 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maxi mum rating must not flow into one pin. Caution P10 to P17, P32, P60 to P63, P70 to P72, a nd P120 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, t he characteristics of alternate-function pins are the same as those of the port pins.

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 102 of 207 Dec 31, 2025 (TA = -40 to +125°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/6) Items Symbol Conditions MIN. TYP. MAX. Unit Output current, low Note 1 I OL1 Per pin for P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P130, P140, P150 to P157 DD0 ≤ 5.5 V 8.5 mA 2.7 V ≤ EVDD0 < 4.0 V 4.0 mA Per pin for P10, P12, P14, P30, P120, P140 (special slew rate) DD0 ≤ 5.5 V 0.59 mA 2.7 V ≤ EVDD0 < 4.0 V 0.07 mA Total of P01, P02, P40 to P47, P120, P125 to P127, P150 to P153 (for duty factors ≤ 70% Note 2) 4.0 V ≤ EVDD0 ≤ 5.5 V 20.0 mA 2.7 V ≤ EVDD0 < 4.0 V 15.0 mA Total of P00, P03, P10 to P17, P30 to P32, P50 to P57, P60 to P67, P70 to P77, P106, P107, P130, P140, P154 to P157 (for duty factors ≤ 70% Note 2) 4.0 V ≤ EVDD0 ≤ 5.5 V 45.0 mA 2.7 V ≤ EVDD0 < 4.0 V 35.0 mA Total of all pins (for duty factors ≤ 70% Note 2) 4.0 V ≤ EVDD0 ≤ 5.5 V 65.0 mA 2.7 V ≤ EVDD0 < 4.0 V 50.0 mA IOL2 Per pin for P33, P34, P80 to P87, P90 to P97, P100 to P105 DD ≤ 5.5 V 0.4 mA Total of all pins (for duty factors ≤ 70% Note 2) 2.7 V ≤ VDD ≤ 5.5 V 5.0 mA Notes 1. Value of current at which the device operation is guaranteed even if the current flows to the EVSS0, EVSS1 and VSS pins from an output pin. 2. These output current values are obtai ned under the condition that the du ty factor is no greater than 70%. The output current values when the duty factor is changed to a value greater than 70% can be calculated from the following expression (when the duty factor is changed to n%).

Total output current of pins (I OL × 0.7) / (n × 0.01) <Example> Where n = 80% and I OL = 10.0 mA Total output current of pins = (10.0 × 0.7) / (80 × 0.01) ≈ 8.7 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maxi mum rating must not flow into one pin. Remark Unless specified otherwise, t he characteristics of alternate-function pins are the same as those of the port pins.

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 103 of 207 Dec 31, 2025 (TA = -40 to +125°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (3/6) Items Symbol Conditions MIN. TYP. MAX. Unit Input voltage, high V IH1 P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P140, P150 to P157 (Schmitt 1 mode) DD0 ≤ 5.5 V 0.65 EVDD0 EV DD0 Note V 2.7 V ≤ EVDD0 < 4.0 V 0.7 EVDD0 EV DD0 Note V VIH2 P10, P11, P13, P14, P16, P17, P30, P41, P43, P50, P52 to P54, P60 to P63, P70, P71, P73, P75 to P77, P107, P120, P125, P150, P152, P153 (Schmitt 3 mode) DD0 ≤ 5.5 V 0.8 EVDD0 EV DD0 Note V 2.7 V ≤ EVDD0 < 4.0 V 0.85 EVDD0 EV DD0 Note V VIH3 P10, P11, P13, P14, P16, P17, P30, P54, P62, P63, P70, P71, P73, P125 (TTL mode) DD0 ≤ 5.5 V 2.2 EV DD0 Note V 2.7 V ≤ EVDD0 < 4.0 V 2.0 EV DD0 Note V VIH4 P33, P34, P80 to P87, P90 to P97, P100 to P105, P137 (fixed to Schmitt 3 mode) DD ≤ 5.5 V 0.8 VDD V DD V 2.7 V ≤ VDD < 4.0 V 0.85 VDD V DD V VIH5 RESET (fixed to Schmitt 1 mode) 4.0 V ≤ VDD ≤ 5.5 V 0.65 VDD V DD V 2.7 V ≤ VDD < 4.0 V 0.7 VDD V DD V VIH6 P121 to P124, EXCLK, EXCLKS (fixed to Schmitt 2 mode) DD ≤ 5.5 V 0.8 VDD V DD V 2.7 V ≤ VDD < 4.0 V 0.8 VDD V DD V Note The maximum value of V IH of the pins P10 to P17, P32, P60 to P63, P70 to P72, and P120 is EV DD0, even in N-ch open-drain mode. Remark Unless specified otherwise, t he characteristics of alternate-function pins are the same as those of the port pins.

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 104 of 207 Dec 31, 2025 (TA = -40 to +125°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (4/6) Items Symbol Conditions MIN. TYP. MAX. Unit Input voltage, low V IL1 P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P140, P150 to P157 (Schmitt 1 mode) DD0 ≤ 5.5 V 0 0.35 EV DD0 V 2.7 V ≤ EVDD0 < 4.0 V 0 0.3 EV DD0 V VIL2 P10, P11, P13, P14, P16, P17, P30, P41, P43, P50, P52 to P54, P60 to P63, P70, P71, P73, P75 to P77, P107, P120, P125, P150, P152, P153 (Schmitt 3 mode) DD0 ≤ 5.5 V 0 0.5 EV DD0 V 2.7 V ≤ EVDD0 < 4.0 V 0 0.4 EV DD0 V VIL3 P10, P11, P13, P14, P16, P17, P30, P54, P62, P63, P70, P71, P73, P125 (TTL mode) DD0 ≤ 5.5 V 0 0.8 V 2.7 V ≤ EVDD0 < 4.0 V 0 0.5 V VIL4 P33, P34, P80 to P87, P90 to P97, P100 to P105, P137 (fixed to Schmitt 3 mode) DD ≤ 5.5 V 0 0.5 V DD V 2.7 V ≤ VDD < 4.0 V 0 0.4 V DD V VIL5 RESET (fixed to Schmitt 1 mode) 4.0 V ≤ VDD ≤ 5.5 V 0 0.35 V DD V 2.7 V ≤ VDD < 4.0 V 0 0.3 V DD V VIL6 P121 to P124, EXCLK, EXCLKS (fixed to Schmitt 2 mode) DD ≤ 5.5 V 0 0.2 V DD V 2.7 V ≤ VDD < 4.0 V 0 0.2 V DD V Remark Unless specified otherwise, t he characteristics of alternate-function pins are the same as those of the port pins.

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 105 of 207 Dec 31, 2025 (TA = -40 to +125°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (5/6) Items Symbol Conditions MIN. TYP. MAX. Unit Output voltage, high V OH1 P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P130, P140, P150 to P157 (normal slew rate) DD0 ≤ 5.5 V, IOH1 = -5.0 mA EVDD0 - 0.9 V 2.7 V ≤ EVDD0 ≤ 5.5 V, IOH1 = -3.0 mA EVDD0 - 0.7 V 2.7 V ≤ EVDD0 ≤ 5.5 V, IOH1 = -1.0 mA EVDD0 - 0.5 V VOH2 P33, P34, P80 to P87, P90 to P97, P100 to P105 2.7 V ≤ VDD ≤ 5.5 V IOH2 = -100 µA VDD - 0.5 V VOH3 P10, P12, P14, P30, P120, P140 (special slew rate) DD0 ≤ 5.5 V, IOH3 = -0.6 mA EVDD0 - 0.8 V 2.7 V ≤ EVDD0 ≤ 5.5 V, IOH3 = -0.2 mA EVDD0 - 0.5 V Output voltage, low V OL1 P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P130, P140, P150 to P157 (normal slew rate) DD0 ≤ 5.5 V, IOL1 = 8.5 mA 0.7 V 4.0 V ≤ EVDD0 ≤ 5.5 V, IOL1 = 4.0 mA 0.4 V 2.7 V ≤ EVDD0 ≤ 5.5 V, IOL1 = 4.0 mA 0.7 V 2.7 V ≤ EVDD0 ≤ 5.5 V, IOL1 = 1.5 mA 0.4 V VOL2 P33, P34, P80 to P87, P90 to P97, P100 to P105 2.7 V ≤ VDD ≤ 5.5 V IOL2 = 400 µA 0.4 V VOL3 P10, P12, P14, P30, P120, P140 (special slew rate) DD0 ≤ 5.5 V, IOL3 = 0.6 mA 0.8 V 2.7 V ≤ EVDD0 ≤ 5.5 V, IOL3 = 0.07 mA 0.5 V Caution P10 to P17, P32, P60 to P63, P70 to P72, a nd P120 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, t he characteristics of alternate-function pins are the same as those of the port pins.

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 106 of 207 Dec 31, 2025 (TA = -40 to +125°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (6/6) Items Symbol Conditions MIN. TYP. MAX. Unit Input leakage current, high ILIH1 P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P140, P150 to P157 V I = EVDD0 1 µA ILIH2 P33, P34, P80 to P87, P90 to P97, P100 to P105, P137, RESET VI = VDD 1 µA ILIH3 P121 to P124 (X1, X2, XT1, XT2, EXCLK, EXCLKS) VI = VDD In input port or external clock input 1 µA In resonator connection 10 µA Input leakage current, low ILIL1 P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P140, P150 to P157 V I = EVSS0 -1 µA ILIL2 P33, P34, P80 to P87, P90 to P97, P100 to P105, P137, RESET VI = VSS -1 µA ILIL3 P121 to P124 (X1, X2, XT1, XT2, EXCLK, EXCLKS) VI = VSS In input port or external clock input -1 µA In resonator connection -10 µA Positive injected current Notes 1, 4 IINJPRMS P00 to P03, P10 to P17, P30 to P32, P41 to P47, P50 to P57, P60 to P67, P75 to P77, P106, P107, P126, P127, P140, P150 to P157 Per pin, V I > EVDD0 0.4 mA Total of all pins, VI > EVDD0 4 mA P70 to P74, P80, P83 to P87 Note 2, P90 to P97, P100 to P105, P120, P125 Per pin, V I > VDD 0.15 mA Total of all pins, VI > VDD 1 mA P81 to P84 Note 3 Total of all pins, V I > VDD 0.15 mA On-chip pull-up resistance RU P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P140, P150 to P157 V I = EVSS0, in input port 10 20 100 kΩ Notes 1. These specifications are not te sted on sorting and are specified based on the device characterization. 2. For RL78/F24 product: P80, P86, P87 3. For RL78/F23 product: P81, P82 4. For RL78/F24 product, P85/ANI07/IV REF0 does not guarantee the electric al characteristics when a positive injection current is generated even if it is within the above specifications. Caution P10 to P17, P32, P60 to P63, P70 to P72, a nd P120 do not output high level in N-ch open-drain mode. Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. 2. VI :This is the input voltage level to the port pins.

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 107 of 207 Dec 31, 2025

4.3.2 Supply Current Characteristics

(1) RL78/F24 (TA = -40 to +125°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2) Items Symbol Conditions MIN. TYP. MAX. Unit Supply current Note 1 IDD1 Operating mode Normal operation Note 2 High-speed on- chip oscillator clock operation f IH = 80 MHz f CLK = 40 MHz Notes 3, 4 10.8 20.0 mA fIH = 40 MHz f CLK = fIH Notes 3, 4 10.1 18.3 mA fIH = 2 MHz f CLK = fIH Notes 3, 4 1.7 3.4 mA Resonator operation fMX = 20 MHz f CLK = fMX Notes 3, 5 5.6 10.3 mA fMX = 2 MHz f CLK = fMX Notes 3, 5 1.5 3.1 mA Resonator operation (PLL operation) (PLL input clock = f MX) fPLL = 80 MHz, fMX = 20 MHz fCLK = 40 MHz Notes 3, 6 10.6 20.0 mA fPLL = 40 MHz, fMX = 20 MHz fCLK = 40 MHz Notes 3, 6 10.2 18.3 mA fPLL = 40 MHz, fMX = 4 MHz fCLK = 40 MHz Notes 3, 6 9.9 17.8 mA Subsystem clock operation fSUB = 32.768 kHz fCLK = fSUB Note 7 7.6 500 µA Low-speed on- chip oscillator clock operation f IL = 15 kHz f CLK = fIL Note 8 4.2 500 µA Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0, VSS, or EVSS0. However, not including the current flowing into the I/O buffer and on- chip pull-up/pull-down resistors. 2. Current drawn when all the CP U instructions are executed. 3. The values below the MAX. column include the peripheral operation current (except for background operation (BGO)). However, the LVD circuit, A/D converter, D/A converter, and comparator are stopped. 4. When high-speed system clock, subsyst em clock, PLL clock, and low-speed on-chip oscillator clock are stopped. 5. When subsystem clock, PLL clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped. 6. When subsystem clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped. 7. When high-speed system clock, PLL cl ock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator are stopped, and with setting of ADSLP = 1. 8. When high-speed system clock, subsystem clock, PLL cl ock, and high-speed on-chip oscillator clock are stopped, and with setting of ADSLP = 1. Remarks 1. f MX: High-speed system clock frequency 2. f SUB: Subsystem clock frequency 3. f PLL: PLL clock frequency 4. f IH: High-speed on-chip oscillator clock frequency 5. f IL: Low-speed on-chip oscillator clock frequency 6. f CLK: CPU/peripheral hardware clock frequency

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 108 of 207 Dec 31, 2025 (TA = -40 to +125°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2) Items Symbol Conditions MIN. TYP. MAX. Unit Supply current Notes 1, 3 IDD2 HALT mode Note 2 High-speed on-chip oscillator clock operation f IH = 80 MHz f CLK = 40 MHz Note 5 3.4 12.0 mA fIH = 40 MHz f CLK = fIH Note 5 2.8 10.5 mA fIH = 2 MHz f CLK = fIH Note 5 0.5 2.0 mA Resonator operation f MX = 20 MHz f CLK = fMX Note 6 1.5 6.5 mA fMX = 2 MHz f CLK = fMX Note 6 0.3 2.0 mA Resonator operation (PLL operation) (PLL input clock = f MX) fPLL = 80 MHz, fMX = 20 MHz fCLK = 40 MHz Note 7 3.2 12.0 mA fPLL = 40 MHz, fMX = 20 MHz fCLK = 40 MHz Note 7 2.9 10.5 mA fPLL = 40 MHz, fMX = 4 MHz fCLK = 40 MHz Note 7 2.6 10.0 mA Subsystem clock operation fSUB = 32.768 kHz fCLK = fSUB Note 8 0.8 300 µA Low-speed on-chip oscillator clock operation f IL = 15 kHz f CLK = fIL Note 9 0.8 300 µA IDD3 STOP mode Note 4 TA = +25°C 0.6 µA TA = +50°C 10 TA = +70°C 25 TA = +105°C 115 TA = +125°C 270 ISNOZ SNOOZE mode DTC operation 7.0 mA Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0, VSS, or EVSS0. However, not including the current flowing into the I/O buffer and on- chip pull-up/pull-down resistors. 2. When HALT mode is entered during fetch from the flash memory. 3. The values below the MAX. column include the pe ripheral operation current and STOP leakage current. However, the watchdog timer, LVD circuit, A/D converter, D/A converter, and comparator are stopped. 4. When high-speed system clock, subsystem clock, PLL clock, high-speed on-chip oscillator clock, and low- speed on-chip oscillator clock are stopped. 5. When high-speed system clock, sub system clock, PLL clock, and low-speed on-chip oscillator clock are stopped. 6. When subsystem clock, PLL clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped. 7. When subsystem clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped. 8. When high-speed system clock, PLL cl ock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped, and with setting of ADSLP = 1. 9. When high-speed system clock, subsyst em clock, PLL clock, and high-speed on-chip oscillator clock are stopped, and with setting of ADSLP = 1. Remarks 1. f MX: High-speed system clock frequency 2. fSUB: Subsystem clock frequency 3. fPLL: PLL clock frequency 4. fIH: High-speed on-chip oscillator clock frequency 5. fIL: Low-speed on-chip oscillator clock frequency 6. fCLK: CPU/peripheral hardware clock frequency

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 109 of 207 Dec 31, 2025 (TA = -40 to +125°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Window watchdog timer operating current IWDT Notes 1, 2 f WDT = 15 kHz 0.3 µA A/D converter operating current I ADC Note 3 When conversion at maximum speed AVREFP = VDD = 5.0 V 1.3 1.7 mA When internal reference voltage is selected Note 5 75.0 µA AVREFP current I ADREF Note 7 AV REFP = 5.0 V 65.0 µA Sample-and-hold circuit operating current IADSH Note 8 0.8 1.2 mA LVD operating current I LVD Note 4 0.08 µA D/A converter operating current I DAC 0.8 1.5 mA Comparator operating current I CMP 50.0 µA BGO operating current I BGO Note 6 2.5 12.2 mA Notes 1. When the high-speed on-chip oscillator clock and high-speed system clock are stopped. 2. Current flowing only to the watchdog timer (including the operation current of the 15 kHz on-chip oscillator). The current value is the sum of IDD1, IDD2, or IDD3 and IWDT when the watchdog timer operates in STOP mode. 3. Current flowing only to the A/D converte r. The current value is the sum of I DD1 or IDD2 and IADC when the A/D converter operates in operation mode or HALT mode. 4. Current flowing only to the LVD circuit. The current value is the sum of IDD1, IDD2, or IDD3 and ILVD when the LVD circuit operates in operation mode, HALT mode, or STOP mode. 5. Operating current that increases when the internal reference voltage is selected. This current flows even when conversion is stopped. 6. Current increased by the BGO operation. The current value is the sum of I DD1 or IDD2 and IBGO when the BGO operates in operation mode or HALT mode. 7. Operating current that increases when the AV REFP is selected. This current flows even when conversion is stopped. 8. Operating current that increases when the sample-and-hol d circuit is used. This current flows for each analog input channel.

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 110 of 207 Dec 31, 2025 (2) RL78/F23 (TA = -40 to +125°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2) Items Symbol Conditions MIN. TYP. MAX. Unit Supply current Note 1 IDD1 Operating mode Normal operation Note 2 High-speed on- chip oscillator clock operation f IH = 80 MHz f CLK = 40 MHz Notes 3, 4 9.7 17.0 mA fIH = 40 MHz f CLK = fIH Notes 3, 4 9.0 15.5 mA fIH = 2 MHz f CLK = fIH Notes 3, 4 1.6 3.0 mA Resonator operation fMX = 20 MHz f CLK = fMX Notes 3, 5 5.0 9.0 mA fMX = 2 MHz f CLK = fMX Notes 3, 5 1.4 2.8 mA Resonator operation (PLL operation) (PLL input clock = f MX) fPLL = 80 MHz, fMX = 20 MHz fCLK = 40 MHz Notes 3, 6 9.2 17.0 mA fPLL = 40 MHz, fMX = 20 MHz fCLK = 40 MHz Notes 3, 6 9.0 15.5 mA fPLL = 40 MHz, fMX = 4 MHz fCLK = 40 MHz Notes 3, 6 8.6 15.0 mA Subsystem clock operation fSUB = 32.768 kHz fCLK = fSUB Note 7 6.5 200 µA Low-speed on- chip oscillator clock operation f IL = 15 kHz f CLK = fIL Note 8 3.3 200 µA Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0, VSS, or EVSS0. However, not including the current flowing into the I/O buffer and on- chip pull-up/pull-down resistors. 2. Current drawn when all the CP U instructions are executed. 3. The values below the MAX. column include the peripheral operation current (except for background operation (BGO)). However, the LVD circuit and A/D converter are stopped. 4. When high-speed system clock, subsyst em clock, PLL clock, and low-speed on-chip oscillator clock are stopped. 5. When subsystem clock, PLL clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped. 6. When subsystem clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped. 7. When high-speed system clock, PLL cl ock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator are stopped, and with setting of ADSLP = 1. 8. When high-speed system clock, subsystem clock, PLL cl ock, and high-speed on-chip oscillator clock are stopped, and with setting of ADSLP = 1. Remarks 1. f MX: High-speed system clock frequency 2. f SUB: Subsystem clock frequency 3. f PLL: PLL clock frequency 4. f IH: High-speed on-chip oscillator clock frequency 5. f IL: Low-speed on-chip oscillator clock frequency 6. f CLK: CPU/peripheral hardware clock frequency

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 111 of 207 Dec 31, 2025 (TA = -40 to +125°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2) Items Symbol Conditions MIN. TYP. MAX. Unit Supply current Notes 1, 3 IDD2 HALT mode Note 2 High-speed on-chip oscillator clock operation f IH = 80 MHz f CLK = 40 MHz Note 5 3.4 11.0 mA fIH = 40 MHz f CLK = fIH Note 5 2.8 9.5 mA fIH = 2 MHz f CLK = fIH Note 5 0.5 1.6 mA Resonator operation f MX = 20 MHz f CLK = fMX Note 6 1.5 5.5 mA fMX = 2 MHz f CLK = fMX Note 6 0.3 1.6 mA Resonator operation (PLL operation) (PLL input clock = f MX) fPLL = 80 MHz, fMX = 20 MHz fCLK = 40 MHz Note 7 3.1 11.0 mA fPLL = 40 MHz, fMX = 20 MHz fCLK = 40 MHz Note 7 2.8 9.5 mA fPLL = 40 MHz, fMX = 4 MHz fCLK = 40 MHz Note 7 2.5 9.0 mA Subsystem clock operation fSUB = 32.768 kHz fCLK = fSUB Note 8 0.7 125 µA Low-speed on-chip oscillator clock operation f IL = 15 kHz f CLK = fIL Note 9 0.7 125 µA IDD3 STOP mode Note 4 TA = +25°C 0.5 µA TA = +50°C 4.5 TA = +70°C 9.0 TA = +105°C 51 TA = +125°C 110 ISNOZ SNOOZE mode DTC operation 6.0 mA Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0, VSS, or EVSS0. However, not including the current flowing into the I/O buffer and on- chip pull-up/pull-down resistors. 2. When HALT mode is entered during fetch from the flash memory. 3. The values below the MAX. column include the pe ripheral operation current and STOP leakage current. However, the watchdog timer, LVD circuit, and A/D converter are stopped. 4. When high-speed system clock, subsystem clock, PLL cl ock, high-speed on-chip oscillator clock, and low- speed on-chip oscillator clock are stopped. 5. When high-speed system clock, subsyst em clock, PLL clock, and low-speed on-chip oscillator clock are stopped. 6. When subsystem clock, PLL clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped. 7. When subsystem clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped. 8. When high-speed system clock, PLL cl ock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped, and with setting of ADSLP = 1. 9. When high-speed system clock, subsystem clock, PLL cl ock, and high-speed on-chip oscillator clock are stopped, and with setting of ADSLP = 1. Remarks 1. f MX: High-speed system clock frequency 2. fSUB: Subsystem clock frequency 3. fPLL: PLL clock frequency 4. fIH: High-speed on-chip oscillator clock frequency 5. fIL: Low-speed on-chip oscillator clock frequency 6. fCLK: CPU/peripheral hardware clock frequency

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 112 of 207 Dec 31, 2025 (TA = -40 to +125°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Window watchdog timer operating current IWDT Notes 1, 2 f WDT = 15 kHz 0.3 µA A/D converter operating current IADC Note 3 When conversion at maximum speed AVREFP = VDD = 5.0 V 1.3 1.7 mA When internal reference voltage is selected Note 5 75.0 µA AVREFP current I ADREF Note 7 AV REFP = 5.0 V 65.0 µA Sample-and-hold circuit operating current IADSH Note 8 0.8 1.2 mA LVD operating current I LVD Note 4 0.08 µA BGO operating current I BGO Note 6 2.5 12.2 mA Notes 1. When the high-speed on-chip oscillator clock and high-speed system clock are stopped. 2. Current flowing only to the watchdog timer (including the operation current of the 15 kHz on-chip oscillator). The current value is the sum of IDD1, IDD2, or IDD3 and IWDT when the watchdog timer operates in STOP mode. 3. Current flowing only to the A/D converte r. The current value is the sum of I DD1 or IDD2 and IADC when the A/D converter operates in operation mode or HALT mode. 4. Current flowing only to the LVD circuit. The current value is the sum of IDD1, IDD2, or IDD3 and ILVD when the LVD circuit operates in operation mode, HALT mode, or STOP mode. 5. Operating current that increases when the internal reference voltage is selected. This current flows even when conversion is stopped. 6. Current increased by the BGO operation. The current value is the sum of I DD1 or IDD2 and IBGO when the BGO operates in operation mode or HALT mode. 7. Operating current that increases when the AV REFP is selected. This current flows even when conversion is stopped. 8. Operating current that increases when the sample-and-hol d circuit is used. This current flows for each analog input channel.

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 113 of 207 Dec 31, 2025

4.4 AC Characteristics

4.4.1 Basic Operation

(TA = -40 to +125°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Instruction cycle (minimum instruction execution time) TCY High-speed on-chip oscillator clock operation 0.025 0.5 µs High-speed system clock operation 0.05 0.5 µs PLL clock operation 0.025 0.5 µs Subsystem clock operation 28.5 30.5 34.5 µs Low-speed on-chip oscillator clock operation 66.6 µs In self programming mode 0.025 0.5 µs CPU/peripheral hardware clock frequency fCLK 0.025 66.6 µs External system clock frequency fEX 2.0 20.0 MHz fEXS 29 35 kHz External system clock input high-level width, low-level width t EXH, tEXL 24 ns tEXHS, tEXLS 13.7 µs TI00 to TI07, TI10 to TI17 input high-level width, low- level width t TIH, tTIL 1/f MCK+10 ns TO00 to TO07, TO10 to TO17, TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1, TRJIO0, TRJO0 output frequency f TO Normal slew rate, C = 30 pF 4.0 V ≤ EVDD0 ≤ 5.5 V 16 MHz 2.7 V ≤ EVDD0 < 4.0 V 8 MHz TO01, TO06, TO07, TO11, TO13, TRDIOC0, TRDIOD0, TRDIOD1, TRJO0 only, Special slew rate, C = 30 pF PCLBUZ0 output frequency f PCL Normal slew rate C = 30 pF 4.0 V ≤ EVDD0 ≤ 5.5 V 16 MHz 2.7 V ≤ EVDD0 < 4.0 V 8 MHz Special slew rate C = 30 pF Timer RJ input cycle t C TRJIO0 100 ns Timer RJ input high-level width, low-level width tTJIH, tTJIL TRJIO0 40 ns Timer RDe input high-level, low-level width tTDIH, tTDIL TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1, TRDCLK0, TRD0RES, TRD1RES 3/f TRD ns Timer RDe pulse output forced cutoff signal low-level width t TDSIL P137/INTP0 2MHz < fCLK ≤ 40MHz 1 µs fCLK ≤ 2 MHz 1/fCLK + 1 µs Caution Excluding the error in oscillation frequency accuracy. Remarks 1. f MCK: Timer array unit operation clock frequency 2. f TRD: Timer RDe operation clock frequency

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 114 of 207 Dec 31, 2025 (TA = -40 to +125°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Interrupt input high-level width, low-level width tINTH, tINTL INTP0 to INTP13 Note 1 1 µs KR0 to KR7 key interrupt input low-level width tKR 250 ns RESET low-level width t RSL Note 1 10 µs Port output rise time, port output fall time tRO, tFO P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P130, P140, P150 to P157 (normal slew rate) C = 30 pF DD0 ≤ 5.5 V 25 ns 2.7 V ≤ EVDD0 < 4.0 V 55 ns P10, P12, P14, P30, P120, P140 (special slew rate) C = 30 pF DD0 ≤ 5.5 V 25 Note 2 60 ns 2.7 V ≤ EVDD0 < 4.0 V 100 ns Notes 1. Pins RESET, INTP0 to INTP3, INTP12, and INTP13 have noise filters for transient levels lasting less than 100 ns. 2. T A = +25°C, EVDD0 = 5.0 V AC Timing Test Points Test pointsVIH VIL VIH VIL

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 115 of 207 Dec 31, 2025 External System Clock Timing EXCLK EXCLKS TI/TO Timing TI00 to TI07, TI10 to TI17, TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1, TRDCLK0, TRD0RES, TRD1RES TO00 to TO07, TO10 to TO17, TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1, TRJIO0, TRJO0 TRJIO0 P137/INTP0 1/f EX t EXL t EXH 0.8 VDD (MIN.) 0.2 VDD (MAX.) 1/f EX S t EXLS t EX HS 0.8 VDD (MIN.) 0.2 VDD (MAX.) t TIL, t TDIL t TIH, t TDIH 1/f TO t TJIL t TJIH t TDSIL

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 116 of 207 Dec 31, 2025 Interrupt Request Input Timing INTP0 to INTP13 Key Interrupt Input Timing KR0 to KR7 RESET Input Timing RESET Output Rising and Falling Timing Output pin t INTL t INTH t KR t RSL t RO t FO

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 117 of 207 Dec 31, 2025

4.5 Peripheral Functions Characteristics

4.5.1 Serial Array Unit

(1) During communication at same pot ential (UART mode) (dedicated baud rate generator output) (TA = -40 to +125°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate – f MCK/6 bps fCLK = 40 MHz, fMCK = fCLK Normal slew rate 6.6 Mbps Special slew rate 2 Mbps UART mode connection diagram (during communication at same potential) UART mode bit width (during communication at same potential) (reference) Caution Select the normal input buffer for the RXD0 pi n and RXD1 pin and normal output mode for the TXD0 pin and TXD1 pin. Remark fMCK: Serial array unit operation clock frequency User's deviceRL78 microcontroller TXD0, TXD1 RXD0, RXD1 RX TX Baud rate error tolerance 1/Transfer rate High-/low-bit width TXD0, TXD1 RXD0, RXD1

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 118 of 207 Dec 31, 2025 (2) During communication at same potential (CSI mode) (master mode, SCKp … internal clock output, normal slew rate) (TA = -40 to +125°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKp cycle time t KCY1 150 Note 5 ns SCKp high-level width, low-level width t KH1, tKL1 4.0 V ≤ EVDD0 ≤ 5.5 V tKCY1/2 – 12 ns 2.7 V ≤ EVDD0 < 4.0 V tKCY1/2 – 18 ns SIp setup time (to SCKp↑) Note 1 tSIK1 4.0 V ≤ EVDD0 ≤ 5.5 V 44 ns 2.7 V ≤ EVDD0 < 4.0 V 55 ns SIp hold time (from SCKp↑) Note 2 tKSI1 30 ns Delay time from SCKp↓ to SOp output Note 3 tKSO1 C = 30 pF Note 4 30 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The Slp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0 or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp ↓” when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp ↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SCKp and SOp output lines. 5. t KCY1 ≥ 4/fMCK must also be satisfied. Caution Select the normal input buffer for the SIp pin and normal output mode for the SOp pin and SCKp pin. Remark p: CSIp (p = 00, 01, 10, 11), m: Unit m (m = 0, 1), n: Channel n (n = 0, 1) <R>

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 119 of 207 Dec 31, 2025 (3) During communication at same potential (CSI mode) (master mode, SCKp … internal clock output, special slew rate) (TA = -40 to +125°C, 4.0 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKp cycle time t KCY1 500 Note 5 ns SCKp high-level width, low-level width t KH1, tKL1 t KCY1/2 – 60 ns SIp setup time (to SCKp↑) Note 1 tSIK1 120 ns SIp hold time (from SCKp↑) Note 2 tKSI1 80 ns Delay time from SCKp↓ to SOp output Note 3 tKSO1 C = 30 pF Note 4 90 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The Slp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0 or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp ↓” when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp ↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SCKp and SOp output lines. 5. t KCY1 ≥ 4/fMCK must also be satisfied. Caution Select the normal input buffer for the SIp pin and normal output mode and special slew rate for the SOp pin and SCKp pin. Remark p: CSIp (p = 00, 01, 10, 11), m: Unit m (m = 0, 1), n: Channel n (n = 0, 1) <R>

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 120 of 207 Dec 31, 2025 (4) During communication at same potential (CSI mode) (s lave mode, SCKp … external clock input, normal slew rate) (TA = -40 to +125°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKp cycle time t KCY2 32 MHz < fMCK 10/fMCK ns fMCK ≤ 32 MHz 8/fMCK ns SCKp high-level width, low-level width tKH2, tKL2 t KCY2/2 ns SIp setup time (to SCKp↑) Note 1 tSIK2 1/f MCK + 20 ns SIp hold time (from SCKp↑) Note 2 tKSI2 1/f MCK + 31 ns Delay time from SCKp↓ to SOp output Note 3 tKSO2 C = 30 pF Note 4 4.0 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V 2/f MCK + 44 ns 2.7 V ≤ VDD = EVDD0 = EVDD1 < 4.0 V 2/f MCK + 57 ns SSIp setup time t SSIK DAP = 0 120 ns DAP = 1 1/f MCK + 120 ns SSIp hold time t KSSI DAP = 0 1/f MCK + 120 ns DAP = 1 120 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The Slp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0 or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp ↓” when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp ↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp, S CKp and SSIp pins and normal output mode for the SOp pin. Remarks 1. p: CSIp (p = 00, 01, 10, 11), m: Unit m (m = 0, 1), n: Channel n (n = 0, 1) 2. f MCK: Serial array unit operation clock frequency

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 121 of 207 Dec 31, 2025 (5) During communication at same potential (CSI mode) (sla ve mode, SCKp … external clock input, special slew rate) (TA = -40 to +125°C, 4.0 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKp cycle time t KCY2 20 MHz < fMCK 10/fMCK ns fMCK ≤ 10 MHz 6/fMCK ns SCKp high-level width, low-level width t KH2, tKL2 t KCY2/2 ns SIp setup time (to SCKp↑) Note1 tSIK2 1/f MCK + 50 ns SIp hold time (from SCKp↑) Note 2 tKSI2 1/f MCK + 50 ns Delay time from SCKp↓ to SOp output Note 3 tKSO2 C = 30 pF Note 4 2/f MCK + 80 ns SSIp setup time t SSIK DAP = 0 120 ns DAP = 1 1/f MCK + 120 ns SSIp hold time t KSSI DAP = 0 1/f MCK + 120 ns DAP = 1 120 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The Slp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0 or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp ↓” when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp ↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp, SCKp and SSIp pins and normal output mode and special slew rate for the SOp pin. Remarks 1. p: CSIp (p = 00, 01, 10, 11), m: Unit m (m = 0, 1), n: Channel n (n = 0, 1) 2. f MCK: Serial array unit operation clock frequency

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 122 of 207 Dec 31, 2025 CSI mode connection diagram (during communication at same potential) CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1) Remark p: CSIp (p = 00, 01, 10, 11), m: Unit m (m = 0, 1), n: Channel n (n = 0, 1) RL78 microcontroller SCKp SSIp User's device SCK SOp SIp SO SI <Master> RL78 microcontroller SCKp SSIp User's device SCK SOp SIp SO SI <Slave> SSO t KCY2 t KL2 t KH2 Input data Output data t SI K2 t KSI2 t KSO2 t KSSI t SSIK SCKp SIp SOp SSIp

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 123 of 207 Dec 31, 2025 CSI mode serial transfer timing (during communication at same potential) (When DAPmn= 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0) Remark p: CSIp (p = 00, 01, 10, 11), m: Unit m (m = 0, 1), n: Channel n (n = 0, 1) t KCY1, 2 t KH1, 2 t KL1, 2 Input data Output data t SI K1, 2 t KSI1, 2 t KSO1, 2 t KSSI t SSIK SCKp SIp SOp SSIp

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 124 of 207 Dec 31, 2025 (6) During communication at same potential (simplified I 2C mode) (SDAr: N-ch open-drain output (EVDD tolerance) mode, SCLr: normal output mode) (TA = -40 to +125°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCLr clock frequency f SCL 1000 Note kHz Hold time when SCLr = “L” t LOW 475 ns Hold time when SCLr = “H” t HIGH 475 ns Data setup time (reception) t SU:DAT 1/f MCK + 85 ns Data hold time (transmission) t HD:DAT Cb = 50 pF, Rb = 2.7 kΩ 0 305 ns Note f CLK ≤ fMCK/4 must also be satisfied. Simplified I2C mode connection diagram (during communication at same potential) Simplified I2C mode serial transfer timing (during communication at same potential) Caution Select the normal input buffer and N-ch open-drain output mode for the SDAr pin and normal output mode for the SCLr pin. Remarks 1. R b [ Ω]: Communication line (SDAr) pull-up resistance, C b [F]: Communication line (SCLr, SDAr) load capacitance 3. f MCK: Serial array unit operation clock frequency User's deviceRL78 microcontroller SDAr SCLr SDA SCL VDD Rb 1/f SCL t LO W t HIGH SCLr SDAr t HD:DAT t SU:DAT

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 125 of 207 Dec 31, 2025 (7) During communication at same potential (simplified I 2C mode) (SDAr and SCLr: N-ch open-drain output (EVDD tolerance) mode) (TA = -40 to +125°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. MAX. Unit SCLr clock frequency f SCL 400 Note kHz Hold time when SCLr = “L” t LOW 4.0 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 1.7 kΩ 1300 ns 2.7 V ≤ VDD < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ Hold time when SCLr = “H” t HIGH 4.0 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 1.7 kΩ 600 ns 2.7 V ≤ VDD < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ Data setup time (reception) t SU:DAT 4.0 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 1.7 kΩ 1/fMCK + 120 ns 2.7 V ≤ VDD < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ 1/fMCK + 270 ns Data hold time (transmission) t HD:DAT 4.0 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 1.7 kΩ 0 300 ns 2.7 V ≤ VDD < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ Note f CLK ≤ fMCK/4 must also be satisfied. Simplified I2C mode connection diagram (during communication at same potential) Caution Select the normal input buffer and N-ch open-drain output mode for the SDAr pin and SCLr pin. Remarks 1. R b [Ω]: Communication line (SDAr, SCLr) pull-up resistance, Cb [F]: Communication line (SDAr, SCLr) load capacitance, Vb[V]: Communication line voltage 3. f MCK: Serial array unit operation clock frequency User's deviceRL78 microcontroller SDAr SCLr SDA SCL Vb Rb Vb Rb

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 126 of 207 Dec 31, 2025 Simplified I2C mode serial transfer timing (during communication at same potential) Remark r: IICr (r = 00, 01, 10, 11) 1/f SCL t LO W t HIGH SCLr SDAr t HD:DAT t SU:DAT

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 127 of 207 Dec 31, 2025 (8) Communication at different potential (UART mode) (T XD output buffer: N-ch open-drain, RXD input buffer: TTL) (TA = -40 to +125°C, 4.0 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate – Reception 2.7 V ≤ Vb ≤ EVDD0, VIH = 2.2 V, VIL = 0.8 V f MCK/6 bps Theoretical value of the maximum transfer rate Note (Cb = 30 pF)

4.0 Mbps

Transmission 2.7 V ≤ Vb ≤ EVDD0, VOH = 2.2 V, VOL = 0.8 V Smaller number of the values given by fMCK/6 and expression 1 is applicable. bps Theoretical value of the maximum transfer rate Note (Cb = 30 pF) Normal slew rate Note Expression 1: Maximum transfer rate = 1 / [ {-Cb × Rb × ln (1 - 2.2/Vb)} × 3 ] UART mode connection diagram (during communication at different potential) User's deviceRL78 microcontroller TXD0, TXD1 RXD0, RXD1 RX TX Vb Rb

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 128 of 207 Dec 31, 2025 UART mode bit width (during communication at different potential) (reference) Caution Select the TTL input buffer for the RXD0 pin and RXD1 pin and N-ch open-drain output mode for the TXD0 pin and TXD1 pin. Remarks 1. R b [Ω]: Communication line (TXD) pull-up resistance, Cb [F]: Communication line (TXD) load capacitance, Vb [V]: Communication line voltage 2. f MCK: Serial array unit operation clock frequency TXD0, TXD1 RXD0, RXD1 Baud rate error tolerance 1/Transfer rate High-/low-bit width Baud rate error tolerance 1/Transfer rate High-bit width Low-bit width

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 129 of 207 Dec 31, 2025 (9) During communication at different potential (3-V supply system) (CSI mode) (master mode, SCKp … internal clock output, normal slew rate) (TA = -40 to +125°C, 4.0 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKp cycle time t KCY1 2.7 V ≤ Vb ≤ EVDD0, Cb = 30 pF, Rb = 1.4 kΩ

400 Note 3 ns

SCKp high-level width t KH1 2.7 V ≤ Vb ≤ EVDD0, Cb = 30 pF, Rb = 1.4 kΩ tKCY1/2 – 75 ns SCKp low-level width t KL1 2.7 V ≤ Vb ≤ EVDD0, Cb = 30 pF, Rb = 1.4 kΩ tKCY1/2 – 20 ns SIp setup time (to SCKp↑) Note 1 tSIK1 2.7 V ≤ Vb ≤ EVDD0, Cb = 30 pF, Rb = 1.4 kΩ 150 ns SIp setup time (to SCKp↓) Note 2 tSIK1 2.7 V ≤ Vb ≤ EVDD0, Cb = 30 pF, Rb = 1.4 kΩ 70 ns SIp hold time (from SCKp↑) Note 1 tKSI1 2.7 V ≤ Vb ≤ EVDD0, Cb = 30 pF, Rb = 1.4 kΩ 30 ns SIp hold time (from SCKp↓) Note 2 tKSI1 2.7 V ≤ Vb ≤ EVDD0, Cb = 30 pF, Rb = 1.4 kΩ 30 ns Delay time from SCKp↓ to SOp output Note 1 tKSO1 2.7 V ≤ Vb ≤ EVDD0, Cb = 30 pF, Rb = 1.4 kΩ 120 ns Delay time from SCKp↑ to SOp output Note 2 tKSO1 2.7 V ≤ Vb ≤ EVDD0, Cb = 30 pF, Rb = 1.4 kΩ 40 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. 2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. tKCY1 ≥ 4/fMCK must also be satisfied. CSI mode connection diagram (during communication at different potential) Caution Select the TTL input buffer for the SIp pin and N-ch open-drain output mode for the SOp pin and SCKp pin. Remarks 1. Rb [Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb [F]: Communication line (SOp, SCKp) load capacitance, Vb [V]: Communication line voltage 2. p: CSIp (p = 00, 01, 10, 11), m: Unit m (m = 0, 1), n: Channel n (n = 0, 1) 3. AC characteristics of the serial array unit during communication at different potential in CSI mode are measured with the VIH and VIL below: User's deviceRL78 microcontroller SCKp SSIp SCK SI Vb Rb Vb Rb SOp SIp SO <Master> <R>

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 130 of 207 Dec 31, 2025 CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1) CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn= 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0) Remark p: CSIp (p = 00, 01, 10, 11), m: Unit m (m = 0, 1), n: Channel n (n = 0, 1) t KCY1 t KL1 t KH1 Input data Output data t SI K1 t KSI1 t KSO1 SCKp SIp SOp t KCY1 t KH1 t KL1 Input data Output data t SI K1 t KSI1 t KSO1 SCKp SIp SOp

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 131 of 207 Dec 31, 2025 (10) During communication at different potential (3-V supply system) (CSI mode) (slave mode, SCKp … external clock input, normal slew rate) (TA = -40 to +125°C, 4.0 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKp cycle time t KCY2 2.7 V ≤ Vb ≤ VDD 32 MHz < fMCK 20/f MCK ns

24 MHz < fMCK ≤ 32 MHz 16/fMCK ns

fMCK ≤ 4 MHz 6/fMCK ns SCKp high-level width, low-level width tKH2, tKL2 2.7 V ≤ Vb ≤ VDD tKCY2/2 – 20 ns SIp setup time (to SCKp↑) Note 1 tSIK2 90 ns SIp hold time (from SCKp↑) Note 2 tKSI2 1/f MCK + 50 ns Delay time from SCKp↓ to SOp output Note 3 tKSO2 2.7 V ≤ Vb ≤ VDD, Cb = 30 pF, Rb = 1.4 kΩ 2/f MCK + 120 ns SSIp setup time t SSIK DAP = 0 120 ns DAP = 1 1/f MCK + 120 ns SSIp hold time t KSSI DAP = 0 1/f MCK + 120 ns DAP = 1 120 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The Slp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0 or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp ↓” when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp ↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 132 of 207 Dec 31, 2025 CSI mode connection diagram (during communication at different potential) Caution Select the TTL input buffer for the SIp, SCKp and SSIp pins and N-ch open-drain output mode for the SOp pin. Remarks 1. R b [Ω]: Communication line (SOp) pull-up resistance, Cb [F]: Communication line (SOp) load capacitance, Vb [V]: Communication line voltage 2. p: CSIp (p = 00, 01, 10, 11), m: Unit m (m = 0, 1), n: Channel n (n = 0, 1) 3. AC characteristics of the serial array unit during communication at different potential in CSI mode are measured with the VIH and VIL below: User's device RL78 microcontroller SCKp SSIp SCK SI Vb Rb SOp SIp SO ＜Slave＞ SSO

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 133 of 207 Dec 31, 2025 CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1) CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn= 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0) Remark p: CSIp (p = 00, 01, 10, 11), m: Unit m (m = 0, 1), n: Channel n (n = 0, 1) t KCY2 t KL2 t KH2 Input data Output data t SI K2 t KSI2 t KSO2 t KSSI t SSIK SCKp SIp SOp SSIp t KCY2 t KH2 t KL2 Input data t SI K2 t KSI2 t KS SI t SSIK SCKp SIp SSIp Output data t KSO2 SOp

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 134 of 207 Dec 31, 2025 (11) During communication at different pot ential (3-V supply system) (simplified I2C mode) (SDAr: TTL input buffer mode or N-ch open-drain output (EVDD tolerance) mode, SCLr: N-ch open-drain output (EVDD tolerance) mode) (TA = -40 to +125°C, 4.0 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. MAX. Unit SCLr clock frequency f SCL 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 1.4 kΩ Hold time when SCLr = “L” t LOW 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 1.4 kΩ 1200 ns Hold time when SCLr = “H” t HIGH 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 1.4 kΩ 600 ns Data setup time (reception) t SU:DAT 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 1.4 kΩ 135 + 1/fMCK ns Data hold time (transmission) t HD:DAT 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 1.4 kΩ 0 140 ns Note fSCL ≤ fMCK/4 must also be satisfied. Simplified I2C mode connection diagram (during communication at different potential) Simplified I2C mode serial transfer timing (during communication at different potential) Caution Select the TTL input buffer and the N-ch open-drain output mode for the SDAr pin and N-ch open-drain output mode for the SCLr pin. Remarks 1. R b [Ω]: Communication line (SDAr, SCLr) pull-up resistance, Cb [F]: Communication line (SDAr, SCLr) load capacitance, Vb [V]: Communication line voltage 2. f MCK: Serial array unit operation clock frequency User's device RL78 microcontroller SDAr SCLr SDA SCL Vb Rb Vb Rb 1/f SCL t LO W t HIGH SCLr SDAr t HD:DAT t SU:DAT

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4.5.2 Serial Interface IICA

(TA = -40 to +125°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions Normal Mode Fast Mode Fast M ode Plus Unit SCLA0 clock frequency f SCL Fast mode plus: Fast mode: Normal mode: Setup time of restart condition Note 1 t SU:STA 4.7 0.6 0.26 µs Hold time t HD:STA 4.0 0.6 0.26 µs Hold time when SCLA0 = “L” t LOW 4.7 1.3 0.5 µs Hold time when SCLA0 = “H” t HIGH 4.0 0.6 0.26 µs Data setup time (reception) t SU:DAT 250 100 50 ns Data hold time (transmission) Note 2 t HD:DAT 0 3.45 0 0.9 0 µs Setup time of stop condition t SU:STO 4.0 0.6 0.26 µs Bus-free time t BUF 4.7 1.3 0.5 µs Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected. 2. The maximum value (MAX.) of t HD:DAT is during normal transfer and a wa it state is inserted in the ACK (acknowledge) timing. Remark The maximum value of C b (communication line capacitance) and the value of R b (communication line pull-up resistor) at that time in each mode are as follows. Standard mode: C b = 400 pF, Rb = 2.7 kΩ Fast mode: C b = 320 pF, Rb = 1.1 kΩ Fast mode plus: C b = 120 pF, Rb = 1.1 kΩ IICA serial transfer timing t LO W SCLA0 SDAA0 Stop condition t R t HD:DAT t HD:STA t HIGH t F t SU:DAT t SU:STA t HD:STA t SU:STO Start condition Restart condition Stop condition t BUF <R> <R> <R>

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4.5.3 On-chip Debug (UART)

(TA = -40 to +125°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate – 115.2 k 1 M bps

4.5.4 LIN/UART Module (RLIN3) UART Mode

(TA = -40 to +125°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate – Operation mode, HALT mode LIN communication clock source (fCLK or fMX): 4 to 40 MHz 4000 kbps SNOOZE mode LIN communication clock source (f CLK): 2 to 40 MHz 9.6

4.5.5 CAN-FD Communication Interface (RS-CANFD lite) Timing

A = -40 to +125°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate – Classical CAN mode 1 Mbps CAN-FD mode Data bit rate 5 Mbps CAN-FD mode Nominal bit rate 1 Mbps Internal delay time Note t NODE 50 ns Note t NODE = Internal input delay time (tINPUT) + Internal output delay time (tOUTPUT) Image of Internal delay RL78/F24 CAN controller CTXD0 CRXD0 Internal output delay time （t OUTPUT） Internal input delay time （t INPUT）

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4.6 Analog Characteristics

4.6.1 A/D Converter Characteristics

Classification of A/D converter characteristics Reference Input channel Reference voltage (+) = AVREFP Reference voltage (-) = AVREFM Reference voltage (+) = VDD Reference voltage (-) = VSS ANI0 to ANI5, ANI8 to ANI30 4.6.1 (1) 4.6.1 (2) ANI6,ANI7 － 4.6.1 (2) Internal reference voltage (+) 4.6.1 (1) 4.6.1 (2) (1) When Reference voltage (+) = AV REFP, Reference voltage (-) = AVREFM = 0 V, target ANI pin: ANI0 to ANI5, ANI8 to ANI30, Internal reference voltage (+). (TA = -40 to +125 °C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = AV REFP, Reference voltage (-) = AVREFM = 0 V) (1/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 12 bit Overall error Note 1 ABS ANI0 to ANI5, ANI8 to ANI23 Note 2, [4.5 V ≤ AVREFP = VDD ≤ 5.5 V] ±5.0 LSB ANI0 to ANI5, ANI8 to ANI23 Note 2, [2.7 V ≤ AVREFP = VDD < 4.5 V] ±5.0 LSB ANI1, ANI2 Note 3, [4.5 V ≤ AVREFP = VDD ≤ 5.5 V], [0.25 V ≤ VAIN ≤ VDD - 0.25 V] ±6.0 LSB ANI1, ANI2 Note 3, [2.7 V ≤ AVREFP = VDD < 4.5 V], [0.25 V ≤ VAIN ≤ VDD - 0.25 V] ±8.0 LSB ANI24 to ANI30, [4.5 V ≤ AVREFP = VDD ≤ 5.5 V] ±11 LSB ANI24 to ANI30, [2.7 V ≤ AVREFP = VDD < 4.5 V] ±13 LSB Integral linearity error Note 1 INL ANI0 to ANI5, ANI8 to ANI23, [AV REFP = VDD] ±3.0 LSB ANI24 to ANI30, [AVREFP = VDD] ±7.0 LSB Differential linearity error Note 1 DNL ANI0 to ANI5, ANI8 to ANI23, [AV REFP = VDD] ±1.5 LSB ANI24 to ANI30, [AVREFP = VDD] ±3.5 LSB Zero-scale error Note 1 ZSE ANI0 to ANI5, ANI8 to ANI23 Note 2, [AVREFP = VDD] ±4.5 LSB ANI24 to ANI30, [AVREFP = VDD] ±8.5 LSB Full-scale error Note 1 FSE ANI0 to ANI5, ANI8 to ANI23 Note 2, [AVREFP = VDD] ±4.5 LSB ANI24 to ANI30, [AVREFP = VDD] ±8.5 LSB (Notes are at the end of this table.)

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 138 of 207 Dec 31, 2025 Parameter Symbol Conditions MIN. TYP. MAX. Unit Reference voltage (+) AV REFP 2.7 V DD V Analog input voltage V AIN ANI0 to ANI5, ANI8 to ANI30 0 AV REFP V Analog input slew rate SR 0.4 V/µs Operation clock f AD 2 40 MHz Conversion time Note 4 (per 1 channel) tCONV ADCLK = 40 MHz, input impedance ≤ 0.5 kΩ ANI0 to ANI5, ANI8 to ANI15 Note 2 1.125 µs ANI16 to ANI30 1.8 µs ANI1, ANI2 Note 3 2.1 µs Notes 1. Excludes quantization error (±1/2 LSB). 2. In case that dedicated sample & hold circuit is not used. 3. In case that dedicated sample & hold circuit is used. 4. The A/D conversion processing time (tCONV) consists of sampling time and time for conversion by successive approximation. (2/2)

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 139 of 207 Dec 31, 2025 (2) When Reference voltage (+) = V DD, Reference voltage (-) = VSS, target ANI pin: ANI0 to ANI30, Internal reference voltage (+). (TA = -40 to +125 °C, 2.7 V ≤ EVDD0 = EV DD1 = V DD ≤ 5.5 V, V SS = EV SS0 = EV SS1 = 0 V, Reference voltage (+) = V DD, Reference voltage (-) = VSS) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 12 bit Overall error Note 1 ABS ANI0 to ANI23 Note 2, [4.5 V ≤ VDD ≤ 5.5 V] ±13.0 LSB ANI0 to ANI23 Note 2, [2.7 V ≤ VDD < 4.5 V] ±15.0 LSB ANI1, ANI2 Note 3, [4.5 V ≤ VDD ≤ 5.5 V], [0.25 V ≤ VAIN ≤ VDD - 0.25 V] ±14.0 LSB ANI1, ANI2 Note 3, [2.7 V ≤ VDD < 4.5 V], [0.25 V ≤ VAIN ≤ VDD - 0.25 V] ±16.0 LSB ANI24 to ANI30, [4.5 V ≤ VDD ≤ 5.5 V] ±19.0 LSB ANI24 to ANI30, [2.7 V ≤ VDD < 4.5 V] ±21.0 LSB Integral linearity error Note 1 INL ANI0 to ANI23 ±7.0 LSB ANI24 to ANI30 ±9.0 LSB Differential linearity error Note 1 DNL ANI0 to ANI23 ±3.5 LSB ANI24 to ANI30 ±5.5 LSB Zero-scale error Note 1 ZSE ANI0 to ANI23 Note 2 ±14.5 LSB ANI24 to ANI30 ±18.5 LSB Full-scale error Note 1 FSE ANI0 to ANI23 Note 2 ±14.5 LSB ANI24 to ANI30 ±18.5 LSB Analog input voltage V AIN ANI0 to ANI30 0 V DD V Analog input slew rate SR 0.4 V/µs Operation clock f AD 2 40 MHz Conversion time Note 4 (per 1 channel) tCONV ADCLK = 40 MHz, input impedance ≤ 0.5 kΩ ANI0 to ANI15 Note 2 1.125 µs ANI16 to ANI30 1.8 µs ANI1, ANI2 Note 3 2.1 µs Notes 1. Excludes quantization error (±1/2 LSB). 2. In case that dedicated sample & hold circuit is not used. 3. In case that dedicated sample & hold circuit is used. 4. The A/D conversion processing time (tCONV) consists of sampling time and time for conversion by successive approximation.

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4.6.2 D/A Converter Characteristics

(TA = -40 to +125°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 8 bit Overall error AINL Rload = 4 M Ω 2.7 V ≤ VDD ≤ 5.5 V ±2.5 LSB Rload = 8 MΩ 2.7 V ≤ VDD ≤ 5.5 V ±2.5 LSB Settling time t SET Cload = 20 pF 2.7 V ≤ VDD ≤ 5.5 V 3 µs

4.6.3 Comparator Characteristics

(TA = -40 to +125°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input offset voltage V IOCMP ±5 ±40 mV Input voltage range V ICMP 0 V DD V Response time t CR, tCF Input amplitude ±100 mV 70 200 ns Stabilization wait time during input channel switching Note 1 tWAIT Input amplitude ±100 mV 300 ns Operation stabilization wait time Note 2 t CMP 3.3 V ≤ VDD ≤ 5.5 V 1 µs 2.7 V ≤ VDD < 3.3 V 3 µs Notes 1. Period of time from when the comparator input channel is switched until the comparator is switched to output. 2. Period of time from when the com parator operation is enabled (HCMPON bit in CMPCTL is set to 1) until the comparator satisfies the DC/AC characteristics.

4.6.4 POR Circuit Characteristics

(TA = -40 to +125°C, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage Note 1 V POR Power supply rise time 1.48 1.56 1.67 V VPDR Power supply fall time 1.47 1.55 1.66 V Minimum pulse width Note 2 T PW 300 µs Detection delay time T PD 350 µs Notes 1. This indicates the POR circuit characteristics, and no rmal operation is not guarante ed under the condition of less than lower limit operation voltage (2.7 V). 2. Minimum time required for a POR reset when V DD exceeds below VPDR. Supply voltage (V DD) TPW V POR V PDR

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4.6.5 LVD Circuit Characteristics

(1) LVD detection voltage of interrupt mode or reset mode (TA = -40 to +125°C, VPDR ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage Supply voltage level V LVD0 Power supply rise time 4.62 4.74 4.94 V Power supply fall time 4.52 4.64 4.84 V VLVD1 Power supply rise time 4.50 4.62 4.82 V Power supply fall time 4.40 4.52 4.71 V VLVD2 Power supply rise time 4.30 4.42 4.61 V Power supply fall time 4.21 4.32 4.51 V VLVD3 Power supply rise time 3.13 3.22 3.39 V Power supply fall time 3.07 3.15 3.31 V VLVD4 Power supply rise time 2.95 3.02 3.17 V Power supply fall time 2.89 2.96 3.09 V VLVD5 Power supply rise time 2.74 2.81 2.95 V Power supply fall time 2.68 Note 2.75 2.88 V Minimum pulse width t LW 300 µs Detection delay time t LD 300 µs Note The minimum value exceeds below the lower limit operation voltage (2.7 V), however, in reset mode, normal operation (same behavior when VDD = 2.7 V) is possible until a reset is effected at the power supply falling time. (2) LVD detection voltage of interrupt and reset mode (TA = -40 to +125°C, VPDR ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Interrupt and reset mode VLVD5 VPOC2, VPOC1, VPOC0 = 0, 0, 1 Note 1, falling reset voltage: 2.75 V 2.68 Note 2 2.75 2.88 V VLVD2 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 4.30 4.42 4.61 V Falling interrupt voltage 4.21 4.32 4.51 V VLVD5 VPOC2, VPOC1, VPOC0 = 0, 1, 0 Note 1, falling reset voltage: 2.75 V 2.68 Note 2 2.75 2.88 V VLVD1 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 4.50 4.62 4.82 V Falling interrupt voltage 4.40 4.52 4.71 V VLVD5 VPOC2, VPOC1, VPOC0 = 0, 1, 1 Note 1, falling reset voltage: 2.75 V 2.68 Note 2 2.75 2.88 V VLVD3 LVIS1, LVIS0 = 0, 1 Rising release reset voltage 3.13 3.22 3.39 V Falling interrupt voltage 3.07 3.15 3.31 V VLVD0 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 4.62 4.74 4.94 V Falling interrupt voltage 4.52 4.64 4.84 V Notes 1. These values indicate setting values of option bytes. 2. The minimum value exceeds below the lower limit operat ion voltage (2.7 V), however, in reset mode, normal operation (same behavior when VDD = 2.7 V) is possible until a reset is effected at the power supply falling time.

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4.7 Power Supply Voltage Rising Time

(TA = -40 to +125°C, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Maximum power supply voltage rising slope Svrmax 0 V → VDD (VPOC2 = 0 or 1 Note 2) 50 Note 3 V/ms Minimum power supply voltage rising slope Note 1 Svrmin 0 V → 2.7 V 6.5 V/ms Notes 1. The minimum power supply voltage rising slope is applied only under the following condition. When the voltage detection (LVD) circuit is not used ( VPOC2 = 1) and an external reset circuit is not used or when a reset is not effected until VDD = 2.7 V. 2. These values indicate setting values of option bytes. 3. If the power supply drops below V PDR and a POR reset is effected, this sp ecification is also applied when the power supply is recovered without dropping to 0 V.

4.8 Regulator Output Voltage Characteristics

A = -40 to +125°C, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit REGC output voltage Note V OREGC C = 0.47 to 1 µF 2.0 2.1 2.2 V Note Other than the following conditions are applicable.  In STOP mode.  When the high-speed system clock (f MX), the high-speed on-chip oscillator clock (fIH), and PLL clock (fPLL) are stopped during CPU operation with the subsystem/low-speed on-chip oscillator clock select clock (fSL).  When the hifh-speed system clock (f MX), the high-speed on-chip oscillator clock (fIH), and PLL clock (fPLL) are stopped during the HALT mode when t he CPU operation with the subsyste m/low-speed on-chip oscillator clock select (fSL) has been set.

4.9 RAM Data Retention Characteristics

A = -40 to +125°C, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention supply voltage V DDDR 1.47 Note 5.5 V Note This depends on the POR detection voltage. For a falling voltage, data in RAM are retained until the voltage reaches the level that triggers a POR reset but not once it reaches the level at which a POR reset is generated. Standby release signal (interrupt request) RAM data retention STOP instruction execution STOP mode Operation mode VDDDR VDD

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4.10 Flash Memory Programming Characteristics

(TA = -40 to +125°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit System clock frequency f CLK 2 40 MHz Number of code flash rewrites Notes 1, 2, 3 C erwr Retained for 20 years TA = +85°C Note 4 1,000 Times Number of data flash rewrites Notes 1, 2, 3 Retained for 20 years TA = +85°C Note 4 10,000 Retained for 5 years TA = +85°C Note 4 100,000 Erase time T erasa Block erase 5 ms Write time T wrwa 1 word write 10 µs Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The starting point of the retaining years are after the erase. 2. When using flash memory programmer and Renesas Electronics self programming code. 3. These are the characteristics of t he flash memory and the results obtained from reliability testing by Renesas Electronics Corporation. 4. The average temperatur e for data retention. (1) Code flash memory processing time (TA = -40 to +125°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Item f CLK = 2 MHz f CLK = 4 MHz f CLK = 8 MHz f CLK = 16 MHz Unit Blank checking time 4 bytes – 29.0 – 22.0 – 19.0 – 17.0 µs 1 KB – 800.0 – 405.0 – 245.0 – 145.0 µs Internal verify time 4 bytes – 350.0 – 175.0 – 90.0 – 45.0 µs 1 KB – 19.0 – 9.5 – 5.0 – 2.5 ms Item f CLK = 20 MHz f CLK = 32 MHz f CLK = 40 MHz Unit Blank checking time 4 bytes – 17.0 – 16.0 – 16.0 µs 1 KB – 145.0 – 135.0 – 135.0 µs Internal verify time 4 bytes – 35.0 – 22.0 – 18.0 µs 1 KB – 2.0 – 1.2 – 1.0 ms Caution The listed values do not include the time until the operations of the flash memory start following execution of an instruction by software.

RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 144 of 207 Dec 31, 2025 (2) Data flash memory processing time (TA = -40 to +125°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Item f CLK = 2 MHz f CLK = 4 MHz f CLK = 8 MHz f CLK = 16 MHz Unit Blank checking time 1 byte – 29.0 – 22.0 – 19.0 – 17.0 µs 1 KB – 3.1 – 1.6 – 0.95 – 0.55 ms Internal verify time 1 byte – 350.0 – 175.0 – 90.0 – 45.0 µs 1 KB – 76.0 – 38.0 – 19.0 – 9.5 ms Item f CLK = 20 MHz f CLK = 32 MHz f CLK = 40 MHz Unit Blank checking time 1 byte – 17.0 – 16.0 – 16.0 µs 1 KB – 0.55 – 0.5 – 0.5 ms Internal verify time 1 byte – 35.0 – 22.0 – 18.0 µs 1 KB – 7.5 – 4.7 – 3.8 ms Caution The listed values do not include the time until the operations of the flash memory start following execution of an instruction by software.

4.11 Dedicated Flash Memory Programmer Communication (UART)

A = -40 to +125°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate – During serial programming 115.2 k 1M bps

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4.12 Timing of Entry to Flash Memory Programming Modes

(TA = -40 to +125°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Time to complete the communication for the initial setting after the external reset is released t SUINIT POR and LVD reset must be released before the external reset is released. 100 ms Time to release the external reset after the TOOL0 pin is set to the low level tSU POR and LVD reset must be released before the external reset is released. 10 µs Time to hold the TOOL0 pin at the low level after the external reset is released (excluding the processing time of the firmware to control the flash memory) tHD POR and LVD reset must be released before the external reset is released. 1 ms <1> The low level is input to the TOOL0 pin. <2> The external reset is released (POR and LVD reset must be released before the external reset is released.). <3> The TOOL0 pin is set to the high level. <4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting. Remarks 1. tSUINIT: Communication for the initial setti ng must be completed within 100 ms after the external reset is released during this period. 2. t SU: Time to release the external reset after the TOOL0 pin is set to the low level 3. t HD: Time to hold the TOOL0 pin at the low level afte r the external reset is released (excluding the processing time of the firmware to control the flash memory) RESET t SU 1 ms + t HD processing time 00H reception (TOOLRXD, TOOLTXD mode) t SUINIT

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 146 of 207 Dec 31, 2025 5. ELECTRICAL SPECIFICATIONS (GRADE 5) Cautions 1. RL78/F23 and RL78/F24 have an on-chip debug function, which is provided for development and evaluation. Do not use the on-ch ip debug function in products designate d for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. 2. With products not provided with an EV DD0, EVDD1, EVSS0, or EVSS1 pin, replace EVDD0 and EVDD1 with VDD, or replace EVSS0 and EVSS1 with VSS. 3. The pins mounted depending on the product. For details, refer to 1.5 Pin Configurations and 2.1 Pin Function List.

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 147 of 207 Dec 31, 2025

5.1 Absolute Maximum Ratings

(1/3) Parameter Symbol Conditions Ratings Unit Supply voltage V DD -0.5 to +6.5 V EVDD0, EVDD1 EV DD0 = EVDD1 = VDD -0.5 to +6.5 V VSS -0.5 to +0.3 V EVSS0, EVSS1 EV SS0 = EVSS1 -0.5 to +0.3 V REGC pin input voltage V IREGC REGC -0.3 to +2.8 and -0.3 to VDD + 0.3 Note 1 V Input voltage V I1 P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P140, P150 to P157 -0.3 to EV DD0 + 0.3 and -0.3 to VDD + 0.3 Note 2 V VI2 P33, P34, P80 to P87, P90 to P97, P100 to P105, P121 to P124, P137, RESET -0.3 to VDD + 0.3 Note 2 V Output voltage V O1 P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P130, P140, P150 to P157 -0.3 to EV DD0 + 0.3 and -0.3 to VDD + 0.3 Note 2 V VO2 P33, P34, P80 to P87, P90 to P97, P100 to P105 -0.3 to V DD + 0.3 V Analog input voltage V AI1 ANI24 to ANI30 -0.3 to EV DD0 + 0.3 and -0.3 to AVREF(+) + 0.3 Notes 2, 3 V VAI2 ANI0 to ANI23 -0.3 to V DD+ 0.3 and -0.3 to AVREF(+) + 0.3 Notes 2, 3 V Notes 1. Connect the REGC pin to VSS via a capacitor (0.47 to 1 µF). This value regulates the absolute maximum rating of the REGC pin. Do not use this pin with voltage applied to it. 2. Must be 6.5 V or lower. 3. For pins to be used in A/D conversion, the voltage should not exceed the value AVREF(+) + 0.3. Caution Product quality may suffer if the absolute m aximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, t he characteristics of alternate-function pins are the same as those of the port pins.

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 148 of 207 Dec 31, 2025 (2/3) Parameter Symbol Conditions Ratings Unit Output current, high I OH1 Per pin P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P130, P140, P150 to P157 -40 mA Total of all pins -170 mA P01, P02, P40 to P47, P120, P125 to P127, P150 to P153 -70 mA P00, P03, P10 to P17, P30 to P32, P50 to P57, P60 to P67, P70 to P77, P106, P107, P130, P140, P154 to P157 -100 mA IOH2 Per pin P33, P34, P80 to P87, P90 to P97, P100 to P105 -0.5 mA Total of all pins -2 mA Output current, low I OL1 Per pin P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P130, P140, P150 to P157 40 mA Total of all pins 170 mA P01, P02, P40 to P47, P120, P125 to P127, P150 to P153 70 mA P00, P03, P10 to P17, P30 to P32, P50 to P57, P60 to P67, P70 to P77, P106, P107, P130, P140, P154 to P157 100 mA IOL2 Per pin P33, P34, P80 to P87, P90 to P97, P100 to P105 1 mA Total of all pins 5 mA Caution Product quality may suffer if the absolute m aximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, t he characteristics of alternate-function pins are the same as those of the port pins.

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 149 of 207 Dec 31, 2025 (3/3) Parameter Symbol Conditions Ratings Unit Positive injected current I > VDD) Note IINJP Per pin P00 to P03, P10 to P17, P30 to P32, P41 to P47, P50 to P57, P60 to P67, P75 to P77, P106, P107, P126, P127, P140, P150 to P157 5 mA P70 to P74, P80 to P87, P90 to P97, P100 to P105, P120, P125 2 mA Negative injected current I < VSS) Note IINJN Per pin P00 to P03, P10 to P17, P30 to P32, P41 to P47, P50 to P57, P60 to P67, P75 to P77, P106, P107, P126, P127, P140, P150 to P157 -5 mA P70 to P74, P80 to P87, P90 to P97, P100 to P105, P120, P125 -0.5 mA Sum of all positive injected currents Note ΣIINJP Total of all pins P00 to P03, P10 to P17, P30 to P32, P41 to P47, P50 to P57, P60 to P67, P75 to P77, P106, P107, P126, P127, P140, P150 to P157 40 mA P70 to P74, P80 to P87, P90 to P97, P100 to P105, P120, P125 10 mA Sum of all negative injected currents Note ΣIINJN Total of all pins P00 to P03, P10 to P17, P30 to P32, P41 to P47, P50 to P57, P60 to P67, P75 to P77, P106, P107, P126, P127, P140, P150 to P157 -40 mA P70 to P74, P80 to P87, P90 to P97, P100 to P105, P120, P125 -2 mA Total of all injected currents Note Σ|IINJP| + Σ|IINJN| Total of all pins P00 to P03, P10 to P17, P30 to P32, P41 to P47, P50 to P57, P60 to P67, P75 to P77, P106, P107, P126, P127, P140, P150 to P157 40 mA P70 to P74, P80 to P87, P90 to P97, P100 to P105, P120, P125 10 mA Operating ambient temperature TA In normal operation mode -40 to +150 °C In flash memory programming mode Storage temperature T stg -65 to +150 °C Note Conditions: 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V Caution Product quality may suffer if the absolute m aximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. 2. VI: This is the input voltage level to the port pins.

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 150 of 207 Dec 31, 2025

5.2 Oscillator Characteristics

5.2.1 Main System Clock Oscillator Characteristics

(TA = -40 to +150°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit Ceramic resonator/ Crystal resonator X1 clock oscillation frequency (fX) 2.7 V ≤ VDD ≤ 5.5 V 2.0 20.0 MHz Cautions 1. When using the X1 oscilla tor, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance.

Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as VSS.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator. 2. Customers are requested to consult the resonato r manufacturer to select an appropriate resonator and to determine the proper osc illation constant. Customers are also requested to adequately evaluate the oscillation on their system. Determine the X1 clock oscillation stabilization time using the oscillation stabilization time of the oscillation stabilization time counter status register (OSTC) and the oscillation stabilizati on time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. Rd X2X1VSS C1 C2

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 151 of 207 Dec 31, 2025

5.2.2 On-chip Oscillator Characteristics

(TA = -40 to +150°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Oscillators Symbol Conditions MIN. TYP. MAX. Unit High-speed on-chip oscillator clock frequency Note fIH 2 80 MHz High-speed on-chip oscillator clock frequency accuracy – -2.2 +2.2 % Low-speed on-chip oscillator clock frequency fIL, fWDT 15 kHz Low-speed on-chip oscillator clock frequency accuracy – -15 +15 % Note High-speed on-chip oscillator frequency is selected with bits 0 to 4 of the option byte (000C2H/040C2H) and bits 0 to 2 of the HOCODIV register.

5.2.3 Subsystem Clock Oscillator Characteristics

Do not use the XT1 oscillator.

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 152 of 207 Dec 31, 2025

5.2.4 PLL Circuit Characteristics

(TA = -40 to +150°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Resonator Symbol Conditions MIN. TYP. MAX. Unit PLL input enable clock frequency Note 1 fPLLI f MAIN: 4.0 MHz FMAINDIV[1:0] = 00B 3.92 4.0 4.08 MHz fMAIN: 8.0 MHz FMAINDIV[1:0] = 00B 7.84 8.0 8.16 MHz fMAIN: 16.0 MHz FMAINDIV[1:0] = 10B 7.84 8.0 8.16 MHz fMAIN: 20.0 MHz FMAINDIV[1:0] = 11B 4.90 5.0 5.10 MHz PLL output frequency (center value) fPLL f MAIN: 20MHz, PLLMULA = 0, PLLMUL = 1 PLLDIV0 = 0, FPLLDIV = 0, PLLDIV1 = 0 fPLLI × 16/2 MHz PLLDIV0 = 0, FPLLDIV = 1, PLLDIV1 = 1 fPLLI × 16 MHz fMAIN: 4 MHz, PLLMULA = 1, PLLMUL = 1 PLLDIV0 = 0, FPLLDIV = 0, PLLDIV1 = 0 fPLLI × 20/2 MHz PLLDIV0 = 0, FPLLDIV = 1, PLLDIV1 = 1 fPLLI × 20 MHz fMAIN: 8 MHz or 16 MHz, PLLMULA = 0, PLLMUL = 0 PLLDIV0 = 1, FPLLDIV = 0, PLLDIV1 = 0 fPLLI × 12/4 MHz PLLDIV0 = 0, FPLLDIV = 0, PLLDIV1 = 1 fPLLI × 12/2 MHz fMAIN: 8 MHz or 16 MHz, PLLMULA = 0, PLLMUL = 1 PLLDIV0 = 1, FPLLDIV = 0, PLLDIV1 = 0 fPLLI × 16/4 MHz PLLDIV0 = 0, FPLLDIV = 0, PLLDIV1 = 1 fPLLI × 16/2 MHz fMAIN: 8 MHz or 16 MHz, PLLMULA = 1, PLLMUL = 0 PLLDIV0 = 0, FPLLDIV = 0, PLLDIV1 = 0 fPLLI × 10/2 MHz PLLDIV0 = 0, FPLLDIV = 1, PLLDIV1 = 1 fPLLI × 10 MHz Long-term jitter Note 2 t LJ term = 1 μs -1 +1 ns term = 10 μs -1 +1 ns term = 20 μs -2 +2 ns Notes 1. If the high-speed on-chip oscillator clock is to be sele cted as the PLL input clock, the minimum and maximum values will reflect the range of accuracy of the oscillation frequency by the high-speed on-chip oscillator clock. 2. Guaranteed by design, but not tested before shipment. Remark f MAIN : Main system clock frequency.

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 153 of 207 Dec 31, 2025

5.3 DC Characteristics

5.3.1 Pin Characteristics

For the relationship between the port pins shown in the following tables and the products, refer to 2. PIN FUNCTIONS. (TA = -40 to +150°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/6) Items Symbol Conditions MIN. TYP. MAX. Unit Output current, high Note 1 I OH1 Per pin for P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P130, P140, P150 to P157 DD0 ≤ 5.5 V -5.0 mA 2.7 V ≤ EVDD0 < 4.0 V -3.0 mA Per pin for P10, P12, P14, P30, P120, P140 (special slew rate) DD0 ≤ 5.5 V -0.6 mA 2.7 V ≤ EVDD0 < 4.0 V -0.2 mA Total of P01, P02, P40 to P47, P120, P125 to P127, P150 to P153 (for duty factors ≤ 70% Note 2) 4.0 V ≤ EVDD0 ≤ 5.5 V -20.0 mA 2.7 V ≤ EVDD0 < 4.0 V -10.0 mA Total of P00, P03, P10 to P17, P30 to P32, P50 to P57, P60 to P67, P70 to P77, P106, P107, P130, P140, P154 to P157 (for duty factors ≤ 70% Note 2) 4.0 V ≤ EVDD0 ≤ 5.5 V -30.0 mA 2.7 V ≤ EVDD0 < 4.0 V -19.0 mA Total of all pins (for duty factors ≤ 70% Note 2) 4.0 V ≤ EVDD0 ≤ 5.5 V -32.0 mA 2.7 V ≤ EVDD0 < 4.0 V -29.0 mA IOH2 Per pin for P33, P34, P80 to P87, P90 to P97, P100 to P105 DD ≤ 5.5 V -0.1 mA Total of all pins (for duty factors ≤ 70% Note 2) 2.7 V ≤ VDD ≤ 5.5 V -2.0 mA Notes 1. Value of current at which the device operation is guaranteed even if the current flows from pins EV DD0, EVDD1 and VDD to an output pin. 2. These output current values are obtai ned under the condition that the du ty factor is no greater than 70%. The output current values when the duty factor is changed to a value greater than 70% can be calculated from the following expression (when the duty factor is changed to n%).

Total output current of pins (I OH × 0.7) / (n × 0.01) <Example> Where n = 80% and I OH = -10.0 mA Total output current of pins = (-10.0 × 0.7) / (80 × 0.01) ≈ -8.7 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maxi mum rating must not flow into one pin. Caution P10 to P17, P32, P60 to P63, P70 to P72, a nd P120 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, t he characteristics of alternate-function pins are the same as those of the port pins.

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 154 of 207 Dec 31, 2025 (TA = -40 to +150°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/6) Items Symbol Conditions MIN. TYP. MAX. Unit Output current, low Note 1 I OL1 Per pin for P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P130, P140, P150 to P157 DD0 ≤ 5.5 V 8.5 mA 2.7 V ≤ EVDD0 < 4.0 V 4.0 mA Per pin for P10, P12, P14, P30, P120, P140 (special slew rate) DD0 ≤ 5.5 V 0.59 mA 2.7 V ≤ EVDD0 < 4.0 V 0.07 mA Total of P01, P02, P40 to P47, P120, P125 to P127, P150 to P153 (for duty factors ≤ 70% Note 2) 4.0 V ≤ EVDD0 ≤ 5.5 V 20.0 mA 2.7 V ≤ EVDD0 < 4.0 V 15.0 mA Total of P00, P03, P10 to P17, P30 to P32, P50 to P57, P60 to P67, P70 to P77, P106, P107, P130, P140, P154 to P157 (for duty factors ≤ 70% Note 2) 4.0 V ≤ EVDD0 ≤ 5.5 V 35.0 mA 2.7 V ≤ EVDD0 < 4.0 V 30.0 mA Total of all pins (for duty factors ≤ 70% Note 2) 4.0 V ≤ EVDD0 ≤ 5.5 V 55.0 mA 2.7 V ≤ EVDD0 < 4.0 V 45.0 mA IOL2 Per pin for P33, P34, P80 to P87, P90 to P97, P100 to P105 DD ≤ 5.5 V 0.4 mA Total of all pins (for duty factors ≤ 70% Note 2) 2.7 V ≤ VDD ≤ 5.5 V 5.0 mA Notes 1. Value of current at which the device operation is guaranteed even if the current flows to the EVSS0, EVSS1 and VSS pins from an output pin. 2. These output current values are obtai ned under the condition that the du ty factor is no greater than 70%. The output current values when the duty factor is changed to a value greater than 70% can be calculated from the following expression (when the duty factor is changed to n%).

Total output current of pins (I OL × 0.7) / (n × 0.01) <Example> Where n = 80% and I OL = 10.0 mA Total output current of pins = (10.0 × 0.7) / (80 × 0.01) ≈ 8.7 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maxi mum rating must not flow into one pin. Remark Unless specified otherwise, t he characteristics of alternate-function pins are the same as those of the port pins.

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 155 of 207 Dec 31, 2025 (TA = -40 to +150°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (3/6) Items Symbol Conditions MIN. TYP. MAX. Unit Input voltage, high V IH1 P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P140, P150 to P157 (Schmitt 1 mode) DD0 ≤ 5.5 V 0.65 EVDD0 EV DD0 Note V 2.7 V ≤ EVDD0 < 4.0 V 0.7 EVDD0 EV DD0 Note V VIH2 P10, P11, P13, P14, P16, P17, P30, P41, P43, P50, P52 to P54, P60 to P63, P70, P71, P73, P75 to P77, P107, P120, P125, P150, P152, P153 (Schmitt 3 mode) DD0 ≤ 5.5 V 0.8 EVDD0 EV DD0 Note V 2.7 V ≤ EVDD0 < 4.0 V 0.85 EVDD0 EV DD0 Note V VIH3 P10, P11, P13, P14, P16, P17, P30, P54, P62, P63, P70, P71, P73, P125 (TTL mode) DD0 ≤ 5.5 V 2.2 EV DD0 Note V 2.7 V ≤ EVDD0 < 4.0 V 2.0 EV DD0 Note V VIH4 P33, P34, P80 to P87, P90 to P97, P100 to P105, P137 (fixed to Schmitt 3 mode) DD ≤ 5.5 V 0.8 VDD V DD V 2.7 V ≤ VDD < 4.0 V 0.85 VDD V DD V VIH5 RESET (fixed to Schmitt 1 mode) 4.0 V ≤ VDD ≤ 5.5 V 0.65 VDD V DD V 2.7 V ≤ VDD < 4.0 V 0.7 VDD V DD V VIH6 P121 to P124, EXCLK, EXCLKS (fixed to Schmitt 2 mode) DD ≤ 5.5 V 0.8 VDD V DD V 2.7 V ≤ VDD < 4.0 V 0.8 VDD V DD V Note The maximum value of V IH of the pins P10 to P17, P32, P60 to P63, P70 to P72, and P120 is EV DD0, even in N-ch open-drain mode. Remark Unless specified otherwise, t he characteristics of alternate-function pins are the same as those of the port pins.

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 156 of 207 Dec 31, 2025 (TA = -40 to +150°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (4/6) Items Symbol Conditions MIN. TYP. MAX. Unit Input voltage, low V IL1 P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P140, P150 to P157 (Schmitt 1 mode) DD0 ≤ 5.5 V 0 0.35 EV DD0 V 2.7 V ≤ EVDD0 < 4.0 V 0 0.3 EV DD0 V VIL2 P10, P11, P13, P14, P16, P17, P30, P41, P43, P50, P52 to P54, P60 to P63, P70, P71, P73, P75 to P77, P107, P120, P125, P150, P152, P153 (Schmitt 3 mode) DD0 ≤ 5.5 V 0 0.5 EV DD0 V 2.7 V ≤ EVDD0 < 4.0 V 0 0.4 EV DD0 V VIL3 P10, P11, P13, P14, P16, P17, P30, P54, P62, P63, P70, P71, P73, P125 (TTL mode) DD0 ≤ 5.5 V 0 0.8 V 2.7 V ≤ EVDD0 < 4.0 V 0 0.5 V VIL4 P33, P34, P80 to P87, P90 to P97, P100 to P105, P137 (fixed to Schmitt 3 mode) DD ≤ 5.5 V 0 0.5 V DD V 2.7 V ≤ VDD < 4.0 V 0 0.4 V DD V VIL5 RESET (fixed to Schmitt 1 mode) 4.0 V ≤ VDD ≤ 5.5 V 0 0.35 V DD V 2.7 V ≤ VDD < 4.0 V 0 0.3 V DD V VIL6 P121 to P124, EXCLK, EXCLKS (fixed to Schmitt 2 mode) DD ≤ 5.5 V 0 0.2 V DD V 2.7 V ≤ VDD < 4.0 V 0 0.2 V DD V Remark Unless specified otherwise, t he characteristics of alternate-function pins are the same as those of the port pins.

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 157 of 207 Dec 31, 2025 (TA = -40 to +150°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (5/6) Items Symbol Conditions MIN. TYP. MAX. Unit Output voltage, high V OH1 P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P130, P140, P150 to P157 (normal slew rate) DD0 ≤ 5.5 V, IOH1 = -5.0 mA EVDD0 - 0.9 V 2.7 V ≤ EVDD0 ≤ 5.5 V, IOH1 = -3.0 mA EVDD0 - 0.7 V 2.7 V ≤ EVDD0 ≤ 5.5 V, IOH1 = -1.0 mA EVDD0 - 0.5 V VOH2 P33, P34, P80 to P87, P90 to P97, P100 to P105 2.7 V ≤ VDD ≤ 5.5 V IOH2 = -100 µA VDD - 0.5 V VOH3 P10, P12, P14, P30, P120, P140 (special slew rate) DD0 ≤ 5.5 V, IOH3 = -0.6 mA EVDD0 - 0.8 V 2.7 V ≤ EVDD0 ≤ 5.5 V, IOH3 = -0.2 mA EVDD0 - 0.5 V Output voltage, low V OL1 P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P130, P140, P150 to P157 (normal slew rate) DD0 ≤ 5.5 V, IOL1 = 8.5 mA 0.7 V 4.0 V ≤ EVDD0 ≤ 5.5 V, IOL1 = 4.0 mA 0.4 V 2.7 V ≤ EVDD0 ≤ 5.5 V, IOL1 = 4.0 mA 0.7 V 2.7 V ≤ EVDD0 ≤ 5.5 V, IOL1 = 1.5 mA 0.4 V VOL2 P33, P34, P80 to P87, P90 to P97, P100 to P105 2.7 V ≤ VDD ≤ 5.5 V IOL2 = 400 µA 0.4 V VOL3 P10, P12, P14, P30, P120, P140 (special slew rate) DD0 ≤ 5.5 V, IOL3 = 0.6 mA 0.8 V 2.7 V ≤ EVDD0 ≤ 5.5 V, IOL3 = 0.07 mA 0.5 V Caution P10 to P17, P32, P60 to P63, P70 to P72, a nd P120 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, t he characteristics of alternate-function pins are the same as those of the port pins.

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 158 of 207 Dec 31, 2025 (TA = -40 to +150°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (6/6) Items Symbol Conditions MIN. TYP. MAX. Unit Input leakage current, high ILIH1 P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P140, P150 to P157 V I = EVDD0 1 µA ILIH2 P33, P34, P80 to P87, P90 to P97, P100 to P105, P137, RESET VI = VDD 1 µA ILIH3 P121 to P124 (X1, X2, EXCLK, EXCLKS) VI = VDD In input port or external clock input 1 µA In resonator connection 10 µA Input leakage current, low ILIL1 P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P140, P150 to P157 V I = EVSS0 -1 µA ILIL2 P33, P34, P80 to P87, P90 to P97, P100 to P105, P137, RESET VI = VSS -1 µA ILIL3 P121 to P124 (X1, X2, EXCLK, EXCLKS) VI = VSS In input port or external clock input -1 µA In resonator connection -10 µA Positive injected current Notes 1, 4 IINJPRMS P00 to P03, P10 to P17, P30 to P32, P41 to P47, P50 to P57, P60 to P67, P75 to P77, P106, P107, P126, P127, P140, P150 to P157 Per pin, V I > EVDD0 0.4 mA Total of all pins, VI > EVDD0 4 mA P70 to P74, P80, P83 to P87 Note 2, P90 to P97, P100 to P105, P120, P125 Per pin, V I > VDD 0.15 mA Total of all pins, VI > VDD 1 mA P81 to P84 Note 3 Total of all pins, V I > VDD 0.15 mA On-chip pull-up resistance RU P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P140, P150 to P157 V I = EVSS0, in input port 10 20 100 kΩ Notes 1. These specifications are not te sted on sorting and are specified based on the device characterization. 2. For RL78/F24 product: P80, P86, P87 3. For RL78/F23 product: P81, P82 4. For RL78/F24 product, P85/ANI07/IV REF0 does not guarantee the electric al characteristics when a positive injection current is generated even if it is within the above specifications. Caution P10 to P17, P32, P60 to P63, P70 to P72, a nd P120 do not output high level in N-ch open-drain mode. Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. 2. VI :This is the input voltage level to the port pins.

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 159 of 207 Dec 31, 2025

5.3.2 Supply Current Characteristics

(1) RL78/F24 (TA = -40 to +150°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2) Items Symbol Conditions MIN. TYP. MAX. Unit Supply current Note 1 IDD1 Operating mode Normal operation Note 2 High-speed on- chip oscillator clock operation f IH = 80 MHz f CLK = 40 MHz Notes 3, 4 10.8 21.0 mA fIH = 40 MHz f CLK = fIH Notes 3, 4 10.1 19.3 mA fIH = 2 MHz f CLK = fIH Notes 3, 4 1.7 4.2 mA Resonator operation fMX = 20 MHz f CLK = fMX Notes 3, 5 5.6 11.3 mA fMX = 2 MHz f CLK = fMX Notes 3, 5 1.5 3.9 mA Resonator operation (PLL operation) (PLL input clock = f MX) fPLL = 80 MHz, fMX = 20 MHz fCLK = 40 MHz Notes 3, 6 10.6 21.0 mA fPLL = 40 MHz, fMX = 20 MHz fCLK = 40 MHz Notes 3, 6 10.2 19.3 mA fPLL = 40 MHz, fMX = 4 MHz fCLK = 40 MHz Notes 3, 6 9.9 18.8 mA Subsystem clock operation SUB = fEXS) fSUB = 32.768 kHz fCLK = fSUB Note 7 7.6 1200 µA Low-speed on- chip oscillator clock operation f IL = 15 kHz f CLK = fIL Note 8 4.2 1200 µA Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0, VSS, or EVSS0. However, not including the current flowing into the I/O buffer and on- chip pull-up/pull-down resistors. 2. Current drawn when all the CP U instructions are executed. 3. The values below the MAX. column include the peripheral operation current (except for background operation (BGO)). However, the LVD circuit, A/D converter, D/A converter, and comparator are stopped. 4. When high-speed system clock, subsyst em clock, PLL clock, and low-speed on-chip oscillator clock are stopped. 5. When subsystem clock, PLL clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped. 6. When subsystem clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped. 7. When high-speed system clock, PLL cl ock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator are stopped, and with setting of ADSLP = 1. 8. When high-speed system clock, subsystem clock, PLL cl ock, and high-speed on-chip oscillator clock are stopped, and with setting of ADSLP = 1. Remarks 1. f MX: High-speed system clock frequency 2. f SUB: Subsystem clock frequency 3. f EXS: External subsystem clock frequency 4. f PLL: PLL clock frequency 5. f IH: High-speed on-chip oscillator clock frequency 6. f IL: Low-speed on-chip oscillator clock frequency 7. fCLK: CPU/peripheral hardware clock frequency

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 160 of 207 Dec 31, 2025 (TA = -40 to +150°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2) Items Symbol Conditions MIN. TYP. MAX. Unit Supply current Notes 1, 3 IDD2 HALT mode Note 2 High-speed on-chip oscillator clock operation fIH = 80 MHz f CLK = 40 MHz Note 5 3.4 13.0 mA fIH = 40 MHz f CLK = fIH Note 5 2.8 11.5 mA fIH = 2 MHz f CLK = fIH Note 5 0.5 2.5 mA Resonator operation f MX = 20 MHz f CLK = fMX Note 6 1.5 7.0 mA fMX = 2 MHz f CLK = fMX Note 6 0.3 2.5 mA Resonator operation (PLL operation) (PLL input clock = f MX) fPLL = 80 MHz, fMX = 20 MHz fCLK = 40 MHz Note 7 3.2 13.0 mA fPLL = 40 MHz, fMX = 20 MHz fCLK = 40 MHz Note 7 2.9 11.5 mA fPLL = 40 MHz, fMX = 4 MHz fCLK = 40 MHz Note 7 2.6 11.0 mA Subsystem clock operation (fSUB = fEXS) fSUB = 32.768 kHz fCLK = fSUB Note 8 0.8 730 µA Low-speed on-chip oscillator clock operation f IL = 15 kHz f CLK = fIL Note 9 0.8 730 µA IDD3 STOP mode Note 4 TA = +25°C 0.6 µA TA = +50°C 10 TA = +70°C 25 TA = +105°C 115 TA = +125°C 270 TA = +150°C 700 ISNOZ SNOOZE mode DTC operation 7.0 mA Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0, VSS, or EVSS0. However, not including the current flowing into the I/O buffer and on- chip pull-up/pull-down resistors. 2. When HALT mode is entered during fetch from the flash memory. 3. The values below the MAX. column include the pe ripheral operation current and STOP leakage current. However, the watchdog timer, LVD circuit, A/D converter, D/A converter, and comparator are stopped. 4. When high-speed system clock, subsystem clock, PLL cl ock, high-speed on-chip oscillator clock, and low- speed on-chip oscillator clock are stopped. 5. When high-speed system clock, subsyst em clock, PLL clock, and low-speed on-chip oscillator clock are stopped. 6. When subsystem clock, PLL clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped. 7. When subsystem clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped. 8. When high-speed system clock, PLL cl ock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped, and with setting of ADSLP = 1. 9. When high-speed system clock, subsystem clock, PLL cl ock, and high-speed on-chip oscillator clock are stopped, and with setting of ADSLP = 1. Remarks 1. f MX: High-speed system clock frequency 2. fSUB: Subsystem clock frequency 3. fEXS: External subsystem clock frequency 4. fPLL: PLL clock frequency 5. fIH: High-speed on-chip oscillator clock frequency 6. fIL: Low-speed on-chip oscillator clock frequency 7. fCLK: CPU/peripheral hardware clock frequency

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 161 of 207 Dec 31, 2025 (TA = -40 to +150°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Window watchdog timer operating current IWDT Notes 1, 2 f WDT = 15 kHz 0.3 µA A/D converter operating current IADC Note 3 When conversion at maximum speed AVREFP = VDD = 5.0 V 1.3 1.7 mA When internal reference voltage is selected Note 5 75.0 µA AVREFP current I ADREF Note 7 AV REFP = 5.0 V 65.0 µA Sample-and-hold circuit operating current IADSH Note 8 0.8 1.2 mA LVD operating current I LVD Note 4 0.08 µA D/A converter operating current IDAC 0.8 1.5 mA Comparator operating current I CMP 50.0 µA BGO operating current I BGO Note 6 2.5 12.2 mA Notes 1. When the high-speed on-chip oscillator clock and high-speed system clock are stopped. 2. Current flowing only to the watchdog timer (including the operation current of the 15 kHz on-chip oscillator). The current value is the sum of IDD1, IDD2, or IDD3 and IWDT when the watchdog timer operates in STOP mode. 3. Current flowing only to the A/D converte r. The current value is the sum of I DD1 or IDD2 and IADC when the A/D converter operates in operation mode or HALT mode. 4. Current flowing only to the LVD circuit. The current value is the sum of IDD1, IDD2, or IDD3 and ILVD when the LVD circuit operates in operation mode, HALT mode, or STOP mode. 5. Operating current that increases when the internal reference voltage is selected. This current flows even when conversion is stopped. 6. Current increased by the BGO operation. The current value is the sum of I DD1 or IDD2 and IBGO when the BGO operates in operation mode or HALT mode. 7. Operating current that increases when the AV REFP is selected. This current flows even when conversion is stopped. 8. Operating current that increases when the sample-and-hol d circuit is used. This current flows for each analog input channel.

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 162 of 207 Dec 31, 2025 (2) RL78/F23 (TA = -40 to +150°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2) Items Symbol Conditions MIN. TYP. MAX. Unit Supply current Note 1 IDD1 Operating mode Normal operation Note 2 High-speed on- chip oscillator clock operation f IH = 80 MHz f CLK = 40 MHz Notes 3, 4 9.7 18.0 mA fIH = 40 MHz f CLK = fIH Notes 3, 4 9.0 16.5 mA fIH = 2 MHz f CLK = fIH Notes 3, 4 1.6 3.2 mA Resonator operation fMX = 20 MHz f CLK = fMX Notes 3, 5 5.0 9.5 mA fMX = 2 MHz f CLK = fMX Notes 3, 5 1.4 3.0 mA Resonator operation (PLL operation) (PLL input clock = f MX) fPLL = 80 MHz, fMX = 20 MHz fCLK = 40 MHz Notes 3, 6 9.2 18.0 mA fPLL = 40 MHz, fMX = 20 MHz fCLK = 40 MHz Notes 3, 6 9.0 16.5 mA fPLL = 40 MHz, fMX = 4 MHz fCLK = 40 MHz Notes 3, 6 8.6 16.0 mA Subsystem clock operation SUB = fEXS) fSUB = 32.768 kHz fCLK = fSUB Note 7 6.5 600 µA Low-speed on- chip oscillator clock operation f IL = 15 kHz f CLK = fIL Note 8 3.3 600 µA Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0, VSS, or EVSS0. However, not including the current flowing into the I/O buffer and on- chip pull-up/pull-down resistors. 2. Current drawn when all the CP U instructions are executed. 3. The values below the MAX. column include the peripheral operation current (except for background operation (BGO)). However, the LVD circuit and A/D converter are stopped. 4. When high-speed system clock, subsyst em clock, PLL clock, and low-speed on-chip oscillator clock are stopped. 5. When subsystem clock, PLL clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped. 6. When subsystem clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped. 7. When high-speed system clock, PLL cl ock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator are stopped, and with setting of ADSLP = 1. 8. When high-speed system clock, subsystem clock, PLL cl ock, and high-speed on-chip oscillator clock are stopped, and with setting of ADSLP = 1. Remarks 1. f MX: High-speed system clock frequency 2. f SUB: Subsystem clock frequency 3. f EXS: External subsystem clock frequency 4. f PLL: PLL clock frequency 5. f IH: High-speed on-chip oscillator clock frequency 6. f IL: Low-speed on-chip oscillator clock frequency 7. fCLK: CPU/peripheral hardware clock frequency

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 163 of 207 Dec 31, 2025 (TA = -40 to +150°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2) Items Symbol Conditions MIN. TYP. MAX. Unit Supply current Notes 1, 3 IDD2 HALT mode Note 2 High-speed on-chip oscillator clock operation f IH = 80 MHz f CLK = 40 MHz Note 5 3.4 12.0 mA fIH = 40 MHz f CLK = fIH Note 5 2.8 10.5 mA fIH = 2 MHz f CLK = fIH Note 5 0.5 1.9 mA Resonator operation f MX = 20 MHz f CLK = fMX Note 6 1.5 6.0 mA fMX = 2 MHz f CLK = fMX Note 6 0.3 1.9 mA Resonator operation (PLL operation) (PLL input clock = f MX) fPLL = 80 MHz, fMX = 20 MHz fCLK = 40 MHz Note 7 3.1 12.0 mA fPLL = 40 MHz, fMX = 20 MHz fCLK = 40 MHz Note 7 2.8 10.5 mA fPLL = 40 MHz, fMX = 4 MHz fCLK = 40 MHz Note 7 2.5 10.0 mA Subsystem clock operation (fSUB = fEXS) fSUB = 32.768 kHz fCLK = fSUB Note 8 0.7 320 µA Low-speed on-chip oscillator clock operation f IL = 15 kHz f CLK = fIL Note 9 0.7 320 µA IDD3 STOP mode Note 4 TA = +25°C 0.5 µA TA = +50°C 4.5 TA = +70°C 9.0 TA = +105°C 51 TA = +125°C 110 TA = +150°C 300 ISNOZ SNOOZE mode DTC operation 6.0 mA Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0, VSS, or EVSS0. However, not including the current flowing into the I/O buffer and on- chip pull-up/pull-down resistors. 2. When HALT mode is entered during fetch from the flash memory. 3. The values below the MAX. column include the pe ripheral operation current and STOP leakage current. However, the watchdog timer, LVD circuit, and A/D converter are stopped. 4. When high-speed system clock, subsystem clock, PLL cl ock, high-speed on-chip oscillator clock, and low- speed on-chip oscillator clock are stopped. 5. When high-speed system clock, subsyst em clock, PLL clock, and low-speed on-chip oscillator clock are stopped. 6. When subsystem clock, PLL clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped. 7. When subsystem clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped. 8. When high-speed system clock, PLL cl ock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped, and with setting of ADSLP = 1. 9. When high-speed system clock, subsystem clock, PLL cl ock, and high-speed on-chip oscillator clock are stopped, and with setting of ADSLP = 1. Remarks 1. f MX: High-speed system clock frequency 2. fSUB: Subsystem clock frequency 3. fEXS: External subsystem clock frequency 4. fPLL: PLL clock frequency 5. fIH: High-speed on-chip oscillator clock frequency 6. fIL: Low-speed on-chip oscillator clock frequency 7. fCLK: CPU/peripheral hardware clock frequency

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 164 of 207 Dec 31, 2025 (TA = -40 to +150°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Window watchdog timer operating current IWDT Notes 1, 2 f WDT = 15 kHz 0.3 µA A/D converter operating current I ADC Note 3 When conversion at maximum speed AVREFP = VDD = 5.0 V 1.3 1.7 mA When internal reference voltage is selected Note 5 75.0 µA AVREFP current I ADREF Note 7 AV REFP = 5.0 V 65.0 µA Sample-and-hold circuit operating current IADSH Note 8 0.8 1.2 mA LVD operating current I LVD Note 4 0.08 µA BGO operating current I BGO Note 6 2.5 12.2 mA Notes 1. When the high-speed on-chip oscillator clock and high-speed system clock are stopped. 2. Current flowing only to the watchdog timer (including the operation current of the 15 kHz on-chip oscillator). The current value is the sum of IDD1, IDD2, or IDD3 and IWDT when the watchdog timer operates in STOP mode. 3. Current flowing only to the A/D converte r. The current value is the sum of I DD1 or IDD2 and IADC when the A/D converter operates in operation mode or HALT mode. 4. Current flowing only to the LVD circuit. The current value is the sum of IDD1, IDD2, or IDD3 and ILVD when the LVD circuit operates in operation mode, HALT mode, or STOP mode. 5. Operating current that increases when the internal reference voltage is selected. This current flows even when conversion is stopped. 6. Current increased by the BGO operation. The current value is the sum of I DD1 or IDD2 and IBGO when the BGO operates in operation mode or HALT mode. 7. Operating current that increases when the AV REFP is selected. This current flows even when conversion is stopped. 8. Operating current that increases when the sample-and-hol d circuit is used. This current flows for each analog input channel.

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 165 of 207 Dec 31, 2025

5.4 AC Characteristics

5.4.1 Basic Operation

(TA = -40 to +150°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Instruction cycle (minimum instruction execution time) TCY High-speed on-chip oscillator clock operation 0.025 0.5 µs High-speed system clock operation 0.05 0.5 µs PLL clock operation 0.025 0.5 µs Subsystem clock operation 28.5 30.5 34.5 µs Low-speed on-chip oscillator clock operation 66.6 µs In self programming mode 0.025 0.5 µs CPU/peripheral hardware clock frequency fCLK 0.025 66.6 µs External system clock frequency fEX 2.0 20.0 MHz fEXS 29 35 kHz External system clock input high-level width, low-level width t EXH, tEXL 24 ns tEXHS, tEXLS 13.7 µs TI00 to TI07, TI10 to TI17 input high-level width, low- level width t TIH, tTIL 1/f MCK+10 ns TO00 to TO07, TO10 to TO17, TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1, TRJIO0, TRJO0 output frequency f TO Normal slew rate, C = 30 pF 4.0 V ≤ EVDD0 ≤ 5.5 V 16 MHz 2.7 V ≤ EVDD0 < 4.0 V 8 MHz TO01, TO06, TO07, TO11, TO13, TRDIOC0, TRDIOD0, TRDIOD1, TRJO0 only, Special slew rate, C = 30 pF PCLBUZ0 output frequency f PCL Normal slew rate C = 30 pF 4.0 V ≤ EVDD0 ≤ 5.5 V 16 MHz 2.7 V ≤ EVDD0 < 4.0 V 8 MHz Special slew rate C = 30 pF Timer RJ input cycle t C TRJIO0 100 ns Timer RJ input high-level width, low-level width tTJIH, tTJIL TRJIO0 40 ns Timer RDe input high-level, low-level width tTDIH, tTDIL TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1, TRDCLK0, TRD0RES, TRD1RES 3/f TRD ns Timer RDe pulse output forced cutoff signal low- level width t TDSIL P137/INTP0 2 MHz < fCLK ≤ 40 MHz 1 µs fCLK ≤ 2 MHz 1/fCLK + 1 µs Caution Excluding the error in oscillation frequency accuracy. Remarks 1. f MCK: Timer array unit operation clock frequency 2. f TRD: Timer RDe operation clock frequency

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 166 of 207 Dec 31, 2025 (TA = -40 to +150°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Interrupt input high-level width, low-level width tINTH, tINTL INTP0 to INTP13 Note 1 1 µs KR0 to KR7 key interrupt input low-level width tKR 250 ns RESET low-level width t RSL Note 1 10 µs Port output rise time, port output fall time tRO, tFO P00 to P03, P10 to P17, P30 to P32, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P106, P107, P120, P125 to P127, P130, P140, P150 to P157 (normal slew rate) C = 30 pF DD0 ≤ 5.5 V 25 ns 2.7 V ≤ EVDD0 < 4.0 V 55 ns P10, P12, P14, P30, P120, P140 (special slew rate) C = 30 pF DD0 ≤ 5.5 V 25 Note 2 60 ns 2.7 V ≤ EVDD0 < 4.0 V 100 ns Notes 1. Pins RESET, INTP0 to INTP3, INTP12, and INTP13 have noise filters for transient levels lasting less than 100 ns. 2. T A = +25°C, EVDD0 = 5.0 V AC Timing Test Points Test pointsVIH VIL VIH VIL

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 167 of 207 Dec 31, 2025 External System Clock Timing EXCLK EXCLKS TI/TO Timing TI00 to TI07, TI10 to TI17, TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1, TRDCLK0, TRD0RES, TRD1RES TO00 to TO07, TO10 to TO17, TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1, TRJIO0, TRJO0 TRJIO0 P137/INTP0 1/f EX t EXL t EXH 0.8 VDD (MIN.) 0.2 VDD (MAX.) 1/f EXS t EX LS t EXHS 0.8 VDD (MIN.) 0.2 VDD (MAX.) t TIL, t TDIL t TIH, t TDIH 1/f TO t TJIL t TJIH t TDSIL

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 168 of 207 Dec 31, 2025 Interrupt Request Input Timing INTP0 to INTP13 Key Interrupt Input Timing KR0 to KR7 RESET Input Timing RESET Output Rising and Falling Timing Output pin t INTL t INTH t KR t RSL t RO t FO

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 169 of 207 Dec 31, 2025

5.5 Peripheral Functions Characteristics

5.5.1 Serial Array Unit

(1) During communication at same pot ential (UART mode) (dedicated baud rate generator output) (TA = -40 to +150°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate – f MCK/6 bps fCLK = 40 MHz, fMCK = fCLK Normal slew rate 6.6 Mbps Special slew rate 2 Mbps UART mode connection diagram (during communication at same potential) UART mode bit width (during communication at same potential) (reference) Caution Select the normal input buffer for the RXD0 pi n and RXD1 pin and normal output mode for the TXD0 pin and TXD1 pin. Remark fMCK: Serial array unit operation clock frequency User's deviceRL78 microcontroller TXD0, TXD1 RXD0, RXD1 RX TX Baud rate error tolerance 1/Transfer rate High-/low-bit width TXD0, TXD1 RXD0, RXD1

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 170 of 207 Dec 31, 2025 (2) During communication at same potential (CSI mode) (master mode, SCKp … internal clock output, normal slew rate) (TA = -40 to +150°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKp cycle time t KCY1 150 Note 5 ns SCKp high-level width, low-level width t KH1, tKL1 4.0 V ≤ EVDD0 ≤ 5.5 V tKCY1/2 – 12 ns 2.7 V ≤ EVDD0 < 4.0 V tKCY1/2 – 18 ns SIp setup time (to SCKp↑) Note 1 tSIK1 4.0 V ≤ EVDD0 ≤ 5.5 V 44 ns 2.7 V ≤ EVDD0 < 4.0 V 55 ns SIp hold time (from SCKp↑) Note 2 tKSI1 30 ns Delay time from SCKp↓ to SOp output Note 3 tKSO1 C = 30 pF Note 4 30 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The Slp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0 or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp ↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SCKp and SOp output lines. 5. t KCY1 ≥ 4/fMCK must also be satisfied. Caution Select the normal input buffer for the SIp pin and normal output mode for the SOp pin and SCKp pin. Remark p: CSIp (p = 00, 01, 10, 11), m: Unit m (m = 0, 1), n: Channel n (n = 0, 1) <R>

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 171 of 207 Dec 31, 2025 (3) During communication at same potential (CSI mode) (master mode, SCKp … internal clock output, special slew rate) (TA = -40 to +150°C, 4.0 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKp cycle time t KCY1 500 Note 5 ns SCKp high-level width, low-level width t KH1, tKL1 t KCY1/2 - 60 ns SIp setup time (to SCKp↑) Note 1 tSIK1 120 ns SIp hold time (from SCKp↑) Note 2 tKSI1 80 ns Delay time from SCKp↓ to SOp output Note 3 tKSO1 C = 30 pF Note 4 90 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The Slp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0 or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp ↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SCKp and SOp output lines. 5. t KCY1 ≥ 4/fMCK must also be satisfied. Caution Select the normal input buffer for the SIp pin and normal output mode and special slew rate for the SOp pin and SCKp pin. Remark p: CSIp (p = 00, 01, 10, 11), m: Unit m (m = 0, 1), n: Channel n (n = 0, 1) <R>

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 172 of 207 Dec 31, 2025 (4) During communication at same potential (CSI mode) (s lave mode, SCKp … external clock input, normal slew rate) (TA = -40 to +150°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKp cycle time t KCY2 32 MHz < fMCK 10/fMCK ns fMCK ≤ 32 MHz 8/fMCK ns SCKp high-level width, low-level width tKH2, tKL2 t KCY2/2 ns SIp setup time (to SCKp↑) Note 1 tSIK2 1/f MCK + 20 ns SIp hold time (from SCKp↑) Note 2 tKSI2 1/f MCK + 31 ns Delay time from SCKp↓ to SOp output Note 3 tKSO2 C = 30 pF Note 4 4.0 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V 2/f MCK + 44 ns 2.7 V ≤ VDD = EVDD0 = EVDD1 < 4.0 V 2/f MCK + 60 ns SSIp setup time t SSIK DAP = 0 120 ns DAP = 1 1/f MCK + 120 ns SSIp hold time t KSSI DAP = 0 1/f MCK + 120 ns DAP = 1 120 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The Slp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0 or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp ↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp, S CKp and SSIp pins and normal output mode for the SOp pin. Remarks 1. p: CSIp (p = 00, 01, 10, 11), m: Unit m (m = 0, 1), n: Channel n (n = 0, 1) 2. f MCK: Serial array unit operation clock frequency

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 173 of 207 Dec 31, 2025 (5) During communication at same potential (CSI mode) (sla ve mode, SCKp … external clock input, special slew rate) (TA = -40 to +150°C, 4.0 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKp cycle time t KCY2 20 MHz < fMCK 10/fMCK ns fMCK ≤ 10 MHz 6/fMCK ns SCKp high-level width, low-level width t KH2, tKL2 t KCY2/2 ns SIp setup time (to SCKp↑) Note1 tSIK2 1/f MCK + 50 ns SIp hold time (from SCKp↑) Note 2 tKSI2 1/f MCK + 50 ns Delay time from SCKp↓ to SOp output Note 3 tKSO2 C = 30 pF Note 4 2/f MCK + 80 ns SSIp setup time t SSIK DAP = 0 120 ns DAP = 1 1/f MCK + 120 ns SSIp hold time t KSSI DAP = 0 1/f MCK + 120 ns DAP = 1 120 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The Slp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0 or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp ↓” when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp ↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp, SCKp and SSIp pins and normal output mode and special slew rate for the SOp pin. Remarks 1. p: CSIp (p = 00, 01, 10, 11), m: Unit m (m = 0, 1), n: Channel n (n = 0, 1) 2. f MCK: Serial array unit operation clock frequency

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 174 of 207 Dec 31, 2025 CSI mode connection diagram (during communication at same potential) CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1) Remark p: CSIp (p = 00, 01, 10, 11), m: Unit m (m = 0, 1), n: Channel n (n = 0, 1) RL78 microcontroller SCKp SSIp User's device SCK SOp SIp SO SI <Master> RL78 microcontroller SCKp SSIp User's device SCK SOp SIp SO SI <Slave> SSO t KCY2 t KL2 t KH2 Input data Output data t SI K2 t KSI2 t KSO2 t KSSI t SSIK SCKp SIp SOp SSIp

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 175 of 207 Dec 31, 2025 CSI mode serial transfer timing (during communication at same potential) (When DAPmn= 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0) Remark p: CSIp (p = 00, 01, 10, 11), m: Unit m (m = 0, 1), n: Channel n (n = 0, 1) t KCY1, 2 t KH1, 2 t KL1, 2 Input data Output data t SI K1, 2 t KSI1, 2 t KSO1, 2 t KSSI t SSIK SCKp SIp SOp SSIp

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 176 of 207 Dec 31, 2025 (6) During communication at same potential (simplified I 2C mode) (SDAr: N-ch open-drain output (EVDD tolerance) mode, SCLr: normal output mode) (TA = -40 to +150°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCLr clock frequency f SCL 1000 Note kHz Hold time when SCLr = “L” t LOW 475 ns Hold time when SCLr = “H” t HIGH 475 ns Data setup time (reception) t SU:DAT 1/f MCK + 85 ns Data hold time (transmission) t HD:DAT Cb = 50 pF, Rb = 2.7 kΩ 0 305 ns Note f CLK ≤ fMCK/4 must also be satisfied. Simplified I2C mode connection diagram (during communication at same potential) Simplified I2C mode serial transfer timing (during communication at same potential) Caution Select the normal input buffer and N-ch open-drain output mode for the SDAr pin and normal output mode for the SCLr pin. Remarks 1. R b [ Ω]: Communication line (SDAr) pull-up resistance, C b [F]: Communication line (SCLr, SDAr) load capacitance 3. f MCK: Serial array unit operation clock frequency User's deviceRL78 microcontroller SDAr SCLr SDA SCL VDD Rb 1/f SCL t LO W t HIGH SCLr SDAr t HD:DAT t SU:DAT

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 177 of 207 Dec 31, 2025 (7) During communication at same potential (simplified I 2C mode) (SDAr and SCLr: N-ch open-drain output (EVDD tolerance) mode) (TA = -40 to +150°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. MAX. Unit SCLr clock frequency f SCL 400 Note kHz Hold time when SCLr = “L” t LOW 4.0 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 1.7 kΩ 1300 ns 2.7 V ≤ VDD < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ Hold time when SCLr = “H” t HIGH 4.0 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 1.7 kΩ 600 ns 2.7 V ≤ VDD < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ Data setup time (reception) t SU:DAT 4.0 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 1.7 kΩ 1/fMCK + 120 ns 2.7 V ≤ VDD < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ 1/fMCK + 270 ns Data hold time (transmission) t HD:DAT 4.0 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 1.7 kΩ 0 300 ns 2.7 V ≤ VDD < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ Note f CLK ≤ fMCK/4 must also be satisfied. Simplified I2C mode connection diagram (during communication at same potential) Caution Select the normal input buffer and N-ch open-drain output mode for the SDAr pin and SCLr pin. Remarks 1. R b [Ω]: Communication line (SDAr, SCLr) pull-up resistance, Cb [F]: Communication line (SDAr, SCLr) load capacitance, Vb [V]: Communication line voltage 3. f MCK: Serial array unit operation clock frequency User's deviceRL78 microcontroller SDAr SCLr SDA SCL Vb Rb Vb Rb

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 178 of 207 Dec 31, 2025 Simplified I2C mode serial transfer timing (during communication at same potential) Remark r: IICr (r = 00, 01, 10, 11) 1/f SCL t LO W t HIGH SCLr SDAr t HD:DAT t SU:DAT

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 179 of 207 Dec 31, 2025 (8) Communication at different potential (UART mode) (T XD output buffer: N-ch open-drain, RXD input buffer: TTL) (TA = -40 to +150°C, 4.0 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate – Reception 2.7 V ≤ Vb ≤ EVDD0, VIH = 2.2 V, VIL = 0.8 V f MCK/6 bps Theoretical value of the maximum transfer rate Note (Cb = 30 pF) Transmission 2.7 V ≤ Vb ≤ EVDD0, VOH = 2.2 V, VOL = 0.8 V Smaller number of the values given by fMCK/6 and expression 1 is applicable. bps Theoretical value of the maximum transfer rate Note (Cb = 30 pF) Normal slew rate Note Expression 1: Maximum transfer rate = 1 / [{-Cb × Rb × ln (1 - 2.2/Vb)} × 3] UART mode connection diagram (during communication at different potential) User's deviceRL78 microcontroller TXD0, TXD1 RXD0, RXD1 RX TX Vb Rb

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 180 of 207 Dec 31, 2025 UART mode bit width (during communication at different potential) (reference) Caution Select the TTL input buffer for the RXD0 pin and RXD1 pin and N-ch open-drain output mode for the TXD0 pin and TXD1 pin. Remarks 1. R b [Ω]: Communication line (TXD) pull-up resistance, Cb [F]: Communication line (TXD) load capacitance, Vb [V]: Communication line voltage 2. f MCK: Serial array unit operation clock frequency TXD0, TXD1 RXD0, RXD1 Baud rate error tolerance 1/Transfer rate High-/low-bit width Baud rate error tolerance 1/Transfer rate High-bit width Low-bit width

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 181 of 207 Dec 31, 2025 (9) During communication at different potential (3-V supply system) (CSI mode) (master mode, SCKp … internal clock output, normal slew rate) (TA = -40 to +150°C, 4.0 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKp cycle time t KCY1 2.7 V ≤ Vb ≤ EVDD0, Cb = 30 pF, Rb = 1.4 kΩ SCKp high-level width t KH1 2.7 V ≤ Vb ≤ EVDD0, Cb = 30 pF, Rb = 1.4 kΩ tKCY1/2 - 75 ns SCKp low-level width t KL1 2.7 V ≤ Vb ≤ EVDD0, Cb = 30 pF, Rb = 1.4 kΩ tKCY1/2 - 20 ns SIp setup time (to SCKp↑) Note 1 tSIK1 2.7 V ≤ Vb ≤ EVDD0, Cb = 30 pF, Rb = 1.4 kΩ 150 ns SIp setup time (to SCKp↓) Note 2 tSIK1 2.7 V ≤ Vb ≤ EVDD0, Cb = 30 pF, Rb = 1.4 kΩ 70 ns SIp hold time (from SCKp↑) Note 1 tKSI1 2.7 V ≤ Vb ≤ EVDD0, Cb = 30 pF, Rb = 1.4 kΩ 30 ns SIp hold time (from SCKp↓) Note 2 tKSI1 2.7 V ≤ Vb ≤ EVDD0, Cb = 30 pF, Rb = 1.4 kΩ 30 ns Delay time from SCKp↓ to SOp output Note1 tKSO1 2.7 V ≤ Vb ≤ EVDD0, Cb = 30 pF, Rb = 1.4 kΩ 120 ns Delay time from SCKp↑ to SOp output Note2 tKSO1 2.7 V ≤ Vb ≤ EVDD0, Cb = 30 pF, Rb = 1.4 kΩ 40 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. 2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. tKCY1 ≥ 4/fMCK must also be satisfied. CSI mode connection diagram (during communication at different potential) Caution Select the TTL input buffer for the SIp pin and N-ch open-drain output mode for the SOp pin and SCKp pin. Remarks 1. Rb [Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb [F]: Communication line (SOp, SCKp) load capacitance, Vb [V]: Communication line voltage 2. p: CSIp (p = 00, 01, 10, 11), m: Unit m (m = 0, 1), n: Channel n (n = 0, 1) 3. AC characteristics of the serial array unit during communication at different potential in CSI mode are measured with the VIH and VIL below: User's deviceRL78 microcontroller SCKp SSIp SCK SI Vb Rb Vb Rb SOp SIp SO <Master> <R>

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 182 of 207 Dec 31, 2025 CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1) CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn= 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0) Remark p: CSIp (p = 00, 01, 10, 11), m: Unit m (m = 0, 1), n: Channel n (n = 0, 1) t KCY1 t KL1 t KH1 Input data Output data t SI K1 t KSI1 t KSO1 SCKp SIp SOp t KCY1 t KH1 t KL1 Input data Output data t SI K1 t KSI1 t KSO1 SCKp SIp SOp

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 183 of 207 Dec 31, 2025 (10) During communication at different potential (3-V supply system) (CSI mode) (slave mode, SCKp … external clock input, normal slew rate) (TA = -40 to +150°C, 4.0 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKp cycle time t KCY2 2.7 V ≤ Vb ≤ VDD 32 MHz < fMCK 20/f MCK ns fMCK ≤ 4 MHz 6/fMCK ns SCKp high-level width, low-level width tKH2, tKL2

2.7 V ≤ Vb ≤ VDD tKCY2/2 – 20 ns

(to SCKp↑) Note 1 tSIK2 90 ns SIp hold time (from SCKp↑) Note 2 tKSI2 1/f MCK + 50 ns Delay time from SCKp↓ to SOp output Note 3 tKSO2 2.7 V ≤ Vb ≤ VDD, Cb = 30 pF, Rb = 1.4 kΩ 2/f MCK + 120 ns SSIp setup time t SSIK DAP = 0 120 ns DAP = 1 1/f MCK + 120 ns SSIp hold time t KSSI DAP = 0 1/f MCK + 120 ns DAP = 1 120 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The Slp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0 or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp ↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 184 of 207 Dec 31, 2025 CSI mode connection diagram (during communication at different potential) Caution Select the TTL input buffer for the SIp, SCKp and SSIp pins and N-ch open-drain output mode for the SOp pin. Remarks 1. R b [Ω]: Communication line (SOp) pull-up resistance, Cb [F]: Communication line (SOp) load capacitance, Vb [V]: Communication line voltage 2. p: CSIp (p = 00, 01, 10, 11), m: Unit m (m = 0, 1), n: Channel n (n = 0, 1) 3. AC characteristics of the serial array unit during communication at different potential in CSI mode are measured with the VIH and VIL below: User's device RL78 microcontroller SCKp SSIp SCK SI Vb Rb SOp SIp SO ＜Slave＞ SSO

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 185 of 207 Dec 31, 2025 CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1) CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn= 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0) Remark p: CSIp (p = 00, 01, 10, 11), m: Unit m (m = 0, 1), n: Channel n (n = 0, 1) t KCY2 t KL2 t KH2 Input data Output data t SI K2 t KSI2 t KSO2 t KS SI t SSIK SCKp SIp SOp SSIp t KCY2 t KH2 t KL2 Input data t SI K2 t KSI2 t KS SI t SSIK SCKp SIp SSIp Output data t KSO2 SOp

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 186 of 207 Dec 31, 2025 (11) During communication at different pot ential (3-V supply system) (simplified I2C mode) (SDAr: TTL input buffer mode or N-ch open-drain output (EVDD tolerance) mode, SCLr: N-ch open-drain output (EVDD tolerance) mode) (TA = -40 to +150°C, 4.0 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. MAX. Unit SCLr clock frequency f SCL 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 1.4 kΩ Hold time when SCLr = “L” t LOW 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 1.4 kΩ 1200 ns Hold time when SCLr = “H” t HIGH 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 1.4 kΩ 600 ns Data setup time (reception) t SU:DAT 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 1.4 kΩ 135 + 1/fMCK ns Data hold time (transmission) t HD:DAT 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 1.4 kΩ 0 140 ns Note fSCL ≤ fMCK/4 must also be satisfied. Simplified I2C mode connection diagram (during communication at different potential) Simplified I2C mode serial transfer timing (during communication at different potential) Caution Select the TTL input buffer and the N-ch open-drain output mode for the SDAr pin and N-ch open-drain output mode for the SCLr pin. Remarks 1. R b [Ω]: Communication line (SDAr, SCLr) pull-up resistance, Cb [F]: Communication line (SDAr, SCLr) load capacitance, Vb [V]: Communication line voltage 2. f MCK: Serial array unit operation clock frequenc User's device RL78 microcontroller SDAr SCLr SDA SCL Vb Rb Vb Rb 1/f SCL t LO W t HIGH SCLr SDAr t HD:DAT t SU:DAT

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 187 of 207 Dec 31, 2025

5.5.2 Serial Interface IICA

(TA = -40 to +150°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions Normal M ode Fast Mode Fast Mode Plus Unit SCLA0 clock frequency f SCL Fast mode plus: Fast mode: Normal mode: Setup time of restart condition Note 1 t SU:STA 4.7 0.6 0.26 µs Hold time t HD:STA 4.0 0.6 0.26 µs Hold time when SCLA0 = ”L” t LOW 4.7 1.3 0.5 µs Hold time when SCLA0 = ”H” t HIGH 4.0 0.6 0.26 µs Data setup time (reception) t SU:DAT 250 100 50 ns Data hold time (transmission) Note 2 t HD:DAT 0 3.45 0 0.9 0 µs Setup time of stop condition t SU:STO 4.0 0.6 0.26 µs Bus-free time t BUF 4.7 1.3 0.5 µs Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected. 2. The maximum value (MAX.) of t HD:DAT is during normal transfer and a wa it state is inserted in the ACK (acknowledge) timing. Remark The maximum value of C b (communication line capacitance) and the value of R b (communication line pull-up resistor) at that time in each mode are as follows. Standard mode: C b = 400 pF, Rb = 2.7 kΩ Fast mode: C b = 320 pF, Rb = 1.1 kΩ Fast mode plus: C b = 120 pF, Rb = 1.1 kΩ IICA serial transfer timing t LO W SCLA0 SDAA0 Stop condition t R t HD:DAT t HD:STA t HIGH t F t SU:DAT t SU:STA t HD:STA t SU:STO Start condition Restart condition Stop condition t BUF <R> <R> <R>

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5.5.3 On-chip Debug (UART)

(TA = -40 to +150°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate – 115.2 k 1 M bps

5.5.4 LIN/UART Module (RLIN3) UART Mode

A = -40 to +150°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate – Operation mode, HALT mode LIN communication clock source (fCLK or fMX): 4 to 40 MHz 4000 kbps SNOOZE mode LIN communication clock source (f CLK): 2 to 40 MHz 9.6

5.5.5 CAN-FD Communication Interface (RS-CANFD lite) Timing

(TA = -40 to +150°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate – Classical CAN mode 1 Mbps CAN-FD mode Data bit rate 5 Mbps CAN-FD mode Nominal bit rate 1 Mbps Internal delay time Note t NODE 50 ns Note t NODE = Internal input delay time (tINPUT) + Internal output delay time (tOUTPUT) Image of Internal delay RL78/F24 CAN controller CTXD0 CRXD0 Internal output delay time （t OUTPUT） Internal input delay time （t INPUT）

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5.6 Analog Characteristics

5.6.1 A/D Converter Characteristics

Classification of A/D converter characteristics Reference Input channel Reference voltage (+) = AVREFP Reference voltage (-) = AVREFM Reference voltage (+) = VDD Reference voltage (-) = VSS ANI0 to ANI5, ANI8 to ANI30 5.6.1 (1) 5.6.1 (2) ANI6,ANI7 － 5.6.1 (2) Internal reference voltage (+) 5.6.1 (1) 5.6.1 (2) (1) When Reference voltage (+) = AV REFP, Reference voltage (-) = AVREFM = 0 V, target ANI pin: ANI0 to ANI5, ANI8 to ANI30, Internal reference voltage (+) (TA = -40 to +150 °C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = AV REFP, Reference voltage (-) = AVREFM = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 12 bit Overall error Note 1 ABS ANI0 to ANI5, ANI8 to ANI23 Note 2, [4.5 V ≤ AVREFP = VDD ≤ 5.5 V] ±5.0 LSB ANI0 to ANI5, ANI8 to ANI23 Note 2, [2.7 V ≤ AVREFP = VDD < 4.5 V] ±5.0 LSB ANI1, ANI2 Note 3, [4.5 V ≤ AVREFP = VDD ≤ 5.5 V], [0.25 V ≤ VAIN ≤ VDD - 0.25 V] ±6.0 LSB ANI1, ANI2 Note 3, [2.7 V ≤ AVREFP = VDD < 4.5 V], [0.25 V ≤ VAIN ≤ VDD - 0.25 V] ±8.0 LSB ANI24 to ANI30, [4.5 V ≤ AVREFP = VDD ≤ 5.5 V] ±11.0 LSB ANI24 to ANI30, [2.7 V ≤ AVREFP = VDD < 4.5 V] ±13.0 LSB Integral linearity error Note 1 INL ANI0 to ANI5, ANI8 to ANI23, [AV REFP = VDD] ±3.0 LSB ANI24 to ANI30, [AVREFP = VDD] ±7.0 LSB Differential linearity error Note 1 DNL ANI0 to ANI5, ANI8 to ANI23, [AV REFP = VDD] ±1.5 LSB ANI24 to ANI30, [AVREFP = VDD] ±3.5 LSB Zero-scale error Note 1 ZSE ANI0 to ANI5, ANI8 to ANI23 Note 2, [AVREFP = VDD] ±4.5 LSB ANI24 to ANI30, [AVREFP = VDD] ±8.5 LSB Full-scale error Note 1 FSE ANI0 to ANI5, ANI8 to ANI23 Note 2, [AVREFP = VDD] ±4.5 LSB ANI24 to ANI30, [AVREFP = VDD] ±8.5 LSB (1/2) (Notes are at the end of this table.)

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 190 of 207 Dec 31, 2025 Parameter Symbol Conditions MIN. TYP. MAX. Unit Reference voltage (+) AV REFP 2.7 V DD V Analog input voltage V AIN ANI0 to ANI5, ANI8 to ANI30 0 AV REFP V Analog input slew rate SR 0.4 V/µs Operation clock f AD 2 40 MHz Conversion time Note 4 (per 1 channel) tCONV ADCLK = 40MHz, input impedance ≤ 0.5 kΩ ANI0 to ANI5, ANI8 to ANI15 Note 2 1.125 µs ANI16 to ANI30 1.8 µs ANI1, ANI2 Note 3 2.1 µs Notes 1. Excludes quantization error (±1/2 LSB). 2. In case that dedicated sample & hold circuit is not used. 3. In case that dedicated sample & hold circuit is used. 4. The A/D conversion processing time (tCONV) consists of sampling time and time for conversion by successive approximation. (2/2)

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 191 of 207 Dec 31, 2025 (2) When Reference voltage (+) = V DD, Reference voltage (-) = VSS, target ANI pin: ANI0 to ANI30, Internal reference voltage (+). (TA = -40 to +150 °C, 2.7 V ≤ EVDD0 = EV DD1 = V DD ≤ 5.5 V, V SS = EV SS0 = EV SS1 = 0 V, Reference voltage (+) = V DD, Reference voltage (-) = VSS) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 12 bit Overall error Note 1 ABS ANI0 to ANI23 Note 2, [4.5 V ≤ VDD ≤ 5.5 V] ±13.0 LSB ANI0 to ANI23 Note 2, [2.7 V ≤ VDD < 4.5 V] ±15.0 LSB ANI1, ANI2 Note 3, [4.5 V ≤ VDD ≤ 5.5 V], [0.25 V ≤ VAIN ≤ VDD - 0.25 V] ±14.0 LSB ANI1, ANI2 Note 3, [2.7 V ≤ VDD < 4.5 V], [0.25 V ≤ VAIN ≤ VDD - 0.25 V] ±16.0 LSB ANI24 to ANI30, [4.5 V ≤ VDD ≤ 5.5 V] ±19.0 LSB ANI24 to ANI30, [2.7 V ≤ VDD < 4.5 V] ±21.0 LSB Integral linearity error Note 1 INL ANI0 to ANI23 ±7.0 LSB ANI24 to ANI30 ±9.0 LSB Differential linearity error Note 1 DNL ANI0 to ANI23 ±3.5 LSB ANI24 to ANI30 ±5.5 LSB Zero-scale error Note 1 ZSE ANI0 to ANI23 Note 2 ±14.5 LSB ANI24 to ANI30 ±18.5 LSB Full-scale error Note 1 FSE ANI0 to ANI23 Note 2 ±14.5 LSB ANI24 to ANI30 ±18.5 LSB Analog input voltage V AIN ANI0 to ANI30 0 V DD V Analog input slew rate SR 0.4 V/µs Operation clock f AD 2 40 MHz Conversion time Note 4 (per 1 channel) tCONV ADCLK = 40 MHz, input impedance ≤ 0.5 kΩ ANI0 to ANI15 Note 2 1.125 µs ANI16 to ANI30 1.8 µs ANI1, ANI2 Note 3 2.1 µs Notes 1. Excludes quantization error (±1/2 LSB). 2. In case that dedicated sample & hold circuit is not used. 3. In case that dedicated sample & hold circuit is used. 4. The A/D conversion processing time (tCONV) consists of sampling time and time for conversion by successive approximation.

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5.6.2 D/A Converter Characteristics

(TA = -40 to +150°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 8 bit Overall error AINL Rload = 4 M Ω 2.7 V ≤ VDD ≤ 5.5 V -2.5/+3.0 LSB Rload = 8 MΩ 2.7 V ≤ VDD ≤ 5.5 V -2.5/+3.0 LSB Settling time t SET Cload = 20 pF 2.7 V ≤ VDD ≤ 5.5 V 3 µs

5.6.3 Comparator Characteristics

(TA = -40 to +150°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input offset voltage V IOCMP ±5 ±90 mV Input voltage range V ICMP 0 V DD V Response time t CR, tCF Input amplitude ±100 mV 70 700 ns Stabilization wait time during input channel switching Note 1 tWAIT Input amplitude ±100 mV 800 ns Operation stabilization wait time Note 2 t CMP 3.3 V ≤ VDD ≤ 5.5 V 1 µs 2.7 V ≤ VDD < 3.3 V 3 µs Notes 1. Period of time from when the comparator input channel is switched until the comparator is switched to output. 2. Period of time from when the com parator operation is enabled (HCMPON bit in CMPCTL is set to 1) until the comparator satisfies the DC/AC characteristics.

5.6.4 POR Circuit Characteristics

A = -40 to +150°C, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage Note 1 V POR Power supply rise time 1.48 1.56 1.73 V VPDR Power supply fall time 1.47 1.55 1.71 V Minimum pulse width Note 2 T PW 300 µs Detection delay time T PD 350 µs Notes 1. This indicates the POR circuit characteristics, and no rmal operation is not guarante ed under the condition of less than lower limit operation voltage (2.7 V). 2. Minimum time required for a POR reset when V DD exceeds below VPDR. Supply voltage (V DD) TPW V PO R V PDR

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5.6.5 LVD Circuit Characteristics

(1) LVD detection voltage of interrupt mode or reset mode (TA = -40 to +150°C, VPDR ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage Supply voltage level V LVD0 Power supply rise time 4.62 4.74 5.25 V Power supply fall time 4.52 4.64 5.11 V VLVD1 Power supply rise time 4.50 4.62 5.12 V Power supply fall time 4.40 4.52 4.98 V VLVD2 Power supply rise time 4.30 4.42 4.92 V Power supply fall time 4.21 4.32 4.76 V VLVD3 Power supply rise time 3.13 3.22 3.66 V Power supply fall time 3.07 3.15 3.52 V VLVD4 Power supply rise time 2.95 3.02 3.44 V Power supply fall time 2.89 2.96 3.31 V VLVD5 Power supply rise time 2.74 2.81 3.22 V Power supply fall time 2.68 Note 2.75 3.06 V Minimum pulse width t LW 300 µs Detection delay time t LD 300 µs Note The minimum value exceeds below the lower limit operation voltage (2.7 V), however, in reset mode, normal operation (same behavior when VDD = 2.7 V) is possible until a reset is effected at the power supply falling time. (2) LVD detection voltage of interrupt & reset mode (TA = -40 to +150°C, VPDR ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Interrupt and reset mode VLVD5 VPOC2, VPOC1, VPOC0 = 0, 0, 1 Note 1, falling reset voltage: 2.75 V 2.68 Note 2 2.75 3.06 V VLVD2 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 4.30 4.42 4.92 V Falling interrupt voltage 4.21 4.32 4.76 V VLVD5 VPOC2, VPOC1, VPOC0 = 0, 1, 0 Note 1, falling reset voltage: 2.75 V 2.68 Note 2 2.75 3.06 V VLVD1 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 4.50 4.62 5.12 V Falling interrupt voltage 4.40 4.52 4.98 V VLVD5 VPOC2, VPOC1, VPOC0 = 0, 1, 1 Note 1, falling reset voltage: 2.75 V 2.68 Note 2 2.75 3.06 V VLVD3 LVIS1, LVIS0 = 0, 1 Rising release reset voltage 3.13 3.22 3.66 V Falling interrupt voltage 3.07 3.15 3.52 V VLVD0 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 4.62 4.74 5.25 V Falling interrupt voltage 4.52 4.64 5.11 V Notes 1. These values indicate setting values of option bytes. 2. The minimum value exceeds below the lower limit operat ion voltage (2.7 V), however, in reset mode, normal operation (same behavior when VDD = 2.7 V) is possible until a reset is effected at the power supply falling time.

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5.7 Power Supply Voltage Rising Time

(TA = -40 to +150°C, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Maximum power supply voltage rising slope Svrmax 0 V → VDD (VPOC2 = 0 or 1 Note 2) 50 Note 3 V/ms Minimum power supply voltage rising slope Note 1 Svrmin 0 V → 2.7 V 6.5 V/ms Notes 1. The minimum power supply voltage rising slope is applied only under the following condition. When the voltage detection (LVD) circuit is not used ( VPOC2 = 1) and an external reset circuit is not used or when a reset is not effected until VDD = 2.7 V. 2. These values indicate setting values of option bytes. 3. If the power supply drops below V PDR and a POR reset is effected, this sp ecification is also applied when the power supply is recovered without dropping to 0 V.

5.8 Regulator Output Voltage Characteristics

A = -40 to +150°C, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit REGC output voltage Note V OREGC C = 0.47 to 1 µF 2.0 2.1 2.2 V Note Other than the following conditions are applicable.  In STOP mode.  When the high-speed system clock (f MX), the high-speed on-chip oscillator clock (fIH), and PLL clock (fPLL) are stopped during CPU operation with the subsystem/low-speed on-chip oscillator clock select clock (fSL).  When the hifh-speed system clock (f MX), the high-speed on-chip oscillator clock (fIH), and PLL clock (fPLL) are stopped during the HALT mode when the CPU operation with the subsyste m/low-speed on-chip oscillator clock select (fSL) has been set.

5.9 RAM Data Retention Characteristics

A = -40 to +150°C, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention supply voltage V DDDR 1.47 Note 5.5 V Note This depends on the POR detection voltage. For a falling voltage, data in RAM are retained until the voltage reaches the level that triggers a POR reset but not once it reaches the level at which a POR reset is generated. Standby release signal (interrupt request) RAM data retention STOP instruction execution STOP mode Operation mode VDDDR VDD

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5.10 Flash Memory Programming Characteristics

(TA = -40 to +150°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit System clock frequency f CLK 2 40 MHz Number of code flash rewrites Notes 1, 2, 3 C erwr Retained for 20 years TA = +85°C Note 4 1,000 Times Number of data flash rewrites Notes 1, 2, 3 Retained for 20 years TA = +85°C Note 4 10,000 Retained for 5 years TA = +85°C Note 4 100,000 Erase time T erasa Block erase 5 ms Write time T wrwa 1 word write 10 µs Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The starting point of the retaining years are after the erase. 2. When using flash memory programmer and Renesas Electronics self programming code. 3. These are the characteristics of t he flash memory and the results obtained from reliability testing by Renesas Electronics Corporation. 4. The average temperatur e for data retention. (1) Code flash memory processing time (TA = -40 to +150°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Item f CLK = 2 MHz f CLK = 4 MHz f CLK = 8 MHz f CLK = 16 MHz Unit Blank checking time 4 bytes – 29.0 – 22.0 – 19.0 – 17.0 µs 1 KB – 800.0 – 405.0 – 245.0 – 145.0 µs Internal verify time 4 bytes – 350.0 – 175.0 – 90.0 – 45.0 µs 1 KB – 19.0 – 9.5 – 5.0 – 2.5 ms Item f CLK = 20 MHz f CLK = 32 MHz f CLK = 40 MHz Unit Blank checking time 4 bytes – 17.0 – 16.0 – 16.0 µs 1 KB – 145.0 – 135.0 – 135.0 µs Internal verify time 4 bytes – 35.0 – 22.0 – 18.0 µs 1 KB – 2.0 – 1.2 – 1.0 ms Caution The listed values do not include the time until the operations of the flash memory start following execution of an instruction by software.

RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 196 of 207 Dec 31, 2025 (2) Data flash memory processing time (TA = -40 to +150°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Item f CLK = 2 MHz f CLK = 4 MHz f CLK = 8 MHz f CLK = 16 MHz Unit Blank checking time 1 byte – 29.0 – 22.0 – 19.0 – 17.0 µs 1 KB – 3.1 – 1.6 – 0.95 – 0.55 ms Internal verify time 1 byte – 350.0 – 175.0 – 90.0 – 45.0 µs 1 KB – 76.0 – 38.0 – 19.0 – 9.5 ms Item f CLK = 20 MHz f CLK = 32 MHz f CLK = 40 MHz Unit Blank checking time 1 byte – 17.0 – 16.0 – 16.0 µs 1 KB – 0.55 – 0.5 – 0.5 ms Internal verify time 1 byte – 35.0 – 22.0 – 18.0 µs 1 KB – 7.5 – 4.7 – 3.8 ms Caution The listed values do not include the time until the operations of the flash memory start following execution of an instruction by software.

5.11 Dedicated Flash Memory Programmer Communication (UART)

A = -40 to +150°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate – During serial programming 115.2 k 1 M bps

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5.12 Timing of Entry to Flash Memory Programming Modes

(TA = -40 to +150°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Time to complete the communication for the initial setting after the external reset is released t SUINIT POR and LVD reset must be released before the external reset is released. 100 ms Time to release the external reset after the TOOL0 pin is set to the low level tSU POR and LVD reset must be released before the external reset is released. 10 µs Time to hold the TOOL0 pin at the low level after the external reset is released (excluding the processing time of the firmware to control the flash memory) t HD POR and LVD reset must be released before the external reset is released. 1 ms <1> The low level is input to the TOOL0 pin. <2> The external reset is released (POR and LVD reset must be released before the external reset is released.). <3> The TOOL0 pin is set to the high level. <4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting. Remarks 1. tSUINIT: Communication for the initial setting must be comple ted within 100 ms after the external reset is released during this period. 2. t SU: Time to release the external reset after the TOOL0 pin is set to the low level 3. t HD: Time to hold the TOOL0 pin at the low level afte r the external reset is released (excluding the processing time of the firmware to control the flash memory) RESET t SU 1 ms + t HD processing time 00H reception (TOOLRXD, TOOLTXD mode) t SUINIT

RL78/F23, F24 6. PACKAGE DRAWINGS R01DS0446EJ0120 Rev.1.20 Page 198 of 207 Dec 31, 2025 6. PACKAGE DRAWINGS 6.1 32-pin Products There are two types of package drawings. You can check which package drawing used by product marking. Please refer to the product packaging information on Renesas website for more information. INDEX AREA SEATING PLANE ccc C NX bbb C A B ddd C NX b N NX L NX K C aaa C B aaa C (A3) A1A eee C fff C A B fff C A B A N TERMINAL CROSS SECTION DETAIL A0.20 REF. 0.06 REF. 0.05 REF. L DETAIL A N-1 N-1 E D e Reference Symbol Dimension in Millimeters Min. Nom. Max. A －－ 0.80 A1 0.00 － 0.05 A3 0.20 REF. b 0.18 0.25 0.30 D － 5.00 － E － 5.00 － e － 0.50 － N3 2 L 0.35 0.40 0.45 K 0.20 －－ D2 3.15 3.20 3.25 E2 3.15 3.20 3.25 aaa －－ 0.15 bbb －－ 0.10 ccc －－ 0.10 ddd －－ 0.05 eee －－ 0.08 fff －－ 0.10 P-HWQFN032-5x5-0.50 PWQN0032KF-B 0.06 <R>

RL78/F23, F24 6. PACKAGE DRAWINGS R01DS0446EJ0120 Rev.1.20 Page 199 of 207 Dec 31, 2025 INDEX AREA K S B y S A TERMINAL CROSS SECTION F-F' 0.10 REF. 0.05 REF. D E C 1724 A Lpeb C Ｆ’F Reference Symbol D i m e n s i o ni nM i l l i m e t e r s Min. Nom. Max. D 4 . 8 55 . 0 05 . 1 5 E 4 . 8 55 . 0 05 . 1 5 A －－ 0.80 A 1 0.00 － 0.05 b 0.18 0.25 0.30 e 0.50 BSC Lp 0.35 0.40 0.45 y －－ 0.08 c － 0.20 － K0 . 2 0 －－ D2 － 3.20 － E2 － 3.20 － P-HWQFN32-5x5-0.50 PWQN0032KH-A 0.06 <R>

RL78/F23, F24 6. PACKAGE DRAWINGS R01DS0446EJ0120 Rev.1.20 Page 200 of 207 Dec 31, 2025 6.2 48-pin Products There are two types of package drawings. You can check which package drawing used by product marking. Please refer to the product packaging information on Renesas website for more information.

RL78/F23, F24 6. PACKAGE DRAWINGS R01DS0446EJ0120 Rev.1.20 Page 201 of 207 Dec 31, 2025

RL78/F23, F24 6. PACKAGE DRAWINGS R01DS0446EJ0120 Rev.1.20 Page 202 of 207 Dec 31, 2025 6.3 64-pin Products There are two types of package drawings. You can check which package drawing used by product marking. Please refer to the product packaging information on Renesas website for more information. P-LFQFP64-10x10-0.50 PLQP0064KF-A P64GB-50-UEU-2 0.35 Sy e Sxb M L c Lp HD HE ZD ZE A D E S 0.145 +0.055 −0.045 (UNIT:mm) ITEM DIMENSIONS D E HD HE A 10.00±0.20 10.00±0.20 12.00±0.20 12.00±0.20 1.60 MAX. 0.10±0.05 1.40±0.05 0.25 c e x y ZD ZE 0.50 0.08 0.08 1.25 1.25 L Lp 0.50 0.60±0.15 1.00±0.20 3° +5° −3° NOTE Each lead centerline is located within 0.08 mm of its true position at maximum material condition. detail of lead end 0.22±0.05b 64 17

RL78/F23, F24 6. PACKAGE DRAWINGS R01DS0446EJ0120 Rev.1.20 Page 203 of 207 Dec 31, 2025

RL78/F23, F24 6. PACKAGE DRAWINGS R01DS0446EJ0120 Rev.1.20 Page 204 of 207 Dec 31, 2025 6.4 80-pin Products There are two types of package drawings. You can check which package drawing used by product marking. Please refer to the product packaging information on Renesas website for more information.

RL78/F23, F24 6. PACKAGE DRAWINGS R01DS0446EJ0120 Rev.1.20 Page 205 of 207 Dec 31, 2025

RL78/F23, F24 6. PACKAGE DRAWINGS R01DS0446EJ0120 Rev.1.20 Page 206 of 207 Dec 31, 2025 6.5 100-pin Products There are two types of package drawings. You can check which package drawing used by product marking. Please refer to the product packaging information on Renesas website for more information.

RL78/F23, F24 6. PACKAGE DRAWINGS R01DS0446EJ0120 Rev.1.20 Page 207 of 207 Dec 31, 2025

R01DS0446EJ0120 Rev.1.20 (A −1) Dec 31, 2025 REVISION HISTORY RL78/F23, F24 Datasheet Rev Date Description Page Summary 1.10 Jun 30, 2024 ‒ First edition issued. 1.20 Dec 31, 2025 2 Modification of Table 1-1. RL78/F23, F24 Lineup (Grade-3) 2 Modification of Table 1-2. RL78/F23, F24 Lineup (Grade-4) 2 Modification of Table 1-3. RL78/F23, F24 Lineup (Grade-5) 16 Modification of Figure 1-10. RL78/F24 Pin Configuration for 100-pin Products 17 Modification of Figure 1-11. RL78/F24 Pin Configuration for 80-pin Products 18 Modification of Figure 1-12. RL78/F23 Pin Configuration for 80-pin Products 19 Modification of Figure 1-13. RL78/F24 Pin Configuration for 64-pin Products 20 Modification of Figure 1-14. RL78/F23 Pin Configuration for 64-pin Products 21 Modification of Figure 1-15. RL78/F24 Pin Configuration for 48-pin Products 22 Modification of Figure 1-16. RL78/F23 Pin Configuration for 48-pin Products 23 Modification of Figure 1-17. RL78/F24 Pin Configuration for 32-pin Products 24 Modification of Figure 1-18. RL78/F23 Pin Configuration for 32-pin Products

65 Modification of Note 5 in (2) During communication at same potential (CSI mode)

(master mode, SCKp … internal clock output, normal slew rate)

66 Modification of Note 5 in (3) During communication at same potential (CSI mode)

(master mode, SCKp … internal clock output, special slew rate)

76 Modification of Note 3 in (9) During comm unication at different potential (3-V supply

system) (CSI mode) (master mode, SCKp … internal clock output, normal slew rate) 82 Modification of 3.5.2 Serial Interface IICA

118 Modification of Note 5 in (2) During communication at same potential (CSI mode)

(master mode, SCKp … internal clock output, normal slew rate)

119 Modification of Note 5 in (3) During communication at same potential (CSI mode)

(master mode, SCKp … internal clock output, special slew rate)

129 Modification of Note 3 in (9) During comm unication at different potential (3-V supply

system) (CSI mode) (master mode, SCKp … internal clock output, normal slew rate) 135 Modification of 4.5.2 Serial Interface IICA

170 Modification of Note 5 in (2) During communication at same potential (CSI mode)

(master mode, SCKp … internal clock output, normal slew rate)

171 Modification of Note 5 in (3) During communication at same potential (CSI mode)

(master mode, SCKp … internal clock output, special slew rate)

181 Modification of Note 3 in (9) During comm unication at different potential (3-V supply

system) (CSI mode) (master mode, SCKp … internal clock output, normal slew rate) 187 Modification of 5.5.2 Serial Interface IICA 198 Modification of 6.1 32-pin Products 199 Addition of Figure PWQN0032K H-A in 6.1 32-pin Products All trademarks and registered trademarks are the property of their respective owners. SuperFlash is a registered trademark of S ilicon Storage Technology, Inc. in severa l countries including the United States and Japan. Caution: This product uses SuperFlash ® technology licensed from Silicon Storage Technology, Inc.

General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1. Precaution against Electrostatic Discharge (ESD) A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices. 2. Processing at power-on The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the level at which resetting is specified. 3. Input of signal during power-off state Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Follow the guideline for input signal during power-off state as described in your product documentation. 4. Handling of unused pins Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. 5. Clock signals After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or f rom an external oscillator during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable. 6. Voltage application waveform at input pin Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between V IL (Max.) and VIH (Min.). 7. Prohibition of access to reserved addresses Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these addresses as the correct operation of the LSI is not guaranteed. 8. Differences between products Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, im plement a system- evaluation test for the given product.

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Product Information

R7F123FMG4AFB-C specifications and overview.

Summary

RENESAS MCU Rev.1.20 Dec 31, 2025

Description

RENESAS MCU Rev.1.20 Dec 31, 2025

Source title R7F123FMG4AFB-C Datasheet(PDF) - Renesas Technology Corp

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