Microcontroller

R7F102GAE2DSP

Renesas Technology Corp

RENESAS MCU Rev.1.20 Jun 30, 2026

Manufacturer: Renesas Technology Corp

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RL78-G22 RENESAS | Alldatasheet

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R01DS0424EJ0120 Rev.1.20 Page 1 of 121 Jun 30, 2026 RL78/G22 RENESAS MCU True low-power platform, 37.5-µA/MHz operating current, 200-nA stop current, 32-/64-KB code flash memory and 4-KB RAM, up to 29 capacitive touch sensors, from 16 to 48 pins, 1.6 to 5.5 V Datasheet 1. Outline

1.1 Features

Ultra-low power consumption technology

Operation from a single power supply (VDD) within the 1.6-V to 5.5-V range
H A L T m o d e
STOP mode High-speed wakeup from the STOP mode is possible.
SNOOZE mode RL78 CPU core
CISC architecture with 3-stage pipeline
The minimum instruction execution time can be changed from high to ultra-low speed. – High speed: 0.03125 µs at 32-MHz operation with the high-speed on-chip oscillator clock – Ultra-low speed: 30.5 µs at 32.768-kHz operation with the subsystem clock
Multiply/divide/multiply & accumulate instructions are supported.
Address space: 1 MB
General-purpose registers: (8-bit register × 8) × 4 banks
On-chip RAM: 4 KB Code flash memory
Code flash memory: 32 or 64 KB
Block size: 2 KB
Security function: Prohibition of block erase and rewriting
On-chip debugging
Self-programming with boot swapping and flash shield window Data flash memory
Data flash memory: 2 KB
Background operation (BGO): Instructions can be executed from the program memory while rewriting the data flash memory.
Number of rewrites: 1,000,000 times (typ.) High-speed on-chip oscillator
Selectable from among 32 MHz, 24 MHz, 16 MHz,

12 MHz, 8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz,

High accuracy: ±1.0% DD = 1.8 to 5.5 V, TA = -20 to +85°C) Middle-speed on-chip oscillator
Selectable from among 4 MHz, 2 MHz, and 1 MHz with adjustability Low-speed on-chip oscillator
32.768 kHz (typ.) with adjustability Operating ambient temperature A = -40 to +85°C (2D: Consumer applications)
TA = -40 to +105°C (3C: Industrial applications) Power management and reset function
Power-on-reset circuit (POR)
Voltage detectors (LVD0 and LVD1) Data transfer controller (DTC)
Transfer modes: Normal transfer mode, repeat transfer mode, block transfer mode
Activation sources: Activated by interrupt sources.
Chain transfer function SNOOZE mode sequencer (SMS)
Calculations and comparison of values by the commands for use in processing by the sequencer can realize intermittent operations where the RL78/G22 does not have to return to normal operation.
Sequentially handling a total of 32 processes with the use of desired commands from among 21 different ones
The SNOOZE mode sequencer offers operation with low power consumption without using the CPU, flash memory, and RAM. R01DS0424EJ0120 Rev.1.20 Jun 30, 2026

RL78/G22 1. Outline R01DS0424EJ0120 Rev.1.20 Page 2 of 121 Jun 30, 2026 Event link controller (ELC)

20 event signals can be set up between specified peripheral functions. Serial interface
Simplified SPI (CSINote): 1 to 5 channels
UART/UART (LIN-bus supported)/UARTA: 1 to 4 channels
I2C/Simplified I2C: 2 to 6 channels Timers
16-bit timer: 8 channels
32-bit interval timer: 1 channel in 32-bit counter mode 2 channels in 16-bit counter mode 4 channels in 8-bit counter mode
Realtime clock: 1 channel (counting of one second to 99 years, alarm interrupt, and clock correction)
Watchdog timer: 1 channel (operates with the low-speed on-chip oscillator clock) A/D converter
8-/10-bit resolution
Analog input: 3 to 10 channels
Internal reference voltage (1.48 V (typ.)) and temperature sensor Capacitive sensing unit
Operating voltage: V DD = 1.8 to 5.5 V
Self-capacitance method: A single pin configures a single key, supporting up to 29 keys
Mutual capacitance method: Pins for transmission and reception can be selected from among up to 29 pins to create a matrix configuration for the keys. Input/output port pins
Number of port pins: 12 to 44 N-ch open-drain I/O pins (withstand voltage of

6 V): 0 to 4

N-ch open-drain I/O pins (withstand voltage of V DD): 4 to 13

Can be set to N-ch open drain or TTL input buffer, and use of an on-chip pull-up resistor can be specified.
Connectable to a device with different voltage (1.8, 2.5, or 3 V) Others
Binary-coded decimal (BCD) correction circuit
Key interrupt input
Clock output/buzzer output controller Note Although the CSI function is generally called SPI, it is also called CSI in this product, so it is referred to as such in this manual. Remark The functions mounted depend on the product. For details, see 1.6 Outline of Functions.

RL78/G22 1. Outline R01DS0424EJ0120 Rev.1.20 Page 3 of 121 Jun 30, 2026 Ο ROM, RAM capacities Code flash memory Data flash memory RAM RL78/G22 16 pins 20 pins 24 pins 25 pins 30 pins

64 KB 2 KB 4 KB R7F102G4E R7F102G6E R7F102G7E R7F102G8E R7F102GAE

32 KB 2 KB 4 KB R7F102G4C R7F102G6C R7F102G7C R7F102G8C R7F102GAC

32 pins 36 pins 40 pins 44 pins 48 pins

64 KB 2 KB 4 KB R7F102GBE R7F102GCE R7F102GEE R7F102GFE R7F102GGE

32 KB 2 KB 4 KB R7F102GBC R7F102GCC R7F102GEC R7F102GFC R7F102GGC

RL78/G22 1. Outline R01DS0424EJ0120 Rev.1.20 Page 4 of 121 Jun 30, 2026

1.2 List of Part Numbers

Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G22 F: Flash memory RL78/G22 ROM capacity Package type Renesas MCU Renesas semiconductor product Pin count Ambient operating temperature range Device type Packaging specification SP: LSSOP, 0.65-mm pitch FP: LQFP, 0.80-mm pitch FB: LFQFP, 0.50-mm pitch NP: HWQFN, 0.50-mm pitch LA: WFLGA, 0.50-mm pitch ROM number (omitted with blank products) 2: -40 to +85°C 3: -40 to +105°C C: 32 KB E: 64 KB 4: 16 pins 6: 20 pins 7: 24 pins 8: 25 pins A: 30 pins B: 32 pins C: 36 pins E: 40 pins F: 44 pins G: 48 pins Fields of application C: Industrial applications D: Consumer applications #AA0, #BA0, #UA0: Tray (LFQFP, LQFP, LSSOP30, HWQFN) #AC0, #BC0, #UC0: Tray (WFLGA) #CA0: Magazine (LSSOP20) #HA0: Embossed tape (LFQFP, LQFP, LSSOP20, LSSOP30, HWQFN) #HC0: Embossed tape (WFLGA) R 7 F 1 0 2 G G E 3 x x x C F B # AA0 Product name Ordering part number

RL78/G22 1. Outline R01DS0424EJ0120 Rev.1.20 Page 5 of 121 Jun 30, 2026 Note For the fields of application, see Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G22. Table 1 - 1 List of Ordering Part Numbers Pin Count Package Fields of Application Note Ordering Part Number Renesas Code Product Name Packaging Specification 16 16-pin plastic HWQFN (3 × 3 mm, 0.50-mm pitch) C R7F102G4C3CNP, R7F102G4E3CNP #AA0, #BA0, #UA0, #HA0 PWQN0016KD-A D R7F102G4C2DNP, R7F102G4E2DNP 20 20-pin plastic LSSOP (4.4 × 6.5 mm, 0.65-mm pitch) C R7F102G6C3CSP, R7F102G6E3CSP #CA0, #HA0 PLSP0020JB-A D R7F102G6C2DSP, R7F102G6E2DSP 24 24-pin plastic HWQFN (4 × 4 mm, 0.5 mm pitch) C R7F102G7C3CNP, R7F102G7E3CNP #AA0, #BA0, #UA0, #HA0 PWQN0024KG-A D R7F102G7C2DNP, R7F102G7E2DNP 25 25-pin plastic WFLGA (3 × 3 mm, 0.5 mm pitch) C R7F102G8C3CLA, R7F102G8E3CLA #AC0, #BC0, #UC0, #HC0 PWLG0025KB-A D R7F102G8C2DLA, R7F102G8E2DLA 30 30-pin plastic LSSOP (7.62 mm (300), 0.65-mm pitch) C R7F102GAC3CSP , R7F102GAE3CSP #AA0, #BA0, #UA0, #HA0 PLSP0030JB-B D R7F102GAC2DSP , R7F102GAE2DSP 32 32-pin plastic HWQFN (5 × 5 mm, 0.50-mm pitch) C R7F102GBC3CNP, R7F102GBE3CNP #AA0, #BA0, #UA0, #HA0 PWQN0032KE-A D R7F102GBC2DNP, R7F102GBE2DNP 32-pin plastic LQFP (7 × 7 mm, 0.80-mm pitch) C R7F102GBC3CFP, R7F102GBE3CFP #AA0, #BA0, #UA0, #HA0 PLQP0032GB-A, PLQP0032GE-A D R7F102GBC2DFP, R7F102GBE2DFP 36 36-pin plastic WFLGA (4 × 4 mm, 0.50-mm pitch) C R7F102GCC3CLA, R7F102GCE3CLA #BC0, #AC0, #UC0, #HC0 PWLG0036KB-A D R7F102GCC2DLA, R7F102GCE2DLA 40 40-pin plastic HWQFN (6 × 6 mm, 0.50-mm pitch) C R7F102GEC3CNP, R7F102GEE3CNP #AA0, #BA0, #UA0, #HA0 PWQN0040KD-A D R7F102GEC2DNP, R7F102GEE2DNP 44 44-pin plastic LQFP (10 × 10 mm, 0.80-mm pitch) C R7F102GFC3CFP , R7F102GFE3CFP #AA0, #BA0, #UA0, #HA0 PLQP0044GC-A, PLQP0044GE-A D R7F102GFC2DFP , R7F102GFE2DFP 48 48-pin plastic LFQFP (7 × 7 mm, 0.50-mm pitch) C R7F102GGC3CFB, R7F102GGE3CFB #AA0, #BA0, #UA0, #HA0 PLQP0048KB-B, PLQP0048KL-A D R7F102GGC2DFB, R7F102GGE2DFB 48-pin plastic HWQFN (7 × 7 mm, 0.50-mm pitch) C R7F102GGC3CNP , R7F102GGE3CNP #AA0, #BA0, #UA0, #HA0 PWQN0048KC-A D R7F102GGC2DNP , R7F102GGE2DNP

RL78/G22 1. Outline R01DS0424EJ0120 Rev.1.20 Page 6 of 121 Jun 30, 2026

1.3 Pin Configuration (Top View)

1.3.1 16-pin products

16-pin plastic HWQFN (3 × 3 mm, 0.5-mm pitch) Caution Connect the REGC pin to V SS via a capacitor (0.47 to 1 µF). Remark For pin identification, see 1.4 Pin Identification. RL78/G22 (Top View) P10/SCK00/SCL00/TS11 P11/SI00/RxD0/TOOLRxD/SDA00/TS12 P12/SO00/TxD0/TOOLTxD/TS13

9 P17/TI02/TO02/TS18/SDA11

8 P30/INTP3/TSCAP/RTC1HZ/SCL11

7 RESET

6 P137/INTP015P20/ANI0/AVREFP

RL78/G22 1. Outline R01DS0424EJ0120 Rev.1.20 Page 7 of 121 Jun 30, 2026 Table 1 - 2 Multiplexed Pin Functions of the 16-pin Products Pin Number I/O Power supply, system clock, and debugging Analog Circuit HMI Timers Communications Interfaces 16HWQFN Digital port A/D converter (ADC) Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA)

1 P122 X2/XT2/EXCLK/

4— V 7 — RESET

8 P30 — — INTP3 — TSCAP — RTC1HZ SCL11 — —

9 P17 — — — — TS18 TI02/TO02 — SDA11 — —

10 P12 TOOLTxD — — — TS13 — — SO00/

11 P11 TOOLRxD — — — TS12 — — SI00/RxD0/

1 2 P 1 0 — ———T S 1 1 ——S C K 0 0 / SCL00

14 P21 — ANI1/

15 P20 — ANI0/

RL78/G22 1. Outline R01DS0424EJ0120 Rev.1.20 Page 8 of 121 Jun 30, 2026 1.3.2 20-pin products

20-pin plastic LSSOP (4.4 × 6.5 mm, 0.65-mm pitch) Caution Connect the REGC pin to V SS via a capacitor (0.47 to 1 µF). Remark For pin identification, see 1.4 Pin Identification. RL78/G22 (Top View)

20 P20/ANI0/AV REFP

19 P21/ANI1/AVREFM

18 P22/ANI2/TS20

17 P147/ANI18/TS10

16 P10/SCK00/SCL00/TS11

15 P11/SI00/RxD0/TOOLRxD/SDA00/TS12

14 P12/SO00/TxD0/TOOLTxD/TS13

13 P16/TI01/TO01/INTP5/TS17/SO11

12 P17/TI02/TO02/TS18/SI11/SDA11

11 P30/INTP3/TSCAP/RTC1HZ/SCL11/SCK11

RL78/G22 1. Outline R01DS0424EJ0120 Rev.1.20 Page 9 of 121 Jun 30, 2026 Table 1 - 3 Multiplexed Pin Functions of the 20-pin Products Pin Number I/O Power supply, system clock, and debugging Analog Circuit HMI Timers Communications Interfaces 20LSSOP Digital port A/D converter (ADC) Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA)

1 P01 — ANI16 — — TS27 TO00 — RxD1 — —

2 P00 — ANI17 — — TS26 TI00 — TxD1 — —

6 P122 X2/XT2/EXCLK/

9— V

11 P30 — — INTP3 — TSCAP — RTC1HZ SCK11/

12 P17 — — — — TS18 TI02/TO02 — SI11/

13 P16 — — INTP5 — TS17 TI01/TO01 — SO11 — —

14 P12 TOOLTxD — — — TS13 — — SO00/

15 P11 TOOLRxD — — — TS12 — — SI00/RxD0/

1 6 P 1 0 — ———T S 1 1 ——S C K 0 0 / SCL00

19 P21 — ANI1/

20 P20 — ANI0/

RL78/G22 1. Outline R01DS0424EJ0120 Rev.1.20 Page 10 of 121 Jun 30, 2026 1.3.3 24-pin products

24-pin plastic HWQFN (4 × 4 mm, 0.50-mm pitch) Caution Connect the REGC pin to V SS via a capacitor (0.47 to 1 µF). Remark For pin identification, see 1.4 Pin Identification. RL78/G22 (Top View) 19P21/ANI1/AVREFM P20/ANI0/AVREFP 20 21P01/TS27/TO00/RxD1/ANI16 P00/TS26/TI00/TxD1/ANI17 22 23P40/TOOL0 24RESET P22/ANI2/TS20 P147/ANI18/TS10 17 16 P10/SCK00/SCL00/TS11 P11/SI00/RxD0/TOOLRxD/SDA00/TS12 15 14 P12/SO00/TxD0/TOOLTxD/TS13 P16/TI01/TO01/INTP5/TS17

12 P17/TI02/TO02/TS18/SO11

P50/TS00/INTP1/SI11/SDA1111

10 P30/INTP3/TSCAP/RTC1HZ/SCL11/SCK11

P31/TI03/TO03/INTP4/TS01/PCLBUZ09 8P 6 1 / S D A A 0 7P 6 0 / S C L A 0 1P137/INTP0 P122/X2/EXCLK/XT2/EXCLKS P121/X1/XT1 4REGC VSS VDD Exposed die pad INDEX MARK

RL78/G22 1. Outline R01DS0424EJ0120 Rev.1.20 Page 11 of 121 Jun 30, 2026 Table 1 - 4 Multiplexed Pin Functions of the 24-pin Products Pin Number I/O Power supply, system clock, and debugging Analog Circuit HMI Timers Communications Interfaces 24HWQFN Digital port A/D converter (ADC) Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA)

2 P122 X2/XT2/EXCLK/

9 P31 PCLBUZ0 — INTP4 — TS01 TI03/TO03 — — — —

10 P30 — — INTP3 — TSCAP — RTC1HZ SCK11/

11 P50 — — INTP1 — TS00 — — SI11/

12 P17 — — — — TS18 TI02/TO02 — SO11 — —

1 3 P 1 6 — —I N T P 5 —T S 1 7 T I 0 1 / T O 0 1 ———— 1 6 P 1 0 — ———T S 1 1 ——S C K 0 0 / SCL00

21 P01 — ANI16 — — TS27 TO00 — RxD1 — —

22 P00 — ANI17 — — TS26 TI00 — TxD1 — —

24 — RESET

RL78/G22 1. Outline R01DS0424EJ0120 Rev.1.20 Page 12 of 121 Jun 30, 2026 1.3.4 25-pin products

25-pin plastic WFLGA (3 × 3 mm, 0.50-mm pitch) Caution Connect the REGC pin to V SS via a capacitor (0.47 to 1 µF). Remark For pin identification, see 1.4 Pin Identification. ABC D E

5 P40/TOOL0 RESET P01/TS27/TO00/RxD1/

P22/ANI2/TS20 P147/ANI18/TS10 5

4 P122/X2/EXCLK/XT2/

P137/INTP0 P00/TS26/TI00/TxD1/ ANI17 P21/ANI1/AVREFM P10/SCK00/SCL00/TS11 4

3 P121/X1/XT1 V DD P20/ANI0/AVREFP P12/SO00/TxD0/

1 P60/SCLA0 P61/SDAA0 P31/TI03/TO03/INTP4/

(Top View) INDEX MARK ABCDE EDCBA INDEX MARK Top View Bottom View

RL78/G22 1. Outline R01DS0424EJ0120 Rev.1.20 Page 13 of 121 Jun 30, 2026 Table 1 - 5 Multiplexed Pin Functions of the 25-pin Products Pin Number I/O Power supply, system clock, and debugging Analog Circuit HMI Timers Communications Interfaces 25WFLGA Digital port A/D converter (ADC) Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) A4 P122 X2/XT2/EXCLK/ EXCLKS C1 P31 PCLBUZ0 — INTP4 — TS01 TI03/TO03 — — — — C2 P30 — — INTP3 — TSCAP — RTC1HZ SCK11/ SCL11 C3 P20 — ANI0/ AV REFP C4 P00 — ANI17 — — TS26 TI00 — TxD1 — — C5 P01 — ANI16 — — TS27 TO00 — RxD1 — — D 1 P 1 6 — —I N T P 5 —T S 1 7 T I 0 1 / T O 0 1 ———— D 2 P 1 7 — ———T S 1 8 T I 0 2 / T O 0 2 —S O 1 1 —— D3 P12 TOOLTxD — — — TS13 — — SO00/ TxD0 D4 P21 — ANI1/ AV REFM E2 P50 — — INTP1 — TS00 — — SI11/ SDA11 E3 P11 TOOLRxD — — — TS12 — — SI00/RxD0/ SDA00 E4 P10 — — — — TS11 — — SCK00/ SCL00

RL78/G22 1. Outline R01DS0424EJ0120 Rev.1.20 Page 14 of 121 Jun 30, 2026 1.3.5 30-pin products

30-pin plastic LSSOP (7.62 mm (300), 0.65-mm pitch) Caution Connect the REGC pin to V SS via a capacitor (0.47 to 1 µF). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). For details, see 4.3.9 Peripheral I/O redirection register (PIOR) in the RL78/G22 User’s Manual. RL78/G22 (Top View) 2P01/TS27/TO00/RxD1/ANI16 3P00/TS26/TI00/TxD1/ANI17 4P120/ANI19 5P40/TOOL0 6RESET 7P137/INTP0 8P122/X2/EXCLK/XT2/EXCLKS 9P121/X1/XT1 REGC 10 VSS 11 VDD 12 P60/SCLA0 13 14P61/SDAA0 15P31/TI03/TO03/INTP4/TS01/PCLBUZ0

29 P22/ANI2/TS20

28 P23/ANI3/TS21

27 P147/ANI18/TS10

26 P10/SCK00/SCL00/TS11/(TI07)/(TO07)

25 P11/SI00/RxD0/TOOLRxD/SDA00/TS12/(TI06)/(TO06)

24 P12/SO00/TxD0/TOOLTxD/TS13/(TI05)/(TO05)

23 P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04)/TS14

22 P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03)/TS15

21 P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02)/TS16

P16/TI01/TO01/INTP5/TS17/(RxD0)20 P17/TI02/TO02/TS18/(TxD0)19 P51/TS28/INTP2/SO1118 P50/TS00/INTP1/SI11/SDA1117 P30/INTP3/TSCAP/RTC1HZ/SCL11/SCK1116 1P20/ANI0/AVREFP 30 P21/ANI1/AV REFM

RL78/G22 1. Outline R01DS0424EJ0120 Rev.1.20 Page 15 of 121 Jun 30, 2026 Table 1 - 6 Multiplexed Pin Functions of the 30-pin Products Pin Number I/O Power supply, system clock, and debugging Analog Circuit HMI Timers Communications Interfaces 30LSSOP Digital port A/D converter (ADC) Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA)

1 P20 — ANI0/

2 P01 — ANI16 — — TS27 TO00 — RxD1 — —

3 P00 — ANI17 — — TS26 TI00 — TxD1 — —

6 — RESET

8 P122 X2/XT2/EXCLK/

11 — V

15 P31 PCLBUZ0 — INTP4 — TS01 TI03/TO03 — —

16 P30 — — INTP3 — TSCAP — RTC1HZ SCK11/

17 P50 — — INTP1 — TS00 — — SI11/

18 P51 — — INTP2 — TS28 — — SO11 — —

19 P17 — — — TS18 TI02/TO02 — (TxD0) — —

20 P16 — — INTP5 — TS17 TI01/TO01 — (RxD0) — —

21 P15 PCLBUZ1 — — — TS16 (TI02)/

(TO02) — SCK20/ SCL20 (TO03) — SI20/RxD2/ SDA20 (SCLA0) — (TO04) — SO20/ TxD2 (SDAA0) —

24 P12 TOOLTxD — — — TS13 (TI05)/

(TO05) — SO00/ TxD0

25 P11 TOOLRxD — — — TS12 (TI06)/

(TO06) — SI00/RxD0/ SDA00 (TO07) — SCK00/ SCL00

30 P21 — ANI1/

RL78/G22 1. Outline R01DS0424EJ0120 Rev.1.20 Page 16 of 121 Jun 30, 2026 1.3.6 32-pin products

32-pin plastic HWQFN (5 × 5 mm, 0.50-mm pitch)
32-pin plastic LQFP (7 × 7 mm, 0.80-mm pitch) Note The 32-pin plastic LQFP (7 × 7 mm, 0.80-mm pitch) products do not have an exposed die pad. Caution Connect the REGC pin to V SS via a capacitor (0.47 to 1 µF). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). For details, see 4.3.9 Peripheral I/O redirection register (PIOR) in the RL78/G22 User’s Manual. Remark 3. It is recommended to connect an exposed die pad to VSS. RL78/G22 (Top View) P10/SCK00/SCL00/TS11/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/TS12/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/TS13/(TI05)/(TO05) 22 21 P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04)/TS14 P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03)/TS15 20 19 P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02)/TS16 P16/TI01/TO01/INTP5/TS17/(RxD0) 18 17 P17/TI02/TO02/TS18/(TxD0)

9 P60/SCLA0

10 P61/SDAA0

P31/TI03/TO03/INTP4/TS01/PCLBUZ012

13 P70/TS02

P30/INTP3/TSCAP/RTC1HZ/SCL11/SCK1114 P50/TS00/INTP1/SI11/SDA1115

16 P51/TS28/INTP2/SO1125P147/ANI18/TS10

P01/TS27/TO00/RxD1/ANI16 30 31P00/TS26/TI00/TxD1/ANI17 32P120/ANI19 P137/INTP0 P122/X2/EXCLK/XT2/EXCLKS 5P121/X1/XT1 REGC VSS VDDINDEX MARK 1P40/TOOL0 2RESET Exposed die pad Note

RL78/G22 1. Outline R01DS0424EJ0120 Rev.1.20 Page 17 of 121 Jun 30, 2026 Table 1 - 7 Multiplexed Pin Functions of the 32-pin Products Pin Number I/O Power supply, system clock, and debugging Analog Circuit HMI Timers Communications Interfaces 32HWQFN 32LQFP Digital port A/D converter (ADC) Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA)

4 P122 X2/XT2/EXCLK/

7— V

12 P31 PCLBUZ0 — INTP4 — TS01 TI03/TO03 — — — —

14 P30 — — INTP3 — TSCAP — RTC1HZ SCK11/

15 P50 — — INTP1 — TS00 — — SI11/

16 P51 — — INTP2 — TS28 — — SO11 — —

17 P17 — — — TS18 TI02/TO02 — (TxD0) — —

18 P16 — — INTP5 — TS17 TI01/TO01 — (RxD0) — —

19 P15 PCLBUZ1 — — — TS16 (TI02)/

(TO02) — SCK20/ SCL20 (TO03) — SI20/RxD2/ SDA20 (SCLA0) — (TO04) — SO20/ TxD2 (SDAA0) —

22 P12 TOOLTxD — — — TS13 (TI05)/

(TO05) — SO00/ TxD0

23 P11 TOOLRxD — — — TS12 (TI06)/

(TO06) — SI00/RxD0/ SDA00 (TO07) — SCK00/ SCL00

28 P21 — ANI1/

29 P20 — ANI0/

30 P01 — ANI16 — — TS27 TO00 — RxD1 — —

31 P00 — ANI17 — — TS26 TI00 — TxD1 — —

RL78/G22 1. Outline R01DS0424EJ0120 Rev.1.20 Page 18 of 121 Jun 30, 2026 1.3.7 36-pin products

36-pin plastic WFLGA (4 × 4 mm, 0.50-mm pitch) Caution Connect the REGC pin to V SS via a capacitor (0.47 to 1 µF). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). For details, see 4.3.9 Peripheral I/O redirection register (PIOR) in the RL78/G22 User’s Manual. ABCDEF

6 P60/SCLA0 V DD P121/X1/XT1 P122/X2/EXCLK/

5 P62 P61/SDAA0 V SS REGC RESET P120/ANI19

4 P72/TS04/SO21/

SDA20/(SCLA0)/ (TI03)/(TO03)/TS15 P31/TI03/TO03/ INTP4/TS01/ PCLBUZ0 P00/TS26/TI00/ TxD1 P01/TS27/TO00/ RxD1

3 P50/TS00/INTP1/

(TI02)/(TO02)/TS16 P22/ANI2/TS20 P20/ANI0/AV REFP P21/ANI1/AVREFM

2 P30/INTP3/TSCAP/

INTP5/TS17/(RxD0) P12/SO00/TxD0/ TOOLTxD/TS13/ (TI05)/(TO05) P11/SI00/RxD0/ TOOLRxD/SDA00/ TS12/(TI06)/(TO06) P24/ANI4/TS22 P23/ANI3/TS21

1 P51/TS28/INTP2/

TS18/(TxD0) P13/TxD2/SO20/ (SDAA0)/(TI04)/ (TO04)/TS14 P10/SCK00/SCL00/ TS11/(TI07)/(TO07) P147/ANI18/TS10 P25/ANI5/TS23 RL78/G22 (Top View) Top View Bottom View FEDCBAABCDEF INDEX MARK

RL78/G22 1. Outline R01DS0424EJ0120 Rev.1.20 Page 19 of 121 Jun 30, 2026 Table 1 - 8 Multiplexed Pin Functions of the 36-pin Products (1/2) Pin Number I/O Power supply, system clock, and debugging Analog Circuit HMI Timers Communications Interfaces 36WFLGA Digital port A/D converter (ADC) Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) A1 P51 — — INTP2 — TS28 — — SO11 — — A2 P30 — — INTP3 — TSCAP — RTC1HZ SCK11/ SCL11 A3 P50 — — INTP1 — TS00 — — SI11/ SDA11 A4 P72 — — — — TS04 — — SO21 — TxDA0 B1 P17 — — — — TS18 TI02/TO02 — (TxD0) — — B2 P16 — — INTP5 — TS17 TI01/TO01 — (RxD0) — — B3 P70 — — — — TS02 — — SCK21/ SCL21 SDA21 —R xDA0 C 1 P 1 3 — ———T S 1 4 ( T I 0 4 ) / (TO04) — SO20/ TxD2 (SDAA0) — C2 P12 TOOLTxD — — — TS13 (TI05)/ (TO05) — SO00/ TxD0 C3 P15 PCLBUZ1 — — — TS16 (TI02)/ (TO02) — SCK20/ SCL20 C 4 P 1 4 — ———T S 1 5 ( T I 0 3 ) / (TO03) — SI20/RxD2/ SDA20 (SCLA0) — D 1 P 1 0 — ———T S 1 1 ( T I 0 7 ) / (TO07) — SCK00/ SCL00 D2 P11 TOOLRxD — — — TS12 (TI06)/ (TO06) — SI00/RxD0/ SDA00 D4 P31 PCLBUZ0 — INTP4 TS01 TI03/TO03 — — — — D6 P122 X2/XT2/EXCLK/ EXCLKS E3 P20 — ANI0/ AV REFP E4 P00 — — — — TS26 TI00 — TxD1 — — E5 — RESET

RL78/G22 1. Outline R01DS0424EJ0120 Rev.1.20 Page 20 of 121 Jun 30, 2026 F3 P21 — ANI1/ AVREFM F 4 P 0 1 — ———T S 2 7 T O 0 0 R x D 1 —— Table 1 - 8 Multiplexed Pin Functions of the 36-pin Products (2/2) Pin Number I/O Power supply, system clock, and debugging Analog Circuit HMI Timers Communications Interfaces 36WFLGA Digital port A/D converter (ADC) Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA)

RL78/G22 1. Outline R01DS0424EJ0120 Rev.1.20 Page 21 of 121 Jun 30, 2026 1.3.8 40-pin products

40-pin plastic HWQFN (6 × 6 mm, 0.50-mm pitch) Caution Connect the REGC pin to V SS via a capacitor (0.47 to 1 µF). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). For details, see 4.3.9 Peripheral I/O redirection register (PIOR) in the RL78/G22 User’s Manual. Remark 3. It is recommended to connect an exposed die pad to VSS. RL78/G22 (Top View) 1P40/TOOL0 2RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 6P122/X2/EXCLK P121/X1/VBAT REGC VSS VDD P147/ANI18/TS10 P10/SCK00/SCL00/TS11/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/TS12/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/TS13/(TI05)/(TO05) 2726 P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04)/TS14 P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03)/TS15 25 24 P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02)/TS16 P16/TI01/TO01/INTP5/TS17/(RxD0) 23 22 P17/TI02/TO02/TS18/(TxD0) P51/TS28/INTP2/SO11 31P26/ANI6/TS24 32P25/ANI5/TS23 33P24/ANI4/TS22 34P23/ANI3/TS21 35P22/ANI2/TS20 P21/ANI1/AVREFM 36 P20/ANI0/AVREFP 37 38P01/TS27/TO00/RxD1 39P00/TS26/TI00/TxD1 40P120/ANI19

20 P50/TS00/INTP1/SI11/SDA11

19 P30/INTP3/TSCAP/RTC1HZ/SCL11/SCK11

P70/KR0/TS02/SCK21/SCL2118 P71/KR1/TS03/SI21/SDA21/RxDA017

16 P72/KR2/TS04/SO21/TxDA0

P31/TI03/TO03/INTP4/TS01/PCLBUZ014

13 P62

12 P61/SDAA0

11 P60/SCLA0

RL78/G22 1. Outline R01DS0424EJ0120 Rev.1.20 Page 22 of 121 Jun 30, 2026 Table 1 - 9 Multiplexed Pin Functions of the 40-pin Products (1/2) Pin Number I/O Power supply, system clock, and debugging Analog Circuit HMI Timers Communications Interfaces 40HWQFN Digital port A/D converter (ADC) Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) 9— V

14 P31 PCLBUZ0 — INTP4 — TS01 TI03/TO03 — — — —

16 P72 — — — KR2 TS04 — — SO21 — TxDA0

17 P71 — — — KR1 TS03 — — SI21/

—R x D A 0

18 P70 — — — KR0 TS02 — — SCK21/

19 P30 — — INTP3 — TSCAP — RTC1HZ SCK11/

20 P50 — — INTP1 — TS00 — — SI11/

21 P51 — — INTP2 — TS28 — — SO11 — —

22 P17 — — — — TS18 TI02/TO02 — (TxD0) — —

23 P16 — — INTP5 — TS17 TI01/TO01 — (RxD0) — —

24 P15 PCLBUZ1 — — — TS16 (TI02)/

(TO02) — SCK20/ SCL20 (TO03) — SI20/RxD2/ SDA20 (SCLA0) — (TO04) — SO20/ TxD2 (SDAA0) —

27 P12 TOOLTxD — — — TS13 (TI05)/

(TO05) — SO00/ TxD0

28 P11 TOOLRxD — — — TS12 (TI06)/

(TO06) — SI00/RxD0/ SDA00 (TO07) — SCK00/ SCL00 <R>

RL78/G22 1. Outline R01DS0424EJ0120 Rev.1.20 Page 23 of 121 Jun 30, 2026

36 P21 — ANI1/

37 P20 — ANI0/

3 8 P 0 1 — ———T S 2 7 T O 0 0 —R x D 1 —— 3 9 P 0 0 — ———T S 2 6 T I 0 0 —T x D 1 —— Table 1 - 9 Multiplexed Pin Functions of the 40-pin Products (2/2) Pin Number I/O Power supply, system clock, and debugging Analog Circuit HMI Timers Communications Interfaces 40HWQFN Digital port A/D converter (ADC) Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA)

RL78/G22 1. Outline R01DS0424EJ0120 Rev.1.20 Page 24 of 121 Jun 30, 2026 1.3.9 44-pin products

44-pin plastic LQFP (10 × 10 mm, 0.80-mm pitch) Caution Connect the REGC pin to V SS via a capacitor (0.47 to 1 µF). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). For details, see 4.3.9 Peripheral I/O redirection register (PIOR) in the RL78/G22 User’s Manual. RL78/G22 (Top View) P147/ANI18/TS10 P146/TS09 P10/SCK00/SCL00/TS11/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/TS12/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/TS13/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04)/TS14 P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03)/TS15 P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02)/TS16 P16/TI01/TO01/INTP5/TS17/(RxD0) P17/TI02/TO02/TS18/(TxD0) P51/TS28/INTP2/SO11 P41/TI07/TO07 1 2P40/TOOL0 3RESET 4P124/XT2/EXCLKS 5P123/XT1 6P137/INTP0 7P122/X2/EXCLK 8P121/X1/VBAT 9REGC VSS VDD 34P27/ANI7/TS25 35P26/ANI6/TS24 36P25/ANI5/TS23 37P24/ANI4/TS22 38P23/ANI3/TS21 39P22/ANI2/TS20 40P21/ANI1/AVREFM 41P20/ANI0/AVREFP 42P01/TS27/TO00/RxD1 43P00/TS26/TI00/TxD1 44P120/ANI19 P50/TS00/INTP1/SI11/SDA1122 P30/INTP3/TSCAP/RTC1HZ/SCL11/SCK1121 P70/KR0/TS02/SCK21/SCL2120 P71/KR1/TS03/SI21/SDA21/RxDA019 P72/KR2/TS04/SO21/TxDA018 P73/KR3/TS0517 P31/TI03/TO03/INTP4/TS01/PCLBUZ016 P6315 P6214 P61/SDAA013 P60/SCLA012

RL78/G22 1. Outline R01DS0424EJ0120 Rev.1.20 Page 25 of 121 Jun 30, 2026 Table 1 - 10 Multiplexed Pin Functions of the 44-pin Products (1/2) Pin Number I/O Power supply, system clock, and debugging Analog Circuit HMI Timers Communications Interfaces 44LQFP Digital port A/D converter (ADC) Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) 10 — V

16 P31 PCLBUZ0 — INTP4 — TS01 TI03/TO03 — — — —

18 P72 — — — KR2 TS04 — — SO21 — TxDA0

19 P71 — — — KR1 TS03 — — SI21/

—R x D A 0

20 P70 — — — KR0 TS02 — — SCK21/

21 P30 — — INTP3 — TSCAP — RTC1HZ SCK11/

22 P50 — — INTP1 — TS00 — — SI11/

23 P51 — — INTP2 — TS28 — — SO11 — —

24 P17 — — — — TS18 TI02/TO02 — (TxD0) — —

25 P16 — — INTP5 — TS17 TI01/TO01 — (RxD0) — —

26 P15 PCLBUZ1 — — — TS16 (TI02)/

(TO02) — SCK20/ SCL20 (TO03) — SI20/RxD2/ SDA20 (SCLA0) — (TO04) — SO20/ TxD2 (SDAA0) —

29 P12 TOOLTxD — — — TS13 (TI05)/

(TO05) — SO00/ TxD0

30 P11 TOOLRxD — — — TS12 (TI06)/

(TO06) — SI00/RxD0/ SDA00 (TO07) — SCK00/ SCL00 <R>

RL78/G22 1. Outline R01DS0424EJ0120 Rev.1.20 Page 26 of 121 Jun 30, 2026

40 P21 — ANI1/

41 P20 — ANI0/

4 2 P 0 1 — ———T S 2 7 T O 0 0 —R x D 1 —— 4 3 P 0 0 — ———T S 2 6 T I 0 0 —T x D 1 —— Table 1 - 10 Multiplexed Pin Functions of the 44-pin Products (2/2) Pin Number I/O Power supply, system clock, and debugging Analog Circuit HMI Timers Communications Interfaces 44LQFP Digital port A/D converter (ADC) Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA)

RL78/G22 1. Outline R01DS0424EJ0120 Rev.1.20 Page 27 of 121 Jun 30, 2026 1.3.10 48-pin products

48-pin plastic LFQFP (7 × 7 mm, 0.50-mm pitch)
48-pin plastic HWQFN (7 × 7 mm, 0.50-mm pitch) Note The 48-pin plastic LFQFP (7 × 7 mm, 0.50-mm pitch) products do not have an exposed die pad. Caution Connect the REGC pin to V SS via a capacitor (0.47 to 1 µF). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). For details, see 4.3.9 Peripheral I/O redirection register (PIOR) in the RL78/G22 User’s Manual. Remark 3. It is recommended to connect an exposed die pad to VSS. RL78/G22 (Top View) P140/PCLBUZ0/INTP6/TS08 P00/TS26/TI00/TxD1 P01/TS27/TO00/RxD1 P20/ANI0/AVREFP P21/ANI1/AVREFM P22/ANI2/TS20 P23/ANI3/TS21 P24/ANI4/TS22 P25/ANI5/TS23 P26/ANI6/TS24 P27/ANI7/TS25 P12/SO00/TxD0/TOOLTxD/TS13/(TI05)/(TO05)20 P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04)/TS1419 P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03)/TS1518 P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02)/TS1617 P16/TI01/TO01/INTP5/TS17/(RxD0)16 P17/TI02/TO02/TS18/(TxD0)15 P51/TS28/INTP2/SO1114 P50/TS00/INTP1/SI11/SDA1113 37P120/ANI19 38P41/TI07/TO07 39P40/TOOL0 40RESET 41P124/XT2/EXCLKS 42P123/XT1 43P137/INTP0 44P122/X2/EXCLK 45P121/X1/VBAT 46REGC 47VSS 48VDD P60/SCLA0 1 2P61/SDAA0 3P62 4P63 5P31/TI03/TO03/INTP4/TS01/(PCLBUZ0) 6P75/KR5/TS07/INTP9/SCK01/SCL01 7P74/KR4/TS06/INTP8/SI01/SDA01 8P73/KR3/TS05/SO01 9P72/KR2/TS04/SO21/TxDA0 P71/KR1/TS03/SI21/SDA21/RxDA0 P70/KR0/TS02/SCK21/SCL21 P30/INTP3/TSCAP/RTC1HZ/SCL11/SCK11 P10/SCK00/SCL00/TS11/(TI07)/(TO07)22 P11/SI00/RxD0/TOOLRxD/SDA00/TS12/(TI06)/(TO06)21 P130/TS19 P147/ANI18/TS1024 P146/TS0923 Exposed die pad Note

RL78/G22 1. Outline R01DS0424EJ0120 Rev.1.20 Page 28 of 121 Jun 30, 2026 Table 1 - 11 Multiplexed Pin Functions of the 48-pin Products (1/2) Pin Number I/O Power supply, system clock, and debugging Analog Circuit HMI Timers Communications Interfaces 48HWQFN 48LFQFP Digital port A/D converter (ADC) Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA)

5 P31 (PCLBUZ0) — INTP4 — TS01 TI03/TO03 — — — —

6 P75 — — INTP9 KR5 TS07 — — SCK01/

7 P74 — — INTP8 KR4 TS06 — — SI01/

9 P 72 — ——K R2 T S04 ——S O21 —T xDA0

10 P71 — — — KR1 TS03 — — SI21/

—R xDA0

11 P70 — — — KR0 TS02 — — SCK21/

12 P30 — — INTP3 — TSCAP — RTC1HZ SCK11/

13 P50 — — INTP1 — TS00 — — SI11/

14 P51 — — INTP2 — TS28 — — SO11 — —

15 P17 — — — — TS18 TI02/TO02 — (TxD0) — —

16 P16 — — INTP5 — TS17 TI01/TO01 — (RxD0) — —

17 P15 PCLBUZ1 — — — TS16 (TI02)/

(TO02) — SCK20/ SCL20 (TO03) — SI20/RxD2/ SDA20 (SCLA0) — (TO04) — SO20/ TxD2 (SDAA0) —

20 P12 TOOLTxD — — — TS13 (TI05)/

(TO05) — SO00/ TxD0

21 P11 TOOLRxD — — — TS12 (TI06)/

(TO06) — SI00/RxD0/ SDA00 (TO07) — SCK00/ SCL00

31 P21 — ANI1/

RL78/G22 1. Outline R01DS0424EJ0120 Rev.1.20 Page 29 of 121 Jun 30, 2026

32 P20 — ANI0/

3 4 P 0 1 — ———T S 2 7 T O 0 0 —R x D 1 —— 3 5 P 0 0 — ———T S 2 6 T I 0 0 —T x D 1 ——

36 P140 PCLBUZ0 — INTP6 — TS08 — — — — —

40 — RESET 47 — V Table 1 - 11 Multiplexed Pin Functions of the 48-pin Products (2/2) Pin Number I/O Power supply, system clock, and debugging Analog Circuit HMI Timers Communications Interfaces 48HWQFN 48LFQFP Digital port A/D converter (ADC) Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA)

RL78/G22 1. Outline R01DS0424EJ0120 Rev.1.20 Page 30 of 121 Jun 30, 2026

1.4 Pin Identification

ANI0 to ANI7, RxD0 to RxD2, ANI16 to ANI19 : Analog input RxDA0 : Receive data AVREFM : Analog reference voltage minus SCLA0, AVREFP : Analog reference voltage plus SCK00, SCK01, EXCLK : External clock input SCK11, SCK20, SCK21 : Serial clock input/output (main system clock) SCL00, SCL01, EXCLKS : External clock input SCL11, SCL20, (subsystem clock) SCL21 : Serial clock output INTP0 to INTP6, INTP8, SDAA0, SDA00, INTP9 : Interrupt request from peripheral SDA01, SDA11, KR0 to KR5 : Key return input SDA20, SDA21 : Serial data input/output P00, P01 : Port 0 SI00, SI01, SI11, P10 to P17 : Port 1 SI20, SI21 : Serial data input P20 to P27 : Port 2 SO00, SO01 P30, P31 : Port 3 SO11, SO20, SO21 : Serial data output P40, P41 : Port 4 TSCAP : Touch sensor capacitance P50, P51 : Port 5 TI00 to TI07 : Timer input P60 to P63 : Port 6 TO00 to TO07 : Timer output P70 to P75 : Port 7 TOOL0 : Data input/output for tool P120 to P124 : Port 12 TOOLRxD, TOOLTxD : Data input/output for external device P130, P137 : Port 13 TS00 to TS28 : Capacitive touch sensor P140, P146, P147 : Port 14 TxD0 to TxD2 PCLBUZ0, PCLBUZ1 : Programmable clo ck output/buzzer TxDA0 : Transmit data output VBAT : Battery backup power supply REGC : Regulator capacitance VDD : Power supply RESET : Reset VSS : Ground RTC1HZ : Realtime clock correction clock (1 Hz) X1, X2 : Crystal oscillator (main system clock) output XT1, XT2 : Crystal oscillator (subsystem clock)

RL78/G22 1. Outline R01DS0424EJ0120 Rev.1.20 Page 31 of 121 Jun 30, 2026

1.5 Block Diagram

Caution 1. The serial interface IICA is only incorporated in the 24- to 48-pin products. Caution 2. The serial interface UARTAn is only incorporated in the 36- to 48-pin products. Caution 3. The key return function is only incorporated in the 40- to 48-pin products. Remark m: Unit number, n: Channel number, p: Simplified SPI (CSI) number, q: UART number, r: Simplified I 2C number, xx: Port number Voltage regulator REGC Interrupt control RAM Power-on reset/ voltage detector POR/LVD control Reset control UARTq IICr INTPn CSIp Key return BCD correction Serial interface IICA Buzzer output Clock output control PCLBUZn RL78 CPU core CRC RxDq TxDq ANIn AVREFP SCLAn SDAAn RTC1HZ RESET KRn Watchdog timer Data transfer controller CHn Port x Pxx Serial array unit m TImn TOmn SCKp SIp SOp SCLr SDAr Code flash memory Data flash memory AVREFM Clock generator and reset generator Middle-speed on-chip oscillator 1t o 4M H z High-speed on-chip oscillator 1 to 32 MHz Subsystem clock oscillator 32.768 kHz X1 X2/EXCLK XT1 XT2/EXCLKS Serial interface UARTAnRxDAn TxDAn SNOOZE mode sequencer Capacitive sensing unit TSn TSCAP High-speed system clock oscillator 1 to 20 MHz Multiplier, divider, and multiply-accumulator TOOL0 On-chip debugging Safety function Security function Low-speed on-chip oscillator 32.768 kHz Realtime clock A/D converter TOOLRxD, TOOLTxD VSSVDD Timer array unit m 32-bit interval timer Event link controller

RL78/G22 1. Outline R01DS0424EJ0120 Rev.1.20 Page 32 of 121 Jun 30, 2026

1.6 Outline of Functions

Caution This outline describes the functi ons at the time when the peripheral I/O redirection register (PIOR) is set to 00H. (1/4) Item 16-pin 20-pin 24-pin 25-pin 30-pin 32-pin 36-pin 40-pin 44-pin 48-pin R7F102G4x R7F102G6x R7F102G7x R7F102G8x R7F102GAx R7F102GBx R7F102GCx R7F102GEx R7F102GFx R7F102GGx Code flash memory 32 or 64 KB Data flash memory 2 KB RAM 4 KB Address space 1 Mbyte CPU/ peripheral hardware clock frequency CLK) Main system clock HS (high-speed main) mode: 1 to 32 MHz (V DD = 1.8 to 5.5 V) HS (high-speed main) mode: 1 to 4 MHzNote 1 (VDD = 1.6 to 5.5 V) LS (low-speed main) mode: 1 to 24 MHz (VDD = 1.8 to 5.5 V) LS (low-speed main) mode: 1 to 4 MHzNote 1 (VDD = 1.6 to 5.5 V) LP (low-power main) mode: 1 to 2 MHzNote 1 (VDD = 1.6 to 5.5 V) Subsystem clock SUB mode: 32.768 kHz (VDD = 1.6 to 5.5 V) Main system clock High- speed system clock (f MX) 1 to 20 MHz High- speed on- chip oscillator clock (f IH)

1 MHz, 2 MHz, 3 MHz, 4 MHz, 6 MHz, 8 MHz, 12 MHz, 16 MHz, 24 MHz, 32 MHz

clock (f IM)

1 MHz, 2 MHz, 4 MHz

SX) Low-speed on-chip oscillator clock (f IL) 32.768 kHz (typ.) General-purpose registers 8 bits × 32 registers (8 bits × 8 registers × 4 banks) Minimum instruction execution time 0.03125 µs (at the 32-MHz operation with the high-speed on-chip oscillator clock (f IH)) Instruction set • Data transfer (8/16 bits)

Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits × 8 bits, 16 bits × 16 bits), division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits)
Multiplication and accumulation (16 bits × 16 bits + 32 bits)
Rotate, barrel shift, and bit manipulation (set, reset, test, and Boolean operation), etc.

RL78/G22 1. Outline R01DS0424EJ0120 Rev.1.20 Page 33 of 121 Jun 30, 2026 I/O port Total number of pins 12 16 20 21 26 28 32 36 40 44 CMOS I/O 11 (N-ch open- drain I/O [withstand voltage of V DD]: 4) (N-ch open- drain I/O [withstand voltage of V DD]: 5) (N-ch open-drain I/O [withstand voltage of V DD]: 6) (N-ch open- drain I/O [withstand voltage of V DD]: 10) (N-ch open- drain I/O [withstand voltage of V DD]: 10) (N-ch open- drain I/O [withstand voltage of V DD]: 12) (N-ch open- drain I/O [withstand voltage of V DD]: 12) (N-ch open- drain I/O [withstand voltage of V DD]: 12) (N-ch open- drain I/O [withstand voltage of V DD]: 13) CMOS input 1 3 CMOS output —1 — 1 N-ch open- drain I/O (withstand voltage of 6V ) —2 3 4 Timers 16-bit timer 8 channels Watchdog timer 1 channel Realtime clock (RTC) 1 channel 32-bit interval timer (TML32) 1 channel in 32-bit counter mode, 2 channels in 16-bit counter mode, 4 channels in 8-bit counter mode Timer output 1 channel (PWM output: 1) 3 channels (PWM outputs: Note 2) 4 channels (PWM outputs: 3Note 2) 4 channels (PWM outputs: 3Note 2), 8 channels (PWM outputs: 7Note 2)Note 3 RTC output 1 channel Clock output/buzzer output

3.91 kHz, 7.81 kHz, 15.63 kHz, 2 MHz, 4 MHz, 8 MHz, 16 MHz (at the 32-MHz operation with the main system clock (fMAIN)) (at the 32.768-kHz operation with the low-speed peripheral clock (fSXP)) 8-/10-bit resolution A/D converter channels 6 channels 8 channels 9 channels 10 channels (2/4) Item 16-pin 20-pin 24-pin 25-pin 30-pin 32-pin 36-pin 40-pin 44-pin 48-pin R7F102G4x R7F102G6x R7F102G7x R7F102G8x R7F102GAx R7F102GBx R7F102GCx R7F102GEx R7F102GFx R7F102GGx

RL78/G22 1. Outline R01DS0424EJ0120 Rev.1.20 Page 34 of 121 Jun 30, 2026 Serial interfaces [16-pin products]

Simplified SPI (CSI): 1 channel, simplified I2C: 1 channel, UART: 1 channel
Simplified I2C: 1 channel [20- to 25-pin products]
Simplified SPI (CSI): 1 channel, simplified I2C: 1 channel, UART: 1 channel
Simplified SPI (CSI): 1 channel, simplified I2C: 1 channel, UART: 1 channel [30- and 32-pin products]
Simplified SPI (CSI): 1 channel, simplified I 2C: 1 channel, UART: 1 channel
Simplified SPI (CSI): 1 channel, simplified I2C: 1 channel, UART: 1 channel
Simplified SPI (CSI): 1 channel, simplified I2C: 1 channel, UART (UART supporting LIN-bus): 1 channel [36- to 44-pin products]
Simplified SPI (CSI): 1 channel, simplified I 2C: 1 channel, UART: 1 channel
Simplified SPI (CSI): 1 channel, simplified I2C: 1 channel, UART: 1 channel
Simplified SPI (CSI): 2 channels, simplified I2C: 2 channels, UART (UART supporting LIN-bus): 1 channel [48-pin products]
Simplified SPI (CSI): 2 channels, simplified I2C: 2 channels, UART: 1 channel
Simplified SPI (CSI): 1 channel, simplified I2C: 1 channel, UART: 1 channel
Simplified SPI (CSI): 2 channels, simplified I2C: 2 channels, UART (UART supporting LIN-bus): 1 channel UARTA — 1 channel I2C bus — 1 channel Data transfer controller (DTC) sources sources 25 sources 28 sources 30 sources 31 sources 32 sources Event link controller (ELC) Event inputs 11 12 14 15 17 18 19 Event trigger outputs SNOOZE mode sequencer (SMS) Capacitive sensing unit 5 9 11 12 16 17 21 23 25 29 Vectored interrupt sources Internal 23 25 26 29 32 E x t e r n a l 2 3 56 71 0 Key interrupt — 46 Reset • Reset by RESET pin
Internal reset by watchdog timer
Internal reset by power-on-reset
Internal reset by voltage detectors (LVD0 and LVD1)
Internal reset by illegal instruction execution Note 4
Internal reset by RAM parity error
Internal reset by illegal-memory access Power-on-reset circuit Detection voltage
1.50 V (typ.) Voltage detector LVD0 Detection voltage
Rising edge: 1.67 to 4.00 V (6 stages)
Falling edge: 1.63 to 3.92 V (6 stages) LVD1 Detection voltage
Rising edge: 1.67 to 4.16 V (18 stages)
Falling edge: 1.63 to 4.08 V (18 stages) On-chip debugging Available Power supply voltage V DD = 1.6 to 5.5 V (3/4) Item 16-pin 20-pin 24-pin 25-pin 30-pin 32-pin 36-pin 40-pin 44-pin 48-pin R7F102G4x R7F102G6x R7F102G7x R7F102G8x R7F102GAx R7F102GBx R7F102GCx R7F102GEx R7F102GFx R7F102GGx

RL78/G22 1. Outline R01DS0424EJ0120 Rev.1.20 Page 35 of 121 Jun 30, 2026 Note 1. Ensure that the operating voltage is at least 1.8 V during overwriting of the flash memory. Note 2. The number of PWM outputs varies depending on the setting of channels in use (the number of masters and slaves). For details, see 7.9.3 Operation for the multiple PWM output function in the RL78/G22 User’s Manual. Note 3. This applies when the corresponding bit in the peripheral I/O redirection register (PIOR) is set to 1. Note 4. In normal operation, executing the instruction code FFH triggers an internal reset, but this is not the case during emulation by the on-chip debugging emulator. Operating ambient temperature TA = –40 to +85°C (2D: Consumer applications), TA = –40 to +105°C (3C: Industrial applications) (4/4) Item 16-pin 20-pin 24-pin 25-pin 30-pin 32-pin 36-pin 40-pin 44-pin 48-pin R7F102G4x R7F102G6x R7F102G7x R7F102G8x R7F102GAx R7F102GBx R7F102GCx R7F102GEx R7F102GFx R7F102GGx

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 36 of 121 Jun 30, 2026 2. Electrical Characteristics This section describes the electrical characteristics of the following products. Caution 1. This MCU has on-chip debugging functionality for use in the development and evaluation of user systems. Do not use on-chip debugging with products designated as part of mass production, because using this function may cause the guaranteed number of times the flash memory is rewritten to be exceeded, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when on-chip debugging is used with products designated as part of mass production. Caution 2. For the consumer application products, the ambient operating temperature of T A = -40 to +85°C applies. Note that the characteristics of the A/D converter for each of the ranges of ambient operating temperature are described in the following sections.

2.6.1 Characteristics of the A/D converter for TA = -40 to +85°C

2.6.2 Characteristics of the A/D converter for TA = -40 to +105°C

Caution 3. The present pins differ depending on the products. For details, see section 2.1 Functions of Port Pins through section 2.2.1 Functions for each product in the RL78/G22 User’s Manual.

2D: Consumer applications, TA = -40 to +85°C R7F102Gxx2Dxx
3C: Industrial applications, TA = -40 to +105°C R7F102Gxx3Cxx

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 37 of 121 Jun 30, 2026

2.1 Absolute Maximum Ratings

Note 1. Connect the REGC pin to VSS via a capacitor (0.47 to 1 µF). The listed value is the absolute maximum rating of the REGC pin. Only use the capacitor connection. Do not apply a specific voltage to this pin. Note 2. This voltage must be no higher than 6.5 V. Note 3. The voltage on a pin in use for A/D conversion must not exceed AVREFP + 0.3. (Caution and Remarks are listed on the next page.) (1/2) Item Symbols Conditions Ratings Unit Supply voltage V DD -0.5 to +6.5 V REGC pin input voltage V IREGC REGC -0.3 to +2.1 and -0.3 to VDD + 0.3Note 1 V Input voltage V I1 P00, P01, P10 to P17, P30, P31, P40, P41, P50, P51, P70 to P75, P120, P140, P146, P147 -0.3 to VDD + 0.3Note 2 V VI2 P60 to P63 (N-ch open-drain) -0.3 to +6.5 V VI3 P20 to P27, P121 to P124, P137, EXCLK, EXCLKS, RESET -0.3 to VDD + 0.3Note 2 V Output voltage V O1 P00, P01, P10 to P17, P30, P31, P40, P41, P50, P51, P60 to P63, P70 to P75, P130, P140, P146, P147 -0.3 to V DD + 0.3Note 2 V VO2 P20 to P27, P121, P122 -0.3 to VDD + 0.3Note 2 V Analog input voltage V AI1 ANI16 to ANI19 -0.3 to VDD + 0.3 and -0.3 to AVREFP + 0.3 Notes 2, 3 V VAI2 ANI0 to ANI7 -0.3 to VDD + 0.3 and -0.3 to AVREFP + 0.3 Notes 2, 3 V High-level output current I OH1 Per pin P00, P01, P10 to P17, P30, P31, P40, P41, P50, P51, P70 to P75, P120, P130, P140, P146, P147 -40 mA Total of all pins -170 mA P00, P01, P40, P41, P120, P130, P140 -70 mA P10 to P17, P30, P31, P50, P51, P70 to P75, P146, P147 -100 mA I OH2 Per pin P20 to P27, P121, P122 -5 mA Total of all pins -20 mA Low-level output current IOL1 Per pin P00, P01, P10 to P17, P30, P31, P40, P41, P50, P51, P60 to P63, P70 to P75, P120, P130, P140, P146, P147 40 mA Total of all pins 170 mA P00, P01, P40, P41, P120, P130, P140 70 mA P10 to P17, P30, P31, P50, P51, P60 to P63, P70 to P75, P146, P147 100 mA I OL2 Per pin P20 to P27, P121, P122 10 mA Total of all pins 20 mA

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 38 of 121 Jun 30, 2026 Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark 1. The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified. Remark 2. AV REFP refers to the positive reference voltage of the A/D converter. Remark 3. The reference voltage is VSS. (2/2) Item Symbols Conditions Ratings Unit Ambient operating temperature TA In normal operation mode 3C: Industrial applications -40 to +105 C 2D: Consumer applications -40 to +85 In flash memory programming mode 3C: Industrial applications -40 to +105 2D: Consumer applications -40 to +85 Storage temperature T stg -65 to +150 C

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 39 of 121 Jun 30, 2026

2.2 Characteristics of the Oscillators

2.2.1 Characteristics of the X1 oscillator

Note The listed time and frequency indicate permissible ranges of the oscillator. For actual applications, request evaluation by the manufacturer of the oscillator circuit mounted on a board so you can use appropriate values. See 2.4 AC Characteristics for instruction execution time. Caution Since the CPU is started by the high-speed on-chip o scillator clock after release from the reset state, the user should use the oscillation stabilization time counter status register (OSTC) to check the X1 clock oscillation stabilization time. Specify the values for the oscillation stabilization time in the OSTC register and the oscillation stabilization time select register (OSTS) after having sufficiently evaluated the oscillation stabilization time with the resonator to be used.

2.2.2 Characteristics of the XT1 oscillator

Note The listed time and frequency indicate permissible ranges of the oscillator. For actual applications, request evaluation by the manufacturer of the oscillator circuit mounted on a board so you can use appropriate values. See 2.4 AC Characteristics for instruction execution time. (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Item Resonator Conditions Min. Typ. Max. Unit X1 clock oscillation allowable input cycle timeNote Ceramic resonator/ crystal resonator 0.05 1 µs (TA = -40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V (16- to 36-pin products), 1.6 V ≤ VDD ≤ 5.5 V (40- to 48-pin products), VSS = 0 V) Item Resonator Conditions Min. Typ. Max. Unit XT1 clock oscillation frequency (fXT)Note Crystal resonator 32.768 kHz

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 40 of 121 Jun 30, 2026

2.2.3 Characteristics of the on-chip oscillators

Note 1. The accuracy values were obtained in testing of this product. Note 2. This condition applies when the setting of the FRQSEL3 bit of the user option byte is 1. Note 3. The listed values only indicate the characteristics of the oscillators. See 2.4 AC Characteristics for instruction execution time. Note 4. These values are the results of characteristic evaluation and are not checked for shipment. (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Item Symbol Conditions Min. Typ. Max. Unit High-speed on-chip oscillator clock frequency fIH 13 2 MHz High-speed on-chip oscillator clock frequency accuracy Note 1 HIPREC = 1 +85 to +105°C 1.8 V ≤ VDD ≤ 5.5 V -2.0 +2.0 % HIPREC = 0Note 2 -15 0 % High-speed on-chip oscillator clock correction resolution 0.05 % Middle-speed on-chip oscillator clock frequencyNote 3 fIM 14 MHz Middle-speed on-chip oscillator clock frequency accuracyNote 1 -12 +12 % Middle-speed on-chip oscillator clock correction resolution 0.15 % Middle-speed on-chip oscillator frequency temperature coefficient ±0.17 Note 4 %/°C Low-speed on-chip oscillator clock frequency Note 3 fIL 32.768 kHz Low-speed on-chip oscillator clock frequency accuracyNote 1 -15 +15 % Low-speed on-chip oscillator clock correction resolution 0.3 % Low-speed on-chip oscillator frequency temperature coefficient ±0.21 Note 4 %/°C

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 41 of 121 Jun 30, 2026

2.3 DC Characteristics

2.3.1 Characteristics of pins

Note 1. Device operation is guaranteed at the listed currents even if current is flowing from the VDD pin to an output pin. Note 2. The combination of these and other pins must also not exceed the value for maximum total current. Note 3. The listed currents apply when the duty cycle is no greater than 70%. Use the following formula to calculate the output current when the duty cycle is greater than 70%, where n is the duty cycle.

Total output current from the listed pins = (IOH  0.7)/(n  0.01) Example when n = 80% and IOH = -10.0 mA Total output current from the listed pins = (-10.0  0.7)/(80  0.01) ≈ -8.7 mA Note that the duty cycle has no effect on the current that is allowed to flow into a single pin. A current higher than the absolute maximum rating must not flow into a single pin. Note 4. The maximum value is -30 mA in the products for industrial applications (R7F102Gxx3xxxC) with an ambient operating temperature range of +85 to +105°C. Note 5. The maximum value is -50 mA in the products for industrial applications (R7F102Gxx3xxxC) with an ambient operating temperature range of +85 to +105°C. Note 6. The maximum values are respectively -100 mA and -60 mA in the products for industrial applications (R7F102Gxx3xxxC) with an ambient operating temperature range of -40 to +85°C and of +85 to +105°C. Caution The following pins are not capable of the output of high-level signals in the N-ch open-drain output mode. P00, P10 to P15, P17, P50, P71, P72, P74, and P120 Remark The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified. Item Symbol Conditions Min. Typ. Max. Unit Allowable high-level output currentNote 1 IOH1 Per pin for P00, P01, P10 to P17, P30, P31, P40, P41, P50, P51, P70 to P75, P120, P130, P140, P146, P147

1.6 V ≤ V

DD ≤ 5.5 V -10.0Note 2 mA Total of P00, P01, P40, P41, P120, P130, P140 (when duty ≤ 70% Note 3) 4.0 V ≤ VDD ≤ 5.5 V -55.0Note 4 mA 2.7 V ≤ VDD < 4.0 V -10.0 mA 1.8 V ≤ VDD < 2.7 V -5.0 mA 1.6 V ≤ VDD < 1.8 V -2.5 mA Total of P10 to P17, P30, P31, P50, P51, P70 to P75, P146, P147 (when duty ≤ 70%Note 3) 4.0 V ≤ VDD ≤ 5.5 V -80.0Note 5 mA 2.7 V ≤ VDD < 4.0 V -19.0 mA 1.8 V ≤ VDD < 2.7 V -10.0 mA 1.6 V ≤ VDD < 1.8 V -5.0 mA Total of all pins (when duty ≤ 70% Note 3) 1.6 V ≤ VDD ≤ 5.5 V -135.0Note 6 mA IOH2 Per pin for P20 to P27, P121, P122 4.0 V ≤ VDD ≤ 5.5 V -3.0Note 2 mA 2.7 V ≤ VDD < 4.0 V -1.0Note 2 mA 1.8 V ≤ VDD < 2.7 V -1.0Note 2 mA 1.6 V ≤ VDD < 1.8 V -0.5Note 2 mA Total of all pins (when duty ≤ 70%Note 3) 4.0 V ≤ VDD ≤ 5.5 V -20.0 mA 2.7 V ≤ VDD < 4.0 V -10.0 mA 1.8 V ≤ VDD < 2.7 V -5.0 mA 1.6 V ≤ VDD < 1.8 V -5.0 mA

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 42 of 121 Jun 30, 2026 Note 1. Device operation is guaranteed at the listed currents even if current is flowing from an output pin to the VSS pin. Note 2. The combination of these and other pins must also not exceed the value for maximum total current. Note 3. The listed currents apply when the duty cycle is no greater than 70%. Use the following formula to calculate the output current when the duty cycle is greater than 70%, where n is the duty cycle.

Total output current from the listed pins = (IOL  0.7)/(n  0.01) Example when n = 80% and IOL = 10.0 mA Total output current from the listed pins = (10.0  0.7)/(80  0.01) ≈8.7 mA Note that the duty cycle has no effect on the current that is allowed to flow into a single pin. A current higher than the absolute maximum rating must not flow into a single pin. Note 4. The maximum value is 40 mA in the products for industrial applications (R7F102Gxx3xxxC) with an ambient operating temperature range of +85 to +105°C. Note 5. The maximum value is 80 mA in the products for industrial applications (R7F102Gxx3xxxC) with an ambient operating temperature range of +85 to +105°C. Remark The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified. Item Symbol Conditions Min. Typ. Max. Unit Allowable low-level output currentNote 1 IOL1 Per pin for P00, P01, P10 to P17, P30, P31, P40, P41, P50, P51, P70 to P75, P120, P130, P140, P146, P147 20.0 Note 2 mA Per pin for P60 to P63 15.0Note 2 mA Total of P00, P01, P40, P41, P120, P130, P140 (when duty ≤ 70%Note 3) 4.0 V ≤ VDD ≤ 5.5 V 70.0Note 4 mA 2.7 V ≤ VDD < 4.0 V 15.0 mA 1.8 V ≤ VDD < 2.7 V 9.0 mA 1.6 V ≤ VDD < 1.8 V 4.5 mA Total of P10 to P17, P30, P31, P50, P51, P60 to P63, P70 to P75, P146, P147 (when duty ≤ 70%Note 3) 4.0 V ≤ VDD ≤ 5.5 V 80.0Note 4 mA 2.7 V ≤ VDD < 4.0 V 35.0 mA 1.8 V ≤ VDD < 2.7 V 20.0 mA 1.6 V ≤ VDD < 1.8 V 10.0 mA Total of all pins (when duty ≤ 70% Note 3) 150.0Note 5 mA IOL2 Per pin for P20 to P27, P121, P122 4.0 V ≤ VDD ≤ 5.5 V 8.5Note 2 mA 2.7 V ≤ VDD < 4.0 V 1.5Note 2 mA 1.8 V ≤ VDD < 2.7 V 0.6Note 2 mA 1.6 V ≤ VDD < 1.8 V 0.4Note 2 mA Total of all pins (when duty ≤ 70%Note 3) 4.0 V ≤ VDD ≤ 5.5 V 20 mA 2.7 V ≤ VDD < 4.0 V 20 mA 1.8 V ≤ VDD < 2.7 V 15 mA 1.6 V ≤ VDD < 1.8 V 10 mA

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 43 of 121 Jun 30, 2026 Caution The maximum value of V IH of pins P00, P10 to P15, P17, P50, P71, P72, P74, and P120 is VDD, even in the N-ch open-drain output mode. Remark The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified. Item Symbol Conditions Min. Typ. Max. Unit Input voltage, high V IH1 P00, P01, P10 to P17, P30, P31, P40, P41, P50, P51, P70 to P75, P120, P140, P146, P147 Normal input buffer 0.8 V DD VDD V VIH2 P01, P10, P11, P13 to P17, P41, P71 TTL input buffer

4.0 V ≤ V

DD ≤ 5.5 V

2.2 V DD V

3.3 V ≤ VDD < 4.0 V

2.0 V DD V

DD < 3.3 V

1.5 V DD V

VIH3 P20 to P27 0.7 VDD VDD V VIH4 P60 to P63 0.7 VDD 6.0 V VIH5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0.8 VDD VDD V Input voltage, low V IL1 P00, P01, P10 to P17, P30, P31, P40, P41, P50, P51, P70 to P75, P120, P140, P146, P147 Normal input buffer 0 0.2 V DD V VIL2 P01, P10, P11, P13 to P17, P41, P71 TTL input buffer DD ≤ 5.5 V 00 . 8 V TTL input buffer

3.3 V ≤ V

DD < 4.0 V 00 . 5 V TTL input buffer 1.6 V ≤ VDD < 3.3 V 00 . 3 2 V VIL3 P20 to P27 0 0.3 VDD V VIL4 P60 to P63 0 0.3 VDD V VIL5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0 0.2 VDD V

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 44 of 121 Jun 30, 2026 Caution P00, P10 to P15, P17, P50, P71, P72, P74, and P120 do not output high-level signals in the N-ch open-drain output mode. Remark The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified. Item Symbol Conditions Min. Typ. Max. Unit Output voltage, high V OH1 P00, P01, P10 to P17, P30, P31, P40, P41, P50, P51, P70 to P75, P120, P130, P140, P146, P147 4.0 V ≤ VDD ≤ 5.5 V, IOH1 = -10.0 mA VDD - 1.5 V 4.0 V ≤ VDD ≤ 5.5 V, IOH1 = -3.0 mA V DD - 0.7 V 2.7 V ≤ VDD ≤ 5.5 V, IOH1 = -2.0 mA V DD - 0.6 V 1.8 V ≤ VDD ≤ 5.5 V, IOH1 = -1.5 mA V DD - 0.5 V 1.6 V ≤ VDD < 5.5 V, IOH1 = -1.0 mA V DD - 0.5 V VOH2 P20 to P27, P121, P122 4.0 V ≤ VDD ≤ 5.5 V, IOH2 = -3.0 mA V DD - 0.7 V 2.7 V ≤ VDD < 4.0 V, IOH2 = -1.0 mA V DD - 0.5 V 1.8 V ≤ VDD < 2.7 V, IOH2 = -1.0 mA V DD - 0.5 V 1.6 V ≤ VDD < 1.8 V, IOH2 = -0.5 mA V DD - 0.5 V Output voltage, low V OL1 P00, P01, P10 to P17, P30, P31, P40, P41, P50, P51, P70 to P75, P120, P130, P140, P146, P147 4.0 V ≤ VDD ≤ 5.5 V, IOL1 = 20.0 mA 1.3 V 4.0 V ≤ VDD ≤ 5.5 V, IOL1 = 8.5 mA 0.7 V 2.7 V ≤ VDD ≤ 5.5 V, IOL1 = 3.0 mA 0.6 V 2.7 V ≤ VDD ≤ 5.5 V, IOL1 = 1.5 mA 0.4 V 1.8 V ≤ VDD ≤ 5.5 V, IOL1 = 0.6 mA 0.4 V 1.6 V ≤ VDD ≤ 5.5 V, IOL1 = 0.3 mA 0.4 V VOL2 P20 to P27, P121, P122 4.0 V ≤ VDD ≤ 5.5 V, IOL2 = 8.5 mA 0.7 V 2.7 V ≤ VDD < 4.0 V, IOL2 = 1.5 mA 0.5 V 1.8 V ≤ VDD < 2.7 V, IOL2 = 0.6 mA 0.4 V 1.6 V ≤ VDD < 1.8 V, IOL2 = 0.4 mA 0.4 V VOL3 P60 to P63 4.0 V ≤ VDD ≤ 5.5 V, IOL3 = 15.0 mA 2.0 V 4.0 V ≤ VDD ≤ 5.5 V, IOL3 = 5.0 mA 0.4 V 2.7 V ≤ VDD ≤ 5.5 V, IOL3 = 3.0 mA 0.4 V 1.8 V ≤ VDD ≤ 5.5 V, IOL3 = 2.0 mA 0.4 V 1.6 V ≤ VDD ≤ 5.5 V, IOL3 = 1.0 mA 0.4 V

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 45 of 121 Jun 30, 2026 Remark The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified. Item Symbol Conditions Min. Typ. Max. Unit Input leakage current, high I LIH1 P00, P01, P10 to P17, P30, P31, P40, P41, P50, P51, P60 to P63, P70 to P75, P120, P130, P140, P146, P147 V I = VDD 0.5 µA ILIH2 P20 to P27, P137, RESET VI = VDD 0.5 µA ILIH3 P121 to P124 (X1, X2, XT1, XT2, EXCLK, EXCLKS) VI = VDD 0.5 µA Input leakage current, low I LIL1 P00, P01, P10 to P17, P30, P31, P40, P41, P50, P51, P60 to P63, P70 to P75, P120, P130, P140, P146, P147 V I = VSS -0.5 µA ILIL2 P20 to P27, P137, RESET VI = VSS -0.5 µA ILIL3 P121 to P124 (X1, X2, XT1, XT2, EXCLK, EXCLKS) V I = VSS -0.5 µA On-chip pull-up resistance R U P00, P01, P10 to P17, P30, P31, P40, P41, P50, P51, P70 to P75, P120 to P122, P140, P146, P147 VI = VSS, In input port 10 20 100 k Ω

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 46 of 121 Jun 30, 2026

2.3.2 Characteristics of the supply current

Note 1. The listed currents are the total currents flowing into VDD, including the input leakage currents flowing when the level of the input pin is fixed to VDD or VSS. The following points apply in the HS (high-speed main), LS (low-speed main), and LP (low- power main) modes.

The currents in the “Typ.” column do not include the operating currents of the peripheral modules.
The currents in the “Max.” column include the operating currents of the PCLBUZ, TAU, SAU, and IICA modules. The operating currents of other peripheral modules are not included. Note 2. The listed currents apply when the high-speed system clock, middle-speed on-chip oscillator, low-speed on-chip oscillator, and subsystem clock X are stopped. Note 3. The listed currents apply when the high-speed on-chip oscillator, high-speed system clock, low-speed on-chip oscillator, and subsystem clock X are stopped. Note 4. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, low-speed on-chip oscillator, and subsystem clock X are stopped. (Remarks are listed on the next page.) Item Symbol Conditions Min. Typ. Max. Unit Supply current Note 1 IDD1 Operating mode HS (high-speed main) mode f IH = 32 MHzNote 2 Basic operation V DD = 5.0 V 1.2 mA VDD = 1.8 V 1.2 Normal operation V DD = 5.0 V 2.7 4.6 mA VDD = 1.8 V 2.7 4.6 LS (low-speed main) mode f IH = 24 MHzNote 2 Normal operation V DD = 5.0 V 2.0 3.5 mA VDD = 1.8 V 2.0 3.5 fIH = 16 MHzNote 2 Normal operation VDD = 5.0 V 1.5 2.5 mA VDD = 1.8 V 1.5 2.5 fIM = 4 MHzNote 3 Normal operation V DD = 5.0 V 0.4 0.7 mA VDD = 1.6 V 0.4 0.7 LP (low-power main) mode f IM = 2 MHzNote 3 Normal operation VDD = 5.0 V 179 300 µA VDD = 1.6 V 179 300 fIM = 1 MHzNote 3 Normal operation V DD = 5.0 V 100 163 µA VDD = 1.6 V 100 163 HS (high-speed main) mode f MX = 20 MHzNote 4, Square wave input Normal operation VDD = 5.0 V 1.7 2.9 mA VDD = 1.8 V 1.6 2.8 LS (low-speed main) mode fMX = 20 MHzNote 4, Square wave input Normal operation VDD = 5.0 V 1.5 2.7 mA VDD = 1.8 V 1.5 2.7 fMX = 20 MHzNote 4, Resonator connection Normal operation V DD = 5.0 V 1.7 3.0 mA VDD = 1.8 V 1.7 3.0 fMX = 10 MHzNote 4, Square wave input Normal operation V DD = 5.0 V 0.8 1.5 mA VDD = 1.8 V 0.8 1.4 fMX = 10 MHzNote 4, Resonator connection Normal operation V DD = 5.0 V 0.9 1.6 mA VDD = 1.8 V 0.9 1.6 fMX = 8 MHzNote 4, Square wave input Normal operation V DD = 5.0 V 0.7 1.2 mA VDD = 1.8 V 0.7 1.2 fMX = 8 MHzNote 4, Resonator connection Normal operation V DD = 5.0 V 0.8 1.3 mA VDD = 1.8 V 0.8 1.3 <R> <R> <R> <R>

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 47 of 121 Jun 30, 2026 Remark 1. fIH: High-speed on-chip oscillator clock frequency Remark 2. fIM: Middle-speed on-chip oscillator clock frequency Remark 3. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 4. The typical value for the ambient operating temperature (TA) is +25°C unless otherwise specified.

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 48 of 121 Jun 30, 2026 Note 1. The listed currents are the total currents flowing into VDD, including the input leakage currents flowing when the level of the input pin is fixed to VDD or VSS. In the subsystem clock operation, the currents in both the “Typ.” and “Max.” columns do not include the operating currents of the peripheral modules. Note 2. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, high-speed system clock, and subsystem clock X are stopped. They do not include the current flowing into the RTC, 32-bit interval timer, and watchdog timer. Note 3. The listed currents apply when the high-speed on-chip oscillator, high-speed system clock, middle-speed on-chip oscillator, and low-speed on-chip oscillator are stopped, and the low power consumption oscillation 3 is specified (AMPHS1, AMPHS0 = 11B). They do not include the currents flowing into the RTC, 32-bit interval timer, and watchdog timer. Remark 1. fIL: Low-speed on-chip oscillator clock frequency Remark 2. fSUB: Subsystem clock frequency Item Symbol Conditions Min. Typ. Max. Unit Supply current Note 1 IDD1 Operating mode Subsystem clock operation mode f SUB = 32.768 kHzNote 2, Low-speed on-chip oscillator operation Normal operation TA = -40°C 2.9 4.7 µA TA = +25°C 3.1 4.9 TA = +50°C 3.3 6.3 TA = +70°C 3.6 9.6 TA = +105°C 5.4 32.2 fSUB = 32.768 kHzNote 3, Square wave input Normal operation T A = -40°C 2.9 4.9 µA TA = +25°C 3.0 5.0 TA = +50°C 3.2 6.4 TA = +70°C 3.5 9.7 TA = +105°C 5.4 32.4 fSUB = 32.768 kHzNote 3, Resonator connection Normal operation TA = -40°C 2.9 4.9 µA TA = +25°C 3.1 5.3 TA = +50°C 3.3 6.7 TA = +105°C 5.5 33.3 <R> <R>

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 49 of 121 Jun 30, 2026 Note 1. The listed currents are the total currents flowing into VDD, including the input leakage currents flowing when the level of the input pin is fixed to VDD or VSS. The following points apply in the HS (high-speed main), LS (low-speed main), and LP (low- power main) modes.

The currents in the “Typ.” column do not include the operating currents of the peripheral modules.
The currents in the “Max.” column include the operating currents of the PCLBUZ, TAU, SAU, and IICA modules. The operating currents of other peripheral modules are not included. Note 2. The listed currents apply when the HALT instruction has been fetched from the flash memory for execution. Note 3. The listed currents apply when the high-speed system clock, middle-speed on-chip oscillator, low-speed on-chip oscillator, and subsystem clock X are stopped. Note 4. The listed currents apply when the high-speed on-chip oscillator, high-speed system clock, low-speed on-chip oscillator, and subsystem clock X are stopped. Note 5. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, low-speed on-chip oscillator, and subsystem clock X are stopped. Remark 1. fIH: High-speed on-chip oscillator clock frequency Remark 2. fIM: Middle-speed on-chip oscillator clock frequency Remark 3. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 4. The typical value for the ambient operating temperature (TA) is +25°C unless otherwise specified. Item Symbol Conditions Min. Typ. Max. Unit Supply currentNote 1 IDD2 Note 2 HALT mode HS (high-speed main) mode fIH = 32 MHzNote 3 VDD = 5.0 V 0.49 1.87 mA VDD = 1.8 V 0.49 1.87 LS (low-speed main) mode fIH = 24 MHzNote 3 VDD = 5.0 V 0.41 1.46 mA VDD = 1.8 V 0.40 1.45 fIH = 16 MHzNote 3 VDD = 5.0 V 0.42 1.15 mA VDD = 1.8 V 0.41 1.14 fIM = 4 MHzNote 4 VDD = 5.0 V 0.08 0.26 mA VDD = 1.6 V 0.07 0.25 LP (low-power main) mode f IM = 2 MHzNote 4 VDD = 5.0 V 29 115 µA VDD = 1.6 V 29 115 fIM = 1 MHzNote 4 VDD = 5.0 V 25 71 µA VDD = 1.6 V 25 71 HS (high-speed main) mode fMX = 20 MHzNote 5, Square wave input VDD = 5.0 V 0.19 1.03 mA VDD = 1.8 V 0.16 0.99 LS (low-speed main) mode f MX = 20 MHzNote 5, Square wave input VDD = 5.0 V 0.19 1.03 mA VDD = 1.8 V 0.16 0.99 fMX = 20 MHzNote 5, Resonator connection VDD = 5.0 V 0.38 1.26 mA VDD = 1.8 V 0.37 1.25 fMX = 10 MHzNote 5, Square wave input VDD = 5.0 V 0.12 0.54 mA VDD = 1.8 V 0.10 0.52 fMX = 10 MHzNote 5, Resonator connection VDD = 5.0 V 0.22 0.67 mA VDD = 1.8 V 0.22 0.66 fMX = 8 MHzNote 5, Square wave input VDD = 5.0 V 0.10 0.45 mA VDD = 1.8 V 0.09 0.43 fMX = 8 MHzNote 5, Resonator connection VDD = 5.0 V 0.20 0.57 mA VDD = 1.8 V 0.20 0.56 <R> <R> <R> <R>

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 50 of 121 Jun 30, 2026 Note 1. The listed currents are the total currents flowing into VDD, including the input leakage currents flowing when the level of the input pin is fixed to VDD or VSS. In the subsystem clock operation mode or the STOP mode, the currents in both the “Typ.” and “Max.” columns do not include the operating currents of the peripheral modules. Note 2. The listed currents apply when the HALT instruction has been fetched from the flash memory for execution. Note 3. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, high-speed system clock, and subsystem clock X are stopped. They do not include the current flowing into the RTC, 32-bit interval timer, and watchdog timer. Note 4. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, high-speed system clock, and low-speed on-chip oscillator are stopped. They do not include the current flowing into the RTC, 32-bit interval timer, and watchdog timer. Note 5. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, high-speed system clock, and low-speed on-chip oscillator are stopped, and the setting of RTCLPC is 1, and the low power consumption oscillation 3 is specified (AMPHS1, AMPHS0 = 11B). They do not include the current flowing into the RTC, 32-bit interval timer, and watchdog timer. Note 6. The listed currents apply when all clocks are stopped. For the currents when operating the low-speed on-chip oscillator or subsystem clock X in the STOP mode, refer to the currents when operating the subsystem clock in the HALT mode. Remark 1. f IL: Low-speed on-chip oscillator clock frequency Remark 2. fSUB: Subsystem clock frequency Item Symbol Conditions Min. Typ. Max. Unit Supply current Note 1 IDD2 Note 2 HALT mode Subsystem clock operation mode fSUB = 32.768 kHzNote 3, Low-speed on-chip oscillator operation TA = -40°C 0.48 1.84 µA TA = +25°C 0.57 1.89 TA = +50°C 0.67 3.19 TA = +70°C 0.91 6.33 TA = +85°C 1.69 12.66 TA = +105°C 3.04 29.93 fSUB = 32.768 kHz, Square wave input Note 4 TA = -40°C 0.20 1.72 µA TA = +25°C 0.29 1.75 TA = +50°C 0.49 3.75 TA = +70°C 0.90 8.16 TA = +85°C 1.41 14.55 TA = +105°C 2.79 32.65 fSUB = 32.768 kHz, Resonator connection Note 5 TA = -40°C 0.21 1.79 µA TA = +25°C 0.33 2.03 TA = +50°C 0.44 3.40 TA = +70°C 0.97 8.65 TA = +85°C 1.48 15.04 TA = +105°C 2.92 33.56 IDD3 STOP mode Note 6 TA = -40°C 0.15 1.10 µA TA = +25°C 0.20 1.10 TA = +50°C 0.40 2.40 TA = +70°C 0.80 5.50 TA = +85°C 1.30 11.00 TA = +105°C 2.70 28.00 <R> <R> <R>

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 51 of 121 Jun 30, 2026 Peripheral Functions Item Symbol Conditions Min. Typ. Max. Unit High-speed on- chip oscillator operating current IFIHNote 1 380 µA Middle-speed on- chip oscillator operating current I FIMNote 1 20 µA Low-speed on- chip oscillator operating current I FILNote 1 0.3 µA RTC operating current I RTC Notes 1, 2, 3 fRTCCLK = 32.768 kHz 0.005 µA fRTCCLK = 128 Hz 0.002 µA 32-bit interval timer operating current I IT Notes 1, 2, 4 0.04 µA Watchdog timer operating current IWDT Notes 1, 2, 5 fIL = 32.768 kHz (typ.) 0.32 µA A/D converter operating current I ADC Notes 1, 6 When conversion at maximum speed Normal mode, AV REFP = VDD = 5.0 V 1.3 1.7 mA Low voltage mode, AVREFP = VDD = 3.0 V 0.5 0.7 mA A/D converter internal reference voltage current I ADREF Note 1 100 µA Temperature sensor operating current I TMPSNote 1 110 µA Serial interface UARTA operating current I UARTA Notes 1, 2, 7 fSXP = 32.768 kHz 1 channel: Reception at 2400 bps 0.14 µA LVD operating current ILVD0 Notes 1, 8 0.02 µA ILVD1 Notes 1, 8 0.02 µA Self-programming operating current IFSP Notes 1, 9 2.5 12.2 mA Data flash memory rewrite operating current I BGO Notes 1, 10 2.5 12.2 mA SNOOZE mode sequencer operating current ISMS Notes 1, 11 fIH = 32 MHz 0.93 mA fIL = 32.768 kHz 0.97 µA SNOOZE operating current I SNOZNote 1 fIH =

32 MHz

The ADC is shifting from the STOP mode to the SNOOZE mode. Note 12 0.5 0.7 mA The ADC is operating in the low-voltage mode. AVREFP = VDD = 3.0 V 0.9 1.4 Simplified SPI (CSI)/UART to be in use 0.6 0.79 mA SMSNote 13 1.4 mA Low-speed peripheral clock supply current I SXP Notes 1, 14 RTCLPC = 0 0.22 µA <R>

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 52 of 121 Jun 30, 2026 Note 1. This current flows into VDD. Note 2. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, and high-speed system clock are stopped. Note 3. This current flows into the realtime clock (RTC). It does not include the operating current of the low-speed on-chip oscillator or the XT1 oscillator. The supply current of this MCU is the sum of either IDD1 or IDD2, and IRTC, when the realtime clock is operating or in the HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be included in the supply current. IDD2 in the subsystem clock operation mode includes the operating current of the realtime clock. Note 4. This current only flows to the 32-bit interval timer. It does not include the operating current of the low-speed on-chip oscillator or the XT1 oscillator. The supply current of this MCU is the sum of either IDD1 or IDD2, and IIT, when the 32-bit interval timer is operating or in the HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be included in the supply current. Note 5. This current only flows to the watchdog timer. It includes the operating current of the low-speed on-chip oscillator. The supply current of this MCU is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer is operating. Note 6. This current only flows to the A/D converter. The supply current of this MCU is the sum of IDD1 or IDD2 and IADC when the A/D converter is operating or in the HALT mode. Note 7. This current only flows to the serial interface UARTA. It does not include the operating current of the low-speed on-chip oscillator or the XT1 oscillator. The supply current of this MCU is the sum of IDD1 or IDD2 and IUARTA when the serial interface UARTA is operating or in the HALT mode. Note that when the serial interface UARTA is in the HALT mode with the subsystem clock X (fSX) selected as the CPU/peripheral hardware clock (fCLK), the low-speed peripheral clock supply current (ISXP) is also added to the supply current. Note 8. This current only flows to the LVD. The supply current of this MCU is the sum of IDD1, IDD2 or IDD3 and ILVD when the LVD is in operation. Note 9. This current only flows during self-programming. Note 10. This current only flows while the data flash memory is being rewritten. Note 11. This current only flows into the SNOOZE mode sequencer. Note that the operating current of the low-speed on-chip oscillator and the XT1 oscillator are not included. The supply current of this MCU is the sum of either IDD1 or IDD2, and ISMS, when the SNOOZE mode sequencer is operating or in the HALT mode. Note 12. For shift time to the SNOOZE mode, see 20.3.3 SNOOZE mode in the RL78/G22 User’s Manual. Note 13. The listed values apply when the SNOOZE mode sequencer is in normal operation equivalent to IDD1. They do not include the current flowing into the peripheral functions other than the SNOOZE mode sequencer. Note 14. This current is added to the supply current in the HALT mode when the setting of RTCLPC is 0 in the STOP mode, or when the setting of RTCLPC is 0 with the subsystem clock X (f SX) selected as the CPU clock, while the subsystem clock X (fsx) is oscillating. Remark 1. fIL: Low-speed on-chip oscillator clock frequency Remark 2. fSX: Subsystem clock X frequency Remark 3. fCLK: CPU/peripheral hardware clock frequency Remark 4. The typical value for the ambient operating temperature (TA) is +25°C unless otherwise specified. Operating current of the true random number generator ITRNG Note 1 1.1 mA Item Symbol Conditions Min. Typ. Max. Unit <R>

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 53 of 121 Jun 30, 2026

2.4 AC Characteristics

Remark fMCK: Timer array unit operating clock frequency To set this operating clock, use the CKSmn0 and CKSmn1 bits of the timer mode register mn (TMRmn). m: Unit number (m = 0), n: Channel number (n = 0 to 3) (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Item Symbol Conditions Min. Typ. Max. Unit Instruction cycle (minimum instruction execution time) T CY Main system clock MAIN) operation HS (high-speed main) mode

1.8 V ≤ V

DD ≤ 5.5 V 0.03125 1 µs 1.6 V ≤ VDD ≤ 1.8 V 0.25 1 µs LS (low-speed main) mode 1.8 V ≤ VDD ≤ 5.5 V 0.04167 1 µs 1.6 V ≤ VDD ≤ 1.8 V 0.25 1 µs LP (low-power main) mode DD ≤ 5.5 V 0.5 1 µs In the self-programming mode HS (high-speed main) mode 1.8 V ≤ VDD ≤ 5.5 V 0.03125 1 µs LS (low-speed main) mode DD ≤ 5.5 V 0.04167 1 µs External system clock frequency fEX 1.8 V ≤ VDD ≤ 5.5 V 1.0 20.0 MHz 1.6 V ≤ VDD < 1.8 V 1.0 4.0 MHz fEXS 32 38.4 kHz External system clock input high-level width, low-level width t EXH, tEXL 1.8 V ≤ VDD ≤ 5.5 V 24 ns 1.6 V ≤ VDD < 1.8 V 120 ns tEXHS, tEXLS 13.7 µs TI00 to TI07 input high-level width, low- level width t TIH, tTIL 1/fMCK + 10 ns TO00 to TO07 output frequency fTO HS (high-speed main) mode LS (low-speed main) mode DD ≤ 5.5 V 16 MHz 2.7 V ≤ VDD < 4.0 V 8 MHz 1.8 V ≤ VDD < 2.7 V 4 MHz 1.6 V ≤ VDD < 1.8 V 2 MHz LP (low-power main) mode 1.6 V ≤ VDD ≤ 5.5 V 2 MHz PCLBUZ0, PCLBUZ1 output frequency f PCL HS (high-speed main) mode LS (low-speed main) mode DD ≤ 5.5 V 16 MHz 2.7 V ≤ VDD < 4.0 V 8 MHz 1.8 V ≤ VDD < 2.7 V 4 MHz 1.6 V ≤ VDD < 1.8 V 2 MHz LP (low-power main) mode 1.6 V ≤ VDD < 1.8 V 2 MHz Interrupt input high-level width, low-level width t INTH, tINTL INTP0 to INTP6, INTP8, INTP9 1.6 V ≤ VDD ≤ 5.5 V 1 µs Key interrupt input high- level width, low-level width t KRH, tKRL KR0 to KR5 1.8 V ≤ VDD ≤ 5.5 V 250 ns 1.6 V ≤ VDD < 1.8 V 1 µs RESET low-level width t RSL 10 µs

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 54 of 121 Jun 30, 2026 Minimum Instruction Execution Time during Main System Clock Operation TCY vs VDD in HS (high-speed main) mode TCY vs VDD in LS (low-speed main) mode 0.01 0.1 Cycle time TCY [µs] Supply voltage VDD [V] 0.03125 0.05 0.25 0.5 1.8 In normal operation 0.03125 0.05 0.25 0.5 1.6 During self-programming 5.5 0.01 0.1 Supply voltage VDD [V] 0.04167 0.05 0.25 0.5 1.6 1.8 In normal operation During self-programming 5.5 Cycle time TCY [µs]

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 55 of 121 Jun 30, 2026 TCY vs VDD in LP (low-power main) mode AC Timing Test Points External System Clock Timing In normal operation Supply voltage VDD [V] 1.0 0.1 0.01 1.6 0.05 Cycle time TCY [µs] 5.5 0.5 VIH/VOH VIL/VOL VIH/VOHTest points VIL/VOL EXCLK/EXCLKS 1/fEX/ 1/fEXS tEXL/ tEXLS tEXH/ tEXHS

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 56 of 121 Jun 30, 2026 TI/TO Timing Interrupt Request Input Timing Key Interrupt Input Timing RESET Input Timing tTIL tTIH 1/fTO TI00 to TI07 TO00 to TO07 INTP0 to INTP6, INTP8, INTP9 tINTL tINTH KR0 to KR5 tKRL tKRH tRSL RESET

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 57 of 121 Jun 30, 2026

2.5 Characteristics of the Peripheral Functions

2.5.1 Serial array unit

In UART communications with devices operating at same voltage levels Note 1. The transfer rate in the SNOOZE mode is within the range from 4800 to 9600 bps. Note 2. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are as follows. Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register (PIMg) and port output mode register (POMg). (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Item Symbol Conditions HS (High-speed Main) Mode LS (Low-speed Main) Mode LP (Low-power Main) Mode Unit Transfer rate Note 1 1.6 V ≤ VDD ≤ 5.5 V fMCK/6 fMCK/6 fMCK/6 bps Theoretical value of the maximum transfer rate fMCK = fCLKNote 2 5.3 4 0.33 Mbps HS (high-speed main) mode: 32 MHz (1.8 V ≤ VDD ≤ 5.5 V) 4 MHz (1.6 V ≤ VDD ≤ 5.5 V) LS (low-speed main) mode: 24 MHz (1.8 V ≤ VDD ≤ 5.5 V) 4 MHz (1.6 V ≤ VDD ≤ 5.5 V) LP (low-power main) mode: 2 MHz (1.6 V ≤ VDD ≤ 5.5 V) VIH/VOH VIL/VOL VIH/VOHTest points VIL/VOL

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 58 of 121 Jun 30, 2026 Connection in the UART communications with devices operating at same voltage levels Bit width in the UART communications when interfacing devices operate at the same voltage level (reference) Remark 1. q: UART number (q = 0 to 2), g: PIM and POM number (g = 0, 1) Remark 2. fMCK: Serial array unit operation clock frequency To set this operating clock, set the CKSmn bit in the serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01, 03, 10, 11) TxDq RxDq User device Rx Tx This MCU Baud rate error tolerance TxDq RxDq Low-/high-bit width 1/Transfer rate

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 59 of 121 Jun 30, 2026 2. In simplified SPI (CSI) communications in the master mode with devices operating at same voltage levels with the internal SCKp clock (the ratings below are only applicable to CSI00) Note 1. The setting applies when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The setting for the SIp setup time becomes “to SCKp↓” and that for the SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 2. This setting applies when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The setting for the delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 3. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using the port input mode register (PIMg) and the port output mode register (POMg). Remark 1. The listed times are only valid when the peripheral I/O redirect function of CSI00 is not in use. Remark 2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM numbers (g = 1) Remark 3. fMCK: Serial array unit operation clock frequency To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00) (TA = -40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Item Symbol Conditions HS (High-speed Main) Mode LS (Low-speed Main) Mode LP (Low-power Main) Mode Unit SCKp cycle time t KCY1 tKCY1 ≥ 2/fCLK 4.0 V ≤ VDD ≤ 5.5 V 62.5 83.3 1000 ns 2.7 V ≤ VDD ≤ 5.5 V 83.3 125 1000 ns SCKp high-/ high-level width, low-level width tKH1, tKL1 4.0 V ≤ VDD ≤ 5.5 V t KCY1/2 - 7 tKCY1/2 - 10 tKCY1/2 - 50 ns 2.7 V ≤ VDD ≤ 5.5 V t KCY1/2 - 10 tKCY1/2 - 15 tKCY1/2 - 50 ns SIp setup time (to SCKp↑)Note 1 tSIK1 4.0 V ≤ VDD ≤ 5.5 V 23 33 110 ns 2.7 V ≤ VDD ≤ 5.5 V 33 50 110 ns SIp hold time (from SCKp↑) Note 1 tKSI1 2.7 V ≤ VDD ≤ 5.5 V 10 10 10 ns Delay time from SCKp↓ to SOp output Note 2 tKSO1 C = 20 pFNote 3 10 10 10 ns

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 60 of 121 Jun 30, 2026 3. In simplified SPI (CSI) communications in the master mode with devices operating at same voltage levels with the internal SCKp clock Note 1. This setting applies when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The setting for the SIp setup time becomes “to SCKp↓” and that for the SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 2. This setting applies when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The setting for the delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 3. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using the port input mode register (PIMg) and the port output mode register (POMg). Remark 1. p: CSI number (p = 00, 01, 11, 20, 21), m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3), g: PIM and POM numbers (g = 0, 1, 5, 7) Remark 2. fMCK: Serial array unit operation clock frequency To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01, 11) (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Item Symbol Conditions HS (High-speed Main) Mode LS (Low-speed Main) Mode LP (Low-power Main) Mode Unit SCKp cycle time t KCY1 tKCY1 ≥ 4/fCLK 2.7 V ≤ VDD ≤ 5.5 V 125 166 2000 ns 2.4 V ≤ VDD ≤ 5.5 V 250 250 2000 ns 1.8 V ≤ VDD ≤ 5.5 V 500 500 2000 ns 1.6 V ≤ VDD ≤ 5.5 V 1000 1000 2000 ns SCKp high-level width, low-level width tKH1, tKL1 4.0 V ≤ VDD ≤ 5.5 V t KCY1/2 - 12 tKCY1/2 - 21 tKCY1/2 - 50 ns 2.7 V ≤ VDD ≤ 5.5 V t KCY1/2 - 18 tKCY1/2 - 25 tKCY1/2 - 50 ns 2.4 V ≤ VDD ≤ 5.5 V t KCY1/2 - 38 tKCY1/2 - 38 tKCY1/2 - 50 ns 1.8 V ≤ VDD ≤ 5.5 V t KCY1/2 - 50 tKCY1/2 - 50 tKCY1/2 - 50 ns 1.6 V ≤ VDD ≤ 5.5 V t KCY1/2 - 100 tKCY1/2 - 100 tKCY1/2 - 100 ns SIp setup time (to SCKp↑)Note 1 tSIK1 4.0 V ≤ VDD ≤ 5.5 V 44 54 110 ns 2.7 V ≤ VDD ≤ 5.5 V 44 54 110 ns 2.4 V ≤ VDD ≤ 5.5 V 75 75 110 ns 1.8 V ≤ VDD ≤ 5.5 V 110 110 110 ns 1.6 V ≤ VDD ≤ 5.5 V 220 220 220 ns SIp hold time (from SCKp↑) Note 1 tKSI1 1.6 V ≤ VDD ≤ 5.5 V 19 19 19 ns Delay time from SCKp↓ to SOp output Note 2 tKSO1 1.6 V ≤ VDD ≤ 5.5 V C = 30 pFNote 3 25 25 25 ns

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 61 of 121 Jun 30, 2026 4. In simplified SPI (CSI) communications in the slave mode with devices operating at same voltage levels with the external SCKp clock (Notes, Caution, and Remarks are listed on the next page.) Item Symbol Conditions HS (High-speed Main) Mode LS (Low-speed Main) Mode LP (Low-power Main) Mode Unit SCKp cycle time Note 4 tKCY2 4.0 V ≤ VDD ≤ 5.5 V 20 MHz < f MCK 8/fMCK 8/fMCK —n s fMCK ≤ 20 MHz 6/f MCK 6/fMCK 6/fMCK ns 2.7 V ≤ VDD ≤ 5.5 V 16 MHz < f MCK 8/fMCK 8/fMCK —n s fMCK ≤ 16 MHz 6/f MCK 6/fMCK 6/fMCK ns 2.4 V ≤ VDD ≤ 5.5 V 6/f MCK and 500 6/fMCK and 500 6/fMCK and 500 ns 1.8 V ≤ VDD ≤ 5.5 V 6/f MCK and 750 6/fMCK and 750 6/fMCK and 750 ns 1.6 V ≤ VDD ≤ 5.5 V 6/f MCK and 1500 6/fMCK and 1500 6/fMCK and 1500 ns SCKp high-/ high-level width, low-level width tKH2, tKL2 4.0 V ≤ VDD ≤ 5.5 V t KCY2/2 - 7 t KCY2/2 - 7 t KCY2/2 - 7 ns 2.7 V ≤ VDD ≤ 5.5 V t KCY2/2 - 8 t KCY2/2 - 8 t KCY2/2 - 8 ns 1.8 V ≤ VDD ≤ 5.5 V t KCY2/2 - 18 tKCY2/2 - 18 tKCY2/2 - 18 ns 1.6 V ≤ VDD ≤ 5.5 V t KCY2/2 - 66 tKCY2/2 - 66 tKCY2/2 - 66 ns

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 62 of 121 Jun 30, 2026 4. In simplified SPI (CSI) communications in the slave mode with devices operating at same voltage levels with the external SCKp clock Note 1. This setting applies when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The setting for the SIp setup time becomes “to SCKp↓” and that for the SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 2. This setting applies when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The setting for the delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 3. C is the load capacitance of the SOp output line. Note 4. Transfer rate in the SNOOZE mode is 1 Mbps at the maximum. Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using the port input mode register (PIMg) and the port output mode register (POMg). Remark 1. p: CSI number (p = 00, 01, 11, 20, 21), m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3), g: PIM and POM numbers (g = 0, 1, 5, 7) Remark 2. fMCK: Serial array unit operation clock frequency To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01, 03, 10, 11) Item Symbol Conditions HS (High-speed Main) Mode LS (Low-speed Main) Mode LP (Low-power Main) Mode Unit SIp setup time (to SCKp↑)Note 1 tSIK2 2.7 V ≤ VDD ≤ 5.5 V 1/f MCK + 20 1/fMCK + 30 1/fMCK + 30 ns 1.8 V ≤ VDD ≤ 5.5 V 1/f MCK + 30 1/fMCK + 30 1/fMCK + 30 ns 1.6 V ≤ VDD ≤ 5.5 V 1/f MCK + 40 1/fMCK + 40 1/fMCK + 40 ns SIp hold time (from SCKp↑) Note 1 tKSI2 1.8 V ≤ VDD ≤ 5.5 V 1/f MCK + 31 1/fMCK + 31 1/fMCK + 31 ns 1.6 V ≤ VDD ≤ 5.5 V 1/f MCK + 250 1/fMCK + 250 1/fMCK + 250 ns Delay time from SCKp↓ to SOp output Note 2 tKSO2 C = 30 pF Note 3 2.7 V ≤ VDD ≤ 5.5 V 2/f MCK + 44 2/fMCK + 110 2/fMCK + 110 ns 2.4 V ≤ VDD ≤ 5.5 V 2/f MCK + 75 2/fMCK + 110 2/fMCK + 110 ns 1.8 V ≤ VDD ≤ 5.5 V 2/f MCK + 110 2/fMCK + 110 2/fMCK + 110 ns 1.6 V ≤ VDD ≤ 5.5 V 2/f MCK + 220 2/fMCK + 220 2/fMCK + 220 ns

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 63 of 121 Jun 30, 2026 Connection in the simplified SPI (CSI) communications with devices operating at same voltage levels Timing of serial transfer in the simplified SPI (CSI) communications with devices operating at same voltage levels when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1 SCKp SOp SCK SI SIp SOThis MCU User device Input dataSIp SOp tKCY1, 2 tKL1, 2 tKH1, 2 tSIK1, 2 tKSI1, 2 tKSO1, 2 Output data SCKp

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 64 of 121 Jun 30, 2026 Timing of serial transfer in the simplified SPI (CSI) communications with devices operating at same voltage levels when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0 Remark 1. p: CSI number (p = 00, 01, 11, 20, 21) Remark 2. m: Unit number, n: Channel number (mn = 00, 01, 03, 10, 11) Input dataSIp SOp tKCY1, 2 tKH1, 2 tKL1, 2 tSIK1, 2 tKSI1, 2 tKSO1, 2 Output data SCKp

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 65 of 121 Jun 30, 2026 5. In simplified I 2C communications with devices operating at same voltage levels (Notes and Caution are listed on the next page, and Remarks are listed on the page after the next page.) Item Symbol Conditions HS (High-speed Main) Mode LS (Low-speed Main) Mode LP (Low-power Main) Mode Unit SCLr clock frequency f SCL 2.7 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 1000 Note 1 1000 Note 1 400Note 1 kHz 1.8 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 400Note 1 400Note 1 400Note 1 kHz 1.8 V ≤ VDD < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 300Note 1 300Note 1 300Note 1 kHz 1.6 V ≤ VDD < 1.8 V, Cb = 100 pF, Rb = 5 kΩ 250Note 1 250Note 1 250Note 1 kHz Hold time when SCLr is low tLOW 2.7 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 475 475 1150 ns 1.8 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 1150 1150 1150 ns 1.8 V ≤ VDD < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 1550 1550 1550 ns 1.6 V ≤ VDD < 1.8 V, Cb = 100 pF, Rb = 5 kΩ 1850 1850 1850 ns Hold time when SCLr is high t HIGH 2.7 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 475 475 1150 ns 1.8 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 1150 1150 1150 ns 1.8 V ≤ VDD < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 1550 1550 1550 ns 1.6 V ≤ VDD < 1.8 V, Cb = 100 pF, Rb = 5 kΩ 1850 1850 1850 ns

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 66 of 121 Jun 30, 2026 5. In simplified I 2C communications with devices operating at same voltage levels Note 1. The listed times must be no greater than fMCK/4. Note 2. Set fMCK so that it will not exceed the hold time when SCLr is low or high. Caution Select the normal input buffer and the N-ch open drain output (withstand voltage of V DD) mode for the SDAr pin and the normal output mode for the SCLr pin by using port input mode register (PIMg) and port output mode register (POMh). (Remarks are listed on the next page.) Item Symbol Conditions HS (High-speed Main) Mode LS (Low-speed Main) Mode LP (Low-power Main) Mode Unit Data setup time (reception) tSU:DAT 2.7 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 1/fMCK + 85 Note 2 1/fMCK + 85 Note 2 1/fMCK + 145 Note 2 ns 1.8 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 1/fMCK + 145 Note 2 1/fMCK + 145 Note 2 1/fMCK + 145 Note 2 ns 1.8 V ≤ VDD < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 1/fMCK + 230 Note 2 1/fMCK + 230 Note 2 1/fMCK + 230 Note 2 ns 1.6 V ≤ VDD < 1.8 V, Cb = 100 pF, Rb = 5 kΩ 1/fMCK + 290 Note 2 1/fMCK + 290 Note 2 1/fMCK + 290 Note 2 ns Data hold time (transmission) tHD:DAT 2.7 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 0 305 0 305 0 305 ns 1.8 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 0 355 0 355 0 355 ns 1.8 V ≤ VDD < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 0 405 0 405 0 405 ns 1.6 V ≤ VDD < 1.8 V, Cb = 100 pF, Rb = 5 kΩ 0 405 0 405 0 405 ns

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 67 of 121 Jun 30, 2026 Connection in the simplified I2C communications with devices operating at same voltage levels Timing of serial transfer in the simplified I2C communications with devices operating at same voltage levels Remark 1. Rb[Ω]: Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance Remark 2. r: IIC number (r = 00, 01, 10, 11, 20, 21), g: PIM number (g = 0, 1, 3, 7), h: POM number (g = 1, 5, 7) Remark 3. fMCK: Serial array unit operation clock frequency To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01, 03, 10, 11) This MCU SDAr SCLr SDA SCL VDD Rb User device SDAr SCLr 1/fSCL tLOW tHIGH tSU:DATtHD:DAT

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 68 of 121 Jun 30, 2026 6. In UART communications with devices operating at different voltage levels (1.8 V, 2.5 V, 3 V) Note 1. Transfer rate in the SNOOZE mode is within the range from 4800 to 9600 bps. Note 2. Use this rate with VDD ≥ Vb. Note 3. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (withstand voltage of V DD) mode for the TxDq pin by using port input mode register (PIMg) and port output mode register (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remark 1. Vb[V]: Communication line voltage Remark 2. q: UART number (q = 0 to 2), g: PIM and POM number (g = 0, 1) Remark 3. fMCK: Serial array unit operation clock frequency To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01) Remark 4. Communications by using UART2 with devices operating at different voltage levels are not possible when the setting of the PIOR1 bit of the peripheral I/O redirection register (PIOR) is 1. Item Symbol Conditions HS (High-speed Main) Mode LS (Low-speed Main) Mode LP (Low-power Main) Mode Unit Transfer rate Reception 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V fMCK/6 Note 1 fMCK/6 Note 1 fMCK/6 Note 1 bps Theoretical value of the maximum transfer rate fMCK = fCLKNote 3 5.3 4 0.33 Mbps 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V fMCK/6 Note 1 fMCK/6 Note 1 fMCK/6 Note 1 bps Theoretical value of the maximum transfer rate fMCK = fCLKNote 3 5.3 4 0.33 Mbps 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V fMCK/6 Notes 1, 2 fMCK/6 Notes 1, 2 fMCK/6 Notes 1, 2 bps Theoretical value of the maximum transfer rate f MCK = fCLKNote 3 5.3 4 0.33 Mbps HS (high-speed main) mode: 32 MHz (1.8 V ≤ VDD ≤ 5.5 V) 4 MHz (1.6 V ≤ VDD ≤ 5.5 V) LS (low-speed main) mode: 24 MHz (1.8 V ≤ VDD ≤ 5.5 V) 4 MHz (1.6 V ≤ VDD ≤ 5.5 V) LP (low-power main) mode: 2 MHz (1.6 V ≤ VDD ≤ 5.5 V)

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 69 of 121 Jun 30, 2026 6. In UART communications with devices operating at different voltage levels (1.8 V, 2.5 V, 3 V) Note 1. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V Note 2. This rate is calculated as an example when the conditions described in the “Conditions” column are met. See Note 1 above to calculate the maximum transfer rate under conditions of the customer. (Notes and Caution are listed on the next page.) Item Symbol Conditions HS (High-speed Main) Mode LS (Low-speed Main) Mode LP (Low-power Main) Mode Unit Transfer rate Transmission 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V Note 1N ote 1N ote 1 bps Theoretical value of the maximum transfer rate C b = 50 pF, Rb = 1.4 kΩ, Vb = 2.7 V 2.8Note 2 2.8Note 2 2.8Note 2 Mbps 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V Note 3N ote 3N ote 3 bps Theoretical value of the maximum transfer rate C b = 50 pF, Rb = 2.7 kΩ, Vb = 2.3 V 1.2Note 4 1.2Note 4 1.2Note 4 Mbps 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Notes 5, 6 Notes 5, 6 Notes 5, 6 bps Theoretical value of the maximum transfer rate C b = 50 pF, Rb = 5.5 kΩ, Vb = 1.6 V 0.43 Note 7 0.43 Note 7 0.43 Note 7 Mbps Maximum transfer rate = [bps] Baud rate error (theoretical value) = Transfer rate  2 Vb Vb ( )  Number of transferred bits1 Transfer rate  100 [%] This value is the theoretical value of the relative difference between the transmission and reception sides.

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 70 of 121 Jun 30, 2026 Note 3. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V Note 4. This rate is calculated as an example when the conditions described in the “Conditions” column are met. See Note 3 above to calculate the maximum transfer rate under conditions of the customer. Note 5. Use this rate with VDD ≥ Vb. Note 6. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 7. This rate is calculated as an example when the conditions described in the “Conditions” column are met. See Note 6 above to calculate the maximum transfer rate under conditions of the customer. Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (withstand voltage of V DD) mode for the TxDq pin by using port input mode register (PIMg) and port output mode register (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Maximum transfer rate = [bps] Baud rate error (theoretical value) = Transfer rate  2 ( )  Number of transferred bits1 Transfer rate  100 [%] Vb Vb This value is the theoretical value of the relative difference between the transmission and reception sides. Maximum transfer rate = [bps] Baud rate error (theoretical value) = Transfer rate  2 ( )  Number of transferred bits1 Transfer rate  100 [%] Vb Vb This value is the theoretical value of the relative difference between the transmission and reception sides.

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 71 of 121 Jun 30, 2026 In UART communications with devices operating at different voltage levels Bit width in the UART communications with devices operating at different voltage levels (reference) Remark 1. Rb[Ω]: Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage Remark 2. q: UART number (q = 0 to 2), g: PIM and POM number (g = 0, 1) Remark 3. fMCK: Serial array unit operation clock frequency To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01) Remark 4. Communications by using UART2 with devices operating at different voltage levels are not possible when the setting of the PIOR1 bit of the peripheral I/O redirection register (PIOR) is 1. This MCU TxDq RxDq Rx Tx Vb Rb User device Baud rate error tolerance Low-/high-bit width 1/Transfer rate Baud rate error tolerance High-bit width Low-bit width 1/Transfer rate TxDq RxDq

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 72 of 121 Jun 30, 2026 7. In simplified SPI (CSI) communications in the master mode with devices operating at different voltage levels (2.5 V or 3 V) with the internal SCKp clock (the ratings below are only applicable to CSI00) (Notes, Caution, and Remarks are listed on the next page.) Item Symbol Conditions HS (High-speed Main) Mode LS (Low-speed Main) Mode LP (Low-power Main) Mode Unit SCKp cycle time t KCY1 tKCY1 ≥ 2/fCLK 4.0 V ≤ VDD ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ 200 200 2300 ns 2.7 V ≤ VDD < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ 300 300 2300 ns SCKp high-level width tKH1 4.0 V ≤ VDD ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ tKCY1/2 - 50 tKCY1/2 - 50 tKCY1/2 - 50 ns 2.7 V ≤ VDD < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ tKCY1/2 - 120 tKCY1/2 - 120 tKCY1/2 - 120 ns SCKp low-level width tKL1 4.0 V ≤ VDD ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ tKCY1/2 - 7 tKCY1/2 - 7 tKCY1/2 - 50 ns 2.7 V ≤ VDD < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ tKCY1/2 - 10 tKCY1/2 - 10 tKCY1/2 - 50 ns SIp setup time (to SCKp↑)Note 1 tSIK1 4.0 V ≤ VDD ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ 58 58 479 ns 2.7 V ≤ VDD < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ 121 121 479 ns SIp hold time (from SCKp↑)Note 1 tKSI1 4.0 V ≤ VDD ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ 10 10 10 ns 2.7 V ≤ VDD < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ 10 10 10 ns Delay time from SCKp↓ to SOp outputNote 1 tKSO1 4.0 V ≤ VDD ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ 60 60 60 ns 2.7 V ≤ VDD < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ 130 130 130 ns

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 73 of 121 Jun 30, 2026 7. In simplified SPI (CSI) communications in the master mode with devices operating at different voltage levels (2.5 V or 3 V) with the internal SCKp clock (the ratings below are only applicable to CSI00) Note 1. This setting applies when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. Note 2. This setting applies when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (withstand voltage of V DD) mode for the SOp pin and SCKp pin by using port input mode register (PIMg) and port output mode register (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remark 1. Rb[Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage Remark 2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM numbers (g = 1) Remark 3. fMCK: Serial array unit operation clock frequency To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn= 00) Remark 4. The listed times are only valid when the peripheral I/O redirect function of CSI00 is not in use. Item Symbol Conditions HS (High-speed Main) Mode LS (Low-speed Main) Mode LP (Low-power Main) Mode Unit SIp setup time (to SCKp↓)Note 2 tSIK1 4.0 V ≤ VDD ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ 23 23 110 ns 2.7 V ≤ VDD < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ 33 33 110 ns SIp hold time (from SCKp↓) Note 2 tKSI1 4.0 V ≤ VDD ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ 10 10 10 ns 2.7 V ≤ VDD < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ 10 10 10 ns Delay time from SCKp↑ to SOp outputNote 2 tKSO1 4.0 V ≤ VDD ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ 10 10 10 ns 2.7 V ≤ VDD < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ 10 10 10 ns

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 74 of 121 Jun 30, 2026 8. In simplified SPI (CSI) communications in the master mode with devices operating at different voltage levels (1.8 V,

2.5 V, or 3 V) with the internal SCKp clock

Note Use this setting with VDD ≥ Vb. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (withstand voltage of V DD) mode for the SOp pin and SCKp pin by using port input mode register (PIMg) and port output mode register (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed two pages after the next page.) Item Symbol Conditions HS (High-speed Main) Mode LS (Low-speed Main) Mode LP (Low-power Main) Mode Unit SCKp cycle time t KCY1 tKCY1 ≥ 4/fCLK 4.0 V ≤ VDD ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ 300 300 2300 ns 2.7 V ≤ VDD < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ 500 500 2300 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote, Cb = 30 pF, Rb = 5.5 kΩ 1150 1150 2300 ns SCKp high-level width t KH1 4.0 V ≤ VDD ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ tKCY1/2 - 75 tKCY1/2 - 75 tKCY1/2 - 75 ns 2.7 V ≤ VDD < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ tKCY1/2 - 170 tKCY1/2 - 170 tKCY1/2 - 170 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote, Cb = 30 pF, Rb = 5.5 kΩ tKCY1/2 - 458 tKCY1/2 - 458 tKCY1/2 - 458 ns SCKp low-level width t KL1 4.0 V ≤ VDD ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ tKCY1/2 - 12 tKCY1/2 - 12 tKCY1/2 - 50 ns 2.7 V ≤ VDD < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ tKCY1/2 - 18 tKCY1/2 - 18 tKCY1/2 - 50 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote, Cb = 30 pF, Rb = 5.5 kΩ tKCY1/2 - 50 tKCY1/2 - 50 tKCY1/2 - 50 ns

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 75 of 121 Jun 30, 2026 8. In simplified SPI (CSI) communications in the master mode with devices operating at different voltage levels (1.8 V, Note 1. This setting applies when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. Note 2. Use this setting with VDD ≥ Vb. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (withstand voltage of V DD) mode for the SOp pin and SCKp pin by using port input mode register (PIMg) and port output mode register (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the page after the next page.) Item Symbol Conditions HS (High-speed Main) Mode LS (Low-speed Main) Mode LP (Low-power Main) Mode Unit SIp setup time (to SCKp↑)Note 1 tSIK1 4.0 V ≤ VDD ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ 81 81 479 ns 2.7 V ≤ VDD < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ 177 177 479 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 30 pF, Rb = 5.5 kΩ 479 479 479 ns SIp hold time (from SCKp↑)Note 1 tKSI1 4.0 V ≤ VDD ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ 19 19 19 ns 2.7 V ≤ VDD < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ 19 19 19 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 30 pF, Rb = 5.5 kΩ 19 19 19 ns Delay time from SCKp↓ to SOp outputNote 1 tKSO1 4.0 V ≤ VDD ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ 100 100 100 ns 2.7 V ≤ VDD < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ 195 195 195 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 30 pF, Rb = 5.5 kΩ 483 483 483 ns

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 76 of 121 Jun 30, 2026 8. In simplified SPI (CSI) communications in the master mode with devices operating at different voltage levels (1.8 V, Note 1. This setting applies when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 2. Use this setting with VDD ≥ Vb. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (withstand voltage of V DD) mode for the SOp pin and SCKp pin by using port input mode register (PIMg) and port output mode register (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.) Item Symbol Conditions HS (High-speed Main) Mode LS (Low-speed Main) Mode LP (Low-power Main) Mode Unit SIp setup time (to SCKp↓)Note 1 tSIK1 4.0 V ≤ VDD ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ 44 44 110 ns 2.7 V ≤ VDD < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ 44 44 110 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 30 pF, Rb = 5.5 kΩ 110 110 110 ns SIp hold time (from SCKp↓)Note 1 tKSI1 4.0 V ≤ VDD ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ 19 19 19 ns 2.7 V ≤ VDD < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ 19 19 19 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 30 pF, Rb = 5.5 kΩ 19 19 19 ns Delay time from SCKp↑ to SOp outputNote 1 tKSO1 4.0 V ≤ VDD ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ 25 25 25 ns 2.7 V ≤ VDD < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ 25 25 25 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 30 pF, Rb = 5.5 kΩ 25 25 25 ns

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 77 of 121 Jun 30, 2026 Connection in the simplified SPI (CSI) communications with devices operating at different voltage levels Remark 1. Rb[Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage Remark 2. p: CSI number (p = 00, 01, 20), m: Unit number, n: Channel number (mn = 00, 01, 03, 10, 11), g: PIM and POM number (g = 1, 3, 7) Remark 3. fMCK: Serial array unit operation clock frequency To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00) Remark 4. Communications by using CSI01 of 48-pin products, and CSI11 and CSI21 with devices operating at different voltage levels are not possible. Use other CSI channels to handle such communications. Timing of serial transfer in the simplified SPI (CSI) communications in the master mode with devices operating at different voltage levels when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1 SCKp SOp SCK SI SIp SO Vb Rb <Master> Vb Rb This MCU User device Input dataSIp SOp tKCY1 tKL1 tKH1 tSIK1 tKSI1 tKSO1 Output data SCKp

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 78 of 121 Jun 30, 2026 Timing of serial transfer in the simplified SPI (CSI) communications in the master mode with devices operating at different voltage levels when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0 Remark 1. p: CSI number (p = 00, 01, 20), m: Unit number, n: Channel number (mn = 00, 01, 03, 10, 11), g: PIM and POM number (g = 1, 3, 7) Remark 2. Communications by using CSI01 of 48-pin products, and CSI11 and CSI21 with devices operating at different voltage levels are not possible. Use other CSI channels to handle such communications. Input data Output data SIp SOp SCKp tKCY1 tKH1 tKL1 tSIK1 tKSI1 tKSO1

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 79 of 121 Jun 30, 2026 9. In simplified SPI (CSI) communications in the slave mode with devices operating at different voltage levels (1.8 V,

2.5 V, or 3 V) with the external SCKp clock

(Notes and Caution are listed on the next page, and Remarks are listed on the page after the next page.) Item Symbol Conditions HS (High-speed Main) Mode LS (Low-speed Main) Mode LP (Low-power Main) Mode Unit SCKp cycle time Note 1 tKCY2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V

24 MHz < fMCK 14/fMCK —— n s

20 MHz < fMCK ≤ 24 MHz 12/f MCK 12/fMCK —n s

8 MHz < fMCK ≤ 20 MHz 10/f MCK 10/fMCK —n s

4 MHz < fMCK ≤ 8 MHz 8/f MCK 8/fMCK —n s

fMCK ≤ 4 MHz 6/f MCK 6/fMCK 10/fMCK ns 2.7 V ≤ VDD < 4.0 V,

24 MHz < fMCK 20/fMCK —— n s

20 MHz < fMCK ≤ 24 MHz 16/f MCK 16/fMCK —n s

16 MHz < fMCK ≤ 20 MHz 14/f MCK 14/fMCK —n s

8 MHz < fMCK ≤ 16 MHz 12/f MCK 12/fMCK —n s

fMCK ≤ 4 MHz 6/f MCK 6/fMCK 10/fMCK ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2

24 MHz < fMCK 48/fMCK —— n s

20 MHz < fMCK ≤ 24 MHz 36/f MCK 36/fMCK —n s

16 MHz < fMCK ≤ 20 MHz 32/f MCK 32/fMCK —n s

8 MHz < fMCK ≤ 16 MHz 26/f MCK 26/fMCK —n s

4 MHz < fMCK ≤ 8 MHz 16/f MCK 16/fMCK —n s

fMCK ≤ 4 MHz 10/f MCK 10/fMCK 10/fMCK ns

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 80 of 121 Jun 30, 2026 9. In simplified SPI (CSI) communications in the slave mode with devices operating at different voltage levels (1.8 V, Note 1. Transfer rate in the SNOOZE mode is 1 Mbps at the maximum. Note 2. Use this setting with VDD ≥ Vb. Note 3. This setting applies when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” and SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 4. This setting applies when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (withstand voltage of V DD) mode for the SOp pin and SCKp pin by using port input mode register (PIMg) and port output mode register (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.) Item Symbol Conditions HS (High-speed Main) Mode LS (Low-speed Main) Mode LP (Low-power Main) Mode Unit SCKp high-level width, low-level width tKH2, tKL2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V tKCY2/2 - 12 tKCY2/2 - 12 tKCY2/2 - 50 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V tKCY2/2 - 18 tKCY2/2 - 18 tKCY2/2 - 50 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2 tKCY2/2 - 50 tKCY2/2 - 50 tKCY2/2 - 50 ns SIp setup time (to SCKp↑)Note 3 tSIK2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V 1/fMCK + 20 1/fMCK + 20 1/fMCK + 30 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V 1/fMCK + 20 1/fMCK + 20 1/fMCK + 30 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2 1/fMCK + 30 1/fMCK + 30 1/fMCK + 30 ns SIp hold time (from SCKp↑)Note 3 tKSI2 1/fMCK + 31 1/fMCK + 31 1/fMCK + 31 ns Delay time from SCKp↓ to SOp outputNote 4 tKSO2 4.0 V ≤ VDD ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ 2/fMCK + 120 2/fMCK + 120 2/fMCK + 573 ns 2.7 V ≤ VDD < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ 2/fMCK + 214 2/fMCK + 214 2/fMCK + 573 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 30 pF, Rb = 5.5 kΩ 2/fMCK + 573 2/fMCK + 573 2/fMCK + 573 ns

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 81 of 121 Jun 30, 2026 Connection in the simplified SPI (CSI) communications with devices operating at different voltage levels Remark 1. Rb[Ω]: Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance, Vb[V]: Communication line voltage Remark 2. p: CSI number (p = 00, 01, 20), m: Unit number, n: Channel number (mn = 00, 01, 03, 10, 11), g: PIM and POM number (g = 1, 3, 7) Remark 3. fMCK: Serial array unit operation clock frequency To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01, 03, 10, 11) Remark 4. Communications by using CSI01 of 48-pin products, and CSI11 and CSI21 with devices operating at different voltage levels are not possible. Use other CSI channels to handle such communications. Timing of serial transfer in the simplified SPI (CSI) communications in the slave mode with devices operating at different voltage levels when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1 SCKp SOp SCK SI SIp SO Vb Rb <Slave> This MCU User device SIp SOp SCKp Input data Output data tKCY2 tKH2tKL2 tSIK2 tKSI2 tKSO2

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 82 of 121 Jun 30, 2026 Timing of serial transfer in the simplified SPI (CSI) communications in the slave mode with devices operating at different voltage levels when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0 Remark 1. p: CSI number (p = 00, 01, 20), m: Unit number, n: Channel number (mn = 00, 01, 03, 10, 11), g: PIM and POM number (g = 1, 3, 7) Remark 2. Communications by using CSI01 of 48-pin products, and CSI11 and CSI21 with devices operating at different voltage levels are not possible. Use other CSI channels to handle such communications. Input data Output data SIp SOp SCKp tKCY2 tKL2tKH2 tSIK2 tKSI2 tKSO2

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 83 of 121 Jun 30, 2026 10. Simplified I2C communications with devices operating at different voltage levels (1.8 V, 2.5 V, or 3 V) Item Symbol Conditions HS (High-speed Main) Mode LS (Low-speed Main) Mode LP (Low-power Main) Mode Unit SCLr clock frequency f SCL 4.0 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 1000 Note 1 1000 Note 1 300 Note 1 kHz 2.7 V ≤ VDD < 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 1000 Note 1 1000 Note 1 300 Note 1 kHz 4.0 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 2.8 kΩ 400 Note 1 400 Note 1 300 Note 1 kHz 2.7 V ≤ VDD < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ 400 Note 1 400 Note 1 300 Note 1 kHz 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 100 pF, Rb = 5.5 kΩ 300 Note 1 300 Note 1 300 Note 1 kHz Hold time when SCLr is low tLOW 4.0 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 475 475 1550 ns 2.7 V ≤ VDD < 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 475 475 1550 ns 4.0 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 2.8 kΩ 1150 1550 1550 ns 2.7 V ≤ VDD < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ 1150 1550 1550 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 100 pF, Rb = 5.5 kΩ 1550 1550 1550 ns Hold time when SCLr is high tHIGH 4.0 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 245 245 610 ns 2.7 V ≤ VDD < 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 200 200 610 ns 4.0 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 2.8 kΩ 675 675 610 ns 2.7 V ≤ VDD < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ 600 600 610 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 100 pF, Rb = 5.5 kΩ 610 610 610 ns

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 84 of 121 Jun 30, 2026 10. Simplified I2C communications with devices operating at different voltage levels (1.8 V, 2.5 V, and 3 V) Note 1. The listed times must be no greater than fMCK/4. Note 2. Use this setting with VDD ≥ Vb. Note 3. Set fMCK so that it will not exceed the hold time when SCLr is low or high. Caution Select the TTL input buffer and the N-ch open drain output (withstand voltage of V DD) mode for the SDAr pin and the N-ch open drain output (withstand voltage of VDD) mode for the SCLr pin by using port input mode register (PIMg) and port output mode register (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.) Item Symbol Conditions HS (High-speed Main) Mode LS (Low-speed Main) Mode LP (Low-power Main) Mode Unit Data setup time (reception) tSU:DAT 4.0 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 1/fMCK + 135 Note 3 1/fMCK + 135 Note 3 1/fMCK + 190 Note 3 ns 2.7 V ≤ VDD < 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 1/fMCK + 135 Note 3 1/fMCK + 135 Note 3 1/fMCK + 190 Note 3 ns 4.0 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 2.8 kΩ 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 ns 2.7 V ≤ VDD < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 100 pF, Rb = 5.5 kΩ 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 ns Data hold time (transmission) tHD:DAT 4.0 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 0 305 0 305 0 305 ns 2.7 V ≤ VDD < 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 0 305 0 305 0 305 ns 4.0 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 2.8 kΩ 0 355 0 355 0 355 ns 2.7 V ≤ VDD < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ 0 355 0 355 0 355 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 100 pF, Rb = 5.5 kΩ 0 405 0 405 0 405 ns

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 85 of 121 Jun 30, 2026 Connection in the I2C communications with devices operating at different voltage levels Timing of serial transfer in the simplified I2C communications with devices operating at different voltage levels Remark 1. Rb[Ω]: Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance, Vb[V]: Communication line voltage Remark 2. r: IIC number (r = 00, 01, 11, 20, 21), g: PIM and POM number (g = 0, 1, 3, 7), POM number (h = 1, 5, 7) Remark 3. fMCK: Serial array unit operation clock frequency To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01, 03, 10,11) This MCU SDAr SCLr SDA SCL Vb Rb Vb Rb User device SDAr SCLr 1/fSCL tLOW tHIGH tSU:DATtHD:DAT

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 86 of 121 Jun 30, 2026

2.5.2 Serial interface UARTA

Caution Select the normal input buffer for the RxDAn pin and the normal output mode for the TxDAn pin by using port input mode register (PIMg) and port output mode register (POMg). Remark 1. g: PIM or POM number (g = 7) Remark 2. n: Unit number (n = 0) (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Item Symbol Conditions Min. Typ. Max. Unit Transfer rate 200 0 153600 bps

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 87 of 121 Jun 30, 2026

2.5.3 Serial interface IICA

I 2C standard mode Note 1. The first clock pulse is generated after this period when the start or restart condition is detected. Note 2. The maximum value of tHD:DAT applies to normal transfer. The clock stretching will be inserted on reception of an acknowledgment (ACK) signal. Caution The listed frequency and times apply even when the PIOR 2 bit in the peripheral I/O redirection register (PIOR) is 1. In such cases, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination. Remark The maximum value of communication line capacitance (Cb) and communication line pull-up resistor (Rb) are as follows. Cb = 400 pF, Rb = 2.7 kΩ (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Item Symbol Conditions Min. Typ. Max. Unit SCLA0 clock frequency fSCL Standard mode: fCLK ≥ 1 MHz 0 100 kHz Setup time of restart condition t SU:STA 4.7 µs Hold timeNote 1 tHD:STA 4.0 µs Hold time when SCLA0 is low t LOW 4.7 µs Hold time when SCLA0 is high t HIGH 4.0 µs Data setup time (reception) tSU:DAT 250 ns Data hold time (transmission)Note 2 tHD:DAT 03 .45 µs Setup time of stop condition tSU:STO 4.0 µs Bus-free time tBUF 4.7 µs

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 88 of 121 Jun 30, 2026 2. I 2C fast mode Note 1. The first clock pulse is generated after this period when the start or restart condition is detected. Note 2. The maximum value of tHD:DAT applies to normal transfer. The clock stretching will be inserted on reception of an acknowledgment (ACK) signal. Caution The values in the above table apply even when the PIOR2 bi t in the peripheral I/O redirection register (PIOR) is 1. In such cases, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination. Remark The maximum value of communication line capacitance (Cb) and communication line pull-up resistor (Rb) are as follows. Cb = 320 pF, Rb = 1.1 kΩ (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Item Symbol Conditions Min. Typ. Max. Unit SCLA0 clock frequency fSCL Fast mode: fCLK ≥ 3.5 MHz 1.8 V ≤ VDD ≤ 5.5 V 0 400 kHz Setup time of restart condition t SU:STA 1.8 V ≤ VDD ≤ 5.5 V 0.6 µs Hold timeNote 1 tHD:STA 1.8 V ≤ VDD ≤ 5.5 V 0.6 µs Hold time when SCLA0 is low t LOW 1.8 V ≤ VDD ≤ 5.5 V 1.3 µs Hold time when SCLA0 is high t HIGH 1.8 V ≤ VDD ≤ 5.5 V 0.6 µs Data setup time (reception) t SU:DAT 1.8 V ≤ VDD ≤ 5.5 V 100 ns Data hold time (transmission)Note 2 tHD:DAT 1.8 V ≤ VDD ≤ 5.5 V 0 0.9 µs Setup time of stop condition t SU:STO 1.8 V ≤ VDD ≤ 5.5 V 0.6 µs Bus-free time t BUF 1.8 V ≤ VDD ≤ 5.5 V 1.3 µs

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 89 of 121 Jun 30, 2026 3. I 2C fast mode plus Note 1. The first clock pulse is generated after this period when the start or restart condition is detected. Note 2. The maximum value of tHD:DAT applies to normal transfer. The clock stretching will be inserted on reception of an acknowledgment (ACK) signal. Caution The values in the above table apply even when the PIOR2 bi t in the peripheral I/O redirection register (PIOR) is 1. In such cases, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination. Remark The maximum value of communication line capacitance (Cb) and communication line pull-up resistor (Rb) are as follows. Cb = 120 pF, Rb = 1.1 kΩ IICA serial transfer timing Remark n = 0 (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Item Symbol Conditions Min. Typ. Max. Unit SCLA0 clock frequency fSCL Fast mode plus: fCLK ≥ 10 MHz 2.7 V ≤ VDD ≤ 5.5 V 0 1000 kHz Setup time of restart condition t SU:STA 2.7 V ≤ VDD ≤ 5.5 V 0.26 µs Hold timeNote 1 tHD:STA 2.7 V ≤ VDD ≤ 5.5 V 0.26 µs Hold time when SCLA0 is low t LOW 2.7 V ≤ VDD ≤ 5.5 V 0.5 µs Hold time when SCLA0 is high t HIGH 2.7 V ≤ VDD ≤ 5.5 V 0.26 µs Data setup time (reception) t SU:DAT 2.7 V ≤ VDD ≤ 5.5 V 50 ns Data hold time (transmission)Note 2 tHD:DAT 2.7 V ≤ VDD ≤ 5.5 V 0 0.45 µs Setup time of stop condition t SU:STO 2.7 V ≤ VDD ≤ 5.5 V 0.26 µs Bus-free time t BUF 2.7 V ≤ VDD ≤ 5.5 V 0.5 µs tSU:DATtHD:STA Restart condition SCLAn SDAAn tLOW tHIGH tR tF tSU:STA tHD:STA tSU:STO Stop condition Stop condition Start condition tHD:DAT tBUF

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 90 of 121 Jun 30, 2026

2.6 Characteristics of the Analog Circuits

Reference voltage (+) = AV REFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) = AVREFM/ANI1 (ADREFM = 1), conversion target: ANI2 to ANI7, internal reference voltage, temperature sensor output voltage, and TSCAP voltage of the CTSU Reference for the characteristics of the A/D converter Reference Voltage Input Channel Reference Voltage (+) = AVREFP Reference Voltage (–) = AVREFM Reference Voltage (+) = VDD Reference Voltage (–) = VSS Reference Voltage (+) = VBGR Reference Voltage (–) = AVREFM ANI16 to ANI19 See 2 in 2.6.1. Internal reference voltage, temperature sensor output voltage, and TSCAP voltage of the CTSU See 1 in 2.6.1.— (TA = -40 to +85°C, 1.6 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = 0 V, reference voltage (+) = AVREFP, reference voltage (-) = AVREFM = 0 V) (1/2) Item Symbol Conditions Min. Typ. Max. Unit Resolution RES 8 10 Bit Overall errorNote 1 AINL 10-bit resolution AVREFP = VDDNote 2 1.8 V ≤ AVREFP ≤ 5.5 V 1.2 ±3.5 LSB

1.6 V ≤ AVREFP ≤

5.5 VNote 3

1.2 ±7.0 LSB Conversion time t CONV 10-bit resolution conversion target: ANI2 to ANI7

3.6 V ≤ V

DD ≤ 5.5 V 2.125 39 µs 2.7 V ≤ VDD ≤ 5.5 V 3.1875 39 µs 1.8 V ≤ VDD ≤ 5.5 V 17 39 µs 1.6 V ≤ VDD ≤ 5.5 V 57 95 µs 10-bit resolution conversion target: Internal reference temperature sensor output voltage, and TSCAP voltage of the CTSU DD ≤ 5.5 V 2.375 39 µs 2.7 V ≤ VDD ≤ 5.5 V 3.5625 39 µs 1.8 V ≤ VDD ≤ 5.5 V 17 39 µs Zero-scale errorNotes 1, 4 EZS 10-bit resolution AVREFP = VDDNote 2 1.8 V ≤ AVREFP ≤ 5.5 V ±0.25 %FSR ±0.50 %FSR Full-scale errorNotes 1, 4 EFS 10-bit resolution AVREFP = VDDNote 2 1.8 V ≤ AVREFP ≤ 5.5 V ±0.25 %FSR ±0.50 %FSR Integral linearity errorNote 1 ILE 10-bit resolution AVREFP = VDDNote 2 1.8 V ≤ AVREFP ≤ 5.5 V ±2.5 LSB ±5.0 LSB Differential linearity errorNote 1 DLE 10-bit resolution AVREFP = VDDNote 2 1.8 V ≤ AVREFP ≤ 5.5 V ±1.5 LSB ±2.0 LSB

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 91 of 121 Jun 30, 2026 Note 1. This value does not include the quantization error (±1/2 LSB). Note 2. When AVREFP < VDD, the maximum values are as follows. Overall error: Add ±10 LSB to the maximum value when VDD = AVREFP. Zero-scale/full-scale error: Add ±0.05%FSR to the maximum value when VDD = AVREFP. Integral linearity error and differential linearity error: Add ±0.5 LSB to the maximum value when VDD = AVREFP. Note 3. The listed value applies when the settings of the maximum and minimum conversion time values are respectively 57 µs and 95 µs. Note 4. This value is indicated as a ratio (%FSR) to the full-scale value. Note 5. See 2.6.3 Characteristics of the temperature sensor and internal reference voltage. Analog input voltage V AIN ANI2 to ANI7 0 AVREFP V Internal reference voltage VBGRNote 5 V Temperature sensor output voltage VTMPS25Note 5 V TSCAP voltage of the CTSU VTSCAP V (TA = -40 to +85°C, 1.6 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = 0 V, reference voltage (+) = AVREFP, reference voltage (-) = AVREFM = 0 V) (2/2) Item Symbol Conditions Min. Typ. Max. Unit <R>

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 92 of 121 Jun 30, 2026 2. Reference voltage (+) = AV REFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (–) = AVREFM/ANI1 (ADREFM = 1), conversion target: ANI16 to ANI19 Note 1. This value does not include the quantization error (±1/2 LSB). Note 2. When AVREFP < VDD, the maximum values are as follows. Overall error: Add ±4.0 LSB to the maximum value when VDD = AVREFP. Zero-scale/full-scale error: Add ±0.20%FSR to the maximum value when VDD = AVREFP. Integral linearity error/differential linearity error: Add ±2.0 LSB to the maximum value when VDD = AVREFP. Note 3. The listed value applies when the settings of the maximum and minimum conversion time values are respectively 57 µs and 95 µs. Note 4. This value is indicated as a ratio (%FSR) to the full-scale value. (TA = -40 to +85°C, 1.6 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = 0 V, reference voltage (+) = AVREFP, reference voltage (–) = AVREFM = 0 V) Item Symbol Conditions Min. Typ. Max. Unit Resolution RES 8 10 Bit Overall errorNote 1 AINL 10-bit resolution AVREFP = VDDNote 2 1.8 V ≤ AVREFP ≤ 5.5 V 1.2 ±5.0 LSB 1.6 V ≤ AVREFP ≤ 5.5 V Note 3 1.2 ±5.0 Conversion time t CONV 10-bit resolution conversion target: ANI16 to ANI19 DD ≤ 5.5 V 2.125 39 µs 2.7 V ≤ VDD ≤ 5.5 V 3.1875 39 µs 1.8 V ≤ VDD ≤ 5.5 V 17 39 µs 1.6 V ≤ VDD ≤ 5.5 V 57 95 Zero-scale errorNotes 1, 4 EZS 10-bit resolution AVREFP = VDDNote 2 1.8 V ≤ AVREFP ≤ 5.5 V ±0.35 %FSR 1.6 V ≤ AVREFP ≤ 5.5 V Note 3 ±0.60 Full-scale errorNotes 1, 4 EFS 10-bit resolution AVREFP = VDDNote 2 1.8 V ≤ AVREFP ≤ 5.5 V ±0.35 %FSR 1.6 V ≤ AVREFP ≤ 5.5 V Note 3 ±0.60 Integral linearity errorNote 1 ILE 10-bit resolution AVREFP = VDDNote 2 1.8 V ≤ AVREFP ≤ 5.5 V ±3.5 LSB 1.6 V ≤ AVREFP ≤ 5.5 V Note 3 ±6.0 Differential linearity errorNote 1 DLE 10-bit resolution AVREFP = VDDNote 2 1.8 V ≤ AVREFP ≤ 5.5 V ±2.0 LSB 1.6 V ≤ AVREFP ≤ 5.5 V Note 3 ±2.5 Analog input voltage V AIN ANI16 to ANI19 0 AVREFP V

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 93 of 121 Jun 30, 2026 3. Reference voltage (+) = V DD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (–) = VSS (ADREFM = 0), conversion target: ANI0 to ANI7, and ANI16 to ANI19, internal reference voltageNote 1, temperature sensor output voltageNote 1, TSCAP voltage of the CTSU Note 1. If the internal reference voltage or temperature sensor output voltage is to be A/D converted, VDD must be at least 1.8 V. Note 2. This value does not include the quantization error (±1/2 LSB). Note 3. The listed value applies when the settings of the maximum and minimum conversion time values are respectively 57 µs and 95 µs. Note 4. This value is indicated as a ratio (%FSR) to the full-scale value. Note 5. See 2.6.3 Characteristics of the temperature sensor and internal reference voltage. (TA = -40 to +85°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V, reference voltage (+) = VDD, reference voltage (–) = VSS) Item Symbol Conditions Min. Typ. Max. Unit Resolution RES 8 10 Bit Overall errorNote 2 AINL 10-bit resolution 1.8 V ≤ VDD ≤ 5.5 V 1.2 ±7.0 LSB 1.6 V ≤ VDD ≤ 5.5 VNote 3 1.2 ±10.5 LSB Conversion time t CONV 10-bit resolution conversion target: ANI0 to ANI7, ANI16 to ANI19 3.6 V ≤ VDD ≤ 5.5 V 2.125 39 µs 2.7 V ≤ VDD ≤ 5.5 V 3.1875 39 µs 1.8 V ≤ VDD ≤ 5.5 V 17 39 µs 1.6 V ≤ VDD ≤ 5.5 V 57 95 µs 10-bit resolution conversion target: Internal reference voltage, temperature sensor output voltage, and TSCAP voltage of the CTSU DD ≤ 5.5 V 2.375 39 µs 2.7 V ≤ VDD ≤ 5.5 V 3.5625 39 µs 1.8 V ≤ VDD ≤ 5.5 V 17 39 µs Zero-scale errorNotes 2, 4 EZS 10-bit resolution 1.8 V ≤ VDD ≤ 5.5 V ±0.60 %FSR 1.6 V ≤ VDD ≤ 5.5 VNote 3 ±0.85 %FSR Full-scale errorNotes 2, 4 EFS 10-bit resolution 1.8 V ≤ VDD ≤ 5.5 V ±0.60 %FSR 1.6 V ≤ VDD ≤ 5.5 VNote 3 ±0.85 %FSR Integral linearity errorNote 2 ILE 10-bit resolution 1.8 V ≤ VDD ≤ 5.5 V ±4.0 LSB 1.6 V ≤ VDD ≤ 5.5 VNote 3 ±6.0 LSB Differential linearity errorNote 2 DLE 10-bit resolution 1.8 V ≤ VDD ≤ 5.5 V ±2.0 LSB 1.6 V ≤ VDD ≤ 5.5 VNote 3 ±2.5 LSB Analog input voltage V AIN ANI0 to ANI7, ANI16 to ANI19 0 VDD V Internal reference voltage (1.8 V ≤ V DD ≤ 5.5 V) VBGRNote 5 V Temperature sensor output voltage VTMPS25Note 5 V TSCAP voltage of the CTSU VTSCAP V

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 94 of 121 Jun 30, 2026 4. Reference voltage (+) = V DD (ADREFP1 = 1, ADREFP0 = 0), reference voltage (–) = AVREFM/ANI1 (ADREFM = 1), conversion target: ANI0, ANI2 to ANI7, ANI16 to ANI19 Note 1. See 2.6.3 Characteristics of the temperature sensor and internal reference voltage. Note 2. When reference voltage (–) = VSS, the maximum values are as follows. Zero-scale error: Add ±0.35%FSR to the maximum value when reference voltage (–) = AVREFM. Integral linearity error: Add ±0.5 LSB to the maximum value when reference voltage (–) = AVREFM. Differential linearity error: Add ±0.2 LSB to the maximum value when reference voltage (–) = AVREFM. Note 3. This value does not include the quantization error (±1/2 LSB). Note 4. This value is indicated as a ratio (%FSR) to the full-scale value. (TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V, reference voltage (+) = VBGRNote 1, reference voltage (–) = AVREFMNote 2 = 0 V) Item Symbol Conditions Min. Typ. Max. Unit Resolution RES 8 Bit Conversion time tCONV 17 39 µs Zero-scale errorNotes 3, 4 EZS ±0.60 %FSR Integral linearity errorNote 3 ILE ±2.0 LSB Differential linearity errorNote 3 DLE ±1.0 LSB Analog input voltage V AIN 0 VBGRNote 1 V

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Reference voltage (+) = AV REFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) = AVREFM/ANI1 (ADREFM = 1), conversion target: ANI2 to ANI7, internal reference voltage, temperature sensor output voltage, and TSCAP voltage of the CTSU Note 1. This value does not include the quantization error (±1/2 LSB). Note 2. When AVREFP < VDD, the maximum values are as follows. Overall error: Add ±10 LSB to the maximum value when VDD = AVREFP. Zero-scale/full-scale error: Add ±0.05%FSR to the maximum value when VDD = AVREFP. Integral linearity error and differential linearity error: Add ±0.5 LSB to the maximum value when VDD = AVREFP. Note 3. This value is indicated as a ratio (%FSR) to the full-scale value. Note 4. See 2.6.3 Characteristics of the temperature sensor and internal reference voltage. Reference for the characteristics of the A/D converter Reference Voltage Input Channel Reference Voltage (+) = AVREFP Reference Voltage (–) = AVREFM Reference Voltage (+) = VDD Reference Voltage (–) = VSS Reference Voltage (+) = VBGR Reference Voltage (–) = AVREFM ANI16 to ANI19 See 2 in 2.6.2. Internal reference voltage, temperature sensor output voltage, and TSCAP voltage of the CTSU See 1 in 2.6.2.— (TA = -40 to +105°C, 2.4 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = 0 V, reference voltage (+) = AVREFP, reference voltage (-) = AVREFM = 0 V) Item Symbol Conditions Min. Typ. Max. Unit Resolution RES 8 10 Bit Overall errorNote 1 AINL 10-bit resolution AVREFP = VDDNote 2 2.4 V ≤ AVREFP ≤ 5.5 V 1.2 ±3.5 LSB Conversion time t CONV 10-bit resolution conversion target: ANI2 to ANI7 3.6 V ≤ VDD ≤ 5.5 V 2.125 39 µs 2.7 V ≤ VDD ≤ 5.5 V 3.1875 39 µs 2.4 V ≤ VDD ≤ 5.5 V 17 39 µs 10-bit resolution conversion target: Internal reference voltage, temperature sensor output voltage, and TSCAP voltage of the CTSU

DD ≤ 5.5 V 2.375 39 µs 2.7 V ≤ VDD ≤ 5.5 V 3.5625 39 µs 2.4 V ≤ VDD ≤ 5.5 V 17 39 µs Zero-scale errorNotes 1, 3 EZS 10-bit resolution AVREFP = VDDNote 2 2.4 V ≤ AVREFP ≤ 5.5 V ±0.25 %FSR Full-scale errorNotes 1, 3 EFS 10-bit resolution AV REFP = VDDNote 2 2.4 V ≤ AVREFP ≤ 5.5 V ±0.25 %FSR Integral linearity errorNote 1 ILE 10-bit resolution AVREFP = VDDNote 2 2.4 V ≤ AVREFP ≤ 5.5 V ±2.5 LSB Differential linearity errorNote 1 DLE 10-bit resolution AVREFP = VDDNote 2 2.4 V ≤ AVREFP ≤ 5.5 V ±1.5 LSB Analog input voltage V AIN ANI2 to ANI7 0 AVREFP V Internal reference voltage VBGRNote 4 V Temperature sensor output voltage VTMPS25Note 4 V TSCAP voltage of the CTSU V TSCAP V <R>

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 96 of 121 Jun 30, 2026 2. Reference voltage (+) = AV REFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (–) = AVREFM/ANI1 (ADREFM = 1), conversion target: ANI16 to ANI19 Note 1. This value does not include the quantization error (±1/2 LSB). Note 2. When AVREFP < VDD, the maximum values are as follows. Overall error: Add ±4.0 LSB to the maximum value when VDD = AVREFP. Zero-scale/full-scale error: Add ±0.20%FSR to the maximum value when VDD = AVREFP. Integral linearity error/differential linearity error: Add ±2.0 LSB to the maximum value when VDD = AVREFP. Note 3. This value is indicated as a ratio (%FSR) to the full-scale value. (TA = -40 to +105°C, 2.4 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = 0 V, reference voltage (+) = AVREFP, reference voltage (–) = AVREFM = 0 V) Item Symbol Conditions Min. Typ. Max. Unit Resolution RES 8 10 Bit Overall errorNote 1 AINL 10-bit resolution AVREFP = VDDNote 2 2.4 V ≤ AVREFP ≤ 5.5 V 1.2 ±5.0 LSB Conversion time t CONV 10-bit resolution conversion target: ANI16 to ANI19 DD ≤ 5.5 V 2.125 39 µs 2.7 V ≤ VDD ≤ 5.5 V 3.1875 39 µs 2.4 V ≤ VDD ≤ 5.5 V 17 39 µs Zero-scale errorNotes 1, 3 EZS 10-bit resolution AVREFP = VDDNote 2 2.4 V ≤ AVREFP ≤ 5.5 V ±0.35 %FSR Full-scale errorNotes 1, 3 EFS 10-bit resolution AVREFP = VDDNote 2 2.4 V ≤ AVREFP ≤ 5.5 V ±0.35 %FSR Integral linearity errorNote 1 ILE 10-bit resolution AVREFP = VDDNote 2 2.4 V ≤ AVREFP ≤ 5.5 V ±3.5 LSB Differential linearity errorNote 1 DLE 10-bit resolution AVREFP = VDDNote 2 2.4 V ≤ AVREFP ≤ 5.5 V ±2.0 LSB Analog input voltage V AIN ANI16 to ANI19 0 AVREFP V

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 97 of 121 Jun 30, 2026 3. Reference voltage (+) = V DD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (–) = VSS (ADREFM = 0), conversion target: ANI0 to ANI7, and ANI16 to ANI19, internal reference voltage, temperature sensor output voltage, and TSCAP voltage of the CTSU Note 1. This value does not include the quantization error (±1/2 LSB). Note 2. This value is indicated as a ratio (%FSR) to the full-scale value. Note 3. See 2.6.3 Characteristics of the temperature sensor and internal reference voltage. (TA = -40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V, reference voltage (+) = VDD, reference voltage (–) = VSS) Item Symbol Conditions Min. Typ. Max. Unit Resolution RES 8 10 Bit Overall errorNote 1 AINL 10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V 1.2 ±7.0 LSB Conversion time t CONV 10-bit resolution conversion target: ANI0 to ANI7, ANI16 to ANI19 3.6 V ≤ VDD ≤ 5.5 V 2.125 39 µs 2.7 V ≤ VDD ≤ 5.5 V 3.1875 39 µs 2.4 V ≤ VDD ≤ 5.5 V 17 39 µs 10-bit resolution conversion target: Internal reference voltage, temperature sensor output voltage, and and TSCAP voltage of the CTSU DD ≤ 5.5 V 2.375 39 µs 2.7 V ≤ VDD ≤ 5.5 V 3.5625 39 µs 2.4 V ≤ VDD ≤ 5.5 V 17 39 µs Zero-scale errorNotes 1, 2 EZS 10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±0.60 %FSR Full-scale errorNotes 1, 2 EFS 10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±0.60 %FSR Integral linearity errorNote 1 ILE 10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±4.0 LSB Differential linearity errorNote 1 DLE 10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±2.0 LSB Analog input voltage V AIN ANI0 to ANI7, ANI16 to ANI19 0 VDD V Internal reference voltage VBGRNote 3 V Temperature sensor output voltage VTMPS25Note 3 V TSCAP voltage of the CTSU V TSCAP V

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 98 of 121 Jun 30, 2026 4. Reference voltage (+) = V DD (ADREFP1 = 1, ADREFP0 = 0), reference voltage (–) = AVREFM/ANI1 (ADREFM = 1), conversion target: ANI0, ANI2 to ANI7, ANI16 to ANI19 Note 1. See 2.6.3 Characteristics of the temperature sensor and internal reference voltage. Note 2. When reference voltage (–) = VSS, the maximum values are as follows. Zero-scale error: Add ±0.35%FSR to the maximum value when reference voltage (–) = AVREFM. Integral linearity error: Add ±0.5 LSB to the maximum value when reference voltage (–) = AVREFM. Differential linearity error: Add ±0.2 LSB to the maximum value when reference voltage (–) = AVREFM. Note 3. This value does not include the quantization error (±1/2 LSB). Note 4. This value is indicated as a ratio (%FSR) to the full-scale value. (TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V, reference voltage (+) = VBGRNote 1, reference voltage (–) = AVREFMNote 2 = 0 V) Item Symbol Conditions Min. Typ. Max. Unit Resolution RES 8 Bit Conversion time tCONV 17 39 µs Zero-scale errorNotes 3, 4 EZS ±0.60 %FSR Integral linearity errorNote 3 ILE ±2.0 LSB Differential linearity errorNote 3 DLE ±1.0 LSB Analog input voltage V AIN 0 VBGRNote 1 V

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 99 of 121 Jun 30, 2026

2.6.3 Characteristics of t he temperature sensor and internal reference voltage

(TA = -40 to +105°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Item Symbol Conditions Min. Typ. Max. Unit Temperature sensor output voltage VTMPS25 Setting ADS register = 80H, TA = +25°C 1.05 V Internal reference voltage V BGR Setting ADS register = 81H 1.42 1.48 1.54 V Temperature coefficient F VTMPS Temperature dependency of the temperature sensor voltage -3.3 mV/°C Operation stabilization wait time t AMP 5µ s

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 100 of 121 Jun 30, 2026

2.6.4 Characteristics of the POR circuit

Note This width is the minimum time required for a POR reset when VDD falls below VPDR. This width is also the minimum time required for a POR reset from when VDD falls below 0.7 V to when VDD exceeds VPOR in the STOP mode or while the main system clock is stopped through setting the HIOSTOP and MSTOP bits in the clock operation status control register (CSC). (TA = -40 to +105°C, VSS = 0 V) Item Symbol Conditions Min. Typ. Max. Unit Detection voltage VPOR, VPDR 1.43 1.50 1.57 V Minimum pulse widthNote TPW 300 µs TPW VPOR VPDR or 0.7 V Supply voltage (VDD)

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2.6.5 Characteristics of the LVD circuit

LVD0 Detection Voltage in the Reset Mode and Interrupt Mode (TA = -40 to +105°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V) Item Symbol Conditions Min. Typ. Max. Unit Detection voltage Supply voltage level V LVD00 The power supply voltage is rising. 3.84 3.96 4.08 V The power supply voltage is falling. 3.76 3.88 4.00 V VLVD01 The power supply voltage is rising. 2.88 2.97 3.06 V The power supply voltage is falling. 2.82 2.91 3.00 V V LVD02 The power supply voltage is rising. 2.59 2.67 2.75 V The power supply voltage is falling. 2.54 2.62 2.70 V V LVD03 The power supply voltage is rising. 2.31 2.38 2.45 V The power supply voltage is falling. 2.26 2.33 2.40 V V LVD04 The power supply voltage is rising. 1.84 1.90 1.95 V The power supply voltage is falling. 1.80 1.86 1.91 V V LVD05 The power supply voltage is rising. 1.64 1.69 1.74 V The power supply voltage is falling. 1.60 1.65 1.70 V Minimum pulse width t LW 500 µs Detection delay time 500 µs

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 102 of 121 Jun 30, 2026 2. LVD1 Detection Voltage of Reset Mode and Interrupt Mode Note This setting can only be used when LVD0 is disabled. (TA = -40 to +105°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V) Item Symbol Conditions Min. Typ. Max. Unit Detection voltage Supply voltage level V LVD10 The power supply voltage is rising. 4.08 4.16 4.24 V The power supply voltage is falling. 4.00 4.08 4.16 V VLVD11 The power supply voltage is rising. 3.88 3.96 4.04 V The power supply voltage is falling. 3.80 3.88 3.96 V V LVD12 The power supply voltage is rising. 3.68 3.75 3.82 V The power supply voltage is falling. 3.60 3.67 3.74 V V LVD13 The power supply voltage is rising. 3.48 3.55 3.62 V The power supply voltage is falling. 3.40 3.47 3.54 V V LVD14 The power supply voltage is rising. 3.28 3.35 3.42 V The power supply voltage is falling. 3.20 3.27 3.34 V V LVD15 The power supply voltage is rising. 3.07 3.13 3.19 V The power supply voltage is falling. 3.00 3.06 3.12 V V LVD16 The power supply voltage is rising. 2.91 2.97 3.03 V The power supply voltage is falling. 2.85 2.91 2.97 V V LVD17 The power supply voltage is rising. 2.76 2.82 2.87 V The power supply voltage is falling. 2.70 2.76 2.81 V V LVD18 The power supply voltage is rising. 2.61 2.66 2.71 V The power supply voltage is falling. 2.55 2.60 2.65 V V LVD19 The power supply voltage is rising. 2.45 2.50 2.55 V The power supply voltage is falling. 2.40 2.45 2.50 V V LVD110 The power supply voltage is rising. 2.35 2.40 2.45 V The power supply voltage is falling. 2.30 2.35 2.40 V V LVD111 The power supply voltage is rising. 2.25 2.30 2.34 V The power supply voltage is falling. 2.20 2.25 2.29 V V LVD112 The power supply voltage is rising. 2.15 2.20 2.24 V The power supply voltage is falling. 2.10 2.15 2.19 V V LVD113 The power supply voltage is rising. 2.05 2.09 2.13 V The power supply voltage is falling. 2.00 2.04 2.08 V V LVD114 The power supply voltage is rising. 1.94 1.98 2.02 V The power supply voltage is falling. 1.90 1.94 1.98 V V LVD115 Note The power supply voltage is rising. 1.84 1.88 1.91 V The power supply voltage is falling. 1.80 1.84 1.87 V V LVD116 Note The power supply voltage is rising. 1.74 1.78 1.81 V The power supply voltage is falling. 1.70 1.74 1.77 V V LVD117 Note The power supply voltage is rising. 1.64 1.67 1.70 V The power supply voltage is falling. 1.60 1.63 1.66 V Minimum pulse width t LW 500 µs Detection delay time 500 µs

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2.6.6 Characteristics of the rising slope of the power supply voltage

Caution Make sure to keep the internal reset state by LVD0 or an external reset until V DD reaches the operating voltage range shown in AC characteristics. (TA = -40 to +105°C, VSS = 0 V) Item Symbol Conditions Min. Typ. Max. Unit Power supply voltage rising slope SVDD 54 V/ms

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2.7 Characteristics of Retention of RAM Data

Note This voltage depends on the POR detection voltage. When the voltage drops, the data in RAM are retained until a POR is applied, but are not retained following a POR.

2.8 Characteristics of Fl ash Memory Programming

Note 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite. Note 2. The listed numbers of times apply when using flash memory programmer and Renesas Electronics self-programming library. Note 3. These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics Corporation. (TA = -40 to +105°C, VSS = 0V) Item Symbol Conditions Min. Typ. Max. Unit Data retention supply voltage V DDDR 1.43Note 5.5 V (TA = -40 to +105°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Item Symbol Conditions Min. Typ. Max. Unit CPU/peripheral hardware clock frequency f CLK 13 2 MHz Number of code flash memory rewritesNotes 1, 2, 3 Cerwr Retained for 20 years TA = +85°C 1,000 Times Number of data flash memory rewritesNotes 1, 2, 3 Retained for 1 year T A = +25°C 1,000,000 Retained for 5 years TA = +85°C 100,000 Retained for 20 years TA = +85°C 10,000 VDD STOP instruction execution Standby release signal (interrupt request) STOP mode RAM data retention Operation mode VDDDR

RL78/G22 2. Electrical Characteristics R01DS0424EJ0120 Rev.1.20 Page 105 of 121 Jun 30, 2026 1. Code flash memory Caution The listed values do not include the time until the operations of the flash memory start following execution of an instruction by software. 2. Data flash memory Caution The listed values do not include the time until the operations of the flash memory start following execution of an instruction by software. (TA = -40 to +105°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Item Symbol fCLK = 1 MHz f CLK = 2 MHz, 3 MHz 4 MHz ≤ fCLK < 8 MHz 8 MHz ≤ fCLK < 32 MHz f CLK = 32 MHz Unit Programming time Blank checking time 4 bytes t Time taken to forcibly stop the erasure t Time until programming starts following cancellation of the STOP instruction (TA = -40 to +105°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Item Symbol fCLK = 1 MHz f CLK = 2 MHz, 3 MHz 4 MHz ≤ fCLK < 8 MHz 8 MHz ≤ fCLK < 32 MHz f CLK = 32 MHz Unit Programming time 1 byte t Blank checking time 1 byte t Time taken to forcibly stop the erasure t Time until programming starts following cancellation of the STOP instruction Time until reading starts following setting of DFLCTL.DFLEN to 1

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2.9 Dedicated Flash Memory Pr ogrammer Communication (UART)

2.10 Timing of Entry to Flas h Memory Programming Modes

<1> The low level is input to the TOOL0 pin. <2> The external reset is released. Note that the POR and LVD reset must be released before the external reset is released. <3> The TOOL0 pin is set to the high level. <4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting. (TA = -40 to +105°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Item Symbol Conditions Min. Typ. Max. Unit Transfer rate During serial programming 115,200 1,000,000 bps (TA = -40 to +105°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Item Symbol Conditions Min. Typ. Max. Unit Time to complete the communication for the initial setting after the external reset is released t SUINIT POR and LVD reset must be released before the external reset is released. 100 ms Time to release the external reset after the TOOL0 pin is set to the low level t SU POR and LVD reset must be released before the external reset is released. 10 µs Time to hold the TOOL0 pin at the low level after the external reset is released (the processing time of the firmware to control the flash memory is not included) t HD POR and LVD reset must be released before the external reset is released. 1m s Remark tSUINIT: The time during which the communications for the initial setting must be completed within 100 ms after the external reset is released. tSU: Time to release the external reset after the TOOL0 pin is set to the low level tHD: Time to hold the TOOL0 pin at the low level after the external reset is released. It does not include the processing time of the firmware to control the flash memory. RESET TOOL0 tSU <4> tSUINIT 723 µs + tHD processing time 1-byte data for setting mode . . .

RL78/G22 3. Package Drawings R01DS0424EJ0120 Rev.1.20 Page 107 of 121 Jun 30, 2026 3. Package Drawings 3.1 16-pin Products 912 12 9 Reference Symbol Dimension in Millimeters Min. Nom. Max. A 䠉䠉 0.80 A1 0.00 0.02 0.05 A3 0.203 REF. b 0.20 0.25 0.30 D 3.00 BSC E 3.00 BSC e 0.50 BSC L 0 . 3 00 . 3 50 . 4 0 K 0.20 䠉䠉 D2 1.65 1.70 1.75 E2 1.65 1.70 1.75 aaa 0.15 bbb 0.10 ccc 0.10 ddd 0.05 eee 0.08 fff 0.10 P-HWQFN016-3x3-0.50 PWQN0016KD-A 0.02 SEATING PLANE C aaa C EXPOSED DIE PAD D AB E INDEX AREA (D/2 X E/2) aaa C ccc C (A3) A1 eee C 16X A e b(16X) bbb C A B ddd C fff C A B fff C A B L(16X) K(16X)

RL78/G22 3. Package Drawings R01DS0424EJ0120 Rev.1.20 Page 108 of 121 Jun 30, 2026 3.2 20-pin Products RENESAS Code P-LSSOP20-4.4x6.5-0.65 PLSP0020JB-A P20MA-65-NAA-1 0.1 1 10 detail of lead end ITEM DIMENSIONS D E e A L c y bp 0.10 0.10 0 to 10 A A1 ey HE c 6.50 4.40 0.20 0.10 6.40 0.100.10 1.45 MAX. 1.15 0.65 0.12 0.10 0.050.22 0.05 0.020.15 0.50 0.20 bp HE E D L NOTE 1.Dimensions “ 1” and “ 2” 2.Dimension “ ” does not include tr MASS (TYP.) [g] 2012 Renesas Electronics Corporation. All rights reserved. (UNIT:mm)

RL78/G22 3. Package Drawings R01DS0424EJ0120 Rev.1.20 Page 109 of 121 Jun 30, 2026 3.3 24-pin Products P-HWQFN24-4x4-0.50 PWQN0024KG-A RENESAS Code MASS (TYP.) [g] 0.04

RL78/G22 3. Package Drawings R01DS0424EJ0120 Rev.1.20 Page 110 of 121 Jun 30, 2026 3.4 25-pin Products

RL78/G22 3. Package Drawings R01DS0424EJ0120 Rev.1.20 Page 111 of 121 Jun 30, 2026 3.5 30-pin Products P-LSSOP30-0300-0.65 PLSP0030JB-B S30MC-65-5A4-3 0.18 S S H J T I G D E F C B K P L U N ITEM B C I L M N A K D E F G H J P 30 16 11 5 A detail of lead end MM T MILLIMETERS 0.65 (T.P .) 0.45 MAX. 0.13 0.5 6.1p0.2 0.10 9.85p0.15 0.17p0.03 0.1p0.05 0.24 1.3p0.1 8.1p0.2 1.2 0.08 0.07 1.0p0.2 0.25 0.6p0.15U NOTE Each lead centerline is located within 0.13 mm of its true position (T.P .) at maximum material condition. 2012 Renesas Electronics Corporation. All rights reserved.

RL78/G22 3. Package Drawings R01DS0424EJ0120 Rev.1.20 Page 112 of 121 Jun 30, 2026 3.6 32-pin Products INDEX AREA (D/2 X E/2) D E SEATING PLANE ccc C 32X bbb C A B ddd C e b(32X) 1724 L(32X) K(32X) C aaa C B aaa C (A3) A1A eee C fff C A B fff C A B A 24 17 Reference Symbol Dimension in Millimeters Min. Nom. Max. A 䠉䠉 0.80 A1 0.00 0.02 0.05 A3 0.203 REF. b 0 . 1 80 . 2 50 . 3 0 D 5.00 BSC E 5.00 BSC e 0.50 BSC L 0 . 3 50 . 4 00 . 4 5 K0 . 2 0 䠉䠉 D2 3.15 3.20 3.25 E2 3.15 3.20 3.25 aaa 0.15 bbb 0.10 ccc 0.10 ddd 0.05 eee 0.08 fff 0.10 P-HWQFN032-5x5-0.50 PWQN0032KE-A 0.06

RL78/G22 3. Package Drawings R01DS0424EJ0120 Rev.1.20 Page 113 of 121 Jun 30, 2026 2012 Renesas Electronics Corporation. All rights reserved. 0.145 ±0.055 (UNIT:mm) ITEM DIMENSIONS D E HD HE A 7.00±0.10 7.00±0.10 9.00±0.20 9.00±0.20 1.70 MAX. 0.10±0.10 1.40 c θ e x y 0.80 0.20 0.10 L 0.50±0.20 0° to 8° 0.37±0.05b NOTE 1.Dimensions “ 1” and “ 2” do not include mold flash. 2.Dimension “ 3” does not include trim offset. y e x bM θ L c HD HE A D E detail of lead end 32 9 P-LQFP32-7x7-0.80 PLQP0032GB-A P32GA-80-GBT -1 0.2

RL78/G22 3. Package Drawings R01DS0424EJ0120 Rev.1.20 Page 114 of 121 Jun 30, 2026 P-LQFP32-7x7-0.80 PLQP0032GE-A 0.18 䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉 /g84 䠉䠉䠉䠉䠉䠉

RL78/G22 3. Package Drawings R01DS0424EJ0120 Rev.1.20 Page 115 of 121 Jun 30, 2026 3.7 36-pin Products

RL78/G22 3. Package Drawings R01DS0424EJ0120 Rev.1.20 Page 116 of 121 Jun 30, 2026 3.8 40-pin Products INDEX AREA (D/2 X E/2) D SEATING PLANE ccc C bbb C A B ddd C e b(40X) L(40X) K(40X) C aaa C B aaa C (A3) A1A eee C fff C A B fff C A B A EXPOSED DIE PAD 11 0 2130 30 21 101 E 40X Reference Symbol Dimension in Millimeters Min. Nom. Max. A 䠉䠉 0.80 A1 0.00 0.02 0.05 A3 0.203 REF. b 0 . 1 80 . 2 50 . 3 0 D 6.00 BSC E 6.00 BSC e 0.50 BSC L 0 . 3 00 . 4 00 . 5 0 K 0.20 䠉䠉 D2 4.45 4.50 4.55 E2 4.45 4.50 4.55 aaa 0.15 bbb 0.10 ccc 0.10 ddd 0.05 eee 0.08 fff 0.10 P-HWQFN040-6x6-0.50 PWQN0040KD-A 0.08

RL78/G22 3. Package Drawings R01DS0424EJ0120 Rev.1.20 Page 117 of 121 Jun 30, 2026 3.9 44-pin Products

RL78/G22 3. Package Drawings R01DS0424EJ0120 Rev.1.20 Page 118 of 121 Jun 30, 2026 P-LQFP044-10x10-0.80 PLQP0044GE-A 0.34 䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉 /g84 䠉䠉䠉䠉䠉䠉

RL78/G22 3. Package Drawings R01DS0424EJ0120 Rev.1.20 Page 119 of 121 Jun 30, 2026 3.10 48-pin Products

RL78/G22 3. Package Drawings R01DS0424EJ0120 Rev.1.20 Page 120 of 121 Jun 30, 2026 P-LFQFP48-7x7-0.50 PLQP0048KL-A 0.18 䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉 /g84 䠉䠉䠉䠉䠉䠉

RL78/G22 3. Package Drawings R01DS0424EJ0120 Rev.1.20 Page 121 of 121 Jun 30, 2026 INDEX AREA (D/2 X E/2) D SEATING PLANE ccc C bbb C A B ddd C e b(48X) L(48X) K(48X) C aaa C B aaa C (A3) A1A eee C fff C A B fff C A B A EXPOSED DIE PAD 11 2 2536 E 48X 36 25 121 37 24 Reference Symbol Dimension in Millimeters Min. Nom. Max. A 䠉䠉 0.80 A1 0.00 0.02 0.05 A3 0.203 REF. b 0.20 0.25 0.30 D 7.00 BSC E 7.00 BSC e 0.50 BSC L 0 . 3 00 . 4 00 . 5 0 K 0.20 䠉䠉 D2 5.25 5.30 5.35 E2 5.25 5.30 5.35 aaa 0.15 bbb 0.10 ccc 0.10 ddd 0.05 eee 0.08 fff 0.10 P-HWQFN048-7x7-0.50 PWQN0048KC-A 0.13 g

Rev. Date

Description

1.00 Dec 28, 2022 — First edition issued

1.10 Jun 12, 2024 p.4 Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G22 was modified. p.5 Table 1 - 1 List of Ordering Part Numbers was modified. p.54 2.4 AC Characteristics was modified. p.114 3.6 32-pin Products: The figure was added. p.118 3.9 44-pin Products: The figure was added. p.120 3.10 48-pin Products: The figure was added. 1.20 Jun 30, 2026 p.22 Table 1 - 9 Multiplexed Pin Functions of the 40-pin Products (1/2) was modified. p.25 Table 1 - 10 Multiplexed Pin Functions of the 44-pin Products (1/2) was modified. p.46 2.3.2 Characteristics of the supply current: Notes 1 to 4 were modified. p.48 2.3.2 Characteristics of the supply current: Note 2 and Remark 2 were modified. p.49 2.3.2 Characteristics of the supply current: Notes 1 and 3 to 5 were modified. p.50 2.3.2 Characteristics of the supply curren t: Notes 3 and 6, and Remark 2 were modified. p.91 2.6.1 Characteristics of the A/D converter for TA = -40 to +85°C: Note 2 was modified. p.95 2.6.2 Characteristics of the A/D converter for TA = -40 to +105°C: Note 2 was modified. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc. All trademarks and registered trademarks are the property of their respective owners.

Revision History

General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1. Precaution against Electrostatic Discharge (ESD) A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices. 2. Processing at power-on The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is ap plied to the external reset pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the level at which resetting is specified. 3. Input of signal during power-off state Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Follow the guideline for input signal during power-off state as described in your product documentation. 4. Handling of unused pins Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. 5. Clock signals After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or f rom an external oscillator during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable. 6. Voltage application waveform at input pin Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between V IL (Max.) and VIH (Min.). 7. Prohibition of access to reserved addresses Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these addresses as the correct operation of the LSI is not guaranteed. 8. Differences between products Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, im plement a system- evaluation test for the given product.

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Product Information

R7F102GAE2DSP specifications and overview.

Summary

RENESAS MCU Rev.1.20 Jun 30, 2026

Description

RENESAS MCU Rev.1.20 Jun 30, 2026

Source title R7F102GAE2DSP Datasheet(PDF) - Renesas Technology Corp

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