Microcontroller

R7F100LLE3CFB

Renesas Technology Corp

RENESAS MCU Rev.1.10 Oct 31, 2025

Manufacturer: Renesas Technology Corp

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RL78-L23 RENESAS | Alldatasheet

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R01DS0502EJ0110 Rev.1.10 Page 1 of 145 Oct 31, 2025 RL78/L23 RENESAS MCU On-chip LCD controller/driver, true low-power platform, 50-µA/MHz operating current, 330-nA data retention current for 4 KB of RAM, up to 512-KB code flash memory and 32-KB RAM, up to 36 capacitive touch sensors, from 44 to 100 pins, 1.6-5.5 V Datasheet 1. Outline

1.1 Features

Ultra-low power consumption technology

VDD = single power supply voltage of 1.6 to 5.5 V
H A L T m o d e
STOP mode High-speed wakeup from the STOP mode is possible.
SNOOZE mode RL78 CPU core
CISC architecture with 3-stage pipeline
Minimum instruction execution time: Can be changed from high speed (0.03125 µs @ 32 MHz operation with the high-speed on-chip oscillator clock) to ultra-low speed (30.5 µs @ 32.768 kHz operation with the subsystem clock)
Multiply/divide/multiply & accumulate instructions are supported.
Address space: 1 MB
General-purpose registers: (8-bit register × 8) × 4 banks
On-chip RAM: 16 to 32 KB Code flash memory
Code flash memory: 64 to 128 KB (single bank)

256 KB (128 KB × 2 banks or a single

256-KB bank)

512 KB (256 KB × 2 banks or a single

512-KB bank)

Block size: 2 KB
Prohibition of block erase and rewriting (security function)
On-chip debugging
Self-programming (with boot swapping and flash shield window)
Bank programming: Enables updating of the program in one bank while the user program is running from the other bank. Data flash memory
Data flash memory: 8 KB
Background operation (BGO): Instructions can be executed from the program memory while rewriting the data flash memory.
Number of rewrites: 1,000,000 times (typ.) High-speed on-chip oscillator
Select from 64 MHz, 48 MHz, 32 MHz, 24 MHz,

16 MHz, 12 MHz, 8 MHz, 6 MHz, 4 MHz, 3 MHz, 2

MHz, or 1 MHz

High accuracy: ±1.0% DD = 1.6 to 5.5 V, TA = -40 to +105°C) Middle-speed on-chip oscillator
Select from 4 MHz, 2 MHz, or 1 MHz (with adjustability) Low-speed on-chip oscillator
32.768 kHz (typ.) (with adjustability) Operating ambient temperature
TA = -40 to +105°C (3C: Industrial applications) Power management and reset function
On-chip power-on-reset (POR) circuit
On-chip voltage detectors (LVD0 and LVD1) Data transfer controller (DTC)
Transfer modes: Normal transfer mode, repeat transfer mode, block transfer mode
Activation sources: Activated by interrupt sources.
Chain transfer function R01DS0502EJ0110 Rev.1.10 Oct 31, 2025

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 2 of 145 Oct 31, 2025 SNOOZE mode sequencer (SMS)

Calculations and comparison of values by the commands for use in processing by the sequencer can realize intermittent operations where the RL78/L23 does not have to return to normal operation.
Sequentially handling a total of 32 processes with the use of desired commands from among 21 different ones
The SNOOZE mode sequencer offers operation with low power consumption without using the CPU, flash memory, and RAM. Logic and event link controller (ELCL)
Event signals can be set up between specified peripheral functions.
The signals can be generated by the input of multiple event signals to the logic circuit.
Flip-flop circuits are incorporated to handle setting and resetting functions. Serial interface
Simplified SPI (CSINote): 5 to 8 channels
UART/UART (LIN-bus supported)/UARTA: 5 to 8 channels
I2C/Simplified I2C: 8 to 10 channels Timers
16-bit timer: 8 channels (with the output of remote control signals)
16-bit timer RJ: 1 or 2 channels
16-bit timers KB40, KB41, and KB42: 1 to 3 channels (with PWM output for IH)
32-bit interval timer: 1 channel in 32-bit counter mode 2 channels in 16-bit counter mode 4 channels in 8-bit counter mode
8-bit interval timer: 4 to 8 units
Realtime clock: 1 channel (counting of one second to 99 years, alarm interrupt, and clock correction)
Watchdog timer: 1 channel (operates with the low- speed on-chip oscillator clock)
External signal sampler: 1 channel
Oscillation stop detector: 1 channel LCD controller/driver
Internal boosting, capacitive division, and external resistor division are switchable as methods of generating the driving voltage.
Number of segment signal outputs: 19 to 56
Number of common signal outputs: 4 to 8 A/D converter
8-/10-/12-bit resolution
Analog input: 8 to 13 channels
Internal reference voltage (1.48 V (typ.)) and temperature sensor D/A converter
8-bit resolution
Analog output: 3 channels (one of the three interfaces is only for the internal reference voltage for the comparator)
Output voltage: 0 V to V DD
Realtime output function Comparator
1 or 2 channels
Operating modes: Comparator high-speed mode and comparator low-speed mode
The external reference voltage and the internal reference voltage or D/A converter output are selectable as the reference voltage. Capacitive sensing unit
Operating voltage condition: VDD = 1.8 to 5.5 V
Self-capacitance method: A single pin configures a single key, supporting up to 36 keys
Mutual capacitance method: Matrix configuration with 8 × 8 pins, supporting up to 64 keys Input/output port pins
Number of port pins: 40 to 95 N-ch open-drain I/O (withstand voltage of 6 V): 2 to 4, N-ch open-drain I/O (VDD withstand voltage): 24 to 57, Controlled current drive pins: 4 to 8
Can be set to N-ch open drain or TTL input buffer, and use of an on-chip pull-up resistor can be specified.
Connectable to a device with different voltage (1.8 V, 2.5 V, or 3 V)

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 3 of 145 Oct 31, 2025 Others

Key interrupt input
Clock output/buzzer output controller
BCD (binary-coded decimal) correction circuit Note Although the CSI function is generally called SPI, it is also called CSI in this product, so it is referred to as such in this manual. Remark The functions mounted depend on the product. For details, see 1.6 Outline of Functions.

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 4 of 145 Oct 31, 2025 Ο ROM, RAM capacities Code flash memory Data flash memory RAM RL78/L23 44 pins 48 pins 52 pins 64 pins 80 pins 100 pins

512 KB 8 KB 32 KB R7F100LFL R7F100LGL R7F100LJL R7F100LLL R7F100LML R7F100LPL

256 KB 8 KB 32 KB R7F100LFJ R7F100LGJ R7F100LJJ R7F100LLJ R7F100LMJ R7F100LPJ

128 KB 8 KB 16 KB R7F100LFG R7F100LGG R7F100LJG R7F100LLG R7F100LMG R7F100LPG

64 KB 8 KB 16 KB R7F100LFE R7F100LGE R7F100LJE R7F100LLE — —

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 5 of 145 Oct 31, 2025

1.2 List of Part Numbers

Figure 1 - 1 Part Number, Memory Size, and Package of RL78/L23 R 7 F 1 0 0 L P L 3 x x x C F B # BA0 F: Flash memory RL78/L23 ROM capacity Package type Renesas MCU Renesas semiconductor product Pin count Ambient operating temperature range Device type Packaging specification #BA0, #UA0: Tray (LFQFP, LQFP, HWQFN) #HA0: Embossed tape (LFQFP, LQFP, HWQFN) FP: LQFP, 0.80-mm pitch FA: LQFP, 0.65-mm pitch FB: LFQFP, 0.50-mm pitch NP: HWQFN, 0.50-mm pitchROM number (omitted with blank products) 3: -40 to +105°C E: 64 KB G: 128 KB J: 256 KB L: 512 KB F: 44 pins G: 48 pins J: 52 pins L: 64 pins M: 80 pins P: 100 pins Fields of application C: Industrial applications Product name Ordering part number

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 6 of 145 Oct 31, 2025 Note For the fields of application, see Figure 1 - 1 Part Number, Memory Size, and Package of RL78/L23. Table 1 - 1 List of Ordering Part Numbers Pin count Package Fields of Application Note Ordering Part Number Renesas Code Product Name Packaging Specification 44 44-pin plastic LQFP (10 × 10 mm, 0.80-mm pitch) C R7F100LFL3CFP , R7F100LFJ3CFP, R7F100LFG3CFP, R7F100LFE3CFP #BA0, #UA0, #HA0 PLQP0044GC-A 48 48-pin plastic LFQFP (7 × 7 mm, 0.50-mm pitch) C R7F100LGL3CFB, R7F100LGJ3CFB, R7F100LGG3CFB, R7F100LGE3CFB #BA0, #UA0, #HA0 PLQP0048KB-B 48-pin plastic HWQFN (7 × 7 mm, 0.50-mm pitch) C R7F100LGL3CNP , R7F100LGJ3CNP, R7F100LGG3CNP, R7F100LGE3CNP #BA0, #UA0, #HA0 PWQN0048KC-A 52 52-pin plastic LQFP (10 × 10 mm, 0.65-mm pitch) C R7F100LJL3CFA, R7F100LJJ3CFA, R7F100LJG3CFA, R7F100LJE3CFA #BA0, #UA0, #HA0 PLQP0052JA-A 64 64-pin plastic LQFP (12 × 12 mm, 0.65-mm pitch) C R7F100LLL3CFA, R7F100LLJ3CFA, R7F100LLG3CFA, R7F100LLE3CFA #BA0, #UA0, #HA0 PLQP0064JB-A 64-pin plastic LFQFP (10 × 10 mm, 0.50-mm pitch) C R7F100LLL3CFB, R7F100LLJ3CFB, R7F100LLG3CFB, R7F100LLE3CFB #BA0, #UA0, #HA0 PLQP0064KB-C 80 80-pin plastic LQFP (14 × 14 mm, 0.65-mm pitch) C R7F100LML3CFA, R7F100LMJ3CFA, R7F100LMG3CFA #BA0, #UA0, #HA0 PLQP0080JA-B 80-pin plastic LFQFP (12 × 12 mm, 0.50-mm pitch) C R7F100LML3CFB, R7F100LMJ3CFB, R7F100LMG3CFB #BA0, #UA0, #HA0 PLQP0080KB-B 100 100-pin plastic LFQFP (14 × 14 mm, 0.50-mm pitch) C R7F100LPL3CFB, R7F100LPJ3CFB, R7F100LPG3CFB #BA0, #UA0, #HA0 PLQP0100KB-B 100-pin plastic LQFP (14 × 20 mm, 0.65-mm pitch) C R7F100LPL3CFA, R7F100LPJ3CFA, R7F100LPG3CFA #BA0, #UA0, #HA0 PLQP0100JC-A

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 7 of 145 Oct 31, 2025

1.3 Pin Configuration (Top View)

1.3.1 44-pin products

44-pin plastic LQFP (10 × 10 mm, 0.80-mm pitch) Note Not present in products with 128 or fewer Kbytes of code flash memory. Caution Connect the REGC pin to V SS via a capacitor (0.47 to 1 µF). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses can be assigned via settings in the peripheral I/O redirection registers (PIORx). For details, see 4.3.10 Peripheral I/O redirection registers (PIORx) in the RL78/L23 User’s Manual. 33 32 31 30 29 28 27 26 25 24 23 P05/SCK10/SCL10/SEG48/TS34/EO05 P06/SI10/RxD1/SDA10/SEG49/TS33/EI06/(PCLBUZ1) P07/SO10/TxD1/SEG50/TS32/EI07/(PCLBUZ0) P90/COM0/TS31/(TI00)/(TO00)/(INTP1) P91/COM1/TS30/(INTP2) P92/COM2/TS29/(TI01)/(TO01) P93/COM3/TS28/(INTP3)/(SCK01)/(SCL01) P94/COM4/SEG0/TS27/(INTP2)/(SI01)/(SDA01)/(TI06)/(TO06) P95/COM5/SEG1/TS26/(TI02)/(TO02)/(INTP1)/(SO01) P96/COM6/SEG2/TS25/(INTP5)/(SI01)/(SDA01)/(SDAA1)/(PCLBUZ0) P97/COM7/SEG3/TS24/(TI05)/(TO05)/(SCK01)/(SCL01)/(SCLA1) P57/INTP6/SEG11/TSCAP/(TI03)/(TO03)/(REMOOUT) P76/KR6/SEG18/TS10/CCD01/TKBO00/RxD2/EI76/EO76/(INTP2)/(RTC1HZ)/(EXSDO1) P77/KR7/SEG19/TS09/CCD00/TKBO01/TxD2/EI77/EO77/(TKBO21) Note/(TI07)/(TO07)/(INTP1)/(EXSDO0) P125/VL3/TS02/(TI06)/(TO06)/(INTP7)/(SDA30)/(PCLBUZ1) P85/VL4/(VCOUT0)/(INTP4)/(SCK10)/(SCL10)/(SCL30) P86/VL2/(TI06)/(TO06)/(INTP3)/(RxD1)/(SI10)/(SDA10)/(PCLBUZ1) P87/VL1/(TxD1)/(SO10) P126/CAPL/TS01/(TI04)/(TO04)/(INTP4) P127/CAPH/TS00/(TI03)/(TO03)/(REMOOUT) P61/SDAA0/CCD05/EO61/(TI02)/(TO02)/(INTP4) P60/SCLA0/CCD04/EO60/(TI01)/(TO01)/(INTP3) RL78/L23 (Top View) P00/SEG43/SO00/TxD0/TOOLTxD/EI00/EO00/EXSDI0/(TKBO01)/(TRJO0) P20/ANI1/AVREFM/EI20/(TI00)/(INTP7)/(PCLBUZ1) P21/ANI0/AVREFP/VBAT1/EI21/(TO00)/(INTP6)/(PCLBUZ0) P22/ANI16/SEG29/SCK21/SCL21/(SCK00)/(SCL00)/(INTP7) P26/ANI20/SEG33/ANO0/EI26/TxDA1/SI21/SDA21/(TKBO20)Note/(INTP5)/(RxD0)/(SI00)/(SDA00)/(EXSDI0) P27/ANI21/SEG34/ANO1/EI27/RxDA1/SO21/(TKBO21)Note/(INTP4)/(TxD0)/(SO00)/(EXSDI1) P10/ANI22/SEG35/TxDA0/SCK11/SCL11/(TKBO10)Note/(INTP0) P11/ANI23/SEG36/RxDA0/SI11/SDA11/(TKBO11)Note/(TRJIO1)Note/(INTP1) 23456789 1 0 1 1P44/IVCMP0/EXSDO1/(TI04)/(TO04)/(INTP7) P40/TOOL0/(TI00)/(TO00) RESET P124/XT2/EXCLKS P123/XT1 P137/EI137/INTP0 P122/X2/EXCLK/EI122 P121/X1/VBAT0/EI121 REGC VSS VDD P17/SEG42/SI00/RxD0/TOOLRxD/SDA00/EI17/EO17/EXSDI1/(TKBO01)/(TRJIO0) P16/SEG41/SCK00/SCL00/EI16/(VCOUT0)/(TKBO01)/(RTC1HZ) P12/ANI24/SEG37/EI12/CLKA0/SO11/(TKBO00)/(TRJO1)Note/(PCLBUZ1)

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 8 of 145 Oct 31, 2025 Table 1 - 2 Multiplexed Pin Functions of the 44-pin Products (1/3) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 44LQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) LCD controller/driver Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Timer RJ 16-bit timers KB40, KB41, and KB42 External signal sampler Realtime clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA)

1 P 4 4 ——— ——I V C M P 0 —( I N T P 7 ) ——( T I 0 4 ) /

(TO04) (TO00) 4P 1 2 4 — — X T 2 / EXCLKS 1 0 ———V 1 2 P 6 0 C C D 0 4 E O 6 0 — ————( I N T P 3 ) ——( T I 0 1 ) / (TO01) 1 3 P 6 1 C C D 0 5 E O 6 1 — ————( I N T P 4 ) ——( T I 0 2 ) / (TO02) (TO03)/ (REMO OUT)

15 P126 — — — — — — CAPL (INTP4) — TS01 (TI04)/

(TO04) (SO10)

17 P86 — — (PCLBUZ1) ———V L2 (INTP3) — — (TI06)/

(TO06) ————( R x D 1 ) / (SI10)/ (SDA10) (VCOUT0) VL4 ( I N T P 4 ) ——————— (SCK10)/ (SCL10)/ (SCL30)

19 P125 — — (PCLBUZ1) ———V L3 (INTP7) — TS02 (TI06)/

(TO06)

20 P77 CCD00 EI77/

— — — — SEG19 (INTP1) KR7 TS09 (TI07)/ (TO07) — TKBO01/ (TKBO21) Note (EXSDO0) — TxD2 — —

21 P76 CCD01 EI76/

— ———S E G 1 8 ( I N T P 2 ) K R 6 T S 1 0 ——T K B O 0 0 (EXSDO1) (RTC1HZ) RxD2 — — 2 2 P 5 7 ——— ———S E G 1 1 I N T P 6 —T S C A P ( T I 0 3 ) / (TO03)/ (REMO OUT) COM7 ——T S 2 4 ( T I 0 5 ) / (TO05) ———— (SCK01)/ (SCL01) (SCLA1) —

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 9 of 145 Oct 31, 2025

24 P96 — — (PCLBUZ0) ———S E G 2 /

(SDA01) (SDAA1) — COM5 (INTP1) — TS26 (TI02)/ (TO02) COM4 (INTP2) — TS27 (TI06)/ (TO06) ———— ( S I 0 1 ) / (SDA01) (SCL01) 2 8 P 9 2 ——— ———C O M 2 ——T S 2 9 ( T I 0 1 ) / (TO01) 3 0 P 9 0 ——— ———C O M 0 ( I N T P 1 ) —T S 3 1 ( T I 0 0 ) / (TO00)

31 P07 — EI07 (PCLBUZ0) ———S E G 5 0 ——T S 3 2 —————S O 1 0 /

32 P06 — EI06 (PCLBUZ1) ———S E G 4 9 ——T S 3 3 —————S I 1 0 /

3 3 P 0 5 —E O 0 5 — ———S E G 4 8 ——T S 3 4 —————S C K 1 0 / SCL10

34 P00 — EI00/

T O O L T x D ———S E G 4 3 ————( T R J O 0 ) (TKBO01) EXSDI0 — SO00/ TxD0

35 P17 — EI17/

T O O L R x D ———S E G 4 2 ———— (TRJIO0) (TKBO01) EXSDI1 — SI00/ RxD0/ SDA00

36 P16 — EI16 — — —

(VCOUT0) S E G 4 1 ————— (TKBO01) — (RTC1HZ) SCK00/ SCL00

37 P12 — EI12 (PCLBUZ1) ANI24 — — SEG37 — — — — (TRJO1)

(TKBO00) ——S O 1 1 —C L K A 0 3 8 P 1 1 ——— A N I 2 3 ——S E G 3 6 ( I N T P 1 ) ——— (TRJIO1) Note (TKBO11) Note ——S I 1 1 / SDA11 —R x D A 0 3 9 P 1 0 ——— A N I 2 2 ——S E G 3 5 ( I N T P 0 ) ———— (TKBO10) Note ——S C K 1 1 / SCL11 —T x D A 0

40 P27 — EI27 — ANI21 ANO1 — SEG34 (INTP4) — — — — (TKBO21)

(EXSDI1) —( T x D 0 ) / (SO00)/ SO21 —R x D A 1

41 P26 — EI26 — ANI20 ANO0 — SEG33 (INTP5) — — — —

(TKBO20) Note (EXSDI0) —S I 2 1 / SDA21/ (RxD0)/ (SI00)/ (SDA00) —T x D A 1 (SCK00)/ (SCL00)/ SCK21/ SCL21

43 P21 — EI21 VBAT1/

(PCLBUZ0) ANI0/ AVREFP Table 1 - 2 Multiplexed Pin Functions of the 44-pin Products (2/3) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 44LQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) LCD controller/driver Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Timer RJ 16-bit timers KB40, KB41, and KB42 External signal sampler Realtime clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA)

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 10 of 145 Oct 31, 2025 Note Not present in products with 128 or fewer Kbytes of code flash memory.

44 P20 — EI20 (PCLBUZ1) ANI1/

Table 1 - 2 Multiplexed Pin Functions of the 44-pin Products (3/3) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 44LQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) LCD controller/driver Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Timer RJ 16-bit timers KB40, KB41, and KB42 External signal sampler Realtime clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA)

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 11 of 145 Oct 31, 2025 1.3.2 48-pin products

48-pin plastic LFQFP (7 × 7 mm, 0.50-mm pitch)
48-pin plastic HWQFN (7 × 7 mm, 0.50-mm pitch) Note 1. Not present in products with 128 or fewer Kbytes of code flash memory. Note 2. The 48-pin plastic LFQFP (7 × 7 mm, 0.50-mm pitch) products do not have an exposed die pad. Caution Connect the REGC pin to V SS via a capacitor (0.47 to 1 µF). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses can be assigned via settings in the peripheral I/O redirection registers (PIORx). For details, see 4.3.10 Peripheral I/O redirection registers (PIORx) in the RL78/L23 User’s Manual. Remark 3. For products in the HWQFN package, solder the exposed die pad to the printed circuit board. We recommend leaving the destination for mounting of the exposed die pad electrically open-circuit. 36 35 34 33 32 31 30 29 28 27 26 25 RL78/L23 (Top View) P57/INTP6/SEG11/TSCAP/(TI03)/(TO03)/(REMOOUT) P75/KR5/SEG17/TS11/CCD02/SCK20/SCL20/(TKBO11)Note 1/(TKBO01)/(TI03)/(TO03)/(REMOOUT)/(INTP0) P76/KR6/SEG18/TS10/CCD01/TKBO00/SI20/SDA20/RxD2/EI76/EO76/(INTP2)/(RTC1HZ)/(EXSDO1) P77/KR7/SEG19/TS09/CCD00/TKBO01/SO20/TxD2/EI77/EO77/(TKBO21) Note 1/(TI07)/(TO07)/(INTP1)/(EXSDO0) P125/VL3/TS02/(TI06)/(TO06)/(INTP7)/(SDA30)/(PCLBUZ1) P85/VL4/(VCOUT0)/(INTP4)/(SCK10)/(SCL10)/(SCL30) P86/VL2/(TI06)/(TO06)/(INTP3)/(RxD1)/(SI10)/(SDA10)/(PCLBUZ1) P87/VL1/(TxD1)/(SO10) P126/CAPL/TS01/(TI04)/(TO04)/(INTP4) P127/CAPH/TS00/(TI03)/(TO03)/(REMOOUT) P61/SDAA0/CCD05/EO61/(TI02)/(TO02)/(INTP4) P60/SCLA0/CCD04/EO60/(TI01)/(TO01)/(INTP3) P45/IVREF0/TxDA2Note 1/SCL30/EXSDO0 P44/IVCMP0/RxDA2Note 1/SDA30/EXSDO1/(TI04)/(TO04)/(INTP7) P40/TOOL0/(TI00)/(TO00) Exposed die pad 23456789 1 0 1 1 1 2 RESET P124/XT2/EXCLKS P123/XT1 P137/EI137/INTP0 P122/X2/EXCLK/EI122 P121/X1/VBAT0/EI121 REGC VSS VDD P54/TI02/TO02/SEG8/TS19/(INTP0)/(PCLBUZ0) P97/COM7/SEG3/TS24/(TI05)/(TO05)/(SCK01)/(SCL01)/(SCLA1) P96/COM6/SEG2/TS25/(INTP5)/(SI01)/(SDA01)/(SDAA1)/(PCLBUZ0) P95/COM5/SEG1/TS26/(TI02)/(TO02)/(INTP1)/(SO01) P94/COM4/SEG0/TS27/(INTP2)/(SI01)/(SDA01)/(TI06)/(TO06) P93/COM3/TS28/(INTP3)/(SCK01)/(SCL01) P92/COM2/TS29/(TI01)/(TO01) P91/COM1/TS30/(INTP2) P90/COM0/TS31/(TI00)/(TO00)/(INTP1) P07/SO10/TxD1/SEG50/TS32/EI07/(PCLBUZ0) P06/SI10/RxD1/SDA10/SEG49/TS33/EI06/(PCLBUZ1) P05/SCK10/SCL10/SEG48/TS34/EO05 P20/ANI1/AVREFM/EI20/(TI00)/(INTP7)/(PCLBUZ1) P21/ANI0/AVREFP/VBAT1/EI21/(TO00)/(INTP6)/(PCLBUZ0) P22/ANI16/SEG29/SCK21/SCL21/(SCK00)/(SCL00)/(INTP7) P26/ANI20/SEG33/ANO0/EI26/TxDA1/SI21/SDA21/(TKBO20)Note 1/(INTP5)/(RxD0)/(SI00)/(SDA00)/(EXSDI0) P27/ANI21/SEG34/ANO1/EI27/RxDA1/SO21/(TKBO21)Note 1/(INTP4)/(TxD0)/(SO00)/(EXSDI1) P10/ANI22/SEG35/TxDA0/SCK11/SCL11/(TKBO10)Note 1/(INTP0) P11/ANI23/SEG36/RxDA0/SI11/SDA11/(TKBO11)Note 1/(TRJIO1)Note 1/(INTP1) P12/ANI24/SEG37/EI12/CLKA0/SO11/(TKBO00)/(TRJO1)Note 1/(PCLBUZ1) P13/ANI25/SEG38 P16/SEG41/SCK00/SCL00/EI16/(VCOUT0)/(TKBO01)/(RTC1HZ) P17/SEG42/SI00/RxD0/TOOLRxD/SDA00/EI17/EO17/EXSDI1/(TKBO01)/(TRJIO0) P00/SEG43/SO00/TxD0/TOOLTxD/EI00/EO00/EXSDI0/(TKBO01)/(TRJO0) Note 2

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 12 of 145 Oct 31, 2025 Table 1 - 3 Multiplexed Pin Functions of the 48-pin Products (1/3) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 48LFQFP, 48HWQFN Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) LCD controller/driver Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Timer RJ 16-bit timers KB40, KB41, and KB42 External signal sampler Realtime clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) Note

2 P 4 4 ——— ——I V C M P 0 —( I N T P 7 ) ——( T I 0 4 ) /

(TO04) —— EXSDO1 —S D A 3 0 —R x D A 2 Note (TO00) 5P 1 2 4 — — X T 2 / EXCLKS 1 1 ———V 1 3 P 6 0 C C D 0 4 E O 6 0 — ————( I N T P 3 ) ——( T I 0 1 ) / (TO01) 1 4 P 6 1 C C D 0 5 E O 6 1 — ————( I N T P 4 ) ——( T I 0 2 ) / (TO02) (TO03)/ (REMO OUT)

16 P126 — — — — — — CAPL (INTP4) — TS01 (TI04)/

(TO04) (SO10)

18 P86 — — (PCLBUZ1) ———V L2 (INTP3) — — (TI06)/

(TO06) ————( R x D 1 ) / (SI10)/ (SDA10) (VCOUT0) VL4 ( I N T P 4 ) ——————— (SCK10)/ (SCL10)/ (SCL30)

20 P125 — — (PCLBUZ1) ———V L3 (INTP7) — TS02 (TI06)/

(TO06)

21 P77 CCD00 EI77/

— — — — SEG19 (INTP1) KR7 TS09 (TI07)/ (TO07) — TKBO01/ (TKBO21) Note (EXSDO0) —S O 2 0 / TxD2

22 P76 CCD01 EI76/

— ———S E G 1 8 ( I N T P 2 ) K R 6 T S 1 0 ——T K B O 0 0 (EXSDO1) (RTC1HZ) SI20/ SDA20/ RxD2

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 13 of 145 Oct 31, 2025

23 P75 CCD02 — — — — — SEG17 (INTP0) KR5 TS11 (TI03)/

(TO03)/ (REMO OUT) (TKBO11) Note/ (TKBO01) ——S C K 2 0 / SCL20 2 4 P 5 7 ——— ———S E G 1 1 I N T P 6 —T S C A P ( T I 0 3 ) / (TO03)/ (REMO OUT)

25 P54 — —

(PCLBUZ0) — — — SEG8 (INTP0) — TS19 TI02/ TO02 COM7 ——T S 2 4 ( T I 0 5 ) / (TO05) ———— (SCK01)/ (SCL01) (SCLA1) —

27 P96 — — (PCLBUZ0) ———S E G 2 /

(SDA01) (SDAA1) — COM5 (INTP1) — TS26 (TI02)/ (TO02) COM4 (INTP2) — TS27 (TI06)/ (TO06) ————( S I 0 1 ) / (SDA01) (SCL01) 3 1 P 9 2 ——— ———C O M 2 ——T S 2 9 ( T I 0 1 ) / (TO01) 3 3 P 9 0 ——— ———C O M 0 ( I N T P 1 ) —T S 3 1 ( T I 0 0 ) / (TO00)

34 P07 — EI07 (PCLBUZ0) ———S E G 5 0 ——T S 3 2 —————S O 1 0 /

35 P06 — EI06 (PCLBUZ1) ———S E G 4 9 ——T S 3 3 —————S I 1 0 /

3 6 P 0 5 —E O 0 5 — ———S E G 4 8 ——T S 3 4 —————S C K 1 0 / SCL10

37 P00 — EI00/

T O O L T x D ———S E G 4 3 ————( T R J O 0 ) (TKBO01) EXSDI0 — SO00/ TxD0

38 P17 — EI17/

T O O L R x D ———S E G 4 2 ———— (TRJIO0) (TKBO01) EXSDI1 — SI00/ RxD0/ SDA00

39 P16 — EI16 — — —

(VCOUT0) S E G 4 1 ————— (TKBO01) — (RTC1HZ) SCK00/ SCL00

41 P12 — EI12 (PCLBUZ1) ANI24 — — SEG37 — — — — (TRJO1)

(TKBO00) ——S O 1 1 —C L K A 0 4 2 P 1 1 ——— A N I 2 3 ——S E G 3 6 ( I N T P 1 ) ——— (TRJIO1) Note (TKBO11) Note ——S I 1 1 / SDA11 —R x D A 0 Table 1 - 3 Multiplexed Pin Functions of the 48-pin Products (2/3) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 48LFQFP, 48HWQFN Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) LCD controller/driver Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Timer RJ 16-bit timers KB40, KB41, and KB42 External signal sampler Realtime clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA)

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 14 of 145 Oct 31, 2025 Note Not present in products with 128 or fewer Kbytes of code flash memory. 4 3 P 1 0 ——— A N I 2 2 ——S E G 3 5 ( I N T P 0 ) ———— (TKBO10) Note ——S C K 1 1 / SCL11 —T x D A 0

44 P27 — EI27 — ANI21 ANO1 — SEG34 (INTP4) — — — — (TKBO21)

(EXSDI1) —( T x D 0 ) / (SO00)/ SO21 —R x D A 1

45 P26 — EI26 — ANI20 ANO0 — SEG33 (INTP5) — — — —

(TKBO20) Note (EXSDI0) —S I 2 1 / SDA21/ (RxD0)/ (SI00)/ (SDA00) —T x D A 1 (SCK00)/ (SCL00)/ SCK21/ SCL21

47 P21 — EI21 VBAT1/

(PCLBUZ0) ANI0/ AVREFP

48 P20 — EI20 (PCLBUZ1) ANI1/

Table 1 - 3 Multiplexed Pin Functions of the 48-pin Products (3/3) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 48LFQFP, 48HWQFN Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) LCD controller/driver Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Timer RJ 16-bit timers KB40, KB41, and KB42 External signal sampler Realtime clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA)

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 15 of 145 Oct 31, 2025 1.3.3 52-pin products

52-pin plastic LQFP (10 × 10 mm, 0.65-mm pitch) Note Not present in products with 128 or fewer Kbytes of code flash memory. Caution Connect the REGC pin to V SS via a capacitor (0.47 to 1 µF). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses can be assigned via settings in the peripheral I/O redirection registers (PIORx). For details, see 4.3.10 Peripheral I/O redirection registers (PIORx) in the RL78/L23 User’s Manual. RL78/L23 (Top View) P05/SCK10/SCL10/SEG48/TS34/EO05 P06/SI10/RxD1/SDA10/SEG49/TS33/EI06/(PCLBUZ1) P07/SO10/TxD1/SEG50/TS32/EI07/(PCLBUZ0) P90/COM0/TS31/(TI00)/(TO00)/(INTP1) P91/COM1/TS30/(INTP2) P92/COM2/TS29/(TI01)/(TO01) P93/COM3/TS28/(INTP3)/(SCK01)/(SCL01) P94/COM4/SEG0/TS27/(INTP2)/(SI01)/(SDA01)/(TI06)/(TO06) P95/COM5/SEG1/TS26/(TI02)/(TO02)/(INTP1)/(SO01) P96/COM6/SEG2/TS25/(INTP5)/(SI01)/(SDA01)/(SDAA1)/(PCLBUZ0) P97/COM7/SEG3/TS24/(TI05)/(TO05)/(SCK01)/(SCL01)/(SCLA1) P53/INTP2/SEG7/TS20/SDA01/(TI07)/(TO07)/(PCLBUZ0) P54/TI02/TO02/SEG8/TS19/SCL01/(INTP0)/(PCLBUZ0) P57/INTP6/SEG11/TSCAP/(TI03)/(TO03)/(REMOOUT) P74/KR4/SEG16/TS12/CCD03/TKBO11Note/(TKBO01) P75/KR5/SEG17/TS11/CCD02/SCK20/SCL20/(TKBO11)Note/(TKBO01)/(TI03)/(TO03)/(REMOOUT)/(INTP0) P76/KR6/SEG18/TS10/CCD01/TKBO00/SI20/SDA20/RxD2/EI76/EO76/(INTP2)/(RTC1HZ)/(EXSDO1) P77/KR7/SEG19/TS09/CCD00/TKBO01/SO20/TxD2/EI77/EO77/(TKBO21) Note/(TI07)/(TO07)/(INTP1)/(EXSDO0) P125/VL3/TS02/(TI06)/(TO06)/(VCOUT1)/(INTP7)/(SDA30)/(PCLBUZ1) P85/VL4/(VCOUT0)/(INTP4)/(SCK10)/(SCL10)/(SCL30) P86/VL2/(TI06)/(TO06)/(INTP3)/(RxD1)/(SI10)/(SDA10)/(PCLBUZ1) P87/VL1/(TxD1)/(SO10) P126/CAPL/TS01/(TI04)/(TO04)/(INTP4) P127/CAPH/TS00/(TI03)/(TO03)/(REMOOUT) P61/SDAA0/CCD05/EO61/(TI02)/(TO02)/(INTP4) P60/SCLA0/CCD04/EO60/(TI01)/(TO01)/(INTP3) P00/SEG43/SO00/TxD0/TOOLTxD/EI00/EO00/EXSDI0/(TKBO01)/(TRJO0) P20/ANI1/AV REFM/EI20/(TI00)/(INTP7)/(PCLBUZ1) P21/ANI0/AVREFP/VBAT1/EI21/(TO00)/(INTP6)/(PCLBUZ0) P22/ANI16/SEG29/SCK21/SCL21/(SCK00)/(SCL00)/(INTP7) P26/ANI20/SEG33/ANO0/EI26/TxDA1/SI21/SDA21/(TKBO20)Note/(INTP5)/(RxD0)/(SI00)/(SDA00)/(EXSDI0) P27/ANI21/SEG34/ANO1/EI27/RxDA1/SO21/(TKBO21)Note/(INTP4)/(TxD0)/(SO00)/(EXSDI1) P10/ANI22/SEG35/TxDA0/SCK11/SCL11/(TKBO10)Note/(INTP0) P11/ANI23/SEG36/RxDA0/SI11/SDA11/(TKBO11)Note/(TRJIO1)Note/(INTP1) P12/ANI24/SEG37/EI12/CLKA0/SO11/(VCOUT1)/(TKBO00)/(TRJO1) Note/(PCLBUZ1) P13/ANI25/SEG38 P14/TI04/TO04/SEG39/ANI26 P16/SEG41/SCK00/SCL00/EI16/(VCOUT0)/(TKBO01)/(RTC1HZ) P17/SEG42/SI00/RxD0/TOOLRxD/SDA00/EI17/EO17/EXSDI1/(TKBO01)/(TRJIO0) 38 37 36 35 34 33 32 31 30 29 28 27 23456789 1 0 1 1 1 2 1 3 RESET P124/XT2/EXCLKS P123/XT1 P137/EI137/INTP0 P122/X2/EXCLK/EI122 P121/X1/VBAT0/EI121 REGC VSS VDD P45/IVREF0/TxDA2Note/SCK30/SCL30/EXSDO0 P44/IVCMP0/RxDA2Note/SI30/SDA30/RxD3/EXSDO1/(TI04)/(TO04)/(INTP7)/(SCL11) P43/IVCMP1/SO30/TxD3/(TI05)/(TO05)/(INTP4)/(SDA11) P40/TOOL0/(TI00)/(TO00)

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 16 of 145 Oct 31, 2025 Table 1 - 4 Multiplexed Pin Functions of the 52-pin Products (1/3) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 52LQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) LCD controller/driver Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Timer RJ 16-bit timers KB40, KB41, and KB42 External signal sampler Realtime clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) SCL30 —T x D A 2 Note (TO04) —— EXSDO1 — SI30/ SDA30/ (SCL11)/ RxD3 —R x D A 2 Note

3 P 4 3 ——— ——I V C M P 1 —( I N T P 4 ) ——( T I 0 5 ) /

(TO05) ———— SO30/ (SDA11)/ TxD3 (TO00) 6P 1 2 4 — — X T 2 / EXCLKS 1 2 ———V 1 4 P 6 0 C C D 0 4 E O 6 0 — ————( I N T P 3 ) ——( T I 0 1 ) / (TO01) 1 5 P 6 1 C C D 0 5 E O 6 1 — ————( I N T P 4 ) ——( T I 0 2 ) / (TO02) (TO03)/ (REMO OUT)

17 P126 — — — — — — CAPL (INTP4) — TS01 (TI04)/

(TO04) (SO10)

19 P86 — — (PCLBUZ1) ———V L2 (INTP3) — — (TI06)/

(TO06) ————( R x D 1 ) / (SI10)/ (SDA10) (VCOUT0) VL4 ( I N T P 4 ) ——————— (SCK10)/ (SCL10)/ (SCL30)

21 P125 — — (PCLBUZ1) —— (VCOUT1) VL3 (INTP7) — TS02 (TI06)/

(TO06)

22 P77 CCD00 EI77/

— — — — SEG19 (INTP1) KR7 TS09 (TI07)/ (TO07) — TKBO01/ (TKBO21) Note (EXSDO0) —S O 2 0 / TxD2

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 17 of 145 Oct 31, 2025

23 P76 CCD01 EI76/

— ———S E G 1 8 ( I N T P 2 ) K R 6 T S 1 0 ——T K B O 0 0 (EXSDO1) (RTC1HZ) SI20/ SDA20/ RxD2

24 P75 CCD02 — — — — — SEG17 (INTP0) KR5 TS11 (TI03)/

(TO03)/ (REMO OUT) (TKBO11) Note/ (TKBO01) ——S C K 2 0 / SCL20

25 P74 CCD03 — — — — — SEG16 — KR4 TS12 — — TKBO11

(TKBO01) 2 6 P 5 7 ——— ———S E G 1 1 I N T P 6 —T S C A P ( T I 0 3 ) / (TO03)/ (REMO OUT)

27 P54 — —

(PCLBUZ0) — — — SEG8 (INTP0) — TS19 TI02/ TO02

28 P53 — — (PCLBUZ0) — — — SEG7 INTP2 — TS20 (TI07)/

(TO07) COM7 ——T S 2 4 ( T I 0 5 ) / (TO05) ———— (SCK01)/ (SCL01) (SCLA1) —

30 P96 — — (PCLBUZ0) ———S E G 2 /

(SDA01) (SDAA1) — COM5 (INTP1) — TS26 (TI02)/ (TO02) COM4 (INTP2) — TS27 (TI06)/ (TO06) ————( S I 0 1 ) / (SDA01) (SCL01) 3 4 P 9 2 ——— ———C O M 2 ——T S 2 9 ( T I 0 1 ) / (TO01) 3 6 P 9 0 ——— ———C O M 0 ( I N T P 1 ) —T S 3 1 ( T I 0 0 ) / (TO00)

37 P07 — EI07 (PCLBUZ0) ———S E G 5 0 ——T S 3 2 —————S O 1 0 /

38 P06 — EI06 (PCLBUZ1) ———S E G 4 9 ——T S 3 3 —————S I 1 0 /

3 9 P 0 5 —E O 0 5 — ———S E G 4 8 ——T S 3 4 —————S C K 1 0 / SCL10

40 P00 — EI00/

T O O L T x D ———S E G 4 3 ————( T R J O 0 ) (TKBO01) EXSDI0 — SO00/ TxD0

41 P17 — EI17/

T O O L R x D ———S E G 4 2 ———— (TRJIO0) (TKBO01) EXSDI1 — SI00/ RxD0/ SDA00 Table 1 - 4 Multiplexed Pin Functions of the 52-pin Products (2/3) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 52LQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) LCD controller/driver Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Timer RJ 16-bit timers KB40, KB41, and KB42 External signal sampler Realtime clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA)

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 18 of 145 Oct 31, 2025 Note Not present in products with 128 or fewer Kbytes of code flash memory.

42 P16 — EI16 — — — (VCOUT0) S E G 4 1 ————— (TKBO01) — (RTC1HZ) SCK00/

4 3 P 1 4 ——— A N I 2 6 ——S E G 3 9 ———T I 0 4 / TO04

45 P12 — EI12 (PCLBUZ1) ANI24 — (VCOUT1) S E G 3 7 ———— (TRJO1)

(TKBO00) ——S O 1 1 —C L K A 0 4 6 P 1 1 ——— A N I 2 3 ——S E G 3 6 ( I N T P 1 ) ——— (TRJIO1) Note (TKBO11) Note ——S I 1 1 / SDA11 —R x D A 0 4 7 P 1 0 ——— A N I 2 2 ——S E G 3 5 ( I N T P 0 ) ———— (TKBO10) Note ——S C K 1 1 / SCL11 —T x D A 0

48 P27 — EI27 — ANI21 ANO1 — SEG34 (INTP4) — — — — (TKBO21)

(EXSDI1) —( T x D 0 ) / (SO00)/ SO21 —R x D A 1

49 P26 — EI26 — ANI20 ANO0 — SEG33 (INTP5) — — — —

(TKBO20) Note (EXSDI0) —S I 2 1 / SDA21/ (RxD0)/ (SI00)/ (SDA00) —T x D A 1 (SCK00)/ (SCL00)/ SCK21/ SCL21

51 P21 — EI21 VBAT1/

(PCLBUZ0) ANI0/ AVREFP

52 P20 — EI20 (PCLBUZ1) ANI1/

Table 1 - 4 Multiplexed Pin Functions of the 52-pin Products (3/3) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 52LQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) LCD controller/driver Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Timer RJ 16-bit timers KB40, KB41, and KB42 External signal sampler Realtime clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA)

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 19 of 145 Oct 31, 2025 1.3.4 64-pin products

64-pin plastic LQFP (12 × 12 mm, 0.65-mm pitch)
64-pin plastic LFQFP (10 × 10 mm, 0.50-mm pitch) Note Not present in products with 128 or fewer Kbytes of code flash memory. Caution Connect the REGC pin to V SS via a capacitor (0.47 to 1 µF). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses can be assigned via settings in the peripheral I/O redirection registers (PIORx). For details, see 4.3.10 Peripheral I/O redirection registers (PIORx) in the RL78/L23 User’s Manual. RL78/L23 (Top View) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P02/INTP7/PCLBUZ0/SEG45/(TKBO21)Note/(SCK20)/(SCL20)/(SCK31)/(SCL31) P01/PCLBUZ1/SEG44/(TI05)/(TO05)/(TKBO11)Note/(INTP5)/(SO31) P00/SEG43/SO00/TxD0/TOOLTxD/EI00/EO00/EXSDI0/(TKBO01)/(TRJO0) P17/SEG42/SI00/RxD0/TOOLRxD/SDA00/EI17/EO17/EXSDI1/(TKBO01)/(TRJIO0) P16/SEG41/SCK00/SCL00/EI16/(VCOUT0)/(TKBO01)/(RTC1HZ) P15/TI07/TO07/SEG40 P14/TI04/TO04/SEG39/ANI26 P13/ANI25/SEG38 P12/ANI24/SEG37/EI12/CLKA0/SO11/(VCOUT1)/(TKBO00)/(TRJO1)Note/(PCLBUZ1) P11/ANI23/SEG36/RxDA0/SI11/SDA11/(TKBO11)Note/(TRJIO1)Note/(INTP1) P10/ANI22/SEG35/TxDA0/SCK11/SCL11/(TKBO10)Note/(INTP0) P27/ANI21/SEG34/ANO1/EI27/RxDA1/SO21/(TKBO21)Note/(INTP4)/(TxD0)/(SO00)/(EXSDI1) P26/ANI20/SEG33/ANO0/EI26/TxDA1/SI21/SDA21/(TKBO20)Note/(INTP5)/(RxD0)/(SI00)/(SDA00)/(EXSDI0) P22/ANI16/SEG29/SCK21/SCL21/(SCK00)/(SCL00)/(INTP7) P21/ANI0/AVREFP/VBAT1/EI21/(TO00)/(INTP6)/(PCLBUZ0) P20/ANI1/AVREFM/EI20/(TI00)/(INTP7)/(PCLBUZ1) P57/INTP6/SEG11/TSCAP/(TI03)/(TO03)/(REMOOUT) P70/KR0/SEG12/TS16/TKBO20 Note P74/KR4/SEG16/TS12/CCD03/TKBO11Note/(TKBO01) P75/KR5/SEG17/TS11/CCD02/SCK20/SCL20/(TKBO11)Note/(TKBO01)/(TI03)/(TO03)/(REMOOUT)/(INTP0) P76/KR6/SEG18/TS10/CCD01/TKBO00/SI20/SDA20/RxD2/EI76/EO76/(INTP2)/(RTC1HZ)/(EXSDO1) P77/KR7/SEG19/TS09/CCD00/TKBO01/SO20/TxD2/EI77/EO77/(TKBO21)Note/(TI07)/(TO07)/(INTP1)/(EXSDO0) P30/TI03/TO03/SEG20/REMOOUT/TS08/(INTP3)/(RTC1HZ) P31/INTP3/RTC1HZ/SEG21/TS07/(TI01)/(TO01) P125/V L3/TS02/(TI06)/(TO06)/(VCOUT1)/(INTP7)/(SDA30)/(PCLBUZ1) P85/VL4/(VCOUT0)/(INTP4)/(SCK10)/(SCL10)/(SCL30) P86/VL2/(TI06)/(TO06)/(INTP3)/(RxD1)/(SI10)/(SDA10)/(PCLBUZ1) P87/VL1/(TxD1)/(SO10) P126/CAPL/TS01/(TI04)/(TO04)/(INTP4) P127/CAPH/TS00/(TI03)/(TO03)/(REMOOUT) P63/SDAA1/CCD07/(TI04)/(TO04)/(INTP6) P62/SCLA1/CCD06/(TI03)/(TO03)/(REMOOUT)/(INTP5) P03/SEG46/VCOUT0/TRJIO0/(RxD2)/(SI20)/(SDA20)/(SI31)/(SDA31) P04/SEG47/VCOUT1/TS35/(INTP6)/(SO20)/(TxD2)/(PCLBUZ0) P05/SCK10/SCL10/SEG48/TS34/EO05 P06/SI10/RxD1/SDA10/SEG49/TS33/EI06/(PCLBUZ1) P07/SO10/TxD1/SEG50/TS32/EI07/(PCLBUZ0) P90/COM0/TS31/(TI00)/(TO00)/(INTP1) P91/COM1/TS30/(INTP2) P92/COM2/TS29/(TI01)/(TO01) P93/COM3/TS28/(INTP3)/(SCK01)/(SCL01) P94/COM4/SEG0/TS27/(INTP2)/(SI01)/(SDA01)/(TI06)/(TO06) P95/COM5/SEG1/TS26/(TI02)/(TO02)/(INTP1)/(SO01) P96/COM6/SEG2/TS25/(INTP5)/(SI01)/(SDA01)/(SDAA1)/(PCLBUZ0) P97/COM7/SEG3/TS24/(TI05)/(TO05)/(SCK01)/(SCL01)/(SCLA1) P52/TI00/TO00/INTP1/SEG6/TS21/SO01/(PCLBUZ1) P53/INTP2/SEG7/TS20/SI01/SDA01/(TI07)/(TO07)/(PCLBUZ0) P54/TI02/TO02/SEG8/TS19/SCK01/SCL01/(INTP0)/(PCLBUZ0) P45/IVREF0/TxDA2Note/SCK30/SCL30/EXSDO0 P44/IVCMP0/RxDA2Note/SI30/SDA30/RxD3/EXSDO1/(TI04)/(TO04)/(INTP7)/(SCK11)/(SCL11) P43/IVCMP1/SO30/TxD3/(TI05)/(TO05)/(INTP4)/(RxDA1)/(SI11)/(SDA11) P42/TI05/TO05/IVREF1/TRJO0/(INTP7)/(TxDA1)/(SDA00)/(SO11)/(PCLBUZ1) P40/TOOL0/(TI00)/(TO00)/(SCL00) RESET P124/XT2/EXCLKS P123/XT1 P137/EI137/INTP0 P122/X2/EXCLK/EI122 P121/X1/VBAT0/EI121 REGC VSS VDD 12 13 14 15 161123456789 1 0 P60/SCLA0/CCD04/EO60/(TI01)/(TO01)/(INTP3) P61/SDAA0/CCD05/EO61/(TI02)/(TO02)/(INTP4)

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 20 of 145 Oct 31, 2025 Table 1 - 5 Multiplexed Pin Functions of the 64-pin Products (1/4) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 64LQFP, 64LFQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) LCD controller/driver Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Timer RJ 16-bit timers KB40, KB41, and KB42 External signal sampler Realtime clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) SCL30 —T x D A 2 Note (TO04) —— EXSDO1 — SI30/ SDA30/ (SCL11)/ (SCK11)/ RxD3 —R x D A 2 Note (TO05) ———— SO30/ (SI11)/ (SDA11)/ TxD3 — (RxDA1) 4P 4 2 — — (PCLBUZ1) ——I V R E F 1 —( I N T P 7 ) ——T I 0 5 / TO05 TRJO0 — — — (SDA00)/ (SO11) —( T x D A 1 ) (TO00) 7P 1 2 4 — — X T 2 / EXCLKS 1 3 ———V 1 5 P 6 0 C C D 0 4 E O 6 0 — ————( I N T P 3 ) ——( T I 0 1 ) / (TO01) 1 6 P 6 1 C C D 0 5 E O 6 1 — ————( I N T P 4 ) ——( T I 0 2 ) / (TO02) 1 7 P 6 2 C C D 0 6 —— ————( I N T P 5 ) ——( T I 0 3 ) / (TO03)/ (REMO OUT) 1 8 P 6 3 C C D 0 7 —— ————( I N T P 6 ) ——( T I 0 4 ) / (TO04) (TO03)/ (REMO OUT)

20 P126 — — — — — — CAPL (INTP4) — TS01 (TI04)/

(TO04) (SO10)

22 P86 — — (PCLBUZ1) ———V L2 (INTP3) — — (TI06)/

(TO06) ————( R x D 1 ) / (SI10)/ (SDA10)

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 21 of 145 Oct 31, 2025 2 3 P 8 5 ——— —— (VCOUT0) VL4 ( I N T P 4 ) ——————— (SCK10)/ (SCL10)/ (SCL30)

24 P125 — — (PCLBUZ1) —— (VCOUT1) VL3 (INTP7) — TS02 (TI06)/

(TO06) 2 5 P 3 1 ——— ———S E G 2 1 I N T P 3 —T S 0 7 ( T I 0 1 ) / (TO01) 2 6 P 3 0 ——— ———S E G 2 0 ( I N T P 3 ) —T S 0 8 T I 0 3 / TO03/ REMOO UT ——— (RTC1HZ) ———

27 P77 CCD00 EI77/

— — — — SEG19 (INTP1) KR7 TS09 (TI07)/ (TO07) — TKBO01/ (TKBO21) Note (EXSDO0) —S O 2 0 / TxD2

28 P76 CCD01 EI76/

— ———S E G 1 8 ( I N T P 2 ) K R 6 T S 1 0 ——T K B O 0 0 (EXSDO1) (RTC1HZ) SI20/ SDA20/ RxD2

29 P75 CCD02 — — — — — SEG17 (INTP0) KR5 TS11 (TI03)/

(TO03)/ (REMO OUT) (TKBO11) Note/ (TKBO01) ——S C K 2 0 / SCL20

30 P74 CCD03 — — — — — SEG16 — KR4 TS12 — — TKBO11

(TKBO01) 3 1 P 7 0 ——— ———S E G 1 2 —K R 0 T S 1 6 ——T K B O 2 0 Note 3 2 P 5 7 ——— ———S E G 1 1 I N T P 6 —T S C A P ( T I 0 3 ) / (TO03)/ (REMO OUT)

33 P54 — —

(PCLBUZ0) — — — SEG8 (INTP0) — TS19 TI02/ TO02 ————S C L 0 1 / SCK01

34 P53 — — (PCLBUZ0) — — — SEG7 INTP2 — TS20 (TI07)/

(TO07) ————S I 0 1 / SDA01

35 P52 — — (PCLBUZ1) — — — SEG6 INTP1 — TS21 TI00/

——T S 2 4 ( T I 0 5 ) / (TO05) ———— (SCK01)/ (SCL01) (SCLA1) —

37 P96 — — (PCLBUZ0) ———S E G 2 /

(SDA01) (SDAA1) — COM5 (INTP1) — TS26 (TI02)/ (TO02) COM4 (INTP2) — TS27 (TI06)/ (TO06) ————( S I 0 1 ) / (SDA01) (SCL01) 4 1 P 9 2 ——— ———C O M 2 ——T S 2 9 ( T I 0 1 ) / (TO01) Table 1 - 5 Multiplexed Pin Functions of the 64-pin Products (2/4) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 64LQFP, 64LFQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) LCD controller/driver Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Timer RJ 16-bit timers KB40, KB41, and KB42 External signal sampler Realtime clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA)

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 22 of 145 Oct 31, 2025 4 3 P 9 0 ——— ———C O M 0 ( I N T P 1 ) —T S 3 1 ( T I 0 0 ) / (TO00)

44 P07 — EI07 (PCLBUZ0) ———S E G 5 0 ——T S 3 2 —————S O 1 0 /

45 P06 — EI06 (PCLBUZ1) ———S E G 4 9 ——T S 3 3 —————S I 1 0 /

4 6 P 0 5 —E O 0 5 — ———S E G 4 8 ——T S 3 4 —————S C K 1 0 / SCL10

47 P04 — —

(PCLBUZ0) —— VCOUT1 S E G 4 7 ( I N T P 6 ) —T S 3 5 —————( T x D 2 ) / (SO20) (SDA31)/ (RxD2)/ (SI20)/ (SDA20) 4 9 P 0 2 ——P C L B U Z 0 ———S E G 4 5 I N T P 7 ———— (TKBO21) Note —— (SCK31)/ (SCL31)/ (SCK20)/ (SCL20) 5 0 P 0 1 ——P C L B U Z 1 ———S E G 4 4 ( I N T P 5 ) ——( T I 0 5 ) / (TO05) (TKBO11) Note ——( S O 3 1 ) ——

51 P00 — EI00/

T O O L T x D ———S E G 4 3 ————( T R J O 0 ) (TKBO01) EXSDI0 — SO00/ TxD0

52 P17 — EI17/

T O O L R x D ———S E G 4 2 ———— (TRJIO0) (TKBO01) EXSDI1 — SI00/ RxD0/ SDA00

53 P16 — EI16 — — —

(VCOUT0) S E G 4 1 ————— (TKBO01) — (RTC1HZ) SCK00/ SCL00 TO07 5 5 P 1 4 ——— A N I 2 6 ——S E G 3 9 ———T I 0 4 / TO04

57 P12 — EI12 (PCLBUZ1) ANI24 — (VCOUT1) S E G 3 7 ———— (TRJO1)

(TKBO00) ——S O 1 1 —C L K A 0 5 8 P 1 1 ——— A N I 2 3 ——S E G 3 6 ( I N T P 1 ) ——— (TRJIO1) Note (TKBO11) Note ——S I 1 1 / SDA11 —R x D A 0 5 9 P 1 0 ——— A N I 2 2 ——S E G 3 5 ( I N T P 0 ) ———— (TKBO10) Note ——S C K 1 1 / SCL11 —T x D A 0

60 P27 — EI27 — ANI21 ANO1 — SEG34 (INTP4) — — — — (TKBO21)

(EXSDI1) —( T x D 0 ) / (SO00)/ SO21 —R x D A 1 Table 1 - 5 Multiplexed Pin Functions of the 64-pin Products (3/4) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 64LQFP, 64LFQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) LCD controller/driver Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Timer RJ 16-bit timers KB40, KB41, and KB42 External signal sampler Realtime clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA)

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 23 of 145 Oct 31, 2025 Note Not present in products with 128 or fewer Kbytes of code flash memory.

61 P26 — EI26 — ANI20 ANO0 — SEG33 (INTP5) — — — — (TKBO20)

(EXSDI0) —S I 2 1 / SDA21/ (RxD0)/ (SI00)/ (SDA00) —T x D A 1 (SCK00)/ (SCL00)/ SCK21/ SCL21

63 P21 — EI21 VBAT1/

(PCLBUZ0) ANI0/ AVREFP

64 P20 — EI20 (PCLBUZ1) ANI1/

Table 1 - 5 Multiplexed Pin Functions of the 64-pin Products (4/4) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 64LQFP, 64LFQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) LCD controller/driver Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Timer RJ 16-bit timers KB40, KB41, and KB42 External signal sampler Realtime clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA)

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 24 of 145 Oct 31, 2025 1.3.5 80-pin products

80-pin plastic LQFP (14 × 14 mm, 0.65-mm pitch)
80-pin plastic LFQFP (12 × 12 mm, 0.50-mm pitch) Caution Connect the REGC pin to V SS via a capacitor (0.47 to 1 µF). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses can be assigned via settings in the peripheral I/O redirection registers (PIORx). For details, see 4.3.10 Peripheral I/O redirection registers (PIORx) in the RL78/L23 User’s Manual. P04/SEG47/VCOUT1/TS35/(INTP6)/(SO20)/(TxD2)/(PCLBUZ0) P05/SCK10/SCL10/SEG48/TS34/EO05 P06/SI10/RxD1/SDA10/SEG49/TS33/EI06/(PCLBUZ1) P07/SO10/TxD1/SEG50/TS32/EI07/(PCLBUZ0) P90/COM0/TS31/(TI00)/(TO00)/(INTP1) P91/COM1/TS30/(INTP2) P92/COM2/TS29/(TI01)/(TO01) P93/COM3/TS28/(INTP3)/(SCK01)/(SCL01) P94/COM4/SEG0/TS27/(INTP2)/(SI01)/(SDA01)/(TI06)/(TO06) P95/COM5/SEG1/TS26/(TI02)/(TO02)/(INTP1)/(SO01) P96/COM6/SEG2/TS25/(INTP5)/(SI01)/(SDA01)/(SDAA1)/(PCLBUZ0) P97/COM7/SEG3/TS24/(TI05)/(TO05)/(SCK01)/(SCL01)/(SCLA1) P50/SEG4/TS23/TxDA3 P51/SEG5/TS22/RxDA3/(INTP6) P52/TI00/TO00/INTP1/SEG6/TS21/SO01/(PCLBUZ1) P53/INTP2/SEG7/TS20/SI01/SDA01/(TI07)/(TO07)/(PCLBUZ0) P54/TI02/TO02/SEG8/TS19/SCK01/SCL01/(INTP0)/(PCLBUZ0) P55/INTP5/SEG9/TS18/(TI02)/(TO02) P56/TI06/TO06/SEG10/TS17 P57/INTP6/SEG11/TSCAP/(TI03)/(TO03)/(REMOOUT) RL78/L23 (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P70/KR0/SEG12/TS16/TKBO20 P71/KR1/SEG13/TS15 P72/KR2/SEG14/TS14/TKBO21 P73/KR3/SEG15/TS13/TKBO10 P74/KR4/SEG16/TS12/CCD03/TKBO11/(TKBO01) P75/KR5/SEG17/TS11/CCD02/SCK20/SCL20/(TKBO11)/(TKBO01)/(TI03)/(TO03)/(REMOOUT)/(INTP0) P76/KR6/SEG18/TS10/CCD01/TKBO00/SI20/SDA20/RxD2/EI76/EO76/(INTP2)/(RTC1HZ)/(EXSDO1) P77/KR7/SEG19/TS09/CCD00/TKBO01/SO20/TxD2/EI77/EO77/(TKBO21)/(TI07)/(TO07)/(INTP1)/(EXSDO0) P30/TI03/TO03/SEG20/REMOOUT/TS08/(INTP3)/(RTC1HZ) P31/INTP3/RTC1HZ/SEG21/TS07/(TI01)/(TO01) P34/SEG24/TS04/(TI01)/(TO01)/(INTP0)/(RxD3) P35/SEG25/TS03/(VCOUT0)/(INTP4)/(SO30)/(TxD3) P125/V L3/TS02/(TI06)/(TO06)/(VCOUT1)/(INTP7)/(RxD3)/(SI30)/(SDA30)/(PCLBUZ1) P85/VL4/(VCOUT0)/(INTP4)/(SCK10)/(SCL10)/(SCK30)/(SCL30) P86/VL2/(TI06)/(TO06)/(INTP3)/(RxD1)/(SI10)/(SDA10)/(PCLBUZ1) P87/VL1/(TxD1)/(SO10) P126/CAPL/TS01/(TI04)/(TO04)/(INTP4) P127/CAPH/TS00/(TI03)/(TO03)/(REMOOUT) P63/SDAA1/CCD07/(TI04)/(TO04)/(INTP6) P130/SEG28/TRJO1/(TxDA0)/(SO21)/(SO01) P20/ANI1/AVREFM/EI20/(TI00)/(INTP7)/(PCLBUZ1) P47/SEG27/(RxDA0)/(SI21)/(SDA21)/(SDA01)/(SI01)/(INTP1) P46/SEG26/(SCK21)/(SCL21)/(SCL01)/(SCK01) P45/IVREF0/TxDA2/SCK30/SCL30/EXSDO0 P44/IVCMP0/RxDA2/SI30/SDA30/RxD3/EXSDO1/(TI04)/(TO04)/(INTP7)/(SCK11)/(SCL11) P43/IVCMP1/SO30/TxD3/(TI05)/(TO05)/(INTP4)/(RxDA1)/(SI11)/(SDA11) P42/TI05/TO05/IVREF1/TRJO0/(INTP7)/(TxDA1)/(SCLA0)/(RxD0)/(TxD1)/(SI00)/(SDA00)/(SO11)/(PCLBUZ1) P41/(TI07)/(TO07)/(INTP6)/(TxD0)/(SDAA0)/(SO00)/(RxD1) P40/TOOL0/(TI00)/(TO00)/(SCK00)/(SCL00) RESET P124/XT2/EXCLKS P123/XT1 P137/EI137/INTP0 P122/X2/EXCLK/EI122 P121/X1/VBAT0/EI121 REGC VSS VDD P60/SCLA0/CCD04/EO60/(TI01)/(TO01)/(INTP3) P61/SDAA0/CCD05/EO61/(TI02)/(TO02)/(INTP4) P62/SCLA1/CCD06/(TI03)/(TO03)/(REMOOUT)/(INTP5) P03/SEG46/VCOUT0/TRJIO0/(RxD2)/(SI20)/(SDA20)/(SI31)/(SDA31) P02/INTP7/PCLBUZ0/SEG45/(TKBO21)/(SCK20)/(SCL20)/(SCK31)/(SCL31) P01/PCLBUZ1/SEG44/(TI05)/(TO05)/(TKBO11)/(INTP5)/(SO31) P00/SEG43/SO00/TxD0/TOOLTxD/EI00/EO00/EXSDI0/(TKBO01)/(TRJO0) P17/SEG42/SI00/RxD0/TOOLRxD/SDA00/EI17/EO17/EXSDI1/(TKBO01)/(TRJIO0) P16/SEG41/SCK00/SCL00/EI16/(VCOUT0)/(TKBO01)/(RTC1HZ) P15/TI07/TO07/SEG40 P14/TI04/TO04/SEG39/ANI26 P13/ANI25/SEG38 P12/ANI24/SEG37/EI12/CLKA0/SO11/(VCOUT1)/(TKBO00)/(TRJO1)/(PCLBUZ1) P11/ANI23/SEG36/RxDA0/SI11/SDA11/(TKBO11)/(TRJIO1)/(INTP1) P10/ANI22/SEG35/TxDA0/SCK11/SCL11/(TKBO10)/(INTP0) P27/ANI21/SEG34/ANO1/EI27/RxDA1/SO21/(TKBO21)/(INTP4)/(TxD0)/(SO00)/(EXSDI1) P26/ANI20/SEG33/ANO0/EI26/TxDA1/SI21/SDA21/(TKBO20)/(INTP5)/(RxD0)/(SI00)/(SDA00)/(EXSDI0) P25/ANI19/SEG32/CLKA1 P24/ANI18/SEG31 P23/ANI17/SEG30/TRJIO1 P22/ANI16/SEG29/SCK21/SCL21/(SCK00)/(SCL00)/(INTP7) P21/ANI0/AVREFP/VBAT1/EI21/(TO00)/(INTP6)/(PCLBUZ0)

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 25 of 145 Oct 31, 2025 Table 1 - 6 Multiplexed Pin Functions of the 80-pin Products (1/4) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 80LQFP, 80LFQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) LCD controller/driver Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Timer RJ 16-bit timers KB40, KB41, and KB42 External signal sampler Realtime clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) (SO01) —( T x D A 0 ) (SI21)/ (SDA01)/ (SDA21) — (RxDA0) (SCK01)/ (SCK21)/ (SCL21) SCL30 —T x D A 2

5 P 4 4 ——— ——I V C M P 0 —( I N T P 7 ) ——( T I 0 4 ) /

(TO04) —— EXSDO1 — SI30/ SDA30/ (SCL11)/ (SCK11)/ RxD3 —R x D A 2

6 P 4 3 ——— ——I V C M P 1 —( I N T P 4 ) ——( T I 0 5 ) /

(TO05) ———— SO30/ (SI11)/ (SDA11)/ TxD3 — (RxDA1) 7P 4 2 — — (PCLBUZ1) ——I V R E F 1 —( I N T P 7 ) ——T I 0 5 / TO05 TRJO0 — — — (SI00)/ (RxD0)/ (SDA00)/ (SO11)/ (TxD1) (SCLA0) (TxDA1) (TO07) ———— (SO00)/ (TxD0)/ (RxD1) (SDAA0) (TO00) ———— (SCL00)/ (SCK00)

11 P124 — — XT2/

1 7 ———V 1 9 P 6 0 C C D 0 4 E O 6 0 — ————( I N T P 3 ) ——( T I 0 1 ) / (TO01) 2 0 P 6 1 C C D 0 5 E O 6 1 — ————( I N T P 4 ) ——( T I 0 2 ) / (TO02) 2 1 P 6 2 C C D 0 6 —— ————( I N T P 5 ) ——( T I 0 3 ) / (TO03)/ (REMO OUT) 2 2 P 6 3 C C D 0 7 —— ————( I N T P 6 ) ——( T I 0 4 ) / (TO04)

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 26 of 145 Oct 31, 2025 (TO03)/ (REMO OUT)

24 P126 — — — — — — CAPL (INTP4) — TS01 (TI04)/

(TO04) (SO10)

26 P86 — — (PCLBUZ1) ———V L2 (INTP3) — — (TI06)/

(TO06) ————( R x D 1 ) / (SI10)/ (SDA10) (VCOUT0) VL4 ( I N T P 4 ) ——————— (SCK10)/ (SCL10)/ (SCK30)/ (SCL30)

28 P125 — — (PCLBUZ1) —— (VCOUT1) VL3 (INTP7) — TS02 (TI06)/

(TO06) ————( S I 3 0 ) / (RxD3)/ (SDA30) (VCOUT0) S E G 2 5 ( I N T P 4 ) —T S 0 3 —————( S O 3 0 ) / (TxD3) 3 0 P 3 4 ——— ———S E G 2 4 ( I N T P 0 ) —T S 0 4 ( T I 0 1 ) / (TO01) 3 1 P 3 1 ——— ———S E G 2 1 I N T P 3 —T S 0 7 ( T I 0 1 ) / (TO01) 3 2 P 3 0 ——— ———S E G 2 0 ( I N T P 3 ) —T S 0 8 T I 0 3 / TO03/ REMOO UT ——— (RTC1HZ) ———

33 P77 CCD00 EI77/

— — — — SEG19 (INTP1) KR7 TS09 (TI07)/ (TO07) — TKBO01/ (TKBO21) (EXSDO0) —S O 2 0 / TxD2

34 P76 CCD01 EI76/

— ———S E G 1 8 ( I N T P 2 ) K R 6 T S 1 0 ——T K B O 0 0 (EXSDO1) (RTC1HZ) SI20/ SDA20/ RxD2

35 P75 CCD02 — — — — — SEG17 (INTP0) KR5 TS11 (TI03)/

(TO03)/ (REMO OUT) (TKBO11)/ (TKBO01) ——S C K 2 0 / SCL20

36 P74 CCD03 — — — — — SEG16 — KR4 TS12 — — TKBO11/

(TKBO01) 4 1 P 5 7 ——— ———S E G 1 1 I N T P 6 —T S C A P ( T I 0 3 ) / (TO03)/ (REMO OUT) Table 1 - 6 Multiplexed Pin Functions of the 80-pin Products (2/4) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 80LQFP, 80LFQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) LCD controller/driver Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Timer RJ 16-bit timers KB40, KB41, and KB42 External signal sampler Realtime clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA)

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 27 of 145 Oct 31, 2025 4 2 P 5 6 ——— ———S E G 1 0 ——T S 1 7 T I 0 6 / TO06 4 3 P 5 5 ——— ———S E G 9 I N T P 5 —T S 1 8 ( T I 0 2 ) / (TO02)

44 P54 — — (PCLBUZ0) — — — SEG8 (INTP0) — TS19 TI02/

————S C L 0 1 / SCK01

45 P53 — — (PCLBUZ0) — — — SEG7 INTP2 — TS20 (TI07)/

(TO07) ————S I 0 1 / SDA01

46 P52 — — (PCLBUZ1) — — — SEG6 INTP1 — TS21 TI00/

——T S 2 4 ( T I 0 5 ) / (TO05) ———— (SCK01)/ (SCL01) (SCLA1) —

50 P96 — — (PCLBUZ0) ———S E G 2 /

(SDA01) (SDAA1) — COM5 (INTP1) — TS26 (TI02)/ (TO02) COM4 (INTP2) — TS27 (TI06)/ (TO06) ————( S I 0 1 ) / (SDA01) (SCL01) 5 4 P 9 2 ——— ———C O M 2 ——T S 2 9 ( T I 0 1 ) / (TO01) 5 6 P 9 0 ——— ———C O M 0 ( I N T P 1 ) —T S 3 1 ( T I 0 0 ) / (TO00)

57 P07 — EI07 (PCLBUZ0) ———S E G 5 0 ——T S 3 2 —————S O 1 0 /

58 P06 — EI06 (PCLBUZ1) ———S E G 4 9 ——T S 3 3 —————S I 1 0 /

5 9 P 0 5 —E O 0 5 — ———S E G 4 8 ——T S 3 4 —————S C K 1 0 / SCL10

60 P04 — —

(PCLBUZ0) —— VCOUT1 S E G 4 7 ( I N T P 6 ) —T S 3 5 —————( T x D 2 ) / (SO20) (SDA31)/ (RxD2)/ (SI20)/ (SDA20) 6 2 P 0 2 ——P C L B U Z 0 ———S E G 4 5 I N T P 7 ———— (TKBO21) —— (SCK31)/ (SCL31)/ (SCK20)/ (SCL20) 6 3 P 0 1 ——P C L B U Z 1 ———S E G 4 4 ( I N T P 5 ) ——( T I 0 5 ) / (TO05) Table 1 - 6 Multiplexed Pin Functions of the 80-pin Products (3/4) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 80LQFP, 80LFQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) LCD controller/driver Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Timer RJ 16-bit timers KB40, KB41, and KB42 External signal sampler Realtime clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA)

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 28 of 145 Oct 31, 2025

64 P00 — EI00/

T O O L T x D ———S E G 4 3 ————( T R J O 0 ) (TKBO01) EXSDI0 — SO00/ TxD0

65 P17 — EI17/

T O O L R x D ———S E G 4 2 ———— (TRJIO0) (TKBO01) EXSDI1 — SI00/ RxD0/ SDA00

66 P16 — EI16 — — —

(VCOUT0) S E G 4 1 ————— (TKBO01) — (RTC1HZ) SCK00/ SCL00 TO07 6 8 P 1 4 ——— A N I 2 6 ——S E G 3 9 ———T I 0 4 / TO04

70 P12 — EI12 (PCLBUZ1) ANI24 — (VCOUT1) SEG37 — — — — (TRJO1) (TKBO00) ——S O 1 1 —C L K A 0

7 1 P 1 1 ——— A N I 2 3 ——S E G 3 6 ( I N T P 1 ) ——— (TRJIO1) (TKBO11) ——S I 1 1 / SDA11 —R x D A 0 7 2 P 1 0 ——— A N I 2 2 ——S E G 3 5 ( I N T P 0 ) ———— (TKBO10) ——S C K 1 1 / SCL11 —T x D A 0

73 P27 — EI27 — ANI21 ANO1 — SEG34 (INTP4) — — — — (TKBO21) (EXSDI1) —( T x D 0 ) /

(SO00)/ SO21 —R x D A 1

74 P26 — EI26 — ANI20 ANO0 — SEG33 (INTP5) — — — —

(TKBO20) (EXSDI0) —S I 2 1 / SDA21/ (RxD0)/ (SI00)/ (SDA00) —T x D A 1 (SCK00)/ (SCL00)/ SCK21/ SCL21

79 P21 — EI21 VBAT1/

(PCLBUZ0) ANI0/ AVREFP

80 P20 — EI20 (PCLBUZ1) ANI1/

Table 1 - 6 Multiplexed Pin Functions of the 80-pin Products (4/4) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 80LQFP, 80LFQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) LCD controller/driver Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Timer RJ 16-bit timers KB40, KB41, and KB42 External signal sampler Realtime clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA)

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 29 of 145 Oct 31, 2025 1.3.6 100-pin products

100-pin plastic LFQFP (14 × 14 mm, 0.50-mm pitch) Caution 1. Connect the EV SS pin to the same ground as the VSS pin. Caution 2. Connect the REGC pin to V SS via a capacitor (0.47 to 1 µF). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to connect the VSS and EVSS pins to separate ground lines. Remark 3. Functions in parentheses can be assigned via settings in the peripheral I/O redirection registers (PIORx). For details, see 4.3.10 Peripheral I/O redirection registers (PIORx) in the RL78/L23 User’s Manual. P140/SCK31/SCL31 P130/SEG28/TRJO1/(TxDA0)/(SO21)/(SO01) P47/SEG27/SO31/(RxDA0)/(SI21)/(SDA21)/(SDA01)/(SI01)/(INTP1) P46/SEG26/SI31/SDA31/(SCK21)/(SCL21)/(SCL01)/(SCK01) P45/IVREF0/TxDA2/SCK30/SCL30/EXSDO0 P44/IVCMP0/RxDA2/SI30/SDA30/RxD3/EXSDO1/(TI04)/(TO04)/(INTP7)/(SCK11)/(SCL11) P43/IVCMP1/SO30/TxD3/(TI05)/(TO05)/(INTP4)/(RxDA1)/(SI11)/(SDA11) P42/TI05/TO05/IVREF1/TRJO0/(INTP7)/(TxDA1)/(SCLA0)/(RxD0)/(TxD1)/(SI00)/(SDA00)/(SO10)/(SO11)/(PCLBUZ1) P41/(TI07)/(TO07)/(INTP6)/(TxD0)/(RxDA3)/(SDAA0)/(SO00)/(SI10)/(SDA10)/(RxD1) P66/(TI05)/(TO05)/(INTP1)/(SCK10)/(SCL10)/(TxDA3) P67/(INTP2)/(TI01)/(TO01) P40/TOOL0/(TI00)/(TO00)/(SCK00)/(SCL00) RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0/EI137 P122/X2/EXCLK/EI122 P121/X1/VBAT0/EI121 REGC VSS VDD EVSS P64/(INTP5)/(SDAA1)/(TI03)/(TO03)/(REMOOUT) P65/(INTP0)/(SCLA1)/(TI05)/(TO05) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P146/(VCOUT1)/(TxD2)/(SO20)/(SO31)/(RxDA2)/(INTP7) P147/(INTP2)/(TxDA3)/(RxD2)/(SI20)/(SDA20) P80/(INTP2)/(SCK20)/(SCL20) P04/SEG47/VCOUT1/TS35/(INTP6)/(SO20)/(TxD2)/(PCLBUZ0) P05/SCK10/SCL10/SEG48/TS34/EO05 P06/SI10/RxD1/SDA10/SEG49/TS33/EI06/(PCLBUZ1) P07/SO10/TxD1/SEG50/TS32/EI07/(PCLBUZ0) P81/(RxD1)/(SI10)/(SDA10) P82/(SCK10)/(SCL10)/(PCLBUZ0) P90/COM0/TS31/(TI00)/(TO00)/(INTP1) P91/COM1/TS30/(INTP2) P92/COM2/TS29/(TI01)/(TO01) P93/COM3/TS28/(INTP3)/(SCK01)/(SCL01) P94/COM4/SEG0/TS27/(INTP2)/(SI01)/(SDA01)/(TI06)/(TO06) P95/COM5/SEG1/TS26/(TI02)/(TO02)/(INTP1)/(SO01) P96/COM6/SEG2/TS25/(INTP5)/(SI01)/(SDA01)/(SDAA1)/(PCLBUZ0) P97/COM7/SEG3/TS24/(TI05)/(TO05)/(SCK01)/(SCL01)/(SCLA1) P50/SEG4/TS23/TxDA3 P51/SEG5/TS22/RxDA3/(INTP6) P52/TI00/TO00/INTP1/SEG6/TS21/SO01/(PCLBUZ1) P53/INTP2/SEG7/TS20/SI01/SDA01/(TI07)/(TO07)/(PCLBUZ0) P54/TI02/TO02/SEG8/TS19/SCK01/SCL01/(INTP0)/(PCLBUZ0) P55/INTP5/SEG9/TS18/(TI02)/(TO02) P56/TI06/TO06/SEG10/TS17 P57/INTP6/SEG11/TSCAP/(TI03)/(TO03)/(REMOOUT) P03/SEG46/VCOUT0/TRJIO0/(TxDA2)/(RxD2)/(SI20)/(SDA20)/(SI31)/(SDA31) P02/INTP7/PCLBUZ0/SEG45/(TKBO21)/(SCK20)/(SCL20)/(SCK31)/(SCL31) P01/PCLBUZ1/SEG44/(TI05)/(TO05)/(TKBO11)/(INTP5)/(SO31) P00/SEG43/SO00/TxD0/TOOLTxD/EI00/EO00/EXSDI0/(TKBO01)/(TRJO0) P17/SEG42/SI00/RxD0/TOOLRxD/SDA00/EI17/EO17/EXSDI1/(TKBO01)/(TRJIO0) P16/SEG41/SCK00/SCL00/EI16/(VCOUT0)/(TKBO01)/(RTC1HZ) P15/TI07/TO07/SEG40 P14/TI04/TO04/SEG39/ANI26 P13/ANI25/SEG38 P12/ANI24/SEG37/EI12/CLKA0/SO11/(VCOUT1)/(TKBO00)/(TRJO1)/(PCLBUZ1) P11/ANI23/SEG36/RxDA0/SI11/SDA11/(TKBO11)/(TRJIO1)/(INTP1) P10/ANI22/SEG35/TxDA0/SCK11/SCL11/(TKBO10)/(INTP0) P145/SEG55/(INTP3)/(TxDA1)/(SDAA0) P144/SEG54/(INTP4)/(RxDA1)/(SCLA0) P27/ANI21/SEG34/ANO1/EI27/RxDA1/SO21/(TKBO21)/(INTP4)/(TxD0)/(SO00)/(EXSDI1) P26/ANI20/SEG33/ANO0/EI26/TxDA1/SI21/SDA21/(TKBO20)/(INTP5)/(RxD0)/(SI00)/(SDA00)/(EXSDI0) P25/ANI19/SEG32/CLKA1 P24/ANI18/SEG31 P143/SEG53/(INTP5)/(TxDA2) P142/SEG52/(INTP7)/(RxDA2) P141/SEG51/(INTP6)/(RxDA3) P23/ANI17/SEG30/TRJIO1 P22/ANI16/SEG29/SCK21/SCL21/(SCK00)/(SCL00)/(INTP7) P21/ANI0/AV REFP/VBAT1/EI21/(TO00)/(INTP6)/(PCLBUZ0) P20/ANI1/AVREFM/EI20/(TI00)/(INTP7)/(PCLBUZ1) P83/(INTP1)/(RxDA0)/(SDAA1) P84/(INTP0)/(TxDA0)/(SCLA1) P70/KR0/SEG12/TS16/TKBO20 P71/KR1/SEG13/TS15 P72/KR2/SEG14/TS14/TKBO21 P73/KR3/SEG15/TS13/TKBO10 P74/KR4/SEG16/TS12/CCD03/TKBO11/(TKBO01) P75/KR5/SEG17/TS11/CCD02/SCK20/SCL20/(TKBO11)/(TKBO01)/(TI03)/(TO03)/(REMOOUT)/(INTP0) P76/KR6/SEG18/TS10/CCD01/TKBO00/SI20/SDA20/RxD2/EI76/EO76/(INTP2)/(RTC1HZ)/(EXSDO1) P77/KR7/SEG19/TS09/CCD00/TKBO01/SO20/TxD2/EI77/EO77/(TKBO21)/(TI07)/(TO07)/(INTP1)/(EXSDO0) P30/TI03/TO03/SEG20/REMOOUT/TS08/(INTP3)/(RTC1HZ) P31/INTP3/RTC1HZ/SEG21/TS07/(TI01)/(TO01) P32/TI01/TO01/SEG22/TS06/(TI03)/(TO03)/(REMOOUT)/(INTP3)/(RTC1HZ) P33/INTP4/SEG23/TS05/(TI01)/(TO01)/(RTC1HZ)/(SCK30)/(SCL30) P34/SEG24/TS04/(TI01)/(TO01)/(INTP0)/(SI30)/(RxD3)/(SDA30) P35/SEG25/TS03/(VCOUT0)/(INTP4)/(SO30)/(TxD3) P125/V L3/TS02/(TI06)/(TO06)/(VCOUT1)/(INTP7)/(RxD3)/(SI30)/(SDA30)/(PCLBUZ1) P85/VL4/(VCOUT0)/(INTP4)/(SCK10)/(SCL10)/(SCK30)/(SCL30) P86/VL2/(TI06)/(TO06)/(INTP3)/(RxD1)/(SI10)/(SDA10)/(PCLBUZ1) P87/VL1/(TxD1)/(SO10) P126/CAPL/TS01/(TI04)/(TO04)/(INTP4) P127/CAPH/TS00/(TI03)/(TO03)/(REMOOUT) P63/SDAA1/CCD07/(TI04)/(TO04)/(INTP6) P62/SCLA1/CCD06/(TI03)/(TO03)/(REMOOUT)/(INTP5) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 RL78/L23 (Top View) P60/SCLA0/CCD04/EO60/(TI01)/(TO01)/(INTP3) P61/SDAA0/CCD05/EO61/(TI02)/(TO02)/(INTP4)

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 30 of 145 Oct 31, 2025 Table 1 - 7 Multiplexed Pin Functions of the 100-pin Products (1/5) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 100LFQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) LCD controller/driver Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Timer RJ 16-bit timers KB40, KB41, and KB42 External signal sampler Realtime clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) SCL31 (SO01) —( T x D A 0 ) (SI01)/ (SI21)/ (SDA01)/ (SDA21) — (RxDA0) SDA31/ (SCL01)/ (SCK01)/ (SCK21)/ (SCL21) SCL30 —T x D A 2

6 P 4 4 ——— ——I V C M P 0 —( I N T P 7 ) ——( T I 0 4 ) /

(TO04) —— EXSDO1 — SI30/ SDA30/ (SCL11)/ (SCK11)/ RxD3 —R x D A 2

7 P 4 3 ——— ——I V C M P 1 —( I N T P 4 ) ——( T I 0 5 ) /

(TO05) ———— SO30/ (SI11)/ (SDA11)/ TxD3 — (RxDA1) 8P 4 2 — — (PCLBUZ1) ——I V R E F 1 —( I N T P 7 ) ——T I 0 5 / TO05 TRJO0 — — — (SI00)/ (RxD0)/ (SDA00)/ (SO11)/ (TxD1)/ (SO10) (SCLA0) (TxDA1) (TO07) ———— (SI10)/ (SO00)/ (TxD0)/ (SDA10)/ (RxD1) (SDAA0) (RxDA3) (TO05) ———— (SCK10)/ (SCL10) —( T x D A 3 ) (TO01) (TO00) ———— (SCL00)/ (SCK00)

14 P124 — — XT2/

2 0 ———V

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 31 of 145 Oct 31, 2025 2 2 P 6 0 C C D 0 4 E O 6 0 — ————( I N T P 3 ) ——( T I 0 1 ) / (TO01) 2 3 P 6 1 C C D 0 5 E O 6 1 — ————( I N T P 4 ) ——( T I 0 2 ) / (TO02) (TO03)/ (REMO OUT) (SDAA1) — (TO05) 2 6 P 6 2 C C D 0 6 —— ————( I N T P 5 ) ——( T I 0 3 ) / (TO03)/ (REMO OUT) 2 7 P 6 3 C C D 0 7 —— ————( I N T P 6 ) ——( T I 0 4 ) / (TO04) (TO03)/ (REMO OUT)

29 P126 — — — — — — CAPL (INTP4) — TS01 (TI04)/

(TO04) (SO10)

31 P86 — — (PCLBUZ1) ———V L2 (INTP3) — — (TI06)/

(TO06) ————( R x D 1 ) / (SI10)/ (SDA10) (VCOUT0) VL4 ( I N T P 4 ) ——————— (SCK10)/ (SCL10)/ (SCK30)/ (SCL30)

33 P125 — — (PCLBUZ1) —— (VCOUT1) VL3 (INTP7) — TS02 (TI06)/

(TO06) ————( S I 3 0 ) / (RxD3)/ (SDA30) (VCOUT0) S E G 2 5 ( I N T P 4 ) —T S 0 3 —————( S O 3 0 ) / (TxD3) 3 5 P 3 4 ——— ———S E G 2 4 ( I N T P 0 ) —T S 0 4 ( T I 0 1 ) / (TO01) ————( S I 3 0 ) / (RxD3)/ (SDA30) 3 6 P 3 3 ——— ———S E G 2 3 I N T P 4 —T S 0 5 ( T I 0 1 ) / (TO01) ——— (RTC1HZ) (SCK30)/ (SCL30) 3 7 P 3 2 ——— ———S E G 2 2 ( I N T P 3 ) —T S 0 6 T I 0 1 / TO01/ (TI03)/ (TO03)/ (REMO OUT) ——— (RTC1HZ) ——— Table 1 - 7 Multiplexed Pin Functions of the 100-pin Products (2/5) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 100LFQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) LCD controller/driver Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Timer RJ 16-bit timers KB40, KB41, and KB42 External signal sampler Realtime clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA)

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 32 of 145 Oct 31, 2025 3 9 P 3 1 ——— ———S E G 2 1 I N T P 3 —T S 0 7 ( T I 0 1 ) / (TO01) 4 0 P 3 0 ——— ———S E G 2 0 ( I N T P 3 ) —T S 0 8 T I 0 3 / TO03/ REMOO UT ——— (RTC1HZ) ———

41 P77 CCD00 EI77/

— — — — SEG19 (INTP1) KR7 TS09 (TI07)/ (TO07) — TKBO01/ (TKBO21) (EXSDO0) —S O 2 0 / TxD2

42 P76 CCD01 EI76/

— ———S E G 1 8 ( I N T P 2 ) K R 6 T S 1 0 ——T K B O 0 0 (EXSDO1) (RTC1HZ) SI20/ SDA20/ RxD2

43 P75 CCD02 — — — — — SEG17 (INTP0) KR5 TS11 (TI03)/

(TO03)/ (REMO OUT) (TKBO11)/ (TKBO01) ——S C K 2 0 / SCL20

44 P74 CCD03 — — — — — SEG16 — KR4 TS12 — — TKBO11/

(TKBO01) (SDAA1) (RxDA0) 5 1 P 5 7 ——— ———S E G 1 1 I N T P 6 —T S C A P ( T I 0 3 ) / (TO03)/ (REMO OUT) 5 2 P 5 6 ——— ———S E G 1 0 ——T S 1 7 T I 0 6 / TO06 5 3 P 5 5 ——— ———S E G 9 I N T P 5 —T S 1 8 ( T I 0 2 ) / (TO02)

54 P54 — —

(PCLBUZ0) — — — SEG8 (INTP0) — TS19 TI02/ TO02 ————S C L 0 1 / SCK01

55 P53 — — (PCLBUZ0) — — — SEG7 INTP2 — TS20 (TI07)/

(TO07) ————S I 0 1 / SDA01

56 P52 — — (PCLBUZ1) — — — SEG6 INTP1 — TS21 TI00/

——T S 2 4 ( T I 0 5 ) / (TO05) ———— (SCK01)/ (SCL01) (SCLA1) —

60 P96 — — (PCLBUZ0) ———S E G 2 /

(SDA01) (SDAA1) — Table 1 - 7 Multiplexed Pin Functions of the 100-pin Products (3/5) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 100LFQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) LCD controller/driver Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Timer RJ 16-bit timers KB40, KB41, and KB42 External signal sampler Realtime clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA)

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 33 of 145 Oct 31, 2025 COM5 (INTP1) — TS26 (TI02)/ (TO02) COM4 (INTP2) — TS27 (TI06)/ (TO06) ————( S I 0 1 ) / (SDA01) (SCL01) 6 4 P 9 2 ——— ———C O M 2 ——T S 2 9 ( T I 0 1 ) / (TO01) 6 6 P 9 0 ——— ———C O M 0 ( I N T P 1 ) —T S 3 1 ( T I 0 0 ) / (TO00) (SCL10) (SI10)/ (SDA10)

69 P07 — EI07

70 P06 — EI06 (PCLBUZ1) ———S E G 4 9 ——T S 3 3 —————S I 1 0 /

7 1 P 0 5 —E O 0 5 — ———S E G 4 8 ——T S 3 4 —————S C K 1 0 / SCL10

72 P04 — —

(PCLBUZ0) —— VCOUT1 S E G 4 7 ( I N T P 6 ) —T S 3 5 —————( T x D 2 ) / (SO20) (SCL20) (SI20)/ (SDA20) —( T x D A 3 ) (VCOUT1) —( I N T P 7 ) ———————( T x D 2 ) / (SO31)/ (SO20) — (RxDA2) VCOUT0 SEG46 — — — — TRJIO0 — — — (SI31)/ (SDA31)/ (RxD2)/ (SI20)/ (SDA20) —( T x D A 2 ) 7 7 P 0 2 ——P C L B U Z 0 ———S E G 4 5 I N T P 7 ———— (TKBO21) —— (SCK31)/ (SCL31)/ (SCK20)/ (SCL20) 7 8 P 0 1 ——P C L B U Z 1 ———S E G 4 4 ( I N T P 5 ) ——( T I 0 5 ) / (TO05)

79 P00 — EI00/

T O O L T x D ———S E G 4 3 ————( T R J O 0 ) (TKBO01) EXSDI0 — SO00/ TxD0

80 P17 — EI17/

T O O L R x D ———S E G 4 2 ———— (TRJIO0) (TKBO01) EXSDI1 — SI00/ RxD0/ SDA00 Table 1 - 7 Multiplexed Pin Functions of the 100-pin Products (4/5) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 100LFQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) LCD controller/driver Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Timer RJ 16-bit timers KB40, KB41, and KB42 External signal sampler Realtime clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA)

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 34 of 145 Oct 31, 2025

81 P16 — EI16 — — — (VCOUT0) S E G 4 1 ————— (TKBO01) — (RTC1HZ) SCK00/

8 3 P 1 4 ——— A N I 2 6 ——S E G 3 9 ———T I 0 4 / TO04

85 P12 — EI12 (PCLBUZ1) ANI24 — (VCOUT1) SEG37 — — — — (TRJO1) (TKBO00) ——S O 1 1 —C L K A 0

8 6 P 1 1 ——— A N I 2 3 ——S E G 3 6 ( I N T P 1 ) ——— (TRJIO1) (TKBO11) ——S I 1 1 / SDA11 —R x D A 0 8 7 P 1 0 ——— A N I 2 2 ——S E G 3 5 ( I N T P 0 ) ———— (TKBO10) ——S C K 1 1 / SCL11 —T x D A 0

90 P27 — EI27 — ANI21 ANO1 — SEG34 (INTP4) — — — — (TKBO21) (EXSDI1) —( T x D 0 ) /

(SO00)/ SO21 —R x D A 1

91 P26 — EI26 — ANI20 ANO0 — SEG33 (INTP5) — — — —

(TKBO20) (EXSDI0) —S I 2 1 / SDA21/ (RxD0)/ (SI00)/ (SDA00) —T x D A 1 (SCK00)/ (SCL00)/ SCK21/ SCL21

99 P21 — EI21 VBAT1/

(PCLBUZ0) ANI0/ AVREFP

100 P20 — EI20 (PCLBUZ1) ANI1/

Table 1 - 7 Multiplexed Pin Functions of the 100-pin Products (5/5) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 100LFQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) LCD controller/driver Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Timer RJ 16-bit timers KB40, KB41, and KB42 External signal sampler Realtime clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA)

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 35 of 145 Oct 31, 2025

100-pin plastic LQFP (14 × 20 mm, 0.65-mm pitch) Caution 1. Connect the EV SS pin to the same ground as the VSS pin. Caution 2. Connect the REGC pin to V SS via a capacitor (0.47 to 1 µF). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to connect the VSS and EVSS pins to separate ground lines. Remark 3. Functions in parentheses can be assigned via settings in the peripheral I/O redirection registers (PIORx). For details, see 4.3.10 Peripheral I/O redirection registers (PIORx) in the RL78/L23 User’s Manual. P46/SEG26/SI31/SDA31/(SCK21)/(SCL21)/(SCL01)/(SCK01) P45/IVREF0/TxDA2/SCK30/SCL30/EXSDO0 P44/IVCMP0/RxDA2/SI30/SDA30/RxD3/EXSDO1/(TI04)/(TO04)/(INTP7)/(SCK11)/(SCL11) P43/IVCMP1/SO30/TxD3/(TI05)/(TO05)/(INTP4)/(RxDA1)/(SI11)/(SDA11) P42/TI05/TO05/IVREF1/TRJO0/(INTP7)/(TxDA1)/(SCLA0)/(RxD0)/(TxD1)/(SI00)/(SDA00)/(SO10)/(SO11)/(PCLBUZ1) P41/(TI07)/(TO07)/(INTP6)/(TxD0)/(RxDA3)/(SDAA0)/(SO00)/(SI10)/(SDA10)/(RxD1) P66/(TI05)/(TO05)/(INTP1)/(SCK10)/(SCL10)/(TxDA3) P67/(INTP2)/(TI01)/(TO01) P40/TOOL0/(TI00)/(TO00)/(SCK00)/(SCL00) RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0/EI137 P122/X2/EXCLK/EI122 P121/X1/VBAT0/EI121 REGC VSS VDD RL78/L23 (Top View) P47/SEG27/SO31/(RxDA0)/(SI21)/(SDA21)/(SDA01)/(SI01)/(INTP1) P130/SEG28/TRJO1/(TxDA0)/(SO21)/(SO01) P140/SCK31/SCL31 P20/ANI1/AV REFM/EI20/(TI00)/(INTP7)/(PCLBUZ1) P21/ANI0/AVREFP/VBAT1/EI21/(TO00)/(INTP6)/(PCLBUZ0) P22/ANI16/SEG29/SCK21/SCL21/(SCK00)/(SCL00)/(INTP7) P23/ANI17/SEG30/TRJIO1 P141/SEG51/(INTP6)/(RxDA3) P142/SEG52/(INTP7)/(RxDA2) P143/SEG53/(INTP5)/(TxDA2) P24/ANI18/SEG31 P25/ANI19/SEG32/CLKA1 P26/ANI20/SEG33/ANO0/EI26/TxDA1/SI21/SDA21/(TKBO20)/(INTP5)/(RxD0)/(SI00)/(SDA00)/(EXSDI0) P27/ANI21/SEG34/ANO1/EI27/RxDA1/SO21/(TKBO21)/(INTP4)/(TxD0)/(SO00)/(EXSDI1) P144/SEG54/(INTP4)/(RxDA1)/(SCLA0) P145/SEG55/(INTP3)/(TxDA1)/(SDAA0) P10/ANI22/SEG35/TxDA0/SCK11/SCL11/(TKBO10)/(INTP0) P11/ANI23/SEG36/RxDA0/SI11/SDA11/(TKBO11)/(TRJIO1)/(INTP1) P12/ANI24/SEG37/EI12/CLKA0/SO11/(VCOUT1)/(TKBO00)/(TRJO1)/(PCLBUZ1) P13/ANI25/SEG38 P14/TI04/TO04/SEG39/ANI26 P15/TI07/TO07/SEG40 P16/SEG41/SCK00/SCL00/EI16/(VCOUT0)/(TKBO01)/(RTC1HZ) P17/SEG42/SI00/RxD0/TOOLRxD/SDA00/EI17/EO17/EXSDI1/(TKBO01)/(TRJIO0) P00/SEG43/SO00/TxD0/TOOLTxD/EI00/EO00/EXSDI0/(TKBO01)/(TRJO0) P01/PCLBUZ1/SEG44/(TI05)/(TO05)/(TKBO11)/(INTP5)/(SO31) P02/INTP7/PCLBUZ0/SEG45/(TKBO21)/(SCK20)/(SCL20)/(SCK31)/(SCL31) P03/SEG46/VCOUT0/TRJIO0/(TxDA2)/(RxD2)/(SI20)/(SDA20)/(SI31)/(SDA31) P146/(VCOUT1)/(TxD2)/(SO20)/(SO31)/(RxDA2)/(INTP7) P147/(INTP2)/(TxDA3)/(RxD2)/(SI20)/(SDA20) P64/(INTP5)/(SDAA1)/(TI03)/(TO03)/(REMOOUT) P65/(INTP0)/(SCLA1)/(TI05)/(TO05) P62/SCLA1/CCD06/(TI03)/(TO03)/(REMOOUT)/(INTP5) P63/SDAA1/CCD07/(TI04)/(TO04)/(INTP6) P127/CAPH/TS00/(TI03)/(TO03)/(REMOOUT) P126/CAPL/TS01/(TI04)/(TO04)/(INTP4) P87/V L1/(TxD1)/(SO10) P86/VL2/(TI06)/(TO06)/(INTP3)/(RxD1)/(SI10)/(SDA10)/(PCLBUZ1) P85/VL4/(VCOUT0)/(INTP4)/(SCK10)/(SCL10)/(SCK30)/(SCL30) P125/VL3/TS02/(TI06)/(TO06)/(VCOUT1)/(INTP7)/(RxD3)/(SI30)/(SDA30)/(PCLBUZ1) P35/SEG25/TS03/(VCOUT0)/(INTP4)/(SO30)/(TxD3) P34/SEG24/TS04/(TI01)/(TO01)/(INTP0)/(SI30)/(RxD3)/(SDA30) P33/INTP4/SEG23/TS05/(TI01)/(TO01)/(RTC1HZ)/(SCK30)/(SCL30) P32/TI01/TO01/SEG22/TS06/(TI03)/(TO03)/(REMOOUT)/(INTP3)/(RTC1HZ) P31/INTP3/RTC1HZ/SEG21/TS07/(TI01)/(TO01) P30/TI03/TO03/SEG20/REMOOUT/TS08/(INTP3)/(RTC1HZ) P77/KR7/SEG19/TS09/CCD00/TKBO01/SO20/TxD2/EI77/EO77/(TKBO21)/(TI07)/(TO07)/(INTP1)/(EXSDO0) P76/KR6/SEG18/TS10/CCD01/TKBO00/SI20/SDA20/RxD2/EI76/EO76/(INTP2)/(RTC1HZ)/(EXSDO1) EVSS P74/KR4/SEG16/TS12/CCD03/TKBO11/(TKBO01) P73/KR3/SEG15/TS13/TKBO10 P72/KR2/SEG14/TS14/TKBO21 P71/KR1/SEG13/TS15 P70/KR0/SEG12/TS16/TKBO20 P84/(INTP0)/(TxDA0)/(SCLA1) P83/(INTP1)/(RxDA0)/(SDAA1) P57/INTP6/SEG11/TSCAP/(TI03)/(TO03)/(REMOOUT) P56/TI06/TO06/SEG10/TS17 P55/INTP5/SEG9/TS18/(TI02)/(TO02) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 100 P80/(INTP2)/(SCK20)/(SCL20) P04/SEG47/VCOUT1/TS35/(INTP6)/(SO20)/(TxD2)/(PCLBUZ0) P05/SCK10/SCL10/SEG48/TS34/EO05 P06/SI10/RxD1/SDA10/SEG49/TS33/EI06/(PCLBUZ1) P07/SO10/TxD1/SEG50/TS32/EI07/(PCLBUZ0) P81/(RxD1)/(SI10)/(SDA10) P82/(SCK10)/(SCL10)/(PCLBUZ0) P90/COM0/TS31/(TI00)/(TO00)/(INTP1) P91/COM1/TS30/(INTP2) P92/COM2/TS29/(TI01)/(TO01) P93/COM3/TS28/(INTP3)/(SCK01)/(SCL01) P94/COM4/SEG0/TS27/(INTP2)/(SI01)/(SDA01)/(TI06)/(TO06) P95/COM5/SEG1/TS26/(TI02)/(TO02)/(INTP1)/(SO01) P96/COM6/SEG2/TS25/(INTP5)/(SI01)/(SDA01)/(SDAA1)/(PCLBUZ0) P97/COM7/SEG3/TS24/(TI05)/(TO05)/(SCK01)/(SCL01)/(SCLA1) P50/SEG4/TS23/TxDA3 P51/SEG5/TS22/RxDA3/(INTP6) P52/TI00/TO00/INTP1/SEG6/TS21/SO01/(PCLBUZ1) P53/INTP2/SEG7/TS20/SI01/SDA01/(TI07)/(TO07)/(PCLBUZ0) P54/TI02/TO02/SEG8/TS19/SCK01/SCL01/(INTP0)/(PCLBUZ0) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 P75/KR5/SEG17/TS11/CCD02/SCK20/SCL20/(TKBO11)/(TKBO01)/(TI03)/(TO03)/(REMOOUT)/(INTP0) P60/SCLA0/CCD04/EO60/(TI01)/(TO01)/(INTP3) P61/SDAA0/CCD05/EO61/(TI02)/(TO02)/(INTP4)

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 36 of 145 Oct 31, 2025 Table 1 - 8 Multiplexed Pin Functions of the 100-pin Products (1/5) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 100LQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) LCD controller/driver Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Timer RJ 16-bit timers KB40, KB41, and KB42 External signal sampler Realtime clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) (TO03)/ (REMO OUT) (SDAA1) — (TO05)

3 P 6 2 C C D 0 6 —— ————( I N T P 5 ) ——( T I 0 3 ) /

(TO03)/ (REMO OUT)

4 P 6 3 C C D 0 7 —— ————( I N T P 6 ) ——( T I 0 4 ) /

(TO04)

5 P 1 2 7 ——— ———C A P H ——T S 0 0 ( T I 0 3 ) /

(TO03)/ (REMO OUT)

6 P 1 2 6 ——— ———C A P L ( I N T P 4 ) —T S 0 1 ( T I 0 4 ) /

(TO04) (SO10) 8P 8 6 — — (PCLBUZ1) ———V L2 (INTP3) — — (TI06)/ (TO06) ————( R x D 1 ) / (SI10)/ (SDA10) (VCOUT0) VL4 ( I N T P 4 ) ——————— (SCK10)/ (SCL10)/ (SCK30)/ (SCL30)

10 P125 — — (PCLBUZ1) —— (VCOUT1) VL3 (INTP7) — TS02 (TI06)/

(TO06) ————( S I 3 0 ) / (RxD3)/ (SDA30) (VCOUT0) S E G 2 5 ( I N T P 4 ) —T S 0 3 —————( S O 3 0 ) / (TxD3) 1 2 P 3 4 ——— ———S E G 2 4 ( I N T P 0 ) —T S 0 4 ( T I 0 1 ) / (TO01) ————( S I 3 0 ) / (RxD3)/ (SDA30) 1 3 P 3 3 ——— ———S E G 2 3 I N T P 4 —T S 0 5 ( T I 0 1 ) / (TO01) ——— (RTC1HZ) (SCK30)/ (SCL30) 1 4 P 3 2 ——— ———S E G 2 2 ( I N T P 3 ) —T S 0 6 T I 0 1 / TO01/ (TI03)/ (TO03)/ (REMO OUT) ——— (RTC1HZ) ——— 1 6 P 3 1 ——— ———S E G 2 1 I N T P 3 —T S 0 7 ( T I 0 1 ) / (TO01)

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 37 of 145 Oct 31, 2025 1 7 P 3 0 ——— ———S E G 2 0 ( I N T P 3 ) —T S 0 8 T I 0 3 / TO03/ REMOO UT ——— (RTC1HZ) ———

18 P77 CCD00 EI77/

— — — — SEG19 (INTP1) KR7 TS09 (TI07)/ (TO07) — TKBO01/ (TKBO21) (EXSDO0) —S O 2 0 / TxD2

19 P76 CCD01 EI76/

— ———S E G 1 8 ( I N T P 2 ) K R 6 T S 1 0 ——T K B O 0 0 (EXSDO1) (RTC1HZ) SI20/ SDA20/ RxD2

20 P75 CCD02 — — — — — SEG17 (INTP0) KR5 TS11 (TI03)/

(TO03)/ (REMO OUT) (TKBO11)/ (TKBO01) ——S C K 2 0 / SCL20

21 P74 CCD03 — — — — — SEG16 — KR4 TS12 — — TKBO11/

(TKBO01) (SDAA1) (RxDA0) 2 8 P 5 7 ——— ———S E G 1 1 I N T P 6 —T S C A P ( T I 0 3 ) / (TO03)/ (REMO OUT) 2 9 P 5 6 ——— ———S E G 1 0 ——T S 1 7 T I 0 6 / TO06 3 0 P 5 5 ——— ———S E G 9 I N T P 5 —T S 1 8 ( T I 0 2 ) / (TO02)

31 P54 — —

(PCLBUZ0) — — — SEG8 (INTP0) — TS19 TI02/ TO02 ————S C L 0 1 / SCK01

32 P53 — — (PCLBUZ0) — — — SEG7 INTP2 — TS20 (TI07)/

(TO07) ————S I 0 1 / SDA01

33 P52 — — (PCLBUZ1) — — — SEG6 INTP1 — TS21 TI00/

——T S 2 4 ( T I 0 5 ) / (TO05) ———— (SCK01)/ (SCL01) (SCLA1) — (SDA01) (SDAA1) — COM5 (INTP1) — TS26 (TI02)/ (TO02) Table 1 - 8 Multiplexed Pin Functions of the 100-pin Products (2/5) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 100LQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) LCD controller/driver Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Timer RJ 16-bit timers KB40, KB41, and KB42 External signal sampler Realtime clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA)

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 38 of 145 Oct 31, 2025 COM4 (INTP2) — TS27 (TI06)/ (TO06) ————( S I 0 1 ) / (SDA01) (SCL01) 4 1 P 9 2 ——— ———C O M 2 ——T S 2 9 ( T I 0 1 ) / (TO01) 4 3 P 9 0 ——— ———C O M 0 ( I N T P 1 ) —T S 3 1 ( T I 0 0 ) / (TO00) (SCL10) (SI10)/ (SDA10)

46 P07 — EI07

47 P06 — EI06 (PCLBUZ1) ———S E G 4 9 ——T S 3 3 —————S I 1 0 /

4 8 P 0 5 —E O 0 5 — ———S E G 4 8 ——T S 3 4 —————S C K 1 0 / SCL10

49 P04 — —

(PCLBUZ0) —— VCOUT1 S E G 4 7 ( I N T P 6 ) —T S 3 5 —————( T x D 2 ) / (SO20) (SCL20) (SI20)/ (SDA20) —( T x D A 3 ) (VCOUT1) —( I N T P 7 ) ———————( T x D 2 ) / (SO31)/ (SO20) — (RxDA2) VCOUT0 SEG46 — — — — TRJIO0 — — — (SI31)/ (SDA31)/ (RxD2)/ (SI20)/ (SDA20) —( T x D A 2 ) 5 4 P 0 2 ——P C L B U Z 0 ———S E G 4 5 I N T P 7 ———— (TKBO21) —— (SCK31)/ (SCL31)/ (SCK20)/ (SCL20) 5 5 P 0 1 ——P C L B U Z 1 ———S E G 4 4 ( I N T P 5 ) ——( T I 0 5 ) / (TO05)

56 P00 — EI00/

T O O L T x D ———S E G 4 3 ————( T R J O 0 ) (TKBO01) EXSDI0 — SO00/ TxD0

57 P17 — EI17/

T O O L R x D ———S E G 4 2 ———— (TRJIO0) (TKBO01) EXSDI1 — SI00/ RxD0/ SDA00

58 P16 — EI16 — — —

(VCOUT0) S E G 4 1 ————— (TKBO01) — (RTC1HZ) SCK00/ SCL00 Table 1 - 8 Multiplexed Pin Functions of the 100-pin Products (3/5) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 100LQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) LCD controller/driver Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Timer RJ 16-bit timers KB40, KB41, and KB42 External signal sampler Realtime clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA)

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 39 of 145 Oct 31, 2025 TO07 6 0 P 1 4 ——— A N I 2 6 ——S E G 3 9 ———T I 0 4 / TO04

62 P12 — EI12 (PCLBUZ1) ANI24 — (VCOUT1) SEG37 — — — — (TRJO1) (TKBO00) ——S O 1 1 —C L K A 0

6 3 P 1 1 ——— A N I 2 3 ——S E G 3 6 ( I N T P 1 ) ——— (TRJIO1) (TKBO11) ——S I 1 1 / SDA11 —R x D A 0 6 4 P 1 0 ——— A N I 2 2 ——S E G 3 5 ( I N T P 0 ) ———— (TKBO10) ——S C K 1 1 / SCL11 —T x D A 0

67 P27 — EI27 — ANI21 ANO1 — SEG34 (INTP4) — — — —

(TKBO21) (EXSDI1) —( T x D 0 ) / (SO00)/ SO21 —R x D A 1

68 P26 — EI26 — ANI20 ANO0 — SEG33 (INTP5) — — — —

(TKBO20) (EXSDI0) —S I 2 1 / SDA21/ (RxD0)/ (SI00)/ (SDA00) —T x D A 1 (SCK00)/ (SCL00)/ SCK21/ SCL21

76 P21 — EI21 VBAT1/

(PCLBUZ0) ANI0/ AVREFP

77 P20 — EI20 (PCLBUZ1) ANI1/

(SO01) —( T x D A 0 ) (SI01)/ (SI21)/ (SDA01)/ (SDA21) — (RxDA0) Table 1 - 8 Multiplexed Pin Functions of the 100-pin Products (4/5) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 100LQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) LCD controller/driver Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Timer RJ 16-bit timers KB40, KB41, and KB42 External signal sampler Realtime clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA)

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 40 of 145 Oct 31, 2025 SDA31/ (SCL01)/ (SCK01)/ (SCK21)/ (SCL21) SCL30 —T x D A 2 8 3 P 4 4 ——— ——I V C M P 0 —( I N T P 7 ) ——( T I 0 4 ) / (TO04) —— EXSDO1 — SI30/ SDA30/ (SCL11)/ (SCK11)/ RxD3 —R x D A 2 8 4 P 4 3 ——— ——I V C M P 1 —( I N T P 4 ) ——( T I 0 5 ) / (TO05) ———— SO30/ (SI11)/ (SDA11)/ TxD3 — (RxDA1)

85 P42 — — (PCLBUZ1) ——I V R E F 1 —( I N T P 7 ) ——T I 0 5 /

TRJO0 — — — (SI00)/ (RxD0)/ (SDA00)/ (SO11)/ (TxD1)/ (SO10) (SCLA0) (TxDA1) (TO07) ———— (SI10)/ (SO00)/ (TxD0)/ (SDA10)/ (RxD1) (SDAA0) (RxDA3) (TO05) ———— (SCK10)/ (SCL10) —( T x D A 3 ) (TO01) (TO00) ———— (SCL00)/ (SCK00)

91 P124 — — XT2/

9 7 ———V 9 9 P 6 0 C C D 0 4 E O 6 0 — ————( I N T P 3 ) ——( T I 0 1 ) / (TO01)

100 P61 CCD05 EO61 — — — — — (INTP4) — — (TI02)/

(TO02) Table 1 - 8 Multiplexed Pin Functions of the 100-pin Products (5/5) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 100LQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) LCD controller/driver Interrupt Key interrupt Capacitive sensing unit (CTSU2La) Timer array unit (TAU) Timer RJ 16-bit timers KB40, KB41, and KB42 External signal sampler Realtime clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA)

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 41 of 145 Oct 31, 2025

1.4 Pin Identification

ANI0, ANI1, PCLBUZ0, PCLBUZ1: Programmable clock output/buzzer output ANI16 to ANI26: Analog input REGC: Regulator capacitance ANO0, ANO1: Analog output RESET : Reset AVREFM: Analog reference voltage minus RTC1HZ: Realtime clock correction clock (1 Hz) output AVREFP: Analog reference voltage plus RxD0 to RxD3, RxDA0, CCD00 to CCD07: Controlled current drive output RxDA1, RxDA2, RxDA3: Receive data CLKA0, CLKA1: Asynchronous serial clock output SCLA0, SCLA1, CAPH, CAPL: Capacitor for LCD SCK00, SCK01, SCK10, COM0 to COM7: LCD common output SCK11, SCK20, SCK21, EI00, EI06, EI07, EI12, SCK30, SCK31: Serial clock input/output EI16, EI17, EI20, EI21, SCL00, SCL01, SCL10, EI26, EI27, EI76, EI77, SCL11, SCL20, SCL21, EI121, EI122, EI137: Logic & event link controller input SCL30, SCL31: Serial clock output EO00, EO05, EO17, SDAA0, SDAA1, SDA00, EO60, EO61, EO76, SDA01, SDA10, SDA11, EO77: Logic & event link controller output SDA20, SDA21, SDA30, EV SS: Ground for port SDA31: Serial data input/output EXCLK: External clock input SEG0 to SEG55: LCD segment output (main system clock) SI00, SI01, SI10, SI11, EXCLKS: External clock input SI20, SI21, SI30, SI31: Serial data input (subsystem clock) SO00, SO01, SO10, EXSDI0, EXSDI1: External signal sampler input SO11, SO20, SO21, EXSDO0, EXSDO1: External signal sampler clock output SO30, SO31: Serial data output INTP0 to INTP7: Interrupt request from perip heral modules TSCAP: Touch sensor capacitance IVCMP0, IVCMP1: Comparator input TI00 to TI07: Timer input IVREF0, IVREF1: Comparator reference input TO00 to TO07: Timer output KR0 to KR7: Key return input TKBO00, TKBO01, TKBO10, P00 to P07: Port 0 TKBO11, TKBO20, TKBO21: Timer KB40, KB41, KB42 output P10 to P17: Port 1 TOOL0: Data input/output for tool P20 to P27: Port 2 TOOLRxD, TOOLTxD: Data input/output for external device P30 to P35: Port 3 TRJIO0, TRJIO1: Timer RJ input/output P40 to P47: Port 4 TS00 to TS35: Capacitive touch sensor P50 to P57: Port 5 TxD0 to TxD3, TxDA0, P60 to P67: Port 6 TxDA1, TxDA2, TxDA3: Transmit data P70 to P77: Port 7 VBAT0, VBAT1: Battery backup power supply P80 to P87: Port 8 VCOUT0, VCOUT1: Comparator output P90 to P97: Port 9 V DD: Power supply P121 to P127: Port 12 V L1 to VL4: LCD power supply P130, P137: Port 13 V SS:G r o u n d P140 to P147: Port 14 X1, X2: Crystal oscillator (main system clock) XT1, XT2: Crystal oscillator (subsystem clock) REMOOUT: Remote control output

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 42 of 145 Oct 31, 2025

1.5 Block Diagram

Remark m: Unit number, n: Channel number, p: Simplified SPI (CSI) number, q: UART number, r: Simplified I2C number, xx: Port number Voltage regulator REGC Interrupt control RAM Power-on reset/ voltage detector POR/LVD control Reset control UARTq IICr Timer array unit m INTPn CSIp Key return BCD correction Serial interface IICAn Buzzer output Clock output control PCLBUZn RL78 CPU core CRC RxDq TxDq ANIn AVREFP SCLAn SDAAn RTC1HZ RESET KRn Watchdog timer Data transfer controller CHn Port x Pxx Serial array unit m TImn TOmn SCKp SIp SOp SCLr SDAr Code flash memory Data flash memory AVREFM Logic and event link controller Clock generator and reset generator Middle-speed on-chip oscillator 1 to 4 MHz High-speed on-chip oscillator 1 to 32 MHz Subsystem clock oscillator 32.768 kHz X1 X2/EXCLK XT1 XT2/EXCLKS D/A converter Comparator ANOn VOUTn IVCMPn IVREFn Serial interface UARTAn RxDAn TxDAn CLKAn 32-bit interval timer SNOOZE mode sequencer Capacitive sensing unit TSn TSCAP High-speed system clock oscillator 1 to 20 MHz Multiplier, divider, and multiply-accumulator EOn EIn TOOL0 On-chip debugging Safety function Security function Low-speed on-chip oscillator 32.768 kHz Realtime clock A/D converter TOOLRxD/P17, TOOLTxD/P00 VDD VSS, EVSS 8-bit interval timer m CHmn Timer KB4m/KB4m-OP CHmnTKBOmn Timer RJ CHnTRJIOn TRJOn External signal samplerEXSDIn EXSDOn LCD controller/driver RAM space for LCD data SEGn COMn VL1 to VL4 CAPH CAPL Oscillation stop detector

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 43 of 145 Oct 31, 2025

1.6 Outline of Functions

Caution This outline describes the functi ons at the time when the peripheral I/O redirection registers (PIORx) are set to 00H. (1/4) Item 44-pin 48-pin 52-pin 64-pin 80-pin 100-pin R7F100LFx R7F100LGx R7F100LJx R7F100LLx R7F100LMx R7F100LPx Code flash memory 512 KB (256 KB × 2 banks or a single 512-KB bank)

256 KB (128 KB × 2 banks or a single 256-KB bank)

128 KB (single bank)

64 KB (single bank)

512 KB (256 KB × 2 banks or

a single 512-KB bank)

256 KB (128 KB × 2 banks or

a single 256-KB bank) Data flash memory 8 KB 8 KB 8 KB 8 KB 8 KB 8 KB RAM 16 to 32 KB 16 to 32 KB 16 to 32 KB 16 to 32 KB 16 to 32 KB 16 to 32 KB Address space 1 MB CPU/peripheral hardware clock frequency (f CLK) Main system clock HS (high-speed main) mode: 1 to 32 MHz (V DD = 1.8 to 5.5 V) HS (high-speed main) mode: 1 to 4 MHzNote 1 (VDD = 1.6 to 5.5 V) LS (low-speed main) mode: 1 to 24 MHz (VDD = 1.8 to 5.5 V) LS (low-speed main) mode: 1 to 4 MHzNote 1(VDD = 1.6 to 5.5 V) LP (low-power main) mode: 1 to 2 MHzNote 2 (VDD = 1.6 to 5.5 V) Subsystem clock SUB mode: 32.768 kHz (V DD = 1.6 to 5.5 V) Main system clock High-speed system clock (fMX) 1 to 20 MHz High-speed on-chip oscillator clock (fIH)

1 MHz, 2 MHz, 3 MHz, 4 MHz, 6 MHz, 8 MHz, 12 MHz, 16 MHz, 24 MHz, 32 MHz

oscillator clock (fIM)

1 MHz, 2 MHz, 4 MHz

(fSX) 32.768 kHz (VDD = 1.6 to 5.5 V) Low-speed on-chip oscillator clock (fIL) 32.768 kHz (typ.) General-purpose registers 8 bits × 32 regi sters (8 bits × 8 registers × 4 banks) Minimum instruction execution time 0. 03125 µs (at the 32-MHz operation with the high-speed on-chip oscillator clock (fIH)) Instruction set • Data transfer (8/16 bits)

Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits × 8 bits, 16 bits × 16 bits), division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits)
Multiplication and accumulation (16 bits × 16 bits + 32 bits)
Rotate, barrel shift, and bit manipulation (set, reset, test, and Boolean operation), etc. I/O port Total number of pins 40 44 48 60 76 95 CMOS I/O 35 (N-ch open- drain I/O [V DD withstand voltage]: 24) (N-ch open- drain I/O [VDD withstand voltage]: 27) (N-ch open- drain I/O [VDD withstand voltage]: 29) (N-ch open- drain I/O [VDD withstand voltage]: 35) (N-ch open- drain I/O [VDD withstand voltage]: 42) (N-ch open- drain I/O [VDD withstand voltage]: 57) C M O S i n p u t 333333 C M O S o u t p u t ————1 1 N-ch open-drain I/O (withstand voltage: 6 V) 222444 Controlled current drive port 456888

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 44 of 145 Oct 31, 2025 Timers 16-bit timer 8 channels Watchdog timer 1 channel Realtime clock (RTC) 1 channel 32-bit interval timer (TML32) 1 channel in 32-bit counter mode, 2 channels in 16-bit counter mode, 4 channels in 8-bit counter mode 8-bit interval timer Products with 256 or 512 Kbytes of flash memory: 8 units Products with 64 or 128 Kbytes of flash memory: 4 units 8 units 16-bit timer RJ Products with 256 or 512 Kbytes of flash memory: 2 channels Products with 64 or 128 Kbytes of flash memory: 1 channel 2 channels 16-bit timers KB40, KB41, and KB42 Products with 256 or 512 Kbytes of flash memory: 3 channels Products with 64 or 128 Kbytes of flash memory: 1 channel 3 channels External signal sampler 1 channel Oscillation stop detector 1 channel Timer output 6 channels (PWM outputs: 5 Note 3), 8 channels (PWM outputs: 7Note 3)Note 4 8 channels (PWM outputs: 7Note 3) RTC output 1 channel Clock output/buzzer output 2 channels

3.91 kHz, 7.81 kHz, 15.63 kHz, 2 MHz, 4 MHz, 8 MHz, 16 MHz (at the 32-MHz operation with the main system clock (fMAIN)) (at the 32.768-kHz operation with the low-speed peripheral clock (fSXP)) 8-/10-/12-bit resolution A/D converter 8 channel s 9 channels 10 channels 10 channels 13 channels 13 channels D/A converter 3 channels (one of the three interfaces is only for the internal reference voltage for the comparator) Comparator 1 channel 2 channels (2/4) Item 44-pin 48-pin 52-pin 64-pin 80-pin 100-pin R7F100LFx R7F100LGx R7F100LJx R7F100LLx R7F100LMx R7F100LPx

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 45 of 145 Oct 31, 2025 Serial interfaces [44-pin products]

Simplified SPI (CSI): 2 channelsNote 4/simplified I2C: 2 channelsNote 4/UART: 1 channel
Simplified SPI (CSI): 2 channels/simplified I2C: 2 channels/UART: 1 channel
Simplified SPI (CSI): 1 channel/simplified I2C: 1 channel/UART (UART supporting LIN-bus): 1 channel
Simplified I2C: 1 channelNote 4 [48-pin products]
Simplified SPI (CSI): 2 channels Note 4/simplified I2C: 2 channelsNote 4/UART: 1 channel
Simplified SPI (CSI): 2 channels/simplified I2C: 2 channels/UART: 1 channel
Simplified SPI (CSI): 2 channels/simplified I2C: 2 channels/UART (UART supporting LIN- bus): 1 channel
Simplified I2C: 1 channel [52-pin products]
Simplified SPI (CSI): 2 channelsNote 4/simplified I2C: 2 channels/UART: 1 channel
Simplified SPI (CSI): 2 channels/simplified I2C: 2 channels/UART: 1 channel
Simplified SPI (CSI): 2 channels/simplified I2C: 2 channels/UART (UART supporting LIN- bus): 1 channel
Simplified SPI (CSI): 1 channel/simplified I2C: 1 channel/UART: 1 channel [64- and 80-pin products]
Simplified SPI (CSI): 2 channels/simplified I2C: 2 channels/UART: 1 channel
Simplified SPI (CSI): 2 channels/simplified I2C: 2 channels/UART: 1 channel
Simplified SPI (CSI): 2 channels/simplified I2C: 2 channels/UART (UART supporting LIN- bus): 1 channel
Simplified SPI (CSI): 2 channelsNote 4/simplified I2C: 2 channelsNote 4/UART: 1 channel [100-pin products]
Simplified SPI (CSI): 2 channels/simplified I2C: 2 channels/UART: 1 channel
Simplified SPI (CSI): 2 channels/simplified I2C: 2 channels/UART: 1 channel
Simplified SPI (CSI): 2 channels/simplified I2C: 2 channels/UART (UART supporting LIN- bus): 1 channel
Simplified SPI (CSI): 2 channels/simplified I2C: 2 channels/UART: 1 channel UARTA 2 channels Products with 256 or 512 Kbytes of flash memory: 3 channels Products with 64 or 128 Kbytes of flash memory: 2 channels 4 channels I2C bus 2 channels Data transfer controller (DTC) 48 sources (44- and 48- pin products with 64 to 128 Kbytes of flash memory) 49 sources (52- and 64-pin products with 64 to 128 Kbytes of flash memory) 51 sources (44-pin products with 256 to 512 Kbytes of flash memory) 53 sources (48-pin products with 256 to 512 Kbytes of flash memory) 54 sources (52- and 64-pin products with 256 to 512 Kbytes of flash memory) 56 sources (80- and 100-pin products with 128 to 512 Kbytes of flash memory) Logic and event link controller (ELCL) 1 SNOOZE mode sequencer (SMS) 1 Capacitive sensing unit 16 18 20 25 34 36 LCD controller/driver Internal boosting, capacitive division, and external resistor division are switchable as methods of generating the driving voltage. Segment signal outputs × common signal outputs 19 seg × 4 com 17 seg × 6 com 15 seg × 8 com 22 seg × 4 com 20 seg × 6 com 18 seg × 8 com 25 seg × 4 com 23 seg × 6 com 21 seg × 8 com 34 seg × 4 com 32 seg × 6 com 30 seg × 8 com 49 seg × 4 com 47 seg × 6 com 45 seg × 8 com 56 seg × 4 com 54 seg × 6 com 52 seg × 8 com Vectored interrupt sources Internal 47 49 50 50 52 52 E x t e r n a l 999999 K e y i n t e r r u p t 234588 (3/4) Item 44-pin 48-pin 52-pin 64-pin 80-pin 100-pin R7F100LFx R7F100LGx R7F100LJx R7F100LLx R7F100LMx R7F100LPx

RL78/L23 1. Outline R01DS0502EJ0110 Rev.1.10 Page 46 of 145 Oct 31, 2025 Note 1. Overwrite the flash memory during operation at 2 MHz or a lower frequency. Note 2. When the flash memory is to be overwritten, switch to high-speed main (HS) mode or low-speed main (LS) mode. Note 3. The number of PWM outputs varies depending on the setting of channels in use (the number of masters and slaves). For details, see 7.9.3 Operation for the multiple PWM output function in the RL78/L23 User’s Manual. Note 4. This applies when the corresponding bit in the peripheral I/O redirection register (PIORx) is set to 1. Note 5. In normal operation, executing the instruction code FFH triggers an internal reset, but this is not the case during emulation by the on-chip debugging emulator. Reset • Reset by RESET pin

Internal reset by watchdog timer
Internal reset by power-on-reset
Internal reset by voltage detectors (LVD0 and LVD1)
Internal reset by illegal instruction execution Note 5
Internal reset by RAM parity error
Internal reset by illegal-memory access Power-on-reset circuit Detection voltage
1.50 V (typ.) Voltage detector LVD0 Detection voltage
Rising edge: 1.69 V to 3.96 V (6 stages)
Falling edge: 1.65 V to 3.88 V (6 stages) LVD1 Detection voltage
Rising edge: 1.67 V to 4.16 V (18 stages)
Falling edge: 1.63 V to 4.08 V (18 stages) On-chip debugging Available (tracing supported) Power supply voltage V DD = 1.6 to 5.5 V Operating ambient temperature T A = –40 to +105°C (3C: Industrial applications) (4/4) Item 44-pin 48-pin 52-pin 64-pin 80-pin 100-pin R7F100LFx R7F100LGx R7F100LJx R7F100LLx R7F100LMx R7F100LPx

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 47 of 145 Oct 31, 2025 2. Electrical Characteristics Caution 1. RL78 microcontrollers have on-chip debugging functionality for use in the development and evaluation of user systems. Do not use on-chip debugging with products designated as part of mass production, because using this function may cause the guaranteed number of times the flash memory is rewritten to be exceeded, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when on-chip debugging is used with products designated as part of mass production. Caution 2. For products that do not have EV SS pins, read EVSS as VSS. Caution 3. The present pins differ depending on the products. For details, see section 2.1 Functions of Port Pins through section 2.2.1 Functions for each product in the RL78/L23 User’s Manual.

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 48 of 145 Oct 31, 2025

2.1 Absolute Maximum Ratings

Note 1. Connect the REGC pin to VSS via a capacitor (0.47 to 1 µF). The listed value is the absolute maximum rating of the REGC pin. Only use the capacitor connection. Do not apply a specific voltage to this pin. Note 2. This voltage must be no higher than 6.5 V. Note 3. The voltage on a pin in use for A/D conversion must not exceed AVREFP +0.3. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark 1. The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified. Remark 2. AV REFP refers to the positive reference voltage of the A/D converter. Remark 3. The reference voltage is VSS. (1/2) Item Symbols Conditions Ratings Unit Supply voltage V DD -0.5 to +6.5 V EVSS -0.5 to +0.3 V REGC pin input voltage V IREGC REGC -0.3 to +2.1 and -0.3 to VDD +0.3Note 1 V Input voltage V I1 P00 to P07, P10 to P17, P22 to P27, P30 to P35, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P125 to P127, P140 to P147 -0.3 to V DD +0.3Note 2 V VI2 P60 to P63 (N-ch open-drain) -0.3 to +6.5 V VI3 P20, P21, P121 to P124, P137, EXCLK, EXCLKS, RESET -0.3 to VDD +0.3Note 2 V Output voltage V O1 P00 to P07, P10 to P17, P22 to P27, P30 to P35, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P125 to P127, P140 to P147 -0.3 to V DD +0.3Note 2 V VO2 P20, P21, P121, P122 -0.3 to VDD +0.3Note 2 V Analog input voltage V AI1 ANI16 to ANI26 -0.3 to V DD +0.3 and -0.3 to AVREFP +0.3Notes 2, 3 V VAI2 ANI0, ANI1 -0.3 to V DD +0.3 and -0.3 to AVREFP +0.3Notes 2, 3 V

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 49 of 145 Oct 31, 2025 Note The rating for the following port pins is 80 mA when IOL1 = 40.0 mA is specified by the 40-mA port output control register (PTDC). Pins P00, P05, and P16 of 44- to 52-pin products, and of 64-pin products with 64- to 128-Kbyte code flash memory Pins P07, P10, and P27 of 64-pin products with 256- to 512-Kbyte code flash memory, and of 80- and 100-pin products Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified. (2/2) Item Symbols Conditions Ratings Unit High-level output current I OH1 Per pin P00 to P07, P10 to P17, P22 to P27, P30 to P35, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P125 to P127, P130, P140 to P147 -40 mA Total of all pins -170 mA P40 to P47, P66, P67, P130, P140 -70 mA P00 to P07, P10 to P17, P22 to P27, P30 to P35, P50 to P57, P64, P65, P70 to P77, P80 to P87, P90 to P97, P125 to P127, P141 to P147 -100 mA I OH2 Per pin P20, P21, P121, P122 -5 mA Total of all pins -20 mA Low-level output current I OL1 Per pin P00 to P07, P10 to P17, P22 to P27, P30 to P35, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P125 to P127, P130, P140 to P147 Note mA Total of all pins 170 mA P40 to P47, P66, P67, P130, P140 70 mA P00 to P07, P10 to P17, P22 to P27, P30 to P35, P50 to P57, P64, P65, P70 to P77, P80 to P87, P90 to P97, P125 to P127, P141 to P147 100 mA I OL2 Per pin P20, P21, P121, P122 10 mA Total of all pins 20 mA Ambient operating temperature TA In normal operation mode -40 to +105 °C In flash memory programming mode -40 to +105 Storage temperature T stg -65 to +150 °C

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 50 of 145 Oct 31, 2025

2.2 Characteristics of the Oscillators

2.2.1 Characteristics of the X1 oscillator

Note The listed time and frequency indicate permissible ranges of the oscillator. For actual applications, request evaluation by the manufacturer of the oscillator circuit mounted on a board so you can use appropriate values. See AC Characteristics for instruction execution time. Caution Since the CPU is started by the high-speed on-chip o scillator clock after release from the reset state, the user should use the oscillation stabilization time counter status register (OSTC) to check the X1 clock oscillation stabilization time. Specify the values for the oscillation stabilization time in the OSTC register and the oscillation stabilization time select register (OSTS) after having sufficiently evaluated the oscillation stabilization time with the resonator to be used.

2.2.2 Characteristics of the XT1 oscillator

Note The listed time and frequency indicate permissible ranges of the oscillator. For actual applications, request evaluation by the manufacturer of the oscillator circuit mounted on a board so you can use appropriate values. See AC Characteristics for instruction execution time. (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Item Resonator Conditions Min. Typ. Max. Unit X1 clock oscillation allowable input cycle timeNote Ceramic resonator/ crystal resonator 0.05 1 µs (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Item Resonator Conditions Min. Typ. Max. Unit XT1 clock oscillation frequency (fXT)Note Crystal resonator 32.768 kHz

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 51 of 145 Oct 31, 2025

2.2.3 Characteristics of the On-chip Oscillators

Note 1. The listed condition applies when the setting of the FRQSEL3 bit in the user option byte is 1. Note 2. The listed values only indicate the characteristics of the oscillators. See 2.4 AC Characteristics for instruction execution time. Note 3. These values are the results of characteristic evaluation and are not checked for shipment. (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Item Symbols Conditions Min. Typ. Max. Unit High-speed on-chip oscillator clock frequency fIH 13 2 M H z High-speed on-chip oscillator clock frequency accuracy HIPREC = 1 -40 to +105°C -1.0 +1.0 % HIPREC = 0Note 1 -15 0 % High-speed on-chip oscillator clock correction resolution 0.05 % Middle-speed on-chip oscillator clock frequencyNote 2 fIM 14 M H z Middle-speed on-chip oscillator clock frequency accuracy -12 +12 % Middle-speed on-chip oscillator clock correction resolution 0.15 % Middle-speed on-chip oscillator frequency temperature coefficient ±0.17 Note 3 %/°C Low-speed on-chip oscillator clock frequencyNote 2 fIL 32.768 kHz Low-speed on-chip oscillator clock frequency accuracy -15 +15 % Low-speed on-chip oscillator clock correction resolution 0.3 % Low-speed on-chip oscillator frequency temperature coefficient ±0.21 Note 3 %/°C

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 52 of 145 Oct 31, 2025

2.3 DC Characteristics

2.3.1 Pin characteristics

Note 1. Device operation is guaranteed at the listed currents even if current is flowing from the VDD pin to an output pin. Note 2. The combination of these and other pins must also not exceed the value for maximum total current. Note 3. The listed currents apply when the duty cycle is no greater than 70%. Use the following formula to calculate the output current when the duty cycle is greater than 70%, where n is the duty cycle.

Total output current from the listed pins = (IOH × 0.7)/(n × 0.01) Example when n = 80% and IOH = -10.0 mA Total output current from the listed pins = (-10.0 × 0.7)/(80 × 0.01) ≈ -8.7 mA Note that the duty cycle has no effect on the current that is allowed to flow into a single pin. A current higher than the absolute maximum rating must not flow into a single pin. (Notes, Caution, and Remark continue on the next page.) (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) (1/7) Item Symbols Conditions Min. Typ. Max. Unit Allowable high-level output currentNote 1 IOH1 Per pin for P00 to P07, P10 to P17, P22 to P27, P30 to P35, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P125 to P127, P130, P140 to P147

1.6 V ≤ V

DD ≤ 5.5 V -10.0 Note 2 mA Total of P40 to P47, P66, P67, P130, P140 (when duty ≤ 70%Note 3) 4.0 V ≤ VDD ≤ 5.5 V -55.0 Note 4 mA 2.7 V ≤ VDD < 4.0 V -10.0 mA 1.8 V ≤ VDD < 2.7 V -5.0 mA 1.6 V ≤ VDD < 1.8 V -2.5 mA Total of P00 to P07, P10 to P17, P22 to P27, P30 to P35, P50 to P57, P64, P65, P70 to P77, P80 to P87, P90 to P97, P125 to P127, P141 to P147 (when duty ≤ 70% Note 3) 4.0 V ≤ VDD ≤ 5.5 V -80.0 Note 5 mA 2.7 V ≤ VDD < 4.0 V -19.0 mA 1.8 V ≤ VDD < 2.7 V -10.0 mA 1.6 V ≤ VDD < 1.8 V -5.0 mA Total of all pins (when duty ≤ 70%Note 3) 1.6 V ≤ VDD ≤ 5.5 V -135.0 Note 6 mA IOH2 Per pin for P20, P21, P121, P122 4.0 V ≤ VDD ≤ 5.5 V -3.0 Note 2 mA 2.7 V ≤ VDD < 4.0 V -1.0 Note 2 mA 1.8 V ≤ VDD < 2.7 V -1.0 Note 2 mA 1.6 V ≤ VDD < 1.8 V -0.5 Note 2 mA Total of all pins (when duty ≤ 70%Note 3) 4.0 V ≤ VDD ≤ 5.5 V -20.0 mA 2.7 V ≤ VDD < 4.0 V -10.0 mA 1.8 V ≤ VDD < 2.7 V -5.0 mA 1.6 V ≤ VDD < 1.8 V -5.0 mA

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 53 of 145 Oct 31, 2025 Note 4. The maximum value is -30 mA with an ambient operating temperature range of +85°C to +105°C. Note 5. The maximum value is -50 mA with an ambient operating temperature range of +85°C to +105°C. Note 6. The maximum values are respectively -100 mA and -60 mA with an ambient operating temperature range of -40 to +85°C and of +85°C to +105°C. Caution The following pins do not output high-level signals in the N-ch open-drain mode: P00 to P07, P10, P11, P16, P17, P22, P26, P27, P33 to P35, P40 to P47, P50, P52 to P54, P64 to P66, P75 to P77, P80 to P87, P93 to P97, P125, P130, P140, and P143 to P147 Remark The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified.

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 54 of 145 Oct 31, 2025 Note 1. Device operation is guaranteed at the listed currents even if current is flowing from an output pin to the EVSS, or VSS pin. Note 2. The combination of these and other pins must also not exceed the value for maximum total current. Note 3. The maximum rating for the following port pins is 40 mA when IOL1 = 40.0 mA is specified by the 40-mA port output control register (PTDC). Pins P00, P05, and P16 of 44- to 52-pin products, and of 64-pin products with 64- to 128-Kbyte code flash memory Pins P07, P10, and P27 of 64-pin products with 256- to 512-Kbyte code flash memory, and of 80- and 100-pin products Note 4. The listed currents apply when the duty cycle is no greater than 70%. Use the following formula to calculate the output current when the duty cycle is greater than 70%, where n is the duty cycle.

Total output current from the listed pins = (I Example when n = 80% and IOL = 10.0 mA Total output current from the listed pins = (10.0 × 0.7)/(80 × 0.01) ≈ 8.7 mA Note that the duty cycle has no effect on the current that is allowed to flow into a single pin. A current higher than the absolute maximum rating must not flow into a single pin. Note 5. The maximum value is 40 mA with an ambient operating temperature range of +85°C to +105°C. Note 6. The maximum value is 80 mA with an ambient operating temperature range of +85°C to +105°C. Remark The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified. (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) (2/7) Item Symbols Conditions Min. Typ. Max. Unit Allowable low-level output currentNote 1 IOL1 Per pin for P00 to P07, P10 to P17, P22 to P27, P30 to P35, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P125 to P127, P130, P140 to P147 20.0 Notes 2, 3 mA Per pin for P60 to P63 15.0 Note 2 mA Total of P40 to P47, P66, P67, P130, P140 (when duty ≤ 70%Note 4) 4.0 V ≤ VDD ≤ 5.5 V 70.0 Note 5 mA 2.7 V ≤ VDD < 4.0 V 15.0 mA 1.8 V ≤ VDD < 2.7 V 9.0 mA 1.6 V ≤ VDD < 1.8 V 4.5 mA Total of P00 to P07, P10 to P17, P22 to P27, P30 to P35, P50 to P57, P64, P65, P70 to P77, P80 to P87, P90 to P97, P125 to P127, P141 to P147 (when duty ≤ 70% Note 4) 4.0 V ≤ VDD ≤ 5.5 V 80.0 Note 5 mA 2.7 V ≤ VDD < 4.0 V 35.0 mA 1.8 V ≤ VDD < 2.7 V 20.0 mA 1.6 V ≤ VDD < 1.8 V 10.0 mA Total of all pins (when duty ≤ 70%Note 4) 150.0 Note 6 mA IOL2 Per pin for P20, P21, P121, P122 4.0 V ≤ VDD ≤ 5.5 V 8.5Note 2 mA 2.7 V ≤ VDD < 4.0 V 1.5Note 2 mA 1.8 V ≤ VDD < 2.7 V 0.6Note 2 mA 1.6 V ≤ VDD < 1.8 V 0.4Note 2 mA Total of all pins (when duty ≤ 70%Note 4) 4.0 V ≤ VDD ≤ 5.5 V 20 mA 2.7 V ≤ VDD < 4.0 V 20 mA 1.8 V ≤ VDD < 2.7 V 15 mA 1.6 V ≤ VDD < 1.8 V 10 mA

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 55 of 145 Oct 31, 2025 Caution The maximum value of V IH of the following pins is VDD, even in the N-ch open-drain mode: P00 to P07, P10, P11, P16, P17, P22, P26, P27, P33 to P35, P40 to P47, P50, P52 to P54, P64 to P66, P75 to P77, P80 to P87, P93 to P97, P125, P130, P140, and P143 to P147. Remark The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified. (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) (3/7) Item Symbols Conditions Min. Typ. Max. Unit Input voltage, high V IH1 P00 to P07, P10 to P17, P22 to P27, P30 to P35, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P125 to P127, P140 to P147 Normal input buffer 0.8 V DD VDD V VIH2 P02, P03, P05, P06, P11, P16, P17, P22, P26, P27, P33, P34, P40 to P47, P51, P53, P54, P64 to P66, P75, P76, P80 to P86, P93, P94, P96, P97, P125, P140 to P142, P144 to P147 TTL input buffer

4.0 V ≤ V

DD ≤ 5.5 V

2.2 V DD V

3.3 V ≤ VDD < 4.0 V

2.0 V DD V

1.6 V ≤ VDD < 3.3 V

1.5 V DD V

VIH3 P20, P21 0.7 V DD VDD V VIH4 P60 to P63 0.7 V DD 6.0 V VIH5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0.8 VDD VDD V Input voltage, low V IL1 P00 to P07, P10 to P17, P22 to P27, P30 to P35, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P125 to P127, P140 to P147 Normal input buffer 0 0.2 V DD V VIL2 P02, P03, P05, P06, P11, P16, P17, P22, P26, P27, P33, P34, P40 to P47, P51, P53, P54, P64 to P66, P75, P76, P80 to P86, P93, P94, P96, P97, P125, P140 to P142, P144 to P147 TTL input buffer DD ≤ 5.5 V 00 . 8 V TTL input buffer 3.3 V ≤ VDD < 4.0 V 00 . 5 V TTL input buffer 1.6 V ≤ VDD < 3.3 V 00 . 3 2 V VIL3 P20, P21 0 0.3 V DD V VIL4 P60 to P63 0 0.3 V DD V VIL5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0 0.2 V DD V

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 56 of 145 Oct 31, 2025 Caution The following pins do not output high-level signals in the N-ch open-drain mode: P00 to P07, P10, P11, P16, P17, P22, P26, P27, P33 to P35, P40 to P47, P50, P52 to P54, P64 to P66, P75 to P77, P80 to P87, P93 to P97, P125, P130, P140, and P143 to P147 Remark The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified. (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) (4/7) Item Symbols Conditions Min. Typ. Max. Unit Output voltage, high V OH1 P00 to P07, P10 to P17, P22 to P27, P30 to P35, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P125 to P127, P130, P140 to P147 DD ≤ 5.5 V, IOH1 = -10.0 mA VDD -1.5 V 4.0 V ≤ VDD ≤ 5.5 V, IOH1 = -3.0 mA VDD -0.7 V 2.7 V ≤ VDD ≤ 5.5 V, IOH1 = -2.0 mA VDD -0.6 V 1.8 V ≤ VDD ≤ 5.5 V, IOH1 = -1.5 mA VDD -0.5 V 1.6 V ≤ VDD < 5.5 V, IOH1 = -1.0 mA VDD -0.5 V VOH2 P20, P21, P121, P122 4.0 V ≤ VDD ≤ 5.5 V, IOH2 = -3.0 mA VDD -0.7 V 2.7 V ≤ VDD < 4.0 V, IOH2 = -1.0 mA VDD -0.5 V 1.8 V ≤ VDD < 2.7 V, IOH2 = -1.0 mA VDD -0.5 V 1.6 V ≤ VDD < 1.8 V, IOH2 = -0.5 mA VDD -0.5 V

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 57 of 145 Oct 31, 2025 Note The listed value applies when IOL1 = 40.0 mA is specified for the following port pins by the 40-mA port output control register (PTDC). Pins P00, P05, and P16 of 44- to 52-pin products, and of 64-pin products with 64- to 128-Kbyte code flash memory Pins P07, P10, and P27 of 64-pin products with 256- to 512-Kbyte code flash memory, and of 80- and 100-pin products Remark The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified. (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) (5/7) Item Symbols Conditions Min. Typ. Max. Unit Output voltage, low VOL1 P00 to P07, P10 to P17, P22 to P27, P30 to P35, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P125 to P127, P130, P140 to P147 DD ≤ 5.5 V I OL1 = 20.0 mA 1.3 V IOL1 = 40.0 mANote 1.3 V 4.0 V ≤ VDD ≤ 5.5 V I OL1 = 8.5 mA 0.7 V IOL1 = 17.0 mANote 0.7 V 2.7 V ≤ VDD ≤ 5.5 V I OL1 = 3.0 mA 0.6 V IOL1 = 6.0 mANote 0.6 V 2.7 V ≤ VDD ≤ 5.5 V I OL1 = 1.5 mA 0.4 V IOL1 = 3.0 mANote 0.4 V 1.8 V ≤ VDD ≤ 5.5 V I OL1 = 0.6 mA 0.4 V IOL1 = 1.2 mANote 0.4 V 1.6 V ≤ VDD ≤ 5.5 V I OL1 = 0.3 mA 0.4 V IOL1 = 0.6 mANote 0.4 V VOL2 P20, P21, P121, P122 4.0 V ≤ VDD ≤ 5.5 V, IOL2 = 8.5 mA 0.7 V 2.7 V ≤ VDD < 4.0 V, IOL2 = 1.5 mA 0.5 V 1.8 V ≤ VDD < 2.7 V, IOL2 = 0.6 mA 0.4 V 1.6 V ≤ VDD < 1.8 V, IOL2 = 0.4 mA 0.4 V VOL3 P60 to P63 4.0 V ≤ VDD ≤ 5.5 V, IOL3 = 15.0 mA 2.0 V 4.0 V ≤ VDD ≤ 5.5 V, IOL3 = 5.0 mA 0.4 V 2.7 V ≤ VDD ≤ 5.5 V, IOL3 = 3.0 mA 0.4 V 1.8 V ≤ VDD ≤ 5.5 V, IOL3 = 2.0 mA 0.4 V 1.6 V ≤ VDD ≤ 5.5 V, IOL3 = 1.0 mA 0.4 V

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 58 of 145 Oct 31, 2025 Note The listed currents apply when the output current control function is enabled. (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) (6/7) Item Symbols Conditions Min. Typ. Max. Unit Output currentNote CCDIOL P74 to P77, P60 to P63

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 59 of 145 Oct 31, 2025 Remark The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified. (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) (7/7) Item Symbols Conditions Min. Typ. Max. Unit Input leakage current, high ILIH1 P00 to P07, P10 to P17, P22 to P27, P30 to P35, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P125 to P127, P140 to P147 V I = VDD 0.5 µA ILIH2 P20, P21, P137, RESET VI = VDD 0.5 µA ILIH3 P121 to P124 (X1, X2, XT1, XT2, EXCLK, EXCLKS) VI = VDD 0.5 µA Input leakage current, low ILIL1 P00 to P07, P10 to P17, P22 to P27, P30 to P35, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P125 to P127, P140 to P147 V I = EVSS -0.5 µA ILIL2 P20, P21, P137, RESET VI = VSS -0.5 µA ILIL3 P121 to P124 (X1, X2, XT1, XT2, EXCLK, EXCLKS) VI = VSS -0.5 µA On-chip pull-up resistance RU P00 to P07, P10 to P17, P22 to P27, P30 to P35, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P121, P122, P125 to P127, P140 to P147 V I = EVSS, In input port 10 20 100 k Ω

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 60 of 145 Oct 31, 2025

2.3.2 Supply current characteristics

44- to 64-pin products with 256- to 512-Kbyte code flash memory and 80- to 100-pin products Note 1. The listed currents are the total currents flowing into VDD, including the input leakage currents flowing when the level of the input pin is fixed to VDD, VSS, or EVSS. In the HS (high-speed main), LS (low-speed main), and LP (low-power main) modes, the currents in the Typ. column do not include the operating currents of the peripheral modules. The currents in the Max. column include the operating currents of the PCLBUZ, TAU, SAU, and IICA modules. The operating currents of other peripheral modules are not included. Note 2. The listed currents apply when the high-speed system clock, middle-speed on-chip oscillator, low-speed on-chip oscillator, and subsystem clock are stopped. Note 3. The listed currents apply when the high-speed on-chip oscillator, high-speed system clock, low-speed on-chip oscillator, and subsystem clock are stopped. (Note and Remarks are listed on the next page.) (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) (1/4) Item Symbols Conditions Min. Typ. Max. Unit Supply current Note 1 IDD1 Operating mode HS (high-speed main) mode f IH = 32 MHzNote 2 Basic operation VDD = 5.0 V 1.6 — mA VDD = 1.8 V 1.6 — Normal operation VDD = 5.0 V 3.5 5.9 mA VDD = 1.8 V 3.5 5.9 LS (low-speed main) mode fIH = 24 MHzNote 2 Normal operation VDD = 5.0 V 2.6 4.5 mA VDD = 1.8 V 2.6 4.5 fIH = 16 MHzNote 2 Normal operation VDD = 5.0 V 1.9 3.2 mA VDD = 1.8 V 1.9 3.2 fIM = 4 MHzNote 3 Normal operation VDD = 5.0 V 0.5 0.9 mA VDD = 1.6 V 0.5 0.9 LP (low-power main) mode fIM = 2 MHzNote 3 Normal operation VDD = 5.0 V 227 379 µA VDD = 1.6 V 226 378 fIM = 1 MHzNote 3 Normal operation VDD = 5.0 V 126 205 µA VDD = 1.6 V 125 204 HS (high-speed main) mode fMX = 20 MHzNote 4, Square wave input Normal operation VDD = 5.0 V 2.3 3.8 mA VDD = 1.8 V 2.2 3.8 LS (low-speed main) mode f MX = 20 MHzNote 4, Square wave input Normal operation VDD = 5.0 V 2.2 3.7 mA VDD = 1.8 V 2.1 3.6 fMX = 20 MHzNote 4, Resonator connection Normal operation VDD = 5.0 V 2.3 3.9 mA VDD = 1.8 V 2.3 3.8 fMX = 10 MHzNote 4, Square wave input Normal operation VDD = 5.0 V 1.1 1.9 mA VDD = 1.8 V 1.1 1.9 fMX = 10 MHzNote 4, Resonator connection Normal operation VDD = 5.0 V 1.2 2.1 mA VDD = 1.8 V 1.2 2.1 fMX = 8 MHzNote 4, Square wave input Normal operation VDD = 5.0 V 0.9 1.5 mA VDD = 1.8 V 0.9 1.5 fMX = 8 MHzNote 4, Resonator connection Normal operation VDD = 5.0 V 1.0 1.7 mA VDD = 1.8 V 1.0 1.7

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 61 of 145 Oct 31, 2025 Note 4. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, low-speed on-chip oscillator, and subsystem clock are stopped. Remark 1. fIH: High-speed on-chip oscillator clock frequency Remark 2. fIM: Middle-speed on-chip oscillator clock frequency Remark 3. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 4. The typical value for the ambient operating temperature (TA) is +25°C unless otherwise specified.

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 62 of 145 Oct 31, 2025 1. 44- to 64-pin products with 256- to 512-Kbyte code flash memory and 80- to 100-pin products Note 1. The listed currents are the total currents flowing into VDD, including the input leakage currents flowing when the level of the input pin is fixed to VDD, VSS, or EVSS. In the subsystem clock operation mode, the currents in the Typ. and Max. columns do not include the operating currents of the peripheral modules. Note 2. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped. Note 3. The listed currents apply when the high-speed on-chip oscillator, high-speed system clock, middle-speed on-chip oscillator, and low-speed on-chip oscillator are stopped, and the low power consumption oscillation 3 is specified (AMPHS1, AMPHS0 = 11B). Remark 1. fIL: Low-speed on-chip oscillator clock frequency Remark 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) (2/4) Item Symbols Conditions Min. Typ. Max. Unit Supply current Note 1 IDD1 Operating mode Subsystem clock operation mode f SUB = 32.768 kHzNote 2, Low-speed on-chip oscillator operation Normal operation T A = -40°C 3.8 6.7 µA TA = +25°C 4.2 7.0 TA = +105°C 10.8 87.2 fSUB = 32.768 kHzNote 3, Square wave input Normal operation TA = -40°C 4.0 7.3 µA TA = +25°C 4.2 8.2 TA = +105°C 10.7 89.3 fSUB = 32.768 kHzNote 3, Resonator connection Normal operation TA = -40°C 3.9 6.9 µA TA = +25°C 4.1 7.3 TA = +105°C 10.2 87.0

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 63 of 145 Oct 31, 2025 1. 44- to 64-pin products with 256- to 512-Kbyte code flash memory and 80- to 100-pin products Note 1. The listed currents are the total currents flowing into VDD, including the input leakage currents flowing when the level of the input pin is fixed to VDD, VSS, or EVSS. In the HS (high-speed main), LS (low-speed main), and LP (low-power main) modes, the currents in the Typ. column do not include the operating currents of the peripheral modules. The currents in the Max. column include the operating currents of the PCLBUZ, TAU, SAU, and IICA modules. The operating currents of other peripheral modules are not included. Note 2. The listed currents apply when the HALT instruction has been fetched from the flash memory for execution. Note 3. The listed currents apply when the high-speed system clock, middle-speed on-chip oscillator, low-speed on-chip oscillator, and subsystem clock are stopped. Note 4. The listed currents apply when the high-speed on-chip oscillator, high-speed system clock, low-speed on-chip oscillator, and subsystem clock are stopped. Note 5. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, low-speed on-chip oscillator, and subsystem clock are stopped. Remark 1. f IH: High-speed on-chip oscillator clock frequency Remark 2. fIM: Middle-speed on-chip oscillator clock frequency Remark 3. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 4. The typical value for the ambient operating temperature (TA) is +25°C unless otherwise specified. (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) (3/4) Item Symbols Conditions Min. Typ. Max. Unit Supply currentNote 1 IDD2 Note 2 HALT mode HS (high-speed main) mode fIH = 32 MHzNote 3 VDD = 5.0 V 0.61 2.24 mA VDD = 1.8 V 0.60 2.23 LS (low-speed main) mode fIH = 24 MHzNote 3 VDD = 5.0 V 0.51 1.74 mA VDD = 1.8 V 0.50 1.73 fIH = 16 MHzNote 3 VDD = 5.0 V 0.47 1.33 mA VDD = 1.8 V 0.47 1.32 fIM = 4 MHzNote 4 VDD = 5.0 V 0.09 0.31 mA VDD = 1.6 V 0.09 0.30 LP (low-power main) mode f IM = 2 MHzNote 4 VDD = 5.0 V 38 140 µA VDD = 1.6 V 37 138 fIM = 1 MHzNote 4 VDD = 5.0 V 32 86 µA VDD = 1.6 V 31 85 HS (high-speed main) mode f MX = 20 MHzNote 5, Square wave input VDD = 5.0 V 0.24 1.23 mA VDD = 1.8 V 0.23 1.21 LS (low-speed main) mode fMX = 20 MHzNote 5, Square wave input VDD = 5.0 V 0.24 1.22 mA VDD = 1.8 V 0.23 1.22 fMX = 20 MHzNote 5, Resonator connection VDD = 5.0 V 0.51 1.56 mA VDD = 1.8 V 0.49 1.54 fMX = 10 MHzNote 5, Square wave input VDD = 5.0 V 0.15 0.65 mA VDD = 1.8 V 0.12 0.61 fMX = 10 MHzNote 5, Resonator connection VDD = 5.0 V 0.30 0.84 mA VDD = 1.8 V 0.29 0.82 fMX = 8 MHzNote 5, Square wave input VDD = 5.0 V 0.13 0.54 mA VDD = 1.8 V 0.10 0.50 fMX = 8 MHzNote 5, Resonator connection VDD = 5.0 V 0.26 0.70 mA VDD = 1.8 V 0.25 0.68 <R> <R> <R> <R>

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 64 of 145 Oct 31, 2025 1. 44- to 64-pin products with 256- to 512-Kbyte code flash memory and 80- to 100-pin products (Notes and Remarks are listed on the next page.) (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) (4/4) Item Symbols Conditions Min. Typ. Max. Unit Supply current Note 1 IDD2 Note 2 HALT mode Subsystem clock operation mode fSUB = 32.768 kHzNote 3, Low-speed on-chip oscillator operation T A = -40°C 0.76 3.30 µA TA = +25°C 0.90 3.38 TA = +50°C 1.12 8.20 TA = +70°C 1.61 21.16 TA = +85°C 2.53 36.29 TA = +105°C 5.39 81.33 fSUB = 32.768 kHz, Square wave inputNote 4 TA = -40°C 0.41 3.39 µA TA = +25°C 0.63 4.23 TA = +50°C 0.87 9.24 TA = +70°C 1.38 22.24 TA = +85°C 2.35 38.01 TA = +105°C 5.22 83.22 fSUB = 32.768 kHz, Resonator connectionNote 5 TA = -40°C 0.36 3.04 µA TA = +25°C 0.50 3.32 TA = +50°C 0.72 8.19 TA = +70°C 1.22 21.12 TA = +85°C 2.11 36.33 TA = +105°C 4.92 81.12 IDD3 STOP mode RAMSDMD = 0, RAMSDS = 0Note 6 TA = -40°C 0.24 2.20 µA TA = +25°C 0.34 2.20 TA = +50°C 0.55 7.00 TA = +70°C 1.06 20.00 TA = +85°C 1.92 35.00 TA = +105°C 4.76 80.00 RAMSDMD = 1, RAMSDS = 1Note 7 TA = -40°C 0.23 2.20 µA TA = +25°C 0.33 2.20 TA = +50°C 0.51 7.00 TA = +70°C 0.91 17.00 TA = +85°C 1.66 30.00 TA = +105°C 4.06 70.00 RAMSDMD = 1, RAMSDS = 1, 128-Hz realtime clock operationNote 8 TA = -40°C 0.28 2.30 µA TA = +25°C 0.40 2.30 TA = +50°C 0.60 7.10 TA = +70°C 0.99 17.10 TA = +85°C 1.76 30.10 TA = +105°C 4.16 70.10

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 65 of 145 Oct 31, 2025 Note 1. The listed currents are the total currents flowing into VDD, including the input leakage currents flowing when the level of the input pin is fixed to VDD, VSS, or EVSS. In the subsystem clock operation mode, the currents in the Typ. and Max. columns do not include the operating currents of the peripheral modules. Note 2. The listed currents apply when the HALT instruction has been fetched from the flash memory for execution. Note 3. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped. Note 4. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, high-speed system clock, and low-speed on-chip oscillator are stopped. Note 5. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, high-speed system clock, and low-speed on-chip oscillator are stopped, and the setting of RTCLPC is 1, and the low power consumption oscillation 3 is specified (AMPHS1, AMPHS0 = 11B). Note 6. The listed currents with this setting allow retention of the contents of the entire RAM area. The listed currents apply when the low-speed on-chip oscillator and subsystem clock oscillation are stopped. For the current for operation of the subsystem clock in the STOP mode, refer to that in the HALT mode. Note 7. The listed currents with this setting allow retention of the contents of a specified 4-Kbyte area of the RAM. The listed currents apply when the low-speed on-chip oscillator and subsystem clock oscillation are stopped. Note 8. The listed currents with this setting allow retention of the contents of a specified 4-Kbyte area of the RAM. The listed currents apply when the low-speed on-chip oscillator is stopped, the setting of RTCLPC is 1, and the low power consumption oscillation 3 is specified (AMPHS1, AMPHS0 = 11B). The current flowing into the RTC is included. Remark 1. fIL: Low-speed on-chip oscillator clock frequency Remark 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 66 of 145 Oct 31, 2025 2. 44- to 64-pin products with 64- to 128-Kbyte code flash memory Note 1. The listed currents are the total currents flowing into VDD, including the input leakage currents flowing when the level of the input pin is fixed to VDD or VSS. In the HS (high-speed main), LS (low-speed main), and LP (low-power main) modes, the currents in the Typ. column do not include the operating currents of the peripheral modules. The currents in the Max. column include the operating currents of the PCLBUZ, TAU, SAU, and IICA modules. The operating currents of other peripheral modules are not included. Note 2. The listed currents apply when the high-speed system clock, middle-speed on-chip oscillator, low-speed on-chip oscillator, and subsystem clock are stopped. Note 3. The listed currents apply when the high-speed on-chip oscillator, high-speed system clock, low-speed on-chip oscillator, and subsystem clock are stopped. Note 4. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, low-speed on-chip oscillator, and subsystem clock are stopped. (Remarks are listed on the next page.) Item Symbols Conditions Min. Typ. Max. Unit Supply current Note 1 IDD1 Operating mode HS (high-speed main) mode f IH = 32 MHzNote 2 Basic operation VDD = 5.0 V 1.4 — mA VDD = 1.8 V 1.4 — Normal operation VDD = 5.0 V 3.0 5.3 mA VDD = 1.8 V 3.0 5.3 LS (low-speed main) mode fIH = 24 MHzNote 2 Normal operation VDD = 5.0 V 2.3 4.0 mA VDD = 1.8 V 2.2 4.0 fIH = 16 MHzNote 2 Normal operation VDD = 5.0 V 1.7 2.9 mA VDD = 1.8 V 1.7 2.9 fIM = 4 MHzNote 3 Normal operation VDD = 5.0 V 0.4 0.8 mA VDD = 1.6 V 0.4 0.8 LP (low-power main) mode fIM = 2 MHzNote 3 Normal operation VDD = 5.0 V 198 342 µA VDD = 1.6 V 196 340 fIM = 1 MHzNote 3 Normal operation VDD = 5.0 V 110 185 µA VDD = 1.6 V 109 184 HS (high-speed main) mode fMX = 20 MHzNote 4, Square wave input Normal operation VDD = 5.0 V 1.9 3.3 mA VDD = 1.8 V 1.9 3.3 LS (low-speed main) mode f MX = 20 MHzNote 4, Square wave input Normal operation VDD = 5.0 V 1.7 3.1 mA VDD = 1.8 V 1.7 3.1 fMX = 20 MHzNote 4, Resonator connection Normal operation VDD = 5.0 V 2.0 3.4 mA VDD = 1.8 V 1.9 3.4 fMX = 10 MHzNote 4, Square wave input Normal operation VDD = 5.0 V 0.9 1.7 mA VDD = 1.8 V 0.9 1.6 fMX = 10 MHzNote 4, Resonator connection Normal operation VDD = 5.0 V 1.0 1.8 mA VDD = 1.8 V 1.0 1.8 fMX = 8 MHzNote 4, Square wave input Normal operation VDD = 5.0 V 0.8 1.4 mA VDD = 1.8 V 0.7 1.3 fMX = 8 MHzNote 4, Resonator connection Normal operation VDD = 5.0 V 0.9 1.5 mA VDD = 1.8 V 0.9 1.5 <R>

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 67 of 145 Oct 31, 2025 Remark 1. fIH: High-speed on-chip oscillator clock frequency Remark 2. fIM: Middle-speed on-chip oscillator clock frequency Remark 3. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 4. The typical value for the ambient operating temperature (TA) is +25°C unless otherwise specified.

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 68 of 145 Oct 31, 2025 2. 44- to 64-pin products with 64- to 128-Kbyte code flash memory Note 1. The listed currents are the total currents flowing into VDD, including the input leakage currents flowing when the level of the input pin is fixed to VDD or VSS. In the subsystem clock operation mode, the currents in the Typ. and Max. columns do not include the operating currents of the peripheral modules. Note 2. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped. Note 3. The listed currents apply when the high-speed on-chip oscillator, high-speed system clock, middle-speed on-chip oscillator, and low-speed on-chip oscillator are stopped, and the low power consumption oscillation 3 is specified (AMPHS1, AMPHS0 = 11B). Remark 1. fIL: Low-speed on-chip oscillator clock frequency Remark 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) Item Symbols Conditions Min. Typ. Max. Unit Supply current Note 1 IDD1 Operating mode Subsystem clock operation mode f SUB = 32.768 kHzNote 2, Low-speed on-chip oscillator operation Normal operation T A = -40°C 3.3 5.3 µA TA = +25°C 3.5 5.4 TA = +50°C 3.8 8.6 TA = +105°C 7.3 55.2 fSUB = 32.768 kHzNote 3, Square wave input Normal operation TA = -40°C 3.7 5.9 µA TA = +25°C 3.9 6.1 TA = +50°C 4.3 9.9 TA = +105°C 8.0 55.7 fSUB = 32.768 kHzNote 3, Resonator connection Normal operation TA = -40°C 3.3 5.6 µA TA = +25°C 3.5 5.8 TA = +50°C 3.8 8.9 TA = +105°C 7.2 55.5 <R>

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 69 of 145 Oct 31, 2025 2. 44- to 64-pin products with 64- to 128-Kbyte code flash memory Note 1. The listed currents are the total currents flowing into VDD, including the input leakage currents flowing when the level of the input pin is fixed to VDD or VSS. In the HS (high-speed main), LS (low-speed main), and LP (low-power main) modes, the currents in the Typ. column do not include the operating currents of the peripheral modules. The currents in the Max. column include the operating currents of the PCLBUZ, TAU, SAU, and IICA modules. The operating currents of other peripheral modules are not included. Note 2. The listed currents apply when the HALT instruction has been fetched from the flash memory for execution. Note 3. The listed currents apply when the high-speed system clock, middle-speed on-chip oscillator, low-speed on-chip oscillator, and subsystem clock are stopped. Note 4. The listed currents apply when the high-speed on-chip oscillator, high-speed system clock, low-speed on-chip oscillator, and subsystem clock are stopped. Note 5. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, low-speed on-chip oscillator, and subsystem clock are stopped. Remark 1. f IH: High-speed on-chip oscillator clock frequency Remark 2. fIM: Middle-speed on-chip oscillator clock frequency Remark 3. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 4. The typical value for the ambient operating temperature (TA) is +25°C unless otherwise specified. Item Symbols Conditions Min. Typ. Max. Unit Supply currentNote 1 IDD2 Note 2 HALT mode HS (high-speed main) mode fIH = 32 MHzNote 3 VDD = 5.0 V 0.57 2.19 mA VDD = 1.8 V 0.56 2.18 LS (low-speed main) mode fIH = 24 MHzNote 3 VDD = 5.0 V 0.48 1.70 mA VDD = 1.8 V 0.47 1.69 fIH = 16 MHzNote 3 VDD = 5.0 V 0.46 1.31 mA VDD = 1.8 V 0.45 1.30 fIM = 4 MHzNote 4 VDD = 5.0 V 0.09 0.30 mA VDD = 1.6 V 0.08 0.29 LP (low-power main) mode f IM = 2 MHzNote 4 VDD = 5.0 V 35 136 µA VDD = 1.6 V 34 135 fIM = 1 MHzNote 4 VDD = 5.0 V 29 83 µA VDD = 1.6 V 28 82 HS (high-speed main) mode f MX = 20 MHzNote 5, Square wave input VDD = 5.0 V 0.24 1.22 mA VDD = 1.8 V 0.21 1.18 LS (low-speed main) mode fMX = 20 MHzNote 5, Square wave input VDD = 5.0 V 0.24 1.22 mA VDD = 1.8 V 0.21 1.18 fMX = 20 MHzNote 5, Resonator connection VDD = 5.0 V 0.47 1.51 mA VDD = 1.8 V 0.45 1.49 fMX = 10 MHzNote 5, Square wave input VDD = 5.0 V 0.15 0.65 mA VDD = 1.8 V 0.12 0.62 fMX = 10 MHzNote 5, Resonator connection VDD = 5.0 V 0.27 0.80 mA VDD = 1.8 V 0.26 0.79 fMX = 8 MHzNote 5, Square wave input VDD = 5.0 V 0.13 0.53 mA VDD = 1.8 V 0.10 0.50 fMX = 8 MHzNote 5, Resonator connection VDD = 5.0 V 0.20 0.62 mA VDD = 1.8 V 0.19 0.61 <R>

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 70 of 145 Oct 31, 2025 2. 44- to 64-pin products with 64- to 128-Kbyte code flash memory (Notes and Remarks are listed on the next page.) Item Symbols Conditions Min. Typ. Max. Unit Supply current Note 1 IDD2 Note 2 HALT mode Subsystem clock operation mode fSUB = 32.768 kHzNote 3, Low-speed on-chip oscillator operation T A = -40°C 0.66 2.46 µA TA = +25°C 0.78 2.47 TA = +50°C 0.93 5.50 TA = +70°C 1.27 10.96 TA = +85°C 1.84 20.89 TA = +105°C 3.72 51.33 fSUB = 32.768 kHz, Square wave inputNote 4 TA = -40°C 0.32 2.25 µA TA = +25°C 0.44 2.33 TA = +50°C 0.66 5.92 TA = +70°C 1.12 12.10 TA = +85°C 1.56 21.02 TA = +105°C 3.18 50.58 fSUB = 32.768 kHz, Resonator connectionNote 5 TA = -40°C 0.33 2.35 µA TA = +25°C 0.46 2.50 TA = +50°C 0.60 5.53 TA = +70°C 0.94 10.88 TA = +85°C 1.47 20.36 TA = +105°C 3.28 51.29 IDD3 STOP mode RAMSDMD = 0, RAMSDS = 0Note 6 TA = -40°C 0.21 1.50 µA TA = +25°C 0.32 1.50 TA = +50°C 0.52 4.50 TA = +70°C 0.82 10.00 TA = +85°C 1.42 20.00 TA = +105°C 3.09 50.00 RAMSDMD = 1, RAMSDS = 1Note 7 TA = -40°C 0.21 1.50 µA TA = +25°C 0.31 1.50 TA = +50°C 0.49 4.00 TA = +70°C 0.78 9.00 TA = +85°C 1.26 18.00 TA = +105°C 2.87 45.00 RAMSDMD = 1, RAMSDS = 1, 128-Hz realtime clock operationNote 8 TA = -40°C 0.28 1.60 µA TA = +25°C 0.40 1.60 TA = +50°C 0.60 4.10 TA = +70°C 0.85 9.10 TA = +85°C 1.39 18.10 TA = +105°C 3.07 45.10 <R>

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 71 of 145 Oct 31, 2025 Note 1. The listed currents are the total currents flowing into VDD, including the input leakage currents flowing when the level of the input pin is fixed to VDD or VSS. In the subsystem clock operation mode, the currents in the Typ. and Max. columns do not include the operating currents of the peripheral modules. Note 2. The listed currents apply when the HALT instruction has been fetched from the flash memory for execution. Note 3. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped. Note 4. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, high-speed system clock, and low-speed on-chip oscillator are stopped. Note 5. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, high-speed system clock, and low-speed on-chip oscillator are stopped, and the setting of RTCLPC is 1, and the low power consumption oscillation 3 is specified (AMPHS1, AMPHS0 = 11B). Note 6. The listed currents with this setting allow retention of the contents of the entire RAM area. The listed currents apply when the low-speed on-chip oscillator and subsystem clock oscillation are stopped. For the current for operation of the subsystem clock in the STOP mode, refer to that in the HALT mode. Note 7. The listed currents with this setting allow retention of the contents of a specified 4-Kbyte area of the RAM. The listed currents apply when the low-speed on-chip oscillator and subsystem clock oscillation are stopped. Note 8. The listed currents with this setting allow retention of the contents of a specified 4-Kbyte area of the RAM. The listed currents apply when the low-speed on-chip oscillator is stopped, the setting of RTCLPC is 1, and the low power consumption oscillation 3 is specified (AMPHS1, AMPHS0 = 11B). The current flowing into the RTC is included. Remark 1. fIL: Low-speed on-chip oscillator clock frequency Remark 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 72 of 145 Oct 31, 2025 3. Peripheral functions (common to all products) (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) (1/3) Item Symbols Conditions Min. Typ. Max. Unit High-speed on-chip oscillator operating current IFIHNote 1 345 µA Middle-speed on-chip oscillator operating current IFIMNote 1 20 µA Low-speed on-chip oscillator operating current I FILNote 1 0.3 µA RTC operating current IRTC Notes 1, 2, 3 fRTCCLK = 32.768 kHz 0.005 µA fRTCCLK = 128 Hz 0.002 µA 32-bit interval timer operating current IIT Notes 1, 2, 4 0.04 µA 8-bit interval timers operating current I TMT Notes 1, 2, 5 fSUB = 32.768 kHz, fMAIN stopped 8-bit counter mode × 2 ch operation 0.08 µA 16-bit counter mode operation 0.06 µA Timer RJ operating current ITMRJNote 6 fSUB = 32.768 kHz, fMAIN stopped, per unit 0.14 µA 16-bit timers KB40, KB41, and KB42 operating current I TMKBNote 7 Standalone mode, timer output disabled, f HOCO = 64 MHz 44- to 64-pin products with 64- to 128-Kbyte code flash memory, one unit 235 µA 44- to 64-pin products with 256- to 512-Kbyte code flash memory and 80- to 100-pin products, three units 530 µA External signal sampler operating current IEXSDNote 8 fSUB = 32.768 kHz, fMAIN stopped 0.03 µA Watchdog timer operating current IWDT Notes 1, 2, 9 fIL = 32.768 kHz (typ.) 0.32 µA Oscillation stop detector operating current IOSDC Note 1 0.02 µA A/D converter operating current IADC Notes 1, 10 When conversion at maximum speed Normal mode, AVREFP = VDD = 5.0 V 0.95 1.6 mA Low voltage mode, AVREFP = VDD = 3.0 V 0.5 0.75 mA AVREFP current I ADREF Note 11 AVREFP = 5.0 V 52 µA A/D converter internal reference voltage current I ADREF Note 1 114 µA Temperature sensor operating current ITMPSNote 1 110 µA D/A converter operating current IDAC Notes 1, 12 Per channel 150 µA Comparator operating current ICMP Notes 1, 13 6µ A LVD operating current ILVD0 Notes 1, 14 0.02 µA ILVD1 Notes 1, 14 0.02 µA <R>

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 73 of 145 Oct 31, 2025 (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) (2/3) Item Symbols Conditions Min. Typ. Max. Unit Self-programming operating current IFSP Notes 1, 15 2.5 12.2 mA Data flash rewrite operating current IBGO Notes 1, 16 2.5 12.2 mA SNOOZE mode sequencer operating current ISMS Notes 1, 17 fIH =

32 MHz

44- to 64-pin products with 64- to 128-Kbyte code flash memory 1.1 mA 44- to 64-pin products with 256- to 512-Kbyte code flash memory and 80- to 100-pin products 1.5 mA fIL = 32.768 kHz 44- to 64-pin products with 64- to 128-Kbyte code flash memory 1.2 µA 44- to 64-pin products with 256- to 512-Kbyte code flash memory and 80- to 100-pin products 1.6 µA SNOOZE operating current ISNOZ Note 1 fIH = The ADC is shifting from the STOP mode to the SNOOZE mode.Note 18 0.6 0.81 mA The ADC is operating in the low-voltage mode. AVREFP = VDD = 3.0 V 1.2 1.56 mA Simplified SPI (CSI)/UART is in use 0.7 0.92 mA SMSNote 19 44- to 64-pin products with 64- to 128- Kbyte code flash memory 1.6 mA 44- to 64-pin products with 256- to 512- Kbyte code flash memory and 80- to 100- pin products 2.0 mA Low-speed peripheral clock supply current I SXP Notes 1, 20 RTCLPC = 0 0.22 µA Output current control operating current ICCDA Notes 1, 21 The setting of the CCDE register is not 00H. 100 µA ICCDP Notes 22, 23 Per single controlled current drive port pin Setting of the low-level output current: Hi-Z 30 µA Setting of the low-level output current: 2 to 15 mA 200 µA Operating current of the true random number generator I TRNG Note 1 1.1 mA <R> <R> <R>

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 74 of 145 Oct 31, 2025 Note 1. This current flows into VDD. Note 2. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, and high-speed system clock are stopped. Note 3. This current flows into the realtime clock (RTC). It does not include the operating current of the low-speed on-chip oscillator or the XT1 oscillator. The supply current of the RL78 microcontrollers is the sum of either IDD1 or IDD2, and IRTC, when the realtime clock is operating or in the HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be included in the supply current. IDD2 in the subsystem clock operation mode includes the operating current of the realtime clock. Note 4. This current only flows to the 32-bit interval timer. It does not include the operating current of the low-speed on-chip oscillator or the XT1 oscillator. The supply current of the RL78 microcontrollers is the sum of either IDD1 or IDD2, and IIT, when the 32- bit interval timer is operating or in the HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be included in the supply current. Note 5. This current only flows to the 8-bit interval timer. It does not include the operating current of the XT1 oscillator. The supply current of the RL78 microcontrollers is the sum of either IDD1 or IDD2 and ITMT when the 8-bit interval timer is operating or in the HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be included in the supply current. Note 6. This current only flows to the timer RJ. It does not include the operating current of the XT1 oscillator. The supply current of the RL78 microcontrollers is the sum of either IDD1 or IDD2 and ITMRJ when the timer RJ is operating or in the HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be included in the supply current. Note 7. This current only flows to the 16-bit timers KB40, KB41, and KB42. It does not include the operating current of the high- speed on-chip oscillator. The supply current of the RL78 microcontrollers is the sum of either IDD1 or IDD2 and ITMKB when the 16-bit timers KB40, KB41, and KB42 are operating or in the HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be included in the supply current. Note 8. This current only flows to the external signal sampler. It does not include the operating current of the low-speed on-chip oscillator, XT1 oscillator, or 8-bit interval timer. The supply current of the RL78 microcontrollers is the sum of either IDD1 or IDD2 and IEXSD when the external signal sampler is operating or in the HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be included in the supply current. Note 9. This current only flows to the watchdog timer. It includes the operating current of the low-speed on-chip oscillator. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer is operating. Note 10. This current only flows to the A/D converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and IADC when the A/D converter is operating or in the HALT mode. Note 11. This current flows into AVREFP. (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) (3/3) Item Symbols Conditions Min. Typ. Max. Unit LCD operating current ILCD1 Notes 1, 24, External resistance division method fLCD = fSUB LCD clock = 128 Hz 1/3 bias, four time slices VDD = 5.0 V VL4 = 5.00 V 0.02 µA ILCD2Note 1 Internal voltage boosting method fLCD = fSUB LCD clock = 128 Hz 1/3 bias, four time slices, V L1 reference VDD = 3.0 V VL4 = 3.03 V (VLCD4-0 = 04H) 0.74 µA VDD = 5.0 V VL4 = 5.01 V (VLCD4-0 = 18H) 1.03 µA fLCD = fSUB LCD clock = 128 Hz 1/3 bias, four time slices, VL2 referenceNote 26 VDD = 3.0 V VL4 = 3.03 V (VLCD4-0 = 04H) 0.63 µA VDD = 5.0 V VL4 = 5.03 V (VLCD4-0 = 18H) 0.83 µA ILCD3Note 1 Capacitor split method f LCD = fSUB LCD clock = 128 Hz 1/3 bias, four time slices, VDD reference VDD = 3.0 V VL4 = 3.00 V 0.14 µA fLCD = fSUB LCD clock = 128 Hz 1/3 bias, four time slices, VL4 reference VDD = 5.0 V VL4 = 3.04 V 0.63 µA

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 75 of 145 Oct 31, 2025 Note 12. This current only flows to the D/A converter. The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IDAC, when the D/A converter is operating or in the HALT mode. Note 13. This current only flows to the comparator. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and ICMP when the comparator is in operation. Note 14. This current only flows to the LVD circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and ILVD when the LVD circuit is in operation. Note 15. This current only flows during self-programming. Note 16. This current only flows while the data flash memory is being rewritten. Note 17. This current only flows into the SNOOZE mode sequencer. Note that the operating current of the low-speed on-chip oscillator and the XT1 oscillator are not included. The supply current of the RL78 microcontrollers is the sum of either IDD1 or IDD2, and ISMS, when the SNOOZE mode sequencer is operating or in the HALT mode. Note 18. For shift time to the SNOOZE mode, see 27.3.3 SNOOZE mode in the RL78/L23 User’s Manual. Note 19. The listed values apply when the SNOOZE mode sequencer is in normal operation equivalent to IDD1. They do not include the current flowing into the peripheral functions other than the SNOOZE mode sequencer. Note 20. This current is added to the supply current in the HALT mode when the setting of RTCLPC is 0 in the STOP mode, or when the setting of RTCLPC is 0 with the subsystem clock X (fSX) selected as the CPU clock, while the subsystem clock X (fsx) is oscillating. Note 21. This current is added to the supply current when the output voltage control port is set. Note 22. This current does not include the current flowing into the I/O port pins. Note 23. This current flows to VDD. Note 24. This current only flows to the LCD controller/driver. The supply current of the RL78 microcontrollers is the sum of the supply current (IDD1 or IDD2) and LCD operating current (ILCD1, ILCD2, or ILCD3) when the LCD controller/driver is operating while the MCU is operating or in the HALT mode. It does not include the current flowing into the LCD panel. The values in the Typ. and Max. columns apply under the following conditions.

Setting 20 pins as the segment function and blinking all
Selecting f SUB when LCD clock = 128 Hz (LCDC0 = 07H)
Setting four time slices and 1/3 bias Note 25. This current does not include the current flowing into the external division resistor when the external resistance division method is in use. boosting method. Remark 1. fIL: Low-speed on-chip oscillator clock frequency Remark 2. fSX: Subsystem clock X frequency Remark 3. fCLK: CPU/peripheral hardware clock frequency Remark 4. The typical value for the ambient operating temperature (TA) is +25°C unless otherwise specified.

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 76 of 145 Oct 31, 2025

2.4 AC Characteristics

(TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) (1/2) Item Symbols Conditions Min. Typ. Max. Unit Instruction cycle (minimum instruction execution time) T CY Main system clock (fMAIN) operation HS (high-speed main) mode

1.8 V ≤ V

DD ≤ 5.5 V 0.03125 1 µs 1.6 V ≤ VDD ≤ 1.8 V 0.25 1 µs LS (low-speed main) mode 1.8 V ≤ VDD ≤ 5.5 V 0.04167 1 µs 1.6 V ≤ VDD ≤ 1.8 V 0.25 1 µs LP (low-power main) mode DD ≤ 5.5 V 0.5 1 µs In the self programming mode HS (high-speed main) mode 1.8 V ≤ VDD ≤ 5.5 V 0.03125 1 µs 1.6 V ≤ VDD ≤ 1.8 V 0.5 1 µs LS (low-speed main) mode 1.8 V ≤ VDD ≤ 5.5 V 0.04167 1 µs 1.6 V ≤ VDD ≤ 1.8 V 0.5 1 µs External system clock frequency fEX 1.8 V ≤ VDD ≤ 5.5 V 1 20 MHz 1.6 V ≤ VDD < 1.8 V 1 4 MHz fEXS 32 38.4 kHz External system clock input high-level width, low-level width t EXH, tEXL 1.8 V ≤ VDD ≤ 5.5 V 24 ns 1.6 V ≤ VDD < 1.8 V 120 ns tEXHS, tEXLS 13.7 µs TI00 to TI07 input high-level width, low-level width tTIH, tTIL 1/fMCK +10 ns Timer RJ input cycle t C TRJIO0, TRJIO1 2.7 V ≤ VDD < 5.5 V 100 ns 1.8 V ≤ VDD < 2.7 V 300 ns 1.6 V ≤ VDD < 1.8 V 500 ns Timer RJ Input high-level width, low-level width t TJIH, tTJIL TRJIO0, TRJIO1 2.7 V ≤ VDD < 5.5 V 40 ns 1.8 V ≤ VDD < 2.7 V 120 ns 1.6 V ≤ VDD < 1.8 V 200 ns TO00 to TO07, TKBO00, TKBO01, TKBO10, TKBO11, TKBO20, TKBO21, TRJIO0, TRJIO1, TRJO0, and TRJO1 output frequency f TO HS (high-speed main) mode, LS (low-speed main) mode 4.0 V ≤ VDD ≤ 5.5 V 16 MHz 2.7 V ≤ VDD < 4.0 V 8 MHz 1.8 V ≤ VDD < 2.7 V 4 MHz 1.6 V ≤ VDD < 1.8 V 2 MHz LP (low-power main) mode 1.6 V ≤ VDD ≤ 5.5 V 2 MHz PCLBUZ0, PCLBUZ1 output frequency fPCL HS (high-speed main) mode, LS (low-speed main) mode 4.0 V ≤ VDD ≤ 5.5 V 16 MHz 2.7 V ≤ VDD < 4.0 V 8 MHz 1.8 V ≤ VDD < 2.7 V 4 MHz 1.6 V ≤ VDD < 1.8 V 2 MHz LP (low-power main) mode 1.6 V ≤ VDD < 5.5 V 2 MHz

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 77 of 145 Oct 31, 2025 Remark fMCK: Timer array unit operating clock frequency To set this operating clock, use the CKSmn0 and CKSmn1 bits of the timer mode register mn (TMRmn) (m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7). (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) (2/2) Item Symbols Conditions Min. Typ. Max. Unit Interrupt input high-level width, low-level width t INTH, tINTL INTP0 to INTP7 1.6 V ≤ VDD ≤ 5.5 V 1 µs Key-input high-level width, low-level width tKRH, tKRL KR0 to KR7 1.8 V ≤ VDD ≤ 5.5 V 250 ns 1.6 V ≤ VDD < 1.8 V 1 µs RESET low-level width t RSL 10 µs

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 78 of 145 Oct 31, 2025 Minimum Instruction Execution Time during Main System Clock Operation TCY vs VDD (HS (high-speed main) mode) TCY vs VDD (LS (low-speed main) mode) In normal operation During self-programming Supply voltage VDD [V] 1.0 0.1 1.8 0.01 1.6 0.03125 0.25 0.05 Cycle time TCY [µs] 5.5 0.5 In normal operation During self-programming Supply voltage VDD [V] 1.0 0.1 1.8 0.01 1.6 0.04167 0.25 0.05 Cycle time TCY [µs] 5.5 0.5

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 79 of 145 Oct 31, 2025 TCY vs VDD (LP (low-power main) mode) In normal operation Supply voltage VDD [V] 1.0 0.1 0.01 1.6 0.05 Cycle time TCY [µs] 5.5 0.5

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 80 of 145 Oct 31, 2025 AC Timing Test Points External System Clock Timing TI/TO Timing VIH/VOH VIL/VOL VIH/VOHTest points VIL/VOL EXCLK/EXCLKS 1/fEX/ 1/fEXS tEXL/ tEXLS tEXH/ tEXHS tTIL tTIH 1/fTO TI00 to TI07 TO00 to TO07 TKBO00, TKBO01, TKBO10, TKBO11, TKBO20, TKBO21, TRJIO0, TRJIO1, TRJO0, TRJO1

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 81 of 145 Oct 31, 2025 Timer RJ Input Timing Interrupt Request Input Timing Key Interrupt Input Timing RESET Input Timing tTJIL tTJIH TRJIO0, TRJIO1 INTP0 to INTP7 tINTL tINTH KR0 to KR7 tKRL tKRH tRSL RESET

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 82 of 145 Oct 31, 2025

2.5 Characteristics of the Peripheral Functions

2.5.1 Serial array unit

In UART communications with devices operating at same voltage levels Note 1. The transfer rate in the SNOOZE mode is within the range from 4800 to 9600 bps. Note 2. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are as follows. Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register (PIMg) and port output mode register (POMg). (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) Item Symbols Conditions HS (high-speed main) mode LS (low-speed main) mode LP (low-power main) mode Unit Transfer rate Note 1 1.6 V ≤ VDD ≤ 5.5 V f MCK/6 f MCK/6 f MCK/6 bps Theoretical value of the maximum transfer rate fMCK = fCLKNote 2 5.3 4 0.33 Mbps HS (high-speed main) mode : 32 MHz (1.8 V ≤ VDD ≤ 5.5 V) 4 MHz (1.6 V ≤ VDD ≤ 5.5 V) LS (low-speed main) mode : 24 MHz (1.8 V ≤ VDD ≤ 5.5 V) 4 MHz (1.6 V ≤ VDD ≤ 5.5 V) LP (low-power main) mode : 2 MHz (1.6 V ≤ VDD ≤ 5.5 V) VIH/VOH VIL/VOL VIH/VOHTest points VIL/VOL

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 83 of 145 Oct 31, 2025 Connection in the UART communications with devices operating at same voltage levels Bit width in the UART communications when interfacing devices operate at the same voltage level (reference) Remark 1. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0 to 9, 12 to 14) Remark 2. fMCK: Serial array unit operation clock frequency To set this operating clock, set the CKSmn bit in the serial mode register mn (SMRmn) (m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13). TxDq RxDq User device Rx Tx RL78 microcontroller Baud rate error tolerance TxDq RxDq High-/low-bit width 1/Transfer rate

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 84 of 145 Oct 31, 2025 2. In simplified SPI (CSI) communications in the master mode with devices operating at same voltage levels with the internal SCKp clock (the ratings below are only applicable to CSI00) Note 1. This is for when the settings are DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. When the settings are DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0, this is the setup time to or from the falling of SCKp. Note 2. This is for when the settings are DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. When the settings are DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0, this is the delay time to the rising of SCKp. Note 3. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using the port input mode register (PIMg) and the port output mode register (POMg). Remark 1. The listed times are only valid when the peripheral I/O redirect function of CSI00 is not in use. Remark 2. p: CSI number (p = 00), g: PIM and POM number (g = 1), m: Unit number (m = 0), n: Channel number (n = 0) Remark 3. fMCK: Serial array unit operation clock frequency To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn) (m: Unit number, n: Channel number (mn = 00). (TA = -40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) Item Symbols Conditions HS (high-speed main) mode LS (low-speed main) mode LP (low-power main) mode Unit SCKp cycle time t KCY1 tKCY1 ≥ 2/fCLK 4.0 V ≤ VDD ≤ 5.5 V 62.5 83.3 1000 ns 2.7 V ≤ VDD ≤ 5.5 V 83.3 125 1000 ns SCKp high-level width, low-level width tKH1, tKL1 4.0 V ≤ VDD ≤ 5.5 V t KCY1/2 tKCY1/2 -10 tKCY1/2 -50 ns 2.7 V ≤ VDD ≤ 5.5 V t KCY1/2 -10 tKCY1/2 -15 tKCY1/2 -50 ns SIp setup time to the rising of SCKp Note 1 tSIK1 4.0 V ≤ VDD ≤ 5.5 V 23 33 110 ns 2.7 V ≤ VDD ≤ 5.5 V 33 50 110 ns SIp hold time from the rising of SCKp Note 1 tKSI1 2.7 V ≤ VDD ≤ 5.5 V 10 10 10 ns Delay time from the falling of SCKp to an SOp output Note 2 tKSO1 2.7 V ≤ VDD ≤ 5.5 V, C = 20 pFNote 3 10 10 10 ns

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 85 of 145 Oct 31, 2025 3. In simplified SPI (CSI) communications in the master mode with devices operating at same voltage levels with the internal SCKp clock Note 1. This is for when the settings are DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. When the settings are DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0, this is the setup time to or from the falling of SCKp. Note 2. This is for when the settings are DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. When the settings are DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0, this is the delay time to the rising of SCKp. Note 3. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using the port input mode register (PIMg) and the port output mode register (POMg). Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), g: PIM and POM number (g = 0 to 9, 12 to 14), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3) Remark 2. fMCK: Serial array unit operation clock frequency To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn) (m: Unit number, n: Channel number = 00 to 03, 10 to 13). (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) Item Symbols Conditions HS (high-speed main) mode LS (low-speed main) mode LP (low-power main) mode Unit SCKp cycle time t KCY1 tKCY1 ≥ 4/fCLK 2.7 V ≤ VDD ≤ 5.5 V 125 166 2000 ns 2.4 V ≤ VDD ≤ 5.5 V 250 250 2000 ns 1.8 V ≤ VDD ≤ 5.5 V 500 500 2000 ns 1.6 V ≤ VDD ≤ 5.5 V 1000 1000 2000 ns SCKp high-level width, low-level width tKH1, tKL1 4.0 V ≤ VDD ≤ 5.5 V t KCY1/2 -12 tKCY1/2 -21 tKCY1/2 -50 ns 2.7 V ≤ VDD ≤ 5.5 V t KCY1/2 -18 tKCY1/2 -25 tKCY1/2 -50 ns 2.4 V ≤ VDD ≤ 5.5 V t KCY1/2 -38 tKCY1/2 -38 tKCY1/2 -50 ns 1.8 V ≤ VDD ≤ 5.5 V t KCY1/2 -50 tKCY1/2 -50 tKCY1/2 -50 ns 1.6 V ≤ VDD ≤ 5.5 V t KCY1/2 -100 tKCY1/2 -100 tKCY1/2 -100 ns SIp setup time to the rising of SCKp Note 1 tSIK1 4.0 V ≤ VDD ≤ 5.5 V 44 54 110 ns 2.7 V ≤ VDD ≤ 5.5 V 44 54 110 ns 2.4 V ≤ VDD ≤ 5.5 V 75 75 110 ns 1.8 V ≤ VDD ≤ 5.5 V 110 110 110 ns 1.6 V ≤ VDD ≤ 5.5 V 220 220 220 ns SIp hold time from the rising of SCKp Note 1 tKSI1 1.6 V ≤ VDD ≤ 5.5 V 19 19 19 ns Delay time from the falling of SCKp to an SOp output Note 2 tKSO1 1.6 V ≤ VDD ≤ 5.5 V, C = 30 pFNote 3 25 25 25 ns

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 86 of 145 Oct 31, 2025 4. In simplified SPI (CSI) communications in the slave mode with devices operating at same voltage levels with the SCKp external clock (Notes, Caution, and Remarks are listed on the next page.) (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) (1/2) Item Symbols Conditions HS (high-speed main) mode LS (low-speed main) mode LP (low-power main) mode Unit SCKp cycle time Note 1 tKCY2 4.0 V ≤ VDD ≤ 5.5 V 20 MHz < f MCK 8/fMCK 8/fMCK —n s fMCK ≤ 20 MHz 6/f MCK 6/fMCK 6/fMCK ns 2.7 V ≤ VDD ≤ 5.5 V 16 MHz < f MCK 8/fMCK 8/fMCK —n s fMCK ≤ 16 MHz 6/f MCK 6/fMCK 6/fMCK ns 2.4 V ≤ VDD ≤ 5.5 V 6/f MCK and 500 6/fMCK and 500 6/fMCK and 500 ns 1.8 V ≤ VDD ≤ 5.5 V 6/f MCK and 750 6/fMCK and 750 6/fMCK and 750 ns 1.6 V ≤ VDD ≤ 5.5 V 6/f MCK and 1500 6/fMCK and 1500 6/fMCK and 1500 ns SCKp high-level width, low-level width tKH2, tKL2 4.0 V ≤ VDD ≤ 5.5 V t KCY2/2 tKCY2/2 tKCY2/2 ns 2.7 V ≤ VDD ≤ 5.5 V t KCY2/2 tKCY2/2 tKCY2/2 ns 1.8 V ≤ VDD ≤ 5.5 V t KCY2/2 -18 tKCY2/2 -18 tKCY2/2 -18 ns 1.6 V ≤ VDD ≤ 5.5 V t KCY2/2 -66 tKCY2/2 -66 tKCY2/2 -66 ns

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 87 of 145 Oct 31, 2025 4. In simplified SPI (CSI) communications in the slave mode with devices operating at same voltage levels with the SCKp external clock Note 1. Transfer rate in the SNOOZE mode is 1 Mbps at the maximum. Note 2. This is for when the settings are DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. When the settings are DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0, this is the setup time to or from the falling of SCKp. Note 3. This is for when the settings are DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. When the settings are DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0, this is the delay time to the rising of SCKp. Note 4. C is the load capacitance of the SOp output line. Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using the port input mode register (PIMg) and the port output mode register (POMg). Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), g: PIM and POM number (g = 0 to 9, 12 to 14), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3) Remark 2. fMCK: Serial array unit operation clock frequency To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn) (m: Unit number, n: Channel number = 00 to 03, 10 to 13). (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) (2/2) Item Symbols Conditions HS (high-speed main) mode LS (low-speed main) mode LP (low-power main) mode Unit SIp setup time to the rising of SCKpNote 2 tSIK2 2.7 V ≤ VDD ≤ 5.5 V 1/f MCK +20 1/fMCK +30 1/fMCK +30 ns 1.8 V ≤ VDD ≤ 5.5 V 1/f MCK +30 1/fMCK +30 1/fMCK +30 ns 1.6 V ≤ VDD ≤ 5.5 V 1/f MCK +40 1/fMCK +40 1/fMCK +40 ns SIp hold time from the rising of SCKp Note 2 tKSI2 1.8 V ≤ VDD ≤ 5.5 V 1/f MCK +31 1/fMCK +31 1/fMCK +31 ns 1.6 V ≤ VDD ≤ 5.5 V 1/f MCK +250 1/fMCK +250 1/fMCK +250 ns Delay time from the falling of SCKp to an SOp outputNote 3 tKSO2 C = 30 pF Note 4 2.7 V ≤ VDD ≤ 5.5 V 2/f MCK +44 2/fMCK +110 2/fMCK +110 ns 2.4 V ≤ VDD ≤ 5.5 V 2/f MCK +75 2/fMCK +110 2/fMCK +110 ns 1.8 V ≤ VDD ≤ 5.5 V 2/f MCK +110 2/fMCK +110 2/fMCK +110 ns 1.6 V ≤ VDD ≤ 5.5 V 2/f MCK +220 2/fMCK +220 2/fMCK +220 ns

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 88 of 145 Oct 31, 2025 Connection in the simplified SPI (CSI) communications with devices operating at same voltage levels Timing of serial transfer in the simplified SPI (CSI) communications with devices operating at same voltage levels when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1 SCKp SOp SCK SI SIp SORL78 microcontroller User device Input dataSIp SOp tKCY1, 2 tKL1, 2 tKH1, 2 tSIK1, 2 tKSI1, 2 tKSO1, 2 Output data SCKp

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 89 of 145 Oct 31, 2025 Timing of serial transfer in the simplified SPI (CSI) communications with devices operating at same voltage levels when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0 Remark p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13) Input dataSIp SOp tKCY1, 2 tKH1, 2 tKL1, 2 tSIK1, 2 tKSI1, 2 tKSO1, 2 Output data SCKp

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 90 of 145 Oct 31, 2025 5. In simplified I 2C communications with devices operating at same voltage levels (Notes and Caution are listed on the next page, and Remarks are listed on page 92.) (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) (1/2) Item Symbols Conditions HS (high-speed main) mode LS (low-speed main) mode LP (low-power main) mode Unit SCLr clock frequency f SCL 2.7 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 1000 Note 1 1000 Note 1 400Note 1 kHz 1.8 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 400Note 1 400Note 1 400Note 1 kHz 1.8 V ≤ VDD < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 300Note 1 300Note 1 300Note 1 kHz 1.6 V ≤ VDD < 1.8 V, Cb = 100 pF, Rb = 5 kΩ 250Note 1 250Note 1 250Note 1 kHz Hold time when SCLr is low tLOW 2.7 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 475 475 1150 ns 1.8 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 1150 1150 1150 ns 1.8 V ≤ VDD < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 1550 1550 1550 ns 1.6 V ≤ VDD < 1.8 V, Cb = 100 pF, Rb = 5 kΩ 1850 1850 1850 ns Hold time when SCLr is high tHIGH 2.7 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 475 475 1150 ns 1.8 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 1150 1150 1150 ns 1.8 V ≤ VDD < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 1550 1550 1550 ns 1.6 V ≤ VDD < 1.8 V, Cb = 100 pF, Rb = 5 kΩ 1850 1850 1850 ns

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 91 of 145 Oct 31, 2025 5. In simplified I 2C communications with devices operating at same voltage levels Note 1. The listed times must be no greater than fMCK/4. Note 2. Set fMCK so that it will not exceed the hold time when SCLr is low or high. Caution Select the normal input buffer and N-ch open-drain output (withstand voltage of V DD) mode for the SDAr pin, and normal output mode for the SCLr pin by using the port input mode register (PIMg) and port output mode register (POMh). (Remarks are listed on the next page.) (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) (2/2) Item Symbols Conditions HS (high-speed main) mode LS (low-speed main) mode LP (low-power main) mode Unit Data setup time (reception) tSU:DAT 2.7 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 1/fMCK +85 Note 2 1/fMCK +85 Note 2 1/fMCK +145 Note 2 ns 1.8 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 1/fMCK +145 Note 2 1/fMCK +145 Note 2 1/fMCK +145 Note 2 ns 1.8 V ≤ VDD < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 1/fMCK +230 Note 2 1/fMCK +230 Note 2 1/fMCK +230 Note 2 ns 1.6 V ≤ VDD < 1.8 V, Cb = 100 pF, Rb = 5 kΩ 1/fMCK +290 Note 2 1/fMCK +290 Note 2 1/fMCK +290 Note 2 ns Data hold time (transmission) tHD:DAT 2.7 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 0 305 0 305 0 305 ns 1.8 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 0 355 0 355 0 355 ns 1.8 V ≤ VDD < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 0 405 0 405 0 405 ns 1.6 V ≤ VDD < 1.8 V, Cb = 100 pF, Rb = 5 kΩ 0 405 0 405 0 405 ns

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 92 of 145 Oct 31, 2025 Connection in the simplified I2C communications with devices operating at same voltage levels Timing of serial transfer in the simplified I2C communications with devices operating at same voltage levels Remark 1. Rb[Ω]: Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance Remark 2. r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31), g: PIM number (g = 0 to 9, 12, 14), h: POM number (h = 0 to 9, 12 to 14) Remark 3. fMCK: Operation clock frequency of the serial array unit To set this operating clock, use the CKSmn bit in the SMRmn register (m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13). RL78 microcontroller SDAr SCLr SDA SCL VDD Rb User device SDAr SCLr 1/fSCL tLOW tHIGH tSU:DATtHD:DAT

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 93 of 145 Oct 31, 2025 6. In UART communications with devices operating at different voltage levels (1.8 V, 2.5 V, 3 V) Note 1. Transfer rate in the SNOOZE mode is within the range from 4800 to 9600 bps. Note 2. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: Note 3. Use this rate with EVDD0 ≥ Vb. Caution Select the TTL input buffer for the RxDq pin, and the N-ch open-drain output (withstand voltage of V DD) mode for the TxDq pin by using the port input mode register (PIMg) and port output mode register (POMg). For VIH and VIL, see the DC characteristics with the TTL input buffer selected. Remark 1. Vb[V]: Communication line voltage Remark 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0 to 9, 12 to 14) Remark 3. fMCK: Serial array unit operation clock frequency To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn) (m: Unit number, n: Channel number = 00 to 03, 10 to 13). (TA = -40 to +105°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) (1/2) Item Symbols Conditions HS (high-speed main) mode LS (low-speed main) mode LP (low-power main) mode Unit Transfer rate Reception 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V fMCK/6 Note 1 fMCK/6 Note 1 fMCK/6 Note 1 bps Theoretical value of the maximum transfer rate fMCK = fCLKNote 2 5.3 4 0.33 Mbps 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V fMCK/6 Note 1 fMCK/6 Note 1 fMCK/6 Note 1 bps Theoretical value of the maximum transfer rate fMCK = fCLKNote 2 5.3 4 0.33 Mbps 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V fMCK/6 Notes 1, 3 fMCK/6 Notes 1, 3 fMCK/6 Notes 1, 3 bps Theoretical value of the maximum transfer rate fMCK = fCLKNote 2 5.3 4 0.33 Mbps HS (high-speed main) mode : 32 MHz (1.8 V ≤ VDD ≤ 5.5 V) 4 MHz (1.6 V ≤ VDD ≤ 5.5 V) LS (low-speed main) mode : 24 MHz (1.8 V ≤ VDD ≤ 5.5 V) 4 MHz (1.6 V ≤ VDD ≤ 5.5 V) LP (low-power main) mode : 2 MHz (1.6 V ≤ VDD ≤ 5.5 V)

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 94 of 145 Oct 31, 2025 6. In UART communications with devices operating at different voltage levels (1.8 V, 2.5 V, 3 V) Note 1. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 4.0 V ≤ VDD ≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V Note 2. This rate is calculated as an example when the conditions described in the Conditions column are met. See Note 1 above to calculate the maximum transfer rate under conditions of the customer. (Notes and Caution continue in the next page.) (TA = -40 to +105°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) (2/2) Item Symbols Conditions HS (high-speed main) mode LS (low-speed main) mode LP (low-power main) mode Unit Transfer rate Transmission 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V Note 1 Note 1 Note 1 bps Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 1.4 kΩ, Vb = 2.7 V 2.8Note 2 2.8Note 2 2.8Note 2 Mbps 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V Note 3 Note 3 Note 3 bps Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 2.7 kΩ, Vb = 2.3 V 1.2Note 4 1.2Note 4 1.2Note 4 Mbps 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Notes 5, 6 Notes 5, 6 Notes 5, 6 bps Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 5.5 kΩ, Vb = 1.6 V 0.43 Note 7 0.43 Note 7 0.43 Note 7 Mbps Maximum transfer rate = [bps] Baud rate error (theoretical value) = Transfer rate × 2 Vb Vb ( ) × Number of transferred bits1 Transfer rate × 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides.

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 95 of 145 Oct 31, 2025 Note 3. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V ≤ VDD < 4.0 V and 2.3 V ≤ Vb ≤ 2.7 V Note 4. This rate is calculated as an example when the conditions described in the Conditions column are met. See Note 3 above to calculate the maximum transfer rate under conditions of the customer. Note 5. Use this rate with VDD ≥ Vb. Note 6. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 1.8 V ≤ VDD < 3.3 V and 1.6 V ≤ Vb ≤ 2.0 V Note 7. This rate is calculated as an example when the conditions described in the Conditions column are met. See Note 6 above to calculate the maximum transfer rate under conditions of the customer. Caution Select the TTL input buffer for the RxDq pin, and the N-ch open-drain output (withstand voltage of V DD) mode for the TxDq pin by using the port input mode register (PIMg) and port output mode register (POMg). For VIH and VIL, see the DC characteristics with the TTL input buffer selected. Maximum transfer rate = [bps] Baud rate error (theoretical value) = Transfer rate × 2 ( ) × Number of transferred bits1 Transfer rate × 100 [%] Vb Vb * This value is the theoretical value of the relative difference between the transmission and reception sides. Maximum transfer rate = [bps] Baud rate error (theoretical value) = Transfer rate × 2 ( ) × Number of transferred bits1 Transfer rate × 100 [%] Vb Vb * This value is the theoretical value of the relative difference between the transmission and reception sides.

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 96 of 145 Oct 31, 2025 In UART communications with devices operating at different voltage levels Bit width in the UART communications with devices operating at different voltage levels (reference) Remark 1. Rb[Ω]: Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage Remark 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0 to 9, 12 to 14) Remark 3. fMCK: Serial array unit operation clock frequency To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn) (m: Unit number, n: Channel number = 00 to 03, 10 to 13). RL78 microcontroller TxDq RxDq Rx Tx Vb Rb User device Baud rate error tolerance High-/Low-bit width 1/Transfer rate Baud rate error tolerance High-bit width Low-bit width 1/Transfer rate TxDq RxDq

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 97 of 145 Oct 31, 2025 7. In simplified SPI (CSI) communications in the master mode with devices operating at different voltage levels (2.5 V or 3 V) with the internal SCKp clock (the ratings below are only applicable to CSI00) (Notes, Caution, and Remarks are listed on the next page.) (TA = -40 to +105°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) (1/2) Item Symbols Conditions HS (high-speed main) mode LS (low-speed main) mode LP (low-power main) mode Unit SCKp cycle time t KCY1 tKCY1 ≥ 2/fCLK 4.0 V ≤ VDD ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ 200 200 2300 ns 2.7 V ≤ VDD < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ 300 300 2300 ns SCKp high-level width tKH1 4.0 V ≤ VDD ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ tKCY1/2 -50 tKCY1/2 -50 tKCY1/2 -50 ns 2.7 V ≤ VDD < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ tKCY1/2 -120 tKCY1/2 -120 tKCY1/2 -120 ns SCKp low-level width tKL1 4.0 V ≤ VDD ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ tKCY1/2 tKCY1/2 tKCY1/2 -50 ns 2.7 V ≤ VDD < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ tKCY1/2 -10 tKCY1/2 -10 tKCY1/2 -50 ns SIp setup time to the rising of SCKp Note 1 tSIK1 4.0 V ≤ VDD ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ 58 58 479 ns 2.7 V ≤ VDD < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ 121 121 479 ns SIp hold time from the rising of SCKp Note 1 tKSI1 4.0 V ≤ VDD ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ 10 10 10 ns 2.7 V ≤ VDD < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ 10 10 10 ns Delay time from the falling of SCKp to an SOp output Note 1 tKSO1 4.0 V ≤ VDD ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ 60 60 60 ns 2.7 V ≤ VDD < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ 130 130 130 ns

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 98 of 145 Oct 31, 2025 7. In simplified SPI (CSI) communications in the master mode with devices operating at different voltage levels (2.5 V or 3 V) with the internal SCKp clock (the ratings below are only applicable to CSI00) Note 1. This setting applies when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. Note 2. This setting applies when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin, and the N-ch open-drain output (withstand voltage of V DD) mode for the SOp and SCKp pins by using the port input mode register (PIMg) and port output mode register (POMg). For VIH and VIL, see the DC characteristics with the TTL input buffer selected. Remark 1. Rb[Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage Remark 2. p: CSI number (p = 00), g: PIM and POM number (g = 1), m: Unit number (m = 0), n: Channel number (n = 0) Remark 3. fMCK: Serial array unit operation clock frequency To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn) (m: Unit number, n: Channel number = 00). Remark 4. The listed times are only valid when the peripheral I/O redirect function of CSI00 is not in use. (TA = -40 to +105°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) (2/2) Item Symbols Conditions HS (high-speed main) mode LS (low-speed main) mode LP (low-power main) mode Unit SIp setup time to the falling of SCKpNote 2 tSIK1 4.0 V ≤ VDD ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ 23 23 110 ns 2.7 V ≤ VDD < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ 33 33 110 ns SIp hold time from the falling of SCKpNote 2 tKSI1 4.0 V ≤ VDD ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ 10 10 10 ns 2.7 V ≤ VDD < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ 10 10 10 ns Delay time from the rising of SCKp to an SOp outputNote 2 tKSO1 4.0 V ≤ VDD ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ 10 10 10 ns 2.7 V ≤ VDD < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ 10 10 10 ns

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 99 of 145 Oct 31, 2025 8. In simplified SPI (CSI) communications in the master mode with devices operating at different voltage levels (1.8 V,

2.5 V, or 3 V) with the internal SCKp clock

Note Use this rate with VDD ≥ Vb. Caution Select the TTL input buffer for the SIp pin, and the N-ch open-drain output (withstand voltage of V DD) mode for the SOp and SCKp pins by using the port input mode register (PIMg) and port output mode register (POMg). For VIH and VIL, see the DC characteristics with the TTL input buffer selected. (Remarks are listed on page 102.) (TA = -40 to +105°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) (1/3) Item Symbols Conditions HS (high-speed main) mode LS (low-speed main) mode LP (low-power main) mode Unit SCKp cycle time t KCY1 tKCY1 ≥ 4/fCLK 4.0 V ≤ VDD ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ 300 300 2300 ns 2.7 V ≤ VDD < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ 500 500 2300 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote, Cb = 30 pF, Rb = 5.5 kΩ 1150 1150 2300 ns SCKp high-level width t KH1 4.0 V ≤ VDD ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ tKCY1/2 -75 tKCY1/2 -75 tKCY1/2 -75 ns 2.7 V ≤ VDD < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ tKCY1/2 -170 tKCY1/2 -170 tKCY1/2 -170 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote, Cb = 30 pF, Rb = 5.5 kΩ tKCY1/2 -458 tKCY1/2 -458 tKCY1/2 -458 ns SCKp low-level width t KL1 4.0 V ≤ VDD ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ tKCY1/2 -12 tKCY1/2 -12 tKCY1/2 -50 ns 2.7 V ≤ VDD < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ tKCY1/2 -18 tKCY1/2 -18 tKCY1/2 -50 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote, Cb = 30 pF, Rb = 5.5 kΩ tKCY1/2 -50 tKCY1/2 -50 tKCY1/2 -50 ns

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 100 of 145 Oct 31, 2025 8. In simplified SPI (CSI) communications in the master mode with devices operating at different voltage levels (1.8 V, Note 1. This setting applies when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. Note 2. Use this value with VDD ≥ Vb. Caution Select the TTL input buffer for the SIp pin, and the N-ch open-drain output (withstand voltage of V DD) mode for the SOp and SCKp pins by using the port input mode register (PIMg) and port output mode register (POMg). For VIH and VIL, see the DC characteristics with the TTL input buffer selected. (Remarks are listed on page 102.) (TA = -40 to +105°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) (2/3) Item Symbols Conditions HS (high-speed main) mode LS (low-speed main) mode LP (low-power main) mode Unit SIp setup time to the rising of SCKpNote 1 tSIK1 4.0 V ≤ VDD ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ 81 81 479 ns 2.7 V ≤ VDD < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ 177 177 479 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 30 pF, Rb = 5.5 kΩ 479 479 479 ns SIp hold time from the rising of SCKpNote 1 tKSI1 4.0 V ≤ VDD ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ 19 19 19 ns 2.7 V ≤ VDD < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ 19 19 19 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 30 pF, Rb = 5.5 kΩ 19 19 19 ns Delay time from the falling of SCKp to an SOp outputNote 1 tKSO1 4.0 V ≤ VDD ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ 100 100 100 ns 2.7 V ≤ VDD < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ 195 195 195 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 30 pF, Rb = 5.5 kΩ 483 483 483 ns

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 101 of 145 Oct 31, 2025 8. In simplified SPI (CSI) communications in the master mode with devices operating at different voltage levels (1.8 V, Note 1. This setting applies when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 2. Use this value with VDD ≥ Vb. Caution Select the TTL input buffer for the SIp pin, and the N-ch open-drain output (withstand voltage of V DD) mode for the SOp and SCKp pins by using the port input mode register (PIMg) and port output mode register (POMg). For VIH and VIL, see the DC characteristics with the TTL input buffer selected. (Remarks are listed on the next page.) (TA = -40 to +105°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) (3/3) Item Symbols Conditions HS (high-speed main) mode LS (low-speed main) mode LP (low-power main) mode Unit SIp setup time to the falling of SCKpNote 1 tSIK1 4.0 V ≤ VDD ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ 44 44 110 ns 2.7 V ≤ VDD < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ 44 44 110 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 30 pF, Rb = 5.5 kΩ 110 110 110 ns SIp hold time from the falling of SCKpNote 1 tKSI1 4.0 V ≤ VDD ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ 19 19 19 ns 2.7 V ≤ VDD < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ 19 19 19 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 30 pF, Rb = 5.5 kΩ 19 19 19 ns Delay time from the rising of SCKp to an SOp outputNote 1 tKSO1 4.0 V ≤ VDD ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ 25 25 25 ns 2.7 V ≤ VDD < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ 25 25 25 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 30 pF, Rb = 5.5 kΩ 25 25 25 ns

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 102 of 145 Oct 31, 2025 Connection in the simplified SPI (CSI) communications with devices operating at different voltage levels Remark 1. Rb[Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage Remark 2. p: CSI number (p = 00, 01, 10, 20, 30, 31), g: PIM and POM number (g = 0 to 9, 12 to 14), m: Unit number, n: Channel number (mn = 00 to 02, 10, 12, 13) Remark 3. fMCK: Serial array unit operation clock frequency To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn) (m: Unit number, n: Channel number = 00). Timing of serial transfer in the simplified SPI (CSI) communications in the master mode with devices operating at different voltage levels when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1 SCKp SOp SCK SI SIp SO Vb Rb <Master> Vb Rb RL78 microcontroller User device Input dataSIp SOp tKCY1 tKL1 tKH1 tSIK1 tKSI1 tKSO1 Output data SCKp

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 103 of 145 Oct 31, 2025 Timing of serial transfer in the simplified SPI (CSI) communications in the master mode with devices operating at different voltage levels when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0 Remark p: CSI number (p = 00, 01, 10, 20, 30, 31), g: PIM and POM number (g = 0 to 9, 12 to 14), m: Unit number, n: Channel number (mn = 00 to 02, 10, 12, 13) Input data Output data SIp SOp SCKp tKCY1 tKH1 tKL1 tSIK1 tKSI1 tKSO1

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 104 of 145 Oct 31, 2025 9. In simplified SPI (CSI) communications in the slave mode wit h devices operating at different voltage levels (1.8 V,

2.5 V, or 3 V) with the external SCKp clock

(Notes and Caution are listed on the next page, and Remarks are listed on page 106.) (TA = -40 to +105°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) (1/2) Item Symbols Conditions HS (high-speed main) mode LS (low-speed main) mode LP (low-power main) mode Unit SCKp cycle timeNote 1 tKCY2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V

24 MHz < fMCK 14/fMCK —— n s

20 MHz < fMCK ≤ 24 MHz 12/f MCK 12/fMCK —n s

8 MHz < fMCK ≤ 20 MHz 10/f MCK 10/fMCK —n s

4 MHz < fMCK ≤ 8 MHz 8/f MCK 8/fMCK —n s

fMCK ≤ 4 MHz 6/f MCK 6/fMCK 10/fMCK ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V

24 MHz < fMCK 20/fMCK —— n s

20 MHz < fMCK ≤ 24 MHz 16/f MCK 16/fMCK —n s

16 MHz < fMCK ≤ 20 MHz 14/f MCK 14/fMCK —n s

8 MHz < fMCK ≤ 16 MHz 12/f MCK 12/fMCK —n s

fMCK ≤ 4 MHz 6/f MCK 6/fMCK 10/fMCK ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2

24 MHz < fMCK 48/fMCK —— n s

20 MHz < fMCK ≤ 24 MHz 36/f MCK 36/fMCK —n s

16 MHz < fMCK ≤ 20 MHz 32/f MCK 32/fMCK —n s

8 MHz < fMCK ≤ 16 MHz 26/f MCK 26/fMCK —n s

4 MHz < fMCK ≤ 8 MHz 16/f MCK 16/fMCK —n s

fMCK ≤ 4 MHz 10/f MCK 10/fMCK 10/fMCK ns

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 105 of 145 Oct 31, 2025 9. In simplified SPI (CSI) communications in the slave mode wit h devices operating at different voltage levels (1.8 V, Note 1. Transfer rate in the SNOOZE mode: 1 Mbps (max.) Note 2. Use this rate with VDD ≥ Vb. Note 3. This is for when the settings are DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. When the settings are DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0, this is the setup time to or from the falling of SCKp. Note 4. This is for when the settings are DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. When the settings are DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0, this is the delay time to the rising of SCKp. Caution Select the TTL input buffer for the SIp and SCKp pins, and the N-ch open-drain output (withstand voltage of V DD) mode for the SOp pin by using the port input mode register (PIMg) and port output mode register (POMg). For VIH and VIL, see the DC characteristics with the TTL input buffer selected. (Remarks are listed on the next page.) (TA = -40 to +105°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) (2/2) Item Symbols Conditions HS (high-speed main) mode LS (low-speed main) mode LP (low-power main) mode Unit SCKp high-/low-level width tKH2, tKL2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V tKCY2/2 -12 tKCY2/2 -12 tKCY2/2 -50 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V tKCY2/2 -18 tKCY2/2 -18 tKCY2/2 -50 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2 tKCY2/2 -50 tKCY2/2 -50 tKCY2/2 -50 ns SIp setup time to the rising of SCKpNote 3 tSIK2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V 1/fMCK +20 1/fMCK +20 1/fMCK +30 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V 1/fMCK +20 1/fMCK +20 1/fMCK +30 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2 1/fMCK +30 1/fMCK +30 1/fMCK +30 ns SIp hold time from the rising of SCKpNote 3 tKSI2 1/fMCK +31 1/fMCK +31 1/fMCK +31 ns Delay time from the falling of SCKp to an SOp outputNote 4 tKSO2 4.0 V ≤ VDD ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ 2/fMCK +120 2/fMCK +120 2/fMCK +573 ns 2.7 V ≤ VDD < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ 2/fMCK +214 2/fMCK +214 2/fMCK +573 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 30 pF, Rb = 5.5 kΩ 2/fMCK +573 2/fMCK +573 2/fMCK +573 ns

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 106 of 145 Oct 31, 2025 Connection in the simplified SPI (CSI) communications with devices operating at different voltage levels Remark 1. Rb[Ω]: Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance, Vb[V]: Communication line voltage Remark 2. p: CSI number (p = 00, 01, 10, 20, 30, 31), g: PIM and POM number (g = 0 to 9, 12 to 14), m: Unit number, n: Channel number (mn = 00 to 02, 10, 12, 13) Remark 3. fMCK: Serial array unit operation clock frequency To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn) (m: Unit number, n: Channel number = 00, 01, 02, 10, 12 and 13). Timing of serial transfer in the simplified SPI (CSI) communications in the slave mode with devices operating at different voltage levels when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1 SCKp SOp SCK SI SIp SO Vb Rb <Slave> RL78 microcontroller User device SIp SOp SCKp Input data Output data tKCY2 tKH2tKL2 tSIK2 tKSI2 tKSO2

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 107 of 145 Oct 31, 2025 Timing of serial transfer in the simplified SPI (CSI) communications in the slave mode with devices operating at different voltage levels when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0 Remark p: CSI number (p = 00, 01, 10, 20, 30, 31), g: PIM and POM number (g = 0 to 9, 12 to 14), m: Unit number, n: Channel number (mn = 00 to 02, 10, 12, 13) Input data Output data SIp SOp SCKp tKCY2 tKL2tKH2 tSIK2 tKSI2 tKSO2

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 108 of 145 Oct 31, 2025 10. Simplified I2C communications with devices operating at different voltage levels (1.8 V, 2.5 V, or 3 V) (TA = -40 to +105°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) (1/2) Item Symbols Conditions HS (high-speed main) mode LS (low-speed main) mode LP (low-power main) mode Unit SCLr clock frequency f SCL 4.0 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 1000 Note 1 1000 Note 1 300 Note 1 kHz 2.7 V ≤ VDD < 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 1000 Note 1 1000 Note 1 300 Note 1 kHz 4.0 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 2.8 kΩ 400 Note 1 400 Note 1 300 Note 1 kHz 2.7 V ≤ VDD < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ 400 Note 1 400 Note 1 300 Note 1 kHz 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 100 pF, Rb = 5.5 kΩ 300 Note 1 300 Note 1 300 Note 1 kHz Hold time when SCLr is low tLOW 4.0 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 475 475 1550 ns 2.7 V ≤ VDD < 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 475 475 1550 ns 4.0 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 2.8 kΩ 1150 1550 1550 ns 2.7 V ≤ VDD < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ 1150 1550 1550 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 100 pF, Rb = 5.5 kΩ 1550 1550 1550 ns Hold time when SCLr is high tHIGH 4.0 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 245 245 610 ns 2.7 V ≤ VDD < 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 200 200 610 ns 4.0 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 2.8 kΩ 675 675 610 ns 2.7 V ≤ VDD < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ 600 600 610 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 100 pF, Rb = 5.5 kΩ 610 610 610 ns

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 109 of 145 Oct 31, 2025 10. Simplified I2C communications with devices operating at different voltage levels (1.8 V, 2.5 V, and 3 V) Note 1. The listed times must be no greater than fMCK/4. Note 2. Use this rate with VDD ≥ Vb. Note 3. Set fMCK so that it will not exceed the hold time when SCLr is low or high. Caution Select the TTL input buffer and N-ch open-drain output (withstand voltage of V DD) mode for the SDAr pin, and the N-ch open-drain output (withstand voltage of VDD) mode for the SCLr pin by using the port input mode register (PIMg) and port output mode register (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.) (TA = -40 to +105°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) (2/2) Item Symbols Conditions HS (high-speed main) mode LS (low-speed main) mode LP (low-power main) mode Unit Data setup time (reception) tSU:DAT 4.0 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 1/fMCK +135 Note 3 1/fMCK +135 Note 3 1/fMCK +190 Note 3 ns 2.7 V ≤ VDD < 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 1/fMCK +135 Note 3 1/fMCK +135 Note 3 1/fMCK +190 Note 3 ns 4.0 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 2.8 kΩ 1/fMCK +190 Note 3 1/fMCK +190 Note 3 1/fMCK +190 Note 3 ns 2.7 V ≤ VDD < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ 1/fMCK +190 Note 3 1/fMCK +190 Note 3 1/fMCK +190 Note 3 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 100 pF, Rb = 5.5 kΩ 1/fMCK +190 Note 3 1/fMCK +190 Note 3 1/fMCK +190 Note 3 ns Data hold time (transmission) tHD:DAT 4.0 V ≤ VDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 0 305 0 305 0 305 ns 2.7 V ≤ VDD < 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 0 305 0 305 0 305 ns 4.0 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 2.8 kΩ 0 355 0 355 0 355 ns 2.7 V ≤ VDD < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ 0 355 0 355 0 355 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 100 pF, Rb = 5.5 kΩ 0 405 0 405 0 405 ns

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 110 of 145 Oct 31, 2025 Connection in the I2C communications with devices operating at different voltage levels Timing of serial transfer in the simplified I2C communications with devices operating at different voltage levels Remark 1. Rb[Ω]: Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance, Vb[V]: Communication line voltage Remark 2. r: IIC number (r = 00, 01, 10, 20, 30, 31), g: PIM and POM number (g = 0 to 9, 12 to 14) Remark 3. fMCK: Serial array unit operation clock frequency To set this operating clock, use the CKSmn bit in the SMRmn register (m: Unit number, n: Channel number (mn = 00 to 02, 10, 12, 13). RL78 microcontroller SDAr SCLr SDA SCL Vb Rb Vb Rb User device SDAr SCLr 1/fSCL tLOW tHIGH tSU:DATtHD:DAT

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 111 of 145 Oct 31, 2025

2.5.2 Serial interface UARTA

Caution Select the normal input buffer for the RxDAn pin, and the normal output mode for the TxDAn pin by using the port input mode register (PIMg) and port output mode register (POMh). Remark n: Unit number (n = 0 to 3), g: PIM number (g = 1, 2, 4, 5, 8, 14), h: POM number (h= 0 to 2, 4 to 6, 8, 13, 14) (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) Item Symbols Conditions Min. Typ. Max. Unit Transfer rate 200 0 153600 bps <R>

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2.5.3 Serial interface IICA

I 2C standard mode Note 1. The first clock pulse is generated after this period when the start or restart condition is detected. Note 2. The maximum value of tHD:DAT applies to normal transfer. The clock stretching will be inserted on reception of an acknowledgment (ACK) signal. Remark 1. The maximum value of communication line capacitance (Cb) and communication line pull-up resistor (Rb) are as follows. Cb = 400 pF, Rb = 2.7 kΩ Remark 2. n = 0, 1 (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) Item Symbols Conditions Min. Typ. Max. Unit SCLA0 clock frequency f SCL Standard mode: fCLK ≥ 1 MHz 0 100 kHz Setup time of restart condition t SU:STA 4.7 µs Hold timeNote 1 tHD:STA 4.0 µs Hold time when SCLA0 is low t LOW 4.7 µs Hold time when SCLA0 is high t HIGH 4.0 µs Data setup time (reception) t SU:DAT 250 ns Data hold time (transmission)Note 2 tHD:DAT 03 . 4 5 µ s Setup time of stop condition t SU:STO 4.0 µs Bus-free time t BUF 4.7 µs

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 113 of 145 Oct 31, 2025 2. I 2C fast mode Note 1. The first clock pulse is generated after this period when the start or restart condition is detected. Note 2. The maximum value of tHD:DAT applies to normal transfer. The clock stretching will be inserted on reception of an acknowledgment (ACK) signal. Remark 1. The maximum value of communication line capacitance (Cb) and communication line pull-up resistor (Rb) are as follows. Cb = 320 pF, Rb = 1.1 kΩ Remark 2. n = 0, 1 (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) Item Symbols Conditions Min. Typ. Max. Unit SCLAn clock frequency f SCL Fast mode: fCLK ≥ 3.5 MHz 1.8 V ≤ VDD ≤ 5.5 V 0 400 kHz Setup time of restart condition t SU:STA 1.8 V ≤ VDD ≤ 5.5 V 0.6 µs Hold timeNote 1 tHD:STA 1.8 V ≤ VDD ≤ 5.5 V 0.6 µs Hold time when SCLAn is low t LOW 1.8 V ≤ VDD ≤ 5.5 V 1.3 µs Hold time when SCLAn is high t HIGH 1.8 V ≤ VDD ≤ 5.5 V 0.6 µs Data setup time (reception) t SU:DAT 1.8 V ≤ VDD ≤ 5.5 V 100 ns Data hold time (transmission)Note 2 tHD:DAT 1.8 V ≤ VDD ≤ 5.5 V 0 0.9 µs Setup time of stop condition t SU:STO 1.8 V ≤ VDD ≤ 5.5 V 0.6 µs Bus-free time t BUF 1.8 V ≤ VDD ≤ 5.5 V 1.3 µs

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 114 of 145 Oct 31, 2025 3. I 2C fast mode plus Note 1. The first clock pulse is generated after this period when the start or restart condition is detected. Note 2. The maximum value of tHD:DAT applies to normal transfer. The clock stretching will be inserted on reception of an acknowledgment (ACK) signal. Remark 1. The maximum value of communication line capacitance (Cb) and communication line pull-up resistor (Rb) are as follows. Cb = 120 pF, Rb = 1.1 kΩ Remark 2. n = 0, 1 IICA serial transfer timing Remark n = 0, 1 (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) Item Symbols Conditions Min. Typ. Max. Unit SCLAn clock frequency f SCL Fast mode plus: fCLK ≥ 10 MHz 2.7 V ≤ VDD ≤ 5.5 V 0 1000 kHz Setup time of restart condition t SU:STA 2.7 V ≤ VDD ≤ 5.5 V 0.26 µs Hold timeNote 1 tHD:STA 2.7 V ≤ VDD ≤ 5.5 V 0.26 µs Hold time when SCLAn is low t LOW 2.7 V ≤ VDD ≤ 5.5 V 0.5 µs Hold time when SCLAn is high t HIGH 2.7 V ≤ VDD ≤ 5.5 V 0.26 µs Data setup time (reception) t SU:DAT 2.7 V ≤ VDD ≤ 5.5 V 50 ns Data hold time (transmission)Note 2 tHD:DAT 2.7 V ≤ VDD ≤ 5.5 V 0 0.45 µs Setup time of stop condition t SU:STO 2.7 V ≤ VDD ≤ 5.5 V 0.26 µs Bus-free time t BUF 2.7 V ≤ VDD ≤ 5.5 V 0.5 µs tSU:DATtHD:STA Restart condition SCLAn SDAAn tLOW tHIGH tR tF tSU:STA tHD:STA tSU:STO Stop condition Stop condition Start condition tHD:DAT tBUF

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2.6 Analog Characteristics

2.6.1 A/D converte r characteristics

Normal modes 1 and 2 Note 1. This value does not include the quantization error (±1/2 LSB). Note 2. The values in the column Max. only apply in the case of a normal distribution with ±3σ variation from the mean. Note 3. We do not inspect the characteristics of the A/D converter before shipment. The listed values are only results of evaluation. Note 4. When AVREFP < VDD, the maximum values are as follows. Note 5. The listed values apply when the conversion resolution is set to 12 bits. Note 6. When the internal reference voltage or the temperature sensor output voltage is selected as the target for conversion, the sampling time must be at least 5 µs. Accordingly, use standard mode 2 with the longer sampling time. Note 7. This value is indicated as a ratio (%FSR) to the full-scale value. (TA = -40 to +105°C, 2.4 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = 0 V, reference voltage (+) = AVREFP (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) = AVREFM (ADREFM = 1), target pins: ANI16 to ANI26) Item Symbols Conditions Min. Typ. Max. Unit Resolution RES 12 bit Conversion clock f AD 13 2 M H z Overall errorNotes 1, 2, 3, 4, 5 AINL 4.5 V ≤ AVREFP = VDD ≤ 5.5 V ±1.8 ±4.1 LSB 2.7 V ≤ AVREFP = VDD ≤ 5.5 V ±2.1 ±4.2 LSB 2.4 V ≤ AVREFP = VDD ≤ 5.5 V ±2.4 ±4.7 LSB Conversion timeNotes 5, 6 tCONV 4.5 V ≤ AVREFP = VDD ≤ 5.5 V 2.0 µs 2.7 V ≤ AVREFP = VDD ≤ 5.5 V 2.0 µs 2.4 V ≤ AVREFP = VDD ≤ 5.5 V 2.0 µs Zero-scale errorNotes 1, 2, 3, 4, 5, 7 EZS 4.5 V ≤ AVREFP = VDD ≤ 5.5 V ±0.01 ±0.06 %FSR 2.7 V ≤ AVREFP = VDD ≤ 5.5 V ±0.02 ±0.09 %FSR 2.4 V ≤ AVREFP = VDD ≤ 5.5 V ±0.03 ±0.11 %FSR Full-scale errorNotes 1, 2, 3, 4, 5, 7 EFS 4.5 V ≤ AVREFP = VDD ≤ 5.5 V ±0.02 ±0.09 %FSR 2.7 V ≤ AVREFP = VDD ≤ 5.5 V ±0.03 ±0.11 %FSR 2.4 V ≤ AVREFP = VDD ≤ 5.5 V ±0.03 ±0.11 %FSR Analog input voltage V AIN 0A V REFP V Overall error/zero-scale error/full-scale error: Add (±0.75 LSB × (VDD voltage (V) - AVREFP voltage (V)) to the maximum value. Integral linearity error: Add (±0.2 LSB × (VDD voltage (V) - AVREFP voltage (V)) to the maximum value.

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 116 of 145 Oct 31, 2025 Note 1. This value does not include the quantization error (±1/2 LSB). Note 2. When pins ANI16 to ANI26 are selected as the target pins for conversion or the TSCAP voltage of the CTSU is to be A/D converted, the maximum values are as follows. Overall error: Add ±3 LSB to the maximum value. Zero-scale/full-scale error: Add ±0.04%FSR to the maximum value. Note 3. When reference voltage (+) = VDD and reference voltage (-) = VSS, the maximum values are as follows. Overall error: Add ±10 LSB to the maximum value. Zero-scale/full-scale error: Add ±0.25%FSR to the maximum value. Integral linearity error: Add ±4 LSB to the maximum value. Note 4. When AVREFP < VDD, the maximum values are as follows. Note 5. When the internal reference voltage or the temperature sensor output voltage is selected as the target for conversion, the sampling time must be at least 5 µs. Accordingly, use standard mode 2 with the longer sampling time. Note 6. This value is indicated as a ratio (%FSR) to the full-scale value. (TA = -40 to +105°C, 2.4 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = 0 V, reference voltage (+) = AVREFP (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) = AVREFM (ADREFM = 1), target pins: internal reference voltage and temperature sensor output voltage) Item Symbols Conditions Min. Typ. Max. Unit Resolution RES 8 12 bit Conversion clock f AD 13 2 M H z Overall errorNotes 1, 2, 3, 4 AINL 12-bit resolution 4.5 V ≤ AVREFP = VDD ≤ 5.5 V ±7.5 LSB 2.7 V ≤ AVREFP = VDD ≤ 5.5 V ±9.0 LSB 2.4 V ≤ AVREFP = VDD ≤ 5.5 V ±9.0 LSB Conversion timeNote 5 tCONV 12-bit resolution 4.5 V ≤ AVREFP = VDD ≤ 5.5 V 2.0 µs 2.7 V ≤ AVREFP = VDD ≤ 5.5 V 2.0 µs 2.4 V ≤ AVREFP = VDD ≤ 5.5 V 2.0 µs Zero-scale errorNotes 1, 2, 3, 4, 6 EZS 12-bit resolution 4.5 V ≤ AVREFP = VDD ≤ 5.5 V ±0.17 %FSR 2.7 V ≤ AVREFP = VDD ≤ 5.5 V ±0.21 %FSR 2.4 V ≤ AVREFP = VDD ≤ 5.5 V ±0.21 %FSR Full-scale errorNotes 1, 2, 3, 4, 6 EFS 12-bit resolution 4.5 V ≤ AVREFP = VDD ≤ 5.5 V ±0.17 %FSR 2.7 V ≤ AVREFP = VDD ≤ 5.5 V ±0.21 %FSR 2.4 V ≤ AVREFP = VDD ≤ 5.5 V ±0.21 %FSR Integral linearity errorNotes 1, 3, 4 ILE 12-bit resolution 4.5 V ≤ AVREFP = VDD ≤ 5.5 V ±3.0 LSB 2.7 V ≤ AVREFP = VDD ≤ 5.5 V ±3.0 LSB 2.4 V ≤ AVREFP = VDD ≤ 5.5 V ±3.0 LSB Differential linearity errorNote 1 DLE 12-bit resolution 4.5 V ≤ AVREFP = VDD ≤ 5.5 V ±1.0 LSB 2.7 V ≤ AVREFP = VDD ≤ 5.5 V ±1.0 LSB 2.4 V ≤ AVREFP = VDD ≤ 5.5 V ±1.0 LSB Analog input voltage V AIN 0A V REFP V Overall error/zero-scale error/full-scale error: Add (±0.75 LSB × (VDD voltage (V) - AVREFP voltage (V)) to the maximum value. Integral linearity error: Add (±0.2 LSB × (VDD voltage (V) - AVREFP voltage (V)) to the maximum value.

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 117 of 145 Oct 31, 2025 2. Low-voltage modes 1 and 2 Note 1. If the internal reference voltage, temperature sensor output voltage, or TSCAP voltage of the CTSU is to be A/D converted, VDD must be at least 1.8 V. Note 2. This value does not include the quantization error (±1/2 LSB). Note 3. When pins ANI16 to ANI26 are selected as the target pins for conversion or the TSCAP voltage of the CTSU is to be A/D converted, the maximum values are as follows. If the CTSU TSCAP voltage is to be A/D converted, VDD must be at least 1.8 V. Overall error: Add ±3 LSB to the maximum value. Zero-scale/full-scale error: Add ±0.04%FSR to the maximum value. Note 4. When reference voltage (+) = VDD and reference voltage (-) = VSS, the maximum values are as follows. Overall error: Add ±10 LSB to the maximum value. Zero-scale/full-scale error: Add ±0.25%FSR to the maximum value. Integral linearity error: Add ±4 LSB to the maximum value. Note 5. When AVREFP < VDD, the maximum values are as follows. (TA = -40 to +105°C, 1.6 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = 0 V, reference voltage (+) = AVREFP (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) = AVREFM (ADREFM = 1), target pins: internal reference voltageNote 1and temperature sensor output voltageNote 1) Item Symbols Conditions Min. Typ. Max. Unit Resolution RES 8 12 bit Conversion clock f AD 12 4 M H z Overall errorNotes 2, 3, 4, 5 AINL 12-bit resolution 2.7 V ≤ AVREFP = VDD ≤ 5.5 V ±9 LSB 2.4 V ≤ AVREFP = VDD ≤ 5.5 V ±9 LSB 1.8 V ≤ AVREFP = VDD ≤ 5.5 V ±11.5 LSB 1.6 V ≤ AVREFP = VDD ≤ 5.5 V ±12.0 LSB Conversion timeNote 6 tCONV 12-bit resolution 2.7 V ≤ AVREFP = VDD ≤ 5.5 V 3.33 µs 2.4 V ≤ AVREFP = VDD ≤ 5.5 V 5.0 µs 1.8 V ≤ AVREFP = VDD ≤ 5.5 V 10.0 µs 1.6 V ≤ AVREFP = VDD ≤ 5.5 V 20.0 µs Zero-scale errorNotes 2, 3, 4, 5, 7 EZS 12-bit resolution 2.7 V ≤ AVREFP = VDD ≤ 5.5 V ±0.21 %FSR 2.4 V ≤ AVREFP = VDD ≤ 5.5 V ±0.21 %FSR 1.8 V ≤ AVREFP = VDD ≤ 5.5 V ±0.27 %FSR 1.6 V ≤ AVREFP = VDD ≤ 5.5 V ±0.28 %FSR Full-scale errorNotes 2, 3, 4, 5, 7 EFS 12-bit resolution 2.7 V ≤ AVREFP = VDD ≤ 5.5 V ±0.21 %FSR 2.4 V ≤ AVREFP = VDD ≤ 5.5 V ±0.21 %FSR 1.8 V ≤ AVREFP = VDD ≤ 5.5 V ±0.27 %FSR 1.6 V ≤ AVREFP = VDD ≤ 5.5 V ±0.28 %FSR Integral linearity errorNotes 2, 4, 5 ILE 12-bit resolution 2.7 V ≤ AVREFP = VDD ≤ 5.5 V ±4.0 LSB 2.4 V ≤ AVREFP = VDD ≤ 5.5 V ±4.0 LSB 1.8 V ≤ AVREFP = VDD ≤ 5.5 V ±4.5 LSB 1.6 V ≤ AVREFP = VDD ≤ 5.5 V ±4.5 LSB Differential linearity errorNote 2 DLE 12-bit resolution 2.7 V ≤ AVREFP = VDD ≤ 5.5 V ±1.5 LSB 2.4 V ≤ AVREFP = VDD ≤ 5.5 V ±1.5 LSB 1.8 V ≤ AVREFP = VDD ≤ 5.5 V ±2.0 LSB 1.6 V ≤ AVREFP = VDD ≤ 5.5 V ±2.0 LSB Analog input voltage V AIN 0A V REFP V Overall error/zero-scale error/full-scale error: Add (±0.75 LSB × (VDD voltage (V) - AVREFP voltage (V)) to the maximum value. Integral linearity error: Add (±0.2 LSB × (VDD voltage (V) - AVREFP voltage (V)) to the maximum value.

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 118 of 145 Oct 31, 2025 Note 6. When the internal reference voltage or the temperature sensor output voltage is selected as the target for conversion, the sampling time must be at least 5 µs. Accordingly, use standard mode 2 with the longer sampling time, and use the conversion clock (f AD) of no more than 16 MHz. Note 7. This value is indicated as a ratio (%FSR) to the full-scale value.

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 119 of 145 Oct 31, 2025 3. When the internal reference voltage is selected as reference voltage (+) Note 1. This value does not include the quantization error (±1/2 LSB). Note 2. This value is indicated as a ratio (%FSR) to the full-scale value. Note 3. When reference voltage (-) is selected as VSS, the maximum values are as follows. Zero-scale error: Add ±0.35%FSR to the maximum value. Integral linearity error: Add ±0.5 LSB to the maximum value. Note 4. See 2.6.2 Temperature sensor/internal reference voltage characteristics. (TA = -40 to +105°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V, low-voltage modes 1 and 2, reference voltage (+) = internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (-) = AVREFM (ADREFM = 1) Item Symbols Conditions Min. Typ. Max. Unit Resolution RES 8 bit Conversion clock f AD 1.8 V ≤ VDD ≤ 5.5 V 1 2 MHz Zero-scale errorNotes 1, 2, 3 EZS 1.8 V ≤ VDD ≤ 5.5 V ±0.6 %FSR Integral linearity errorNotes 1, 3 ILE 1.8 V ≤ VDD ≤ 5.5 V ±2.0 LSB Differential linearity errorNote 1 DLE 1.8 V ≤ VDD ≤ 5.5 V ±1.0 LSB Analog input voltage V AIN 0V BGR Note 4 V

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2.6.2 Temperature sensor/internal reference voltage characteristics

2.6.3 D/A converter characteristics

(TA = -40 to +105°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Item Symbols Conditions Min. Typ. Max. Unit Temperature sensor output voltage VTMPS25 Setting ADS register = 80H, TA = +25°C 1.05 V Internal reference voltage V BGR Setting ADS register = 81H 1.42 1.48 1.54 V Temperature coefficient F VTMPS Temperature dependency of the temperature sensor voltage -3.3 mV/°C Operation stabilization wait time tAMP 5µ s (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) Item Symbols Conditions Min. Typ. Max. Unit Resolution RES 8b i t Overall error AINL Rload = 8 M Ω 1.8 V ≤ VDD ≤ 5.5 V ±2.5 LSB Rload = 4 MΩ 1.8 V ≤ VDD ≤ 5.5 V ±2.5 LSB Settling time t SET Cload = 20 pF 2.7 V ≤ VDD ≤ 5.5 V 3 µs 1.6 V ≤ VDD ≤ 5.5 V 6 µs

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2.6.4 Comparator characteristics

Note The internal reference voltage can be selected as comparator reference voltage only when 1.8 V ≤ VDD ≤ 5.5 V. (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) Item Symbols Conditions Min. Typ. Max. Unit Input voltage range I VREF Input to the IVREF0 and IVREF1 pins C0LVL = 0, C1LVL = 0 0V DD -1.4 V Input to the IVREF0 and IVREF1 pins C0LVL = 1, C1LVL = 1

1.4 V DD V

IVCMP Input to the IVCMP0 and IVCMP1 pins -0.3 V DD +0.3 V Output delay td V DD = 3.0 V, Input slew rate > 1 V/µs High-speed mode 1.5 µs Low-speed mode 3.0 µs Offset voltage V IOCMP High-speed mode 50 mV Low-speed mode 40 mV Operation stabilization wait time t CMP 30 µs Internal reference voltageNote VBGR2 Internal reference voltage 1.4 1.6 V VDA2 D/A converter output 2 + comparator offset voltage 1.8 V ≤ VDD ≤ 5.5 V V DD × (DACS2)/ 256 + VIOCMP V D/A converter channel 2 settling time tSET2 When changing the DACS2 settings 2.7 V ≤ VDD ≤ 5.5 3 µs 1.6 V ≤ VDD ≤ 5.5 V 6 µs

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2.6.5 POR circuit characteristics

Note This width is the minimum time required for a POR reset when VDD falls below VPDR. This width is also the minimum time required for a POR reset from when VDD falls below 0.7 V to when VDD exceeds VPOR in the STOP mode or while the main system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control register (CSC). (TA = -40 to +105°C, VSS = 0 V) Item Symbols Conditions Min. Typ. Max. Unit Detection voltage V POR, VPDR 1.43 1.50 1.57 V Minimum pulse widthNote TPW 300 µs TPW VPOR VPDR or 0.7 V Supply voltage (VDD)

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2.6.6 LVD circuit characteristics

LVD0 Detection Voltage in the Reset Mode and Interrupt Mode (TA = -40 to +105°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V) Item Symbols Conditions Min. Typ. Max. Unit Detection voltage Supply voltage level V LVD00 The power supply voltage is rising. 3.84 3.96 4.08 V The power supply voltage is falling. 3.76 3.88 4.00 V VLVD01 The power supply voltage is rising. 2.88 2.97 3.06 V The power supply voltage is falling. 2.82 2.91 3.00 V V LVD02 The power supply voltage is rising. 2.59 2.67 2.75 V The power supply voltage is falling. 2.54 2.62 2.70 V V LVD03 The power supply voltage is rising. 2.31 2.38 2.45 V The power supply voltage is falling. 2.26 2.33 2.40 V V LVD04 The power supply voltage is rising. 1.84 1.90 1.95 V The power supply voltage is falling. 1.80 1.86 1.91 V V LVD05 The power supply voltage is rising. 1.64 1.69 1.74 V The power supply voltage is falling. 1.60 1.65 1.70 V Minimum pulse width t LW 500 µs Detection delay time 500 µs

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 124 of 145 Oct 31, 2025 2. LVD1 Detection Voltage of Reset Mode and Interrupt Mode (TA = -40 to +105°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V) Item Symbols Conditions Min. Typ. Max. Unit Detection voltage Supply voltage level V LVD10 The power supply voltage is rising. 4.08 4.16 4.24 V The power supply voltage is falling. 4.00 4.08 4.16 V VLVD11 The power supply voltage is rising. 3.88 3.96 4.04 V The power supply voltage is falling. 3.80 3.88 3.96 V V LVD12 The power supply voltage is rising. 3.68 3.75 3.82 V The power supply voltage is falling. 3.60 3.67 3.74 V V LVD13 The power supply voltage is rising. 3.48 3.55 3.62 V The power supply voltage is falling. 3.40 3.47 3.54 V V LVD14 The power supply voltage is rising. 3.28 3.35 3.42 V The power supply voltage is falling. 3.20 3.27 3.34 V V LVD15 The power supply voltage is rising. 3.07 3.13 3.19 V The power supply voltage is falling. 3.00 3.06 3.12 V V LVD16 The power supply voltage is rising. 2.91 2.97 3.03 V The power supply voltage is falling. 2.85 2.91 2.97 V V LVD17 The power supply voltage is rising. 2.76 2.82 2.87 V The power supply voltage is falling. 2.70 2.76 2.81 V V LVD18 The power supply voltage is rising. 2.61 2.66 2.71 V The power supply voltage is falling. 2.55 2.60 2.65 V V LVD19 The power supply voltage is rising. 2.45 2.50 2.55 V The power supply voltage is falling. 2.40 2.45 2.50 V V LVD110 The power supply voltage is rising. 2.35 2.40 2.45 V The power supply voltage is falling. 2.30 2.35 2.40 V V LVD111 The power supply voltage is rising. 2.25 2.30 2.34 V The power supply voltage is falling. 2.20 2.25 2.29 V V LVD112 The power supply voltage is rising. 2.15 2.20 2.24 V The power supply voltage is falling. 2.10 2.15 2.19 V V LVD113 The power supply voltage is rising. 2.05 2.09 2.13 V The power supply voltage is falling. 2.00 2.04 2.08 V V LVD114 The power supply voltage is rising. 1.94 1.98 2.02 V The power supply voltage is falling. 1.90 1.94 1.98 V V LVD115 The power supply voltage is rising. 1.84 1.88 1.91 V The power supply voltage is falling. 1.80 1.84 1.87 V V LVD116 The power supply voltage is rising. 1.74 1.78 1.81 V The power supply voltage is falling. 1.70 1.74 1.77 V V LVD117 The power supply voltage is rising. 1.64 1.67 1.70 V The power supply voltage is falling. 1.60 1.63 1.66 V Minimum pulse width t LW 500 µs Detection delay time 500 µs

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 125 of 145 Oct 31, 2025

2.6.7 Power supply voltage rising slope characteristics

Caution Make sure to keep the internal reset state by the LVD0 circuit or an external reset until V DD reaches the operating voltage range shown in AC characteristics. (TA = -40 to +105°C, VSS = 0 V) Item Symbols Conditions Min. Typ. Max. Unit Power supply voltage rising slope SVDD 54 V/ms

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 126 of 145 Oct 31, 2025

2.6.8 LCD characteristics

2.6.8.1 External resist ance division method

Static display mode 2. 1/2 bias method, 1/4 bias method 3. 1/3 bias method A = -40 to +105°C, VL4 (Min.) ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) Item Symbols Conditions Min. Typ. Max. Unit LCD drive voltage V L4 2.0 V DD V (TA = -40 to +105°C, VL4 (Min.) ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) Item Symbols Conditions Min. Typ. Max. Unit LCD drive voltage V L4 2.7 V DD V (TA = -40 to +105°C, VL4 (Min.) ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) Item Symbols Conditions Min. Typ. Max. Unit LCD drive voltage V L4 2.5 V DD V

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 127 of 145 Oct 31, 2025

2.6.8.2 Internal volt age boosting method

1/3 bias method, V L1 reference (MDSET2 to MDSET0 = 001B, LBAS1 to LBAS0 = 01B) Note 1. C1 to C4 are the capacitors that are to be connected to the LCD drive voltage pins of the MCU. C1 is to be connected between CAPH and CAPL. C2 is to be connected between V L1 and GND. C3 is to be connected between VL2 and GND. C4 is to be connected between VL4 and GND. C1 = C2 = C3 = C4 = 0.47 µF ±30% Note 2. This is the time required to wait from when the reference voltage is specified by using the VLCD register (or when the internal voltage boosting method is selected (MDSET2 to MDSET0 = 001B) if the default reference voltage is used) until voltage boosting starts (VLCON = 1). Note 3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1). (TA = -40 to +105°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) Item Symbols Conditions Min. Typ. Max. Unit VL1 output voltage V L1 C1 to C4Note 1 = 0.47 µF VLCD4-0 = 04H 0.97 1.01 1.04 V VLCD4-0 = 05H 1.00 1.04 1.08 V VLCD4-0 = 06H 1.04 1.07 1.11 V VLCD4-0 = 07H 1.07 1.11 1.14 V VLCD4-0 = 08H 1.10 1.14 1.18 V VLCD4-0 = 09H 1.13 1.17 1.21 V VLCD4-0 = 0AH 1.16 1.21 1.25 V VLCD4-0 = 0BH 1.20 1.24 1.28 V VLCD4-0 = 0CH 1.23 1.27 1.32 V VLCD4-0 = 0DH 1.26 1.31 1.35 V VLCD4-0 = 0EH 1.29 1.34 1.38 V VLCD4-0 = 0FH 1.33 1.37 1.42 V VLCD4-0 = 10H 1.36 1.40 1.45 V VLCD4-0 = 11H 1.39 1.44 1.49 V VLCD4-0 = 12H 1.42 1.47 1.52 V VLCD4-0 = 13H 1.45 1.50 1.55 V VLCD4-0 = 14H 1.49 1.54 1.59 V VLCD4-0 = 15H 1.52 1.57 1.62 V VLCD4-0 = 16H 1.55 1.60 1.66 V VLCD4-0 = 17H 1.58 1.64 1.69 V VLCD4-0 = 18H 1.61 1.67 1.73 V VLCD4-0 = 19H 1.65 1.70 1.76 V VLCD4-0 = 1AH 1.68 1.74 1.79 V VL2 output voltage V L2 C1 to C4Note 1 = 0.47 µF 2VL1 -5% 2V L1 2VL1 V VL4 output voltage V L4 C1 to C4Note 1 = 0.47 µF 3VL1 -6% 3V L1 3VL1 V Reference voltage setup time Note 2 tVWAIT1 10 ms Voltage boost wait timeNote 3 tVWAIT2 C1 to C4Note 1 = 0.47 µF 500 ms

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 128 of 145 Oct 31, 2025 2. 1/3 bias method, V L2 reference (MDSET2 to MDSET0 = 101B, LBAS1 to LBAS0 = 01B) Note 1. C1 to C4 are the capacitors that are to be connected to the LCD drive voltage pins of the MCU. C1 is to be connected between CAPH and CAPL. C2 is to be connected between V L1 and GND. C3 is to be connected between VL2 and GND. C4 is to be connected between VL4 and GND. C1 = C2 = C3 = C4 = 0.47 µF ±30% Note 2. This is the time required to wait from when the reference voltage is specified by using the VLCD register (or when the internal voltage boosting method is selected (MDSET2 to MDSET0 = 101B) if the default reference voltage is used) until voltage boosting starts (VLCON = 1). Note 3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1). (TA = -40 to +105°C, VL2 (Max.) + 0.1 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) Item Symbols Conditions Min. Typ. Max. Unit VL1 output voltage V L1 C1 to C4Note 1 = 0.47 µF 1/2VL2 -5% 1/2VL2 1/2VL2 V VL2 output voltage V L2 C1 to C4Note 1 = 0.47 µF VLCD4-0 = 04H 1.94 2.02 2.11 V VLCD4-0 = 05H 2.00 2.09 2.18 V VLCD4-0 = 06H 2.07 2.16 2.25 V VLCD4-0 = 07H 2.13 2.22 2.32 V VLCD4-0 = 08H 2.19 2.29 2.39 V VLCD4-0 = 09H 2.26 2.36 2.46 V VLCD4-0 = 0AH 2.32 2.42 2.53 V VLCD4-0 = 0BH 2.39 2.49 2.59 V VLCD4-0 = 0CH 2.45 2.56 2.66 V VLCD4-0 = 0DH 2.51 2.62 2.73 V VLCD4-0 = 0EH 2.58 2.69 2.80 V VLCD4-0 = 0FH 2.64 2.76 2.87 V VLCD4-0 = 10H 2.70 2.82 2.94 V VLCD4-0 = 11H 2.77 2.89 3.01 V VLCD4-0 = 12H 2.83 2.96 3.08 V VLCD4-0 = 13H 2.90 3.02 3.15 V VLCD4-0 = 14H 2.96 3.09 3.22 V VLCD4-0 = 15H 3.02 3.15 3.29 V VLCD4-0 = 16H 3.09 3.22 3.35 V VLCD4-0 = 17H 3.15 3.29 3.42 V VLCD4-0 = 18H 3.21 3.35 3.49 V VLCD4-0 = 19H 3.28 3.42 3.56 V VLCD4-0 = 1AH 3.34 3.49 3.63 V VL4 output voltage V L4 C1 to C4Note 1 = 0.47 µF 3/2VL2 -6% 3/2VL2 3/2VL2 V Reference voltage setup time Note 2 tVWAIT1 10 ms Voltage boost wait timeNote 3 tVWAIT2 C1 to C4Note 1 = 0.47 µF 500 ms

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 129 of 145 Oct 31, 2025 3. 1/4 bias method, V L1 reference (MDSET2 to MDSET0 = 001B, LBAS1 to LBAS0 = 10B) Note 1. C1 to C5 are the capacitors that are to be connected to the LCD drive voltage pins of the MCU. C1 is to be connected between CAPH and CAPL. C2 is to be connected between V L1 and GND. C3 is to be connected between VL2 and GND. C4 is to be connected between VL3 and GND. C5 is to be connected between VL4 and GND. C1 = C2 = C3 = C4 = C5 = 0.47 µF ±30% Note 2. This is the time required to wait from when the reference voltage is specified by using the VLCD register (or when the internal voltage boosting method is selected (MDSET2 to MDSET0 = 001B) if the default reference voltage is used) until voltage boosting starts (VLCON = 1). Note 3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1). (TA = -40 to +105°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) Item Symbols Conditions Min. Typ. Max. Unit VL1 output voltage V L1 C1 to C5Note 1 = 0.47 µF VLCD4-0 = 04H 0.97 1.01 1.04 V VLCD4-0 = 05H 1.00 1.04 1.08 V VLCD4-0 = 06H 1.04 1.07 1.11 V VLCD4-0 = 07H 1.07 1.11 1.14 V VLCD4-0 = 08H 1.10 1.14 1.18 V VLCD4-0 = 09H 1.13 1.17 1.21 V VLCD4-0 = 0AH 1.16 1.21 1.25 V VLCD4-0 = 0BH 1.20 1.24 1.28 V VLCD4-0 = 0CH 1.23 1.27 1.32 V VLCD4-0 = 0DH 1.26 1.31 1.35 V VL2 output voltage V L2 C1 to C5Note 1 = 0.47 µF 2VL1 -5% 2VL1 2VL1 V VL3 output voltage V L3 C1 to C5Note 1 = 0.47 µF 3VL1 -6% 3VL1 3VL1 V VL4 output voltage V L4 C1 to C5Note 1 = 0.47 µF 4VL1 -6% 4VL1 4VL1 V Reference voltage setup time Note 2 tVWAIT1 10 ms Voltage boost wait timeNote 3 tVWAIT2 C1 to C5Note 1 = 0.47 µF 500 ms

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 130 of 145 Oct 31, 2025

2.6.8.3 Capacitor split method

1/3 bias method, V DD reference (MDSET2 to MDSET0 = 010B, LBAS1 to LBAS0 = 01B) Note 1. C1 to C4 are the capacitors that are to be connected to the LCD drive voltage pins of the MCU. C1 is to be connected between CAPH and CAPL. C2 is to be connected between V L1 and GND. C3 is to be connected between VL2 and GND. C4 is to be connected between VL4 and GND. This is required when the voltage generation method is switched to the internal voltage boosting method. C1 = C2 = C3 = C4 = 0.47 µF ±30% Note 2. This is the wait time from when voltage bucking is started (VLCON = 1) until display is enabled (LCDON = 1). 2. 1/3 bias method, VL4 reference (MDSET2 to MDSET0 = 110B, LBAS1 to LBAS0 = 01B) Note 1. C1 to C4 are the capacitors that are to be connected to the LCD drive voltage pins of the MCU. C1 is to be connected between CAPH and CAPL. C2 is to be connected between V L1 and GND. C3 is to be connected between VL2 and GND. C4 is to be connected between VL4 and GND. C1 = C2 = C3 = C4 = 0.47 µF ±30% Note 2. The time required to wait from when the capacitor split method is selected (MDSET2 to MDSET0 = 110B) until voltage bucking starts (VLCON = 1). Note 3. This is the wait time from when voltage bucking is started (VLCON = 1) until display is enabled (LCDON = 1). (TA = -40 to +105°C, 2.2 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) Item Symbols Conditions Min. Typ. Max. Unit VL4 output voltage V L4 C1 to C4 = 0.47 µFNote 1 VDD V VL2 output voltage V L2 C1 to C4 = 0.47 µFNote 1 2/3VL4 -3% 2/3VL4 2/3VL4 +3% V VL1 output voltage V L1 C1 to C4 = 0.47 µFNote 1 1/3VL4 -3% 1/3VL4 1/3VL4 +3% V Capacitor split wait timeNote 2 tVWAIT 100 ms (TA = -40 to +105°C, 3.2 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) Item Symbols Conditions Min. Typ. Max. Unit VL4 output voltage V L4 C1 to C4 = 0.47 µFNote 1 2.89 3.04 3.20 V VL2 output voltage V L2 C1 to C4 = 0.47 µFNote 1 1.89 2.03 2.17 V VL1 output voltage V L1 C1 to C4 = 0.47 µFNote 1 0.94 1.01 1.08 V Reference voltage setup time Note 2 tVWAIT1 10 ms Capacitor split wait timeNote 3 tVWAIT 100 ms

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 131 of 145 Oct 31, 2025 3. 1/4 bias method, VDD reference (MDSET2 to MDSET0 = 010B, LBAS1 to LBAS0 = 10B) Note 1. C1 to C5 are the capacitors that are to be connected to the LCD drive voltage pins of the MCU. C1 is to be connected between CAPH and CAPL. C2 is to be connected between V L1 and GND. C3 is to be connected between VL2 and GND. C4 is to be connected between VL3 and GND. This is required when the voltage generation method is switched to the internal voltage boosting method. C5 is to be connected between V L4 and GND. C1 = C2 = C3 = C4 = C5 = 0.47 µF ±30% Note 2. This is the wait time from when voltage bucking is started (VLCON = 1) until display is enabled (LCDON = 1). (TA = -40 to +105°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) Item Symbols Conditions Min. Typ. Max. Unit VL4 output voltage V L4 C1 to C5 = 0.47 µFNote 1 VDD V VL3 output voltage V L3 C1 to C5 = 0.47 µFNote 1 3/4VL4 -3% 3/4VL4 3/4VL4 +3% V VL2 output voltage V L2 C1 to C5 = 0.47 µFNote 1 1/2VL4 -3% 1/2VL4 1/2VL4 +3% V VL1 output voltage V L1 C1 to C5 = 0.47 µFNote 1 1/4VL4 -3% 1/4VL4 1/4VL4 +3% V Capacitor split wait timeNote 2 tVWAIT 100 ms

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 132 of 145 Oct 31, 2025

2.7 RAM Data Retention Characteristics

Note This voltage depends on the POR detection voltage. When the voltage drops, the data in RAM are retained until a POR is applied, but are not retained following a POR. (TA = -40 to +105°C, VSS = 0V) Item Symbols Conditions Min. Typ. Max. Unit Data retention supply voltage V DDDR 1.43Note 5.5 V VDD STOP instruction execution Standby release signal (interrupt request) STOP mode RAM data retention Operation mode VDDDR

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 133 of 145 Oct 31, 2025

2.8 Flash Memory Progr amming Characteristics

Note 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite. Note 2. The listed numbers of times apply when the flash memory programmer or self-programming function is in use. Note 3. These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics Corporation. Note 4. This temperature is the average value at which data are retained. (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Item Symbols Conditions Min. Typ. Max. Unit CPU/peripheral hardware clock frequency f CLK 13 2 M H z Number of code flash rewritesNotes 1, 2, 3 Cerwr Retained for 10 years TA = +85°CNote 4 10,000 Times Retained for 20 years TA = +85°CNote 4 1,000 Number of data flash rewritesNotes 1, 2, 3 Retained for 1 year TA = +25°C 1,000,000 Retained for 5 years TA = +85°CNote 4 100,000 Retained for 20 years TA = +85°CNote 4 10,000

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 134 of 145 Oct 31, 2025 1. Code flash memory Caution The listed values do not include the time until the operations of the flash memory start following execution of an instruction by software. 2. Data flash memory Caution The listed values do not include the time until the operations of the flash memory start following execution of an instruction by software. (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Item Symbols fCLK = 1 MHz f CLK = 2 MHz, 3 MHz 4 MHz ≤ fCLK < 8 MHz 8 MHz ≤ fCLK < 32 MHz f CLK = 32 MHz Unit Programming time Blank checking time Time taken to forcibly stop the erasure Time until programming starts following cancellation of the STOP instruction (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Item Symbols fCLK = 1 MHz f CLK = 2 MHz, 3 MHz 4 MHz ≤ fCLK < 8 MHz 8 MHz ≤ fCLK < 32 MHz f CLK = 32 MHz Unit Programming time Blank checking time Time taken to forcibly stop the erasure Time until programming starts following cancellation of the STOP instruction Time until reading starts following setting DFLCTL.DFLEN to 1

RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 135 of 145 Oct 31, 2025

2.9 Dedicated Flash Memory Pr ogrammer Communication (UART)

2.10 Timing of Entry to Flas h Memory Programming Modes

<1> The low level is input to the TOOL0 pin. <2> The external reset is released. Note that the POR and LVD reset must be released before the external reset is released. <3> The TOOL0 pin is set to the high level. <4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting. (TA = -40 to +105°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) Item Symbols Conditions Min. Typ. Max. Unit Transfer rate During serial programming 115,200 1,000,000 bps (TA = -40 to +105°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) Item Symbols Conditions Min. Typ. Max. Unit Time to complete the communication for the initial setting after the external reset is released t SUINIT POR and LVD reset must be released before the external reset is released. 100 ms Time to release the external reset after the TOOL0 pin is set to the low level tSU POR and LVD reset must be released before the external reset is released. 10 µs Time to hold the TOOL0 pin at the low level after the external reset is released (the processing time of the firmware to control the flash memory is not included) t HD POR and LVD reset must be released before the external reset is released. 1m s Remark tSUINIT : The time during which the communications for the initial setting must be completed within 100 ms after the external reset is released. tSU : Time to release the external reset after the TOOL0 pin is set to the low level tHD : Time to hold the TOOL0 pin at the low level after the external reset is released. It does not include the processing time of the firmware to control the flash memory. RESET TOOL0 tSU <4> tSUINIT 723 µs + tHD processing time 1-byte data for setting mode . . .

RL78/L23 3. Package Drawings R01DS0502EJ0110 Rev.1.10 Page 136 of 145 Oct 31, 2025 3. Package Drawings 3.1 44-pin Products P-LQFP44-10x10-0.80 PLQP0044GC-A P44GB-80-UES-2 0.36 Sy e Sb x M T c L Lp HD ZD ZE A D EH E S 0.145 0.055 0.045 (UNIT:mm) ITEM DIMENSIONS D E HD HE A 10.00r0.20 10.00r0.20 12.00r0.20 12.00r0.20 1.60 MAX. 0.10r0.05 1.40r0.05 0.25 c T ZE 1.00 L Lp 0.50 0.60r0.15 1.00r0.20 3q5q e 0.80 x 0.20 NOTE y 0.10 Each lead centerline is located within 0.20 mm of ZD 1.00 its true position at maximum material c ondition. detail of lead end 0.37 0.08 0.07b 111 44 12 2012 Renesas Electronics Corporation. All rights reserved.

RL78/L23 3. Package Drawings R01DS0502EJ0110 Rev.1.10 Page 137 of 145 Oct 31, 2025 3.2 48-pin Products

RL78/L23 3. Package Drawings R01DS0502EJ0110 Rev.1.10 Page 138 of 145 Oct 31, 2025 INDEX AREA (D/2 X E/2) D SEATING PLANE ccc C bbb C A B ddd C e b(48X) L(48X) K(48X) C aaa C B aaa C (A3) A1A eee C fff C A B fff C A B A EXPOSED DIE PAD 11 2 2536 E 48X 36 25 121 37 24 Reference Symbol Dimension in Millimeters Min. Nom. Max. A 䠉䠉 0.80 A1 0.00 0.02 0.05 A3 0.203 REF. b 0.20 0.25 0.30 D 7.00 BSC E 7.00 BSC e 0.50 BSC L 0 . 3 00 . 4 00 . 5 0 K 0.20 䠉䠉 D2 5.25 5.30 5.35 E2 5.25 5.30 5.35 aaa 0.15 bbb 0.10 ccc 0.10 ddd 0.05 eee 0.08 fff 0.10 P-HWQFN048-7x7-0.50 PWQN0048KC-A 0.13 g

RL78/L23 3. Package Drawings R01DS0502EJ0110 Rev.1.10 Page 139 of 145 Oct 31, 2025 3.3 52-pin Products y e xb M θ L c HD HE A D E 0.145 ±0.055 (UNIT:mm) ITEM DIMENSIONS D E HD HE A 10.00 ±0.10 10.00 ±0.10 12.00 ±0.20 12.00 ±0.20 1.70 MAX. 0.10 ±0.05 1.40 c θ e x y 0.65 0.13 0.10 L 0.50 ±0.15 0° to 8 ° detail of lead end 0.32 ±0.05b 152 2012 Renesas Electronics Corporation. All rights reserved. NOTE 1.Dimensions “ 1” and “ 2” do not include mold flash. 2.Dimension “ 3” does not include trim offset. P-LQFP52-10x10-0.65 PLQP0052JA-A P52GB-65-GBS-1 0.3

RL78/L23 3. Package Drawings R01DS0502EJ0110 Rev.1.10 Page 140 of 145 Oct 31, 2025 3.4 64-pin Products GHWDLORIOHDGHQG 㻝㻝㻢㻝㻣㻟㻞㻟㻟㻠㻤㻠㻥㻢㻠㻖㻝㻖㻞 ES 㻌㼤㻌 H $ $ F V 㻖㻟 Reference Symbol Dimension in Millimeters Min. Nom. Max. E 11.90 12.00 12.10 D 11.90 12.00 12.10 A2 䠉 1.40 䠉 HD 13.80 14.00 14.20 HE 13.80 14.00 14.20 A 䠉䠉 1.70 A1 0.05 䠉 0.15 Lp 0.45 0.60 0.75 L1 䠉 1.00 䠉 bp 0.27 0.32 0.37 c0 . 0 9 䠉 0.20 e 䠉 0.65 䠉 /g84 0.00 3.50 8.00 x 䠉䠉 0.08 y 䠉䠉 0.08 P-LQFP64-12x12-0.65 PLQP0064JB-A 0.50

RL78/L23 3. Package Drawings R01DS0502EJ0110 Rev.1.10 Page 141 of 145 Oct 31, 2025 MASS (Typ) [g] 0.3 Unit: mm Previous CodeRENESAS Code PLQP0064KB-C — P-LFQFP64-10x10-0.50 © 2015 Renesas Electronics Corporation. All rights reserved. D E HD HE A bp c T e x y L p 9.9 9.9 11.8 11.8 0.05 0.15 0.09 0.45 Min Nom Dimensions in millimetersReference Symbol Max 10.0 10.0 1.4 12.0 12.0 0.20 3.5q 0.5 0.6 1.0 10.1 10.1 12.2 12.2 1.7 0.15 0.27 0.20 0.08 0.08 0.75 NOTE) 1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH. 2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET. 3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE LOCATED WITHIN THE HATCHED AREA. 4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY. HD A2A1 Lp Detail F A c 0.25 D 48 33 3249 161 F NOTE 4 NOTE 3 Index area HE E*2 bpe yS S M T

RL78/L23 3. Package Drawings R01DS0502EJ0110 Rev.1.10 Page 142 of 145 Oct 31, 2025 3.5 80-pin Products MASS (Typ) [g] 0.6 Unit: mm Previous CodeRENESAS Code PLQP0080JA-B — P-LQFP80-14x14-0.65 © 2016 Renesas Electronics Corporation. All rights reserved. D E HD HE A bp c T e x y L p 13.9 13.9 15.8 15.8 0.05 0.22 0.09 0.45 Min Nom Dimensions in millimetersReference Symbol Max 14.0 14.0 1.4 16.0 16.0 0.30 3.5q 0.65 0.6 1.0 14.1 14.1 16.2 16.2 1.7 0.15 0.38 0.20 0.13 0.10 0.75 NOTE) 1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH. 2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET. 3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE LOCATED WITHIN THE HATCHED AREA. 4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY. 4160 12 0 HD D*1 HE E NOTE 4 NOTE 3 Index area S e y S F *3 bp M A2A1 A Lp Detail F c 0.25 T

RL78/L23 3. Package Drawings R01DS0502EJ0110 Rev.1.10 Page 143 of 145 Oct 31, 2025 MASS (Typ) [g] 0.5 Unit: mm Previous CodeRENESAS Code PLQP0080KB-B — P-LFQFP80-12x12-0.50 © 2017 Renesas Electronics Corporation. All rights reserved. D E HD HE A bp c T e x y L p 11.9 11.9 13.8 13.8 0.05 0.15 0.09 0.45 Min Nom Dimensions in millimetersReference Symbol Max 12.0 12.0 1.4 14.0 14.0 0.20 3.5q 0.5 0.6 1.0 12.1 12.1 14.2 14.2 1.7 0.15 0.27 0.20 0.08 0.08 0.75 NOTE) 1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH. 2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET. 3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE LOCATED WITHIN THE HATCHED AREA. 4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY. HD D*1 4160 12 0 HE E NOTE 4 NOTE 3 Index area S e y S bp M F A2A1 A Lp Detail F c 0.25 T

RL78/L23 3. Package Drawings R01DS0502EJ0110 Rev.1.10 Page 144 of 145 Oct 31, 2025 3.6 100-pin Products MASS (Typ) [g] 0.6 Unit: mm Previous CodeRENESAS Code PLQP0100KB-B — P-LFQFP100-14x14-0.50 © 2015 Renesas Electronics Corporation. All rights reserved. D E HD HE A bp c T e x y L p 13.9 13.9 15.8 15.8 0.05 0.15 0.09 0.45 Min Nom Dimensions in millimetersReference Symbol Max 14.0 14.0 1.4 16.0 16.0 0.20 3.5q 0.5 0.6 1.0 14.1 14.1 16.2 16.2 1.7 0.15 0.27 0.20 0.08 0.08 0.75 NOTE) 1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH. 2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET. 3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE LOCATED WITHIN THE HATCHED AREA. 4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY. T HD A2A1 Lp Detail F A c 0.25 D 100 26 251 F NOTE 4 NOTE 3 Index area HE E*2 *3 bpe yS S M

RL78/L23 3. Package Drawings R01DS0502EJ0110 Rev.1.10 Page 145 of 145 Oct 31, 2025 B Sy e Sxb M L c Lp HD HE ZD ZE A D E S 0.145 (UNIT:mm) ITEM DIMENSIONS D E HD HE A 20.00 0.20 14.00 0.20 22.00 0.20 16.00 0.20 1.60 MAX. 0.10 0.05 1.40 0.05 0.07 0.08 0.055 0.045 0.25 c e x y ZD ZE 0.65 0.13 0.10 0.575 0.825 L Lp 0.50 0.60 0.15 1.00 0.20 detail of lead end 0.32b 100 31 A AB P-LQFP100-14x20-0.65 PLQP0100JC-A P100GF-65-GBN-1 0.92 2012 Renesas Electronics Corporation. All rights reserved.

Rev. Date

Description

1.00 May 30, 2025 — First edition issued

flash memory and 80- to 100-pin products was modified. flash memory was added. modified. p.111 2.5.2 Serial interface UARTA: Caution was modified. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc. All trademarks and registered trademarks are the property of their respective owners.

Revision History

General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1. Precaution against Electrostatic Discharge (ESD) A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices. 2. Processing at power-on The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the level at which resetting is specified. 3. Input of signal during power-off state Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Follow the guideline for input signal during power-off state as described in your product documentation. 4. Handling of unused pins Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. 5. Clock signals After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable. 6. Voltage application waveform at input pin Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.). 7. Prohibition of access to reserved addresses Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these addresses as the correct operation of the LSI is not guaranteed. 8. Differences between products Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system- evaluation test for the given product.

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Product Information

R7F100LLE3CFB specifications and overview.

Summary

RENESAS MCU Rev.1.10 Oct 31, 2025

Description

RENESAS MCU Rev.1.10 Oct 31, 2025

Source title R7F100LLE3CFB Datasheet(PDF) - Renesas Technology Corp

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