Microcontroller

R7F100GBH2DNP

Renesas Technology Corp

RENESAS MCU Rev.1.40 Oct 31, 2025

Manufacturer: Renesas Technology Corp

Document: 183 Pages / 1Mb

Request Quote Download Datasheet Read online HTML view

More from Renesas Technology Corp Browse R parts

Online Datasheet

Read R7F100GBH2DNP online.

RL78-G23 RENESAS | Alldatasheet

Document overview

Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
PDF pages: 183

Technical content

R01DS0395EJ0140 Rev.1.40 Page 1 of 177 Oct 31, 2025 RL78/G23 RENESAS MCU True low-power platform, 41-µA/MHz operating current, 210-nA data retention current for 4 KB of RAM, up to 768-KB code flash memory and 48-KB RAM, capacitive sensing unit, from 30 to 128 pins, 1.6-5.5 V Datasheet 1. Outline

1.1 Features

Ultra-low power consumption technology

VDD = single power supply voltage of 1.6 to 5.5 V
H A L T m o d e
STOP mode High-speed wakeup from the STOP mode is possible.
SNOOZE mode RL78 CPU core
CISC architecture with 3-stage pipeline
The minimum instruction execution time can be changed from high to ultra-low speed. – High speed: 0.03125 µs at 32-MHz operation with the high-speed on-chip oscillator clock – Ultra-low speed: 30.5 µs at 32.768-kHz operation with the subsystem clock
Multiply/divide/multiply & accumulate instructions are supported.
Address space: 1 MB
General-purpose registers: (8-bit register × 8) × 4 banks
On-chip RAM: 12 to 48 KB Code flash memory
Code flash memory: 96 to 768 KB
Block size: 2 KB
Prohibition of block erase and rewriting (security function)
On-chip debugging
Self-programming (with boot swapping and flash shield window) Data flash memory
Data flash memory: 8 KB
Background operation (BGO): Instructions can be executed from the program memory while rewriting the data flash memory.
Number of rewrites: 1,000,000 times (typ.) High-speed on-chip oscillator
Selectable from among 32 MHz, 24 MHz, 16 MHz,

12 MHz, 8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz,

High accuracy: ±1.0% DD = 1.8 to 5.5 V, TA = -20 to +85°C) Middle-speed on-chip oscillator
Selectable from among 4 MHz, 2 MHz, and 1 MHz with adjustability Low-speed on-chip oscillator
32.768 kHz (typ.) with adjustability Operating ambient temperature A = -40 to +85°C (2D: Consumer applications)
TA = -40 to +105°C (3C: Industrial applications) Power management and reset function
Power-on-reset circuit (POR)
Voltage detectors (LVD0 and LVD1) Data transfer controller (DTC)
Transfer modes: Normal transfer mode, repeat transfer mode, block transfer mode
Activation sources: Activated by interrupt sources.
Chain transfer function SNOOZE mode sequencer (SMS)
Calculations and comparison of values by the commands for use in processing by the sequencer can realize intermittent operations where the RL78/G23 does not have to return to normal operation.
Sequentially handling a total of 32 processes with the use of desired commands from among 21 different ones
The SNOOZE mode sequencer offers operation with low power consumption without using the CPU, flash memory, and RAM. R01DS0395EJ0140 Rev.1.40 Oct 31, 2025

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 2 of 177 Oct 31, 2025 Logic and event link controller (ELCL)

Event signals can be set up between specified peripheral functions.
The signals can be generated by the input of multiple event signals to the logic circuit.
Flip-flop circuits are incorporated to handle setting and resetting functions. Serial interface
Simplified SPI (CSINote 1): 3 to 8 channels
UART/UART (LIN-bus supported)/UARTA: 3 to 6 channels
I2C/Simplified I2C: 4 to 10 channels Remote control signal receiver
1 channel
Matching of 4 waveform patterns (header, data 0, data 1, and special data) Timers
16-bit timer: 8 to 16 channels
32-bit interval timer: 1 channel in 32-bit counter mode 2 channels in 16-bit counter mode 4 channels in 8-bit counter mode
Realtime clock: 1 channel (counting of one second to 99 years, alarm interrupt, and clock correction)
Watchdog timer: 1 channel (operates with the low-speed on-chip oscillator clock) A/D converter
8-/10-/12-bit resolution
Analog input: 8 to 26 channels
Internal reference voltage (1.48 V) and temperature sensor D/A converter
8-bit resolution
Analog output: 2 channels
Output voltage: 0 V to V DD
Realtime output function Comparator
2 channels
Operating modes: Comparator high-speed mode and comparator low-speed mode
The external reference voltage and the internal reference voltage or D/A converter output are selectable as the reference voltage. Capacitive sensing unit
Operating voltage condition: V DD = 1.8 to 5.5 V
Self-capacitance method: A single pin configures a single key, supporting up to 32 keys
Mutual capacitance method: Matrix configuration with 8 × 8 pins, supporting up to 64 keys Input/output port pins
Number of port pins: 26 to 120 N-ch open-drain I/O (withstand voltage of 6 V): 2 to 4 N-ch open-drain I/O (V DD withstand voltage Note 2/EVDD withstand voltageNote 3): 10 to 33 Controlled current drive port pins: 6 to 8
Can be set to N-ch open drain or TTL input buffer, and use of an on-chip pull-up resistor can be specified.
Connectable to a device with different voltage (1.8, 2.5, or 3 V) Others
Key interrupt input
Clock output/buzzer output controller
BCD (binary-coded decimal) correction circuit Note 1. Although the CSI function is generally called SPI, it is also called CSI in this product, so it is referred to as such in this manual. Note 2. This applies to the 30- to 52-pin products. Note 3. This applies to the 64- to 128-pin products. Remark The functions mounted depend on the product. For details, see 1.6 Outline of Functions.

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 3 of 177 Oct 31, 2025 Ο ROM, RAM capacities Code flash memory Data flash memory RAM RL78/G23 30 pins 32 pins 36 pins 40 pins 44 pins 48 pins

768 KB 8 KB 48 KB — — — — R7F100GFN R7F100GGN

512 KB 8 KB 48 KB — — — — R7F100GFL R7F100GGL

384 KB 8 KB 32 KB — — — — R7F100GFK R7F100GGK

256 KB 8 KB 24 KB R7F100GAJ R7F100GBJ R7F100GCJ R7F100GEJ R7F100GFJ R7F100GGJ

192 KB 8 KB 20 KB R7F100GAH R7F100GBH R7F100GCH R7F100GEH R7F100GFH R7F100GGH

128 KB 8 KB 16 KB R7F100GAG R7F100GBG R7F100GCG R7F100GEG R7F100GFG R7F100GGG

96 KB 8 KB 12 KB R7F100GAF R7F100GBF R7F100GCF R7F100GEF R7F100GFF R7F100GGF

52 pins 64 pins 80 pins 100 pins 128 pins

768 KB 8 KB 48 KB R7F100GJN R7F100GLN R7F100GMN R7F100GPN R7F100GSN

512 KB 8 KB 48 KB R7F100GJL R7F100GLL R7F100GML R7F100GPL R7F100GSL

384 KB 8 KB 32 KB R7F100GJK R7F100GLK R7F100GMK R7F100GPK R7F100GSK

256 KB 8 KB 24 KB R7F100GJJ R7F100GLJ R7F100GMJ R7F100GPJ R7F100GSJ

192 KB 8 KB 20 KB R7F100GJH R7F100GLH R7F100GMH R7F100GPH —

128 KB 8 KB 16 KB R7F100GJG R7F100GLG R7F100GMG R7F100GPG —

96 KB 8 KB 12 KB R7F100GJF R7F100GLF — — —

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 4 of 177 Oct 31, 2025

1.2 List of Part Numbers

Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G23 R 7 F 1 0 0 G L J 3 x x x C F B # AA0 RL78/G23 Renesas MCU Renesas semiconductor product Packaging specification #AA0, #BA0, #UA0: Tray (LFQFP, LQFP, LSSOP, HWQFN) #AC0, #BC0, #UC0: Tray (WFLGA) #HA0: Embossed tape (LFQFP, LQFP, LSSOP, HWQFN) #HC0: Embossed tape (WFLGA) ROM number (omitted with blank products) Product name Ordering part number Package type SP: LSSOP, 0.65-mm pitch FP: LQFP, 0.80-mm pitch FA: LQFP, 0.65-mm pitch FB: LFQFP, 0.50-mm pitch NP: HWQFN, 0.50-mm pitch LA: WFLGA, 0.50-mm pitch Fields of application C: Industrial applications D: Consumer applications Ambient operating temperature range 2: -40 to +85°C 3: -40 to +105°C ROM capacity F: 96 KB G: 128 KB H: 192 KB J: 256 KB K: 384 KB L: 512 KB N: 768 KB Pin count A: 30 pins B: 32 pins C: 36 pins E: 40 pins F: 44 pins G: 48 pins J: 52 pins L: 64 pins M: 80 pins P: 100 pins S: 128 pins F: Flash memory Device type

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 5 of 177 Oct 31, 2025 Table 1 - 1 List of Ordering Part Numbers (1/3) Pin count Package Fields of Application Note Ordering Part Number Renesas Code Product Name Packaging Specification 30 30-pin plastic LSSOP (7.62 mm (300), 0.65-mm pitch) C R7F100GAF3CSP, R7F100GAG3CSP , R7F100GAH3CSP, R7F100GAJ3CSP #AA0, #BA0, #UA0, #HA0 PLSP0030JB-B D R7F100GAF2DSP, R7F100GAG2DSP , R7F100GAH2DSP, R7F100GAJ2DSP 32 32-pin plastic HWQFN (5 × 5 mm, 0.5-mm pitch) C R7F100GBF3CNP , R7F100GBG3CNP, R7F100GBH3CNP, R7F100GBJ3CNP #AA0, #BA0, #UA0, #HA0 PWQN0032KE-A D R7F100GBF2DNP , R7F100GBG2DNP, R7F100GBH2DNP, R7F100GBJ2DNP 32-pin plastic LQFP (7 × 7 mm, 0.80-mm pitch) C R7F100GBF3CFP, R7F100GBG3CFP , R7F100GBH3CFP , R7F100GBJ3CFP #AA0, #BA0, #UA0, #HA0 PLQP0032GB-A, PLQP0032GE-A D R7F100GBF2DFP, R7F100GBG2DFP , R7F100GBH2DFP , R7F100GBJ2DFP 36 36-pin plastic WFLGA (4 × 4 mm, 0.50-mm pitch) C R7F100GCF3CLA, R7F100GCG3CLA, R7F100GCH3CLA, R7F100GCJ3CLA #AC0, #BC0, #UC0, #HC0 PWLG0036KB-A D R7F100GCF2DLA, R7F100GCG2DLA, R7F100GCH2DLA, R7F100GCJ2DLA 40 40-pin plastic HWQFN (6 × 6 mm, 0.50-mm pitch) C R7F100GEF3CNP , R7F100GEG3CNP, R7F100GEH3CNP, R7F100GEJ3CNP #AA0, #BA0, #UA0, #HA0 PWQN0040KD-A D R7F100GEF2DNP , R7F100GEG2DNP, R7F100GEH2DNP, R7F100GEJ2DNP 44 44-pin plastic LQFP (10 × 10 mm, 0.80-mm pitch) C R7F100GFF3CFP, R7F100GFG3CFP , R7F100GFH3CFP, R7F100GFJ3CFP , R7F100GFK3CFP, R7F100GFL3CFP , R7F100GFN3CFP #AA0, #BA0, #UA0, #HA0 PLQP0044GC-A, PLQP0044GE-A D R7F100GFF2DFP, R7F100GFG2DFP , R7F100GFH2DFP, R7F100GFJ2DFP , R7F100GFK2DFP, R7F100GFL2DFP , R7F100GFN2DFP 48 48-pin plastic LFQFP (7 × 7 mm, 0.50-mm pitch) C R7F100GGF3CFB, R7F100GGG3CFB, R7F100GGH3CFB, R7F100GGJ3CFB, R7F100GGK3CFB, R7F100GGL3CFB, R7F100GGN3CFB #AA0, #BA0, #UA0, #HA0 PLQP0048KB-B, PLQP0048KL-A D R7F100GGF2DFB, R7F100GGG2DFB, R7F100GGH2DFB, R7F100GGJ2DFB, R7F100GGK2DFB, R7F100GGL2DFB, R7F100GGN2DFB 48-pin plastic HWQFN (7 × 7 mm, 0.50-mm pitch) C R7F100GGF3CNP, R7F100GGG3CNP, R7F100GGH3CNP, R7F100GGJ3CNP , R7F100GGK3CNP, R7F100GGL3CNP , R7F100GGN3CNP #AA0, #BA0, #UA0, #HA0 PWQN0048KC-A D R7F100GGF2DNP, R7F100GGG2DNP, R7F100GGH2DNP, R7F100GGJ2DNP , R7F100GGK2DNP, R7F100GGL2DNP , R7F100GGN2DNP

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 6 of 177 Oct 31, 2025 52 52-pin plastic LQFP (10 × 10 mm, 0.65-mm pitch) C R7F100GJF3CFA, R7F100GJG3CFA, R7F100GJH3CFA, R7F100GJJ3CFA, R7F100GJK3CFA, R7F100GJL3CFA, R7F100GJN3CFA #AA0, #BA0, #UA0, #HA0 PLQP0052JA-A D R7F100GJF2DFA, R7F100GJG2DFA, R7F100GJH2DFA, R7F100GJJ2DFA, R7F100GJK2DFA, R7F100GJL2DFA, R7F100GJN2DFA 64 64-pin plastic LQFP (12 × 12 mm, 0.65-mm pitch) C R7F100GLF3CFA, R7F100GLG3CFA, R7F100GLH3CFA, R7F100GLJ3CFA, R7F100GLK3CFA, R7F100GLL3CFA, R7F100GLN3CFA #AA0, #BA0, #UA0, #HA0 PLQP0064JA-A D R7F100GLF2DFA, R7F100GLG2DFA, R7F100GLH2DFA, R7F100GLJ2DFA, R7F100GLK2DFA, R7F100GLL2DFA, R7F100GLN2DFA 64-pin plastic LFQFP (10 × 10 mm, 0.50-mm pitch) C R7F100GLF3CFB, R7F100GLG3CFB, R7F100GLH3CFB, R7F100GLJ3CFB, R7F100GLK3CFB, R7F100GLL3CFB, R7F100GLN3CFB #AA0, #BA0, #UA0, #HA0 PLQP0064KB-C, PLQP0064KL-A D R7F100GLF2DFB, R7F100GLG2DFB, R7F100GLH2DFB, R7F100GLJ2DFB, R7F100GLK2DFB, R7F100GLL2DFB, R7F100GLN2DFB 64-pin plastic WFLGA (5 × 5 mm, 0.50-mm pitch) C R7F100GLF3CLA, R7F100GLG3CLA, R7F100GLH3CLA, R7F100GLJ3CLA, R7F100GLK3CLA, R7F100GLL3CLA, R7F100GLN3CLA #AC0, #BC0, #UC0, #HC0 PWLG0064KB-A D R7F100GLF2DLA, R7F100GLG2DLA, R7F100GLH2DLA, R7F100GLJ2DLA, R7F100GLK2DLA, R7F100GLL2DLA, R7F100GLN2DLA 80 80-pin plastic LQFP (14 × 14 mm, 0.65-mm pitch) C R7F100GMG3CFA, R7F100GMH3CFA, R7F100GMJ3CFA, R7F100GMK3CFA, R7F100GML3CFA, R7F100GMN3CFA #AA0, #BA0, #UA0, #HA0 PLQP0080JA-B D R7F100GMG2DFA, R7F100GMH2DFA, R7F100GMJ2DFA, R7F100GMK2DFA, R7F100GML2DFA, R7F100GMN2DFA 80-pin plastic LFQFP (12 × 12 mm, 0.50-mm pitch) C R7F100GMG3CFB, R7F100GMH3CFB, R7F100GMJ3CFB, R7F100GMK3CFB, R7F100GML3CFB, R7F100GMN3CFB #AA0, #BA0, #UA0, #HA0 PLQP0080KB-B, PLQP0080KJ-A D R7F100GMG2DFB, R7F100GMH2DFB, R7F100GMJ2DFB, R7F100GMK2DFB, R7F100GML2DFB, R7F100GMN2DFB Table 1 - 1 List of Ordering Part Numbers (2/3) Pin count Package Fields of Application Note Ordering Part Number Renesas Code Product Name Packaging Specification <R>

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 7 of 177 Oct 31, 2025 Note For the fields of application, see Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G23. 100 100-pin plastic LFQFP (14 × 14 mm, 0.50-mm pitch) C R7F100GPG3CFB, R7F100GPH3CFB, R7F100GPJ3CFB, R7F100GPK3CFB, R7F100GPL3CFB, R7F100GPN3CFB #AA0, #BA0, #UA0, #HA0 PLQP0100KB-B D R7F100GPG2DFB, R7F100GPH2DFB, R7F100GPJ2DFB, R7F100GPK2DFB, R7F100GPL2DFB, R7F100GPN2DFB 100-pin plastic LQFP (14 × 20 mm, 0.65-mm pitch) C R7F100GPG3CFA, R7F100GPH3CFA, R7F100GPJ3CFA, R7F100GPK3CFA, R7F100GPL3CFA, R7F100GPN3CFA #AA0, #BA0, #UA0, #HA0 PLQP0100JC-A D R7F100GPG2DFA, R7F100GPH2DFA, R7F100GPJ2DFA, R7F100GPK2DFA, R7F100GPL2DFA, R7F100GPN2DFA 128 128-pin plastic LFQFP (14 × 20 mm, 0.50-mm pitch) C R7F100GSJ3CFB, R7F100GSK3CFB, R7F100GSL3CFB, R7F100GSN3CFB #AA0, #BA0, #UA0, #HA0 PLQP0128KD-A D R7F100GSJ2DFB, R7F100GSK2DFB, R7F100GSL2DFB, R7F100GSN2DFB Table 1 - 1 List of Ordering Part Numbers (3/3) Pin count Package Fields of Application Note Ordering Part Number Renesas Code Product Name Packaging Specification

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 8 of 177 Oct 31, 2025

1.3 Pin Configuration (Top View)

1.3.1 30-pin products

30-pin plastic LSSOP (7.62 mm (300), 0.65-mm pitch) Note Not present in products with 128 or fewer Kbytes of code flash memory. Caution Connect the REGC pin to V SS via a capacitor (0.47 to 1 µF). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). For details, see 4.3.10 Peripheral I/O redirection register (PIOR) in the RL78/G23 User’s Manual. P20/ANI0/AVREFP/EI20 P01/ANI16/TS27Note/EI01/EO01/TO00/RxD1 P00/ANI17/TS26Note/EI00/TI00/TxD1 P120/ANI19/IVCMP1/EI120 P40/TOOL0 RESET P137/EI137/INTP0 P122/X2/EXCLK/XT2/EXCLKS/EI122 P121/X1/XT1/EI121 REGC VSS VDD P60/EO60/CCD04/SCLA0 P61/EO61/CCD05/SDAA0 P31/TS01/EI31/TI03/TO03/INTP4/PCLBUZ0 P21/ANI1/AVREFM/EI21 P22/ANI2/ANO0/TS20Note/EI22 P23/ANI3/ANO1/IVREF0/TS21Note/EI23 P147/ANI18/IVCMP0/EI147 P10/EI10/EO10/SCK00/SCL00/(TI07)/(TO07) P11/EI11/EO11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/EI12/EO12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) P13/IVREF1/EO13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/VCOUT1/EO14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/EO15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P16/EO16/CCD00/TI01/TO01/INTP5/(RxD0) P17/EO17/CCD01/TI02/TO02/(TxD0) P51/EI51/EO51/CCD02/INTP2/SO11 P50/TS00/EI50/EO50/CCD03/INTP1/SI11/SDA11 P30/VCOUT0/TSCAP/EI30/INTP3/RTC1HZ/SCK11/SCL11 RL78/G23 (Top View)

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 9 of 177 Oct 31, 2025 Table 1 - 2 Multiplexed Pin Functions of the 30-pin Products (1/2) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 30LSSOP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) Interrupt Key interrupt Capacitive sensing unit (CTSU2L) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) Remote control signal receiver (REMC)

1 P20 — EI20 — ANI0/

2 P01 — EI01/

TO00 — RxD1 — — —

3 P 0 0 —E I 0 0 — A N I 1 7 ————T S 2 6

TI00 — TxD1 — — — 6 — — — RESET

8 P122 — EI122 X2/XT2/

1 1 ———V

15 P31 — EI31 PCLBUZ0 — — — INTP4 — TS01 TI03/

16 P30 — EI30 — — — VCOUT0 INTP3 — TSCAP — RTC1HZ SCK11/

———

17 P50 CCD03 EI50/

———

18 P51 CCD02 EI51/

19 P17 CCD01 EO17 — — — — — — TI02/

— (TxD0) — — —

20 P16 CCD00 EO16 — — — — INTP5 — — TI01/

— (RxD0) — — —

21 P15 — EO15 PCLBUZ1 — — — — — — (TI02)/

(TO02) — SCK20/ SCL20 ———

22 P14 — EO14 — — — VCOUT1 — — — (TI03)/

(TO03) — SI20/ RxD2/ SDA20 (SCLA0) — —

23 P13 — EO13 — — — IVREF1 — — — (TI04)/

(TO04) — SO20/ TxD2 (SDAA0) — —

24 P12 — EI12/

T O O L T x D ——————( T I 0 5 ) / (TO05) — SO00/ TxD0 ———

25 P11 — EI11/

T O O L R x D ——————( T I 0 6 ) / ( TO06) — SI00/ RxD0/ SDA00 ———

26 P10 — EI10/

(TO07) — SCK00/ SCL00 ———

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 10 of 177 Oct 31, 2025 Note Not present in products with 128 or fewer Kbytes of code flash memory.

28 P23 — EI23 — ANI3 ANO1 IVREF0 — — TS21

29 P22 — EI22 — ANI2 ANO0 — — — TS20

30 P21 — EI21 — ANI1/

Table 1 - 2 Multiplexed Pin Functions of the 30-pin Products (2/2) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 30LSSOP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) Interrupt Key interrupt Capacitive sensing unit (CTSU2L) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) Remote control signal receiver (REMC)

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 11 of 177 Oct 31, 2025 1.3.2 32-pin products

32-pin plastic HWQFN (5 × 5 mm, 0.50-mm pitch)
32-pin plastic LQFP (7 × 7 mm, 0.80-mm pitch) Note 1. Not present in products with 128 or fewer Kbytes of code flash memory. Note 2. The 32-pin plastic LQFP (7 × 7 mm, 0.80-mm pitch) products do not have an exposed die pad. Caution Connect the REGC pin to V SS via a capacitor (0.47 to 1 µF). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). For details, see 4.3.10 Peripheral I/O redirection register (PIOR) in the RL78/G23 User’s Manual. Remark 3. It is recommended to connect an exposed die pad to VSS. 24 23 22 21 2019 18 17 12345678 RL78/G23 (Top View) INDEX MARK P51/EI51/EO51/CCD02/INTP2/SO11 P50/TS00/EI50/EO50/CCD03/INTP1/SI11/SDA11 P30/VCOUT0/TSCAP/EI30/INTP3/RTC1HZ/SCK11/SCL11 P70/RIN0/TS02 P31/TS01/EI31/TI03/TO03/INTP4/PCLBUZ0 P62/CCD06 P61/EO61/CCD05/SDAA0 P60/EO60/CCD04/SCLA0 Exposed die pad Note 2 P10/EI10/EO10/SCK00/SCL00/(TI07)/(TO07) P11/EI11/EO11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/EI12/EO12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) P13/IVREF1/EO13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/VCOUT1/EO14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/EO15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P16/EO16/CCD00/TI01/TO01/INTP5/(RxD0) P17/EO17/CCD01/TI02/TO02/(TxD0) P40/TOOL0 RESET P137/EI137/INTP0 P122/X2/EXCLK/XT2/EXCLKS/EI122 P121/X1/XT1/EI121 REGC V SS VDD P147/ANI18/IVCMP0/EI147 P23/ANI3/ANO1/IVREF0/TS21Note 1/EI23 P22/ANI2/ANO0/TS20Note 1/EI22 P21/ANI1/AVREFM/EI21 P20/ANI0/AVREFP/EI20 P01/ANI16/TS27Note 1/EI01/EO01/TO00/RxD1 P00/ANI17/TS26Note 1/EI00/TI00/TxD1 P120/ANI19/IVCMP1/EI120

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 12 of 177 Oct 31, 2025 Table 1 - 3 Multiplexed Pin Functions of the 32-pin Products (1/2) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 32HWQFN, 32LQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) Interrupt Key interrupt Capacitive sensing unit (CTSU2L) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) Remote control signal receiver (REMC)

4 P122 — EI122 X2/XT2/

7— — — V

12 P31 — EI31 PCLBUZ0 — — — INTP4 — TS01 TI03/

14 P30 — EI30 — — — VCOUT0 INTP3 — TSCAP — RTC1HZ SCK11/

———

15 P50 CCD03 EI50/

———

16 P51 CCD02 EI51/

17 P17 CCD01 EO17 — — — — — — — TI02/

— (TxD0) — — —

18 P16 CCD00 EO16 — — — — INTP5 — — TI01/

— (RxD0) — — —

19 P15 — EO15 PCLBUZ1 — — — — — — (TI02)/

(TO02) — SCK20/ SCL20 ———

20 P14 — EO14 — — — VCOUT1 — — — (TI03)/

(TO03) — SI20/ RxD2/ SDA20 (SCLA0) — —

21 P13 — EO13 — — — IVREF1 — — — (TI04)/

(TO04) — SO20/ TxD2 (SDAA0) — —

22 P12 — EI12/

T O O L T x D ——————( T I 0 5 ) / (TO05) — SO00/ TxD0 ———

23 P11 — EI11/

T O O L R x D ——————( T I 0 6 ) / (TO06) — SI00/ RxD0/ SDA00 ———

24 P10 — EI10/

(TO07) — SCK00/ SCL00 ———

26 P23 — EI23 — ANI3 ANO1 IVREF0 — — TS21

27 P22 — EI22 — ANI2 ANO0 — — — TS20

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 13 of 177 Oct 31, 2025 Note Not present in products with 128 or fewer Kbytes of code flash memory.

28 P21 — EI21 — ANI1/

29 P20 — EI20 — ANI0/

30 P01 — EI01/

TO00 — RxD1 — — —

31 P00 — EI00 — ANI17 — — — — TS26

TI00 — TxD1 — — — Table 1 - 3 Multiplexed Pin Functions of the 32-pin Products (2/2) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 32HWQFN, 32LQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) Interrupt Key interrupt Capacitive sensing unit (CTSU2L) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) Remote control signal receiver (REMC)

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 14 of 177 Oct 31, 2025 1.3.3 36-pin products

36-pin plastic WFLGA (4 × 4 mm, 0.50-mm pitch) Note Not present in products with 128 or fewer Kbytes of code flash memory. Caution Connect the REGC pin to V SS via a capacitor (0.47 to 1 µF). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). For details, see 4.3.10 Peripheral I/O redirection register (PIOR) in the RL78/G23 User’s Manual. ABCDEF

6 P60/EO60/CCD04/

VDD P121/X1/XT1/EI121 P122/X2/EXCLK/XT2/ EXCLKS/EI122 P137/EI137/INTP0 P40/TOOL0

5 P62/CCD06 P61/EO61/CCD05/

VSS REGC RESET P120/ANI19/IVCMP1/ EI120

4 P72/TS04/SO21/

(SCLA0)/(TI03)/ (TO03) P31/TS01/EI31/TI03/ TO03/INTP4/ PCLBUZ0 P00/TS26 Note/EI00/ TI00/TxD1 P01/TS27Note/EI01/ EO01/TO00/RxD1

3 P50/TS00/EI50/EO50/

(TI02)/(TO02) P22/ANI2/ANO0/ TS20 Note/EI22 P20/ANI0/AVREFP/ EI20 P21/ANI1/AVREFM/ EI21

2 P30/VCOUT0/TSCAP/

(RxD0) P12/EI12/EO12/SO00/ TxD0/TOOLTxD/ (TI05)/(TO05) P11/EI11/EO11/SI00/ RxD0/TOOLRxD/ SDA00/(TI06)/(TO06) P24/ANI4/TS22 Note P23/ANI3/ANO1/ IVREF0/TS21Note/ EI23

1 P51/EI51/EO51/

TI02/TO02/(TxD0) P13/IVREF1/EO13/ TxD2/SO20/(SDAA0)/ (TI04)/(TO04) P10/EI10/EO10/ SCK00/SCL00/ (TI07)/(TO07) P147/ANI18/IVCMP0/ EI147 P25/ANI5/TS23 Note Top View Bottom View FEDCBAABCDEF RL78/G23 (Top View) INDEX MARK

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 15 of 177 Oct 31, 2025 Table 1 - 4 Multiplexed Pin Functions of the 36-pin Products (1/2) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 36WFLGA Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) Interrupt Key interrupt Capacitive sensing unit (CTSU2L) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) Remote control signal receiver (REMC) A1 P51 CCD02 EI51/ EO51 A2 P30 — EI30 — — — VCOUT0 INTP3 — TSCAP — RTC1HZ SCK11/ SCL11 ——— A3 P50 CCD03 EI50/ EO50 SDA11 ——— B1 P17 CCD01 EO17 — — — — — — — TI02/ TO02 — (TxD0) — — — B2 P16 CCD00 EO16 — — — — INTP5 — — TI01/ TO01 — (RxD0) — — — SCL21 — — RIN0 SDA21 — RxDA0 — B 6 ———V C1 P13 — EO13 — — — IVREF1 — — — (TI04)/ (TO04) — SO20/ TxD2 (SDAA0) — — C2 P12 — EI12/ EO12 T O O L T x D ——————( T I 0 5 ) / (TO05) — SO00/ TxD0 ——— C3 P15 — EO15 PCLBUZ1 — — — — — — (TI02)/ (TO02) — SCK20/ SCL20 ——— C4 P14 — EO14 — — — VCOUT1 — — — (TI03)/ (TO03) — SI20/ RxD2/ SDA20 (SCLA0) — — D1 P10 — EI10/ EO10 (TO07) — SCK00/ SCL00 ——— D2 P11 — EI11/ EO11 T O O L R x D ——————( T I 0 6 ) / (TO06) — SI00/ RxD0/ SDA00 ——— D3 P22 — EI22 — ANI2 ANO0 — — — TS20 Note D4 P31 — EI31 PCLBUZ0 — — — INTP4 — TS01 TI03/ TO03 D6 P122 — EI122 X2/XT2/ EXCLK/ EXCLKS Note

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 16 of 177 Oct 31, 2025 Note Not present in products with 128 or fewer Kbytes of code flash memory. E3 P20 — EI20 — ANI0/ AVREFP Note TI00 — TxD1 — — — Note F2 P23 — EI23 — ANI3 ANO1 IVREF0 — — TS21 Note F3 P21 — EI21 — ANI1/ AVREFM F4 P01 — EI01/ EO01 Note TO00 — RxD1 — — — Table 1 - 4 Multiplexed Pin Functions of the 36-pin Products (2/2) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 36WFLGA Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) Interrupt Key interrupt Capacitive sensing unit (CTSU2L) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) Remote control signal receiver (REMC)

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 17 of 177 Oct 31, 2025 1.3.4 40-pin products

40-pin plastic HWQFN (6 × 6 mm, 0.50-mm pitch) Note Not present in products with 128 or fewer Kbytes of code flash memory. Caution Connect the REGC pin to V SS via a capacitor (0.47 to 1 µF). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). For details, see 4.3.10 Peripheral I/O redirection register (PIOR) in the RL78/G23 User’s Manual. Remark 3. It is recommended to connect an exposed die pad to VSS. 123456789 1 0 30 29 28 27 26 25 24 23 22 21 P50/TS00/EI50/EO50/CCD03/INTP1/SI11/SDA11 P30/VCOUT0/TSCAP/EI30/INTP3/RTC1HZ/SCK11/SCL11 P70/TS02/RIN0/KR0/SCK21/SCL21 P71/TS03/KR1/SI21/SDA21/RxDA0 P72/TS04/KR2/SO21/TxDA0 P73/TS05/KR3 P31/TS01/EI31/TI03/TO03/INTP4/PCLBUZ0 P62/CCD06 P61/EO61/CCD05/SDAA0 P60/EO60/CCD04/SCLA0 P147/ANI18/IVCMP0/EI147 P10/EI10/EO10/SCK00/SCL00/(TI07)/(TO07) P11/EI11/EO11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/EI12/EO12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) P13/IVREF1/EO13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/VCOUT1/EO14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/EO15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P16/EO16/CCD00/TI01/TO01/INTP5/(RxD0) P17/EO17/CCD01/TI02/TO02/(TxD0) P51/EI51/EO51/CCD02/INTP2/SO11 RL78/G23 (Top View) INDEX MARK P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/EI137/INTP0 P122/X2/EXCLK/EI122 P121/X1/VBAT/EI121 REGC VSS VDD P26/ANI6/TS24Note P25/ANI5/TS23Note P24/ANI4/TS22Note P23/ANI3/ANO1/IVREF0/TS21Note/EI23 P22/ANI2/ANO0/TS20Note/EI22 P21/ANI1/AVREFM/EI21 P20/ANI0/AVREFP/EI20 P01/TS27Note/EI01/EO01/TO00/RxD1 P00/TS26Note/EI00/TI00/TxD1 P120/ANI19/IVCMP1/EI120 Exposed die pad

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 18 of 177 Oct 31, 2025 Table 1 - 5 Multiplexed Pin Functions of the 40-pin Products (1/2) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 40HWQFN Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) Interrupt Key interrupt Capacitive sensing unit (CTSU2L) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) Remote control signal receiver (REMC) 3P 1 2 4 — — X T 2 / EXCLKS 9— — — V

14 P31 — EI31 PCLBUZ0 — — — INTP4 — TS01 TI03/

— RxDA0 — SCL21 — — RIN0

19 P30 — EI30 — — — VCOUT0 INTP3 — TSCAP — RTC1HZ SCK11/

———

20 P50 CCD03 EI50/

———

21 P51 CCD02 EI51/

22 P17 CCD01 EO17 — — — — — — — TI02/

— (TxD0) — — —

23 P16 CCD00 EO16 — — — — INTP5 — — TI01/

— (RxD0) — — —

24 P15 — EO15 PCLBUZ1 — — — — — — (TI02)/

(TO02) — SCK20/ SCL20 ———

25 P14 — EO14 — — — VCOUT1 — — — (TI03)/

(TO03) — SI20/ xD2/ SDA20 (SCLA0) — —

26 P13 — EO13 — — — IVREF1 — — — (TI04)/

(TO04) — SO20/ TxD2 (SDAA0) — —

27 P12 — EI12/

T O O L T x D ——————( T I 0 5 ) / (TO05) — SO00/ TxD0 ———

28 P11 — EI11/

T O O L R x D ——————( T I 0 6 ) / (TO06) — SI00/ RxD0/ SDA00 ———

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 19 of 177 Oct 31, 2025 Note Not present in products with 128 or fewer Kbytes of code flash memory.

29 P10 — EI10/

(TO07) — SCK00/ SCL00 ——— Note Note Note

34 P23 — EI23 — ANI3 ANO1 IVREF0 — — TS21

35 P22 — EI22 — ANI2 ANO0 — — — TS20

36 P21 — EI21 — ANI1/

37 P20 — EI20 — ANI0/

38 P01 — EI01/

TO00 — RxD1 — — — Note TI00 — TxD1 — — — Table 1 - 5 Multiplexed Pin Functions of the 40-pin Products (2/2) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 40HWQFN Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) Interrupt Key interrupt Capacitive sensing unit (CTSU2L) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) Remote control signal receiver (REMC)

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 20 of 177 Oct 31, 2025 1.3.5 44-pin products

44-pin plastic LQFP (10 × 10 mm, 0.80-mm pitch) Note Not present in products with 128 or fewer Kbytes of code flash memory. Caution Connect the REGC pin to V SS via a capacitor (0.47 to 1 µF). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). For details, see 4.3.10 Peripheral I/O redirection register (PIOR) in the RL78/G23 User’s Manual. 33 32 31 30 29 28 27 26 25 24 23 P147/ANI18/IVCMP0/EI147 P146 P10/EI10/EO10/SCK00/SCL00/(TI07)/(TO07) P11/EI11/EO11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/EI12/EO12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) P13/IVREF1/EO13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/VCOUT1/EO14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/EO15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P16/EO16/CCD00/TI01/TO01/INTP5/(RxD0) P17/EO17/CCD01/TI02/TO02/(TxD0) P51/EI51/EO51/CCD02/INTP2/SO11 P50/TS00/EI50/EO50/INTP1/SI11/SDA11 P30/VCOUT0/TSCAP/EI30/INTP3/RTC1HZ/SCK11/SCL11 P70/TS02/RIN0/KR0/SCK21/SCL21 P71/TS03/KR1/SI21/SDA21/RxDA0 P72/TS04/KR2/SO21/TxDA0 P73/TS05/KR3 P31/TS01/EI31/TI03/TO03/INTP4/PCLBUZ0 P63/CCD07/SDAA1 P62/CCD06/SCLA1 P61/EO61/CCD05/SDAA0 P60/EO60/CCD04/SCLA0 RL78/G23 (Top View) P41/RxDA1/TI07/TO07 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/EI137/INTP0 P122/X2/EXCLK/EI122 P121/X1/VBAT/EI121 REGC VSS VDD P27/ANI7/TS25Note P26/ANI6/TS24Note P25/ANI5/TS23Note P24/ANI4/TS22Note P120/ANI19/IVCMP1/TxDA1/EI120 P00/TS26Note/EI00/TI00/TxD1 P01/TS27Note/EI01/EO01/TO00/RxD1 P20/ANI0/AVREFP/EI20 P21/ANI1/AVREFM/EI21 P22/ANI2/ANO0/TS20Note/EI22 P23/ANI3/ANO1/IVREF0/TS21Note/EI23 23456789 1 0 1 1

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 21 of 177 Oct 31, 2025 Table 1 - 6 Multiplexed Pin Functions of the 44-pin Products (1/2) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 44LQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) Interrupt Key interrupt Capacitive sensing unit (CTSU2L) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) Remote control signal receiver (REMC) TO07 ———R x D A 1 — 4P 1 2 4 — — X T 2 / EXCLKS 1 0 ———V

16 P31 — EI31 PCLBUZ0 — — — INTP4 — TS01 TI03/

— RxDA0 — SCL21 — — RIN0

21 P30 — EI30 — — — VCOUT0 INTP3 — TSCAP — RTC1HZ SCK11/

———

22 P50 — EI50/

———

23 P51 CCD02 EI51/

24 P17 CCD01 EO17 — — — — — — TI02/

— (TxD0) — — —

25 P16 CCD00 EO16 — — — — INTP5 — — TI01/

— (RxD0) — — —

26 P15 — EO15 PCLBUZ1 — — — — — — (TI02)/

(TO02) — SCK20/ SCL20 ———

27 P14 — EO14 — — — VCOUT1 — — — (TI03)/

(TO03) — SI20/ RxD2/ SDA20 (SCLA0) — —

28 P13 — EO13 — — — IVREF1 — — — (TI04)/

(TO04) — SO20/ TxD2 (SDAA0) — —

29 P12 — EI12/

T O O L T x D ——————( T I 0 5 ) / (TO05) — SO00/ TxD0 ———

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 22 of 177 Oct 31, 2025 Note Not present in products with 128 or fewer Kbytes of code flash memory.

30 P11 — EI11/

T O O L R x D ——————( T I 0 6 ) / (TO06) — SI00/ RxD0/ SDA00 ———

31 P10 — EI10/

(TO07) — SCK00/ SCL00 ——— Note Note Note Note

38 P23 — EI23 — ANI3 ANO1 IVREF0 — — TS21

39 P22 — EI22 — ANI2 ANO0 — — — TS20

40 P21 — EI21 — ANI1/

41 P20 — EI20 — ANI0/

42 P01 — EI01/

TO00 — RxD1 — — — Note TI00 — TxD1 — — — 4 4 P 1 2 0 —E I 1 2 0 — A N I 1 9 —I V C M P 1 ———————T x D A 1 — Table 1 - 6 Multiplexed Pin Functions of the 44-pin Products (2/2) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 44LQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) Interrupt Key interrupt Capacitive sensing unit (CTSU2L) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) Remote control signal receiver (REMC)

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 23 of 177 Oct 31, 2025 1.3.6 48-pin products

48-pin plastic LFQFP (7 × 7 mm, 0.50-mm pitch)
48-pin plastic HWQFN (7 × 7 mm, 0.50-mm pitch) Note 1. Not present in products with 128 or fewer Kbytes of code flash memory. Note 2. The 48-pin plastic LFQFP (7 × 7 mm, 0.50-mm pitch) products do not have an exposed die pad. Caution Connect the REGC pin to V SS via a capacitor (0.47 to 1 µF). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). For details, see 4.3.10 Peripheral I/O redirection register (PIOR) in the RL78/G23 User’s Manual. Remark 3. It is recommended to connect an exposed die pad to VSS. 36 35 34 33 32 31 30 29 28 27 26 25 RL78/G23 (Top View) P147/ANI18/IVCMP0/EI147 P146 P10/EI10/EO10/SCK00/SCL00/(TI07)/(TO07) P11/EI11/EO11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/EI12/EO12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) P13/IVREF1/EO13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/VCOUT1/EO14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/EO15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P16/EO16/CCD00/TI01/TO01/INTP5/(RxD0) P17/EO17/CCD01/TI02/TO02/(TxD0) P51/EI51/EO51/CCD02/INTP2/SO11 P50/TS00/EI50/EO50/CCD03/INTP1/SI11/SDA11 P60/EO60/CCD04/SCLA0 P61/EO61/CCD05/SDAA0 P62/CCD06/SCLA1 P63/CCD07/SDAA1 P31/TS01/EI31/TI03/TO03/INTP4/(PCLBUZ0) P75/TS07/KR5/INTP9/SCK01/SCL01 P74/TS06/KR4/INTP8/SI01/SDA01 P73/TS05/KR3/SO01 P72/TS04/KR2/SO21/TxDA0 P71/TS03/KR1/SI21/SDA21/RxDA0 P70/TS02/RIN0/KR0/SCK21/SCL21 P30/VCOUT0/TSCAP/EI30/INTP3/RTC1HZ/SCK11/SCL11 P140/PCLBUZ0/INTP6 P00/TS26Note 1/EI00/TI00/TxD1 P01/TS27Note 1/EI01/EO01/TO00/RxD1 P130 P20/ANI0/AVREFP/EI20 P21/ANI1/AVREFM/EI21 P22/ANI2/ANO0/TS20Note 1/EI22 P23/ANI3/ANO1/IVREF0/TS21Note 1/EI23 P24/ANI4/TS22Note 1 P25/ANI5/TS23Note 1 P26/ANI6/TS24Note 1 P27/ANI7/TS25Note 1 P120/ANI19/IVCMP1/TxDA1/EI120 P41/RxDA1/TI07/TO07 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/EI137/INTP0 P122/X2/EXCLK/EI122 P121/X1/VBAT/EI121 REGC VSS VDD Exposed die padNote 2 23456789 1 0 1 1 1 2

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 24 of 177 Oct 31, 2025 Table 1 - 7 Multiplexed Pin Functions of the 48-pin Products (1/2) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 48LFQFP, 48HWQFN Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) Interrupt Key interrupt Capacitive sensing unit (CTSU2L) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) Remote control signal receiver (REMC)

5 P31 — EI31 (PCLBUZ0) — — — INTP4 — TS01 TI03/

6 P75 — — — — — — INTP9 KR5 TS07 — — SCK01/

———

7 P74 — — — — — — INTP8 KR4 TS06 — — SI01/

——— SDA21 — RxDA0 — SCL21 — — RIN0

12 P30 — EI30 — — — VCOUT0 INTP3 — TSCAP — RTC1HZ SCK11/

———

13 P50 CCD03 EI50/

———

14 P51 CCD02 EI51/

15 P17 CCD01 EO17 — — — — — — — TI02/

— (TxD0) — — —

16 P16 CCD00 EO16 — — — — INTP5 — — TI01/

— (RxD0) — — —

17 P15 — EO15 PCLBUZ1 — — — — — — (TI02)/

(TO02) — SCK20/ SCL20 ———

18 P14 — EO14 — — — VCOUT1 — — — (TI03)/

(TO03) — SI20/ RxD2/ SDA20 (SCLA0) — —

19 P13 — EO13 — — — IVREF1 — — — (TI04)/

(TO04) — SO20/ TxD2 (SDAA0) — —

20 P12 — EI12/

T O O L T x D ——————( T I 0 5 ) / (TO05) — SO00/ TxD0 ———

21 P11 — EI11/

T O O L R x D ——————( T I 0 6 ) / (TO06) — SI00/ RxD0/ SDA00 ———

22 P10 — EI10/

(TO07) — SCK00/ SCL00 ——— Note Note

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 25 of 177 Oct 31, 2025 Note Not present in products with 128 or fewer Kbytes of code flash memory. Note Note

29 P23 — EI23 — ANI3 ANO1 IVREF0 — — TS21

30 P22 — EI22 — ANI2 ANO0 — — — TS20

31 P21 — EI21 — ANI1/

32 P20 — EI20 — ANI0/

34 P01 — EI01/

TO00 — RxD1 — — — Note TI00 — TxD1 — — — 3 7 P 1 2 0 —E I 1 2 0 — A N I 1 9 —I V C M P 1 ———————T x D A 1 — TO07 ———R x D A 1 — 40 — — — RESET

41 P124 — — XT2/

4 7 ———V Table 1 - 7 Multiplexed Pin Functions of the 48-pin Products (2/2) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 48LFQFP, 48HWQFN Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) Interrupt Key interrupt Capacitive sensing unit (CTSU2L) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) Remote control signal receiver (REMC)

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 26 of 177 Oct 31, 2025 1.3.7 52-pin products

52-pin plastic LQFP (10 × 10 mm, 0.65-mm pitch) Note Not present in products with 128 or fewer Kbytes of code flash memory. Caution Connect the REGC pin to V SS via a capacitor (0.47 to 1 µF). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). For details, see 4.3.10 Peripheral I/O redirection register (PIOR) in the RL78/G23 User’s Manual. RL78/G23 (Top View) P147/ANI18/IVCMP0/EI147 P146 P10/EI10/EO10/SCK00/SCL00/(TI07)/(TO07) P11/EI11/EO11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/EI12/EO12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) P13/IVREF1/EO13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/VCOUT1/EO14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/EO15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P16/EO16/CCD00/TI01/TO01/INTP5/(RxD0) P17/EO17/CCD01/TI02/TO02/(TxD0) P51/EI51/EO51/CCD02/INTP2/SO11 P50/TS00/EI50/EO50/CCD03/INTP1/SI11/SDA11 P30/VCOUT0/TSCAP/EI30/INTP3/RTC1HZ/SCK11/SCL11 P70/TS02/RIN0/KR0/SCK21/SCL21 P71/TS03/KR1/SI21/SDA21/RxDA0 P72/TS04/KR2/SO21/TxDA0 P73/TS05/KR3/SO01 P74/TS06/KR4/INTP8/SI01/SDA01 P75/TS07/KR5/INTP9/SCK01/SCL01 P76/TS08/KR6/INTP10/(RxD2) P77/TS09/KR7/INTP11/(TxD2) P31/TS01/EI31/TI03/TO03/INTP4/(PCLBUZ0) P63/CCD07/SDAA1 P62/CCD06/SCLA1 P61/EO61/CCD05/SDAA0 P60/EO60/CCD04/SCLA0 P140/PCLBUZ0/INTP6 P120/ANI19/IVCMP1/TxDA1/EI120 P41/RxDA1/TI07/TO07 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/EI137/INTP0 P122/X2/EXCLK/EI122 P121/X1/VBAT/EI121 REGC VSS VDD P27/ANI7/TS25Note P00/TS26Note/EI00/TI00 P01/TS27Note/EI01/EO01/TO00 P02/ANI17/TS28Note/TxD1 P03/ANI16/TS29Note/RxD1 P130 P20/ANI0/AVREFP/EI20 P21/ANI1/AVREFM/EI21 P22/ANI2/ANO0/TS20Note/EI22 P23/ANI3/ANO1/IVREF0/TS21Note/EI23 P24/ANI4/TS22Note P25/ANI5/TS23Note P26/ANI6/TS24Note 38 37 36 35 34 33 32 31 30 29 28 27 23456789 1 0 1 1 1 2 1 3

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 27 of 177 Oct 31, 2025 Table 1 - 8 Multiplexed Pin Functions of the 52-pin Products (1/2) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 52LFQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) Interrupt Key interrupt Capacitive sensing unit (CTSU2L) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) Remote control signal receiver (REMC) TO07 ———R x D A 1 — 5 — — — RESET 6P 1 2 4 — — X T 2 / EXCLKS 1 2 ———V

18 P31 — EI31 (PCLBUZ0) — — — INTP4 — TS01 TI03/

1 9 P 7 7 ——— ———I N T P 1 1 K R 7 T S 0 9 ——( T x D 2 ) ——— 2 0 P 7 6 ——— ———I N T P 1 0 K R 6 T S 0 8 ——( R x D 2 ) ———

21 P75 — — — — — — INTP9 KR5 TS07 — — SCK01/

———

22 P74 — — — — — — INTP8 KR4 TS06 — — SI01/

——— SDA21 — RxDA0 — SCL21 — — RIN0

27 P30 — EI30 — — — VCOUT0 INTP3 — TSCAP — RTC1HZ SCK11/

———

28 P50 CCD03 EI50/

———

29 P51 CCD02 EI51/

30 P17 CCD01 EO17 — — — — — — — TI02/

— (TxD0) — — —

31 P16 CCD00 EO16 — — — — INTP5 — — TI01/

— (RxD0) — — —

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 28 of 177 Oct 31, 2025 Note Not present in products with 128 or fewer Kbytes of code flash memory.

32 P15 — EO15 PCLBUZ1 — — — — — — (TI02)/

(TO02) — SCK20/ SCL20 ———

33 P14 — EO14 — — — VCOUT1 — — — (TI03)/

(TO03) — SI20/ RxD2/ SDA20 (SCLA0) — —

34 P13 — EO13 — — — IVREF1 — — — (TI04)/

(TO04) — SO20/ TxD2 (SDAA0) — —

35 P12 — EI12/

T O O L T x D ——————( T I 0 5 ) / (TO05) — SO00/ TxD0 ———

36 P11 — EI11/

T O O L R x D ——————( T I 0 6 ) / (TO06) — SI00/ RxD0/ SDA00 ———

37 P10 — EI10/

(TO07) — SCK00/ SCL00 ——— Note Note Note Note

44 P23 — EI23 — ANI3 ANO1 IVREF0 — — TS21

45 P22 — EI22 — ANI2 ANO0 — — — TS20

46 P21 — EI21 — ANI1/

47 P20 — EI20 — ANI0/

51 P01 — EI01/

Table 1 - 8 Multiplexed Pin Functions of the 52-pin Products (2/2) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 52LFQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) Interrupt Key interrupt Capacitive sensing unit (CTSU2L) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) Remote control signal receiver (REMC)

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 29 of 177 Oct 31, 2025 1.3.8 64-pin products

64-pin plastic LQFP (12 × 12 mm, 0.65-mm pitch)
64-pin plastic LFQFP (10 × 10 mm, 0.50-mm pitch) Note Not present in products with 128 or fewer Kbytes of code flash memory. Caution 1. Connect the EV SS0 pin to the same ground as the VSS pin. Caution 2. Make sure that the voltage on the V DD pin is no less than that on the EVDD0 pin. Caution 3. Connect the REGC pin to V SS via a capacitor (0.47 to 1 µF). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the VDD and EVDD0 pins and connect the VSS and EVSS0 pins to separate ground lines. Remark 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). For details, see 4.3.10 Peripheral I/O redirection register (PIOR) in the RL78/G23 User’s Manual. RL78/G23 (Top View) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P27/ANI7/TS25Note P26/ANI6/TS24Note P25/ANI5/TS23Note P24/ANI4/TS22Note P23/ANI3/ANO1/IVREF0/TS21Note/EI23 P22/ANI2/ANO0/TS20Note/EI22 P21/ANI1/AVREFM/EI21 P20/ANI0/AVREFP/EI20 P130 P04/SCK10/SCL10 P03/ANI16/TS29Note/SI10/RxD1/SDA10 P02/ANI17/TS28Note/SO10/TxD1 P01/TS27Note/EI01/EO01/TO00 P00/TS26Note/EI00/TI00 P141/PCLBUZ1/INTP7 P140/PCLBUZ0/INTP6 P30/VCOUT0/TSCAP/EI30/INTP3/RTC1HZ/SCK11/SCL11 P05/TS10/TI05/TO05 P06/TS11/TI06/TO06/CLKA0 P70/TS02/RIN0/KR0/SCK21/SCL21 P71/TS03/KR1/SI21/SDA21/RxDA0 P72/TS04/KR2/SO21/TxDA0 P73/TS05/KR3/SO01 P74/TS06/KR4/INTP8/SI01/SDA01 P75/TS07/KR5/INTP9/SCK01/SCL01 P76/TS08/KR6/INTP10/(RxD2) P77/TS09/KR7/INTP11/(TxD2) P31/TS01/EI31/TI03/TO03/INTP4/(PCLBUZ0) P63/CCD07/SDAA1 P62/CCD06/SCLA1 P61/EO61/CCD05/SDAA0 P60/EO60/CCD04/SCLA0 P147/ANI18/IVCMP0/EI147 P146 P10/EI10/EO10/SCK00/SCL00/(TI07)/(TO07) P11/EI11/EO11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/EI12/EO12/SO00/TxD0/TOOLTxD/(INTP5)/(TI05)/(TO05) P13/IVREF1/EO13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/VCOUT1/EO14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/EO15/SCK20/SCL20/(TI02)/(TO02) P16/EO16/CCD00/TI01/TO01/INTP5/(SI00)/(RxD0) P17/EO17/CCD01/TI02/TO02/(SO00)/(TxD0) P55/(PCLBUZ1)/(SCK00) P54 P53/(INTP11) P52/(INTP10) P51/EI51/EO51/CCD02/INTP2/SO11 P50/TS00/EI50/EO50/CCD03/INTP1/SI11/SDA11 P120/ANI19/IVCMP1/EI120 P43/CLKA1 P42/TxDA1/TI04/TO04 P41/RxDA1/TI07/TO07 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/EI137/INTP0 P122/X2/EXCLK/EI122 P121/X1/VBAT/EI121 REGC VSS EVSS0 VDD EVDD0 12 13 14 15 161123456789 1 0

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 30 of 177 Oct 31, 2025 Table 1 - 9 Multiplexed Pin Functions of the 64-pin Products (1/3) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 64LFQFP, 64LQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) Interrupt Key interrupt Capacitive sensing unit (CTSU2L) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) Remote control signal receiver (REMC) TO04 ———T x D A 1 — TO07 ———R x D A 1 — 6 — — — RESET 7P 1 2 4 — — X T 2 / EXCLKS 1 3 ———V

21 P31 — EI31 (PCLBUZ0) — — — INTP4 — TS01 TI03/

2 2 P 7 7 ——— ———I N T P 1 1 K R 7 T S 0 9 ——( T x D 2 ) ——— 2 3 P 7 6 ——— ———I N T P 1 0 K R 6 T S 0 8 ——( R x D 2 ) ———

24 P75 — — — — — — INTP9 KR5 TS07 — — SCK01/

———

25 P74 — — — — — — INTP8 KR4 TS06 — — SI01/

——— SDA21 — RxDA0 — SCL21 — — RIN0 TO06 ———C L K A 0 — TO05

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 31 of 177 Oct 31, 2025

32 P30 — EI30 — — — VCOUT0 INTP3 — TSCAP — RTC1HZ SCK11/

———

33 P50 CCD03 EI50/

———

34 P51 CCD02 EI51/

39 P17 CCD01 EO17 — — — — — — — TI02/

— (SO00)/ (TxD0) ———

40 P16 CCD00 EO16 — — — — INTP5 — — TI01/

— (SI00)/ (RxD0) ——— (TO02) — SCK20/ SCL20 ———

42 P14 — EO14 — — — VCOUT1 — — — (TI03)/

(TO03) — SI20/ RxD2/ SDA20 (SCLA0) — —

43 P13 — EO13 — — — IVREF1 — — — (TI04)/

(TO04) — SO20/ TxD2 (SDAA0) — —

44 P12 — EI12/

TOOLTxD — — — (INTP5) — — (TI05)/ (TO05) — SO00/ TxD0 ———

45 P11 — EI11/

T O O L R x D ——————( T I 0 6 ) / (TO06) — SI00/ RxD0/ SDA00 ———

46 P10 — EI10/

(TO07) — SCK00/ SCL00 ——— Note Note Note Note

53 P23 — EI23 — ANI3 ANO1 IVREF0 — — TS21

54 P22 — EI22 — ANI2 ANO0 — — — TS20

55 P21 — EI21 — ANI1/

56 P20 — EI20 — ANI0/

Table 1 - 9 Multiplexed Pin Functions of the 64-pin Products (2/3) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 64LFQFP, 64LQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) Interrupt Key interrupt Capacitive sensing unit (CTSU2L) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) Remote control signal receiver (REMC)

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 32 of 177 Oct 31, 2025 Note Not present in products with 128 or fewer Kbytes of code flash memory. SCL10 ——— Note — — SI10/ RxD1/ SDA10 ——— Note — — SO10/ TxD1 ———

61 P01 — EI01/

Table 1 - 9 Multiplexed Pin Functions of the 64-pin Products (3/3) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 64LFQFP, 64LQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) Interrupt Key interrupt Capacitive sensing unit (CTSU2L) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) Remote control signal receiver (REMC)

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 33 of 177 Oct 31, 2025

64-pin plastic WFLGA (5 × 5 mm, 0.50-mm pitch) Note Not present in products with 128 or fewer Kbytes of code flash memory. (Cautions and Remarks are listed on the next page.) ABCDEFGH

8 EVDD0 EVSS0 P121/X1/EI121/

7 P60/CCD04/

V DD VSS REGC RESET P01/TS27Note/ EI01/EO01/ TO00 P00/TS26 Note/ EI00/TI00 P140/PCLBUZ0/ INTP6

6 P61/CCD05/

5 P77/KR7/TS09/

INTP11/(TxD2) P31/TI03/TO03/ INTP4/TS01/ EI31/(PCLBUZ0) P53/(INTP11) P42/TI04/TO04/ TxDA1 P03/ANI16/ TS29 Note/ SI10/RxD1/ SDA10 P04/SCK10/ SCL10 P130 P20/ANI0/ AV REFP/EI20

4 P75/KR5/TS07/

INTP10/(RxD2) P52/(INTP10) P54 P16/CCD00/ TI01/TO01/ INTP5/EO16/ (SI00)/(RxD0) P21/ANI1/ AV REFM/EI21 P22/ANI2/ANO0/ EI22/TS20Note P23/ANI3/ANO1/ IVREF0/EI23/ TS21Note

3 P70/KR0/TS02/

EO17/(SO00)/ (TxD0) P15/SCK20/ SCL20/EO15/ (TI02)/(TO02) P12/SO00/TxD0/ TOOLTxD/EI12/ EO12/(INTP5)/ (TI05)/(TO05) P24/ANI4/ TS22 Note P26/ANI6/ TS24 Note

2 P30/INTP3/

(SCLA0)/(TI03)/ (TO03) P11/SI00/RxD0/ TOOLRxD/ SDA00/EI11/ EO11/(TI06)/ (TO06) P25/ANI5/ TS23 Note P27/ANI7/ TS25 Note

1 P05/TS10/TI05/

P55/(PCLBUZ1)/ (SCK00) P13/TxD2/SO20/ IVREF1/EO13/ (SDAA0)/(TI04)/ (TO04) P10/SCK00/ SCL00/EI10/ EO10/(TI07)/ (TO07) P146 P147/ANI18/ EI147/IVCMP0 HGFEDCBA RL78/G23 (Top View) A B CDE F GH Top View Bottom View Index mark

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 34 of 177 Oct 31, 2025 Caution 1. Connect the EV SS0 pin to the same ground as the VSS pin. Caution 2. Make sure that the voltage on the V DD pin is no less than that on the EVDD0 pin. Caution 3. Connect the REGC pin to V SS via a capacitor (0.47 to 1 µF). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the VDD and EVDD0 pins and connect the VSS and EVSS0 pins to separate ground lines. Remark 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). For details, see 4.3.10 Peripheral I/O redirection register (PIOR) in the RL78/G23 User’s Manual.

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 35 of 177 Oct 31, 2025 Table 1 - 10 Multiplexed Pin Functions 2 of the 64-pin Products (1/3) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 64WFLGA Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) Interrupt Key interrupt Capacitive sensing unit (CTSU2L) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) Remote control signal receiver (REMC) TO05 A2 P30 — EI30 — — — VCOUT0 INTP3 — TSCAP — RTC1HZ SCK11/ SCL11 ——— SCL21 — — RIN0 A4 P75 — — — — — — INTP9 KR5 TS07 — — SCK01/ SCL01 ——— A 5 P 7 7 ——— ———I N T P 1 1 K R 7 T S 0 9 ——( T x D 2 ) ——— A 8 ———E V B1 P50 CCD03 EI50/ EO50 SDA11 ——— B5 P31 — EI31 (PCLBUZ0) — — — INTP4 — TS01 TI03/ TO03 B 7 ———V C1 P51 CCD02 EI51/ EO51 SDA21 — RxDA0 — C3 P74 — — — — — — INTP8 KR4 TS06 — — SI01/ SDA01 ——— C 7 ———V TO06 ———C L K A 0 — D3 P17 CCD01 EO17 — — — — — — — TI02/ TO02 — (SO00)/ (TxD0) ——— TO04 ———T x D A 1 —

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 36 of 177 Oct 31, 2025 E1 P13 — EO13 — — — IVREF1 — — — (TI04)/ (TO04) — SO20/ TxD2 (SDAA0) — — E2 P14 — EO14 — — — VCOUT1 — — — (TI03)/ (TO03) — SI20/ RxD2/ SDA20 (SCLA0) — — (TO02) — SCK20/ SCL20 ——— E4 P16 CCD00 EO16 — — — — INTP5 — — TI01/ TO01 — (SI00)/ (RxD0) ——— Note — — SI10/ RxD1/ SDA10 ——— TO07 ———R x D A 1 — E7 — — — RESET F1 P10 — EI10/ EO10 (TO07) — SCK00/ SCL00 ——— F2 P11 — EI11/ EO11 T O O L R x D ——————( T I 0 6 ) / (TO06) — SI00/ RxD0/ SDA00 ——— F3 P12 — EI12/ EO12 TOOLTxD — — — (INTP5) — — (TI05)/ (TO05) — SO00/ TxD0 ——— F4 P21 — EI21 — ANI1/ AV REFM SCL10 ——— F7 P01 — EI01/ EO01 Note Note Note G4 P22 — EI22 — ANI2 ANO0 — — — TS20 Note Note — — SO10/ TxD1 ——— Note G8 P124 — — XT2/ EXCLKS Table 1 - 10 Multiplexed Pin Functions 2 of the 64-pin Products (2/3) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 64WFLGA Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) Interrupt Key interrupt Capacitive sensing unit (CTSU2L) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) Remote control signal receiver (REMC)

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 37 of 177 Oct 31, 2025 Note Not present in products with 128 or fewer Kbytes of code flash memory. Note Note H4 P23 — EI23 — ANI3 ANO1 IVREF0 — — TS21 Note H5 P20 — EI20 — ANI0/ AVREFP Table 1 - 10 Multiplexed Pin Functions 2 of the 64-pin Products (3/3) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 64WFLGA Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) Interrupt Key interrupt Capacitive sensing unit (CTSU2L) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) Remote control signal receiver (REMC)

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 38 of 177 Oct 31, 2025 1.3.9 80-pin products

80-pin plastic LQFP (14 × 14 mm, 0.65-mm pitch)
80-pin plastic LFQFP (12 × 12 mm, 0.50-mm pitch) Caution 1. Connect the EV SS0 pin to the same ground as the VSS pin. Caution 2. Make sure that the voltage on the V DD pin is no less than that on the EVDD0 pin. Caution 3. Connect the REGC pin to V SS via a capacitor (0.47 to 1 µF). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the VDD and EVDD0 pins and connect the VSS and EVSS0 pins to separate ground lines. Remark 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). For details, see 4.3.10 Peripheral I/O redirection register (PIOR) in the RL78/G23 User’s Manual. P153/ANI11/TS33 P100/ANI20 P147/ANI18/EI147/IVCMP0 P146 P111/(INTP11) P110/(INTP10) P10/SCK00/SCL00/EI10/EO10/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/EI11/EO11/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/EI12/EO12/(INTP5)/(TI05)/(TO05) P13/TxD2/SO20/IVREF1/EO13/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/VCOUT1/EO14/(SCLA0)/(TI03)/(TO03) P15/SCK20/SCL20/EO15/(TI02)/(TO02) P16/CCD00/TI01/TO01/INTP5/EO16/(SI00)/(RxD0) P17/CCD01/TI02/TO02/EO17/(SO00)/(TxD0) P55/(PCLBUZ1)/(SCK00) P54/SCK31/SCL31 P53/SI31/SDA31 P52/SO31 P51/CCD02/EI51/EO51/INTP2/SO11 P50/CCD03/TS00/EI50/EO50/INTP1/SI11/SDA11 RL78/G23 (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P30/INTP3/TSCAP/RTC1HZ/EI30/VCOUT0/SCK11/SCL11 P05/TS10/TI05/TO05 P06/TS11/TI06/TO06/CLKA0 P70/KR0/TS02/RIN0/SCK21/SCL21 P71/KR1/TS03/SI21/SDA21/RxDA0 P72/KR2/TS04/SO21/TxDA0 P73/KR3/TS05 P74/KR4/TS06/INTP8 P75/KR5/TS07/INTP9 P76/KR6/TS08/INTP10/(RxD2) P77/KR7/TS09/INTP11/(TxD2) P67/TI13/TO13/TS15 P66/TI12/TO12/TS14 P65/TI11/TO11/TS13 P64/TI10/TO10/TS12 P31/TI03/TO03/INTP4/TS01/EI31/(PCLBUZ0) P63/CCD07/SDAA1 P62/CCD06/SCLA1 P61/CCD05/SDAA0/EO61 P60/CCD04/SCLA0/EO60 P141/PCLBUZ1/INTP7 P140/PCLBUZ0/INTP6 P120/ANI19/IVCMP1/EI120 P45/SO01 P44/SI01/SDA01 P43/SCK01/SCL01/CLKA1 P42/TI04/TO04/TxDA1 P41/TI07/TO07/RxDA1 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0/EI137 P122/X2/EXCLK/EI122 P121/X1/EI121/VBAT REGC VSS EVSS0 VDD EVDD0 P152/ANI10/TS32 P151/ANI9/TS31 P150/ANI8/TS30 P27/ANI7/TS25 P26/ANI6/TS24 P25/ANI5/TS23 P24/ANI4/TS22 P23/ANI3/ANO1/IVREF0/EI23/TS21 P22/ANI2/ANO0/EI22/TS20 P21/ANI1/AV REFM/EI21 P20/ANI0/AVREFP/EI20 P130 P04/SCK10/SCL10 P03/ANI16/TS29/SI10/RxD1/SDA10 P02/ANI17/TS28/SO10/TxD1 P01/TS27/EI01/EO01/TO00 P00/TS26/EI00/TI00 P144/SO30/TxD3 P143/SI30/RxD3/SDA30 P142/SCK30/SCL30

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 39 of 177 Oct 31, 2025 Table 1 - 11 Multiplexed Pin Functions of the 80-pin Products (1/3) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 80LFQFP, 80LQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) Interrupt Key interrupt Capacitive sensing unit (CTSU2L) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) Remote control signal receiver (REMC) SDA01 ——— SCL01 — CLKA1 — TO04 ———T x D A 1 — TO07 ———R x D A 1 — 10 — — — RESET

11 P124 — — XT2/

1 7 ———V

25 P31 — EI31 (PCLBUZ0) — — — INTP4 — TS01 TI03/

3 0 P 7 7 ——— ———I N T P 1 1 K R 7 T S 0 9 ——( T x D 2 ) ——— 3 1 P 7 6 ——— ———I N T P 1 0 K R 6 T S 0 8 ——( R x D 2 ) ———

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 40 of 177 Oct 31, 2025 SDA21 — RxDA0 — SCL21 — — RIN0 TO06 ———C L K A 0 — TO05

40 P30 — EI30 — — — VCOUT0 INTP3 — TSCAP — RTC1HZ SCK11/

———

41 P50 CCD03 EI50/

———

42 P51 CCD02 EI51/

——— SCL31 ———

47 P17 CCD01 EO17 — — — — — — — TI02/

— (SO00)/ (TxD0) ———

48 P16 CCD00 EO16 — — — — INTP5 — — TI01/

— (SI00)/ (RxD0) ——— (TO02) — SCK20/ SCL20 ———

50 P14 — EO14 — — — VCOUT1 — — — (TI03)/

(TO03) — SI20/ RxD2/ SDA20 (SCLA0) — —

51 P13 — EO13 — — — IVREF1 — — — (TI04)/

(TO04) — SO20/ TxD2 (SDAA0) — —

52 P12 — EI12/

TOOLTxD — — — (INTP5) — — (TI05)/ (TO05) — SO00/ TxD0 ———

53 P11 — EI11/

T O O L R x D ——————( T I 0 6 ) / (TO06) — SI00/ RxD0/ SDA00 ———

54 P10 — EI10/

(TO07) — SCK00/ SCL00 ——— Table 1 - 11 Multiplexed Pin Functions of the 80-pin Products (2/3) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 80LFQFP, 80LQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) Interrupt Key interrupt Capacitive sensing unit (CTSU2L) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) Remote control signal receiver (REMC)

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 41 of 177 Oct 31, 2025

68 P23 — EI23 — ANI3 ANO1 IVREF0 — — TS21 — — — — — —

70 P21 — EI21 — ANI1/

71 P20 — EI20 — ANI0/

——— RxD1/ SDA10 ——— TxD1 ———

76 P01 — EI01/

——— RxD3/ SDA30 ——— SCL30 ——— Table 1 - 11 Multiplexed Pin Functions of the 80-pin Products (3/3) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 80LFQFP, 80LQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) Interrupt Key interrupt Capacitive sensing unit (CTSU2L) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) Remote control signal receiver (REMC)

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 42 of 177 Oct 31, 2025 1.3.10 100-pin products

100-pin plastic LFQFP (14 × 14 mm, 0.50-mm pitch) Caution 1. Connect the EV SS0 and EVSS1 pins to the same ground as the VSS pin. Caution 2. Make sure that the voltage on the V DD pin is no less than that on the EVDD0 and EVDD1 pins. Also make sure that the voltage on the EVDD0 is the same as that on the EVDD1 pin. Caution 3. Connect the REGC pin to V SS via a capacitor (0.47 to 1 µF). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the VDD, EVDD0, and EVDD1 pins and connect the VSS, EVSS0, and EVSS1 pins to separate ground lines. Remark 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). For details, see 4.3.10 Peripheral I/O redirection register (PIOR) in the RL78/G23 User’s Manual. P142/SCK30/SCL30 P141/PCLBUZ1/INTP7 P140/PCLBUZ0/INTP6 P120/ANI19/IVCMP1/EI120 P47/INTP2 P46/INTP1/TI05/TO05 P45/SO01 P44/SI01/SDA01 P43/SCK01/SCL01/CLKA1 P42/TI04/TO04/TxDA1 P41/RxDA1 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0/EI137 P122/X2/EXCLK/EI122 P121/X1/EI121/VBAT REGC VSS EVSS0 VDD EVDD0 P60/CCD04/SCLA0/EO60 P61/CCD05/SDAA0/EO61 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P100/ANI20 P147/ANI18/EI147/IVCMP0 P146/(INTP4) P111/(INTP11) P110/(INTP10) P101 P10/SCK00/SCL00/EI10/EO10/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/EI11/EO11/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/EI12/EO12/(INTP5)/(TI05)/(TO05) P13/TxD2/SO20/IVREF1/EO13/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/VCOUT1/EO14/(SCLA0)/(TI03)/(TO03) P15/SCK20/SCL20/EO15/(TI02)/(TO02) P16/CCD00/TI01/TO01/INTP5/EO16/(SI00)/(RxD0) P17/CCD01/TI02/TO02/EO17/(SO00)/(TxD0) P57/(INTP3) P56/(INTP1) P55/(PCLBUZ1)/(SCK00) P54/SCK31/SCL31 P53/SI31/SDA31 P52/SO31 P51/CCD02/EI51/EO51/SO11 P50/CCD03/TS00/EI50/EO50/SI11/SDA11 EV DD1 P30/INTP3/TSCAP/RTC1HZ/EI30/VCOUT0/SCK11/SCL11 P87/(INTP9) P156/ANI14 P155/ANI13/TS35 P154/ANI12/TS34 P153/ANI11/TS33 P152/ANI10/TS32 P151/ANI9/TS31 P150/ANI8/TS30 P27/ANI7/TS25 P26/ANI6/TS24 P25/ANI5/TS23 P24/ANI4/TS22 P23/ANI3/ANO1/IVREF0/EI23/TS21 P22/ANI2/ANO0/EI22/TS20 P21/ANI1/AV REFM/EI21 P20/ANI0/AVREFP/EI20 P130 P102/TI06/TO06 P04/SCK10/SCL10 P03/ANI16/TS29/SI10/RxD1/SDA10 P02/ANI17/TS28/SO10/TxD1 P01/TS27/EI01/EO01/TO00 P00/TS26/EI00/TI00 P145/TI07/TO07 P144/SO30/TxD3 P143/SI30/RxD3/SDA30 P86/(INTP8) P85/(INTP7)/CLKA0 P84/(INTP6)/RxDA0 P83/TxDA0 P82/(SO10)/(TxD1) P81/(SI10)/(RxD1)/(SDA10) P80/(SCK10)/(SCL10) EV SS1 P05/TS10 P06/TS11 P70/KR0/TS02/RIN0/SCK21/SCL21 P71/KR1/TS03/SI21/SDA21 P72/KR2/TS04/SO21 P73/KR3/TS05 P74/KR4/TS06/INTP8 P75/KR5/TS07/INTP9 P76/KR6/TS08/INTP10/(RxD2) P77/KR7/TS09/INTP11/(TxD2) P67/TI13/TO13/TS15 P66/TI12/TO12/TS14 P65/TI11/TO11/TS13 P64/TI10/TO10/TS12 P31/TI03/TO03/INTP4/TS01/EI31/(PCLBUZ0) P63/CCD07/SDAA1 P62/CCD06/SCLA1 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 RL78/G23 (Top View)

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 43 of 177 Oct 31, 2025 Table 1 - 12 Multiplexed Pin Functions of the 100-pin Products (1/4) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 100LFQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) Interrupt Key interrupt Capacitive sensing unit (CTSU2L) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) Remote control signal receiver (REMC) SCL30 ——— TO05 SDA01 ——— SCL01 — CLKA1 — TO04 ———T x D A 1 — 13 — — — RESET

14 P124 — — XT2/

2 0 ———V

28 P31 — EI31 (PCLBUZ0) — — — INTP4 — TS01 TI03/

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 44 of 177 Oct 31, 2025 TO13 3 3 P 7 7 ——— ———I N T P 1 1 K R 7 T S 0 9 ——( T x D 2 ) ——— 3 4 P 7 6 ——— ———I N T P 1 0 K R 6 T S 0 8 ——( R x D 2 ) ——— SDA21 ——— SCL21 — — RIN0 4 3 ———E V (SCL10) ——— (RxD1)/ (SDA10) ——— (TxD1) ———

52 P30 — EI30 — — — VCOUT0 INTP3 — TSCAP — RTC1HZ SCK11/

——— 5 3 ———E V

54 P50 CCD03 EI50/

———

55 P51 CCD02 EI51/

——— SCL31 ———

62 P17 CCD01 EO17 — — — — — — — TI02/

— (SO00)/ (TxD0) ——— Table 1 - 12 Multiplexed Pin Functions of the 100-pin Products (2/4) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 100LFQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) Interrupt Key interrupt Capacitive sensing unit (CTSU2L) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) Remote control signal receiver (REMC)

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 45 of 177 Oct 31, 2025

63 P16 CCD00 EO16 — — — — INTP5 — — TI01/

— (SI00)/ (RxD0) ——— (TO02) — SCK20/ SCL20 ———

65 P14 — EO14 — — — VCOUT1 — — — (TI03)/

(TO03) — SI20/ RxD2/ SDA20 (SCLA0) — —

66 P13 — EO13 — — — IVREF1 — — — (TI04)/

(TO04) — SO20/ TxD2 (SDAA0) — —

67 P12 — EI12/

TOOLTxD — — — (INTP5) — — (TI05)/ (TO05) — SO00/ TxD0 ———

68 P11 — EI11/

T O O L R x D ——————( T I 0 6 ) / (TO06) — SI00/ RxD0/ SDA00 ———

69 P10 — EI10/

(TO07) — SCK00/ SCL00 ———

87 P23 — EI23 — ANI3 ANO1 IVREF0 — — TS21 — — — — — —

89 P21 — EI21 — ANI1/

90 P20 — EI20 — ANI0/

——— Table 1 - 12 Multiplexed Pin Functions of the 100-pin Products (3/4) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 100LFQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) Interrupt Key interrupt Capacitive sensing unit (CTSU2L) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) Remote control signal receiver (REMC)

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 46 of 177 Oct 31, 2025 RxD1/ SDA10 ——— TxD1 ———

96 P01 — EI01/

——— RxD3/ SDA30 ——— Table 1 - 12 Multiplexed Pin Functions of the 100-pin Products (4/4) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 100LFQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) Interrupt Key interrupt Capacitive sensing unit (CTSU2L) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) Remote control signal receiver (REMC)

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 47 of 177 Oct 31, 2025

100-pin plastic LQFP (14 × 20 mm, 0.65-mm pitch) Caution 1. Connect the EV SS0 and EVSS1 pins to the same ground as the VSS pin. Caution 2. Make sure that the voltage on the V DD pin is no less than that on the EVDD0 and EVDD1 pins. Also make sure that the voltage on the EVDD0 is the same as that on the EVDD1 pin. Caution 3. Connect the REGC pin to V SS via a capacitor (0.47 to 1 µF). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the VDD, EVDD0, and EVDD1 pins and connect the VSS, EVSS0, and EVSS1 pins to separate ground lines. Remark 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). For details, see 4.3.10 Peripheral I/O redirection register (PIOR) in the RL78/G23 User’s Manual. P120/ANI19/IVCMP1/EI120 P47/INTP2 P46/INTP1/TI05/TO05 P45/SO01 P44/SI01/SDA01 P43/SCK01/SCL01/CLKA1 P42/TI04/TO04/TxDA1 P41/RxDA1 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0/EI137 P122/X2/EXCLK/EI122 P121/X1/EI121/VBAT REGC VSS EVSS0 VDD EVDD0 RL78/G23 (Top View) P140/PCLBUZ0/INTP6 P141/PCLBUZ1/INTP7 P142/SCK30/SCL30 P143/SI30/RxD3/SDA30 P144/SO30/TxD3 P145/TI07/TO07 P00/TS26/EI00/TI00 P01/TS27/EI01/EO01/TO00 P02/ANI17/TS28/SO10/TxD1 P03/ANI16/TS29/SI10/RxD1/SDA10 P04/SCK10/SCL10 P102/TI06/TO06 P130 P20/ANI0/AV REFP/EI20 P21/ANI1/AVREFM/EI21 P22/ANI2/ANO0/EI22/TS20 P23/ANI3/ANO1/IVREF0/EI23/TS21 P24/ANI4/TS22 P25/ANI5/TS23 P26/ANI6/TS24 P27/ANI7/TS25 P150/ANI8/TS30 P151/ANI9/TS31 P152/ANI10/TS32 P153/ANI11/TS33 P154/ANI12/TS34 P155/ANI13/TS35 P156/ANI14 P100/ANI20 P147/ANI18/EI147/IVCMP0 P60/CCD04/SCLA0/EO60 P61/CCD05/SDAA0/EO61 P62/CCD06/SCLA1 P63/CCD07/SDAA1 P31/TI03/TO03/INTP4/TS01/EI31/(PCLBUZ0) P64/TI10/TO10/TS12 P65/TI11/TO11/TS13 P66/TI12/TO12/TS14 P67/TI13/TO13/TS15 P77/KR7/TS09/INTP11/(TxD2) P76/KR6/TS08/INTP10/(RxD2) P75/KR5/TS07/INTP9 P74/KR4/TS06/INTP8 P73/KR3/TS05 P72/KR2/TS04/SO21 P71/KR1/TS03/SI21/SDA21 P70/KR0/TS02/RIN0/SCK21/SCL21 P06/TS11 P05/TS10 EV SS1 P80/(SCK10)/(SCL10) P81/(SI10)/(RxD1)/(SDA10) P82/(SO10)/(TxD1) P83/TxDA0 P84/(INTP6)/RxDA0 P85/(INTP7)/CLKA0 P86/(INTP8) P87/(INTP9) P30/INTP3/TSCAP/RTC1HZ/EI30/VCOUT0/SCK11/SCL11 EV DD1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 100 P146/(INTP4) P111/(INTP11) P110/(INTP10) P101 P10/SCK00/SCL00/EI10/EO10/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/EI11/EO11/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/EI12/EO12/(INTP5)/(TI05)/(TO05) P13/TxD2/SO20/IVREF1/EO13/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/VCOUT1/EO14/(SCLA0)/(TI03)/(TO03) P15/SCK20/SCL20/EO15/(TI02)/(TO02) P16/CCD00/TI01/TO01/INTP5/EO16/(SI00)/(RxD0) P17/CCD01/TI02/TO02/EO17/(SO00)/(TxD0) P57/(INTP3) P56/(INTP1) P55/(PCLBUZ1)/(SCK00) P54/SCK31/SCL31 P53/SI31/SDA31 P52/SO31 P51/CCD02/EI51/EO51/SO11 P50/CCD03/TS00/EI50/EO50/SI11/SDA11 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 48 of 177 Oct 31, 2025 Table 1 - 13 Multiplexed Pin Functions 2 of the 100-pin Products (1/4) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 100LQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) Interrupt Key interrupt Capacitive sensing unit (CTSU2L) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) Remote control signal receiver (REMC) 1 0 P 7 7 ——— ———I N T P 1 1 K R 7 T S 0 9 ——( T x D 2 ) ——— 1 1 P 7 6 ——— ———I N T P 1 0 K R 6 T S 0 8 ——( R x D 2 ) ——— SDA21 ——— SCL21 — — RIN0 2 0 ———E V (SCL10) ——— (RxD1)/ (SDA10) ——— (TxD1) ———

29 P30 — EI30 — — — VCOUT0 INTP3 — TSCAP — RTC1HZ SCK11/

——— 3 0 ———E V

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 49 of 177 Oct 31, 2025

31 P50 CCD03 EI50/

———

32 P51 CCD02 EI51/

——— SCL31 ——— — (SO00)/ (TxD0) ——— — (SI00)/ (RxD0) ——— (TO02) — SCK20/ SCL20 ——— (TO03) — SI20/ RxD2/ SDA20 (SCLA0) — — (TO04) — SO20/ TxD2 (SDAA0) — — TOOLTxD — — — (INTP5) — — (TI05)/ (TO05) — SO00/ TxD0 ——— T O O L R x D ——————( T I 0 6 ) / (TO06) — SI00/ RxD0/ SDA00 ——— (TO07) — SCK00/ SCL00 ——— Table 1 - 13 Multiplexed Pin Functions 2 of the 100-pin Products (2/4) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 100LQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) Interrupt Key interrupt Capacitive sensing unit (CTSU2L) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) Remote control signal receiver (REMC)

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 50 of 177 Oct 31, 2025

64 P23 — EI23 — ANI3 ANO1 IVREF0 — — TS21 — — — — — —

66 P21 — EI21 — ANI1/

67 P20 — EI20 — ANI0/

——— RxD1/ SDA10 ——— TxD1 ———

73 P01 — EI01/

——— RxD3/ SDA30 ——— SCL30 ——— TO05 SDA01 ——— SCL01 — CLKA1 — TO04 ———T x D A 1 — Table 1 - 13 Multiplexed Pin Functions 2 of the 100-pin Products (3/4) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 100LQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) Interrupt Key interrupt Capacitive sensing unit (CTSU2L) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) Remote control signal receiver (REMC)

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 51 of 177 Oct 31, 2025

91 P124 — — XT2/

9 7 ———V Table 1 - 13 Multiplexed Pin Functions 2 of the 100-pin Products (4/4) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 100LQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) Interrupt Key interrupt Capacitive sensing unit (CTSU2L) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) Remote control signal receiver (REMC)

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 52 of 177 Oct 31, 2025 1.3.11 128-pin products

128-pin plastic LFQFP (14 × 20 mm, 0.50-mm pitch) Caution 1. Connect the EV SS0 and EVSS1 pins to the same ground as the VSS pin. Caution 2. Make sure that the voltage on the V DD pin is no less than that on the EVDD0 and EVDD1 pins. Also make sure that the voltage on the EVDD0 is the same as that on the EVDD1 pin. Caution 3. Connect the REGC pin to V SS via a capacitor (0.47 to 1 µF). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the VDD, EVDD0, and EVDD1 pins and connect the VSS, EVSS0, and EVSS1 pins to separate ground lines. Remark 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). For details, see 4.3.10 Peripheral I/O redirection register (PIOR) in the RL78/G23 User’s Manual. RL78/G23 (Top View) P100/ANI20 P147/ANI18/EI147/IVCMP0 P146/(INTP4) P111/(INTP11) P110/(INTP10) P101 P117/ANI24 P116/ANI25 P115/ANI26 P114 P113 P112 P97/SO11 P96/SI11/SDA11 P95/SCK11/SCL11 P94 P93 P92 P91 P90 P10/SCK00/SCL00/EI10/EO10/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/EI11/EO11/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/EI12/EO12/(INTP5)/(TI05)/(TO05) P13/TxD2/SO20/IVREF1/EO13/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/VCOUT1/EO14/(SCLA0)/(TI03)/(TO03) P15/SCK20/SCL20/EO15/(TI02)/(TO02) P16/CCD00/TI01/TO01/INTP5/EO16/(SI00)/(RxD0) P17/CCD01/TI02/TO02/EO17/(SO00)/(TxD0) P57/(INTP3) P56/(INTP1) P55/(PCLBUZ1)/(SCK00) P54/SCK31/SCL31 P53/SI31/SDA31 P52/SO31 P51/CCD02/EI51/EO51 P50/CCD03/TS00/EI50/EO50 P30/INTP3/TSCAP/RTC1HZ/EI30/VCOUT0 P87/(INTP9) P142/SCK30/SCL30 P141/PCLBUZ1/INTP7 P140/PCLBUZ0/INTP6 P120/ANI19/IVCMP1/EI120 P37/ANI21 P36/ANI22 P35/ANI23 P34/TxDA1 P33/RxDA1 P32/CLKA1 P106/TI17/TO17 P105/TI16/TO16 P104/TI15/TO15 P103/TI14/TO14 P47/INTP2 P46/INTP1/TI05/TO05 P45/SO01 P44/SI01/SDA01 P43/SCK01/SCL01 P42/TI04/TO04 P41 P40/TOOL0 P127 P126 P125 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0/EI137 P122/X2/EXCLK/EI122 P121/X1/EI121/VBAT REGC V SS EVSS0 VDD EVDD0 P60/CCD04/SCLA0/EO60 P61/CCD05/SDAA0/EO61 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 102 101 100 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 P86/(INTP8) P85/(INTP7)/CLKA0 P84/(INTP6)/RxDA0 P83/TxDA0 P82/(SO10)/(TxD1) P81/(SI10)/(RxD1)/(SDA10) P80/(SCK10)/(SCL10) EV DD1 EVSS1 P05/TS10 P06/TS11 P70/KR0/TS02/RIN0/SCK21/SCL21 P71/KR1/TS03/SI21/SDA21 P72/KR2/TS04/SO21 P73/KR3/TS05 P74/KR4/TS06/INTP8 P75/KR5/TS07/INTP9 P76/KR6/TS08/INTP10/(RxD2) P77/KR7/TS09/INTP11/(TxD2) P67/TI13/TO13/TS15 P66/TI12/TO12/TS14 P65/TI11/TO11/TS13 P64/TI10/TO10/TS12 P31/TI03/TO03/INTP4/TS01/EI31/(PCLBUZ0) P63/CCD07/SDAA1 P62/CCD06/SCLA1 P156/ANI14 P155/ANI13/TS35 P154/ANI12/TS34 P153/ANI11/TS33 P152/ANI10/TS32 P151/ANI9/TS31 P150/ANI8/TS30 P27/ANI7/TS25 P26/ANI6/TS24 P25/ANI5/TS23 P24/ANI4/TS22 P23/ANI3/ANO1/IVREF0/EI23/TS21 P22/ANI2/ANO0/EI22/TS20 P21/ANI1/AV REFM/EI21 P20/ANI0/AVREFP/EI20 P130 P102/TI06/TO06 P07 P04/SCK10/SCL10 P03/ANI16/TS29/SI10/RxD1/SDA10 P02/ANI17/TS28/SO10/TxD1 P01/TS27/EI01/EO01/TO00 P00/TS26/EI00/TI00 P145/TI07/TO07 P144/SO30/TxD3 P143/SI30/RxD3/SDA30 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 6599 98 97 96 95 94 93 92 91 90 89 88 87 86 85

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 53 of 177 Oct 31, 2025 Table 1 - 14 Multiplexed Pin Functions of the 128-pin Products (1/5) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 128LFQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) Interrupt Key interrupt Capacitive sensing unit (CTSU2L) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) Remote control signal receiver (REMC) SCL30 ——— TO17 TO16 TO15 TO14 TO05 SDA01 ——— SCL01 ——— TO04 26 — — — RESET

27 P124 — — XT2/

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 54 of 177 Oct 31, 2025

41 P31 — EI31 (PCLBUZ0) — — — INTP4 — TS01 TI03/

4 6 P 7 7 ——— ———I N T P 1 1 K R 7 T S 0 9 ——( T x D 2 ) ——— 4 7 P 7 6 ——— ———I N T P 1 0 K R 6 T S 0 8 ——( R x D 2 ) ——— SDA21 ——— SCL21 — — RIN0 5 6 ———E V (SCL10) ——— (RxD1)/ (SDA10) ——— (TxD1) ——— Table 1 - 14 Multiplexed Pin Functions of the 128-pin Products (2/5) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 128LFQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) Interrupt Key interrupt Capacitive sensing unit (CTSU2L) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) Remote control signal receiver (REMC)

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 55 of 177 Oct 31, 2025

66 P30 — EI30 — — — VCOUT0 INTP3 — TSCAP — RTC1HZ — — — —

67 P50 CCD03 EI50/

68 P51 CCD02 EI51/

——— SCL31 ———

75 P17 CCD01 EO17 — — — — — — — TI02/

— (SO00)/ (TxD0) ———

76 P16 CCD00 EO16 — — — — INTP5 — — TI01/

— (SI00)/ (RxD0) ——— (TO02) — SCK20/ SCL20 ———

78 P14 — EO14 — — — VCOUT1 — — — (TI03)/

(TO03) — SI20/ RxD2/ SDA20 (SCLA0) — —

79 P13 — EO13 — — — IVREF1 — — — (TI04)/

(TO04) — SO20/ TxD2 (SDAA0) — —

80 P12 — EI12/

TOOLTxD — — — (INTP5) — — (TI05)/ (TO05) — SO00/ TxD0 ———

81 P11 — EI11/

T O O L R x D ——————( T I 0 6 ) / (TO06) — SI00/ RxD0/ SDA00 ———

82 P10 — EI10/

(TO07) — SCK00/ SCL00 ——— SCL11 ——— SDA11 ——— Table 1 - 14 Multiplexed Pin Functions of the 128-pin Products (3/5) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 128LFQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) Interrupt Key interrupt Capacitive sensing unit (CTSU2L) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) Remote control signal receiver (REMC)

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 56 of 177 Oct 31, 2025

114 P23 — EI23 — ANI3 ANO1 IVREF0 — — TS21 — — — — — —

116 P21 — EI21 — ANI1/

117 P20 — EI20 — ANI0/

——— RxD1/ SDA10 ——— TxD1 ———

124 P01 — EI01/

Table 1 - 14 Multiplexed Pin Functions of the 128-pin Products (4/5) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 128LFQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) Interrupt Key interrupt Capacitive sensing unit (CTSU2L) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) Remote control signal receiver (REMC)

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 57 of 177 Oct 31, 2025 TxD3 ——— RxD3/ SDA30 ——— Table 1 - 14 Multiplexed Pin Functions of the 128-pin Products (5/5) Pin Number I/O Power supply, system clock, and debugging Analog Circuits HMIs Timers Communications Interfaces 128LFQFP Digital port Controlled current drive port ELCL input/output port A/D converter (ADC) D/A converter (DAC) Comparator (CMP) Interrupt Key interrupt Capacitive sensing unit (CTSU2L) Timer array unit (TAU) Realtime Clock (RTC) Serial array unit (SAU) Serial interface IICA (IICA) Serial interface UARTA (UARTA) Remote control signal receiver (REMC)

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 58 of 177 Oct 31, 2025

1.4 Pin Identification

ANI0 to ANI14, PCLBUZ0, PCLBUZ1: Programmable clock output/buzzer ANI16 to ANI26: Analog input output ANO0, ANO1: Analog output REGC: Regulator capacitance AVREFM: Analog reference voltage minus RESET: Reset AVREFP: Analog reference voltage plus RIN0: IR remote controller input CCD00 to CCD07: Controlled current drive output RTC1HZ: Realtime clock correction clock (1 Hz) CLKA0, CLKA1: Asynchronous serial clock output output EI00, EI01, EI10 to EI12, RxD0 to RxD3, EI20 to EI23, EI30, EI31, RxDA0, RxDA1: Receive data EI50, EI51, SCLA0, SCLA1, EI120 to EI122, SCK00, SCK01, SCK10, EI137, EI147: Logic & event link controller input SCK11, SCK20, SCK21, EO01, EO10 to EO17, SCK30, SCK31: Serial clock input/output EO50, EO51, SCL00, SCL01, SCL10, EO60, EO61: Logic & event link controller output SCL11, SCL20, SCL21, EVDD0, EVDD1: Power supply for port SCL30, SCL31: Serial clock output EVSS0, EVSS1: Ground for port SDAA0, SDAA1, SDA00, EXCLK: External clock input SDA01, SDA10, SDA11, (main system clock) SDA20, SDA21, SDA30, EXCLKS: External clock input SDA31: Serial data input/output (subsystem clock) SI00, SI01, SI10, SI11, INTP0 to INTP11: Interrupt request from SI20, SI21, SI30, SI31: Serial data input peripheral modules SO00, SO01, SO10, IVCMP0, IVCMP1: Comparator input SO11, SO20, SO21, IVREF0, IVREF1: Comparator reference input SO30, SO31: Serial data output KR0 to KR7: Key return input TSCAP: Touch sensor capacitance P00 to P07: Port 0 TI00 to TI07, TI10 to TI17: Timer input P10 to P17: Port 1 TO00 to TO07, P20 to P27: Port 2 TO10 to TO17: Timer output P30 to P37: Port 3 TOOL0: Data input/output for tool P40 to P47: Port 4 TOOLRxD, TOOLTxD: Data input/output for external device P50 to P57: Port 5 TS00 to TS15, TS20 to TS35: Capacitive touch sensor P60 to P67: Port 6 TxD0 to TxD3, P70 to P77: Port 7 TxDA0, TxDA1: Transmit data P80 to P87: Port 8 VBAT: Battery backup power supply P90 to P97: Port 9 VCOUT0, VCOUT1: Comparator output P100 to P106: Port 10 VDD: Power supply P110 to P117: Port 11 VSS: Ground P120 to P127: Port 12 X1, X2: Cr ystal oscillator (main system clock) P130, P137: Port 13 XT1, XT2: Cr ystal oscillator (subsystem clock) P140 to P147: Port 14 P150 to P156: Port 15

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 59 of 177 Oct 31, 2025

1.5 Block Diagram

Caution 1. 32- to 128-pin products incorporate the remote control signal receiver. Caution 2. 36- to 128-pin products incorporate the serial interface UARTAn. Caution 3. 40- to 128-pin products incorporate the key return function. Remark m: Unit number, n: Channel number, p: Simplified SPI (CSI) number, q: UART number, r: Simplified I 2C number, xx: Port number Voltage regulator REGC Interrupt control RAM Power-on reset/ voltage detector POR/LVD control Reset control UARTq IICr INTPn CSIp Key return BCD correction Serial interface IICAn Buzzer output Clock output control PCLBUZn RL78 CPU core CRC RxDq TxDq ANIn AVREFP SCLAn SDAAn RTC1HZ RESET KRn Watchdog timer Data transfer controller CHn Port x Pxx Serial array unit m TImn TOmn SCKp SIp SOp SCLr SDAr Code flash memory Data flash memory AVREFM Logic and event link controller Clock generator and reset generator Middle-speed on-chip oscillator 1t o 4M H z High-speed on-chip oscillator 1 to 32 MHz Subsystem clock oscillator 32.768 kHz X1 X2/EXCLK XT1 XT2/EXCLKS D/A converter Comparator ANOn VOUTn IVCMPn IVREFn Serial interface UARTAn RxDAn TxDAn CLKAn SNOOZE mode sequencer Remote control signal receiverRIN0 Capacitive sensing unit TSn TSCAP High-speed system clock oscillator 1 to 20 MHz Multiplier, divider, and multiply-accumulator EOn EIn TOOL0 On-chip debugging Safety function Security function Low-speed on-chip oscillator 32.768 kHz Realtime clock A/D converter TOOLRxD, TOOLTxD VSS, EVSS0, EVSS1 VDD, EVDD0, EVDD1 Timer array unit m 32-bit interval timer

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 60 of 177 Oct 31, 2025

1.6 Outline of Functions

[30- to 48-pin products] Caution This outline describes the functi ons at the time when the peripheral I/O redirection register (PIOR) is set to 00H. (1/3) Item 30-pin 32-pin 36-pin 40-pin 44-pin 48-pin R7F100GAx R7F100GBx R7F100GCx R7F100GEx R7F100GFx R7F100GGx Code flash memory 96 to 256 KB 96 to 256 KB 96 to 256 KB 96 to 256 KB 96 to 768 KB 96 to 768 KB Data flash memory 8 KB 8 KB 8 KB 8 KB 8 KB 8 KB RAM 12 to 24 KB 12 to 24 KB 12 to 24 KB 12 to 24 KB 12 to 48 KB 12 to 48 KB Address space 1 MB CPU/ peripheral hardware clock frequency CLK) Main system clock HS (high-speed main) mode: 1 to 32 MHz (V DD = 1.8 to 5.5 V) HS (high-speed main) mode: 1 to 4 MHzNote 1 (VDD = 1.6 to 5.5 V) LS (low-speed main) mode: 1 to 24 MHz (VDD = 1.8 to 5.5 V) LS (low-speed main) mode: 1 to 4 MHzNote 1 (VDD = 1.6 to 5.5 V) LP (low-power main) mode: 1 to 2 MHzNote 2 (VDD = 1.6 to 5.5 V) Subsystem clock SUB mode: 32.768 kHz (V DD = 1.6 to 5.5 V) Main system clock High-speed system clock (f MX) 1 to 20 MHz High-speed on-chip oscillator clock (f IH)

1 MHz, 2 MHz, 3 MHz, 4 MHz, 6 MHz, 8 MHz, 12 MHz, 16 MHz, 24 MHz, 32 MHz

oscillator clock (fIM)

1 MHz, 2 MHz, 4 MHz

SX) 32.768 kHz (VDD = 1.6 to 5.5 V or VDD = 2.4 to

5.5 V when fXT is selected)

32.768 kHz (VDD = 1.6 to 5.5 V) Low-speed on-chip oscillator clock (f IL) 32.768 kHz (typ.) General-purpose registers 8 bits × 32 regi sters (8 bits × 8 registers × 4 banks) Minimum instruction execution time 0. 03125 µs (at the 32-MHz operation with the high-speed on-chip oscillator clock (fIH)) Instruction set • Data transfer (8/16 bits)

Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits × 8 bits, 16 bits × 16 bits), division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits)
Multiplication and accumulation (16 bits × 16 bits + 32 bits)
Rotate, barrel shift, and bit manipulation (set, reset, test, and Boolean operation), etc. I/O port Total number of pins 26 28 32 36 40 44 CMOS I/O 23 (N-ch open- drain I/O [V DD withstand voltage]: 10) (N-ch open- drain I/O [V DD withstand voltage]: 10) (N-ch open- drain I/O [V DD withstand voltage]: 12) (N-ch open- drain I/O [V DD withstand voltage]: 12) (N-ch open- drain I/O [V DD withstand voltage]: 12) (N-ch open- drain I/O [V DD withstand voltage]: 13) C M O S i n p u t 111333 C M O S o u t p u t —————1 N-ch open-drain I/O (withstand voltage: 6 V) 233344 Controlled current drive port 677778 <R>

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 61 of 177 Oct 31, 2025 Timers 16-bit timer 8 channels Watchdog timer 1 channel Realtime clock (RTC) 1 channel 32-bit interval timer (TML32) 1 channel in 32-bit counter mode, 2 channels in 16-bit counter mode, 4 channels in 8-bit counter mode Timer output 4 channels (PWM outputs: 3 Note 3), 8 channels (PWM outputs: 7Note 3)Note 4 5 channels (PWM outputs: 4Note 3), 8 channels (PWM outputs: 7 Note 3)Note 4 RTC output 1 channel Clock output/buzzer output 2 channels

3.91 kHz, 7.81 kHz, 15.63 kHz, 2 MHz, 4 MHz, 8 MHz, 16 MHz (at the 32-MHz operation with the main system clock (fMAIN)) (at the 32.768-kHz operation with the low-speed peripheral clock (fSXP)) 8-/10-/12-bit resolution A/D converter 8 channels 9 channels 10 channels D/A converter 2 channels Comparator 2 channels Serial interface [30- and 32-pin products]
Simplified SPI (CSI): 1 channel/simplified I 2C: 1 channel/UART: 1 channel
Simplified SPI (CSI): 1 channel/simplified I2C: 1 channel/UART: 1 channel
Simplified SPI (CSI): 1 channel/simplified I2C: 1 channel/UART (UART supporting LIN-bus): 1 channel [36- to 44-pin products]
Simplified SPI (CSI): 1 channel/simplified I2C: 1 channel/UART: 1 channel
Simplified SPI (CSI): 1 channel/simplified I2C: 1 channel/UART: 1 channel
Simplified SPI (CSI): 2 channels/simplified I2C: 2 channels/UART (UART supporting LIN- bus): 1 channel [48-pin products]
Simplified SPI (CSI): 2 channels/simplified I 2C: 2 channels/UART: 1 channel
Simplified SPI (CSI): 1 channel/simplified I2C: 1 channel/UART: 1 channel
Simplified SPI (CSI): 2 channels/simplified I2C: 2 channels/UART (UART supporting LIN- bus): 1 channel UARTA — 1 channel 2 channels I2C bus 1 channel 2 channels Remote control signal receiver — 1 channel Data transfer controller (DTC) 30 sources 30 sources 32 sources 33 sources 35 sources 36 sources Logic and event link controller (ELCL) 1 SNOOZE mode sequencer (SMS) 1 Capacitive sensing unit ROM size: 96 to 128 KB 235668 ROM size: 192 to 768 KB 671 1 1 3 1 4 1 6 Vectored interrupt sources Internal 31 32 35 35 39 39 E x t e r n a l 666771 0 Key interrupt — 4 6 (2/3) Item 30-pin 32-pin 36-pin 40-pin 44-pin 48-pin R7F100GAx R7F100GBx R7F100GCx R7F100GEx R7F100GFx R7F100GGx

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 62 of 177 Oct 31, 2025 Note 1. Overwrite the flash memory during operation at 2 MHz or a lower frequency. Note 2. When the flash memory is to be overwritten, switch to high-speed main (HS) mode or low-speed main (LS) mode. Note 3. The number of PWM outputs varies depending on the setting of channels in use (the number of masters and slaves). For details, see 7.9.3 Operation for the multiple PWM output function in the RL78/G23 User’s Manual. Note 4. This applies when the corresponding bit in the peripheral I/O redirection register (PIOR) is set to 1. Note 5. In normal operation, executing the instruction code FFH triggers an internal reset, but this is not the case during emulation by the on-chip debugging emulator. Reset • Reset by RESET pin

Internal reset by watchdog timer
Internal reset by power-on-reset
Internal reset by voltage detectors (LVD0 and LVD1)
Internal reset by illegal instruction executionNote 5
Internal reset by RAM parity error
Internal reset by illegal-memory access Power-on-reset circuit Detection voltage
1.50 V (typ.) Voltage detector LVD0 Detection voltage
Rising edge: 1.69 V to 3.96 V (6 stages)
Falling edge: 1.65 V to 3.88 V (6 stages) LVD1 Detection voltage
Rising edge: 1.67 V to 4.16 V (18 stages)
Falling edge: 1.63 V to 4.08 V (18 stages) On-chip debugging Available (tracing supported) Power supply voltage V DD = 1.6 to 5.5 V Operating ambient temperature T A = -40 to +85°C (2D: Consumer applications), TA = -40 to +105°C (3C: Industrial applications) (3/3) Item 30-pin 32-pin 36-pin 40-pin 44-pin 48-pin R7F100GAx R7F100GBx R7F100GCx R7F100GEx R7F100GFx R7F100GGx

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 63 of 177 Oct 31, 2025 [52- to 128-pin products] Caution This outline describes the functi ons at the time when the peripheral I/O redirection register (PIOR) is set to 00H. (1/3) Item 52-pin 64-pin 80-pin 100-pin 128-pin R7F100GJx R7F100GLx R7F100GMx R7F100GPx R7F100GSx Code flash memory 96 to 768 KB 96 to 768 KB 128 to 768 KB 128 to 768 KB 256 to 768 KB Data flash memory 8 KB 8 KB 8 KB 8 KB 8 KB RAM 12 to 48 KB 12 to 48 KB 16 to 48 KB 16 to 48 KB 24 to 48 KB Address space 1 MB CPU/ peripheral hardware clock frequency CLK) Main system clock HS (high-speed main) mode: 1 to 32 MHz (V DD = 1.8 to 5.5 V) HS (high-speed main) mode: 1 to 4 MHzNote 1 (VDD = 1.6 to 5.5 V) LS (low-speed main) mode: 1 to 24 MHz (VDD = 1.8 to 5.5 V) LS (low-speed main) mode: 1 to 4 MHzNote 1 (VDD = 1.6 to 5.5 V) LP (low-power main) mode: 1 to 2 MHzNote 2 (VDD = 1.6 to 5.5 V) Subsystem clock SUB mode: 32.768 kHz (V DD = 1.6 to 5.5 V) Main system clock High-speed system clock MX) 1 to 20 MHz High-speed on-chip oscillator clock (fIH) oscillator clock (fIM) Subsystem clock X (f SX) 32.768 kHz (V DD = 1.6 to 5.5 V) Low-speed on-chip oscillator clock (f IL) 32.768 kHz (typ.) General-purpose registers 8 bits × 32 r egisters (8 bits × 8 registers × 4 banks) Minimum instruction execution time 0.03125 µs (at the 32-MHz operation with the high-speed on-chip oscillator clock (fIH)) Instruction set • Data transfer (8/16 bits)

Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits × 8 bits, 16 bits × 16 bits), division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits)
Multiplication and accumulation (16 bits × 16 bits + 32 bits)
Rotate, barrel shift, and bit manipulation (set, reset, test, and Boolean operation), etc. I/O port Total number of pins 48 58 74 92 120 CMOS I/O 40 (N-ch open- drain I/O [V DD withstand voltage]: 15) (N-ch open- drain I/O [EV DD withstand voltage]: Note 3/ 18Note 4) (N-ch open- drain I/O [EV DD withstand voltage]: 27) (N-ch open- drain I/O [EV DD withstand voltage]: 31) 112 (N-ch open-drain I/O [EV DD withstand voltage]: 33) CMOS input 3 3 3 3 3 CMOS output 1 1 1 1 1 N-ch open-drain I/O (withstand voltage: 6 V) 44444 Controlled current drive port 8 8 8 8 8

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 64 of 177 Oct 31, 2025 Timers 16-bit timer 8 channels 12 channels 16 channels Watchdog timer 1 channel Realtime clock (RTC) 1 channel 32-bit interval timer (TML32) 1 channel in 32-bit counter mode, 2 channels in 16-bit counter mode, 4 channels in 8-bit counter mode Timer output 5 channels (PWM outputs: Note 5), 8 channels (PWM outputs: 7Note 5)Note 6 8 channels (PWM outputs: 7Note 5) 12 channels (PWM outputs: 10Note 5) 16 channels (PWM outputs: 14Note 5) RTC output 1 channel Clock output/buzzer output 2 channels

3.91 kHz, 7.81 kHz, 15.63 kHz, 2 MHz, 4 MHz, 8 MHz, 16 MHz (at the 32-MHz operation with the main system clock (fMAIN)) (at the 32.768-kHz operation with the low-speed peripheral clock (fSXP)) 8-/10-/12-bit resolution A/D converter 12 channels 12 channels 17 channe ls 20 channels 26 channels D/A converter 2 channels Comparator 2 channels Serial interfaces [52-pin products]
Simplified SPI (CSI): 2 channels/simplified I 2C: 2 channels/UART: 1 channel
Simplified SPI (CSI): 1 channel/simplified I2C: 1 channel/UART: 1 channel
Simplified SPI (CSI): 2 channels/simplified I2C: 2 channels/UART (UART supporting LIN- bus): 1 channel [64-pin products]
Simplified SPI (CSI): 2 channels/simplified I2C: 2 channels/UART: 1 channel
Simplified SPI (CSI): 2 channels/simplified I2C: 2 channels/UART: 1 channel
Simplified SPI (CSI): 2 channels/simplified I2C: 2 channels/UART (UART supporting LIN- bus): 1 channel [80- to 128-pin products]
Simplified SPI (CSI): 2 channels/simplified I 2C: 2 channels/UART: 1 channel
Simplified SPI (CSI): 2 channels/simplified I2C: 2 channels/UART: 1 channel
Simplified SPI (CSI): 2 channels/simplified I2C: 2 channels/UART (UART supporting LIN- bus): 1 channel
Simplified SPI (CSI): 2 channels/simplified I2C: 2 channels/UART: 1 channel UARTA 2 channels I2C bus 2 channels Remote control signal receiver 1 channel Data transfer controller (DTC) 36 sources 37 sources 39 sources Logic and event link controller (ELCL) 1 SNOOZE mode sequencer (SMS) 1 Capacitive sensing unit ROM size: 96 to 128 KB 10 12 30 32 32 ROM size: 192 to 768 KB 20 22 30 32 32 Vectored interrupt sources Internal 39 39 44 44 48 External 12 13 13 13 13 Key interrupt 8 (2/3) Item 52-pin 64-pin 80-pin 100-pin 128-pin R7F100GJx R7F100GLx R7F100GMx R7F100GPx R7F100GSx

RL78/G23 1. Outline R01DS0395EJ0140 Rev.1.40 Page 65 of 177 Oct 31, 2025 Note 1. Overwrite the flash memory during operation at 2 MHz or a lower frequency. Note 2. When the flash memory is to be overwritten, switch to high-speed main (HS) mode or low-speed main (LS) mode. Note 3. This only applies to the products with 96- and 128-Kbyte flash memory. Note 4. This only applies to the products with 192- to 768-Kbyte flash memory. Note 5. The number of PWM outputs varies depending on the setting of channels in use (the number of masters and slaves). For details, see 7.9.3 Operation for the multiple PWM output function in the RL78/G23 User’s Manual. Note 6. This applies when the corresponding bit in the peripheral I/O redirection register (PIOR) is set to 1. Note 7. In normal operation, executing the instruction code FFH triggers an internal reset, but this is not the case during emulation by the on-chip debugging emulator. Reset • Reset by RESET pin

Internal reset by watchdog timer
Internal reset by power-on-reset
Internal reset by voltage detectors (LVD0 and LVD1)
Internal reset by illegal instruction executionNote 7
Internal reset by RAM parity error
Internal reset by illegal-memory access Power-on-reset circuit Detection voltage
1.50 V (typ.) Voltage detector LVD0 Detection voltage
Rising edge: 1.69 V to 3.96 V (6 stages)
Falling edge: 1.65 V to 3.88 V (6 stages) LVD1 Detection voltage
Rising edge: 1.67 V to 4.16 V (18 stages)
Falling edge: 1.63 V to 4.08 V (18 stages) On-chip debugging Available (tracing supported) Power supply voltage V DD = 1.6 to 5.5 V Operating ambient temperature T A = -40 to +85°C (2D: Consumer applications), TA = -40 to +105°C (3C: Industrial applications) (3/3) Item 52-pin 64-pin 80-pin 100-pin 128-pin R7F100GJx R7F100GLx R7F100GMx R7F100GPx R7F100GSx

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 66 of 177 Oct 31, 2025 2. Electrical Characteristics This section describes the electrical characteristics of the following products. Caution 1. RL78 microcontrollers have on-chip debugging functionality for use in the development and evaluation of user systems. Do not use on-chip debugging with products designated as part of mass production, because using this function may cause the guaranteed number of times the flash memory is rewritten to be exceeded, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when on-chip debugging is used with products designated as part of mass production. Caution 2. For the consumer application products, the ambient operating temperature of T A = -40°C to +85°C applies. Caution 3. For products that do not have an EV DD0, EVDD1, EVSS0, or EVSS1 pin, read EVDD0 and EVDD1 as VDD, and EVSS0 and EVSS1 as VSS. Caution 4. The present pins differ depending on the products. For details, see section 2.1 Functions of Port Pins through section 2.2.1 Functions for each product in the RL78/G23 User’s Manual.

2D : Consumer applications, TA = -40 to +85°C R7F100Gxx2Dxx
3C : Industrial applications, TA = -40 to +105°C R7F100Gxx3Cxx

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 67 of 177 Oct 31, 2025

2.1 Absolute Maximum Ratings

Note 1. Connect the REGC pin to VSS via a capacitor (0.47 to 1 µF). The listed value is the absolute maximum rating of the REGC pin. Only use the capacitor connection. Do not apply a specific voltage to this pin. Note 2. This voltage must be no higher than 6.5 V. Note 3. The voltage on a pin in use for A/D conversion must not exceed AVREFP + 0.3. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark 1. The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified. Remark 2. AV REFP refers to the positive reference voltage of the A/D converter. Remark 3. The reference voltage is VSS. (1/2) Item Symbols Conditions Ratings Unit Supply voltage VDD -0.5 to +6.5 V EVDD0, EVDD1 EVDD0 = EVDD1 -0.5 to +6.5 V EVSS0, EVSS1 EVSS0 = EVSS1 -0.5 to +0.3 V REGC pin input voltage V IREGC REGC -0.3 to +2.1 and -0.3 to VDD + 0.3Note 1 V Input voltage V I1 P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P140 to P147 -0.3 to EV DD0 + 0.3 and -0.3 to VDD + 0.3Note 2 V VI2 P60 to P63 (N-ch open-drain) -0.3 to +6.5 V VI3 P20 to P27, P121 to P124, P137, P150 to P156, EXCLK, EXCLKS, RESET -0.3 to VDD + 0.3Note 2 V Output voltage V O1 P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 -0.3 to EV DD0 + 0.3 and -0.3 to VDD + 0.3Note 2 V VO2 P20 to P27, P121, P122, P150 to P156 -0.3 to VDD + 0.3Note 2 V Analog input voltage V AI1 ANI16 to ANI26 -0.3 to EVDD0 + 0.3 and -0.3 to AVREFP + 0.3 Notes 2, 3 V VAI2 ANI0 to ANI14 -0.3 to VDD + 0.3 and -0.3 to AVREFP + 0.3 Notes 2, 3 V

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 68 of 177 Oct 31, 2025 Note The rating for the following port pins is 80 mA when IOL1 = 40.0 mA is specified by the 40-mA port output control register (PTDC).

Pins P04, P10, and P120 of the 64- to 100-pin package products with 384- to 768-Kbyte code flash memory
Pin P110 of the 100-pin package products with 384- to 768-Kbyte code flash memory
Pins P17 and P51 of the 30- to 52-pin package products
Pin P70 of the 32- to 52-pin package products Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified. (2/2) Item Symbols Conditions Ratings Unit High-level output current I OH1 Per pin P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 -40 mA Total of all pins -170 mA P00 to P04, P07, P32 to P37, P40 to P47, P102 to P106, P120, P125 to P127, P130, P140 to P145 -70 mA P05, P06, P10 to P17, P30, P31, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100, P101, P110 to P117, P146, P147 -100 mA I OH2 Per pin P20 to P27, P121, P122, P150 to P156 -5 mA Total of all pins -20 mA Low-level output current I OL1 Per pin P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 Note mA Total of all pins 170 mA P00 to P04, P07, P32 to P37, P40 to P47, P102 to P106, P120, P125 to P127, P130, P140 to P145 70 mA P05, P06, P10 to P17, P30, P31, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100, P101, P110 to P117, P146, P147 100 mA I OL2 Per pin P20 to P27, P121, P122, P150 to P156 10 mA Total of all pins 20 mA Ambient operating temperature TA In normal operation mode 3C: Industrial applications -40 to +105 C 2D: Consumer applications -40 to +85 In flash memory programming mode 3C: Industrial applications -40 to +105 2D: Consumer applications -40 to +85 Storage temperature T stg -65 to +150 C

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 69 of 177 Oct 31, 2025

2.2 Characteristics of the Oscillators

2.2.1 Characteristics of the X1 oscillator

Note The listed time and frequency indicate permissible ranges of the oscillator. For actual applications, request evaluation by the manufacturer of the oscillator circuit mounted on a board so you can use appropriate values. Refer to 2.4 AC Characteristics for instruction execution time. Caution Since the CPU is started by the high-speed on-chip o scillator clock after release from the reset state, the user should use the oscillation stabilization time counter status register (OSTC) to check the X1 clock oscillation stabilization time. Specify the values for the oscillation stabilization time in the OSTC register and the oscillation stabilization time select register (OSTS) after having sufficiently evaluated the oscillation stabilization time with the resonator to be used.

2.2.2 Characteristics of the XT1 oscillator

Note The listed time and frequency indicate permissible ranges of the oscillator. For actual applications, request evaluation by the manufacturer of the oscillator circuit mounted on a board so you can use appropriate values. Refer to 2.4 AC Characteristics for instruction execution time. (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Item Resonator Conditions Min. Typ. Max. Unit X1 clock oscillation allowable input cycle timeNote Ceramic resonator/ crystal resonator 0.05 1 µs (TA = -40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V for the 30- to 36-pin products, 1.6 V ≤ VDD ≤ 5.5 V for the 40- to 128-pin products, VSS = 0 V) Item Resonator Conditions Min. Typ. Max. Unit XT1 clock oscillation frequency (fXT)Note Crystal resonator 32.768 kHz

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 70 of 177 Oct 31, 2025

2.2.3 Characteristics of the on-chip oscillators

Note 1. The accuracy values were obtained in testing of this product. Note 2. The listed condition applies when the setting of the FRQSEL3 bit of the user option byte is 1. Note 3. The listed values only indicate the characteristics of the oscillators. Refer to 2.4 AC Characteristics for instruction execution time. Note 4. These values are the results of characteristic evaluation and are not checked for shipment. (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Item Symbol Conditions Min. Typ. Max. Unit High-speed on-chip oscillator clock frequency fIH 13 2 MHz High-speed on-chip oscillator clock frequency accuracy Note 1 HIPREC = 1 +85 to +105°C 1.8 V ≤ VDD ≤ 5.5 V -2.0 +2.0 % HIPREC = 0Note 2 -15 0 % High-speed on-chip oscillator clock correction resolution 0.05 % Middle-speed on-chip oscillator clock frequencyNote 3 fIM 14 MHz Middle-speed on-chip oscillator clock frequency accuracyNote 1 -12 +12 % Middle-speed on-chip oscillator clock correction resolution 0.15 % Middle-speed on-chip oscillator frequency temperature coefficient ±0.17 Note 4 %/°C Low-speed on-chip oscillator clock frequency Note 3 fIL 32.768 kHz Low-speed on-chip oscillator clock frequency accuracyNote 1 -15 +15 % Low-speed on-chip oscillator clock correction resolution 0.3 % Low-speed on-chip oscillator frequency temperature coefficient ±0.21 Note 4 %/°C

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 71 of 177 Oct 31, 2025

2.3 DC Characteristics

2.3.1 Pin characteristics

Note 1. Device operation is guaranteed at the listed currents even if current is flowing from the EVDD0, EVDD1, or VDD pin to an output pin. Note 2. The combination of these and other pins must also not exceed the value for maximum total current. Note 3. The listed currents apply when the duty cycle is no greater than 70%. Use the following formula to calculate the output current when the duty cycle is greater than 70%, where n is the duty cycle.

Total output current from the listed pins = (IOH  0.7)/(n  0.01) Example when n = 80% and IOH = -10.0 mA Total output current from the listed pins = (-10.0  0.7)/(80  0.01) ≈ -8.7 mA Note that the duty cycle has no effect on the current that is allowed to flow into a single pin. A current higher than the absolute maximum rating must not flow into a single pin. (Notes, Caution, and Remark continue on the next page.) (TA = -40 to +105°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/7) Item Symbol Conditions Min. Typ. Max. Unit Allowable high-level output currentNote 1 IOH1 Per pin for P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147

1.6 V ≤ EV

DD0 ≤ 5.5 V -10.0 Note 2 mA Total of P00 to P04, P07, P32 to P37, P40 to P47, P102 to P106, P120, P125 to P127, P130, P140 to P145 (when duty ≤ 70% Note 3) 4.0 V ≤ EVDD0 ≤ 5.5 V -55.0 Note 4 mA 2.7 V ≤ EVDD0 < 4.0 V -10.0 mA 1.8 V ≤ EVDD0 < 2.7 V -5.0 mA 1.6 V ≤ EVDD0 < 1.8 V -2.5 mA Total of P05, P06, P10 to P17, P30, P31, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100, P101, P110 to P117, P146, P147 (when duty ≤ 70% Note 3) 4.0 V ≤ EVDD0 ≤ 5.5 V -80.0 Note 5 mA 2.7 V ≤ EVDD0 < 4.0 V -19.0 mA 1.8 V ≤ EVDD0 < 2.7 V -10.0 mA 1.6 V ≤ EVDD0 < 1.8 V -5.0 mA Total of all pins (when duty ≤ 70%Note 3) 1.6 V ≤ EVDD0 ≤ 5.5 V -135.0 Note 6 mA IOH2 Per pin for P20 to P27, P121, P122, P150 to P156 4.0 V ≤ VDD ≤ 5.5 V -3.0 Note 2 mA 2.7 V ≤ VDD < 4.0 V -1.0 Note 2 mA 1.8 V ≤ VDD < 2.7 V -1.0 Note 2 mA 1.6 V ≤ VDD < 1.8 V -0.5 Note 2 mA Total of all pins (when duty ≤ 70%Note 3) 4.0 V ≤ VDD ≤ 5.5 V -20.0 mA 2.7 V ≤ VDD < 4.0 V -10.0 mA 1.8 V ≤ VDD < 2.7 V -5.0 mA 1.6 V ≤ VDD < 1.8 V -5.0 mA

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 72 of 177 Oct 31, 2025 Note 4. The maximum value is -30 mA in the products for industrial applications (R7F100Gxx3Cxx) with an ambient operating temperature range of +85°C to +105°C. Note 5. The maximum value is -50 mA in the products for industrial applications (R7F100Gxx3Cxx) with an ambient operating temperature range of +85°C to +105°C. Note 6. The maximum values are respectively -100 mA and -60 mA in the products for industrial applications (R7F100Gxx3Cxx) with an ambient operating temperature range of -40°C to +85°C and of +85°C to +105°C. Caution The following pins are not capable of the output of high-level signals in the N-ch open-drain output mode. P00, P02 to P04, P10 to P15, P17, P34, P42 to P45, P50, P52 to P55, P71, P72, P74, P80 to P83, P96, P120, and P142 to P144 Remark The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified.

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 73 of 177 Oct 31, 2025 Note 1. Device operation is guaranteed at the listed currents even if current is flowing from an output pin to the EVSS0, EVSS1, or VSS pin. Note 2. The combination of these and other pins must also not exceed the value for maximum total current. Note 3. The maximum rating for the following port pins is 40 mA when IOL1 = 40.0 mA is specified by the 40-mA port output control register (PTDC).

Pins P04, P10, and P120 of the 64- to 100-pin package products with 384- to 768-Kbyte code flash memory
Pin P101 of the 100-pin package products with 384- to 768-Kbyte code flash memory
Pins P17 and P51 of the 30- to 52-pin package products
Pin P70 of the 32- to 52-pin package products Note 4. The listed currents apply when the duty cycle is no greater than 70%. Use the following formula to calculate the output current when the duty cycle is greater than 70%, where n is the duty cycle.
Total output current from the listed pins = (IOL  0.7)/(n  0.01) Example when n = 80% and IOL = 10.0 mA Total output current from the listed pins = (10.0  0.7)/(80  0.01) ≈8.7 mA Note that the duty cycle has no effect on the current that is allowed to flow into a single pin. A current higher than the absolute maximum rating must not flow into a single pin. (Notes and Remark continue on the next page.) (TA = -40 to +105°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/7) Item Symbol Conditions Min. Typ. Max. Unit Allowable low-level output currentNote 1 IOL1 Per pin for P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 20.0 Notes 2, 3 mA Per pin for P60 to P63 15.0 Note 2 mA Total of P00 to P04, P07, P32 to P37, P40 to P47, P102 to P106, P120, P125 to P127, P130, P140 to P145 (when duty ≤ 70% Note 4) 4.0 V ≤ EVDD0 ≤ 5.5 V 70.0 Note 5 mA 2.7 V ≤ EVDD0 < 4.0 V 15.0 mA 1.8 V ≤ EVDD0 < 2.7 V 9.0 mA 1.6 V ≤ EVDD0 < 1.8 V 4.5 mA Total of P05, P06, P10 to P17, P30, P31, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100, P101, P110 to P117, P146, P147 (when duty ≤ 70% Note 4) 4.0 V ≤ EVDD0 ≤ 5.5 V 80.0 Note 5 mA 2.7 V ≤ EVDD0 < 4.0 V 35.0 mA 1.8 V ≤ EVDD0 < 2.7 V 20.0 mA 1.6 V ≤ EVDD0 < 1.8 V 10.0 mA Total of all pins (when duty ≤ 70% Note 4) 150.0 Note 6 mA IOL2 Per pin for P20 to P27, P121, P122, P150 to P156 4.0 V ≤ VDD ≤ 5.5 V 8.5Note 2 mA 2.7 V ≤ VDD < 4.0 V 1.5Note 2 mA 1.8 V ≤ VDD < 2.7 V 0.6Note 2 mA 1.6 V ≤ VDD < 1.8 V 0.4Note 2 mA Total of all pins (when duty ≤ 70%Note 4) 4.0 V ≤ VDD ≤ 5.5 V 20 mA 2.7 V ≤ VDD < 4.0 V 20 mA 1.8 V ≤ VDD < 2.7 V 15 mA 1.6 V ≤ VDD < 1.8 V 10 mA

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 74 of 177 Oct 31, 2025 Note 5. The maximum value is 40 mA in the products for industrial applications (R7F100Gxx3Cxx) with an ambient operating temperature range of +85°C to +105°C. Note 6. The maximum value is 80 mA in the products for industrial applications (R7F100Gxx3Cxx) with an ambient operating temperature range of +85°C to +105°C. Remark The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified.

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 75 of 177 Oct 31, 2025 Caution The maximum value of V IH of pins P00, P02 to P04, P10 to P15, P17, P34, P42 to P45, P50, P52 to P55, P71, P72, P74, P80 to P83, P96, P120, and P142 to P144 is EVDD0, even in the N-ch open-drain output mode. Remark The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified. (TA = -40 to +105°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (3/7) Item Symbol Conditions Min. Typ. Max. Unit Input voltage, high V IH1 P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P140 to P147 Normal input buffer 0.8 EV DD0 EVDD0 V VIH2 P01, P03, P04, P10, P11, P13 to P17, P41, P43, P44, P53 to P55, P71, P80, P81, P142, P143 TTL input buffer

4.0 V ≤ EV

DD0 ≤ 5.5 V

2.2 EV DD0 V

3.3 V ≤ EV

DD0 < 4.0 V

2.0 EV DD0 V

DD0 < 3.3 V

1.5 EV DD0 V

VIH3 P20 to P27, P150 to P156 0.7 VDD VDD V VIH4 P60 to P63 0.7 EVDD0 6.0 V VIH5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0.8 VDD VDD V Input voltage, low V IL1 P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P140 to P147 Normal input buffer 0 0.2 EV DD0 V VIL2 P01, P03, P04, P10, P11, P13 to P17, P41, P43, P44, P53 to P55, P71, P80, P81, P142, P143 TTL input buffer DD0 ≤ 5.5 V 00 . 8 V TTL input buffer 3.3 V ≤ EVDD0 < 4.0 V 00 . 5 V TTL input buffer DD0 < 3.3 V 00 . 3 2 V VIL3 P20 to P27, P150 to P156 0 0.3 VDD V VIL4 P60 to P63 0 0.3 EVDD0 V VIL5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0 0.2 VDD V <R> <R>

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 76 of 177 Oct 31, 2025 Caution P00, P02 to P04, P10 to P15, P17, P34, P42 to P45, P 50, P52 to P55, P71, P72, P74, P80 to P83, P96, P120, and P142 to P144 do not output high-level signals in the N-ch open-drain output mode. Remark The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified. (TA = -40 to +105°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (4/7) Item Symbol Conditions Min. Typ. Max. Unit Output voltage, high V OH1 P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 DD0 ≤ 5.5 V, IOH1 = -10.0 mA EVDD0 - 1.5 V 4.0 V ≤ EVDD0 ≤ 5.5 V, IOH1 = -3.0 mA EVDD0 - 0.7 V 2.7 V ≤ EVDD0 ≤ 5.5 V, IOH1 = -2.0 mA EVDD0 - 0.6 V 1.8 V ≤ EVDD0 ≤ 5.5 V, IOH1 = -1.5 mA EVDD0 - 0.5 V 1.6 V ≤ EVDD0 < 5.5 V, IOH1 = -1.0 mA EVDD0 - 0.5 V VOH2 P20 to P27, P121, P122, P150 to P156

4.0 V ≤ V

DD ≤ 5.5 V, IOH2 = -3.0 mA VDD - 0.7 V 2.7 V ≤ VDD < 4.0 V, IOH2 = -1.0 mA VDD - 0.5 V 1.8 V ≤ VDD < 2.7 V, IOH2 = -1.0 mA VDD - 0.5 V 1.6 V ≤ VDD < 1.8 V, IOH2 = -0.5 mA VDD - 0.5 V

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 77 of 177 Oct 31, 2025 Note The listed value applies when IOL1 = 40.0 mA is specified for the following port pins by the 40-mA port output control register (PTDC).

Pins P04, P10, and P120 of the 64- to 100-pin package products with 384- to 768-Kbyte code flash memory
Pin P101 of the 100-pin package products with 384- to 768-Kbyte code flash memory
Pins P17 and P51 of the 30- to 52-pin package products
Pin P70 of the 32- to 52-pin products Remark The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified. (TA = -40 to +105°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (5/7) Item Symbol Conditions Min. Typ. Max. Unit Output voltage, low V OL1 P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147

DD0 ≤ 5.5 V I OL1 = 20.0 mA 1.3 V IOL1 = 40.0 mANote 1.3 V 4.0 V ≤ EVDD0 ≤ 5.5 V I OL1 = 8.5 mA 0.7 V IOL1 = 17.0 mANote 0.7 V 2.7 V ≤ EVDD0 ≤ 5.5 V I OL1 = 3.0 mA 0.6 V IOL1 = 6.0 mANote 0.6 V 2.7 V ≤ EVDD0 ≤ 5.5 V I OL1 = 1.5 mA 0.4 V IOL1 = 3.0 mANote 0.4 V 1.8 V ≤ EVDD0 ≤ 5.5 V I OL1 = 0.6 mA 0.4 V IOL1 = 1.2 mANote 0.4 V 1.6 V ≤ EVDD0 ≤ 5.5 V I OL1 = 0.3 mA 0.4 V IOL1 = 0.6 mANote 0.4 V VOL2 P20 to P27, P121, P122, P150 to P156 DD ≤ 5.5 V, IOL2 = 8.5 mA 0.7 V 2.7 V ≤ VDD < 4.0 V, IOL2 = 1.5 mA 0.5 V 1.8 V ≤ VDD < 2.7 V, IOL2 = 0.6 mA 0.4 V 1.6 V ≤ VDD < 1.8 V, IOL2 = 0.4 mA 0.4 V VOL3 P60 to P63 4.0 V ≤ EVDD0 ≤ 5.5 V, IOL3 = 15.0 mA 2.0 V 4.0 V ≤ EVDD0 ≤ 5.5 V, IOL3 = 5.0 mA 0.4 V 2.7 V ≤ EVDD0 ≤ 5.5 V, IOL3 = 3.0 mA 0.4 V 1.8 V ≤ EVDD0 ≤ 5.5 V, IOL3 = 2.0 mA 0.4 V 1.6 V ≤ EVDD0 ≤ 5.5 V, IOL3 = 1.0 mA 0.4 V

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 78 of 177 Oct 31, 2025 Note The listed currents apply when the output current control function is enabled. (TA = -40 to +105°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (6/7) Item Symbol Conditions Min. Typ. Max. Unit Output currentNote CCDIOL P16, P17, P50, P51, P60 to P63

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 79 of 177 Oct 31, 2025 Remark The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified. (TA = -40 to +105°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (7/7) Item Symbol Conditions Min. Typ. Max. Unit Input leakage current, high ILIH1 P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P140 to P147 V I = EVDD0 0.5 µA ILIH2 P20 to P27, P137, P150 to P156, RESET VI = VDD 0.5 µA ILIH3 P121 to P124 (X1, X2, XT1, XT2, EXCLK, EXCLKS) VI = VDD 0.5 µA Input leakage current, low I LIL1 P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P140 to P147 V I = EVSS0 -0.5 µA ILIL2 P20 to P27, P137, P150 to P156, RESET VI = VSS -0.5 µA ILIL3 P121 to P124 (X1, X2, XT1, XT2, EXCLK, EXCLKS) V I = VSS -0.5 µA On-chip pll-up resistance RU P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120 to P122, P125 to P127, P140 to P147 V I = EVSS0, In input port 10 20 100 k Ω

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 80 of 177 Oct 31, 2025

2.3.2 Supply current characteristics

30- to 64-pin package products with 96- to 128-Kbyte code flash memory Note 1. The listed currents are the total currents flowing into VDD and EVDD0, including the input leakage currents flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The following points apply in the HS (high-speed main), LS (low- speed main), and LP (low-power main) modes.

The currents in the “Typ.” column do not include the operating currents of the peripheral modules.
The currents in the “Max.” column include the operating currents of the PCLBUZ, TAU, SAU, and IICA modules. Note 2. The listed currents apply when the high-speed system clock, middle-speed on-chip oscillator, low-speed on-chip oscillator, and subsystem clock are stopped. Note 3. The listed currents apply when the high-speed on-chip oscillator, high-speed system clock, low-speed on-chip oscillator, and subsystem clock are stopped. Note 4. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, low-speed on-chip oscillator, and subsystem clock are stopped. (Remarks are listed on the next page.) (TA = -40 to +105°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = 0 V) (1/4) Item Symbol Conditions Min. Typ. Max. Unit Supply current Note 1 IDD1 Operating mode HS (high-speed main) mode f IH = 32 MHzNote 2 Basic operation VDD = 5.0 V 1.3 — mA VDD = 1.8 V 1.3 — Normal operation V DD = 5.0 V 3.0 5.0 mA VDD = 1.8 V 3.0 5.0 LS (low-speed main) mode fIH = 24 MHzNote 2 Normal operation VDD = 5.0 V 2.3 3.8 mA VDD = 1.8 V 2.3 3.8 fIH = 16 MHzNote 2 Normal operation V DD = 5.0 V 1.7 2.7 mA VDD = 1.8 V 1.7 2.7 fIM = 4 MHzNote 3 Normal operation V DD = 5.0 V 0.4 0.7 mA VDD = 1.6 V 0.4 0.7 LP (low-power main) mode f IM = 2 MHzNote 3 Normal operation VDD = 5.0 V 200 325 µA VDD = 1.6 V 200 325 fIM = 1 MHzNote 3 Normal operation V DD = 5.0 V 112 178 µA VDD = 1.6 V 111 176 HS (high-speed main) mode f MX = 20 MHzNote 4, Square wave input Normal operation VDD = 5.0 V 1.9 3.2 mA VDD = 1.8 V 1.9 3.2 LS (low-speed main) mode f MX = 20 MHzNote 4, Square wave input Normal operation V DD = 5.0 V 1.8 3.0 mA VDD = 1.8 V 1.7 3.0 fMX = 20 MHzNote 4, Resonator connection Normal operation V DD = 5.0 V 1.9 3.2 mA VDD = 1.8 V 1.9 3.2 fMX = 10 MHzNote 4, Square wave input Normal operation V DD = 5.0 V 0.9 1.6 mA VDD = 1.8 V 0.9 1.6 fMX = 10 MHzNote 4, Resonator connection Normal operation V DD = 5.0 V 1.0 1.7 mA VDD = 1.8 V 1.0 1.7 fMX = 8 MHzNote 4, Square wave input Normal operation V DD = 5.0 V 0.8 1.3 mA VDD = 1.8 V 0.7 1.3 fMX = 8 MHzNote 4, Resonator connection Normal operation V DD = 5.0 V 0.9 1.4 mA VDD = 1.8 V 0.8 1.4 <R>

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 81 of 177 Oct 31, 2025 Remark 1. fIH: High-speed on-chip oscillator clock frequency Remark 2. fIM: Middle-speed on-chip oscillator clock frequency Remark 3. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 4. The typical value for the ambient operating temperature (TA) is +25°C unless otherwise specified.

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 82 of 177 Oct 31, 2025 1. 30- to 64-pin package products with 96- to 128-Kbyte code flash memory Note 1. The listed currents are the total currents flowing into VDD and EVDD0, including the input leakage currents flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. In the subsystem clock operation mode, the currents in both the “Typ.” and “Max.” columns do not include the operating currents of the peripheral modules. Note 2. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped. Note 3. The listed currents apply when the high-speed on-chip oscillator, high-speed system clock, middle-speed on-chip oscillator, and low-speed on-chip oscillator are stopped, and the low power consumption oscillation 3 is specified (AMPHS1, AMPHS0 = 11B). Remark 1. fIL: Low-speed on-chip oscillator clock frequency Remark 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) (TA = -40 to +105°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = 0 V) (2/4) Item Symbol Conditions Min. Typ. Max. Unit Supply current Note 1 IDD1 Operating mode Subsystem clock operation mode f SUB = 32.768 kHzNote 2, Low-speed on-chip oscillator operation Normal operation T A = -40°C 3.2 5.5 µA TA = +25°C 3.5 5.8 TA = +50°C 3.8 8.5 TA = +105°C 7.7 40.9 fSUB = 32.768 kHzNote 3, Square wave input Normal operation TA = -40°C 3.2 5.6 µA TA = +25°C 3.4 5.7 TA = +50°C 3.7 8.5 TA = +105°C 7.6 39.0 fSUB = 32.768 kHzNote 3, Resonator connection Normal operation T A = -40°C 3.2 5.2 µA TA = +25°C 3.4 5.4 TA = +50°C 3.7 7.7 TA = +105°C 7.7 38.5

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 83 of 177 Oct 31, 2025 1. 30- to 64-pin package products with 96- to 128-Kbyte code flash memory Note 1. The listed currents are the total currents flowing into VDD and EVDD0, including the input leakage currents flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The following points apply in the HS (high-speed main), LS (low- speed main), and LP (low-power main) modes.

The currents in the “Typ.” column do not include the operating currents of the peripheral modules.
The currents in the “Max.” column include the operating currents of the PCLBUZ, TAU, SAU, and IICA modules. Note 2. The listed currents apply when the HALT instruction has been fetched from the flash memory for execution. Note 3. The listed currents apply when the high-speed system clock, middle-speed on-chip oscillator, low-speed on-chip oscillator, and subsystem clock are stopped. Note 4. The listed currents apply when the high-speed on-chip oscillator, high-speed system clock, low-speed on-chip oscillator, and subsystem clock are stopped. Note 5. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, low-speed on-chip oscillator, and subsystem clock are stopped. (Remarks are listed on the next page.) (TA = -40 to +105°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = 0 V) (3/4) Item Symbol Conditions Min. Typ. Max. Unit Supply currentNote 1 IDD2 Note 2 HALT mode HS (high-speed main) mode fIH = 32 MHzNote 3 VDD = 5.0 V 0.54 1.93 mA VDD = 1.8 V 0.53 1.92 LS (low-speed main) mode f IH = 24 MHzNote 3 VDD = 5.0 V 0.45 1.50 mA VDD = 1.8 V 0.44 1.49 fIH = 16 MHzNote 3 VDD = 5.0 V 0.45 1.19 mA VDD = 1.8 V 0.44 1.18 fIM = 4 MHzNote 4 VDD = 5.0 V 0.08 0.26 mA VDD = 1.6 V 0.08 0.26 LP (low-power main) mode f IM = 2 MHzNote 4 VDD = 5.0 V 33 120 µA VDD = 1.6 V 33 120 fIM = 1 MHzNote 4 VDD = 5.0 V 29 76 µA VDD = 1.6 V 28 74 HS (high-speed main) mode f MX = 20 MHzNote 5, Square wave input VDD = 5.0 V 0.22 1.07 mA VDD = 1.8 V 0.19 1.03 LS (low-speed main) mode fMX = 20 MHzNote 5, Square wave input VDD = 5.0 V 0.22 1.07 mA VDD = 1.8 V 0.19 1.03 fMX = 20 MHzNote 5, Resonator connection VDD = 5.0 V 0.40 1.28 mA VDD = 1.8 V 0.39 1.27 fMX = 10 MHzNote 5, Square wave input VDD = 5.0 V 0.14 0.57 mA VDD = 1.8 V 0.12 0.54 fMX = 10 MHzNote 5, Resonator connection VDD = 5.0 V 0.24 0.69 mA VDD = 1.8 V 0.23 0.68 fMX = 8 MHzNote 5, Square wave input VDD = 5.0 V 0.12 0.47 mA VDD = 1.8 V 0.10 0.44 fMX = 8 MHzNote 5, Resonator connection VDD = 5.0 V 0.21 0.58 mA VDD = 1.8 V 0.20 0.57 <R>

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 84 of 177 Oct 31, 2025 Remark 1. fIH: High-speed on-chip oscillator clock frequency Remark 2. fIM: Middle-speed on-chip oscillator clock frequency Remark 3. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 4. The typical value for the ambient operating temperature (TA) is +25°C unless otherwise specified.

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 85 of 177 Oct 31, 2025 1. 30- to 64-pin package products with 96- to 128-Kbyte code flash memory (Notes and Remarks are listed on the next page.) (TA = -40 to +105°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = 0 V) (4/4) Item Symbol Conditions Min. Typ. Max. Unit Supply current Note 1 IDD2 Note 2 HALT mode Subsystem clock operation mode fSUB = 32.768 kHzNote 3, Low-speed on-chip oscillator operation TA = -40°C 0.53 2.31 µA TA = +25°C 0.65 2.38 TA = +50°C 0.80 4.95 TA = +70°C 1.17 9.97 TA = +85°C 1.78 17.96 TA = +105°C 4.41 37.71 fSUB = 32.768 kHzNote 4, Square wave input TA = -40°C 0.20 1.97 µA TA = +25°C 0.29 2.00 TA = +50°C 0.54 5.33 TA = +70°C 0.99 10.94 TA = +85°C 1.70 19.62 TA = +105°C 4.10 41.82 fSUB = 32.768 kHzNote 5, Resonator connection TA = -40°C 0.21 2.04 µA TA = +25°C 0.33 2.28 TA = +50°C 0.49 4.98 TA = +70°C 1.05 11.36 TA = +85°C 1.76 20.04 TA = +105°C 4.20 42.52 IDD3 STOP mode RAMSDS = 0Note 6 TA = -40°C 0.15 1.45 µA TA = +25°C 0.23 1.45 TA = +50°C 0.45 4 TA = +70°C 0.9 9 TA = +85°C 1.6 17 TA = +105°C 4 35 RAMSDS = 1Note 7 TA = -40°C 0.14 1.45 µA TA = +25°C 0.21 1.45 TA = +50°C 0.4 3.5 TA = +70°C 0.8 8.5 TA = +85°C 1.4 15 TA = +105°C 3.2 30 RAMSDS = 1, 128-Hz realtime clock operationNote 8 TA = -40°C 0.22 1.53 µA TA = +25°C 0.32 1.56 TA = +50°C 0.53 3.62 TA = +70°C 0.94 8.64 TA = +85°C 1.55 15.15 TA = +105°C 3.40 30.20

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 86 of 177 Oct 31, 2025 Note 1. The listed currents are the total currents flowing into VDD and EVDD0, including the input leakage currents flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. In the subsystem clock operation mode or the STOP mode, the currents in both the “Typ.” and “Max.” columns do not include the operating currents of the peripheral modules. Note 2. The listed currents apply when the HALT instruction has been fetched from the flash memory for execution. Note 3. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped. Note 4. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, high-speed system clock, and low-speed on-chip oscillator are stopped. Note 5. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, high-speed system clock, and low-speed on-chip oscillator are stopped, and the setting of RTCLPC is 1, and the low power consumption oscillation 3 is specified (AMPHS1, AMPHS0 = 11B). Note 6. The listed currents with this setting allow retention of the contents of the entire RAM area. The listed currents apply when the low-speed on-chip oscillator and subsystem clock oscillation are stopped. For the current for operation of the subsystem clock in the STOP mode, refer to that in the HALT mode. Note 7. The listed currents with this setting allow retention of the contents of a specified 4-Kbyte area of the RAM. The listed currents apply when the low-speed on-chip oscillator and subsystem clock oscillation are stopped. Note 8. The listed currents with this setting allow retention of the contents of a specified 4-Kbyte area of the RAM. The listed currents apply when the low-speed on-chip oscillator is stopped, the setting of RTCLPC is 1, and the low power consumption oscillation 3 is specified (AMPHS1, AMPHS0 = 11B). The current flowing into the RTC is included. Remark 1. f IL: Low-speed on-chip oscillator clock frequency Remark 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 87 of 177 Oct 31, 2025 2. 30- to 64-pin package products with 192- to 256-Kbyte code flash memory and 80-pin package product with 128- to 256-Kbyte code flash memory Note 1. The listed currents are the total currents flowing into VDD and EVDD0, including the input leakage currents flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The following points apply in the HS (high-speed main), LS (low- speed main), and LP (low-power main) modes.

The currents in the “Typ.” column do not include the operating currents of the peripheral modules.
The currents in the “Max.” column include the operating currents of the PCLBUZ, TAU, SAU, and IICA modules. Note 2. The listed currents apply when the high-speed system clock, middle-speed on-chip oscillator, low-speed on-chip oscillator, and subsystem clock are stopped. Note 3. The listed currents apply when the high-speed on-chip oscillator, high-speed system clock, low-speed on-chip oscillator, and subsystem clock are stopped. Note 4. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, low-speed on-chip oscillator, and subsystem clock are stopped. (Remarks are listed on the next page.) (TA = -40 to +105°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = 0 V) (1/4) Item Symbol Conditions Min. Typ. Max. Unit Supply current Note 1 IDD1 Operating mode HS (high-speed main) mode f IH = 32 MHzNote 2 Basic operation VDD = 5.0 V 1.4 ― mA VDD = 1.8 V 1.4 ― Normal operation V DD = 5.0 V 3.0 5.0 mA VDD = 1.8 V 3.0 5.0 LS (low-speed main) mode f IH = 24 MHzNote 2 Normal operation V DD = 5.0 V 2.3 3.8 mA VDD = 1.8 V 2.3 3.8 fIH = 16 MHzNote 2 Normal operation V DD = 5.0 V 1.7 2.8 mA VDD = 1.8 V 1.7 2.7 fIM = 4 MHzNote 3 Normal operation V DD = 5.0 V 0.4 0.7 mA VDD = 1.6 V 0.4 0.7 LP (low-power main) mode f IM = 2 MHzNote 3 Normal operation V DD = 5.0 V 203 329 µA VDD = 1.6 V 202 328 fIM = 1 MHzNote 3 Normal operation V DD = 5.0 V 115 181 µA VDD = 1.6 V 114 180 HS (high-speed main) mode f MX = 20 MHzNote 4, Square wave input Normal operation V DD = 5.0 V 1.9 3.2 mA VDD = 1.8 V 1.9 3.2 LS (low-speed main) mode fMX = 20 MHzNote 4, Square wave input Normal operation VDD = 5.0 V 1.8 3.0 mA VDD = 1.8 V 1.7 3.0 fMX = 20 MHzNote 4, Resonator connection Normal operation V DD = 5.0 V 1.9 3.2 mA VDD = 1.8 V 1.9 3.2 fMX = 10 MHzNote 4, Square wave input Normal operation V DD = 5.0 V 0.9 1.6 mA VDD = 1.8 V 0.9 1.6 fMX = 10 MHzNote 4, Resonator connection Normal operation V DD = 5.0 V 1.0 1.7 mA VDD = 1.8 V 1.0 1.7 fMX = 8 MHzNote 4, Square wave input Normal operation V DD = 5.0 V 0.8 1.3 mA VDD = 1.8 V 0.7 1.3 fMX = 8 MHzNote 4, Resonator connection Normal operation V DD = 5.0 V 0.9 1.4 mA VDD = 1.8 V 0.8 1.4 <R>

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 88 of 177 Oct 31, 2025 Remark 1. fIH: High-speed on-chip oscillator clock frequency Remark 2. fIM: Middle-speed on-chip oscillator clock frequency Remark 3. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 4. The typical value for the ambient operating temperature (TA) is +25°C unless otherwise specified.

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 89 of 177 Oct 31, 2025 2. 30- to 64-pin package products with 192- to 256-Kbyte code flash memory and 80-pin package product with 128- to 256-Kbyte code flash memory Note 1. The listed currents are the total currents flowing into VDD and EVDD0, including the input leakage currents flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. In the subsystem clock operation mode, the currents in both the “Typ.” and “Max.” columns do not include the operating currents of the peripheral modules. Note 2. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped. Note 3. The listed currents apply when the high-speed on-chip oscillator, high-speed system clock, middle-speed on-chip oscillator, and low-speed on-chip oscillator are stopped, and the low power consumption oscillation 3 is specified (AMPHS1, AMPHS0 = 11B). Remark 1. fIL: Low-speed on-chip oscillator clock frequency Remark 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) (TA = -40 to +105°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = 0 V) (2/4) Item Symbol Conditions Min. Typ. Max. Unit Supply current Note 1 IDD1 Operating mode Subsystem clock operation mode f SUB = 32.768 kHzNote 2, Low-speed on-chip oscillator operation Normal operation T A = -40°C 3.3 6.1 µA TA = +25°C 3.6 6.3 TA = +50°C 3.9 9.6 TA = +105°C 7.8 56.3 fSUB = 32.768 kHzNote 3, Square wave input Normal operation T A = -40°C 3.3 6.1 µA TA = +25°C 3.5 6.4 TA = +50°C 3.8 9.6 TA = +105°C 7.8 57.0 fSUB = 32.768 kHzNote 3, Resonator connection Normal operation T A = -40°C 3.3 6.0 µA TA = +25°C 3.5 6.0 TA = +50°C 3.8 8.9 TA = +105°C 7.9 55.3

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 90 of 177 Oct 31, 2025 2. 30- to 64-pin package products with 192- to 256-Kbyte code flash memory and 80-pin package product with 128- to 256-Kbyte code flash memory Note 1. The listed currents are the total currents flowing into VDD and EVDD0, including the input leakage currents flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The following points apply in the HS (high-speed main), LS (low- speed main), and LP (low-power main) modes.

The currents in the “Typ.” column do not include the operating currents of the peripheral modules.
The currents in the “Max.” column include the operating currents of the PCLBUZ, TAU, SAU, and IICA modules. Note 2. The listed currents apply when the HALT instruction has been fetched from the flash memory for execution. Note 3. The listed currents apply when the high-speed system clock, middle-speed on-chip oscillator, low-speed on-chip oscillator, and subsystem clock are stopped. Note 4. The listed currents apply when the high-speed on-chip oscillator, high-speed system clock, low-speed on-chip oscillator, and subsystem clock are stopped. Note 5. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, low-speed on-chip oscillator, and subsystem clock are stopped. (Remarks are listed on the next page.) (TA = -40 to +105°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = 0 V) (3/4) Item Symbol Conditions Min. Typ. Max. Unit Supply currentNote 1 IDD2 Note 2 HALT mode HS (high-speed main) mode fIH = 32 MHzNote 3 VDD = 5.0 V 0.57 1.97 mA VDD = 1.8 V 0.56 1.96 LS (low-speed main) mode f IH = 24 MHzNote 3 VDD = 5.0 V 0.47 1.53 mA VDD = 1.8 V 0.47 1.52 fIH = 16 MHzNote 3 VDD = 5.0 V 0.48 1.22 mA VDD = 1.8 V 0.47 1.21 fIM = 4 MHzNote 4 VDD = 5.0 V 0.08 0.27 mA VDD = 1.6 V 0.08 0.26 LP (low-power main) mode fIM = 2 MHzNote 4 VDD = 5.0 V 38 126 µA VDD = 1.6 V 37 125 fIM = 1 MHzNote 4 VDD = 5.0 V 32 79 µA VDD = 1.6 V 32 79 HS (high-speed main) mode fMX = 20 MHzNote 5, Square wave input VDD = 5.0 V 0.23 1.07 mA VDD = 1.8 V 0.19 1.03 LS (low-speed main) mode f MX = 20 MHzNote 5, Square wave input VDD = 5.0 V 0.23 1.07 mA VDD = 1.8 V 0.19 1.03 fMX = 20 MHzNote 5, Resonator connection VDD = 5.0 V 0.41 1.30 mA VDD = 1.8 V 0.40 1.28 fMX = 10 MHzNote 5, Square wave input VDD = 5.0 V 0.14 0.57 mA VDD = 1.8 V 0.12 0.54 fMX = 10 MHzNote 5, Resonator connection VDD = 5.0 V 0.24 0.69 mA VDD = 1.8 V 0.23 0.68 fMX = 8 MHzNote 5, Square wave input VDD = 5.0 V 0.12 0.47 mA VDD = 1.8 V 0.10 0.44 fMX = 8 MHzNote 5, Resonator connection VDD = 5.0 V 0.21 0.58 mA VDD = 1.8 V 0.20 0.57 <R>

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 91 of 177 Oct 31, 2025 Remark 1. fIH: High-speed on-chip oscillator clock frequency Remark 2. fIM: Middle-speed on-chip oscillator clock frequency Remark 3. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 4. The typical value for the ambient operating temperature (TA) is +25°C unless otherwise specified.

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 92 of 177 Oct 31, 2025 2. 30- to 64-pin package products with 192- to 256-Kbyte code flash memory and 80-pin package product with 128- to 256-Kbyte code flash memory (Notes and Remarks are listed on the next page.) (TA = -40 to +105°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = 0 V) (4/4) Item Symbol Conditions Min. Typ. Max. Unit Supply current Note 1 IDD2 Note 2 HALT mode Subsystem clock operation mode fSUB = 32.768 kHzNote 3, Low-speed on-chip oscillator operation T A = -40°C 0.62 2.94 µA TA = +25°C 0.74 3.00 TA = +50°C 0.88 6.00 TA = +70°C 1.22 12.01 TA = +85°C 2.69 22.92 TA = +105°C 5.08 54.47 fSUB = 32.768 kHz, Square wave inputNote 4 TA = -40°C 0.25 2.54 µA TA = +25°C 0.37 2.73 TA = +50°C 0.74 7.35 TA = +70°C 1.33 15.13 TA = +85°C 2.35 27.33 TA = +105°C 4.81 62.95 fSUB = 32.768 kHz, Resonator connectionNote 5 TA = -40°C 0.27 2.68 µA TA = +25°C 0.39 2.87 TA = +50°C 0.78 7.63 TA = +70°C 1.34 15.20 TA = +85°C 2.35 27.33 TA = +105°C 4.67 61.97 IDD3 STOP mode RAMSDS = 0Note 6 TA = -40°C 0.19 2.00 µA TA = +25°C 0.30 2.00 TA = +50°C 0.65 5.00 TA = +70°C 1.20 11.00 TA = +85°C 2.20 20.00 TA = +105°C 4.50 50.00 RAMSDS = 1Note 7 TA = -40°C 0.18 2.00 µA TA = +25°C 0.29 2.00 TA = +50°C 0.60 4.50 TA = +70°C 1.10 10.00 TA = +85°C 2.00 19.00 TA = +105°C 4.00 45.00 RAMSDS = 1, 128-Hz realtime clock operationNote 8 TA = -40°C 0.23 2.05 µA TA = +25°C 0.40 2.11 TA = +50°C 0.72 4.62 TA = +70°C 1.23 10.13 TA = +85°C 2.14 19.14 TA = +105°C 4.16 45.16

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 93 of 177 Oct 31, 2025 Note 1. The listed currents are the total currents flowing into VDD and EVDD0, including the input leakage currents flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. In the subsystem clock operation mode or the STOP mode, the currents in both the “Typ.” and “Max.” columns do not include the operating currents of the peripheral modules. Note 2. The listed currents apply when the HALT instruction has been fetched from the flash memory for execution. Note 3. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped. Note 4. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, high-speed system clock, and low-speed on-chip oscillator are stopped. Note 5. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, high-speed system clock, and low-speed on-chip oscillator are stopped, and the setting of RTCLPC is 1, and the low power consumption oscillation 3 is specified (AMPHS1, AMPHS0 = 11B). Note 6. The listed currents with this setting allow retention of the contents of the entire RAM area. The listed currents apply when the low-speed on-chip oscillator and subsystem clock oscillation are stopped. For the current for operation of the subsystem clock in the STOP mode, refer to that in the HALT mode. Note 7. The listed currents with this setting allow retention of the contents of a specified 4-Kbyte area of the RAM. The listed currents apply when the low-speed on-chip oscillator and subsystem clock oscillation are stopped. Note 8. The listed currents with this setting allow retention of the contents of a specified 4-Kbyte area of the RAM. The listed currents apply when the low-speed on-chip oscillator is stopped, the setting of RTCLPC is 1, and the low power consumption oscillation 3 is specified (AMPHS1, AMPHS0 = 11B). The current flowing into the RTC is included. Remark 1. f IL: Low-speed on-chip oscillator clock frequency Remark 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 94 of 177 Oct 31, 2025 3. 44- to 80-pin package products with 384- to 768-Kbyte code flash memory and 100- to 128-pin package products Note 1. The listed currents are the total currents flowing into VDD, EVDD0 and EVDD1, including the input leakage currents flowing when the level of the input pin is fixed to VDD, EVDD0, EVDD1 or VSS, EVSS0, EVSS1. The following points apply in the HS (high-speed main), LS (low-speed main), and LP (low-power main) modes.

The currents in the “Typ.” column do not include the operating currents of the peripheral modules.
The currents in the “Max.” column include the operating currents of the PCLBUZ, TAU, SAU, and IICA modules. Note 2. The listed currents apply when the high-speed system clock, middle-speed on-chip oscillator, low-speed on-chip oscillator, and subsystem clock are stopped. Note 3. The listed currents apply when the high-speed on-chip oscillator, high-speed system clock, low-speed on-chip oscillator, and subsystem clock are stopped. Note 4. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, low-speed on-chip oscillator, and subsystem clock are stopped. (Remarks are listed on the next page.) (TA = -40 to +105°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/4) Item Symbol Conditions Min. Typ. Max. Unit Supply current Note 1 IDD1 Operating mode HS (high-speed main) mode f IH = 32 MHzNote 2 Basic operation VDD = 5.0 V 1.6 ― mA VDD = 1.8 V 1.5 ― Normal operation V DD = 5.0 V 3.5 5.6 mA VDD = 1.8 V 3.5 5.6 LS (low-speed main) mode f IH = 24 MHzNote 2 Normal operation VDD = 5.0 V 2.6 4.2 mA VDD = 1.8 V 2.6 4.2 fIH = 16 MHzNote 2 Normal operation VDD = 5.0 V 2.0 3.1 mA VDD = 1.8 V 1.9 3.1 fIM = 4 MHzNote 3 Normal operation V DD = 5.0 V 0.5 0.9 mA VDD = 1.6 V 0.5 0.8 LP (low-power main) mode f IM = 2 MHzNote 3 Normal operation VDD = 5.0 V 229 361 µA VDD = 1.6 V 227 358 fIM = 1 MHzNote 3 Normal operation V DD = 5.0 V 128 197 µA VDD = 1.6 V 125 193 HS (high-speed main) mode f MX = 20 MHzNote 4, Square wave input Normal operation VDD = 5.0 V 2.2 3.5 mA VDD = 1.8 V 2.2 3.5 LS (low-speed main) mode f MX = 20 MHzNote 4, Square wave input Normal operation V DD = 5.0 V 2.1 3.4 mA VDD = 1.8 V 2.0 3.3 fMX = 20 MHzNote 4, Resonator connection Normal operation V DD = 5.0 V 2.2 3.6 mA VDD = 1.8 V 2.2 3.5 fMX = 10 MHzNote 4, Square wave input Normal operation V DD = 5.0 V 1.1 1.8 mA VDD = 1.8 V 1.1 1.8 fMX = 10 MHzNote 4, Resonator connection Normal operation V DD = 5.0 V 1.2 1.9 mA VDD = 1.8 V 1.2 1.9 fMX = 8 MHzNote 4, Square wave input Normal operation V DD = 5.0 V 0.9 1.5 mA VDD = 1.8 V 0.9 1.5 fMX = 8 MHzNote 4, Resonator connection Normal operation V DD = 5.0 V 1.0 1.6 mA VDD = 1.8 V 1.0 1.6 <R>

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 95 of 177 Oct 31, 2025 Remark 1. fIH: High-speed on-chip oscillator clock frequency Remark 2. fIM: Middle-speed on-chip oscillator clock frequency Remark 3. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 4. The typical value for the ambient operating temperature (TA) is +25°C unless otherwise specified.

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 96 of 177 Oct 31, 2025 3. 44- to 80-pin package products with 384- to 768-Kbyte code flash memory and 100- to 128-pin package products Note 1. The listed currents are the total currents flowing into VDD, EVDD0 and EVDD1, including the input leakage currents flowing when the level of the input pin is fixed to VDD, EVDD0, EVDD1 or VSS, EVSS0, EVSS1. In the subsystem clock operation mode, the currents in both the “Typ.” and “Max.” columns do not include the operating currents of the peripheral modules. Note 2. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped. Note 3. The listed currents apply when the high-speed on-chip oscillator, high-speed system clock, middle-speed on-chip oscillator, and low-speed on-chip oscillator are stopped, and the low power consumption oscillation 3 is specified (AMPHS1, AMPHS0 = 11B). Remark 1. fIL: Low-speed on-chip oscillator clock frequency Remark 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) (TA = -40 to +105°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/4) Item Symbol Conditions Min. Typ. Max. Unit Supply current Note 1 IDD1 Operating mode Subsystem clock operation mode f SUB = 32.768 kHzNote 2, Low-speed on-chip oscillator operation Normal operation T A = -40°C 3.8 7.7 µA TA = +25°C 4.1 8.0 TA = +105°C 11.1 88.8 fSUB = 32.768 kHzNote 3, Square wave input Normal operation TA = -40°C 3.8 7.7 µA TA = +25°C 4.0 8.0 TA = +105°C 10.7 88.1 fSUB = 32.768 kHzNote 3, Resonator connection Normal operation T A = -40°C 3.8 7.4 µA TA = +25°C 4.1 7.8 TA = +105°C 10.8 87.4

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 97 of 177 Oct 31, 2025 3. 44- to 80-pin package products with 384- to 768-Kbyte code flash memory and 100- to 128-pin package products Note 1. The listed currents are the total currents flowing into VDD, EVDD0 and EVDD1, including the input leakage currents flowing when the level of the input pin is fixed to VDD, EVDD0, EVDD1 or VSS, EVSS0, EVSS1. The following points apply in the HS (high-speed main), LS (low-speed main), and LP (low-power main) modes.

The currents in the “Typ.” column do not include the operating currents of the peripheral modules.
The currents in the “Max.” column include the operating currents of the PCLBUZ, TAU, SAU, and IICA modules. Note 2. The listed currents apply when the HALT instruction has been fetched from the flash memory for execution. Note 3. The listed currents apply when the high-speed system clock, middle-speed on-chip oscillator, low-speed on-chip oscillator, and subsystem clock are stopped. Note 4. The listed currents apply when the high-speed on-chip oscillator, high-speed system clock, low-speed on-chip oscillator, and subsystem clock are stopped. Note 5. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, low-speed on-chip oscillator, and subsystem clock are stopped. (Remarks are listed on the next page.) (TA = -40 to +105°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (3/4) Item Symbol Conditions Min. Typ. Max. Unit Supply currentNote 1 IDD2 Note 2 HALT mode HS (high-speed main) mode fIH = 32 MHzNote 3 VDD = 5.0 V 0.60 2.00 mA VDD = 1.8 V 0.59 1.99 LS (low-speed main) mode f IH = 24 MHzNote 3 VDD = 5.0 V 0.49 1.56 mA VDD = 1.8 V 0.48 1.55 fIH = 16 MHzNote 3 VDD = 5.0 V 0.49 1.24 mA VDD = 1.8 V 0.48 1.23 fIM = 4 MHzNote 4 VDD = 5.0 V 0.09 0.28 mA VDD = 1.6 V 0.09 0.27 LP (low-power main) mode f IM = 2 MHzNote 4 VDD = 5.0 V 40 129 µA VDD = 1.6 V 37 125 fIM = 1 MHzNote 4 VDD = 5.0 V 33 80 µA VDD = 1.6 V 32 79 HS (high-speed main) mode f MX = 20 MHzNote 5, Square wave input VDD = 5.0 V 0.25 1.10 mA VDD = 1.8 V 0.21 1.05 LS (low-speed main) mode fMX = 20 MHzNote 5, Square wave input VDD = 5.0 V 0.25 1.10 mA VDD = 1.8 V 0.21 1.05 fMX = 20 MHzNote 5, Resonator connection VDD = 5.0 V 0.41 1.30 mA VDD = 1.8 V 0.40 1.28 fMX = 10 MHzNote 5, Square wave input VDD = 5.0 V 0.15 0.59 mA VDD = 1.8 V 0.13 0.55 fMX = 10 MHzNote 5, Resonator connection VDD = 5.0 V 0.25 0.70 mA VDD = 1.8 V 0.24 0.69 fMX = 8 MHzNote 5, Square wave input VDD = 5.0 V 0.13 0.48 mA VDD = 1.8 V 0.11 0.45 fMX = 8 MHzNote 5, Resonator connection VDD = 5.0 V 0.22 0.59 mA VDD = 1.8 V 0.21 0.58 <R>

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 98 of 177 Oct 31, 2025 Remark 1. fIH: High-speed on-chip oscillator clock frequency Remark 2. fIM: Middle-speed on-chip oscillator clock frequency Remark 3. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 4. The typical value for the ambient operating temperature (TA) is +25°C unless otherwise specified.

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 99 of 177 Oct 31, 2025 3. 44- to 80-pin package products with 384- to 768-Kbyte code flash memory and 100- to 128-pin package products (Notes and Remarks are listed on the next page.) (TA = -40 to +105°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (4/4) Item Symbol Conditions Min. Typ. Max. Unit Supply current Note 1 IDD2 Note 2 HALT mode Subsystem clock operation mode fSUB = 32.768 kHzNote 3, Low-speed on-chip oscillator operation TA = -40°C 0.62 3.95 µA TA = +25°C 0.78 4.00 TA = +50°C 1.03 9.16 TA = +70°C 1.62 19.34 TA = +85°C 3.50 37.35 TA = +105°C 6.77 85.36 fSUB = 32.768 kHz, Square wave inputNote 4 TA = -40°C 0.25 3.55 µA TA = +25°C 0.41 3.73 TA = +50°C 0.90 10.93 TA = +70°C 1.76 23.42 TA = +85°C 2.92 41.07 TA = +105°C 6.27 94.30 fSUB = 32.768 kHz, Resonator connectionNote 5 TA = -40°C 0.27 3.62 µA TA = +25°C 0.43 3.87 TA = +50°C 0.92 11.07 TA = +70°C 1.79 23.63 TA = +85°C 2.94 41.21 TA = +105°C 6.28 94.37 IDD3 STOP mode RAMSDS = 0Note 6 TA = -40°C 0.21 3.00 µA TA = +25°C 0.35 3.00 TA = +50°C 0.75 8.00 TA = +70°C 1.60 18.00 TA = +85°C 2.80 34.00 TA = +105°C 6.00 80.00 RAMSDS = 1Note 7 TA = -40°C 0.19 3.00 µA TA = +25°C 0.32 3.00 TA = +50°C 0.65 7.00 TA = +70°C 1.25 17.00 TA = +85°C 2.10 30.00 TA = +105°C 4.50 70.00 RAMSDS = 1, 128-Hz realtime clock operationNote 8 TA = -40°C 0.27 3.08 µA TA = +25°C 0.42 3.10 TA = +50°C 0.76 7.11 TA = +70°C 1.38 17.13 TA = +85°C 2.23 30.13 TA = +105°C 4.64 70.14

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 100 of 177 Oct 31, 2025 Note 1. The listed currents are the total currents flowing into VDD, EVDD0 and EVDD1, including the input leakage currents flowing when the level of the input pin is fixed to VDD, EVDD0, EVDD1 or VSS, EVSS0, EVSS1. In the subsystem clock operation mode or the STOP mode, the currents in both the “Typ.” and “Max.” columns do not include the operating currents of the peripheral modules. Note 2. The listed currents apply when the HALT instruction has been fetched from the flash memory for execution. Note 3. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped. Note 4. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, high-speed system clock, and low-speed on-chip oscillator are stopped. Note 5. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, high-speed system clock, and low-speed on-chip oscillator are stopped, and the setting of RTCLPC is 1, and the low power consumption oscillation 3 is specified (AMPHS1, AMPHS0 = 11B). Note 6. The listed currents with this setting allow retention of the contents of the entire RAM area. The listed currents apply when the low-speed on-chip oscillator and subsystem clock oscillation are stopped. For the current for operation of the subsystem clock in the STOP mode, refer to that in the HALT mode. Note 7. The listed currents with this setting allow retention of the contents of a specified 4-Kbyte area of the RAM. The listed currents apply when the low-speed on-chip oscillator and subsystem clock oscillation are stopped. Note 8. The listed currents with this setting allow retention of the contents of a specified 4-Kbyte area of the RAM. The listed currents apply when the low-speed on-chip oscillator is stopped, the setting of RTCLPC is 1, and the low power consumption oscillation 3 is specified (AMPHS1, AMPHS0 = 11B). The current flowing into the RTC is included. Remark 1. f IL: Low-speed on-chip oscillator clock frequency Remark 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 101 of 177 Oct 31, 2025 4. Peripheral Functions (Common to all products) (TA = -40 to +105°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2) Item Symbol Conditions Min. Typ. Max. Unit High-speed on- chip oscillator operating current IFIHNote 1 380 µA Middle-speed on- chip oscillator operating current I FIMNote 1 20 µA Low-speed on- chip oscillator operating current I FILNote 1 0.3 µA RTC operating current I RTC Notes 1, 2, 3 fRTCCLK = 32.768 kHz 0.005 µA fRTCCLK = 128 Hz 0.002 µA 32-bit interval timer operating current I IT Notes 1, 2, 4 0.04 µA Watchdog timer operating current IWDT Notes 1, 2, 5 fIL = 32.768 kHz (typ.) 0.32 µA A/D converter operating current I ADC Notes 1, 6 When conversion at maximum speed Normal mode, AV REFP = VDD = 5.0 V 0.95 1.6 mA Low voltage mode, AVREFP = VDD = 3.0 V 0.5 0.75 mA AVREFP current I ADREF Note 7 AVREFP = 5.0 V 52 µA A/D converter internal reference voltage current I ADREF Note 1 114 µA Temperature sensor operating current ITMPSNote 1 110 µA D/A converter operating current I DAC Notes 1, 8 Per channel 150 µA Comparator operating current ICMP Notes 1, 9 6µ A LVD operating current ILVD0 Notes 1, 10 0.02 µA ILVD1 Notes 1, 10 0.02 µA Self-programming operating current I FSP Notes 1, 11 2.5 12.2 mA Data flash memory rewrite operating current I BGO Notes 1, 12 2.5 12.2 mA

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 102 of 177 Oct 31, 2025 (Notes and Remarks continue on the next page.) (TA = -40 to +105°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2) Item Symbol Conditions Min. Typ. Max. Unit SNOOZE mode sequencer operating current I SMS Notes 1, 13 fIH = 32 MHz 30- to 64-pin package products with 96- to 128-Kbyte code flash memory 1.1 mA 30- to 64-pin package products with 192- to 256-Kbyte code flash memory and 80-pin package product with 128- to 256-Kbyte code flash memory 1.1 44- to 80-pin package products with 384- to 768-Kbyte code flash memory and 100- to 128-pin package products 1.4 f IL = 32.768 kHz 30- to 64-pin package products with 96- to 128-Kbyte code flash memory 1.2 µA 30- to 64-pin package products with 192- to 256-Kbyte code flash memory and 80-pin package product with 128- to 256-Kbyte code flash memory 1.2 44- to 80-pin package products with 384- to 768-Kbyte code flash memory and 100- to 128-pin package products 1.6 SNOOZE operating current I SNOZ Note 1 fIH=32 MHz ADC to be in use The ADC is shifting from the STOP mode to the SNOOZE mode.Note 14 0.6 0.81 mA The ADC is operating in the low-voltage mode. AVREFP = VDD = 3.0 V 1.2 1.56 Simplified SPI (CSI)/UART to be in use 0.7 0.92 mA SMSNote 15 30- to 64-pin package products with 96- to 128-Kbyte code flash memory 1.6 mA 30- to 64-pin package products with 192- to 256-Kbyte code flash memory and 80-pin package product with 128- to 256-Kbyte code flash memory 1.7 44- to 80-pin package products with 384- to 768-Kbyte code flash memory, and 100- to 128-pin package products 2.0 Remote control signal receiver operating current I REM Notes 1, 16 0.03 µA Low-speed peripheral clock supply current ISXP Notes 1, 17 RTCLPC = 0 0.22 µA Output current control operating current I CCDA Notes 1, 18 The setting of the CCDE register is not 00H. 100 µA ICCDP Notes 19, 20 Per single output current control port Setting of the low-level output current: Hi-Z 30 µA Setting of the low-level output current: 2 to 15 mA 200 µA Operating current of the true random number generator ITRNG Note 1 1.1 mA

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 103 of 177 Oct 31, 2025 Note 1. This current flows into VDD. Note 2. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, and high-speed system clock are stopped. Note 3. This current flows into the realtime clock (RTC). It does not include the operating current of the low-speed on-chip oscillator or the XT1 oscillator. The supply current of the RL78 microcontrollers is the sum of either IDD1 or IDD2, and IRTC, when the realtime clock is operating or in the HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be included in the supply current. IDD2 in the subsystem clock operation mode includes the operating current of the realtime clock. Note 4. This current only flows to the 32-bit interval timer. It does not include the operating current of the low-speed on-chip oscillator or the XT1 oscillator. The supply current of the RL78 microcontrollers is the sum of either IDD1 or IDD2, and IIT, when the 32- bit interval timer is operating or in the HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be included in the supply current. Note 5. This current only flows to the watchdog timer. It includes the operating current of the low-speed on-chip oscillator. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer is operating. Note 6. This current only flows to the A/D converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and IADC when the A/D converter is operating or in the HALT mode. Note 7. This current flows into AVREFP. Note 8. This current only flows to the D/A converter. The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IDAC, when the D/A converter is operating or in the HALT mode. Note 9. This current only flows to the comparator. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and ICMP when the comparator is in operation. Note 10. This current only flows to the LVD circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and ILVD when the LVD circuit is in operation. Note 11. This current only flows during self programming. Note 12. This current only flows while the data flash memory is being rewritten. Note 13. This current only flows into the SNOOZE mode sequencer. Note that the operating current of the low-speed on-chip oscillator and the XT1 oscillator are not included. The supply current of the RL78 microcontrollers is the sum of either IDD1 or IDD2, and ISMS, when the SNOOZE mode sequencer is operating or in the HALT mode. Note 14. For shift time to the SNOOZE mode, see 23.3.3 SNOOZE mode in the RL78/G23 User’s Manual. Note 15. The listed values apply when the SNOOZE mode sequencer is in normal operation equivalent to IDD1. They do not include the current flowing into the peripheral functions other than the SNOOZE mode sequencer. Note 16. This current flows into the remote control signal receiver. It does not include the operating current of the low-speed on-chip oscillator or the XT1 oscillator. The supply current of the RL78 microcontrollers is the sum of either IDD1 or IDD2, and IIT, when the remote control signal receiver is operating or in the HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be included in the supply current. Note 17. This current is added to the supply current in the HALT mode when the setting of RTCLPC is 0 in the STOP mode, or when the setting of RTCLPC is 0 with the subsystem clock X (f SX) selected as the CPU clock, while the subsystem clock X (fsx) is oscillating. Note 18. This current is added to the supply current when the output voltage control port is set. Note 19. This current does not include the current flowing into the I/O port pins. Note 20. This current only flows to EVDD0 and EVDD1. Remark 1. fIL: Low-speed on-chip oscillator clock frequency Remark 2. fSX: Subsystem clock X frequency Remark 3. fCLK: CPU/peripheral hardware clock frequency Remark 4. The typical value for the ambient operating temperature (TA) is +25°C unless otherwise specified.

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 104 of 177 Oct 31, 2025

2.4 AC Characteristics

(Note and Remark are listed on the next page.) (TA = -40 to +105°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Item Symbol Conditions Min. Typ. Max. Unit Instruction cycle (minimum instruction execution time) TCY Main system clock (fMAIN) operation HS (high-speed main) mode

1.8 V ≤ V

DD ≤ 5.5 V 0.03125 1 µs 1.6 V ≤ VDD ≤ 1.8 V 0.25 1 µs LS (low-speed main) mode DD ≤ 5.5 V 0.04167 1 µs 1.6 V ≤ VDD ≤ 1.8 V 0.25 1 µs LP (low-power main) mode

1.6 V ≤ V

DD ≤ 5.5 V 0.5 1 µs In the self programming mode HS (high-speed main) mode DD ≤ 5.5 V 0.03125 1 µs 1.6 V ≤ VDD ≤ 1.8 V 0.5 1 µs LS (low-speed main) mode DD ≤ 5.5 V 0.04167 1 µs 1.6 V ≤ VDD ≤ 1.8 V 0.5 1 µs External system clock frequency f EX 1.8 V ≤ VDD ≤ 5.5 V 1.0 20.0 MHz 1.6 V ≤ VDD < 1.8 V 1.0 4.0 MHz fEXS 32 38.4 kHz External system clock input high-level width, low-level width t EXH, tEXL 1.8 V ≤ VDD ≤ 5.5 V 24 ns 1.6 V ≤ VDD < 1.8 V 120 ns tEXHS, tEXLS 13.7 µs TI00 to TI07, TI10 to TI17 input high-level width, low-level width t TIH, tTIL 1/fMCK + 10 nsNote TO00 to TO07, TO10 to TO17 output frequency f TO HS (high-speed main) mode LS (low-speed main) mode DD0 ≤ 5.5 V 16 MHz 2.7 V ≤ EVDD0 < 4.0 V 8 MHz 1.8 V ≤ EVDD0 < 2.7 V 4 MHz 1.6 V ≤ EVDD0 < 1.8 V 2 MHz LP (low-power main) mode 1.6 V ≤ EVDD0 ≤ 5.5 V 2 MHz PCLBUZ0, PCLBUZ1 output frequency fPCL HS (high-speed main) mode LS (low-speed main) mode DD0 ≤ 5.5 V 16 MHz 2.7 V ≤ EVDD0 < 4.0 V 8 MHz 1.8 V ≤ EVDD0 < 2.7 V 4 MHz 1.6 V ≤ EVDD0 < 1.8 V 2 MHz LP (low-power main) mode 1.6 V ≤ EVDD0 < 1.8 V 2 MHz Interrupt input high-level width, low-level width t INTH, tINTL INTP0 1.6 V ≤ VDD ≤ 5.5 V 1 µs INTP1 to INTP11 1.6 V ≤ EVDD0 ≤ 5.5 V 1 µs Key interrupt input high- level width, low-level width tKRH, tKRL KR0 to KR7 1.8 V ≤ EVDD0 ≤ 5.5 V 250 ns 1.6 V ≤ EVDD0 < 1.8 V 1 µs RESET low-level width t RSL 10 µs <R> <R>

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 105 of 177 Oct 31, 2025 Note The following conditions are required for low voltage interface when EVDD0 < VDD. 1.8 V ≤ EVDD0 < 2.7 V: 125 ns min. 1.6 V ≤ EVDD0 < 1.8 V: 250 ns min. Remark fMCK: Timer array unit operating clock frequency (To set this operating clock, use the CKSmn0 and CKSmn1 bits of the timer mode register mn (TMRmn) (m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7).)

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 106 of 177 Oct 31, 2025 Minimum Instruction Execution Time during Main System Clock Operation TCY vs VDD (HS (high-speed main) mode) TCY vs VDD (LS (low-speed main) mode) In normal operation During self programming Supply voltage VDD [V] 1.0 0.1 1.8 0.01 1.6 0.03125 0.25 0.05 Cycle time TCY [µs] 5.5 0.5 In normal operation During self programming Supply voltage VDD [V] 1.0 0.1 1.8 0.01 1.6 0.04167 0.25 0.05 Cycle time TCY [µs] 5.5 0.5

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 107 of 177 Oct 31, 2025 TCY vs VDD (LP (low-power main) mode) In normal operation Supply voltage VDD [V] 1.0 0.1 0.01 1.6 0.05 Cycle time TCY [µs] 5.5 0.5

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 108 of 177 Oct 31, 2025 AC Timing Test Points External System Clock Timing TI/TO Timing VIH/VOH VIL/VOL VIH/VOHTest points VIL/VOL EXCLK/EXCLKS 1/fEX/ 1/fEXS tEXL/ tEXLS tEXH/ tEXHS tTIL tTIH 1/fTO TI00 to TI07, TI10 to TI17 TO00 to TO07, TO10 to TO17

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 109 of 177 Oct 31, 2025 Interrupt Request Input Timing Key Interrupt Input Timing RESET Input Timing INTP0 to INTP11 tINTL tINTH KR0 to KR7 tKRL tKRH tRSL RESET

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 110 of 177 Oct 31, 2025

2.5 Characteristics of the Peripheral Functions

2.5.1 Serial array unit

In UART communications with devices operating at same voltage levels Note 1. The transfer rate in the SNOOZE mode is within the range from 4800 to 9600 bps. Note 2. The following conditions are required for low voltage interface when EVDD0 < VDD. 2.4 V ≤ EVDD0 < 2.7 V: 2.6 Mbps max. 1.8 V ≤ EVDD0 < 2.4 V: 1.3 Mbps max. 1.6 V ≤ EVDD0 < 1.8 V: 0.6 Mbps max. Note 3. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are as follows. Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using a port input mode register (PIMg) and port output mode register (POMg). (TA = -40 to +105°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Item Symbol Conditions HS (High-Speed Main) Mode LS (Low-Speed Main) Mode LP (Low-Power Main) Mode Unit Transfer rate Note 1 1.6 V ≤ EVDD0 ≤ 5.5 V f MCK/6 Note 2 fMCK/6 Note 2 fMCK/6 bps Theoretical value of the maximum transfer rate fMCK = fCLKNote 3 5.3 4 0.33 Mbps HS (high-speed main) mode : 32 MHz (1.8 V ≤ VDD ≤ 5.5 V) 4 MHz (1.6 V ≤ VDD ≤ 5.5 V) LS (low-speed main) mode : 24 MHz (1.8 V ≤ VDD ≤ 5.5 V) 4 MHz (1.6 V ≤ VDD ≤ 5.5 V) LP (low-power main) mode : 2 MHz (1.6 V ≤ VDD ≤ 5.5 V) VIH/VOH VIL/VOL VIH/VOHTest points VIL/VOL

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 111 of 177 Oct 31, 2025 Connection in the UART communications with devices operating at same voltage levels Bit width in the UART communications when interfacing devices operate at the same voltage level (reference) Remark 1. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14) Remark 2. fMCK: Serial array unit operation clock frequency (To set this operating clock, set the CKSmn bit in the serial mode register mn (SMRmn) (m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13).) TxDq RxDq User device Rx Tx RL78 microcontroller Baud rate error tolerance TxDq RxDq Low-/high-bit width 1/Transfer rate

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 112 of 177 Oct 31, 2025 2. In simplified SPI (CSI) communications in the master mode with devices operating at same voltage levels with the internal SCKp clock (the ratings below are only applicable to CSI00) Note 1. The setting applies when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The setting for the SIp setup time becomes “to SCKp↓” and that for the SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 2. This setting applies when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The setting for the delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 3. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using a port input mode register (PIMg) and port output mode register (POMg). Remark 1. The listed times are only valid when the peripheral I/O redirect function of CSI00 is not in use. Remark 2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM numbers (g = 1) Remark 3. fMCK: Serial array unit operation clock frequency (To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn) (m: Unit number, n: Channel number (mn = 00).) (TA = -40 to +85°C, 2.7 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Item Symbol Conditions HS (High-Speed Main) Mode LS (Low-Speed Main) Mode LP (Low-Power Main) Mode Unit SCKp cycle time t KCY1 tKCY1 ≥ 2/fCLK 4.0 V ≤ EVDD0 ≤ 5.5 V 62.5 83.3 1000 ns 2.7 V ≤ EVDD0 ≤ 5.5 V 83.3 125 1000 ns SCKp high-level width, low-level width tKH1, tKL1 4.0 V ≤ EVDD0 ≤ 5.5 V t KCY1/2 - 7 tKCY1/2 - 10 tKCY1/2 - 50 ns 2.7 V ≤ EVDD0 ≤ 5.5 V t KCY1/2 - 10 tKCY1/2 - 15 tKCY1/2 - 50 ns SIp setup time (to SCKp↑)Note 1 tSIK1 4.0 V ≤ EVDD0 ≤ 5.5 V 23 33 110 ns 2.7 V ≤ EVDD0 ≤ 5.5 V 33 50 110 ns SIp hold time (from SCKp↑) Note 1 tKSI1 2.7 V ≤ EVDD0 ≤ 5.5 V 10 10 10 ns Delay time from SCKp↓ to SOp output Note 2 tKSO1 C = 20 pFNote 3 10 10 10 ns

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 113 of 177 Oct 31, 2025 3. In simplified SPI (CSI) communications in the master mode with devices operating at same voltage levels with the internal SCKp clock Note 1. This setting applies when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The setting for the SIp setup time becomes “to SCKp↓” and that for the SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 2. This setting applies when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The setting for the delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 3. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using a port input mode register (PIMg) and port output mode register (POMg). Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM and POM numbers (g = 0, 1, 4, 5, 8, 14) Remark 2. fMCK: Serial array unit operation clock frequency (To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn) (m: Unit number, n: Channel number = 00 to 03, 10 to 13).) (TA = -40 to +105°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Item Symbol Conditions HS (High-Speed Main) Mode LS (Low-Speed Main) Mode LP (Low-Power Main) Mode Unit SCKp cycle time t KCY1 tKCY1 ≥ 4/fCLK 2.7 V ≤ EVDD0 ≤ 5.5 V 125 166 2000 ns 2.4 V ≤ EVDD0 ≤ 5.5 V 250 250 2000 ns 1.8 V ≤ EVDD0 ≤ 5.5 V 500 500 2000 ns 1.6 V ≤ EVDD0 ≤ 5.5 V 1000 1000 2000 ns SCKp high-level width, low-level width tKH1, tKL1 4.0 V ≤ EVDD0 ≤ 5.5 V t KCY1/2 - 12 tKCY1/2 - 21 tKCY1/2 - 50 ns 2.7 V ≤ EVDD0 ≤ 5.5 V t KCY1/2 - 18 tKCY1/2 - 25 tKCY1/2 - 50 ns 2.4 V ≤ EVDD0 ≤ 5.5 V t KCY1/2 - 38 tKCY1/2 - 38 tKCY1/2 - 50 ns 1.8 V ≤ EVDD0 ≤ 5.5 V t KCY1/2 - 50 tKCY1/2 - 50 tKCY1/2 - 50 ns 1.6 V ≤ EVDD0 ≤ 5.5 V t KCY1/2 - 100 tKCY1/2 - 100 tKCY1/2 - 100 ns SIp setup time (to SCKp↑)Note 1 tSIK1 4.0 V ≤ EVDD0 ≤ 5.5 V 44 54 110 ns 2.7 V ≤ EVDD0 ≤ 5.5 V 44 54 110 ns 2.4 V ≤ EVDD0 ≤ 5.5 V 75 75 110 ns 1.8 V ≤ EVDD0 ≤ 5.5 V 110 110 110 ns 1.6 V ≤ EVDD0 ≤ 5.5 V 220 220 220 ns SIp hold time (from SCKp↑) Note 1 tKSI1 1.6 V ≤ EVDD0 ≤ 5.5 V 19 19 19 ns Delay time from SCKp↓ to SOp output Note 2 tKSO1 1.6 V ≤ EVDD0 ≤ 5.5 V C = 30 pFNote 3 25 25 25 ns

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 114 of 177 Oct 31, 2025 4. In simplified SPI (CSI) communications in the slave mode with devices operating at same voltage levels with the SCKp external clock (Notes, Caution, and Remarks are listed on the next page.) (TA = -40 to +105°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2) Item Symbol Conditions HS (High-Speed Main) Mode LS (Low-Speed Main) Mode LP (Low-Power Main) Mode Unit SCKp cycle time Note 1 tKCY2 4.0 V ≤ EVDD0 ≤ 5.5 V 20 MHz < f MCK 8/fMCK 8/fMCK —n s fMCK ≤ 20 MHz 6/f MCK 6/fMCK 6/fMCK ns 2.7 V ≤ EVDD0 ≤ 5.5 V 16 MHz < f MCK 8/fMCK 8/fMCK —n s fMCK ≤ 16 MHz 6/f MCK 6/fMCK 6/fMCK ns 2.4 V ≤ EVDD0 ≤ 5.5 V 6/f MCK and 500 6/fMCK and 500 6/fMCK and 500 ns 1.8 V ≤ EVDD0 ≤ 5.5 V 6/f MCK and 750 6/fMCK and 750 6/fMCK and 750 ns 1.6 V ≤ EVDD0 ≤ 5.5 V 6/f MCK and 1500 6/fMCK and 1500 6/fMCK and 1500 ns SCKp high-level width, low-level width tKH2, tKL2 4.0 V ≤ EVDD0 ≤ 5.5 V t KCY2/2 - 7 t KCY2/2 - 7 t KCY2/2 - 7 ns 2.7 V ≤ EVDD0 ≤ 5.5 V t KCY2/2 - 8 t KCY2/2 - 8 t KCY2/2 - 8 ns 1.8 V ≤ EVDD0 ≤ 5.5 V t KCY2/2 - 18 tKCY2/2 - 18 tKCY2/2 - 18 ns 1.6 V ≤ EVDD0 ≤ 5.5 V t KCY2/2 - 66 tKCY2/2 - 66 tKCY2/2 - 66 ns

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 115 of 177 Oct 31, 2025 4. In simplified SPI (CSI) communications in the slave mode with devices operating at same voltage levels with the SCKp external clock Note 1. Transfer rate in the SNOOZE mode is 1 Mbps at the maximum. Note 2. This setting applies when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The setting for the SIp setup time becomes “to SCKp↓” and that for the SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 3. This setting applies when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The setting for the delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 4. C is the load capacitance of the SOp output line. Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using a port input mode register (PIMg) and port output mode register (POMg). Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM and POM numbers (g = 0, 1, 4, 5, 8, 14) Remark 2. fMCK: Serial array unit operation clock frequency (To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn) (m: Unit number, n: Channel number = 00 to 03, 10 to 13).) (TA = -40 to +105°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2) Item Symbol Conditions HS (High-Speed Main) Mode LS (Low-Speed Main) Mode LP (Low-Power Main) Mode Unit SIp setup time (to SCKp↑)Note 2 tSIK2 2.7 V ≤ EVDD0 ≤ 5.5 V 1/f MCK + 20 1/fMCK + 30 1/fMCK + 30 ns 1.8 V ≤ EVDD0 ≤ 5.5 V 1/f MCK + 30 1/fMCK + 30 1/fMCK + 30 ns 1.6 V ≤ EVDD0 ≤ 5.5 V 1/f MCK + 40 1/fMCK + 40 1/fMCK + 40 ns SIp hold time (from SCKp↑)Note 2 tKSI2 1.8 V ≤ EVDD0 ≤ 5.5 V 1/f MCK + 31 1/fMCK + 31 1/fMCK + 31 ns 1.6 V ≤ EVDD0 ≤ 5.5 V 1/f MCK + 250 1/fMCK + 250 1/fMCK + 250 ns Delay time from SCKp↓ to SOp output Note 3 tKSO2 C = 30 pF Note 4 2.7 V ≤ EVDD0 ≤ 5.5 V 2/f MCK + 44 2/fMCK + 110 2/fMCK + 110 ns 2.4 V ≤ EVDD0 ≤ 5.5 V 2/f MCK + 75 2/fMCK + 110 2/fMCK + 110 ns 1.8 V ≤ EVDD0 ≤ 5.5 V 2/f MCK + 110 2/fMCK + 110 2/fMCK + 110 ns 1.6 V ≤ EVDD0 ≤ 5.5 V 2/f MCK + 220 2/fMCK + 220 2/fMCK + 220 ns

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 116 of 177 Oct 31, 2025 Connection in the simplified SPI (CSI) communications with devices operating at same voltage levels Timing of serial transfer in the simplified SPI (CSI) communications with devices operating at same voltage levels when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1 SCKp SOp SCK SI SIp SORL78 microcontroller User device Input dataSIp SOp tKCY1, 2 tKL1, 2 tKH1, 2 tSIK1, 2 tKSI1, 2 tKSO1, 2 Output data SCKp

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 117 of 177 Oct 31, 2025 Timing of serial transfer in the simplified SPI (CSI) communications with devices operating at same voltage levels when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0 Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31) Remark 2. m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13) Input dataSIp SOp tKCY1, 2 tKH1, 2 tKL1, 2 tSIK1, 2 tKSI1, 2 tKSO1, 2 Output data SCKp

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 118 of 177 Oct 31, 2025 5. In simplified I 2C communications with devices operating at same voltage levels (Notes and Caution are listed on the next page, and Remarks are listed on page 120.) (TA = -40 to +105°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2) Item Symbol Conditions HS (High-Speed Main) Mode LS (Low-Speed Main) Mode LP (Low-Power Main) Mode Unit SCLr clock frequency f SCL 2.7 V ≤ EVDD0 ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 1000 Note 1 1000 Note 1 400Note 1 kHz 1.8 V ≤ EVDD0 ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 400Note 1 400Note 1 400Note 1 kHz 1.8 V ≤ EVDD0 < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 300Note 1 300Note 1 300Note 1 kHz 1.6 V ≤ EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 kΩ 250Note 1 250Note 1 250Note 1 kHz Hold time when SCLr is low tLOW 2.7 V ≤ EVDD0 ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 475 475 1150 ns 1.8 V ≤ EVDD0 ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 1150 1150 1150 ns 1.8 V ≤ EVDD0 < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 1550 1550 1550 ns 1.6 V ≤ EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 kΩ 1850 1850 1850 ns Hold time when SCLr is high tHIGH 2.7 V ≤ EVDD0 ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 475 475 1150 ns 1.8 V ≤ EVDD0 ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 1150 1150 1150 ns 1.8 V ≤ EVDD0 < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 1550 1550 1550 ns 1.6 V ≤ EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 kΩ 1850 1850 1850 ns

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 119 of 177 Oct 31, 2025 5. In simplified I 2C communications with devices operating at same voltage levels Note 1. The listed times must be no greater than fMCK/4. Note 2. Set fMCK so that it will not exceed the hold time when SCLr is low or high. Caution Select the normal input buffer and the N-ch open drain output (withstand voltage of V DD (when 30- to 52-pin products)/withstand voltage of EVDD (when 64- to 128-pin products)) mode for the SDAr pin and the normal output mode for the SCLr pin by using a port input mode register (PIMg) and port output mode register (POMh). (Remarks are listed on the next page.) (TA = -40 to +105°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2) Item Symbol Conditions HS (High-Speed Main) Mode LS (Low-Speed Main) Mode LP (Low-Power Main) Mode Unit Data setup time (reception) tSU:DAT 2.7 V ≤ EVDD0 ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 1/fMCK + 85 Note 2 1/fMCK + 85 Note 2 1/fMCK + 145 Note 2 ns 1.8 V ≤ EVDD0 ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 1/fMCK + 145 Note 2 1/fMCK + 145 Note 2 1/fMCK + 145 Note 2 ns 1.8 V ≤ EVDD0 < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 1/fMCK + 230 Note 2 1/fMCK + 230 Note 2 1/fMCK + 230 Note 2 ns 1.6 V ≤ EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 kΩ 1/fMCK + 290 Note 2 1/fMCK + 290 Note 2 1/fMCK + 290 Note 2 ns Data hold time (transmission) tHD:DAT 2.7 V ≤ EVDD0 ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 0 305 0 305 0 305 ns 1.8 V ≤ EVDD0 ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 0 355 0 355 0 355 ns 1.8 V ≤ EVDD0 < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 0 405 0 405 0 405 ns 1.6 V ≤ EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 kΩ 0 405 0 405 0 405 ns

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 120 of 177 Oct 31, 2025 Connection in the simplified I2C communications with devices operating at same voltage levels Timing of serial transfer in the simplified I2C communications with devices operating at same voltage levels Remark 1. Rb[Ω]: Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance Remark 2. r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31), g: PIM number (g = 0, 1, 4, 5, 8, 14), h: POM number (g = 0, 1, 4, 5, 7 to 9, 14) Remark 3. fMCK: Serial array unit operation clock frequency (To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn) (m: Unit number, n: Channel number = 00 to 03, 10 to 13).) RL78 microcontroller SDAr SCLr SDA SCL VDD Rb User device SDAr SCLr 1/fSCL tLOW tHIGH tSU:DATtHD:DAT

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 121 of 177 Oct 31, 2025 6. In UART communications with devices operating at different voltage levels (1.8 V, 2.5 V, 3 V) Note 1. Transfer rate in the SNOOZE mode is within the range from 4800 to 9600 bps. Note 2. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: Note 3. Use this rate with EVDD0 ≥ Vb. Note 4. The following conditions are required for low voltage interface when EVDD0 < VDD. 2.4 V ≤ EVDD0 < 2.7 V: 2.6 Mbps (max.) 1.8 V ≤ EVDD0 < 2.4 V: 1.3 Mbps (max.) Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (withstand voltage of V DD (when 30- to 52-pin products)/withstand voltage of EVDD (when 64- to 128-pin products)) mode for the TxDq pin by using a port input mode register (PIMg) and port output mode register (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remark 1. Vb[V]: Communication line voltage Remark 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14) Remark 3. fMCK: Serial array unit operation clock frequency (To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn) (m: Unit number, n: Channel number = 00 to 03, 10 to 13).) Remark 4. Communications by using UART2 with devices operating at different voltage levels are not possible when the setting of the PIOR1 bit of the peripheral I/O redirection register (PIOR) is 1. (TA = -40 to +105°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2) Item Symbol Conditions HS (High-Speed Main) Mode LS (Low-Speed Main) Mode LP (Low-Power Main) Mode Unit Transfer rate Reception 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V fMCK/6 Note 1 fMCK/6 Note 1 fMCK/6 Note 1 bps Theoretical value of the maximum transfer rate f MCK = fCLKNote 2 5.3 4 0.33 Mbps 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V fMCK/6 Note 1 fMCK/6 Note 1 fMCK/6 Note 1 bps Theoretical value of the maximum transfer rate f MCK = fCLKNote 2 5.3 4 0.33 Mbps 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V fMCK/6 Notes 1, 3, 4 fMCK/6 Notes 1, 3 fMCK/6 Notes 1, 3 bps Theoretical value of the maximum transfer rate fMCK = fCLKNote 2 5.3 4 0.33 Mbps HS (high-speed main) mode : 32 MHz (1.8 V ≤ VDD ≤ 5.5 V) 4 MHz (1.6 V ≤ VDD ≤ 5.5 V) LS (low-speed main) mode : 24 MHz (1.8 V ≤ VDD ≤ 5.5 V) 4 MHz (1.6 V ≤ VDD ≤ 5.5 V) LP (low-power main) mode : 2 MHz (1.6 V ≤ VDD ≤ 5.5 V)

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 122 of 177 Oct 31, 2025 6. In UART communications with devices operating at different voltage levels (1.8 V, 2.5 V, 3 V) Note 1. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V Note 2. This rate is calculated as an example when the conditions described in the “Conditions” column are met. See Note 1 above to calculate the maximum transfer rate under conditions of the customer. (Notes and Caution continue in the next page.) (TA = -40 to +105°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2) Item Symbol Conditions HS (High-Speed Main) Mode LS (Low-Speed Main) Mode LP (Low-Power Main) Mode Unit Transfer rate Transmission 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V Note 1N ote 1N ote 1 bps Theoretical value of the maximum transfer rate C b = 50 pF, Rb = 1.4 kΩ, Vb = 2.7 V 2.8Note 2 2.8Note 2 2.8Note 2 Mbps 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V Note 3N ote 3N ote 3 bps Theoretical value of the maximum transfer rate C b = 50 pF, Rb = 2.7 kΩ, Vb = 2.3 V 1.2Note 4 1.2Note 4 1.2Note 4 Mbps 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Notes 5, 6 Notes 5, 6 Notes 5, 6 bps Theoretical value of the maximum transfer rate C b = 50 pF, Rb = 5.5 kΩ, Vb = 1.6 V 0.43 Note 7 0.43 Note 7 0.43 Note 7 Mbps Maximum transfer rate = [bps] Baud rate error (theoretical value) = Transfer rate  2 Vb Vb ( )  Number of transferred bits1 Transfer rate  100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides .

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 123 of 177 Oct 31, 2025 Note 3. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V Note 4. This rate is calculated as an example when the conditions described in the “Conditions” column are met. See Note 3 above to calculate the maximum transfer rate under conditions of the customer. Note 5. Use this rate with EVDD0 ≥ Vb. Note 6. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 7. This rate is calculated as an example when the conditions described in the “Conditions” column are met. Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer. Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (withstand voltage of V DD (when 30- to 52-pin products)/withstand voltage of EVDD (when 64- to 128-pin products)) mode for the TxDq pin by using a port input mode register (PIMg) and port output mode register (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Maximum transfer rate = [bps] Baud rate error (theoretical value) = Transfer rate  2 ( )  Number of transferred bits1 Transfer rate  100 [%] Vb Vb * This value is the theoretical value of the relative difference between the transmission and reception sides. Maximum transfer rate = [bps] Baud rate error (theoretical value) = Transfer rate  2 ( )  Number of transferred bits1 Transfer rate  100 [%] Vb Vb * This value is the theoretical value of the relative difference between the transmission and reception sides.

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 124 of 177 Oct 31, 2025 In UART communications with devices operating at different voltage levels Bit width in the UART communications with devices operating at different voltage levels (reference) Remark 1. Rb[Ω]: Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage Remark 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14) Remark 3. fMCK: Serial array unit operation clock frequency (To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn) (m: Unit number, n: Channel number = 00 to 03, 10 to 13).) Remark 4. Communications by using UART2 with devices operating at different voltage levels are not possible when the setting of the PIOR1 bit of the peripheral I/O redirection register (PIOR) is 1. RL78 microcontroller TxDq RxDq Rx Tx Vb Rb User device Baud rate error tolerance Low-/high-bit width 1/Transfer rate Baud rate error tolerance High-bit width Low-bit width 1/Transfer rate TxDq RxDq

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 125 of 177 Oct 31, 2025 7. In simplified SPI (CSI) communications in the master mode with devices operating at different voltage levels (2.5 V or 3 V) with the internal SCKp clock (the ratings below are only applicable to CSI00) (Notes, Caution, and Remarks are listed on the next page.) (TA = -40 to +105°C, 2.7 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2) Item Symbol Conditions HS (High-Speed Main) Mode LS (Low-Speed Main) Mode LP (Low-Power Main) Mode Unit SCKp cycle time t KCY1 tKCY1 ≥ 2/fCLK 4.0 V ≤ EVDD0 ≤ 5.5 Cb = 20 pF, Rb = 1.4 kΩ 200 200 2300 ns 2.7 V ≤ EVDD0 < 4.0 Cb = 20 pF, Rb = 2.7 kΩ 300 300 2300 ns SCKp high-level width tKH1 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ tKCY1/2 - 50 tKCY1/2 - 50 tKCY1/2 - 50 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ tKCY1/2 - 120 tKCY1/2 - 120 tKCY1/2 - 120 ns SCKp low-level width tKL1 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ tKCY1/2 - 7 tKCY1/2 - 7 tKCY1/2 - 50 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ tKCY1/2 - 10 tKCY1/2 - 10 tKCY1/2 - 50 ns SIp setup time (to SCKp↑)Note 1 tSIK1 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ 58 58 479 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ 121 121 479 ns SIp hold time (from SCKp↑)Note 1 tKSI1 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ 10 10 10 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ 10 10 10 ns Delay time from SCKp↓ to SOp outputNote 1 tKSO1 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ 60 60 60 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ 130 130 130 ns

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 126 of 177 Oct 31, 2025 7. In simplified SPI (CSI) communications in the master mode with devices operating at different voltage levels (2.5 V or 3 V) with the internal SCKp clock (the ratings below are only applicable to CSI00) Note 1. This setting applies when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. Note 2. This setting applies when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (withstand voltage of V DD (when 30- to 52-pin products)/withstand voltage of EVDD (when 64- to 128-pin products)) mode for the SOp pin and SCKp pin by using a port input mode register (PIMg) and port output mode register (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remark 1. Rb[Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage Remark 2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM numbers (g = 1) Remark 3. fMCK: Serial array unit operation clock frequency (To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn) (m: Unit number, n: Channel number = 00).) Remark 4. The listed times are only valid when the peripheral I/O redirect function of CSI00 is not in use. (TA = -40 to +105°C, 2.7 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2) Item Symbol Conditions HS (High-Speed Main) Mode LS (Low-Speed Main) Mode LP (Low-Power Main) Mode Unit SIp setup time (to SCKp↓)Note 2 tSIK1 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ 23 23 110 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ 33 33 110 ns SIp hold time (from SCKp↓) Note 2 tKSI1 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ 10 10 10 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ 10 10 10 ns Delay time from SCKp↑ to SOp outputNote 2 tKSO1 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ 10 10 10 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ 10 10 10 ns

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 127 of 177 Oct 31, 2025 8. In simplified SPI (CSI) communications in the master mode with devices operating at different voltage levels (1.8 V,

2.5 V, or 3 V) with the internal SCKp clock

Note Use this setting with EVDD0 ≥ Vb. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (withstand voltage of V DD (when 30- to 52-pin products)/withstand voltage of EVDD (when 64- to 128-pin products)) mode for the SOp pin and SCKp pin by using a port input mode register (PIMg) and port output mode register (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on page 130.) (TA = -40 to +105°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/3) Item Symbol Conditions HS (High-Speed Main) Mode LS (Low-Speed Main) Mode LP (Low-Power Main) Mode Unit SCKp cycle time t KCY1 tKCY1 ≥ 4/fCLK 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ 300 300 2300 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ 500 500 2300 ns 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote, Cb = 30 pF, Rb = 5.5 kΩ 1150 1150 2300 ns SCKp high-level width t KH1 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ tKCY1/2 - 75 tKCY1/2 - 75 tKCY1/2 - 75 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ tKCY1/2 - 170 tKCY1/2 - 170 tKCY1/2 - 170 ns 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote, Cb = 30 pF, Rb = 5.5 kΩ tKCY1/2 - 458 tKCY1/2 - 458 tKCY1/2 - 458 ns SCKp low-level width t KL1 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ tKCY1/2 - 12 tKCY1/2 - 12 tKCY1/2 - 50 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ tKCY1/2 - 18 tKCY1/2 - 18 tKCY1/2 - 50 ns 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote, Cb = 30 pF, Rb = 5.5 kΩ tKCY1/2 - 50 tKCY1/2 - 50 tKCY1/2 - 50 ns

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 128 of 177 Oct 31, 2025 8. In simplified SPI (CSI) communications in the master mode with devices operating at different voltage levels (1.8 V, Note 1. This setting applies when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. Note 2. Use this setting with EVDD0 ≥ Vb. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (withstand voltage of V DD (when 30- to 52-pin products)/withstand voltage of EVDD (when 64- to 128-pin products)) mode for the SOp pin and SCKp pin by using a port input mode register (PIMg) and port output mode register (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on page 130.) (TA = -40 to +105°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/3) Item Symbol Conditions HS (High-Speed Main) Mode LS (Low-Speed Main) Mode LP (Low-Power Main) Mode Unit SIp setup time (to SCKp↑)Note 1 tSIK1 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ 81 81 479 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ 177 177 479 ns 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 30 pF, Rb = 5.5 kΩ 479 479 479 ns SIp hold time (from SCKp↑)Note 1 tKSI1 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ 19 19 19 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ 19 19 19 ns 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 30 pF, Rb = 5.5 kΩ 19 19 19 ns Delay time from SCKp↓ to SOp outputNote 1 tKSO1 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ 100 100 100 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ 195 195 195 ns 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 30 pF, Rb = 5.5 kΩ 483 483 483 ns

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 129 of 177 Oct 31, 2025 8. In simplified SPI (CSI) communications in the master mode with devices operating at different voltage levels (1.8 V, Note 1. This setting applies when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 2. Use this setting with EVDD0 ≥ Vb. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (withstand voltage of V DD (when 30- to 52-pin products)/withstand voltage of EVDD (when 64- to 128-pin products)) mode for the SOp pin and SCKp pin by using a port input mode register (PIMg) and port output mode register (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.) (TA = -40 to +105°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (3/3) Item Symbol Conditions HS (High-Speed Main) Mode LS (Low-Speed Main) Mode LP (Low-Power Main) Mode Unit SIp setup time (to SCKp↓)Note 1 tSIK1 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ 44 44 110 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ 44 44 110 ns 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 30 pF, Rb = 5.5 kΩ 110 110 110 ns SIp hold time (from SCKp↓)Note 1 tKSI1 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ 19 19 19 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ 19 19 19 ns 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 30 pF, Rb = 5.5 kΩ 19 19 19 ns Delay time from SCKp↑ to SOp outputNote 1 tKSO1 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ 25 25 25 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ 25 25 25 ns 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 30 pF, Rb = 5.5 kΩ 25 25 25 ns

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 130 of 177 Oct 31, 2025 Connection in the simplified SPI (CSI) communications with devices operating at different voltage levels Remark 1. Rb[Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage Remark 2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number, n: Channel number (mn = 00, 01, 02, 10, 12, 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14) Remark 3. fMCK: Serial array unit operation clock frequency (To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn) (m: Unit number, n: Channel number = 00).) Remark 4. Communications by using CSI01 of 48- to 64-pin products, and CSI11 and CSI21 with devices operating at different voltage levels are not possible. Use other CSI channels to handle such communications. Timing of serial transfer in the simplified SPI (CSI) communications in the master mode with devices operating at different voltage levels when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1 SCKp SOp SCK SI SIp SO Vb Rb <Master> Vb Rb RL78 microcontroller User device Input dataSIp SOp tKCY1 tKL1 tKH1 tSIK1 tKSI1 tKSO1 Output data SCKp

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 131 of 177 Oct 31, 2025 Timing of serial transfer in the simplified SPI (CSI) communications in the master mode with devices operating at different voltage levels when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0 Remark 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number, n: Channel number (mn = 00, 01, 02, 10, 12, 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14) Remark 2. Communications by using CSI01 of 48- to 64-pin products, and CSI11 and CSI21 with devices operating at different voltage levels are not possible. Use other CSI channels to handle such communications. Input data Output data SIp SOp SCKp tKCY1 tKH1 tKL1 tSIK1 tKSI1 tKSO1

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 132 of 177 Oct 31, 2025 9. In simplified SPI (CSI) communications in the slave mode wit h devices operating at different voltage levels (1.8 V,

2.5 V, or 3 V) with the external SCKp clock

(Notes and Caution are listed on the next page, and Remarks are listed on page 134.) (TA = -40 to +105°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2) Item Symbol Conditions HS (High-Speed Main) Mode LS (Low-Speed Main) Mode LP (Low-Power Main) Mode Unit SCKp cycle time Note 1 tKCY2 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V

24 MHz < fMCK 14/fMCK —— n s

20 MHz < fMCK ≤ 24 MHz 12/f MCK 12/fMCK —n s

8 MHz < fMCK ≤ 20 MHz 10/f MCK 10/fMCK —n s

4 MHz < fMCK ≤ 8 MHz 8/f MCK 8/fMCK —n s

fMCK ≤ 4 MHz 6/f MCK 6/fMCK 10/fMCK ns 2.7 V ≤ EVDD0 < 4.0 V,

24 MHz < fMCK 20/fMCK —— n s

20 MHz < fMCK ≤ 24 MHz 16/f MCK 16/fMCK —n s

16 MHz < fMCK ≤ 20 MHz 14/f MCK 14/fMCK —n s

8 MHz < fMCK ≤ 16 MHz 12/f MCK 12/fMCK —n s

fMCK ≤ 4 MHz 6/f MCK 6/fMCK 10/fMCK ns 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2

24 MHz < fMCK 48/fMCK —— n s

20 MHz < fMCK ≤ 24 MHz 36/f MCK 36/fMCK —n s

16 MHz < fMCK ≤ 20 MHz 32/f MCK 32/fMCK —n s

8 MHz < fMCK ≤ 16 MHz 26/f MCK 26/fMCK —n s

4 MHz < fMCK ≤ 8 MHz 16/f MCK 16/fMCK —n s

fMCK ≤ 4 MHz 10/f MCK 10/fMCK 10/fMCK ns

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 133 of 177 Oct 31, 2025 9. In simplified SPI (CSI) communications in the slave mode wit h devices operating at different voltage levels (1.8 V, Note 1. Transfer rate in the SNOOZE mode is 1 Mbps at the maximum. Note 2. Use this setting with EVDD0 ≥ Vb. Note 3. This setting applies when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” and SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 4. This setting applies when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (withstand voltage of V DD (for the 30- to 52-pin products)/withstand voltage of EVDD (for the 64- to 128-pin products)) mode for the SOp pin and SCKp pin by using a port input mode register (PIMg) and port output mode register (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.) (TA = -40 to +105°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2) Item Symbol Conditions HS (High-Speed Main) Mode LS (Low-Speed Main) Mode LP (Low-Power Main) Mode Unit SCKp high-level width, low-level width tKH2, tKL2 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V tKCY2/2 - 12 tKCY2/2 - 12 tKCY2/2 - 50 ns 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V tKCY2/2 - 18 tKCY2/2 - 18 tKCY2/2 - 50 ns 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2 tKCY2/2 - 50 tKCY2/2 - 50 tKCY2/2 - 50 ns SIp setup time (to SCKp↑)Note 3 tSIK2 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V 1/fMCK + 20 1/fMCK + 20 1/fMCK + 30 ns 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V 1/fMCK + 20 1/fMCK + 20 1/fMCK + 30 ns 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2 1/fMCK + 30 1/fMCK + 30 1/fMCK + 30 ns SIp hold time (from SCKp↑)Note 3 tKSI2 1/fMCK + 31 1/fMCK + 31 1/fMCK + 31 ns Delay time from SCKp↓ to SOp outputNote 4 tKSO2 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ 2/fMCK + 120 2/fMCK + 120 2/fMCK + 573 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ 2/fMCK + 214 2/fMCK + 214 2/fMCK + 573 ns 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 30 pF, Rb = 5.5 kΩ 2/fMCK + 573 2/fMCK + 573 2/fMCK + 573 ns

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 134 of 177 Oct 31, 2025 Connection in the simplified SPI (CSI) communications with devices operating at different voltage levels Remark 1. Rb[Ω]: Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance, Vb[V]: Communication line voltage Remark 2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number, n: Channel number (mn = 00, 01, 02, 10, 12, 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14) Remark 3. fMCK: Serial array unit operation clock frequency (To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn) (m: Unit number, n: Channel number = 00, 01, 02, 10, 12 and 13).) Remark 4. Communications by using CSI01 of 48- to 64-pin products, and CSI11 and CSI21 with devices operating at different voltage levels are not possible. Use other CSI channels to handle such communications. Timing of serial transfer in the simplified SPI (CSI) communications in the slave mode with devices operating at different voltage levels when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1 SCKp SOp SCK SI SIp SO Vb Rb <Slave> RL78 microcontroller User device SIp SOp SCKp Input data Output data tKCY2 tKH2tKL2 tSIK2 tKSI2 tKSO2

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 135 of 177 Oct 31, 2025 Timing of serial transfer in the simplified SPI (CSI) communications in the slave mode with devices operating at different voltage levels when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0 Remark 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number, n: Channel number (mn = 00, 01, 02, 10, 12, 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14) Remark 2. Communications by using CSI01 of 48- to 64-pin products, and CSI11 and CSI21 with devices operating at different voltage levels are not possible. Use other CSI channels to handle such communications. Input data Output data SIp SOp SCKp tKCY2 tKL2tKH2 tSIK2 tKSI2 tKSO2

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 136 of 177 Oct 31, 2025 10. Simplified I2C communications with devices operating at different voltage levels (1.8 V, 2.5 V, or 3 V) (TA = -40 to +105°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2) Item Symbol Conditions HS (High-Speed Main) Mode LS (Low-Speed Main) Mode LP (Low-Power Main) Mode Unit SCLr clock frequency f SCL 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 1000 Note 1 1000 Note 1 300 Note 1 kHz 2.7 V ≤ EVDD0 < 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 1000 Note 1 1000 Note 1 300 Note 1 kHz 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 100 pF, Rb = 2.8 kΩ 400 Note 1 400 Note 1 300 Note 1 kHz 2.7 V ≤ EVDD0 < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ 400 Note 1 400 Note 1 300 Note 1 kHz 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 100 pF, Rb = 5.5 kΩ 300 Note 1 300 Note 1 300 Note 1 kHz Hold time when SCLr is low tLOW 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 475 475 1550 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 475 475 1550 ns 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 100 pF, Rb = 2.8 kΩ 1150 1550 1550 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ 1150 1550 1550 ns 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 100 pF, Rb = 5.5 kΩ 1550 1550 1550 ns Hold time when SCLr is high tHIGH 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 245 245 610 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 200 200 610 ns 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 100 pF, Rb = 2.8 kΩ 675 675 610 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ 600 600 610 ns 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 100 pF, Rb = 5.5 kΩ 610 610 610 ns

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 137 of 177 Oct 31, 2025 10. Simplified I2C communications with devices operating at different voltage levels (1.8 V, 2.5 V, and 3 V) Note 1. The listed times must be no greater than fMCK/4. Note 2. Use this setting with EVDD0 ≥ Vb. Note 3. Set fMCK so that it will not exceed the hold time when SCLr is low or high. Caution Select the TTL input buffer and the N-ch open drain output (withstand voltage of V DD (for the 30- to 52-pin products)/withstand voltage of EVDD (for the 64- to 128-pin products)) mode for the SDAr pin and the N-ch open drain output (withstand voltage of VDD (for the 30- to 52-pin products)/withstand voltage of EVDD (for the 64- to 128-pin products)) mode for the SCLr pin by using a port input mode register (PIMg) and port output mode register (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.) (TA = -40 to +105°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2) Item Symbol Conditions HS (High-Speed Main) Mode LS (Low-Speed Main) Mode LP (Low-Power Main) Mode Unit Data setup time (reception) tSU:DAT 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 1/fMCK + 135 Note 3 1/fMCK + 135 Note 3 1/fMCK + 190 Note 3 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 1/fMCK + 135 Note 3 1/fMCK + 135 Note 3 1/fMCK + 190 Note 3 ns 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 100 pF, Rb = 2.8 kΩ 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 ns 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 100 pF, Rb = 5.5 kΩ 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 ns Data hold time (transmission) t HD:DAT 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 0 305 0 305 0 305 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 0 305 0 305 0 305 ns 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 100 pF, Rb = 2.8 kΩ 0 355 0 355 0 355 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ 0 355 0 355 0 355 ns 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 100 pF, Rb = 5.5 kΩ 0 405 0 405 0 405 ns

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 138 of 177 Oct 31, 2025 Connection in the I2C communications with devices operating at different voltage levels Timing of serial transfer in the simplified I2C communications with devices operating at different voltage levels Remark 1. Rb[Ω]: Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance, Vb[V]: Communication line voltage Remark 2. r: IIC number (r = 00, 01, 10, 20, 30, 31), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14) Remark 3. fMCK: Serial array unit operation clock frequency (To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn) (m: Unit number, n: Channel number = 00, 01, 02, 10, 12 and 13).) RL78 microcontroller SDAr SCLr SDA SCL Vb Rb Vb Rb User device SDAr SCLr 1/fSCL tLOW tHIGH tSU:DATtHD:DAT

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 139 of 177 Oct 31, 2025

2.5.2 Serial interface UARTA

Caution Select the normal input buffer for the RxDAn pin and the normal output mode for the TxDAn pin by using a port input mode register (PIMg) and port output mode register (POMg). Remark n = Unit number (n = 0, 1), g: PIM number (g = 3, 4, 7, 8), h: POM number (h = 3, 4, 7, 8, 12) (TA = -40 to +105°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Item Symbol Conditions Min. Typ. Max. Unit Transfer rate 200 0 153600 bps <R>

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 140 of 177 Oct 31, 2025

2.5.3 Serial interface IICA

I 2C standard mode Note 1. The first clock pulse is generated after this period when the start or restart condition is detected. Note 2. The maximum value of tHD:DAT applies to normal transfer. The clock stretching will be inserted on reception of an acknowledgment (ACK) signal. Caution The listed frequency and times apply even when the PIOR 2 bit in the peripheral I/O redirection register (PIOR) is 1. In such cases, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination. Remark The maximum value of communication line capacitance (Cb) and communication line pull-up resistor (Rb) are as follows. Cb = 400 pF, Rb = 2.7 kΩ (TA = -40 to +105°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Item Symbol Conditions Min. Typ. Max. Unit SCLA0 clock frequency fSCL Standard mode: fCLK ≥ 1 MHz 0 100 kHz Setup time of restart condition t SU:STA 4.7 µs Hold timeNote 1 tHD:STA 4.0 µs Hold time when SCLA0 is low t LOW 4.7 µs Hold time when SCLA0 is high t HIGH 4.0 µs Data setup time (reception) tSU:DAT 250 ns Data hold time (transmission)Note 2 tHD:DAT 03 .45 µs Setup time of stop condition tSU:STO 4.0 µs Bus-free time tBUF 4.7 µs

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 141 of 177 Oct 31, 2025 2. I 2C fast mode Note 1. The first clock pulse is generated after this period when the start or restart condition is detected. Note 2. The maximum value of tHD:DAT applies to normal transfer. The clock stretching will be inserted on reception of an acknowledgment (ACK) signal. Caution The values in the above table apply even when the PIOR2 bi t in the peripheral I/O redirection register (PIOR) is 1. In such cases, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination. Remark The maximum value of communication line capacitance (Cb) and communication line pull-up resistor (Rb) are as follows. Cb = 320 pF, Rb = 1.1 kΩ (TA = -40 to +105°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Item Symbol Conditions Min. Typ. Max. Unit SCLA0 clock frequency fSCL Fast mode: fCLK ≥ 3.5 MHz 1.8 V ≤ EVDD0 ≤ 5.5 V 0 400 kHz Setup time of restart condition t SU:STA 1.8 V ≤ EVDD0 ≤ 5.5 V 0.6 µs Hold timeNote 1 tHD:STA 1.8 V ≤ EVDD0 ≤ 5.5 V 0.6 µs Hold time when SCLA0 is low t LOW 1.8 V ≤ EVDD0 ≤ 5.5 V 1.3 µs Hold time when SCLA0 is high t HIGH 1.8 V ≤ EVDD0 ≤ 5.5 V 0.6 µs Data setup time (reception) t SU:DAT 1.8 V ≤ EVDD0 ≤ 5.5 V 100 ns Data hold time (transmission)Note 2 tHD:DAT 1.8 V ≤ EVDD0 ≤ 5.5 V 0 0.9 µs Setup time of stop condition t SU:STO 1.8 V ≤ EVDD0 ≤ 5.5 V 0.6 µs Bus-free time t BUF 1.8 V ≤ EVDD0 ≤ 5.5 V 1.3 µs

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 142 of 177 Oct 31, 2025 3. I 2C fast mode plus Note 1. The first clock pulse is generated after this period when the start or restart condition is detected. Note 2. The maximum value of tHD:DAT applies to normal transfer. The clock stretching will be inserted on reception of an acknowledgment (ACK) signal. Caution The values in the above table apply even when the PIOR2 bi t in the peripheral I/O redirection register (PIOR) is 1. In such cases, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination. Remark The maximum value of communication line capacitance (Cb) and communication line pull-up resistor (Rb) are as follows. Cb = 120 pF, Rb = 1.1 kΩ IICA serial transfer timing Remark n = 0, 1 (TA = -40 to +105°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Item Symbol Conditions Min. Typ. Max. Unit SCLA0 clock frequency fSCL Fast mode plus: fCLK ≥ 10 MHz 2.7 V ≤ EVDD0 ≤ 5.5 V 0 1000 kHz Setup time of restart condition t SU:STA 2.7 V ≤ EVDD0 ≤ 5.5 V 0.26 µs Hold timeNote 1 tHD:STA 2.7 V ≤ EVDD0 ≤ 5.5 V 0.26 µs Hold time when SCLA0 is low t LOW 2.7 V ≤ EVDD0 ≤ 5.5 V 0.5 µs Hold time when SCLA0 is high t HIGH 2.7 V ≤ EVDD0 ≤ 5.5 V 0.26 µs Data setup time (reception) t SU:DAT 2.7 V ≤ EVDD0 ≤ 5.5 V 50 ns Data hold time (transmission)Note 2 tHD:DAT 2.7 V ≤ EVDD0 ≤ 5.5 V 0 0.45 µs Setup time of stop condition t SU:STO 2.7 V ≤ EVDD0 ≤ 5.5 V 0.26 µs Bus-free time t BUF 2.7 V ≤ EVDD0 ≤ 5.5 V 0.5 µs tSU:DATtHD:STA Restart condition SCLAn SDAAn tLOW tHIGH tR tF tSU:STA tHD:STA tSU:STO Stop condition Stop condition Start condition tHD:DAT tBUF

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 143 of 177 Oct 31, 2025

2.6 Analog Characteristics

2.6.1 A/D converter characteristics

Normal modes 1 and 2 Note 1. This value does not include the quantization error (±1/2 LSB). Note 2. The values in the column Max. only apply in the case of a normal distribution with ±3σ variation from the mean. Note 3. We do not inspect the characteristics of the A/D converter before shipment. The listed values are only results of evaluation. Note 4. When AVREFP < VDD, the maximum values are as follows. Note 5. The listed values apply when the conversion resolution is set to 12 bits. Note 6. When the internal reference voltage or the temperature sensor output voltage is selected as the target for conversion, the sampling time must be at least 5 µs. Accordingly, use standard mode 2 with the longer sampling time. Note 7. This value is indicated as a ratio (%FSR) to the full-scale value. (TA = -40 to +105°C, 2.4 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = 0 V, reference voltage (+) = AVREFP (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) = AVREFM (ADREFM = 1), target pins: ANI2 to ANI14, internal reference voltage, and temperature sensor output voltage) Item Symbol Conditions Min. Typ. Max. Unit Resolution RES 12 bit Conversion clock fAD 13 2 MHz Overall errorNotes 1, 2, 3, 4, 5 AINL 4.5 V ≤ AVREFP = VDD ≤ 5.5 V ±2.4 ±4.5 LSB 2.7 V ≤ AVREFP = VDD ≤ 5.5 V ±2.9 ±5.7 LSB 2.4 V ≤ AVREFP = VDD ≤ 5.5 V ±3.0 ±5.8 LSB Conversion timeNotes 5, 6 tCONV 4.5 V ≤ AVREFP = VDD ≤ 5.5 V 2.0 µs 2.7 V ≤ AVREFP = VDD ≤ 5.5 V 2.0 µs 2.4 V ≤ AVREFP = VDD ≤ 5.5 V 2.0 µs Zero-scale errorNotes 1, 2, 3, 4, 5, 7 EZS 4.5 V ≤ AVREFP = VDD ≤ 5.5 V ±0.01 ±0.08 %FSR 2.7 V ≤ AVREFP = VDD ≤ 5.5 V ±0.01 ±0.09 %FSR 2.4 V ≤ AVREFP = VDD ≤ 5.5 V ±0.03 ±0.13 %FSR Full-scale errorNotes 1, 2, 3, 4, 5, 7 EFS 4.5 V ≤ AVREFP = VDD ≤ 5.5 V ±0.03 ±0.09 %FSR 2.7 V ≤ AVREFP = VDD ≤ 5.5 V ±0.05 ±0.13 %FSR 2.4 V ≤ AVREFP = VDD ≤ 5.5 V ±0.05 ±0.13 %FSR Analog input voltage V AIN 0A VREFP V Overall error/zero-scale error/full-scale error: Add (±0.75 LSB × (V DD voltage (V) - AVREFP voltage (V)) to the maximum value. Integral linearity error: Add (±0.2 LSB × (VDD voltage (V) - AVREFP voltage (V)) to the maximum value.

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 144 of 177 Oct 31, 2025 Note 1. This value does not include the quantization error (±1/2 LSB). Note 2. When pins ANI16 to ANI26 are selected as the target pins for conversion or the TSCAP voltage of the CTSU is to be A/D converted, the maximum values are as follows. Overall error: Add ±3 LSB to the maximum value. Zero-scale/full-scale error: Add ±0.04%FSR to the maximum value. Note 3. When reference voltage (+) = VDD and reference voltage (-) = VSS, the maximum values are as follows. Overall error: Add ±10 LSB to the maximum value. Zero-scale/full-scale error: Add ±0.25%FSR to the maximum value. Integral linearity error: Add ±4 LSB to the maximum value. Note 4. When AVREFP < VDD, the maximum values are as follows. Note 5. When the internal reference voltage or the temperature sensor output voltage is selected as the target for conversion, the sampling time must be at least 5 µs. Accordingly, use standard mode 2 with the longer sampling time. Note 6. This value is indicated as a ratio (%FSR) to the full-scale value. (TA = -40 to +105°C, 2.4 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = 0 V, reference voltage (+) = AVREFP (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) = AVREFM (ADREFM = 1), target pins: ANI2 to ANI14, internal reference voltage, and temperature sensor output voltage) Item Symbol Conditions Min. Typ. Max. Unit Resolution RES 8 12 Bit Conversion clock fAD 13 2 MHz Overall errorNotes 1, 2, 3, 4 AINL 12-bit resolution 4.5 V ≤ AVREFP = VDD ≤ 5.5 V ±7.5 LSB 2.7 V ≤ AVREFP = VDD ≤ 5.5 V ±9.0 LSB 2.4 V ≤ AVREFP = VDD ≤ 5.5 V ±9.0 LSB Conversion timeNote 5 tCONV 12-bit resolution 4.5 V ≤ AVREFP = VDD ≤ 5.5 V 2.0 µs 2.7 V ≤ AVREFP = VDD ≤ 5.5 V 2.0 µs 2.4 V ≤ AVREFP = VDD ≤ 5.5 V 2.0 µs Zero-scale errorNotes 1, 2, 3, 4, 6 EZS 12-bit resolution 4.5 V ≤ AVREFP = VDD ≤ 5.5 V ±0.17 %FSR 2.7 V ≤ AVREFP = VDD ≤ 5.5 V ±0.21 %FSR 2.4 V ≤ AVREFP = VDD ≤ 5.5 V ±0.21 %FSR Full-scale errorNotes 1, 2, 3, 4, 6 EFS 12-bit resolution 4.5 V ≤ AVREFP = VDD ≤ 5.5 V ±0.17 %FSR 2.7 V ≤ AVREFP = VDD ≤ 5.5 V ±0.21 %FSR 2.4 V ≤ AVREFP = VDD ≤ 5.5 V ±0.21 %FSR Integral linearity errorNotes 1, 3, 4 ILE 12-bit resolution 4.5 V ≤ AVREFP = VDD ≤ 5.5 V ±3.0 LSB 2.7 V ≤ AVREFP = VDD ≤ 5.5 V ±3.0 LSB 2.4 V ≤ AVREFP = VDD ≤ 5.5 V ±3.0 LSB Differential linearity errorNote 1 DLE 12-bit resolution 4.5 V ≤ AVREFP = VDD ≤ 5.5 V ±1.0 LSB 2.7 V ≤ AVREFP = VDD ≤ 5.5 V ±1.0 LSB 2.4 V ≤ AVREFP = VDD ≤ 5.5 V ±1.0 LSB Analog input voltage V AIN 0A VREFP V Overall error/zero-scale error/full-scale error: Add (±0.75 LSB × (V DD voltage (V) - AVREFP voltage (V)) to the maximum value. Integral linearity error: Add (±0.2 LSB × (VDD voltage (V) - AVREFP voltage (V)) to the maximum value. <R>

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 145 of 177 Oct 31, 2025 2. Low-voltage modes 1 and 2 Note 1. If the internal reference voltage, temperature sensor output voltage, or TSCAP voltage of the CTSU is to be A/D converted, VDD must be at least 1.8 V. Note 2. This value does not include the quantization error (±1/2 LSB). Note 3. When pins ANI16 to ANI26 are selected as the target pins for conversion or the TSCAP voltage of the CTSU is to be A/D converted, the maximum values are as follows. Overall error: Add ±3 LSB to the maximum value. Zero-scale/full-scale error: Add ±0.04%FSR to the maximum value. Note 4. When reference voltage (+) = VDD and reference voltage (-) = VSS, the maximum values are as follows. Overall error: Add ±10 LSB to the maximum value. Zero-scale/full-scale error: Add ±0.25%FSR to the maximum value. Integral linearity error: Add ±4 LSB to the maximum value. Note 5. When AVREFP < VDD, the maximum values are as follows. (TA = -40 to +105°C, 1.6 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = 0 V, reference voltage (+) = AVREFP (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) = AVREFM (ADREFM = 1), target pins ANI2 to ANI14, internal reference voltageNote 1, and temperature sensor output voltageNote 1) Item Symbol Conditions Min. Typ. Max. Unit Resolution RES 8 12 Bit Conversion clock fAD 12 4 MHz Overall errorNotes 2, 3, 4, 5 AINL 12-bit resolution 2.7 V ≤ AVREFP = VDD ≤ 5.5 V ±9 LSB 2.4 V ≤ AVREFP = VDD ≤ 5.5 V ±9 LSB 1.8 V ≤ AVREFP = VDD ≤ 5.5 V ±11.5 LSB 1.6 V ≤ AVREFP = VDD ≤ 5.5 V ±12.0 LSB Conversion timeNote 6 tCONV 12-bit resolution 2.7 V ≤ AVREFP = VDD ≤ 5.5 V 3.33 µs 2.4 V ≤ AVREFP = VDD ≤ 5.5 V 5.0 µs 1.8 V ≤ AVREFP = VDD ≤ 5.5 V 10.0 µs 1.6 V ≤ AVREFP = VDD ≤ 5.5 V 20.0 µs Zero-scale errorNotes 2, 3, 4, 5, 7 EZS 12-bit resolution 2.7 V ≤ AVREFP = VDD ≤ 5.5 V ±0.21 %FSR 2.4 V ≤ AVREFP = VDD ≤ 5.5 V ±0.21 %FSR 1.8 V ≤ AVREFP = VDD ≤ 5.5 V ±0.27 %FSR 1.6 V ≤ AVREFP = VDD ≤ 5.5 V ±0.28 %FSR Full-scale errorNotes 2, 3, 4, 5, 7 EFS 12-bit resolution 2.7 V ≤ AVREFP = VDD ≤ 5.5 V ±0.21 %FSR 2.4 V ≤ AVREFP = VDD ≤ 5.5 V ±0.21 %FSR 1.8 V ≤ AVREFP = VDD ≤ 5.5 V ±0.27 %FSR 1.6 V ≤ AVREFP = VDD ≤ 5.5 V ±0.28 %FSR Integral linearity errorNotes 2, 4, 5 ILE 12-bit resolution 2.7 V ≤ AVREFP = VDD ≤ 5.5 V ±4.0 LSB 2.4 V ≤ AVREFP = VDD ≤ 5.5 V ±4.0 LSB 1.8 V ≤ AVREFP = VDD ≤ 5.5 V ±4.5 LSB 1.6 V ≤ AVREFP = VDD ≤ 5.5 V ±4.5 LSB Differential linearity errorNote 2 DLE 12-bit resolution 2.7 V ≤ AVREFP = VDD ≤ 5.5 V ±1.5 LSB 2.4 V ≤ AVREFP = VDD ≤ 5.5 V ±1.5 LSB 1.8 V ≤ AVREFP = VDD ≤ 5.5 V ±2.0 LSB 1.6 V ≤ AVREFP = VDD ≤ 5.5 V ±2.0 LSB Analog input voltage V AIN 0A VREFP V Overall error/zero-scale error/full-scale error: Add (±0.75 LSB × (V DD voltage (V) - AVREFP voltage (V)) to the maximum value. Integral linearity error: Add (±0.2 LSB × (VDD voltage (V) - AVREFP voltage (V)) to the maximum value. <R> <R>

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 146 of 177 Oct 31, 2025 Note 6. When the internal reference voltage or the temperature sensor output voltage is selected as the target for conversion, the sampling time must be at least 5 µs. Accordingly, use standard mode 2 with the longer sampling time, and use the conversion clock (fAD) of no more than 16 MHz. Note 7. This value is indicated as a ratio (%FSR) to the full-scale value.

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 147 of 177 Oct 31, 2025 3. When the internal reference voltage is selected as reference voltage (+) Note 1. This value does not include the quantization error (±1/2 LSB). Note 2. This value is indicated as a ratio (%FSR) to the full-scale value. Note 3. When reference voltage (-) is selected as VSS, the maximum values are as follows. Zero-scale error: Add ±0.35%FSR to the maximum value. Integral linearity error: Add ±0.5 LSB to the maximum value. Note 4. Refer to 2.6.2 Temperature sensor/internal reference voltage characteristics. (TA = -40 to +105°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V, low-voltage modes 1 and 2, reference voltage (+) = internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (-) = AVREFM (ADREFM = 1) Item Symbol Conditions Min. Typ. Max. Unit Resolution RES 8 Bit Conversion clock fAD 1.6 V ≤ VDD ≤ 5.5 V 1 2 MHz Zero-scale errorNotes 1, 2, 3 EZS 1.6 V ≤ VDD ≤ 5.5 V ±0.6 %FSR Integral linearity errorNotes 1, 3 ILE 1.6 V ≤ VDD ≤ 5.5 V ±2.0 LSB Differential linearity errorNote 1 DLE 1.6 V ≤ VDD ≤ 5.5 V ±1.0 LSB Analog input voltage V AIN 0V BGR Note 4 V

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 148 of 177 Oct 31, 2025

2.6.2 Temperature sensor/internal reference voltage characteristics

2.6.3 D/A converter characteristics

2.6.4 Comparator characteristics

Note The internal reference voltage can be selected as comparator reference voltage only when 1.8 V ≤ VDD ≤ 5.5 V. (TA = -40 to +105°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Item Symbol Conditions Min. Typ. Max. Unit Temperature sensor output voltage VTMPS25 Setting ADS register = 80H, TA = +25°C 1.05 V Internal reference voltage V BGR Setting ADS register = 81H 1.42 1.48 1.54 V Temperature coefficient F VTMPS Temperature dependency of the temperature sensor voltage -3.3 mV/°C Operation stabilization wait time t AMP 5µ s (TA = -40 to +105°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Item Symbol Conditions Min. Typ. Max. Unit Resolution RES 8B i t Overall error AINL Rload = 8 M Ω 1.8 V ≤ VDD ≤ 5.5 V ±2.5 LSB Rload = 4 MΩ 1.8 V ≤ VDD ≤ 5.5 V ±2.5 LSB Settling time t SET Cload = 20 pF 2.7 V ≤ VDD ≤ 5.5 V 3 µs 1.6 V ≤ VDD ≤ 5.5 V 6 µs (TA = -40 to +105°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Item Symbol Conditions Min. Typ. Max. Unit Input voltage range I VREF Input to the IVREF0 and IVREF1 pins C0LVL = 0, C1LVL = 0 DD - 1.4 and EVDD0 V Input to the IVREF0 and IVREF1 pins C0LVL = 1, C1LVL = 1

1.4 EV DD0 V

IVCMP Input to the IVCMP0 and IVCMP1 pins -0.3 EVDD0 + 0.3 V Output delay td V DD = 3.0 V, Input slew rate > 1 V/µs High-speed mode 1.5 µs Low-speed mode 3.0 µs Offset voltage — High-speed mode 50 mV Low-speed mode 40 mV Operation stabilization wait time tCMP 30 µs Internal reference voltageNote VBGR2 1.4 1.6 V

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 149 of 177 Oct 31, 2025

2.6.5 POR circuit characteristics

Note This width is the minimum time required for a POR reset when VDD falls below VPDR. This width is also the minimum time required for a POR reset from when VDD falls below 0.7 V to when VDD exceeds VPOR in the STOP mode or while the main system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control register (CSC). (TA = -40 to +105°C, VSS = 0 V) Item Symbol Conditions Min. Typ. Max. Unit Detection voltage VPOR, VPDR 1.43 1.50 1.57 V Minimum pulse widthNote TPW 300 µs TPW VPOR VPDR or 0.7 V Supply voltage (VDD)

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 150 of 177 Oct 31, 2025

2.6.6 LVD circuit characteristics

LVD0 Detection Voltage in the Reset Mode and Interrupt Mode (TA = -40 to +105°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V) Item Symbol Conditions Min. Typ. Max. Unit Detection voltage Supply voltage level V LVD00 The power supply voltage is rising. 3.84 3.96 4.08 V The power supply voltage is falling. 3.76 3.88 4.00 V VLVD01 The power supply voltage is rising. 2.88 2.97 3.06 V The power supply voltage is falling. 2.82 2.91 3.00 V V LVD02 The power supply voltage is rising. 2.59 2.67 2.75 V The power supply voltage is falling. 2.54 2.62 2.70 V V LVD03 The power supply voltage is rising. 2.31 2.38 2.45 V The power supply voltage is falling. 2.26 2.33 2.40 V V LVD04 The power supply voltage is rising. 1.84 1.90 1.95 V The power supply voltage is falling. 1.80 1.86 1.91 V V LVD05 The power supply voltage is rising. 1.64 1.69 1.74 V The power supply voltage is falling. 1.60 1.65 1.70 V Minimum pulse width t LW 500 µs Detection delay time 500 µs

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 151 of 177 Oct 31, 2025 2. LVD1 Detection Voltage of Reset Mode and Interrupt Mode Note This setting can only be used when LVD0 is disabled. (TA = -40 to +105°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V) Item Symbol Conditions Min. Typ. Max. Unit Detection voltage Supply voltage level V LVD10 The power supply voltage is rising. 4.08 4.16 4.24 V The power supply voltage is falling. 4.00 4.08 4.16 V VLVD11 The power supply voltage is rising. 3.88 3.96 4.04 V The power supply voltage is falling. 3.80 3.88 3.96 V V LVD12 The power supply voltage is rising. 3.68 3.75 3.82 V The power supply voltage is falling. 3.60 3.67 3.74 V V LVD13 The power supply voltage is rising. 3.48 3.55 3.62 V The power supply voltage is falling. 3.40 3.47 3.54 V V LVD14 The power supply voltage is rising. 3.28 3.35 3.42 V The power supply voltage is falling. 3.20 3.27 3.34 V V LVD15 The power supply voltage is rising. 3.07 3.13 3.19 V The power supply voltage is falling. 3.00 3.06 3.12 V V LVD16 The power supply voltage is rising. 2.91 2.97 3.03 V The power supply voltage is falling. 2.85 2.91 2.97 V V LVD17 The power supply voltage is rising. 2.76 2.82 2.87 V The power supply voltage is falling. 2.70 2.76 2.81 V V LVD18 The power supply voltage is rising. 2.61 2.66 2.71 V The power supply voltage is falling. 2.55 2.60 2.65 V V LVD19 The power supply voltage is rising. 2.45 2.50 2.55 V The power supply voltage is falling. 2.40 2.45 2.50 V V LVD110 The power supply voltage is rising. 2.35 2.40 2.45 V The power supply voltage is falling. 2.30 2.35 2.40 V V LVD111 The power supply voltage is rising. 2.25 2.30 2.34 V The power supply voltage is falling. 2.20 2.25 2.29 V V LVD112 The power supply voltage is rising. 2.15 2.20 2.24 V The power supply voltage is falling. 2.10 2.15 2.19 V V LVD113 The power supply voltage is rising. 2.05 2.09 2.13 V The power supply voltage is falling. 2.00 2.04 2.08 V V LVD114 The power supply voltage is rising. 1.94 1.98 2.02 V The power supply voltage is falling. 1.90 1.94 1.98 V V LVD115 Note The power supply voltage is rising. 1.84 1.88 1.91 V The power supply voltage is falling. 1.80 1.84 1.87 V V LVD116 Note The power supply voltage is rising. 1.74 1.78 1.81 V The power supply voltage is falling. 1.70 1.74 1.77 V V LVD117 Note The power supply voltage is rising. 1.64 1.67 1.70 V The power supply voltage is falling. 1.60 1.63 1.66 V Minimum pulse width t LW 500 µs Detection delay time 500 µs

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 152 of 177 Oct 31, 2025

2.6.7 Power supply voltage rising slope characteristics

Caution Make sure to keep the internal reset state by the LVD0 circuit or an external reset until V DD reaches the operating voltage range shown in AC characteristics. (TA = -40 to +105°C, VSS = 0 V) Item Symbol Conditions Min. Typ. Max. Unit Power supply voltage rising slope SVDD 54 V/ms

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 153 of 177 Oct 31, 2025

2.7 RAM Data Retention Characteristics

Note This voltage depends on the POR detection voltage. When the voltage drops, the data in RAM are retained until a POR is applied, but are not retained following a POR.

2.8 Flash Memory Progr amming Characteristics

Note 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite. Note 2. The listed numbers of times apply when using flash memory programmer and Renesas Electronics self programming library. Note 3. These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics Corporation. (TA = -40 to +105°C, VSS = 0V) Item Symbol Conditions Min. Typ. Max. Unit Data retention supply voltage V DDDR 1.43Note 5.5 V (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Item Symbol Conditions Min. Typ. Max. Unit CPU/peripheral hardware clock frequency f CLK 13 2 MHz Number of code flash memory rewritesNotes 1, 2, 3 Cerwr Retained for 20 years TA = +85°C 1,000 Times Number of data flash memory rewritesNotes 1, 2, 3 Retained for 1 year TA = +25°C 1,000,000 Retained for 5 years TA = +85°C 100,000 Retained for 20 years T A = +85°C 10,000 VDD STOP instruction execution Standby release signal (interrupt request) STOP mode RAM data retention Operation mode VDDDR

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 154 of 177 Oct 31, 2025 1. Code flash memory Caution The listed values do not include the time until the operations of the flash memory start following execution of an instruction by software. 2. Data flash memory Caution The listed values do not include the time until the operations of the flash memory start following execution of an instruction by software. (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Item Symbol fCLK = 1 MHz f CLK = 2 MHz, 3 MHz 4 MHz ≤ fCLK < 8 MHz 8 MHz ≤ fCLK < 32 MHz f CLK = 32 MHz Unit Programming time Blank checking time 4 bytes t Time taken to forcibly stop the erasure t Time until programming starts following cancellation of the STOP instruction (TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Item Symbol fCLK = 1 MHz f CLK = 2 MHz, 3 MHz 4 MHz ≤ fCLK < 8 MHz 8 MHz ≤ fCLK < 32 MHz f CLK = 32 MHz Unit Programming time 1 byte t Blank checking time 1 byte t Time taken to forcibly stop the erasure t Time until programming starts following cancellation of the STOP instruction Time until reading starts following setting DFLCTL.DFLEN to 1

RL78/G23 2. Electrical Characteristics R01DS0395EJ0140 Rev.1.40 Page 155 of 177 Oct 31, 2025

2.9 Dedicated Flash Memory P rogrammer Communication (UART)

2.10 Timing of Entry to Flas h Memory Programming Modes

<1> The low level is input to the TOOL0 pin. <2> The external reset is released. Note that the POR and LVD reset must be released before the external reset is released. <3> The TOOL0 pin is set to the high level. <4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting. (TA = -40 to +105°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Item Symbol Conditions Min. Typ. Max. Unit Transfer rate During serial programming 115,200 1,000,000 bps (TA = -40 to +105°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Item Symbol Conditions Min. Typ. Max. Unit Time to complete the communication for the initial setting after the external reset is released tSUINIT POR and LVD reset must be released before the external reset is released. 100 ms Time to release the external reset after the TOOL0 pin is set to the low level t SU POR and LVD reset must be released before the external reset is released. 10 µs Time to hold the TOOL0 pin at the low level after the external reset is released (the processing time of the firmware to control the flash memory is not included) t HD POR and LVD reset must be released before the external reset is released. 1m s Remark tSUINIT : The time during which the communications for the initial setting must be completed within 100 ms after the external reset is released. tSU : Time to release the external reset after the TOOL0 pin is set to the low level tHD : Time to hold the TOOL0 pin at the low level after the external reset is released. It does not include the processing time of the firmware to control the flash memory. RESET TOOL0 tSU <4> tSUINIT 723 µs + tHD processing time 1-byte data for setting mode . . .

RL78/G23 3. Package Drawings R01DS0395EJ0140 Rev.1.40 Page 156 of 177 Oct 31, 2025 3. Package Drawings 3.1 30-pin Products P-LSSOP30-0300-0.65 PLSP0030JB-B S30MC-65-5A4-3 0.18 S S H J T I G D E F C B K P L U N ITEM B C I L M N A K D E F G H J P 30 16 11 5 A detail of lead end MM T MILLIMETERS 0.65 (T.P .) 0.45 MAX. 0.13 0.5 6.1p0.2 0.10 9.85p0.15 0.17p0.03 0.1p0.05 0.24 1.3p0.1 8.1p0.2 1.2 0.08 0.07 1.0p0.2 0.25 0.6p0.15U NOTE Each lead centerline is located within 0.13 mm of its true position (T.P .) at maximum material condition. 2012 Renesas Electronics Corporation. All rights reserved.

RL78/G23 3. Package Drawings R01DS0395EJ0140 Rev.1.40 Page 157 of 177 Oct 31, 2025 3.2 32-pin Products INDEX AREA (D/2 X E/2) D E SEATING PLANE ccc C 32X bbb C A B ddd C e b(32X) 1724 L(32X) K(32X) C aaa C B aaa C (A3) A1A eee C fff C A B fff C A B A 24 17 EXPOSED DIE PAD Reference Symbol Dimension in Millimeters Min. Nom. Max. A 䠉䠉 0.80 A1 0.00 0.02 0.05 A3 0.203 REF. b 0.18 0.25 0.30 D 5.00 BSC E 5.00 BSC e 0.50 BSC L 0 . 3 50 . 4 00 . 4 5 K 0.20 䠉䠉 D2 3.15 3.20 3.25 E2 3.15 3.20 3.25 aaa 0.15 bbb 0.10 ccc 0.10 ddd 0.05 eee 0.08 fff 0.10 P-HWQFN032-5x5-0.50 PWQN0032KE-A 0.06

RL78/G23 3. Package Drawings R01DS0395EJ0140 Rev.1.40 Page 158 of 177 Oct 31, 2025 2012 Renesas Electronics Corporation. All rights reserved. 0.145 ±0.055 (UNIT:mm) ITEM DIMENSIONS D E HD HE A 7.00±0.10 7.00±0.10 9.00±0.20 9.00±0.20 1.70 MAX. 0.10±0.10 1.40 c θ e x y 0.80 0.20 0.10 L 0.50±0.20 0° to 8° 0.37±0.05b NOTE 1.Dimensions “ 1” and “ 2” do not include mold flash. 2.Dimension “ 3” does not include trim offset. y e x bM θ L c HD HE A D E detail of lead end 32 9 P-LQFP32-7x7-0.80 PLQP0032GB-A P32GA-80-GBT -1 0.2

RL78/G23 3. Package Drawings R01DS0395EJ0140 Rev.1.40 Page 159 of 177 Oct 31, 2025 P-LQFP32-7x7-0.80 PLQP0032GE-A 0.18 䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉 /g84 䠉䠉䠉䠉䠉䠉

RL78/G23 3. Package Drawings R01DS0395EJ0140 Rev.1.40 Page 160 of 177 Oct 31, 2025 3.3 36-pin Products

RL78/G23 3. Package Drawings R01DS0395EJ0140 Rev.1.40 Page 161 of 177 Oct 31, 2025 3.4 40-pin Products INDEX AREA (D/2 X E/2) D SEATING PLANE ccc C bbb C A B ddd C e b(40X) L(40X) K(40X) C aaa C B aaa C (A3) A1A eee C fff C A B fff C A B A EXPOSED DIE PAD 11 0 2130 30 21 101 E 40X Reference Symbol Dimension in Millimeters Min. Nom. Max. A 䠉䠉 0.80 A1 0.00 0.02 0.05 A3 0.203 REF. b 0 . 1 80 . 2 50 . 3 0 D 6.00 BSC E 6.00 BSC e 0.50 BSC L 0 . 3 00 . 4 00 . 5 0 K 0.20 䠉䠉 D2 4.45 4.50 4.55 E2 4.45 4.50 4.55 aaa 0.15 bbb 0.10 ccc 0.10 ddd 0.05 eee 0.08 fff 0.10 P-HWQFN040-6x6-0.50 PWQN0040KD-A 0.08

RL78/G23 3. Package Drawings R01DS0395EJ0140 Rev.1.40 Page 162 of 177 Oct 31, 2025 3.5 44-pin Products

RL78/G23 3. Package Drawings R01DS0395EJ0140 Rev.1.40 Page 163 of 177 Oct 31, 2025 P-LQFP044-10x10-0.80 PLQP0044GE-A 0.34 䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉 /g84 䠉䠉䠉䠉䠉䠉

RL78/G23 3. Package Drawings R01DS0395EJ0140 Rev.1.40 Page 164 of 177 Oct 31, 2025 3.6 48-pin Products

RL78/G23 3. Package Drawings R01DS0395EJ0140 Rev.1.40 Page 165 of 177 Oct 31, 2025 P-LFQFP48-7x7-0.50 PLQP0048KL-A 0.18 䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉 /g84 䠉䠉䠉䠉䠉䠉

RL78/G23 3. Package Drawings R01DS0395EJ0140 Rev.1.40 Page 166 of 177 Oct 31, 2025 INDEX AREA (D/2 X E/2) D SEATING PLANE ccc C bbb C A B ddd C e b(48X) L(48X) K(48X) C aaa C B aaa C (A3) A1A eee C fff C A B fff C A B A EXPOSED DIE PAD 11 2 2536 E 48X 36 25 121 37 24 Reference Symbol Dimension in Millimeters Min. Nom. Max. A 䠉䠉 0.80 A1 0.00 0.02 0.05 A3 0.203 REF. b 0.20 0.25 0.30 D 7.00 BSC E 7.00 BSC e 0.50 BSC L 0 . 3 00 . 4 00 . 5 0 K 0.20 䠉䠉 D2 5.25 5.30 5.35 E2 5.25 5.30 5.35 aaa 0.15 bbb 0.10 ccc 0.10 ddd 0.05 eee 0.08 fff 0.10 P-HWQFN048-7x7-0.50 PWQN0048KC-A 0.13 g

RL78/G23 3. Package Drawings R01DS0395EJ0140 Rev.1.40 Page 167 of 177 Oct 31, 2025 3.7 52-pin Products y e x bM θ L c HD HE A D E 0.145 ±0.055 (UNIT:mm) ITEM DIMENSIONS D E HD HE A 10.00± 0.10 10.00± 0.10 12.00± 0.20 12.00± 0.20 1.70 MAX. 0.10±0.05 1.40 c θ e x y 0.65 0.13 0.10 L 0.50±0.15 0° to 8° detail of lead end 0.32±0.05b 152 2012 Renesas Electronics Corporation. All rights reserved. NOTE 1.Dimensions “ 1” and “ 2” do not include mold flash. 2.Dimension “ 3” does not include trim offset. P-LQFP52-10x10-0.65 PLQP0052JA-A P52GB-65-GBS-1 0.3

RL78/G23 3. Package Drawings R01DS0395EJ0140 Rev.1.40 Page 168 of 177 Oct 31, 2025 3.8 64-pin Products P-LQFP64-12x12-0.65 PLQP0064JA-A P64GK-65-UET -2 0.51 NOTE Each lead centerline is located within 0.13 mm of its true position at maximum material condition. detail of lead end Q L c Lp HD HE ZD ZE A D E 64 17 Sy e S x bM S 0.145 0.055 0.045 (UNIT:mm) ITEM DIMENSIONS D E HD HE A 12.00p 0.20 12.00p 0.20 14.00p 0.20 14.00p 0.20 1.60 MAX. 0.10p 0.05 1.40p 0.05 0.25 c Q e x y ZD ZE 0.65 0.13 0.10 1.125 1.125 L Lp 0.50 0.60p 0.15 1.00p 0.20 0.32 0.08 0.07b 2012 Renesas Electronics Corporation. All rights reserved.

RL78/G23 3. Package Drawings R01DS0395EJ0140 Rev.1.40 Page 169 of 177 Oct 31, 2025 MASS (Typ) [g] 0.3 Unit: mm Previous CodeRENESAS Code PLQP0064KB-C — P-LFQFP64-10x10-0.50 © 2015 Renesas Electronics Corporation. All rights reserved. D E HD HE A bp c T e x y Lp 9.9 9.9 11.8 11.8 0.05 0.15 0.09 0.45 Min Nom Dimensions in millimetersReference Symbol Max 10.0 10.0 1.4 12.0 12.0 0.20 3.5q 0.5 0.6 1.0 10.1 10.1 12.2 12.2 1.7 0.15 0.27 0.20 0.08 0.08 0.75 NOTE) 1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH. 2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET. 3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE LOCATED WITHIN THE HATCHED AREA. 4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY. HD A2A1 Lp Detail F A c 0.25 D 48 33 3249 161 F NOTE 4 NOTE 3 Index area HE E*2 bpe yS S M T

RL78/G23 3. Package Drawings R01DS0395EJ0140 Rev.1.40 Page 170 of 177 Oct 31, 2025 P-LFQFP064-10x10-0.50 PLQP0064KL-A 0.36 䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉 /g84 䠉䠉䠉䠉䠉䠉

RL78/G23 3. Package Drawings R01DS0395EJ0140 Rev.1.40 Page 171 of 177 Oct 31, 2025

RL78/G23 3. Package Drawings R01DS0395EJ0140 Rev.1.40 Page 172 of 177 Oct 31, 2025 3.9 80-pin Products MASS (Typ) [g] 0.6 Unit: mm Previous CodeRENESAS Code PLQP0080JA-B — P-LQFP80-14x14-0.65 © 2016 Renesas Electronics Corporation. All rights reserved. D E HD HE A bp c T e x y Lp 13.9 13.9 15.8 15.8 0.05 0.22 0.09 0.45 Min Nom Dimensions in millimetersReference Symbol Max 14.0 14.0 1.4 16.0 16.0 0.30 3.5q 0.65 0.6 1.0 14.1 14.1 16.2 16.2 1.7 0.15 0.38 0.20 0.13 0.10 0.75 NOTE) 1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH. 2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET. 3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE LOCATED WITHIN THE HATCHED AREA. 4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY. 4160 12 0 HD D*1 HE E NOTE 4 NOTE 3 Index area S e y S F *3 bp M A2A1 A Lp Detail F c 0.25 T

RL78/G23 3. Package Drawings R01DS0395EJ0140 Rev.1.40 Page 173 of 177 Oct 31, 2025 MASS (Typ) [g] 0.5 Unit: mm Previous CodeRENESAS Code PLQP0080KB-B — P-LFQFP80-12x12-0.50 © 2017 Renesas Electronics Corporation. All rights reserved. D E HD HE A bp c T e x y Lp 11.9 11.9 13.8 13.8 0.05 0.15 0.09 0.45 Min Nom Dimensions in millimetersReference Symbol Max 12.0 12.0 1.4 14.0 14.0 0.20 3.5q 0.5 0.6 1.0 12.1 12.1 14.2 14.2 1.7 0.15 0.27 0.20 0.08 0.08 0.75 NOTE) 1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH. 2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET. 3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE LOCATED WITHIN THE HATCHED AREA. 4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY. HD D*1 4160 12 0 HE E NOTE 4 NOTE 3 Index area S e y S bp M F A2A1 A Lp Detail F c 0.25 T

RL78/G23 3. Package Drawings R01DS0395EJ0140 Rev.1.40 Page 174 of 177 Oct 31, 2025 P-LFQFP80-12x12-0.50 PLQP0080KJ-A 0.49 䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉䠉 /g84 䠉䠉䠉䠉䠉䠉 <R>

RL78/G23 3. Package Drawings R01DS0395EJ0140 Rev.1.40 Page 175 of 177 Oct 31, 2025 3.10 100-pin Products MASS (Typ) [g] 0.6 Unit: mm Previous CodeRENESAS Code PLQP0100KB-B — P-LFQFP100-14x14-0.50 © 2015 Renesas Electronics Corporation. All rights reserved. D E HD HE A bp c T e x y Lp 13.9 13.9 15.8 15.8 0.05 0.15 0.09 0.45 Min Nom Dimensions in millimetersReference Symbol Max 14.0 14.0 1.4 16.0 16.0 0.20 3.5q 0.5 0.6 1.0 14.1 14.1 16.2 16.2 1.7 0.15 0.27 0.20 0.08 0.08 0.75 NOTE) 1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH. 2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET. 3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE LOCATED WITHIN THE HATCHED AREA. 4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY. T HD A2A1 Lp Detail F A c 0.25 D 100 26 251 F NOTE 4 NOTE 3 Index area HE E*2 *3 bpe yS S M

RL78/G23 3. Package Drawings R01DS0395EJ0140 Rev.1.40 Page 176 of 177 Oct 31, 2025 B Sy e S x bM L c Lp HD HE ZD ZE A D E S 0.145 (UNIT:mm) ITEM DIMENSIONS D E HD HE A 20.00 0.20 14.00 0.20 22.00 0.20 16.00 0.20 1.60 MAX. 0.10 0.05 1.40 0.05 0.07 0.08 0.055 0.045 0.25 c e x y ZD ZE 0.65 0.13 0.10 0.575 0.825 L Lp 0.50 0.60 0.15 1.00 0.20 detail of lead end 0.32b 100 31 A AB P-LQFP100-14x20-0.65 PLQP0100JC-A P100GF-65-GBN-1 0.92 2012 Renesas Electronics Corporation. All rights reserved.

RL78/G23 3. Package Drawings R01DS0395EJ0140 Rev.1.40 Page 177 of 177 Oct 31, 2025 3.11 128-pin Products Sy e S x bM L Q c Lp HD HE ZD ZE A D E S 0.145 (UNIT:mm) ITEM DIMENSIONS D E HD HE A 20.00p 0.20 14.00p 0.20 22.00p 0.20 16.00p 0.20 1.60 MAX. 0.10p0.05 1.40p0.05 0.25 c e x y ZD ZE 0.50 0.08 0.08 0.75 0.75 L Lp 0.50 0.60p0.15 1.00p0.20 detail of lead end b 128 39 65102 103 0.22 Q 3o 0.055 0.045 p0.05 A B AB 2012 Renesas Electronics Corporation. All rights reserved. P-LFQFP128-14x20-0.50 PLQP0128KD-A P128GF-50-GBP-1 0.92

Rev. Date

Description

1.00 Apr 13, 2021 — First edition issued

1.10 Nov 18, 2021 All The module name for 3-wire SPI was changed to simplified SPI. All The module name for SPI was changed to simplified SPI. p.1 The operating current in the title was modified. p.1 1.1 Features: The descriptions of Middle -speed on-chip oscillator were modified. p.2 1.1 Features: The descriptions of Timers were modified. p.4 Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G23 was modified. p.11 1.3.4 40-pin products: Figure was modified. p.12 1.3.5 44-pin products: Figure was modified. p.13 1.3.6 48-pin products: Note 2 was modified. p.13 1.3.6 48-pin products: Remark 3 was added. p.23 1.5 Block Diagram was modified. p.24 to p.26 1.6 Outline of Functions [30-, 32-, 36-, 40-, 44-, and 48-pin products]: The descriptions were modified. p.27 to p.29 1.6 Outline of Functions [52-, 64-, 80- , 100-, and 128-pin products]: The descriptions were modified. p.31 2.1 Absolute Maximum Ratings: Note was modified. p.32 2.2.1 Characteristics of the X1 and XT1 oscillators: Condition was modified. p.35 2.3.1 Pin characteristics: Notes 4 to 6 were modified. p.43 to p.49 2.3.2 Supply current characteristics, (1) 30- to 64-pin package products with 96- to 128- Kbyte flash ROM: The descriptions in the tables were modified. p.50 to p.56 2.3.2 Supply current characteristics, (2) 30- to 64-pin package products with 192- to 256- Kbyte flash ROM and 80-pin package product with 128- to 256-Kbyte flash ROM was added. p.57 to p.63 2.3.2 Supply current characteristics, (3) 44- to 80-pin package products with 384- to 768- Kbyte flash ROM and 100- to 128-pin package products was added. p.64 to p.66 2.3.2 Supply current characteristics, (4) Peripheral Functions (Common to all products): The descriptions in the tables were added. Notes 13, 14, and 16 were modified. Note 19 was modified. p.102 2.5.2 Serial interface UARTA: The table was modified. p.106 2.6.1 A/D converter characteristics, (1) Normal modes 1 and 2: The descriptions in the table were modified. p.108 2.6.1 A/D converter characteristics, (2) Low-voltage modes 1 and 2: The descriptions in the table were modified. P .110 2.6.1 A/D converter characteristics, (3) When the internal reference voltage is selected as reference voltage (+): The descriptions in the table were modified. p.111 2.6.4 Comparator characteristics: T he descriptions in the table were modified. p.114 2.6.6 LVD circuit characteristics, (2) LVD1 Detection Voltage of Reset Mode and Interrupt Mode: The table was modified. p.117 2.8 Flash Memory Programming Characteristics, (2) Data flash memory: The descriptions in the table were modified. p.123 3.4 40-Pin Products: The figure was added. p.126 3.6 48-Pin Products: The figure was added.

Revision History

1.20 Oct 12, 2022 p.5, p.6 Table 1 - 1 List of Ordering Part Numbers was modified. p.9, p.10 Table 1 - 2 Multiplexed Pin F unctions of the 30-pin Products was added. p.12, p.13 Table 1 - 3 Multiplexed Pin F unctions of the 32-pin Products was added. p.15, p.16 Table 1 - 4 Multiplexed Pin F unctions of the 36-pin Products was added. p.18, p.19 Table 1 - 5 Multiplexed Pin F unctions of the 40-pin Products was added. p.21, p.22 Table 1 - 6 Multiplexed Pin F unctions of the 44-pin Products was added. p.24, p.25 Table 1 - 7 Multiplexed Pin F unctions of the 48-pin Products was added. p.27, p.28 Table 1 - 8 Multiplexed Pin F unctions of the 52-pin Products was added. p.30 to p.32 Table 1 - 9 Multiplexed Pin Functions of the 64-pin Products was added. p.35 to p.37 Table 1 - 10 Multiplexed Pin Functions 2 of the 64-pin Products was added. p.39 to p.41 Table 1 - 11 Multiplexed Pin Functions of the 80-pin Products was added. p.43 to p.46 Table 1 - 12 Multiplexed Pin Functions of the 100-pin Products was added. p.48 to p.51 Table 1 - 13 Multiplexed Pin Functions 2 of the 100-pin Products was added. p.53 to p.57 Table 1 - 14 Multiplexed Pin Functions of the 128-pin Products was added. P .62 1.6 Outline of Functions [30-, 32-, 36-, 40-, 44-, and 48-pin products] was modified. P .65 1.6 Outline of Functions [52-, 64-, 80-, 100-, and 128-pin products] was modified. P .66 2 The section title was modified, and the description and Cautions 1 to 4 were added to the beginning of the section. p.67, p.68 2.1 Absolute Maximum Ratings was modified. p.69 2.2.1 Characteristics of the X1 oscillator was modified. p.69 2.2.2 Characteristics of the XT1 oscillator was added. p.72, p.75 to p.77, p.79 2.3.1 Pin characteristics, Note, and Cautions were modified. modified, and Note 20 was added. p.101 2.4 AC Characteristics was modified. 7 was added. p.156 3.3 36-pin Products was modified. p.164 3.8 64-pin Products was modified. 1.21 Nov 15, 2022 p.5 Table 1 - 1 List of Ordering Part Numbers was modified. 1.30 Jan 31, 2024 p.4 Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G23 was modified. p.5 to p.7 Table 1 - 1 List of Ordering Part Numbers was modified. p.80 2.3.2 Supply current characteristics, 1. 30- to 64-pin package products with 96- to 128- Kbyte flash ROM (1/4): Note 1 was modified. p.82 2.3.2 Supply current characteristics, 1. 30- to 64-pin package products with 96- to 128- Kbyte flash ROM (2/4): Notes 1 to 3 were modified. p.83 2.3.2 Supply current characteristics, 1. 30- to 64-pin package products with 96- to 128- Kbyte flash ROM (3/4): Note 1 was modified. p.86 2.3.2 Supply current characteristics, 1. 30- to 64-pin package products with 96- to 128- Kbyte flash ROM (4/4): Notes 1 and 3 to 8 were modified. Rev. Date

Kbyte flash ROM and 80-pin package product with 128- to 256-Kbyte flash ROM (1/4): Note 1 was modified. p.89 2.3.2 Supply current characteristics, 2. 30- to 64-pin package products with 192- to 256- Kbyte flash ROM and 80-pin package product with 128- to 256-Kbyte flash ROM (2/4): Notes 1 to 3 were modified. p.90 2.3.2 Supply current characteristics, 2. 30- to 64-pin package products with 192- to 256- Kbyte flash ROM and 80-pin package product with 128- to 256-Kbyte flash ROM (3/4): Note 1 was modified. p.93 2.3.2 Supply current characteristics, 2. 30- to 64-pin package products with 192- to 256- Kbyte flash ROM and 80-pin package product with 128- to 256-Kbyte flash ROM (4/4): Notes 1 and 3 to 8 were modified. p.94 2.3.2 Supply current characteristics, 3. 44- to 80-pin package products with 384- to 768- Kbyte flash ROM and 100- to 128-pin package products (1/4) and Note 1 was modified. p.96 2.3.2 Supply current characteristics, 3. 44- to 80-pin package products with 384- to 768- Kbyte flash ROM and 100- to 128-pin package products (2/4) and Notes 1 to 3 were modified. p.97 2.3.2 Supply current characteristics, 3. 44- to 80-pin package products with 384- to 768- Kbyte flash ROM and 100- to 128-pin package products (3/4) and Note 1 was modified. Kbyte flash ROM and 100- to 128-pin package products (4/4), Notes 1, and 3 to 8 were modified. p.104 2.4 AC Characteristics was modified. p.148 2.6.4 Comparator characteristics: Note was added. p.159 3.2 32-pin Products: The figure was added. p.163 3.5 44-pin Products: The figure was added. p.165 3.6 48-pin Products: The figure was added. p.170 3.8 64-pin Products: The figure was added. 1.40 Oct 31, 2025 p.6 Table 1 - 1 List of Ordering Part Numbers (2/3) was modified. p.60 1.6 Outline of Functions: Table was modified. p.75 2.3.1 Pin characteristics: Table (3/7) was modified. p.80 2.3.2 Supply current characteristics 1. 30- to 64-pin package products with 96- to 128-Kbyte code flash memory Table (1/4): Note 1 was modified. p.83 2.3.2 Supply current characteristics 1. 30- to 64-pin package products with 96- to 128-Kbyte code flash memory Table (3/4): Note 1 was modified. p.87 2.3.2 Supply current characteristics 2. 30- to 64-pin package products with 192- to 256-Kbyte code flash memory and 80-pin package product with 128- to 256-Kbyte code flash memory Table (1/4): Note 1 was modified. p.90 2.3.2 Supply current characteristics 2. 30- to 64-pin package products with 192- to 256-Kbyte code flash memory and 80-pin package product with 128- to 256-Kbyte code flash memory Table (3/4): Note 1 was modified. p.94 2.3.2 Supply current characteristics 3. 44- to 80-pin package products with 384- to 768-Kbyte code flash memory and 100- to 128-pin package products Table (1/4): Note 1 was modified. p.97 2.3.2 Supply current characteristics 3. 44- to 80-pin package products with 384- to 768-Kbyte code flash memory and 100- to 128-pin package products Table (3/4): Note 1 was modified. Rev. Date

1.40 Oct 31, 2025 p.104 2.4 AC Characteristics: Table was modified. p.139 2.5.2 Serial interface UARTA: Caution was modified. p.144 2.6.1 A/D converter characteristics 1. Normal modes 1 and 2: Note 2 was modified. p.145 2.6.1 A/D converter characteristics 2. Low-voltage modes 1 and 2: Notes 1 and 3 were modified. p.174 3.9 80-pin Products: Figure was added. Rev. Date SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc. All trademarks and registered trademarks are the property of their respective owners.

General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1. Precaution against Electrostatic Discharge (ESD) A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices. 2. Processing at power-on The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is ap plied to the external reset pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the level at which resetting is specified. 3. Input of signal during power-off state Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Follow the guideline for input signal during power-off state as described in your product documentation. 4. Handling of unused pins Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. 5. Clock signals After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or f rom an external oscillator during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable. 6. Voltage application waveform at input pin Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between V IL (Max.) and VIH (Min.). 7. Prohibition of access to reserved addresses Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these addresses as the correct operation of the LSI is not guaranteed. 8. Differences between products Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, im plement a system- evaluation test for the given product.

© 2025 Renesas Electronics Corporation. All rights reserved. Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operati on of semiconductor products and application examples. You are fully responsible for the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by you or third parties arising from the use of these circuits, software, or information. 2. Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims invo lving patents, copyrights, or other intellectual property rights of third parties, by or arising from the use of Renesas Electronics products or technical information described in this document, including but not limited to, the product data, drawings, charts, programs, algorithms, and application examples. 3. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. 4. You shall be responsible for determining what licenses are required from any third parties, and obtaining such licenses for the lawful import, export, manufacture, sales, utilization, distribution or other disposal of any products incorporating Renesas Electronics products, if required. 5. You shall not alter, modify, copy, or reverse engineer any Renesas Electronics product, whether in whole or in part. Renesas Electronics disclaims any and all liability for any losses or damages incurred by you or third parties arising from such alteration, modification, copyin g or reverse engineering. 6. Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The intended applications for each Renesas Electronics product depends on the product’s quality grade, as indicated below. "Standard": Computers; office equipment; communications equipm ent; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; industrial robots; etc. "High Quality": Transportation equipment (automobiles, trains, ship s, etc.); traffic control (traffic lights); large-scale communication equipment; key financial terminal systems; safety control equipment; etc. Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are not intended or authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems; surgical implantations; etc.), or may cause serious property damage (space system; undersea repeaters; nuclear power control systems; aircraft control systems; key plant systems; military equipment; etc.). Renesas Electronics disclaims any and all liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or other Renesas Electronics document. 7. No semiconductor product is absolutely secu re. Notwithstanding any security measures or features that may be implemented in Renesas Electronics hardware or software products, Renesas Electronics shall have absolutely no liability arising out of any vulnerability or security breach, including but not limited to any unauthorized access to or use of a Renesas Electronics product or a system that uses a Renesas Electronics product. RENESAS ELECTRONICS DOES NOT WARRANT OR GUARANTEE THAT RENESAS ELECTRONICS PRODUCTS, OR ANY SYSTEMS CREATED USING RENESAS ELECTRONICS PRODUCTS WILL BE INVULNERABLE OR FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (“Vulnerability Issues”). RENESAS ELECTRONICS DISCLAIMS ANY AND ALL RESPONSIBILITY OR LIABILITY ARISING FROM OR RELATED TO ANY VULNERABILITY ISSUES. FURTHERMORE, TO THE EXTENT PERMITTED BY APPLICABLE LAW, RENESAS ELECTRONICS DISCLAIMS ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, WITH RESPECT TO THIS DOCUMENT AND ANY RELATED OR ACCOMPANYING SOFTWARE OR HARDWARE, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY , OR FITNESS FOR A PARTICULAR PURPOSE. 8. When using Renesas Electronics products, refer to the latest product information (data sheets, user’s manuals, application notes, “General Notes for Handling and Using Semiconductor Devices” in the reliability handbook, etc.), and ensure that usage conditions are within the ranges specified by Renesas E lectronics with respect to maximum ratings, operating power supply voltage range, heat dissipation characteristics, installation, etc. Renesas Electronics disclaims any and all liability for any malfunctions, failure or accident arising out of the use of Renesas Electronics products outside of such specified ranges. 9. Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics products, semiconductor products have specific characteristics, such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Unless designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are not subject to radiation resistance design. You are responsible for implementing safety measures to guard against the possibility of bodily injury, injury or damage caused by fire, and/or danger to the public in the event of a failure or malfunction of Renesas Electronics products, such as safety design for hardware and software, including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult and impractical, you are responsible for evaluating the safety of the final products or systems manufactured by you. 10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. You are responsible for carefully and sufficiently investigating applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive, and using Renesas Electronics products in compliance with all these applicable laws and regulations. Renesas Electronics disclaims any and all liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. Renesas Electronics products and technologies shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. You shall comply with any applicable export control laws and regulations promulgated and administered by the governments of any countries asserting jurisdiction over the parties or transactions. 12. It is the responsibility of the buyer or distributor of Rene sas Electronics products, or any other party who distributes, disposes of, or otherwise sells or transfers the product to a third party, to notify such third party in advance of the contents and conditions set forth in this document. 13. This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics. 14. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products. (Note1) “Renesas Electronics” as used in th is document means Renesas Electronics Corporation and also includes its directly or indirectly controlled subsidiaries. (Note2) “Renesas Electronics product(s) ” means any product developed or manufactured by or for Renesas Electronics. (Rev.5.0-1 October 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners.

Product Information

R7F100GBH2DNP specifications and overview.

Summary

RENESAS MCU Rev.1.40 Oct 31, 2025

Description

RENESAS MCU Rev.1.40 Oct 31, 2025

Source title R7F100GBH2DNP Datasheet(PDF) - Renesas Technology Corp

Related Parts

More parts from the same family.

Browse manufacturer