R710FZ2T6

STR71XFXX STMICROELECTRONICS | Alldatasheet

Document overview

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• PDF pages: 80

Technical content

Datasheet sections

• 1 Introduction
• 2 Description
• 3 System architecture
• 3.1 On-chip peripherals
• 3.2 Related documentation
• 3.3 Pin description for 144-pin packages
• 3.4 Pin description for 64-pin packages
• 3.5 External connections
• 3.6 I/O port configuration
• 3.7 Memory mapping
• 4 Electrical parameters
• 4.1 Parameter conditions
• 4.1.1 Minimum and maximum values
• 4.1.2 Typical values
• 4.1.3 Typical curves
• 4.1.4 Loading capacitor
• 4.1.5 Pin input voltage
• 4.2 Absolute maximum ratings
• 4.3 Operating conditions
• 4.3.1 Supply current characteristics
• 4.3.2 Clock and timing characteristics
• 4.3.3 Memory characteristics
• 4.3.4 EMC characteristics
• 4.3.5 I/O port pin characteristics
• 4.3.6 TIM timer characteristics
• 4.3.7 EMI - external memory interface
• 4.3.8 I2C - inter IC control interface
• 4.3.9 BSPI - buffered serial periph eral interface
• 4.3.10 USB characteristics
• 4.3.11 ADC characteristics

Features

■ Core – ARM7TDMI 32-bit RISC CPU – 59 MIPS @ 66 MHz from SRAM – 45 MIPS @ 50 MHz from Flash ■ Memories – Up to 256 Kbytes Flash program memory (10 kcycles endurance, 20 years retention @ 85 ° C) – 16 Kbytes Flash data memory (100 kcycles endurance, 20 years retention@ 85 ° C) – Up to 64 Kbytes RAM – External Memory Interface (EMI) for up to 4 banks of SRAM, Flash, ROM – Multi-boot capability ■ Clock, reset and supply management – 3.0 to 3.6 V application supply and I/Os – Internal 1.8 V regulator for core supply – Clock input from 0 to 16.5 MHz – Embedded RTC osc. running from external 32 kHz crystal – Embedded PLL for CPU clock – Realtime Clock for clock-calendar function – 5 power saving modes: SLOW, WAIT, LPWAIT, STOP and STANDBY modes ■ Nested interrupt controller – Fast interrupt handling with multiple vectors – 32 vectors with 16 IRQ priority levels – 2 maskable FIQ sources ■ Up to 48 I/O ports – 30/32/48 multifunctional bidirectional I/Os Up to 14 ports with interrupt capability ■ 5 timers – 16-bit watchdog timer – 3 16-bit timers with 2 input captures, 2 output compares, PWM and pulse counter – 16-bit timer for timebase functions ■ 10 communication interfaces –2 I 2C interfaces (1 multiplexed with SPI) – 4 UART asynchronous serial interfaces – Smartcard ISO7816-3 interface on UART1 – 2 BSPI synchronous serial interfaces – CAN interface (2.0B Active) – USB Full Speed (12 Mbit/s) Device Function with Suspend and Resume – HDLC synchronous communications ■ 4-channel 12-bit A/D converter – Sampling frequency up to 1 kHz – Conversion range: 0 to 2.5 V ■ Development tools support – Atomic bit SET and RES operations Table 1. Device summary

STR71xFxx STR710RZ Contents Doc ID 10350 Rev 13 3/80

1 Introduction

For complete information on the STR71x microcontroller memory, registers and peripherals. please refer to the STR71x reference manual. please refer to the STR7 Flash programming reference manual. Table 2. Device overview

STR71xFxx STR710RZ Description Doc ID 10350 Rev 13 7/80

2 Description

ARM® core with embedded Flash and RAM The STR71x series is a family of ARM-powered 32-bit microcontrollers with embedded Flash and RAM. It combines the high performance ARM7TDMI CPU with an extensive range of peripheral functions and enhanced I/O capabilities. STR71xF devices have on-chip high-speed single voltage FLASH memory and high-speed RAM. STR710R devices have high-speed RAM but no internal Flash. The STR71x family has an embedded ARM core and is therefore compatible with all ARM tools and software. Extensive tools support STMicroelectronics’ 32-bit, ARM core-based microcontrollers are supported by a complete range of high-end and low-cost development tools to meet the needs of application developers. This extensive line of hardware/software tools includes starter kits and complete development packages all tailored for ST’s ARM core-based MCUs. The range of development packages includes third-party solutions that come complete with a graphical development environment and an in-circuit emulator/programmer featuring a JTAG application interface. These support a range of embedded operating systems (OS), while several royalty-free OSs are also available. For more information, please refer to ST MCU site http://www.st.com/mcu

System architecture STR71xFxx STR710RZ 8/80 Doc ID 10350 Rev 13

3 System architecture

Package choice: low pin-count 64-pin or feature-rich 144-pin LQFP or BGA The STR71x family is available in 5 main versions. The 144-pin versions have the full set of all features including CAN, USB and External Memory Interface (EMI).

• STR710F: 144-pin BGA or LQFP with CAN, USB and EMI
• STR710R: Flashless 144-pin BGA or LQFP with CAN, USB and EMI (no internal Flash memory) The three 64-pin versions (LQFP) do not include External Memory Interface.
• STR715F: 64-pin LQFP without CAN or USB
• STR711F: 64-pin LQFP with USB
• STR712F: 64-pin LQFP with CAN High speed Flash memory (STR71xF) The Flash program memory is organized in two banks of 32-bit wide Burst Flash memories enabling true read-while-write (RWW) operation. Device Bank 0 is up to 256 Kbytes in size, typically for the application program code. Bank 1 is 16 Kbytes, typically used for storing data constants. Both banks are accessed by the CPU with zero wait states @ 33 MHz Bank 0 memory endurance is 10K write/erase cycles and Bank 1 endurance is 100K write/erase cycles. Data retention is 20 years at 85°C on both banks. The two banks can be accessed independently in read or write. Flash memory can be accessed in two modes:
• Burst mode: 64-bit wide memory access at up to 50 MHz.
• Direct 32-bit wide memory access for deterministic operation at up to 33 MHz. The STR7 embedded Flash memory can be programmed using In-Circuit Programming or In-Application programming. IAP (in-application programming): The IAP is the ability to re-program the Flash memory of a microcontroller while the user program is running. ICP (in-circuit programming): The ICP is the ability to program the Flash memory of a microcontroller using JTAG protocol while the device is mounted on the user application board. The Flash memory can be protected against different types of unwanted access (read/write/erase). There are two types of protection:
• Sector Write Protection
• Flash Debug Protection (locks JTAG access) Refer to the STR7 Flash Programming Reference manual for details. Optional external memory (STR710) The non-multiplexed 16-bit data/24-bit address bus available on the STR710 (144-pin) supports four 16-Mbyte banks of external memory. Wait states are programmable individually for each bank allowing different memory types (Flash, EPROM, ROM, SRAM etc.) to be used to store programs or data. Figure 1 shows the general block diagram of the device family.

STR71xFxx STR710RZ System architecture Doc ID 10350 Rev 13 9/80 Flexible power management To minimize power consumption, you can program the STR71x to switch to SLOW, WAIT, LPWAIT (low power wait), STOP or STANDBY mode depending on the current system activity in the application. Flexible clock control Two external clock sources can be used, a main clock and a 32 kHz backup clock. The embedded PLL allows the internal system clock (up to 66 MHz) to be generated from a main clock frequency of 16 MHz or less. The PLL output frequency can be programmed using a wide selection of multipliers and dividers. The microcontroller core, APB1 and APB2 peripherals are in separate clock domains and can be programmed to run at different frequencies during application runtime. The clock to each peripheral is gated with an individual control bit to optimize power usage by turning off peripherals any time they are not required. Voltage regulators The STR71x requires an external 3.0-3.6V power supply. There are two internal Voltage Regulators for generating the 1.8V power supply for the core and peripherals. The main VR is switched off during low power operation. Low voltage detectors Both the Main Voltage Regulator and the Low Power Voltage Regulator contain each a low voltage detection circuitry which keep the device under reset when the corresponding controlled voltage value (V 18 or V18BKP) falls below 1.35V (+/- 10%). This enhances the security of the system by preventing the MCU from going into an unpredictable state. An external reset circuit must be used to provide the RESET at V33 power-up. It is not sufficient to rely on the RESET generated by the LVD in this case. This is because LVD operation is guaranteed only when V33 is within the specification.

3.1 On-chip peripherals

CAN interface (STR710 and STR712) The CAN module is compliant with the CAN specification V2.0 part B (active). The bit rate can be programmed up to 1 MBaud. USB interface (STR710 and STR711) The full-speed USB interface is USB V2.0 compliant and provides up to 16 bidirectional/32 unidirectional endpoints, up to 12 Mb/s (full-speed), support for bulk transfer, isochronous transfers and USB Suspend/Resume functions. Standard timers Each of the four timers have a 16-bit free-running counter with 7-bit prescaler Three timers each provide up to two input capture/output compare functions, a pulse counter function, and a PWM channel with selectable frequency. The fourth timer is not connected to the I/O ports. It can be used by the application software for general timing functions.

System architecture STR71xFxx STR710RZ 10/80 Doc ID 10350 Rev 13 Realtime clock (RTC) The RTC provides a set of continuously running counters driven by the 32 kHz external crystal. The RTC can be used as a general timebase or clock/calendar/alarm function. When the STR71x is in Standby mode the RTC can be kept running, powered by the low power voltage regulator and driven by the 32 kHz external crystal. UARTs The 4 UARTs allow full duplex, asynchronous, communications with external devices with independently programmable TX and RX baud rates up to 1.25 Mb/s. Smartcard interface UART1 is configurable to function either as a general purpose UART or as an asynchronous Smartcard interface as defined by ISO 7816-3. It includes Smartcard clock generation and provides support features for synchronous cards. Buffered serial peripheral interfaces (BSPI) Each of the two SPIs allow full duplex, synchronous communications with external devices, master or slave communication at up to 5.5 Mb/s in Master mode and 4 Mb/s in Slave mode. I 2C interfaces The two I2C Interfaces provide multi-master and slave functions, support normal and fast I2C mode (400 kHz) and 7 or 10-bit addressing modes. One I2C Interface is multiplexed with one SPI, so either 2xSPI+1x I2C or 1xSPI+2x I2C may be used at a time. HDLC interface The High Level Data Link Controller (HDLC) unit supports full duplex operation and NRZ, NRZI, FM0 or MANCHESTER protocols. It has an internal 8-bit baud rate generator. A/D converter The Analog to Digital Converter, converts in single channel or up to 4 channels in single- shot or round robin mode. Resolution is 12-bit with a sampling frequency of up to 1 kHz. The input voltage range is 0-2.5V. Watchdog The 16-bit Watchdog Timer protects the application against hardware or software failures and ensures recovery by generating a reset. I/O ports The 48 I/O ports are programmable as Inputs or Outputs. External interrupts Up to 14 external interrupts are available for application use or to wake up the application from STOP mode.

Figure 1. STR71x block diagram

System architecture STR71xFxx STR710RZ 12/80 Doc ID 10350 Rev 13

3.2 Related documentation

Available from www.arm.com: ARM7TDMI Technical reference manual Available from http://www.st.com: STR71x Reference manual STR7 Flash programming manual AN1774 - STR71x Software development getting started AN1775 - STR71x Hardware development getting started AN1776 - STR71x Enhanced interrupt controller AN1777 - STR71x memory mapping AN1780 - Real time clock with STR71x AN1781 - Four 7 segment display drive using the STR71x The above is a selected list only, a full list STR71x application notes can be viewed at http://www.st.com.

3.3 Pin description for 144-pin packages

Figure 2. STR710 LQFP pinout

pu= in reset state, the internal 100kΩ weak pull-up is enabled. pd = in reset state, the internal 100kΩ weak pull-down is enabled. Table 3. STR710 BGA ball connections

Table 4. STR710 pin description

16 G1 BOOTEN I C T

21 F5 V

22 F6 V 33 S Supply voltage for digital I/Os 4)

30 L1 JTDI I T T JTAG Data input. External pull-up required.

31 H2 JTMS I T T

33 H4 JTDO O 8mA X JTAG Data output. Note: Reset state = HiZ. 34 J2 JTRST I T T JTAG Reset Input. External pull-up required. 35 J3 NU Reserved, must be forced to ground. 36 K2 TEST Reserved, must be forced to ground. 38 L2 TEST Reserved, must be forced to ground.

40 K3 V 33IO-PLL S Supply voltage for digital I/O circuitry and for PLL

42 L4 V SSIO-PLL S Ground voltage for digital I/O circuitry and for PLL

44 M3 DBGRQS I C T Debug Mode request input (active high)

45 K4 CKOUT O 8mA X Clock output (fPCLK2) Note: Enabled by CKDIS

46 J4 CK I C Reference clock input

Port 0.15 Wakeup from Standby mode input. Note: This port is input only.

49 K5 RTCXTI Realtime Clock input and input of 32 kHz

50 J5 RTCXTO Output of 32 kHz oscillator amplifier circuit

51 M6 STDBY I/O C T 4mA X X

Software Standby mode entry.

52 M7 RSTIN IC T X Reset input

54 L6 V SSBKP S X Stabilization for low power voltage regulator.

55 K6 V 18BKP SX

Stabilization for low power voltage regulator. between V18BKP and VSS18BKP. See Figure 5.

58 G6 V 18 S

between V18 and VSS18. See Figure 5.

59 L7 V SS18 S Stabilization for main voltage regulator.

66 M11 V DDA S Supply voltage for A/D Converter

67 K8 V SSA S Ground voltage for A/D Converter

72 L10

83 H12 V 33IO-PLL S Supply voltage for digital I/O circuitry and for PLL

84 H11 V SSIO-PLL S Ground voltage for digital I/O circuitry and for PLL

90 G11 USBDP I/O C T

91 G10 USBDN I/O C T

Note: On STR710 and STR711 only.

103 E10 V SS S Ground voltage for digital I/O circuitry 4)

104 E9 V 33 S Supply voltage for digital I/O circuitry 4)

112 A9 V SS S Ground voltage for digital I/O circuitry 4)

113 B9 V 33 S Supply voltage for digital I/O circuitry 4)

128 D7 V SS18 S Stabilization for main voltage regulator.

129 E7 V 18 S

between V18 and VSS18. See Figure 5.

138 A3 V 33 S Supply voltage for digital I/Os 4)

139 A2 V SS S Ground voltage for digital I/Os 4)

1. The Reset configuration of the I/O Ports is IPUPD (input pull-up/pull down). Refer to Table 6 on page 30.
2. In reset state, these pins configured as Input PU /PD with weak pull-up enabled. They must be configured
3. In reset state, these pins configured as Input PU/PD with weak pull-down enabled to output Address
4. V 33IO-PLL and V33 are internally connected. VSSIO-PLL and VSS are internally connected.
5. During the reset phase, these pins ar e in input pull-up state. When reset is released, they are configured as
6. During the reset phase, these pins ar e in input pull-up state. When reset is released, they are configured as
7. During the reset phase, these pins are in input pull-dow n state. When reset is released, they are configured
8. During the reset phase, this pin is in input floating stat e. When reset is released, it is configured as Output

3.4 Pin description for 64-pin packages

Figure 3. STR712/STR715 LQFP64 pinout

1. CANTX and CANRX in STR712F only, in STR715F they are general purpose I/Os.

Figure 4. STR711 LQFP64 pinout pu= in reset state, the internal 100kΩ weak pull-up is enabled. pd = in reset state, the internal 100kΩ weak pull-down is enabled.

Table 5. STR711/STR712/STR715 pin description 10 JTDI I T T JTAG Data input. External pull-up required.

11 JTMS I T T

13 JTDO O 8mA X JTAG Data output. Note: Reset state = HiZ. 14 JTRST I T T JTAG Reset Input. External pull-up required. 15 NU Reserved, must be forced to ground. 16 TEST Reserved, must be forced to ground.

17 V 33IO-PLL S Supply voltage for digital I/O circuitry and for PLL

18 V SSIO-PLL S Ground voltage for digital I/O circuitry and for PLL

19 CK I C Reference clock input

Port 0.15 Wakeup from Standby mode input. Note: This port is input only.

21 RTCXTI Realtime Clock input and input of 32 kHz oscillator

22 RTCXTO Output of 32 kHz oscillator amplifier circuit

23 STDBY I/O C T 4mA X X

Software Standby mode entry. impedance except those marked Active in Stdby.

24 RSTIN IC T X Reset input

25 V SSBKP S X Stabilization for low power voltage regulator.

26 V 18BKP SX

Stabilization for low power voltage regulator. 18BKP and VSS18BKP. See Figure 5. between V18 and VSS18. See Figure 5. 28 V SS18 S Stabilization for main voltage regulator.

29 V DDA S Supply voltage for A/D Converter

30 V SSA S Ground voltage for A/D Converter

Table 5. STR711/STR712/STR715 pin description (continued)

38 V 33IO-PLL S Supply voltage for digital I/O circuitry and for PLL

39 V SSIO-PLL S Ground voltage for digital I/O circuitry and for PLL

42 USBDP I/O C T

43 USBDN I/O C T

Note: On STR710 and STR711 only.

44 V SS S Ground voltage for digital I/O circuitry 2)

50 V SS S Ground voltage for digital I/O circuitry 2)

51 V 33 S Supply voltage for digital I/O circuitry 2)

by SPI_EN bit in the BOOTCR register. by SPI_EN bit in the BOOTCR register. 57 V SS18 S Stabilization for main voltage regulator.

58 V 18 S

between V18 and VSS18. See Figure 5.

59 V SS S Ground voltage for digital I/Os

1. The Reset configuration of the I/O Ports is IPUPD (input pull-up/pull down). Refer to Table 6 on page 30.
2. V 33IO-PLL and V33 are internally connected. VSSIO-PLL and VSS are internally connected.

3.5 External connections

Figure 5. Recommended external connection of V 18 and V18BKP pins

3.6 I/O port configuration

N.A.: not applicable. In Output mode, a read access to the port gets the output latch value. Table 6. Port bit configuration table

3.7 Memory mapping

Figure 6. Memory map

4 Gbytes

272 Kbytes + regs

Figure 7. Mapping of Flash memory versions Table 7. RAM memory mapping

16 Kbytes 0x2000 0000 0x2000 3FFF

32 Kbytes 0x2000 0000 0x2000 7FFF

64 Kbytes 0x2000 0000 0x2000 FFFF

64 Kbytes + 16K RWW + regs

128 Kbytes + 16K RWW + regs

256 Kbytes + 16K RWW + regs

Figure 8. External memory map

64 MBytes

4 Electrical parameters

4.1 Parameter conditions

Unless otherwise specified, all voltages are referred to VSS.

4.1.1 Minimum and maximum values

selected temperature range). mean value plus or minus three times the standard deviation (mean±3Σ).

4.1.2 Typical values

4.1.3 Typical curves

4.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 9.

4.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 10. Figure 9. Pin loading conditions Figure 10. Pin input voltage

4.2 Absolute maximum ratings

Table 8. Voltage characteristics

The IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. corresponding VIN maximum must always be respected. Data based on TA = 25 °C. be connected to the external 3.3V supply. Section 4.3.11: ADC characteristics on page 66. (VSS18, VSSBKP) pins must always be connected to the external 1.8V supply. Table 9. Current characteristics Table 10. Thermal characteristics

4.3 Operating conditions

Subject to general operating conditions for V33, and TA.

1. Data guaranteed by characteri zation, not tested in production

Table 11. General operating conditions Table 12. Operating conditions at power-up / power-down

4.3.1 Supply current characteristics

• All I/O pins in input mode with a static value at V33 or VSS (no load)
• All peripherals are disabled except if explicitly mentioned.
• Embedded Regulators are used to provide 1.8V (except if explicitly mentioned) Subject to general operating conditions for V33, and TA. Notes: 1. Typical data are based on T A=25°C, V33=3.3V. 2. Data based on characterization results, tested in production at V 33, fMCLK max. and TA max. 3. Based on device characterisa tion, device power consumption in STOP mode at TA 25°C is predicted to be 30µA or less in 99.730020% of parts. 4. The conditions for these c onsumption measurements are described in application note AN2100.

Table 13. Total current consumption

Table 14. Typical power consumption data

1. Data based on a differential I DD measurement between reset configuration and timer counter running at

16MHz. No IC/OC programmed (no I/O pads toggling).

1. Data based on a differential I DD measurement between the on-chip peripheral when kept under reset and

not clocked and the on-chip peripheral when clocked and not kept under reset. No I/O pads toggling.

1. Data based on a differential I DD measurement between reset configuration and continuous A/D

Table 15. Peripheral current consumption

4.3.2 Clock and timi ng characteristics

Subject to general operating conditions for V33, and TA.

1. Data based on design simulation and/or technology characteristics, not tested in production.

Figure 14. CK external clock source Table 16. CK external clock characteristics

1. Data based on design simulation and/or technology characteristics, not tested in production.

Table 17. RTCXT1 external clock characteristics

The STR7 RTC clock can be supplied with a 32 kHz Crystal/Ceramic resonator oscillators. for more details (frequency, package, accuracy...).

1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with
2. t SU(OSC32KHZ) is the start-up time measured from the moment it is enabled (by software) to a stabilized

Figure 15. Typical application with a 32 kHz crystal Table 18. 32K oscillator characteristics (f OSC32K= 32.768 kHz)

Figure 16. RTC crystal oscillator and resonator Table 19. PLL1 characteristics

Table 20. PLL2 characteristics Table 21. Low-power mode wakeup timing

1. Clock selected is CK2_16, Main VReg OFF and Flash in power-down
2. The CLK clock is derived from the external oscillator.
3. Refer to Figure 7. Reset General Timing in the STR71xF Reference Manual (UM0084)

Table 19. PLL1 characteristics (continued)

4.3.3 Memory characteristics

V33 = 3.0 to 3.6V, TA = -40 to 85 °C unless otherwise specified.

1. T A=45°C after 0 cycles. Guaranteed by characterization, not tested in production.
2. Guaranteed by design, not tested in production

Table 22. Flash memory characteristics

4.3.4 EMC characteristics

Susceptibility tests are performed on a sample basis during product characterization. Functional EMS (electro magnetic susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs).

• ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard.
• FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709. Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations: The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical Data corruption (control registers...) Prequalification trials: Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). In the case of an ARM7 CPU, in order to write robust code that can withstand all kinds of stress, such as very strong electromagnetic disturbance, it is mandatory that the Data Abort, Prefetch Abort and Undefined Instruction exceptions are managed by the application software. This will prevent the code going into an undefined state or performing any unexpected operation.

norm SAE J 1752/3 which specifies the board and the loading of each pin.

1. Not tested in production.
2. BGA and LQFP devices have similar EMI characteristics.

product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181. JESD22-A114A/A115A standard. Table 23. EMS data Table 24. EMI data

0.1 MHz to 30 MHz 17 19

130 MHz to 1 GHz 11 11

1. Data based on characterization results, not tested in production.

• LU: 3 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181.
• DLU: Electro-Static Discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. Power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards. For more details, refer to the application note AN1181. Electrical sensitivities

Table 25. ESD absolute maximum ratings Table 26. Static and dynamic latch-up

1. Class description: A Class is an STMi croelectronics internal specification. All its limits are higher than the

Class strictly covers all the JEDEC criteria (international standard).

4.3.5 I/O port pin characteristics

an external pull-up or pull-down resistor.

1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
3. When the current limitation is not possible, the V IN absolute maximum rating must be respected, otherwise

induced by VIN<VSS. Refer to Section 4.2 on page 35 for more details.

1. Leakage could be higher than max. if negativ e current is injected on adjacent pins.
2. The R PU pull-up and RPD pull-down equivalent resistor are based on a resistive transistor (corresponding

IPU and IPD current characteristics described in Figure 18 to Figure 19). Table 27. I/O static characteristics

Subject to general operating conditions for V33 and TA unless otherwise specified.

1. The I IO current sunk must always respect the absolute maximum rating specified in Table 9 and the sum of

IIO (I/O ports and control pins) must not exceed IVSS.

1. The I IO current sourced must always respect the absolute maximum rating specified in Table 9 and the

sum of IIO (I/O ports and control pins) must not exceed IV33. Figure 21. Typical V OL and VOH at V33=3.3V (high current ports) Table 28. Output driving current

Subject to general operating conditions for V33 and TA unless otherwise specified.

1. Data based on characterization results, not tested in production.

2) Data guaranteed by design, not tested in production. Figure 24. Recommended RSTIN pin protection.1)

1. The R PU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current

characteristics described in Figure 18).

1. The reset network protects t he device against parasitic resets.
2. The user must ensure that the level on the RSTIN pin can go below the VIL(RSTINn) max. level specified in

Table 29. Otherwise the reset will not be taken into account internally. Table 29. RESET pin characteristics

4.3.6 TIM timer characteristics

external clock, PWM output...).

4.3.7 EMI - external memory interface

Subject to general operating conditions for VDD, fHCLK, and TA unless otherwise specified. Table 30. TIM characteristics

60 MHz 01 5 M H z

Table 31. EMI general characteristics

See Figure 25, Figure 26, Figure 27 and Figure 28 for related timing diagrams.

1. Data based on characterisation results, not tested in production.

See Figure 29, Figure 30, Figure 31 and Figure 32 for related timing diagrams.

1. Data based on characterisation results, not tested in production.

Table 32. EMI read operation Table 33. EMI write operation

Figure 31. Write cycle timing: 16-bit write on 8-bit memory Figure 32. Write cycle timing: 32-bit write on 8-bit memory See Table 33 for write timing data.

4.3.8 I2C - inter IC control interface

Subject to general operating conditions for V33, fPCLK1, and TA unless otherwise specified. disabled, but it is still present. Also, there is a protection diode between the I/O pin and V33. STR7X will be powered by the protection diode. characteristics (SDA and SCL).

1. Data based on standard I 2C protocol requirement, not tested in production.
2. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the

undefined region of the falling edge of SCL.

1. The maximum hold time t h(SDA) is not applicable.
2. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
3. f PCLK1, must be at least 8 MHz to achieve max fast I2C speed (400 kHz).
4. The following table gives the values to be wri tten in the I2CCCR register to obtain the required I2C SCL line

Table 34. I2C characteristics

Figure 33. Typical application with I2C bus and timing diagram The above variations depend on the accuracy of the external components used. Table 35. SCL Frequency Table ( fPCLK1=8 MHz.,V33 = 3.3 V)

20 C4h

4.3.9 BSPI - buffered ser ial peripheral interface

Subject to general operating conditions for VDD, TA and fPCLK1 ,unless otherwise specified. function characteristics (SS, SCK, MOSI, MISO). Table 36. BSPI characteristics

1. Data based on design simulation and/or char acterisation results, not tested in production.
2. Depends on f PCLK1. For example, if fPCLK1=8 MHz, then tPCLK1 = 1/fPCLK1 =125 ns and tv(MO) = 255 ns.
3. Min. time is the minimum time to drive the output and the max. time is the maximum time to validate the data.
4. Min time is the minimun time to invalidate the output and the max time is the maximum time to put the data in Hi-Z.

4.3.10 USB characteristics

The USB interface is USB-IF certified (Full Speed). Figure 37. USB: data signal rise and fall time Table 37. USB startup time Table 38. USB DC characteristics

1. All the voltages are measured from the local ground potential.
2. It is important to be aware that the DP/DM pins are not 5 V tolerant. As a consequence, in case of a a
3. RL is the load connected on the USB drivers

Table 39. USB: Full speed driver electrical characteristics

1. Measured from 10% to 90% of the data signal. For more detailed information, please refer to USB

Specification - Chapter 7 (version 2.0).

4.3.11 ADC characteristics

Subject to general operating conditions for AVDD, fPCLK2, and TA unless otherwise specified.

1. Unless otherwise specifi ed, typical data are based on TA=25°C and AVDD-AVSS=3.3V. They are given only

as design guidelines and are not tested.

1. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than

10kΩ). Data based on characterization results, not tested in production.

1. Calibration is needed once after each power-up.

Table 40. ADC characteristics

Data are based on characterisation and are not tested in production. current on robust pins is specified in Section 4.3.5. Section 4.3.5 does not affect the ADC accuracy. Table 41. ADC accuracy with f PCLK2 = 20 MHz, fADC=10 MHz, AVDD=3.3 V

Figure 38. ADC accuracy characteristics

1. Example of an actual transfer curve
2. End point correlation line

ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one.

5 Package characteristics

5.1 Package mechanical data

Figure 40. 64-Pin low profile quad flat package (10x10)

Figure 41. 144-Pin low profile quad flat package rounded to 3 decimal digits.

5.2 Thermal characteristics

• TA is the Ambient Temperature in ° C,
• ΘJA is the Package Junction-to-Ambient Thermal Resistance, in ° C/W,
• PD is the sum of PINT and PI/O (PD = PINT + PI/O),
• PINT is the product of IDD and VDD, expressed in Watts. This is the Chip Internal Power. PI/O represents the Power Dissipation on Input and Output Pins; Most of the time for the application PI/O< PINT and can be neglected. On the other hand, PI/O may be significant if the device is configured to drive continuously external modules and/or memories. An approximate relationship between PD and TJ (if PI/O is neglected) is given by: Therefore (solving equations 1 and 2): K = PD x (TA + 273°C) + ΘJA x PD 2 (3) where: K is a constant for the particular part, which may be determined from equation (3) by measuring P D (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ may be obtained by solving equations (1) and (2) iteratively for any value of TA.

Table 42. Thermal characteristics

6 Product history

identical and differ only with the points listed below. production replacing version "A". Version "Z" has lower power consumption in STOP mode. Version "X" is the latest introduced. four examples in Figure 45 through Figure 48. Figure 45. LQFP144 STR710 version “A” Figure 46. LQFP64 STR712 version “Z”

Figure 47. BGA144 STR710 version “Z” Figure 48. BGA64 STR711 version “X” Table 43. A, Z and X version differences

0001 Version bits [31:28] = 0010 Version bits [31:28] =

Line must be connected to an open drain buffer.

7 Ordering information

Figure 49. STR71xF ordering information scheme

1. For a list of available options (e.g. memory size, package) and orderable part numbers or for

STR71xFxx STR710RZ Known limitations Doc ID 10350 Rev 13 77/80

8 Known limitations

Description

If an IRQ or FIQ interrupt is pending and the Interrupt vector register (EIC_IVR) is not yet read, the HALT bit in the RCCU_SMR register can not be written. Therefore a software reset can not be generated. Workaround To generate a software reset when an IRQ or FIQ line is pending, either:

• reset the EIC peripheral by setting bit 14 in the APB2_SWRES register, or
• read the EIC_IVR register prior to generating a software reset.

9 Revision history

Table 44. Document revision history 08-Apr-2004 2.1 Corrected STR712F Pinout. Pins 43/42 swapped. 15-Apr-2004 2.2 PDF hyperlinks corrected. required’ to ‘External pull-up or pull down required’. Updated ordering information in Section 7. and flash register changed to 36 bytes.

Added notes under Table 4 on EMI pin reset state. Flash data retention changed to 20 years at 85° C. Table 44. Document revision history (continued)