R65C22C2 | DigiCamel IC Datasheet

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R65C22 ETC1 | Alldatasheet

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direction (input or output) on an individual line basis. . Figure 1. R65C22 Pin Assignments

R65C22 Versatile Interface Adapter (VIA)

ORDERING INFORMATION

Part Number: BUS INTERFACE INTERFACE Rescz2 | on Ca» <> moar Temperature Range (T, to Ty): Lcd cAY Blank = 0°C to +70°C _ E = -40°C to +85°C Rw Caz cst, C82 2 cer Frequency RSO-RS3 cB2 t= 1 MHz 2= 2MHz Ld a= MHz me K >

424 MHz PBO-PB7

¢ = 40-Pin Ceramic OIP oe P = 40-Pin Plastic DIP Fe Pisets Leaded Figure 2. R65C22 VIA Intertace Signals Chip Carrier (PLCC) = CHIP SELECTS (CS1, C52) Normally, the two chip select lines are connected to the micro- INTERFACE SIGNALS processor address lines. This connection may be direct or . through decoding. To access a selected R65C22 register, CS1 Figure 1 (on the front page) shows the R65C22 VIA pin assign- must be high (logic 1) and CS2 must be low (logic 0). ‘ments and Figure 2 groups the signals by functional interface. RESET (RES) REGISTER SELECTS (RSO-RS3) r (Re ) The Register Select inputs allow the microprocessor to select Reset (RES) clears all internal registers (except T1 and T2 one of 16 internal registers within the R65C22. Refer to Table 1 counters and latches, and the Shift Register (SR)). In the RES for Register Select coding and a functional description. condition, all peripheral interface lines (PA and PB) are placed — in the input state. Also, the Timers (T1 and 72), SR and inter- INTERRUPT REQUEST (IRQ) rupt logic are disabled from operation. ‘The Interrupt Request (IAG) output signal is generated whenever an internal Interrupt Flag bit is set and the corresponding Inter- INPUT CLOCK (PHASE 2) rupt Enable bit is @ Logic 1. The Interrupt Request output is an ‘The system Phase 2 (92) Input Clock controls all data transfers ‘open-drain configuration, thus allowing the IRQ signal to be between the R65C22 and the microprocessor. wire-ORed to a common microprocessor IRQ input line. READIWRITE (R/W) PERIPHERAL PORT A (PAO-PA7) The direction of the data tran: between the R65C22 and the Peripheral Data Port A is an 8-line, bidirectional bus for the sfers between tne Re transfer of data, control and status information between the system processor is controlled by the R/W line in conjunction see Cat and GS in ae R65C22 and a peripheral device. Each Peripheral Data Port bus puts. When R/W is low (write opera- A 1 line may be individually programmed as either an input or output tion) and the R65C22 is selected, data is transferred from the s processor bus into the selected R65C22 register. When RIW is under control of a Data Direction Register. Data flow direction 4 , may be selected on a line-by-line basis with intermixed input and high (read operation) and the R65C22 is selected, data is trans- ‘output lines within the same port a0" is written to any ferred from the selected R65C22 register to the processor bus. bit position of the Data Direction Register, the corresponding tine will be programmed as an input. When a “1” is written into DATA BUS (D0-07) any bit position of the register, the corresponding data line will ‘The eight bidirectional Data Bus lines transfer data between the ‘serve as an output. Polarity of the data output is determined by R65C22 and the microprocessor. During a read operation, the ‘the Output Register, while input data may be latched into the contents of the selected R65C22 internal register are transferred Input Register under control of the CAt line. All modes are pro- to the microprocessor via the Data Bus lines, During a write ‘gram controlled by the microprocessor by way of the R65C22's operation, the Data Bus lines serve as high impedance inputs internal control registers. Each Peripheral Data Port line repre- over which data is transferred from the microprocessor to a ‘sents two TTL loads in the input mode and will drive two standard selected R65C22 register. The Data Bus lines are in the high TTL loads in the output mode. A typical output circuit for impedance state when the R65C22 is unselected. Peripheral Data Port A is shown in Figure 3. 1-32

internal Interrupt Flag with a corresponding Interrupt Enable bit. loads in the input mode and will drive two TTL loads in the toads in the output mode. Table 1. R65C22 Register Addressing Figure 3. Port A and B Output Circuits

Figure 9. Read Handshake Timing (Port A Only)

2 SU eS UL

Figure 10. Write Handshake Timing

Figure 14. Auxiliary Control Register (ACR) in Figure 15. ‘ed in this specification.

1 COUNTER ’

Figure 15. Timer 1 One-Shot Mode Timing

R65C22 Versatile Interface Adapter (VIA) eee Oo Timer 1 Free-Run Mode the time-out can be prevented completely if the processor con- tinues 10 rewrite the timer before it reaches zero. Timer 1 will in this manner if the processor writes into the high order The most important advantage associated with the latches in T1 ‘operate in o is the ability to produce a continuous series of evenly spaced counter (T1C-H). However, by loading the latches only, the interrupts and the ability to produce a square wave on PB7 whose Processor can access the timer during each down counting frequency is not affected by variations in the processor interrupt ‘operation without affecting the time-out in process. Instead, the response time. This is accomplished in the “free-running” mode. data loaded into the latches wil determine the length of the next time-out period. This capability is particularly valuable in the free- running mode with the output enabled. In this mode, the signal In the free-running mode, the interrupt flag is set and the signal on PB7 is inverted and the interrupt flag is set with each time- on PB7 is inverted each time the counter reaches zero at which ut. By responding to the interrupts with new data for the latches, time the timer automatically transfers the contents of the latch the processor can determine the period of the next half cycle into the counter (16 bits) and continues to decrement from there. during each halt cycle of the output signal on PBT. In this manner, The interrupt flag can be cleared by writing TIC-H or TIL-H, by very complex waveforms can be generated. reading TIC-L, or by writing directly into the flag as described later. However, itis not necessary to rewrite the timer to enable ‘A precaution to take in the use of PB7 as the timer output con- ‘setting the interrupt flag on the next time-out. cerns the Data Direction Register contents for P87. Both DDRB- bit 7 and ACR bit 7 must be 1 for PB7 to function as the timer All interval timers in the R65C22 are “‘re-riggerable”. Rewriting output. If one is 1 and other is 0, then PB7 functions as @ nor- the counter will always re-initialize the time-out period. In fact, mal outpin pin, controlled by ORB bit 7. were Tie | | | | operation —S Lj, —> | IRO ourpuT 1 _ pa ourput 1 rr es | ws ts cveres—-|- w+ 2everes | Figure 16, Timer 1 Free-Run Mode Timing Timer 2 Operation decrementing again through zero. The processor must rewrite Timer 2 operates as an interval timer (in the “one-shot” mode T2C-H to enable setting of the interrupt flag. The interrupt fag is cleared by reading T2C-L or by writing T2C-H. Timing for this only), of as a counter for counting negative pulses on the PBS operation is shown in Figure 18. peripheral pin. A single control bitin the Auxiliary Control Register ‘o selects between these two modes. This timer is comprised of 2 “write-only” lower-order latch (T2L-), a “read-only” loworder Timer 2 Pulse Counting Mode i ). Th counter (T2C-L) and & read/write high order counter (T2C-H), The In the pulse counting mode, T2 counts a predetermined number counter registers act as a 16-bit counter which decrements at sa " 02 rate. Figure 17 illustrates the T2 Latch/Counter Registers. of negative-going pulses on PBS. This is accomplished by first loading a number into T2. Writing into T2C-H clears the inter- wi rupt flag and allows the counter to decrement each time a pulse Timer 2 One-Shot is applied to PBS, The interrupt flag is set when T2 counts down As an interval timer, T2 operates in the “one-shot” mode similar past zero. The counter will then continue to decrement with each to Timer 1. In this mode, T2 provides a single interrupt for each pulse on PBS. However, it is necessary to rewrite T2C-H to allow “write T2C-H” operation. Atter timing out, the counter will con- the interrupt flag to set on a subsequent time-out. Timing for this tinue to decrement. However, setting of the interrupt flag is dis- mode is shown in Figure 19. The pulse must be low on the leading abled after initial time-out so that it will not be set by the counter edge of 02. 1-99

2 COUNTER No [out {ne | ns | | 0 | FrFF | FFE | FrFD | FFFC |

Figure 18. Timer 2 One-Shot Mode Timing

he shift register counter will interrupt the processor each time the shift ‘counter is disabled. 8 bits have been shifted in. The shift register stops after 8 counts . Mode 4 is very similar to mode 1 in which the shifting rate is the SR Interrupt Flag is set and CB2 remains at the last data level. Figure 24. SR Mode 3 — Shift In Under CB1 Control

82 OUTPUT RRR XB XC XO |

Figure 25. SR Mode 4 — Shift Out Under T2 Control (Free-Run)

within the chip. Interrupt flags are set in the Interrupt Flag leak . Register (IFR) by conditions detected within the R65C22 or on x = logic AND, + = Logic OR. highest to lowest priority. as discussed in the next section. Interrupt Flag Register (IFR) 0 clears the corresponding bit in the Interrupt Enable Register. In the R65C22, all the interrupt flags are contained in one register, unaffected. processor. In addition, individual flag bits may be cleared by writ- ‘of the interrupts during system operation. ‘the status of the IRQ output. This bit corresponds to the logic however. Figure 29. Interrupt Flag Register (IFR) Figure 30. Interrupt Enable Register (IER)

R65C22 Versatile Interface Adapter (VIA) SWITCHING CHARACTERISTICS (Vcc = 5:0 Vdc +5%, Vg = 0, Ta = T, to Ty, unless otherwise noted) PERIPHERAL INTERFACE TIMING [io nd Fa Tne tr GH, O07, Ghz ard cB2 nowt Sera ws | | 0 | | — eile ce ad el of pulse mode) [aly Tine, Cock nega Tansionw GA2 Pome Tans no nead | ws | Pe w]e] Delay Tie. CAT Ave Traelion lo GK2 Posi Tension indshake made) [tng [= [a0 foe] a] liaise cd Mal al el [ety Tn, Pog Gua aia CHE nag Faron | eo | | a [iy Tire, Ck Posie Tariton to CA@ or CB Ponte Taraon ue rede) | tas | — | 10 |» | —_ate_| Ee i al a (handshake mode) [ow Tre Regured Fon C2 Ops 1 CAT Acie anand nado) [tw | #00 | =| m= | aa] [Seip Tine, Perphr! Data vai to CA o OY Ache Tanson put were) | te | 000” | — | mm | ave | [ent 81 Setup Pier anoton Am tah tg ae] Peripheral Data Hold Aer CAt, CB1 Transition es ee [Sina t= tons oe | pa | stn Su Tie — Tine for C82 Oats no 9 Ring E690 | tox | aw | ~ | me | any | [sr Shit Cock 1) Sup ane Rove 02 Teng E698 | tou | 10 | Ter |= | —at5 | [ruse Wath Poo pu use ef Tee Po] a a Pulse Spacing — PBS input Pulse [tes | 2* Tey | | a BUS TIMING __Parameter Symbot_{ win [wax [win [wax [win [wax | win wean [ao | =| ae [= f= | eof me] ae [prose ruse wanton | tex | 0 | — | ao] = [wo | — [we | — [=] am [rree2tonsnon | tw | - |» ]-- | =] - 7») - |] »] | [Read | Select Riv soup [ tacn [veo [ — [oo [ - [oe [= To [= Tm | [sous aise | ea Je = [of = po =| ep pm] [oa 8s Ovsy | te | =] met - [we | =m | | = |] a Perptwol Da Soup | wen | 00 = | wo | =| vo | =} m=] — 1 =| [vee | Sewct an sewp | tuow [veo [ - [9% | = [eT = [ows [= Tos | [Seiecr RWHo | tew [|e | = | oe [= [oe T= [oo | — [oe | [Data evs Sewe | tow [ves f= fs | | es | = [we [Te | [Data BusHold | tw | 10 | =~ | 10 va) Pe gt SS SH Pesigheral Dain Dolry teow [= [4000 [= = | so [= [0 [ns |

R65C22 Versatile Interface Adapter (VIA) ABSOLUTE MAXIMUM RATINGS* [Parameter —__[Symbot[Vatwe [unt | “NOTE: Stresses above those listed may cause permanent [Supphy Votiage | eo | 0810 +70 | vee| damage to the device. This 8 str088 a on oe spore Vorteae. Noe. O30 +70 {Noe al operation of the device at these or any other conditions above Input Vottage those indicated in the other sections of this document is not ‘Output Voltage | Vour_[-0.8 to Voq +0.3| Vac | implied. Exposure to absolute maximum rating conditions for Operating Temperate th ra extended periods may affect device reliability ‘Commercial Oto +70 Industrial 40 to +85 [Storage Temperature | Tore | —s5to +160 °c] OPERATING CONDITIONS [Supply vonage | Yeo Sv 8% | Temperature Range 710 Tw Commercial 0°C to 70°C Industrial = 40°C to + 85°C

ELECTRICAL CHARACTERISTICS

(Woe = 5.0 Vde 45%, Ves = 0, Ta = Ti to Ty, unless otherwise noted) [Paramitar ———«d Sembh [ win. Typ? [max [unit Test Conations_| Input High Vorage v Logie +20 Vee 6 324 Vee Tnput Low Voltage Logie -03 +08 $2 =04 404 Input Leakage Current _ we TA | Vai = OV 10 Veo IW, RES, RSO, RS1, AS2, AS3, CS1, CS2, CA1, 2 Veo = 5.25V Input Leakage Current for Three-State Off rst £10 yA | Vm = 0.4V 0 24V 00-07 Veo "= 525V Tut High Current TA [Vm = 24V PAQ-PA7, CA2, PBO-P87, CBI, CB2 Input Low Current ma |v, = 04V PAO-PA7, CA2, PBO-PB7, CB, CB2 Sutput High Voltage Von Voo = 475 Al outputs Vv | hono = 200 9A PBO-PB7, CBI and CB2 (Darlington Drive) v loan? = -3.2 mA Output Low Voltage Pry Vv | Voc = 475¥ PAQ-PA7, CA2, PBO-PB7, CBI, CB2, hon = 3.2 mA D0-D7, IRO Kegan = 1.6 mA ‘Output High Current Sourcing) on Logie wr | Vow = 24V PBO-PB7, CB1 and CB2 (Darlington Drive) mA | Von = 1.8V Output Low Current (Sinking) Te | 3 [| - [| = [oma |va-o | Output Leakage Current (Ott State) loer oA [Vou = 24¥ ko Vor = 5.25V [PoworDisspaion i eT | | tO fw | Input Capacitance Veo = 5.0V DO-D7, PAO-PAT, CAt, CA2, PB0-PB7, CBI, CB2 10 pe | Vas ov RW, RES, RSO, RS1, RS2, RS3, CS1, CS2, 7 pF t= 2MHz 2 20 pF | t= 25°C [ups Gapactance SSCs oe | | | PP Notes: . 1. All units are direct current (DC) except for capacitance. 2. Negative sign incicates outward current flow, posve indicates inward flow. 3, Typical values shown for Voc = 5.0V and T, = 25°C. 1-50

R65C22 Versatile Interface Adapter (VIA) R65NC22/R65C22 DIFFERENCES 1. Register select lines are decoded during $2. 4. Register select lines are decoded during #2 only if CS2 is active tow. 2. CB1 must not change during last 100 ns of #2. CB1 must have a 2. CBI can change anytime but is sampled only during #2, CB1 must pulse width greater than one period have a pulse greater than one period 3. PBO-PBT and CB1, CB2 have active pull-ups 3. PBO-PB7 and CB1, CB2 have passive pull ups (~3 KO). 4. PBO-PB7, CBI and CB2 represent two standard TTL loads in the 4, PBO-PB7, CBI and CB2 represent one standard TTL load in the input input mode end wil dive two standard TTL loads inthe output mode. mode and will drive one standard TTL load in the output mode. 1-52

Product Information

R65C22C2 specifications and overview.

Summary

Versatile Interface Adapter (VIA)

Description

Versatile Interface Adapter (VIA)

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