R65C21 ETC1 | Alldatasheet

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‘¢ Commercial and industrial temperature range versions. Figure 1. R65C21 Pin Assignments

Table 1. ORA and ORB Register Addressing INTERRUPT INPUT/PERIPHERAL CONTROL LINES Hla Read CRB {Write CRB 6n this input will set bit 7 of the Control Register A to a logic 1. ‘The active low Interrupt Request lines (IRQA and iRQB) act to transition. request line services one peripheral data port. and 7 in the two Control Registers (CRA, CRB). These flags act peripheral device andthe processor interrupt structure, The inter. microprocessor interrupt inputs. Each flag has a corresponding system interrupt. setting bit 0 in CRA to a 0. Likewise, CRA bit 6 (IRQA2) is make sequential data available on the Peripheral input lines. Table 2. Jow. This signals the peripheral device that t can make newdata controlled by CRB bit3. Also, both bit 6 and bit 7 of CRB are reset respectively. by a "Read Peripheral B Output Register” operation. FRB goes tow (Active) fers from the processor into the peripheral device.

Registers (DRA, DDAB) and the Output Registers (ORA, ORB). Figure 3. R65C21 PIA Block Diagram

Table 3. Control Registers Bit Designations to program each line in the 8-bit Peripheral V/O port to be either Tho ewniches can atnka tui a.2 mA, makiog these butters supa. rere VO line to act as an input; a 1 causes it to act as an lines also represent two standard TTL loads in the input mode. will not go higher than + 2.4 Vde. “The four interruptiperipheral control lines (CA1, CA2, CB1, CB2) switch, such as @ Darlington pair. for those lines programmed to act as inputs. by writing data into the Peripheral Output Register. They also allow put buffer enters the high impedance state. causes the corresponding Peripheral /O lines to act as.an input. in an input mode).

0 No transition has occurred on CA\\ that satisfies the bit 1 |RQA1 transition polarity criteria. 1 | Select Output Register A. 0 | Select Data Direction Register A. 1 | Enable assertion of IRQA when IRQA\\ Flag (bit 7)is set. ° Disable assertion of IRQA when IRQA1 Flag (bit 7) is set. 1 transition has occurred on CA2 that satisfies the bit 4 0 Always zero. BRS CA2 MODE SELECT 1 (CA2 goes low when a zero is written into CRA bit 3. ° ‘Select CA2 Input Mode. CA2 goes high when a one is written into CRA bit 3.

0 CA2 goes low on the first negative (high-to-low) 62 clock

Bit4 IRQA2 TRANSITION SELECT transition following a read of Output Register A.

1 SetIRQA2 Flag bit )on a positive (low-t-high) transition CA2 returns high as specified by bit3

transition following a read of Output Register A. Figure 4. Control Line Operations Summary (1 of 2)

0 No transition has occurred on CB1 that satisfies the bit 1 IRQB1 transition polarity criteria. 1 | Select Output Register B. 1 | Enable assertion of RGB when IROB! Flag (bit 7) is set. 1 A transition has occurred on CB2 that satisfies the bit 4 0 Always zero. 0 Select CB2 Input Mode, ‘CB2 goes high when a one is written into CRB bit 3. ‘Bit4 — IRQB2 TRANSITION SELECT transition following a read of Output Register 8.

1 Set ROB2 Flag bit6) ona positive low-to-high transition 082 returns high as specified by bit 3

transition folowing a read of Output Register B. ° Disable assertion of IROB when IRQA2 Flag (bit 6) is set. bit 1. Figure 4. Control Line Operations Summary (2 of 2)

READING THE PERIPHERAL A 1/0 PORT +24 Vde when the Peripheral Output register contains alogic 1. situation, the data bus will contain both the input and output data. ‘and output data in a manner similar to the Peripheral A port. This is true when the I/O pin is not allowed to go to a full processor on a Read operation. Figure 5. Read Timing Wavetorms

Figure 6. Write Timing Waveform

R65C21 Peripheral Interface Adapter (PIA) ee SWITCHING WAVEFORMS (Voc = 5.0 Vde +5%, Vsg = 0, Ty = Ty to Th, unless otherwise noted) BUS TIMING La a to oe | a | Parameter Symbo! ae $2 Pulse Width te | a0 [= 7 20 | = | eo [— | to [= Tos | [e2Risoandfaitime | tote | — | 2 | — | ws | — [ w | = | [ns | [Address SerupTime | tac | tao | — | of — [oss | — [oss | — Ts | [Address Hoistime | tom | 0 | — | 0 | = | oo | — [oo | = | ns | ae bet Data Bus Hold Time | twa | — | 20 | Write = — hase Sop Tne a ‘Address Hold Time {tow | 0 [| — [oe | = | o | - | oo] — J as | [RwWseuptime | tac | 100 | — | 9 | — [oo [| — [as | ~ T ns | [pwHowtime | tow | 0 | = | oo | — | io | = [oo | = [ns | Data Bus Set-Up Time [ete fae | ps—= fe Data Bus Hold Time _ tw sf 2 | as | Peripheral Data Delay Time low | — | 10 | | 05 | | = fos | us | Peripneral Data Delay Time toes [= [2 [= re f-f7 Toi" TOCMOS Lovel _ _ _ _ PERIPHERAL INTERFACE TIMING [Peripheral Data Setuo ten | 900 [ — [sso [ — Tuo [ — Tm | — [ns | [ wetertecaenewoaey | tae | [vo {= fos {= fos f= jos fn |

2 Low to CA2 High Delay [Hs = a a es

CAI Active to CA2 High Delay [= [eo | =o [ - fo [= fo Tas | [earigntoCeetow Dewy | toe | — | ro | — [os | — [os [ ~ [os | as | | Peripheral Data Validio CB2Low Delay | to | 0 | 1s | 0 | ov | o [os | o | os | ws | | @2High to Ce2Hign Delay | tags || [os | — | os [ates fs BI Active to CB2 High Delay _ aso | — | 10 | — | 067 CAt.CA2, CBI and CB r- [| of | Input ise and Fal Time NOTE: Timing measurements are referenced to and from a low voltage of 0.8 Vdc and a high voltage of 2.0 Vdc. 1-28

R65C21 Peripheral Interface Adapter (PIA) eEV—e ABSOLUTE MAXIMUM RATINGS* [Parmeter Symbot]| vee [a] “NOTE: Stesses above those listed may cuso permanent damageto ede, Tels asteeraog ny andtuntona wep ese [ve] raat veg +03 | vee] ‘operation of the device at these or any other conditions above [imoutvotage | Vw loc +0 those indicated in other sections of this document snot implied. [Ouputvonage | Vour_| = 0310 Vee +03 | vac] Exposure to absolute maximum rating conditions for extended ‘Operaiing Temperature Range | T, °C periods may affect device reliability. ‘Commercial Oto +70 Industrial =40 to +85 [Seago Tengen | Taw | a8 9180 | -C| OPERATING CONDITIONS [__Panmeter | _Symbal Vane Supply Voltage Veo BV 25% Temperature Range TA 0 Th ‘Commorcial | 0°10 70°6 Industrial 40°C to + 85°C

ELECTRICAL CHARACTERISTICS

(Woe = 5.0 Vde 5%, Veg = 0, Ta = Ti to Ty, unless otherwise noted) [Parameter | Symbon Tin typt [max [unite [Tost Conaitions_| 0 A [nputtowVotage | | -08 | =| oe |v |i? Input Leakage Curent A | Vy = OVI0Vco IW, RES, RSO, RS1, CSO, 32, CA1, CBI, 02 Veo = 5.25V cst Input Leakage Current for Three-State Off Tesi $10 7A |Vy=O4Vi024V ‘00-07, PBO-PB7, CB2 Veg = 5.25 input High Current TA [Vm = 20V PAQ-PAT, CA2 Input Low Current hy Ve = 08V PAO-PA7, CA2 ‘Output High Votiage Vou V_ [Veo = 475, Logie ono = ~200xA PBO-PB7, CB2 (Darlington Drive) Non = —3.2mA ‘Output Low Voltage +04 Veo = 4.75V PAQ-PA7, CA2, PBO-PB7, CB2 luoao = 3.2 mA 0-07. IROA, IROB None 2 116 ma ‘Output High Current (Sourcing) ton Logie 1500 A |Vow = 2.4V PBO-PB7, CB2 (Darlington Drive) -6 mA _|Vou = 1.8V ‘Output Low Current (Sinking) Vo. = 04V PAQ-PAT, PBO-PB7, CB2, CA2 ma 0-07, IGA, RGB ma ‘Output Leakage Current (OM State) WA [Von = 24V TRQA, IROB Veg = 5.25V Pover Osspaian ea | input Capacitance Veo = 50V 100-07, PAO-PA7, PBO-PB7, CA2, CB2 10 pF Va = OV RAW, RES, ASO, RS1, CSO, CS1, CS2 7 pet = 2MHz CAI, CBI, 62 20 pF [t= 25°C Gp Caactancs a A Notes: 1. All units are direct current (de) except capacitance. 2. Negative sign indicates outward current flow, positive indicates inward flow. 3. Typical valves are shown for Vog = 5.0V and T, = 25°C. 1.29

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