R65C102J4

R65C02 ETC1 | Alldatasheet

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R65C02 * R65C102 « R65C112 CD R65C02, R65C102 and R65C112 Rockwell R65C00 Microprocessors (CPU) _ OocKkwe DESCRIPTION FEATURES * CMOS silicon gate technology ‘The 8-bit R65C00 microprocessor family of devices are produced * Low Power (4 mA/MHz) Using CMOS silicon gate technology which provides advanced sys- * Software compatible with 6502 tem architecture for performance speed and system cost- * Single 5V +5% power supply requirements effectiveness enhancements over their NMOS counterparts, the * Eight-bit parallel processing 6500 family of microprocessor devices. * Decimal and binary arithmetic © True indexing capability Three CPU devices are available. All are software-compatible and ‘* Programmable stack pointer provide 64K bytes of memory addressing, two interrupt inputs, and ‘* Interrupt capability ‘on-chip clock oscillators andlor drivers. All are bus-compatible with + Non-maskabie interrupt the NMOS R6500 family devices. '* Eight-bit bidirectional data bus ‘* Memory address range of up to 64K bytes ‘The CMOS family includes two microprocessors (R65CO2 and : ison dh input \\ 65C102) with on-board clock oscillators and drivers and one 2 pmetmemony access (OMA) capabilty ‘microprocessor (RE5C112) driven by an extemal cock. The on-chip one oes Sle, and 4 MHz vers Glock versions are aimed at high performance, low-cost applications 2 Choiedotexternal ar versions where single phase inputs, crystal or RC inputs provide the time See ot omer onenip clocks base. The slave processor version is geared for multiprocessor sys- ia oe lock i tem applications where maximum timing controlis mandatory. All ape nlpea re ate m 65CO0 microprocessors are available in ceramic and plastic pack- Direct exystal input (+ i ‘aging, operating frequency of 1 MHz,2 MHz, 3MHz and 4 MHz, and 5 Sommercial and ncesirel temperature veralone ‘commercial and industrial temperature versions. All three devices . Shave proce rs (RESC112) are available in 40-pin DIP or 44-pin PLCC packages. lave processor version ( J

ORDERING INFORMATION

Part Number: MAJOR FEATURES AND DIFFERENCES Resco2, __ _ Rescio2 RESC112 Pin compatible with NMOS R502 x Temp. Range (T_ to Ty) |64K addressable bytes of memory x x x Blank = 0°Cto +70°C FA interrupt x x x E = -40°Cto +85°C |On-chip clock oscillator x M = —8°Cto 125°C External clock only x x | Frequency Range TTL level single phase clock input x x 1 = 1MHz RC time base clock input x x 2 = 2MHz Crystal time base clock input x x 3 = 3MHz Single phase clock input x 4 = 4MHz Two phase output clock x x ‘Package |SYNC and RDY signals x x x = 40-Pin Coramic DP ‘Bus Enable (BE) signal x x P = 40-Pin Plastic DIP MAL) J = 44-Pin Plastic Leaded Chip ‘Memory Lock (ML) output signal x x Carer (PLCC) ‘Direct Memory Access (OMA) capacity | x x NMI interrupt signal x x x | Document No. 29651N52 Product Description Order No. 2149 13 Rev. 6, June 1987

R65C02, R65C102, R65C112 R65C00 Microprocessors (CPU) INTERFACE SIGNALS therefore not related to, or controlled by the CPU internal clock Figure 1 shows the pin assignments for the members of the signals. Figure 5 shows timing relationships of BE to R/W and R65C00 CPU family. All devices are housed in 40-pin ceramic address output buffers. or plastic dual-in-line (DIP) or 44-pin plastic leaded chip carrier INTERRUPT REQUEST (IRQ) (PLCC) packages. This TTL compatible input requests that an interrupt sequence Refer to the timing diagrams (Figures 3, 4, and 5) for the partic- begin within the microprocessor. IRQ is sampled at the falling ular device in the following discussion ‘edge of 2 prior to the last cycle of the instruction; if the inter- rupt flag in the processor status register is zero, the current ‘CLOCK SIGNALS (R65C02) instruction is completed and the interrupt sequence begins dur- The R65CO2 requires an external 0 clock. See Figure 6 for an ing 01. The program counter and processor status register are ‘example clock circuit. $0 is a TTL level input that is used to stored in the stack. The microprocessor will then set the inter- generate the interrial clocks of the R65C02. Two full level out- rupt mask flag high so that no further IRQs may occur. At the ut clocks are generated by the R65CO2. The 02 clock is in end of this cycle, the program counter low byte will be loaded phase with $0. The 01 clock output is 180° out of phase with from address FFFE, and program counter high byte from loca- 90. When the input clock is stopped, the CPU is in the standby tion FFFF, thus transferring program control to the memory mode. See Figure 8 for special standby mode considerations. vector located at these addresses. The RDY signal must be in the high state for any interrupt to be recognized. A SK ohm For non-critical timing configurations, a simple RC or crystal net- external resistor should be used for proper wire OR operation. work may be strapped between 60 (IN) and 61 (OUT). —_ MEMORY LOCK (ML) CLOCK SIGNALS (R65C102) In a multiprocessor system, the ML output indicates the need The F5C102 internal clocks may be generated by a TTL level to defer the rearbitration of the next bus cycle to ensure the single phase input, an RC time base input, or a crystal ime base integrity of read-modify-write instructions. ML goes low during input (= 4) using the XTLO and XTLI input pins. See Figure 7 ASL, DEC, INC, LSA, ROL, ROR, RMB, SMB, TAB, TSB for an example of a crystal time base circuit. Two full level out- memory referencing instructions. This signal is low for the modify put clocks are generated by the R65C-102. The $2 clock output and write cycles. provides timing for external RW operations. Addresses are (NM valid after the address delay time (taps) referenced to the fall- NON-MASKABLE INTERRUPT (NMI) ing edge of 92 (OUT). The $4 output is a quadrature output clock A negative-going edge on this input requests that a non- that is delayed from the falling edge of the $2 clock by delay maskable interrupt sequence be generated within the time tavs. Using the 04 clock, addresses are valid at the rising microprocessor. The NMI is sampled during 2; the current edge of 64. instruction is completed and the interrupt sequence begins during 01. The program counter is loaded with the interrupt CLOCK SIGNALS (R65C112) vector from locations FFFA (low byte) and FFFB (high byte), All internal clock signals for the R65C112 are generated by the reeeeene rogram contrat to the non-maskable inor- input clock signal $2 (IN). Since this device is intended to be . ‘operated in the slave mode it does not have internal clock gener- NOTE ation, but rather requires the external clock 02 (IN) from a host Since this interrupt is non-maskable, another NMI can device. Figure 7 shows an example of a clock circuit for the occur before the first is finished. Care should be taken R65C112 configured for slave mode. when using NMI to avoid this. ADDRESS BUS (A0-A15) READY (RDY) ‘Address lines AO-A15 form a 16-bit address bus for memory and This input allows the user to single-cycle the microprocessor on V/O exchanges on the data bus. The output of each address line all cycles including write cycles. A negative transition to the low is TTL compatible, capable of driving one standard TTL load state, during or coincident with 02, will halt the microprocessor and 130 pF. with the output address lines reflecting the current address. This condition will remain through a subsequent 02 in which the RDY DATA BUS (D0-D7) ‘signal is low. This feature allows microprocessor interfacing with ‘The data lines (00-07) constitute an 8-bit bidirectional data bus low-speed memory as well as direct memory access (OMA). used for data exchanges to and from the device and peripherals. READ/WRITE (R/W) The ouput are tri-state buffers capable of driving one TTL load This signal is normally in the high state indicating that the a PF. microprocessor is reading data from memory or V/O bus. In the low state the data bus has valid data from the microprocessor BUS ENABLE (BE) to be stored at the addressed memory location. This signal allows external control of the data and the address 50 output butters and RIW. For normal operation, BE is high causing SET OVERFLOW (SO) the address buffers and P/W to be active and the data buffers ‘A negative transition on this line sets the overflow bit (V) in the to be active during a write cycle. For external control, BE is held processor status register. The signal is sampled prior to the rising low to disable the buffers. BE is an asynchronous signal and ‘edge of 2 by the SO setup time ('sos)

sync 7 ab nw swe qe pms 33H we. Figure 1. Pin Assignments

———eeeeeeeeeeeeSSSSSSSSSSSsSSSSSSSSSSSSSSSsHesese R65C02, R65C102, R65C112 R65C00 Microprocessors (CPU) eee RESET (RES) program counter (PCH) is placed on the high-order 8 bits. The ‘This input resets the microprocessor. Reset must be held low for ‘counter is incremented each time an instruction or datais fetched atleast two clock cycles after Voc reaches operating voltage from from program memory. be ekuhediielalanerit edn yeibringedarthaitih eral INSTRUCTION REGISTER AND DECODE ialization sequence to beg) 7 system has Instructions fetched from memory are gated onto the internal data ‘operating, a low on this line of at least two cycles will cease : ssing activi, followed by iniialization after the positive bbus. These instructions are latched into the instruction register, then pineal " ‘decoded, along with timing and interrupt signals, to generate con- ‘ - ‘rol signals for the various registers. ‘When a positive edge is detected, there is an initialization sequence lasting seven clock cycles. Then the interrupt mask flag is set, the ARITHMETIC AND LOGIC UNIT (ALU) decimal mode is cleared, and the program counter is loaded with Allarithmetic and logic operations take place in the ALU including the restart vector from locations FFFC (low byte) and FFFD (high incrementing and decrementing internal registers (except the pro- byte). This is the start location for program control. This input should gram counter). The ALU has no internal memory andis used only be high in normal operation. to perform logical and transient numerical operations. SYNCHRONIZE (SYNC) ACCUMULATOR This output line identifies those cycles during which the micro- ‘The accumulator is a general purpose 8-bit register that stores the processor is fetching the instruction operation code (OP CODE}. results of most arithmetic and logic operations, and in addition, the The SYNC line goes high during@1 of an OP CODE fetch and stays accumulator usually contains one of the two data words used in high for the remainder of that cycle. Ifthe ROY fine is pulled low dur- these operations. ing the clock cycle in which SYNC went high, the processor will stop inits current state and will remain inthe state untilthe DY line goes INDEX REGISTERS high. n this manner, the SYNC signal can be used to control ROY There are two &-bit index registers (X and Y), which may be used to cause single instruction execution. to count program steps or to provide an index value to be used in generating an effective address. FUNCTIONAL DESCRIPTION ‘When executing an instruction which specifies indexed address- Figure 2 shows the! ofthe FESCODCPU intematarch- ing, the CPU fetches the op code and the base address, and doar : modifies the address by adding the index register tot prior to per- tecture for all three devices. With the exception of the crystal Oscillator, clock signals, Memory Lock (ML, and Bus Enable (BE) forming the desired operation. Pre- or postindexing of indirect signals, the internal architecture of the three members of the addresses is possible (see addressing modes) 65CO0 CPU of devices is identical. This block diagram supports. STACK POINTER the folowing text that describes the function of sachof the device's ‘The stack pointer is an 8-bit register used to control the address- ‘major elements. ing of the variabletength stack on page one. The stack pointer is cRYsT ATOR (R6SC1 automatically incremented and decremented under control of the fAL OSCILLATOR (R65C102 Only) ‘microprocessor toperform stack manipulations under direction of The crystal oscillator, driven by a crystal across XTLO and XTU, either the program or interrupts (NMI and IRQ). The stack allows divides the erystal frequency by four to provide the basic 2 clock simple implementation of nested subroutines and multiple level ‘signal that drives the intemal clock generator. interrupts. The stack pointer should be initialized before any inter- CLOCK GENERATOR rupts or stack operations occur. The clock generator develops all internal clock signals, and (where PROCESSOR STATUS REGISTER applicable) external clock signals, associated with the device. Itis ‘The &-it processor status register contains seven status flags. the clock generator that drives the timing control unit and the ‘Some of the flags are controlled by the program, others may be con- external timing for slave mode operations. trolled both by the program and the CPU. The R65C00 instruction sset contains a number of conditional branch instructions which are TIMING CONTROL designed to allow testing of these flags. The timing control unit keeps track of the instruction cycle being ‘monitored. The unit is set to zero each time an instruction fetch is HARDWARE ENHANCEMENTS ‘executed and is advanced at the beginning of each phase one clock ‘The R65C00 family of CPU devices have incorporated hardware pulse for as many cycles as is required to complete the instruction. enhancements over their NMOS counterpart, the F502. These Each data transfer which takes place between the registers hardware enhancements are: depends upon decoding the contents of both the instruction register '* The NMOS device would ignore the assertion of a Ready (RDY) and the timing control unit. during a write operation. The CMOS family will stop the processor during @2 clock if ROY is asserted during a write PROGRAM COUNTER oer fun 62 ii The 16-bit program counter provides the addresses which step the ‘+ Onthe NMOS device, unused input-only pins (IRQ, NM, RDY, microprocessor through sequential instructions in a program. RES, and SO) must be connected to a low impedance signal to Each time the microprocessor fetches an instruction from program ‘avoid noise problems. These unused pins on the CMOS devices memory, the lower byte of the program counter (PCL) is placed on are internally connected by a high impedance to Vcc (approx- the low-order bits of the address bus and the higher byte of the imately 250K ohms).

ae [| [REGISTER P GENERATOR . Figure 2. R65C00 Internal Architecture

R65C02, R65C102, R65C112 R65CO00 Microprocessors (CPU) ADDRESSING MODES RELATIVE ADDRESSING [Relative] — Relative addressing is The R6SCOO CPU family has 15 address modes (two more than used only with branch instructions and establishes a destina- the NMOS equivalent family). In the following discussion of these tion for the conditional branch. addressit 7 ion follows the til Set Op Code Matrix table (later in this product description) to is an “Offset” added to the contents of the lower eight bits of make it easier to identify the actual addressing mode used by the program counter when the counter is set at the next instruc- the instruction. tion. The range of the offset is - 128 to +127 bytes from the next instruction. ACCUMULATOR ADDRESSING [Accum]— This form of ZEROPAGERELATIVE ADDRESSING [2P REL]* — Thismode addressing is represented with a one byte instruction, implying bit tests the zero page location pected for bit eoveset per the an operation on the accumulator. mask and performs a conditional relative branch based on the results of the bit test, IMMEDIATE ADDRESSING [IMM] — In immediate addressing, the second byte of the instruction contains the operand, with INDEXED INDIRECT ADDRESSING [(IND, X)] — In indexed no further memory addressing required. indirect addressing (referred to as (Indirect, X)), the second byte of the instruction is added to the contents of the X index register, ABSOLUTE ADDRESSING [ABS] — In absolute addressing, discarding the carry. The result of this addition points to a the second byte of the instruction specifies the eight low order memory location on page zero whose contents are the low order bits of the effective address while the third byte specifies the eight bits of the effective address. The next memory location eight high order bits. Thus the absolute addressing mode allows in page zero contains the high order eight bits of the effective access to the entire 64K bytes of addressable memory. address. Both memory locations specifying the high and low order bytes of the effective address must be in page zero. penile et tent tbat BUR teri eet nari INDIRECT INDEXED ADDRESSING [(IND), Y] — In indirect for shorter code and execution times by fetching only the ‘ second byte ofthe instruction and assuming a zero high address indexed addressing (referred to as (Indirect), ¥), the second byte byte. Careful use of the zero page can result in significant of the instruction points to a memory location in page zero. The increase in code efficiency contents of this memory location are added to the contents of the Y index register, the result being the low order eight bits of the effective address. The carry from this addition is added ZERO PAGE INDEXED ADDRESSING [ZP, X or Y] —(K, Y to the contents of the next page zero memory location, the result indexing) — This form of addressing is used with the index being the high order eight bits of the effective address. register and is referred to as “Zero Page, X" or “Zero Page, Y". The effective address is calculated by adding the second byte ABSOLUTE INDIRECT {(ABS)]—The second byte of the to the contents of the index register. Since this is a form of "Zero instruction contains the low order eight bits of a memory loca- Page" addressing, the content of the second byte references tion. The high order eight bits of that memory location are con- a location in page zero. Additionally, due to the "Zero Page” tained in the third byte of the instruction. The contents of the addressing nature of this mode, no carry is added to the high fully specified memory location are the low order byte of the ‘order eight bits of memory and crossing of page boundaries does effective address. The next memory location contains the high not occur. order byte of the effective address which is loaded into the six- teen bits of the program counter. (JMP (ABS) only.) ABSOLUTE INDEXED ADDRESSING [ABS, X or ¥] — (X, Y indexing) — This form of addressing is used in conjunction with INDIRECT [(IND)]* — The second byte of the instruction con- X and Y index register and is referred to as “Absolute, X" and tains a zero page address serving as the indirect pointer. “Absolute, Y". The effective address is formed by adding the contents of X or Y to the address contained in the second and ENHANCEMENTS OVER R6502 third bytes of the instruction. This mode allows the index register to contain the index or count value and the instruction to con- ‘The CMOS family of microprocessor devices has been designed tain the base address. This type of indexing allows any location with many enhancements over the R6502 NMOS device while referencing and the index to modify fields, resulting in reduced ‘maintaining software compatibility. Besides the increased speed coding and execution time. and lower power consumption inherent in CMOS technology, the R65CO0 family has the following additional characteristics. INDEXED ABSOLUTE INDIRECT [(ABS, X)]* — The contents ‘* 12 new instructions for a total of 68 ‘of the second and third instruction bytes are added to the ‘+ 59 new op codes, for a total of 210 X-register. The sixteen-bit result is a memory address contain- ‘* Two new addressing modes ing the effective address. (JMP (ABS, X) only). ‘= Seven software/operational enhancements ‘+ Two hardware enhancements IMPLIED ADDRESSING [Implied] — In the implied addressing mode, the address containing the operand is implicitly stated “These addressing modes are not available to the NMOS CPU in the operation code of the instruction family (@.g., the R6502).

family. Table 3|lists those instructions that were available on the results with their NMOS R6502 counterpart. Table 1. Alphabetic Listing of the R65C00 Instruction Set

2 BIT | Test Bits in Memory with Accurnuiator PLP | Pull Processor Status from Stack

DEY | Decrement index Y by One. (1) Instruction not available on the NMOS family. (2) R6502 instruction with additional addressing mode(s).

Table 2. Hexadecimal Codes For New Instructions in the R65C00 Microprocessors

80 BRA Branch relative always (Relative)

64 Siz ‘Store zero (ZP]

1, Most significant digit change only. Table 3. Hexadecimal Codes For A65C00 Instructions With New Addressing Modes

2 ADC Add memory to accumulator with carry [(IND)]

32 AND AND memory with accumulator [(IND)]

52 EOR Exclusive Or memory with accumulator ((IND))

7 JMP- Jump (New addressing mode) [(ABS, X)]

82 LDA Load accumulator with memory [(IND)]

Table 4. R65COO Operational Enhancements Execution of invalid op codes. Some terminate only by reset. Results are All are NOPs (reserved for future use). Read/modifytwrite instructions at effective. One read and two write cycles. ‘Two read and one write cycle. Flags after decimal operation. Invalid N, V and Z flags. _ Valid flag adds one additional cycle.

R65C02, R65C102, and R65C112 R65C00 Microprocessors (CPU) INSTRUCTION SET OP CODE MATRIX ‘The following matrix shows the 210 Op Codes associated with the number of instruction bytes, and the number of machine the RG65CO0 family of CPU devices. The matrix identifies the cycles associated with each Op Code. Also, refer to the instruc- hexadecimal code, the mnemonic code, the addressing mode, tion set summary for additional information on these Op Codes. 1 Po 4 2 3 4 5 6 7 @ 9 A 8B C D_eE F

8 Tom [ona Tee] one | ast [rus] oie Tas] ora] ast

© | imple |(ND. 0) ze | ze | ze | zp | implies aps | ass | Aas ° 1? |26 2sjes|2s|zs|2 oefoslas ‘OFA mwer] cic | ORA Tas | oA | ast | sant 1 no). ¥ ZP_ | irpied | ABS, ¥ ass | aes.x|aas.x] ze | 25 as|relse Se]se|37]os [ase or | ano | AO [awer| PLP ROL | BBR? 2) Aes ze | ze | ze | 2 | amples aes | zp |2 36 z2alzales|es|re a6 [os ou | AND ROL ar not | Bore 3 Rettve| (IND), ¥ wx ps, x ass.x| zp | 2 Pee as 26 Ew 27 [os ant | GOR tsa [anes tA ame | EOR | LSR «| impted | 0.20 ze | z secu nas | ass | ABs ‘ Te 28 2s|2s te sai alas ve tsa [ames] cu | cor | Pav Eon | is | BBR 5 | Rotive 2.x | 2° | implied | ABS, ¥ | imped aps.x{aas,x] 2p | 6 ze 26lzs|reloe[ro oe] 37 [os RTS | anc n0G | ROR me | ADC Bane 6 | imptiaa| ND. x) twat | Accum as) | ABs 2 |e ve | 2 et ml ie 36/3 4 aos avs | AC svz | aoc | Aon | Auer ‘aoc | Puy moe | ROR (pe 2st zajes|26|2s aap 3 4t| a7 ra] sta ov ‘neo | OEY THA ‘stv aso 8 [reine] ino. 0 ES P| inphied shes Aas ze |e ae] 28 23 2s |e Te a4 a5 sta | sta sv om wa | sta] 138 oz east ° ano, | (NO) Bx wy imped |A88.¥ | mies 28s ze |e ze [28 24 24 te|ss|re oa a" twa | tox wr | wa | 10x TAY TAX tor was A so.) | nae ze | 2 | 2 mpi’ pte 85 ze fA 26 |22 zalzales te Te a4 a cS | LOA LOA uoy | Loa | Lox | smeo LDA | TSX Loy Lox | 88S3 8 | Relative (WD), ¥ | (IND) wx | 2x 2. | 2 488, | impieo nes. x nes y] ze |e pejes [2s zalee 2aas ae te ewe fee Ei cry | ow | vEC Ny oex || omy ease c ze | 2 | 2 ses pte ABs zw ic zoles es ve Te aa a axe | owe | ome cap oe cub owe 3558 © | Retaive| NO), | «IND BX | IX ines ABS. x ze lo zr les [2s 2428 te ae ae Px cx | sec) we | owas nor 38C ease | im ze | ze | 2 | 2 Impiec 28S 2 |e 22 2alenies|es Te? aa as | Bea | sac | sec sme7| SEO | SBC spc | INC | 8BS7 F | Rotave) anos. ¥] (ND) 2°. | impies | ABS, ¥ ass.x|ass.x] zp |e 22" | 2 5¢ [2 5 as|re [st 3 et| 37 [os o ot 2 9 # 5 6 7 8 89 A 8 C BD € F orm] —or 1446 110 Nin deine! mado OP Code “ha 140 N# page boundary ocrsoed. — New Opcode 0 | implied | —Addressing Mode “Add 1 40 Nf branch occurs 10 same page: 1 7 | —Instruction Bytes; Machine Cycles ‘Add 2 to Nf branch occurs to different page. tt

R65C02, R65C 102, and R65C112 R65CO00 Microprocessors (CPU) INSTRUCTION SET SUMMARY

3 NNN I INININININIIIRIII ONINIINIIROIEERE GMIINIRIIN o

f= ii [ales a Al se = = an2 EO ne At 7 a Cry ary ——— ee ee ; ——S=S= === es Hh ——— aera ae [sige g Eos oe _vRguyy ee wees oe 33 —— | [s[se A ess = 23 Fa pide . ° gif og? dig d | SEES eT ee asa 6 TBeedios 7 HEY fie _ - - Hedy fe é 3 peers tet 3 142

R65C02, R65C102, and R65C112 R65C00 Microprocessors (CPU) SWITCHING CHARACTERISTICS (Over operating conditions unless otherwise noted) [tae _[ sme [see Tome] CLOCK TIMING [ se oyee Time [cw] 000 | Nowe [sto [ nowt [ so [news | om [ Nowr [ mw a a a ro towie sat | ef = f= f= | | =P ef | P| a [tenon Puse we® | ter [450 [saab [aa | sooo | 60 | stoo [wo [ooo [ne | [oust fee araruties [we [=| sp -[ =) —| »| —| 2% | [aw oo Tine | we [= | [me pp ey [pe Tread coos Tine | we | ef = [oe | = | as | | | | TN a a [wmomowree tee [=e fe fe Pe To | Wt Dia Hl Tine tw | | | et = ep te | CONTROL LINE TIMING [sncoouy [eg [=] wt = wl -[ »[-[ »[~ | [Ror sewp Tine | toe | fe we Pe ["Soseup time | wef sf ff | of | | | ee ce eo "io, Aes Sout | yy | ae | | wf | we] | po] A 2. RESCO2 only. 2 reece 4. RESC102 only. 6. R65C112 only. 1-13,

1 OUT)"

1 Resce2

Figure 3. Timing Diagram for the R65C02 and R65C112

——— SeSeSeSSeSeSeeeseseeeeeSeseSSSSSSSeSeSSSSSSSSSSSSSsSsesessssssseses R65C02, R65C102, and R65C112 R65C00 Microprocessors (CPU) Eee ABSOLUTE MAXIMUM RATINGS* [Parameter [Symbot[ Value __ [unt] “NOTE: Stresses above those listed may cause permanent |Sueely Votage | -031 +70 | vac] Cae on ene rating only ad tne = ve Supply Voltage | vec | -03t0 +70 [vac tional operation of the device at these or any other conditions above those indicated inthe other sections ofthis document 08 0 Vee +0.3| Vac | is not implied. Exposure to absolute maximum rating condi- [seuseTenpaatre | Too | -s5w +160 [re] tons for extended pores may act deve eit. OPERATING CONDITIONS [—_~Fwraneter [Syma Vee |" Svac 25% _ | Operating Temperature (Ambient) | T, to Ty Commercial 0°¢ to 70°6 Industrial —40°C to +85°C Miltary =55°C to + 125°C

ELECTRICAL CHARACTERISTICS

(Over operating conditions unless otherwise noted) [Parameter [Sebo win [tye [Max [unit teat Conattions | Input High Voltage 40°C to 85°C Vog +0.3 ~85°C to 125°C Vog 40.3 Input Low Voltage Ve 40°C to 85°C +08 =85°C to 125°C +04 put High Vtape 60 RSH [Wee [2 | [ee vo Input Low Voltage 60 (RESCO2) [Vio [ -o3 [| oa Tov [| pu Hh Vtape 62 08) RESET [vie | Wee-08 | [Wes v0 |v || Input Low Votage @2 (IN) (RBSC112) [Vis [-o3 [| +oe [ov [| input Leakage Current hw A [Vy = OV 10 5.25V Fill, 180, BE, ROY, RES, SO Vee = OV 92 (IN), 90 (IN), XTLI | Three-State (Off State) Input Current pA Vy = 0.4V to 2.4V) Data Lines Voc = 5.25V [Output High Voltage | Vou V_ |Wec = 4750 SYNC, Data, AO-A15, R/W, 01 (OUT), #2 (OUT), 64 (OUT), ML ican = — 100 «A. [Output Low Voltage Z | Vo Vv [Vcc = 4.75V SYNC, Data, AQ-A15, RAW, 01 (OUT), 62 (OUT), #4 (OUT). ML how = 1.8 mA [Supply Current lee Wee = 5.0V ‘Standby* 2 10 A Active (RESCO2) 26 4 mane] Active (RBSC102) 5 7 |mamea| Active (RBSC112) 2 4 |maMe2| Low Power (R65CO2) 1s 2 |mamie|RDY =o Low Power (RB5C102) 3 5 |mamez|ROY=0 Low Power (RB5C112) o7 1 __|mamMitz|ROY=0 (Capacitance Voc = 50V 'NMi, IRQ, SO, BE, ROY _ _ | Gy 7 Vy = OV SYNC, Data, AO-A15, R/W, 61 (OUT), 62 (OUT), 64 (OUT). ML, Cour 10 Vig = OV xTLO 12 1 MHz 90 (IN), XTL Cy 10 Th = 25°C #2(1N) c 20 Notes: 1. All units are direct current (dc). 2. Negative sign indicates outward current flow, positive indicates inward flow. 3. IR and NMI require external pull-up resistor ‘4. Typical values shown far Veo = 5.0V and T, = 25°C. 417

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