R5F61644A

H8SX1648 RENESAS | Alldatasheet

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 1472

Technical content

Datasheet sections

• 1.1 Features
• 1.1.1 Applications
• 1.1.2 Overview of Functions
• 1.2 List of Products
• 1.3 Block Diagram
• 1.4.1 Pin Assignments
• 1.4.2 Correspondence between Pin Configuration and Operating Modes
• 1.4.3 Pin Functions
• 2.1 Features
• 2.2 CPU Operating Modes
• 2.2.1 Normal Mode
• 2.2.2 Middle Mode
• 2.2.3 Advanced Mode
• 2.2.4 Maximum Mode
• 2.3 Instruction Fetch
• 2.4 Address Space
• 2.5 Registers
• 2.5.1 General Registers
• 2.5.2 Program Counter (PC)
• 2.5.3 Condition-Code Register (CCR)
• 2.5.4 Extended Control Register (EXR)
• 2.5.5 Vector Base Register (VBR)
• 2.5.6 Short Address Base Register (SBR)
• 2.5.7 Multiply-Accumulate Register (MAC)
• 2.5.8 Initial Values of CPU Registers
• 2.6 Data Formats
• 2.6.1 General Register Data Formats
• 2.6.2 Memory Data Formats
• 2.7 Instruction Set
• 2.7.1 Instructions and Addressing Modes
• 2.7.2 Table of Instructions Classified by Function
• 2.7.3 Basic Instruction Formats

Revision Date: Jul. 31, 2008

32 Hardware Manual

Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series H8SX/1648 R5F61648 H8SX/1644 R5F61644 H8SX/1642 R5F61642 H8SX/1648A R5F61648A H8SX/1644A R5F61644A H8SX/1642A R5F61642A H8SX/1648L R5F61648L H8SX/1644L R5F61644L H8SX/1642L R5F61642L H8SX/1648G R5F61648G H8SX/1644G R5F61644G H8SX/1642G R5F61642G H8SX/1648H R5F61648H H8SX/1644H R5F61644H H8SX/1642H R5F61642H Rev.2.00 REJ09B0365-0200 All information contained in this material, including products and product specifications at the time of publication of this material, is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp. website (http://www.renesas.com). H8SX/1648, H8SX/1648A, H8SX/1648L, H8SX/1648G, H8SX/1648H Group

Rev. 2.00 Jul. 31, 2008 Page ii of xxx

Rev. 2.00 Jul. 31, 2008 Page iii of xxx 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Notes regarding these materials

Rev. 2.00 Jul. 31, 2008 Page iv of xxx General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.  The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied.  The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited.  The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized.  When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems.  The characteristics of MPU/MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different type numbers, implement a system-evaluation test for each of the products.

Rev. 2.00 Jul. 31, 2008 Page v of xxx How to Use This Manual 1. Objective and Target Users This manual was written to explain the hardware functions and electrical characteristics of this LSI to the target users, i.e. those who will be using this LSI in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logic circuits, and microcomputers. This manual is organized in the following items: an overview of the product, descriptions of the CPU, system control functions, and peripheral functions, electrical characteristics of the device, and usage notes. When designing an application system that includes this LSI, take all points to note into account. Points to note are given in their contexts and at the final part of each section, and in the section giving usage notes. The list of revisions is a summary of major points of revision or addition for earlier versions. It does not cover all revised items. For details on the revised points, see the actual locations in the manual. The following documents have been prepared for the H8SX/1648A, H8SX/1648L, H8SX/1648G, H8SX/1648H Group. Before using any of the documents, please visit our web site to verify that you have the most up-to-date available version of the document. Document Type Contents Document Title Document No. Data Sheet Overview of hardware and electrical characteristics   Hardware Manual Hardware specifications (pin assignments, memory maps, peripheral specifications, electrical characteristics, and timing charts) and descriptions of operation H8SX/1648A, H8SX/1648L, H8SX/1648G, H8SX/1648H Group Hardware Manual This manual Software Manual Detailed descriptions of the CPU and instruction set H8SX Family Software Manual REJ09B0102 Application Note Exampl es of applications and sample programs Renesas Technical Update Preliminary report on the specifications of a product, document, etc. The latest versions are available from our web site.

Rev. 2.00 Jul. 31, 2008 Page vi of xxx 2. Description of Numbers and Symbols Aspects of the notations for register names, bit names, numbers, and symbolic names in this manual are explained below. CMCSR indicates compare match generation, enables or disables interrupts, and selects the counter input clock. Generation of a WDTOVF signal or interrupt initializes the TCNT value to 0.

14.3 Operation

The style "register name"_"instance number" is used in cases where there is more than one instance of the same function or similar functions. [Example] CMCSR_0: Indicates the CMCSR register for the compare-match timer of channel 0. In descriptions involving the names of bits and bit fields within this manual, the modules and registers to which the bits belong may be clarified by giving the names in the forms "module name"."register name"."bit name" or "register name"."bit name". (1) Overall notation (2) Register notation Rev. 0.50, 10/04, page 416 of 914

14.2.2 Compare Match Control/Status Register_0, _1 (CMCSR_0, CMCSR_1)

14.3.1 Interval Count Operation

(4) (3) (2) Binary numbers are given as B'nnnn (B' may be omitted if the number is obviously binary), hexadecimal numbers are given as H'nnnn or 0xnnnn, and decimal numbers are given as nnnn. [Examples] Binary: B'11 or 11 Hexadecimal: H'EFA0 or 0xEFA0 Decimal: 1234 (3) Number notation An overbar on the name indicates that a signal or pin is active-low. [Example] WDTOVF Note: The bit names and sentences in the above figure are examples and have nothing to do with the contents of this manual. (4) Notation for active-low When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in CMCNT and the compare match constant register (CMCOR) match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. When the CKS1 and CKS0 bits are set to B'01 at this time, a f/4 clock is selected.

Rev. 2.00 Jul. 31, 2008 Page vii of xxx 3. Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described below. Indicates the bit number or numbers. In the case of a 32-bit register, the bits are arranged in order from 31 to 0. In the case of a 16-bit register, the bits are arranged in order from 15 to 0. Indicates the name of the bit or bit field. When the number of bits has to be clearly indicated in the field, appropriate notation is included (e.g., ASID[3:0]). A reserved bit is indicated by "−". Certain kinds of bits, such as those of timer counters, are not assigned bit names. In such cases, the entry under Bit Name is blank. (1) Bit (2) Bit name Indicates the value of each bit immediately after a power-on reset, i.e., the initial value. 0: The initial value is 0 1: The initial value is 1 −: The initial value is undefined (3) Initial value For each bit and bit field, this entry indicates whether the bit or field is readable or writable, or both writing to and reading from the bit or field are impossible. The notation is as follows: R/W: R/(W): The bit or field is readable and writable. The bit or field is readable and writable. However, writing is only performed to flag clearing. The bit or field is readable. "R" is indicated for all reserved bits. When writing to the register, write the value under Initial Value in the bit chart to reserved bits or fields. The bit or field is writable. Note: The bit names and sentences in the above figure are examples, and have nothing to do with the contents of this manual. (4) R/W Describes the function of the bit or field and specifies the values for writing. (5) Description Bit 13 to 11 All 0 R R/W R R Address Identifier These bits enable or disable the pin function. Reserved This bit is always read as 0. Reserved This bit is always read as 1. ASID2 to ASID0 Bit Name Initial Value R/WDescription [Bit Chart] [Table of Bits] 1 5 1 4 1 3 1 2 1 1 1 0 9876543210Bit: Initial value: R/W: 0000001000000000 R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W  ASID2  ACMP2Q IFE ASID1 ASID0 ACMP1 ACMP0 − 0 R Reserved These bits are always read as 0.

Rev. 2.00 Jul. 31, 2008 Page viii of xxx 4. Description of Abbreviations The abbreviations used in this manual are listed below.

• Abbreviations specific to this product Abbreviation Description BSC Bus controller CPG Clock pulse generator DTC Data transfer controller INTC Interrupt controller PPG Programmable pulse generator SCI Serial communications interface TMR 8-bit timer TPU 16-bit timer pulse unit WDT Watchdog timer
• Abbreviations other than those listed above Abbreviation Description ACIA Asynchronous communications interface adapter bps Bits per second CRC Cyclic redundancy check DMA Direct memory access DMAC Direct memory access controller GSM Global System for Mobile Communications Hi-Z High impedance IEBus Inter Equipment Bus (IEBus is a trademark of NEC Electronics Corporation.) I/O Input/output IrDA Infrared Data Association LSB Least significant bit MSB Most significant bit NC No connection PLL Phase-locked loop PWM Pulse width modulation SFR Special function register SIM Subscriber Identity Module UART Universal asynchronous receiver/transmitter VCO Voltage-controlled oscillator All trademarks and registered trademarks are the property of their respective owners.

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2.8.3 Register Indirect with Displacement —@(d:2, ERn), @(d:16, ERn), or

2.8.4 Index Register Indirect with Displacement—@(d:16,RnL.B), @(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or

2.8.5 Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment, or

2.8.9 Program-Counter Relative with Index Register—@(RnL.B, PC),

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5.3.3 Release from Deep Software Standby Mode by the Voltage-Detection

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7.3.3 Interrupt Priority Register H8SX/1648 Group, H8SX/1648A Group and

H8SX/1648L Group: Interrupt Priority Registers A to I, K to O, Q, and R (IPRA to IPRI, IPRK to IPRO, IPRQ, and IPRR) H8SX/1648G Group, and H8SX/1648H Group: Interrupt Priority Registers A to O, O, and R (IPRA to

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12.9.6 Transfer Information Start Address, Source Address, and Destination

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13.1.1 Data Direction Register (PnDDR)

13.1.4 Input Buffer Control Register (PnICR)

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15.4.6 Example of Non-Overlapping Pulse Output (Example of 4-Phase

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19.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous

19.6.5 Simultaneous Serial Data Transmission and Reception

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19.10.4 Receive Error Flags and Transmit Operations

20.3.1 I 20.3.2 I 20.3.3 I 20.3.4 I 20.3.5 I 20.3.7 I 20.3.8 I 20.3.9 I 20.4.1 I

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27.8.4 Bφ or SDRAMφ Operation after Exit from Deep Software Standby

27.8.5 Setting Oscillation Settling Time after Exit from Deep Software Standby

27.12.7 Conflict between a transition to deep software standby mode and

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29.2 DC Characteristics, H8SX/1648 Group, H8SX/1648A Group, and H8SX/1648G

29.8 Power-On Reset Circuit and Voltage-Detection Circuit Characteristics

Rev. 2.00 Jul. 31, 2008 Page 1 of 1438 REJ09B0365-0200 Section 1 Overview

1.1 Features

The core of each product in the H8SX/1648 Group, H8SX/1648A Group, H8SX/1648L Group, H8SX/1648G Group, and H8SX/1648H Group of CISC (complex instruction set computer) microcontrollers is an H8SX CPU, which has an internal 32-bit architecture. The H8SX CPU provides upward-compatibility with the CPUs of other Renesas Technology-original microcontrollers; H8/300, H8/300H, and H8S. As peripheral functions, each LSI of the Group includes a DMA controller and EXDMA controller* , which enable high-speed data transfer, and a bus-state controller, which enables direct connection to different kinds of memory. The LSI of the Group also includes serial communication interfaces, A/D and D/A converters, and a multi-function timer that makes motor control easy. Together, the modules realize low-cost configurations for end systems. The power consumption of these modules is kept down dynamically by an on-chip power-management function. The on-chip ROM is a flash memory (F-ZTAT TM *) with a capacity of 1024 Kbytes (H8SX/1648, H8SX/1648A, H8SX/1648L, H8SX/1648G, and H8SX/1648H), 512 Kbytes (H8SX/1644, H8SX/1644A, H8SX/1644L, H8SX/1644G, and H8SX/1644H), or 256 Kbytes (H8SX/1642, H8SX/1642A, H8SX/1642L, H8SX/1642G, and H8SX/1642H). Note: 1. Supported only by the H8SX/1648G Group and H8SX/1648H Group. 2. F-ZTAT TM is a trademark of Renesas Technology Corp.

1.1.1 Applications

Examples of the applications of this LSI include PC peripheral equipment, optical storage devices, office automation equipment, and industrial equipment.

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1.1.2 Overview of Functions

Table 1.1 lists the functions of H8SX/1648 Group products in outline. Table 1.2 shows the comparison of support functions in each group. Table 1.1 Overview of Functions Classification Module/ Function Description ROM • ROM capacity: 1024 Kbytes, 512 Kbytes, or 256 Kbytes Memory RAM • RAM capacity: 56 Kbytes, 40 Kbytes, or 24 Kbytes CPU • 32-bit high-speed H8SX CPU (CISC type) Upwardly compatible for H8/300, H8/300H, and H8S CPUs at object level

• General-register architecture (sixteen 16-bit general registers)
• Eleven addressing modes
• 4-Gbyte address space Program: 4 Gbytes available Data: 4 Gbytes available
• 87 basic instructions, classifiable as bit arithmetic and logic instructions, multiply and divide instructions, bit manipulation instructions, multiply-and-accumulate instructions, and others
• Minimum instruction execution time: 20.0 ns (for an ADD instruction while system clock Iφ = 50 MHz and VCC = 3.0 to 3.6 V)
• On-chip multiplier (16 × 16 → 32 bits)
• Supports multiply-and-accumulate instructions (16 × 16 + 42 → 42 bits) CPU Operating mode
• Advanced mode Normal, middle, or maximum mode is not supported.

Rev. 2.00 Jul. 31, 2008 Page 3 of 1438 REJ09B0365-0200 Classification Module/ Function Description CPU MCU operating mode Mode 1: User boot mode (selected by driving the MD2 and MD1 pins low and driving the MD0 pin high) Mode 2: Boot mode (selected by driving the MD2 and MD0 pins low and driving the MD1 pin high) Mode 3: Boundary scan enabled single-chip mode (selected by driving the MD2 pin low and driving the MD1 and MD0 pins high) Mode 4: On-chip ROM disabled external extended mode, 16-bit bus (selected by driving the MD1 and MD0 pins low and driving the MD2 pin high) Mode 5: On-chip ROM disabled external extended mode, 8-bit bus (selected by driving the MD1 pin low and driving the MD2 and MD0 pins high) Mode 6: On-chip ROM enabled external extended mode (selected by driving the MD0 pin low and driving the MD2 and MD1 pins high) Mode 7: Single-chip mode (can be externally extended) (selected by driving the MD2, MD1, and MD0 pins high)

• Low power consumption state (transition driven by the SLEEP instruction) Power on reset (POR)*
• At power-on or low power supply voltage, an internal reset signal is generated Voltage detection circuit (LVD)*
• At low power supply voltage, an internal reset signal and an interrupt are generated.

Rev. 2.00 Jul. 31, 2008 Page 4 of 1438 REJ09B0365-0200 Classification Module/ Function Description Interrupt (source) Interrupt controller (INTC)

• Seventeen external interrupt pins (NMI, and IRQ15 to IRQ0)
• Number of internal interrupt sources H8SX/1648, H8SX/1648A Group: 113 pins H8SX/1648L: 114 pins H8SX/1648G: 123 pins H8SX/1648H: 124 pins
• Two interrupt control modes (specified by the interrupt control register)
• Eight priority orders specifiable (by setting the interrupt priority register)
• Independent vector addresses Break interrupt (UBC)
• Break point can be set for four channels
• Address break can be set for CPU instruction fetch cycles EXDMA controller (EXDMAC)*
• Four-channel DMA transfer available
• Two activation methods (auto-request and external request)
• Four transfer modes (normal, repeat, block, and cluster transfer)
• Dual or single address mode selectable
• Extended repeat area function DMA controller (DMAC)
• Four-channel DMA transfer available
• Three activation methods (auto-request, on-chip module interrupt, and external request)
• Three transfer modes (normal, repeat, and block transfer)
• Dual or single address mode selectable
• Extended repeat area function DMA Data transfer controller (DTC)
• H8SX/1648, H8SX/1648A, and H8SX/1648L Groups: Allow DMA transfer over 76 channels (number of DTC activation sources)
• H8SX/1648G and H8SX/1648H Groups:
• Allow DMA transfer over 84 channels (number of DTC activation sources)
• Activated by interrupt sources (chain transfer enabled)
• Three transfer modes (normal, repeat, and block transfer)
• Short-address mode or full-address mode selectable

Rev. 2.00 Jul. 31, 2008 Page 5 of 1438 REJ09B0365-0200 Classification Module/ Function Description

• 16-Mbyte external address space
• The external address space can be divided into eight areas, each of which is independently controllable  Chip-select signals (CS0 to CA7) can be output  Access in two or three states can be selected for each area  Program wait cycles can be inserted  The period of CS assertion can be extended  Idle cycles can be inserted
• Bus arbitration function (arbitrates bus mastership among the internal CPU, DMAC, EXDMAC* , DTC, refresh* , and external bus masters) Bus formats
• External memory interfaces (for the connection of ROM, burst ROM, SRAM* , byte control SRAM, DRAM* , synchronous DRAM*
• Address/data bus format: Support for both separate and multiplexed buses (8-bit access or 16-bit access) External bus extension Bus controller (BSC)
• Endian conversion function for connecting devices in little- endian format Clock Clock pulse generator (CPG)
• One clock generation circuit available
• Separate clock signals are provided for each of functional modules (detailed below) and each is independently specifiable (multi-clock function)  System-intended data transfer modules, i.e. the CPU, runs in synchronization with the system clock (Iφ): 8 to 50 MHz  Internal peripheral functions run in synchronization with the peripheral module clock (Pφ): 8 to 35 MHz  Modules in the external space are supplied with the external bus clock (Bφ): 8 to 50 MHz
• Includes a PLL frequency multiplication circuit and frequency divider, so the operating frequency is selectable
• Five low-power-consumption modes: sleep mode, all-module- clock-stop mode, software standby mode, deep software standby mode, and hardware standby mode

Rev. 2.00 Jul. 31, 2008 Page 6 of 1438 REJ09B0365-0200 Classification Module/ Function Description A/D converter A/D converter (ADC)

• 10-bit resolution × three units
• Selectable input channel and unit configuration Four channels × three units (units 0, 1, and 2) Eight channels × one unit (unit 0) + four channels × one unit (unit 2)
• Sample and hold function included
• Conversion time: 2.7 µs per channel (with peripheral module clock (Pφ) at 25-MHz operation)
• Two operating modes: single mode and scan mode
• Three ways to start A/D conversion: Unit 0: Software, timer (TPU/TMR (units 0 and 1)) trigger, and external trigger Unit 1: Software, TMR (units 2 and 3) trigger, and external trigger Unit 2: Software, TMR (units 2 and 3) trigger, and external trigger
• Activation of DTC and DMAC by ADI interrupt: Unit 0: DTC and DMAC can be activated by an ADI0 interrupt. Unit 1: DMAC can be activated by an ADI1 interrupt. Unit 2: DMAC can be activated by an ADI2 interrupt. D/A converter D/A converter (DAC)
• 8-bit resolution × two output channels
• Output voltage: 0 V to Vref, maximum conversion time: 10 µs (with 20-pF load) Timer 8-bit timer (TMR)
• 8 bits × eight channels (can be used as 16 bits × four channels)
• Select from among seven clock sources (six internal clocks and one external clock)
• Allows the output of pulse trains with a desired duty cycle or PWM signals

Rev. 2.00 Jul. 31, 2008 Page 7 of 1438 REJ09B0365-0200 Classification Module/ Function Description 16-bit timer pulse unit (TPU)

• 16 bits × 12* channels (general pulse timer unit)
• Select from among eight counter-input clocks for each channel
• Up to 16 pulse inputs and outputs
• Counter clear operation, simultaneous writing to multiple timer counters (TCNT), simultaneous clearing by compare match and input capture possible, simultaneous input/output for registers possible by counter synchronous operation, and up to 15-phase PWM output possible by combination with synchronous operation
• Buffered operation, cascaded operation (32 bits × two channels), and phase counting mode (two-phase encoder input) settable for each channel
• Input capture function supported
• Output compare function (by the output of compare match waveform) supported Note: * The pin function of unit 1 cannot be used in external bus extended mode. Timer Program- mable pulse generator (PPG)
• 32-bit* pulse output
• Four output groups, non-overlapping mode, and inverted output can be set
• Selectable output trigger signals; the PPG can operate in conjunction with the data transfer controller (DTC) and the DMA controller (DMAC) Notes: 1. Pulse output pins PO 31 to PO16 cannot be activated by input capture. 2. Pulse of unit 1 cannot be output in external bus extended mode. Watchdog timer Watchdog timer (WDT)
• 8 bits × one channels (selectable from eight counter input clocks)
• Switchable between watchdog timer mode and interval timer mode 32K timer 32K timer (TM32K)
• Eight counter clocks which divides the 32.768 Hz clock can be selected
• 8 bits x one channel or 24 bits x 1 channel can be selected
• Interrupts can be generated when the counter overflows
• Eight overflow cycles selectable (250 msec, 500 msec, 1 sec, 2 sec, 30 sec, 60 sec, about 23 days, and about 48 days)

Rev. 2.00 Jul. 31, 2008 Page 8 of 1438 REJ09B0365-0200 Classification Module/ Function Description Serial interface • Seven channels (select asynchronous or clock synchronous serial communication mode)

• Full-duplex communication capability
• Select the desired bit rate and LSB-first or MSB-first transfer
• Transfer rate clock input from TMR (SCI_5, SCI_6)
• IrDA transmission and reception conformant with the IrDA Specifications version 1.0
• On-chip cyclic redundancy check (CRC) calculator for improved reliability in data transfer Smart card/SIM Serial communi- cation interface (SCI)
• The SCI module supports a smart card (SIM) interface. I C bus interface I C bus interface 2 (IIC2)
• Four channels
• Bus can be directly driven (the SCL and SDA pins are NMOS open drains).
• IIC2 (unit 1) is open drain pins supporting 5 V input. I/O ports • Input-only pins: H8SX/1648 Group, H8SX/1648A Group, H8SX/1648L Group: 13 pins each. H8SX/1648G Group, H8SX/1648H Group: 13 pins each.
• Input/Output pins: H8SX/1648 Group, H8SX/1648A Group, H8SX/1648L Group: 97 pins each. H8SX/1648G Group, H8SX/1648H: 102 pins each.
• Eight large-current drive pins (port 3)
• 40 pull-up resistors
• 16 open drains
• Four open-drain I/O pins supporting 5 V input Package • LQFP-144 package*
• LFBGA176 package*

Rev. 2.00 Jul. 31, 2008 Page 9 of 1438 REJ09B0365-0200 Classification Module/ Function Description Operating frequency/ Power supply voltage

• Operating frequency: 8 to 50 MHz Operating peripheral temperature (°C)
• − 20 to +75°C (regular specifications)
• − 40 to +85°C (wide-range specifications) Notes: 1. Supported only by the H8 SX/1648G Group and the H8SX/1648H Group. 2. Supported only by the H8SX/1 648 Group, the H8SX/1648A Group, and the H8SX/1648L Group. 3. Supported only by the H8SX/1 648L Group and the H8SX/1648H Group.

Rev. 2.00 Jul. 31, 2008 Page 10 of 1438 REJ09B0365-0200 Table 1.2 Comparison of Support Functions in the H8SX/1648, 1648A, 1648L, 1648G, and 1648H Groups Function The H8SX/1648 and H8SX/1648A Group * The H8SX/1648L Group The H8SX/1648G Group The H8SX/1648H Group DMAC O O O O DTC O O O O PPG O O O O UBC O O O O SCI O O O O IIC2 O O O O TMR O O O O WDT O O O O 10-bit ADC O O O O 8-bit DAC O O O O EXDMAC   O O SDRAM interface   O O 32K timer   O O POR/LVD  O  O LQFP-144 O O   Package LFBGA-176   O O Note: * The setting method of Port 6 differs in the H8SX/1648 Group and the H8SX/1648A Group. For details, see section 13.2.5, Port 6.

Rev. 2.00 Jul. 31, 2008 Page 11 of 1438 REJ09B0365-0200

1.2 List of Products

Table 1.3 is the list of products, and figure 1.1 shows how to read the product name code. Table 1.3 List of Products Group Part No. ROM Capacity RAM Capacity Package Remarks R5F61648N50FPV 1024 Kbytes 56 Kbytes LQFP-144 R5F61644N50FPV 512 Kbytes 40 Kbytes LQFP-144 R5F61642N50FPV 256 Kbytes 24 Kbytes LQFP-144 Regular specifica- tions R5F61648D50FPV 1024 Kbytes 56 Kbytes LQFP-144 R5F61644D50FPV 512 Kbytes 40 Kbytes LQFP-144 H8SX/1648 R5F61642D50FPV 256 Kbytes 24 Kbytes LQFP-144 Wide range specifica- tions R5F61648AN50FPV 1024 Kbytes 56 Kbytes LQFP-144 R5F61644AN50FPV 512 Kbytes 40 Kbytes LQFP-144 R5F61642AN50FPV 256 Kbytes 24 Kbytes LQFP-144 Regular specifica- tions R5F61648AD50FPV 1024 Kbytes 56 Kbytes LQFP-144 R5F61644AD50FPV 512 Kbytes 40 Kbytes LQFP-144 H8SX/1648A R5F61642AD50FPV 256 Kbytes 24 Kbytes LQFP-144 Wide range specifica- tions R5F61648GN50BGV 1024 Kbyt es 56 Kbytes LFBGA-176 R5F61644GN50BGV 512 Kbyt es 40 Kbytes LFBGA-176 R5F61642GN50BGV 256 Kbyt es 24 Kbytes LFBGA-176 Regular specifica- tions R5F61648GD50BGV 1024 Kbyt es 56 Kbytes LFBGA-176 R5F61644GD50BGV 512 Kbyt es 40 Kbytes LFBGA-176 H8SX/1648G R5F61642GD50BGV 256 Kbyt es 24 Kbytes LFBGA-176 Wide range specifica- tions R5F61648LN50FPV 1024 Kbytes 56 Kbytes LQFP-144 R5F61644LN50FPV 512 Kbytes 40 Kbytes LQFP-144 R5F61642LN50FPV 256 Kbytes 24 Kbytes LQFP-144 Regular specifica- tions R5F61648LD50FPV 1024 Kbytes 56 Kbytes LQFP-144 R5F61644LD50FPV 512 Kbytes 40 Kbytes LQFP-144 H8SX/1648L R5F61642LD50FPV 256 Kbytes 24 Kbytes LQFP-144 Wide range specifica- tions

Rev. 2.00 Jul. 31, 2008 Page 12 of 1438 REJ09B0365-0200 Group Part No. ROM Capacity RAM Capacity Package Remarks R5F61648HN50BGV 1024 Kbytes 56 Kbytes LFBGA-176 R5F61644 HN50BGV 512 Kbytes 40 Kbytes LFBGA-176 H8SX/1648H R5F61642 HN50BGV 256 Kbytes 24 Kbytes LFBGA-176 Regular specifica- tions R5F61648HD50BGV 1024 Kbytes 56 Kbytes LFBGA-176 R5F61644 HD50BGV 512 Kbytes 40 Kbytes LFBGA-176 R5F61642 HD50BGV 256 Kbytes 24 Kbytes LFBGA-176 Wide range specifica- tions Part No. Indicates the Pb-free version. Indicates a Renesas semiconductor product. Indicates the package. FP: LQFP BG: LFBGA Indicates the product-specific number. N: Regular specification D: Wide range specification Indicates the type of ROM device. F: On-chip flash memory Product classification Microcontroller R 5 F 61648N50 FP V Figure 1.1 How to Read the Product Name Code

• Small Package Package Package Code Body Size Pin Pitch LQFP-144 PLQP0144KA-A (FP-144LV) * 20.0 × 20.0 mm 0.50 mm LFBGA-176 PLBG0176GA-A (BP-176V) * 13.0 × 13.0 mm 0.80 mm Note: * Pb-free version

Rev. 2.00 Jul. 31, 2008 Page 13 of 1438 REJ09B0365-0200

1.3 Block Diagram

POR/LVD*3 BSC DMAC × 4 channels EXDMAC × 4 channels*2 TMR × 2 channels (Unit0) TMR × 2 channels (Unit1) TPU × 6 channels (Unit0) IIC2 × 4 channels SCI × 7 channels TMR × 2 channels (Unit3) TMR × 2 channels (Unit2) WDT TM32K*2 TPU × 6 channels (Unit1) PPG × 16 channels (Unit0) PPG × 16 channels (Unit1) 10-bit AD × 4 channels (Unit1) 10-bit AD × 4 channels (Unit2) 10-bit AD × 4 channels (Unit0) Port 1 Port 2 Port 3 Port 6 Port A Port B Port C Port D/ Port J*1 Port E/ Port K*1 Port F Port H Port I Port N Port M*2 8-bitDA × 2 channels Port 5 Port 4 Main clock oscillator Sub clock osillator*2 Interrupt controller Internal system bus Internal system bus Internal system bus [Legend] Central processing unit Data transfer controller Bus controller DMA controller EXDMA Controller 32K Timer Watchdog timer 8-bit timer 16-bit timer pulse unit Programmable pulse generator Serial communications interface IIC bus interface 2 Power-on reset / Low voltage detection circuit TMR: TPU: PPG: SCI: IIC2: POR/LVD *3: CPU: DTC: BSC: DMAC: EXDMAC *2: TM32K*2: WDT: Note: *1 In single-chip mode, the port D and port E functions can be used in the initial state. Pin functions are selectable by setting the PCJKE bit in PFCRD. Ports D and E are enabled when PCJKE = 0 (initial value) and ports J and K are enabled when PCJKE = 1. In external extended mode, only ports D and E can be used. * 2 Supported only by the H8SX/1648G Group and H8SX/1648H Group. * 3 Supported only by the 8SX/1648L Group and H8SX/1648H Group. Figure 1.2 Block Diagram

Rev. 2.00 Jul. 31, 2008 Page 14 of 1438 REJ09B0365-0200

1.4 Pin Assignments

1.4.1 Pin Assignments

108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 PB1/CS1/CS2-B/CS5-A/CS6-B/CS7-B PB2/CS2-A/CS6-A PB3/CS3-A/CS7-A VSS PB7/CS7-D VCC MD2 PN0/SDA2 PN1/SCL2 PC5 PF7/A23/SCK5 PF6/A22/RxD5/IrRxD PF5/A21/TxD5/IrTxD PF4/A20 PF3/A19 VSS PF2/A18 PF1/A17 PF0/A16 PE7/A15 PE6/A14 PE5/A13 VSS PE4/A12 VCC PE3/A11 PE2/A10 PE1/A9 PE0/A8 PD7/A7 PD6/A6 VSS PD5/A5 PD4/A4 PD3/A3 PD2/A2 PK7/PO31/TIOCA11/TIOCB11 PK6/PO30/TIOCA11 PK5/PO29/TIOCA10/TIOCB10 PJ5/PO21/TIOCA7/TIOCB7/TCLKG PJ4/PO20/TIOCA7 PJ3/PO19/TIOCC6/TIOCD6/TCLKF PJ2/PO18/TIOCC6/TCLKE PK3/PO27/TIOCC9/TIOCD9 PK2/PO26/TIOCC9 PK1/PO25/TIOCA9/TIOCB9 PK0/PO24/TIOCA9 PJ7/PO23/TIOCA8/TIOCB8/TCLKH PJ6/PO22/TIOCA8 PK4/PO28/TIOCA10 P61/TMCI2/RxD4/TEND2/IRQ9-B P60/TMRI2/TxD4/DREQ2/IRQ8-B P37/PO15/TIOCA2/TIOCB2/TCLKD-A P36/PO14/TIOCA2 P35/PO13/TIOCA1/TIOCB1/TCLKC-A/DACK1-B VSS STBY P17/TCLKD-B/SCL0/ADTRG1-A/IRQ7-A P16/TCLKC-B/SCK3/SDA0/DACK1-A/IRQ6-A Vcc EXTAL XTAL Vss WDTOVF/TDO P15/TCLKB-B/RxD3/SCL1/TEND1-A/IRQ5-A P14/TCLKA-B/TxD3/SDA1/DREQ1-A/IRQ4-A VCL RES P67/IRQ15-B P66 VSS P13/ADTRG0-A/IRQ3-A P12/SCK2/DACK0-A/IRQ2-A P11/RxD2/TEND0-A/IRQ1-A P10/TxD2/DREQ0-A/IRQ0-A PI7/D15 PI6/D14 PI5/D13 PI4/D12 Vss PI3/D11 PI2/D10 PI1/D9 PI0/D8 VCC PH7/D7 PH6/D6 PH5/D5 PH4/D4 VSS PH3/D3 PH2/D2 PH1/D1 PH0/D0 VCC P34/PO12/TIOCA1/TEND1-B P33/PO11/TIOCC0/TIOCD0/TCLKB-A/DREQ1-B NMI P27/PO7/TIOCA5/TIOCB5/IRQ15-A P26/PO6/TIOCA5/TMO1/TxD1/IRQ14 P32/PO10/TIOCC0/TCLKA-A/DACK0-B P31/PO9/TIOCA0/TIOCB0/TEND0-B P30/PO8/TIOCA0/DREQ0-B P25/PO5/TIOCA4/TMCI1/RxD1/IRQ13-A P24/PO4/TIOCA4/TIOCB4/TMRI1/SCK1/IRQ12-A P23/PO3/TIOCC3/TIOCD3/IRQ11-A P22/PO2/TIOCC3/TMO0/TxD0/IRQ10-A P21/PO1/TIOCA3/TMCI0/RxD0/IRQ9-A VCC P20/PO0/TIOCA3/TIOCB3/TMRI0/SCK0/IRQ8-A VSS PC4/ADTRG2 PC1/CS4-C/CS5-C/CS6-C/CS7-C PC0/CS3-B/WAIT-B/ADTRG1-B PB6/CS6-D/(RD/WR-B)/ADTRG0-B PB5/CS5-D PB4/CS4-B PN3/SCL3 PN2/SDA3 EMLE PD0/A0 PD1/A1 PJ0/PO16/TIOCA6 PJ1/PO17/TIOCA6/TIOCB6 P62/TMO2/SCK4/DACK2/IRQ10-B/TRST PLLVCC P63/TMRI3/TxD6/DREQ3/IRQ11-B/TMS PLLVSS P64/TMCI3/RxD6/TEND3/IRQ12-B/TDI P65/TMO3/SCK6/DACK3/IRQ13-B/TCK MD0 PC2 PC3 P50/AN0/IRQ0-B P51/AN1/IRQ1-B P52/AN2/IRQ2-B AVcc P53/AN3/IRQ3-B AVss P54/AN4/IRQ4-B Vref P55/AN5/IRQ5-B P56/AN6/DA0/IRQ6-B P57/AN7/DA1/IRQ7-B P44/AN8 P45/AN9 P46/AN10 P47/AN11 MD1 PA0/BREQO/BS-A PA1/BACK/(RD/WR-A) PA2/BREQ/WAIT-A PA3/LLWR/LLB PA4/LHWR/LUB PA5/RD PA6/AS/AH/BS-B Vss PA7/Bφ Vcc PB0/CS0/CS4-A/CS5-B 88 87 86 85 84 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 92 0 2 12 22 32 42 5 26 27 28 29 30 31 32 33 34 35 36 83 82 81 80 79 78 77 76 75 74 73 LQFP-144 (Top Vew) Notes: 1. In single-chip mode prots D and E can be used (initial state). Pin functions are selectable by setting the PCJKE bit in PFCRD. Pin functions are selectable by setting the PCJKE bit in PFCRD. Ports D and E are enabled when PCJKE = 0 (initial value) and ports J and K are enabled when PCJKE = 1. In external extended mode, only ports D and E can be used. 2. This pin is an on-chip emulator enable pin. Drive this pin low for the connection in normal operating mode. The on-chip emulator function is enabled by driving this pin high. When the on-chip emulator is in use, the P62, P63, P64, P65, and WDTOVF pins are dedicated pins for the on-chip emulator. For details on a connection example with the E10A, see E10A Emulator User's Manual. Figure 1.3 Pin Assignments (LQFP-144: H8SX/1648, 1648A, and 1648L Groups)

Rev. 2.00 Jul. 31, 2008 Page 15 of 1438 REJ09B0365-0200 1110 91 4 1 5 131287654321 PB1 PB3 Vcc PN0 PM2 PF6 Vss PF0 Vss PE3*1 PE0*1 Vss PD4*1 PD1*1 EMLE*2 PC3 MD0 P64 P37 P17 WDTOVF RES P67 P13 PI7 PI3 Vss PH2 PH1 PH0 PLLVcc P61 P36 STBY Vcc XTAL P14 OSC2*4 Vss P11 PI6 Vss PI1 Vcc PH7 NC*3 P62 P60 Vss P16 EXTAL P15 OSC1*4 P66 P12 PI5 PI2 NC PH6 PH5 P65 PLLVss P63 P35 NC*3 Vss VCL NC*3 Vss P10 PI4 PI0 Vss PH4 PH3 PA1 PA2 PA0 PA3 NC NC*3 Vss NC*3 P47 MD1 P46 P45 P80 NC PC1 Vss PC4 AVcc P53 NC *3 P52 P31 P32 P27 P26 P51 P50 NC*3 PC2 Vcc NMI P34 P33 Vref NC*3 P54 AVss P23 P23 P24 P30 P25 P57 P44 P56 P55 P20 Vcc P22 P21 NC*3 MD3*4 NC*3 NC*3 PB4 PB4 PB5 PC0 PB6 PA4 PA5 PA6 Vss PM0 PC5 PF4 PF2 PE6 Vcc PD6*1 PD3*1 PM4 NC*3 NC*3 Vcc PA7 PB2 PB7 PM1 PF7 PF3 PF1 PE5 NC*3 PE1*1 PD5*1 PN2 PN3 Vcc Vcc PB0 Vss MD2 PN1 PF5 Vss PE7*1 PE4*1 PE2*1 PD7*1 Vss PD2*1 PD0*1 PM3 91 4 1 5 131287654321 A B C D E F G H J K L M N P R A B C D E F G H J K L M N P R LFBGA-176 (Top view) Notes: 1. In single-chip mode prots D and E can be used (initial state). Pin functions are selectable by setting the PCJKE bit in PFCRD. Pin functions are selectable by setting the PCJKE bit in PFCRD. Ports D and E are enabled when PCJKE = 0 (initial value) and ports J and K are enabled when PCJKE = 1. In external extended mode, only ports D and E can be used. This pin is an on-chip emulator enable pin. Drive this pin low for the connection in normal operating mode. The on-chip emulator function is enabled by driving this pin high. When the on-chip emulator is in use, the P62, P63, P64, P65, and WDTOVF pins are dedicated pins for the on-chip emulator. For details on a connection example with the E10A, see E10A Emulator User's Manual. 3. NC should be left open. Figure 1.4 Pin Assignments (LFBGA-176: H8SX/1648G and 1648H Groups)

Rev. 2.00 Jul. 31, 2008 Page 16 of 1438 REJ09B0365-0200

1.4.2 Correspondence between Pin Configuration and Operating Modes

Table 1.4 Pin Configuration in Each Operating Mode (H8SX/1648, 1648A, 1648G, and 1648H Groups) Pin no. Pin name LQFP- 144 LFBGA- 176 Mode 1, 2, 6 Mode 3, 7 Mode 4. 5

1 A1 PB1/ CS1/CS2-B/CS5-A/

2 C3 PB2/ CS2-A/CS6-A/RAS*

PB2/ CS2-A/CS6-A/RAS* PB2/ CS2-A/CS6-A/RAS*

3 B1 PB3/ CS3-A/CS7-A/CAS*

PB3/ CS3-A/CS7-A/CAS* PB3/ CS3-A/CS7-A/CAS*

4 C2 VSS VSS VSS

5 D3 PB7/ CS7-D/SDRAMφ*

PB7/ CS7-D/SDRAMφ* PB7/ CS7-D/SDRAMφ*

6 C1 VCC VCC VCC

7 D2 MD2 MD2 MD2

 E4 PM0 * PM0 * PM0 *

8 D1 PN0/SDA2 PN0/SDA2 PN0/SDA2

 E3 PM1 * PM1 * PM1 *

9 E2 PN1/SCL2 PN1/SCL2 PN1/SCL2

 E1 PM2 * PM2 * PM2 *

10 F4 PC5 PC5 PC5

11 F3 PF7/A23/SCK5 PF7/A23/SCK5 PF7/A23/SCK5

12 F1 PF6/A22/RxD5/IrRxD PF6/A22/RxD5/IrRxD PF6/A22/RxD5/IrRxD

13 F2 PF5/A21/TxD5/IrTxD PF5/A21/TxD5/IrTxD PF5/A21/TxD5/IrTxD

14 G4 PF4/A20 PF4/A20 A20

15 G3 PF3/A19 PF3/A19 A19

16 G1 VSS VSS Vss

 G2 VSS VSS VSS

17 H4 PF2/A18 PF2/A18 A18

18 H3 PF1/A17 PF1/A17 A17

19 H1 PF0/A16 PF0/A16 A16

20 H2 PE7/A15 PE7/A15 PK7/PO31/

TIOCB11* A15

Rev. 2.00 Jul. 31, 2008 Page 17 of 1438 REJ09B0365-0200 Pin no. Pin name LQFP- 144 LFBGA- 176 Mode 1, 2, 6 Mode 3, 7 Mode 4. 5

21 J4 PE6/A14 PE6/A14 PK6/PO30/

TIOCA11* A14

22 J3 PE5/A13 PE5/A13 PK5/PO29/

TIOCB10* A13

23 J1 Vss Vss Vss

24 J2 PE4/A12 PE4/A12 PK4/PO28/

TIOCA10* A12

25 K4 Vcc Vcc Vcc

 K3 NC NC NC

26 K1 PE3/A11 PE3/A11 PK3/PO27/

TIOCD9* A11

27 K2 PE2/A10 PE2/A10 PK2/PO26/

TIOCC9* A10

28 L3 PE1/A9 PE1/A9 PK1/PO25/

TIOCA9/TIOCB9*

29 L1 PE0/A8 PE0/A8 PK0/PO24/

TIOCA9*

30 L2 PD7/A7 PD7/A7 PJ7/PO23/

TCLKH*

31 L4 PD6/A6 PD6/A6 PJ6/PO22/

TIOCA8*

32 M1 Vss Vss Vss

 M2 Vss Vss Vss

33 M3 PD5/A5 PD5/A5 PJ5/PO21/

TCLKG*

34 N1 PD4/A4 PD4/A4 PJ4/PO20/

TIOCA7*

35 M4 PD3/A3 PD3/A3 PJ3/PO19/

TCLKF*

36 N2 PD2/A2 PD2/A2 PJ2/PO18/

TIOCC6/TCLKE*

Rev. 2.00 Jul. 31, 2008 Page 18 of 1438 REJ09B0365-0200 Pin no. Pin name LQFP- 144 LFBGA- 176 Mode 1, 2, 6 Mode 3, 7 Mode 4. 5

37 P1 PD1/A1 PD1/A1 PJ1/PO17/

TIOCA6/TIOCB6*

38 P2 PD0/A0 PD0/A0 PJ0/PO16/

TIOCA6*

39 R1 EMLE EMLE EMLE

40 N3 PN2/SDA3 PN2/SDA3 PN2/SDA3

 R2 PM3 * PM3 * PM3 *

41 P3 PN3/SCL3 PN3/SCL3 PN3/SCL3

 N4 PM4 * PM4 * PM4 *  R3 VCC VCC VCC  P4 NC NC NC  M5 NC NC NC  R4 NC NC NC  N5 NC NC NC  P5 Vss Vss Vss  R5 NC NC NC

42 M6 PB4/ CS4-B/WE*

PB4/ CS4-B/WE* PB4/ CS4-B/WE*

43 N6 PB5/ CS5-D/OE/CKE*

PB5/ CS5-D/OE/CKE* PB5/ CS5-D/OE/CKE*

44 R6 PB6/ CS6-D/

(RD/WR-B)/ADTRG0-B PB6/CS6-D/ (RD/WR-B)/ADTRG0-B PB6/CS6-D/ (RD/WR-B)/ADTRG0-B

45 P6 PC0/ CS3-B/WAIT-

 M7 NC NC NC

46 N7 PC1/ CS4-C/CS5-C/

47 R7 PC4/ ADTRG2 PC4/ ADTRG2 PC4/ ADTRG2

48 P7 VSS VSS VSS

49 M8 P20/PO0/TIOCA3/TIOCB3/

50 N8 VCC VCC VCC

51 R8 P21/PO1/TIOCA3/TMCI0/

Rev. 2.00 Jul. 31, 2008 Page 19 of 1438 REJ09B0365-0200 Pin no. Pin name LQFP- 144 LFBGA- 176 Mode 1, 2, 6 Mode 3, 7 Mode 4. 5

52 P8 P22/PO2/TIOCC3/TMO0/

53 M9 P23/PO3/TIOCC3/TIOCD3/

54 N9 P24/PO4/TIOCA4/TIOCB4/

55 R9 P25/PO5/TIOCA4/TMCI1/

56 P9 P30/PO8/TIOCA0/

DREQ0-B/EDREQ2* P30/PO8/TIOCA0/ DREQ0-B/EDREQ2* P30/PO8/TIOCA0/ DREQ0-B/EDREQ2*

57 M10 P31/PO9/TIOCA0/TIOCB0/

TEND0-B/ETEND2* P31/PO9/TIOCA0/TIOCB0/ TEND0-B/ETEND2* P31/PO9/TIOCA0/TIOCB0/ TEND0-B/ETEND2*

58 N10 P32/PO10/TIOCC0/TCLKA-A/

DACK0-B/EDACK2* P32/PO10/TIOCC0/TCLKA-A/ DACK0-B/EDACK2* P32/PO10/TIOCC0/TCLKA- DACK0-B/EDACK2*

59 R10 P26/PO6/TIOCA5/TMO1/

60 P10 P27/PO7/TIOCA5/TIOCB5/

61 N11 NMI NMI NMI

62 R11 P33/PO11/TIOCC0/TIOCD0/

EDREQ3* P33/PO11/TIOCC0/TIOCD0/ TCLKB-A/DREQ1-B/ EDREQ3* P33/PO11/TIOCC0/TIOCD0/ TCLKB-A/DREQ1-B/ EDREQ3*

63 P11 P34/PO12/TIOCA1/

TEND1-B/ETEND3* P34/PO12/TIOCA1/ TEND1-B/ETEND3* P34/PO12/TIOCA1/ TEND1-B/ETEND3*

64 M11 VCC VCC VCC

65 R12 PH0/D0 PH0/D0 D0

66 P12 PH1/D1 PH1/D1 D1

67 N12 PH2/D2 PH2/D2 D2

68 R13 PH3/D3 PH3/D3 D3

69 M12 VSS VSS VSS

70 P13 PH4/D4 PH4/D4 D4

71 R14 PH5/D5 PH5/D5 D5

72 P14 PH6/D6 PH6/D6 D6

Rev. 2.00 Jul. 31, 2008 Page 20 of 1438 REJ09B0365-0200 Pin no. Pin name LQFP- 144 LFBGA- 176 Mode 1, 2, 6 Mode 3, 7 Mode 4. 5

73 R15 PH7/D7 PH7/D7 D7

 N13 Vcc Vcc Vcc

74 P15 Vcc Vcc Vcc

 N14 NC NC NC

75 M13 PI0/D8 PI0/D8 PI0/D8

76 N15 PI1/D9 PI1/D9 PI1/D9

77 M14 PI2/D10 PI2/D10 PI2/D10

78 L12 PI3/D11 PI3/D11 PI3/D11

79 M15 Vss Vss Vss

80 L13 PI4/D12 PI4/D12 PI4/D12

81 L14 PI5/D13 PI5/D13 PI5/D13

82 L15 PI6/D14 PI6/D14 PI6/D14

83 K12 PI7/D15 PI7/D15 PI7/D15

84 K13 P10/TxD2/ DREQ0-A/

EDREQ0-A* /IRQ0-A P10/TxD2/DREQ0-A/ EDREQ0-A* /IRQ0-A P10/TxD2/DREQ0-A/ EDREQ0-A* /IRQ0-A

85 K15 P11/RxD2/ TEND0-A/

ETEND0-A* /IRQ1-A P11/RxD2/TEND0-A/ ETEND0-A* /IRQ1-A P11/RxD2/TEND0-A/ ETEND0-A* /IRQ1-A

86 K14 P12/SCK2/ DACK0-A/

EDACK0-A* /IRQ2-A P12/SCK2/DACK0-A/ EDACK0-A* /IRQ2-A P12/SCK2/DACK0-A/ EDACK0-A* /IRQ2-A

87 J12 P13/ ADTRG0-A/EDRAK0-A*

P13/ADTRG0-A/EDRAK0-A* IRQ3-A P13/ADTRG0-A/ EDRAK0-A* /IRQ3-A

88 J13 Vss Vss Vss

 J15 Vss Vss Vss

89 J14 P66/ EDRAK0-B*

P66/ EDRAK0-B* P66/ EDRAK0-B*

90 H12 P67/ EDRAK1-B*

/IRQ15-B P67/ EDRAK1-B* /IRQ15-B P67/ EDRAK1-B* /IRQ15-B  H13 NC NC NC  H15 OSC2 * OSC2 * OSC2 *  H14 OSC1 * OSC1 * OSC1 *

91 G12 RES RES RES

92 G13 VCL VCL VCL

Rev. 2.00 Jul. 31, 2008 Page 21 of 1438 REJ09B0365-0200 Pin no. Pin name LQFP- 144 LFBGA- 176 Mode 1, 2, 6 Mode 3, 7 Mode 4. 5

93 G15 P14/TCLKA-B/TxD3/

EDREQ1-A* /IRQ4-A P14/TCLKA-B/TxD3/ SDA1/DREQ1-A/ EDREQ1-A* /IRQ4-A P14/TCLKA-B/TxD3/ SDA1/DREQ1-A/ EDREQ1-A* /IRQ4-A

94 G14 P15/TCLKB-B/RxD3/

ETEND1-A* /IRQ5-A* P15/TCLKB-B/RxD3/ SCL1/TEND1-A/ ETEND1-A* /IRQ5-A* P15/TCLKB-B/RxD3/ SCL1/TEND1-A/ ETEND1-A* /IRQ5-A*

95 F12 WDTOVF WDTOVF/TDO*

96 F13 Vss Vss Vss

97 F15 XTAL XTAL XTAL

98 F14 EXTAL EXTAL EXTAL

 E13 NC NC NC

99 E15 Vcc Vcc Vcc

100 E14 P16/TCLKC-B/

EDACK1-A* /IRQ6-A P16/TCLKC-B/ SCK3/SDA0/DACK1-A/ EDACK1-A* /IRQ6-A P16/TCLKC-B/ SCK3/SDA0/DACK1-A/ EDACK1-A* /IRQ6-A

101 E12 P17/TCLKD-B/

EDRAK1-A* /IRQ7-A P17/TCLKD-B/ SCL0/ADTRG1-A/ EDRAK1-A* /IRQ7-A P17/TCLKD-B/ SCL0/ADTRG1-A/ EDRAK1-A* /IRQ7-A

102 D15 STBY STBY STBY

103 D14 Vss Vss Vss

104 D13 P35/PO13/TIOCA1/TIOCB1/

EDACK3* P35/PO13/TIOCA1/TIOCB1/ TCLKC-A/DACK1-B/ EDACK3* P35/PO13/TIOCA1/TIOCB1/ TCLKC-A/DACK1-B/ EDACK3*

105 C15 P36/PO14/TIOCA2/

EDRAK2* P36/PO14/TIOCA2/ EDRAK2* P36/PO14/TIOCA2/ EDRAK2*

106 D12 P37/PO15/TIOCA2/TIOCB2/

TCLKD-A/EDRAK3* P37/PO15/TIOCA2/TIOCB2/ TCLKD-A/EDRAK3* P37/PO15/TIOCA2/TIOCB2/ TCLKD-A/EDRAK3*

107 C14 P60/TMRI2/TxD4/ DERQ2/

EDREQ0-B* /IRQ8-B P60/TMRI2/TxD4/DERQ2/ EDREQ0-B* /IRQ8-B P60/TMRI2/TxD4/DERQ2/ EDREQ0-B* /IRQ8-B

108 B15 P61/TMCI2/RxD4/ TEND2/ET

END0-B* /IRQ9-B P61/TMCI2/RxD4/TEND2/ET END0-B* /IRQ9-B P61/TMCI2/RxD4/TEND2/ ETEND0-B* /IRQ9-B

109 B14 P62/TMO2/SCK4/ DACK2/

EDACK0-B* IRQ10-B P62/TMO2/SCK4/DACK2/ EDACK0-B* /TRST* P62/TMO2/SCK4/DACK2/ EDACK0-B*

110 A15 PLLVcc PLLVcc PLLVcc

Rev. 2.00 Jul. 31, 2008 Page 22 of 1438 REJ09B0365-0200 Pin no. Pin name LQFP- 144 LFBGA- 176 Mode 1, 2, 6 Mode 3, 7 Mode 4. 5

111 C13 P63/TMRI3/TxD6/ DREQ3/

EDREQ1-B* IRQ11-B P63/TMRI3/TxD6/DREQ3/ EDREQ1-B* IRQ11-B/TMS* P63/TMRI3/TxD6/DREQ3/ EDREQ1-B* IRQ11-B  A14 NC NC NC

112 B13 PLLVss PLLVss PLLVss

113 C12 P64/TMCI3/RxD6/ TEND3/

ETEND1-B* IRQ12-B P64/TMCI3/RxD6/TEND3/ ETEND1-B* IRQ12-B/TDI* P64/TMCI3/RxD6/TEND3/ ETEND1-B* /IRQ12-B

114 A13 P65/TMO3/SCK6/ DACK3/

EDACK1-B* IRQ13-B P65/TMO3/SCK6/DACK3/ EDACK1-B* IRQ13-B/TCK* P65/TMO3/SCK6/DACK3/ EDACK1-B* IRQ13-B

115 B12 MD0 MD0 MD0

116 D11 PC2/ LUCAS/DQMLU*

PC2/ LUCAS/DQMLU* PC2/ LUCAS/DQMLU*

117 A12 PC3/ LLCAS/DQMLL*

PC3/ LLCAS/DQMLL* PC3/ LLCAS/DQMLL*  C11 NC NC NC

118 B11 P50/AN0/ IRQ0-B P50/AN0/ IRQ0-B P50/AN0/ IRQ0-B

119 A11 P51/AN1/ IRQ1-B P51/AN1/ IRQ1-B P51/AN1/ IRQ1-B

120 D10 P52/AN2/ IRQ2-B P52/AN2/ IRQ2-B P52/AN2/ IRQ2-B

 C10 NC NC NC

121 A10 Avcc Avcc Avcc

122 B10 P53/AN3/ IRQ3-B P53/AN3/ IRQ3-B P53/AN3/ IRQ3-B

123 D9 Avss Avss Avss

124 C9 P54/AN4/ IRQ4-B P54/AN4/ IRQ4-B P54/AN4/ IRQ4-B

125 A9 Vref Vref Vref

 B9 NC NC NC

126 D8 P55/AN5/ IRQ5-B P55/AN5/ IRQ5-B P55/AN5/ IRQ5-B

127 C8 P56/AN6/DA0/ IRQ6-B P56/AN6/DA0/ IRQ6-B P56/AN6/DA0/ IRQ6-B

128 A8 P57/AN7/DA1/ IRQ7-B P57/AN7/DA1/ IRQ7-B P57/AN7/DA1/ IRQ7-B

129 B8 P44/AN8 P44/AN8 P44/AN8

130 D7 P45/AN9 P45/AN9 P45/AN9

131 C7 P46/AN10 P46/AN10 P46/AN10

132 A7 P47/AN11 P47/AN11 P47/AN11

Rev. 2.00 Jul. 31, 2008 Page 23 of 1438 REJ09B0365-0200 Pin no. Pin name LQFP- 144 LFBGA- 176 Mode 1, 2, 6 Mode 3, 7 Mode 4. 5

133 B7 MD1 MD1 MD1

 D6 NC NC NC  C6 NC NC NC  A6 NC NC NC  B6 MD3 * MD3 * MD3 *

134 C5 PA0/ BREQO/BS-A PA0/ BREQO/BS-A PA0/ BREQO/BS-A

135 A5 PA1/ BACK/(RD/WR-A) PA1/ BACK/(RD/WR-A) PA1/ BACK/(RD/WR-A)

136 B5 PA2/ BREQ/WAIT-A PA2/ BREQ/WAIT-A PA2/ BREQ/WAIT-A

137 D5 PA3/ LLWR/LLB PA3/ LLWR/LLB LLWR/LLB

138 A4 PA4/ LHWR/LUB PA4/ LHWR/LUB PA4/ LHWR/LUB

139 B4 PA5/ RD PA5/ RD RD

140 C4 PA6/ AS/AH/BS-B PA6/ AS/AH/BS-B PA6/ AS/AH/BS-B

 A3 Vcc Vcc Vcc

141 D4 Vss Vss Vss

142 B3 PA7/B φ PA7/B φ PA7/B φ

143 A2 Vcc Vcc Vcc

144 B2 PB0/ CS0/CS4-A/CS5-B PB0/ CS0/CS4-A/CS5-B PB0/ CS0/CS4-A/CS5-B

Notes: 1. These pins can be used when the PCJKE bit in PFCRD is set to 1 in single-chip mode. 2. Pins TDO, TRST, TMS, TDI, and TCK are enabled in mode 3. 3. Supported only by the H8SX/1 648G Group and the H8SX/1648H Group. 4. The IRQ15-A is not supported by the H8SX/1648G Group and the H8SX/1648H Group.

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1.4.3 Pin Functions

Table 1.5 Pin Functions Classification Pin Name I/O Description Power supply V CC Input Power supply pins. Connect them to the system power supply. V CL Input Connect this pin to V SS via a 0.1-µF capacitor (The capacitor should be placed close to the pin). V SS Input Ground pins. Connect them to the system power supply (0 V). PLLV CC Input Power supply pin for the PLL circuit. PLLV SS Input Ground pin for the PLL circuit. Clock XTAL Input EXTAL Input Pins for a crystal resonator. An external clock signal can be input through the EXTAL pin. For an example of this connection, see section 26, Clock Pulse Generator. OSC1 * Input The 32.768 kHz crystal res onator is connected to this pin. OSC2 * Input The 32.768 kHz crystal res onator is connected to this pin. Bφ Output Outputs the system clock for external devices. SDRAMφ* Output When connecting the synchronous DRAM, connect it to the CLK pin of synchronous DRAM. For detail, see section 9, Bus Controller (BSC). Operating mode control MD3 to MD0 Input Pins for setting the operating mode. The signal levels on these pins must not be changed during operation. System control RES Input Reset signal input pin. This LSI enters the reset state when this signal goes low. STBY Input This LSI enters hardware standby mode when this signal goes low. EMLE Input Input pin for the on- chip emulator enable signal. If the on- chip emulator is used, the signal level should be fixed high. If the on-chip emulator is not used, the signal level should be fixed low. TRST Input TMS Input TDI Input TCK Input On-chip emulator TDO Output On-chip emulator pins or boundary scan pins. When the EMLE pin is driven high, these pins are dedicated for the on-chip emulator. When the EMLE pin is driven low and set to mode 3, these pins are dedicated for the boundary scan mode. Address bus A23 to A0 Output Output pins for the address bits.

Rev. 2.00 Jul. 31, 2008 Page 25 of 1438 REJ09B0365-0200 Classification Pin Name I/O Description Data bus D15 to D0 Input/ output Input and output for the bidirectional data bus. These pins also output addresses when accessing an address– data multiplexed I/O interface space. BREQ Input External bus-master modules assert this signal to request the bus. BREQO Output Internal bus-master modul es assert this signal to request access to the external space via the bus in the external bus released state. BACK Output Bus acknowledge signal, which indicates that the bus has been released. BS-A/BS-B Output Indicates the start of a bus cycle. AS Output Strobe signal which indicates that the output address on the address bus is valid in access to the basic bus interface or byte control SRAM interface space. AH Output This signal is used to hold the address when accessing the address-data multiplexed I/O interface space. RD Output Strobe signal which indica tes that reading from the basic bus interface space is in progress. RD/WR Output Indicates the direction (input or output) of the data bus. LHWR Output Strobe signal which indica tes that the higher-order byte (D15 to D8) is valid in access to the basic bus interface space. LLWR Output Strobe signal which indica tes that the lower-order byte (D7 to D0) is valid in access to the basic bus interface space. LUB Output Strobe signal which indica tes that the higher-order byte (D15 to D8) is valid in access to the byte control SRAM interface space. Bus control LLB Output Strobe signal which indica tes that the lower-order byte (D7 to D0) is valid in access to the byte control SRAM interface space.

Rev. 2.00 Jul. 31, 2008 Page 26 of 1438 REJ09B0365-0200 Classification Pin Name I/O Description CS0 CS1 CS2-A/CS2-B CS3-A/CS3-B CS4-A/CS4-B/ CS4-C CS5-A/CS5-B/ CS5-C/CS5-D CS6-A/CS6-B/ CS6-C/CS6-D CS7-A/CS7-B/ CS7- C/CS7-D Output Select signals for areas 0 to 7. WAIT-A/ WAIT-B Input Requests wait cycles in access to the external space. RAS* Output • Row address strobe signal when area 2 is specified as DRAM interface space

• Row address strobe signal when area 2 is specified as synchronous DRAM space CAS* Output Column address strobe signal when area 2 is specified as synchronous DRAM interface space WE* Output • Write enable signal for DRAM space
• Write enable signal when area 2 is specified as synchronous DRAM interface space OE/CKE* Output • Output enable signal for DRAM interface space
• Clock enable signal for synchronous DRAM interface space LUCAS* Output Upper column address strobe signal for 16-bit DRAM interface space LLCAS* Output • Lower-column address strobe signal for 16-bit DRAM interface space
• Column address strobe signal for 8-bit DRAM interface space DQMLU* Output Upper-data mask enable signal for 16-bit synchronous DRAM interface space Bus control DQMLL* Output • Lower-data mask enable signal for 16-bit synchronous DRAM interface space
• Data mask enable signal for 8-bit synchronous DRAM interface space

Rev. 2.00 Jul. 31, 2008 Page 27 of 1438 REJ09B0365-0200 Classification Pin Name I/O Description Interrupt NMI Input Non-maskable interr upt request signal. When this pin is not in use, this signal must be fixed high. IRQ15-A* /IRQ15-B IRQ14 IRQ13-A/IRQ13-B IRQ12-A/IRQ12-B IRQ11-A/IRQ11-B IRQ10-A/IRQ10-B IRQ9-A/IRQ9-B IRQ8-A/IRQ8-B IRQ7-A/IRQ7-B IRQ6-A/IRQ6-B IRQ5-A/IRQ5-B IRQ4-A/IRQ4-B IRQ3-A/IRQ3-B IRQ2-A/IRQ2-B IRQ1-A/IRQ1-B IRQ0-A/IRQ0-B Input Maskable interrupt request signal. DREQ0-A/DREQ0-B DREQ1-A/DREQ1-B DREQ2 DREQ3 Input Requests DMAC activation. DACK0-A/DACK0-B DACK1-A/DACK1-B DACK2 DACK3 Output DMAC single address- transfer acknowledge signal. DMA controller (DMAC) TEND0-A/TEND0-B TEND1-A/TEND1-B TEND2 TEND3 Output Indicates end of data transfer by the DMAC. EDREQ0-A/EDREQ0-B EDREQ1-A/EDREQ1-B EDREQ2 EDREQ3 Input Requests EXDMAC activation. EDACK0-A/EDACK0-B EDACK1-A/EDACK1-B EDACK2 EDACK3 Output EXDMAC single address-tr ansfer acknowledge signal. EXMDA controller (EXDMAC)* ETEND0-A/ETEND0-B ETEND1-A/ETEND1-B ETEND2 ETEND3 Output Indicates end of data transfer by the EXDMAC.

Rev. 2.00 Jul. 31, 2008 Page 28 of 1438 REJ09B0365-0200 Classification Pin Name I/O Description EXMDA controller (EXDMAC)* EDRAK0-A/EDRAK0-B EDRAK1-A/EDRAK1-B EDRAK2 EDRAK3 Output Notification to external device of EXDMAC external request acceptance and start of execution 16-bit timer pulse unit (TPU) TCLKA-A/TCLKA-B TCLKB-A/TCLKB-B TCLKC-A/TCLKC-B TCLKD-A/TCLKD-B Input Input pins for the external clock signals. TIOCA0 TIOCB0 TIOCC0 TIOCD0 Input/ output Signals for TGRA_0 to TGRD_0. These pins are used as input capture inputs, output compare outputs, or PWM outputs. TIOCA1 TIOCB1 Input/ output Signals for TGRA_1 and TGRB_1. These pins are used as input capture inputs, output compare outputs, or PWM outputs. TIOCA2 TIOCB2 Input/ output Signals for TGRA_2 and TGRB_2. These pins are used as input capture inputs, output compare outputs, or PWM outputs. TIOCA3 TIOCB3 TIOCC3 TIOCD3 Input/ output Signals for TGRA_3 to TGRD_3. These pins are used as input capture inputs, output compare outputs, or PWM outputs. TIOCA4 TIOCB4 Input/ output Signals for TGRA_4 and TGRB_4. These pins are used as input capture inputs, output compare outputs, or PWM outputs. TIOCA5 TIOCB5 Input/ output Signals for TGRA_5 and TGRB_5. These pins are used as input capture inputs, output compare outputs, or PWM outputs. TCLKE TCLKF TCLKG TCLKH Input Input pins for ex ternal clock signals. TIOCA6 TIOCB6 TIOCC6 TIOCD6 Input/ output Signals for TGRA_6 to TGRD_6. These pins are used as input capture inputs, output compare outputs, or PWM outputs. TIOCA7 TIOCB7 Input/ output Signals for TGRA_7 and TGRB_7. These pins are used as input capture inputs, output compare outputs, or PWM outputs.

Rev. 2.00 Jul. 31, 2008 Page 29 of 1438 REJ09B0365-0200 Classification Pin Name I/O Description 16-bit timer pulse unit (TPU) TIOCA8 TIOCB8 Input/ output Signals for TGRA_8 and TGRB_8. These pins are used as input capture inputs, output compare outputs, or PWM outputs. TIOCA9 TIOCB9 TIOCC9 TIOCD9 Input/ output Signals for TGRA_9 to TGRD_9. These pins are used as input capture inputs, output compare outputs, or PWM outputs. TIOCA10 TIOCB10 Input/ output Signals for TGRA_10 and TGRB_10. These pins are used as input capture inputs, output compare outputs, or PWM outputs. TIOCA11 TIOCB11 Input/ output Signals for TGRA_11 and TGRB_11. These pins are used as input capture inputs, output compare outputs, or PWM outputs. Programmable pulse generator (PPG) PO31 to PO0 Output Output pins for the pulse signals. TMO0 to TMO3 Output Output pins for the compare match signals. TMCI0 to TMCI3 Input Input pins for the external clock signals that drive for the counters. 8-bit timer (TMR) TMRI0 to TMRI3 Input Input pins for the counter-reset signals. Watchdog timer (WDT) WDTOVF Output Output pin for the counter-overflow signal in watchdog- timer mode. Serial communication interface (SCI) TxD0 TxD1 TxD2 TxD3 TxD4 TxD5 TxD6 Output Output pins for data transmission. RxD0 RxD1 RxD2 RxD3 RxD4 RxD5 RxD6 Input Input pins for data reception.

Rev. 2.00 Jul. 31, 2008 Page 30 of 1438 REJ09B0365-0200 Classification Pin Name I/O Description Serial communication interface (SCI) SCK0 SCK1 SCK2 SCK3 SCK4 SCK5 SCK6 Input/ output Input/output pins for clock signals. IrTxD Output Output pin that outputs encoded data for IrDA. SCI with IrDA (SCI) IrRxD Input Input pin that inputs encoded data for IrDA. SCL0 SCL1 SCL2 SCL3 Input/ output Input/output pin for IIC clock. Bus can be directly driven by the NMOS open drain output. SCL2 and SCL3 support 5-V input. I C bus interface 2 (IIC2) SDA0 SDA1 SDA2 SDA3 Input/ output Input/output pin for IIC data. Bus can be directly driven by the NMOS open drain output. SDA2 and SDA3 support 5-V input. AN11 to AN0 Input Input pins for the analog signals to be processed by the A/D converter. A/D converter ADTRG0-A/ ADTRG0-B ADTRG1-A/ ADTRG1-B ADTRG2 Input Input pins for the external trigger signal that starts A/D conversion. D/A converter DA1, DA0 Output Output pins for the analog signals from the D/A converter. A/D converter, D/A converter AV CC Input Analog power supply pin for the A/D and D/A converters. When the A/D and D/A converters are not in use, connect this pin to the system power supply. AV SS Input Ground pin for the A/D and D/A converters. Connect this pin to the system power supply (0 V). Vref Input Reference power supply pin for the A/D and D/A converters. When the A/D and D/A converters are not in use, connect this pin to the system power supply. P17 to P10 Input/ output 8-bit input/output pins. P27 to P20 Input/ output 8-bit input/output pins.

Rev. 2.00 Jul. 31, 2008 Page 31 of 1438 REJ09B0365-0200 Classification Pin Name I/O Description I/O ports P37 to P30 Input/ output 8-bit input/output pins. P47 to P44 Input 4-bit input-only pins. P57 to P50 Input 8-bit input-only pins. P67 to P60 Input/ output 8-bit input/output pins. PA7 Input Input-only pin. PA6 to PA0 Input/ output 7-bit input/output pins. PB7 to PB0 Input/ output 8-bit input/output pins. PC5 to PC0 Input/ output 6-bit input/output pins. PD7 to PD0 Input/ output 8-bit input/output pins. PE7 to PE0 Input/ output 8-bit input/output pins. PF7 to PF0 Input/ output 8-bit input/output pins. PH7 to PH0 Input/ output 8-bit input/output pins. PI7 to PI0 Input/ output 8-bit input/output pins. PN3 to PN0 Input/ output 4-bit input/output (open drain) pins. PM4 to PM0 * Input/ output 5-bit input/output pins PJ7 to PJ0 * Input/ output 8-bit input/output pins. PK7 to PK0 * Input/ output 8-bit input/output pins. Note: 1. These pins can be used when the PCJKE bit in PFCRD is set to 1 in single-chip mode. 2. The IRQ15-A is not supported by the H8SX/1648G Group and the H8SX/1648H Group. 3. Supported only by the H8SX/1 648G Group and the H8SX/1648H Group.

Rev. 2.00 Jul. 31, 2008 Page 32 of 1438 REJ09B0365-0200

Rev. 2.00 Jul. 31, 2008 Page 33 of 1438 REJ09B0365-0200 Section 2 CPU The H8SX CPU is a high-speed CPU with an internal 32-bit architecture that is upward compatible with the H8/300, H8/300H, and H8S CPUs. The H8SX CPU has sixteen 16-bit general registers, can handle a 4-Gbyte linear address space, and is ideal for a realtime control system.

2.1 Features

• Upward-compatible with H8/300, H8/300H, and H8S CPUs  Can execute object programs of these CPUs
• Sixteen 16-bit general registers  Also usable as sixteen 8-bit registers or eight 32-bit registers
• 87 basic instructions  8/16/32-bit arithmetic and logic instructions  Multiply and divide instructions  Bit field transfer instructions  Powerful bit-manipulation instructions  Bit condition branch instructions  Multiply-and-accumulate instruction
• Eleven addressing modes  Register direct [Rn]  Register indirect [@ERn]  Register indirect with displacement [@(d:2,ERn), @(d:16,ERn), or @(d:32,ERn)]  Index register indirect with displacement [@(d:16,RnL.B), @(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L)]  Register indirect with pre-/post-increment or pre-/post-decrement [@+ERn, @−ERn, @ERn+, or @ERn−]  Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]  Immediate [#xx:3, #xx:4, #xx:8, #xx:16, or #xx:32]  Program-counter relative [@(d:8,PC) or @(d:16,PC)]  Program-counter relative with index register [@(RnL.B,PC), @(Rn.W,PC), or @(ERn.L,PC)]  Memory indirect [@@aa:8]  Extended memory indirect [@@vec:7]

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• Two base registers  Vector base register  Short address base register
• 4-Gbyte address space  Program: 4 Gbytes  Data: 4 Gbytes
• High-speed operation  All frequently-used instructions executed in one or two states  8/16/32-bit register-register add/subtract: 1 state  8 × 8-bit register-register multiply: 1 state  16 ÷ 8-bit register-register divide: 10 states  16 × 16-bit register-register multiply: 1 state  32 ÷ 16-bit register-register divide: 18 states  32 × 32-bit register-register multiply: 5 states  32 ÷ 32-bit register-register divide: 18 states
• Four CPU operating modes  Normal mode  Middle mode  Advanced mode  Maximum mode
• Power-down modes  Transition is made by execution of SLEEP instruction  Choice of CPU operating clocks Notes: 1. Advanced mode is only supported as the CPU operating mode of the H8SX/1648 Group, the H8SX/1648A Group, the H8SX/1648L Group, the H8SX/1648G Group, and the H8SX/1648H Group. Normal, middle, and maximum modes are not supported. 2. The multiplier and divider are supported by the H8SX/1648 Group, the H8SX/1648A Group, the H8SX/1648L Group, the H8SX/1648G Group, and the H8SX/1648H Group.

Rev. 2.00 Jul. 31, 2008 Page 35 of 1438 REJ09B0365-0200

2.2 CPU Operating Modes

The H8SX CPU has four operating modes: normal, middle, advanced and maximum modes. These modes can be selected by the mode pins of this LSI. CPU operating modes Normal mode Maximum mode Maximum 64 kbytes for program and data areas combined Maximum 4 Gbytes for program and data areas combined Maximum 16-Mbyte program area and 64-kbyte data area, maximum 16 Mbytes for program and data areas combined Maximum 16-Mbyte program area and 4-Gbyte data area, maximum 4 Gbytes for program and data areas combined Advanced mode Middle mode Figure 2.1 CPU Operating Modes

2.2.1 Normal Mode

The exception vector table and stack have the same structure as in the H8/300 CPU.

• Address Space The maximum address space of 64 kbytes can be accessed.
• Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When the extended register En is used as a 16-bit register it can contain any value, even when the corresponding general register Rn is used as an address register. (If the general register Rn is referenced in the register indirect addressing mode with pre-/post-increment or pre-/post-decrement and a carry or borrow occurs, however, the value in the corresponding extended register En will be affected.)
• Instruction Set All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid.

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2.2.2 Middle Mode

The program area in middle mode is extended to 16 Mbytes as compared with that in normal mode.

• Address Space The maximum address space of 16 Mbytes can be accessed as a total of the program and data areas. For individual areas, up to 16 Mbytes of the program area or up to 64 kbytes of the data area can be allocated.
• Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When the extended register En is used as a 16-bit register (in other than the JMP and JSR instructions), it can contain any value even when the corresponding general register Rn is used as an address register. (If the general register Rn is referenced in the register indirect addressing mode with pre-/post-increment or pre-/post- decrement and a carry or borrow occurs, however, the value in the corresponding extended register En will be affected.)
• Instruction Set All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid and the upper eight bits are sign-extended.
• Exception Vector Table and Memory Indirect Branch Addresses In middle mode, the top area starting at H'000000 is allocated to the exception vector table. One branch address is stored per 32 bits. The upper eight bits are ignored and the lower 24 bits are stored. The structure of the exception vector table is shown in figure 2.4. The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction code specifies a memory location. Execution branches to the contents of the memory location. In middle mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch address. The upper eight bits are reserved and assumed to be H'00.
• Stack Structure The stack structure of PC at a subroutine branch and that of PC and CCR at an exception handling are shown in figure 2.5. The PC contents are saved or restored in 24-bit units.

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2.2.3 Advanced Mode

The data area is extended to 4 Gbytes as compared with that in middle mode.

• Address Space The maximum address space of 4 Gbytes can be linearly accessed. For individual areas, up to 16 Mbytes of the program area and up to 4 Gbytes of the data area can be allocated.
• Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers.
• Instruction Set All instructions and addressing modes can be used.
• Exception Vector Table and Memory Indirect Branch Addresses In advanced mode, the top area starting at H'00000000 is allocated to the exception vector table. One branch address is stored per 32 bits. The upper eight bits are ignored and the lower 24 bits are stored. The structure of the exception vector table is shown in figure 2.4. H'00000000 H'00000003 H'00000004 Exception vector table Reserved Reset exception vector Reserved H'00000007 H'00000001 H'00000002 H'00000005 H'00000006 Figure 2.4 Exception Vector Table (Middle and Advanced Modes) The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction code specifies a memory location. Execution branches to the contents of the memory location. In advanced mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch address. The upper eight bits are reserved and assumed to be H'00.

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• Stack Structure The stack structure of PC at a subroutine branch and that of PC and CCR at an exception handling are shown in figure 2.5. The PC contents are saved or restored in 24-bit units. (a) Subroutine Branch (b) Exception Handling PC (24 bits) EXR*1 Reserved*1, *3 CCR PC (24 bits) SP SP Notes: 1. When EXR is not used it is not stored on the stack. SP when EXR is not used. Ignored on return. (SP ) *2Reserved Figure 2.5 Stack Structure (Middle and Advanced Modes)

2.2.4 Maximum Mode

The program area is extended to 4 Gbytes as compared with that in advanced mode.

• Address Space The maximum address space of 4 Gbytes can be linearly accessed.
• Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers or as the upper 16-bit segments of 32-bit registers or address registers.
• Instruction Set All instructions and addressing modes can be used.
• Exception Vector Table and Memory Indirect Branch Addresses In maximum mode, the top area starting at H'00000000 is allocated to the exception vector table. One branch address is stored per 32 bits. The structure of the exception vector table is shown in figure 2.6.

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2.3 Instruction Fetch

The H8SX CPU has two modes for instruction fetch: 16-bit and 32-bit modes. It is recommended that the mode be set according to the bus width of the memory in which a program is stored. The instruction-fetch mode setting does not affect operation other than instruction fetch such as data accesses. Whether an instruction is fetched in 16- or 32-bit mode is selected by the FETCHMD bit in SYSCR. For details, see section 3.2.2, System Control Register (SYSCR).

2.4 Address Space

Figure 2.8 shows a memory map of the H8SX CPU. The address space differs depending on the CPU operating mode. H'0000 H'000000 H'007FFF H'FF8000 H'FFFFFF H'00000000 H'00FFFFFF H'FFFFFFFF H'00000000 H'FFFFFFFF H'FFFF Normal mode Program area Data area (64 kbytes) Program area Data area (4 Gbytes) Program area (16 Mbytes) Program area (16 Mbytes)Data area (64 kbytes) Data area (4 Gbytes) Middle mode Advanced mode Maximum mode Figure 2.8 Memory Map

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2.5 Registers

The H8SX CPU has the internal registers shown in figure 2.9. There are two types of registers: general registers and control registers. The control registers are the 32-bit program counter (PC), 8-bit extended control register (EXR), 8-bit condition-code register (CCR), 32-bit vector base register (VBR), 32-bit short address base register (SBR), and 64-bit multiply-accumulate register (MAC). T ———— I2 I1 I0EXR 76543210 31 0 15 0 7 0 7 0 R0H R1H R2H R3H R4H R5H R6H R7H R0L R1L R2L R3L R4L R5L R6L R7L General Registers and Extended Registers Control Registers [Legend] Stack pointer Program counter Condition-code register Interrupt mask bit User bit or interrupt mask bit Half-carry flag SP: PC: CCR: UI: User bit Negative flag Zero flag Overflow flag Carry flag Extended control register EXR: ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) I UI HUNZVCCCR 7654321 0 Sign extension 63 3241 031 MAC PC (Reserved) 31 012 VBR (Reserved) 31 08 SBR MACL Trace bit Interrupt mask bits Vector base register Short address base register Multiply-accumulate register I2 to I0: VBR: SBR: MAC: MACH Figure 2.9 CPU Registers

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2.5.1 General Registers

The H8SX CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.10 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). When the general registers are used as 16-bit registers, the ER registers are divided into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. When the general registers are used as 8-bit registers, the R registers are divided into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. The general registers ER (ER0 to ER7), R (R0 to R7), and RL (R0L to R7L) are also used as index registers. The size in the operand field determines which register is selected. The usage of each register can be selected independently. Address registers 32-bit registers 32-bit index registers 16-bit registers General registers E (E0 to E7) 8-bit registers General registers RH (R0H to R7H) 16-bit registers 16-bit index registers General registers R (R0 to R7) 8-bit registers 8-bit index registers General registers RL (R0L to R7L) General registers ER (ER0 to ER7) Figure 2.10 Usage of General Registers

Rev. 2.00 Jul. 31, 2008 Page 44 of 1438 REJ09B0365-0200 General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine branches. Figure 2.11 shows the stack. Free area Stack area SP (ER7) Figure 2.11 Stack

2.5.2 Program Counter (PC)

PC is a 32-bit counter that indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 16 bits (one word) or a multiple of 16 bits, so the least significant bit is ignored. (When the instruction code is fetched, the least significant bit is regarded as 0.

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2.5.3 Condition-Code Register (CCR)

CCR is an 8-bit register that contains internal CPU status information, including an interrupt mask (I) and user (UI, U) bits and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branch conditions for conditional branch (Bcc) instructions. Bit Bit Name Initial Value R/W Description

7 I 1 R/W Interrupt Mask Bit

Masks interrupts when set to 1. This bit is set to 1 at the start of an exception handling.

6 UI Undefined R/W User Bit

Can be written to and read from by software using the LDC, STC, ANDC, ORC, and XORC instructions.

5 H Undefined R/W Half-Carry Flag

or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise.

4 U Undefined R/W User Bit

Can be written to and read from by software using the LDC, STC, ANDC, ORC, and XORC instructions.

3 N Undefined R/W Negative Flag

Stores the value of the most significant bit (regarded as sign bit) of data.

Rev. 2.00 Jul. 31, 2008 Page 46 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description

2 Z Undefined R/W Zero Flag

Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.

1 V Undefined R/W Overflow Flag

Set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise.

0 C Undefined R/W Carry Flag

Set to 1 when a carry occurs, and cleared to 0 otherwise. A carry has the following types:  Carry from the result of addition  Borrow from the result of subtraction  Carry from the result of shift or rotation The carry flag is also used as a bit accumulator by bit manipulation instructions.

2.5.4 Extended Control Register (EXR)

EXR is an 8-bit register that contains the trace bit (T) and three interrupt mask bits (I2 to I0). Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC instructions. For details, see section 6, Exception Handling. Bit Bit Name Initial Value R/W Description

7 T 0 R/W Trace Bit

When this bit is set to 1, a trace exception is generated each time an instruction is executed. When this bit is cleared to 0, instructions are executed in sequence. 6 to 3 — All 1 R/W Reserved These bits are always read as 1. R/W R/W R/W Interrupt Mask Bits These bits designate the interrupt mask level (0 to 7).

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2.5.5 Vector Base Register (VBR)

VBR is a 32-bit register in which the upper 20 bits are valid. The lower 12 bits of this register are read as 0s. This register is a base address of the vector area for exception handlings other than a reset and a CPU address error (extended memory indirect is also out of the target). The initial value is H'00000000. The VBR contents are changed with the LDC and STC instructions.

2.5.6 Short Address Base Register (SBR)

SBR is a 32-bit register in which the upper 24 bits are valid. The lower eight bits are read as 0s. In 8-bit absolute address addressing mode (@aa:8), this register is used as the upper address. The initial value is H'FFFFFF00. The SBR contents are changed with the LDC and STC instructions.

2.5.7 Multiply-Accumulate Register (MAC)

MAC is a 64-bit register that stores the results of multiply-and-accumulate operations. It consists of two 32-bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the upper bits are sign extended. The MAC contents are changed with the MAC, CLRMAC, LDMAC, and STMAC instructions.

2.5.8 Initial Values of CPU Registers

Reset exception handling loads the start address from the vector table into the PC, clears the T bit in EXR to 0, and sets the I bits in CCR and EXR to 1. The general registers, MAC, and the other bits in CCR are not initialized. In particular, the initial value of the stack pointer (ER7) is undefined. The SP should therefore be initialized using an MOV.L instruction executed immediately after a reset.

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2.6 Data Formats

The H8SX CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.

2.6.1 General Register Data Formats

Figure 2.12 shows the data formats in general registers. 7 6 5 4 3 2 1 0 Don't care 7 0 Don't care 7 6 5 4 3 2 1 0 4370 Don’t careUpper Lower LSB MSB LSB 1-bit data 1-bit data 4-bit BCD data 4-bit BCD data Byte data Byte data Word data Word data Longword data RnH RnL RnH RnL RnH RnL Rn En ERn MSB Don't care Upper Lower 437 0 Don't care 7 0 Don't care General register ER General register E General register R General register RH [Legend] ERn: En: Rn: RnH: MSB LSB LSB 1516 MSB En Rn MSB LSB RnL: MSB: LSB: General register RL Most significant bit Least significant bit Figure 2.12 General Register Data Formats

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2.6.2 Memory Data Formats

Figure 2.13 shows the data formats in memory. The H8SX CPU can access word data and longword data which are stored at any addresses in memory. When word data begins at an odd address or longword data begins at an address other than a multiple of 4, a bus cycle is divided into two or more accesses. For example, when longword data begins at an odd address, the bus cycle is divided into byte, word, and byte accesses. In this case, these accesses are assumed to be individual bus cycles. However, instructions to be fetched, word and longword data to be accessed during execution of the stack manipulation, branch table manipulation, block transfer instructions, and MAC instruction should be located to even addresses. When SP (ER7) is used as an address register to access the stack, the operand size should be word size or longword size. 76543210 MSB LSB MSB LSB MSB LSB Data Type Data Format 1-bit data Byte data Word data Longword data Address Address L Address L Address 2M Address 2M + 1 Address 2N Address 2N + 1 Address 2N + 2 Address 2N + 3 Figure 2.13 Memory Data Formats

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2.7 Instruction Set

The H8SX CPU has 87 types of instructions. The instructions are classified by function as shown in table 2.1. The arithmetic operation, logic operation, shift, and bit manipulation instructions are called operation instruction in this manual. Table 2.1 Instruction Classification Function Instructions Size Types Data transfer MOV B/W/L 6 MOVFPE, MOVTPE B POP, PUSH * W/L LDM, STM L MOVA B/W * Block transfer EEPMOV B 3 MOVMD B/W/L MOVSD B Arithmetic operations ADD, ADDX, SUB, SUBX, CMP, NEG, INC, DEC B/W/L 27 DAA, DAS B ADDS, SUBS L MULXU, DIVXU, MULXS, DIVXS B/W MULU, DIVU, MULS, DIVS W/L MULU/U * , MULS/U* L EXTU, EXTS W/L TAS B MAC * LDMAC * , STMAC* CLRMAC * Logic operations AND, OR, XOR, NOT B/W/L 4 Shift SHLL, SHLR, SHAL, SHAR, RO TL, ROTR, ROTXL, ROTXR B/W/L 8 Bit manipulation BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST B 20 BSET/EQ, BSET/NE, BCLR/EQ, BCLR/NE, BSTZ, BISTZ B BFLD, BFST B

Rev. 2.00 Jul. 31, 2008 Page 51 of 1438 REJ09B0365-0200 Function Instructions Size Types Branch BRA/BS, BRA/BC, BSR/BS, BSR/BC B * Bcc * , JMP, BSR, JSR, RTS — RTS/L L * BRA/S — System control TRAPA, RTE, SLEEP, NOP — 10 RTE/L L * LDC, STC, ANDC, ORC, XORC B/W/L Total 87 [Legend] B: Byte size W: Word size L: Longword size @−SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP +, ERn and MOV.L ERn, @−SP. 2. Size of data to be added with a displacement 3. Size of data to specify a branch condition 4. Bcc is the generic designation of a conditional branch instruction. 5. Size of general register to be restored 6. Only when the multiplier is available.

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2.7.1 Instructions and Addressing Modes

Table 2.2 indicates the combinations of instructions and addressing modes that the H8SX CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes (1) Addressing Mode Classifi- cation Instruction Size #xx Rn @ERn @(d,ERn) @(d, RnL.B/ Rn.W/ ERn.L) @ −ERn/ @ERn +/ @ERn −/ @ +ERn @aa:8 @aa:16/ @aa:32 — Data transfer MOV B/W/L S SD SD SD SD SD SD B S/D S/D MOVFPE, MOVTPE B S/D S/D * POP, PUSH W/L S/D S/D * LDM, STM L S/D S/D * MOVA * B/W S S S S S S EEPMOV B SD * Block transfer MOVMD B/W/L SD * MOVSD B SD * ADD, CMP B S D D D D D D D B S D D D D D D B D S S S S S S B SD SD SD SD SD W/L S SD SD SD SD SD SD Arithmetic operations SUB B S D D D D D D B S D D D D D D B D S S S S S S B SD SD SD SD SD W/L S SD SD SD SD SD SD ADDX, SUBX B/W/L S SD B/W/L S SD B/W/L S SD * INC, DEC B/W/L D ADDS, SUBS L D DAA, DAS B D MULXU, DIVXU B/W S:4 SD MULU, DIVU W/L S:4 SD

Rev. 2.00 Jul. 31, 2008 Page 53 of 1438 REJ09B0365-0200 Addressing Mode Classifi- cation Instruction Size #xx Rn @ERn @(d,ERn) @(d, RnL.B/ Rn.W/ ERn.L) @ −ERn/ @ERn +/ @ERn −/ @ +ERn @aa:8 @aa:16/ @aa:32 — Arithmetic operations MULXS, DIVXS B/W S:4 SD MULS, DIVS W/L S:4 SD NEG B D D D D D D D W/L D D D D D D EXTU, EXTS W/L D D D D D D TAS B D MAC * CLRMAC * — O LDMAC * — S STMAC * — D AND, OR, XOR B S D D D D D D B D S S S S S S B SD SD SD SD SD W/L S SD SD SD SD SD SD Logic operations NOT B D D D D D D D W/L D D D D D D Shift SHLL, SHLR B D D D D D D D W/L * D D D D D D B/W/L * D B D D D D D D D SHAL, SHAR ROTL, ROTR ROTXL, ROTXR W/L D D D D D D Bit manipu- lation BSET, BCLR, BNOT, BTST, BSET/cc, BCLR/cc B D D D D BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST, BSTZ, BISTZ B D D D D

Rev. 2.00 Jul. 31, 2008 Page 54 of 1438 REJ09B0365-0200 Addressing Mode Classifi- cation Instruction Size #xx Rn @ERn @(d,ERn) @(d, RnL.B/ Rn.W/ ERn.L) @ −ERn/ @ERn +/ @ERn −/ @ +ERn @aa:8 @aa:16/ @aa:32 — BFLD B D S S S Bit manipu- lation BFST B S D D D Branch BRA/BS, BRA/BC * B S S S BSR/BS, BSR/BC * B S S S LDC (CCR, EXR) B/W* S S S S S * S LDC (VBR, SBR) L S STC (CCR, EXR) B/W* D D D D * D System control STC (VBR, SBR) L D ANDC, ORC, XORC B S SLEEP — O NOP — O [Legend] d: d:16 or d:32 S: Can be specified as a source operand. D: Can be specified as a destination operand. SD: Can be specified as either a s ource or destination operand or both. S/D: Can be specified as either a source or destination operand. S:4: 4-bit immediate data can be specified as a source operand. Notes: 1. Only @aa:16 is available. 2. @ERn + as a source operand and @−ERn as a destination operand 3. Specified by ER5 as a source addre ss and ER6 as a destination address for data transfer. 4. Size of data to be added with a displacement 5. Only @ERn − is available 6. When the number of bits to be shifted is 1, 2, 4, 8, or 16 7. When the number of bits to be shifted is specified by 5-bit immediate data or a general register 8. Size of data to specify a branch condition 9. Byte when immediate or r egister direct, otherwise, word 10. Only @ERn + is available 11. Only @ −ERn is available 12. Not available in this LSI.

Rev. 2.00 Jul. 31, 2008 Page 55 of 1438 REJ09B0365-0200 Table 2.2 Combinations of Instructions and Addressing Modes (2) Addressing Mode Classifi- cation Instruction Size @ERn @(d,PC) @(RnL. B/Rn.W/ ERn.L, PC) @aa:24 aa:32 @@ aa:8 @@vec: 7 — Branch BRA/BS, BRA/BC — O BSR/BS, BSR/BC — O Bcc — O BRA — O O BRA/S — O * JMP — O O O O O BSR — O JSR — O O O O O RTS, RTS/L — O TRAPA — O System control RTE, RTE/L — O [Legend] d: d:8 or d:16 Note: * Only @(d:8, PC) is available.

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2.7.2 Table of Instructions Classified by Function

Tables 2.4 to 2.11 summarize the instructions in each functional category. The notation used in these tables is defined in table 2.3. Table 2.3 Operation Notation Operation Notation Description Rd General register (destination) * Rs General register (source) * Rn General register * ERn General register (32-bit register) (EAd) Destination operand (EAs) Source operand EXR Extended control register CCR Condition-code register VBR Vector base register SBR Short address base register N N (negative) flag in CCR Z Z (zero) flag in CCR V V (overflow) flag in CCR C C (carry) flag in CCR PC Program counter SP Stack pointer #IMM Immediate data disp Displacement + Addition − Subtraction × Multiplication ÷ Division ∧ Logical AND ∨ Logical OR ⊕ Logical exclusive OR → Move ∼ Logical not (logical complement) Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7).

Rev. 2.00 Jul. 31, 2008 Page 57 of 1438 REJ09B0365-0200 Table 2.4 Data Transfer Instructions Instruction Size Function MOV B/W/L #IMM → (EAd), (EAs) → (EAd) Transfers data between immediate data, general registers, and memory. MOVFPE B (EAs) → Rd MOVTPE B Rs → (EAs) POP W/L @SP + → Rn Restores the data from the stack to a general register. PUSH W/L Rn → @−SP Saves general register contents on the stack. LDM L @SP + → Rn (register list) Restores the data from the stack to multiple general registers. Two, three, or four general registers which have serial register numbers can be specified. STM L Rn (register list) → @−SP Saves the contents of multiple general registers on the stack. Two, three, or four general registers which have serial register numbers can be specified. MOVA B/W EA → Rd Zero-extends and shifts the contents of a specified general register or memory data and adds them with a displacement. The result is stored in a general register.

Rev. 2.00 Jul. 31, 2008 Page 58 of 1438 REJ09B0365-0200 Table 2.5 Block Transfer Instructions Instruction Size Function EEPMOV.B EEPMOV.W B Transfers a data block. Transfers byte data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of byte data to be transferred is specified by R4 or R4L. MOVMD.B B Transfers a data block. Transfers byte data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of byte data to be transferred is specified by R4. MOVMD.W W Transfers a data block. Transfers word data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of word data to be transferred is specified by R4. MOVMD.L L Transfers a data block. Transfers longword data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of longword data to be transferred is specified by R4. MOVSD.B B Transfers a data block with zero data detection. Transfers byte data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of byte data to be transferred is specified by R4. When zero data is detected during transfer, the transfer stops and execution branches to a specified address.

Rev. 2.00 Jul. 31, 2008 Page 59 of 1438 REJ09B0365-0200 Table 2.6 Arithmetic Operation Instructions Instruction Size Function ADD SUB B/W/L (EAd) ± #IMM → (EAd), (EAd) ± (EAs) → (EAd) Performs addition or subtraction on data between immediate data, general registers, and memory. Immediate byte data cannot be subtracted from byte data in a general register. ADDX SUBX B/W/L (EAd) ± #IMM ± C → (EAd), (EAd) ± (EAs) ± C → (EAd) Performs addition or subtraction with carry on data between immediate data, general registers, and memory. The addressing mode which specifies a memory location can be specified as register indirect with post-decrement or register indirect. INC DEC B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) ADDS SUBS L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd Adds or subtracts the value 1, 2, or 4 to or from data in a general register. DAA DAS B Rd (decimal adjust) → Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 2-digit 4-bit BCD data. MULXU B/W Rd × Rs → Rd Performs unsigned multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits, or 16 bits × 16 bits → 32 bits. MULU W/L Rd × Rs → Rd Performs unsigned multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits, or 16 bits × 16 bits → 32 bits. MULU/U* L Rd × Rs → Rd Performs unsigned multiplication on data in two general registers (32 bits × 32 bits → upper 32 bits). MULXS B/W Rd × Rs → Rd Performs signed multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits, or 16 bits × 16 bits → 32 bits. MULS W/L Rd × Rs → Rd Performs signed multiplication on data in two general registers: either 16 bits × 16 bits → 16 bits, or 32 bits × 32 bits → 32 bits. MULS/U* L Rd × Rs → Rd Performs signed multiplication on data in two general registers (32 bits × 32 bits → upper 32 bits). DIVXU B/W Rd ÷ Rs → Rd Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder, or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder.

Rev. 2.00 Jul. 31, 2008 Page 60 of 1438 REJ09B0365-0200 Instruction Size Function DIVU W/L Rd ÷ Rs → Rd Performs unsigned division on data in two general registers: either 16 bits ÷ 16 bits → 16-bit quotient, or 32 bits ÷ 32 bits → 32-bit quotient. DIVXS B/W Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder, or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. DIVS W/L Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 16 bits → 16-bit quotient, or 32 bits ÷ 32 bits → 32-bit quotient. CMP B/W/L (EAd) − #IMM, (EAd) − (EAs) Compares data between immediate data, general registers, and memory and stores the result in CCR. NEG B/W/L 0 − (EAd) → (EAd) Takes the two's complement (arithmetic complement) of data in a general register or the contents of a memory location. EXTU W/L (EAd) (zero extension) → (EAd) Performs zero-extension on the lower 8 or 16 bits of data in a general register or memory to word or longword size. The lower 8 bits to word or longword, or the lower 16 bits to longword can be zero-extended. EXTS W/L (EAd) (sign extension) → (EAd) Performs sign-extension on the lower 8 or 16 bits of data in a general register or memory to word or longword size. The lower 8 bits to word or longword, or the lower 16 bits to longword can be sign-extended. TAS B @ERd − 0, 1 → (<bit 7> of @EAd) Tests memory contents, and sets the most significant bit (bit 7) to 1. MAC* — (EAs) × (EAd) + MAC → MAC Performs signed multiplication on memory contents and adds the result to MAC. CLRMAC* — 0 → MAC Clears MAC to zero. LDMAC* — Rs → MAC Loads data from a general register to MAC. STMAC* — MAC → Rd Stores data from MAC to a general register. Note: * When supporting multiplier only

Rev. 2.00 Jul. 31, 2008 Page 61 of 1438 REJ09B0365-0200 Table 2.7 Logic Operation Instructions Instruction Size Function AND B/W/L (EAd) ∧ #IMM → (EAd), (EAd) ∧ (EAs) → (EAd) Performs a logical AND operation on data between immediate data, general registers, and memory. OR B/W/L (EAd) ∨ #IMM → (EAd), (EAd) ∨ (EAs) → (EAd) Performs a logical OR operation on data between immediate data, general registers, and memory. XOR B/W/L (EAd) ⊕ #IMM → (EAd), (EAd) ⊕ (EAs) → (EAd) Performs a logical exclusive OR operation on data between immediate data, general registers, and memory. NOT B/W/L ∼ (EAd) → (EAd) Takes the one's complement of the contents of a general register or a memory location. Table 2.8 Shift Operation Instructions Instruction Size Function SHLL SHLR B/W/L (EAd) (shift) → (EAd) Performs a logical shift on the contents of a general register or a memory location. The contents of a general register or a memory location can be shifted by 1, 2, 4, 8, or 16 bits. The contents of a general register can be shifted by any bits. In this case, the number of bits is specified by 5-bit immediate data or the lower 5 bits of the contents of a general register. SHAL SHAR B/W/L (EAd) (shift) → (EAd) Performs an arithmetic shift on the contents of a general register or a memory location. 1-bit or 2-bit shift is possible. ROTL ROTR B/W/L (EAd) (rotate) → (EAd) Rotates the contents of a general register or a memory location. 1-bit or 2-bit rotation is possible. ROTXL ROTXR B/W/L (EAd) (rotate) → (EAd) Rotates the contents of a general register or a memory location with the carry bit. 1-bit or 2-bit rotation is possible.

Rev. 2.00 Jul. 31, 2008 Page 62 of 1438 REJ09B0365-0200 Table 2.9 Bit Manipulation Instructions Instruction Size Function BSET B 1 → (<bit-No.> of <EAd>) Sets a specified bit in the contents of a general register or a memory location to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BSET/cc B if cc, 1 → (<bit-No.> of <EAd>) If the specified condition is satisfied, this instruction sets a specified bit in a memory location to 1. The bit number can be specified by 3-bit immediate data, or by the lower three bits of a general register. The Z flag status can be specified as a condition. BCLR B 0 → (<bit-No.> of <EAd>) Clears a specified bit in the contents of a general register or a memory location to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR/cc B if cc, 0 → (<bit-No.> of <EAd>) If the specified condition is satisfied, this instruction clears a specified bit in a memory location to 0. The bit number can be specified by 3-bit immediate data, or by the lower three bits of a general register. The Z flag status can be specified as a condition. BNOT B ∼ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>) Inverts a specified bit in the contents of a general register or a memory location. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BTST B ∼ (<bit-No.> of <EAd>) → Z Tests a specified bit in the contents of a general register or a memory location and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BAND B C ∧ (<bit-No.> of <EAd>) → C ANDs the carry flag with a specified bit in the contents of a general register or a memory location and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BIAND B C ∧ [∼ (<bit-No.> of <EAd>)] → C ANDs the carry flag with the inverse of a specified bit in the contents of a general register or a memory location and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BOR B C ∨ (<bit-No.> of <EAd>) → C ORs the carry flag with a specified bit in the contents of a general register or a memory location and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.

Rev. 2.00 Jul. 31, 2008 Page 63 of 1438 REJ09B0365-0200 Instruction Size Function BIOR B C ∨ [~ (<bit-No.> of <EAd>)] → C ORs the carry flag with the inverse of a specified bit in the contents of a general register or a memory location and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BXOR B C ⊕ (<bit-No.> of <EAd>) → C Exclusive-ORs the carry flag with a specified bit in the contents of a general register or a memory location and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BIXOR B C ⊕ [~ (<bit-No.> of <EAd>)] → C Exclusive-ORs the carry flag with the inverse of a specified bit in the contents of a general register or a memory location and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BLD B (<bit-No.> of <EAd>) → C Transfers a specified bit in the contents of a general register or a memory location to the carry flag. The bit number is specified by 3-bit immediate data. BILD B ~ (<bit-No.> of <EAd>) → C Transfers the inverse of a specified bit in the contents of a general register or a memory location to the carry flag. The bit number is specified by 3-bit immediate data. BST B C → (<bit-No.> of <EAd>) Transfers the carry flag value to a specified bit in the contents of a general register or a memory location. The bit number is specified by 3-bit immediate data. BSTZ B Z → (<bit-No.> of <EAd>) Transfers the zero flag value to a specified bit in the contents of a memory location. The bit number is specified by 3-bit immediate data. BIST B ∼ C → (<bit-No.> of <EAd>) Transfers the inverse of the carry flag value to a specified bit in the contents of a general register or a memory location. The bit number is specified by 3-bit immediate data.

Rev. 2.00 Jul. 31, 2008 Page 64 of 1438 REJ09B0365-0200 Instruction Size Function BISTZ B ∼ Z → (<bit-No.> of <EAd>) Transfers the inverse of the zero flag value to a specified bit in the contents of a memory location. The bit number is specified by 3-bit immediate data. BFLD B (EAs) (bit field) → Rd Transfers a specified bit field in memory location contents to the lower bits of a specified general register. BFST B Rs → (EAd) (bit field) Transfers the lower bits of a specified general register to a specified bit field in memory location contents. Table 2.10 Branch Instructions Instruction Size Function BRA/BS BRA/BC B Tests a specified bit in memory location contents. If the specified condition is satisfied, execution branches to a specified address. BSR/BS BSR/BC B Tests a specified bit in memory location contents. If the specified condition is satisfied, execution branches to a subroutine at a specified address. Bcc — Branches to a specified address if the specified condition is satisfied. BRA/S — Branches unconditionally to a s pecified address after executing the next instruction. The next instruction should be a 1-word instruction except for the block transfer and branch instructions. JMP — Branches unconditionally to a specified address. BSR — Branches to a subroutine at a specified address. JSR — Branches to a subroutine at a specified address. RTS — Returns from a subroutine. RTS/L — Returns from a subroutine, restor ing data from the stack to multiple general registers.

Rev. 2.00 Jul. 31, 2008 Page 65 of 1438 REJ09B0365-0200 Table 2.11 System Control Instructions Instruction Size Function TRAPA — Starts trap-instruct ion exception handling. RTE — Returns from an exception-handling routine. RTE/L — Returns from an exception-handli ng routine, restoring data from the stack to multiple general registers. SLEEP — Causes a transition to a power-down state. B/W #IMM → CCR, (EAs) → CCR, #IMM → EXR, (EAs) → EXR Loads immediate data or the contents of a general register or a memory location to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. LDC L Rs → VBR, Rs → SBR Transfers the general register contents to VBR or SBR. B/W CCR → (EAd), EXR → (EAd) Transfers the contents of CCR or EXR to a general register or memory. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. STC L VBR → Rd, SBR → Rd Transfers the contents of VBR or SBR to a general register. ANDC B CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR Logically ANDs the CCR or EXR contents with immediate data. ORC B CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR Logically ORs the CCR or EXR contents with immediate data. XORC B CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR Logically exclusive-ORs the CCR or EXR contents with immediate data. NOP — PC + 2 → PC Only increments the program counter.

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2.7.3 Basic Instruction Formats

The H8SX CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.14 shows examples of instruction formats. op op rn rm NOP, RTS, etc. ADD.B Rn, Rm, etc. MOV.B @(d:16, Rn), Rm, etc. (1) Operation field only (2) Operation field and register fields (3) Operation field, register fields, and effective address extension rn rmop EA (disp) (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc Figure 2.14 Instruction Formats

• Operation Field Indicates the function of the instruction, and specifies the addressing mode and operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields.
• Register Field Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field.
• Effective Address Extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.
• Condition Field Specifies the branch condition of Bcc instructions.

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2.8 Addressing Modes and Effective Address Calculation

The H8SX CPU supports the 11 addressing modes listed in table 2.12. Each instruction uses a subset of these addressing modes. Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.12 Addressing Modes No. Addressing Mode Symbol

1 Register direct Rn

2 Register indirect @ERn

3 Register indirect with displacement @(d:2,ERn)/@(d:16,ERn)/@(d:32,ERn)

4 Index register indirect with displacement @(d:16, RnL.B)/@(d: 16,Rn.W)/@(d:16,ERn.L) @(d:32, RnL.B)/@(d:32,Rn.W)/@(d:32,ERn.L)

5 Register indirect with post-increment @ERn +

Register indirect with pre-decrement @ −ERn Register indirect with pre-increment @ +ERn Register indirect with post-decrement @ERn −

6 Absolute address @aa:8/@aa:16/@aa:24/@aa:32

7 Immediate #xx:3/#xx: 4/#xx:8/#xx:16/#xx:32

8 Program-counter relati ve @(d:8,PC)/@(d:16,PC)

9 Program-counter relative with index regi ster @(RnL.B,PC)/@(Rn.W,PC)/@(ERn.L,PC)

10 Memory indirect @@aa:8

11 Extended memory indirect @@vec:7

2.8.1 Register Direct—Rn

The operand value is the contents of an 8-, 16-, or 32-bit general register which is specified by the register field in the instruction code. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.

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2.8.2 Register Indirect—@ERn

The operand value is the contents of the memory location which is pointed to by the contents of an address register (ERn). ERn is specified by the register field of the instruction code. In advanced mode, if this addressing mode is used in a branch instruction, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00).

2.8.3 Register Indirect with Displacement —@(d:2, ERn), @(d:16, ERn),

or @(d:32, ERn) The operand value is the contents of a memory location which is pointed to by the sum of the contents of an address register (ERn) and a 16- or 32-bit displacement. ERn is specified by the register field of the instruction code. The displacement is included in the instruction code and the 16-bit displacement is sign-extended when added to ERn. This addressing mode has a short format (@(d:2, ERn)). The short format can be used when the displacement is 1, 2, or 3 and the operand is byte data, when the displacement is 2, 4, or 6 and the operand is word data, or when the displacement is 4, 8, or 12 and the operand is longword data. 2.8.4 Index Register Indirect with Displacement—@(d:16,RnL.B), @(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L) The operand value is the contents of a memory location which is pointed to by the sum of the following operation result and a 16- or 32-bit displacement: a specified bits of the contents of an address register (RnL, Rn, ERn) specified by the register field in the instruction code are zero- extended to 32-bit data and multiplied by 1, 2, or 4. The displacement is included in the instruction code and the 16-bit displacement is sign-extended when added to ERn. If the operand is byte data, ERn is multiplied by 1. If the operand is word or longword data, ERn is multiplied by 2 or 4, respectively.

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2.8.5 Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment,

or Post-Decrement—@ERn +, @−ERn, @ +ERn, or @ERn −

• Register indirect with post-increment—@ERn + The operand value is the contents of a memory location which is pointed to by the contents of an address register (ERn). ERn is specified by the register field of the instruction code. After the memory location is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access.
• Register indirect with pre-decrement—@ −ERn The operand value is the contents of a memory location which is pointed to by the following operation result: the value 1, 2, or 4 is subtracted from the contents of an address register (ERn). ERn is specified by the register field of the instruction code. After that, the operand value is stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for longword access.
• Register indirect with pre-increment—@ +ERn The operand value is the contents of a memory location which is pointed to by the following operation result: the value 1, 2, or 4 is added to the contents of an address register (ERn). ERn is specified by the register field of the instruction code. After that, the operand value is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access.
• Register indirect with post-decrement—@ERn − The operand value is the contents of a memory location which is pointed to by the contents of an address register (ERn). ERn is specified by the register field of the instruction code. After the memory location is accessed, 1, 2, or 4 is subtracted from the address register contents and the remainder is stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. Using this addressing mode, data to be written is the contents of the general register after calculating an effective address. If the same general register is specified in an instruction and two effective addresses are calculated, the contents of the general register after the first calculation of an effective address is used in the second calculation of an effective address. Example 1: MOV.W R0, @ER0 + When ER0 before execution is H'12345678, H'567A is written at H'12345678.

Rev. 2.00 Jul. 31, 2008 Page 70 of 1438 REJ09B0365-0200 Example 2: MOV.B @ER0+, @ER0+ When ER0 before execution is H'00001000, H'00001000 is read and the contents is written at H'00001001. After execution, ER0 is H'00001002.

2.8.6 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32

The operand value is the contents of a memory location which is pointed to by an absolute address included in the instruction code. There are 8-bit (@aa:8), 16-bit (@aa:16), 24-bit (@aa:24), and 32-bit (@aa:32) absolute addresses. To access the data area, the absolute address of 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) is used. For an 8-bit absolute address, the upper 24 bits are specified by SBR. For a 16- bit absolute address, the upper 16 bits are sign-extended. A 32-bit absolute address can access the entire address space. To access the program area, the absolute address of 24 bits (@aa:24) or 32 bits (@aa:32) is used. For a 24-bit absolute address, the upper 8 bits are all assumed to be 0 (H'00). Table 2.13 shows the accessible absolute address ranges. Table 2.13 Absolute Address Access Ranges Absolute Address Normal Mode Middle Mode Advanced Mode Maximum Mode Data area 8 bits (@aa:8) A consecutive 256-byte area (the upper address is set in SBR) 16 bits (@aa:16) H'0000 to H'FFFF H'00000000 to H'00007FFF, H'FFFF8000 to H'FFFFFFFF 32 bits (@aa:32) H'000000 to H'007FFF, H'FF8000 to H'FFFFFF H'00000000 to H'FFFFFFFF Program area 24 bits (@aa:24) H'000000 to H'FFFFFF H'00000000 to H'00FFFFFF 32 bits (@aa:32) H'00000000 to H'00FFFFFF H'00000000 to H'FFFFFFFF

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2.8.7 Immediate—#xx

The operand value is 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) data included in the instruction code. This addressing mode has short formats in which 3- or 4-bit immediate data can be used. When the size of immediate data is less than that of the destination operand value (byte, word, or longword) the immediate data is zero-extended. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, for specifying a bit number. The BFLD and BFST instructions contain 8-bit immediate data in the instruction code, for specifying a bit field. The TRAPA instruction contains 2-bit immediate data in the instruction code, for specifying a vector address.

2.8.8 Program-Counter Relative—@(d:8, PC) or @(d:16, PC)

This mode is used in the Bcc and BSR instructions. The operand value is a 32-bit branch address, which is the sum of an 8- or 16-bit displacement in the instruction code and the 32-bit address of the PC contents. The 8-bit or 16-bit displacement is sign-extended to 32 bits when added to the PC contents. The PC contents to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is −126 to +128 bytes (−63 to +64 words) or −32766 to +32768 bytes (−16383 to +16384 words) from the branch instruction. The resulting value should be an even number. In advanced mode, only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). 2.8.9 Program-Counter Relative with Index Register—@(RnL.B, PC), @(Rn.W, PC), or @(ERn.L, PC) This mode is used in the Bcc and BSR instructions. The operand value is a 32-bit branch address, which is the sum of the following operation result and the 32-bit address of the PC contents: the contents of an address register specified by the register field in the instruction code (RnL, Rn, or ERn) is zero-extended and multiplied by 2. The PC contents to which the displacement is added is the address of the first byte of the next instruction. In advanced mode, only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00).

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2.8.10 Memory Indirect—@@aa:8

This mode can be used by the JMP and JSR instructions. The operand value is a branch address, which is the contents of a memory location pointed to by an 8-bit absolute address in the instruction code. The upper bits of an 8-bit absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in other modes). In normal mode, the memory location is pointed to by word-size data and the branch address is 16 bits long. In other modes, the memory location is pointed to by longword-size data. In middle or advanced mode, the first byte of the longword-size data is assumed to be all 0 (H'00). Note that the top part of the address range is also used as the exception handling vector area. A vector address of an exception handling other than a reset or a CPU address error can be changed by VBR. Figure 2.15 shows an example of specification of a branch address using this addressing mode. (a) Normal Mode (b) Advanced Mode Branch addressSpecified by @aa:8 Specified by @aa:8 Reserved Branch address Figure 2.15 Branch Address Specification in Memory Indirect Mode

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2.8.11 Extended Memo ry Indirect—@@vec:7

This mode can be used by the JMP and JSR instructions. The operand value is a branch address, which is the contents of a memory location pointed to by the following operation result: the sum of 7-bit data in the instruction code and the value of H'80 is multiplied by 2 or 4. The address range to store a branch address is H'0100 to H'01FF in normal mode and H'000200 to H'0003FF in other modes. In assembler notation, an address to store a branch address is specified. In normal mode, the memory location is pointed to by word-size data and the branch address is 16 bits long. In other modes, the memory location is pointed to by longword-size data. In middle or advanced mode, the first byte of the longword-size data is assumed to be all 0 (H'00).

2.8.12 Effective Address Calculation

Tables 2.14 and 2.15 show how effective addresses are calculated in each addressing mode. The lower bits of the effective address are valid and the upper bits are ignored (zero extended or sign extended) according to the CPU operating mode. The valid bits in middle mode are as follows:

• The lower 16 bits of the effective address are valid and the upper 16 bits are sign-extended for the transfer and operation instructions.
• The lower 24 bits of the effective address are valid and the upper eight bits are zero-extended for the branch instructions.

Rev. 2.00 Jul. 31, 2008 Page 74 of 1438 REJ09B0365-0200 Table 2.14 Effective Address Calculation for Transfer and Operation Instructions 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 15 31 15 31 0 31 0 31 15 0 31 0 1, 2, or 4 31 0 31 0 1, 2, or 4 1, 2, or 4 31 0 7 No. op op rm rn IMM op r op disp disp disp disp aa aa aa disp r op disp r op aa op disp r op disp r op aa op r op r op aa 31 0 1, 2, or 4 Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Immediate Register direct Register indirect Register indirect with 16-bit displacement Register indirect with 32-bit displacement Index register indirect with 16-bit displacement Index register indirect with 32-bit displacement Register indirect with post-increment or post-decrement Register indirect with pre-increment or pre-decrement 8-bit absolute address 16-bit absolute address 32-bit absolute address Sign extension SBR General register contents General register contents Zero extension Contents of general register (RL, R, or ER) Zero extension Contents of general register (RL, R, or ER) Sign extension General register contents General register contents General register contents Sign extension

Rev. 2.00 Jul. 31, 2008 Page 75 of 1438 REJ09B0365-0200 Table 2.15 Effective Address Calculation for Branch Instructions 31 0 31 0 31 0 31 0 31 23 0 31 0 31 0 2 or 4 vec op disp op disp op r op aa op r op aa aa aa op aa aa 31 0 31 0 op vec 31 0 31 0 31 0 31 0 31 7 0 disp 31 0 31 0 31 15 0 disp 31 0 31 0 No. Register indirect Program-counter relative with 8-bit displacement 24-bit absolute address 32-bit absolute address Zero extension Contents of general register (RL, R, or ER) General register contents Sign extension Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) PC contents Sign extension PC contents Zero extension Zero extension Memory contents Memory contents Zero extension PC contents Program-counter relative with 16-bit displacement Program-counter relative with index register Memory indirect Extended memory indirect

2.8.13 MOVA Instruction

The MOVA instruction stores the effective address in a general register. 1. Firstly, data is obtained by the addressing mode shown in item 2 of table 2.14. 2. Next, the effective address is calculated using the obtained data as the index by the addressing mode shown in item 5 of table 2.14. The obtained data is used instead of the general register. The result is stored in a general register. For details, see H8SX Family Software Manual.

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2.9 Processing States

The H8SX CPU has five main processing states: the reset state, exception-handling state, program execution state, bus-released state, and program stop state. Figure 2.16 indicates the state transitions.

• Reset state In this state the CPU and internal peripheral modules are all initialized and stopped. When the RES input goes low, all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. For details, see section 6, Exception Handling. The reset state can also be entered by a watchdog timer overflow when available.
• Exception-handling state The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to activation of an exception source, such as, a reset, trace, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception handling vector table and branches to that address. For further details, see section 6, Exception Handling.
• Program execution state In this state the CPU executes program instructions in sequence.
• Bus-released state The bus-released state occurs when the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts operations.
• Program stop state This is a power-down state in which the CPU stops operating. The program stop state occurs when a SLEEP instruction is executed or the CPU enters hardware standby mode. For details, see section 27, Power-Down Modes. Note: * A transition to the reset state occurs whenever the RES signal goes low. A transition can also be made to the reset state when the watchdog timer overflows. Reset state* Exception-handling state Request for exception handling End of exception handling Program execution state Bus-released state Bus request End of bus request Program stop state SLEEP instruction Interrupt request Bus request End of bus request RES = high RES = low Figure 2.16 State Transitions

Section 3 MCU Operating Modes Rev. 2.00 Jul. 31, 2008 Page 77 of 1438 REJ09B0365-0200 Section 3 MCU Operating Modes

3.1 Operating Mode Selection

This LSI has seven operating modes (modes 1, 2, 3, 4, 5, 6, and 7). The operating mode is selected by the setting of mode pins MD2 to MD0. Enabling and disabling of the SDRAM interface can be selected with the MD3 setting for each operating mode. Table 3.1 lists MCU operating mode settings. Table 3.2 shows the SDRAM interface* setting for each MCU operating mode Table 3.1 MCU Operating Mode Settings External Data Bus Width MCU Operating Mode MD2 MD1 MD0 CPU Operating Mode Address Space LSI Initiation Mode On-Chip ROM Default Max. 1 0 0 1 User boot mode Enabled  16 bits 2 0 1 0 Boot mode Enabled  16 bits 3 0 1 1 Boundary scan enabled single-chip mode Enabled  16 bits 4 1 0 0 Disabled 16 bits 16 bits 5 1 0 1 On-chip ROM disabled extended mode Disabled 8 bits 16 bits 6 1 1 0 On-chip ROM enabled extended mode Enabled 8 bits 16 bits 7 1 1 1 Advanced mode

16 Mbytes

Single-chip mode Enabled  16 bits Table 3.2 SDRAM Interface Setting for each MCU Operating Mode MD3 SDRAM Interface

0 Disabled

1 Enabled

In this LSI, an advanced mode as the CPU operating mode and a 16-Mbyte address space are available. The initial external bus widths are eight or 16 bits. As the LSI initiation mode, the external extended mode, on-chip ROM initiation mode, or single-chip initiation mode can be selected. Modes 1 and 2 are the user boot mode and the boot mode, respectively, in which the flash memory can be programmed and erased. For details on the user boot mode and boot mode, see section 24, Flash Memory.

Section 3 MCU Operating Modes Rev. 2.00 Jul. 31, 2008 Page 78 of 1438 REJ09B0365-0200 Mode 3 is the boundary scan function enabled single-chip mode. For details on the boundary scan function, see section 25, Boundary Scan. Mode 7 is a single-chip initiation mode. All I/O ports can be used as general input/output ports. The external address space cannot be accessed in the initial state, but setting the EXPE bit in the system control register (SYSCR) to 1 enables to use the external address space. After the external address space is enabled, ports D, E, and F can be used as an address output bus and ports H and I as a data bus by specifying the data direction register (DDR) for each port. When the external address space is not in use, ports J and K can be used by setting the PCJKE bit in the port function control register D (PFCRD) to 1. Modes 4 to 6 are external extended modes, in which the external memory and devices can be accessed. In the external extended modes, the external address space can be designated as 8-bit or 16-bit address space for each area by the bus controller after starting program execution. If 16-bit address space is designated for any one area, it is called the 16-bit bus widths mode. If 8- bit address space is designated for all areas, it is called the 8-bit bus width mode. Note: * Supported only by the H8SX/1648G Group and H8SX/1648H Group.

Section 3 MCU Operating Modes Rev. 2.00 Jul. 31, 2008 Page 79 of 1438 REJ09B0365-0200

3.2 Register Descriptions

The following registers are related to the operating mode setting.

• Mode control register (MDCR)
• System control register (SYSCR)

3.2.1 Mode Control Register (MDCR)

MDCR indicates the current operating mode. When MDCR is read from, the states of signals MD3 to MD0 are latched. Latching is released by a reset. Bit Bit Name Initial Value R/W Notes: 1. Determined by the settings of pins MD2 to MD0 2. Determined by the setting of MD3 pin. 3. Supported only by the H8SX/1648G Group and H8SX/1648H Group. MDS3* 0/Undefined*2*3 R R R R MDS3 Undefined*1 R MDS2 Undefined*1 R MDS1 Undefined*1 R MDS0 Undefined*1 R Bit Bit Name Initial Value R/W 0/Undefined* 2*3 R R R R Undefined*1 R Undefined*1 R Undefined*1 R Undefined*1 R Bit Bit Name Initial Value R/W Descriptions  0 R • H8SX/1648, H8SX/1648A, H8SX/1648L Group: Reserved These are read-only bits and cannot be modified. MDS7* Undefined * R • H8SX/1648G, H8SX/1648H Group: This pin indicates a value set with the mode pin (MD3) When MDCR is read, the signal levels input on the MD3 pin is latched into this bit. This latch is released by a reset.

Section 3 MCU Operating Modes Rev. 2.00 Jul. 31, 2008 Page 80 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Descriptions R R R Reserved These are read-only bits and cannot be modified. MDS3 MDS2 MDS1 MDS0 Undefined* Undefined* Undefined* Undefined* R R R R Mode Select 3 to 0 These bits indicate the operating mode selected by the mode pins (MD2 to MD0) (see table 3.3). When MDCR is read, the signal levels input on pins MD2 to MD0 are latched into these bits. These latches are released by a reset. 0/Undefined* Undefined* Undefined* Undefined* Undefined* R R R R R R R R Reserved These are read-only bits and cannot be modified. Notes: 1. Determined by the settings of pins MD2 to MD0 2. Determined by the setting of MD3 pin. 3. Supported only by the H8SX/1 648G Group and the H8SX/1648H Group. Table 3.3 Settings of Bits MDS3 to MDS0 Mode Pins MDCR MCU Operating Mode MD2 MD1 MD0 MDS3 MDS2 MDS1 MDS0 1 0 0 1 1 1 0 1 2 0 1 0 1 1 0 0 3 0 1 1 0 1 0 0 4 1 0 0 0 0 1 0 5 1 0 1 0 0 0 1 6 1 1 0 0 1 0 1 7 1 1 1 0 1 0 0

Section 3 MCU Operating Modes Rev. 2.00 Jul. 31, 2008 Page 81 of 1438 REJ09B0365-0200

3.2.2 System Control Register (SYSCR)

SYSCR controls MAC saturation operation, selects bus width mode for instruction fetch, sets external bus mode, enables/disables the on-chip RAM, and selects the DTC address mode. Bit Bit Name Initial Value R/W Note: * The initial value depends on the startup mode. R/W R/W MACS R/W R/W FETCHMD R/W Undefined* R EXPE Undefined* R/W RAME R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W DTCMD R/W R/W Bit Bit Name Initial Value R/W Descriptions R/W R/W Reserved These bits are always read as 1. The write value should always be 1.

13 MACS 0 R/W MAC Saturation Operation Control

Selects either saturation operation or non-saturation operation for the MAC instruction. 0: MAC instruction is non-saturation operation 1: MAC instruction is saturation operation 12  1 R/W Reserved This bit is always read as 1. The write value should always be 1.

11 FETCHMD 0 R/W Instruction Fetch Mode Select

This LSI can prefetch an instruction in units of 16 bits or 32 bits. Select the bus width for instruction fetch depending on the used memory for the storage of programs. 0: 32-bit mode 1: 16-bit mode

Section 3 MCU Operating Modes Rev. 2.00 Jul. 31, 2008 Page 82 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Descriptions 10  Undefined* R Reserved This bit is fixed at 1 in on-chip ROM enabled mode, and 0 in on-chip ROM disabled mode. This bit cannot be changed.

9 EXPE Undefined*

R/W External Bus Mode Enable Selects external bus mode. In external extended mode, this bit is fixed 1 and cannot be changed. In single-chip mode, the initial value of this bit is 0, and can be read from or written to when PCKJE = 0. Do not write to this bit when PCKJE = 1* When writing 0 to this bit after reading EXPE = 1, an external bus cycle should not be executed. The external bus cycle may be carried out in parallel with the internal bus cycle depending on the setting of the write data buffer function, refresh control function and EXDMAC bus right release state and others. 0: External bus disabled 1: External bus enabled

8 RAME 1 R/W RAM Enable

Enables or disables the on-chip RAM. This bit is initialized when the reset state is released. Do not write 0 during access to the on-chip RAM. 0: On-chip RAM disabled 1: On-chip RAM enabled 7 to 2  All 0 R/W Reserved These bits are always read as 0. The write value should always be 0.

1 DTCMD 1 R/W DTC Mode Select

Selects DTC operating mode. 0: DTC is in full-address mode 1: DTC is in short address mode 0  1 R/W Reserved This bit is always read as 1. The write value should always be 1. Notes: 1. The initial value dep ends on the LSI initiation mode. 2. For details on the settings of the EXPE and PCJKE bits when the external address space is in use, see section 13.3.12, Port Function Control Register D (PFCRD).

Section 3 MCU Operating Modes Rev. 2.00 Jul. 31, 2008 Page 83 of 1438 REJ09B0365-0200

3.3 Operating Mode Descriptions

3.3.1 Mode 1

This is the user boot mode for the flash memory. The LSI operates in the same way as in mode 7 except for programming and erasing of the flash memory. For details, see section 24, Flash Memory.

3.3.2 Mode 2

This is the boot mode for the flash memory. The LSI operates in the same way as in mode 7 except for programming and erasing of the flash memory. For details, see section 24, Flash Memory.

3.3.3 Mode 3

This is the boundary scan function enabled single-chip activation mode. The operation is the same as mode 7 except for the boundary scan function. For details on the boundary scan function, see section 25, Boundary Scan.

3.3.4 Mode 4

The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the on- chip ROM is disabled. The initial bus width mode immediately after a reset is 16 bits, with 16-bit access to all areas. Ports D, E, and F function as an address bus, ports H and I function as a data bus, and parts of ports A and B function as bus control signals. However, if all areas are designated as an 8-bit access space by the bus controller, the bus mode switches to eight bits, and only port H functions as a data bus.

Section 3 MCU Operating Modes Rev. 2.00 Jul. 31, 2008 Page 84 of 1438 REJ09B0365-0200

3.3.5 Mode 5

The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the on- chip ROM is disabled. The initial bus width mode immediately after a reset is eight bits, with 8-bit access to all areas. Ports D, E, and F function as an address bus, port H functions as a data bus, and parts of ports A and B function as bus control signals. However, if any area is designated as a 16-bit access space by the bus controller, the bus width mode switches to 16 bits, and ports H and I function as a data bus.

3.3.6 Mode 6

The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the on- chip ROM is enabled. The initial bus width mode immediately after a reset is eight bits, with 8-bit access to all areas. Ports D, E, and F function as input ports, but they can be used as an address bus by specifying the data direction register (DDR) for each port. For details, see section 13, I/O Ports. Port H functions as a data bus, and parts of ports A and B function as bus control signals. However, if any area is designated as a 16-bit access space by the bus controller, the bus width mode switches to 16 bits, and ports H and I function as a data bus.

3.3.7 Mode 7

The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the on- chip ROM is enabled. All I/O ports can be used as general input/output ports. The external address space cannot be accessed in the initial state, but setting the EXPE bit in the system control register (SYSCR) to 1 enables the external address space. After the external address space is enabled, ports D, E, and F can be used as an address output bus and ports H and I as a data bus by specifying the data direction register (DDR) for each port. When the external address space is not in use, ports J and K can be used by setting the PCJKE bit in the port function control register D (PFCRD) to 1. For details, see section 13, I/O Ports.

Section 3 MCU Operating Modes Rev. 2.00 Jul. 31, 2008 Page 85 of 1438 REJ09B0365-0200

3.3.8 Pin Functions

Table 3.4 shows the pin functions in each operating mode. Table 3.4 Pin Functions in Each Operating Mode (Advanced Mode) Port A Port B Port C Port F MCU Operating Mode PA7 PA6-3 PA2-0 PB7-1 PB0 PC1-0 PC3-2 Port D Port E PF4-0 PF7-5 Port H Port I

1 P */C P */C P */C P */C P */C P */C P */C*

P */A P */A P */A P */A P */D P */D

2 P */C P */C P */C P */C P */C P */C P */C*

P */A P */A P */A P */A P */D P */D

3 P */C P */C P */C P */C P */C P */C P */C*

P */A P */A P */A P */A P */D P */D

4 P/C * P/C * P */C P */C P/C * P */C P */C*

A A A P */A D P/D *

5 P/C * P/C * P */C P */C P/C * P */C P */C*

A A A P */A D P */D

6 P/C * P/C * P */C P */C P */C P */C P */C*

P */A P */A P */A P */A D P */D

7 P */C P */C P */C P */C P */C P */C P */C*

P */A P */A P */A P */A P */D P */D [Legend] P: I/O port A: Address bus output D: Data bus input/output C: Control signals, clock input/output *: Immediately after a reset Note: 1. Supported only by the H8SX/ 1648G Group and the H8SX/1648H Group.

3.4 Address Map

3.4.1 Address Map

Figures 3.1 to 3.3 show the address map in each operating mode.

Section 3 MCU Operating Modes Rev. 2.00 Jul. 31, 2008 Page 86 of 1438 REJ09B0365-0200 Modes 1 and 2 User boot mode, boot mode (Advanced mode) External address space/ reserved area*1*3 External address space/ reserved area*1*3 External address space/ reserved area*1*3 External address space/ reserved area*1*3 Access prohibited area On-chip ROM On-chip RAM*2 On-chip I/O registers On-chip I/O registers H'000000 H'100000 H'FEE000 H'FFC000 H'FD9000 H'FDC000 H'FFEA00 H'FFFF00 H'FFFF20 H'FFFFFF Reserved area*3H'FEC000 Modes 3 and 7 Boundary scan enabled single-chip mode, single-chip mode (Advanced mode) External address space/ reserved area*1*3 External address space/ reserved area*1*3 External address space/ reserved area*1*3 External address space/ reserved area*1*3 Access prohibited area On-chip ROM On-chip RAM/ External address space*4 On-chip I/O registers On-chip I/O registers H'000000 H'100000 H'FEE000 H'FFC000 H'FD9000 H'FDC000 H'FFEA00 H'FFFF00 H'FFFF20 H'FFFFFF Reserved area*3H'FEC000 H'FEE000 H'FFC000 H'FD9000 H'FDC000 H'FFEA00 H'FFFF00 H'FFFF20 H'FFFFFF H'FEC000 External address space External address space External address space External address space Access prohibited area On-chip RAM/ External address space*4 On-chip I/O registers On-chip I/O registers Reserved area*3 Modes 4 and 5 On-chip ROM disabled extended mode (Advanced mode) H'000000 This area is specified as the external address space when EXPE = 1 and the reserved area when EXPE = 0. The on-chip RAM is used for flash memory programming. Do not clear the RAME bit in SYSCR to 0. Do not access the reserved areas. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0. Notes: Figure 3.1 Address Map in Each Operating Mode of H8SX/1648, 1648A, 1648L, 1648G, and 1648H (1)

Section 3 MCU Operating Modes Rev. 2.00 Jul. 31, 2008 Page 87 of 1438 REJ09B0365-0200 External address space On-chip ROM Mode 6 On-chip ROM enabled extended mode (Advanced mode) External address space External address space Access prohibited area On-chip RAM/ External address space*2 On-chip I/O registers On-chip I/O registers Reserved area*1 H'000000 H'100000 H'FEE000 H'FD9000 H'FDC000 H'FFEA00 H'FFFF00 H'FFFF20 H'FFFFFF H'FEC000 External address space H'FFC000 Do not access the reserved area. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0. Notes: Figure 3.1 Address Map in Each Operating Mode of H8SX/1648, 1648A, 1648L, 1648G, and 1648H (2)

Section 3 MCU Operating Modes Rev. 2.00 Jul. 31, 2008 Page 88 of 1438 REJ09B0365-0200 External address space/ reserved area*1*3 External address space/ reserved area*1*3 External address space/ reserved area*1*3 External address space/ reserved area*1*3 Access prohibited area On-chip ROM On-chip RAM*2 On-chip I/O registers On-chip I/O registers H'000000 H'080000 H'FF2000 H'FFC000 H'FD9000 H'FDC000 H'FFEA00 H'FFFF00 H'FFFF20 H'FFFFFF Reserved area*3 H'FEC000 External address space/ reserved area*1*3 External address space/ reserved area*1*3 External address space/ reserved area*1*3 External address space/ reserved area*1*3 Access prohibited area Access prohibited area Access prohibited area On-chip ROM On-chip I/O registers On-chip I/O registers H'100000 H'000000 H'080000 H'FF2000 H'FFC000 H'FD9000 H'FDC000 H'FFEA00 H'FFFF00 H'FFFF20 H'FFFFFF H'FEC000 H'100000 External address space External address space External address space External address space Access prohibited area Reserved area*3 Reserved area*3 On-chip RAM/ External address space*4 On-chip RAM/ External address space*4 On-chip I/O registers On-chip I/O registers H'000000 H'FF2000 H'FFC000 H'FD9000 H'FDC000 H'FEC000 H'FFEA00 H'FFFF00 H'FFFF20 H'FFFFFF This area is specified as the external address space when EXPE = 1 and the reserved area when EXPE = 0. The on-chip RAM is used for flash memory programming. Do not clear the RAME bit in SYSCR to 0. Do not access the reserved areas. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0. Notes: Modes 1 and 2 User boot mode, boot mode (Advanced mode) Modes 3 and 7 Boundary scan enabled single-chip mode, single-chip mode (Advanced mode) Modes 4 and 5 On-chip ROM disabled extended mode (Advanced mode) Figure 3.2 Address Map in Each Operating Mode of H8SX/1644, 1644A, 1644L, 1644G, and 1644H (1)

Section 3 MCU Operating Modes Rev. 2.00 Jul. 31, 2008 Page 89 of 1438 REJ09B0365-0200 MOde 6 On-chip ROM enabled extended mode (Advanced mode) External address space External address space External address space External address space Access prohibited area On-chip ROM On-chip RAM/ External address space*2 On-chip I/O registers On-chip I/O registers H'000000 H'080000 H'FF2000 H'FFC000 H'FD9000 H'FDC000 H'FFEA00 H'FFFF00 H'FFFF20 H'FFFFFF Reserved area*1 H'FEC000 Access prohibited area H'100000 Do not access the reserved area. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0. Notes: Figure 3.2 Address Map in Each Operating Mode of H8SX/1644, 1644A, 1644L, 1644G, and 1644H (2)

Section 3 MCU Operating Modes Rev. 2.00 Jul. 31, 2008 Page 90 of 1438 REJ09B0365-0200 External address space/ reserved area*1*3 External address space/ reserved area*1*3 External address space/ reserved area*1*3 External address space/ reserved area*1*3 Access prohibited area On-chip ROM On-chip RAM*2 On-chip I/O registers On-chip I/O registers H'000000 H'060000 H'FF6000 H'FFC000 H'FD9000 H'FDC000 H'FFEA00 H'FFFF00 H'FFFF20 H'FFFFFF Reserved area*3 H'FEC000 External address space/ reserved area*1*3 External address space/ reserved area*1*3 External address space/ reserved area*1*3 External address space/ reserved area*1*3 Access prohibited area Access prohibited area Access prohibited area On-chip ROM On-chip I/O registers On-chip I/O registers H'100000 H'000000 H'060000 H'FF6000 H'FFC000 H'FD9000 H'FDC000 H'FFEA00 H'FFFF00 H'FFFF20 H'FFFFFF H'FEC000 H'100000 External address space External address space External address space External address space Access prohibited area Reserved area*3 Reserved area*3 On-chip RAM/ External address space*4 On-chip RAM/ External address space*4 On-chip I/O registers On-chip I/O registers H'000000 H'FF6000 H'FFC000 H'FD9000 H'FDC000 H'FEC000 H'FFEA00 H'FFFF00 H'FFFF20 H'FFFFFF This area is specified as the external address space when EXPE = 1 and the reserved area when EXPE = 0. The on-chip RAM is used for flash memory programming. Do not clear the RAME bit in SYSCR to 0. Do not access the reserved areas. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0. Notes: Modes 1 and 2 User boot mode, boot mode (Advanced mode) Modes 3 and 7 Boundary scan enabled single-chip mode, single-chip mode (Advanced mode) Modes 4 and 5 On-chip ROM disabled extended mode (Advanced mode) Figure 3.3 Address Map in Each Operating Mode of H8SX/1642, 1642A, 1642L, 1642G, and 1642H (1)

Section 3 MCU Operating Modes Rev. 2.00 Jul. 31, 2008 Page 91 of 1438 REJ09B0365-0200 MOde 6 On-chip ROM enabled extended mode (Advanced mode) External address space External address space External address space External address space Access prohibited area On-chip ROM On-chip RAM/ External address space*2 On-chip I/O registers On-chip I/O registers H'000000 H'060000 H'FF6000 H'FFC000 H'FD9000 H'FDC000 H'FFEA00 H'FFFF00 H'FFFF20 H'FFFFFF Reserved area*1 H'FEC000 Access prohibited area H'100000 Do not access the reserved area. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0. Notes: Figure 3.3 Address Map in Each Operating Mode of H8SX/1642, 1642A, 1642L, 1642G, and 1642H (2)

Section 3 MCU Operating Modes Rev. 2.00 Jul. 31, 2008 Page 92 of 1438 REJ09B0365-0200

Rev. 2.00 Jul. 31, 2008 Page 93 of 1438 REJ09B0365-0200 Section 4 Reset

4.1 Types of Reset

There are three types of reset: a pin reset, power-on reset*, voltage-monitoring reset*, deep software standby reset, and watchdog timer reset. Table 4.1 shows the reset names and sources. The internal state and pins are initialized by a reset. Figure 4.1 shows the reset targets to be initialized. When using power-on reset* and voltage monitoring reset*, RES pin must be fixed high. Table 4.1 Reset Names And Sources Reset Name Source Pin reset Voltage input to the RES pin is driven low. Power-on reset* Vcc rises or lowers Voltage-monitoring reset* Vcc falls (voltage-detection: Vdet) Deep software standby reset Deep software standby mode is canceled by an interrupt. Watchdog timer reset The watchdog timer overflows. Note: * Supported only by the H8SX/1648 L Group and the H8SX/1648H Group.

Rev. 2.00 Jul. 31, 2008 Page 94 of 1438 REJ09B0365-0200 Vcc RES Power-on rest circuit registers* (RSTSR.PORF) RSTSR.LVDF LVDCR.LVDE LVDRI RSTSR.DPSRSTF DPSBYCR, DPSWCR DPSIER, DPSIFR DPSIEGR, DPSBKRn RSTCR for WDT Pin reset Power-on reset Voltage-monitoring reset Deep software standby reset Watchdog timer reset Registers for voltage-monitoring* Registers related to power-down mode Internal state other than above, and pin states. Power-on reset circuit* Deep software standby reset generation circuit Watchdog timer Voltage detection circuit* Note: * Supported only by the H8SX/1648LGroup and H8SX/1648H Group. Figure 4.1 Block Diagram of Reset Circuit

Rev. 2.00 Jul. 31, 2008 Page 95 of 1438 REJ09B0365-0200 Note that some registers are not initialized by any of the reset. The following describes the CPU internal registers. The PC, one of the CPU internal registers, is initialized by loading the start address from vector addresses with the reset exception handling. At this time, the T bit in EXR is cleared to 0 and the I bits in EXR and CCR are set to 1. The general registers, MAC, and other bits in CCR are not initialized. The initial value of the SP (ER7) is undefined. The SP should be initialized using the MOV.L instruction immediately after a reset. For details, see section 2, CPU. For other registers that are not initialized by a reset, see register descriptions in each section. When a reset is canceled, the reset exception handling is started. For the reset exception handling, see section 6.3, Reset.

4.2 Input/Output Pin

Table 4.2 shows the pin related to reset. Table 4.2 Pin Configuration Pin Name Symbol I/O Function Reset RES Input Reset input

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4.3 Register Descriptions

This LSI has the following registers for reset.

• Reset status register (RSTSR)
• Reset control/status register (RSTCSR)

4.3.1 Reset Status Register (RSTSR)

RSTSR indicates a source for generating an internal reset and voltage monitoring interrupt. Bit Bit name Initial value: R/W: DPSRSTF R/(W)*1 R/W R/W R/W R/W LVDF*2 0*3 R/W*4 0*3 R/W PORF*2 0*3 R/W*5 Note: 1. Only 0 can be written to clear the flag. 2. Supported only by the H8SX/1648LGroup and H8SX/1648H Group. 3. Initial value is undefined in the H8SX/1648L Group and H8SX/1648H Group. 4. Only 0 can be written to clear the flag in the H8SX/1648L Group and H8SX/1648H Group. 5. Only read is possible in the H8SX/1648L Group and H8SX/1648H Group. Bit Bit Name Initial Value R/W Description

7 DPSRSTF 0 R/(W) *

Deep Software Standby Reset Flag Indicates that deep software standby mode is canceled by an interrupt source specified with DPSIER or DPSIEGR and an internal reset is generated. [Setting condition] When deep software standby mode is canceled by an interrupt source. [Clearing conditions]

• When this bit is read as 1 and then written by 0.
• When a pin reset, power-on reset* and voltage- monitoring reset* is generated. 6 to 3  All 0 R/W Reserved These bits are always read as 0. The write value should always be 0.

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• H8SX/1648 Group, H8SX/1648A Group, H8SX/1648G Group 2 to 0  All 0 R/W Reserved These bits are always read as 0. The write value should always be 0.
• H8SX/1648L Group, H8SX/1648H Group

2 LVDF Undefined R/(W) *

This bit indicates that the voltage detection circuit has detected a low voltage (Vcc at or below Vdet). [Setting condition] Vcc falling to or below Vdet. [Clearing condition]

• After Vcc has exceeded Vdet and the specified stabilization period has elapsed, writing 0 to the bit after reading it as 1.
• Generation of a pin reset or power-on reset. 1 — Undefined R/W Reserved The write value should always be 0.

0 PORF Undefined R Power-on Reset Flag

This bit indicates that a power-on reset has been generated. [Setting condition] Generation of a power-on reset [Clearing condition] Generation of a pin reset Note: 1. Only 0 can be written to clear the flag. 2. Supported only by the H8 SX/1648L Group and H8SX/1648H Group.

Rev. 2.00 Jul. 31, 2008 Page 98 of 1438 REJ09B0365-0200

4.3.2 Reset Control/Status Register (RSTCSR)

RSTCSR controls an internal reset signal generated by the watchdog timer and selects the internal reset signal type. RSTCSR is initialized to H’1F by a pin reset or a deep software standby reset, but not by the internal reset signal generated by a WDT overflow. Bit Bit name Initial value: R/W: WOVF R/(W)* RSTE R/W R/W R R R R R Note: * Only 0 can be written to clear the flag. Bit Bit Name Initial Value R/W Description

7 WOVF 0 R/(W) * Watchdog Timer Overflow Flag

This bit is set when TCNT overflows in watchdog timer mode, but not set in interval timer mode. Only 0 can be written to. [Setting condition] When TCNT overflows (H’FF → H’00) in watchdog timer mode. [Clearing condition] When this bit is read as 1 and then written by 0. (The flag must be read after writing of 0, when this bit is cleared by the CPU using an interrupt.)

6 RSTE 0 R/W Reset Enable

Selects whether or not the LSI internal state is reset by a TCNT overflow in watchdog timer mode. 0: Internal state is not reset when TCNT overflows. (Although this LSI internal state is not reset, TCNT and TCSR of the WDT are reset.) 1: Internal state is reset when TCNT overflows. 5  0 R/W Reserved Although this bit is readable/writable, operation is not affected by this bit. 4 to 0  1 R Reserved These are read-only bits but cannot be modified. Note: * Only 0 can be written to clear the flag.

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4.4 Pin Reset

This is a reset generated by the RES pin. When the RES pin is driven low, all the processing in progress is aborted and the LSI enters a reset state. In order to firmly reset the LSI, the STBY pin should be set to high and the RES pin should be held low at least for 20 ms at a power-on. During operation, the RES pin should be held low at least for 20 states.

4.5 Power-on Reset (POR) (H8SX/1648L Group and H8SX/1648H

Group) This is an internal reset generated by the power-on reset circuit. If RES is in the high-level state when power is supplied, a power-on reset is generated. After Vcc has exceeded Vpor and the specified period (power-on reset time) has elapsed, the chip is released from the power-on reset state. The power-on reset time is a period for stabilization of the external power supply and the LSI circuit. If RES is at the high-level when the power-supply voltage (Vcc) falls to or below Vpor, a power- on reset is generated. The chip is released after Vcc has risen above Vpor and the power-on reset time has elapsed. After a power-on reset has been generated, the PORF bit in RSTSR is set to 1. The PORF bit is in a read-only register and is only initialized by a pin reset. Figure 4.2 shows the operation of a power-on reset.

Rev. 2.00 Jul. 31, 2008 Page 100 of 1438 REJ09B0365-0200 V V V Vpor*1 External power supply Vcc Vcc Vcc Vcc Vcc RES pin POR signal ("L" is valid) Reset signal ("L" is valid) Pin reset and OR signal for POR PORF Reset state Reset state tPOR*2 tPOR*2 Set Set Notes: For details of the electrical characteristics, see section 29, Electrical Characteristics. 1. V POR shows a level of power-on reset detection level. 2. T POR shows a time for power-on reset. Figure 4.2 Operation of a Power on Reset

4.6 Power Supply Monitoring Reset (H8SX1648L Group, H8SX1648H

Group) This is an internal reset generated by the power-supply detection circuit. When Vcc falls below Vdet in the state where the LVDE bit in LVDCR has been set to 1 and the LVDR1 bit has been cleared to 0, a voltage-monitoring reset is generated. When Vcc subsequently rises above Vdet, release from the voltage-monitoring reset proceeds after a specified time has elapsed. For details of the voltage-monitoring reset, see section 5, Voltage Detection Circuit (LVD), and section 29, Electrical Characteristics.

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4.7 Deep Software Standby Reset

This is an internal reset generated when deep software standby mode is canceled by an interrupt. When deep software standby mode is canceled, a deep software standby reset is generated, and simultaneously, clock oscillation starts. After the time specified with DPSWCR has elapsed, the deep software standby reset is canceled. For details of the deep software standby reset, see section 27, Power-Down Modes.

4.8 Watchdog Timer Reset

This is an internal reset generated by the watchdog timer. When the RSTE bit in RSTCSR is set to 1, a watchdog timer reset is generated by a TCNT overflow. After a certain time, the watchdog timer reset is canceled. For details of the watchdog timer reset, see section 18, Watchdog Timer (WDT).

4.9 Determination of Reset Generation Source

Reading RSTCSR, RSTSR, and LVDCR* of the voltage detection circuit determines which reset was used to execute the reset exception handling. Figure 4.2 shows an example the flow to identify a reset generation source. Note: * Supported only by the H8SX/1648L Group and H8SX/1648H Group.

Rev. 2.00 Jul. 31, 2008 Page 102 of 1438 REJ09B0365-0200 No Pin reset No No Yes LVDCR.LVDE=1 & LVDCR.LCDRI=0 & RSTSR.LVDF=1 Yes RSTSR. PORF=1 Power-on reset* Reset exception handling RSTCSR.RSTE=1 and RSTCSR.WOVF=1 No Yes Yes RSTSR. DPSRSTF=1 Deep software standby reset Watchdog timer reset Voltage monitoring reset* Note: * Supported only by the H8SX/1648LGroup and H8SX/1648H Group. Figure 4.3 Example of Reset Generation Source Determination Flow

Section 5 Voltage Detection Circuit (LVD) Rev. 2.00 Jul. 31, 2008 Page 103 of 1438 REJ09B0365-0200 Section 5 Voltage Detection Circuit (LVD) The voltage detection circuit (LVD) is only supported by the H8SX/1648L Group and the H8SX/1648H Group. This circuit is used to monitor Vcc. The LVD is capable of internally resetting the LSI when Vcc falls and crosses the voltage detection level. An interrupt can also be generated.

5.1 Features

• Voltage-detection circuit Capable of detecting the power-supply voltage (Vcc) becoming less than or equal to Vdet. Capable of generating an internal reset or interrupt when a low voltage is detected. A block diagram of the voltage detection circuit is shown in figure 5.1. Vcc LVDF LVDE LVDRI LVDMONOn-chip reference voltage (for sensing Vdet) [Legend] LVDE: LVD enable LVDRI: LVD reset / interrupt select LVDMON: LVD monitor LVDF: LVD flag Power-supply stabilization time generation circuit Reset / interrupt control circuit Voltage-monitoring reset Voltage-monitoring interrupt Figure 5.1 Block Diagram of Voltage-Detection Circuit

Section 5 Voltage Detection Circuit (LVD) Rev. 2.00 Jul. 31, 2008 Page 104 of 1438 REJ09B0365-0200

5.2 Register Descriptions

The registers of the voltage detection circuit are listed below.

• Voltage detection control register (LVDCR)
• Reset status register (RSTSR)

5.2.1 Voltage Detection Control Register (LVDCR)

The LVDCR controls the voltage-detection circuit. LVDE, LVDRI, and LVDMON are initialized by a pin reset or power-on reset Bit Bit name Initial value: R/W: LVDE R/W LVDRI R/W R/W LVDMON R R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description

7 LVDE 0 R/W LVD Enable

This bit enables or disables issuing of a reset or interrupt by the voltage-detection circuit. 0: Disabled 1: Enabled

6 LVDRI 0 R/W LVD Reset/Interrupt Select

This bit selects whether an internal reset or interrupt is generated when the voltage detection circuit detects a low voltage. When modifying the LVDRI bit, ensure that low-voltage detection is in the disabled state (the LVDE bit is cleared to 0). 0: A reset is generated when a voltage is detected. 1: An interrupt is generated when a low voltage is detected. 5 — 0 R/W Reserved This bit is always read as 0 and the write value should always be 0.

Section 5 Voltage Detection Circuit (LVD) Rev. 2.00 Jul. 31, 2008 Page 105 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description

4 LVDMON 0 R LVD Monitor

This bit monitors the voltage level. This bit is valid when the LVDE bit is 1 and read as 0 when the LVDE bit is 0. Writing to this bit is ineffective. 0: Vcc must fall below Vdet. 1: Vcc must rise above Vdet. 3 to 0 — 0 R/W Reserved These bits are always read as 0 and the write value should always be 0.

5.2.2 Reset Status Register (RSTSR)

RSTSR indicates the source of an internal reset or voltage monitoring interrupt. Note: * To clear the flag, only 0 should be written to. DPSRSTF R/(W)* R/W R/W R/W R/W LVDF Undefined R/(W)* Undefined R/W PORF Undefined R Bit Bit name Initial value: R/W: Bit Bit Name Initial Value R/W Description

7 DPSRSTF 0 R/W * Deep Software Standby Reset Flag

This bit indicates release from deep software standby mode due to the interrupt source selected by DPSIER and DPSIEGR, and generation of an internal reset. [Setting condition] Release from deep software standby mode due to an interrupt source. [Clearing condition]

• Writing 0 to the bit after reading it as1.
• Generation of a pin reset, power on reset, or voltage monitoring reset.

Section 5 Voltage Detection Circuit (LVD) Rev. 2.00 Jul. 31, 2008 Page 106 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description 6 to 3 — All 0 R/W Reserved These bits are always read as 0 and the write value should always be 0.

2 LVDF Undefined R/(W) * LVD Flag

This bit indicates that the voltage detection circuit has detected a low voltage (Vcc at or below Vdet). [Setting condition] Vcc falling to or below Vdet. [Clearing condition]

• After Vcc has exceeded Vdet and the specified stabilization period has elapsed, writing 0 to the bit after reading it as 1.
• Generation of a pin reset or power-on reset. 1 — Undefined R/W Reserved The write value should always be 0.

This bit indicates that a power-on reset has been generated. [Setting condition] Generation of a power-on reset [Clearing condition] Generation of a pin reset Note: * To clear the flag, only 0 should be written to.

Section 5 Voltage Detection Circuit (LVD) Rev. 2.00 Jul. 31, 2008 Page 107 of 1438 REJ09B0365-0200

5.3 Voltage Detection Circuit

5.3.1 Voltage Monitoring Reset

Figure 5.2 shows the timing of a voltage monitoring reset by the voltage-detection circuit. When Vcc falls below Vdet in the state where the LVDE bit in LVDCR has been set to 1 and the LVDRI bit has been cleared to 0, the LVDF bit is set to 1 and the voltage-detection circuit generates a voltage monitoring reset. Next, after Vcc has risen above Vdet, release from the voltage-monitoring reset takes place after a period for stabilization (tpor) has elapsed. The period for stabilization (tpor) is a time that is generated by the voltage detection circuit in order to stabilize the Vcc and the internal circuit of the LSI. When a voltage-monitoring reset is generated, the LVDF bit is set to 1. For details, see section 29, Electrical Characteristics. Vdet Vpor LVDE LVDRI Internal reset signal (Low) Stabilization time (t POR) Vcc ↓Write 1 ↓Write 0 Figure 5.2 Timing of the Voltage-Monitoring Reset

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5.3.2 Voltage Moni toring Interrupt

Figure 5.3 shows the timing of a voltage monitoring interrupt by the voltage-detection circuit. When Vcc falls below the Vdet in a state where the LVDE and LVDRI bits in LVDCR are both set to 1, the LVDF bit is set to 1 and a voltage monitoring interrupt is requested. The voltage monitoring interrupt signal is internally connected to IRQ14-B, so the IRQ14F bit in the ISR is set to 1 when the interrupt is generated. As for the IRQ14 setting, set both the ITS14 bit in PFCRB and the IRQ14E bit in the IER to 1, and the IRQ14SR and IRQ14SF bits in the ISCR to 01 (interrupt request on falling edge). Figure 5.4 shows the procedure for setting the voltage-monitoring interrupt. Vdet Vpor LVDE LVDRI Stabilization time (tPOR) Vcc ↓Write 1 ↓Write 1 LVDF Set Set Voltage-monitoring interrupt signal (IRQ14) IRQ14F Voltage-monitoring signal Write 0 after reading as 1 Figure 5.3 Timing of the Voltage-Monitoring Interrupt

Section 5 Voltage Detection Circuit (LVD) Rev. 2.00 Jul. 31, 2008 Page 109 of 1438 REJ09B0365-0200 IER.IRQ14E = write 0 LVDCR.LVDRI = write 1 LVDCR.LVDE = write 1 PFCRB.ITS14 = write 1 ISR.IRQ14F = clear Clear RSTSR.LVDF* IER.IRQ14E = write 1 ISCR setting (IRQ14SR = 0, IRQ14SF = 1) LVDCR. LVDMON = 1 (Vcc low) (Vcc high) No Yes Note: * When the LVDF cannot be cleared despite Vcc being at a higher electrical potential than Vdet (LVDMON = 1), the voltage-detection circuit is in the state of waiting for stabilization. Clear the bit again after the stabilization time (t POR) has elapsed. Start program Processing for lowered Vcc Interrupt generation when a low voltage is detected Voltage monitoring interrupt (IRQ14) disabled Voltage detection and IRQ register settings If the flag has been set to 1 before the voltage-monitoring interrupt is enabled, clear it by writing 0 after having read it as 1. Voltage-monitoring interrupt (IRQ14) enabled Processing for lowered Vcc Figure 5.4 Example of the Procedure for Setting the Voltage-Monitoring Interrupt

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5.3.3 Release from Deep Software Standby Mode by the Voltage-Detection Circuit

If the LVDE and LVDRI bits in LVDCR and the DLVDIE bit in DPSIER have all been set to 1 during a period in deep software standby mode, the voltage-detection circuit requests release from deep software standby mode when Vcc falls to or below Vdet. This sets the DLVDIF bit in DPSIFR to 1, thus producing release from the deep software standby mode. For the deep software standby mode, see section 27, Power-Down Modes.

5.3.4 Voltage Monitor

The result of voltage detection by the voltage-detection circuit can be monitored by checking the value of the LVDMON bit in LVDCR. When the LVDMON bit has been enabled by setting the LVDE bit, 0 indicates that Vcc is at or below Vdet and 1 indicates that Vcc is above Vdet. This bit should be read while the voltage-monitoring reset has been disabled by setting the LVDRI bit to 1. Before clearing the LVDF bit in RSTSR to 0, confirm that the LVDMON bit is set to 1 (indicating that Vcc is above Vdet). When it is impossible to clear the LVDF bit despite the LVDMON bit being 1, the voltage-detection circuit is in the state of waiting for stabilization. In such cases, clear the bit again after the stabilization time (t por) has elapsed.

Section 6 Exception Handling Rev. 2.00 Jul. 31, 2008 Page 111 of 1438 REJ09B0365-0200 Section 6 Exception Handling

6.1 Exception Handling Types and Priority

As table 6.1 indicates, exception handling is caused by a reset, a trace, an address error, an interrupt, a trap instruction, a sleep instruction, and an illegal instruction (general illegal instruction or slot illegal instruction). Exception handling is prioritized as shown in table 6.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Exception sources, the stack structure, and operation of the CPU vary depending on the interrupt control mode. For details on the interrupt control mode, see section 7, Interrupt Controller. Table 6.1 Exception Types and Priority Priority Exception Type E xception Handling Start Timing High Reset Exception handling starts at the timing of level change from low to high on the RES pin, or when the watchdog timer overflows. The CPU enters the reset state when the RES pin is low. Illegal instruction Exception hand ling starts when an undefined code is executed. Trace * Exception handling starts a fter execution of the current instruction or exception handling, if the trace (T) bit in EXR is set to 1. Address error After an address error has occurred, exception handling starts on completion of instruction execution. Interrupt Exception handling starts after execution of the current instruction or exception handling, if an interrupt request has occurred.* Sleep instruction Exception handling star ts by execution of a sleep instruction (SLEEP), if the SSBY bit in SBYCR is set to 0 and the SLPIE bit in SBYCR is set to 1. Low Trap instruction* Exception handling starts by execution of a trap instruction (TRAPA). Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not executed after execution of an RTE instruction. 2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. 3. Trap instruction exception handling reques ts and sleep instruction exception handling requests are accepted at all times in program execution state.

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6.2 Exception Sources and Exception Handling Vector Table

Different vector table address offsets are assigned to different exception sources. The vector table addresses are calculated from the contents of the vector base register (VBR) and vector table address offset of the vector number. The start address of the exception service routine is fetched from the exception handling vector table indicated by this vector table address. Table 6.2 shows the correspondence between the exception sources and vector table address offsets. Table 6.3 shows the calculation method of exception handling vector table addresses. Table 6.2 Exception Handling Vector Table Vector Table Address Offset* Exception Source Vector Number Normal Mode * Advanced, Middle* Maximum * Modes Reset 0 H'0000 to H'0001 H'0000 to H'0003 Reserved for system use 1 H'000 2 to H'0003 H' 0004 to H'0007

2 H'0004 to H'0005 H'0008 to H'000B

3 H'0006 to H'0007 H'000C to H'000F

Illegal instruction 4 H'0008 to H'0009 H'0010 to H'0013 Trace 5 H'000A to H'000B H'0014 to H'0017 Reserved for system use 6 H'000C to H'000D H'0018 to H'001B Interrupt (NMI) 7 H'000E to H'000F H'001C to H'001F Trap instruction (#0) 8 H'001 0 to H'0011 H'0020 to H'0023 (#1) 9 H'0012 to H'0013 H'0024 to H'0027 (#2) 10 H'0014 to H'0015 H'0028 to H'002B (#3) 11 H'0016 to H'0017 H'002C to H'002F CPU address error 12 H'0018 to H'0019 H'0030 to H'0033 DMA address error*

13 H'001A to H'001B H'0034 to H'0037

UBC break interrupt 14 H'001C to H'001D H'0038 to H'003B Reserved for system use 15 H'001E to H'001F H'0022 to H'0023 H'003C to H'003F H'0044 to H'0047 Sleep interrupt 18 H'0024 to H'0025 H'0048 to H'004B

Section 6 Exception Handling Rev. 2.00 Jul. 31, 2008 Page 113 of 1438 REJ09B0365-0200 Vector Table Address Offset* Exception Source Vector Number Normal Mode * Advanced, Middle* Maximum * Modes Reserved for system use 19 H'0026 to H'0027 H'002E to H'002F H'004C to H'004F H'005C to H'005F User area (not used) 24 H'0030 to H'0031 H'007E to H'007F H'0060 to H'0063 H'00FC to H'00FF External interrupt IRQ0 64 H'0080 to H'0081 H'0100 to H'0103 IRQ1 65 H'0082 to H'0083 H'0104 to H'0107 IRQ2 66 H'0084 to H'0085 H'0108 to H'010B IRQ3 67 H'0086 to H'0087 H'010C to H'010F IRQ4 68 H'0088 to H'0089 H'0110 to H'0113 IRQ5 69 H'008A to H'008B H'0114 to H'0117 IRQ6 70 H'008C to H'008D H'0118 to H'011B IRQ7 71 H'008E to H'008F H'011C to H'011F IRQ8 72 H'0090 to H'0091 H'0120 to H'0123 IRQ9 73 H'0092 to H'0093 H'0124 to H'0127 IRQ10 74 H'0094 to H'0095 H'0128 to H'012B IRQ11 75 H'0096 to H'0097 H'012C to H'012F IRQ12 76 H'0098 to H'0099 H'0130 to H'0133 IRQ13 77 H'009A to H'009B H'0134 to H'0137 IRQ14 78 H'009C to H'009D H'0138 to H'013B IRQ15 79 H'009E to H'009F H'013C to H'013F Internal interrupt* 255 H'00A0 to H'00A1 H'01FE to H'01FF H'0140 to H'0143 H'03FC to H'03FF Notes: 1. Lower 16 bits of the address. 2. Not available in this LSI. 3. A DMA address error is generated by the DTC, DMAC, and EXDMAC * 4. For details of internal interrupt vectors, see section 7.5, Interrupt Exception Handling Vector Table. 5. Supported only by the H8SX/1 648G Group and the H8SX/1648H Group.

Section 6 Exception Handling Rev. 2.00 Jul. 31, 2008 Page 114 of 1438 REJ09B0365-0200 Table 6.3 Calculation Method of Exception Handling Vector Table Address Exception Source Calculation Method of Vector Table Address Reset, CPU address error Vector table address = (vector table address offset) Other than above Vector table address = VBR + (vector table address offset) [Legend] VBR: Vector base register Vector table address offset: See table 6.2.

6.3 Reset

A reset has priority over any other exception. When the RES pin goes low, all processing halts and this LSI enters the reset state. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms with the STBY pin driven high when the power is turned on. When operation is in progress, hold the RES pin low for at least 20 cycles. The chip can also be reset by release of deep software standby mode or overflow of the watchdog timer. For details, see section 18, Watchdog Timer (WDT) and section 27, Power-Down Modes. A reset initializes the internal state of the CPU and the registers of the on-chip peripheral modules. The interrupt control mode is 0 immediately after a reset.

6.3.1 Reset Exception Handling

When the RES pin goes high after being held low for the necessary time, this LSI starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized, VBR is cleared to H'00000000, the T bit is cleared to 0 in EXR, and the I bits are set to 1 in EXR and CCR. 2. The reset exception handling vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figures 6.1 and 6.2 show examples of the reset sequence.

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6.3.2 Interrupts after Reset

If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx: 32, SP).

6.3.3 On-Chip Peripheral Functions after Reset Release

After the reset state is released, MSTPCRA and MSTPCRB are initialized to H'0FFF and H'FFFF, respectively, and all modules except for EXDMAC*, the DTC, and DMAC enter the module stop state. Consequently, on-chip peripheral module registers cannot be read or written to. Register reading and writing is enabled when the module stop state is canceled. Note: * Supported only by the H8SX/1648G Group and H8SX/1648H Group. RES High Vector fetch Internal operation First instruction prefetch (1): Reset exception handling vector address (when reset, (1) = H'000000) (2): Start address (contents of reset exception handling vector address) (3) Start address ((3) = (2)) (4) First instruction in the exception handling routine Iφ Internal address bus Internal read signal Internal write signal Internal data bus (1) (2) (4) (3) Figure 6.1 Reset Sequence (On-chip ROM Enabled Advanced Mode)

Section 6 Exception Handling Rev. 2.00 Jul. 31, 2008 Page 116 of 1438 REJ09B0365-0200 RES RD HWR, LWR D15 to D0 High * * * Bφ Address bus Vector fetch Internal operation First instruction prefetch (1) (2) (4) (6) (3) (5) (1)(3) Reset exception handling vector address (when reset, (1) = H'000000, (3) = H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5) = (2)(4)) (6) First instruction in the exception handling routine Note: * Seven program wait cycles are inserted. Figure 6.2 Reset Sequence (16-Bit External Access in On-chip ROM Disabled Advanced Mode)

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6.4 Traces

Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. Before changing interrupt control modes, the T bit must be cleared. For details on interrupt control modes, see section 7, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is not affected by interrupt masking by CCR. Table 6.4 shows the state of CCR and EXR after execution of trace exception handling. Trace mode is canceled by clearing the T bit in EXR to 0 during the trace exception handling. However, the T bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine by the RTE instruction, trace mode resumes. Trace exception handling is not carried out after execution of the RTE instruction. Interrupts are accepted even within the trace exception handling routine. Table 6.4 Status of CCR and EXR after Trace Exception Handling CCR EXR Interrupt Control Mode I UI T I2 to I0 0 Trace exception handling cannot be used. 2 1  0  [Legend] 1: Set to 1 0: Cleared to 0 : Retains the previous value.

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6.5 Address Error

6.5.1 Address Error Source

Instruction fetch, stack operation, or data read/write shown in table 6.5 may cause an address error. Table 6.5 Bus Cycle and Address Error Bus Cycle Type Bus Master Description Address Error Instruction fetch CPU Fetches instructi ons from even addresses No (normal) Fetches instructions from odd addresses Occurs Fetches instructions from areas other than on-chip peripheral module space* No (normal) Fetches instructions from on-chip peripheral module space* Occurs Fetches instructions from external memory space in single-chip mode Occurs Fetches instructions fr om access prohibited area.* Occurs Stack operation CPU Accesses stack w hen the stack pointer value is even address No (normal) Accesses stack when the stack pointer value is odd Occurs Data read/write CPU Accesses word data from even addresses No (normal) Accesses word data from odd addresses No (normal) Accesses external memory sp ace in single-chip mode Occurs Accesses to access prohibited area * Occurs Data read/write DTC or DMAC Accesses word data from even addresses No (normal) Accesses word data from odd addresses No (normal) Accesses external memory sp ace in single-chip mode Occurs Accesses to access prohibited area * Occurs Accesses word data from even addresses No (normal) Accesses word data from odd addresses No (normal) Accesses external memory space in single-chip mode Occurs Accesses to access prohibited area* Occurs Accesses to external memory space No (normal) Data read/write EXDMAC * Accesses to space other than external memory space Occurs

Section 6 Exception Handling Rev. 2.00 Jul. 31, 2008 Page 119 of 1438 REJ09B0365-0200 Bus Cycle Type Bus Master Description Address Error Single address transfer DMAC/ EXDMAC* Address access space is the external memory space for single address transfer No (normal) Address access space is not the external memory space for single address transfer Occurs Notes: 1. For on-chip peripheral module spac e, see section 9, Bus Controller (BSC). 2. For the access prohibited area, refer to figure 3.1 in section 3.4, Address Map. 3. Supported only by the H8SX/1 648G Group and the H8SX/1648H Group.

6.5.2 Address Error Exception Handling

When an address error occurs, address error exception handling starts after the bus cycle causing the address error ends and current instruction execution completes. The address error exception handling is as follows: 1. The contents of PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. An exception handling vector table address corresponding to the address error is generated, the start address of the exception service routine is loaded from the vector table to PC, and program execution starts from that address. Even though an address error occurs during a transition to an address error exception handling, the address error is not accepted. This prevents an address error from occurring due to stacking for exception handling, thereby preventing infinitive stacking. If the SP contents are not a multiple of 2 when an address error exception handling occurs, the stacked values (PC, CCR, and EXR) are undefined. When an address error occurs, the following is performed to halt the DTC, DMAC, and EXDMAC*.

Section 6 Exception Handling Rev. 2.00 Jul. 31, 2008 Page 120 of 1438 REJ09B0365-0200

• The ERR bit of DTCCR in the DTC is set to 1.
• The ERRF bit of DMDR_0 in the DMAC is set to 1.
• The ERRF bit of EDMDR_0 in the EXDMAC* is set to 1.
• The DTE bits of DMDRs for all channels in the DMAC are cleared to 0 to forcibly terminate transfer.
• The DTE bits of EDMDRs for all channels in the EXDMAC* are cleared to 0 to forcibly terminate transfer. Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group. Table 6.6 shows the state of CCR and EXR after execution of the address error exception handling. Table 6.6 Status of CCR and EXR after Address Error Exception Handling CCR EXR Interrupt Control Mode I UI T I2 to I0 0 1    2 1  0 7 [Legend] 1: Set to 1 0: Cleared to 0 : Retains the previous value.

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6.6 Interrupts

6.6.1 Interrupt Sources

Interrupt sources are NMI, UBC break interrupt, IRQ0 to IRQ15, and on-chip peripheral modules, as shown in table 6.7. Table 6.7 Interrupt Sources Type Source Number of Sources NMI NMI pin (external input) 1 UBC break interrupt User break controller (UBC) 1 IRQ0 to IRQ15 IRQ0 to IRQ15 pin (external input) 16 Voltage- detection circuit* Voltage-detection circuit (LVD) * 32K timer (TM32K)* DMA controller (DMAC) 8 EXDMA controller* (EXDMAC)* Watchdog timer (WDT) 1 On-chip peripheral module A/D converter 3 16-bit timer pulse unit (TPU) 52 8-bit timer (TMR) 16 Serial communications interface (SCI) 28 I C bus interface 2 (IIC2) 4 Refresh controller * Notes: 1. Supported only by the H8 SX/1648G Group and the H8SX/1648H Group. 2. Supported only by the H8SX/1 648L Group and the H8SX/1648H Group. Different vector numbers and vector table offsets are assigned to different interrupt sources. For vector number and vector table offset, refer to table 7.2, Interrupt Sources, Vector Address Offsets, and Interrupt Priority in section 7, Interrupt Controller.

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6.6.2 Interrupt Exception Handling

Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to eight priority/mask levels to enable multiple-interrupt control. The source to start interrupt exception handling and the vector address differ depending on the product. For details, refer to section 7, Interrupt Controller. The interrupt exception handling is as follows: 1. The contents of PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is update d and the T bit is cleared to 0. 3. An exception handling vector table address corresponding to the interrupt source is generated, the start address of the exception service routine is loaded from the vector table to PC, and program execution starts from that address.

6.7 Instruction Exception Handling

There are three instructions that cause exception handling: trap instruction, sleep instruction, and illegal instruction.

6.7.1 Trap Instruction

Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The trap instruction exception handling is as follows: 1. The contents of PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. An exception handling vector table address co rresponding to the vector number specified in the TRAPA instruction is generated, the start address of the exception service routine is loaded from the vector table to PC, and program execution starts from that address. A start address is read from the vector table corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 6.8 shows the state of CCR and EXR after execution of trap instruction exception handling.

Section 6 Exception Handling Rev. 2.00 Jul. 31, 2008 Page 123 of 1438 REJ09B0365-0200 Table 6.8 Status of CCR and EXR after Trap Instruction Exception Handling CCR EXR Interrupt Control Mode I UI T I2 to I0 0 1    2 1  0  [Legend] 1: Set to 1 0: Cleared to 0 : Retains the previous value.

6.7.2 Sleep Instruction Exception Handling

The sleep instruction exception handling starts when a sleep instruction is executed with the SSBY bit in SBYCR set to 0 and the SLPIE bit in SBYCR set to 1. The sleep instruction exception handling can always be executed in the program execution state. In the exception handling, the CPU operates as follows. 1. The contents of PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. An exception handling vector table address co rresponding to the vector number specified in the SLEEP instruction is generated, the start address of the exception service routine is loaded from the vector table to PC, and program execution starts from that address. Bus masters other than the CPU may gain the bus mastership after a sleep instruction has been executed. In such cases the sleep instruction will be started when the transactions of a bus master other than the CPU has been completed and the CPU has gained the bus mastership. Table 6.9 shows the state of CCR and EXR after execution of sleep instruction exception handling. For details, see section 27.10, Sleep Instruction Exception Handling.

Section 6 Exception Handling Rev. 2.00 Jul. 31, 2008 Page 124 of 1438 REJ09B0365-0200 Table 6.9 Status of CCR and EXR after Sleep Instruction Exception Handling CCR EXR Interrupt Control Mode I UI T I2 to I0 0 1    2 1  0 7 [Legend] 1: Set to 1 0: Cleared to 0 : Retains the previous value.

6.7.3 Exception Handling by Illegal Instruction

The illegal instructions are general illegal instructions and slot illegal instructions. The exception handling by the general illegal instruction starts when an undefined code is executed. The exception handling by the slot illegal instruction starts when a particular instruction (e.g. its code length is two words or more, or it changes the PC contents) at a delay slot (immediately after a delayed branch instruction) is executed. The exception handling by the general illegal instruction and slot illegal instruction is always executable in the program execution state. The exception handling is as follows: 1. The contents of PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is update d and the T bit is cleared to 0. 3. An exception handling vector table address corresponding to the occurred exception is generated, the start address of the exception service routine is loaded from the vector table to PC, and program execution starts from that address. Table 6.10 shows the state of CCR and EXR after execution of illegal instruction exception handling.

Section 6 Exception Handling Rev. 2.00 Jul. 31, 2008 Page 125 of 1438 REJ09B0365-0200 Table 6.10 Status of CCR and EXR after Illegal Instruction Exception Handling CCR EXR Interrupt Control Mode I UI T I2 to I0 0 1    2 1  0  [Legend] 1: Set to 1 0: Cleared to 0 : Retains the previous value.

6.8 Stack Status after Exception Handling

Figure 6.3 shows the stack after completion of exception handling. CCR PC (24 bits) SP EXR Reserved* CCR PC (24 bits) SP Advanced mode Interrupt control mode 0 Interrupt control mode 2 Note: * Ignored on return. Figure 6.3 Stack Status after Exception Handling

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6.9 Usage Note

When performing stack-manipulating access, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by a word transfer instruction or a longword transfer instruction, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn (or MOV.W Rn, @-SP) PUSH.L ERn (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W Rn (or MOV.W @SP+, Rn) POP.L ERn (or MOV.L @SP+, ERn) Performing stack manipulation while SP is set to an odd value leads to an address error. Figure 6.4 shows an example of operation when the SP value is odd. SP CCR : PC : R1L : SP : Condition code register Program counter General register R1L Stack pointer CCR SP SP R1L H'FFFEFA H'FFFEFB H'FFFEFC H'FFFEFD H'FFFEFE H'FFFEFF PC PC TRAPA instruction executed SP set to H'FFFEFF Data saved above SP MOV.B R1L, @-ER7 executed Contents of CCR lost Address [Legend] Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. (Address error occurred) Figure 6.4 Operation when SP Value is Odd

Section 7 Interrupt Controller Rev. 2.00 Jul. 31, 2008 Page 127 of 1438 REJ09B0365-0200 Section 7 Interrupt Controller

7.1 Features

• Two interrupt control modes Any of two interrupt control modes can be set by means of bits INTM1 and INTM0 in the interrupt control register (INTCR).
• Priority can be assigned by the interrupt priority register (IPR) IPR provides for setting interrupt priory. Eight levels can be set for each module for all interrupts except for the interrupt requests listed below. The following eight interrupt requests are given priority of 8, therefore they are accepted at all times.  NMI  Illegal instructions  Trace  Trap instructions  CPU address error  DMA address error*  Sleep instruction  UBC break interrupt
• Independent vector addresses All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine.
• Seventeen external interrupts NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge detection can be selected for NMI. Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ15 to IRQ0.
• DTC and DMAC control DTC and DMAC can be activated by means of interrupts.
• CPU priority control function The priority levels can be assigned to the CPU, DTC, DMAC, and EXDMAC* . The priority level of the CPU can be automatically assigned on an exception generation. Priority can be given to the CPU interrupt exception handling over that of the DTC, DMAC, and EXDMAC* transfer. Notes: 1. DMA address error is occurred in the DTC, DMAC, and EXDMAC* 2. Supported only by the H8SX/1648G Group and the H8SX/1648H Group.

Section 7 Interrupt Controller Rev. 2.00 Jul. 31, 2008 Page 128 of 1438 REJ09B0365-0200 A block diagram of the interrupt controller is shown in figure 7.1. INTCR IPR NMI input IRQ input Internal interrupt sources WOVI to ADI1 INTM1, INTM0 NMIEG NMI input unit IRQ input unit CPU priority DTC priority Interrupt controller Priority determination Source selector CPU interrupt request CPU vector DTC vector Activation request clear signal DTC activation request I I2 to I0 CCR EXR CPU DTC INTCR: CPUPCR: ISCR: IER: ISR: Interrupt control register CPU priority control register IRQ sense control register IRQ enable register IRQ status register SSIER: IPR: DTCER: DTCCR: Software standby release IRQ enable register Interrupt priority register DTC enable register DTC control register [Legend] ISCR SSIER IER DTCER DTC priority controlDTCCR ISR DMAC activation permission DMDR DMAC DMAC priority control CPUPCR IRQ15 IRQ14 TM32K*1 LVD2*2 Notes: 1. Supported only by the H8SX/1648G Group and H8SX/1648H Group. 2. Supported only by the H8SX/1648L Group and H8SX/1648H Group. Figure 7.1 Block Diagram of Interrupt Controller

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7.2 Input/Output Pins

Table 7.1 shows the pin configuration of the interrupt controller. Table 7.1 Pin Configuration Name I/O Function NMI Input Nonmaskable External Interrupt Rising or falling edge can be selected. IRQ15 to IRQ0 Input Maskable External Interrupts Rising, falling, or both edges, or level sensing, can be independently selected.

7.3 Register Descriptions

The interrupt controller has the following registers.

• Interrupt control register (INTCR)
• CPU priority control register (CPUPCR)
• Interrupt priority register H8SX/1648 Group, H8SX/1648A Group, H8SX/1648L Group: Interrupt priority registers A to I, K to O, Q, and R (IPRA to IPRI, IPRK to IPRO, IPRQ, and IPRR) H8SX/1648G Group, H8SX/1648H Group: Interrupt priority registers A to O, Q, and R (IPRA to IPRO, IPRQ, and IPRR)
• IRQ enable register (IER)
• IRQ sense control registers H and L (ISCRH, ISCRL)
• IRQ status register (ISR)
• Software standby release IRQ enable register (SSIER)

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7.3.1 Interrupt Cont rol Register (INTCR)

INTCR selects the interrupt control mode, and the edge which detects NMI. Bit Bit Name Initial Value R/W R R INTM1 R/W INTM0 R/W NMIEG R/W R R R Bit Bit Name Initial Value R/W Description R R Reserved These are read-only bits and cannot be modified. INTM1 INTM0 R/W R/W Interrupt Control Select Mode 1 and 0 These bits select either of two interrupt control modes for the interrupt controller. 00: Interrupt control mode 0 Interrupts are controlled by I bit in CCR. 01: Setting prohibited. 10: Interrupt control mode 2 Interrupts are controlled by bits I2 to I0 in EXR, and IPR. 11: Setting prohibited.

3 NMIEG 0 R/W NMI Edge Select

Selects the input edge for the NMI pin. 0: Interrupt request generated at falling edge of NMI input 1: Interrupt request generated at rising edge of NMI input 2 to 0  All 0 R Reserved These are read-only bits and cannot be modified.

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7.3.2 CPU Priority Control Register (CPUPCR)

CPUPCR sets whether or not the CPU has priority over the DTC, DMAC, and EXDMAC*. The interrupt exception handling by the CPU can be given priority over that of the DTC, DMAC, and EXDMAC* transfer. The priority level of the DTC is set by bits DTCP2 to DTCP0 in CPUPCR. The priority level of the DMAC and EXDMAC* is set by the DMAC and EXDMAC* control registers for each channel. Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group. Bit Bit Name Initial Value R/W Note: * When the IPSETE bit is set to 1, the CPU priority is automatically updated, so these bits cannot be modified. CPUPCE R/W DTCP2 R/W DTCP1 R/W DTCP0 R/W IPSETE R/W CPUP2 R/(W)* CPUP1 R/(W)* CPUP0 R/(W)*

Section 7 Interrupt Controller Rev. 2.00 Jul. 31, 2008 Page 132 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description

7 CPUPCE 0 R/W CPU Priority Control Enable

Controls the CPU priority control function. Setting this bit to 1 enables the CPU priority control over the DTC, DMAC, and EXDMAC* 0: CPU always has the lowest priority 1: CPU priority control enabled DTCP2 DTCP1 DTCP0 R/W R/W R/W DTC Priority Level 2 to 0 These bits set the DTC priority level. 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest)

3 IPSETE 0 R/W Interrupt Priority Set Enable

Controls the function which automatically assigns the interrupt priority level of the CPU. Setting this bit to 1 automatically sets bits CPUP2 to CPUP0 by the CPU interrupt mask bit (I bit in CCR or bits I2 to I0 in EXR). 0: Bits CPUP2 to CPUP0 are not updated automatically 1: The interrupt mask bit value is reflected in bits CPUP2 to CPUP0

Section 7 Interrupt Controller Rev. 2.00 Jul. 31, 2008 Page 133 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description CPUP2 CPUP1 CPUP0 R/(W)* R/(W)* R/(W)* CPU Priority Level 2 to 0 These bits set the CPU priority level. When the CPUPCE is set to 1, the CPU priority control function over the DTC, DMAC, and EXDMAC* becomes valid and the priority of CPU processing is assigned in accordance with the settings of bits CPUP2 to CPUP0. 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest) Notes: 1. Supported only by the H8 SX/1648G Group and the H8SX/1648H Group. 2. When the IPSETE bit is set to 1, the CPU priority is automatically updated, so these bits cannot be modified.

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7.3.3 Interrupt Pr iority Register

H8SX/1648 Group, H8SX/1648A Group and H8SX/1648L Group: Interrupt Priority Registers A to I, K to O, Q, and R (IPRA to IPRI, IPRK to IPRO, IPRQ, and IPRR) H8SX/1648G Group, and H8SX/1648H Group: Interrupt Priority Registers A to O, O, and R (IPRA to IPRO, IPRQ, and IPRR) IPR sets priory (levels 7 to 0) for interrupts other than NMI. Setting a value in the range from B'000 to B'111 in the 3-bit groups of bits 14 to 12, 10 to 8, 6 to 4, and 2 to 0 assigns a priority level to the corresponding interrupt. For the correspondence between the interrupt sources and the IPR settings, see table 7.2. Bit Bit Name Initial Value R/W R IPR14 R/W IPR13 R/W IPR12 R/W R IPR10 R/W IPR9 R/W IPR8 R/W Bit Bit Name Initial Value R/W R IPR6 R/W IPR5 R/W IPR4 R/W R IPR2 R/W IPR1 R/W IPR0 R/W Bit Bit Name Initial Value R/W Description 15  0 R Reserved This is a read-only bit and cannot be modified. IPR14 IPR13 IPR12 R/W R/W R/W Sets the priority level of the corresponding interrupt source. 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest)

Section 7 Interrupt Controller Rev. 2.00 Jul. 31, 2008 Page 135 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description 11  0 R Reserved This is a read-only bit and cannot be modified. IPR10 IPR9 IPR8 R/W R/W R/W Sets the priority level of the corresponding interrupt source. 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest) 7  0 R Reserved This is a read-only bit and cannot be modified. IPR6 IPR5 IPR4 R/W R/W R/W Sets the priority level of the corresponding interrupt source. 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest) 3  0 R Reserved This is a read-only bit and cannot be modified. IPR2 IPR1 IPR0 R/W R/W R/W Sets the priority level of the corresponding interrupt source. 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest)

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7.3.4 IRQ Enable Register (IER)

IER enables interrupt requests IRQ15 to IRQ0. Bit Bit Name Initial Value R/W IRQ15E R/W IRQ14E R/W IRQ13E R/W IRQ12E R/W IRQ11E R/W IRQ10E R/W IRQ9E R/W IRQ8E R/W Bit Bit Name Initial Value R/W IRQ7E R/W IRQ6E R/W IRQ5E R/W IRQ4E R/W IRQ3E R/W IRQ2E R/W IRQ1E R/W IRQ0E R/W Bit Bit Name Initial Value R/W Description

15 IRQ15E 0 R/W IRQ15 Enable

The IRQ15 interrupt request is enabled when this bit is 1. The 32KOVI interrupt in the TM32K* is also enabled.

14 IRQ14E 0 R/W IRQ14 Enable

The IRQ14 interrupt request is enabled when this bit is 1 The voltage-monitoring interrupt in the LVD* is enabled.

13 IRQ13E 0 R/W IRQ13 Enable

The IRQ13 interrupt request is enabled when this bit is 1.

12 IRQ12E 0 R/W IRQ12 Enable

The IRQ12 interrupt request is enabled when this bit is 1.

11 IRQ11E 0 R/W IRQ11 Enable

The IRQ11 interrupt request is enabled when this bit is 1.

10 IRQ10E 0 R/W IRQ10 Enable

The IRQ10 interrupt request is enabled when this bit is 1.

9 IRQ9E 0 R/W IRQ9 Enable

The IRQ9 interrupt request is enabled when this bit is 1.

8 IRQ8E 0 R/W IRQ8 Enable

The IRQ8 interrupt request is enabled when this bit is 1.

7 IRQ7E 0 R/W IRQ7 Enable

The IRQ7 interrupt request is enabled when this bit is 1.

Section 7 Interrupt Controller Rev. 2.00 Jul. 31, 2008 Page 137 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description

6 IRQ6E 0 R/W IRQ6 Enable

The IRQ6 interrupt request is enabled when this bit is 1.

5 IRQ5E 0 R/W IRQ5 Enable

The IRQ5 interrupt request is enabled when this bit is 1.

4 IRQ4E 0 R/W IRQ4 Enable

The IRQ4 interrupt request is enabled when this bit is 1.

3 IRQ3E 0 R/W IRQ3 Enable

The IRQ3 interrupt request is enabled when this bit is 1.

2 IRQ2E 0 R/W IRQ2 Enable

The IRQ2 interrupt request is enabled when this bit is 1.

1 IRQ1E 0 R/W IRQ1 Enable

The IRQ1 interrupt request is enabled when this bit is 1.

0 IRQ0E 0 R/W IRQ0 Enable

The IRQ0 interrupt request is enabled when this bit is 1. Notes: 1. Supported only by the H8 SX/1648G Group and the H8SX/1648H Group. 2. Supported only by the H8SX/1 648L Group and the H8SX/1648H Group.

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7.3.5 IRQ Sense Control Registers H and L (ISCRH, ISCRL)

ISCRH and ISCRL select the source that generates an interrupt request from IRQ15 to IRQ0 input. Upon changing the setting of ISCR, IRQnF (n = 0 to 15) in ISR is often set to 1 accidentally through an internal operation. In this case, an interrupt exception handling is executed if an IRQn interrupt request is enabled. In order to prevent such an accidental interrupt from occurring, the setting of ISCR should be changed while the IRQn interrupt is disabled, and then the IRQnF in ISR should be cleared to 0.

• ISCRH Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W IRQ15SR R/W IRQ15SF R/W IRQ14SR R/W IRQ14SF R/W IRQ13SR R/W IRQ13SF R/W IRQ12SR R/W IRQ12SF R/W IRQ11SR R/W IRQ11SF R/W IRQ10SR R/W IRQ10SF R/W IRQ9SR R/W IRQ9SF R/W IRQ8SR R/W IRQ8SF R/W
• ISCRL Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W IRQ7SR R/W IRQ7SF R/W IRQ6SR R/W IRQ6SF R/W IRQ5SR R/W IRQ5SF R/W IRQ4SR R/W IRQ4SF R/W IRQ3SR R/W IRQ3SF R/W IRQ2SR R/W IRQ2SF R/W IRQ1SR R/W IRQ1SF R/W IRQ0SR R/W IRQ0SF R/W

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• ISCRH Bit Bit Name Initial Value R/W Description IRQ15SR IRQ15SF R/W R/W IRQ15 Sense Control Rise IRQ15 Sense Control Fall
• When used as IRQ15 00: Interrupt request generated by low level of IRQ15 01: Interrupt request generated at falling edge of IRQ15 10: Interrupt request generated at rising edge of IRQ15 11: Interrupt request generated at both falling and rising edges of IRQ15
• TM32K* : When used as 32KOVI IRQ15 is used as the 32KOVI interrupt in the TM32K. IRQ15 is generated at falling edge of IRQ15. 00: Initial value 01: Interrupt request generated at falling edge of IRQ15 10: Setting prohibited 11: Setting prohibited IRQ14SR IRQ14SF R/W R/W IRQ14 Sense Control Rise IRQ14 Sense Control Fall
• When used as IRQ14 00: Interrupt request generated by low level of IRQ14 01: Interrupt request generated at falling edge of IRQ14 10: Interrupt request generated at rising edge of IRQ14 11: Interrupt request generated at both falling and rising edges of IRQ14
• LVD* : When used as a voltage-monitoring interrupt IRQ14 is used as the LVD voltage-monitoring interrupt. IRQ14 is generated at falling edge of IRQ14. 00: Initial value 01: Interrupt request generated at falling edge of IRQ14 10: Setting prohibited 11: Setting prohibited

Section 7 Interrupt Controller Rev. 2.00 Jul. 31, 2008 Page 140 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description IRQ13SR IRQ13SF R/W R/W IRQ13 Sense Control Rise IRQ13 Sense Control Fall 00: Interrupt request generated by low level of IRQ13 01: Interrupt request generated at falling edge of IRQ13 10: Interrupt request generated at rising edge of IRQ13 11: Interrupt request generated at both falling and rising edges of IRQ13 IRQ12SR IRQ12SF R/W R/W IRQ12 Sense Control Rise IRQ12 Sense Control Fall 00: Interrupt request generated by low level of IRQ12 01: Interrupt request generated at falling edge of IRQ12 10: Interrupt request generated at rising edge of IRQ12 11: Interrupt request generated at both falling and rising edges of IRQ12 IRQ11SR IRQ11SF R/W R/W IRQ11 Sense Control Rise IRQ11 Sense Control Fall 00: Interrupt request generated by low level of IRQ11 01: Interrupt request generated at falling edge of IRQ11 10: Interrupt request generated at rising edge of IRQ11 11: Interrupt request generated at both falling and rising edges of IRQ11 IRQ10SR IRQ10SF R/W R/W IRQ10 Sense Control Rise IRQ10 Sense Control Fall 00: Interrupt request generated by low level of IRQ10 01: Interrupt request generated at falling edge of IRQ10 10: Interrupt request generated at rising edge of IRQ10 11: Interrupt request generated at both falling and rising edges of IRQ10

Section 7 Interrupt Controller Rev. 2.00 Jul. 31, 2008 Page 141 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description IRQ9SR IRQ9SF R/W R/W IRQ9 Sense Control Rise IRQ9 Sense Control Fall 00: Interrupt request generated by low level of IRQ9 01: Interrupt request generated at falling edge of IRQ9 10: Interrupt request generated at rising edge of IRQ9 11: Interrupt request generated at both falling and rising edges of IRQ9 IRQ8SR IRQ8SF R/W R/W IRQ8 Sense Control Rise IRQ8 Sense Control Fall 00: Interrupt request generated by low level of IRQ8 01: Interrupt request generated at falling edge of IRQ8 10: Interrupt request generated at rising edge of IRQ8 11: Interrupt request generated at both falling and rising edges of IRQ8 Notes: 1. Supported only by the H8SX/1648G Group and H8SX/1648H Group. 2. Supported only by the H8SX/ 1648L Group and H8SX/1648H Group.

• ISCRL Bit Bit Name Initial Value R/W Description IRQ7SR IRQ7SF R/W R/W IRQ7 Sense Control Rise IRQ7 Sense Control Fall 00: Interrupt request generated by low level of IRQ7 01: Interrupt request generated at falling edge of IRQ7 10: Interrupt request generated at rising edge of IRQ7 11: Interrupt request generated at both falling and rising edges of IRQ7 IRQ6SR IRQ6SF R/W R/W IRQ6 Sense Control Rise IRQ6 Sense Control Fall 00: Interrupt request generated by low level of IRQ6 01: Interrupt request generated at falling edge of IRQ6 10: Interrupt request generated at rising edge of IRQ6 11: Interrupt request generated at both falling and rising edges of IRQ6

Section 7 Interrupt Controller Rev. 2.00 Jul. 31, 2008 Page 142 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description IRQ5SR IRQ5SF R/W R/W IRQ5 Sense Control Rise IRQ5 Sense Control Fall 00: Interrupt request generated by low level of IRQ5 01: Interrupt request generated at falling edge of IRQ5 10: Interrupt request generated at rising edge of IRQ5 11: Interrupt request generated at both falling and rising edges of IRQ5 IRQ4SR IRQ4SF R/W R/W IRQ4 Sense Control Rise IRQ4 Sense Control Fall 00: Interrupt request generated by low level of IRQ4 01: Interrupt request generated at falling edge of IRQ4 10: Interrupt request generated at rising edge of IRQ4 11: Interrupt request generated at both falling and rising edges of IRQ4 IRQ3SR IRQ3SF R/W R/W IRQ3 Sense Control Rise IRQ3 Sense Control Fall 00: Interrupt request generated by low level of IRQ3 01: Interrupt request generated at falling edge of IRQ3 10: Interrupt request generated at rising edge of IRQ3 11: Interrupt request generated at both falling and rising edges of IRQ3 IRQ2SR IRQ2SF R/W R/W IRQ2 Sense Control Rise IRQ2 Sense Control Fall 00: Interrupt request generated by low level of IRQ2 01: Interrupt request generated at falling edge of IRQ2 10: Interrupt request generated at rising edge of IRQ2 11: Interrupt request generated at both falling and rising edges of IRQ2

Section 7 Interrupt Controller Rev. 2.00 Jul. 31, 2008 Page 143 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description IRQ1SR IRQ1SF R/W R/W IRQ1 Sense Control Rise IRQ1 Sense Control Fall 00: Interrupt request generated by low level of IRQ1 01: Interrupt request generated at falling edge of IRQ1 10: Interrupt request generated at rising edge of IRQ1 11: Interrupt request generated at both falling and rising edges of IRQ1 IRQ0SR IRQ0SF R/W R/W IRQ0 Sense Control Rise IRQ0 Sense Control Fall 00: Interrupt request generated by low level of IRQ0 01: Interrupt request generated at falling edge of IRQ0 10: Interrupt request generated at rising edge of IRQ0 11: Interrupt request generated at both falling and rising edges of IRQ0

7.3.6 IRQ Status Register (ISR)

ISR is an IRQ15 to IRQ0 interrupt request register. Bit Bit Name Initial Value R/W IRQ15F R/(W)* IRQ14F R/(W)* IRQ13F R/(W)* IRQ12F R/(W)* IRQ11F R/(W)* IRQ10F R/(W)* IRQ9F R/(W)* IRQ8F R/(W)* Bit Bit Name Initial Value R/W Note: * Only 0 can be written, to clear the flag. The bit manipulation instructions or memory operation instructions should be used to clear the flag. IRQ7F R/(W)* IRQ6F R/(W)* IRQ5F R/(W)* IRQ4F R/(W)* IRQ3F R/(W)* IRQ2F R/(W)* IRQ1F R/(W)* IRQ0F R/(W)*

Section 7 Interrupt Controller Rev. 2.00 Jul. 31, 2008 Page 144 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description

15 IRQ15F 0 R/(W) *

When used as IRQ15: [Setting condition]

• When the interrupt selected by ISCR occurs [Clearing conditions]
• Writing 0 after reading IRQ15F = 1
• When interrupt exception handling is executed while low-level sensing is selected and IRQ15 input is high
• When IRQ15 interrupt exception handling is executed while falling-, rising-, or both-edge sensing is selected
• When the DTC is activated by an IRQ15 interrupt, and the DISEL bit in MRB of the DTC is cleared to 0 TM32K* : When used as 32KOVI [Setting condition]
• When the interrupt selected by ISCR occurs [Clearing condition]
• Writing 0 after reading IRQ15F = 1
• When IRQ15 interrupt exception handling is executed while falling-edge sensing is selected

Section 7 Interrupt Controller Rev. 2.00 Jul. 31, 2008 Page 145 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description

14 IRQ14F 0 R/(W) *

When used as IRQ14: [Setting condition]

• When the interrupt selected by ISCR occurs [Clearing conditions]
• Writing 0 after reading IRQ14F = 1
• When interrupt exception handling is executed while low-level sensing is selected and IRQ14 input is high
• When IRQ14 interrupt exception handling is executed while falling-, rising-, or both-edge sensing is selected
• When the DTC is activated by an IRQ14 interrupt, and the DISEL bit in MRB of the DTC is cleared to 0 LVD* : When used as a voltage-monitoring interrupt [Setting condition]
• When the interrupt selected by ISCR occurs [Clearing condition]
• Writing 0 after reading IRQ14F = 1
• When IRQ14 interrupt exception handling is executed while falling-edge sensing is selected

Section 7 Interrupt Controller Rev. 2.00 Jul. 31, 2008 Page 146 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description IRQ13F IRQ12F IRQ11F IRQ10F IRQ9F IRQ8F IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* [Setting condition]

• When the interrupt selected by ISCR occurs [Clearing conditions]
• Writing 0 after reading IRQnF = 1 (n=13 to 0)
• When interrupt exception handling is executed while low-level sensing is selected and IRQn input is high
• When IRQn interrupt exception handling is executed while falling-, rising-, or both-edge sensing is selected
• When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the DTC is cleared to 0 Note: 1. Only 0 can be written, to clear the flag. 2. Supported only by the H8 SX/1648G Group and H8SX/1648H Group. 3. Supported only by the H8SX/ 1648L Group and H8SX/1648H Group.

Section 7 Interrupt Controller Rev. 2.00 Jul. 31, 2008 Page 147 of 1438 REJ09B0365-0200

7.3.7 Software Standby Release IRQ Enable Register (SSIER)

SSIER selects the IRQ interrupt used to leave software standby mode. The IRQ interrupt used to leave software standby mode should not be set as the DTC activation source. Bit Bit Name Initial Value R/W SSI15 R/W SSI14 R/W SSI13 R/W SSI12 R/W SSI11 R/W SSI10 R/W SSI9 R/W SSI8 R/W Bit Bit Name Initial Value R/W SSI7 R/W SSI6 R/W SSI5 R/W SSI4 R/W SSI3 R/W SSI2 R/W SSI1 R/W SSI0 R/W Bit Bit Name Initial Value R/W Description SSI15 SSI14 SSI13 SSI12 SSI11 SSI10 SSI9 SSI8 SSI7 SSI6 SSI5 SSI4 SSI3 SSI2 SSI1 SSI0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Software Standby Release IRQ Setting These bits select the IRQn interrupt used to leave software standby mode (n = 15 to 0). 0: An IRQn request is not sampled in software standby mode 1: When an IRQn request occurs in software standby mode, this LSI leaves software standby mode after the oscillation settling time has elapsed

Section 7 Interrupt Controller Rev. 2.00 Jul. 31, 2008 Page 148 of 1438 REJ09B0365-0200

7.4 Interrupt Sources

7.4.1 External Interrupts

There are seventeen external interrupts: NMI and IRQ15 to IRQ0. These interrupts can be used to leave software standby mode. (1) NMI Interrupts Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the settings of the CPU interrupt mask bits. The NMIEG bit in INTCR selects whether an interrupt is requested at the rising or falling edge on the NMI pin. When an NMI interrupt is generated, the interrupt controller determines that an error has occurred, and performs the following procedure.

• Sets the ERR bit of DTCCR in the DTC to 1.
• Sets the ERRF bit of DMDR_0 in the DMAC to 1
• Sets the ERRF bit of DMDR_0 in the EXDMAC* to 1
• Clears the DTE bits of DMDRs for all channels in the DMAC to 0 to forcibly terminate transfer
• Clears the DTE bits of DMDRs for all channels in the EXDMAC* to 0 to forcibly terminate transfer Note: * Supported only by the H8SX/1648G and H8SX/1648H groups. (2) IRQn Interrupts An IRQn interrupt is requested by a signal input on pins IRQ15 to IRQ0. IRQn (n = 15 to 0) have the following features:
• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, on pins IRQn.
• Enabling or disabling of interrupt requests IRQn can be selected by IER.
• The interrupt priority can be set by IPR.
• The status of interrupt requests IRQn is indicated in ISR. ISR flags can be cleared to 0 by software. The bit manipulation instructions and memory operation instructions should be used to clear the flag.

Section 7 Interrupt Controller Rev. 2.00 Jul. 31, 2008 Page 149 of 1438 REJ09B0365-0200 Detection of IRQn interrupts is enabled through the P1ICR, P2ICR, P5ICR, and P6ICR register settings, and does not change regardless of the output setting. However, when a pin is used as an external interrupt input pin, the pin must not be used as an I/O pin for another function by clearing the corresponding DDR bit to 0. A block diagram of interrupts IRQn is shown in figure 7.2. IRQn interrupt request IRQnE IRQnF S R Q Clear signal Edge/level detection circuitInput buffer Corresponding bit in ICR IRQnSF, IRQnSR IRQn input [Legend] n = 15 to 0 Figure 7.2 Block Diagram of Interrupts IRQn When the IRQ sensing control in ISCR is set to a low level of signal IRQn, the level of IRQn should be held low until an interrupt handling starts. Then set the corresponding input signal IRQn to high in the interrupt handling routine and clear the IRQnF to 0. Interrupts may not be executed when the corresponding input signal IRQn is set to high before the interrupt handling begins.

7.4.2 Internal Interrupts

The sources for internal interrupts from on-chip peripheral modules have the following features:

• For each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that enable or disable these interrupts. They can be controlled independently. When the enable bit is set to 1, an interrupt request is issued to the interrupt controller.
• The interrupt priority can be set by means of IPR.
• The DTC and DMAC can be activated by a TPU, SCI, or other interrupt request.
• The priority levels of DTC and DMAC activation can be controlled by the DTC and DMAC priority control functions.

Section 7 Interrupt Controller Rev. 2.00 Jul. 31, 2008 Page 150 of 1438 REJ09B0365-0200

7.5 Interrupt Exception Handling Vector Table

Table 7.2 lists interrupt exception handling sources, vector address offsets, and interrupt priority. In the default priority order, a lower vector number corresponds to a higher priority. When interrupt control mode 2 is set, priority levels can be changed by setting the IPR contents. The priority for interrupt sources allocated to the same level in IPR follows the default priority, that is, they are fixed. Table 7.2 Interrupt Sources, Vector Address Offsets, and Interrupt Priority Vector Address Offset* Classification Interrupt Source Vector Number Advanced Mode Middle Mode Maximum Mode IPR Priority DTC Activation DMAC Activation External pin NMI 7 H'001C    UBC UBC break interrupt

14 H'0038 

  External pin IRQ0 64 H'0100 IPRA14 to IPRA12 O  IRQ1 65 H'0104 IPRA10 to IPRA8 O  IRQ2 66 H'0108 IPRA6 to IPRA4 O  IRQ3 67 H'010C IPRA2 to IPRA0 O  IRQ4 68 H'0110 IPRB14 to IPRB12 O  IRQ5 69 H'0114 IPRB10 to IPRB8 O  IRQ6 70 H'0118 IPRB6 to IPRB4 O  IRQ7 71 H'011C IPRB2 to IPRB0 O  IRQ8 72 H'0120 IPRC14 to IPRC12 O  IRQ9 73 H'0124 IPRC10 to IPRC8 O  IRQ10 74 H'0128 IPRC6 to IPRC4 O  IRQ11 75 H'012C IPRC2 to IPRC0 O  IRQ12 76 H'0130 IPRD14 to IPRD12 O  IRQ13 77 H'0134 IPRD10 to IPRD8 O  IRQ14 O  LVD* Voltage- monitoring interrupt

78 H'0138 IPRD6 to IPRD4

O  External pin IRQ15 O  TM32K* 32KOVI

79 H'013C IPRD2 to IPRD0

   Reserved for system use

80 H'0140 

  WDT WOVI 81 H'0144 IPRE10 to IPRE8 Low  

Section 7 Interrupt Controller Rev. 2.00 Jul. 31, 2008 Page 151 of 1438 REJ09B0365-0200 Vector Address Offset* Classification Interrupt Source Vector Number Advanced Mode Middle Mode Maximum Mode IPR Priority DTC Activation DMAC Activation  Reserved for system use

82 H'0148  High  

controller* CMI 83 H'014C IPRE2 to IPRE0    Reserved for system use

84 H'0150   

 Reserved for system use

85 H'0154  

A/D_0 ADI0 86 H'0158 IPRF10 to IPRF8 O O  Reserved for system use

87 H'015C 

  TGI0A 88 H'0160 O O TPU_0 TGI0B 89 H'0164 IPRF6 to IPRF4 O  TGI0C 90 H'0168 O  TGI0D 91 H'016C O  TCI0V 92 H'0170   TGI1A 93 H'0174 O O TPU_1 TGI1B 94 H'0178 IPRF2 to IPRF0 O  TCI1V 95 H'017C   TCI1U 96 H'0180   TGI2A 97 H'0184 O O TPU_2 TGI2B 98 H'0188 IPRG14 to IPRG12 O  TCI2V 99 H'018C   TCI2U 100 H'0190   TGI3A 101 H'0194 O O TPU_3 TGI3B 102 H'0198 IPRG10 to IPRG8 O  TGI3C 103 H'019C O  TGI3D 104 H'01A0 O  TCI3V 105 H'01A4   TGI4A 106 H'01A8 O O TPU_4 TGI4B 107 H'01AC IPRG6 to IPRG4 O  TCI4V 108 H'01B0   TCI4U 109 H'01B4 Low  

Section 7 Interrupt Controller Rev. 2.00 Jul. 31, 2008 Page 152 of 1438 REJ09B0365-0200 Vector Address Offset* Classification Interrupt Source Vector Number Advanced Mode Middle Mode Maximum Mode IPR Priority DTC Activation DMAC Activation TGI5A 110 H'01B8 High O O TPU_5 TGI5B 111 H'01BC IPRG2 to IPRG0 O  TCI5V 112 H'01C0   TCI5U 113 H'01C4    114 H'01C8   Reserved for system use 115 H'01CC   CMI0A 116 H'01D0 O  TMR_0 CMI0B 117 H'01D4 IPRH14 to IPRH12 O  OV0I 118 H'01D8   CMI1A 119 H'01DC O  TMR_1 CMI1B 120 H'01E0 IPRH10 to IPRH8 O  OV1I 121 H'01E4   CMI2A 122 H'01E8 O  TMR_2 CMI2B 123 H'01EC IPRH6 to IPRH4 O  OV2I 124 H'01F0   CMI3A 125 H'01F4 O  TMR_3 CMI3B 126 H'01F8 IPRH2 to IPRH0 O  OV3I 127 H'01FC   DMTEND0 128 H'0200 IPRI14 to IPRI12 O  DMAC DMTEND1 129 H'0204 IPRI10 to IPRI8 O  DMTEND2 130 H'0208 IPRI6 to IPRI4 O  DMTEND3 131 H'020C IPRI2 to IPRI0 O  EXDMTEND0 132 H'0210 IPRJ14 to IPRJ12 O  EXDMAC* EXDMTEND1 133 H'0214 IPRJ10 to IPRJ8 O  EXDMTEND2 134 H'0218 IPRJ6 to IPRJ4 O  EXDMTEND3 135 H'021C IPRJ2 to IPRJ0 O  DMEEND0 136 H'0220 O  DMAC DMEEND1 137 H'0224 IPRK14 to IPRK12 O  DMEEND2 138 H'0228 O  DMEEND3 139 H'022C Low O 

Section 7 Interrupt Controller Rev. 2.00 Jul. 31, 2008 Page 153 of 1438 REJ09B0365-0200 Vector Address Offset* Classification Interrupt Source Vector Number Advanced Mode Middle Mode Maximum Mode IPR Priority DTC Activation DMAC Activation EXDMTEEND0 140 H'0230 High O  EXDMAC* EXDMTEEND1 141 H'0234 O  EXDMTEEND2 142 H'0238 O  EXDMTEEND3 143 H'023C IPRK10 to IPRK8 O  ERI0 144 H'0240   SCI_0 RXI0 145 H'0244 IPRK6 to IPRK4 O O TXI0 146 H'0248 O O TEI0 147 H'024C   ERI1 148 H'0250   SCI_1 RXI1 149 H'0254 IPRK2 to IPRK0 O O TXI1 150 H'0258 O O TEI1 151 H'025C   ERI2 152 H'0260   SCI_2 RXI2 153 H'0264 IPRL14 to IPRL12 O O TXI2 154 H'0268 O O TEI2 155 H'026C   ERI3 156 H'0270   SCI_3 RXI3 157 H'0274 IPRL10 to IPRL8 O O TXI3 158 H'0278 O O TEI3 159 H'027C   ERI4 160 H'0280   SCI_4 RXI4 161 H'0284 IPRL6 to IPRL4 O O TXI4 162 H'0288 O O TEI4 163 H'028C Low  

Section 7 Interrupt Controller Rev. 2.00 Jul. 31, 2008 Page 154 of 1438 REJ09B0365-0200 Vector Address Offset* Classification Interrupt Source Vector Number Advanced Mode Middle Mode Maximum Mode IPR Priority DTC Activation DMAC Activation TGI6A 164 H'0290 High O O TGI6B 165 H'0294 O  TGI6C 166 H'0298 O  TGI6D 167 H'029C IPRL2 to IPRL0 O  TPU_6 TCI6V 168 H'02A0 IPRM14 to IPRM12   TGI7A 169 H'02A4 O O TGI7B 170 H'02A8 IPRM10 to IPRM8 O  TCI7V 171 H'02AC   TPU_7 TCI7U 172 H'02B0 IPRM6 to IPRM4   TGI8A 173 H'02B4 O O TGI8B 174 H'02B8 IPRM2 to IPRM0 O  TCI8V 175 H'02BC   TPU_8 TCI8U 176 H'02C0 IPRN14 to IPRN12   TGI9A 177 H'02C4 O O TGI9B 178 H'02C8 O  TGI9C 179 H'02CC O  TGI9D 180 H'02D0 IPRN10 to IPRN8 O  TPU_9 TCI9V 181 H'02D4 IPRN6 to IPRN4   TGI10A 182 H'02D8 O O TGI10B 183 H'02DC IPRN2 to IPRN0 O  Reserved for system use

184 H'02E0  

185 H'02E4

  TCI10V 186 H'02E8 O  TPU_10 TCI10U 187 H'02EC IPRO14 to IPRO12   TGI11A 188 H'02F0 O O TGI11B 189 H'02F4 IPRO10 to IPRO8 O  TCI11V 190 H'02F8   TPU_11 TCI11U 191 H'02FC IPRO6 to IPRO4   — Reserved for system use 192 215 H'0300 H'035C IIC2_0 IICI0 216 H'0360 — — — Reserved for system use

217 H'0364

— —

Section 7 Interrupt Controller Rev. 2.00 Jul. 31, 2008 Page 155 of 1438 REJ09B0365-0200 Vector Address Offset* Classification Interrupt Source Vector Number Advanced Mode Middle Mode Maximum Mode IPR Priority DTC Activation DMAC Activation IIC2_1 IICI1 218 H'0368 High — — — Reserved for system use

219 H'036C

— — RXI5 220 H'0370 — O SCI_5 TXI5 221 H'0374 IPRQ2 to IPRQ0 — O ERI5 222 H'0378 — — TEI5 223 H'037C — — RXI6 224 H'0380 — O SCI_6 TXI6 225 H'0384 IPRR14 to IPRR12 — O ERI6 226 H'0388 — — TEI6 227 H'038C — — TMR_4 CMIA4 or CMIB4

228 H'0390 — —

TMR_5 CMIA5 or CMIB5

229 H'0394

— — TMR_6 CMIA6 or CMIB6

230 H'0398 — —

TMR_7 CMIA7 or CMIB7

231 H'039C — —

A/D_2 ADI2 232 H'03A0 — O — Reserved for system use

233 H'03A4 — —

IIC2_2 IICI2 234 H'03A8 — — IIC2_3 IICI3 235 H'03AC IPRR6 to IPRR4 — — — Reserved for system use

236 H'03B0 — — —

A/D_1 ADI1 237 H'03B4 IPRR2 to IPRR0 — O — Reserved for system use 238 255 H'03B8 H'03FC Low Notes: 1. Lower 16 bits of the start address. 2. Supported only by the H8 SX/1648G and the H8SX/1648H groups. 3. Supported only by the H8 SX/1648L and the H8SX/1648H groups.

Section 7 Interrupt Controller Rev. 2.00 Jul. 31, 2008 Page 156 of 1438 REJ09B0365-0200

7.6 Interrupt Control Modes and Interrupt Operation

The interrupt controller has two interrupt control modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by INTCR. Table 7.3 shows the differences between interrupt control mode 0 and interrupt control mode 2. Table 7.3 Interrupt Control Modes Interrupt Control Mode Priority Setting Register Interrupt Mask Bit Description

0 Default I The priority levels of the interrupt sources are fixed

default settings. The interrupts except for NMI is masked by the I bit.

2 IPR I2 to I0 Eight priority leve ls can be set for interrupt sources

except for NMI with IPR. 8-level interrupt mask control is performed by bits I2 to I0.

7.6.1 Interrupt Control Mode 0

In interrupt control mode 0, interrupt requests except for NMI are masked by the I bit in CCR of the CPU. Figure 7.3 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt request occurs when the corresponding interrupt enable bit is set to 1, the interrupt request is sent to the interrupt controller. 2. If the I bit in CCR is set to 1, NMI is accepted, and other interrupt requests are held pending. If the I bit is cleared to 0, an interrupt request is accepted. 3. For multiple interrupt requests, the interrupt controller selects the interrupt request with the highest priority, sends the request to the CPU, and holds other interrupt requests pending. 4. When the CPU accepts the interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC and CCR contents are saved to the stack area during the interrupt exception handling. The PC contents saved on the stack is the address of the first instruction to be executed after returning from the interrupt handling routine. 6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI.

Section 7 Interrupt Controller Rev. 2.00 Jul. 31, 2008 Page 157 of 1438 REJ09B0365-0200 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Program execution state Interrupt generated? NMI IRQ0 IRQ1 TEI4 I = 0 Save PC and CCR I ← 1 Read vector address Branch to interrupt handling routine Yes No Yes Yes Yes No No No Yes Yes No Pending Figure 7.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0

Section 7 Interrupt Controller Rev. 2.00 Jul. 31, 2008 Page 158 of 1438 REJ09B0365-0200

7.6.2 Interrupt Control Mode 2

In interrupt control mode 2, interrupt requests except for NMI are masked by comparing the interrupt mask level (I2 to I0 bits) in EXR of the CPU and the IPR setting. There are eight levels in mask control. Figure 7.4 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt request occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. For multiple interrupt requests, the interrupt controller selects the interrupt request with the highest priority according to the IPR setting, and holds other interrupt requests pending. If multiple interrupt requests have the same priority, an interrupt request is selected according to the default setting shown in table 7.2. 3. Next, the priority of the selected interrupt reque st is compared with the interrupt mask level set in EXR. When the interrupt request does not have priority over the mask level set, it is held pending, and only an interrupt request with a priority over the interrupt mask level is accepted. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC, CCR, and EXR contents are saved to the stack area during interrupt exception handling. The PC saved on the stack is the address of the first instruction to be executed after returning from the interrupt handling routine. 6. The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority of the accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H'7. 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table.

Section 7 Interrupt Controller Rev. 2.00 Jul. 31, 2008 Page 159 of 1438 REJ09B0365-0200 Yes Program execution state Interrupt generated? NMI Level 6 interrupt? Mask level 5 or below? Level 7 interrupt? Mask level 6 or below? Save PC, CCR, and EXR Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Pending Level 1 interrupt? Mask level 0? Yes Yes No Yes Yes Yes No Yes Yes No No No No No No Figure 7.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2

Section 7 Interrupt Controller Rev. 2.00 Jul. 31, 2008 Page 160 of 1438 REJ09B0365-0200

7.6.3 Interrupt Except ion Handling Sequence

Figure 7.5 shows the interrupt exception handling sequence. The example is for the case where interrupt control mode 0 is set in maximum mode, and the program area and stack area are in on- chip memory. (12)(10)(6)(4)(2) Instruction prefetch Interrupt acceptance Interrupt level determination Wait for end of instruction (3) (8) Instruction prefetch in interrupt handling routineInternal operationVector fetchStack Internal operation Interrupt request signal Internal address bus Internal read signal Internal write signal Internal data bus Iφ (1) (2) (4) (3) (5) (7) Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) Instruction code (Not executed.) Instruction prefetch address (Not executed.) SP − 2 SP − 4 Saved PC and saved CCR Vector address Start address of interrupt handling routine (vector address contents) Start address of Interrupt handling routine ((11) = (10)) First instruction of interrupt handling routine (6) (8) (9) (10) (11) (12) Figure 7.5 Interrupt Exception Handling

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7.6.4 Interrupt Response Times

Table 7.4 shows interrupt response times – the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The symbols for execution states used in table 7.4 are explained in table 7.5. This LSI is capable of fast word transfer to on-chip memory, so allocating the program area in on- chip ROM and the stack area in on-chip RAM enables high-speed processing. Table 7.4 Interrupt Response Times Normal Mode * Advanced Mode Maximum Mode * Execution State Interrupt Control Mode 0 Interrupt Control Mode 2 Interrupt Control Mode 0 Interrupt Control Mode 2 Interrupt Control Mode 0 Interrupt Control Mode 2 Interrupt priority determination* Number of states until executing instruction ends* 1 to 19 + 2·SI PC, CCR, EXR stacking S K to 2·SK* 2·S K S K to 2·SK* 2·S K 2·S K 2·S K Vector fetch S h Instruction fetch* 2·S I Internal processing* Total (using on-chip memory) 10 to 31 11 to 31 10 to 31 11 to 31 11 to 31 11 to 31 Notes: 1. Two states for an internal interrupt. 2. In the case of the MULXS or DIVXS instruction 3. Prefetch after interrupt acceptance or for an instruction in the interrupt handling routine. 4. Internal operation after interru pt acceptance or after vector fetch 5. Not available in this LSI. 6. When setting the SP value to 4n, the interrupt response time is S K; when setting to 4n + 2, the interrupt response time is 2·SK.

Section 7 Interrupt Controller Rev. 2.00 Jul. 31, 2008 Page 162 of 1438 REJ09B0365-0200 Table 7.5 Number of Execution States in Interrupt Handling Routine Object of Access External Device 8-Bit Bus 16-Bit Bus Symbol On-Chip Memory 2-State Access 3-State Access 2-State Access 3-State Access Vector fetch Sh 1 8 12 + 4m 4 6 + 2m Instruction fetch SI 1 4 6 + 2m 2 3 + m Stack manipulation SK 1 8 12 + 4m 4 6 + 2m [Legend] m: Number of wait cycles in an external device access.

7.6.5 DTC and DMAC Acti vation by Interrupt

The DTC and DMAC can be activated by an interrupt. In this case, the following options are available:

• Interrupt request to the CPU
• Activation request to the DTC
• Activation request to the DMAC
• Combination of the above For details on interrupt requests that can be used to activate the DTC and DMAC, see table 7.2, section 10, DMA Controller (DMAC), and section 12, Data Transfer Controller (DTC). Figure 7.6 shows a block diagram of the DTC, DMAC, and interrupt controller.

Section 7 Interrupt Controller Rev. 2.00 Jul. 31, 2008 Page 163 of 1438 REJ09B0365-0200 Select signal DTCER DMRSR_0 to DMRSR_3 Select signal IRQ interrupt On-chip peripheral module Interrupt controller Clear signal Control signal DMAC activation request signal Clear signal DTC/CPU select circuit DMAC select circuit DTC control circuit Priority determination DTC DMAC CPU Interrupt request Clear signal Interrupt request Interrupt request clear signal Interrupt request clear signal Interrupt request DTC activation request vector number CPU interrupt request vector number Clear signal I, I2 to I0 Figure 7.6 Block Diagram of DTC, DMAC, and Interrupt Controller (1) Selection of Interrupt Sources The activation source for each DMAC channel is selected by DMRSR. The selected activation source is input to the DMAC through the select circuit. When transfer by an on-chip module interrupt is enabled (DTF1 = 1, DTF0 = 0, and DTE = 1 in DMDR) and the DTA bit in DMDR is set to 1, the interrupt source selected for the DMAC activation source is controlled by the DMAC and cannot be used as a DTC activation source or CPU interrupt source. Interrupt sources that are not controlled by the DMAC are set for DTC activation sources or CPU interrupt sources by the DTCE bit in DTCERA to DTCERH of the DTC. Specifying the DISEL bit in MRB of the DTC generates an interrupt request to the CPU by clearing the DTCE bit to 0 after the individual DTC data transfer. Note that when the DTC performs a predetermined number of data transfers and the transfer counter indicates 0, an interrupt request is made to the CPU by clearing the DTCE bit to 0 after the DTC data transfer. When the same interrupt source is set as both the DTC and DMAC activation source and CPU interrupt source, the DTC and DMAC must be given priority over the CPU. If the IPSETE bit in CPUPCR is set to 1, the priority is determined according to the IPR setting. Therefore, the CPUP setting or the IPR setting corresponding to the interrupt source must be set to lower than or equal to the DTCP and DMAP setting. If the CPU is given priority over the DTC or DMAC, the DTC or DMAC may not be activated, and the data transfer may not be performed.

Section 7 Interrupt Controller Rev. 2.00 Jul. 31, 2008 Page 164 of 1438 REJ09B0365-0200 (2) Priority Determination The DTC activation source is selected according to the default priority, and the selection is not affected by its mask level or priority level. For respective priority levels, see table 12.1, Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs. (3) Operation Order If the same interrupt is selected as both the DTC activation source and CPU interrupt source, the CPU interrupt exception handling is performed after the DTC data transfer. If the same interrupt is selected as the DTC or DMAC activation source or CPU interrupt source, respective operations are performed independently. Table 7.6 lists the selection of interrupt sources and interrupt source clear control by setting the DTA bit in DMDR of the DMAC, the DTCE bit in DTCERA to DTCERH of the DTC, and the DISEL bit in MRB of the DTC. Table 7.6 Interrupt Source Selection and Clear Control DMAC Setting DTC Setting Interrupt Source Selection/Clear Control DTA DTCE DISEL DMAC DTC CPU 0 0 * O X √ 1 0 O √ X

1 O O √

1 * * √ X X [Legend] √: The corresponding interrupt is used. The interrupt source is cleared. (The interrupt source flag must be cleared in the CPU interrupt handling routine.) O: The corresponding interrupt is used. The interrupt source is not cleared. X: The corresponding interrupt is not available. *: Don't care. (4) Usage Note The interrupt sources of the SCI, and A/D converter are cleared according to the setting shown in table 7.6, when the DTC or DMAC reads/writes the prescribed register. To initiate multiple channels for the DTC with the same interrupt, the same priority (DTCP = DMAP) should be assigned.

Section 7 Interrupt Controller Rev. 2.00 Jul. 31, 2008 Page 165 of 1438 REJ09B0365-0200

7.7 CPU Priority Control Function Over DTC, DMAC, and EXDMAC*

The interrupt controller has a function to control the priority among the DTC, DMAC, EXDMAC* and the CPU by assigning different priority levels to the DTC, DMAC, EXDMAC* and CPU. Since the priority level can automatically be assigned to the CPU on an interrupt occurrence, it is possible to execute the CPU interrupt exception handling prior to the DTC, DMAC, or EXDMAC* transfer. The priority level of the CPU is assigned by bits CPUP2 to CPUP0 in CPUPCR. The priority level of the DTC is assigned by bits DTCP2 to DTCP0 in CPUPCR. The priority level of the DMAC is assigned by bits DMAP2 to DMAP0 in DMDR for each channel. The priority level of the EXDMAC* is assigned by bits EDMAP2 to EDMAP0 in the EXDMA mode control register (EDMDR_0 to EDMDR_3) for each channel. The priority control function over the DTC, DMAC, and EXDMAC* is enabled by setting the CPUPCE bit in CPUPCR to 1. When the CPUPCE bit is 1, the DTC, DMAC, and EXDMAC* activation sources are controlled according to the respective priority levels. The DTC activation source is controlled according to the priority level of the CPU indicated by bits CPUP2 to CPUP0 and the priority level of the DTC indicated by bits DTCP2 to DTCP0. If the CPU has priority, the DTC activation source is held. The DTC is activated when the condition by which the activation source is held is cancelled (CPUPCE = 1 and value of bits CPUP2 to CPUP0 is greater than that of bits DTCP2 to DTCP0). The priority level of the DTC is assigned by the DTCP2 to DTCP0 bits regardless of the activation source. For the DMAC, the priority level can be specified for each channel. The DMAC activation source is controlled according to the priority level of each DMAC channel indicated by bits DMAP2 to DMAP0 and the priority level of the CPU. If the CPU has priority, the DMAC activation source is held. The DMAC is activated when the condition by which the activation source is held is cancelled (CPUPCE = 1 and value of bits CPUP2 to CPUP0 is greater than that of bits DMAP2 to DMAP0). If different priority levels are specified for channels, the channels of the higher priority levels continue transfer and the activation sources for the channels of lower priority levels than that of the CPU are held.

Section 7 Interrupt Controller Rev. 2.00 Jul. 31, 2008 Page 166 of 1438 REJ09B0365-0200 For the EXDMAC*, the priority level can be specified for each channel. The EXDMAC* activation source is controlled according to the priority level of each EXDMAC* channel indicated by bits EDMAP2 to EDMAP0 and the priority level of the CPU. If the CPU has priority, the EXDMAC* activation source is held. The EXDMAC* is activated when the condition by which the activation source is held is cancelled (CPUPCE = 1 and value of bits CPUP2 to CPUP0 is greater than that of bits DMAP2 to EDMAP0). If different priority levels are specified for channels, the channels of the higher priority levels continue transfer and the activation sources for the channels of lower priority levels than that of the CPU are held. There are two methods for assigning the priority level to the CPU by the IPSETE bit in CPUPCR. Setting the IPSETE bit to 1 enables a function to automatically assign the value of the interrupt mask bit of the CPU to the CPU priority level. Clearing the IPSETE bit to 0 disables the function to automatically assign the priority level. Therefore, the priority level is assigned directly by software rewriting bits CPUP2 to CPUP0. Even if the IPSETE bit is 1, the priority level of the CPU is software assignable by rewriting the interrupt mask bit of the CPU (I bit in CCR or I2 to I0 bits in EXR). The priority level which is automatically assigned when the IPSETE bit is 1 differs according to the interrupt control mode. In interrupt control mode 0, the I bit in CCR of the CPU is reflected in bit CPUP2. Bits CPUP1 and CPUP0 are fixed 0. In interrupt control mode 2, the values of bits I2 to I0 in EXR of the CPU are reflected in bits CPUP2 to CPUP0. Table 7.7 shows the CPU priority control. Table 7.7 CPU Priority Control Control Status Interrupt Control Mode Interrupt Priority Interrupt Mask Bit IPSETE in CPUPCR CPUP2 to CPUP0 Updating of CPUP2 to CPUP0

0 Default I = any 0 B'111 to B'000 Enabled

I = 0 1 B'000 Disabled I = 1 B'100

2 IPR setting I2 to I0 0 B'111 to B'000 Enabled

1 I2 to I0 Disabled

Section 7 Interrupt Controller Rev. 2.00 Jul. 31, 2008 Page 167 of 1438 REJ09B0365-0200 Table 7.8 shows a setting example of the priority control function over the DTC, DMAC, and EXDMAC* and the transfer request control state. A priority level can be independently set to each DMAC and EXDMAC* channels, but the table only shows one of the each channel for example. Transfers through the DMAC and EXDMAC* channels can be separately controlled by assigning different priority levels for channels. Table 7.8 Example of Priority Control Function Setting and Control State Transfer Request Control State Interrupt Control Mode CPUPCE in CPUPCR CPUP2 to CPUP0 DTCP2 to DTCP0 DMAP2 to DMAP0 EDMAP2 * to EDMAP0 * DTC DMAC EXDMAC * 0 0 Any Any Any Any Enabled Enabled Enabled

1 B'000 B'000 B'000 B'000 E nabled Enabled Enabled

B'100 B'000 B'000 B'000 Masked Masked Masked B'100 B'000 B'011 B'100 Masked Masked Enabled B'100 B'111 B'101 B'000 E nabled Enabled Masked B'000 B'111 B'101 B'000 E nabled Enabled Enabled 2 0 Any Any Any Any Enabled Enabled Enabled B'000 B'011 B'101 B'110 E nabled Enabled Enabled B'011 B'011 B'101 B'110 E nabled Enabled Enabled B'100 B'011 B'101 B'110 Ma sked Enabled Enabled B'101 B'011 B'101 B'110 Ma sked Enabled Enabled B'110 B'011 B'101 B'110 Masked Masked Enabled B'111 B'011 B'101 B'110 Masked Masked Masked B'101 B'011 B'101 B'011 Masked Enabled Masked B'101 B'110 B'101 B'011 E nabled Enabled Masked Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.

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7.8 Usage Notes

7.8.1 Conflict between Interrupt Generation and Disabling

When an interrupt enable bit is cleared to 0 to mask the interrupt, the masking becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request with priority over that interrupt, interrupt exception handling will be executed for the interrupt with priority, and another interrupt will be ignored. The same also applies when an interrupt source flag is cleared to 0. Figure 7.7 shows an example in which the TCIEV bit in TIER of the TPU is cleared to 0. The above conflict will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. Internal address bus Internal write signal Pφ TCIEV TCFV TCIV interrupt signal TIER_0 write cycle by CPU TCIV exception handling TIER_0 address Figure 7.7 Conflict between Interrupt Generation and Disabling Similarly, when an interrupt is requested immediately before the DTC enable bit is changed to activate the DTC, DTC activation and the interrupt exception handling by the CPU are both executed. When changing the DTC enable bit, make sure that an interrupt is not requested.

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7.8.2 Instructions that Disable Interrupts

Instructions that disable interrupts immediately after execution are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends.

7.8.3 Times when Interrupts are Disabled

There are times when interrupt acceptance is disabled by the interrupt controller. The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask level with an LDC, ANDC, ORC, or XORC instruction, and for a period of writing to the registers of the interrupt controller.

7.8.4 Interrupts during Execution of EEPMOV Instruction

Interrupt operation differs between the EEPMOV.B and the EEPMOV.W instructions. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the transfer is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at the end of the individual transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W MOV.W R4,R4 BNE L1

7.8.5 Interrupts during Execution of MOVMD and MOVS D Instructions

With the MOVMD or MOVSD instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at the end of the individual transfer cycle. The PC value saved on the stack in this case is the address of the MOVMD or MOVSD instruction. The transfer of the remaining data is resumed after returning from the interrupt handling routine.

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7.8.6 Interrupts of Peripheral Modules

To clear an interrupt source flag by the CPU using an interrupt function of a peripheral module, the flag must be read from after clearing within the interrupt processing routine. This makes the request signal synchronized with the peripheral module clock. For details, refer to section 26.6.1, Notes on Clock Pulse Generator.

Section 8 User Break Controller (UBC) Rev. 2.00 Jul. 31, 2008 Page 171 of 1438 REJ09B0365-0200 Section 8 User Break Controller (UBC) The user break controller (UBC) generates a UBC break interrupt request each time the state of the program counter matches a specified break condition. The UBC break interrupt is a non- maskable interrupt and is always accepted, regardless of the interrupt control mode and the state of the interrupt mask bit of the CPU. For each channel, the break control register (BRCR) and break address register (BAR) are used to specify the break condition as a combination of address bits and type of bus cycle. Four break conditions are independently specifiable on four channels, A to D.

8.1 Features

• Number of break channels: four (channels A, B, C, and D)
• Break comparison conditions (each channel)  Address  Bus master (CPU cycle)  Bus cycle (instruction execution (PC break))
• UBC break interrupt exception handling is executed immediately before execution of the instruction fetched from the specified address (PC break).
• Module stop state can be set

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8.2 Block Diagram

Internal bus (input side) Internal bus (output side) Instruction execution pointer BARAH BARAL BARBH BARBL BARCH BARCL BARDH BARDL BRCRA BRCRB BRCRC BRCRD PC break control Address comparator A ch Condition match determination Condition match determination Condition match determination Condition match determination Address comparator B ch Address comparator C ch Address comparator D ch Flag set control BARAH, BARAL: BARBH, BARBL: BARCH, BARCL: BARDH, BARDL: BRCRA: BRCRB: BRCRC: BRCRD: Break address register A Break address register B Break address register C Break address register D Break control register A Break control register B Break control register C Break control register D [Legend] Figure 8.1 Block Diagram of UBC

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8.3 Register Descriptions

Table 8.1 lists the register configuration of the UBC. Table 8.1 Register Configuration Register Name Abbreviation R/W Initial Value Address Access Size BARAH R/W H'0000 H'FFA00 16 Break address register A BARAL R/W H'0000 H'FFA02 16 BAMRAH R/W H'0000 H'FFA04 16 Break address mask register A BAMRAL R/W H'0000 H'FFA06 16 BARBH R/W H'0000 H'FFA08 16 Break address register B BARBL R/W H'0000 H'FFA0A 16 BAMRBH R/W H'0000 H'FFA0C 16 Break address mask register B BAMRBL R/W H'0000 H'FFA0E 16 BARCH R/W H'0000 H'FFA10 16 Break address register C BARCL R/W H'0000 H'FFA12 16 BAMRCH R/W H'0000 H'FFA14 16 Break address mask register C BAMRCL R/W H'0000 H'FFA16 16 BARDH R/W H'0000 H'FFA18 16 Break address register D BARDL R/W H'0000 H'FFA1A 16 BAMRDH R/W H'0000 H'FFA1C 16 Break address mask register D BAMRDL R/W H'0000 H'FFA1E 16 Break control register A BRCRA R/W H'0000 H'FFA28 8/16 Break control register B B RCRB R/W H'0000 H'FFA2C 8/16 Break control register C BRCRC R/W H'0000 H'FFA30 8/16 Break control register D BRCRD R/W H'0000 H'FFA34 8/16

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8.3.1 Break Address Register n (BARA, BARB, BARC, BARD)

Each break address register n (BARn) consists of break address register nH (BARnH) and break address register nL (BARnL). Together, BARnH and BARnL specify the address used as a break condition on channel n of the UBC. Bit: Initial Value: R/W: Bit: Initial Value: R/W: BARn31 R/W BARn30 R/W BARn29 R/W BARn28 R/W BARn27 R/W BARn24 R/W BARn26 R/W BARn25 R/W BARn23 R/W BARn22 R/W BARn21 R/W BARn20 R/W BARn19 R/W BARn16 R/W BARn18 R/W BARn17 R/W BARn15 R/W BARn14 R/W BARn13 R/W BARn12 R/W BARn11 R/W BARn8 R/W BARn10 R/W BARn9 R/W BARn7 R/W BARn6 R/W BARn5 R/W BARn4 R/W BARn3 R/W BARn0 R/W BARn2 R/W BARn1 R/W BARnH BARnL

• BARnH Bit Bit Name Initial Value R/W Description 31 to 16 BARn31 to BARn16 All 0 R/W Break Address n31 to 16 These bits hold the upper bit values (bits 31 to 16) for the address break-condition on channel n. [Legend] n = Channels A to D
• BARnL Bit Bit Name Initial Value R/W Description 15 to 0 BARn15 to BARn0 All 0 R/W Break Address n15 to 0 These bits hold the lower bit values (bits 15 to 0) for the address break-condition on channel n. [Legend] n = Channels A to D

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8.3.2 Break Address Mask Register n (BAMRA, BAMRB, BAMRC, BAMRD)

Be sure to write H'FF00 0000 to break address mask register n (BAMRn). Operation is not guaranteed if another value is written here. Bit: Initial Value: R/W: Bit: Initial Value: R/W: BAMRn31 R/W BAMRn30 R/W BAMRn29 R/W BAMRn28 R/W BAMRn27 R/W BAMRn24 R/W BAMRn26 R/W BAMRn25 R/W BAMRn23 R/W BAMRn22 R/W BAMRn21 R/W BAMRn20 R/W BAMRn19 R/W BAMRn16 R/W BAMRn18 R/W BAMRn17 R/W BAMRn15 R/W BAMRn14 R/W BAMRn13 R/W BAMRn12 R/W BAMRn11 R/W BAMRn8 R/W BAMRn10 R/W BAMRn9 R/W BAMRn7 R/W BAMRn6 R/W BAMRn5 R/W BAMRn4 R/W BAMRn3 R/W BAMRn0 R/W BAMRn2 R/W BAMRn1 R/W BAMRnH BAMRnL

• BAMRnH Bit Bit Name Initial Value R/W Description 31 to 16 BAMRn31 to BAMRn16 All 0 R/W Break Address Mask n31 to 16 Be sure to write H'FF00 here before setting a break condition in the break control register. [Legend] n = Channels A to D
• BAMRnL Bit Bit Name Initial Value R/W Description 15 to 0 BAMRn15 to BAMRn0 All 0 R/W Break Address Mask n15 to 0 Be sure to write H'0000 here before setting a break condition in the break control register. [Legend] n = Channels A to D

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8.3.3 Break Control Register n (BRCRA, BRCRB, BRCRC, BRCRD)

BRCRA, BRCRB, BRCRC, and BRCRD are used to specify and control conditions for channels A, B, C, and D of the UBC. Bit: Initial Value: R/W: [Legend] n = Channels A to D R/W R/W CMFCPn R/W R/W CPn2 R/W R/W CPn1 R/W CPn0 R/W R/W R/W IDn1 R/W IDn0 R/W RWn1 R/W R/W RWn0 R/W R/W Bit Bit Name Initial Value R/W Description R/W R/W Reserved These bits are always read as 0. The write value should always be 0.

13 CMFCPn 0 R/W Condition Match CPU Flag

UBC break source flag that indicates satisfaction of a specified CPU bus cycle condition. 0: The CPU cycle condition for channel n break requests has not been satisfied. 1: The CPU cycle condition for channel n break requests has been satisfied. 12  0 R/W Reserved These bits are always read as 0. The write value should always be 0. CPn2 CPn1 CPn0 R/W R/W R/W CPU Cycle Select These bits select CPU cycles as the bus cycle break condition for the given channel. 000: Break requests will not be generated. 001: The bus cycle break condition is CPU cycles. 01x: Setting prohibited 1xx: Setting prohibited R/W R/W R/W Reserved These bits are always read as 0. The write value should always be 0.

Section 8 User Break Controller (UBC) Rev. 2.00 Jul. 31, 2008 Page 177 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description IDn1 IDn0 R/W R/W Break Condition Select These bits select the PC break as the source of UBC break interrupt requests for the given channel. 00: Break requests will not be generated. 01: UBC break condition is the PC break. 1x: Setting prohibited RWn1 RWn0 R/W R/W Read Select These bits select read cycles as the bus cycle break condition for the given channel. 00: Break requests will not be generated. 01: The bus cycle break condition is read cycles. 1x: Setting prohibited R/W R/W Reserved These bits are always read as 0. The write value should always be 0. [Legend] n = Channels A to D

Section 8 User Break Controller (UBC) Rev. 2.00 Jul. 31, 2008 Page 178 of 1438 REJ09B0365-0200

8.4 Operation

The UBC does not detect condition matches in standby states (sleep mode, all module clock stop mode, software standby mode, deep software standby, and hardware standby mode).

8.4.1 Setting of Break Control Conditions

1. The address condition for the break is set in break address register n (BARn). A mask for the address is set in break address mask register n (BAMRn). 2. The bus and break conditions are set in br eak control register n (BRCRn). Bus conditions consist of CPU cycle, PC break, and reading. Condition comparison is not performed when the CPU cycle setting is CPn = B'000, the PC break setting is IDn = B'00, or the read setting is RWn = B'00. 3. The condition match CPU flag (CMFCPn) is set in the event of a break condition match on the corresponding channel. These flags are set when the break condition matches but are not cleared when it no longer does. To confirm setting of the same flag again, read the flag once from the break interrupt handling routine, and then write 0 to it (the flag is cleared by writing 0 to it after reading it as 1). [Legend] n = Channels A to D

8.4.2 PC Break

1. When specifying a PC break, speci fy the address as the first address of the required instruction. If the address for a PC break condition is not the first address of an instruction, a break will never be generated. 2. The break occurs after fetching and execution of the target instruction have been confirmed. In cases of contention between a break before instruction execution and a user maskable interrupt, priority is given to the break before instruction execution. 3. A break will not be generated even if a break be fore instruction execution is set in a delay slot. 4. The PC break condition is generated by specif ying CPU cycles as the bus condition in break control register n (BRCRn.CPn0 = 1), PC break as the break condition (IDn0 = 1), and read cycles as the bus-cycle condition (RWn0 = 1). [Legend] n = Channels A to D

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8.4.3 Condition Match Flag

Condition match flags are set when the break conditions match. The condition match flags of the UBC are listed in table 8.2. Table 8.2 List of Condition Match Flags Register Flag Bit Source BRCRA CMFCPA (bit 13) Indicates that t he condition matches in the CPU cycle for channel A BRCRB CMFCPB (bit 13) Indicates that t he condition matches in the CPU cycle for channel B BRCRC CMFCPC (bit 13) Indicates that t he condition matches in the CPU cycle for channel C BRCRD CMFCPD (bit 13) Indicates that t he condition matches in the CPU cycle for channel D

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8.5 Usage Notes

1. PC break usage note  Contention between a SLEEP instruction (to place the chip in the sleep state or on software standby) and PC break If a break before a PC break instruction is set for the instruction after a SLEEP instruction and the SLEEP instruction is executed with the SSBY bit cleared to 0, break interrupt exception handling is executed without sleep mode being entered. In this case, the instruction after the SLEEP instruction is executed after the RTE instruction. When the SSBY bit is set to 1, break interrupt exception handling is executed after the oscillation settling time has elapsed subsequent to the transition to software standby mode. When an interrupt is the canceling source, interrupt exception handling is executed after the RTE instruction, and the instruction following the SLEEP instruction is then executed. SLEEP Break interrupt exception handling Interrupt exception handlingSoftware standby (PC break source) (Cancelling source) Cancelling source CLK Figure 8.2 Contention between SLEEP Instruction (Software Standby) and PC Break 2. Prohibition on Setting of PC Break  Setting of a UBC break interrupt for program within the UBC break interrupt handling routine is prohibited. 3. The procedure for clearing a UBC flag bit (condition match flag) is shown below. A flag bit is cleared by writing 0 to it after reading it as 1. As the register that contains the flag bits is accessible in byte units, bit manipulation instructions can be used.

Section 8 User Break Controller (UBC) Rev. 2.00 Jul. 31, 2008 Page 181 of 1438 REJ09B0365-0200 CKS Register read The value read as 1 is retained Register write Flag bit Flag bit is set to 1 Flag bit is cleared to 0 Figure 8.3 Flag Bit Clearing Sequence (Condition Match Flag) 4. After setting break conditions for the UBC, an unexpected UBC break interrupt may occur after the execution of an illegal instruction. This depends on the value of the program counter and the internal bus cycle.

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Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 183 of 1438 REJ09B0365-0200 Section 9 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters; CPU, DMAC, EXDMAC*, and DTC. Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.

9.1 Features

• Manages external address space in area units Manages the external address space divided into eight areas Chip select signals (CS0 to CS7) can be output for each area Bus specifications can be set independently for each area 8-bit access or 16-bit access can be selected for each area DRAM*, synchronous DRAM*, burst ROM, byte control SRAM, or address/data multiplexed I/O interface can be set An endian conversion function is provided to connect a device of little endian
• Basic bus interface This interface can be connected to the SRAM and ROM 2-state access or 3-state access can be selected for each area Program wait cycles can be inserted for each area Wait cycles can be inserted by the WAIT pin. Extension cycles can be inserted while CSn is asserted for each area (n = 0 to 7) The negation timing of the read strobe signal (RD) can be modified
• Byte control SRAM interface Byte control SRAM interface can be set for areas 0 to 7 The SRAM that has a byte control pin can be directly connected
• Burst ROM interface Burst ROM interface can be set for areas 0 and 1 Burst ROM interface parameters can be set independently for areas 0 and 1
• Address/data multiplexed I/O interface Address/data multiplexed I/O interface can be set for areas 3 to 7

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• DRAM interface* DRAM interface is available as area 2 Row/column address-multiplexed output (8, 9, 10, or 11 bits) Two CAS signals control byte accesses for 16-bit data bus device CAS assertion period can be extended by a program wait and a pin wait Burst access can be performed in fast page mode Tp cycle for ensuring a RAS precharge time can be inserted CAS-before-RAS refresh (CBR refresh) and self refresh are selectable
• Synchronous DRAM interface* Synchronous DRAM interface is available as area 2 Row/column address-multiplexed output (8, 9, 10, or 11 bits) DQM signals control byte access for 16-bit data bus device Auto refresh and self refresh are selectable CAS latency can be selected from 2 to 4 High-speed data transfer is available using EXDMAC cluster transfer
• Idle cycle insertion Idle cycles can be inserted between external read accesses to different areas Idle cycles can be inserted before the external write access after an external read access Idle cycles can be inserted before the external read access after an external write access Idle cycles can be inserted before the external access after a DMAC/EXDMAC* single address transfer (write access)
• Write buffer function External write cycles and internal accesses can be executed in parallel Write accesses to the on-chip peripheral module and on-chip memory accesses can be executed in parallel DMAC single address transfers and internal accesses can be executed in parallel
• External bus release function
• Bus arbitration function Includes a bus arbiter that arbitrates bus mastership among the CPU, DMAC, EXDMAC*, DTC, refresh*, and external bus master
• EXDMAC external bus transfers and internal accesses can be executed in parallel*.
• Multi-clock function The internal peripheral functions can be operated in synchronization with the peripheral module clock (Pφ). Accesses to the external address space can be operated in synchronization with the external bus clock (Bφ).

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• The bus start (BS) and read/write (RD/WR) signals can be output. Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group. A block diagram of the bus controller is shown in figure 9.1.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 186 of 1438 REJ09B0365-0200 Address selector Area decoder Internal bus control unit Internal data bus Internal bus control signals External bus control unit External bus arbiter Internal bus arbiter CPU address bus CS7 to CS0 WAIT BREQ BACK BREQO DTC address bus EXDMAC address bus* CPU bus acknowledge signal DTC bus acknowledge signal CPU bus request signal DTC bus request signal EXDMAC bus acknowledge signal* EXDMAC bus request signal* External bus control signals Control registers ABWCR ASTCR WTCRA WTCRB RDNCR CSACR IDLCR BCR1 BCR2 RTCNT* RTCOR* ENDIANCR SRAMCR BROMCR MPXCR [Legend] ABWCR: ASTCR: WTCRA: WTCRB: RDNCR: CSACR: IDLCR: BCR1: BCR2: ENDIANCR: Bus width control register Access state control register Wait control register A Wait control register B Read strobe timing control register CS assertion period control register Idle control register Bus control register 1 Bus control register 2 Endian control register SRAMCR: BROMCR: MPXCR: DRAMCR*: DRACCR*: SDCR*: REFCR*: RTCNT*: RTCOR*: SRAM mode control register Burst ROM interface control register Address/data multiplexed I/O control register DRAM control register DRAM access control register Synchronous DRAM control register Refresh control register Refresh timer counter Refresh time constant register DMAC address bus DMAC bus acknowledge signal DMAC bus request signal DRAMCR* DRACCR* SDCR* REFCR* Refresh timer* Note: * Supported only by the H8SX/1648G Group and H8SX/1648H Group. Figure 9.1 Block Diagram of Bus Controller

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9.2 Register Descriptions

The bus controller has the following registers.

• Bus width control register (ABWCR)
• Access state control register (ASTCR)
• Wait control register A (WTCRA)
• Wait control register B (WTCRB)
• Read strobe timing control register (RDNCR)
• CS assertion period control register (CSACR)
• Idle control register (IDLCR)
• Bus control register 1 (BCR1)
• Bus control register 2 (BCR2)
• Endian control register (ENDIANCR)
• SRAM mode control register (SRAMCR)
• Burst ROM interface control register (BROMCR)
• Address/data multiplexed I/O control register (MPXCR)
• DRAM control register (DRAMCR)*
• DRAM access control register (DRACCR)*
• Synchronous DRAM control register (SDCR)*
• Refresh control register (REFCR)*
• Refresh timer counter (RTCNT)*
• Refresh time constant register (RTCOR)* Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.

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9.2.1 Bus Width Control Register (ABWCR)

ABWCR specifies the data bus width for each area in the external address space. Bit Bit Name Initial Value R/W ABWH7 R/W ABWH6 R/W ABWH5 R/W ABWH4 R/W ABWH3 R/W ABWH2 R/W ABWH1 R/W ABWH0 R/W Bit Bit Name Initial Value R/W Note: * Initial value at 16-bit bus initiation is H'FEFF , and that at 8-bit bus initiation is H'FFFF . ABWL7 R/W ABWL6 R/W ABWL5 R/W ABWL4 R/W ABWL3 R/W ABWL2 R/W ABWL1 R/W ABWL0 R/W Bit Bit Name Initial Value* R/W Description ABWH7 ABWH6 ABWH5 ABWH4 ABWH3 ABWH2 ABWH1 ABWL0 ABWL7 ABWL6 ABWL5 ABWL4 ABWL3 ABWL2 ABWL1 ABWL0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Area 7 to 0 Bus Width Control These bits select whether the corresponding area is to be designated as 8-bit access space or 16-bit access space. ABWHn ABWLn (n = 7 to 0) × 0: Setting prohibited 0 1: Area n is designated as 16-bit access space 1 1: Area n is designated as 8-bit access space* [Legend] ×: Don't care Notes: 1. Initial value at 16-bit bus initiation is H'FEFF, and that at 8-bit bus initiation is H'FFFF. 2. An address space specified as byte contro l SRAM interface must not be specified as 8- bit access space.

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9.2.2 Access State Control Register (ASTCR)

ASTCR designates each area in the external address space as either 2-state access space or 3-state access space and enables/disables wait cycle insertion. Bit Bit Name Initial Value R/W AST7 R/W AST6 R/W AST5 R/W AST4 R/W AST3 R/W AST2 R/W AST1 R/W AST0 R/W Bit Bit Name Initial Value R/W R R R R R R R R Bit Bit Name Initial Value R/W Description AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 R/W R/W R/W R/W R/W R/W R/W R/W Area 7 to 0 Access State Control These bits select whether the corresponding area is to be designated as 2-state access space or 3-state access space. Wait cycle insertion is enabled or disabled at the same time. 0: Area n is designated as 2-state access space Wait cycle insertion in area n access is disabled 1: Area n is designated as 3-state access space Wait cycle insertion in area n access is enabled (n = 7 to 0) 7 to 0  All 0 R Reserved These are read-only bits and cannot be modified.

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9.2.3 Wait Control Registers A and B (WTCRA, WTCRB)

WTCRA and WTCRB select the number of program wait cycles for each area in the external address space. Bit Bit Name Initial Value R/W R  WTCRA  WTCRB W72 R/W W71 R/W W70 R/W R W62 R/W W61 R/W W60 R/W Bit Bit Name Initial Value R/W R W52 R/W W51 R/W W50 R/W R W42 R/W W41 R/W W40 R/W Bit Bit Name Initial Value R/W R W32 R/W W31 R/W W30 R/W R W22 R/W W21 R/W W20 R/W Bit Bit Name Initial Value R/W R W12 R/W W11 R/W W10 R/W R W02 R/W W01 R/W W00 R/W

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• WTCRA Bit Bit Name Initial Value R/W Description 15  0 R Reserved This is a read-only bit and cannot be modified. W72 W71 W70 R/W R/W R/W Area 7 Wait Control 2 to 0 These bits select the number of program wait cycles when accessing area 7 while bit AST7 in ASTCR is 1. 000: Program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted 11  0 R Reserved This is a read-only bit and cannot be modified. W62 W61 W60 R/W R/W R/W Area 6 Wait Control 2 to 0 These bits select the number of program wait cycles when accessing area 6 while bit AST6 in ASTCR is 1. 000: Program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted 7  0 R Reserved This is a read-only bit and cannot be modified.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 192 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description W52 W51 W50 R/W R/W R/W Area 5 Wait Control 2 to 0 These bits select the number of program wait cycles when accessing area 5 while bit AST5 in ASTCR is 1. 000: Program cycle wait not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted 3  0 R Reserved This is a read-only bit and cannot be modified. W42 W41 W40 R/W R/W R/W Area 4 Wait Control 2 to 0 These bits select the number of program wait cycles when accessing area 4 while bit AST4 in ASTCR is 1. 000: Program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted

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• WTCRB Bit Bit Name Initial Value R/W Description 15  0 R Reserved This is a read-only bit and cannot be modified. W32 W31 W30 R/W R/W R/W Area 3 Wait Control 2 to 0 These bits select the number of program wait cycles when accessing area 3 while bit AST3 in ASTCR is 1. 000: Program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted 11  0 R Reserved This is a read-only bit and cannot be modified. W22 W21 W20 R/W R/W R/W Area 2 Wait Control 2 to 0 These bits select the number of program wait cycles when accessing area 2 while bit AST2 in ASTCR is 1. When SDRAM* is connected, the CAS latency is specified. At this time, W22 is ignored. The CAS latency can be specified even if the wait cycle insertion is disabled by ASTCR. Selection of number of program wait cycles: 000: Program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted Setting of CAS latency (W22 is ignored.)*: 00: Setting prohibited 01: SDRAM with a CAS latency of 2 is connected. 10: SDRAM with a CAS latency of 3 is connected. 11: SDRAM with a CAS latency of 4 is connected.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 194 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description 7  0 R Reserved This is a read-only bit and cannot be modified. W12 W11 W10 R/W R/W R/W Area 1 Wait Control 2 to 0 These bits select the number of program wait cycles when accessing area 1 while bit AST1 in ASTCR is 1. 000: Program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted 3  0 R Reserved This is a read-only bit and cannot be modified. W02 W01 W00 R/W R/W R/W Area 0 Wait Control 2 to 0 These bits select the number of program wait cycles when accessing area 0 while bit AST0 in ASTCR is 1. 000: Program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted Note: * Supported only by the H8SX1648G Group and the H8SX1648H Group.

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9.2.4 Read Strobe Timing Control Register (RDNCR)

RDNCR selects the negation timing of the read strobe signal (RD) when reading the external address spaces specified as a basic bus interface or the address/data multiplexed I/O interface. Bit Bit Name Initial Value R/W RDN7 R/W RDN6 R/W RDN5 R/W RDN4 R/W RDN3 R/W RDN2 R/W RDN1 R/W RDN0 R/W Bit Bit Name Initial Value R/W R R R R R R R R Bit Bit Name Initial Value R/W Description RDN7 RDN6 RDN5 RDN4 RDN3 RDN2 RDN1 RDN0 R/W R/W R/W R/W R/W R/W R/W R/W Read Strobe Timing Control RDN7 to RDN0 set the negation timing of the read strobe in a corresponding area read access. As shown in figure 9.2, the read strobe for an area for which the RDNn bit is set to 1 is negated one half- cycle earlier than that for an area for which the RDNn bit is cleared to 0. The read data setup and hold time are also given one half-cycle earlier. 0: In an area n read access, the RD signal is negated at the end of the read cycle 1: In an area n read access, the RD signal is negated one half-cycle before the end of the read cycle (n = 7 to 0) 7 to 0  All 0 R Reserved These are read-only bits and cannot be modified. Notes: 1. In an external address space which is specified as byte control SRAM interface, the RDNCR setting is ignored and the same operation when RDNn = 1 is performed. 2. In an external address space which is specified as the burst ROM interface, the RDNCR setting is ignored and the same operation when RDNn = 0 is performed during read accesses by the CPU and EXDMAC* cluster transfer. * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 196 of 1438 REJ09B0365-0200 Bus cycle T1 T2 RD Bφ Data RD Data RDNn = 0 RDNn = 1 (n = 7 to 0) Figure 9.2 Read Strobe Negation Timing (Example of 3-State Access Space)

9.2.5 CS Assertion Period Control Registers (CSACR)

CSACR selects whether or not the assertion periods of the chip select signals (CSn) and address signals for the basic bus, byte-control SRAM, burst ROM, and address/data multiplexed I/O interface are to be extended. Extending the assertion period of the CSn and address signals allows the setup time and hold time of read strobe (RD) and write strobe (LHWR/LLWR) to be assured and to make the write data setup time and hold time for the write strobe become flexible. Bit Bit Name Initial Value R/W CSXH7 R/W CSXH6 R/W CSXH5 R/W CSXH4 R/W CSXH3 R/W CSXH2 R/W CSXH1 R/W CSXH0 R/W Bit Bit Name Initial Value R/W CSXT7 R/W CSXT6 R/W CSXT5 R/W CSXT4 R/W CSXT3 R/W CSXT2 R/W CSXT1 R/W CSXT0 R/W

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 197 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description CSXH7 CSXH6 CSXH5 CSXH4 CSXH3 CSXH2 CSXH1 CSXH0 R/W R/W R/W R/W R/W R/W R/W R/W CS and Address Signal Assertion Period Control 1 These bits specify whether or not the Th cycle is to be inserted (see figure 9.3). When an area for which bit CSXHn is set to 1 is accessed, one Th cycle, in which the CSn and address signals are asserted, is inserted before the normal access cycle. 0: In access to area n, the CSn and address assertion period (Th) is not extended 1: In access to area n, the CSn and address assertion period (Th) is extended (n = 7 to 0) CSXT7 CSXT6 CSXT5 CSXT4 CSXT3 CSXT2 CSXT1 CSXT0 R/W R/W R/W R/W R/W R/W R/W R/W CS and Address Signal Assertion Period Control 2 These bits specify whether or not the Tt cycle is to be inserted (see figure 9.3). When an area for which bit CSXTn is set to 1 is accessed, one Tt cycle, in which the CSn and address signals are retained, is inserted after the normal access cycle. 0: In access to area n, the CSn and address assertion period (Tt) is not extended 1: In access to area n, the CSn and address assertion period (Tt) is extended (n = 7 to 0) Notes: In burst ROM interface, the CSXTn settings are ignored during read accesses by the CPU and EXDMAC* cluster transfer. * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 198 of 1438 REJ09B0365-0200 Read data Write data Bus cycle Th T1 T2 T3 Tt Bφ Address CSn AS BS RD/WR RD Read Write Data bus Data bus LHWR, LLWR Figure 9.3 CS and Address Assertion Period Extension (Example of Basic Bus Interface, 3-State Access Space, and RDNn = 0)

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9.2.6 Idle Control Register (IDLCR)

IDLCR specifies the idle cycle insertion conditions and the number of idle cycles. Bit Bit Name Initial Value R/W IDLS3 R/W IDLS2 R/W IDLS1 R/W IDLS0 R/W IDLCB1 R/W IDLCB0 R/W IDLCA1 R/W IDLCA0 R/W Bit Bit Name Initial Value R/W IDLSEL7 R/W IDLSEL6 R/W IDLSEL5 R/W IDLSEL4 R/W IDLSEL3 R/W IDLSEL2 R/W IDLSEL1 R/W IDLSEL0 R/W Bit Bit Name Initial Value R/W Description

15 IDLS3 1 R/W Idle Cycle Insertion 3

Inserts an idle cycle between the bus cycles when the DMAC or EXDMAC* single address transfer (write cycle) is followed by external access. 0: No idle cycle is inserted 1: An idle cycle is inserted

14 IDLS2 1 R/W Idle Cycle Insertion 2

Inserts an idle cycle between the bus cycles when the external write cycle is followed by external read cycle. 0: No idle cycle is inserted 1: An idle cycle is inserted

13 IDLS1 1 R/W Idle Cycle Insertion 1

Inserts an idle cycle between the bus cycles when the external read cycles of different areas continue. 0: No idle cycle is inserted 1: An idle cycle is inserted

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 200 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description

12 IDLS0 1 R/W Idle Cycle Insertion 0

Inserts an idle cycle between the bus cycles when the external read cycle is followed by external write cycle. 0: No idle cycle is inserted 1: An idle cycle is inserted IDLCB1 IDLCB0 R/W R/W Idle Cycle State Number Select B Specifies the number of idle cycles to be inserted for the idle condition specified by IDLS1 and IDLS0. 00: No idle cycle is inserted 01: 2 idle cycles are inserted 00: 3 idle cycles are inserted 01: 4 idle cycles are inserted IDLCA1 IDLCA0 R/W R/W Idle Cycle State Number Select A Specifies the number of idle cycles to be inserted for the idle condition specified by IDLS3 to IDLS0. 00: 1 idle cycle is inserted 01: 2 idle cycles are inserted 10: 3 idle cycles are inserted 11: 4 idle cycles are inserted IDLSEL7 IDLSEL6 IDLSEL5 IDLSEL4 IDLSEL3 IDLSEL2 IDLSEL1 IDLSEL0 R/W R/W R/W R/W R/W R/W R/W R/W Idle Cycle Number Select Specifies the number of idle cycles to be inserted for each area for the idle insertion condition specified by IDLS1 and IDLS0. 0: Number of idle cycles to be inserted for area n is specified by IDLCA1 and IDLCA0. 1: Number of idle cycles to be inserted for area n is specified by IDLCB1 and IDLCB0. (n = 7 to 0) Note: * Supported only by the groups H8 SX/1648G Group and the H8SX/1648H Group.

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9.2.7 Bus Control Register 1 (BCR1)

BCR1 is used for selection of the external bus released state protocol, enabling/disabling of the write data buffer function, and enabling/disabling of the WAIT pin input. Bit Bit Name Initial Value R/W BRLE R/W BREQOE R/W R R R/W R/W WDBE R/W WAITE R/W Bit Bit Name Initial Value R/W DKC R/W EDKC R/W R R R R R R Note: * Supported only by the H8SX/1648G Group and H8SX/1648H Group. Bit Bit Name Initial Value R/W Description

15 BRLE 0 R/W External Bus Release Enable

Enables/disables external bus release. 0: External bus release disabled BREQ , BACK, and BREQO pins can be used as I/O ports 1: External bus release enabled* For details, see section 13, I/O Ports.

14 BREQOE 0 R/W BREQO Pin Enable

Controls outputting the bus request signal (BREQO) to the external bus master in the external bus released state when an internal bus master performs an external address space access. 0: BREQO output disabled BREQO pin can be used as I/O port 1: BREQO output enabled 13, 12  All 0 R Reserved These are read-only bits and cannot be modified.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 202 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description 11, 10  All 0 R/W Reserved These bits are always read as 0. The write value should always be 0.

9 WDBE 0 R/W Write Data Buffer Enable

The write data buffer function can be used for an external write cycle and a DMAC single address transfer cycle. The changed setting may not affect an external access immediately after the change. 0: Write data buffer function not used 1: Write data buffer function used

8 WAITE 0 R/W WAIT Pin Enable

Selects enabling/disabling of wait input by the WAIT pin. When area 2 is specified as the synchronous DRAM space, the setting of this bit does not affect the synchronous DRAM space access operation. 0: Wait input by WAIT pin disabled WAIT pin can be used as I/O port 1: Wait input by WAIT pin enabled For details, see section 13, I/O Ports.

7 DKC 0 R/W DACK Control

Selects the timing of DMAC transfer acknowledge signal assertion. 0: DACK signal is asserted at the Bφ falling edge 1: DACK signal is asserted at the Bφ rising edge

6 EDKC * 0 R/W EDACK Control

Controls the assertion timing of an acknowledge signal for an EXDMAC transfer. 0: EDACK signal asserted at the falling edge of Bφ 1: EDACK signal asserted at the rising edge of Bφ 5 to 0  All 0 R Reserved These are read-only bits and cannot be modified. Notes: When external bus release is enabled or input by the WAIT pin is enabled, make sure to set the ICR bit to 1. For details, see section 13, I/O Ports. * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.

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9.2.8 Bus Control Register 2 (BCR2)

BCR2 is used for bus arbitration control of the CPU, DMAC, EXDMAC*, and DTC, and enabling/disabling of the write data buffer function to the peripheral modules. Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group. Bit Bit Name Initial Value R/W R R EBCCS* R/W IBCCS R/W R R R/W PWDBE R/W Note: * Supported only by the H8SX/1648G Group and H8SX/1648H Group. Bit Bit Name Initial Value R/W Description 7, 6  All 0 R Reserved These are read-only bits and cannot be modified.

5 EBCCS * 0 R/W External Bus Cycle Control Select

Selects the method for external bus arbitration. 0: Releases the bus depending on the priority 1: Executes the bus cycle alternatively when a conflict occurs between a bus request by the EXDMAC, external bus master or refresh bus and a request for an external space access by the CPU, DMAC, or DTC.

4 IBCCS 0 R/W Internal Bus Cycle Control Select

Selects the internal bus arbiter function. 0: Releases the bus mastership according to the priority 1: Executes the bus cycles alternatively when a CPU bus mastership request conflicts with a DMAC or DTC bus mastership request 3, 2  All 0 R Reserved These are read-only bits and cannot be modified. 1  1 R/W Reserved This bit is always read as 1. The write value should always be 1.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 204 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description

0 PWDBE 0 R/W Peripheral Module Write Data Buffer Enable

Specifies whether or not to use the write data buffer function for the peripheral module write cycles. 0: Write data buffer function not used 1: Write data buffer function used Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.

9.2.9 Endian Control Register (ENDIANCR)

ENDIANCR selects the endian format for each area of the external address space. Though the data format of this LSI is big endian, data can be transferred in the little endian format during external address space access. Note that the data format for the areas used as a program area or a stack area should be big endian. Bit Bit Name Initial Value R/W LE7 R/W LE6 R/W LE5 R/W LE4 R/W LE3 R/W LE2 R/W R R Bit Bit Name Initial Value R/W Description LE7 LE6 LE5 LE4 LE3 LE2 R/W R/W R/W R/W R/W R/W Little Endian Select Selects the endian for the corresponding area. 0: Data format of area n is specified as big endian 1: Data format of area n is specified as little endian (n = 7 to 2) 1, 0  All 0 R Reserved These are read-only bits and cannot be modified.

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9.2.10 SRAM Mode Control Register (SRAMCR)

SRAMCR specifies the bus interface of each area in the external address space as a basic bus interface or a byte control SRAM interface. In areas specified as 8-bit access space by ABWCR, the SRAMCR setting is ignored and the byte control SRAM interface cannot be specified. Bit Bit Name Initial Value R/W BCSEL7 R/W BCSEL6 R/W BCSEL5 R/W BCSEL4 R/W BCSEL3 R/W BCSEL2 R/W BCSEL1 R/W BCSEL0 R/W Bit Bit Name Initial Value R/W R R R R R R R R Bit Bit Name Initial Value R/W Description BCSEL7 BCSEL6 BCSEL5 BCSEL4 BCSEL3 BCSEL2 BCSEL1 BCSEL0 R/W R/W R/W R/W R/W R/W R/W R/W Byte Control SRAM Interface Select Selects the bus interface for the corresponding area. When setting a bit to 1, the bus interface select bits in BROMCR, DRAMCR* and MPXCR must be cleared to 0: Area n is basic bus interface 1: Area n is byte control SRAM interface (n = 7 to 0) 7 to 0  All 0 R Reserved These are read-only bits and cannot be modified. Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.

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9.2.11 Burst ROM Interface Control Register (BROMCR)

BROMCR specifies the burst ROM interface. Bit Bit Name Initial Value R/W BSRM0 R/W BSTS02 R/W BSTS01 R/W BSTS00 R/W R R BSWD01 R/W BSWD00 R/W Bit Bit Name Initial Value R/W BSRM1 R/W BSTS12 R/W BSTS11 R/W BSTS10 R/W R R BSWD11 R/W BSWD10 R/W Bit Bit Name Initial Value R/W Description

15 BSRM0 0 R/W Area 0 Burst ROM Interface Select

Specifies the area 0 bus interface. To set this bit to 1, clear bit BCSEL0 in SRAMCR to 0. 0: Basic bus interface or byte-control SRAM interface 1: Burst ROM interface BSTS02 BSTS01 BSTS00 R/W R/W R/W Area 0 Burst Cycle Select Specifies the number of burst cycles of area 0 000: 1 cycle 001: 2 cycles 010: 3 cycles 011: 4 cycles 100: 5 cycles 101: 6 cycles 110: 7 cycles 111: 8 cycles 11, 10  All 0 R Reserved These are read-only bits and cannot be modified.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 207 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description BSWD01 BSWD00 R/W R/W Area 0 Burst Word Number Select Selects the number of words in burst access to the area 0 burst ROM interface 00: Up to 4 words (8 bytes) 01: Up to 8 words (16 bytes) 10: Up to 16 words (32 bytes) 11: Up to 32 words (64 bytes)

7 BSRM1 0 R/W Area 1 Burst ROM Interface Select

Specifies the area 1 bus interface as a basic interface or a burst ROM interface. To set this bit to 1, clear bit BCSEL1 in SRAMCR to 0. 0: Basic bus interface or byte-control SRAM interface 1: Burst ROM interface BSTS12 BSTS11 BSTS10 R/W R/W R/W Area 1 Burst Cycle Select Specifies the number of cycles of area 1 burst cycle 000: 1 cycle 001: 2 cycles 010: 3 cycles 011: 4 cycles 100: 5 cycles 101: 6 cycles 110: 7 cycles 111: 8 cycles 3, 2  All 0 R Reserved These are read-only bits and cannot be modified. BSWD11 BSWD10 R/W R/W Area 1 Burst Word Number Select Selects the number of words in burst access to the area 1 burst ROM interface 00: Up to 4 words (8 bytes) 01: Up to 8 words (16 bytes) 10: Up to 16 words (32 bytes) 11: Up to 32 words (64 bytes)

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9.2.12 Address/Data Multiplexed I/O Control Register (MPXCR)

MPXCR specifies the address/data multiplexed I/O interface. Bit Bit Name Initial Value R/W MPXE7 R/W MPXE6 R/W MPXE5 R/W MPXE4 R/W MPXE3 R/W R R R Bit Bit Name Initial Value R/W R R R R R R R ADDEX R/W Bit Bit Name Initial Value R/W Description MPXE7 MPXE6 MPXE5 MPXE4 MPXE3 R/W R/W R/W R/W R/W Address/Data Multiplexed I/O Interface Select Specifies the bus interface for the corresponding area. To set this bit to 1, clear the BCSELn bit in SRAMCR to 0: Area n is specified as a basic interface or a byte control SRAM interface. 1: Area n is specified as an address/data multiplexed I/O interface (n = 7 to 3) 10 to 1  All 0 R Reserved These are read-only bits and cannot be modified.

0 ADDEX 0 R/W Address Output Cycle Extension

Specifies whether a wait cycle is inserted for the address output cycle of address/data multiplexed I/O interface. 0: No wait cycle is inserted for the address output cycle 1: One wait cycle is inserted for the address output cycle

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9.2.13 DRAM Control Register (DRAMCR)

DRAMCR specifies the DRAM/SDRAM interface. Rewrite this register while the DRAM/SDRAM is not accessed. Bit Bit Name Initial Value R/W DRAME R/W DTYPE R/W R R OEE R/W RAST R/W R CAST R/W Bit Bit Name Initial Value R/W BE R/W RCDM R/W DDS R/W EDDS R/W R R/W MXC1 R/W MXC0 R/W Bit Bit Name Initial Value R/W Description

15 DRAME 0 R/W Area 2 DRAM Interface Select

Selects whether or not area 2 is specified as the DRAM/SDRAM interface. When this bit is set to 1, select the type of DRAM to be used in area 2 with the DTYPE bit. When this bit is set to 1, the BCSEL2 bit in SRAMCR should be set to 0. 0: Basic bus interface or byte-control SRAM interface 1: DRAM/SDRAM interface

14 DTYPE 0 R/W DRAM Select

Selects the type of DRAM to be used in area 2. 0: DRAM is used in area 2 1: SDRAM is used in area 2 13, 12  All 0 R Reserved The initial value should not be changed.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 210 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description

11 OEE 0 R/W OE Output Enable

The OE signal is output when DRAM with the EDO page mode is connected, whereas the CKE signal is output when SDRAM is connected. 0: OE/CKE signal output disabled (the OE/CKE pin can be used as an I/O port) 1: OE/CKE signal enabled

10 RAST 0 R/W RAS Assertion Timing Select

Selects whether the RAS signal is asserted at the rising edge or falling edge of the Bφ signal in the Tr cycle during a DRAM access. The relationship between this bit and RAS assertion timing is shown in figure 9.4. When SDRAM is used, the setting of this bit does not affect operation. 0: RAS signal is asserted at the falling edge of the Bf signal in the Tr cycle 1: RAS signal is asserted at the rising edge of the Bf signal in the Tr cycle 9  0 R Reserved The initial value should not be changed.

8 CAST 0 R/W Column Address Output Cycle Count Select

Selects whether the number of column address output cycles is two or three during a DRAM access. When SDRAM is used, the setting of this bit does not affect operation. 0: Column address is output for two cycles 1: Column address is output for three cycles

7 BE 0 R/W Burst Access Enable

Enables or disables a burst access to the DRAM/SDRAM. The DRAM/SDRAM is accessed in high-speed page mode. When DRAM with the EDO page mode is used, connect the OE signal of this LSI to the OE signal of DRAM. 0: DRAM/SDRAM is accessed with full access 1: DRAM/SDRAM is accessed in high-speed page mode

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 211 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description

6 RCDM 0 R/W RAS Down Mode

Selects the RAS signal state while a DRAM access is halted when a basic bus interface area or an on-chip I/O register is accessed: keep the RAS signal low (RAS down mode) and high (RAS up mode). This bit is effective when BE = 1. Clearing this bit to 0 with RCDM = 1 in RAS down mode cancels the RAS down mode and the RAS signal goes high. If the RAS down mode is selected for the SDRAM interface, the READ/WRIT command is issued without issuance of the ACTV command when the same row address is accessed consecutively. 0: RAS up mode when the DRAM/SDRAM is accessed 1: RAS down mode when the DRAM/SDRAM is accessed

5 DDS 0 R/W DMAC Single Address Transfer Option

Selects whether a DMAC single address transfer through the DRAM/SDRAM interface is enabled only in full access mode or is also enabled in fast-page access mode. When clearing the BE bit to 0 to disable a burst access to the DRAM/SDRAM interface, a DMAC single address transfer is performed in full access mode regardless of this bit. This bit does not affect an external access by other bus masters or a DMAC dual address transfer. Setting this bit to 1 changes the DACK output timing. 0: DMAC single address transfer through the DRAM/SDRAM is enabled only in full access mode 1: DMAC single address transfer through the DRAM/SDRAM is also enabled in fast-page access mode

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 212 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description

4 EDDS 0 R/W EXDMAC Single Address Transfer Option

Selects whether an EXDMAC single address transfer through the DRAM/SDRAM interface is enabled only in full access mode or is also enabled in fast-page access mode. When clearing the BE bit to 0 to disable a burst access to the DRAM/SDRAM interface, an EXDMAC single address transfer is performed in full access mode regardless of this bit. This bit does not affect an external access by other bus masters or an EXDMAC dual address transfer. Setting this bit to 1 changes the EDACK output timing. 0: EXDMAC single address transfer through the DRAM/SDRAM is enabled only in full access mode 1: EXDMAC single address transfer through the DRAM/SDRAM is also enabled in fast-page access mode R R/W Reserved The initial value should not be changed.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 213 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description MCX1 MCX0 R/W R/W Multiplexed Address Bit Select Select the number of bits by which a row address multiplexed with a column address is shifted to the lower side. At the same time, these bits select row address bits compared during a burst access to the DRAM/SDRAM interface. 00: Shifted by 8 bits A23 to A8 are compared for 8-bit access space A23 to A9 are compared for 16-bit access space 01: Shifted by 9 bits A23 to A9 are compared for 8-bit access space A23 to A10 are compared for 16-bit access space 10: Shifted by 10 bits A23 to A10 are compared for 8-bit access space A23 to A11 are compared for 16-bit access space 11: Shifted by 11 bits A23 to A11 are compared for 8-bit access space A23 to A12 are compared for 16-bit access space Note: Supported only by the H8SX/1 648G Group and the H8SX/1648H Group. Bφ Address RAS (When RAST = 0) RAS (When RAST = 1) LUCAS, LLCAS Tp Tr Tc1 Tc2 Row address Column address Bus cycle Note: Supported only by the H8SX/1648G Group and the H8SX/1648H Group. Figure 9.4 RAS Assertion Timing (Column Address Output for 2 states in Full Access Mode)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 214 of 1438 REJ09B0365-0200

9.2.14 DRAM Access Co ntrol Register (DRACCR)

DRACCR specifies the settings for the DRAM/SDRAM interface. Rewrite this register while the DRAM/SDRAM is not accessed. Bit Bit Name Initial Value R/W R R TPC1 R/W TPC0 R/W R R RCD1 R/W RCD0 R/W Bit Bit Name Initial Value R/W R R R R R R R R Bit Bit Name Initial Value R/W Description 15, 14  All 0 R Reserved The initial value should not be changed. TPC1 TPC0 R/W R/W Precharge Cycle Control Select the number of RAS precharge cycles on a normal access and a refresh cycle. 00: One cycle 01: Two cycles 10: Three cycles 11: Four cycles 11, 10  All 0 R Reserved The initial value should not be changed. RCD1 RCD0 R/W R/W RAS-CAS Wait Control Select the number of wait cycles inserted between RAS and CAS cycles. 00: No wait cycle inserted 01: One wait cycle inserted 10: Two wait cycles inserted 11: Three wait cycles inserted 7 to 0  All 0 R Reserved The initial value should not be changed. Note: Supported only by the H8SX/1 648G Group and the H8SX/1648H Group.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 215 of 1438 REJ09B0365-0200

9.2.15 Synchronous DRAM Control Register (SDCR)

SDCR specifies the settings for the SDRAM interface (when the DTYPE bit in DRAMCR is set to 1). Rewrite this register while the SDRAM is not accessed. When the SDRAM interface is not used, the initial value must not be changed. Bit Bit Name Initial Value R/W MRSE R/W R R R R/W R/W R R/W Bit Bit Name Initial Value R/W CKSPE R/W R R R R R R TRWL R/W Bit Bit Name Initial Value R/W Description

15 MRSE 0 R/W Mode Register Set Enable

Enables the setting in the SDRAM mode register. See section 9.11.14, Setting SDRAM Mode Register. 0: Disables to set the SDRAM mode register 1: Enables to set the SDRAM mode register 14 to 12  All 0 R Reserved These bits are always read as 0. The initial value should not be changed. 11, 10  0 R/W Reserved The initial value should not be changed. R R/W Reserved The initial value should not be changed.

7 CKSPE 0 R/W Clock Suspend Enable

Enables the clock suspend mode in which read data output cycles are extended. Setting this bit to 1 extends cycles in which read data is output from SDRAM. 0: Disables the clock suspend mode 1: Enables the clock suspend mode

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 216 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description 6 to 1  All 0 R Reserved The initial value should not be changed.

0 TRWL 0 R/W Write-Precharge Delay Control

Specifies the time until the precharge command is issued after the write command is issued to the SDRAM. Setting this bit to 1 inserts one wait cycle after the write command is issued. 0: No wait cycle inserted 1: One wait cycle inserted Note: Supported only by the H8SX/1 648G Group and the H8SX/1648H Group.

9.2.16 Refresh Control Register (REFCR)

REFCR specifies the refresh type for the DRAM/SDRAM interface. Bit Bit Name Initial Value R/W CMF R/(W)* CMIE R/W RCW1 R/W RCW0 R/W R RTCK2 R/W RTCK1 R/W RTCK0 R/W Bit Bit Name Initial Value R/W Note: * Only 0 can be written to this bit, to clear the flag. RFSHE R/W RLW2 R/W RLW1 R/W RLW0 R/W SLFRF R/W TPCS2 R/W TPCS1 R/W TPCS0 R/W

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 217 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description

15 CMF 0 R/(W) * Compare Match Flag

Indicates that the refresh timer counter (RTCNT) and refresh timer constant register (RTCOR) match. [Clearing conditions]

• When 0 is written to this bit after this bit is read as 1 with RFSHE = 0
• When CBR refresh is performed with RFSHE = 1 [Setting condition]
• When RTCNT matches RTCOR

14 CMIE 0 R/W Compare Match Interrupt Enable

Enables or disables an interrupt request (CMI) when the CMF flag is set to 1. This bit is effective when refresh control is not performed (RFSHE = 0). When refresh control is performed (RFSHE = 1), this bit is always cleared to 0. This bit cannot be modified. 0: Interrupt requests by the CMF flag disabled 1: Interrupt requests by the CMF flag enabled 13 to 12 RCW1 RCW0 R/W R/W CAS-RAS Wait Control Select the number of wait cycles inserted between the CAS asserted cycle and CAS asserted cycle during DRAM refresh. When the SDRAM space is selected, these bits do not affect operations although they can be read from or written to. 00: No wait cycle inserted 01: One wait cycle inserted 10: Two wait cycles inserted 11: Three wait cycles inserted 11  0 R Reserved The initial value should not be changed.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 218 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description RTCK2 RTCK1 RTCK0 R/W R/W R/W Refresh Counter Clock Select Select the clock used to count up the refresh counter from the seven internal clocks generated by dividing the on-chip peripheral module clock (Pφ). When the clock is selected, the refresh counter starts to count up. 000: Counting halted 001: Counts on Pφ/2 010: Counts on Pφ/8 011: Counts on Pφ/32 100: Counts on Pφ/128 101: Counts on Pφ/512 110: Counts on Pφ/2048 111: Counts on Pφ/4096

7 RFSHE 0 R/W Refresh Control

Enables or disables refresh control. When refresh control is disabled, the refresh timer can be used as the interval timer. In single-chip activation mode, the setting of this bit should be made after setting the EXPE bit in SYSCR to 1. For SYSCR, see section 3, MCU Operating Modes. 0: Refresh control enabled 1: Refresh control disabled RLW2 RLW1 RLW0 R/W R/W R/W Refresh Cycle Wait Control Select the number of wait cycles during a CAS before RAS refresh cycle for the DRAM interface and an auto- refresh cycle for the SDRAM interface. 000: No wait cycle inserted 001: One wait cycle inserted 010: Two wait cycles inserted 010: Three wait cycles inserted 010: Four wait cycles inserted 010: Five wait cycles inserted 010: Six wait cycles inserted 010: Seven wait cycles inserted

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 219 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description

3 SLFRF 0 R/W Self-Refresh Enable

Selects the self-refresh mode for the DRAM/SDRAM interface when a transition to the software standby mode is made with this bit set to 1. To perform a refresh cycle by setting the RFSHE bit is set to 1, this bit is effective. To perform a self-refresh cycle when the SDRAM interface is selected, enable the CKE output by setting the OEE bit in DRAMCR. 0: Disables self-refresh 1: Enables self-refresh TPCS2 TPCS1 TPCS0 R/W R/W R/W Precharge Cycle Control during Self-Refresh Selects the number of precharge cycles immediately after a self-refresh cycle. The number of actual number of precharge cycles is the sum of the numbers indicated by these bits and bits TPC1 and TPC0. 000: No wait cycle inserted 001: One wait cycle inserted 010: Two wait cycles inserted 011: Three wait cycles inserted 100: Four wait cycles inserted 101: Five wait cycles inserted 110: Six wait cycles inserted 111: Seven wait cycles inserted Notes: * Only 0 can be written to this bit, to clear the flag. Supported only by the H8SX/1648G Group and the H8SX/1648H Group.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 220 of 1438 REJ09B0365-0200

9.2.17 Refresh Time r Counter (RTCNT)

RTCNT counts up on the internal clock selected by bits RTCK2 to RTCK0 in REFCR. When the RTCNT value matches the RTCOR value (compare match), the CMF flag in REFCR is set to 1 and RTCNT is initialized to H'00. At this time, when the RFSHE bit in REFCR is set to 1, a refresh cycle is generated. When the RFSHE bit is cleared to 0 and the CMIE bit in REFCR is set to 1, a compare match interrupt (CMI) is generated. Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Supported only by the H8SX/1648G Group and the H8SX/1648H Group.

9.2.18 Refresh Time Constant Register (RTCOR)

RTCOR specifies intervals at which a compare match for RTCOR and RTCNT is generated. The RTCOR value is always compared with the RTCNT value. When they match, the CMF flag in REFCR is set to 1 and RTCNT is initialized to H'00. Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Supported only by the H8SX/1648G Group and the H8SX/1648H Group.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 221 of 1438 REJ09B0365-0200

9.3 Bus Configuration

Figure 9.5 shows the internal bus configuration of this LSI. The internal bus of this LSI consists of the following three types. 1. Internal system bus 1: A bus that connects the CPU, DTC, DMAC, on-chip RAM, on-chip ROM, internal peripheral bus, and external access bus. 2. Internal system bus 2*: A bus that connects the EXDMAC and external access bus 3. Internal peripheral bus: A bus that accesses re gisters in the bus controller, interrupt controller, DMAC, and EXDMAC*, and registers of peripheral modules such as SCI and timer. 4. External access bus: A bus that accesses exte rnal devices via the external bus interface. Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group. CPU DTC DMAC B φ synchronization P φ synchronization I φ synchronization Bus controller, interrupt controller, power-down controller External bus interface Peripheral functions On-chip RAM On-chip ROM Internal system bus 1 Internal peripheral bus Write data buffer Write data buffer External access bus Internal system bus 2* EXDMAC* Note: * Supported only by the H8SX/1648G Group and H8SX/1648H Group. Figure 9.5 Internal Bus Configuration

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 222 of 1438 REJ09B0365-0200

9.4 Multi-Clock Function and Number of Access Cycles

The internal functions of this LSI operate synchronously with the system clock (Iφ), the peripheral module clock (Pφ), or the external bus clock (Bφ). Table 9.1 shows the synchronization clock and their corresponding functions. Table 9.1 Synchronization Clocks and Their Corresponding Functions Synchronization Clock Function Name Iφ MCU operating mode Interrupt controller Bus controller CPU DTC DMAC EXDMAC* Internal memory Clock pulse generator Power down control Pφ I/O ports TPU PPG TMR WDT SCI A/D D/A IIC2 Bφ External bus interface Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group. The frequency of each synchronization clock (Iφ, Pφ, and Bφ) is specified by the system clock control register (SCKCR) independently. For further details, see section 26, Clock Pulse Generator. There will be cases when Pφ and Bφ are equal to Iφ and when Pφ and Bφ are different from Iφ according to the SCKCR specifications. In any case, access cycles for internal peripheral functions and external space is performed synchronously with Pφ and Bφ, respectively.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 224 of 1438 REJ09B0365-0200 Divided clock synchronization cycle T Address Iφ Bφ AS CSn RD D15 to D8 D7 to D0 D15 to D8 D7 to D0 Read LHWR LLWR Write T2Tsy BS RD/WR Figure 9.6 System Clock: External Bus Clock = 4:1, External 2-State Access

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 225 of 1438 REJ09B0365-0200 Divided clock synchronization cycle T Address Iφ Bφ AS CSn RD D15 to D8 D7 to D0 D15 to D8 D7 to D0 Read LHWR LLWR Write T2Tsy T3 BS RD/WR Figure 9.7 System Clock: External Bus Clock = 2:1, External 3-State Access

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 226 of 1438 REJ09B0365-0200

9.5 External Bus

9.5.1 Input/Output Pins

Table 9.2 shows the pin configuration of the bus controller and table 9.3 shows the pin functions on each interface. Table 9.2 Pin Configuration Name Symbol I/O Function Bus cycle start BS Output Signal indicating that the bus cycle has started Address strobe/ address hold AS/AH Output • Strobe signal indicating that the basic bus, byte control SRAM, or burst ROM space is accessed and address output on address bus is enabled

• Signal to hold the address during access to the address/data multiplexed I/O interface Read strobe RD Output Strobe signal indicating t hat the basic bus, byte control SRAM, burst ROM, or address/data multiplexed I/O space is being read Read/write RD/ WR Output • Signal indicating the input or output direction
• Write enable signal of the SRAM during access to the byte control SRAM space Low-high write/ lower-upper byte select LHWR/LUB Output • Strobe signal indicating that the basic bus, burst ROM, or address/data multiplexed I/O space is written to, and the upper byte (D15 to D8) of data bus is enabled
• Strobe signal indicating that the byte control SRAM space is accessed, and the upper byte (D15 to D8) of data bus is enabled Low-low write/ lower-lower byte select LLWR/LLB Output • Strobe signal indicating that the basic bus, burst ROM, or address/data multiplexed I/O space is written to, and the lower byte (D7 to D0) of data bus is enabled
• Strobe signal indicating that the byte control SRAM space is accessed, and the lower byte (D7 to D0) of data bus is enabled

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 227 of 1438 REJ09B0365-0200 Name Symbol I/O Function Chip select 0 CS0 Output Strobe signal indicating that area 0 is selected Chip select 1 CS1 Output Strobe signal indicating that area 1 is selected Chip select 2 CS2 Output Strobe signal indicating that area 2 is selected Chip select 3 CS3 Output Strobe signal indicating that area 3 is selected Chip select 4 CS4 Output Strobe signal indicating that area 4 is selected Chip select 5 CS5 Output Strobe signal indicating that area 5 is selected Chip select 6 CS6 Output Strobe signal indicating that area 6 is selected Chip select 7 CS7 Output Strobe signal indicating that area 7 is selected Row address strobe* RAS Output • Row address strobe signal when area 2 is specified as DRAM space

• Row address strobe signal when area 2 is specified as SDRAM space Column address strobe* CAS Output Column address strobe signal when area 2 is specified as SDRAM space Write enable* WE Output • Write enable signal for DRAM
• Write enable signal when area 2 is specified as SDRAM space Lower-upper-column address strobe/lower-upper-data mask enable* LUCAS/ DQMLU Output • Lower-upper-column address strobe signal for 32- bit DRAM
• Upper-column address strobe signal for 16-bit DRAM
• Lower-upper-data mask enable signal for 32-bit SDRAM
• Upper-data mask enable signal for 16-bit SDRAM Lower-lower-column address strobe/lower-lower-data mask enable* LLCAS/ DQMLL Output • Lower-lower-column address strobe signal for 32- bit DRAM
• Lower-column address strobe signal for 16-bit DRAM
• Column address strobe signal for 8-bit DRAM
• Lower-lower-data mask enable signal for 32-bit SDRAM
• Lower-data mask enable signal for 16-bit SDRAM
• Data mask enable signal for 8-bit SDRAM

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 228 of 1438 REJ09B0365-0200 Name Symbol I/O Function Output enable/clock enable* OE/CKE Output • Output enable signal for DRAM

• Clock enable signal for SDRAM SDRAMφ* SDRAM φ Output SDRAM dedicated clock Wait WAIT Input Wait request signal w hen accessing external address space Bus request BREQ Input Request signal for release of bus to external bus master Bus request acknowledge BACK Output Acknowledge signal i ndicating that bus has been released to external bus master Bus request output BREQO Output External bus request signal used when internal bus master accesses external address space in the external-bus released state Data transfer acknowledge 3 (DMAC_3) DACK3 Output Data acknowledge si gnal for DMAC_3 single address transfer Data transfer acknowledge 2 (DMAC_2 DACK2 Output Data acknowledge si gnal for DMAC_2 single address transfer Data transfer acknowledge 1 (DMAC_1) DACK1 Output Data acknowledge si gnal for DMAC_1 single address transfer Data transfer acknowledge 0 (DMAC_0) DACK0 Output Data acknowledge si gnal for DMAC_0 single address transfer Data transfer acknowledge 3 (EXDMAC_3)* EDACK3 Output Data acknowledge signal for EXDMAC_3 single address transfer Data transfer acknowledge 2 (EXDMAC_2)* EDACK2 Output Data acknowledge signal for EXDMAC_2 single address transfer Data transfer acknowledge 1 (EXDMAC_1)* EDACK1 Output Data acknowledge signal for EXDMAC_1 single address transfer Data transfer acknowledge 0 (EXDMAC_0)* EDACK0 Output Data acknowledge signal for EXDMAC_0 single address transfer External bus clock B φ Output External bus clock Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 229 of 1438 REJ09B0365-0200 Table 9.3 Pin Functions in Each Interface Pin Name Bφ SDRAMφ∗ CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 BS RD/WR AS AH RD LHWR/LUB LLWR/LLB RAS* CAS* WE* LUCAS/DQMLU* LLCAS/DQMLL* OE* CKE* WAIT O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O Output (Output) Output Output Output Output Output Output (Output) Output Output Output Output Output Controlled by MD3 [Legend] O: Used as bus control signal. : Not used as bus control signal (I/O port as initial state). Initial State Basic Bus Byte-Control SRAM DRAM* SDRAM* Burst ROM Address/Data Multiplexed I/O Controlled by DRAME and OEE Controlled by WAITE Controlled by DRAME and OEE RemarksSingle Chip Note: * Supported only by the H8SX/1648G Group and H8SX/1648H Group.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 230 of 1438 REJ09B0365-0200

9.5.2 Area Division

The bus controller divides the 16-Mbyte address space into eight areas, and performs bus control for the external address space in area units. Chip select signals (CS0 to CS7) can be output for each area. Figure 9.8 shows an area division of the 16-Mbyte address space. For details on address map, see section 3, MCU Operating Modes. 16-Mbyte space Area 0 (2 Mbytes) Area 1 (2 Mbytes) Area 2 (8 Mbytes) Area 3 (2 Mbytes) Area 4 (1 Mbyte) Area 5 (1 Mbyte − 8 kbytes) Area 6 (8 kbytes − 256 bytes) Area 7 (256 bytes) H'000000 H'1FFFFF H'200000 H'3FFFFF H'400000 H'BFFFFF H'C00000 H'DFFFFF H'E00000 H'EFFFFF H'F00000 H'FFDFFF H'FFE000 H'FFFEFF H'FFFF00 H'FFFFFF Figure 9.8 Address Space Area Division

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 231 of 1438 REJ09B0365-0200

9.5.3 Chip Select Signals

This LSI can output chip select signals (CS0 to CS7) for areas 0 to 7. The signal outputs low when the corresponding external address space area is accessed. Figure 9.9 shows an example of CSn (n = 0 to 7) signal output timing. Enabling or disabling of CSn signal output is set by the port function control register (PFCR). For details, see section 13.3, Port Function Controller. In on-chip ROM disabled extended mode, pin CS0 is placed in the output state after a reset. Pins CS1 to CS7 are placed in the input state after a reset and so the corresponding PFCR bits should be set to 1 when outputting signals CS1 to CS7. In on-chip ROM enabled extended mode, pins CS0 to CS7 are all placed in the input state after a reset and so the corresponding PFCR bits should be set to 1 when outputting signals CS0 to CS7. The PFCR can specify multiple CS outputs for a pin. If multiple CSn outputs are specified for a single pin by the PFCR, CS to be output are generated by mixing all the CS signals. In this case, the settings for the external bus interface areas in which the CSn signals are output to a single pin should be the same. Figure 9.10 shows the signal output timing when the CS signals to be output to areas 5 and 7 are output to the same pin. Bus cycle T1 T2 T3 External address of area nAddress bus Bφ CSn Figure 9.9 CSn Signal Output Timing (n = 0 to 7)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 232 of 1438 REJ09B0365-0200 Output waveform Bφ Area 5 access CS6 CS5 Area 6 access Area 5 access Area 6 accessAddress bus Figure 9.10 Timing When CS Signal is Output to the Same Pin

9.5.4 External Bus Interface

The type of the external bus interfaces, bus width, endian format, number of access cycles, and strobe assert/negate timings can be set for each area in the external address space. The bus width and the number of access cycles for both on-chip memory and internal I/O registers are fixed, and are not affected by the external bus settings. (1) Type of External Bus Interface Six types of external bus interfaces are provided and can be selected in area units. Table 9.4 shows each interface name, description, area name to be set for each interface. Table 9.5 shows the areas that can be specified for each interface. The initial state of each area is a basic bus interface.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 233 of 1438 REJ09B0365-0200 Table 9.4 Interface Names and Area Names Interface Description Area Name Basic interface Directly connected to ROM and RAM Basic bus space Byte control SRAM interface Directly connected to byte SRAM with byte control pin Byte control SRAM space Burst ROM interface Directly connected to the ROM that allows page access Burst ROM space Address/data multiplexed I/O interface Directly connected to the peripheral LSI that requires address and data multiplexing Address/data multiplexed I/O space DRAM interface* Directly connected to DRAM DRAM space Synchronous DRAM interface* Directly connected to synchronous DRAM Synchronous DRAM space Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group. Table 9.5 Areas Specifiable for Each Interface Areas Interface Related Registers 0 1 2 3 4 5 6 7 Basic interface O O O O O O O O Byte control SRAM interface SRAMCR O O O O O O O O Burst ROM interface BROMCR O O       Address/data multiplexed I/O interface MPXCR    O O O O O Synchronous DRAM interface* DRAMCR Note: * Supported only by the H8SX/1648LGroup and the H8SX/1648H Group.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 234 of 1438 REJ09B0365-0200 (2) Bus Width A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit bus is selected functions as an 8-bit access space and an area for which a 16-bit bus is selected functions as a 16-bit access space. In addition, the bus width of address/data multiplexed I/O space is 8 bits or 16 bits, and the bus width for the byte control SRAM space is 16 bits. The initial state of the bus width is specified by the operating mode. If all areas are designated as 8-bit access space, 8-bit bus mode is set; if any area is designated as 16-bit access space, 16-bit bus mode is set. (3) Endian Format Though the endian format of this LSI is big endian, data can be converted into little endian format when reading or writing to the external address space. Areas 7 to 2 can be specified as either big endian or little endian format by the LE7 to LE2 bits in ENDIANCR. The initial state of each area is the big endian format. Note that the data format for the areas used as a program area or a stack area should be big endian.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 235 of 1438 REJ09B0365-0200 (4) Number of Access Cycles (a) Basic Bus Interface The number of access cycles in the basic bus interface can be specified as two or three cycles by the ASTCR. An area specified as 2-state access is specified as 2-state access space; an area specified as 3-state access is specified as 3-state access space. For the 2-state access space, a wait cycle insertion is disabled. For the 3-state access space, a program wait (0 to 7 cycles) specified by WTCRA and WTCRB or an external wait by WAIT can be inserted. Assertion period of the chip select signal can be extended by CSACR. Number of access cycles in the basic bus interface = number of basic cycles (2, 3) + number of program wait cycles (0 to 7) + number of CS extension cycles (0, 1, 2) [+ number of external wait cycles by the WAIT pin] (b) Byte Control SRAM Interface The number of access cycles in the byte control SRAM interface is the same as that in the basic bus interface. Number of access cycles in byte control SRAM interface = number of basic cycles (2, 3) + number of program wait cycles (0 to 7) + number of CS extension cycles (0, 1, 2) [+ number of external wait cycles by the WAIT pin] (c) Burst ROM Interface The number of access cycles at full access in the burst ROM interface is the same as that in the basic bus interface. The number of access cycles in the burst access can be specified as one to eight cycles by the BSTS bit in BROMCR. Number of access cycles in the burst ROM interface = number of basic cycles (2, 3) + number of program wait cycles (0 to 7) + number of CS extension cycles (0, 1) [+number of external wait cycles by the WAIT pin] + number of burst access cycles (1 to 8) × number of burst accesses (0 to 63)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 236 of 1438 REJ09B0365-0200 (d) Address/data multiplexed I/O interface The number of access cycles in data cycle of the address/data multiplexed I/O interface is the same as that in the basic bus interface. The number of access cycles in address cycle can be specified as two or three cycles by the ADDEX bit in MPXCR. Number of access cycles in the address/data multiplexed I/O interface = number of address output cycles (2, 3) + number of data output cycles (2, 3) + number of program wait cycles (0 to 7) + number of CS extension cycles (0, 1, 2) [+number of external wait cycles by the WAIT pin] (e) DRAM Interface In the DRAM interface, the numbers of precharge cycles, row address output cycles, and column address output cycles can be specified. The number of precharge cycles can be specified as one to four cycles by bits TPC1 and TPC0 in DRACCR. The number of row address output cycles can be specified as one to four cycles by bits RCD1 and RCD0 in DRACCR. The number of column address output cycles can be specified as two or three cycles by the CAST bit in DRAMCR. For the column address output cycle, program wait (0 to 7 cycles) specified by WTCRB or external wait by WAIT can be inserted. Number of access cycles in the DRAM interface = number of precharge cycles (1 to 4) + number of row address output cycles (1 to 4) + number of column address output cycles (2 or 3) + number of program wait cycles (0 to 7) [+number of external wait cycles by the WAIT pin] Note: Supported only by the H8SX/1648G Group and the H8SX/1648H Group. (f) SDRAM Interface In the SDRAM interface, the numbers of precharge cycles, row address output cycles, and column address output cycles, as well as clock suspend and write-precharge delay, can be specified by DRACCR and WTCRB. The number of precharge cycles can be specified as one to four cycles by bits TPC1 and TPC0 in DRACCR. The number of row address output cycles can be specified as one to four cycles by bits RCD1 and RCD0 in DRACCR. The number of column address output cycles during read access can be specified as two to four cycles by bits W21 and W20 in WTCRB. The cycles for clock suspend and write-precharge delay can be inserted by bits CKSPE and TRWL in SDCR.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 237 of 1438 REJ09B0365-0200 Number of access cycles in the SDRAM interface = number of precharge cycles (1 to 4) + number of row address output cycles (1 to 4) + number of column address output cycles (read: 2 to 4, write: 2) + number of clock suspend cycles (only read: 0 or 1) + number of write precharge delay cycles (only write: 0 or 1) Note: Supported only by the H8SX/1 648G Group and the H8SX/1648H Group. Table 9.6 lists the number of access cycles for each interface. Table 9.6 Number of Access Cycles [Legend] Number enclosed by bracket: Number of access cycles n: Pin wait (0 to ∞) m: Number of burst accesses (0 to 63) s: Time for a transition to or from software standby mode Basic bus interface Byte-control SRAM interface Burst ROM interface Address/data multiplexed I/O interface DRAM inter- face* SDRAM interface* Full access Fast page Refresh Self-refresh Setting mode register Full access (read) Full access (write) Page access (read) Page access (write) Cluster transfer (read) Cluster transfer (write) Refresh Self-refresh =Tma [2,3] =Tma [2,3] =Tp [1 to 4] =TRp [1 to 4] =TRp [1 to 4] Th [0,1] Th [0,1] Th [0,1] Th [0,1] Th [0,1] Th [0,1] +Th [0,1] +Th [0,1] +Tr [1] +TRrw [0 to 3] +TRrw [0 to 3] Tp [1 to 4] Tp [1 to 4] Tp [1 to 4] Tp [1 to 4] Tp [1 to 4] TRp [1 to 4] TRp [1 to 4] +T1 [1] +T1 [1] +T1 [1] +T1 [1] +T1 [1] +T1 [1] +T1 [1] +T1 [1] +Trw [0 to 3] +TRr [1] +TRr [1] +Tr [1] +Tr [1] +Tr [1] +Tr [1] +Tr [1] +TRr [1] +TRr [1] +T2 [1] +T2 [1] +T2 [1] +T2 [1] +T2 [1] +T2 [1] +T2 [1] +T2 [1] +TC1 [1] TC1 [1] +TRc1 [1] +Trw [0 to 3] +Trw [0 to 3] +Trw [0 to 3] +Trw [0 to 3] +Trw [0 to 3] +TRc1 [1] +Tt [0,1] +Tt [0,1] +Tt [0,1] +Tt [0,1] +Tt [0,1] +Tt [0,1] +Tc3 [0,1] +Tc3 [0,1] +TRc4 [1] +Tsp [0,1] +Tsp [0,1] +TRp [0 to 7] [2 to 4] [3 to 12+n] [2 to 4] [3 to 12+n] [(2 to 3)+(1 to 8) x m] [(2 to 11+n)+(1 to 8) x m] [4 to 7] [5 to 15+n] [4 to 18+n] [2 to 10+n] [4 to 17] [5 to 18+s] [4 to 11] [5 to 14] [4 to 11] [3 to 6] [2 to 3] [5 to 44] [3 to 36] [4 to 41] [2 to 33] [4 to 14] [5 to 15+s] +Tb [(1 to 8) x m] +Tb [(1 to 8) x m] +TRp [0 to 7] +Tc2 [1] +Tc2 [1] +Tc2 [1] +Tc2 [1] +Tc2 [1] +Tc2 [1] +Tc2 [1] +Tc2 [1] +Tc2 [1] +Trwl [0,1] +Trwl [0,1] +Tcb [0 to 31] +Tcb [0 to 31] +Trwl [0,1] +Tpw [0 to 7] +Tpw [0 to 7] +Tpw [0 to 7] +Tpw [0 to 7] +Tpw [0 to 7] +Tpw [0 to 7] +TRcw [0 to 7] +Tc1 [1] +Tc1 [1] +Tc1 [1] Tc1 [1] Tc1 [1] +Tc1 [1] Tc1 [1] +Tc1 [1] Tc1 [1] +TRcw [0 to 7] +Ttw [n] +Ttw [n] +Ttw [n] +Ttw [n] +Ttw [n] +Ttw [n] +TRc2 [1] +Tcb [0 to 31] +Tcb [0 to 31] +TRc2 [1] +TRc2 [1] +T3 [1] +T3 [1] +T3 [1] +T3 [1] +Tc2 [1] +Tc2 [1] +TRc3 [1] +Tcl [1 to 3] +Tcl [1 to 3] +Tcl [1 to 3] +Tcl [1 to 3] +TRc3 [1] Software standby mode [1+s] Softwarestandby mode[1+s] Note: * Supported only by the H8SX/1648G Group and H8SX/1648H Group.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 238 of 1438 REJ09B0365-0200 (5) Strobe Assert/Negate Timings The assert and negate timings of the strobe signals can be modified as well as number of access cycles.

• Read strobe (RD) in the basic bus interface
• Chip select assertion period extension cycles in the basic bus interface
• Data transfer acknowledge (DACK3 to DACK0) output for DMAC single address transfers
• Data transfer acknowledge (EDACK3 to EDACK0) output for EXDMAC* single address transfers Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.

9.5.5 Area and Extern al Bus Interface

(1) Area 0 Area 0 includes on-chip ROM. All of area 0 is used as external address space in on-chip ROM disabled extended mode, and the space excluding on-chip ROM is external address space in on- chip ROM enabled extended mode. When area 0 external address space is accessed, the CS0 signal can be output. Either of the basic bus interface, byte control SRAM interface, or burst ROM interface can be selected for area 0 by bit BSRM0 in BROMCR and bit BCSEL0 in SRAMCR. Table 9.7 shows the external interface of area 0. Table 9.7 Area 0 Ex ternal Interface Register Setting Interface BSRM0 of BROMCR BCSEL0 of SRAMCR Basic bus interface 0 0 Byte control SRAM interface 0 1 Burst ROM interface 1 0 Setting prohibited 1 1

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 239 of 1438 REJ09B0365-0200 (2) Area 1 In externally extended mode, all of area 1 is external address space. In on-chip ROM enabled extended mode, the space excluding on-chip ROM is external address space. When area 1 external address space is accessed, the CS1 signal can be output. Either of the basic bus interface, byte control SRAM, or burst ROM interface can be selected for area 1 by bit BSRM1 in BROMCR and bit BCSEL1 in SRAMCR. Table 9.8 shows the external interface of area 1. Table 9.8 Area 1 Ex ternal Interface Register Setting Interface BSRM1 of BROMCR BCSEL1 of SRAMCR Basic bus interface 0 0 Byte control SRAM interface 0 1 Burst ROM interface 1 0 Setting prohibited 1 1 (3) Area 2 In externally extended mode, all of area 2 is external address space. When area 2 external address space is accessed, the CS2 signal can be output. The basic bus interface, byte-control SRAM interface, DRAM interface*, or SDRAM interface* can be selected for area 2 by the DRAME and DTYPE bits in DRAMCR* and bit BCSEL2 in SRAMCR. Table 9.9 shows the external interface of area 2. Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 240 of 1438 REJ09B0365-0200 Table 9.9 Area 2 Ex ternal Interface Register Setting Interface DRAME in DRAMCR * DTYPE in DRAMCR * BCSEL2 in SRAMCR Basic bus interface 0 * 0 Byte-control SRAM interface 0 * 1 DRAM interface* 1 0 0 SDRAM interface* 1 1 0 Setting prohibited 1 * 1 Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group. (4) Area 3 In externally extended mode, all of area 3 is external address space. When area 3 external address space is accessed, the CS3 signal can be output. Either of the basic bus interface, byte control SRAM interface, or address/data multiplexed I/O interface can be selected for area 3 by bit MPXE3 in MPXCR and bit BCSEL3 in SRAMCR. Table 9.10 shows the external interface of area 3. Table 9.10 Area 3 External Interface Register Setting Interface MPXE3 of MPXCR BCSEL3 of SRAMCR Basic bus interface 0 0 Byte control SRAM interface 0 1 Address/data multiplexed I/O interface 1 0 Setting prohibited 1 1

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 241 of 1438 REJ09B0365-0200 (5) Area 4 In externally extended mode, all of area 4 is external address space. When area 4 external address space is accessed, the CS4 signal can be output. Either of the basic bus interface, byte control SRAM interface, or address/data multiplexed I/O interface can be selected for area 4 by bit MPXE4 in MPXCR and bit BCSEL4 in SRAMCR. Table 9.11 shows the external interface of area 4. Table 9.11 Area 4 External Interface Register Setting Interface MPXE4 of MPXCR BCSEL4 of SRAMCR Basic bus interface 0 0 Byte control SRAM interface 0 1 Address/data multiplexed I/O interface 1 0 Setting prohibited 1 1

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 242 of 1438 REJ09B0365-0200 (6) Area 5 Area 5 includes the on-chip RAM and access prohibited spaces. In external extended mode, area 5, other than the on-chip RAM and access prohibited spaces, is external address space. Note that the on-chip RAM is enabled when the RAME bit in SYSCR are set to 1. If the RAME bit in SYSCR is cleared to 0, the on-chip RAM is disabled and the corresponding addresses are an external address space. For details, see section 3, MCU Operating Modes. When area 5 external address space is accessed, the CS5 signal can be output. Either of the basic bus interface, byte control SRAM interface, or address/data multiplexed I/O interface can be selected for area 5 by the MPXE5 bit in MPXCR and the BCSEL5 bit in SRAMCR. Table 9.12 shows the external interface of area 5. Table 9.12 Area 5 External Interface Register Setting Interface MPXE5 of MPXCR BCSEL5 of SRAMCR Basic bus interface 0 0 Byte control SRAM interface 0 1 Address/data multiplexed I/O interface 1 0 Setting prohibited 1 1 (7) Area 6 Area 6 includes internal I/O registers. In external extended mode, area 6 other than on-chip I/O register area is external address space. When area 6 external address space is accessed, the CS6 signal can be output. Either of the basic bus interface, byte control SRAM interface, or address/data multiplexed I/O interface can be selected for area 6 by the MPXE6 bit in MPXCR and the BCSEL6 bit in SRAMCR. Table 9.13 shows the external interface of area 6.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 243 of 1438 REJ09B0365-0200 Table 9.13 Area 6 External Interface Register Setting Interface MPXE6 of MPXCR BCSEL6 of SRAMCR Basic bus interface 0 0 Byte control SRAM interface 0 1 Address/data multiplexed I/O interface 1 0 Setting prohibited 1 1 (8) Area 7 Area 7 includes internal I/O registers. In external extended mode, area 7 other than internal I/O register area is external address space. When area 7 external address space is accessed, the CS7 signal can be output. Either of the basic bus interface, byte control SRAM interface, or address/data multiplexed I/O interface can be selected for area 7 by the MPXE7 bit in MPXCR and the BCSEL7 bit in SRAMCR. Table 9.14 shows the external interface of area 7. Table 9.14 Area 7 External Interface Register Setting Interface MPXE7 of MPXCR BCSEL7 of SRAMCR Basic bus interface 0 0 Byte control SRAM interface 0 1 Address/data multiplexed I/O interface 1 0 Setting prohibited 1 1

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 244 of 1438 REJ09B0365-0200

9.5.6 Endian and Data Alignment

Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and controls whether the upper byte data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space), the data size, and endian format when accessing external address space. (1) 8-Bit Access Space With the 8-bit access space, the lower byte data bus (D7 to D0) is always used for access. The amount of data that can be accessed at one time is one byte: a word access is performed as two byte accesses, and a longword access, as four byte accesses. Figures 9.11 and 9.12 illustrate data alignment control for the 8-bit access space. Figure 9.11 shows the data alignment when the data endian format is specified as big endian. Figure 9.12 shows the data alignment when the data endian format is specified as little endian. Longword Access Address Access Count 15 8 Data Size Byte Byte Byte Byte Byte Byte Byte Byte Word 1 1st 1st 2nd 1st 2nd 3rd 4th Bus Cycle Data Size Data bus D15 D8 D7 D0 RD LHWR/LUB LLWR /LLB Strobe signal n n n Figure 9.11 Access Sizes and Data Alignment Control for 8-Bit Access Space (Big Endian)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 245 of 1438 REJ09B0365-0200 Longword Access Address Access Count 23 16 2431 Data Size Byte Byte Byte Byte Byte Byte Byte Byte Word 1 1st 1st 2nd 1st 2nd 3rd 4th Bus Cycle Data Size Data bus D15 D8 D7 D0 RD LHWR/LUB LLWR /LLB Strobe signal n n n Figure 9.12 Access Sizes and Data Alignment Control for 8-Bit Access Space (Little Endian) (2) 16-Bit Access Space With the 16-bit access space, the upper byte data bus (D15 to D8) and lower byte data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word. Figures 9.13 and 9.14 illustrate data alignment control for the 16-bit access space. Figure 9.13 shows the data alignment when the data endian format is specified as big endian. Figure 9.14 shows the data alignment when the data endian format is specified as little endian. In big endian, byte access for an even address is performed by using the upper byte data bus and byte access for an odd address is performed by using the lower byte data bus. In little endian, byte access for an even address is performed by using the lower byte data bus, and byte access for an odd address is performed by using the third byte data bus.

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9.6 Basic Bus Interface

The basic bus interface can be connected directly to the ROM and SRAM. The bus specifications can be specified by the ABWCR, ASTCR, WTCRA, WTCRB, RDNCR, CSACR, and ENDIANCR.

9.6.1 Data Bus

Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and controls whether the upper byte data bus (D15 to D8) or lower byte data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space), the data size, and endian format when accessing external address space,. For details, see section 9.5.6, Endian and Data Alignment.

9.6.2 I/O Pins Used for Basic Bus Interface

Table 9.15 shows the pins used for basic bus interface. Table 9.15 I/O Pins for Basic Bus Interface Name Symbol I/O Function Bus cycle start BS Output Signal indicating that the bus cycle has started Address strobe AS* Output Strobe signal indicati ng that an address output on the address bus is valid during access Read strobe RD Output Strobe signal indicating the read access Read/write RD/ WR Output Signal indicating the data bus input or output direction Low-high write LHWR Output Strobe signal indicating that the upper byte (D15 to D8) is valid during write access Low-low write LLWR Output Strobe signal indicating that the lower byte (D7 to D0) is valid during write access Chip select 0 to 7 CS0 to CS7 Output Strobe signal indicati ng that the area is selected Wait WAIT Input Wait request signal used when an external address space is accessed Note: * When the address/data multiplexed I/O is selected, this pin only functions as the AH output and does not function as the AS output.

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9.6.3 Basic Timing

This section describes the basic timing when the data is specified as big endian. (1) 16-Bit 2-State Access Space Figures 9.15 to 9.17 show the bus timing of 16-bit 2-state access space. When accessing 16-bit access space, the upper byte data bus (D15 to D8) is used for even addresses access, and the lower byte data bus (D7 to D0) is used for odd addresses. No wait cycles can be inserted. 1. n = 0 to 7 2. When RDNn = 0 3. When DKC and EDKC* = 0 Valid Invalid Valid T1 T2 Address CSn AS RD D15 to D8 D7 to D0 D15 to D8 D7 to D0 LHWR LLWR Read Write Notes: High level High-Z Bφ Bus cycle BS RD/WR DACK or EDACK* * Supported only by the H8SX/1648G Group and H8SX/1648H Group. Figure 9.15 16-Bit 2-State Access Space Bus Timing (Byte Access for Even Address)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 249 of 1438 REJ09B0365-0200 Invalid Valid T1 T2 Address CSn AS RD D15 to D8 D7 to D0 D15 to D8 D7 to D0 LHWR LLWR Read Write High level High-Z Bφ Bus cycle Valid BS RD/WR 1. n = 0 to 7 2. When RDNn = 0 3. When DKC and EDKC* = 0 Notes: DACK or EDACK* * Supported only by the H8SX/1648G Group and H8SX/1648H Group. Figure 9.16 16-Bit 2-State Access Space Bus Timing (Byte Access for Odd Address)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 250 of 1438 REJ09B0365-0200 1. n = 0 to 7 2. When RDNn = 0 3. When DKC and EDKC* = 0 Notes: DACK or EDACK* Valid Valid T1 T2 Address CSn AS RD D15 to D8 D7 to D0 D15 to D8 D7 to D0 LHWR LLWR Read Write Bφ Bus cycle Valid Valid BS RD/WR * Supported only by the H8SX/1648G Group and H8SX/1648H Group. Figure 9.17 16-Bit 2-State Access Space Bus Timing (Word Access for Even Address)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 251 of 1438 REJ09B0365-0200 (2) 16-Bit 3-State Access Space Figures 9.18 to 9.20 show the bus timing of 16-bit 3-state access space. When accessing 16-bit access space, the upper byte data bus (D15 to D8) is used for even addresses, and the lower byte data bus (D7 to D0) is used for odd addresses. Wait cycles can be inserted. 1. n = 0 to 7 2. When RDNn = 0 3. When DKC and EDKC* = 0 Notes: DACK or EDACK* Valid Invalid T1 T2 T3 Address CSn AS RD D15 to D8 D7 to D0 D15 to D8 D7 to D0 LHWR LLWR High level High-Z Bφ Bus cycle Valid BS RD/WR Read Write * Supported only by the H8SX/1648G Group and H8SX/1648H Group. Figure 9.18 16-Bit 3-State Access Space Bus Timing (Byte Access for Even Address)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 252 of 1438 REJ09B0365-0200 1. n = 0 to 7 2. When RDNn = 0 3. When DKC and EDKC* = 0 * Supported only by the H8SX/1648G Group and H8SX/1648H Group. Notes: DACK or EDACK* Invalid Valid T1 T2 T3 Address CSn AS RD D15 to D8 D7 to D0 D15 to D8 D7 to D0 LHWR LLWR High level High-Z Bφ Bus cycle Valid BS RD/WR Read Write Figure 9.19 16-Bit 3-State Access Space Bus Timing (Word Access for Odd Address)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 253 of 1438 REJ09B0365-0200 1. n = 0 to 7 2. When RDNn = 0 3. When DKC and EDKC* = 0 * Supported only by the H8SX/1648G Group and H8SX/1648H Group. Notes: DACK or EDACK* Valid Valid T1 T2 T3 Address CSn AS RD Bφ Bus cycle Valid Valid RD D15 to D8 D7 to D0 D15 to D8 D7 to D0 LHWR LLWR Read Write BS RD/WR Figure 9.20 16-Bit 3-State Access Space Bus Timing (Word Access for Even Address)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 254 of 1438 REJ09B0365-0200

9.6.4 Wait Control

This LSI can extend the bus cycle by inserting wait cycles (Tw) when the external address space is accessed. There are two ways of inserting wait cycles: program wait (Tpw) insertion and pin wait (Ttw) insertion using the WAIT pin. (1) Program Wait Insertion From 0 to 7 wait cycles can be inserted automatically between the T2 state and T3 state for 3-state access space, according to the settings in WTCRA and WTCRB. (2) Pin Wait Insertion For 3-state access space, when the WAITE bit in BCR1 is set to 1 and the corresponding ICR bit is set to 1, wait input by means of the WAIT pin is enabled. When the external address space is accessed in this state, a program wait (Tpw) is first inserted according to the WTCRA and WTCRB settings. If the WAIT pin is low at the falling edge of Bφ in the last T2 or Tpw cycle, another Ttw cycle is inserted until the WAIT pin is brought high. The pin wait insertion is effective when the Tw cycles are inserted to seven cycles or more, or when the number of Tw cycles to be inserted is changed according to the external devices. The WAITE bit is common to all areas. For details on ICR, see section 13, I/O Ports.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 256 of 1438 REJ09B0365-0200

9.6.5 Read Strobe ( RD) Timing

The read strobe timing can be modified in area units by setting bits RDN7 to RDN0 in RDNCR to Note that the RD timing with respect to the DACK and EDACK*rising edge will change if the read strobe timing is modified by setting RDNn to 1 when the DMAC or the EXDMAC* is used in the single address mode. Figure 9.22 shows an example of timing when the read strobe timing is changed in the basic bus 3- state access space. Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 257 of 1438 REJ09B0365-0200 Bus cycle T1 T2 Address bus Bφ CSn AS RD Data bus RD Data bus RDNn = 0 RDNn = 1 BS RD/WR DACK or EDACK* 1. n = 0 to 7 2. When DKC and EDKC* = 0 * Supported only by the H8SX/1648G Group and H8SX/1648H Group. Notes: Figure 9.22 Example of Read Strobe Timing

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9.6.6 Extension of Chip Select (CS) Assertion Period

Some external I/O devices require a setup time and hold time between address and CS signals and strobe signals such as RD, LHWR, and LLWR. Settings can be made in CSACR to insert cycles in which only the CS, AS, and address signals are asserted before and after a basic bus space access cycle. Extension of the CS assertion period can be set in area units. With the CS assertion extension period in write access, the data setup and hold times are less stringent since the write data is output to the data bus. Figure 9.23 shows an example of the timing when the CS assertion period is extended in basic bus 3-state access space. Both extension cycle Th inserted before the basic bus cycle and extension cycle Tt inserted after the basic bus cycle, or only one of these, can be specified for individual areas. Insertion or non- insertion can be specified for the Th cycle with the upper eight bits (CSXH7 to CSXH0) in CSACR, and for the Tt cycle with the lower eight bits (CSXT7 to CSXT0).

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 259 of 1438 REJ09B0365-0200 DACK or EDACK* 1. n = 0 to 7 2. When DKC and EDKC* = 0 * Supported only by the H8SX/1648G Group and H8SX/1648H Group. Notes: Th T1 T2 T3 Tt Address Bus cycle Bφ AS CSn RD Data bus Read data Read LHWR, LLWR Write data Write Data bus BS RD/WR Figure 9.23 Example of Timing when Chip Select Assertion Period is Extended

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 260 of 1438 REJ09B0365-0200

9.6.7 DACK and EDACK* Signal Output Timing

When the DMAC or EXDMAC* transfers data in single address mode, the output timing of the DACK and EDACK* signals can be changed by the DKC and EDKC* bits in BCR1. Figure 9.24 shows the output timing of the DACK and EDACK *signals. The DACK and EDACK* signals are asserted a half cycle earlier by setting the DKC or EDKC* bits to 1. Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 261 of 1438 REJ09B0365-0200 T1 T2 Bus cycle Bφ Address bus Write data Write Read data Read CSn AS RD Data bus Data bus LHWR, LLWR BS RD/WR DKC, EDKC* = 0 DKC, EDKC* = 1 DACK or EDACK* Notes: 1. n = 7 to 0 2. RDNn = 0 * Supported only by the H8SX/1648G Group and H8SX/1648H Group. Figure 9.24 DACK and EDACK* Signal Output Timing Note: Supported only by the H8SX/1648G Group and the H8SX/1648H Group.

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9.7 Byte Control SRAM Interface

The byte control SRAM interface is a memory interface for outputting a byte select strobe during a read or a write bus cycle. This interface has 16-bit data input/output pins and can be connected to the SRAM that has the upper byte select and the lower byte select strobes such as UB and LB. The operation of the byte control SRAM interface is the same as the basic bus interface except that: the byte select strobes (LUB and LLB) are output from the write strobe output pins (LHWR and LLWR), respectively; the read strobe (RD) negation timing is a half cycle earlier than that in the case where RDNn = 0 in the basic bus interface regardless of the RDNCR settings; and the RD/WR signal is used as write enable.

9.7.1 Byte Control SRAM Space Setting

Byte control SRAM interface can be specified for areas 0 to 7. Each area can be specified as byte control SRAM interface by setting bits BCSELn (n = 0 to 7) in SRAMCR. For the area specified as burst ROM interface or address/data multiplexed I/O interface, the SRAMCR setting is invalid and byte control SRAM interface cannot be used.

9.7.2 Data Bus

The bus width of the byte control SRAM space can be specified as 16-bit byte control SRAM space according to bits ABWHn and ABWLn (n = 0 to 7) in ABWCR. The area specified as 8-bit access space cannot be specified as the byte control SRAM space. For the 16-bit byte control SRAM space, data bus (D15 to D0) is valid. Access size and data alignment are the same as the basic bus interface. For details, see section 9.5.6, Endian and Data Alignment.

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9.7.3 I/O Pins Used for Byte Control SRAM Interface

Table 9.16 shows the pins used for the byte control SRAM interface. In the byte control SRAM interface, write strobe signals (LHWR and LLWR) are output from the byte select strobes. The RD/WR signal is used as a write enable signal. Table 9.16 I/O Pins for Byte Control SRAM Interface Pin When Byte Control SRAM is Specified Name I/O Function AS/AH AS Address strobe Output Strobe signal indi cating that the address output on the address bus is valid when a basic bus interface space or byte control SRAM space is accessed CSn CSn Chip select Output Strobe signal indicating that area n is selected RD RD Read strobe Output Output enable for the SRAM when the byte control SRAM space is accessed RD/WR RD/ WR Read/write Output Write enable signal for the SRAM when the byte control SRAM space is accessed LHWR/LUB LUB Lower-upper byte select Output Upper byte select when the 16-bit byte control SRAM space is accessed LLWR/LLB LLB Lower-lower byte select Output Lower byte select when the 16-bit byte control SRAM space is accessed WAIT WAIT Wait Input Wait request signal used when an external address space is accessed A23 to A0 A23 to A0 Address pin Output Address output pin D15 to D0 D15 to D0 Data pin Input/ output Data input/output pin

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9.7.4 Basic Timing

(1) 2-State Access Space Figure 9.25 shows the bus timing when the byte control SRAM space is specified as a 2-state access space. Data buses used for 16-bit access space is the same as those in basic bus interface. No wait cycles can be inserted. Bφ Address D15 to D8 D7 to D0 High level D15 to D8 D7 to D0 Bus cycle CSn AS RD LUB LLB DACK or EDACK* BS RD/WR RD RD/WR T1 T2 Note: n = 0 to 7 * Supported only by the H8SX/1648G Group and H8SX/1648H Group. Valid Valid Read Write Valid Valid Figure 9.25 16-Bit 2-State Access Space Bus Timing

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9.7.5 Wait Control

The bus cycle can be extended for the byte control SRAM interface by inserting wait cycles (Tw) in the same way as the basic bus interface. (1) Program Wait Insertion From 0 to 7 wait cycles can be inserted automatically between T2 cycle and T3 cycle for the 3- state access space in area units, according to the settings in WTCRA and WTCRB. (2) Pin Wait Insertion For 3-state access space, when the WAITE bit in BCR1 is set to 1, the corresponding DDR bit is cleared to 0, and the ICR bit is set to 1, wait input by means of the WAIT pin is enabled. For details on DDR and ICR, refer to section 13, I/O Ports. Figure 9.27 shows an example of wait cycle insertion timing.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 267 of 1438 REJ09B0365-0200 Wait by program wait Address Bφ AS DACK or EDACK* LUB, LLB CSn RD RD RD/WR RD/WR Data bus Read data Read BS Write data High levelWrite Notes: 1. Upward arrows indicate the timing of WAIT pin sampling. 2. n = 0 to 7 * Supported only by the H8SX/1648G Group and H8SX/1648H Group. WAIT Data bus T2 Tpw Ttw Ttw T3 Wait by WAIT pin Figure 9.27 Example of Wait Cycle Insertion Timing

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9.7.6 Read Strobe ( RD)

When the byte control SRAM space is specified, the RDNCR setting for the corresponding space is invalid. The read strobe negation timing is the same timing as when RDNn = 1 in the basic bus interface. Note that the RD timing with respect to the DACK and EDACK*rising edge becomes different.

9.7.7 Extension of Chip Select (CS) Assertion Period

In the byte control SRAM interface, the extension cycles can be inserted before and after the bus cycle in the same way as the basic bus interface. For details, refer to section 9.6.6, Extension of Chip Select (CS) Assertion Period.

9.7.8 DACK and EDACK* Signal Output Timing

For DMAC or EXDMAC* single address transfers, the DACK and EDACK*signal assert timing can be modified by using the DKC and EDKC* bits in BCR1. Figure 9.28 shows the DACK and EDACK* signal output timing. Setting the DKC bit or the EDKC* bit to 1 asserts the DACK or EDACK* signal a half cycle earlier.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 269 of 1438 REJ09B0365-0200 Bφ Address D15 to D8 D7 to D0 High level D15 to D8 D7 to D0 DKC, EDKC* = 0 DKC, EDKC* = 1 Bus cycle CSn AS RD LUB LLB BS DACK or EDACK* RD/WR RD RD/WR T1 T2 Valid Valid Read Write Valid Valid Note: * Supported only by the H8SX/1648G Group and H8SX/1648H Group. Figure 9.28 Output Timing for DACK and EDACK*Signals Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.

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9.8 Burst ROM Interface

In this LSI, external address space areas 0 and 1 can be designated as burst ROM space, and burst ROM interfacing performed. The burst ROM interface enables ROM with page access capability to be accessed at high speed. Areas 1 and 0 can be designated as burst ROM space by means of bits BSRM1 and BSRM0 in BROMCR. Consecutive burst accesses of up to 32 words can be performed, according to the setting of bits BSWDn1 and BSWDn0 (n = 0, 1) in BROMCR. From one to eight cycles can be selected for burst access. Settings can be made independently for area 0 and area 1. In the burst ROM interface, the burst access covers only read accesses by the CPU and EXDMAC cluster transfer. Other accesses are performed with the similar method to the basic bus interface.

9.8.1 Burst ROM Space Setting

Burst ROM interface can be specified for areas 0 and 1. Areas 0 and 1 can be specified as burst ROM space by setting bits BSRMn (n = 0, 1) in BROMCR.

9.8.2 Data Bus

The bus width of the burst ROM space can be specified as 8-bit or 16-bit burst ROM interface space according to the ABWHn and ABWLn bits (n = 0, 1) in ABWCR. For the 8-bit bus width, data bus (D7 to D0) is valid. For the 16-bit bus width, data bus (D15 to D0) is valid. Access size and data alignment are the same as the basic bus interface. For details, see section 9.5.6, Endian and Data Alignment.

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9.8.3 I/O Pins Used for Burst ROM Interface

Table 9.17 shows the pins used for the burst ROM interface. Table 9.17 I/O Pins Used for Burst ROM Interface Name Symbol I/O Function Bus cycle start BS Output Signal indicati ng that the bus cycle has started. Address strobe AS Output Strobe signal indicating that an address output on the address bus is valid during access Read strobe RD Output Strobe signal indicating the read access Read/write RD/ WR Output Signal indicating the data bus input or output direction Low-high write LHWR Output Strobe signal indicating that the upper byte (D15 to D8) is valid during write access Low-low write LLWR Output Strobe signal indicating that the lower byte (D7 to D0) is valid during write access Chip select 0 and 1 CS0, CS1 Output Strobe signal indicati ng that the area is selected Wait WAIT Input Wait request signal used when an external address space is accessed

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9.8.4 Basic Timing

The number of access cycles in the initial cycle (full access) on the burst ROM interface is determined by the basic bus interface settings in ABWCR, ASTCR, WTCRA, WTCRB, and bits CSXHn in CSACR (n = 0 to 7). When area 0 or area 1 designated as burst ROM space is read by the CPU or EXDMAC* cluster transfer, the settings in RDNCR and bits CSXTn in CSACR (n = 0 to 7) are ignored. From one to eight cycles can be selected for the burst cycle, according to the settings of bits BSTS02 to BSTS00 and BSTS12 to BSTS10 in BROMCR. Wait cycles cannot be inserted. In addition, 4-word, 8-word, 16-word, or 32-word consecutive burst access can be performed according to the settings of BSTS01, BSTS00, BSTS11, and BSTS10 bits in BROMCR. The basic access timing for burst ROM space is shown in figures 9.29 and 9.30. Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group. T1 T2 T1 T2 T1 T2T3 Bφ Upper address bus Note: n = 1, 0 Lower address bus Data bus Full access Burst access CSn AS RD BS RD/WR Figure 9.29 Example of Burst ROM Access Timing (ASTn = 1, Two Burst Cycles)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 273 of 1438 REJ09B0365-0200 T1 T2 T1T1 Bφ Upper address bus Lower address bus Data bus Full access Burst access CSn AS RD BS RD/WR Note: n = 1, 0 Figure 9.30 Example of Burst ROM Access Timing (ASTn = 0, One Burst Cycle)

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9.8.5 Wait Control

As with the basic bus interface, either program wait insertion or pin wait insertion by the WAIT pin can be used in the initial cycle (full access) on the burst ROM interface. See section 9.6.4, Wait Control. Wait cycles cannot be inserted in a burst cycle.

9.8.6 Read Strobe ( RD) Timing

When the burst ROM space is read by the CPU or EXDMAC* cluster transfer, the RDNCR setting for the corresponding space is invalid. The read strobe negation timing is the same timing as when RDNn = 0 in the basic bus interface. Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.

9.8.7 Extension of Chip Select (CS) Assertion Period

In the burst ROM interface, the extension cycles can be inserted in the same way as the basic bus interface. For the burst ROM space, the burst access can be enabled only in read access by the CPU or EXDMAC* cluster transfer. In this case, the setting of the corresponding CSXTn bit in CSACR is ignored and an extension cycle can be inserted only before the full access cycle. Note that no extension cycle can be inserted before or after the burst access cycles. In accesses other than read accesses by the CPU and EXDMAC* cluster transfer, the burst ROM space is equivalent to the basic bus interface space. Accordingly, extension cycles can be inserted before and after the burst access cycles. Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.

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9.9 Address/Data Multiplexed I/O Interface

If areas 3 to 7 of external address space are specified as address/data multiplexed I/O space in this LSI, the address/data multiplexed I/O interface can be performed. In the address/data multiplexed I/O interface, peripheral LSIs that require the multiplexed address/data can be connected directly to this LSI.

9.9.1 Address/Data Multiplexed I/O Space Setting

Address/data multiplexed I/O interface can be specified for areas 3 to 7. Each area can be specified as the address/data multiplexed I/O space by setting bits MPXEn (n = 3 to 7) in MPXCR.

9.9.2 Address/Data Multiplex

In the address/data multiplexed I/O space, data bus is multiplexed with address bus. Table 9.18 shows the relationship between the bus width and address output. Table 9.18 Address/Data Multiplex Bus Width Cycle Data Pins Address Data Address Data 8 bits 16 bits PI7 A15 D15 PI6 A14 D14 PI5 A13 D13 PI4 A12 D12 PI3 A11 D11 PI2 A10 D10 PI1 PI0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0

9.9.3 Data Bus

The bus width of the address/data multiplexed I/O space can be specified for either 8-bit access space or 16-bit access space by the ABWHn and ABWLn bits (n = 3 to 7) in ABWCR. For the 8-bit access space, D7 to D0 are valid for both address and data. For 16-bit access space, D15 to D0 are valid for both address and data. If the address/data multiplexed I/O space is accessed, the corresponding address will be output to the address bus. For details on access size and data alignment, see section 9.5.6, Endian and Data Alignment.

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9.9.4 I/O Pins Used for Address/Data Multiplexed I/O Interface

Table 9.19 shows the pins used for the address/data multiplexed I/O Interface. Table 9.19 I/O Pins for Address/Data Multiplexed I/O Interface Pin When Byte Control SRAM is Specified Name I/O Function CSn CSn Chip select Output Chip select (n = 3 to 7) when area n is specified as the address/data multiplexed I/O space AS/AH AH* Address hold Output Signal to hold an address when the address/data multiplexed I/O space is specified RD RD Read strobe Output Signal indicating that the address/data multiplexed I/O space is being read LHWR/LUB LHWR Low-high write Output Strobe signal indicating that the upper byte (D15 to D8) is valid when the address/data multiplexed I/O space is written LLWR/LLB LLWR Low-low write Output Strobe signal indicating that the lower byte (D7 to D0) is valid when the address/data multiplexed I/O space is written D15 to D0 D15 to D0 Address/data Input/ output Address and data multiplexed pins for the address/data multiplexed I/O space. Only D7 to D0 are valid when the 8-bit space is specified. D15 to D0 are valid when the 16-bit space is specified. A23 to A0 A23 to A0 Address Output Address output pin WAIT WAIT Wait Input Wait request signal used when the external address space is accessed BS BS Bus cycle start Output Signal to indicate the bus cycle start RD/WR RD/ WR Read/write Output Signal indicating t he data bus input or output direction Note: * The AH output is multiplexed with the AS output. At the timing that an area is specified as address/data multiplexed I/O, this pin starts to function as the AH output meaning that this pin cannot be used as the AS output. At this time, when other areas set to the basic bus interface is accessed, this pin does not function as the AS output. Until an area is specified as address/data multiplexed I/O, be aware that this pin functions as the AS output.

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9.9.5 Basic Timing

The bus cycle in the address/data multiplexed I/O interface consists of an address cycle and a data cycle. The data cycle is based on the basic bus interface timing specified by the ABWCR, ASTCR, WTCRA, WTCRB, RDNCR, and CSACR. Figures 9.31 and 9.32 show the basic access timings. Tma1 Tma2 T2T1 Bφ Address bus D7 to D0 D7 to D0 Address cycle Data cycle CSn LLWR AH RD DACK or EDACK* BS RD/WR Notes: n = 3 to 7 * Supported only by the H8SX/1648G Group and H8SX/1648H Group. Address Read data Address Write data Read Write Figure 9.31 8-Bit Access Space Access Timing (ABWHn = 1, ABWLn = 1)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 278 of 1438 REJ09B0365-0200 RD Tma1 Tma2 T2T1 Bφ Address bus D15 to D0 D15 to D0 Address cycle Bus cycle Data cycle CSn LHWR LLWR AH DACK or EDACK* BS RD/WR Note: n = 3 to 7 * Supported only by the H8SX/1648G Group and H8SX/1648H Group. Address Read data Address Write data Read Write Figure 9.32 16-Bit Access Space Access Timing (ABWHn = 0, ABWLn = 1)

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9.9.6 Address Cycle Control

An extension cycle (Tmaw) can be inserted between Tma1 and Tma2 cycles to extend the AH signal output period by setting the ADDEX bit in MPXCR. By inserting the Tmaw cycle, the address setup for AH and the AH minimum pulse width can be assured. Figure 9.33 shows the access timing when the address cycle is three cycles. Tma1 Tmaw Tma2 T2T1 Bφ Address bus D15 to D0 D15 to D0 Address cycle Data cycle CSn LHWR LLWR AH RD DACK or EDACK* BS RD/WR Note: n = 3 to 7 * Supported only by the H8SX/1648G Group and H8SX/1648H Group. Address Read data Address Write data Read Write Figure 9.33 Access Timing of 3 Address Cycles (ADDEX = 1)

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9.9.7 Wait Control

In the data cycle of the address/data multiplexed I/O interface, program wait insertion and pin wait insertion by the WAIT pin are enabled in the same way as in the basic bus interface. For details, refer to section 9.6.4, Wait Control. Wait control settings do not affect the address cycles.

9.9.8 Read Strobe ( RD) Timing

In the address/data multiplexed I/O interface, the read strobe timing of data cycles can be modified in the same way as in basic bus interface. For details, refer to section 9.6.5, Read Strobe (RD) Timing. Figure 9.34 shows an example when the read strobe timing is modified.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 281 of 1438 REJ09B0365-0200 Tma1 Tma2 T2T1 Bφ Address bus D15 to D0 D15 to D0 Address cycle Data cycle CSn RD AH RD DACK or EDACK* BS RD/WR Note: n = 3 to 7 * Supported only by the H8SX/1648G Group and H8SX/1648H Group. Address Read data Address Read data RDNn = 0 RDNn = 1 Figure 9.34 Read Strobe Timing

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9.9.9 Extension of Chip Select (CS) Assertion Period

In the address/data multiplexed interface, the extension cycles can be inserted before and after the bus cycle. For details, see section 9.6.6, Extension of Chip Select (CS) Assertion Period. Figure 9.35 shows an example of the chip select (CS) assertion period extension timing. Tma1 Tma2 T2 TtT1Th Bφ Address bus D15 to D0 D15 to D0 Address cycle Bus cycle Data cycle CSn LHWR LLWR AH RD DACK or EDACK* BS RD/WR Note: n = 3 to 7 * Supported only by the H8SX/1648G Group and H8SX/1648H Group. Address Read data Address Write data Read Write Figure 9.35 Chip Select (CS) Assertion Period Extension Timing in Data Cycle

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9.9.10 DACK and EDACK* Signal Output Timing

For DMAC or EXDMAC* single address transfers, the DACK and EDACK* signal assert timing can be modified by using bits DKC and EDKC* in BCR1. Figure 9.37 shows the DACK and EDACK* signal output timing. Setting the DKC bit or the EDKC* bit to 1 asserts the DACK or EDACK* signal a half cycle earlier. Tma1 Tma2 T2T1 Bφ DKC, EDKC* = 0 DKC, EDKC* = 1 Address bus D15 to D0 D15 to D0 Address cycle Data cycle CSn RD AH RD DACK or EDACK* BS RD/WR Note: n = 3 to 7 * Supported only by the H8SX/1648G Group and H8SX/1648H Group. Address Read data RDNn = 0 RDNn = 1 Address Read data Figure 9.37 Output Timing for DACK and EDACK* Signals Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.

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9.10 DRAM Interface

Supported only by the H8SX/1648G Group and the H8SX/1648H Group. In this LSI, area 2 in the external space can be used as the DRAM interface space. Up to 8 Mbytes of DRAM is directly connected via the DRAM interface.

9.10.1 Setting DRAM Space

Area 2 can be specified as the DRAM space by the DRAME and DTYPE bits in DRAMCR. Table 9.20 lists the relationship among the DRAME and DTYPE bits and area 2 interfaces. The bus settings of the DRAM space such as bus width and wait cycle number depend on area 2 settings. Table 9.20 Relationship Among DRAME and DTYPE and Area 2 Interfaces DRAME DTYPE Area 2 Interface 0 × Basic bus space (initial state)/byte-control SRAM space 1 0 DRAM space 1 1 SDRAM space [Legend] ×: Don't care

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9.10.2 Address Multiplexing

A Row address and a column address are multiplexed in the DRAM space. Select the number of row address bits to be shifted with bits MXC1 and MXC0 in DRAMCR. Table 9.21 lists the relationship among bits MXC1 and MXC0 and shifted bit number. Table 9.21 Relationship Among MXC1 and MXC0 and Shifted Bit Count DRAMCR MXC1 0 8 bits 9 bits 10 bits 11 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits MXC0 A27 to A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A23 to A18 A17 - A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A23 to A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A23 to A18 A17 -- A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A23 to A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A23 to A18 A17 --- A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A23 to A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A23 to A18 A17 ---- A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A23 to A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Row address Column address Row address Column address Row address Column address Row address Column address Shit Bit Count Data Bus Width Address External Address Pin

9.10.3 Data Bus

The data bus width of the DRAM space can be selected from 8 and 16 bits by bits ABWH2 and ABWL2 in ABWCR. DRAM with 16-bit words can be connected directly to 16-bit bus width space. D7 to D0 are valid in 8-bit DRAM space, and D15 to D0 are valid in 16-bit DRAM space. The data endian format can be selected by bit LE2 in ENDIANCR. For details on the access size and alignment, see section 9.5.6, Endian and Data Alignment.

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9.10.4 I/O Pins Used for DRAM Interface

Table 9.22 shows the pins used for the DRAM interface. Table 9.22 I/O Pins for DRAM Interface Pin DRAM Selected Name I/O Function WE WE Write enable Output Write enable signal for accessing the DRAM interface RAS RAS Row address strobe Output Row address strobe when the DRAM space is specified as area 2 LUCAS/ DQMLU LUCAS Lower-upper column address strobe Output • Lower-upper column address strobe when the 32-bit DRAM space is accessed

• Upper column address strobe when the 16-bit DRAM space is accessed LLCAS/ DQMLL LLCAS Lower-lower column address strobe Output • Lower-lower column address strobe when the 32-bit DRAM space is accessed
• Lower column address strobe when the 16-bit DRAM space is accessed OE OE Output enable Output Output enable signal when the DRAM space is accessed WAIT WAIT Wait Input Wait request signal used when an external address space is accessed A17 to A0 A17 to A0 Address pin Out put Multiplexed addr ess/data output pin D15 to D0 D15 to D0 Data pin Input/ output Data input/output pin

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9.10.5 Basic Timing

Figure 9.38 shows a basic access timing of the DRAM space. A basic bus cycle consists of four clock cycles: one precharge cycle (Tp), one row address output cycle (Tr), and two column address output cycles (Tc1 and Tc2). The RD signal is output to DRAM as an OE signal on a DRAM access. When DRAM with the EDO page mode function is in use, connect the OE signal to the OE pin of the DRAM. Tp Tr Tc1 Tc2 Address bus Row address Column address Bφ RAS LUCAS LLCAS WE OE (RD) WE OE (RD) Data bus High High Read Write Data bus BS RD/WR Figure 9.38 DRAM Basic Access Timing (RAS = 0 and CAST = 0)

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9.10.6 Controlling Column Address Output Cycle

The number of column address output cycles can be changed from two to three clock cycles by setting the CAST bit in DRAMCR. Set the bit according to the DRAM to be used and the frequency of this LSI so that the CAS pulse width can be optimal. Figure 9.39 shows a timing example when the number of column address output cycles is set to three clock cycles. Tp Tr Tc1 Tc2 Tc3 Address bus Row address Column address Bφ RAS LUCAS LLCAS WE OE (RD) WE OE (RD) Data bus High High Read Write Data bus BS RD/WR Figure 9.39 Access Timing Example of Column Address Output Cycles for 3 Clock Cycles (RAST = 0)

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9.10.7 Controlling Row Address Output Cycle

The RAS signal is driven low at the start of the Tr cycle by setting the RAST bit to 1. The row address hold time to the falling edge of the RAS signal and the DRAM read access time are changed. Set the bit according to the DRAM to be used and the frequency of this LSI so that required performance can be obtained. Figure 9.40 shows a timing example when the RAS signal is driven low at the start of the Tr cycle. Tp Tr Tc1 Tc2 Address bus Row address Column address Bφ RAS LUCAS LLCAS WE OE (RD) WE OE (RD) Data bus High High Read Write Data bus BS RD/WR Figure 9.40 Access Timing Example of RAS Signal Driven Low at Start of Tr Cycle (CAST = 0)

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9.10.8 Controlling Precharge Cycle

The number of precharge cycles (Tp) can be selected from one to four clock cycles by bits TPC1 and TPC0 in DRACCR. Set the bit according to the DRAM to be used and the frequency of this LSI so that the number of precharge cycle can be optimal. Figure 9.42 shows an access timing example when two Tp cycles are specified. The setting of bits TPC1 and TPC0 affect the Tp cycle of a refresh cycle. Tp1 Tp2 Tr Tc1 Tc2 Address bus Row address Column address Bφ RAS LUCAS LLCAS WE OE (RD) WE OE (RD) Data bus High High Read Write Data bus BS RD/WR Figure 9.42 Access Timing Example of Two Precharge Cycles (RAST = 0 and CAST = 0)

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9.10.9 Wait Control

There are two methods of inserting wait cycles during a DRAM access cycle: program wait insertion and pin wait insertion using the WAIT pin. Wait cycles are inserted to extend the CAS assertion period during a DRAM read cycle and to ensure the write data setup time to the falling edge of the CAS signal during a DRAM write cycle. (1) Program Wait Insertion When bit AST2 in ASTCR is set to 1, zero to seven of wait cycles can automatically be inserted between the Tc1 and Tc2 cycles. The number of wait cycles is selected by bits W22 to W20 in WTCRB. (2) Pin Wait Insertion When the WAITE bit in BCR1 is set to 1, and the AST2 bit in ASTCR is set to 1, setting the ICR bit for the corresponding pin to 1 enables wait input by the WAIT pin. When the DRAM space is accessed in this state, a program wait (Tpw) is first inserted. If the WAIT pin is low at the rising edge of Bφ in the last Tc1 or Tpw cycle, another Ttw cycle is inserted until the WAIT pin is driven high. For details on ICR, see section 13, I/O Ports. Figure 9.43 shows an example of wait cycle insertion timing for 2-cycle column address output. Figure 9.44 shows an example of wait cycle insertion timing for 3-cycle column address output.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 294 of 1438 REJ09B0365-0200 High High Row address Column address Wait by program wait Tp Address bus Bφ RAS WE OE (RD) Data bus LUCAS, LLCAS LUCAS, LLCAS WE OE (RD) Data bus Read Write WAIT Tr Tc1 Tpw Ttw Tc2 Wait by WAIT pin BS RD/WR Note: Upward arrows indicate the timing of WAIT pin sampling. Figure 9.43 Example of Wait Cycle Insertion Timing for 2-Cycle Column Address Output

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 295 of 1438 REJ09B0365-0200 High High Row address Column address Wait by program wait Tp Address bus Bφ LUCAS, LLCAS RAS WE OE (RD) Data bus LUCAS, LLCAS WE OE (RD) Data bus Read Write WAIT Tr Tc1 Tpw Ttw Tc2 Tc3 Wait by WAIT pin BS RD/WR Note: Upward arrows indicate the timing of WAIT pin sampling. Figure 9.44 Example of Wait Cycle Insertion Timing for 3-Cycle Column Address Output

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 296 of 1438 REJ09B0365-0200

9.10.10 Controlling Byte and Word Accesses

When 16-bit bus DRAM is used, two CAS signals can be used to control byte and word accesses. Figures 9.45 and 9.46 show control timing examples with use of two CAS signals (in big endian format). Figure 9.47 shows an example of connection for control with two CAS signals. Tp Tr Tc1 Tc2 Bφ Address bus RAS LUCAS LLCAS WE OE (RD) D15 to D8 D7 to D0 High Row address Column address BS RD/WR Figure 9.45 Timing Example of Byte Control with Use of Two CAS Signals (Write Access with Lowest Bit of Address = B'0, RAST = 0, CAST = 0)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 297 of 1438 REJ09B0365-0200 Tp Tr Tc1 Tc2 Bφ Address bus RAS LUCAS LLCAS WE OE (RD) D15 to D8 D7 to D0 High Row address Column address BS RD/WR Figure 9.46 Timing Example of Word Control with Use of Two CAS Signals (Read Access with Lowest Bit of Address = B'0, RAST = 0, CAST = 0)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 298 of 1438 REJ09B0365-0200 RAS UCAS LCAS WE OE A10 D15 to D0 RAS LUCAS LLCAS WE RD (OE) A11 A10 D15 to D0 This LSI (Address shifted by 11 bits) Two CAS signals used 64-Mbit DRAM (4 Mwords × 16 bits) 11-bit column address Row address input: A10 to A0 Column address input: A10 to A0 Figure 9.47 Example of Connection for Control with Two CAS Signals

9.10.11 Burst Access Operation

Besides an accessing method in which this LSI outputs a row address every time it accesses the DRAM (called full access or normal access), some DRAMs have a fast-page mode function in which fast speed access can be achieved by modifying only a column address with the same row address output (burst access) when consecutive accesses are made to the same row address. The fast-page mode (burst access) can be specified when the BE bit in DRAMCR is set to one, (1) Burst Access (Fast-Page Mode) Operation Timing Figures 9.48 and 9.49 show operation timing of the fast-page mode. When access cycles to the DRAM space are continued and the row addresses of the consecutive two cycles are the same, output cycles of the CAS and column address signals follow. The row address bits to be compared are decided by bits MXC1 and MXC0 in DRAMCR. Wait cycles can be inserted during a burst access. The method and timing of the wait insertion are the same as that of full access mode. For details, see section 9.10.9, Wait Control.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 299 of 1438 REJ09B0365-0200 Tp Tr Tc1 Tc2 Tc1 Tc2 Address bus Row address Column address Column address Bφ RAS LUCAS LLCAS WE OE (RD) WE OE (RD) Data bus Read Write Data bus BS RD/WR Figure 9.48 Operation Timing of Fast-Page Mode (RAST = 0, CAST = 0)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 300 of 1438 REJ09B0365-0200 Tp Tr Tc1 Tc2 Tc3 Tc3Tc1 Tc2 Address bus Row address Column address Column address Bφ RAS LUCAS LLCAS WE OE (RD) WE OE (RD) Data bus High High Read Write Data bus BS RD/WR Figure 9.49 Operation Timing of Fast-Page Mode (RAST = 0, CAST = 1)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 301 of 1438 REJ09B0365-0200 (2) RAS Down Mode and RAS Up Mode Even if the fast-page mode is selected, the DRAM space is not consecutively accessed and other spaces may be accessed. The RAS signal can be held low during other space accesses. The fast- page mode access can be resumed (burst access) when the same row address in the DRAM space is accessed. (a) RAS Down Mode Set the RCDM and BE bits in DRAMCR to 1 to make a transition to the RAS down mode. The RCDM bit is enabled only when the BE bit is set to 1. The fast-page mode access (burst access) is resumed when the row addresses of the current cycle and previous cycle are the same. While other spaces are accessed when the DRAM space access is halted, the RAS signal must be low. Figure 9.50 shows a timing example of RAS down mode. The RAS signal goes high under the following conditions.

• When a refresh cycle is performed during RAS down mode
• When a self-refresh is performed
• When a transition to software standby mode is made
• When the external bus requested by the BREQ signal is released
• When either the RCDM or BE bit is cleared to 0 If a transition to the all-module clock-stop mode is made during RAS down mode, clocks are stopped with the RAS signal driven low. To make a transition with the RAS signal driven high, clear the RCDM bit to 0 before execution of the SLEEP instruction. Clear the RCDM bit to 0 for write access to SCKCR to set the clock frequencies. For SCKCR, see section 26, Clock Pulse Generator.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 302 of 1438 REJ09B0365-0200 Tp Tr Tc1 Tc2 Tc2Tc1Tc1 Tc2 Address bus Row address Column address DRAM space read Basic bus space read DRAM space read External address Column address Bφ RAS LUCAS LLCAS WE RD OE Data bus High BS RD/WR Figure 9.50 Timing Example of RAS Down Mode (RAST = 0, CAST = 0)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 304 of 1438 REJ09B0365-0200

9.10.12 Refresh Control

This LSI includes a DRAM refresh control function. The refresh method is the CAS before RAS (CBR) refresh. Self-refresh cycles can be performed in software standby mode. The refresh control function is enabled when area 2 is specified as the DRAM space by the DRAME and DTYPE bits in DRAMCR. (1) CAS before RAS (CBR) Refresh Mode Set the RFSHE bit in REFCR to 1 to select the CBR refresh mode. A CBR refresh cycle is performed when the value set in RTCOR matches the RTCNT value (compare match). RTCNT is an up-counter operated on the input clock specified by bits RTCK2 to RTCK0 in REFCR. RTCNT is initialized upon the compare match and restarts to count up with H'00. Accordingly, a CBR refresh cycle is repeated at intervals specified by bits RTCK2 to RTCK0 in RTCOR. Set the bits so that the required refresh intervals of the DRAM must be satisfied. Since setting bits RTCK2 to RTCK0 starts RTCNT to count up, set RTCNT and RTCOR before setting bits RTCK2 to RTCK0. When changing RTCNT and RTCOR, the counting operation should be halted. When changing bits RTCK2 to RTCK0, change them only after disabling external access and bus release by the EXDMAC, and if the write data buffer function is in use, disabling the write data buffer function and reading the external space. The external space cannot be accessed in CBR refresh mode. Figure 9.52 shows RTCNT operation, figure 9.53 shows compare match timing, and figure 9.54 shows CBR refresh timing. Table 9.23 lists the pin states during a CBR refresh cycle. RTCOR H'00 Refresh request RTCNT Figure 9.52 RTCNT Operation

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 307 of 1438 REJ09B0365-0200 (2) Self-Refresh Mode Some DRAMs have a self-refresh mode (battery backup mode). The self-refresh mode is a kind of standby mode and refresh timing and refresh address are controlled internally. The self-refresh mode is selected by setting the RFSHE and SLFRF bits in REFCR to 1. The CAS and RAS signals are output as shown in figure 9.56 by executing the SLEEP instruction. Then, DRAM enters self-refresh mode. When a CBR refresh is requested on a transition to the standby mode, the CBR refresh is first performed and then the self-refresh mode is entered. When the self-refresh mode is used, do not clear the OPE bit in SBYCR to 0. For details, see section 27.2.1, Standby Control Register (SBYCR). TRp TRr TRc3 Bφ RAS LUCAS LLCAS WE BS RD/WR High Software standby TRc4 High High Figure 9.56 Self-Refresh Timing

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 309 of 1438 REJ09B0365-0200 (3) Refresh and All-Module Clock Stop Mode This LSI is entered in all-module clock stop mode by the following operation: Stop the clocks of all on-chip peripheral modules by setting the ACSE bit in MSTPCR to 1 (MSTPCRA, MSTPCRB = H'FFFFFFFF) or run only the 8-bit timer (MSTPCRA, MSTPCRB = H'F[C to F]FFFFFF), then execute the SLEEP instruction to enter the sleep mode. In all-module clock stop mode, clocks for the bus controller and I/O ports are stopped. Since the clock for the bus controller is stopped, a CBR refresh cycle cannot be performed. When external DRAM is used and the contents of the DRAM in sleep mode should be held, clear the ACSE bit in MSTPCE to 0. For details, see section 27.2.2, Module Stop Control Registers A and B (MSTPCRA and MSTPCRB).

9.10.13 DRAM Interface and Single Address Transfer by DMAC and EXDMAC

When fast-page mode (BE = 1) is set for the DRAM space, either fast-page access or full access can be selected, by the setting of bits DDS and EDDS in DRAMCR, for the single address transfer by the DMAC or EXDMAC where the DRAM space is specified as the transfer source or destination. At the same time, the output timings of the DACK, EDACK and BS signals are changed. When BE = 0, full access to the DRAM space is performed by single address transfer regardless of the setting of bits DDS and EDDS. However, the output timing of the DACK, EDACK and BS signals can be changed by the setting of bits DDS and EDDS. The assertion timing of the DACK and EDACK signal can be changed by bits DKC and EDKC in BCR1.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 312 of 1438 REJ09B0365-0200

9.11 Synchronous DRAM Interface

Supported only by the H8SX/1648G Group and the H8SX/1648H Group. In this LSI, area 2 in the external space can be used as the SDRAM interface space. Up to 8 Mbytes (64 Mbits) of DRAM is directly connected via the SDRAM interface. The CAS latency with 2 to 4 is supported.

9.11.1 Setting SDRAM space

Area 2 can be specified as the SDRAM space by the DRAME and DTYPE bits in DRAMCR. Table 9.24 lists the relationship among the DRAME and DTYPE bits and area 2 interfaces. In the SDRAM space, pins PB2, PB3, and PB4 are used as the RAS, CAS, and WE signals. The PB1 pin is used as the CS2 signal by the PFCR setting, and the PB5 pin is used as the CKE signal by setting the OEE bit in DRAMCR to 1. The bus settings of the SDRAM space depend on area 2 settings. The pin wait and program wait for the SDRAM space are not available. For PFCR, see section 13, I/O Ports. An SDRAM command is designated by the combination of the RAS, CAS, and WE signals and the precharge-sel command (Precharge-sel) output on the upper column address. This LSI supports the following commands: the NOP, auto-refresh (REF), self-refresh (SELF), all- bank-precharge (PALL), bank active (ACTV), read (READ), write (WRIT), and mode register setting (MRS). Commands controlling a bank are not supported. Table 9.24 Relationship among DRAME and DTYPE and Area 2 Interfaces DRAME DTYPE Area 2 Interface

0 X Basic bus space (initial state)/byte-control SRAM space

[Legend] X: Don't care

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9.11.2 Address Multiplexing

A Row address and a column address are multiplexed in the SDRAM space. Select the number of row address bits to be shifted with bits MXC1 and MXC0 in DRAMCR. The precharge set command (Precharge-sel) is output on the upper column address. Table 9.25 lists the relationship among bits MXC1 and MXC0 and shifted bit number. Table 9.25 Relationship Among MXC1 and MXC0 and Shifted Bit Count DRAMCR Row address Column address Row address Column address MXC1 0 0 8 bits 8 bits 16 bits MXC0 A23 to A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A23 to A18 -- A23 A22 A21 A20 A19 P/A18* A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A23 to A18 -- A23 A22 A21 A20 A19 P A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A23 to A18 -- A23 A22 A21 A20 P/A19* A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A23 to A18 -- A23 A22 A21 A20 P A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Row address Column address Row address Column address 1 0 10 bits 8 bits 16 bits A23 to A18 ---- A23 A22 A21 P/A20* A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A23 to A18 ---- A 2 3 A 2 2 A 2 1P A 9A 8A 7A 6A 5A 4A 3A 2A 1A 0 A23 to A18 ---- A23 A22 P/A21* A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A23 to A18 ---- A23 A22 P A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Row address Column address Row address Column address 0 1 9 bits 8 bits 16 bits A23 to A18 A17 -- A23 A22 A21 A20 P/A19* A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A23 to A18 A17 -- A23 A22 A21 A20 P A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A23 to A18 A17 -- A23 A22 A21 P/A20* A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A23 to A18 A17 -- A23 A22 A21 P A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Row address Column address Row address Column address 1 1 11 bits 8 bits 16 bits A23 to A18 A17 ---- A23 A22 P/A21* A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A23 to A18 A17 ---- A 2 3 A 1 0P A 9A 8A 7A 6A 5A 4A 3A 2A 1A 0 A23 to A18 A17 ---- A23 P/A22* A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A23 to A18 A17 ---- A11 P A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Note: * When issuing the PALL command, precharge-sel = 1 is output and when issuing the ACTIV command, a corresponding address is outp ut. Shift Bit Count Data Bus Width Address External Address Pin

9.11.3 Data Bus

Either 8 or 16 bits can be selected as the data bus width of the SDRAM space by bits ABWH2 and ABWL2 in ABWCR. SDRAM with 16-bit words can be connected directly to 16-bit bus width space. D7 to D0 are valid in 8-bit SDRAM space and D15 to D0 are valid in 16-bit SDRAM space. The data endian format can be selected by bit LE2 in ENDIANCR. For details on the access size and alignment, see section 9.5.6, Endian and Data Alignment.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 314 of 1438 REJ09B0365-0200

9.11.4 I/O Pins Used for DRAM Interface

Table 9.26 shows the pins used for the SDRAM interface. Since a CS pin functions as an input after a reset, set the bit in PFCR to 1 to output the CS signal. For details, see section 13, I/O Ports. To enable the SDRAM interface, select the appropriate MCU operating mode. For details, see section 3, MCU Operating Modes. Table 9.26 I/O Pins for SDRAM Interface Pin DRAM Selected Name I/O Function RAS RAS Row address strobe Output Row address strobe when the SDRAM space is specified as area 2 CAS CAS Column address strobe Output Column address strobe when the SDRAM space is specified as area 2 WE WE Write enable Output Write enable signal for accessing the SDRAM interface OE/CKE CKE Clock enable Output Clock enable signal when the SDRAM space is specified as area 2. LLCAS/ DQMLU DQMLU Lower-upper data mask enable Output Upper data mask enable when the 16- bit SDRAM space is accessed LLCAS/ DQMLL DQMLL Lower-lower data mask enable Output • Lower data mask enable when the 16-bit SDRAM space is accessed

• Data mask enable when the 8-bit SDRAM is accessed A17 to A0 A17 to A0 Address pin Out put Multiplexed row/column-address output pin D15 to D0 D15 to D0 Data pin Input/ output Data input/output pin PB7 SDRAM φ Clock Output SDRAM clock CS2 CS Chip select Output Strobe si gnal indicating that SDRAM is selected

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 315 of 1438 REJ09B0365-0200

9.11.5 Basic Timing

Figures 9.60 and 9.61 show a basic access timing of the SDRAM space. A basic read cycle consists of five clock cycles: one precharge cycle (Tp), one row address output cycle (Tr), and three column address output cycles (Tc1, Tcl, and Tc2). A basic write cycle consists of four clock cycles: one precharge cycle (Tp), one row address output cycle (Tr), and two column address output cycles (Tc1 and Tc2). When the SDRAM space is selected, the WAITE bit in BCR, the RAST and CAST bits in DRAMCR, bits RCW1 and RCW0 in REFCR are ignored. Tp Tr Tc1 Tcl Tc2 Address bus Row address Column address SDRAMφ CS Precharge-sel RAS CAS WE CKE PALL ACTV READ NOP DQMLU DQMLL D7 to D0 BS RD/WR D15 to D8 Row address Figure 9.60 SDRAM Basic Read Access Timing (CAS Latency = 2)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 316 of 1438 REJ09B0365-0200 Tp Tr Tc1 Tc2 Address bus Row address Column address SDRAMφ CS Precharge-sel RAS CAS WE CKE High PALL ACTV NOP WRIT DQMLU DQMLL D7 to D0 BS RD/WR D15 to D8 Row address Figure 9.61 SDRAM Basic Write Access Timing

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 317 of 1438 REJ09B0365-0200

9.11.6 CAS Latency Control

The CAS latency is controlled by bits W21 and W20 in WTCRB. Table 9.27 lists the setting and CAS latency. CAS latency control cycles (Tcl) are inserted in a read cycle according to the W21 and W20 settings. WTCRB can be specified regardless of bit AST2 in ASTCR. Figure 9.62 shows a timing example when SDRAM with a CAS latency of 3 is in use. Bits W21 and W20 is initialized to B'11. Table 9.27 CAS Latency Setting W21 W20 Description Number of CAS Latency Cycles 0 0 Setting prohibited 

1 SDRAM with CAS latency of 2 is in use 1

1 0 SDRAM with CAS latency of 3 is in use 2

1 SDRAM with CAS latency of 4 is in use 3

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 318 of 1438 REJ09B0365-0200 Tp Tr Tc1 Tcl1 Tcl2 Tc2 Address bus Row address Column address SDRAMφ CS Precharge-sel RAS CAS WE CKE PALL ACTV READ NOP DQMLU DQMLL D7 to D0 BS RD/WR D15 to D8 Row address High Figure 9.62 Timing Example of CAS Latency (CAS Latency = 3)

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9.11.7 Controlling Row Address Output Cycle

When the time between the ACTV command and the subsequent READ or WRIT command does not meet a given specification, the Trw cycle in which the NOP command is output can be inserted for one to three cycles between the Tr cycle in which the ACTV command is output and the Tc1 cycle in which the column address is output. Set the bit according to the SDRAM to be used and the frequency of this LSI so that the number of wait cycles can be optimal. Figures 9.63 and 9.64 show a timing example when the one Trw cycle is inserted. Tp Tr Trw Tc1 Tcl Tc2 Address bus Row address Column address SDRAMφ CS Precharge-sel RAS CAS WE CKE PALL ACTV READ NOPNOP DQMLU DQMLL D7 to D0 BS RD/WR D15 to D8 Row address High Figure 9.63 Read Timing Example of Row Address Output Retained for 1 Clock Cycle (RCD1 = 0, RCD0 = 1, CAS Latency = 2)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 320 of 1438 REJ09B0365-0200 Tp Tr Trw Tc1 Tc2 Address bus Row address Column address SDRAMφ CS Precharge-sel RAS CAS WE CKE PALL ACTV WRIT NOPNOP DQMUU DQMLL D7 to D0 BS RD/WR D15 to D8 Row address High Figure 9.64 Write Timing Example of Row Address Output Retained for 1 Clock Cycle (RCD1 = 0, RCD0 = 1)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 321 of 1438 REJ09B0365-0200

9.11.8 Controlling Precharge Cycle

When the time between the PALL or PRE command and the subsequent ACTV or REF command does not meet a given specification, the Tp cycles can be extended by one to four cycles by bits TPC1 and TPC0 in DRACCR. Set the bit according to the SDRAM to be used and the frequency of this LSI so that the number of Tp cycles can be optimal. Figures 9.65 and 9.66 show a timing example when the two Tp cycles are inserted. Bits TPC1 and TPC0 are effective for the Tp cycle in a refresh cycle. Tp1 Tp2 Tr Tc1 Tcl Tc2 Address bus Row address Column address SDRAMφ CS Precharge-sel RAS CAS WE CKE PALL ACTV READ NOPNOP DQMLU DQMLL D7 to D0 BS RD/WR D15 to D8 Row address High Figure 9.65 Read Timing Example of Two Precharge Cycles (TPC1 = 0, TPC0 = 1, CAS Latency = 2)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 322 of 1438 REJ09B0365-0200 Tp1 Tp2 Tr Tc1 Tc2 Address bus Row address Column address SDRAMφ CS Precharge-sel RAS CAS WE CKE PALL ACTV NOP WRITNOP DQMLU DQMLL D7 to D0 BS RD/WR D15 to D8 Row address High Figure 9.66 Write Timing Example of Two Precharge Cycles (TPC1 = 0, TPC0 = 1)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 323 of 1438 REJ09B0365-0200

9.11.9 Controlling Clock Suspend Insertion

When the SDRAM space is read, the read data settling cycle can be inserted for one cycle using the clock suspend mode. To enter the clock suspend mode, set the CKSPE bit in SDCR and the OEE bit in DRAMCR to 1and enable the CKE pin. Figure 9.67 shows a read timing example when CKSPE = 1. Tp Tr Tc1 Tcl Tc2 Tc1 Tcl Tc2Tsp Tsp SDRAMφ CS Precharge-sel Address bus Row address Row address Column address 1 Column address 2 RAS CAS WE CKE PALL ACTV READ READ NOP NOP DQMLU DQMLL D7 to D0 BS RD/WR D15 to D8 Figure 9.67 Read Timing Example when CKSPE = 1 (CAS Latency = 2)

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9.11.10 Controlling Write-Precharge Delay

In an SDRAM write cycle, a certain time is required until the write operation is completed inside of the SDRAM. When the time between the WRIT command and the subsequent PALL command does not meet a given specification, the Trwl cycle can be inserted for one cycle by the TRWL bit in SDCR. Whether or not to insert the Trwl cycle depends on the SDRAM to be used and the frequency of this LSI. Figure 9.68 shows a timing example when one Trwl cycle is inserted. Tp Tr TrwlTc1 Tc2 Address bus Row address Column address SDRAMφ CS Precharge-sel RAS CAS WE CKE PALL ACTV WRIT NOPNOP DQMLU DQMLL D7 to D0 BS RD/WR D15 to D8 Row address High Figure 9.68 Write Timing Example when Write-Precharge Delay Cycle Insertion (TRWL = 1)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 325 of 1438 REJ09B0365-0200

9.11.11 Controlling Byte and Word Accesses

When 16-bit bus SDRAM is used, byte and word accesses are performed through the control of DQMLU and DQMLL. Figures 9.69 and 9.70 show control timing examples of the DQM signals in the big endian format. Figure 9.71 shows a connection example when the DQM signals are used for the byte and word control. Tp Tr Tc1 Tcl Tc2 Address bus Row address Column address SDRAMφ CS Precharge-sel RAS CAS WE CKE PALL ACTV READ NOP DQMLU DQMLL D7 to D0 BS RD/WR D15 to D8 Row address High High Hi-Z Figure 9.69 Control Timing Example of Byte Control by DQM in 16-Bit Access Space (Read Access with Lowest Bit of Address = B'0)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 326 of 1438 REJ09B0365-0200 Tp Tr Tc1 Tcl Tc2 Address bus Row address Column address SDRAMφ CS Precharge-sel RAS CAS WE CKE PALL ACTV READ NOP DQMLU DQMLL D7 to D0 BS RD/WR D15 to D8 Row address High Figure 9.70 Control Timing Example of Word Control by DQM in 16-Bit Access Space (Read Access with Lowest Bit of Address = B'0, CAS Latency = 2)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 327 of 1438 REJ09B0365-0200 RAS CAS WE DQMU DQML CLK CKE CS A11 (BA1) A10 (BA0) DQ15 to DQ0 RAS CAS WE DQMLU DQMLL SDφ OE/CKE CS A12 A11 A10 D15 to D0 This LSI (Address shifted by 8 bis) 64-Mbit synchronous DRAM (1 Mwords × 16 bits × 4 banks) 10-bit column address Row address: A11 to A0 Column address: A9 to A0 Bank select address: A11/A10 Figure 9.71 Connection Example of DQM Byte/Word Control

9.11.12 Fast-Page Access Operation

Besides an accessing method in which this LSI outputs a row address every time it accesses the SDRAM (called full access or normal access), some SDRAMs have a fast-page mode function in which fast speed access can be achieved by modifying only a column address with the same row address output when consecutive accesses are made to the same row address. The fast-page mode can be used by setting the BE bit in DRAMCR to 1.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 328 of 1438 REJ09B0365-0200 (1) Fast-Page Mode Operation Timing When access cycles to the SDRAM space are continued and the row addresses of the consecutive two cycles are the same, a column address output cycle follows. The row address bits to be compared are decided by bits MXC1 and MXC0 in DRAMCR. A fast-page mode access is performed when the access data size exceeds the bus width of the SDRAM and when consecutive accesses to the SDRAM are generated. Figures 9.72 and 9.73 show longword access timing of the 16-bit bus SDRAM and word access timing of the 8-bit bus SDRAM, respectively. Tp Tr Tc1 Tc2 Tc1 Tc2 CS Precharge-sel RAS CAS WE CKE PALL ACTV WRIT NOP NOP DQMLU DQMLL BS RD/WR WRIT Address bus Row address Column address 1 Column address 2 SDRAMφ D7 to D0 D15 to D8 Row address High Figure 9.72 Longword Write Timing in 16-Bit Access Space (BE = 1, RCDM = 0)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 329 of 1438 REJ09B0365-0200 Tp Tr Tc1 Tc1Tcl Tc2 Tcl Tc2 High Row address Row address Column address 1 Column address 2Address bus SDRAMφ CS Precharge-sel RAS CAS WE CKE DQMLL PALL ACTV READ READ NOP NOP D7 to D0 BS RD/WR Figure 9.73 Word Read Timing in 8-Bit Access Space (BE = 1, RCDM = 0, CAS Latency = 2)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 330 of 1438 REJ09B0365-0200 (2) RAS Down Mode Set the RCDM and BE bits in DRAMCR to 1 to make a transition to the RAS down mode. The RCDM bit is enabled only when the BE bit is set to 1. Even if the fast-page mode is selected, the DRAM space is not consecutively accessed and other spaces may be accessed. The RAS signal can be held low during other space accesses. Similarly to the DRAM RAS down mode, the READ or WRIT command can be issued without the ACTV command. However, two DQM cycles are always inserted for a SDRAM read cycle. Figures 9.74 and 9.75 show a timing example of RAS down mode. The next cycle after one of the following conditions is satisfied is a full access cycle.

• When a refresh cycle is performed during RAS down mode
• When a self-refresh is performed
• When a transition to software standby mode is made
• When the external bus requested by the BREQ signal is released
• When either the RCDM or BE bit is cleared to 0
• When setting the SDRAM mode register Some SDRAMs have a limitation on the time to hold each bank active. When such SDRAM is in use, if the user program cannot control the time (such as software standby or sleep mode), select the auto-refresh or self-refresh so that the given specification can be satisfied. If a refresh cycle is not used, the user program must control the time. Clear the RCDM bit to 0 for write access to SCKCR to set the clock frequencies. For SCKCR, see section 26, Clock Pulse Generator. (3) RAS Up Mode Clear the RCDM bit in DRAMCR to 0 to set the RAS up mode. Whenever a SDRAM space access is halted and other spaces are accessed, the next cycle is the PALL command cycle. Only when the SDRAM space continues to be accessed, the fast-page mode access is performed.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 331 of 1438 REJ09B0365-0200 Tp Tr Tc1 Tcl Tc2 Tc1 Tcl Tc2T1 T2 PALL ACTV READ READ NOP NOP Address bus Row address Row address Column address 1 Column address 2 SDRAM space read External space readSDRAM space read External address External address SDRAMφ CS Precharge-sel RAS CAS WE CKE DQMLU DQMLL D7 to D0 BS RD/WR D15 to D8 High Figure 9.74 Timing Example of RAS Down Mode (BE = 1, RCDM = 1, CAS Latency = 2)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 332 of 1438 REJ09B0365-0200 Tp Tr Tc1 Tc2Tcl Tc1 Tc2T1 T2 Address bus SDRAM space read SDRAM space read External space read Row address Row address Column address 1 Column address 2External address External address SDRAMφ CS Precharge-sel RAS CAS WE CKE PALL ACTV READ WRIT NOP DQMLU DQMLL D7 to D0 BS RD/WR D15 to D8 High Figure 9.75 Timing Example of RAS Down Mode (BE = 1, RCDM = 1, CAS Latency = 2)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 333 of 1438 REJ09B0365-0200

9.11.13 Refresh Control

This LSI includes a DRAM refresh control function. The refresh method is the auto-refresh. Self- refresh cycles can be performed in software standby mode. The refresh control function is enabled when area 2 is specified as the SDRAM space by the DRAME and DTYPE bits in DRAMCR. (1) Auto-Refresh Mode Set the RFSHE bit in REFCR to 1 to select auto-refreshing. An auto-refresh cycle is performed when the value set in RTCOR matches the RTCNT value (compare match). RTCNT is an up-counter operated on the input clock specified bits RTCK2 to RTCK0 in REFCR. RTCNT is initialized upon the compare match and restarts to count up with H'00. Accordingly, an auto-refresh cycle is repeated at intervals specified by bits RTCK2 to RTCK0 in RTCOR. Set the bits so that the required refresh intervals of the DRAM must be satisfied. Since setting bits RTCK2 to RTCK0 starts RTCNT to count up, set RTCNT and RTCOR before setting bits RTCK2 to RTCK0. When changing RTCNT and RTCOR, the count operation should be halted. When changing bits RTCK2 to RTCK0, change them only after disabling the external access and external bus release by the EXDMAC, if the write data buffer function is in use, disabling the write data buffer function and reading the external space. The external space cannot be accessed during auto-refresh.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 334 of 1438 REJ09B0365-0200 TRp TRr TRc1 TRc2 Address bus SDRAMφ CS Precharge-sel RAS CAS WE CKE PALL REF NOP BS RD/WR High High High Figure 9.76 Auto-Refresh Operation

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 337 of 1438 REJ09B0365-0200 (2) Self-Refresh Mode Some SDRAMs have a self-refresh mode (battery backup mode). The self-refresh is a kind of standby mode and refresh timing and refresh address are controlled internally. (a) Self-Refresh in Software Standby Mode The self-refresh is selected by setting the RFSHE and SLFRF bits in REFCR to 1. The SELF- command is issued as shown in figure 9.79 by executing the SLEEP instruction to enter the software standby mode. When an auto-refresh is requested on a transition to the software standby mode, the auto-refresh is first performed and then the self-refresh is entered. When making a transition to the self-refresh, set the OEE bit in SBYCR to 1 and connect the CKE pin. When the self-refresh is used, do not clear the OPE bit in SBYCR to 0. TRp TRr TRc2 TRc3 CS Precharge-sel RAS CAS WE CKE PALL SELF NOP Software standby BS RD/WR Address bus SDRAMφ High High Figure 9.79 Self-Refresh Timing in software standby mode (TPC1 = 0, TPC0 = 0, RCW1 = 0, RCW0 = 0, RLW2 = 0, RLW1 = 0, RLW0 = 0)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 339 of 1438 REJ09B0365-0200 (b) Self-Refresh in Deep Software Standby Mode The chip passes through the software standby mode in transitions to deep software standby mode. The states of pins in software standby mode are retained in the deep software standby mode. Therefore, the transition to self-refreshing is possible in deep software standby mode as well as in software standby mode. In deep software standby mode, initiate the transition to the self-refresh after having set the IOKEEP bit in DPSBYCR to 1 as well as making the setting in "(a) Self-Refresh in Software Standby Mode ". On exit from deep software standby mode, use the following procedure to cancel self-refresh. (See figure 9.81). 1. In PBDDR/PBDR, set PB1 ( CS2) as a high-level output and PB5(CKE) as a low-level output. Since the setting of the IOKEEP bit ensures retention of pin state at this time, the existing state of high-level output on CS2 and low-level output on is retained. 2. Set the PSTOP0 bit in SCKCR to1 and SDRAM φ as a high level output. Since the setting of the IOKEEP bit continues to ensure retention of pin state, the existing state of high- level output on SDRAMφ is retained. 3. Clear the IOKEEP bit in DPSBYCR. This releases pin states from retention due to the setting of the IOKEEP bit, but the states of pins CS2, CKE, and SDRAMφ as set in steps 1and 2 do not change. 4. In the synchronous DRAM-related control regi sters that were initialized by the internal reset that accompanied the transition to deep software standby mode, remake the settings to enable the synchronous DRAM interface. At this time, do not make settings in REFCR, RTCNT, and RTCOR. Once the synchronous DRAM interface has been enabled, the state of the CKE pin changes from low-level output to high-level output. 5. Restart output of the SDRAM φ clock signal by clearing the PSTOP0 bit in SCKCR. This restarts supply of SDRAMφ to the synchronous DRAM. 6. Set REFCR, RTCNT, and RTCOR and enable refreshing. As the state of the CKE pin has been changed in the step 4, adjust the time between the state of change of the CKE pin and the next cycle of auto-refreshing in this procedure within the stipulated refreshing interval of the synchronous DRAM. 7. Resume access to the synchronous DRAM. Pre-charging time after the termination of self-refresh will be secured by the timing of the setting in step 6.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 340 of 1438 REJ09B0365-0200 For details on the software standby mode and deep software standby mode, see section 27, Power-Down Modes. EXTAL SDRAMφ Precharge-sel CS2 RAS CAS WE CKE Internal reset Address bus TRp TRr Deep software standby mode PSTOP0 set PSTOP0 clear IOKEEP clear Port setting PB1/CS2 = H output setting PB5/CKE = L output setting Register setting in SDRAM (DRAMCR, etc.) REFCR, RTCNT, RTCOR Pin status saved with deep software standby mode (IOKEEP=1) Pin status depends on I/O port register Pin status in DRAM interface Figure 9.81 Self-Refresh Timing in Deep Software Standby Mode (TPC1 = 0, TPC0 = 0, RCW1 = 0, RCW0 = 0, RLW2 = 0, RLW1 = 0, RLW0 = 0)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 341 of 1438 REJ09B0365-0200 (3) Refresh and All-Module Clock Stop Mode This LSI is entered in all-module clock stop mode by the following operation: Stop the clocks of all on-chip peripheral modules by setting the ACSE bit in MSTPCRA to 1 (MSTPCRA, MSTPCRB = H'FFFFFFFF) or run only the 8-bit timer (MSTPCRA, MSTPCRB = H'F[C to F]FFFFFF), then execute the SLEEP instruction to enter the sleep mode. In all-module clock stop mode, clocks for the bus controller and I/O ports are stopped. Since the clock for the bus controller is stopped, an auto-refresh cycle cannot be performed. When external SDRAM is used and the contents of the SDRAM in sleep mode should be held, clear the ACSE bit in MSTPCE to 0. For details, see section 27.2.2, Module Stop Control Registers A and B (MSTPCRA and MSTPCRB).

9.11.14 Setting SDRAM Mode Register

To use SDRAM, the mode register must be specified after a power-on reset. Setting the MRSE bit in SDCR to 1 enables the SDRAM mode register setting. After this, write to the SDRAM space in bytes. When the value to be set in the SDRAM mode register is x, write to the following memory location (address). The value of x is written to the SDRAM mode register.

• H'4000000/H'400000 + x for 8-bit bus SDRAM
• H'4000000/H'400000 + 2x for 16-bit bus SDRAM The SDRAM mode register latches the address signals when the MRS command is issued. This LSI does not support the burst read/burst write mode of SDRAM. When setting the SDRAM mode register, use the burst read/single write mode and set the burst length to 1. Setting in the SDRAM mode register must be consistent with that in the bus controller.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 342 of 1438 REJ09B0365-0200 Figure 9.82 shows the timing of setting SDRAM mode register. Tp Tr Tc1 CS RAS CAS WE CKE High Mode register setting Mode register setting BS High RD/WR High PALL NOP MRS NOP Tc2 Precharge-sel Address bus SDRAMφ Figure 9.82 Timing of Setting SDRAM Mode Register

9.11.15 SDRAM Interface and Single Address Transfer by DMAC and EXDMAC

When fast-page mode (BE = 1) is set for the SDRAM space, either fast-page access or full access can be selected, by the setting of bits DDS and EDDS in DRAMCR, for the single address transfer by the DMAC or EXDMAC where the SDRAM space is specified as the transfer source or destination. At the same time, the output timing of the DACK and EDACK and BS signals can be changed. When BE = 0, a full access to the SDRAM space is performed with a single address transfer regardless of the setting of bits DDS and EDDS. However, the output timing of the DACK, EDACK and BS signals can be changed by the setting of bits DDS and EDDS. The assertion timing of the DACK and EDACK signals can be changed by the bits DKC and EDKC in BCR1. The output timing of the DACK and EDACK signals can be independently set by the bits TRWL and CKSPE in SDCR and bit DKC and EDKC in BCR1 regardless of the setting of bits DDS and EDDS.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 343 of 1438 REJ09B0365-0200 (1) When DDS = 1 or EDDS = 1 A fast-page access is performed regardless of the bus master, only according to the address. The DACK and EDACK signals are asserted within the Tc1 cycle in both read and write accesses. Figures 9.83 and 9.84 show the output timing example of the DACK and EDACK signals when DDS = 1 or EDDS = 1. Tp Tr Tc1 Tc2 Tc1 Tc2 CS Precharge-sel RAS CAS WE CKE PALL ACTV NOP NOP WRIT WRIT DQMLU DQMLL D7 to D0 BS DACK or EDACK RD/WR D15 to D8 Address bus Row address Row address Column address 1 Column address 2 SDRAMφ High Figure 9.83 Output Timing Example of DACK and EDACK when DDS = 1 or EDDS = 1 (Write)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 344 of 1438 REJ09B0365-0200 CS Precharge-sel RAS CAS WE CKE High DQMLU DQMLL D7 to D0 BS DACK or EDACK RD/WR D15 to D8 Address bus Row address Row address Column address 1 Column address 2 SDRAMφ Tp Tr Tc1 Tcl Tc2 Tc1 Tcl Tc2 PALL ACTV READ READ NOP NOP Figure 9.84 Output Timing Example of DACK and EDACK when DDS = 1 or EDDS = 1 (Read, CAS Latency = 2)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 345 of 1438 REJ09B0365-0200 (2) When DDS = 0 or EDDS = 0 Single address transfer by the DMAC or EXDMAC takes place as a full access (normal access) to the SDRAM space. The DACK and EDACK signals are asserted within the Tr cycle and the BS signal is also asserted in the Tr cycle. When the SDRAM space is accessed with other than the single address transfer by the DMAC or EXDMAC, a fast-page access is available. Figures 9.85 and 9.86 show an output timing example of the DACK and EDACK signals when DDS = 0 or EDDS = 0. Tp Tr Tc1 Tc2 Address bus Row address Column address SDRAMφ CS Precharge-sel RAS CAS WE CKE PALL ACTV WRIT NOP DQMLU DQMLL D7 to D0 BS RD/WR D15 to D8 Row address High DACK or EDACK Figure 9.85 Output Timing Example of DACK and EDACK when DDS = 0 or EDDS = 0 (Write)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 346 of 1438 REJ09B0365-0200 Tp Tr Tc1 Tcl Tc2 Address bus Row address Cloumn address SDRAMφ CS Precharge-sel RAS CAS WE CKE PALL ACTV READ NOP DQMLU DQMLL D7 to D0 BS RD/WR D15 to D8 Row address High DACK or EDACK Figure 9.86 Output Timing Example of DACK and EDACK when DDS = 0 or EDDS = 0 (Read, CAS Latency = 2)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 350 of 1438 REJ09B0365-0200 Tp Tr Tc1 Tc2 Address bus Row address Cloumn address SDRAMφ CS Precharge-sel RAS CAS WE CKE PALL ACTV WRIT NOP DQMLU DQMLL D7 to D0 BS RD/WR D15 to D8 Row address High DACK or EDACK Figure 9.90 Output Timing Example of DACK and EDACK when DKC = 1 or EDKC = 1 and DDS = 0 or EDDS = 0 (Write)

9.11.16 EXDMAC Cluster Transfer

Using an EXDMAC cluster transfer mode, data can be read from or written to consecutively. For details, see section 11, EXDMA Controller (EXDMAC). Figures 9.91 and 9.92 show a read/write timing using a cluster transfer. For 1-cycle read or write, set the BE bit in DRAMCR to 1, clear the TRWL bit in SDCR to 0, and set the CAS latency to 2. During a read cycle, the clock suspend mode cannot be used. Do not change the bus controller register settings during a cluster transfer.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 351 of 1438 REJ09B0365-0200 A refresh cycle is not executed during a consecutive cluster transfer even if a refresh request is generated. Therefore, user program must control the time so that each bank should not be activated over a given specification. The external bus is not released during a cluster transfer. Tp Tr Tcb Tc2TcbTcb Tcb Tcb Tc1 Tcl PALL ACTV READ NOP Address bus Row Cloumn 1 Cloumn 2 Cloumn 3 Cloumn 4 Cloumn 5 Cloumn 6 SDRAMφ CS Precharge-sel RAS CAS WE CKE DQMUU DQMUL D31 to D24 D23 to D16 DQMLU DQMLL D7 to D0 BS RD/WR D15 to D8 Row High Figure 9.91 Word-Size 6-Word Cluster Transfer (Read, BE = 1, EDDS = 1, CAS Latency = 2)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 352 of 1438 REJ09B0365-0200 Tp Tr Tc1 Tc2 Tcb Tcb Tcb Tcb Tcb PALL ACTV WRITNOP Address bus Row Cloumn 1 Cloumn 2 Cloumn 3 Cloumn 4 Cloumn 5 Cloumn 6 SDRAMφ CS Precharge-sel RAS CAS WE CKE DQMUU DQMUL D31 to D24 D23 to D16 DQMLU DQMLL D7 to D0 BS RD/WR D15 to D8 Row High Figure 9.92 Word-Size 6-Word Cluster Transfer (Write, BE = 1, EDDS = 1)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 353 of 1438 REJ09B0365-0200

9.12 Idle Cycle

In this LSI, idle cycles can be inserted between the consecutive external accesses. By inserting the idle cycle, data conflicts between ROM read cycle whose output floating time is long and an access cycle from/to high-speed memory or I/O interface can be prevented.

9.12.1 Operation

When this LSI consecutively accesses external address space, it can insert an idle cycle between bus cycles in the following four cases. These conditions are determined by the sequence of read and write and previously accessed area. 1. When read cycles of different areas in the external address space occur consecutively 2. When an external write cycle occurs immediately after an external read cycle 3. When an external read cycle occurs immediately after an external write cycle 4. When an external access oc curs immediately after a DMAC or EXDMAC* single address transfer (write cycle) Up to four idle cycles can be inserted under the conditions shown above. The number of idle cycles to be inserted should be specified to prevent data conflicts between the output data from a previously accessed device and data from a subsequently accessed device. Under conditions 1 and 2, which are the conditions to insert idle cycles after read, the number of idle cycles can be selected from setting A specified by bits IDLCA1 and IDLCA0 in IDLCR or setting B specified by bits IDLCB1 and IDLCB0 in IDLCR: Setting A can be selected from one to four cycles, and setting B can be selected from one or two to four cycles. Setting A or B can be specified for each area by setting bits IDLSEL7 to IDLSEL0 in IDLCR. Note that bits IDLSEL7 to IDLSEL0 correspond to the previously accessed area of the consecutive accesses. The number of idle cycles to be inserted under conditions 3 and 4, which are conditions to insert idle cycles after write, can be determined by setting A as described above. After the reset release, IDLCR is initialized to four idle cycle insertion under all conditions 1 to 4 shown above. Table 9.28 shows the correspondence between conditions 1 to 4 and number of idle cycles to be inserted for each area. Table 9.29 shows the correspondence between the number of idle cycles to be inserted specified by settings A and B, and number of cycles to be inserted. Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 354 of 1438 REJ09B0365-0200 Table 9.28 Number of Idle Cycle Insertion Selection in Each Area Bit Settings IDLSn IDLSELn Area of Previous Access Insertion Condition n Setting n = 0 to 7 0 1 2 3 4 5 6 7 0  Invalid

0 A A A A A A A A

Consecutive reads in different areas 1

1 B B B B B B B B

0  Invalid

0 Invalid Read after write 2

A

0 Invalid External access after single address

A [Legend] A: Number of idle cycle insertion A is selected. B: Number of idle cycle insertion B is selected. Invalid: No idle cycle is inserted for the corresponding condition. Table 9.29 Number of Idle Cycles Inserted Bit Settings A B IDLCA1 IDLCA0 IDLCB1 IDLCB0 Number of Cycles   0 0 0 0 0   1 0 1 0 1 2 1 0 1 0 3 1 1 1 1 4

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 360 of 1438 REJ09B0365-0200 (6) Relationship between Chip Select (CS) Signal and Read (RD) Signal Depending on the system's load conditions, the RD signal may lag behind the CS signal. An example is shown in figure 9.98. In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the RD signal in bus cycle A and the CS signal in bus cycle B. Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS signals. In the initial state after reset release, idle cycle indicated in (b) is set. Bus cycle A Bus cycle B Bφ Address bus CS (area A) CS (area B) RD T1 T2 T3 T1 T2 Bus cycle A Bus cycle B T1 T2 T3 T1Ti T2 Overlap time may occur between the CS (area B) and RD (a) No idle cycle inserted (IDLS1 = 0) (b) Idle cycle inserted (IDLS1 = 1, IDLSELn = 0, IDLCA1 = 0, IDLCA0 = 0) Figure 9.98 Relationship between Chip Select (CS) and Read (RD)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 361 of 1438 REJ09B0365-0200 (7) Idle Cycle for Accessing to DRAM/SDRAM Space In the following read cycles, when the DRAM/SDRAM space is accessed in a full access, the Tp and Tr cycles are also counted as idle cycles. Figures 9.99 and 9.100 show timing examples of full accesses to the DRAM/SDRAM space when four idle cycles are inserted. When accessing the DRAM/SDRAM space, the Ti cycles are inserted so that the sum of the numbers of Tp (precharge), Tr (row address output), and Ti cycles satisfies the specified number of idle cycles. The Ti cycles are inserted before the column address output cycle. While the SDRAM space is accessed in a full access, the CS2 signal is driven low even in an idle cycle. The idle cycle insertion is enabled even in a fast-page access in RAS down mode. The specified number of idle cycles is inserted. Figure 9.101 shows a timing example of the idle cycle insertion in RAS down mode. Note: Supported only by the H8SX/1648G Group and the H8SX/1648H Group. Bφ Address bus RD RAS LLCAS T1 T2 T3 TrTp Ti Tc1Ti Tc2 External space read DRAM space read Data bus Figure 9.99 Example of DRAM Full Access after External Read (CAST = 0)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 362 of 1438 REJ09B0365-0200 T1 T2 T3 TclTc1TrTp Tc2TiTi Address bus External space (area A) read SDRAM space read Data bus SDRAMφ CS (area A) CS (area 2) RAS RD CAS WE DQMLL Figure 9.100 Example of SDRAM Full Access after External Read (CAS Latency = 2)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 363 of 1438 REJ09B0365-0200 Tp Address bus Bφ RD RAS UCAS, LCAS External space read Idle cycle Data bus Tr Tc1 Tc2 T1 DRAM space writeDRAM space read T2 Tc2 WR T3 Ti Tc1 Figure 9.101 Example of Idle Cycles in RAS Down Mode (Write after Read)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 364 of 1438 REJ09B0365-0200 Table 9.30 Idle Cycles in Mixed Accesses to Normal Space and DRAM/SDRAM Space IDLS IDLSEL IDLCA IDLCB Previous Access Next Access 3 2 1 0 7 to 0 1 0 1 0 Idle Cycle   1  0 0 0   1 cycle inserted Normal/DRAM/ SDRAM space read Normal/DRAM/ SDRAM space read 0 1 2 cycles inserted 1 0 3 cycles inserted 1 1 4 cycles inserted 1   0 0 0 cycle inserted 0 1 2 cycles inserted 1 0 3 cycles inserted 1 1 4 cycles inserted    1 0 0 0   1 cycle inserted Normal/DRAM/ SDRAM space read Normal/DRAM/ SDRAM space read 0 1 2 cycles inserted 1 0 3 cycles inserted 1 1 4 cycles inserted 1 0 0 0 cycle inserted 0 1 2 cycles inserted 1 0 3 cycles inserted 1 1 4 cycles inserted  1    0 0   1 cycle inserted Normal/DRAM/ SDRAM space write Normal/DRAM/ SDRAM space read 0 1 2 cycles inserted 1 0 3 cycles inserted 1 1 4 cycles inserted 0         Disabled Single address write Normal/DRAM/ SDRAM space write 1     0 0   1 cycle inserted 0 1 2 cycles inserted 1 0 3 cycles inserted 1 1 4 cycles inserted

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 365 of 1438 REJ09B0365-0200

9.12.2 Pin States in Idle Cycle

Table 9.31 shows the pin states in an idle cycle. Table 9.31 Pin States in Idle Cycle Pins Pin State A23 to A0 Contents of following bus cycle D15 to D0 High impedance CSn (n = 7 to 0) High * LUCAS, LLCAS* High DQMLU, DQMLL* High * AS High RD High BS High RD/WR High * AH low LHWR, LLWR High LUB, LLB High CKE* High OE* High RAS* High/Low * CAS* High WE* High DACKn (n = 3 to 0) High EDACKn (n = 3 to 0) * High Notes: 1. Low when accessing the SDRAM * in full access cycle 2. Low when reading the SDRAM * in full access cycle 3. Low when accessing or writing to the DRAM/SDRAM * in full access cycle 4. The pin state varies depending on the DRAM space access/ area access other than the DRAM space, or RAS up mode/RAS down mode. For details, see figures 9.98 and 9.100. 5. Supported only by the H8SX/1 648G Group and the H8SX/1648H Group.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 366 of 1438 REJ09B0365-0200

9.13 Bus Release

This LSI can release the external bus in response to a bus request from an external device. In the external bus released state, the internal bus masters other than the EXDMAC* continue to operate as long as there is no external access. In addition, in the external bus released state, the BREQO signal can be driven low to output a bus request externally. Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.

9.13.1 Operation

In external extended mode, when the BRLE bit in BCR1 is set to 1, and the ICR bit for the corresponding pin is set to 1, the bus can be released to the external. Driving the BREQ pin low issues an external bus request to this LSI. When the BREQ pin is sampled, at the prescribed timing, the BACK pin is driven low, and the address bus, data bus, and bus control signals are placed in the high-impedance state, establishing the external bus released state. For ICR, see section 13, I/O Ports. In the external bus released state, the CPU, DTC, DMAC can access the internal space using the internal bus. When any one of the CPU, DTC, DMAC, and EXDMAC*attempts to accesses the external address space, it temporarily defers initiation of the bus cycle, and waits for the bus request from the external bus master to be canceled. In the external bus released state, certain operations are suspended as follows until the bus request from the external bus master is canceled:

• When a refresh is requested, refresh control is suspended.
• When the SLEEP instruction is executed to enter software standby mode or all-module clock- stop mode, control for software standby mode or all-module clock-stop mode is suspended.
• When SCKCR is written to set the clock frequencies, changing of clock frequencies is suspended. For SCKCR, see section 26, Clock Pulse Generator. If the BREQOE bit in BCR1is set to 1, the BREQO pin can be driven low to request cancellation of the bus request when any of the following requests are issued.
• When any one of the CPU, DTC, DMAC, and EXDMAC* attempts to access the external address space
• When a refresh* is requested

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 367 of 1438 REJ09B0365-0200

• When a SLEEP instruction is executed to place the chip in software standby mode or all- module-clock-stop mode
• When SCKCR is written to set the clock frequencies If an external bus release request, external access, and a refresh* request occur simultaneously, the order of priority is as follows: Refresh* > EXDMAC* > External bus release > External access by CPU, DTC, and DMAC Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.

9.13.2 Pin States in External Bus Released State

Table 9.32 shows pin states in the external bus released state.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 368 of 1438 REJ09B0365-0200 Table 9.32 Pin States in Bus Released State Pins Pin State A23 to A0 High impedance D15 to D0 High impedance BS High impedance CSn (n = 7 to 0) High impedance AS High impedance AH High impedance RD/WR High impedance LUCAS, LLCAS* High impedance RD High impedance RAS* High impedance CAS* High impedance WE High impedance DQMLU, DQMLL* High impedance CKE* High impedance OE* High impedance LUB, LLB High impedance LHWR, LLWR High impedance DACKn (n = 3 to 0) High EDACKn (n = 3 to 0)* High Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 369 of 1438 REJ09B0365-0200

9.13.3 Transition Timing

Figures 9.102 and 9.103* show the timing of transition to the bus released state. Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group. Bφ Address bus CSn LHWR, LLWR AS Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z RD BREQ BACK BREQO External space access cycle CPU cycleExternal bus released state Data bus T1 T2 [1] A low level of the BREQ signal is sampled at the rising edge of the Bφ signal. [2] The bus control signals are driven high at the end of the external space access cycle. It takes two cycles or more after the low level of the BREQ signal is sampled. [3] The BACK signal is driven low, releasing bus to the external bus master. [4] The BREQ signal state sampling is continued in the external bus released state. [5] A high level of the BREQ signal is sampled. [6] The external bus released cycles are ended one cycle after the BREQ signal is driven high. [7] When the external space is accessed by an internal bus master during external bus released while the BREQOE bit is set to 1, the BREQO signal goes low. [8] Normally the BREQO signal goes high at the rising edge of the BACK signal. Figure 9.102 Bus Released State Transition Timing (SRAM Interface is Not Used)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 370 of 1438 REJ09B0365-0200 SDRAMφ Address bus RAS CAS Precharge-sel NOP PALL NOP NOP Hi-Z Hi-Z Hi-Z Hi-Z CS2 Hi-Z WE Hi-Z Hi-Z Hi-Z CKE BREQ BACK BREQO Hi-Z Data bus T1 T2 DQMLU, DQMLL External access cycle CPU cycleExternal bus released state [1] A low level of the BREQ signal is sampled at the rising edge of the Bφ signal. [2] The PALL command is issued. [3] The bus control signals are driven high at the end of the external access cycle. It takes two cycles or more after the low level of the BREQ signal is sampled. [4] The BACK signal is driven low, releasing bus to the external bus master. [5] The BREQ signal state sampling is continued in the external bus released state. [6] A high level of the BREQ signal is sampled. [7] The BACK signal is driven high, ending external bus release cycle after one cycle. [8] When the external space is accessed by an internal bus master or a refresh cycle is requested during external bus released while the BREQOE bit is set to 1, the BREQO signal goes low. [9] Normally the BREQO signal goes high at the rising edge of the BACK signal. Figure 9.103 Bus Released State Transition Timing (SRAM Interface is Used)

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 371 of 1438 REJ09B0365-0200

9.14 Internal Bus

9.14.1 Access to Internal Address Space

The internal address spaces of this LSI are the on-chip ROM space, on-chip RAM space, and register space for the on-chip peripheral modules. The number of cycles necessary for access differs according the space. Table 9.33 shows the number of access cycles for each on-chip memory space. Table 9.33 Number of Access Cycles for On-Chip Memory Spaces Access Space Access Number of Access Cycles Read One I φ cycle On-chip ROM space Write Three I φ cycles Read One I φ cycle On-chip RAM space Write One I φ cycle In access to the registers for on-chip peripheral modules, the number of access cycles differs according to the register to be accessed. When the dividing ratio of the operating clock of a bus master and that of a peripheral module is 1 : n, synchronization cycles using a clock divided by 0 to n-1 are inserted for register access in the same way as for external bus clock division. Table 9.34 lists the number of access cycles for registers of on-chip peripheral modules.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 372 of 1438 REJ09B0365-0200 Table 9.34 Number of Access Cycles for Registers of On-Chip Peripheral Modules Number of Cycles Module to be Accessed Read Write Write Data Buffer Function DMAC and EXDMAC* registers Two Iφ Disabled MCU operating mode, clock pulse generator, power-down control registers, interrupt controller, bus controller, DTC registers, and LVD* registers. Two Iφ Three I φ Disabled I/O port registers of PFCR and WDT Two Pφ Three P φ Disabled I/O port registers other than PFCR, PORTM* ,and TPU, PPG0, TMR0, TMR1, SCI0 to SCI4, IIC2_0, IIC2_1, A/D_0, and D/A registers Two Pφ Enabled I/O port registers of PORTM* , N, TMR2, TMR3, SCI5, SCI6, IIC2_3, IIC2_4, A/D_1, AD_2, and PPG1 registers Three Pφ Enabled Notes: 1. Supported only by the H8 SX/1648G Group and the H8SX/1648H Group. 2. Supported only by the H8SX/1 648L Group and the H8SX/1648H Group.

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9.15 Write Data Buffer Function

9.15.1 Write Data Buffer Function for External Data Bus

This LSI has a write data buffer function for the external data bus. Using the write data buffer function enables internal accesses in parallel with external writes or DMAC single address transfers. The write data buffer function is made available by setting the WDBE bit to 1 in BCR1. Figure 9.104 shows an example of the timing when the write data buffer function is used. When this function is used, if an external address space write or a DMAC single address transfer continues for two cycles or longer, and there is an internal access next, an external write only is executed in the first two cycles. However, from the next cycle onward, internal accesses (on-chip memory or internal I/O register read/write) and the external address space write rather than waiting until it ends are executed in parallel. On-chip memory read Peripheral module read Peripheral module address External write cycle On-chip memory 2 On-chip memory 1 External address Internal address bus Bφ Address bus CSn LHWR, LLWR D15 to D0 Write to external space T

1 T2 T3

Iφ Figure 9.104 Example of Timing when Write Data Buffer Function is Used

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9.15.2 Write Data Buffer Function for Peripheral Modules

This LSI has a write data buffer function for the peripheral module access. Using the write data buffer function enables peripheral module writes and on-chip memory or external access to be executed in parallel. The write data buffer function is made available by setting the PWDBE bit in BCR2 to 1. For details on the on-chip peripheral module registers, see table 9.34, Number of Access Cycles for Registers of On-Chip Peripheral Modules in section 9.14, Internal Bus. Figure 9.105 shows an example of the timing when the write data buffer function is used. When this function is used, if an internal I/O register write continues for two cycles or longer and then there is an on-chip RAM, an on-chip ROM, or an external access, internal I/O register write only is performed in the first two cycles. However, from the next cycle onward an internal memory or an external access and internal I/O register write are executed in parallel rather than waiting until it ends. On-chip memory read Peripheral module write Peripheral module address Internal address bus Pφ Iφ Internal I/O address bus Internal I/O data bus Figure 9.105 Example of Timing when Peripheral Module Write Data Buffer Function is Used

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9.16 Bus Arbitration

This LSI has bus arbiters that arbitrate bus mastership operations (bus arbitration). This LSI incorporates internal access and external access bus arbiters that can be used and controlled independently. The internal bus arbiter handles the CPU, DTC, and DMAC accesses. The external bus arbiter handles the external access by the CPU, DTC, DMAC, and EXDMAC*, refresh*, and external bus release request (external bus master). The bus arbiters determine priorities at the prescribed timing, and permit use of the bus by means of the bus request acknowledge signal. Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.

9.16.1 Operation

The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master. If there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. The priority of the internal bus arbitration: DMAC > DTC > CPU The priority of the external bus arbitration: Refresh* > EXDMAC* > External bus release request > External access by the CPU, DTC, or DMAC If the DMAC or DTC accesses continue, the CPU can be given priority over the DMAC or DTC to execute the bus cycles alternatively between them by setting the IBCCS bit in BCR2. In this case, the priority between the DMAC and DTC does not change. If an external bus release request, an EXDMAC* access, and a refresh* cycle request continue, an external bus access by the CPU, DTC, and DMAC can be given priority to execute the bus cycles alternatively between them by setting the EBCCS bit in BCR2. In this case, the priorities among the refresh*, EXDMAC*, and external bus release request do not change. An internal bus access by internal bus masters and an external bus access by an external bus release request, a refresh* cycle, or an EXDMAC* access can be executed in parallel. Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.

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9.16.2 Bus Transfer Timing

Even if a bus request is received from a bus master with a higher priority over that of the bus master that has taken control of the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific timings at which each bus master can release the bus. (1) CPU The CPU is the lowest-priority bus master, and if a bus request is received from the DTC or DMAC, the bus arbiter transfers the bus to the bus master that issued the request. When the CPU accesses the external space and a bus request is received from the EXDMAC*, the external bus arbiter transfer the bus to the EXDMAC*. The timing for transfer of the bus is at the end of the bus cycle. In sleep mode, the bus is transferred synchronously with the clock. Note, however, that the bus cannot be transferred in the following cases.

• The word or longword access is performed in some divisions.
• Stack handling is performed in multiple bus cycles.
• Transfer data read or write by memory transfer instructions, block transfer instructions, or TAS instruction. (In the block transfer instructions, the bus can be transferred in the write cycle and the following transfer data read cycle.)
• From the target read to write in the bit manipulation instructions or memory operation instructions. (In an instruction that performs no write operation according to the instruction condition, up to a cycle corresponding the write cycle) Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group. (2) DTC The DTC sends the internal bus arbiter a request for the bus when an activation request is generated. When the DTC accesses an external bus space, the DTC first takes control of the bus from the internal bus arbiter and then requests a bus to the external bus arbiter. Once the DTC takes control of the bus, the DTC continues the transfer processing cycles. If a bus master whose priority is higher than the DTC requests the bus, the DTC transfers the bus to the higher priority bus master. If the IBCCS bit in BCR2 is set to 1, the DTC transfers the bus to the CPU.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 377 of 1438 REJ09B0365-0200 Note, however, that the bus cannot be transferred in the following cases.

• During transfer information read
• During the first data transfer
• During transfer information write back The DTC releases the bus when the consecutive transfer cycles completed. (3) DMAC The DMAC sends the internal bus arbiter a request for the bus when an activation request is generated. When the DMAC accesses an external bus space, the DMAC first takes control of the bus from the internal bus arbiter and then requests a bus to the external bus arbiter. After the DMAC takes control of the bus, it may continue the transfer processing cycles or release the bus at the end of every bus cycle depending on the conditions. The DMAC continues transfers without releasing the bus in the following case:
• Between the read cycle in the dual-address mode and the write cycle corresponding to the read cycle If no bus master of a higher priority than the DMAC requests the bus and the IBCCS bit in BCR2 is cleared to 0, the DMAC continues transfers without releasing the bus in the following cases:
• During 1-block transfers in the block transfer mode
• During transfers in the burst mode In other cases, the DMAC transfers the bus at the end of the bus cycle. (4) EXDMAC The EXDMAC sends the external bus arbiter a request for the bus when an activation request is generated. If an internal bus master accesses the external space, the bus is passed to the EXDMAC when the bus master can release the bus. Some EXDMAC transfers are continued once it takes control of the bus. Some EXDMAC transfers are divided and it releases the bus for each transfer cycle.
• Transfers are continued without bus release between a read cycle and the subsequent write cycle in dual address mode
• Transfers are continued without bus release in cluster transfer mode

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• Transfers are continued without bus release when a bus master with priority over the DMAC is not requesting the bus, the EBCCS bit in BCR2 is cleared to 0, and either the following conditions are executed.  While one block of data is being transferred in block transfer mode  While data is being transferred in burst mode A transfer other than the above is stopped and the bus is passed when the bus cycle is completed. However, the EXDMAC takes control of the bus and EXDMAC transfers are continued when multiple channels in the EXDMAC request the bus while other bus masters are not requesting the bus. Note: Supported only by the H8SX/1648G Group and the H8SX/1648H Group. (5) External Bus Release When the BREQ pin goes low and an external bus release request is issued while the BRLE bit in BCR1 is set to 1 with the corresponding ICR bit set to 1, a bus request is sent to the bus arbiter. External bus release can be performed on completion of an external bus cycle. (6) Refresh When area 2 is specified as the DRAM space or SDRAM space with the RFSHE bit in REFCR set to 1, RTCNT starts to count up. When the RTCOR value matches RTCNT, a bus request is sent to the bus arbiter. A refresh cycle is inserted on completion of the external bus cycle. A refresh cycle is not consecutively inserted. Once a refresh cycle is inserted, the bus is passed to another bus master. When the bus is passed, if there is no bus request from other bus masters, NOP cycles are inserted. Note: Supported only by the H8SX/1648G Group and the H8SX/1648H Group.

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9.17 Bus Controller Operation in Reset

In a reset, this LSI, including the bus controller, enters the reset state immediately, and any executing bus cycle is aborted.

9.18 Usage Notes

(1) Setting Registers The BSC registers must be specified before accessing the external address space. In on-chip ROM disabled mode, the BSC registers must be specified before accessing the external address space for other than an instruction fetch access. (2) Mode Settings The burst read-burst write mode of synchronous DRAM is not supported. When setting the mode register of synchronous DRAM, the burst read-single write mode must be selected and the burst length must be 1. Note: Supported only by the H8SX/1648G Group and the H8SX/1648H Group. (3) External Bus Release Function and All-Module-Clock-Stop Mode In this LSI, if the ACSE bit in MSTPCRA is set to 1 and a SLEEP instruction is executed to enter the sleep state after shutting off the clocks to all peripheral modules (MSTPCRA and MSTPCRB = H'FFFFFFF) or allowing operation of the 8-bit timer module alone (MSTPCRA and MSTPCRB = H'F[C to F]FFFFFF), the all-module-clock-stop mode is entered in which the clock for the bus controller and I/O ports is also stopped. For details, see section 27, Power-Down Modes. In this state, the external bus release function is halted. To use the external bus release function in sleep mode, the ACSE bit in MSTPCRA must be cleared to 0. Conversely, if a SLEEP instruction to place the chip in all-module-clock-stop mode is executed in the external bus released state, the transition to all-module-clock-stop mode is deferred and performed until after the bus is recovered. (4) External Bus Release Function and Software Standby Mode In this LSI, internal bus master operation does not stop even while the bus is released, as long as the program is running in on-chip ROM, etc., and no external access occurs. If a SLEEP instruction to place the chip in software standby mode is executed while the external bus is released, the transition to software standby mode is deferred and performed after the bus is recovered.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 380 of 1438 REJ09B0365-0200 Also, since clock oscillation halts in software standby mode, if the BREQ signal goes low in this mode, indicating an external bus release request, the request cannot be answered until the chip has recovered from the software standby mode. Note that the BACK and BREQO pins are both in the high-impedance state in software standby mode. (5) External Bus Release Function and CBR-Refresh or Auto-Refresh Cycle The CBR refresh or auto-refresh cycle cannot be performed while the external bus is released. When a CBR-refresh or an auto-refresh cycle is requested, the BREQO signal can be output by setting the BREQOE bit in BCR1 to 1. (6) BREQO Output Timing When the BREQOE bit is set to 1 and the BREQO signal is output, both the BREQO and BACK signals may go low simultaneously. This will occur if the next external access request occurs while internal bus arbitration is in progress after the chip samples a low level of the BREQ signal. Note: Supported only by the H8SX/1648G Group and the H8SX/1648H Group. (7) Refresh Settings In single-chip activation mode, the setting of the RFSHE bit in REFCR should be made after setting the EXPE bit in SYSCR to 1. For SYSCR, see section 3, MCU Operating Modes. Note: Supported only by the H8SX/1648G Group and the H8SX/1648H Group. (8) Refresh Timer Settings The setting of bits RTCK2 to RTCK0 in REFCR should be made after RTCNT and RTCOR have been set. When changing RTCNT and RTCOR, the counter operation should be halted. When changing bits RTCK2 to RTCK0, external access and external bus release by the EXDMAC should be prohibited. The write data buffer function should be used after the write data buffer function is disabled and the external space is read. Note: Supported only by the H8SX/1648G Group and the H8SX/1648H Group.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 381 of 1438 REJ09B0365-0200 (9) Switching Between Refresh Timer and Interval Timer When changing the RFSHE bit in REFCR from 1 to 0, a refresh cycle may be inserted until the bit change is reflected. After this, when using RTCNT as an interval timer, the compare match flag (CMF) may be set to 1. Therefore, confirm the state before setting the CMIE bit to 1. Note: Supported only by the H8SX/1648G Group and the H8SX/1648H Group. (10) RAS Down Mode and Software Standby Mode for DRAM Interface When making a transition to software standby mode with the OPE bit in SBYCR set to 0 without using the self-refresh mode, the transition should be made in RAS up mode (RCDM = 0). When RAS down mode (RCDM = 1) is used, execute the SLEEP instruction after setting the RCDM bit to 0. RAS down mode should be set again after recovery from software standby mode. For SBYCR, see section 27, Power-Down Modes. Note: Supported only by the H8SX/1648G Group and the H8SX/1648H Group. (11) RAS Down Mode and Clock F requencies Setting for DRAM/SDRAM Write access to SCKCR for setting the clock frequencies should be performed in RAS up mode (RCDM = 0). When RAS down mode (RCDM = 1) is used, set the RCDM bit to 0 before writing to SCKCR. RAS down mode should be set again after clock frequencies are set. For SCKCR, see section 26, Clock Pulse Generator. Note: Supported only by the H8SX/1648G Group and the H8SX/1648H Group. (12) Cluster Transfer to SDRAM Space Cluster transfer mode is available for the SDRAM with CAS latency of 2. When the SDRAM is used in cluster transfer mode, the SDRAM with CAS latency of 2 should be used. In cluster transfer mode, the write-precharge output delay function by the TRWL bit is not available. The TRWL bit must be cleared to 0. Note: Supported only by the H8SX/1648G Group and the H8SX/1648H Group.

Section 9 Bus Controller (BSC) Rev. 2.00 Jul. 31, 2008 Page 382 of 1438 REJ09B0365-0200

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 383 of 1438 REJ09B0365-0200 Section 10 DMA Controller (DMAC) This LSI includes a 4-channel DMA controller (DMAC).

10.1 Features

• Maximum of 4-G byte address space can be accessed
• Byte, word, or longword can be set as data transfer unit
• Maximum of 4-G bytes (4,294,967,295 bytes) can be set as total transfer size Supports free-running mode in which total transfer size setting is not needed
• DMAC activation methods are auto-request, on-chip module interrupt, and external request. Auto request: CPU activates (cycle st ealing or burst access can be selected) On-chip module interrupt: Interrupt requests from on-chip peripheral modules can be selected as an activation source External request: Low level or falling edge detection of the DACK signal can be selected. External request is available for all four channels.
• Dual or single address mode can be selected as address mode Dual address mode: Both source and destination are specified by addresses Single address mode: Either source or destination is specified by the DACK signal and the other is specified by address
• Normal, repeat, or block transfer can be selected as transfer mode Normal transfer mode: One byte, one word, or one longword data is transferred at a single transfer request Repeat transfer mode: One byte, one word, or one longword data is transferred at a single transfer request Repeat size of data is transfer red and then a transfer address returns to the transfer start address Up to 65536 transfers (65,536 bytes/words/longwords) can be set as repeat size Block transfer mode: One block data is transferred at a single transfer request Up to 65,536 bytes/words/longwords can be set as block size

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• Extended repeat area function which repeats the addressees within a specified area using the transfer address with the fixed upper bits (ring buffer transfer can be performed, as an example) is available One bit (two bytes) to 27 bits (128 Mbytes) for transfer source and destination can be set as extended repeat areas
• Address update can be selected from fixed address, offset addition, and increment or decrement by 1, 2, or 4 Address update by offset addition enables to transfer data at addresses which are not placed continuously
• Word or longword data can be transferred to an address which is not aligned with the respective boundary Data is divided according to its address (byte or word) when it is transferred
• Two types of interrupts can be requested to the CPU A transfer end interrupt is generated after the number of data specified by the transfer counter is transferred. A transfer escape end interrupt is generated when the remaining total transfer size is less than the transfer data size at a single transfer request, when the repeat size of data transfer is completed, or when the extended repeat area overflows.
• Module stop state can be set.

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 385 of 1438 REJ09B0365-0200 A block diagram of the DMAC is shown in figure 10.1. External pins DREQn DACKn TENDn Interrupt signals requested to the CPU by each channel Internal activation sources Internal activation source detector Controller DMDR_n DMRSR_n DACR_n DOFR_n Internal address bus Internal data bus DSAR_n DDAR_n DTCR_n DBSR_n Module data bus Address buffer Data buffer Operation unit Operation unit ... [Legend] DSAR_n: DMA source address register DREQn: DMA transfer request DDAR_n: DMA destination address register DACKn: DMA transfer acknowledge DOFR_n: DMA offset register TENDn: DMA transfer end DTCR_n: DMA transfer count register n = 0 to 3 DBSR_n: DMA block size register DMDR_n: DMA mode control register DACR_n: DMA address control register DMRSR_n: DMA module request select register Figure 10.1 Block Diagram of DMAC

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 386 of 1438 REJ09B0365-0200

10.2 Input/Output Pins

Table 10.1 shows the pin configuration of the DMAC. Table 10.1 Pin Configuration Channel Pin Name Abbr. I/O Function

0 DMA transfer request 0 DREQ0 Input Channel 0 external request

DMA transfer acknowledge 0 DACK0 Output Channel 0 single address transfer acknowledge DMA transfer end 0 TEND0 Output Channel 0 transfer end

1 DMA transfer request 1 DREQ1 Input Channel 1 external request

DMA transfer acknowledge 1 DACK1 Output Channel 1 single address transfer acknowledge DMA transfer end 1 TEND1 Output Channel 1 transfer end

2 DMA transfer request 2 DREQ2 Input Channel 2 external request

DMA transfer acknowledge 2 DACK2 Output Channel 2 single address transfer acknowledge DMA transfer end 2 TEND2 Output Channel 2 transfer end

3 DMA transfer request 3 DREQ3 Input Channel 3 external request

DMA transfer acknowledge 3 DACK3 Output Channel 3 single address transfer acknowledge DMA transfer end 3 TEND3 Output Channel 3 transfer end

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 387 of 1438 REJ09B0365-0200

10.3 Register Descriptions

The DMAC has the following registers. Channel 0:

• DMA source address register_0 (DSAR_0)
• DMA destination address register_0 (DDAR_0)
• DMA offset register_0 (DOFR_0)
• DMA transfer count register_0 (DTCR_0)
• DMA block size register_0 (DBSR_0)
• DMA mode control register_0 (DMDR_0)
• DMA address control register_0 (DACR_0)
• DMA module request select register_0 (DMRSR_0) Channel 1:
• DMA source address register_1 (DSAR_1)
• DMA destination address register_1 (DDAR_1)
• DMA offset register_1 (DOFR_1)
• DMA transfer count register_1 (DTCR_1)
• DMA block size register_1 (DBSR_1)
• DMA mode control register_1 (DMDR_1)
• DMA address control register_1 (DACR_1)
• DMA module request select register_1 (DMRSR_1) Channel 2:
• DMA source address register_2 (DSAR_2)
• DMA destination address register_2 (DDAR_2)
• DMA offset register_2 (DOFR_2)
• DMA transfer count register_2 (DTCR_2)
• DMA block size register_2 (DBSR_2)
• DMA mode control register_2 (DMDR_2)
• DMA address control register_2 (DACR_2)
• DMA module request select register_2 (DMRSR_2)

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 388 of 1438 REJ09B0365-0200 Channel 3:

• DMA source address register_3 (DSAR_3)
• DMA destination address register_3 (DDAR_3)
• DMA offset register_3 (DOFR_3)
• DMA transfer count register_3 (DTCR_3)
• DMA block size register_3 (DBSR_3)
• DMA mode control register_3 (DMDR_3)
• DMA address control register_3 (DACR_3)
• DMA module request select register_3 (DMRSR_3)

10.3.1 DMA Source Addr ess Register (DSAR)

DSAR is a 32-bit readable/writable register that specifies the transfer source address. DSAR updates the transfer source address every time data is transferred. When DDAR is specified as the destination address (the DIRS bit in DACR is 1) in single address mode, DSAR is ignored. Although DSAR can always be read from by the CPU, it must be read from in longwords and must not be written to while data for the channel is being transferred. R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 389 of 1438 REJ09B0365-0200

10.3.2 DMA Destination Address Register (DDAR)

DDAR is a 32-bit readable/writable register that specifies the transfer destination address. DDAR updates the transfer destination address every time data is transferred. When DSAR is specified as the source address (the DIRS bit in DACR is 0) in single address mode, DDAR is ignored. Although DDAR can always be read from by the CPU, it must be read from in longwords and must not be written to while data for the channel is being transferred. R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 390 of 1438 REJ09B0365-0200

10.3.3 DMA Offset Register (DOFR)

DOFR is a 32-bit readable/writable register that specifies the offset to update the source and destination addresses. Although different values are specified for individual channels, the same values must be specified for the source and destination sides of a single channel. R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 391 of 1438 REJ09B0365-0200

10.3.4 DMA Transfer Count Register (DTCR)

DTCR is a 32-bit readable/writable register that specifies the size of data to be transferred (total transfer size). To transfer 1-byte data in total, set H'00000001 in DTCR. When H'00000000 is set in this register, it means that the total transfer size is not specified and data is transferred with the transfer counter stopped (free running mode). When H'FFFFFFFF is set, the total transfer size is 4 Gbytes (4,294,967,295), which is the maximum size. While data is being transferred, this register indicates the remaining transfer size. The value corresponding to its data access size is subtracted every time data is transferred (byte: −1, word: −2, and longword: −4). Although DTCR can always be read from by the CPU, it must be read from in longwords and must not be written to while data for the channel is being transferred. R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 392 of 1438 REJ09B0365-0200

10.3.5 DMA Block Size Register (DBSR)

DBSR specifies the repeat size or block size. DBSR is enabled in repeat transfer mode and block transfer mode and is disabled in normal transfer mode. BKSZH31 R/W BKSZH30 R/W BKSZH29 R/W BKSZH28 R/W BKSZH27 R/W BKSZH24 R/W BKSZH26 R/W BKSZH25 R/W Bit Bit Name Initial Value R/W BKSZH23 R/W BKSZH22 R/W BKSZH21 R/W BKSZH20 R/W BKSZH19 R/W BKSZH16 R/W BKSZH18 R/W BKSZH17 R/W Bit Bit Name Initial Value R/W BKSZ15 R/W BKSZ14 R/W BKSZ13 R/W BKSZ12 R/W BKSZ11 R/W BKSZ8 R/W BKSZ10 R/W BKSZ9 R/W Bit Bit Name Initial Value R/W BKSZ7 R/W BKSZ6 R/W BKSZ5 R/W BKSZ4 R/W BKSZ3 R/W BKSZ0 R/W BKSZ2 R/W BKSZ1 R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description 31 to 16 BKSZH31 to BKSZH16 All 0 R/W Specify the repeat size or block size. When H'0001 is set, the repeat or block size is one byte, one word, or one longword. When H'0000 is set, it means the maximum value (refer to table 10.1). While the DMA is in operation, the setting is fixed. 15 to 0 BKSZ15 to BKSZ0 All 0 R/W Indicate the remaining repeat or block size while the DMA is in operation. The value is decremented by 1 every time data is transferred. When the remaining size becomes 0, the value of the BKSZH bits is loaded. Set the same value as the BKSZH bits.

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 393 of 1438 REJ09B0365-0200 Table 10.2 Data Access Size, Valid Bits, and Settable Size Mode Data Access Size BKSZH Valid Bits BKSZ Valid Bits Settable Size (Byte) Byte 31 to 16 15 to 0 1 to 65,536 Repeat transfer and block transfer Word 2 to 131,072 Longword 4 to 262,144

10.3.6 DMA Mode Control Register (DMDR)

DMDR controls the DMAC operation.

• DMDR_0 DTE R/W DACKE R/W TENDE R/W R/W DREQS R/W R NRD R/W R Bit Bit Name Initial Value R/W ACT R R R R ERRF R/(W)* DTIF R/(W)* R ESIF R/(W)* Bit Bit Name Initial Value R/W DTSZ1 R/W DTSZ0 R/W MDS1 R/W MDS0 R/W TSEIE R/W DTIE R/W R ESIE R/W Bit Bit Name Initial Value R/W DTF1 R/W DTF0 R/W DTA R/W R R DMAP0 R/W DMAP2 R/W DMAP1 R/W Bit Bit Name Initial Value R/W Note: * Only 0 can be written to this bit after having been read as 1, to clear the flag.

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 394 of 1438 REJ09B0365-0200

• DMDR_1 to DMDR_3 DTE R/W DACKE R/W TENDE R/W R/W DREQS R/W R NRD R/W R Bit Bit Name Initial Value R/W ACT R R R R R DTIF R/(W)* R ESIF R/(W)* Bit Bit Name Initial Value R/W DTSZ1 R/W DTSZ0 R/W MDS1 R/W MDS0 R/W TSEIE R/W DTIE R/W R ESIE R/W Bit Bit Name Initial Value R/W DTF1 R/W DTF0 R/W DTA R/W R R DMAP0 R/W DMAP2 R/W DMAP1 R/W Bit Bit Name Initial Value R/W Note: * Only 0 can be written to this bit after having been read as 1, to clear the flag.

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 395 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description

31 DTE 0 R/W Data Transfer Enable

Enables/disables a data transfer for the corresponding channel. When this bit is set to 1, it indicates that the DMAC is in operation. Setting this bit to 1 starts a transfer when the auto- request is selected. When the on-chip module interrupt or external request is selected, a transfer request after setting this bit to 1 starts the transfer. While data is being transferred, clearing this bit to 0 stops the transfer. In block transfer mode, if writing 0 to this bit while data is being transferred, this bit is cleared to 0 after the current 1-block size data transfer. If an event which stops (sustains) a transfer occurs externally, this bit is automatically cleared to 0 to stop the transfer. Operating modes and transfer methods must not be changed while this bit is set to 1. 0: Disables a data transfer 1: Enables a data transfer (DMA is in operation) [Clearing conditions]

• When the specified total transfer size of transfers is completed
• When a transfer is stopped by an overflow interrupt by a repeat size end
• When a transfer is stopped by an overflow interrupt by an extended repeat size end
• When a transfer is stopped by a transfer size error interrupt
• When clearing this bit to 0 to stop a transfer In block transfer mode, this bit changes after the current block transfer.
• When an address error or an NMI interrupt is requested
• In the reset state or hardware standby mode

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 396 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description

30 DACKE 0 R/W DACK Signal Output Enable

Enables/disables the DACK signal output in single address mode. This bit is ignored in dual address mode. 0: Disables DACK signal output 1: Enables DACK signal output

29 TENDE 0 R/W TEND Signal Output Enable

Enables/disables the TEND signal output. 0: Disables TEND signal output 1: Enables TEND signal output 28  0 R/W Reserved Initial value should not be changed.

27 DREQS 0 R/W DREQ Select

Selects whether a low level or the falling edge of the DREQ signal used in external request mode is detected. 0: Low level detection 1: Falling edge detection (the first transfer after a transfer enabled is detected on a low level)

26 NRD 0 R/W Next Request Delay

Selects the accepting timing of the next transfer request. 0: Starts accepting the next transfer request after completion of the current transfer 1: Starts accepting the next transfer request one cycle after completion of the current transfer 25, 24  All 0 R Reserved These bits are always read as 0 and cannot be modified.

23 ACT 0 R Active State

Indicates the operating state for the channel. 0: Waiting for a transfer request or a transfer disabled state by clearing the DTE bit to 0 1: Active state 22 to 20  All 0 R Reserved These bits are always read as 0 and cannot be modified.

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 397 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description

19 ERRF 0 R/(W) * System Error Flag

Indicates that an address error or an NMI interrupt has been generated. This bit is available only in DMDR_0. Setting this bit to 1 prohibits writing to the DTE bit for all the channels. This bit is reserved in DMDR_1 to DMDR_3. It is always read as 0 and cannot be modified. 0: An address error or an NMI interrupt has not been generated 1: An address error or an NMI interrupt has been generated [Clearing condition]

• When clearing to 0 after reading ERRF = 1 [Setting condition]
• When an address error or an NMI interrupt has been generated However, when an address error or an NMI interrupt has been generated in DMAC module stop mode, this bit is not set to 1. 18  0 R Reserved This bit is always read as 0 and cannot be modified.

17 ESIF 0 R/(W) * Transfer Escape Interrupt Flag

Indicates that a transfer escape end interrupt has been requested. A transfer escape end means that a transfer is terminated before the transfer counter reaches 0. 0: A transfer escape end interrupt has not been requested 1: A transfer escape end interrupt has been requested [Clearing conditions]

• When setting the DTE bit to 1
• When clearing to 0 before reading ESIF = 1 [Setting conditions]
• When a transfer size error interrupt is requested
• When a repeat size end interrupt is requested
• When a transfer end interrupt by an extended repeat area overflow is requested

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 398 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description

16 DTIF 0 R/(W) * Data Transfer Interrupt Flag

Indicates that a transfer end interrupt by the transfer counter has been requested. 0: A transfer end interrupt by the transfer counter has not been requested 1: A transfer end interrupt by the transfer counter has been requested [Clearing conditions]

• When setting the DTE bit to 1
• When clearing to 0 after reading DTIF = 1 [Setting condition]
• When DTCR reaches 0 and the transfer is completed DTSZ1 DTSZ0 R/W R/W Data Access Size 1 and 0 Select the data access size for a transfer. 00: Byte size (eight bits) 01: Word size (16 bits) 10: Longword size (32 bits) 11: Setting prohibited MDS1 MDS0 R/W R/W Transfer Mode Select 1 and 0 Select the transfer mode. 00: Normal transfer mode 01: Block transfer mode 10: Repeat transfer mode 11: Setting prohibited

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 399 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description

11 TSEIE 0 R/W Transfer Size Error Interrupt Enable

Enables/disables a transfer size error interrupt. When the next transfer is requested while this bit is set to 1 and the contents of the transfer counter is less than the size of data to be transferred at a single transfer request, the DTE bit is cleared to 0. At this time, the ESIF bit is set to 1 to indicate that a transfer size error interrupt has been requested. The sources of a transfer size error are as follows:

• In normal or repeat transfer mode, the total transfer size set in DTCR is less than the data access size
• In block transfer mode, the total transfer size set in DTCR is less than the block size 0: Disables a transfer size error interrupt request 1: Enables a transfer size error interrupt request 10  0 R Reserved This bit is always read as 0 and cannot be modified.

9 ESIE 0 R/W Transfer Escape Interrupt Enable

Enables/disables a transfer escape end interrupt request. When the ESIF bit is set to 1 with this bit set to 1, a transfer escape end interrupt is requested to the CPU or DTC. The transfer end interrupt request is cleared by clearing this bit or the ESIF bit to 0. 0: Disables a transfer escape end interrupt 1: Enables a transfer escape end interrupt

8 DTIE 0 R/W Data Transfer End Interrupt Enable

Enables/disables a transfer end interrupt request by the transfer counter. When the DTIF bit is set to 1 with this bit set to 1, a transfer end interrupt is requested to the CPU or DTC. The transfer end interrupt request is cleared by clearing this bit or the DTIF bit to 0. 0: Disables a transfer end interrupt 1: Enables a transfer end interrupt

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 400 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description DTF1 DTF0 R/W R/W Data Transfer Factor 1 and 0 Select a DMAC activation source. When the on-chip peripheral module setting is selected, the interrupt source should be selected by DMRSR. When the external request setting is selected, the sampling method should be selected by the DREQS bit. 00: Auto request (cycle stealing) 01: Auto request (burst access) 10: On-chip module interrupt 11: External request

5 DTA 0 R/W Data Transfer Acknowledge

This bit is valid in DMA transfer by the on-chip module interrupt source. This bit enables or disables to clear the source flag selected by DMRSR. 0: To clear the source in DMA transfer is disabled. Since the on-chip module interrupt source is not cleared in DMA transfer, it should be cleared by the CPU or DTC transfer. 1: To clear the source in DMA transfer is enabled. Since the on-chip module interrupt source is cleared in DMA transfer, it does not require an interrupt by the CPU or DTC transfer. 4, 3  All 0 R Reserved These bits are always read as 0 and cannot be modified.

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 401 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description DMAP2 DMAP1 DMAP0 R/W R/W R/W DMA Priority Level 2 to 0 Select the priority level of the DMAC when using the CPU priority control function over DTC and DMAC. When the CPU has priority over the DMAC, the DMAC masks a transfer request and waits for the timing when the CPU priority becomes lower than the DMAC priority. The priority levels can be set to the individual channels. This bit is valid when the CPUPCE bit in CPUPCR is set to 1. 000: Priority level 0 (low) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (high) Note: * Only 0 can be written to, to clear the flag.

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 402 of 1438 REJ09B0365-0200

10.3.7 DMA Address Control Register (DACR)

DACR specifies the operating mode and transfer method. AMS R/W DIRS R/W R R R ARS0 R/W RPTIE R/W ARS1 R/W Bit Bit Name Initial Value R/W R R SAT1 R/W SAT0 R/W R DAT0 R/W R DAT1 R/W Bit Bit Name Initial Value R/W SARIE R/W R R SARA4 R/W SARA3 R/W SARA0 R/W SARA2 R/W SARA1 R/W Bit Bit Name Initial Value R/W DARIE R/W R R DARA4 R/W DARA3 R/W DARA0 R/W DARA2 R/W DARA1 R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description

31 AMS 0 R/W Address Mode Select

Selects address mode from single or dual address mode. In single address mode, the DACK pin is enabled according to the DACKE bit. 0: Dual address mode 1: Single address mode

30 DIRS 0 R/W Single Address Direction Select

Specifies the data transfer direction in single address mode. This bit s ignored in dual address mode. 0: Specifies DSAR as source address 1: Specifies DDAR as destination address 29 to 27  0 R/W Reserved These bits are always read as 0 and cannot be modified.

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 403 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description

26 RPTIE 0 R/W Repeat Size End Interrupt Enable

Enables/disables a repeat size end interrupt request. In repeat transfer mode, when the next transfer is requested after completion of a 1-repeat-size data transfer while this bit is set to 1, the DTE bit in DMDR is cleared to 0. At this time, the ESIF bit in DMDR is set to 1 to indicate that a repeat size end interrupt is requested. Even when the repeat area is not specified (ARS1 = 1 and ARS0 = 0), a repeat size end interrupt after a 1-block data transfer can be requested. In addition, in block transfer mode, when the next transfer is requested after 1-block data transfer while this bit is set to 1, the DTE bit in DMDR is cleared to 0. At this time, the ESIF bit in DMDR is set to 1 to indicate that a repeat size end interrupt is requested. 0: Disables a repeat size end interrupt 1: Enables a repeat size end interrupt ARS1 ARS0 R/W R/W Area Select 1 and 0 Specify the block area or repeat area in block or repeat transfer mode. 00: Specify the block area or repeat area on the source address 01: Specify the block area or repeat area on the destination address 10: Do not specify the block area or repeat area 11: Setting prohibited 23, 22  All 0 R Reserved These bits are always read as 0 and cannot be modified. SAT1 SAT0 R/W R/W Source Address Update Mode 1 and 0 Select the update method of the source address (DSAR). When DSAR is not specified as the transfer source in single address mode, this bit is ignored. 00: Source address is fixed 01: Source address is updated by adding the offset 10: Source address is updated by adding 1, 2, or 4 according to the data access size 11: Source address is updated by subtracting 1, 2, or 4 according to the data access size

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 404 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description 19, 18  All 0 R Reserved These bits are always read as 0 and cannot be modified. DAT1 DAT0 R/W R/W Destination Address Update Mode 1 and 0 Select the update method of the destination address (DDAR). When DDAR is not specified as the transfer destination in single address mode, this bit is ignored. 00: Destination address is fixed 01: Destination address is updated by adding the offset 10: Destination address is updated by adding 1, 2, or 4 according to the data access size 11: Destination address is updated by subtracting 1, 2, or 4 according to the data access size

15 SARIE 0 R/W Interrupt Enable for Source Address Extended Area

Enables/disables an interrupt request for an extended area overflow on the source address. When an extended repeat area overflow on the source address occurs while this bit is set to 1, the DTE bit in DMDR is cleared to 0. At this time, the ESIF bit in DMDR is set to 1 to indicate an interrupt by an extended repeat area overflow on the source address is requested. When block transfer mode is used with the extended repeat area function, an interrupt is requested after completion of a 1-block size transfer. When setting the DTE bit in DMDR of the channel for which a transfer has been stopped to 1, the transfer is resumed from the state when the transfer is stopped. When the extended repeat area is not specified, this bit is ignored. 0: Disables an interrupt request for an extended area overflow on the source address 1: Enables an interrupt request for an extended area overflow on the source address 14, 13  All 0 R Reserved These bits are always read as 0 and cannot be modified.

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 405 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description SARA4 SARA3 SARA2 SARA1 SARA0 R/W R/W R/W R/W R/W Source Address Extended Repeat Area Specify the extended repeat area on the source address (DSAR). With the extended repeat area, the specified lower address bits are updated and the remaining upper address bits are fixed. The extended repeat area size is specified from four bytes to 128 Mbytes in units of byte and a power of 2. When the lower address is overflowed from the extended repeat area by address update, the address becomes the start address and the end address of the area for address addition and subtraction, respectively. When an overflow in the extended repeat area occurs with the SARIE bit set to 1, an interrupt can be requested. Table 10.3 shows the settings and areas of the extended repeat area.

7 DARIE 0 R/W Destination Address Extended Repeat Area Overflow

Enables/disables an interrupt request for an extended area overflow on the destination address. When an extended repeat area overflow on the destination address occurs while this bit is set to 1, the DTE bit in DMDR is cleared to 0. At this time, the ESIF bit in DMDR is set to 1 to indicate an interrupt by an extended repeat area overflow on the destination address is requested. When block transfer mode is used with the extended repeat area function, an interrupt is requested after completion of a 1-block size transfer. When setting the DTE bit in DMDR of the channel for which the transfer has been stopped to 1, the transfer is resumed from the state when the transfer is stopped. When the extended repeat area is not specified, this bit is ignored. 0: Disables an interrupt request for an extended area overflow on the destination address 1: Enables an interrupt request for an extended area overflow on the destination address 6, 5  All 0 R Reserved These bits are always read as 0 and cannot be modified.

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 406 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description DARA4 DARA3 DARA2 DARA1 DARA0 R/W R/W R/W R/W R/W Destination Address Extended Repeat Area Specify the extended repeat area on the destination address (DDAR). With the extended repeat area, the specified lower address bits are updated and the remaining upper address bits are fixed. The extended repeat area size is specified from four bytes to 128 Mbytes in units of byte and a power of 2. When the lower address is overflowed from the extended repeat area by address update, the address becomes the start address and the end address of the area for address addition and subtraction, respectively. When an overflow in the extended repeat area occurs with the DARIE bit set to 1, an interrupt can be requested. Table 10.3 shows the settings and areas of the extended repeat area.

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 407 of 1438 REJ09B0365-0200 Table 10.3 Settings and Areas of Extended Repeat Area SARA4 to SARA0 or DARA4 to DARA0 Extended Repeat Area

00000 Not specified

00001 2 bytes specified as extended repeat area by the lower 1 bit of the address 00010 4 bytes specified as extended repeat area by the lower 2 bits of the address 00011 8 bytes specified as extended repeat area by the lower 3 bits of the address 00100 16 bytes specified as extended repeat area by the lower 4 bits of the address 00101 32 bytes specified as extended repeat area by the lower 5 bits of the address 00110 64 bytes specified as extended repeat area by the lower 6 bits of the address 00111 128 bytes specified as extended repeat area by the lower 7 bits of the address 01000 256 bytes specified as extended repeat area by the lower 8 bits of the address 01001 512 bytes specified as extended repeat area by the lower 9 bits of the address 01010 1 Kbyte specified as extended repeat area by the lower 10 bits of the address 01011 2 Kbytes specified as extended repeat area by the lower 11 bits of the address 01100 4 Kbytes specified as extended repeat area by the lower 12 bits of the address 01101 8 Kbytes specified as extended repeat area by the lower 13 bits of the address 01110 16 Kbytes specified as extended repeat ar ea by the lower 14 bits of the address 01111 32 Kbytes specified as extended repeat ar ea by the lower 15 bits of the address 10000 64 Kbytes specified as extended repeat ar ea by the lower 16 bits of the address 10001 128 Kbytes specified as extended repeat area by the lower 17 bits of the address 10010 256 Kbytes specified as extended repeat area by the lower 18 bits of the address 10011 512 Kbytes specified as extended repeat area by the lower 19 bits of the address 10100 1 Mbyte specified as extended repeat area by the lower 20 bits of the address 10101 2 Mbytes specified as extended repeat area by the lower 21 bits of the address 10110 4 Mbytes specified as extended repeat area by the lower 22 bits of the address 10111 8 Mbytes specified as extended repeat area by the lower 23 bits of the address 11000 16 Mbytes specified as extended repeat ar ea by the lower 24 bits of the address 11001 32 Mbytes specified as extended repeat ar ea by the lower 25 bits of the address 11010 64 Mbytes specified as extended repeat ar ea by the lower 26 bits of the address 11011 128 Mbytes specified as extended repeat area by the lower 27 bits of the address 111×× Setting prohibited [Legend] ×: Don't care

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 408 of 1438 REJ09B0365-0200

10.3.8 DMA Module Request Select Register (DMRSR)

DMRSR is an 8-bit readable/writable register that specifies the on-chip module interrupt source. The vector number of the interrupt source is specified in eight bits. However, 0 is regarded as no interrupt source. For the vector numbers of the interrupt sources, refer to table 10.5. R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 409 of 1438 REJ09B0365-0200

10.4 Transfer Modes

Table 10.4 shows the DMAC transfer modes. The transfer modes can be specified to the individual channels. Table 10.4 Transfer Modes Address Register Address Mode Transfer mode Activati on Source Common Function Source Destina- tion Dual address

• Normal transfer
• Repeat transfer
• Block transfer Repeat or block size = 1 to 65,536 bytes, 1 to 65,536 words, or 1 to 65,536 longwords
• Auto request (activated by CPU)
• On-chip module interrupt
• External request
• Total transfer size: 1 to 4 Gbytes or not specified
• Offset addition
• Extended repeat area function DSAR DDAR Single address
• Instead of specifying the source or destination address registers, data is directly transferred from/to the external device using the DACK pin
• The same settings as above are available other than address register setting (e.g., above transfer modes can be specified)
• One transfer can be performed in one bus cycle (the types of transfer modes are the same as those of dual address modes) DSAR/ DACK DACK/ DDAR When the auto request setting is selected as the activation source, the cycle stealing or burst access can be selected. When the total transfer size is not specified (DTCR = H'00000000), the transfer counter is stopped and the transfer is continued without the limitation of the transfer count.

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 410 of 1438 REJ09B0365-0200

10.5 Operations

10.5.1 Address Modes

(1) Dual Address Mode In dual address mode, the transfer source address is specified in DSAR and the transfer destination address is specified in DDAR. A transfer at a time is performed in two bus cycles (when the data bus width is less than the data access size or the access address is not aligned with the boundary of the data access size, the number of bus cycles are needed more than two because one bus cycle is divided into multiple bus cycles). In the first bus cycle, data at the transfer source address is read and in the next cycle, the read data is written to the transfer destination address. The read and write cycles are not separated. Other bus cycles (bus cycle by other bus masters, refresh cycle, and external bus release cycle) are not generated between read and write cycles. The TEND signal output is enabled or disabled by the TENDE bit in DMDR. The TEND signal is output in two bus cycles. When an idle cycle is inserted before the bus cycle, the TEND signal is also output in the idle cycle. The DACK signal is not output. Figure 10.2 shows an example of the signal timing in dual address mode and figure 10.3 shows the operation in dual address mode. Address bus Bφ RD WR TEND DMA read cycle DMA write cycle DSAR DDAR Figure 10.2 Example of Signal Timing in Dual Address Mode

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 411 of 1438 REJ09B0365-0200 TransferAddress TA Address BA Address update setting is as follows: Source address increment Fixed destination address Address T B Figure 10.3 Operations in Dual Address Mode (2) Single Address Mode In single address mode, data between an external device and an external memory is directly transferred using the DACK pin instead of DSAR or DDAR. A transfer at a time is performed in one bus cycle. In this mode, the data bus width must be the same as the data access size. For details on the data bus width, see section 9, Bus Controller (BSC). The DMAC accesses an external device as the transfer source or destination by outputting the strobe signal (DACK) to the external device with DACK and accesses the other transfer target by outputting the address. Accordingly, the DMA transfer is performed in one bus cycle. Figure 10.4 shows an example of a transfer between an external memory and an external device with the DACK pin. In this example, the external device outputs data on the data bus and the data is written to the external memory in the same bus cycle. The transfer direction is decided by the DIRS bit in DACR which specifies an external device with the DACK pin as the transfer source or destination. When DIRS = 0, data is transferred from an external memory (DSAR) to an external device with the DACK pin. When DIRS = 1, data is transferred from an external device with the DACK pin to an external memory (DDAR). The settings of registers which are not used as the transfer source or destination are ignored. The DACK signal output is enabled in single address mode by the DACKE bit in DMDR. The DACK signal is low active. The TEND signal output is enabled or disabled by the TENDE bit in DMDR. The TEND signal is output in one bus cycle. When an idle cycle is inserted before the bus cycle, the TEND signal is also output in the idle cycle.

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 414 of 1438 REJ09B0365-0200

10.5.2 Transfer Modes

(1) Normal Transfer Mode In normal transfer mode, one data access size of data is transferred at a single transfer request. Up to 4 Gbytes can be specified as a total transfer size by DTCR. DBSR is ignored in normal transfer mode. The TEND signal is output only in the last DMA transfer. The DACK signal is output every time a transfer request is received and a transfer starts. Figure 10.7 shows an example of the signal timing in normal transfer mode and figure 10.8 shows the operation in normal transfer mode. Read Write Read Write DMA transfer cycle Last DMA transfer cycle Bus cycle Auto request transfer in dual address mode: External request transfer in single address mode: TEND DMA DMA DREQ Bus cycle DACK Figure 10.7 Example of Signal Timing in Normal Transfer Mode

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 416 of 1438 REJ09B0365-0200 TransferAddress TA Address TB Address BB Address BA Operation when the repeat area is specified to the source side Repeat size = BKSZH × data access size Total transfer size (DTCR) Figure 10.9 Operations in Repeat Transfer Mode (3) Block Transfer Mode In block transfer mode, one block size of data is transferred at a single transfer request. Up to 4 Gbytes can be specified as total transfer size by DTCR. The block size can be specified in DBSR up to 65536 × data access size. While one block of data is being transferred, transfer requests from other channels are suspended. When the transfer is completed, the bus is released to the other bus master. The block area can be specified for the source or destination address side by bits ARS1 and ARS0 in DACR. The address specified as the block area returns to the transfer start address when the block size of data is completed. When the block area is specified as neither source nor destination address side, the operation continues without returning the address to the transfer start address. A repeat size end interrupt can be requested. The TEND signal is output every time 1-block data is transferred in the last DMA transfer cycle. When an interrupt request by an extended repeat area overflow is used in block transfer mode, settings should be selected carefully. For details, see section 10.5.5, Extended Repeat Area Function.

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 418 of 1438 REJ09B0365-0200 Transfer Address TA Address BA Address TB Address BB Nth block Second block First block Nth block Second block First block BKSZH × data access size Total transfer size (DTCR) Figure 10.12 Operation in Dual Address Mode in Block Transfer Mode (Block Area Not Specified)

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 419 of 1438 REJ09B0365-0200

10.5.3 Activa tion Sources

The DMAC is activated by an auto request, an on-chip module interrupt, and an external request. The activation source is specified by bits DTF1 and DTF0 in DMDR. (1) Activation by Auto Request The auto request activation is used when a transfer request from an external device or an on-chip peripheral module is not generated such as a transfer between memory and memory or between memory and an on-chip peripheral module which does not request a transfer. A transfer request is automatically generated inside the DMAC. In auto request activation, setting the DTE bit in DMDR starts a transfer. The bus mode can be selected from cycle stealing and burst modes. (2) Activation by On-Chip Module Interrupt An interrupt request from an on-chip peripheral module (on-chip peripheral module interrupt) is used as a transfer request. When a DMA transfer is enabled (DTE = 1), the DMA transfer is started by an on-chip module interrupt. The activation source of the on-chip module interrupt is selected by the DMA module request select register (DMRSR). The activation sources are specified to the individual channels. Table 10.5 is a list of on-chip module interrupts for the DMAC. The interrupt request selected as the activation source can generate an interrupt request simultaneously to the CPU or DTC. For details, refer to section 7, Interrupt Controller. The DMAC receives interrupt requests by on-chip peripheral modules independent of the interrupt controller. Therefore, the DMAC is not affected by priority given in the interrupt controller. When the DMAC is activated while DTA = 1, the interrupt request flag is automatically cleared by a DMA transfer. If multiple channels use a single transfer request as an activation source, when the channel having priority is activated, the interrupt request flag is cleared. In this case, other channels may not be activated because the transfer request is not held in the DMAC. When the DMAC is activated while DTA = 0, the interrupt request flag is not cleared by the DMAC and should be cleared by the CPU or DTC transfer. When an activation source is selected while DTE = 0, the activation source does not request a transfer to the DMAC. It requests an interrupt to the CPU or DTC. In addition, make sure that an interrupt request flag as an on-chip module interrupt source is cleared to 0 before writing 1 to the DTE bit.

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 420 of 1438 REJ09B0365-0200 Table 10.5 List of On-chip module interrupts to DMAC On-Chip Module Interrupt Source On-Chip Module DMRSR (Vector Number) ADI0 (conversion end interrupt for A/D converter unit 0) A/D_0 86 TGI0A (TGI0A input capture/compare match) TPU_0 88 TGI1A (TGI1A input capture/compare match) TPU_1 93 TGI2A (TGI2A input capture/compare match) TPU_2 97 TGI3A (TGI3A input capture/compare match) TPU_3 101 TGI4A (TGI4A input capture/compare match) TPU_4 106 TGI5A (TGI5A input capture/compare match) TPU_5 110 RXI0 (receive data full interrupt for SCI channel 0) SCI_0 145 TXI0 (transmit data empty interrupt for SCI channel 0) SCI_0 146 RXI1 (receive data full interrupt for SCI channel 1) SCI_1 149 TXI1 (transmit data empty interrupt for SCI channel 1) SCI_1 150 RXI2 (receive data full interrupt for SCI channel 2) SCI_2 153 TXI2 (transmit data empty interrupt for SCI channel 2) SCI_2 154 RXI3 (receive data full interrupt for SCI channel 3) SCI_3 157 TXI3 (transmit data empty interrupt for SCI channel 3) SCI_3 158 RXI4 (receive data full interrupt for SCI channel 4) SCI_4 161 TXI4 (transmit data empty interrupt for SCI channel 4) SCI_4 162 TGI6A (TGI6A input capture/compare match) TPU_6 164 TGI7A (TGI7A input capture/compare match) TPU_7 169 TGI8A (TGI8A input capture/compare match) TPU_8 173 TGI9A (TGI9A input capture/compare match) TPU_9 177 TGI10A (TGI10A input capture/compare match) TPU_10 182 TGI11A (TGI11A input capture/compare match) TPU_11 188 RXI5 (receive data full interrupt for SCI channel 5) SCI_5 220 TXI5 (transmit data empty interrupt for SCI channel 5) SCI_5 221 RXI6 (receive data full interrupt for SCI channel 6) SCI_6 224 TXI6 (transmit data empty interrupt for SCI channel 6) SCI_6 225 ADI2 (conversion end interrupt for A/D converter unit 2) A/D_2 232 ADI1 (conversion end interrupt for A/D converter unit 1) A/D_1 237

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 421 of 1438 REJ09B0365-0200 (3) Activation by External Request A transfer is started by a transfer request signal (DREQ) from an external device. When a DMA transfer is enabled (DTE = 1), the DMA transfer is started by the DREQ assertion. When a DMA transfer between on-chip peripheral modules is performed, select an activation source from the auto request and on-chip module interrupt (the external request cannot be used). A transfer request signal is input to the DREQ pin. The DREQ signal is detected on the falling edge or low level. Whether the falling edge or low level detection is used is selected by the DREQS bit in DMDR. When an external request is selected as an activation source, clear the DDR bit to 0 and set the ICR bit to 1 for the corresponding pin. For details, see section 13, I/O Ports.

10.5.4 Bus Access Modes

There are two types of bus access modes: cycle stealing and burst. When an activation source is the auto request, the cycle stealing or burst mode is selected by bit DTF0 in DMDR. When an activation source is the on-chip module interrupt or external request, the cycle stealing mode is selected. (1) Cycle Stealing Mode In cycle stealing mode, the DMAC releases the bus every time one unit of transfers (byte, word, longword, or 1-block size) is completed. After that, when a transfer is requested, the DMAC obtains the bus to transfer 1-unit data and then releases the bus on completion of the transfer. This operation is continued until the transfer end condition is satisfied. When a transfer is requested to another channel during a DMA transfer, the DMAC releases the bus and then transfers data for the requested channel. For details on operations when a transfer is requested to multiple channels, see section 10.5.8, Priority of Channels.

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 423 of 1438 REJ09B0365-0200

10.5.5 Extended Repeat Area Function

The source and destination address sides can be specified as the extended repeat area. The contents of the address register repeat addresses within the area specified as the extended repeat area. For example, to use a ring buffer as the transfer target, the contents of the address register should return to the start address of the buffer every time the contents reach the end address of the buffer (overflow on the ring buffer address). This operation can automatically be performed using the extended repeat area function of the DMAC. The extended repeat areas can be specified independently to the source address register (DSAR) and destination address register (DDAR). The extended repeat area on the source address is specified by bits SARA4 to SARA0 in DACR. The extended repeat area on the destination address is specified by bits DARA4 to DARA0 in DACR. The extended repeat area sizes for each side can be specified independently. A DMA transfer is stopped and an interrupt by an extended repeat area overflow can be requested to the CPU when the contents of the address register reach the end address of the extended repeat area. When an overflow on the extended repeat area set in DSAR occurs while the SARIE bit in DACR is set to 1, the ESIF bit in DMDR is set to 1 and the DTE bit in DMDR is cleared to 0 to stop the transfer. At this time, if the ESIE bit in DMDR is set to 1, an interrupt by an extended repeat area overflow is requested to the CPU. When the DARIE bit in DACR is set to 1, an overflow on the extended repeat area set in DDAR occurs, meaning that the destination side is a target. During the interrupt handling, setting the DTE bit in DMDR resumes the transfer.

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10.5.6 Address Update Function using Offset

The source and destination addresses are updated by fixing, increment/decrement by 1, 2, or 4, or offset addition. When the offset addition is selected, the offset specified by the offset register (DOFR) is added to the address every time the DMAC transfers the data access size of data. This function realizes a data transfer where addresses are allocated to separated areas. Figure 10.17 shows the address update method. + offset ±1, 2, or 4 Address not updated Data access size added to or subtracted from address (addresses are continuous) Offset is added to address (addresses are not continuous) (a) Address fixed (b) Increment or decrement by 1, 2, or 4 (c) Offset addition External memoryExternal memory External memory Figure 10.17 Address Update Method In item (a), Address fixed, the transfer source or destination address is not updated indicating the same address. In item (b), Increment or decrement by 1, 2, or 4, the transfer source or destination address is incremented or decremented by the value according to the data access size at each transfer. Byte, word, or longword can be specified as the data access size. The value of 1 for byte, 2 for word, and 4 for longword is used for updating the address. This operation realizes the data transfer placed in consecutive areas. In item (c), Offset addition, the address update does not depend on the data access size. The offset specified by DOFR is added to the address every time the DMAC transfers data of the data access size.

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 430 of 1438 REJ09B0365-0200 (3) Offset Subtraction When setting the negative value in DOFR, the offset value must be 2's complement. The 2's complement is obtained by the following formula. 2's complement of offset = 1 + ~offset (~: bit inversion) Example: 2's complement of H'0001FFFF = H'FFFE0000 + H'00000001 = H'FFFE0001 The value of 2's complement can be obtained by the NEG.L instruction.

10.5.7 Register during DMA Transfer

The DMAC registers are updated by a DMA transfer. The value to be updated differs according to the other settings and transfer state. The registers to be updated are DSAR, DDAR, DTCR, bits BKSZH and BKSZ in DBSR, and the DTE, ACT, ERRF, ESIF, and DTIF bits in DMDR. (1) DMA Source Address Register When the transfer source address set in DSAR is accessed, the contents of DSAR are output and then are updated to the next address. The increment or decrement can be specified by bits SAT1 and SAT0 in DACR. When SAT1 and SAT0 = B'00, the address is fixed. When SAT1 and SAT0 = B'01, the address is added with the offset. When SAT1 and SAT0 = B'10, the address is incremented. When SAT1 and SAT0 = B'11, the address is decremented. The size of increment or decrement depends on the data access size. The data access size is specified by bits DTSZ1 and DTSZ0 in DMDR. When DTSZ1 and DTSZ0 = B'00, the data access size is byte and the address is incremented or decremented by 1. When DTSZ1 and DTSZ0 = B'01, the data access size is word and the address is incremented or decremented by 2. When DTSZ1 and DTSZ0 = B'10, the data access size is longword and the address is incremented or decremented by 4. Even if the access data size of the source address is word or longword, when the source address is not aligned with the word or longword boundary, the read bus cycle is divided into byte or word cycles. While data of one word or one longword is being read, the size of increment or decrement is changing according to the actual data access size, for example, +1 or +2 for byte or word data. After one word or one longword of data is read, the address when the read cycle is started is incremented or decremented by the value according to bits SAT1 and SAT0.

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 431 of 1438 REJ09B0365-0200 In block or repeat transfer mode, when the block or repeat size of data transfers is completed while the block or repeat area is specified to the source address side, the source address returns to the transfer start address and is not affected by the address update. When the extended repeat area is specified to the source address side, operation follows the setting. The upper address bits are fixed and is not affected by the address update. While data is being transferred, DSAR must be accessed in longwords. If the upper word and lower word are read separately, incorrect data may be read from since the contents of DSAR during the transfer may be updated regardless of the access by the CPU. Moreover, DSAR for the channel being transferred must not be written to. (2) DMA Destination Address Register When the transfer destination address set in DDAR is accessed, the contents of DDAR are output and then are updated to the next address. The increment or decrement can be specified by bits DAT1 and DAT0 in DACR. When DAT1 and DAT0 = B'00, the address is fixed. When DAT1 and DAT0 = B'01, the address is added with the offset. When DAT1 and DAT0 = B'10, the address is incremented. When DAT1 and DAT0 = B'11, the address is decremented. The incrementing or decrementing size depends on the data access size. The data access size is specified by bits DTSZ1 and DTSZ0 in DMDR. When DTSZ1 and DTSZ0 = B'00, the data access size is byte and the address is incremented or decremented by 1. When DTSZ1 and DTSZ0 = B'01, the data access size is word and the address is incremented or decremented by 2. When DTSZ1 and DTSZ0 = B'10, the data access size is longword and the address is incremented or decremented by 4. Even if the access data size of the destination address is word or longword, when the destination address is not aligned with the word or longword boundary, the write bus cycle is divided into byte and word cycles. While one word or one longword of data is being written, the incrementing or decrementing size is changing according to the actual data access size, for example, +1 or +2 for byte or word data. After the one word or one longword of data is written, the address when the write cycle is started is incremented or decremented by the value according to bits SAT1 and SAT0. In block or repeat transfer mode, when the block or repeat size of data transfers is completed while the block or repeat area is specified to the destination address side, the destination address returns to the transfer start address and is not affected by the address update. When the extended repeat area is specified to the destination address side, operation follows the setting. The upper address bits are fixed and is not affected by the address update.

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 432 of 1438 REJ09B0365-0200 While data is being transferred, DDAR must be accessed in longwords. If the upper word and lower word are read separately, incorrect data may be read from since the contents of DDAR during the transfer may be updated regardless of the access by the CPU. Moreover, DDAR for the channel being transferred must not be written to. (3) DMA Transfer Count Register (DTCR) A DMA transfer decrements the contents of DTCR by the transferred bytes. When byte data is transferred, DTCR is decremented by 1. When word data is transferred, DTCR is decremented by 2. When longword data is transferred, DTCR is decremented by 4. However, when DTCR = 0, the contents of DTCR are not changed since the number of transfers is not counted. While data is being transferred, all the bits of DTCR may be changed. DTCR must be accessed in longwords. If the upper word and lower word are read separately, incorrect data may be read from since the contents of DTCR during the transfer may be updated regardless of the access by the CPU. Moreover, DTCR for the channel being transferred must not be written to. When a conflict occurs between the address update by DMA transfer and write access by the CPU, the CPU has priority. When a conflict occurs between change from 1, 2, or 4 to 0 in DTCR and write access by the CPU (other than 0), the CPU has priority in writing to DTCR. However, the transfer is stopped. (4) DMA Block Size Register (DBSR) DBSR is enabled in block or repeat transfer mode. Bits 31 to 16 in DBSR function as BKSZH and bits 15 to 0 in DBSR function as BKSZ. The BKSZH bits (16 bits) store the block size and repeat size and its value is not changed. The BKSZ bits (16 bits) function as a counter for the block size and repeat size and its value is decremented every transfer by 1. When the BKSZ value is to change from 1 to 0 by a DMA transfer, 0 is not stored but the BKSZH value is loaded into the BKSZ bits. Since the upper 16 bits of DBSR are not updated, DBSR can be accessed in words. DBSR for the channel being transferred must not be written to.

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 434 of 1438 REJ09B0365-0200 (6) ACT Bit in DMDR The ACT bit in DMDR indicates whether the DMAC is in the idle or active state. When DTE = 0 or DTE = 1 and the DMAC is waiting for a transfer request, the ACT bit is 0. Otherwise (the DMAC is in the active state), the ACT bit is 1. When individual transfers are stopped by writing 0 and the transfer is not completed, the ACT bit retains 1. In block transfer mode, even if individual transfers are stopped by writing 0 to the DTE bit, the 1- block size of transfers is not stopped. The ACT bit retains 1 from writing 0 to the DTE bit to completion of a 1-block size transfer. In burst mode, up to three times of DMA transfer are performed from the cycle in which the DTE bit is written to 0. The ACT bit retains 1 from writing 0 to the DTE bit to completion of DMA transfer. (7) ERRF Bit in DMDR When an address error or an NMI interrupt occur, the DMAC clears the DTE bits for all the channels to stop a transfer. In addition, it sets the ERRF bit in DMDR_0 to 1 to indicate that an address error or an NMI interrupt has occurred regardless of whether or not the DMAC is in operation. (8) ESIF Bit in DMDR When an interrupt by an transfer size error, a repeat size end, or an extended repeat area overflow is requested, the ESIF bit in DMDR is set to 1. When both the ESIF and ESIE bits are set to 1, a transfer escape interrupt is requested to the CPU or DTC. The ESIF bit is set to 1 when the ACT bit in DMDR is cleared to 0 to stop a transfer after the bus cycle of the interrupt source is completed. The ESIF bit is automatically cleared to 0 and a transfer request is cleared if the transfer is resumed by setting the DTE bit to 1 during interrupt handling. For details on interrupts, see section 10.8, Interrupt Sources.

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 435 of 1438 REJ09B0365-0200 (9) DTIF Bit in DMDR The DTIF bit in DMDR is set to 1 after the total transfer size of transfers is completed. When both the DTIF and DTIE bits in DMDR are set to 1, a transfer end interrupt by the transfer counter is requested to the CPU or DTC. The DTIF bit is set to 1 when the ACT bit in DMDR is cleared to 0 to stop a transfer after the bus cycle is completed. The DTIF bit is automatically cleared to 0 and a transfer request is cleared if the transfer is resumed by setting the DTE bit to 1 during interrupt handling. For details on interrupts, see section 10.8, Interrupt Sources.

10.5.8 Priority of Channels

The channels of the DMAC are given following priority levels: channel 0 > channel 1 > channel 2 > channel3. Table 10.6 shows the priority levels among the DMAC channels. Table 10.6 Priority among DMAC Channels Channel Priority Channel 0 High Channel 1 Channel 2 Channel 3 Low The channel having highest priority other than the channel being transferred is selected when a transfer is requested from other channels. The selected channel starts the transfer after the channel being transferred releases the bus. At this time, when a bus master other than the DMAC requests the bus, the cycle for the bus master is inserted. In a burst transfer or a block transfer, channels are not switched.

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10.5.9 DMA Basic Bus Cycle

Figure 10.23 shows an examples of signal timing of a basic bus cycle. In figure 10.23, data is transferred in words from the 16-bit 2-state access space to the 8-bit 3-state access space. When the bus mastership is passed from the DMAC to the CPU, data is read from the source address and it is written to the destination address. The bus is not released between the read and write cycles by other bus requests. DMAC bus cycles follows the bus controller settings. CPU cycle DMAC cycle (one word transfer) CPU cycle Address bus Bφ T1 T2 T1 T2 T3 T1 T2 T3 Source address Destination address RD LHWR LLWR High Figure 10.23 Example of Bus Timing of DMA Transfer

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10.5.10 Bus Cycles in Dual Address Mode

(1) Normal Transfer Mode (Cycle Stealing Mode) In cycle stealing mode, the bus is released every time one transfer size of data (one byte, one word, or one longword) is completed. One bus cycle or more by the CPU or DTC are executed in the bus released cycles. In figure 10.24, the TEND signal output is enabled and data is transferred in words from the external 16-bit 2-state access space to the external 16-bit 2-state access space in normal transfer mode by cycle stealing. DMA read cycle DMA write cycle Address bus DMA read cycle DMA write cycle DMA read cycle DMA write cycle Bφ RD LHWR, LLWR TEND Bus released Bus released Bus released Bus released Last transfer cycle Figure 10.24 Example of Transfer in Normal Transfer Mode by Cycle Stealing In figures 10.25 and 10.26, the TEND signal output is enabled and data is transferred in longwords from the external 16-bit 2-state access space to the 16-bit 2-state access space in normal transfer mode by cycle stealing. In figure 10.25, the transfer source (DSAR) is not aligned with a longword boundary and the transfer destination (DDAR) is aligned with a longword boundary. In figure 10.26, the transfer source (DSAR) is aligned with a longword boundary and the transfer destination (DDAR) is not aligned with a longword boundary.

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 440 of 1438 REJ09B0365-0200 (2) Normal Transfer Mode (Burst Mode) In burst mode, one byte, one word, or one longword of data continues to be transferred until the transfer end condition is satisfied. When a burst transfer starts, a transfer request from a channel having priority is suspended until the burst transfer is completed. In figure 10.27, the TEND signal output is enabled and data is transferred in words from the external 16-bit 2-state access space to the external 16-bit 2-state access space in normal transfer mode by burst access. DMA read cycle DMA read cycleDMA write cycle Address bus DMA write cycle DMA read cycle DMA write cycle Bφ RD LHWR, LLWR TEND Bus released Bus released Last transfer cycle Burst transfer Figure 10.27 Example of Transfer in Normal Transfer Mode by Burst Access

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 441 of 1438 REJ09B0365-0200 (3) Block Transfer Mode In block transfer mode, the bus is released every time a 1-block size of transfers at a single transfer request is completed. In figure 10.28, the TEND signal output is enabled and data is transferred in words from the external 16-bit 2-state access space to the external 16-bit 2-state access space in block transfer mode. DMA read cycle DMA read cycle DMA write cycle Address bus DMA write cycle DMA read cycle DMA read cycle DMA write cycle DMA write cycle Bφ RD LHWR, LLWR TEND Bus released Bus released Bus released Last block transfer cycleBlock transfer Figure 10.28 Example of Transfer in Block Transfer Mode

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10.5.11 Bus Cycles in Single Address Mode

(1) Single Address Mode (Read and Cycle Stealing) In single address mode, one byte, one word, or one longword of data is transferred at a single transfer request and after the transfer the bus is released temporarily. One bus cycle or more by the CPU or DTC are executed in the bus released cycles. In figure 10.34, the TEND signal output is enabled and data is transferred in bytes from the external 8-bit 2-state access space to the external device in single address mode (read). Bus released Bus released Bus released DMA read cycle DMA read cycle DMA read cycle DMA read cycle Bφ Address bus Bus released Bus released Last transfer cycle RD TEND DACK Figure 10.34 Example of Transfer in Single Address Mode (Byte Read)

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 448 of 1438 REJ09B0365-0200 (2) Single Address Mode (Write and Cycle Stealing) In single address mode, data of one byte, one word, or one longword is transferred at a single transfer request and after the transfer the bus is released temporarily. One bus cycle or more by the CPU or DTC are executed in the bus released cycles. In figure 10.35, the TEND signal output is enabled and data is transferred in bytes from the external 8-bit 2-state access space to the external device in single address mode (write). Bus released Bus released DMA write cycle Bφ Address bus Bus released Bus released Last transfer cycle TEND DACK DMA write cycle DMA write cycle DMA write cycle LLWR Bus released Figure 10.35 Example of Transfer in Single Address Mode (Byte Write)

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10.6 DMA Transfer End

Operations on completion of a transfer differ according to the transfer end condition. DMA transfer completion is indicated that the DTE and ACT bits in DMDR are changed from 1 to 0. (1) Transfer End by DTCR Change from 1, 2, or 4, to 0 When DTCR is changed from 1, 2, or 4 to 0, a DMA transfer for the channel is completed. The DTE bit in DMDR is cleared to 0 and the DTIF bit in DMDR is set to 1. At this time, when the DTIE bit in DMDR is set to 1, a transfer end interrupt by the transfer counter is requested. When the DTCR value is 0 before the transfer, the transfer is not stopped. (2) Transfer End by Transfer Size Error Interrupt When the following conditions are satisfied while the TSEIE bit in DMDR is set to 1, a transfer size error occurs and a DMA transfer is terminated. At this time, the DTE bit in DMDR is cleared to 0 and the ESIF bit in DMDR is set to 1.

• In normal transfer mode and repeat transfer mode, when the next transfer is requested while a transfer is disabled due to the DTCR value less than the data access size
• In block transfer mode, when the next transfer is requested while a transfer is disabled due to the DTCR value less than the block size When the TSEIE bit in DMDR is cleared to 0, data is transferred until the DTCR value reaches 0. A transfer size error is not generated. Operation in each transfer mode is shown below.
• In normal transfer mode and repeat transfer mode, when the DTCR value is less than the data access size, data is transferred in bytes
• In block transfer mode, when the DTCR value is less than the block size, the specified size of data in DTCR is transferred instead of transferring the block size of data. The transfer is performed in bytes.

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 453 of 1438 REJ09B0365-0200 (3) Transfer End by Repeat Size End Interrupt In repeat transfer mode, when the next transfer is requested after completion of a 1-repeat size data transfer while the RPTIE bit in DACR is set to 1, a repeat size end interrupt is requested. When the interrupt is requested to complete DMA transfer, the DTE bit in DMDR is cleared to 0 and the ESIF bit in DMDR is set to 1. Under this condition, setting the DTE bit to 1 resumes the transfer. In block transfer mode, when the next transfer is requested after completion of a 1-block size data transfer, a repeat size end interrupt can be requested. (4) Transfer End by Interrupt on Extended Repeat Area Overflow When an overflow on the extended repeat area occurs while the extended repeat area is specified and the SARIE or DARIE bit in DACR is set to 1, an interrupt by an extended repeat area overflow is requested. When the interrupt is requested, the DMA transfer is terminated, the DTE bit in DMDR is cleared to 0, and the ESIF bit in DMDR is set to 1. In dual address mode, even if an interrupt by an extended repeat area overflow occurs during a read cycle, the following write cycle is performed. In block transfer mode, even if an interrupt by an extended repeat area overflow occurs during a 1- block transfer, the remaining data is transferred. The transfer is not terminated by an extended repeat area overflow interrupt unless the current transfer is complete. (5) Transfer End by Clearing DTE Bit in DMDR When the DTE bit in DMDR is cleared to 0 by the CPU, a transfer is completed after the current DMA cycle and a DMA cycle in which the transfer request is accepted are completed. In block transfer mode, a DMA transfer is completed after 1-block data is transferred.

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 454 of 1438 REJ09B0365-0200 (6) Transfer End by NMI Interrupt When an NMI interrupt is requested, the DTE bits for all the channels are cleared to 0 and the ERRF bit in DMDR_0 is set to 1. When an NMI interrupt is requested during a DMA transfer, the transfer is forced to stop. To perform DMA transfer after an NMI interrupt is requested, clear the ERRF bit to 0 and then set the DTE bits for the channels to 1. The transfer end timings after an NMI interrupt is requested are shown below. (a) Normal Transfer Mode and Repeat Transfer Mode In dual address mode, a DMA transfer is completed after completion of the write cycle for one transfer unit. In single address mode, a DMA transfer is completed after completion of the bus cycle for one transfer unit. (b) Block Transfer Mode A DMA transfer is forced to stop. Since a 1-block size of transfers is not completed, operation is not guaranteed. In dual address mode, the write cycle corresponding to the read cycle is performed. This is similar to (a) in normal transfer mode. (7) Transfer End by Address Error When an address error occurs, the DTE bits for all the channels are cleared to 0 and the ERRF bit in DMDR_0 is set to 1. When an address error occurs during a DMA transfer, the transfer is forced to stop. To perform a DMA transfer after an address error occurs, clear the ERRF bit to 0 and then set the DTE bits for the channels. The transfer end timing after an address error is the same as that after an NMI interrupt. (8) Transfer End by Hardware Standby Mode or Reset The DMAC is initialized by a reset and a transition to the hardware standby mode. A DMA transfer is not guaranteed.

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10.7 Relationship among DMAC and Other Bus Masters

10.7.1 CPU Priority Control Function Over DMAC

The CPU priority control function over DMAC can be used according to the CPU priority control register (CPUPCR) setting. For details, see section 7.7, CPU Priority Control Function Over DTC, DMAC, and EXDMAC. The priority level of the DMAC is specified by bits DMAP2 to DMAP0 and can be specified for each channel. The priority level of the CPU is specified by bits CPUP2 to CPUP0. The value of bits CPUP2 to CPUP0 is updated according to the exception handling priority. If the CPU priority control is enabled by the CPUPCE bit in CPUPCR, when the CPU has priority over the DMAC, a transfer request for the corresponding channel is masked and the transfer is not activated. When another channel has priority over or the same as the CPU, a transfer request is received regardless of the priority between channels and the transfer is activated. The transfer request masked by the CPU priority control function is suspended. When the transfer channel is given priority over the CPU by changing priority levels of the CPU or channel, the transfer request is received and the transfer is resumed. Writing 0 to the DTE bit clears the suspended transfer request. When the CPUPCE bit is cleared to 0, it is regarded as the lowest priority.

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10.7.2 Bus Arbitration among DMAC and Other Bus Masters

When DMA transfer cycles are consecutively performed, bus cycles of other bus masters may be inserted between the transfer cycles. The DMAC can release the bus temporarily to pass the bus to other bus masters. The consecutive DMA transfer cycles may not be divided according to the transfer mode settings to achieve high-speed access. The read and write cycles of a DMA transfer are not separated. Refreshing, external bus release, and on-chip bus master (CPU, DTC, or EXDMAC*) cycles are not inserted between the read and write cycles of a DMA transfer. In block transfer mode and an auto request transfer by burst access, bus cycles of the DMA transfer are consecutively performed. For this duration, since the DMAC has priority over the CPU and DTC, accesses to the external space are suspended (the IBCCS bit in the bus control register 2 (BCR2) is cleared to 0). When the bus is passed to another channel or an auto request transfer by cycle stealing, bus cycles of the DMAC and on-chip bus master are performed alternatively. When the arbitration function among the DMAC and on-chip bus masters is enabled by setting the IBCCS bit in BCR2, the bus is used alternatively except the bus cycles which are not separated. For details, see section 9, Bus Controller (BSC). A conflict may occur among the external space access of a DMAC, refresh cycle*, an EXDMAC cycle*, and an external bus release cycle. Even if a burst or block transfer is performed by the DMAC, the transfer is stopped temporarily and the refresh cycle*, EXDMAC cycle*, and external bus release cycle are inserted by the BSC according to the external bus priority (when the CPU external access and the DTC external access do not have priority over a DMAC transfer, the transfers are not operated until the DMAC releases the bus). In dual address mode, the DMAC releases the external bus after the external space write cycle. Since the read and write cycles are not separated, the bus is not released. An internal space (on-chip memory and internal I/O registers) access of the DMAC and a refresh cycle, an EXDMAC cycle, and an external bus release cycle may be performed at the same time. Note: * Supported only by the H8S/1648G Group and H8S/1648H Group.

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 457 of 1438 REJ09B0365-0200

10.8 Interrupt Sources

The DMAC interrupt sources are a transfer end interrupt by the transfer counter and a transfer escape end interrupt which is generated when a transfer is terminated before the transfer counter reaches 0. Table 10.7 shows interrupt sources and priority. For details, see section 7, Interrupt Controller. Table 10.7 Interrupt Sources and Priority Abbr. Interrupt Sources Priority DMTEND0 Transfer end interrupt by channel 0 transfer counter High DMTEND1 Transfer end interrupt by channel 1 transfer counter DMTEND2 Transfer end interrupt by channel 2 transfer counter DMTEND3 Transfer end interrupt by channel 3 transfer counter DMEEND0 Interrupt by channel 0 transfer size error Interrupt by channel 0 repeat size end Interrupt by channel 0 extended repeat area overflow on source address Interrupt by channel 0 extended repeat area overflow on destination address DMEEND1 Interrupt by channel 1 transfer size error Interrupt by channel 1 repeat size end Interrupt by channel 1 extended repeat area overflow on source address Interrupt by channel 1 extended repeat area overflow on destination address DMEEND2 Interrupt by channel 2 transfer size error Interrupt by channel 2 repeat size end Interrupt by channel 2 extended repeat area overflow on source address Interrupt by channel 2 extended repeat area overflow on destination address DMEEND3 Interrupt by channel 3 transfer size error Interrupt by channel 3 repeat size end Interrupt by channel 3 extended repeat area overflow on source address Interrupt by channel 3 extended repeat area overflow on destination address Low Each interrupt is enabled or disabled by the DTIE and ESIE bits in DMDR for the corresponding channel. A DMTEND interrupt is generated by the combination of the DTIF and DTIE bits in DMDR. A DMEEND interrupt is generated by the combination of the ESIF and ESIE bits in DMDR. The DMEEND interrupt sources are not distinguished. The priority among channels is decided by the interrupt controller and it is shown in table 10.7. For details, see section 7, Interrupt Controller.

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 458 of 1438 REJ09B0365-0200 Each interrupt source is specified by the interrupt enable bit in the register for the corresponding channel. A transfer end interrupt by the transfer counter, a transfer size error interrupt, a repeat size end interrupt, an interrupt by an extended repeat area overflow on the source address, and an interrupt by an extended repeat area overflow on the destination address are enabled or disabled by the DTIE bit in DMDR, the TSEIE bit in DMDR, the RPTIE bit in DACR, SARIE bit in DACR, and the DARIE bit in DACR, respectively. A transfer end interrupt by the transfer counter is generated when the DTIF bit in DMDR is set to 1. The DTIF bit is set to 1 when DTCR becomes 0 by a transfer while the DTIE bit in DMDR is set to 1. An interrupt other than the transfer end interrupt by the transfer counter is generated when the ESIF bit in DMDR is set to 1. The ESIF bit is set to 1 when the conditions are satisfied by a transfer while the enable bit is set to 1. A transfer size error interrupt is generated when the next transfer cannot be performed because the DTCR value is less than the data access size, meaning that the data access size of transfers cannot be performed. In block transfer mode, the block size is compared with the DTCR value for transfer error decision. A repeat size end interrupt is generated when the next transfer is requested after completion of the repeat size of transfers in repeat transfer mode. Even when the repeat area is not specified in the address register, the transfer can be stopped periodically according to the repeat size. At this time, when a transfer end interrupt by the transfer counter is generated, the ESIF bit is set to 1. An interrupt by an extended repeat area overflow on the source and destination addresses is generated when the address exceeds the extended repeat area (overflow). At this time, when a transfer end interrupt by the transfer counter, the ESIF bit is set to 1. Figure 10.39 is a block diagram of interrupts and interrupt flags. To clear an interrupt, clear the DTIF or ESIF bit in DMDR to 0 in the interrupt handling routine or continue the transfer by setting the DTE bit in DMDR after setting the register. Figure 10.40 shows procedure to resume the transfer by clearing an interrupt.

Section 10 DMA Controller (DMAC) Rev. 2.00 Jul. 31, 2008 Page 460 of 1438 REJ09B0365-0200

10.9 Usage Notes

1. DMAC Register Access During Operation Except for clearing the DTE bit in DMDR, the settings for channels being transferred (including waiting state) must not be changed. The register settings must be changed during the transfer prohibited state. 2. Settings of Module Stop Function The DMAC operation can be enabled or disabled by the module stop control register. The DMAC is enabled by the initial value. Setting bit MSTPA13 in MSTPCRA stops the clock supplied to the DMAC and the DMAC enters the module stop state. However, when a transfer for a channel is enabled or when an interrupt is being requested, bit MSTPA13 cannot be set to 1. Clear the DTE bit to 0, clear the DTIF or DTIE bit in DMDR to 0, and then set bit MSTPA13. When the clock is stopped, the DMAC registers cannot be accessed. However, the following register settings are valid in the module stop state. Disable them before entering the module stop state, if necessary.  TENDE bit in DMDR is 1 (the TEND signal output enabled)  DACKE bit in DMDR is 1 (the DACK signal output enabled) 3. Activation by DREQ Falling Edge The DREQ falling edge detection is synchronized with the DMAC internal operation. A. Activation request waiting state: Waiting for detecting the DREQ low level. A transition to 2. is made. B. Transfer waiting state: Waiting for a DMAC transfer. A transition to 3. is made. C. Transfer prohibited state: Waiting for detecting the DREQ high level. A transition to 1. is made. After a DMAC transfer enabled, a transition to 1. is made. Therefore, the DREQ signal is sampled by low level detection at the first activation after a DMAC transfer enabled. 4. Acceptation of Activation Source At the beginning of an activation source reception, a low level is detected regardless of the setting of DREQ falling edge or low level detection. Therefore, if the DREQ signal is driven low before setting DMDR, the low level is received as a transfer request. When the DMAC is activated, clear the DREQ signal of the previous transfer.

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 461 of 1438 REJ09B0365-0200 Section 11 EXDMA Controller (EXDMAC) EXDMAC is supported both by the H8SX/1648G Group and H8SX/1648H Group but neither by the H8SX/1648 Group, H8SX/1648A Group, nor the H8SX/1648L Group. This LSI has an on-chip four-channel external bus transfer DMA controller (EXDMAC). The EXDMAC can carry out high-speed data transfer, in place of the CPU, to and from external devices and external memory. Also, the EXDMAC allows external bus transfer in parallel with the internal CPU operation when there is no external bus request from a controller other than the EXDMAC.

11.1 Features

• Up to 4-Gbyte address space accessible
• Selection of byte, word, or longword transfer data length
• Total transfer size of up to 4 Gbytes (4,294,967,295 bytes) Selection of free-running mode (with no total transfer size specified)
• Selection of auto-requests or external requests for activating the EXDMAC Auto-request: Activation from the CPU (Cycle steal mode or burst mode can be selected.) External request: Low level sensing or falling edge sensing for the EDREQ signal can be selected. All of four channels can accept external requests.
• Selection of dual address mode or single address mode Dual address mode: Both the transfer source and destination addresses are specified to transfer data. Single address mode: The EDACK signal is used to access the transfer source or destination peripheral device and the address of the other device is specified to transfer data.
• Normal, repeat, block, or cluster transfer (only for the EXDMAC) can be selected as transfer mode Normal transfer mode: One byte, one word, or on e longword data is transferred at a single transfer request Repeat transfer mode: One byte, one word, or one longword data is transferred at a single transfer request Repeat size of data is transferred an d then a transfer address returns to the transfer start address Up to 64-kbyte transfers can be set as repeat size (65,536 bytes/words/longwords) Block transfer mode: One block data is transferred at a single transfer request

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 462 of 1438 REJ09B0365-0200 Up to 64-kbyte data can be set as block size (65,536 bytes/words/longwords) Cluster transfer mode: One cluster data is transferred at a single transfer request Up to 32-byte data can be set as cluster size

• Selection of extended repeat area function (to transfer data such as ring buffer data by fixing the upper bit value in the transfer address register and repeating the address values in a specified range) For the extended repeat area, 1 bit (2 bytes) to 27 bits (128 Mbytes) can be set independently for the transfer source or destination.
• Selection of address update methods: Increment/decrement by 1, 2 or 4, fixed, or offset addition When offset addition is used to update addresses, the mid-addresses can be skipped during data transfer.
• Transfer of word or longword data to addresses beyond each data boundary Data can be divided into an optimal data size (byte or word) according to addresses when transferring data.
• Two kinds of interrupts requested to the CPU Transfer end interrupt: Requested after the number of data set by the transfer counter has been completely transferred Transfer escape end interrupt: Requested when the remaining transfer size is smaller than the size set for a single transfer request, after a repeat-size transfer is completed, or when an extended repeat area overflow occurs.
• Acceptance of a transfer request can be reported to an external device via the EDRAK pin (only for the EXDMAC).
• Operation of EXDMAC, connected to a dedicated bus, in parallel with a bus master such as the CPU, DTC, or DMAC (only for the EXDMAC).
• Module stop state can be set.

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 464 of 1438 REJ09B0365-0200

11.2 Input/Output Pins

Table 11.1 shows the EXDMAC pin configuration. Table 11.1 Pin Configuration Channel Name A bbr. I/O Function EXDMA transfer request 0 EDREQ0 Input Channel 0 external request EXDMA transfer acknowledge 0 EDACK0 Output Channel 0 single address transfer acknowledge EXDMA transfer end 0 ETEND0 Output Channel 0 transfer end EDREQ0 acceptance acknowledge EDRAK0 Output Notification to external device of channel 0 external request acceptance and start of execution EXDMA transfer request 1 EDREQ1 Input Channel 1 external request EXDMA transfer acknowledge 1 EDACK1 Output Channel 1 single address transfer acknowledge EXDMA transfer end 1 ETEND1 Output Channel 1 transfer end EDREQ1 acceptance acknowledge EDRAK1 Output Notification to external device of channel 1 external request acceptance and start of execution EXDMA transfer request 2 EDREQ2 Input Channel 2 external request EXDMA transfer acknowledge 2 EDACK2 Output Channel 2 single address transfer acknowledge EXDMA transfer end 2 ETEND2 Output Channel 2 transfer end EDREQ2 acceptance acknowledge EDRAK2 Output Notification to external device of channel 2 external request acceptance and start of execution EXDMA transfer request 3 EDREQ3 Input Channel 3 external request EXDMA transfer acknowledge 3 EDACK3 Output Channel 3 single address transfer acknowledge EXDMA transfer end 3 ETEND3 Output Channel 3 transfer end EDREQ3 acceptance acknowledge EDRAK3 Output Notification to external device of channel 3 external request acceptance and start of execution

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 465 of 1438 REJ09B0365-0200

11.3 Registers Descriptions

The EXDMAC has the following registers. Channel 0

• EXDMA source address register_0 (EDSAR_0)
• EXDMA destination address register_0 (EDDAR_0)
• EXDMA offset register_0 (EDOFR_0)
• EXDMA transfer count register_0 (EDTCR_0)
• EXDMA block size register_0 (EDBSR_0)
• EXDMA mode control register_0 (EDMDR_0)
• EXDMA address control register_0 (EDACR_0) Channel 1
• EXDMA source address register_1 (EDSAR_1)
• EXDMA destination address register_1 (EDDAR_1)
• EXDMA offset register_1 (EDOFR_1)
• EXDMA transfer count register_1 (EDTCR_1)
• EXDMA block size register_1 (EDBSR_1)
• EXDMA mode control register_1 (EDMDR_1)
• EXDMA address control register_1 (EDACR_1) Channel 2
• EXDMA source address register_2 (EDSAR_2)
• EXDMA destination address register_2 (EDDAR_2)
• EXDMA offset register_2 (EDOFR_2)
• EXDMA transfer count register_2 (EDTCR_2)
• EXDMA block size register_2 (EDBSR_2)
• EXDMA mode control register_2 (EDMDR_2)
• EXDMA address control register_2 (EDACR_2)

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 466 of 1438 REJ09B0365-0200 Channel 3

• EXDMA source address register_3 (EDSAR_3)
• EXDMA destination address register_3 (EDDAR_3)
• EXDMA offset register_3 (EDOFR_3)
• EXDMA transfer count register_3 (EDTCR_3)
• EXDMA block size register_3 (EDBSR_3)
• EXDMA mode control register_3 (EDMDR_3)
• EXDMA address control register_3 (EDACR_3) Common register
• Cluster buffer registers 0 to 7 (CLSBR0 to CLSBR7)

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 467 of 1438 REJ09B0365-0200

11.3.1 EXDMA Source Ad dress Register (EDSAR)

EDSAR is a 32-bit readable/writable register that specifies the transfer source address. An address update function is provided that updates the register contents to the next transfer source address each time transfer processing is performed. In single address mode, the EDSAR value is ignored when the address specified by EDDAR is transferred as a destination address (DIRS = 1 in EDACR). EDSAR can be read at all times by the CPU. When reading EDSAR for a channel on which EXDMA transfer processing is in progress, a longword-size read must be executed. Do not write to EDSAR for a channel on which EXDMA transfer is in progress. R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 468 of 1438 REJ09B0365-0200

11.3.2 EXDMA Destination Address Register (EDDAR)

EDDAR is a 32-bit readable/writable register that specifies the transfer destination address. An address update function is provided that updates the register contents to the next transfer destination address each time transfer processing is performed. In single address mode, the EDDAR value is ignored when the address specified by EDSAR is transferred as a source address (DIRS = 0 in EDACR). EDDAR can be read at all times by the CPU. When reading EDDAR for a channel on which EXDMA transfer processing is in progress, a longword-size read must be executed. Do not write to EDDAR for a channel on which EXDMA transfer is in progress. R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 469 of 1438 REJ09B0365-0200

11.3.3 EXDMA Offset Register (EDOFR)

EDOFR is a 32-bit readable/writable register that sets the offset value when offset addition is selected for updating source or destination addresses. This register can be set independently for each channel, but the same offset value must be used for the source and destination addresses on the same channel. R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 470 of 1438 REJ09B0365-0200

11.3.4 EXDMA Transfer Count Register (EDTCR)

EDTCR is a 32-bit readable/writable register that specifies the size of data to be transferred (total transfer size). When EDTCR is set to H'00000001, the total transfer size is 1 byte. When EDTCR is set to H'00000000, the total transfer size is not specified and the transfer counter is halted (free-running mode). In this case, no transfer end interrupt by the transfer counter is generated. When EDTCR is set to H'FFFFFFFF, up to 4 Gbytes (4,294,967,295 bytes) of the total transfer size is set. When the EXDMA is active, EDTCR indicates the remaining transfer size. The value according to the data access size (byte: −1, word: −2, longword: −4) is decremented each time of a data transfer. EDTCR can be read at all times by the CPU. When reading EDTCR for a channel on which EXDMA transfer processing is in progress, a longword-size read must be executed. Do not write to EDTCR for a channel on which EXDMA transfer is in progress. R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 471 of 1438 REJ09B0365-0200

11.3.5 EXDMA Block Size Register (EDBSR)

EDBSR sets the repeat size, block size, or cluster size. EDBSR is enabled in repeat transfer, block transfer, and cluster transfer modes. EDBSR is disabled in normal transfer mode. When BKSZH and BKSZ are set to H'0001 in cluster transfer mode (dual address mode), the EXDMAC operates in block transfer mode (dual address mode). BKSZH31 R/W BKSZH30 R/W BKSZH29 R/W BKSZH28 R/W BKSZH27 R/W BKSZH24 R/W BKSZH26 R/W BKSZH25 R/W Bit Bit Name Initial Value R/W BKSZH23 R/W BKSZH22 R/W BKSZH21 R/W BKSZH20 R/W BKSZH19 R/W BKSZH16 R/W BKSZH18 R/W BKSZH17 R/W Bit Bit Name Initial Value R/W BKSZ15 R/W BKSZ14 R/W BKSZ13 R/W BKSZ12 R/W BKSZ11 R/W BKSZ8 R/W BKSZ10 R/W BKSZ9 R/W Bit Bit Name Initial Value R/W BKSZ7 R/W BKSZ6 R/W BKSZ5 R/W BKSZ4 R/W BKSZ3 R/W BKSZ0 R/W BKSZ2 R/W BKSZ1 R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial value R/W Description 31 to 16 BKSZH31 to BKSZH16 All 0 R/W Sets the repeat size, block size, or cluster size. When these bits are set to H'0001, one byte-, one word-, or one longword-size is set. When these bits are set to H'0000, the maximum values are set (see table 11.2). These bits are always fixed during an EXDMA operation. 15 to 0 BKSZ15 to BKSZ0 All 0 R/W In an EXDMA operation, the remaining repeat size, block size, or cluster size is indicated. The value is decremented by one each time of a data transfer. When the remaining size becomes zero, the BKSZH value is loaded. Set the same initial value as for the BKSZH bit when writing.

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 472 of 1438 REJ09B0365-0200 Table 11.2 Data Access Size, Enable Bit, and Allowable Size Mode Data Access Size BKSZH enable bit BKSZ enable bit Allowable size (in bytes) Byte 1 to 65,536 Word 2 to 131,072 Repeat transfer mode Block transfer mode Longword 31 to 16 15 to 0 4 to 262,144 Byte 20 to 16 4 to 0 1 to 32 Word 19 to 16 3 to 0 2 to 32 Cluster transfer mode Longword 18 to 16 2 to 0 4 to 32

11.3.6 EXDMA Mode Control Register (EDMDR)

EDMDR controls EXDMAC operations.

• EDMDR_0 DTE R/W EDACKE R/W ETENDE R/W EDRAKE R/W EDREQS R/W R NRD R/W R Bit Bit Name Initial Value R/W ACT R R R R ERRF R/(W)* DTIF R/(W)* R ESIF R/(W)* Bit Bit Name Initial Value R/W DTSZ1 R/W DTSZ0 R/W MDS1 R/W MDS0 R/W TSEIE R/W DTIE R/W R ESIE R/W Bit Bit Name Initial Value R/W DTF1 R/W DTF0 R/W R/W R R EDMAP0 R/W EDMAP2 R/W EDMAP1 R/W Bit Bit Name Initial Value R/W Note: * Only 0 can be written to this bit after having been read as 1, to clear the flag.

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 473 of 1438 REJ09B0365-0200

• EDMDR_1 to EDMDR_3 DTE R/W EDACKE R/W ETENDE R/W EDRAKE R/W DREQS R/W R NRD R/W R Bit Bit Name Initial Value R/W ACT R R R R R DTIF R/(W)* R ESIF R/(W)* Bit Bit Name Initial Value R/W DTSZ1 R/W DTSZ0 R/W MDS1 R/W MDS0 R/W TSEIE R/W DTIE R/W R ESIE R/W Bit Bit Name Initial Value R/W DTF1 R/W DTF0 R/W R/W R R EDMAP0 R/W EDMAP2 R/W EDMAP1 R/W Bit Bit Name Initial Value R/W Note: * Only 0 can be written to this bit after having been read as 1, to clear the flag.

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 474 of 1438 REJ09B0365-0200 Bit Bit Name Initial value R/W Description Enables or disables data transfer on the corresponding channel. When this bit is set to 1, this indicates that an EXDMA operation is in progress. When auto-request mode is specified, transfer processing begins when this bit is set to 1. With external requests, transfer processing begins when a transfer request is issued after this bit has been set to 1. When this bit is cleared to 0 during an EXDMA operation, transfer is halted. If this bit is cleared to 0 during an EXDMA operation in block transfer mode, this bit is cleared to 0 on completion of the currently executing one-block transfer. When this bit is cleared to 0 during an EXDMA operation in cluster transfer mode, this bit is cleared to 0 on completion of the currently executing one-cluster transfer. If an external source that ends (aborts) transfer occurs, this bit is automatically cleared to 0 and transfer is terminated. Do not change the operating mode, transfer method, or other parameters while this bit is set to 1. 0: Data transfer disabled 1: Data transfer enabled (during an EXDMA operation) [Clearing conditions]

• When transfer of the total transfer size specified ends
• When operation is halted by a repeat size end interrupt
• When operation is halted by an extended repeat area overflow interrupt
• When operation is halted by a transfer size error interrupt
• When 0 is written to terminate transfer In block transfer mode, the value written is effective after one-block transfer ends. In cluster transfer mode, the value written is effective after one-cluster transfer ends.
• When an address error or NMI interrupt occurs
• Reset, hardware standby mode

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 475 of 1438 REJ09B0365-0200 Bit Bit Name Initial value R/W Description

30 EDACKE 0 R/W EDACK Pin Output Enable

In single address mode, enables or disables output from the EDACK pin. In dual address mode, the specification by this bit is ignored. 0: EDACK pin output disabled 1: EDACK pin output enabled

29 ETENDE 0 R/W ETEND Pin Output Enable

Enables or disables output from the ETEND pin. 0: ETEND pin output disabled 1: ETEND pin output enabled

28 EDRAKE 0 R/W EDRAK Pin Output Enable

Enables or disables output from the EDRAK pin. 0: EDRAK pin output disabled 1: EDRAK pin output enabled

27 EDREQS 0 R/W EDREQ Select

Selects whether a low level or the falling edge of the EDREQ signal used in external request mode is detected. 0: Low-level detection 1: Falling edge detection (the first transfer is detected on a low level after a transfer is enabled.) Selects the timing of the next transfer request to be accepted. 0: Next transfer request starts to be accepted after transfer of the bus cycle in progress ends. 1: Next transfer request starts to be accepted after one cycle of Bφ from the completion of the bus cycle in progress. 25, 24  All 0 R Reserved They are always read as 0 and cannot be modified.

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 476 of 1438 REJ09B0365-0200 Bit Bit Name Initial value R/W Description Indicates the operation state of the corresponding channel. 0: Transfer request wait state or transfer disabled state (DTE = 0) 1: Active state 22 to 20  All 0 R Reserved They are always read as 0 and cannot be modified. Flag that indicates the occurrence of an address error or NMI interrupt. This bit is only enabled in EDMDR_0. When this bit is set to 1, write to the DTE bit for all channels is disabled. This bit is reserved in EDMDR_1 to EDMDR_3. They are always read as 0 and cannot be modified. 0: Address error or NMI interrupt is not generated 1: Address error or NMI interrupt is generated [Clearing condition]

• Writing 0 to ERRF after reading ERRF = 1 [Setting condition]
• When an address error or NMI interrupt occurred However, when an address error or an NMI interrupt has been generated in EXDMAC module stop mode, this bit is not set to 1. 18  0 R Reserved They are always read as 0 and cannot be modified.

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 477 of 1438 REJ09B0365-0200 Bit Bit Name Initial value R/W Description Flag indicating that a transfer escape end interrupt request has occurred before the transfer counter becomes 0 and transfer escape has ended. 0: Transfer escape end interrupt request is not generated 1: Transfer escape end interrupt request is generated [Clearing conditions]

• Writing 1 to the DTE bit
• Writing 0 to ESIF while reading ESIF = 1 [Setting conditions]
• Transfer size error interrupt request is generated
• Repeat size end interrupt request is generated
• Extended repeat area overflow end interrupt request is generated

Flag indicating that a transfer end interrupt request has occurred by the transfer counter. 0: Transfer end interrupt request is not generated by the transfer counter 1: Transfer end interrupt request is generated by the transfer counter [Clearing conditions]

• Writing 1 to the DTE bit
• Writing 0 to DTIF while reading DTIF = 1 [Setting condition]
• When EDTCR becomes 0 and transfer has ended DTSZ1 DTSZ0 R/W R/W Data Access Size 1 and 0 Selects the data access size. 00: Byte-size (8 bits) 01: Word-size (16 bits) 10: Longword-size (32 bits) 11: Setting prohibited

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 478 of 1438 REJ09B0365-0200 Bit Bit Name Initial value R/W Description MDS1 MDS0 R/W R/W Transfer Mode Select 1 and 0 Selects the transfer mode. 00: Normal transfer mode 01: Block transfer mode 10: Repeat transfer mode 11: Cluster transfer mode Enables or disables a transfer size error interrupt request. When this bit is set to 1 and the transfer counter value becomes smaller than the data access size for one transfer request by EXDMAC transfer, the DTE bit is cleared to 0 by the next transfer request. At the same time, the ESIF bit is set to 1 to indicate that a transfer size error interrupt request is generated. When cluster transfer read/write address mode is specified, this bit should be set to 1. Transfer size error interrupt request occurs in the following conditions:

• In normal transfer and repeat transfer modes, the total transfer size set in EDTCR is smaller than the data access size
• In block transfer mode, the total transfer size set in EDTCR is smaller than the block size
• In cluster transfer mode, the total transfer size set in EDTCR is smaller than the cluster size 0: Transfer size error interrupt request disabled 1: Transfer size error interrupt request enabled 10  0 R Reserved They are always read as 0 and cannot be modified.

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 479 of 1438 REJ09B0365-0200 Bit Bit Name Initial value R/W Description Enables or disables a transfer escape end interrupt request occurred during EXDMA transfer. When this bit is set to 1, and the ESIF bit is set to 1, a transfer escape end interrupt is requested to the CPU or DTC. The transfer escape end interrupt request is canceled by clearing this bit or the ESIF bit to 0. 0: Transfer escape interrupt request disabled 1: Transfer escape interrupt request enabled

8 DTIE 0 R/W Data Transfer Interrupt Enable

Enables or disables a transfer end interrupt request by the transfer counter. When this bit is set to 1 and the DTIF bit is set to 1, a transfer end interrupt is requested to the CPU or DTC. The transfer end interrupt request is canceled by clearing this bit or the DTIF bit to 0. 0: Transfer end interrupt request disabled 1: Transfer end interrupt request enabled DTF1 DTF0 R/W R/W Data Transfer Factor 1 and 0 Selects a source to activate EXDMAC. For external requests, a sampling method is selected by the EDREQS bit. 00: Auto-request (cycle steal mode) 01: Auto-request (burst mode) 10: Setting prohibited 11: External request 5  0 R/W Reserved The initial value should not be changed.

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 480 of 1438 REJ09B0365-0200 Bit Bit Name Initial value R/W Description 4, 3  All 0 R Reserved They are always read as 0 and cannot be modified. EDMAP2 EDMAP1 EDMAP0 R/W R/W R/W EXDMA Priority Levels 2 to 0 Selects the EXDMAC priority level when using the CPU priority control function over DTC and EXDMAC. When the EXDMAC priority level is lower than the CPU priority level, EXDMAC masks the acceptance of transfer source and waits until the CPU priority level becomes low. The priority level can be set independently for each channel. This bit is enabled when the CPUPCE bit in CPUPCR is 1. 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest) Note: * Only 0 can be written to these bits after 1 is read to clear the flag.

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11.3.7 EXDMA Address Control Register (EDACR)

EDACR sets the operating modes and transfer methods. AMS R/W DIRS R/W R R R ARS0 R/W RPTIE R/W ARS1 R/W Bit Bit Name Initial Value R/W R R SAT1 R/W SAT0 R/W R DAT0 R/W R DAT1 R/W Bit Bit Name Initial Value R/W SARIE R/W R R SARA4 R/W SARA3 R/W SARA0 R/W SARA2 R/W SARA1 R/W Bit Bit Name Initial Value R/W DARIE R/W R R DARA4 R/W DARA3 R/W DARA0 R/W DARA2 R/W DARA1 R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial value R/W Description Selects single address mode or dual address mode. When single address mode is selected, EDACK pin is valid due to the EDACKE bit setting in EDMDR. 0: Dual address mode 1: Single address mode Specifies the data transfer direction in single address mode. In dual address mode, the specification by this bit is ignored. In cluster transfer mode, the internal cluster buffer will be the source or destination in place of the external device with DACK. 0: EDSAR transferred as a source address 1: EDDAR transferred as a destination address

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 482 of 1438 REJ09B0365-0200 Bit Bit Name Initial value R/W Description 29 to 27  All 0 R Reserved They are always read as 0 and cannot be modified. Enables or disables a repeat size end interrupt request. When this bit is set to 1 and the next transfer source is generated at the end of a repeat-size transfer in repeat transfer mode, the DTE bit in EDMDR is cleared to 0. At the same time, the ESIF bit in EDMDR is set to 1 to indicate that a repeat size end interrupt is requested. Even if the repeat area is not specified (ARS1, ARS0 = B'10), the repeat size end interrupt can be requested at the end of a repeat-size transfer. When this bit is set to 1 and the next transfer source is generated at the end of a block- or cluster-size transfer in block transfer or cluster transfer mode, the DTE bit in EDMDR is cleared to 0. At the same time, the ESIF bit in EDMDR is set to 1 to indicate that the repeat size end interrupt is requested. 0: Repeat size end interrupt request disabled 1: Repeat size end interrupt request enabled ARS1 ARS0 R/W R/W Area Select 1 and 0 Select the block area or repeat area in block transfer, repeat transfer or cluster transfer mode. 00: Block area/repeat area on the source address side 01: Block area/repeat area on the destination address side 10: Block area/repeat area not specified 11: Setting prohibited 23, 22  All 0 R Reserved They are always read as 0 and cannot be modified.

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 483 of 1438 REJ09B0365-0200 Bit Bit Name Initial value R/W Description SAT1 SAT0 R/W R/W Source Address Update Mode 1 and 0 These bits specify incrementing/decrementing of the transfer source address (EDSAR). When the transfer source is not specified in EDSAR in single address mode, the specification by these bits is ignored. 00: Fixed 01: Offset added 10: Incremented (+1, +2, or +4 according to the data access size) 11: Decremented (−1, −2, or −4 according to the data access size) 19, 18  All 0 R Reserved They are always read as 0 and cannot be modified. DAT1 DAT0 R/W R/W Destination Address Update Mode 1 and 0 These bits specify incrementing/decrementing of the transfer destination address (EDDAR). When the transfer source is not specified in EDDAR in single address mode, the specification by these bits is ignored. 00: Fixed 01: Offset added 10: Incremented (+1, +2, or +4 according to the data access size) 11: Decremented (−1, −2, or −4 according to the data access size)

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 484 of 1438 REJ09B0365-0200 Bit Bit Name Initial value R/W Description

15 SARIE 0 R/W Source Address Extended Repeat Area Overflow

Enables or disables the source address extended repeat area overflow interrupt request. When this bit is set to 1, in the event of source address extended repeat area overflow, the DTE bit is cleared to 0 in EDMDR. At the same time, the ESIF bit is set to 1 in EDMDR to indicate that the source address extended repeat area overflow interrupt is requested. When used together with block transfer mode, an interrupt is requested at the end of a block-size transfer. If the DTE bit is set to 1 in EDMDR for the channel on which transfer is terminated by an interrupt, transfer can be resumed from the state in which it ended. If a source address extended repeat area is not designated, the specification by this bit is ignored. 0: Source address extended repeat area overflow interrupt request disabled 1: Source address extended repeat area overflow interrupt request enabled 14, 13  All 0 R Reserved They are always read as 0 and cannot be modified. SARA4 SARA3 SARA2 SARA1 SARA0 R/W R/W R/W R/W R/W Source Address Extended Repeat Area These bits specify the source address (EDSAR) extended repeat area. The extended repeat area function updates the specified lower address bits, leaving the remaining upper address bits always the same. An extended repeat area size of 4 bytes to 128 Mbytes can be specified. The setting interval is a power-of-two number of bytes. When extended repeat area overflow results from incrementing or decrementing an address, the lower address is the start address of the extended repeat area in the case of address incrementing, or the last address of the extended repeat area in the case of address decrementing. If SARIE bit is set to 1, an interrupt can be requested when an extended repeat area overflow occurs. Table 11.3 shows the settings and ranges of the extended repeat area.

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 485 of 1438 REJ09B0365-0200 Bit Bit Name Initial value R/W Description Enables or disables a destination address extended repeat area overflow interrupt request. When this bit is set to 1, in the event of destination address extended repeat area overflow, the DTE bit in EDMDR is cleared to 0. At the same time, the ESIF bit in EDMDR is set to 1 to indicate that a destination address extended repeat area overflow interrupt is requested. When used together with block transfer mode, an interrupt is requested at the end of a block-size transfer. If DTE bit is set to 1 in EDMDR for the channel on which transfer is terminated by an interrupt, transfer can be resumed from the state in which it ended. If a destination address extended repeat area is not designated, the specification by this bit is ignored. 0: Destination address extended repeat area overflow interrupt request disabled 1: Destination address extended repeat area overflow interrupt request enabled 6, 5  All 0 R Reserved They are always read as 0 and cannot be modified. DARA4 DARA3 DARA2 DARA1 DARA0 R/W R/W R/W R/W R/W Destination Address Extended Repeat Area These bits specify the destination address (EDDAR) extended repeat area. The extended repeat area function updates the specified lower address bits, leaving the remaining upper address bits always the same. An extended repeat area size of 4 bytes to 128 Mbytes can be specified. The setting interval is a power-of-two number of bytes. When extended repeat area overflow results from incrementing or decrementing an address, the lower address is the start address of the extended repeat area in the case of address incrementing, or the last address of the extended repeat area in the case of address decrementing. If the DARIE bit is set to 1, an interrupt can be requested when an extended repeat area overflow occurs. Table 11.3 shows the settings and ranges of the extended repeat area.

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 486 of 1438 REJ09B0365-0200 Table 11.3 Settings and Ranges of Extended Repeat Area Value of SARA4 to SARA0/ DARA4 to DARA0 Range of Extended Repeat Area

00000 Not designated as extended repeat area

00001 Lower 1 bit (2-byte area) designated as extended repeat area

00010 Lower 2 bit (4-byte area) designated as extended repeat area

00011 Lower 3 bit (8-byte area) designated as extended repeat area

00100 Lower 4 bit (16-byte area) designated as extended repeat area

00101 Lower 5 bit (32-byte area) designated as extended repeat area

00110 Lower 6 bit (64-byte area) designated as extended repeat area

00111 Lower 7 bit (128-byte area) designated as extended repeat area

01000 Lower 8 bit (256-byte area) designated as extended repeat area

01001 Lower 9 bit (512-byte area) designated as extended repeat area

01010 Lower 10 bit (1-kbyte area) designated as extended repeat area

01011 Lower 11 bit (2-kbyte area) designated as extended repeat area

01100 Lower 12 bit (4-kbyte area) designated as extended repeat area

01101 Lower 13 bit (8-kbyte area) designated as extended repeat area

01110 Lower 14 bit (16-kbyte area) de signated as extended repeat area

01111 Lower 15 bit (32-kbyte area) de signated as extended repeat area

10000 Lower 16 bit (64-kbyte area) de signated as extended repeat area

10001 Lower 17 bit (128-kbyte area) designated as extended repeat area

10010 Lower 18 bit (256-kbyte area) designated as extended repeat area

10011 Lower 19 bit (512-kbyte area) designated as extended repeat area

10100 Lower 20 bit (1-Mbyte area) de signated as extended repeat area

10101 Lower 21 bit (2-Mbyte area) de signated as extended repeat area

10110 Lower 22 bit (4-Mbyte area) de signated as extended repeat area

10111 Lower 23 bit (8-Mbyte area) de signated as extended repeat area

11000 Lower 24 bit (16-Mbyte area) designated as extended repeat area

11001 Lower 25 bit (32-Mbyte area) designated as extended repeat area

11010 Lower 26 bit (64-Mbyte area) designated as extended repeat area

11011 Lower 27 bit (128-Mbyte area) designated as extended repeat area

[Legend] X: Don't care

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11.3.8 Cluster Buffer Registers 0 to 7 (CLSBR0 to CLSBR7)

CLSBR0 to CLSBR7 are 32-bit readable/writable registers that store the transfer data. The transfer data is stored in order from CLSBR0 to CLSBR7 in cluster transfer mode. The data stored in cluster transfer mode or by the CPU write operation is held until the next cluster transfer or CPU write operation is performed. When reading the data stored in cluster transfer mode by the CPU, check the completion of cluster transfer and then perform only a cluster-size read specified for the cluster transfer. Data with another size is undefined. In cluster transfer mode, the same CLSBR is used for all channels. When the CPU write operation to CLSBR conflicts with cluster transfer, the contents of transferred data are not guaranteed. When cluster transfer read/write address mode is specified and if another channel is set for cluster transfer, the transferred data may be overwritten. Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Bit Bit Name Initial Value R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Bit Bit Name Initial Value R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Bit Bit Name Initial Value R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Bit Bit Name Initial Value R/W

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11.4 Transfer Modes

11.4.1 Ordinary Modes

The ordinary modes of EXDMAC are summarized in table 11.4. The transfer mode can be set independently for each channel. Table 11.4 Ordinary Modes Address Register Address Mode Transfer Mode Activation Source Common Function Source Destination Dual address mode

• Normal transfer mode
• Repeat transfer mode
• Block transfer mode (Repeat size/ block size = 1 to 65,536 bytes/ word/longword)
• Auto-request (activated by the CPU)
• External request
• Total transfer size: 1 to 4 Gbytes, or no specification
• Offset addition
• Extended repeat area function EDSAR EDDAR Single address mode
• Direct data transfer to/from external devices using EDACK pin instead of source or destination address register
• Above transfer mode can be specified in addition to address register setting
• One transfer possible in one bus cycle (Transfer mode variations are the same as in dual address mode.) EDSAR/ EDACK EDACK/ EDDAR When the activation source is an auto-request, cycle steal mode or burst mode can be selected. When the total transfer size is not specified (EDTCR = H'00000000), the transfer counter is halted and the transfer count is not restricted, allowing continuous transfer.

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11.4.2 Cluster Transfer Modes

Table 11.5 shows cluster transfer modes. Cluster transfer mode can be set independently for each channel. The cluster buffer is common to all channels. Table 11.5 Cluster Transfer Mode Address Mode Activation Source Common Function Transfer Source Cluster Buffer Function Transfer Destination Cluster transfer Dual address mode EDSAR Read from the transfer source and written to the transfer destination EDDAR Cluster transfer Read address mode (DIRS = 0) EDSAR Read from the transfer source Cluster transfer Write address mode (DIRS = 1)

• Auto-request (activated by the CPU)
• External request
• Cluster size One access size (byte/word/longword) to 32 bytes
• Total transfer size 1 to 4 Gbytes, or no specification
• Offset addition
• Extended repeat area function  Written to the transfer destination EDDAR In cluster transfer mode, the specified cluster size is transferred in response to a single transfer request. The cluster size can be from one access size (byte, word, or longword) to 32 bytes. Within a cluster, a cluster-size transfer is performed in burst transfer mode. With a cluster-size access in cluster transfer mode (dual address mode), block transfer mode (dual address mode) is used. With auto-requests, cycle steal mode is set.

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11.5 Mode Operation

11.5.1 Address Modes

(1) Dual Address Mode In dual address mode, the transfer source address is set in EDSAR, and the transfer destination address is set in EDDAR. One transfer operation is executed in two bus cycles. (When the data bus width is smaller than the data access size or when the address to be accessed is not at the data boundary of the data access size, the bus cycle is divided, resulting more than two bus cycles.) In a transfer operation, the data on the transfer source address is read in the first bus cycle, and is written to the transfer destination address in the next bus cycle. These consecutive read and write cycles are indivisible: another bus cycle (external access by another bus master, refresh cycle, or external bus release cycle) does not occur between these two cycles. ETEND pin output can be enabled or disabled by means of the ETENDE bit in EDMDR. ETEND is output for two consecutive bus cycles. When an idle cycle is inserted before the bus cycle, the ETEND signal is also output in the idle cycle. The EDACK signal is not output. Figure 11.2 shows an example of the timing in dual address mode and figure 11.3 shows the dual address mode operation. Address bus Bφ RD WR ETEND EXDMA read cycle EXDMA write cycle EDSAR EDDAR Figure 11.2 Example of Timing in Dual Address Mode

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 493 of 1438 REJ09B0365-0200 Address T Address B EDACKTransfer Figure 11.6 Single Address Mode Operation

11.5.2 Transfer Modes

(1) Normal Transfer Mode In normal transfer mode, transfer of one data access size unit is processed in response to one transfer request. The total transfer size of up to 4 Gbytes can be set by EDTCR. EDBSR is invalid in normal transfer mode. The ETEND signal is output only for the last EXDMA transfer. The EDRAK signal is output each time a transfer request is accepted and transfer processing is started. Figure 11.7 shows examples of transfer timing in normal transfer mode and figure 11.8 shows the normal transfer mode operation in dual address mode. Read Write Read Write EXDMA transfer cycle Last EXDMA transfer cycle Bus cycle Transfer conditions: Dual address mode, auto-request mode Transfer conditions: Single address mode, external request mode ETEND EDREQ EDACK EXDMA EXDMABus cycle EDRAK Figure 11.7 Examples of Timing in Normal Transfer Mode

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 495 of 1438 REJ09B0365-0200 TransferAddress TA Address TB Address BB Address BA Operation with the repeat area specified on the source address side Total transfer size (EDTCR) Repeat size (BKSZH × data access size) Figure 11.9 Repeat Transfer Mode Operation (3) Block Transfer Mode In block transfer mode, transfer of one block size unit is processed in response to one transfer request. The total transfer size of up to 4 Gbytes can be set by EDTCR. The block size of up to 64 kbytes × data access size can be set by EDBSR. A transfer request from another channel is held pending during one block transfer. When one- block transfer is completed, the bus mastership is released for another bus master. A block area can be specified by the ARS1 or ARS0 bit in EDACR on the source or destination address side. The address specified for the block area is restored to the transfer start address each time one-block transfer completes. When no repeat area is specified on the source and destination address sides, the address is not restored to the transfer start address and the operation proceeds to the next sequence. A repeat size end interrupt can be generated. The ETEND signal is output for each block transfer in the EXDMA transfer cycle in which the block ends. The EDRAK signal is output once for one transfer request (for transfer of one block). Caution is required when setting the extended repeat area overflow interrupt in block transfer mode. For details, see section 11.5.5, Extended Repeat Area Function.

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 497 of 1438 REJ09B0365-0200 TransferAddress TA Address BA Address TB Address BB Nth block Second block First block Nth block Second block First block BKSZH × data access size Total transfer size (EDTCR) Figure 11.12 Block Transfer Mode Operation in Dual Address Mode (without Block Area Specified)

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11.5.3 Activa tion Sources

The EXDMAC is activated by an auto request or an external request. This activation source is selected by the DTF1 or DTF0 bit in EDMDR. (1) Activation by Auto-Request The transfer request signal is automatically generated in EXDMAC with auto-request activation when no transfer request signal is generated from external or peripheral modules, incase of transfer among memory or between memory and peripheral modules that cannot generate the transfer request signal. The transfer starts when the DTE bit in EDMDR is set to 1 with auto- request activation. The bus mode can be selected from cycle steal mode and burst mode with auto- request activation. (2) Activation by External Request Transfer is started by the transfer request signal (EDREQ) from the external device for activation by an external request. When the EXDMA transfer is enabled (DTE = 1), the EXDMA transfer starts by EDREQ input. The transfer request signal is accepted by the EDREQ pin. The EDREQS bit in EDMDR selects whether the EDREQ is detected by falling edge sensing or low level sensing. When the EDRAKE bit in EDMDR is set to 1, the signal notifying transfer request acceptance is output from the EDRAK pin. The EDRAK signal is accepted for one external request and is output when transfer processing starts. When specifying an external request as an activation source, set the DDR bit to 0 and the ICR bit to 1 on the corresponding pin in advance. For details, see section 13, I/O Ports.

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11.5.4 Bus Mode

There are two bus modes: cycle steal mode and burst mode. For auto-request activation, either cycle steal mode or burst mode can be selected by the DTF0 bit in EDMDR. When the activation source is an external request, cycle steal mode is used. (1) Cycle Steal Mode In cycle steal mode, the EXDMAC releases the bus mastership at the end of each transfer of a transfer unit (byte, word, longword, one block size, or one cluster size). If there is a subsequent transfer request, the EXDMAC takes back the bus mastership, performs another transfer-unit transfer, and then releases the bus mastership again at the end of the transfer. This procedure is repeated until the transfer end condition is satisfied. If a transfer request occurs in another channel during EXDMA transfer, the bus mastership is temporarily released for another bus master, then transfer is performed on the channel for which the transfer request was issued. For details on the operation when there are transfer requests for a number of channels, see section 11.5.8, Channel Priority Order. Figure 11.13 shows an example of the timing in cycle steal mode. The transfer conditions are as follows:

• Address mode: Single address mode
• Sampling method on the EDREQ pin: Low level sensing
• CPU internal bus master is operating in external space CPU CPU CPUEXDMAC CPUEXDMAC EDREQ EDRAK Bus cycle Bus mastership returned temporarily to CPU Figure 11.13 Example of Timing in Cycle Steal Mode

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 500 of 1438 REJ09B0365-0200 (2) Burst Mode In burst mode, once the EXDMAC acquires the bus mastership, it continues transferring data, without releasing the bus mastership, until the transfer end condition is satisfied. In burst mode, once transfer is started it is not interrupted even if there is a transfer request for another channel with higher priority. When the burst mode channel finishes its transfer, it releases the bus mastership in the next cycle in the same way as in cycle steal mode. However, when the EBCCS bit in BCR2 of the bus controller is set to 1, the EXDMAC can temporarily release the bus mastership for another bus master when an external access request is generated from another bus master. In block transfer mode and cluster transfer mode, the setting of burst mode is invalid (one-block or one-cluster transfer is processed in the same way as in burst mode). The EXDMAC always operates in cycle steal mode. When the DTE bit is cleared to 0 in EDMDR, EXDMA transfer is halted. However, EXDMA transfer is executed for all transfer requests generated within the EXDMAC until the DTE bit is cleared to 0. If a transfer size error interrupt, a repeat size end interrupt, or extended repeat area overflow interrupt is generated, the DTE bit is cleared to 0 and transfer is terminated. Figure 11.14 shows an example of the timing in burst mode. CPU CPU CPU CPUEXDMAC EXDMAC EXDMACBus cycle CPU cycle not generated Figure 11.14 Example of Timing in Burst Mode

11.5.5 Extended Repeat Area Function

The EXDMAC has a function for designating an extended repeat area for source addresses and/or destination addresses. When an extended repeat area is designated, the address register values repeat within the range specified as the extended repeat area. Normally, when a ring buffer is involved in a transfer, an operation is required to restore the address register value to the buffer start address each time the address register value becomes the last address in the buffer (i.e. when ring buffer address overflow occurs). However, if the extended repeat area function is used, the operation that restores the address register value to the buffer start address is processed automatically within the EXDMAC. The extended repeat area function can be set independently for the source address register (EDSAR) and the destination address register (EDDAR).

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 503 of 1438 REJ09B0365-0200

11.5.6 Address Update Function Using Offset

There are the following update methods for transfer destination and source addresses: Fixed, increment/decrement by 1, 2 or 4, and offset addition. With the offset addition method, the offset specified by the offset register (EDOFR) is added each time the EXDMAC performs a data- access-size transfer. This function allows the mid-addresses being skipped during data transfer. Figure 11.17 shows the address update methods. + Offset ±1, 2, or 4 Address not updated Value, that corresponds to data access size, incremented, decremented to/from the address (Successive addresses) (a) Fixed (b) Increment/decrement by 1, 2 or 4 (c) Offset addition External memoryExternal memory External memory Offset value added to the address (Insuccessive addresses) Figure 11.17 Address Update Method For the fixed method (a), the same address is always indicated without the transfer destination or source address being updated. For the method of increment/decrement by 1, 2 or 4 (b), the value corresponding to the data access size is incremented or decremented to or from the transfer destination or source address each time the data is transferred. A byte, word, or longword can be specified for the data access size. The value used for increment or decrement of an address is 1 for a byte-size , 2 for a word-size , and 4 for a longword-size transfer. This function allows continuous address transfer of EXDMAC.

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 507 of 1438 REJ09B0365-0200 (3) Offset subtraction specification To set a negative value in EDOFR, specify a twos complement as an offset value. A twos complement is derived by the following expression: [Twos complement expression for negative offset value] = −[offset value] + 1 (−: bit reverse) Example: Twos complement expression of H'0001FFFF = H'FFFE0000 + H'00000001 = H'FFFE0001 A twos complement can be derived by the NEG.L instruction of the CPU.

11.5.7 Registers during EXDMA Transfer Operation

EXDMAC register values are updated as EXDMA transfer processing is performed. The updated values depend on various settings and the transfer status. The following registers and bits are updated: EDSAR, EDDAR, EDTCR, bits BKSZH and BKSZ in EDBSR, and bits DTE, ACT, ERRF, ESIF and DTIF in EDMDR. (1) EXDMA Source Address Register (EDSAR) When the EDSAR address is accessed as the transfer source, the EDSAR value is output, and then EDSAR is updated with the address to be accessed next. Bits SAT1 and SAT0 in EDACR specify incrementing or decrementing. The address is fixed when SAT1 and SAT0 = B′00, incremented by offset register value when SAT1 and SAT0 = B′01, incremented when SAT1 and SAT0 = B′10, and decremented when SAT1 and SAT0 = B′11. (The increment or decrement value is determined by the data access size.) The DTSZ1 and DTSZ0 bits in EDMDR set the data access size. When DTSZ1 and DTSZ0 = B′00, the data is byte-size and the address is incremented or decremented by 1. When DTSZ1 and DTSZ0 = B′01, the data is word-size and the address is incremented or decremented by 2. When DTSZ1and DTSZ0 = B′10, the data is longword-size and the address is incremented or decremented by 4. When a word-size or longword-size is specified but the source address is not at the word or longword boundary, the data is divided into bytes or words for reading. When a word or longword is divided for reading, the address is incremented or decremented by 1 or 2 according to an actual byte-or word-size read. After a word-size or longword-size read, the address is incremented or decremented to or from the read start address according to the setting of SAT1 and SAT0.

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 508 of 1438 REJ09B0365-0200 When a block area (repeat area) is set for the source address in block transfer mode (or repeat transfer mode), the source address is restored to the transfer start address at the end of block-size (repeat-size) transfer and is not affected by address updating. When an extended repeat area is set for the source address, the operation conforms to that setting. The upper addresses set for the extended repeat area is fixed, and is not affected by address updating. When EDSAR is read during a transfer operation, a longword access must be used. During a transfer operation, EDSAR may be updated without regard to accesses from the CPU, and the correct values may not be read if the upper and lower words are read separately. Do not write to EDSAR for a channel on which a transfer operation is in progress. (2) EXDMA Destination Address Register (EDDAR) When the EDDAR address is accessed as the transfer destination, the EDDAR value is output, and then EDDAR is updated with the address to be accessed next. Bits DAT1 and DAT0 in EDACR specify incrementing or decrementing. The address is fixed when DAT1 and DAT0 = B′00, incremented by offset register value when DAT1 and DAT0 = B′01, incremented when DAT1 and DAT0 = B′10, and decremented when DAT1 and DAT0 = B′11. (The increment or decrement value is determined by the data access size.) The DTSZ1 and DTSZ0 bits in EDMDR set the data access size. When DTSZ1 and DTSZ0 = B′00, the data is byte-size and the address is incremented or decremented by 1. When DTSZ1 and DTSZ0 = B′01, the data is word-size and the address is incremented or decremented by 2. When DTSZ1 and DTSZ0 = B′10, the data is longword-size and the address is incremented or decremented by 4. When a word-size or longword-size is specified but the destination address is not at the word or longword boundary, the data is divided into bytes or words for writing. When a word or a longword is divided for writing, the address is incremented or decremented by 1 or 2 according to an actual byte- or word-size written. After a word-size or longword-size write, the address is incremented or decremented to or from the write start address according to the setting of SAT1 and SAT0. When a block area (repeat area) is set for the destination address in block transfer mode (or repeat transfer mode), the destination address is restored to the transfer start address at the end of block- size (repeat-size) transfer and is not affected by address updating. When an extended repeat area is set for the destination address, the operation conforms to that setting. The upper addresses set for the extended repeat area is fixed, and is not affected by address updating.

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 509 of 1438 REJ09B0365-0200 When EDDAR is read during a transfer operation, a longword access must be used. During a transfer operation, EDDAR may be updated without regard to accesses from the CPU, and the correct values may not be read if the upper and lower words are read separately. Do not write to EDDAR for a channel on which a transfer operation is in progress. (3) EXDMA Transfer Count Register (EDTCR) When an EXDMA transfer is performed, the value in EDTCR is decremented by the number of bytes transferred. When a byte is transferred, the value is decremented by 1; when a word is transferred, the value is decremented by 2; when a longword is transferred, the value is decremented by 4. However, when the EDTCR value is 0, transfers are not counted and the EDTCR value does not change. All of the bits of EDTCR may change, so when EDTCR is read by the CPU during EXDMA transfer, a longword access must be used. During a transfer operation, EDTCR may be updated without regard to accesses from the CPU, and the correct values may not be read if the upper and lower words are read separately. Do not write to EDTCR for a channel on which a transfer operation is in progress. If there is conflict between an address update associated with EXDMA transfer and a write by the CPU, the CPU write has priority. In the event of conflict between an EDTCR update from 1, 2, or 4 to 0 and a write (of a nonzero value) by the CPU, the CPU write value has priority as the EDTCR value, but transfer is terminated. (4) EXDMA Block Size Register (EDBSR) EDBSR is valid in block transfer or repeat transfer mode. EDBSR31 and EDBSR16 are used as BKSZH and EDBSR15 and EDBSR0 for BKSZ. The 16 bits of BKSZH holds a block size and repeat size and their values do not change. The 16 bits of BKSZ functions as a block size or repeat size counter, the value of which is decremented by 1 when one data transfer is performed. When the BKSZ value is determined as 0 during EXDMA transfer, the EXDMAC does not store 0 in BKSZ and stores the BKSZH value. The upper 16 bits of EDBSR is never updated, allowing a word-size access. Do not write to EDBSR for a channel on which a transfer operation is in progress.

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 511 of 1438 REJ09B0365-0200 (6) ACT bit in EDMDR The ACT bit in EDMDR indicates whether the EXDMAC is in standby or active state. When DTE = 0 and DTE = 1 (transfer request wait status) are specified, the ACT bit is set to 0. In another case (EXDMAC in the active state), the ACT bit is set to 1. The ACT bit is held to 1 during EXDMA transfer even if 0 is written to the DTE bit to halt transfer. In block transfer mode, a block-size transfer is not halted even if 0 is written to the DTE bit to halt transfer. The ACT bit is held to 1 until a block-size transfer completes after 0 is written to the DTE bit. In burst mode, transfer is halted after up to three times of EXDMA transfers are performed since the bus cycle in which 0 is written to the DTE bit has been processed. The ACT bit is held to 1 between termination of the last EXDMA cycle and 0-write in the DTE bit. (7) ERRF bit in EDMDR This bit specifies termination of transfer by EXDMAC clearing the DTE bit to 0 for all channels if an address error or NMI interrupt is generated. The EXDMAC also sets 1 to the ERRF bit of EDMDR_0 regardless of the EXDMAC operation to indicate that an address error or NMI interrupt is generated. However, when an address error or an NMI interrupt has been generated in EXDMAC module stop mode, the ERRF bit is not set to 1. (8) ESIF bit in EDMDR The ESIF bit in EDMDR is set to 1 when a transfer size interrupt, repeat size end interrupt, or an extended repeat area overflow interrupt is requested. When the ESIF bit is set to 1 and the ESIE bit in EDMDR is set to 1, a transfer escape interrupt is requested to the CPU or DTC. The timing that the ESIF bit is set to 1 is when the EXDMA transfer bus cycle (the source of an interrupt request) terminates, the ACT bit in EDMDR is set to 0, and transfer is terminated. When the DTE bit is set to 1 to resume transfer during interrupt processing, the ESIF bit is automatically cleared to 0 to cancel the interrupt request. For details on interrupts, see section 11.9, Interrupt Sources.

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 512 of 1438 REJ09B0365-0200 (9) DTIF bit in EDMDR The DTIF bit in EDMDR is set to 1 after the data of total transfer size is transferred completely by EXDMA transfer. When the DTIF bit is set to 1 and the DTIE bit in EDMDR is set to 1, a transfer end interrupt by the transfer counter is requested to the CPU or DTC. The timing that the DTIF bit is set to 1 is when the EXDMA transfer bus cycle is terminated, the ACT bit in EDMDR is set to 0, and the transfer is terminated. When the DTE bit is set to 1 to resume transfer during interrupt processing, the DTIF bit is automatically cleared to 0 to cancel the interrupt request. For details on interrupts, see section 11.9, Interrupt Sources.

11.5.8 Channel Priority Order

The priority order of the EXDMAC channels is: channel 0 > channel 1 > channel 2 > channel 3. Table 11.6 shows the EXDMAC channel priority order. Table 11.6 EXDMAC Ch annel Priority Order Channel Channel Priority Channel 0 Channel 1 Channel 2 Channel 3 High Low If transfer requests occur simultaneously for a number of channels, the highest-priority channel according to the priority order is selected for transfer. Transfer starts after the channel in progress releases the bus. If a bus request is issued from another bus master other than EXDMAC during a transfer operation, another bus master cycle is initiated. Channels are not switched during burst transfer, a block-size transfer in block transfer mode or a cluster-size transfer in cluster transfer mode. Figure 11.22 shows an example of the transfer timing when transfer requests occur simultaneously for channels 0, 1, and 2.

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 513 of 1438 REJ09B0365-0200 Channel 0 Channel 1 Channel 2 Channel 0 transfer Channel 1 transfer Channel 2 transfer Channel 0 Channel 1 Channel 2Idle Idle Request cleared Request cleared Request cleared Request held Request held Request held Selected SelectedNot selected Address bus Channel 0 Channel 1 Channel 2 Bφ EXDMAC control Figure 11.22 Example of Channel Priority Timing

11.5.9 Basic Bus Cycles

An example of the basic bus cycle timing is shown in figure 11.23. In this example, word-size transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the bus mastership is transferred from the CPU to the EXDMAC, a source address read and destination address write are performed. The bus is not released in response to another bus request, etc., between these read and write operations. As like CPU cycles, EXDMAC cycles conform to the bus controller settings. CPU cycle EXDMAC cycle (one word transfer) CPU cycle Address bus Bφ T1 T2 T1 T2 T3 T1 T2 T3 Source address Destination address RD LHWR LLWR High Figure 11.23 Example of EXDMA Transfer Bus Timing

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11.5.10 Bus Cycles in Dual Address Mode

(1) Normal Transfer Mode (Cycle Steal Mode) In cycle steal mode, the bus is released after one byte, word, or longword has been transferred. While the bus is released, one CPU, DMAC, or DTC bus cycle is initiated. Figure 11.24 shows an example of transfer when ETEND output is enabled, and word-size, normal transfer mode (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. EXDMA read EXDMA write Address bus EXDMA read EXDMA write EXDMA read EXDMA write Bφ RD LHWR, LLWR ETEND Bus release Last transfer cycleBus release Bus release Bus release Figure 11.24 Example of Normal Transfer Mode (Cycle Steal Mode) Transfer Figures 10.25 and 10.26 show examples of transfer when ETEND output is enabled, and longword-size, normal transfer mode (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. In figure 11.25, the transfer source (SAR) address is not at a longword boundary and the transfer destination (DAR) address is at the longword boundary. In figure 11.26, the transfer source (SAR) address is at the longword boundary and the transfer destination (DAR) address is not at the longword boundary.

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11.5.11 Bus Cycles in Single Address Mode

(1) Single Address Mode (Read in Cycle Steal Mode) In single address mode, the bus is released after one byte, word, or longword has been transferred in response to one transfer request. While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated. Figure 11.34 shows an example of transfer when ETEND output is enabled, and byte-size, single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. Bus released Bus release Bus release EXDMA read EXDMA read EXDMA read EXDMA read Bφ Address bus Bus release Bus release Last transfer cycle RD ETEND EDACK Figure 11.34 Example of Single Address Mode (Byte Read) Transfer

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11.5.12 Operation Timing in Each Mode

This section describes examples of operation timing in each mode. The CPU external bus cycle is shown as an example of conflict with another bus master. (1) Auto-Request/Normal Transfer Mode/Cycle Steal Mode With auto-request (in cycle steal mode), when the DTE bit is set to 1 in EDMDR, an EXDMA transfer cycle is started a minimum of three cycles later. If there is a transfer request for another channel of higher priority, the transfer request by the original channel is held pending, and transfer is performed on the higher-priority channel from the next transfer. Transfer on the original channel is resumed on completion of the higher-priority channel transfer. Figures 10.39 and 10.40 show operation timing examples for various conditions. 3 cycles Bus release EXDMA write EXDMA read EXDMA write EXDMA read 0 1 0 Bφ Bus cycle CPU operation ETEND DTE bit 3 cycles EXDMA write EXDMA read Bus release Bus release Bus release DTE 1 write Internal bus space cycles 3 cycles Last transfer cycle Figure 11.39 Auto-Request/Normal Transfer Mode/Cycle Steal Mode (No Conflict/Dual Address Mode)

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 533 of 1438 REJ09B0365-0200 (4) External Request/Block Transfer Mode/Cycle Steal Mode In block transfer mode, transfer of one block is performed continuously in the same way as in burst mode. The timing of the start of the next block transfer is the same as in normal transfer mode. If a transfer request is generated for another channel, an EXDMA cycle for the other channel is generated before the next block transfer. The EDREQ pin sensing timing is different for low level sensing and falling edge sensing. The same applies to transfer request acceptance and transfer start timing. Figures 10.48 to 10.52 show operation timing examples for various conditions.

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 534 of 1438 REJ09B0365-0200 Bus release Bus release EXDMA read EXDMA write EXDMA read EXDMA write EXDMA read EXDMA write Bus release EXDMA read EXDMA write Repeated EXDMA read EXDMA write Repeated Last block 3 cycles Last transfer cycleEnd of block Bφ EDREQ EDRAK Bus cycle ETEND DTE bit 1 0 One block size transfer period Figure 11.48 External Request/Block Transfer Mode/Cycle Steal Mode (No Conflict/Dual Address Mode/Low Level Sensing)

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 535 of 1438 REJ09B0365-0200 Bus release Bus releaseEXDMA single transfer cycle EXDMA single transfer cycle EXDMA single transfer cycle EXDMA single transfer cycle EXDMA single transfer cycle Bus release Last block 3 cycles Last transfer cycleEnd of block One block size transfer period Bφ EDREQ EDRAK Bus cycle EDACK ETEND Repeated Repeated Figure 11.49 External Request/Block Transfer Mode/Cycle Steal Mode (No Conflict/Single Address Mode/Falling Edge Sensing)

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 536 of 1438 REJ09B0365-0200 Bφ EDREQ EDRAK Bus cycle ETEND EDACK External space External space CPU cycle CPU operation CPU cycleEXDMA single transfer cycle EXDMA single transfer cycle EXDMA single transfer cycle EXDMA single transfer cycleCPU cycle Repeated Repeated CPU cycle External space External space One block size transfer period One block size transfer period End of block Bus cycle Last block Figure 11.50 External Request/Block Transfer Mode/Cycle Steal Mode (CPU Cycles/Single Address Mode/Low Level Sensing)

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 537 of 1438 REJ09B0365-0200 EDREQ EDRAK EDREQ of another channel EDRAK of another channel Bus cycle ETEND EXDMA read EXDMA write EXDMA read EXDMA write EXDMA read EXDMA write EXDMA read EXDMA writeBus release EXDMA cycle of another channel Bφ Repeated Repeated One block size transfer period One block size transfer period End of block Last block Figure 11.51 External Request/Block Transfer Mode/Cycle Steal Mode (Conflict with Another Channel/Dual Address Mode/Low Level Sensing)

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 538 of 1438 REJ09B0365-0200 Bus cycle Last block Bφ EDREQ EDRAK Bus cycle ETEND EDACK Externalspace Externalspace Externalspace Externalspace CPU cycle CPU cycle CPU operation CPU cycle CPU cycleEXDMA single transfer cycle EXDMA single transfer cycle EXDMA single transfer cycle EXDMA single transfer cycle Repeated Repeated One block size transfer period One block size transfer period End of block Figure 11.52 External Request/Block Transfer Mode/Cycle Steal Mode (CPU Cycles/EBCCS = 1/Single Address Mode/Low Level Sensing)

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11.6 Operation in Cluster Transfer Mode

In cluster transfer mode, transfer is performed by the consecutive read and write operations of 1 to 32 bytes using the cluster buffer. A part of the cluster transfer mode function differs from the ordinary transfer mode functions (normal transfer, repeat transfer, and block transfer modes).

11.6.1 Address Mode

(1) Cluster Transfer Dual Address Mode (AMS = 0) In this mode, both the transfer source and destination addresses are specified for transfer in the EXDMAC internal registers. The transfer source address is set in the source address register (EDSAR), and the transfer destination address is set in the destination address register (EDDAR). The transfer is processed by performing the consecutive read of a cluster-size from the transfer source address and then the consecutive write of that data to the transfer destination address. One data access size to 32 bytes can be specified as a cluster size. When one data access size is specified as a cluster size, block transfer mode (dual address mode) is used. The cycles in a cluster-size transfer are indivisible: another bus cycle (external access by another bus master, refresh cycle, or external bus release cycle) does not occur in a cluster-size transfer. ETEND pin output can be enabled or disabled by means of the ETENDE bit in EDMDR. ETEND is output for the last write cycle. The EDACK signal is not output. Figure 11.53 shows the data flow in the cluster transfer mode (dual address mode), figure 11.54 shows an example of the timing in cluster transfer dual address mode, and figure 11.55 shows the cluster transfer dual address mode operation. Consecutive read Consecutive write LSI Cluster buffer EDSAR access Read Read Read Read One cluster size One cluster size EDDAR acces Write Write Write Write Transfer destination: External deviceTransfer source: External memory Figure 11.53 Data Flow in Cluster Transfer Dual Address Mode

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 544 of 1438 REJ09B0365-0200 Address bus Bφ EXDMA write cycle RD WR ETEND EDDAR EDDAR EDDAR High Figure 11.60 Timing in Cluster Transfer Write Address Mode (from Cluster Buffer to External Memory)

11.6.2 Setting of Address Update Mode

The cluster transfer mode transfer is restricted by the address update mode function. There are the following four address update methods: increment, decrement, fixed, and offset addition. When the address increment method is specified and if the specified address is not at the address boundary for the data access size (odd address for a word-size transfer, address beyond the 4n boundary for a longword-size transfer), the bus cycle is divided for transfer until the address becomes at the address boundary. When the address matches the boundary, transfer is processed in units of data access sizes. At the end of transfer, the bus cycle is divided again to transfer the remaining data in cluster transfer mode. With address decrement, fixed, or offset addition method, specify the address, that matches the address boundary for the data access size, in EDSAR and EDDAR. When specifying the address, that is not at the address boundary for the data access size, in EDSAR and EDDAR, fix the lower bit to 0 (lower one bit for a word-size transfer, and lower two bits for a longword-size transfer) in the address register so that the transfer is processed in units of data access sizes. The block transfer mode must be used for transfer of data by dividing the bus cycle according to the address boundary. When the EDTCR value is smaller than the cluster size, a transfer size error occurs. In this case, when the TSEIE bit in EDMDR is cleared to 0, the cluster transfer mode is switched to the block transfer mode to process the remaining data. With the decrement, fixed, or offset addition method, transfer is performed without fixing the lower bit to 0.

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11.6.3 Caution for Combining with Extended Repeat Area Function

As with the block transfer mode, the address register value must be set in cluster transfer mode, so that the end of the cluster size coincides with the end of the extended repeat area range. When an extended repeat area overflow occurs during a cluster-size transfer in the cluster transfer mode, the extended repeat area overflow interrupt request is held pending until the end of a cluster-size transfer, and transfer overrun will occur.

11.6.4 Bus Cycles in Cluster Transfer Dual Address Mode

(1) Cluster transfer mode In cluster transfer mode, a cluster-size transfer is processed in response to one transfer request. In an example shown in figure 11.61, the ETEND pin output is enabled, and word-size transfer is performed with 4-byte cluster size in cluster transfer mode from the external 16-bit, 2-state access space to the external 16-bit, 2-state access space. EXDMA read EXDMA read EXDMA write EXDMA write Bus release Bφ Address bus LHWR, LLWR ETEND RD Figure 11.61 Example of Cluster Transfer Mode Transfer

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11.6.5 Operation Timing in Cluster Transfer Mode

This section describes examples of operation timing in cluster transfer mode. The CPU external bus cycle is shown as an example of conflict with another bus master. (1) Auto-Request/Cluster Transfer Mode/Cycle Steal Mode With auto-request (in cycle steal mode), when the DTE bit is set to 1 in EDMDR, a continuous EXDMA transfer cycle is started a minimum of three cycles later. If there is a transfer request for another channel of higher priority, the transfer request by the original channel is held pending, and transfer is performed on the higher-priority channel from the next transfer. Transfer on the original channel is resumed on completion of the higher-priority channel transfer. The cluster transfer mode (read address mode and write address mode) can not be used with the cluster transfer mode (dual address mode) among more than one channel at the same time. When using the cluster transfer mode (read address mode and write address mode), do not set the cluster transfer mode for another channel. Figures 10.64 to 10.66 show operation timing examples for various conditions.

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 549 of 1438 REJ09B0365-0200 0 1 0 Bφ ETEND DTE bit Bus cycle 3 cycles 3 cycles 3 cycles Bus release Bus release Bus releaseConsecutive EXDMA read Consecutive EXDMA read Consecutive EXDMA read Consecutive EXDMA write Consecutive EXDMA write Consecutive EXDMA write One cluster transfer One cluster transfer Last cluster cycle CPU operation DTE = 1 write Internal bus space cycles Figure 11.64 Auto-Request/Cluster Transfer Mode/Cycle Steal Mode (No Confict/Dual Address Mode)

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 550 of 1438 REJ09B0365-0200 Bφ ETEND DTE bit 0 1 0 Bus cycle CPU cycle CPU cycle CPU cycle CPU cycleConsecutive EXDMA read Consecutive EXDMA read Consecutive EXDMA read Consecutive EXDMA write Consecutive EXDMA write Consecutive EXDMA write One cluster transfer One cluster transfer Last cluster cycle CPU operation DTE = 1 write External space External space External space External space Figure 11.65 Auto-Request/Cluster Transfer Mode/Cycle Steal Mode (CPU Cycles/Dual Address Mode)

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 551 of 1438 REJ09B0365-0200 Bφ Bus cycle Consecutive EXDMA read Consecutive EXDMA read Consecutive EXDMA read Consecutive EXDMA write Consecutive EXDMA write Consecutive EXDMA writeBus release EXDMA single transfer cycle of another channel with higher priority One cluster transferOne cluster transfer Last cluster transfer Transfer request from another channel (EDREQ) Figure 11.66 Auto-Request/Cluster Transfer Mode/Cycle Steal Mode (Conflict with Another Channel/Dual Address Mode)

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 552 of 1438 REJ09B0365-0200 (2) External Request/Cluster Transfer Mode/Cycle Steal Mode With external requests, a cluster-size transfer is performed continuously. The start timing of the next cluster transfer is the same as for normal transfer mode. If a transfer request is generated for another channel, an EXDMA cycle for the other channel is generated before the next cluster transfer. The cluster transfer mode (read address mode and write address mode) can not be used with the cluster transfer mode (dual address mode) among more than one channel at the same time. When using the cluster transfer mode (read address mode and write address mode), do not set the cluster transfer mode for another channel. The EDREQ pin sensing timing is different for low level sensing and falling edge sensing. The same applies to transfer request acceptance and transfer start timing. Figures 10.67 to 10.69 show operation timing examples for various conditions.

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 553 of 1438 REJ09B0365-0200 EDREQ EDRAK DTE bit ETEND Bus cycle Bφ Bus release Bus releaseEXDMA read EXDMA read EXDMA readEXDMA read EXDMA write EXDMA writeEXDMA write EXDMA write One cluster transfer Consecutive read Consecutive read Consecutive writeConsecutive write 3 cycles Last cluster Figure 11.67 External Request/Cluster Transfer Mode/Cycle Steal Mode (No Conflict/Dual Address Mode/Low Level Sensing)

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 554 of 1438 REJ09B0365-0200 EDREQ EDRAK Bus cycle CPU cycle EXDMA read EXDMA write One cluster size transfer period CPU cycle CPU cycle CPU cycleEXDMA read EXDMA write CPU operation External space External space External space CPU cycle Bφ Figure 11.68 External Request/Cluster Transfer Mode/Cycle Steal Mode (CPU Cycles/Dual Address Mode/Low Level Sensing)

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 555 of 1438 REJ09B0365-0200 EDREQ EDRAK ETEND Bus cycle CPU cycle Consecutive EXDMA read Consecutive EXDMA write EXDMA cycle of another channel One cluster size transfer period One cluster size transfer period (Last cluster transfer) EDREQ of another channel EDRAK of another channel CPU cycle Consecutive EXDMA read Consecutive EXDMA write Bφ Figure 11.69 External Request/Cluster Transfer Mode/Cycle Steal Mode (Conflict with Another Channel/Dual Address Mode/Low Level Sensing)

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11.7 Ending EXDMA Transfer

The operation for ending EXDMA transfer depends on the transfer end conditions. When EXDMA transfer ends, the DTE bit and the ACT bit in EDMDR change from 1 to 0, indicating that EXDMA transfer has ended. (1) Transfer End by EDTCR Change from 1, 2, or 4 to 0 When the value of EDTCR changes from 1, 2, or 4 to 0, EXDMA transfer ends on the corresponding channel. The DTE bit in EDMDR is cleared to 0, and the DTIF bit in EDMDR is set to 1. If the DTIE bit in EDMDR is set to 1 at this time, a transfer end interrupt request is generated by the transfer counter. EXDMA transfer does not end if the EDTCR value has been 0 since before the start of transfer. (2) Transfer End by Transfer Size Error Interrupt When the following conditions are satisfied while the TSEIE bit in EDMDR is set to 1, a transfer size error occurs and an EXDMA transfer is terminated. At this time, the DTE bit in EDMDR is cleared to 0 and the ESIF bit in EDMDR is set to 1.

• In normal transfer mode and repeat transfer mode, when the next transfer is requested while a transfer is disabled due to the EDTCR value less than the data access size.
• In block transfer mode, when the next transfer is requested while a transfer is disabled due to the EDTCR value less than the block size.
• In cluster transfer mode, when the next transfer is requested while a transfer is disabled due to the EDTCR value less than the cluster size. When the TSEIE bit in EDMDR is cleared to 0, data is transferred until the EDTCR value reaches 0. A transfer size error is not generated. Operation in each transfer mode is described below.
• In normal transfer mode and repeat mode, when the EDTCR value is less than the data access size, data is transferred in bytes.
• In block transfer mode, when the EDTCR value is less than the block size, the specified size of data in EDTCR is transferred instead of transferring the block size of data. When the EDTCR value is less than the data access size, data is transferred in bytes.
• In cluster transfer mode, when the EDTCR value is less than the cluster size, the specified size of data in EDTCR is transferred instead of transferring the cluster size of data. When the EDTCR value is less than the data access size, data is transferred in bytes.

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 557 of 1438 REJ09B0365-0200 (3) Transfer End by Repeat Size End Interrupt In repeat transfer mode, when the RPTIE bit in EDACR is set to 1 and the next transfer request is generated on completion of a repeat-size transfer, a repeat size end interrupt request is generated. The interrupt request terminates EXDMA transfer, the DTE bit in EDMDR is cleared to 0, and the ESIF bit in EDMDR is set to 1 at the same time. If the DTE bit is set to 1 in this state, transfer resumes. In block transfer or cluster transfer mode, a repeat size end interrupt request can be generated. In block transfer mode, if the next transfer request is generated at the end of a block-size transfer, a repeat size end interrupt request is generated. In cluster transfer mode, if the next transfer request is generated at the end of a cluster-size transfer, a repeat size end interrupt request is generated. (4) Transfer End by Extended Repeat Area Overflow Interrupt If an address overflows the extended repeat area when an extended repeat area specification has been made and the SARIE or DARIE bit in EDACR is set to 1, an extended repeat area overflow interrupt is requested. The interrupt request terminates EXDMA transfer, the DTE bit in EDMDR is cleared to 0, and the ESIF bit in EDMDR is set to 1 at the same time. In dual address mode, if an extended repeat area overflow interrupt is requested during a read cycle, the following write cycle processing is still executed. In block transfer mode, if an extended repeat area overflow interrupt is requested during transfer of a block, transfer continues to the end of the block. Transfer end by means of an extended repeat area overflow interrupt occurs between block-size transfers. In cluster transfer mode, if an extended repeat area overflow interrupt is requested during transfer of a cluster, transfer continues to the end of the cluster. Transfer end by means of an extended repeat area overflow interrupt occurs between cluster-size transfers. (5) Transfer End by 0-Write to DTE Bit in EDMDR When 0 is written to the DTE bit in EDMDR by the CPU, etc., transfer ends after completion of the EXDMA cycle in which transfer is in progress or a transfer request was accepted. In block transfer mode, EXDMA transfer ends after completion of one-block-size transfer in progress. In cluster transfer mode, EXDMA transfer ends after completion of one-cluster-size transfer in progress.

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 558 of 1438 REJ09B0365-0200 (6) Transfer End by NMI Interrupt If an NMI interrupt occurs, the EXDMAC clears the DTE bit to 0 in all channels and sets the ERRF bit in EDMDR_0 to 1. EXDMA transfer is aborted when an NMI interrupt is generated during EXDMA transfer. To perform EXDMA transfer after an NMI interrupt occurs, clear the ERRF bit to 0 and then set the DTE bit to 1 in all channels. The following explains the transfer end timing in each mode after an NMI interrupt is detected. (a) Normal transfer mode and repeat transfer mode In dual address mode, EXDMA transfer ends at the end of the EXDMA transfer write cycle in units of transfers. In single address mode, EXDMA transfer ends at the end of the EXDMA transfer bus cycle in units of transfers. (b) Block transfer mode A block size EXDMA transfer is aborted. A block size transfer is not correctly executed, thus matching between the actual transfer and the transfer request is not guaranteed. In dual address mode, a write cycle corresponding to a read cycle is executed as well as in the normal transfer mode. (c) Cluster transfer mode A cluster size EXDMA transfer is aborted. If transfer is aborted in a read cycle, the read data is not guaranteed. If transfer is aborted in a write cycle, the data not transferred is not guaranteed. Matching between the transfer counter and the address register is not guaranteed since the transfer processing cannot be controlled. (7) Transfer End by Address Error If an address error occurs, the EXDMAC clears the DTE bit to 0 in all channels, and set the ERRF bit in EDMDR_0 to 1. An address error during EXDMA transfer forcibly terminates the transfer. To perform EXDMA transfer after an address error occurs, clear the ERRF bit to 0 and then set the DTE bit to 1 in each channel. The transfer end timing after address error detection is the same as for the one when an NMI interrupt occurs.

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 559 of 1438 REJ09B0365-0200 (8) Transfer End by Hardware Standby Mode and Reset Input The EXDMAC is initialized in hardware standby mode and by a reset. EXDMA transfer is not guaranteed in these cases.

11.8 Relationship among EXDMAC and Other Bus Masters

11.8.1 CPU Priority Control Function Over EXDMAC

The EXDMAC priority level control function can be used for the CPU by setting the CPU priority control register (CPUPCR). For details, see section 7.7, CPU Priority Control Function Over DTC, DMAC, and EXDMAC. The EXDMAC priority level can be set independently for each channel by the EDMAP2 to EDMAP0 bits in EDMDR. The CPU priority level, which corresponds to the priority level of exception handling, can be set by updating the values of the CPUP2 to CPUP0 bits in CPUPCR with the interrupt mask bit values. When the CPUPCE bit in CPUPCR is set to 1 to enable the CPU priority level control and the EXDMAC priority level is lower than the CPU priority level, the transfer request of the corresponding channel is masked and the channel activation is disabled. When the priority level of another channel is the same or higher than the CPU priority level, the transfer request for another channel is accepted and transfer is enabled regardless of the priority levels of channels. The CPU priority level control function holds pending the transfer source, which masked the transfer request. When the CPU priority level becomes lower than the channel priority level by updating one of them, the transfer request is accepted and transfer starts. The transfer request held pending is cleared by writing 0 to the DTE bit. When the CPUPCE bit is cleared to 0, the lowest CPU priority level is assumed.

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11.8.2 Bus Arbitration with Another Bus Master

A cycle of another bus master may (or not) be inserted among consecutive EXDMA transfer bus cycles. The EXDMAC bus mastership can be set so that it is released and transferred to another bus master. Some of the consecutive EXDMA transfer bus cycles may be indivisible due to the transfer mode specification, may be consecutive bus cycles for high-speed access due to the transfer mode specification, or may be consecutive bus cycles because another bus master does not request the bus mastership. These consecutive EXDMA read and write cycles are indivisible: refresh cycle, external bus release cycle, or external space access cycle by internal bus master (CPU, DTC, DMAC) does not occur between a read cycle and a write cycle. In cluster transfer mode, the transfer cycle in one cluster is indivisible. In block transfer mode and auto-request burst mode, the EXDMA transfer bus cycles continues. In this period, the bus priority level of the internal bus master is lower than the EXDMAC so that the external space access is held pending (when EBCCS = 0 in the bus control register 2 (BCR2)). When switching to another channel, or in the auto-request cycle steal mode, the EXDMA transfer cycles and internal bus master cycles are alternatively executed. When the internal bus master is not issuing an external space access cycle, the EXDMA transfer bus cycles are continuously executed in the allowable range. When the EBCCS bit in BCR2 is set to 1 to enable the arbitration function between the EXDMAC and the internal bus master, the bus mastership is released, except for indivisible bus cycles, and transferred between the EXDMAC and the internal bus master alternatively. For details, see section 9, Bus Controller (BSC).

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 561 of 1438 REJ09B0365-0200

11.9 Interrupt Sources

EXDMAC interrupt sources are a transfer end by the transfer counter, and an escape end interrupt which is caused by the transfer counter not becoming 0. Table 11.7 shows the interrupt sources and their priority order. Table 11.7 Interrupt Sources and Priority Order Interrupt Interrupt Source Interrupt Priority EXDMTEND0 Transfer end indicated by channel 0 transfer counter EXDMTEND1 Transfer end indicated by channel 1 transfer counter EXDMTEND2 Transfer end indicated by channel 2 transfer counter EXDMTEND3 Transfer end indicated by channel 3 transfer counter EXDMEEND0 Channel 0 transfer size error Channel 0 repeat size end Channel 0 source address extended repeat area overflow Channel 0 destination address extended repeat area overflow EXDMEEND1 Channel 1 transfer size error Channel 1 repeat size end Channel 1 source address extended repeat area overflow Channel 1 destination address extended repeat area overflow EXDMEEND2 Channel 2 transfer size error Channel 2 repeat size end Channel 2 source address extended repeat area overflow Channel 2 destination address extended repeat area overflow EXDMEEND3 Channel 3 transfer size error Channel 3 repeat size end Channel 3 source address extended repeat area overflow Channel 3 destination address extended repeat area overflow High Low Interrupt source can be enabled or disabled by setting the DTIE and ESIE bits in EDMDR for the relevant channels. The DTIE bit can be combined with the DTIF bit in EDMDR to generate an EXDMTEND interrupt. The ESIE bit can be combined with the ESIF bit in EDMDR to generate an EXDMEEND interrupt. Interrupt sources in EXDMEEND are not identified as common interrupts. The interrupt priority order among channels is determined by the interrupt controller as shown in table 11.8. For detains, see section 7, Interrupt Controller.

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 562 of 1438 REJ09B0365-0200 Interrupt source settings are made individually with the interrupt enable bits in the registers for the relevant channels. The transfer counter's transfer end interrupt is enabled or disabled by means of the DTIE bit in EDMDR, the transfer size error interrupt by means of the TSEIE bit in EDMDR, the repeat size end interrupt by means of the RPTIE bit in EDACR, the source address extended repeat area overflow interrupt by means of the SARIE bit in EDACR, and the destination address extended repeat area overflow interrupt by means of the DARIE bit in EDACR. The transfer end interrupt by the transfer counter occurs when the DTIE bit in EDMDR is set to 1, the EDTCR becomes 0 by transfer, and then the DTIF bit in EDMDR is set to 1. Interrupts other than the transfer end interrupt by the transfer counter occurs when the corresponding interrupt enable bit is set to 1, the condition for that interrupt is satisfied, and then the ESIF bit in EDMDR is set to 1. The transfer size error interrupt occurs when the EDTCR value is smaller than the data access size and a data-access-size transfer for one request cannot be performed for a transfer request. In block transfer mode, the block size is compared to the EDTCR value to determine a transfer size error. In cluster transfer mode, the cluster size is compared to the EDTCR value to determine a transfer size error. The repeat size end interrupt occurs when the next transfer request is generated after the end of a repeat size transfer in repeat transfer mode. When the repeat area is not set in the address register, transfer can be aborted periodically based on the set repeat size value. If the transfer end interrupt by the transfer counter occurs at the same time, the ESIF bit is set to 1. The source/destination address extended repeat area overflow interrupt occurs when the addresses overflow the specified extended repeat area. If the transfer end interrupt by the transfer counter occurs at the same time, the ESIF bit is set to 1. Figure 11.70 shows the block diagram of various interrupts and their interrupt flags. The transfer end interrupt can be cleared either by clearing the DTIF or ESIF bit to 0 in EDMDR within the interrupt handling routine, or by re-setting the address registers and then setting the DTE bit to 1 in EDMDR to perform transfer continuation processing. An example of the procedure for clearing the transfer end interrupt and restarting transfer is shown in figure 11.71.

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 564 of 1438 REJ09B0365-0200

11.10 Usage Notes

1. EXDMAC Register A ccess during Operation Except for clearing the DTE bit to 0 in EDMDR, settings should not be changed for a channel in operation (including the transfer standby state). Transfer must be disabled before changing a setting for an operational channel. 2. Module Stop State The EXDMAC operation can be enabled or disabled by the module stop control register. The initial value is "enabled". When the MSTPA14 bit is set to 1 in MSTPCRA, the EXDMAC clock stops and the EXDMAC enters the module stop state. However, 1 cannot be written to the MSTPA14 bit when any of the EXDMAC's channels is enabled for transfer, or when an interrupt is being requested. Before setting the MSTPA14 bit, first clear the DTE bit in EDMDR to 0, then clear the DTIF or DTIE bit in EDMDR to 0. When the EXDMAC clock stops, EXDMAC registers can no longer be accessed. The following EXDMAC register settings remain valid in the module stop state, and so should be disabled, if necessary, before making the module stop transition.

• ETENDE = 1 in EDMDR (ETEND pin enable)
• EDRAKE = 1 in EDMDR (EDRAK pin enable)
• EDACKE = 1 in EDMDR (EDACK pin enable) 3. EDREQ Pin Falling Edge Activation Falling edge sensing on the EDREQ pin is performed in synchronization with EXDMAC internal operations, as indicated below. 1. Activation request standby state: Waits for low level sensing on EDREQ pin, then goes to [2]. 2. Transfer standby state: Waits for EXDMAC data transfer to become possible, then goes to [3]. 3. Activation request disabled state: Waits for high level sensing on EDREQ pin, then goes to [1]. After EXDMAC transfer is enabled, the EXDMAC goes to state [1], so low level sensing is used for the initial activation after transfer is enabled.

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 565 of 1438 REJ09B0365-0200 4. Activation So urce Acceptance At the start of activation source acceptance, low level sensing is used for both falling edge sensing and low level sensing on the EDREQ. Therefore, a request is accepted in the case of a low level at the EDREQ pin that occurs before execution of the EDMDR write for setting the transfer-enabled state. At EXDMAC activation, low level on the EDREQ pin must not remain at the end of the previous transfer. 5. Conflict in Cluster Transfer In cluster transfer mode, the same cluster buffer is used for all channels. When more than one cluster transfer conflicts, the cluster buffer register holds the value of the last cluster transfer. When the transfer between the transfer source/destination and the cluster buffer conflicts with another cluster transfer, the transferred data in the cluster buffer may be overwritten by another channel cluster transfer. Therefore, in the cluster transfer mode (single address mode), do not set the cluster transfer mode for any other channels. 6. Cluster Transfer Mode and Endian In cluster transfer mode, only a transfer to the areas in the big endian format is supported. When cluster transfer mode is specified, do not specify the areas in the little endian format for EDSAR and EDDAR. For details on the endian, see section 9, Bus Controller (BSC).

Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Jul. 31, 2008 Page 566 of 1438 REJ09B0365-0200

Section 12 Data Transfer Controller (DTC) Rev. 2.00 Jul. 31, 2008 Page 567 of 1438 REJ09B0365-0200 Section 12 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated to transfer data by an interrupt request.

12.1 Features

• Transfer possible over any number of channels: Multiple data transfer enabled for one activation source (chain transfer) Chain transfer specifiable after data transfer (when the counter is 0)
• Three transfer modes Normal/repeat/block transfer modes selectable Transfer source and destination addresses can be selected from increment/decrement/fixed
• Short address mode or full address mode selectable  Short address mode Transfer information is located on a 3-longword boundary The transfer source and destination addresses can be specified by 24 bits to select a 16- Mbyte address space directly  Full address mode Transfer information is located on a 4-longword boundary The transfer source and destination addresses can be specified by 32 bits to select a 4- Gbyte address space directly
• Size of data for data transfer can be specified as byte, word, or longword The bus cycle is divided if an odd address is specified for a word or longword transfer. The bus cycle is divided if address 4n + 2 is specified for a longword transfer.
• A CPU interrupt can be requested for the interrupt that activated the DTC A CPU interrupt can be requested after one data transfer completion A CPU interrupt can be requested after the specified data transfer completion
• Read skip of the transfer information specifiable
• Writeback skip executed for the fixed transfer source and destination addresses
• Module stop state specifiable

Section 12 Data Transfer Controller (DTC) Rev. 2.00 Jul. 31, 2008 Page 569 of 1438 REJ09B0365-0200

12.2 Register Descriptions

DTC has the following registers.

• DTC mode register A (MRA)
• DTC mode register B (MRB)
• DTC source address register (SAR)
• DTC destination address register (DAR)
• DTC transfer count register A (CRA)
• DTC transfer count register B (CRB) These six registers MRA, MRB, SAR, DAR, CRA, and CRB cannot be directly accessed by the CPU. The contents of these registers are stored in the data area as transfer information. When a DTC activation request occurs, the DTC reads a start address of transfer information that is stored in the data area according to the vector address, reads the transfer information, and transfers data. After the data transfer, it writes a set of updated transfer information back to the data area.
• DTC enable registers A to F (DTCERA to DTCERF)
• DTC control register (DTCCR)
• DTC vector base register (DTCVBR)

Section 12 Data Transfer Controller (DTC) Rev. 2.00 Jul. 31, 2008 Page 570 of 1438 REJ09B0365-0200

12.2.1 DTC Mode Register A (MRA)

MRA selects DTC operating mode. MRA cannot be accessed directly by the CPU. Bit Bit Name Initial Value R/W MD1 Undefined MD0 Undefined Sz1 Undefined Sz0 Undefined SM1 Undefined SM0 Undefined Undefined Undefined Bit Bit Name Initial Value R/W Description MD1 MD0 Undefined Undefined DTC Mode 1 and 0 Specify DTC transfer mode. 00: Normal mode 01: Repeat mode 10: Block transfer mode 11: Setting prohibited Sz1 Sz0 Undefined Undefined DTC Data Transfer Size 1 and 0 Specify the size of data to be transferred. 00: Byte-size transfer 01: Word-size transfer 10: Longword-size transfer 11: Setting prohibited SM1 SM0 Undefined Undefined Source Address Mode 1 and 0 Specify an SAR operation after a data transfer. 0x: SAR is fixed (SAR writeback is skipped) 10: SAR is incremented after a transfer (by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10) 11: SAR is decremented after a transfer (by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10) 1, 0  Undefined  Reserved The write value should always be 0. [Legend] x: Don't care

Section 12 Data Transfer Controller (DTC) Rev. 2.00 Jul. 31, 2008 Page 571 of 1438 REJ09B0365-0200

12.2.2 DTC Mode Register B (MRB)

MRB selects DTC operating mode. MRB cannot be accessed directly by the CPU. Bit Bit Name Initial Value R/W CHNE Undefined CHNS Undefined DISEL Undefined DTS Undefined DM1 Undefined DM0 Undefined Undefined Undefined Bit Bit Name Initial Value R/W Description

7 CHNE Undefined  DTC Chain Transfer Enable

Specifies the chain transfer. For details, see section 12.7.2, Chain Transfer. The chain transfer condition is selected by the CHNS bit. 0: Disables the chain transfer 1: Enables the chain transfer

6 CHNS Undefined  DTC Chain Transfer Select

Specifies the chain transfer condition. If the following transfer is a chain transfer, the completion check of the specified transfer count is not performed and activation source flag or DTCER is not cleared. 0: Chain transfer every time 1: Chain transfer only when transfer counter = 0

5 DISEL Undefined  DTC Interrupt Select

When this bit is set to 1, a CPU interrupt request is generated every time after a data transfer ends. When this bit is set to 0, a CPU interrupt request is only generated when the specified number of data transfer ends.

4 DTS Undefined  DTC Transfer Mode Select

Specifies either the source or destination as repeat or block area during repeat or block transfer mode. 0: Specifies the destination as repeat or block area 1: Specifies the source as repeat or block area

Section 12 Data Transfer Controller (DTC) Rev. 2.00 Jul. 31, 2008 Page 572 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description DM1 DM0 Undefined Undefined Destination Address Mode 1 and 0 Specify a DAR operation after a data transfer. 0X: DAR is fixed (DAR writeback is skipped) 10: DAR is incremented after a transfer (by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10) 11: SAR is decremented after a transfer (by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10) 1, 0  Undefined  Reserved The write value should always be 0. [Legend] x: Don't care

12.2.3 DTC Source Address Register (SAR)

SAR is a 32-bit register that designates the source address of data to be transferred by the DTC. In full address mode, 32 bits of SAR are valid. In short address mode, the lower 24 bits of SAR is valid and bits 31 to 24 are ignored. At this time, the upper eight bits are filled with the value of bit 23. If a word or longword access is performed while an odd address is specified in SAR or if a longword access is performed while address 4n + 2 is specified in SAR, the bus cycle is divided into multiple cycles to transfer data. For details, see section 12.5.1, Bus Cycle Division. SAR cannot be accessed directly from the CPU.

Section 12 Data Transfer Controller (DTC) Rev. 2.00 Jul. 31, 2008 Page 573 of 1438 REJ09B0365-0200

12.2.4 DTC Destination Address Register (DAR)

DAR is a 32-bit register that designates the destination address of data to be transferred by the DTC. In full address mode, 32 bits of DAR are valid. In short address mode, the lower 24 bits of DAR is valid and bits 31 to 24 are ignored. At this time, the upper eight bits are filled with the value of bit 23. If a word or longword access is performed while an odd address is specified in DAR or if a longword access is performed while address 4n + 2 is specified in DAR, the bus cycle is divided into multiple cycles to transfer data. For details, see section 12.5.1, Bus Cycle Division. DAR cannot be accessed directly from the CPU.

12.2.5 DTC Transfer Count Register A (CRA)

CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal transfer mode, CRA functions as a 16-bit transfer counter (1 to 65,536). It is decremented by 1 every time data is transferred, and bit DTCEn (n = 15 to 0) corresponding to the activation source is cleared and then an interrupt is requested to the CPU when the count reaches H'0000. The transfer count is 1 when CRA = H'0001, 65,535 when CRA = H'FFFF, and 65,536 when CRA = H'0000. In repeat transfer mode, CRA is divided into two parts: the upper eight bits (CRAH) and the lower eight bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent to CRAL when the count reaches H'00. The transfer count is 1 when CRAH = CRAL = H'01, 255 when CRAH = CRAL = H'FF, and 256 when CRAH = CRAL = H'00. In block transfer mode, CRA is divided into two parts: the upper eight bits (CRAH) and the lower eight bits (CRAL). CRAH holds the block size while CRAL functions as an 8-bit block-size counter (1 to 256 for byte, word, or longword). CRAL is decremented by 1 every time a byte (word or longword) data is transferred, and the contents of CRAH are sent to CRAL when the count reaches H'00. The block size is 1 byte (word or longword) when CRAH = CRAL =H'01, 255 bytes (words or longwords) when CRAH = CRAL = H'FF, and 256 bytes (words or longwords) when CRAH = CRAL =H'00. CRA cannot be accessed directly from the CPU.

Section 12 Data Transfer Controller (DTC) Rev. 2.00 Jul. 31, 2008 Page 574 of 1438 REJ09B0365-0200

12.2.6 DTC Transfer Count Register B (CRB)

CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1 every time data is transferred, and bit DTCEn (n = 15 to 0) corresponding to the activation source is cleared and then an interrupt is requested to the CPU when the count reaches H'0000. The transfer count is 1 when CRB = H'0001, 65,535 when CRB = H'FFFF, and 65,536 when CRB = H'0000. CRB is not available in normal and repeat modes and cannot be accessed directly by the CPU.

12.2.7 DTC enable registers A to H (DTCERA to DTCERH)

DTCER, which is comprised of eight registers, DTCERA to DTCERH, is a register that specifies DTC activation interrupt sources. The correspondence between interrupt sources and DTCE bits is shown in table 12.1. Use bit manipulation instructions such as BSET and BCLR to read or write a DTCE bit. If all interrupts are masked, multiple activation sources can be set at one time (only at the initial setting) by writing data after executing a dummy read on the relevant register. Bit Bit Name Initial Value R/W DTCE15 R/W DTCE14 R/W DTCE13 R/W DTCE12 R/W DTCE11 R/W DTCE10 R/W DTCE9 R/W DTCE8 R/W Bit Bit Name Initial Value R/W DTCE7 R/W DTCE6 R/W DTCE5 R/W DTCE4 R/W DTCE3 R/W DTCE2 R/W DTCE1 R/W DTCE0 R/W

Section 12 Data Transfer Controller (DTC) Rev. 2.00 Jul. 31, 2008 Page 575 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description DTCE15 DTCE14 DTCE13 DTCE12 DTCE11 DTCE10 DTCE9 DTCE8 DTCE7 DTCE6 DTCE5 DTCE4 DTCE3 DTCE2 DTCE1 DTCE0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DTC Activation Enable 15 to 0 Setting this bit to 1 specifies a relevant interrupt source to a DTC activation source. [Clearing conditions]

• When writing 0 to the bit to be cleared after reading 1
• When the DISEL bit is 1 and the data transfer has ended
• When the specified number of transfers have ended These bits are not cleared when the DISEL bit is 0 and the specified number of transfers have not ended

12.2.8 DTC Control Register (DTCCR)

DTCCR specifies transfer information read skip. Bit Bit Name Initial Value R/W Note: * Only 0 can be written to clear the flag. R/W R/W R/W RRS R/W RCHNE R/W R R ERR R/(W)* Bit Bit Name Initial Value R/W Description 7 to 5  All 0 R/W Reserved These bits are always read as 0. The write value should always be 0.

Section 12 Data Transfer Controller (DTC) Rev. 2.00 Jul. 31, 2008 Page 576 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description

4 RRS 0 R/W DTC Transfer Information Read Skip Enable

Controls the vector address read and transfer information read. A DTC vector number is always compared with the vector number for the previous activation. If the vector numbers match and this bit is set to 1, the DTC data transfer is started without reading a vector address and transfer information. If the previous DTC activation is a chain transfer, the vector address read and transfer information read are always performed. 0: Transfer read skip is not performed. 1: Transfer read skip is performed when the vector numbers match.

3 RCHNE 0 R/W Chain Transfer Enable After DTC Repeat Transfer

Enables/disables the chain transfer while transfer counter (CRAL) is 0 in repeat transfer mode. In repeat transfer mode, the CRAH value is written to CRAL when CRAL is 0. Accordingly, chain transfer may not occur when CRAL is 0. If this bit is set to 1, the chain transfer is enabled when CRAH is written to CRAL. 0: Disables the chain transfer after repeat transfer 1: Enables the chain transfer after repeat transfer 2, 1  All 0 R Reserved These are read-only bits and cannot be modified.

0 ERR 0 R/(W) * Transfer Stop Flag

Indicates that an address error or an NMI interrupt occurs. If an address error or an NMI interrupt occurs, the DTC stops. 0: No interrupt occurs 1: An interrupt occurs [Clearing condition]

• When writing 0 after reading 1 Note: * Only 0 can be written to clear this flag.

Section 12 Data Transfer Controller (DTC) Rev. 2.00 Jul. 31, 2008 Page 577 of 1438 REJ09B0365-0200

12.2.9 DTC Vector Base Register (DTCVBR)

DTCVBR is a 32-bit register that specifies the base address for vector table address calculation. Bits 31 to 28 and bits 11 to 0 are fixed 0 and cannot be written to. The initial value of DTCVBR is H'00000000. Bit Bit Name Initial Value R/W R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R R R R R R R R R R R R

12.3 Activation Sources

The DTC is activated by an interrupt request. The interrupt source is selected by DTCER. A DTC activation source can be selected by setting the corresponding bit in DTCER; the CPU interrupt source can be selected by clearing the corresponding bit in DTCER. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source interrupt flag or corresponding DTCER bit is cleared.

12.4 Location of Transfer Information and DTC Vector Table

Locate the transfer information in the data area. The start address of transfer information should be located at the address that is a multiple of four (4n). Otherwise, the lower two bits are ignored during access ([1:0] = B'00.) Transfer information can be located in either short address mode (three longwords) or full address mode (four longwords). The DTCMD bit in SYSCR specifies either short address mode (DTCMD = 1) or full address mode (DTCMD = 0). For details, see section 3.2.2, System Control Register (SYSCR). Transfer information located in the data area is shown in figure 12.2 The DTC reads the start address of transfer information from the vector table according to the activation source, and then reads the transfer information from the start address. Figure 12.3 shows correspondences between the DTC vector address and transfer information.

Section 12 Data Transfer Controller (DTC) Rev. 2.00 Jul. 31, 2008 Page 579 of 1438 REJ09B0365-0200 Table 12.1 shows correspondence between the DTC activation source and vector address. Table 12.1 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Origin of Activation Source Activation Source Vector Number DTC Vector Address Offset DTCE * Priority External pin IRQ0 64 H'500 DTCEA15 High IRQ1 65 H'504 DTCEA14 IRQ2 66 H'508 DTCEA13 IRQ3 67 H'50C DTCEA12 IRQ4 68 H'510 DTCEA11 IRQ5 69 H'514 DTCEA10 IRQ6 70 H'518 DTCEA9 IRQ7 71 H'51C DTCEA8 IRQ8 72 H'520 DTCEA7 IRQ9 73 H'524 DTCEA6 IRQ10 74 H'528 DTCEA5 IRQ11 75 H'52C DTCEA4 IRQ12 76 H'530 DTCEA3 IRQ13 77 H'534 DTCEA2 IRQ14 78 H'538 DTCEA1 IRQ15 79 H'53C DTCEA0 A/D_0 ADI0 (A/D_0 conversion end)

86 H'558 DTCEB15

TPU_0 TGI0A 88 H'560 DTCEB13 TGI0B 89 H'564 DTCEB12 TGI0C 90 H'568 DTCEB11 TGI0D 91 H'56C DTCEB10 TPU_1 TGI1A 93 H'574 DTCEB9 TGI1B 94 H'578 DTCEB8 TPU_2 TGI2A 97 H'584 DTCEB7 TGI2B 98 H'588 DTCEB6 TPU_3 TGI3A 101 H'594 DTCEB5 TGI3B 102 H'598 DTCEB4 TGI3C 103 H'59C DTCEB3 TGI3D 104 H'5A0 DTCEB2 Low

Section 12 Data Transfer Controller (DTC) Rev. 2.00 Jul. 31, 2008 Page 580 of 1438 REJ09B0365-0200 Origin of Activation Source Activation Source Vector Number DTC Vector Address Offset DTCE * Priority TGI4A 106 H'5A8 DTCEB1 High TPU_4 TGI4B 107 H'5AC DTCEB0 TGI5A 110 H'5B8 DTCEC15 TPU_5 TGI5B 111 H'5BC DTCEC14 TMR_0 CMI0A 116 H'5D0 DTCEC13 CMI0B 117 H'5D4 DTCEC12 TMR_1 CMI1A 119 H'5DC DTCEC11 CMI1B 120 H'5E0 DTCEC10 TMR_2 CMI2A 122 H'5E8 DTCEC9 CMI2B 123 H'5EC DTCEC8 TMR_3 CMI3A 125 H'5F4 DTCEC7 CMI3B 126 H'5F8 DTCEC6 DMAC DMTEND0 128 H'600 DTCEC5 DMTEND1 129 H'604 DTCEC4 DMTEND2 130 H'608 DTCEC3 DMTEND3 131 H'60C DTCEC2 EXDMAC* EXDMTEND0 132 H'610 DTCEC1 EXDMTEND1 133 H'614 DTCEC0 EXDMTEND2 134 H'618 DTCED15 EXDMTEND3 135 H'61C DTCED14 DMAC DMEEND0 136 H'620 DTCED13 DMEEND1 137 H'624 DTCED12 DMEEND2 138 H'628 DTCED11 DMEEND3 139 H'62C DTCED10 EXDMEEND0 140 H'630 DTCED9 EXDMEEND1 141 H'634 DTCED8 EXDMEEND2 142 H'638 DTCED7 EXDMAC* EXDMEEND3 143 H'63C DTCED6 Low

Section 12 Data Transfer Controller (DTC) Rev. 2.00 Jul. 31, 2008 Page 581 of 1438 REJ09B0365-0200 Origin of Activation Source Activation Source Vector Number DTC Vector Address Offset DTCE * Priority SCI_0 RXI0 145 H'644 DTCED5 High TXI0 146 H'648 DTCED4 SCI_1 RXI1 149 H'654 DTCED3 TXI1 150 H'658 DTCED2 SCI_2 RXI2 153 H'664 DTCED1 TXI2 154 H'668 DTCED0 SCI_3 RXI3 157 H'674 DTCED15 TXI3 158 H'678 DTCED14 SCI_4 RXI4 161 H'684 DTCEE13 TXI4 162 H'688 DTCEE12 TGI6A 164 H'690 DTCEE11 TGI6B 165 H'694 DTCEE10 TGI6C 166 H'698 DTCEE9 TPU_6 TGI6D 167 H'69C DTCEE8 TGI7A 169 H'6A4 DTCEE7 TPU_7 TGI7B 170 H'6A8 DTCEE6 TGI8A 173 H'6B4 DTCEE5 TPU_8 TGI8B 174 H'6B8 DTCEE4 TGI9A 177 H'6C4 DTCEE3 TGI9B 178 H'6C8 DTCEE2 TGI9C 179 H'6CC DTCEE1 TPU_9 TGI9D 180 H'6D0 DTCEE0 TGI10A 182 H'6D8 DTCEF15 TGI10B 183 H'6DC DTCEF14 TPU_10 TGI10V 186 H'6E8 DTCEF11 TGI11A 188 H'6F 0 DTCEF10 TPU_11 TGI11B 189 H'6F4 DTCEF9 Low Notes: 1. The DTCE bits with no corresponding in terrupt are reserved, and the write value should always be 0. To leave software standby mode or all-module-clock-stop mode with an interrupt, write 0 to the corresponding DTCE bit. 2. Supported only by the H8 SX/1648G Group and H8SX/1648H Group.

Section 12 Data Transfer Controller (DTC) Rev. 2.00 Jul. 31, 2008 Page 582 of 1438 REJ09B0365-0200

12.5 Operation

The DTC stores transfer information in the data area. When activated, the DTC reads transfer information that is stored in the data area and transfers data on the basis of that transfer information. After the data transfer, it writes updated transfer information back to the data area. Since transfer information is in the data area, it is possible to transfer data over any required number of channels. There are three transfer modes: normal, repeat, and block. The DTC specifies the source address and destination address in SAR and DAR, respectively. After a transfer, SAR and DAR are incremented, decremented, or fixed independently. Table 12.2 shows the DTC transfer modes. Table 12.2 DTC Transfer Modes Transfer Mode Size of Data Transferred at One Transfer Request Memory Address Increment or Decrement Transfer Count Normal 1 byte/word/longword Increment ed/decremented by 1, 2, or 4, or fixed 1 to 65536 Repeat* 1 byte/word/longword Incremented /decremented by 1, 2, or 4, or fixed 1 to 256* Block* Block size specified by CRAH (1 to 256 bytes/words/longwords) Incremented/decremented by 1, 2, or 4, or fixed 1 to 65536 Notes: 1. Either source or destinat ion is specified to repeat area. 2. Either source or destinati on is specified to block area. 3. After transfer of the specified transfer co unt, initial state is recovered to continue the operation. Setting the CHNE bit in MRB to 1 makes it possible to perform a number of transfers with a single activation (chain transfer). Setting the CHNS bit in MRB to 1 can also be made to have chain transfer performed only when the transfer counter value is 0. Figure 12.4 shows a flowchart of DTC operation, and table 12.3 summarizes the chain transfer conditions (combinations for performing the second and third transfers are omitted).

Section 12 Data Transfer Controller (DTC) Rev. 2.00 Jul. 31, 2008 Page 583 of 1438 REJ09B0365-0200 Start Match & RRS = 1 Not match | RRS = 0 Next transfer Read transfer information Transfer data Update transfer information Update the start address of transfer information Write transfer information CHNE = 1 Transfer counter = 0 or DISEL = 1 Clear activation source flag End CHNS = 0 Transfer counter = 0 DISEL = 1 Clear DTCER/request an interrupt to the CPU No No No No No Yes Yes Yes Yes Yes Vector number comparison Read DTC vector Figure 12.4 Flowchart of DTC Operation

Section 12 Data Transfer Controller (DTC) Rev. 2.00 Jul. 31, 2008 Page 584 of 1438 REJ09B0365-0200 Table 12.3 Chain Transfer Conditions 1st Transfer 2nd Transfer CHNE CHNS DISEL Transfer Counter* CHNE CHNS DISEL Transfer Counter* DTC Transfer 0  0 Not 0     Ends at 1st transfer 0  0 0 *     Ends at 1st transfer 0  1     Interrupt request to CPU 0  0 Not 0 Ends at 2nd transfer 0  0 0 * Ends at 2nd transfer 1 0   0  1  Interrupt request to CPU 1 1 0 Not 0    Ends at 1st transfer 0  0 Not 0 Ends at 2nd transfer 0  0 0 * Ends at 2nd transfer 1 1  0 * 0  1 Interrupt request to CPU 1 1 1 Not 0     Ends at 1st transfer Interrupt request to CPU Notes: 1. CRA in normal mode transfer, CRAL in repeat transfer mode, or CRB in block transfer mode 2. When the contents of the CRAH is wr itten to the CRAL in repeat transfer mode

12.5.1 Bus Cycle Division

When the transfer data size is word and the SAR and DAR values are not a multiple of 2, the bus cycle is divided and the transfer data is read from or written to in bytes. Similarly, when the transfer data size is longword and the SAR and DAR values are not a multiple of 4, the bus cycle is divided and the transfer data is read from or written to in words. Table 12.4 shows the relationship among, SAR, DAR, transfer data size, bus cycle divisions, and access data size. Figure 12.5 shows the bus cycle division example. Table 12.4 Number of Bus Cycle Divisions and Access Size Specified Data Size SAR and DAR Values Byte (B) Word (W) Longword (LW) Address 4n 1 (B) 1 (W) 1 (LW) Address 2n + 1 1 (B) 2 (B-B) 3 (B-W-B) Address 4n + 2 1 (B) 1 (W) 2 (W-W)

Section 12 Data Transfer Controller (DTC) Rev. 2.00 Jul. 31, 2008 Page 585 of 1438 REJ09B0365-0200 Clock Address DTC activation request DTC request BBW R W Clock Address DTC activation request DTC request WW L R W Clock Address DTC activation request DTC request BB L W R W [Example 1: When an odd address and even address are specified in SAR and DAR, respectively, and when the data size of transfer is specified as word] [Example 2: When an odd address and address 4n are specified in SAR and DAR, respectively, and when the data size of transfer is specified as longword] [Example 3: When address 4n + 2 and address 4n are specified in SAR and DAR, respectively, and when the data size of transfer is specified as longword] Vector read Transfer information read Data transfer Transfer information write Vector read Transfer information read Data transfer Transfer information write Vector read Transfer information read Data transfer Transfer information write Figure 12.5 Bus Cycle Division Example

Section 12 Data Transfer Controller (DTC) Rev. 2.00 Jul. 31, 2008 Page 586 of 1438 REJ09B0365-0200

12.5.2 Transfer Information Read Skip Function

By setting the RRS bit of DTCCR, the vector address read and transfer information read can be skipped. The current DTC vector number is always compared with the vector number of previous activation. If the vector numbers match when RRS = 1, a DTC data transfer is performed without reading the vector address and transfer information. If the previous activation is a chain transfer, the vector address read and transfer information read are always performed. Figure 12.6 shows the transfer information read skip timing. To modify the vector table and transfer information, temporarily clear the RRS bit to 0, modify the vector table and transfer information, and then set the RRS bit to 1 again. When the RRS bit is cleared to 0, the stored vector number is deleted, and the updated vector table and transfer information are read at the next activation. Clock Vector read Note: Transfer information read is skipped when the activation sources of (1) and (2) (vector numbers) are the same while RRS = 1. (1) (2) Transfer information read Data transfer Transfer information write Address DTC activation request DTC request Transfer information read skip R W Data transfer Transfer information write R W Figure 12.6 Transfer Information Read Skip Timing

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12.5.3 Transfer Information Writeback Skip Function

By specifying bit SM1 in MRA and bit DM1 in MRB to the fixed address mode, a part of transfer information will not be written back. This function is performed regardless of short or full address mode. Table 12.5 shows the transfer information writeback skip condition and writeback skipped registers. Note that the CRA and CRB are always written back regardless of the short or full address mode. In addition in full address mode, the writeback of the MRA and MRB are always skipped. Table 12.5 Transfer Information Writeback Skip Condition and Writeback Skipped Registers SM1 DM1 SAR DAR 0 0 Skipped Skipped 0 1 Skipped Written back 1 0 Written back Skipped 1 1 Written back Written back

12.5.4 Normal Transfer Mode

In normal transfer mode, one operation transfers one byte, one word, or one longword of data. From 1 to 65,536 transfers can be specified. The transfer source and destination addresses can be specified as incremented, decremented, or fixed. When the specified number of transfers ends, an interrupt can be requested to the CPU. Table 12.6 lists the register function in normal transfer mode. Figure 12.7 shows the memory map in normal transfer mode. Table 12.6 Register Function in Normal Transfer Mode Register Function Written Back Value SAR Source address Incremented/decremented/fixed * DAR Destination address Incremented/decremented/fixed * CRA Transfer count A CRA − 1 CRB Transfer count B Not updated Note: * Transfer information writeback is skipped.

Section 12 Data Transfer Controller (DTC) Rev. 2.00 Jul. 31, 2008 Page 588 of 1438 REJ09B0365-0200 SAR Transfer source data area DAR Transfer Transfer destination data area Figure 12.7 Memory Map in Normal Transfer Mode

12.5.5 Repeat Transfer Mode

In repeat transfer mode, one operation transfers one byte, one word, or one longword of data. By the DTS bit in MRB, either the source or destination can be specified as a repeat area. From 1 to 256 transfers can be specified. When the specified number of transfers ends, the transfer counter and address register specified as the repeat area is restored to the initial state, and transfer is repeated. The other address register is then incremented, decremented, or left fixed. In repeat transfer mode, the transfer counter (CRAL) is updated to the value specified in CRAH when CRAL becomes H'00. Thus the transfer counter value does not reach H'00, and therefore a CPU interrupt cannot be requested when DISEL = 0. Table 12.7 lists the register function in repeat transfer mode. Figure 12.8 shows the memory map in repeat transfer mode.

Section 12 Data Transfer Controller (DTC) Rev. 2.00 Jul. 31, 2008 Page 589 of 1438 REJ09B0365-0200 Table 12.7 Register Function in Repeat Transfer Mode Written Back Value Register Function CRAL is not 1 CRAL is 1 SAR Source address Incremented/decremented/fixed DTS =0: Incremented/ decremented/fixed* DTS = 1: SAR initial value DAR Destination address Incremented/decremented/fixed DTS = 0: DAR initial value DTS =1: Incremented/ decremented/fixed* CRAH Transfer count storage CRAH CRAH CRAL Transfer count A CRAL − 1 CRAH CRB Transfer count B Not updated Not updated Note: * Transfer information writeback is skipped. SAR Transfer source data area (specified as repeat area) DAR Transfer Transfer destination data area Figure 12.8 Memory Map in Repeat Transfer Mode (When Transfer Source is Specified as Repeat Area)

Section 12 Data Transfer Controller (DTC) Rev. 2.00 Jul. 31, 2008 Page 590 of 1438 REJ09B0365-0200

12.5.6 Block Transfer Mode

In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area by the DTS bit in MRB. The block size is 1 to 256 bytes (1 to 256 words, or 1 to 256 longwords). When the transfer of one block ends, the block size counter (CRAL) and address register (SAR when DTS = 1 or DAR when DTS = 0) specified as the block area is restored to the initial state. The other address register is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified. When the specified number of transfers ends, an interrupt is requested to the CPU. Table 12.8 lists the register function in block transfer mode. Figure 12.9 shows the memory map in block transfer mode. Table 12.8 Register Function in Block Transfer Mode Register Function Written Back Value SAR Source address DTS =0: Incremented/decremented/fixed * DTS = 1: SAR initial value DAR Destination address DTS = 0: DAR initial value DTS =1: Incremented/decremented/fixed* CRAH Block size storage CRAH CRAL Block size counter CRAH CRB Block transfer counter CRB − 1 Note: * Transfer information writeback is skipped. Transfer source data area Transfer destination data area (specified as block area) Block area DAR SAR Transfer1st block Nth block Figure 12.9 Memory Map in Block Transfer Mode (When Transfer Destination is Specified as Block Area)

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12.5.7 Chain Transfer

Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. Setting the CHNE and CHNS bits in MRB set to 1 enables a chain transfer only when the transfer counter reaches 0. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 12.10 shows the chain transfer operation. In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the end of the specified number of transfers or by setting the DISEL bit to 1, and the interrupt source flag for the activation source and DTCER are not affected. In repeat transfer mode, setting the RCHNE bit in DTCCR and the CHNE and CHNS bits in MRB to 1 enables a chain transfer after transfer with transfer counter = 1 has been completed. Transfer information CHNE = 1 Transfer information CHNE = 0 Transfer information stored in user area Data area Transfer source data (1) Transfer destination data (1) Transfer source data (2) Transfer destination data (2) Transfer information start address Vector table DTC vector address Figure 12.10 Operation of Chain Transfer

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12.5.8 Operation Timing

Figures 10.11 to 10.14 show the DTC operation timings. Clock Address DTC activation request DTC request R W Vector read Transfer information read Data transfer Transfer information write Figure 12.11 DTC Operation Timing (Example of Short Address Mode in Normal Transfer Mode or Repeat Transfer Mode) Clock Address DTC activation request DTC request RWR W Vector read Transfer information read Data transfer Transfer information write Figure 12.12 DTC Operation Timing (Example of Short Address Mode in Block Transfer Mode with Block Size of 2)

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12.5.9 Number of DTC Execution Cycles

Table 12.9 shows the execution status for a single DTC data transfer, and table 12.10 shows the number of cycles required for each execution. Table 12.9 DTC Execution Status Mode Vector Read I Transfer Information Read J Transfer Information Write L Data Read L Data Write M Internal Operation N Normal 1 0 * 4 * 3 * 0 * 3 * 2.3 2 * 1 * 3 * 2 * 1 3 * 2 * 1 1 0 * Repeat 1 0 * 4 * 3 * 0 * 3 * 2.3 2 * 1 * 3 * 2 * 1 3 * 2 * 1 1 0 * Block transfer 1 0 * 4 * 3 * 0 * 3 * 2.3 2 * 1 * 3•P 2P* 1P 3P 2P* 1P 1 0 * [Legend] P: Block size (CRAH and CRAL value) Note: 1. When transfer information read is skipped 2. In full address mode operation 3. In short address mode operation 4. When the SAR or DAR is in fixed mode 5. When the SAR and DAR are in fixed mode 6. When a longword is transferred while an odd address is specified in the address register 7. When a word is transferred while an odd addr ess is specified in the address register or when a longword is transferred while address 4n + 2 is specified

Section 12 Data Transfer Controller (DTC) Rev. 2.00 Jul. 31, 2008 Page 595 of 1438 REJ09B0365-0200 Table 12.10 Number of Cycles Required for Each Execution State Object to be Accessed On-Chip RAM On-Chip ROM On-Chip I/O Registers External Devices Bus width 32 32 8 16 32 8 16 Access cycles 1 1 2 2 2 2 3 2 3 Vector read SI 1 1    8 12 + 4m 4 6 + 2m Transfer information read SJ 1 1    8 12 + 4m 4 6 + 2m Execution status Transfer information write Sk 1 1    8 12 + 4m 4 6 + 2m Byte data read S L 1 1 2 2 2 2 3 + m 2 3 + m Word data read S L 1 1 4 2 2 4 4 + 2m 2 3 + m Longword data read S L 1 1 8 4 2 8 12 + 4m 4 6 + 2m Byte data write S M 1 1 2 2 2 2 3 + m 2 3 + m Word data write S M 1 1 4 2 2 4 4 + 2m 2 3 + m Longword data write S M 1 1 8 4 2 8 12 + 4m 4 6 + 2m Internal operation S N 1 [Legend] m: Number of wait cycles 0 to 7 (For details, see section 9, Bus Controller (BSC).) The number of execution cycles is calculated from the formula below. Note that Σ means the sum of all transfers activated by one activation event (the number in which the CHNE bit is set to 1, plus 1). Number of execution cycles = I • SI + Σ (J • SJ + K • SK + L • SL + M • SM) + N • SN

12.5.10 DTC Bus Release Timing

The DTC requests the bus mastership to the bus arbiter when an activation request occurs. The DTC releases the bus after a vector read, transfer information read, a single data transfer, or transfer information writeback. The DTC does not release the bus during transfer information read, single data transfer, or transfer information writeback.

12.5.11 DTC Priority Level Control to the CPU

The priority of the DTC activation sources over the CPU can be controlled by the CPU priority level specified by bits CPUP2 to CPUP0 in CPUPCR and the DTC priority level specified by bits DTCP2 to DTCP0. For details, see section 7, Interrupt Controller.

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12.6 DTC Activation by Interrupt

The procedure for using the DTC with interrupt activation is shown in figure 12.15. Clearing the RRS bit in DTCCR to 0 clears the read skip flag of transfer information. Read skip is not performed when the DTC is activated after clearing the RRS bit. When updating transfer information, the RRS bit must be cleared. Set the MRA, MRB, SAR, DAR, CRA, and CRB transfer information in the data area. For details on setting transfer information, see section 12.3, Register Descriptions. For details on location of transfer information, see section 12.4, Location of Transfer Information and DTC Vector Table. Set the start address of the transfer information in the DTC vector table. For details on setting DTC vector table, see section 12.4, Location of Transfer Information and DTC Vector Table. Setting the RRS bit to 1 performs a read skip of second time or later transfer information when the DTC is activated consecu- tively by the same interrupt source. Setting the RRS bit to 1 is always allowed. However, the value set during transfer will be valid from the next transfer. Set the bit in DTCER corresponding to the DTC activation interrupt source to 1. For the correspondence of interrupts and DTCER, refer to table 12.1. The bit in DTCER may be set to 1 on the second or later transfer. In this case, setting the bit is not needed. Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC is activated when an interrupt used as an activation source is generated. For details on the settings of the interrupt enable bits, see the corresponding descriptions of the corresponding module. After the end of one data transfer, the DTC clears the activation source flag or clears the corresponding bit in DTCER and requests an interrupt to the CPU. The operation after transfer depends on the transfer information. For details, see section 12.3, Register Descriptions and figure 12.4. DTC activation by interrupt Clear RRS bit in DTCCR to 0 Set transfer information (MRA, MRB, SAR, DAR, CRA, CRB) Set starts address of transfer information in DTC vector table Set RRS bit in DTCCR to 1 Set corresponding bit in DTCER to 1 Set enable bit of interrupt request for activation source to 1 Interrupt request generated DTC activated Corresponding bit in DTCER cleared or CPU interrupt requested Transfer end [1] [2] [3] [4] [5] [6] [7] [1] [2] [3] [4] [5] [6] [7] Determine clearing method of activation source Clear activation source Clear corresponding bit in DTCER Figure 12.15 DTC with Interrupt Activation

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12.7 Examples of Use of the DTC

12.7.1 Normal Transfer Mode

An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. 1. Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal transfer mode (MD1 = MD0 = 0), and byte size (Sz1 = Sz0 = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the RDR address of the SCI in SAR, the start address of the RAM area where the data will be received in DAR, and 128 (H'0080) in CRA. CRB can be set to any value. 2. Set the start address of the transfer informatio n for an RXI interrupt at the DTC vector address. 3. Set the corresponding bit in DTCER to 1. 4. Set the SCI to the appropriate receive mode. Se t the RIE bit in SCR to 1 to enable the receive end (RXI) interrupt. Since the generation of a receive error during the SCI reception operation will disable subsequent reception, the CPU should be enabled to accept receive error interrupts. 5. Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is automatically cleared to 0. 6. When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. Termination processing should be performed in the interrupt handling routine.

12.7.2 Chain Transfer

An example of DTC chain transfer is shown in which pulse output is performed using the PPG. Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle updating. Repeat mode transfer to the PPG's NDR is performed in the first half of the chain transfer, and normal mode transfer to the TPU's TGR in the second half. This is because clearing of the activation source and interrupt generation at the end of the specified number of transfers are restricted to the second half of the chain transfer (transfer when CHNE = 0).

Section 12 Data Transfer Controller (DTC) Rev. 2.00 Jul. 31, 2008 Page 598 of 1438 REJ09B0365-0200 1. Perform settings for transfer to the PPG' s NDR. Set MRA to source address incrementing (SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), repeat mode (MD1 = 0, MD0 = 1), and word size (Sz1 = 0, Sz0 = 1). Set the source side as a repeat area (DTS = 1). Set MRB to chain transfer mode (CHNE = 1, CHNS = 0, DISEL = 0). Set the data table start address in SAR, the NDRH address in DAR, and the data table size in CRAH and CRAL. CRB can be set to any value. 2. Perform settings for transfer to the TPU's TGR. Set MRA to source address incrementing (SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), normal mode (MD1 = MD0 = 0), and word size (Sz1 = 0, Sz0 = 1). Set the data table start address in SAR, the TGRA address in DAR, and the data table size in CRA. CRB can be set to any value. 3. Locate the TPU transfer information consec utively after the NDR transfer information. 4. Set the start address of the NDR transfer information to the DTC vector address. 5. Set the bit corresponding to the TGIA interrupt in DTCER to 1. 6. Set TGRA as an output compare register (output disabled) with TIOR, and enable the TGIA interrupt with TIER. 7. Set the initial output value in PODR, and the next output value in NDR. Set bits in DDR and NDER for which output is to be performed to 1. Using PCR, select the TPU compare match to be used as the output trigger. 8. Set the CST bit in TSTR to 1, and start the TCNT count operation. 9. Each time a TGRA compare match occurs, the ne xt output value is transferred to NDR and the set value of the next output trigger period is transferred to TGRA. The activation source TGFA flag is cleared. 10. When the specified number of transfers are completed (the TPU transfer CRA value is 0), the TGFA flag is held at 1, the DTCE bit is cleared to 0, and a TGIA interrupt request is sent to the CPU. Termination processing should be performed in the interrupt handling routine.

12.7.3 Chain Transfer when Counter = 0

By executing a second data transfer and performing re-setting of the first data transfer only when the counter value is 0, it is possible to perform 256 or more repeat transfers. An example is shown in which a 128-kbyte input buffer is configured. The input buffer is assumed to have been set to start at lower address H'0000. Figure 12.16 shows the chain transfer when the counter value is 0.

Section 12 Data Transfer Controller (DTC) Rev. 2.00 Jul. 31, 2008 Page 599 of 1438 REJ09B0365-0200 1. For the first transfer, set the normal transfer mode for input data. Set the fixed transfer source address, CRA = H'0000 (65,536 times), CHNE = 1, CHNS = 1, and DISEL = 0. 2. Prepare the upper 8-bit addresses of the start addresses for 65,536-transfer units for the first data transfer in a separate area (in ROM, etc.). For example, if the input buffer is configured at addresses H'200000 to H'21FFFF, prepare H'21 and H'20. 3. For the second transfer, set rep eat transfer mode (with the source side as the repeat area) for re- setting the transfer destination address for the first data transfer. Use the upper eight bits of DAR in the first transfer information area as the transfer destination. Set CHNE = DISEL = 0. If the above input buffer is specified as H'200000 to H'21FFFF, set the transfer counter to 2. 4. Execute the first data transfer 65536 times by means of interrupts. When the transfer counter for the first data transfer reaches 0, the second data transfer is started. Set the upper eight bits of the transfer source address for the first data transfer to H'21. The lower 16 bits of the transfer destination address of the first data transfer and the transfer counter are H'0000. 5. Next, execute the first data transfer the 65536 times specified for the first data transfer by means of interrupts. When the transfer counter for the first data transfer reaches 0, the second data transfer is started. Set the upper eight bits of the transfer source address for the first data transfer to H'20. The lower 16 bits of the transfer destination address of the first data transfer and the transfer counter are H'0000. 6. Steps 4 and 5 are repeated endlessly. As repeat mode is specified for the second data transfer, no interrupt request is sent to the CPU. 1st data transfer information 2nd data transfer information Transfer information located on the on-chip memory Chain transfer (counter = 0) Input circuit Input buffer Upper 8 bits of DAR Figure 12.16 Chain Transfer when Counter = 0

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12.8 Interrupt Sources

An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and priority level control in the interrupt controller.

12.9 Usage Notes

12.9.1 Module Stop State Setting

Operation of the DTC can be disabled or enabled using the module stop control register. The initial setting is for operation of the DTC to be enabled. Register access is disabled by setting the module stop state. The module stop state cannot be set while the DTC is activated. For details, refer to section 27, Power-Down Modes.

12.9.2 On-Chip RAM

Transfer information can be located in on-chip RAM. In this case, the RAME bit in SYSCR must not be cleared to 0.

12.9.3 DMAC Transfer End Interrupt

When the DTC is activated by a DMAC transfer end interrupt, the DTE bit of DMDR is not controlled by the DTC but its value is modified with the write data regardless of the transfer counter value and DISEL bit setting. Accordingly, even if the DTC transfer counter value becomes 0, no interrupt request may be sent to the CPU in some cases. When the DTC is activated by a DMAC transfer end interrupt, even if DISEL=0, an automatic clearing of the relevant activation source flag is not automatically cleared by the DTC. Therefore, write 1 to the DTE bit by the DTC transfer and clear the activation source flag to 0.

12.9.4 DTCE Bit Setting

For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts are disabled, multiple activation sources can be set at one time (only at the initial setting) by writing data after executing a dummy read on the relevant register.

Section 12 Data Transfer Controller (DTC) Rev. 2.00 Jul. 31, 2008 Page 601 of 1438 REJ09B0365-0200

12.9.5 Chain Transfer

When chain transfer is used, clearing of the activation source or DTCER is performed when the last of the chain of data transfers is executed. At this time, SCI and A/D converter interrupt/activation sources, are cleared when the DTC reads or writes to the relevant register. Therefore, when the DTC is activated by an interrupt or activation source, if a read/write of the relevant register is not included in the last chained data transfer, the interrupt or activation source will be retained.

12.9.6 Transfer Information Start Address, Source Address, and Destination Address

The transfer information start address to be specified in the vector table should be address 4n. If an address other than address 4n is specified, the lower 2 bits of the address are regarded as 0s. The source and destination addresses specified in SAR and DAR, respectively, will be transferred in the divided bus cycles depending on the address and data size.

12.9.7 Transfer Information Modification

When IBCCS = 1 and the DMAC is used, clear the IBCCS bit to 0 and then set to 1 again before modifying the DTC transfer information in the CPU exception handling routine initiated by a DTC transfer end interrupt.

12.9.8 Endian Format

The DTC supports big and little endian formats. The endian formats used when transfer information is written to and when transfer information is read from by the DTC must be the same. 12.9.9 Points for Caution when Overwriting DTCER. When overwriting of the DTC-transfer enable register (DTCER) and the generation of an interrupt that is a source for DTC activation are in competition, activation of the DTC and interrupt exception processing by the CPU will both proceed at the same time. Depending on the conditions at this time, doubling of interrupts may occur. If there is a possibility of competition between overwriting of the DTCER and generation of an interrupt that is a source for DTC activation, proceed with overwriting of the DTCER according to the relevant procedure given below.

Section 12 Data Transfer Controller (DTC) Rev. 2.00 Jul. 31, 2008 Page 602 of 1438 REJ09B0365-0200 END END In the case of interrupt-control mode 0 Back-up the value of the CCR. Set the interrupt-mask bit to 1 (corresponding bit = 1 in the CCR). Overwrite the DTCER. Dummy-read the DTCER. Restore the original value of the interrupt-mask bit. In the case of interrupt-control mode 2 Back-up the value of the EXR. Set the interrupt-request masking level to 7 (in the EXR, I2, I1, I0 = b'111). Overwrite the DTCER. Dummy-read the DTCER. Restore the original value of the interrupt-request masking level. Interrupts are masked Figure 12.17 Example of Procedures for Overwriting the DTCER

Rev. 2.00 Jul. 31, 2008 Page 603 of 1438 REJ09B0365-0200 Section 13 I/O Ports Table 13.1 summarizes the port functions. The pins of each port also have other functions such as input/output pins of on-chip peripheral modules or external interrupt input pins. Each I/O port includes a data direction register (DDR) that controls input/output, a data register (DR) that stores output data, a port register (PORT) used to read the pin states, and an input buffer control register (ICR) that controls input buffer on/off. Ports 4, and 5 do not have a DR or a DDR register. Ports D to F and H to K have internal input pull-up MOSs and a pull-up MOS control register (PCR) that controls the on/off state of the input pull-up MOSs. Ports 2 and F include an open-drain control register (ODR) that controls on/off of the output buffer PMOSs. Port N supports 5-V input and functions as an NMOS open-drain output pin. All of the I/O ports can drive a single TTL load with a capacitive component of up to 30 pF and drive Darlington transistors when functioning as output ports. Pins on ports 2, 3, J, and K have Schmitt-trigger inputs. Schmitt-trigger input is enabled for pins of other ports when they are used as IRQ, TPU, TMR, or IIC2 inputs. Table 13.1 Port Functions Function Port Description Bit I/O Input Output Schmitt- Trigger Input* Input Pull- up MOS Function Open- Drain Output Function Port 1 7 P17/SCL0 IRQ7-A/ TCLKD-B/ ADTRG1-A EDRAK1-A* IRQ7-A, TCLKD-B, SCL0  

6 P16/SDA0/SCK3 IRQ6-A/

EDACK1-A* IRQ6-A, TCLKC-B, SDA0

5 P15/SCL1 IRQ5-A/

ETEND1-A* IRQ5-A, TCLKB-B, SCL1 General I/O port function multiplexed with interrupt input, SCI I/O, DMAC I/O, EXDMAC I/O* , A/D converter input, TPU input, and IIC2 I/O

4 P14/SDA1 DREQ1-A/

EDREQ1-A* TxD3 IRQ4-A, TCLKA-B, SDA1

3 P13 ADTRG0-A/

EDRAK0-A* IRQ3-A

Rev. 2.00 Jul. 31, 2008 Page 604 of 1438 REJ09B0365-0200 Function Port Description Bit I/O Input Output Schmitt- Trigger Input* Input Pull- up MOS Function Open- Drain Output Function Port 1

2 P12/SCK2 IRQ2-A DACK0-A/

EDACK0-A* IRQ2-A  

1 P11 RxD2/

ETEND0-A* IRQ1-A General I/O port function multiplexed with interrupt input, SCI I/O, DMAC I/O, A/D converter input, TPU input, and IIC2 I/O

0 P10 DREQ0-A/

EDREQ0-A* TxD2 IRQ0-A Port 2 7 P27/ TIOCB5 TIOCA5/ IRQ15-A* PO7 All input functions  O

6 P26/

interrupt input, PPG output, TPU I/O, TMR I/O, and SCI I/O

5 P25/

PO5 P25, TIOCA4, TMCI1, IRQ13-A

4 P24/

PO4 P24, TIOCB4, TIOCA4, TMRI1, IRQ12-A

3 P23/

2 P22/

1 P21/

PO1 P21, TIOCA3, TMCI0, IRQ9-A

0 P20/

PO0 P20, TIOCB3, TIOCA3, TMRI0, IRQ8-A

Rev. 2.00 Jul. 31, 2008 Page 605 of 1438 REJ09B0365-0200 Function Port Description Bit I/O Input Output Schmitt- Trigger Input* Input Pull- up MOS Function Open- Drain Output Function Port 3 7 P37/ TIOCB2 TIOCA2/ TCLKD-A PO15 EDRAK3* All input functions  

6 P36/

 PO14 EDRAK2* All input functions

5 P35/

EDACK3* All input functions General I/O port function multiplexed with PPG output, EXDMAC I/O* DMAC I/O, and TPU I/O

4 P34/

 PO12/ ETEND3* All input functions

3 P33/

EDREQ3* PO11 All input functions

2 P32/

EDACK2* All input functions

1 P31/

ETEND2* All input functions

0 P30/

EDREQ2* PO8 All input functions Port 4 7  P47/AN11     6  P46/AN10  5  P45/AN9  General I/O port function multiplexed with A/D converter input 4  P44/AN8  3    2    1    0   

Rev. 2.00 Jul. 31, 2008 Page 606 of 1438 REJ09B0365-0200 Function Port Description Bit I/O Input Output Schmitt- Trigger Input* Input Pull- up MOS Function Open- Drain Output Function Port 5 7  P57/AN7/ IRQ7-B DA1 IRQ7-B   6  P56/AN6/ IRQ6-B DA0 IRQ6-B 5  P55/AN5/ IRQ5-B  IRQ5-B General input port function multiplexed with interrupt input, A/D converter input, and D/A converter output 4  P54/AN4/ IRQ4-B  IRQ4-B 3  P53/AN3/ IRQ3-B  IRQ3-B 2  P52/AN2/ IRQ2-B  IRQ2-B 1  P51/AN1/ IRQ1-B  IRQ1-B 0  P50/AN0/ IRQ0-B  IRQ0-B

Rev. 2.00 Jul. 31, 2008 Page 607 of 1438 REJ09B0365-0200 Function Port Description Bit I/O Input Output Schmitt- Trigger Input* Input Pull- up MOS Function Open- Drain Output Function Port 6 7 P67 IRQ15-B EDRAK1-B* IRQ15-B  

6 P66  EDRAK0-B*

5 P65/SCK6 TCK/

EDACK1-B* IRQ13-B, TCK

4 P64 TMCI3/TDI/

ETEND1-B* TMCI3/ IRQ12-B, TDI

3 P63 TMRI3/

EDREQ1-B* TxD6 TMRI3, IRQ11-B, TMS

2 P62/SCK4 IRQ10-B/

EDACK0-B* IRQ10-B, TRST General I/O port function multiplexed with TMR I/O, SCI I/O, EXDMAC I/O* DMAC I/O, H-UDI input, and interrupt input

1 P61 TMCI2/

ETEND0-B* TMCI2, IRQ9-B

0 P60 TMRI2/

EDREQ0-B* TxD4 TMRI2, IRQ8-B Port A 7  PA7 B φ   

6 PA6  AS/AH/

5 PA5  RD

4 PA4  LHWR/LUB

3 PA3  LLWR/LLB

2 PA2 BREQ/

1 PA1  BACK/

(RD/WR-A) General I/O port function multiplexed with system clock output and bus control I/O

0 PA0  BREQO/

Rev. 2.00 Jul. 31, 2008 Page 608 of 1438 REJ09B0365-0200 Function Port Description Bit I/O Input Output Schmitt- Trigger Input* Input Pull- up MOS Function Open- Drain Output Function Port B 7 PB7  CS7-D/ SDRAMφ*   

6 PB6 ADTRG0-B CS6-D

(RD/WR-B)

5 PB5  CS5-D/OE*

CKE*

4 PB4  CS4-B/WE*

3 PB3  CS3-A/

CAS*

2 PB2  CS2-A/

RAS*

1 PB1  CS1/

0 PB0  CS0/

6   

5 PC5  

4 PC4 ADTRG2 

3 PC3  LLCAS*

DQMLL*

2 PC2  LUCAS*

DQMLU*

1 PC1  CS4-C/

0 PC0 WAIT-B/

Rev. 2.00 Jul. 31, 2008 Page 609 of 1438 REJ09B0365-0200 Function Port Description Bit I/O Input Output Schmitt- Trigger Input* Input Pull- up MOS Function Open- Drain Output Function

7 PD7  A7  O  Port D*

6 PD6  A6

5 PD5  A5

4 PD4  A4

3 PD3  A3

2 PD2  A2

1 PD1  A1

0 PD0  A0

7 PE7  A15  O  Port E*

6 PE6  A14

5 PE5  A13

4 PE4  A12

3 PE3  A11

2 PE2  A10

1 PE1  A9

0 PE0  A8

7 PF7/SCK5  A23  O O

6 PF6 RxD5/IrRxD A22

5 PF5  A21/

4 PF4  A20

3 PF3  A19

2 PF2  A18

1 PF1  A17

0 PF0  A16

Rev. 2.00 Jul. 31, 2008 Page 610 of 1438 REJ09B0365-0200 Function Port Description Bit I/O Input Output Schmitt- Trigger Input* Input Pull- up MOS Function Open- Drain Output Function

7 PH7/D7 *

   O  Port H

6 PH6/D6 *

 

5 PH5/D5 *

  General I/O port function multiplexed with bi-directional data bus 4 PH4/D4 *  

3 PH3/D3 *

 

2 PH2/D2 *

 

1 PH1/D1 *

 

0 PH0/D0 *

 

7 PI7/D15 *

   O  Port I

6 PI6/D14 *

 

5 PI5/D13 *

  General I/O port function multiplexed with bi-directional data bus 4 PI4/D12 *  

3 PI3/D11 *

 

2 PI2/D10 *

 

1 PI1/D9 *

 

0 PI0/D8 *

 

7 PJ7/

O 

6 PJ6/

 PO22 All input functions

5 PJ5/

4 PJ4/

 PO20 All input functions

3 PJ3/

2 PJ2/

1 PJ1/

0 PJ0/

 PO16 All input functions

Rev. 2.00 Jul. 31, 2008 Page 611 of 1438 REJ09B0365-0200 Function Port Description Bit I/O Input Output Schmitt- Trigger Input* Input Pull- up MOS Function Open- Drain Output Function

7 PK7/

O  Port

6 PK6/

 PO30 All input functions

5 PK5/

4 PK4/

 PO28 All input functions

3 PK3/

2 PK2/

 PO26 All input functions

1 PK1/

0 PK0/

 PO24 All input functions 7    6    5   

4 PM4 *

 

3 PM3 *

 

2 PM2 *

 

1 PM1 *

  Port M* General I/O port

0 PM0 *

    

Rev. 2.00 Jul. 31, 2008 Page 612 of 1438 REJ09B0365-0200 Function Port Description Bit I/O Input Output Schmitt- Trigger Input* Input Pull- up MOS Function Open- Drain Output Function 6    5    4   

3 PN3/SCL3   SCL3

2 PN2/SDA3   SDA3

1 PN1/SCL2   SCL2

0 PN0/SDA2   SDA2

Notes: 1. Pins without Schmitt-trigger input buffer have CMOS input buffer. 2. Addresses are also output when accessing to the address/data multiplexed I/O space. 3. Ports D and E are disabled when PCJKE = 1. 4. Ports J and K are disabled when PCJKE = 0. 5. Output on the pins of port N is always NMOS open-drain output. 6. Supported only by the H8SX/1648 Group, H8SX/1648A Group, and H8SX/1648L Group. 7. Supported only by the H8SX/1648G Group and H8SX/1648H Group.

Rev. 2.00 Jul. 31, 2008 Page 613 of 1438 REJ09B0365-0200

13.1 Register Descriptions

Table 13.2 lists each port registers. Table 13.2 Register Configuration in Each Port Registers Port Number of Pins DDR DR PORT ICR PCR ODR Port 1 8 O O O O   Port 2 8 O O O O  O Port 3 8 O O O O   Port 4 4   O O   Port 5 8   O O   Port 6 8 O O O O   Port A 8 O O O O   Port B 8 O O O O   Port C*

6 O O O O  

Port D*

8 O O O O O 

Port E* Port H 8 O O O O O  Port I 8 O O O O O  Port J* Port K* Port M*

5 O O O O  

Port N 4 O O O O   [Legend] O: Register exists : No register exists Notes: 1. Write the initial value to any of bits in port C registers. 2. Do not access port D or E registers when PCJKE = 1. 3. Do not access port J or K registers when PCJKE = 0. 4. Supported only by the H8 SX/1648G Group and H8SX/1648H Group.

Rev. 2.00 Jul. 31, 2008 Page 614 of 1438 REJ09B0365-0200

13.1.1 Data Direction Register (PnDDR) (n = 1, 2, 3, 6, A, to F, H to K, M*, and N)

Note: * Supported only by the H8SX/1648G Group and H8SX/1648H Group. DDR is an 8-bit write-only register that specifies the port input or output for each bit. A read from the DDR is invalid and DDR is always read as an undefined value. When the general I/O port function is selected, the corresponding pin functions as an output port by setting the corresponding DDR bit to 1; the corresponding pin functions as an input port by clearing the corresponding DDR bit to 0. The initial DDR values are shown in table 13.3. Bit Bit Name Initial Value R/W The lower six bits of port C registers are effective while the upper two bits are reserved. The lower five bits of port M registers are effective while the upper three bits are reserved. The lower four bits of port N registers are effective while the upper four bits are reserved. Do not access port J or port K registers when PCJKE = 0. Do not access port D or port E registers when PCJKE = 1. Pn7DDR W Pn6DDR W Pn5DDR W Pn4DDR W Pn3DDR W Pn2DDR W Pn1DDR W Pn0DDR W Notes: Table 13.3 Startup Mode and Initial Value Startup Mode Port External Extended Mode Single-Chip Mode Port A H'80 H'00 Other ports H'00 H'00

Rev. 2.00 Jul. 31, 2008 Page 615 of 1438 REJ09B0365-0200

13.1.2 Data Register (PnDR) (n = 1, 2, 3, 6, A, to F, H to K, M*, and N)

Note: * Supported only by the H8SX/1648G Group and H8SX/1648H Group. DR is an 8-bit readable/writable register that stores the output data of the pins to be used as the general output port. The initial value of DR is H'00. The lower six bits of port C registers are effective while the upper two bits are reserved. The lower five bits of port M registers are effective while the upper three bits are reserved. The lower four bits of port N registers are effective while the upper four bits are reserved. Do not access port J or port K registers when PCJKE = 0. Do not access port D or port E registers when PCJKE = 1. Bit Bit Name Initial Value R/W Pn7DR R/W Pn6DR R/W Pn5DR R/W Pn4DR R/W Pn3DR R/W Pn2DR R/W Pn1DR R/W Pn0DR R/W Notes:

13.1.3 Port Register (PORTn) (n = 1 to 6, A to F, H to K, M*, and N)

Note: * Supported only by the H8SX/1648G Group and H8SX/1648H Group. PORT is an 8-bit read-only register that reflects the port pin state. A write to PORT is invalid. When PORT is read, the DR bits that correspond to the respective DDR bits set to 1 are read and the status of each pin whose corresponding DDR bit is cleared to 0 is also read regardless of the ICR value. The initial value of PORT is undefined and is determined based on the port pin state. Notes: The upper four bits of port 4 registers are effective while the lower four bits are reserved. The lower six bits of port C registers are effective while the upper two bits are reserved. The lower five bits of port M registers are effective while the upper three bits are reserved. The lower four bits of port N registers are effective while the upper four bits are reserved. Do not access port J or port K registers when PCJKE = 0. Do not access port D or port E registers when PCJKE = 1. Bit Bit Name Initial Value R/W Pn7 Undefined R Pn6 Undefined R Pn5 Undefined R Pn4 Undefined R Pn3 Undefined R Pn2 Undefined R Pn1 Undefined R Pn0 Undefined R

Rev. 2.00 Jul. 31, 2008 Page 616 of 1438 REJ09B0365-0200

13.1.4 Input Buffer Control Register (PnICR) (n = 1 to 6, A to F, H to K, M*, and N)

Note: * Supported only by the H8SX/1648G Group and H8SX/1648H Group. ICR is an 8-bit readable/writable register that controls the port input buffers. For bits in ICR set to 1, the input buffers of the corresponding pins are valid. For bits in ICR cleared to 0, the input buffers of the corresponding pins are invalid and the input signals are fixed high. When the pin functions as an input for the peripheral modules, the corresponding bits should be set to 1. The initial value should be written to a bit whose corresponding pin is not used as an input or is used as an analog input/output pin. When PORT is read, the pin state is always read regardless of the ICR value. When the ICR value is cleared to 0 at this time, the read pin state is not reflected in a corresponding on-chip peripheral module. If ICR is modified, an internal edge may occur depending on the pin state. Accordingly, ICR should be modified when the corresponding input pins are not used. For example, an IRQ input, modify ICR while the corresponding interrupt is disabled, clear the IRQF flag in ISR of the interrupt controller to 0, and then enable the corresponding interrupt. If an edge occurs after the ICR setting, the edge should be cancelled. The initial value of ICR is H'00. Notes: The upper four bits of port 4 registers are effective while the lower four bits are reserved. The lower six bits of port C registers are effective while the upper two bits are reserved. The lower five bits of port M registers are effective while the upper three bits are reserved. The lower four bits of port N registers are effective while the upper four bits are reserved. Do not access port J or port K registers when PCJKE = 0. Do not access port D or port E registers when PCJKE = 1. Bit Bit Name Initial Value R/W Pn7ICR R/W Pn6ICR R/W Pn5ICR R/W Pn4ICR R/W Pn3ICR R/W Pn2ICR R/W Pn1ICR R/W Pn0ICR R/W

Rev. 2.00 Jul. 31, 2008 Page 617 of 1438 REJ09B0365-0200

13.1.5 Pull-Up MOS Control Register (PnPCR) (n = D to F and H to K)

PCR is an 8-bit readable/writable register that controls on/off of the port input pull-up MOS. If a bit in PCR is set to 1 while the pin is in input state, the input pull-up MOS corresponding to the bit in PCR is turned on. Table 13.4 shows the input pull-up MOS status. The initial value of PCR is H'00. Bit Bit Name Initial Value R/W Pn7PCR R/W Pn6PCR R/W Pn5PCR R/W Pn4PCR R/W Pn3PCR R/W Pn2PCR R/W Pn1PCR R/W Pn0PCR R/W Table 13.4 Input Pull-Up MOS State Port Pin State Reset Hardware Standby Mode Software Standby Mode Other Operation Port D Address output OFF OFF OFF OFF Port output OFF OFF OFF OFF Port input OFF OFF ON/OFF ON/OFF Port E Address output OFF OFF OFF OFF Port output OFF OFF OFF OFF Port input OFF OFF ON/OFF ON/OFF Port F Address output OFF OFF OFF OFF Peripheral module ou tput OFF OFF OFF OFF Port output OFF OFF OFF OFF Port input OFF OFF ON/OFF ON/OFF Port H Data input/output OFF OFF OFF OFF Port output OFF OFF OFF OFF Port input OFF OFF ON/OFF ON/OFF Port I Data input/output OFF OFF OFF OFF Port output OFF OFF OFF OFF Port input OFF OFF ON/OFF ON/OFF Port J Peripheral module output OFF OFF OFF OFF Port output OFF OFF OFF OFF Port input OFF OFF ON/OFF ON/OFF

Rev. 2.00 Jul. 31, 2008 Page 618 of 1438 REJ09B0365-0200 Port Pin State Reset Hardware Standby Mode Software Standby Mode Other Operation Port K Peripheral module output OFF OFF OFF OFF Port output OFF OFF OFF OFF Port input OFF OFF ON/OFF ON/OFF [Legend] OFF: The input pull-up MOS is always off. ON/OFF: If PCR is set to 1, the input pull-up MOS is on; if PCR is cleared to 0, the input pull-up MOS is off.

13.1.6 Open-Drain Control Register (PnODR) (n = 2 and F)

ODR is an 8-bit readable/writable register that selects the open-drain output function. If a bit in ODR is set to 1, the pin corresponding to that bit in ODR functions as an NMOS open- drain output. If a bit in ODR is cleared to 0, the pin corresponding to that bit in ODR functions as a CMOS output. The initial value of ODR is H'00. Bit Bit Name Initial Value R/W Pn7ODR R/W Pn6ODR R/W Pn5ODR R/W Pn4ODR R/W Pn3ODR R/W Pn2ODR R/W Pn1ODR R/W Pn0ODR R/W

13.2 Output Buffer Control

This section describes the output priority of each pin. The name of each peripheral module pin is followed by "_OE". This (for example: TIOCA4_OE) indicates whether the output of the corresponding function is valid (1) or if another setting is specified (0). Table 13.5 lists each port output signal's valid setting. For details on the corresponding output signals, see the register description of each peripheral module. If the name of each peripheral module pin is followed by A or B, the pin function can be modified by the port function control register (PFCR). For details, see section 13.3, Port Function Controller. For a pin whose initial value changes according to the activation mode, "Initial value E" indicates the initial value when the LSI is started up in external extended mode and "Initial value S" indicates the initial value when the LSI is started in single-chip mode.

Rev. 2.00 Jul. 31, 2008 Page 619 of 1438 REJ09B0365-0200

13.2.1 Port 1

(1) P17/IRQ7-A/TCLKD-B/SCL0/ ADTRG1-A/ EDRAK1-A* The pin function is switched as shown below according to the combination of the EXDMAC* and IIC2 register setting and P17DDR bit setting. Setting EXDMAC * IIC2 I/O Port Module Name Pin Function EDRAK1A_OE * SCL0_OE P17DDR EXDMAC* EDRAK1-A* 1   IIC2 SCL0 input/output 0 1  P17 output 0 0 1 I/O port P17 input (initial setting) 0 0 0 Note: * Supported only by the H8SX/ 1648G Group and H8SX/1648H Group. (2) P16/DACK1-A/IRQ6-A/TCLKC-B/SDA0/SCK3/ EDACK1-A* The pin function is switched as shown below according to the combination of the EXDMAC*, DMAC, SCI, and IIC2 register setting and P16DDR bit setting. Setting EXDMAC * DMAC SCI IIC2 I/O Port Module Name Pin Function EDACK1A_OE * DACK1A_OE SCK3_OE SDA0_OE P16DDR EXDMAC* EDACK1-A output* 1  DMAC DACK1-A output 0 1   — SCI SCK3 output 0 0 1   IIC2 SDA0 input/output 0 0 0 1  I/O port P16 output 0 0 0 0 1 P16 input (initial setting) 0 0 0 0 0 Note: * Supported only by the H8SX/ 1648G Group and H8SX/1648H Group.

Rev. 2.00 Jul. 31, 2008 Page 620 of 1438 REJ09B0365-0200 (3) P15/RxD3/TEND1-A/IRQ5-A/TCLKB-B/SCL1/ ETEND1-A* The pin function is switched as shown below according to the combination of the EXDMAC*, DMAC and IIC2 register setting and P15DDR bit setting. Setting EXDMAC * DMAC IIC2 I/O Port Module Name Pin Function ETEND1A_OE * TEND1A_OE SCL1_OE P15DDR EXDMAC* ETEND1-A output* 1    DMAC TEND1-A output 0 1  — IIC2 SCL1 input/output 0 0 1  I/O port P15 output 0 0 0 1 P15 input (initial setting) 0 0 0 0 Note: * Supported only by the H8SX/ 1648G Group and H8SX/1648H Group. (4) P14/TxD3/DREQ1-A/EDREQ1-A*/IRQ4-A/TCLKA-B/SDA1 The pin function is switched as shown below according to the combination of the SCI and IIC2 register setting and P14DDR bit setting. Setting SCI IIC2 I/O Port Module Name Pin Function TxD3_OE SDA1_OE P14DDR SCI TxD3 output 1 — — IIC2 SDA1 input/output 0 1 — I/O port P14 output 0 0 1 P14 input (initial setting) 0 0 0 Note: * Supported only by the H8SX/ 1648G Group and H8SX/1648H Group.

Rev. 2.00 Jul. 31, 2008 Page 621 of 1438 REJ09B0365-0200 (5) P13/ADTRG0-A/IRQ3-A/ EDRAK0-A* The pin function is switched as shown below according to the EXDMAC* register setting and P13DDR bit setting. Setting EXDMAC * I/O Port Module Name Pin Function EDRAK0A_OE * P13DDR EXDMAC* EDRAK0-A output* 1 — I/O port P13 output 0 1 P13 input (initial setting) 0 0 Note: * Supported only by the H8SX/ 1648G Group and H8SX/1648H Group. (6) P12/SCK2/ DACK0-A/IRQ2-A/ EDACK0-A* The pin function is switched as shown below according to the combination of the EXDMAC*, DMAC and SCI register settings and P12DDR bit setting. Setting EXDMAC * DMAC SCI I/O Port Module Name Pin Function EDACK0A_OE * DACK0A_OE SCK2_OE P12DDR EXDMAC* EDACK0-A output* 1    DMAC DACK0-A output 0 1   SCI SCK2 output 0 0 1  I/O port P12 output 0 0 0 1 P12 input (initial setting) 0 0 0 0 Note: * Supported only by the H8SX/ 1648G Group and H8SX/1648H Group.

Rev. 2.00 Jul. 31, 2008 Page 622 of 1438 REJ09B0365-0200 (7) P11/RxD2/TEND0-A/IRQ1-A/ ETEND0-A* The pin function is switched as shown below according to the combination of the EXDMAC* and DMAC register settings and P11DDR bit setting. Setting EXDMAC * DMAC I/O Port Module Name Pin Function ETEND0A_OE * TEND0A_OE P11DDR EXDMAC* ETEND0-A output* 1   DMAC TEND0-A output 10 1  I/O port P11 output 0 0 1 P11 input (initial setting) 0 0 0 Note: * Supported only by the H8SX/ 1648G Group and H8SX/1648H Group. (8) P10/TxD2/DREQ0-A/IRQ0-A/EDERQ0-A* The pin function is switched as shown below according to the combination of the SCI register setting and P10DDR bit setting. Setting SCI I/O Port Module Name Pin Function TxD2_OE P10DDR SCI TxD2 output 1  P10 output 0 1 I/O port P10 input (initial setting) 0 0 Note: * Supported only by the H8SX/ 1648G Group and H8SX/1648H Group.

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13.2.2 Port 2

(1) P27/PO7/TIOCA5/TIOCB5/ IRQ15-A The pin function is switched as shown below according to the combination of the TPU and PPG register settings and P27DDR bit setting. Setting TPU PPG I/O Port Module Name Pin Function TIOCB5_OE PO7_OE P27DDR TPU TIOCB5 output 1 — — PPG PO7 output 0 1 — P27 output 0 0 1 I/O port P27 input (initial setting) 0 0 0 (2) P26/PO6/TIOCA5/TMO1/TxD1/ IRQ14-A The pin function is switched as shown below according to the combination of the TPU, TMR, SCI, and PPG register settings and P26DDR bit setting. Setting TPU TMR SCI PPG I/O Port Module Name Pin Function TIOCA5_OE TMO1_OE TxD1_OE PO6_OE P26DDR TPU TIOCA5 output 1     TMR TMO1 output 0 1    SCI TxD1 output 0 0 1   PPG PO6 output 0 0 0 1  P26 output 0 0 0 0 1 I/O port P26 input (initial setting) 0 0 0 0 0

Rev. 2.00 Jul. 31, 2008 Page 624 of 1438 REJ09B0365-0200 (3) P25/PO5/TIOCA4/TMCI1/RxD1/ IRQ13-A The pin function is switched as shown below according to the combination of the TPU and PPG register settings and P25DDR bit setting. Setting TPU PPG I/O Port Module Name Pin Function TIOCA4_OE PO5_OE P25DDR TPU TIOCA4 output 1   PPG PO5 output 0 1  P25 output 0 0 1 I/O port P25 input (initial setting) 0 0 0 (4) P24/PO4/TIOCA4/TIOCB4/TMRI1/SCK1/ IRQ12-A The pin function is switched as shown below according to the combination of the TPU, SCI, and PPG register settings and P24DDR bit setting. Setting TPU SCI PPG I/O Port Module Name Pin Function TIO CB4_OE SCK1_OE PO4_OE P24DDR TPU TIOCB4 output 1    SCI SCK1 output 0 1   PPG PO4 output 0 0 1  P24 output 0 0 0 1 I/O port P24 input (initial setting) 0 0 0 0

Rev. 2.00 Jul. 31, 2008 Page 625 of 1438 REJ09B0365-0200 (5) P23/PO3/TIOCC3/TIOCD3/ IRQ11-A The pin function is switched as shown below according to the combination of the TPU and PPG register settings and P23DDR bit setting. Setting TPU PPG I/O Port Module Name Pin Function TIOCD3_OE PO3_OE P23DDR TPU TIOCD3 output 1 — — PPG PO3 output 0 1 — P23 output 0 0 1 I/O port P23 input (initial setting) 0 0 0 (6) P22 /PO2/TIOCC3/TMO0/TxD0/ IRQ10-A The pin function is switched as shown below according to the combination of the TPU, TMR, SCI, and PPG register settings and P22DDR bit setting. Setting TPU TMR SCI PPG I/O Port Module Name Pin Function TIOCC3_OE TMO0_OE TxD0_OE PO2_OE P22DDR TPU TIOCC3 output 1     TMR TMO0 output 0 1    SCI TxD0 output 0 0 1   PPG PO2 output 0 0 0 1  P22 output 0 0 0 0 1 I/O port P22 input (initial setting) 0 0 0 0 0

Rev. 2.00 Jul. 31, 2008 Page 626 of 1438 REJ09B0365-0200 (7) P21/PO1/TIOCA3/TMCI0/RxD0/ IRQ9-A The pin function is switched as shown below according to the combination of the TPU and PPG register settings and P21DDR bit setting. Setting TPU PPG I/O Port Module Name Pin Function TIOCA3_OE PO1_OE P21DDR TPU TIOCA3 output 1   PPG PO1 output 0 1  P21 output 0 0 1 I/O port P21 input (initial setting) 0 0 0 (8) P20/PO0/TIOCA3/TIOCB3/TMRI0/SCK0/ IRQ8-A The pin function is switched as shown below according to the combination of the TPU, SCI, and PPG register settings and P20DDR bit setting. Setting TPU SCI PPG I/O Port Module Name Pin Function T IOCB3_OE SCK0_OE PO0_OE P20DDR TPU TIOCB3 output 1    SCI SCK0 output 0 1   PPG PO0 output 0 0 1  P20 output 0 0 0 1 I/O port P20 input (initial setting) 0 0 0 0

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13.2.3 Port 3

(1) P37/PO15/TIOCA2/TIOCB2/TCLKD-A/ EDRAK3* The pin function is switched as shown below according to the combination of the EXDMAC*, TPU and PPG register settings and P37DDR bit setting. Setting EXDMAC * TPU PPG I/O Port Module Name Pin Function EDRAK3 _OE* TIOCB2_OE PO15_OE P37DDR EXDMAC* EDRAK3 output* 1 — — — TPU TIOCB2 output 0 1 — — PPG PO15 output 0 0 1 — P37 output 0 0 0 1 I/O port P37 input (initial setting) 0 0 0 0 Note: * Supported only by the H8SX/ 1648G Group and H8SX/1648H Group. (2) P36/PO14/TIOCA2/ EDRAK2* The pin function is switched as shown below according to the combination of the EXDMAC*, TPU and PPG register settings and P36DDR bit setting. Setting EXDMAC * TPU PPG I/O Port Module Name Pin Function EDRAK2 _OE* TIOCA2_OE PO14_OE P36DDR EXDMAC* EDRAK2 output* 1 — — — TPU TIOCA2 output 0 1 — — PPG PO14 output 0 0 1 — P36 output 0 0 0 1 I/O port P36 input (initial setting) 0 0 0 0 Note: * Supported only by the H8SX/ 1648G Group and H8SX/1648H Group.

Rev. 2.00 Jul. 31, 2008 Page 628 of 1438 REJ09B0365-0200 (3) P35/PO13/TIOCA1/TIOCB1/TCLKC-A/ DACK1-B/ EDACK3* The pin function is switched as shown below according to the combination of the EXDMAC*, DMAC, TPU, and PPG register settings and P35DDR bit setting. Setting EXDMAC * DMAC TPU PPG I/O Port Module Name Pin Function EDACK3 _OE* DACK1B _OE TIOCB2_OE PO14_OE P36DDR EXDMAC* EDACK3 output* 1 — — — — DMAC DACK1-B output 0 1 — — — TPU TIOCB1 output 0 0 1 — — PPG PO13 output 0 0 0 1 — P35 output 0 0 0 0 1 I/O port P35 input (initial setting) 0 0 0 0 0 Note: * Supported only by the H8SX/ 1648G Group and H8SX/1648H Group.

Rev. 2.00 Jul. 31, 2008 Page 629 of 1438 REJ09B0365-0200 (4) P34/PO12/TIOCA1/ TEND1-B/ETEND3* The pin function is switched as shown below according to the combination of the EXDMAC*, DMAC, TPU, and PPG register settings and P34DDR bit setting. Setting EXDMAC * DMAC TPU PPG I/O Port Module Name Pin Function ETEND3 _OE* TEND1B_OE TIOCA1_OE PO12_OE P34DDR EXDMAC* ETEND3 output* 1 — — — — DMAC TEND1-B output 0 1 — — — TPU TIOCA1 output 0 0 1 — — PPG PO12 output 0 0 0 1 — P34 output 0 0 0 0 1 I/O port P34 input (initial setting) 0 0 0 0 0 Note: * Supported only by the H8SX/ 1648G Group and H8SX/1648H Group.

Rev. 2.00 Jul. 31, 2008 Page 630 of 1438 REJ09B0365-0200 (5) P33/PO11/TIOCC0/TIOCD0/TCLKB-A/ DREQ1-B/EDREQ3* The pin function is switched as shown below according to the combination of the TPU and PPG register settings and P33DDR bit setting. Setting TPU PPG I/O Port Module Name Pin Function TIOCD0_OE PO11_OE P33DDR TPU TIOCD0 output 1 — — PPG PO11 output 0 1 — P33 output 0 0 1 I/O port P33 input (initial setting) 0 0 0 Note: * Supported only by the H8SX/ 1648G Group and H8SX/1648H Group. (6) P32/PO10/TIOCC0/TCLKA-A/ DACK0-B/EDACK2* The pin function is switched as shown below according to the combination of the EXDMAC*, DMAC, TPU, and PPG register settings and P32DDR bit setting. Setting EXDMAC * DMAC TPU PPG I/O Port Module Name Pin Function EDACK2_OE * DACK0B_OE TIOCC0_OE PO10_OE P32DDR EXDMAC* EDACK2 output* 1 — — — — DMAC DACK0-B output 0 1 — — — TPU TIOCA1 output 0 0 1 — — PPG PO12 output 0 0 0 1 — P34 output 0 0 0 0 1 I/O port P34 input (initial setting) 0 0 0 0 0 Note: * Supported only by the H8SX/ 1648G Group and H8SX/1648H Group.

Rev. 2.00 Jul. 31, 2008 Page 631 of 1438 REJ09B0365-0200 (7) P31/PO9/TIOCA0/TIOCB0/ TEND0-B/ETEND2* The pin function is switched as shown below according to the combination of the EXDMAC*, DMAC, TPU, and PPG register settings and P31DDR bit setting. Setting EXDMAC * DMAC TPU PPG I/O Port Module Name Pin Function ETEND2_OE * TEND0B_OE TIOCB0_OE PO9_OE P31DDR EXDMAC* ETEND2 output* 1 — — — — DMAC TEND0-B output 0 1 — — — TPU TIOCB0 output 0 0 1 — — PPG PO9 output 0 0 0 1 — P31 output 0 0 0 0 1 I/O port P31 input (initial setting) 0 0 0 0 0 Note: * Supported only by the H8SX/ 1648G Group and H8SX/1648H Group. (8) P30/PO8/TIOCA0/ DREQ0-B/EDREQ2* The pin function is switched as shown below according to the combination of the TPU and PPG register settings and P33DDR bit setting. Setting TPU PPG I/O Port Module Name Pin Function TIOCA0_OE PO8_OE P30DDR TPU TIOCA0 output 1   PPG PO8 output 0 1  P30 output 0 0 1 I/O port P30 input (initial setting) 0 0 0 Note: * Supported only by the H8SX/ 1648G Group and H8SX/1648H Group.

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13.2.4 Port 5

(1) P57/AN7/DA1/ IRQ7-B Module Name Pin Function D/A converter DA1 output (2) P56/AN6/DA0/ IRQ6-B Module Name Pin Function D/A converter DA0 output

13.2.5 Port 6

(1) P67/IRQ15-B/EDRAK1-B*

• H8SX/1648 Group The pin function is switched as shown below according to the combination of the SCI register setting and P67DDR bit setting. Setting SCI I/O Port Module Name Pin Function SCK6_OE P67DDR  1 I/O port P67 output 1 0 P67 input (initial setting) 0 0
• H8SX/1648A Group and H8SX/1648L Group The pin function is switched as shown below according to the combination of the P67DDR bit setting. Setting I/O Port Module Name Pin Function P67DDR I/O port P67 output 1 P67 input (initial setting) 0

Rev. 2.00 Jul. 31, 2008 Page 633 of 1438 REJ09B0365-0200

• H8SX/1648G Group, H8SX/1648H Group The pin function is switched as shown below according to the combination of the EXDMAC* register setting and P67DDR bit setting. Setting EXDMAC * I/O Port Module Name Pin Function EDRAK1B_OE * P67DDR EXDMAC* EDRAK1-B output* 1 0 I/O Port P67 output 0 1 P67 input (initial setting) 0 0 Note: * Supported only by the H8SX/ 1648G Group and H8SX/1648H Group. (2) P66/EDRAK-0-B*
• H8SX/1648 Group The pin function is switched as shown below according to the combination of the SCI register setting and P66DDR bit setting. Setting SCI I/O Port Module Name Pin Function TXD6_OE P66DDR  1 I/O port P66 output 1 0 P66 input (initial setting) 0 0
• H8SX/1648A Group and H8SX/1648L Group The pin function is switched as shown below according to the combination of the P66DDR bit setting. Setting I/O Port Module Name Pin Function P66DDR I/O port P66 output 1 P66 input (initial setting) 0

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• H8SX/1648G Group, H8SX/1648H Group The pin function is switched as shown below according to the combination of the EXDMAC* register setting and P66DDR bit setting. Setting EXDMAC * I/O Port Module Name Pin Function EDRAK0B_OE * P66DDR EXDMAC* EDRAK0-B output* 1 0 I/O Port P66 output 0 1 P66 input (initial setting) 0 0 Note: * Supported only by the H8SX/ 1648G Group and H8SX/1648H Group. (3) P65/TMO3/ DACK3/EDACK1-B* /TCK/SCK6/ IRQ13-B The pin function is switched as shown below according to the combination of operation mode, the EXDMAC* , DMAC, TMR, and SCI register settings and P65DDR bit setting. Setting SCI EXDMAC * DMAC TMR I/O Port Module Name Pin Function MCU Operating Mode SCK6_ OE EDACK1B_ OE * DACK3_OE TMO3_ OE P65DDR SCI SCK6 output 1     EXDMAC* EDACK1-B output* 0 1 0   DMAC DACK3 output 0 0 1   TMR TMO3 output 0 0 0 1  P65 output 0 0 0 0 1 I/O port P65 input (initial setting) Modes other than the boundary scan enabled mode* 0 0 0 0 0 Notes: 1. These pins are boundary scan ded icated input pins during boundary scan enabled mode. 2. Supported only by the H8SX/ 1648G Group and H8SX/1648H Group.

Rev. 2.00 Jul. 31, 2008 Page 635 of 1438 REJ09B0365-0200 (4) P64/TMCI3/ TEND3/ETEND1-B* /TDI/RxD6/IRQ12-B The pin function is switched as shown below according to the combination of operation mode, the EXDMAC* , DMAC register setting and P64DDR bit setting. Setting EXDMAC * DMAC I/O Port Module Name Pin Function MCU Operating Mode ETEND1B_OE * TEND3_OE P64DDR EXDMAC* ETEND1-B output* 1   DMAC TEND3 output 0 1  I/O port P64 output 0 0 1 P64 input (initial setting) Modes other than the boundary scan enabled mode* 0 0 0 Notes: 1. These pins are boundary scan ded icated input pins during boundary scan enabled mode. 2. Supported only by the H8 SX/1648G Group and H8SX/1648H Group. (5) P63/TMRI3/ DREQ3/ EDREQ1-B* /IRQ11-B/TxD6/TMS The pin function is switched as shown below according to the combination of operation mode, the SCI register setting and P63DDR bit setting. Setting SCI I/O Port Module Name Pin Function MCU Operating Mode TxD6_OE P63DDR SCI TxD6 output 1  I/O port P63 output 0 1 P63 input (initial setting) Modes other than the boundary scan enabled mode* 0 0 Notes: 1. These pins are boundary scan ded icated input pins during boundary scan enabled mode. 2. Supported only by the H8 SX/1648G Group and H8SX/1648H Group.

Rev. 2.00 Jul. 31, 2008 Page 636 of 1438 REJ09B0365-0200 (6) P62/TMO2/SCK4/ DACK2/ EDACK0-B* /IRQ10-B/TRST The pin function is switched as shown below according to the combination of the EXDMAC* DMAC, TMR, and SCI register settings and P62DDR bit setting. Setting EXDMAC * DMAC TMR SCI I/O Port Module Name Pin Function MCU Operating Mode EDACK0B_OE * DACK2_OE TMO2_OE SCK4_OE P62DDR EXDMAC* EDACK0-B output* 1     DMAC DACK2 output 0 1    TMR TMO2 output 0 0 1   SCI SCK4 output 0 0 0 1  P62 output 0 0 0 0 1 I/O port P62 input (initial setting) Modes other than the boundary scan enabled mode* 0 0 0 0 0 Notes: 1. These pins are boundary scan ded icated input pins during boundary scan enabled mode. 2. Supported only by the H8 SX/1648G Group and H8SX/1648H Group. (7) P61/TMCI2/RxD4/ TEND2/ ETEND0-B*/IRQ9-B The pin function is switched as shown below according to the combination of the EXDMAC*, DMAC register setting and P61DDR bit setting. Setting EXDMAC * DMAC I/O Port Module Name Pin Function ETEND0B_OE * TEND2-OE P61DDR EXDMAC* ETEND0-B output* 1   DMAC TEND2 output 0 1  I/O port P61 output 0 0 1 P61 input (initial setting) 0 0 0 Note: * Supported only by the H8SX/ 1648G Group and H8SX/1648H Group.

Rev. 2.00 Jul. 31, 2008 Page 637 of 1438 REJ09B0365-0200 (8) P60/TMRI2/TxD4/ DREQ2/ EDREQ0-B*/IRQ8-B The pin function is switched as shown below according to the combination of the SCI register setting and P60DDR bit setting. Setting SCI I/O Port Module Name Pin Function TxD4_OE P60DDR SCI TxD4 output 1  P60 output 0 1 I/O port P60 input (initial setting) 0 0 Note: * Supported only by the H8SX/ 1648G Group and H8SX/1648H Group.

13.2.6 Port A

(1) PA7/B φ The pin function is switched as shown below according to the PA7DDR bit setting. Setting I/O Port Module Name Pin Function PA7DDR I/O port B φ output (initial setting E) PA7 input (initial setting S) [Legend] Initial setting E: Initial setting in external extended mode Initial setting S: Initial setting in single-chip mode

Rev. 2.00 Jul. 31, 2008 Page 638 of 1438 REJ09B0365-0200 (2) PA6/AS/AH/BS-B The pin function is switched as shown below according to the combination of operating mode, EXPE bit, bus controller register, port function control register (PFCR), and the PA6DDR bit settings. Setting Bus Controller I/O Port Module Name Pin Function AH_OE BS-B_OE AS_OE PA6DDR AH output* 1    BS-B output* 0 1   Bus controller AS output* (initial setting E) 0 0 1  PA6 output 0 0 0 1 I/O port PA6 input (initial setting S) 0 0 0 0 [Legend] Initial setting E: Initial setting in external extended mode Initial setting S: Initial setting in single-chip mode Note: * Valid in external extended mode (EXPE = 1) (3) PA5/RD The pin function is switched as shown below according to the combination of operating mode, the EXPE bit, and the PA5DDR bit settings. Setting MCU Operating Mode I/O Port Module Name Pin Function EXPE PA5DDR Bus controller RD output* (Initial setting E) 1  PA5 output 0 1 I/O port PA5 input (initial setting S) 0 0 [Legend] Initial setting E: Initial setting in external extended mode Initial setting S: Initial setting in single-chip mode Note: * Valid in external extended mode (EXPE = 1)

Rev. 2.00 Jul. 31, 2008 Page 639 of 1438 REJ09B0365-0200 (4) PA4/LHWR/LUB The pin function is switched as shown below according to the combination of operating mode, EXPE bit, bus controller register, port function control register (PFCR), and the PA4DDR bit settings. Setting Bus Controller I/O Port Module Name Pin Function LUB_OE * LHWR_OE * PA4DDR LUB output* 1   Bus controller LHWR output* (initial setting E)  1  PA4 output 0 0 1 I/O port PA4 input (initial setting S) 0 0 0 [Legend] Initial setting E: Initial setting in external extended mode Initial setting S: Initial setting in single-chip mode Notes: 1. Valid in external extended mode (EXPE = 1) 2. When the byte control SRAM space is ac cessed while the byte control SRAM space is specified or while LHWR_OE = 1, this pin functions as the LUB output; otherwise, the LHWR output.

Rev. 2.00 Jul. 31, 2008 Page 640 of 1438 REJ09B0365-0200 (5) PA3/LLWR/LLB The pin function is switched as shown below according to the combination of operating mode, EXPE bit, bus controller register, and the PA3DDR bit settings. Setting Bus Controller I/O Port Module Name Pin Function LLB_OE * LLWR_OE * PA3DDR LLB output* 1   Bus controller LLWR output* (initial setting E)  1  PA3 output 0 0 1 I/O port PA3 input (initial setting S) 0 0 0 [Legend] Initial setting E: Initial setting in external extended mode Initial setting S: Initial setting in single-chip mode Notes: 1. Valid in external extended mode (EXPE = 1) 2. If the byte control SRAM space is accessed, this pin functions as the LLB output; otherwise, the LLWR. (6) PA2/BREQ/WAIT-A The pin function is switched as shown below according to the combination of the bus controller register setting and the PA2DDR bit setting. Setting Bus Controller I/O Port Module Name Pin Function BCR_BRLE BCR_WAITE PA2DDR BREQ input 1   Bus controller WAIT-A input 0 1  PA2 output 0 0 1 I/O port PA2 input (initial setting) 0 0 0

Rev. 2.00 Jul. 31, 2008 Page 641 of 1438 REJ09B0365-0200 (7) PA1/BACK/(RD/WR-A) The pin function is switched as shown below according to the combination of operating mode, EXPE bit, bus controller register, port function control register (PFCR), and the PA1DDR bit settings. Setting Bus Controller I/O Port Module Name Pin Function BACK_OE Byte control SRAM Selection (RD/ WR)-A_OE PA1DDR BACK output* 1    0 1   Bus controller RD/WR –A output* 0 0 1  PA1 output 0 0 0 1 I/O port PA1 input (initial setting) 0 0 0 0 Note: * Valid in external extended mode (EXPE = 1) (8) PA0/BREQO/BS-A The pin function is switched as shown below according to the combination of operating mode, EXPE bit, bus controller register, port function control register (PFCR), and the PA0DDR bit settings. Setting I/O Port Bus Controller I/O Port Module Name Pin Function BS-A_OE BREQO_OE PA0DDR BS-A output* 1   Bus controller BREQO output* 0 1  PA0 output 0 0 1 I/O port PA0 input (initial setting) 0 0 0 Note: * Valid in external extended mode (EXPE = 1)

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13.2.7 Port B

(1) PB7/CS7-D/SDφ* The pin function is switched as shown below according to the combination of operating mode, EXPE bit, port function control register (PFCR), and PB7DDR bit settings. Setting MCU Operating Mode Bus Controller I/O Port Module Name Pin Function SDRAM CS7D_OE PB7DDR Clock Pulse Generator SDφ output* 1   Bus controller CS7-D output* 0 1  PB7 output 0 0 1 I/O port PB7 input (initial setting) 0 0 0 Notes: 1. Valid in SDRAM mode 2. Valid in external extended mode (EXPE = 1) 3. Supported only by the H8 SX/1648G Group and H8SX/1648H Group. (2) PB6/CS6-D/(RD/WR-B)/ADTRG0-B The pin function is switched as shown below according to the combination of operating mode, EXPE bit, bus controller register, port function control register (PFCR), and PB6DDR bit settings.

Rev. 2.00 Jul. 31, 2008 Page 643 of 1438 REJ09B0365-0200 Setting I/O Port Module Name Pin Function Byte control SRAM Selection (RD/WR)- B_OE CS6D_OE PB6DDR 1    RD/WR-B output* 0 1   Bus controller CS6-D output* 0 0 1  PB6 output 0 0 0 1 I/O port PB6 input (initial setting) 0 0 0 0 Note: * Valid in external extended mode (EXPE = 1) (3) PB5/CS5-D/OE* /CKE* The pin function is switched as shown below according to the combination of operating mode, EXPE bit, bus controller register, port function control register (PFCR), and PB5DDR bit. Setting Bus Controller I/O Port Module Name Pin Function CKE_OE OE-OE CS5D_OE PB5DDR CKE output* 1    OE output* 0 1   Bus controller CS5-D output* 0 0  PB5 output 0 0 1 1 I/O port PB5 input (initial setting) 0 0 0 0 Notes: 1. Valid in external extended mode (EXPE = 1) 2. Supported only by the H8 SX/1648G Group and H8SX/1648H Group.

Rev. 2.00 Jul. 31, 2008 Page 644 of 1438 REJ09B0365-0200 (4) PB4/CS4-B/WE* The pin function is switched as shown below according to the combination of operating mode, EXPE bit, bus controller register, port function control register (PFCR), and PB4DDR bit settings. Setting Bus Controller I/O Port Bus Controller Module Name Pin Function WE_OE CS4B_OE PB4DDR WE output* 1   Bus controller CS4-B output* 0 1  PB4 output 0 0 1 I/O port PB4 input (initial setting) 0 0 0 Notes: 1. Valid in external extended mode (EXPE = 1) 2. Supported only by the H8 SX/1648G Group and H8SX/1648H Group. (5) PB3/CS3-A/CS7-A/CAS* The pin function is switched as shown below according to the combination of operating mode, EXPE bit, port function control register (PFCR), and the PB3DDR bit settings. Setting Bus Controller I/O Port Module Name Pin Function CAS_OE CS3A_OE CS7A_OE PB3DDR CAS output* 1    CS3-A output*  1   Bus controller CS7-A output*   1  PB3 output 0 0 0 1 I/O port PB3 input (initial setting) 0 0 0 0 Notes: 1. Valid in external extended mode (EXPE = 1) 2. Supported only by the H8 SX/1648G Group and H8SX/1648H Group.

Rev. 2.00 Jul. 31, 2008 Page 645 of 1438 REJ09B0365-0200 (6) PB2/CS2-A/CS6-A/RAS* The pin function is switched as shown below according to the combination of operating mode, EXPE bit, bus controller register, port function control register (PFCR), and the PB2DDR bit settings. Setting Bus Controller I/O Port Module Name Pin Function RAS_OE CS2A_OE CS6A_OE PB3DDR RAS output* 1    CS2-A output* 0 1   Bus controller CS6-A output* 0 0 1  PB2 output 0 0 0 1 I/O port PB2 input (initial setting) 0 0 0 0 Notes: 1. Valid in external extended mode (EXPE = 1) 2. Supported only by the H8 SX/1648G Group and H8SX/1648H Group. (7) PB1/CS1/CS2-B/CS5-A/CS6-B/CS7-B The pin function is switched as shown below according to the combination of operating mode, EXPE bit, port function control register (PFCR), and the PB1DDR bit settings. Setting I/O Port Module Name Pin Function CS1_OE CS2B_OE CS5A_OE CS6B_OE CS7B_OE PB1DDR Bus controller PB1 output 0 0 0 0 0 1 I/O port PB1 input (initial setting) 0 0 0 0 0 0 Note: * Valid in external extended mode (EXPE = 1)

Rev. 2.00 Jul. 31, 2008 Page 646 of 1438 REJ09B0365-0200 (8) PB0/CS0/CS4-A/CS5-B The pin function is switched as shown below according to the combination of operating mode, EXPE bit, port function control register (PFCR), and the PB0DDR bit settings. Setting I/O Port Module Name Pin Function CS0_OE CS4A_OE CS5B_OE PB0DDR CS0 output (initial setting E) 1    CS4-A output  1   Bus controller CS5-B output   1  PB0 output 0 0 0 1 I/O port PB0 input (initial setting S) 0 0 0 0 [Legend] Initial setting E: Initial setting in on- chip ROM disabled external extended mode Initial setting S: Initial setting in other modes

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13.2.8 Port C

(1) PC5, PC4/ADTRG2 The pin function is switched as shown below according to the PCnDDR bit setting. Setting I/O Port Module Name Pin Function PCnDDR PCn output 1 I/O port PCn input (initial setting) [Legend] n: 4 to 5 (2) PC3/LLCAS* /DQMLL * The pin function is switched as shown below according to the combination of operating mode, EXPE bit, bus controller register, and PC3DDR bit settings. Setting Bus Controller I/O Port Module Name Pin Function LLCAS_OE DQMLL_OE PC3DDR LLCAS output* 1   Bus controller DQMLL output*  1  PC3 output* 0 0 1 I/O port PC3 input (initial setting) 0 0 0 Notes: 1. Valid in external extended mode (EXPE = 1) 2. Supported only by the H8 SX/1648G Group and H8SX/1648H Group.

Rev. 2.00 Jul. 31, 2008 Page 648 of 1438 REJ09B0365-0200 (3) PC2/LUCAS* -/DQMLU * The pin function is switched as shown below according to the combination of operating mode, EXPE bit, bus controller register, and PC2DDR bit settings. Setting Bus Controller I/O Port Module Name Pin Function LUCAS_OE DQMLU_OE PC2DDR LUCAS output* 1   Bus controller DQMLU output*  1  PC2 output 0 0 1 I/O port PC2 input (initial setting) 0 0 0 Notes: 1. Valid in external extended mode (EXPE = 1) 2. Supported only by the H8 SX/1648G Group and H8SX/1648H Group. (4) PC1/CS4-C/CS5-C/CS6-C/CS7-C The pin function is switched as shown below according to the combination of operating mode, EXPE bit, port function control register (PFCR), and the PC1DDR bit settings. Setting I/O Port Module Name Pin Function CS4C_OE CS5C_OE CS6C_OE CS7C_OE PB1DDR Bus controller PC1 output 0 0 0 0 1 I/O port PC1 input (initial setting) 0 0 0 0 0 Note: * Valid in external extended mode (EXPE = 1)

Rev. 2.00 Jul. 31, 2008 Page 649 of 1438 REJ09B0365-0200 (5) PC0/CS3-B/WAIT-B/ADTRG1-B The pin function is switched as shown below according to the combination of operating mode, EXPE bit, port function control register (PFCR), and PC1DDR bit settings. Setting Bus Controller I/O Port Module Name Pin Function WAITE bit in BCR CS3B_OE PC0DDR WAIT-B input* 1   Bus controller CS3-B* 0 1  PC0 output 0 0 1 I/O port PC0 input (initial setting) 0 0 0 Note: * Valid in external extended mode (EXPE = 1)

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13.2.9 Port D

The pin function of port D can be switched with that of port J according to the combination of operating mode, the EXPE bit, and the PCJKE bit settings. The pin function of port D can be switched according to the PCJKE bit setting in the single-chip mode (EXPE = 0). However, do not change the setting of the PCJKE bit in external extended mode. For details, see section 13.3.12, Port Function Control Register D (PFCRD). (1) PD7/A7, PD6/A6, PD5/A5, PD4/A4, PD3/A3, PD2/A2, PD1/A1, PD0/A0 The pin function is switched as shown below according to the combination of operating mode, the EXPE bit, and the PDnDDR bit settings. Setting I/O Port Module Name Pin Function MCU Operating Mode PDnDDR On-chip ROM disabled extended mode  Bus controller Address output On-chip ROM enabled extended mode 1 PDn output Single-chip mode * 1 I/O port PDn input (initial setting) Modes other than on-chip ROM disabled extended mode [Legend] n: 0 to 7 Note: * Address output is enabled by setting PDnDDR = 1 in external extended mode (EXPE = 1)

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13.2.10 Port E

The pin function of port E can be switched with that of port K according to the combination of operating mode, the EXPE bit, and the PCJKE bit settings. The pin function of port E can be switched according to the PCJKE bit setting in the single-chip mode (EXPE = 0). However, do not change the setting of the PCJKE bit in external extended mode. For detail, see section 13.3.12, Port Function Control Register D (PFCRD). (1) PE7/A15, PE6/A14, PE5/A13, PE4/A12, PE3/A11, PE2/A10, PE1/A9, PE0/A8 The pin function is switched as shown below according to the combination of operating mode, the EXPE bit, and the PEnDDR bit settings. Setting I/O Port Module Name Pin Function MCU Operating Mode PEnDDR On-chip ROM disabled extended mode  Bus controller Address output On-chip ROM enabled extended mode 1 PEn output Single-chip mode * 1 I/O port PEn input (initial setting) Modes other than on-chip ROM disabled extended mode [Legend] n: 0 to 7 Note: * Address output is enabled by setting PDnDDR = 1 in external extended mode (EXPE = 1)

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13.2.11 Port F

(1) PF7/A23/SCK5 The pin function is switched as shown below according to the combination of SCI register, operating mode, EXPE bit, port function control register (PFCR), and PF7DDR bit settings. Setting SCI I/O Port Module Name Pin Function SCK5_OE A23_OE PF7DDR SCI SCK5 output 1   Bus controller A23 output * 0 1  PF7 output 0 0 1 I/O port PF7 input (initial setting) 0 0 0 Note: * Valid in external extended mode (EXPE = 1) (2) PF6/A22/RxD5/IrRXD The pin function is switched as shown below according to the combination of operating mode, EXPE bit, port function control register (PFCR), and PF6DDR bit settings. Setting I/O Port I/O Port Module Name Pin Function A22_OE PF6DDR Bus controller A22 output * 1  PF6 output 0 1 I/O port PF6 input (initial setting) 0 0 Note: * Valid in external extended mode (EXPE = 1)

Rev. 2.00 Jul. 31, 2008 Page 653 of 1438 REJ09B0365-0200 (3) PF5/A21/TxD5/IrTXD The pin function is switched as shown below according to the combination of SCI and IrDA registers, operating mode, EXPE bit, port function control register (PFCR), and PF5DDR bit settings. Setting SCI IrDA I/O port Module Name Pin Function TxD5_OE IrTXD_OE A21_OE PF5DDR SCI TxD5 output 1    IrDA IrTXD output 0 1   Bus controller A21 output * 0 0 1  PF5 output 0 0 0 1 I/O port PF5 input (initial setting) 0 0 0 0 Note: * Valid in external extended mode (EXPE = 1) (4) PF4/A20 The pin function is switched as shown below according to the combination of operating mode, the EXPE bit, port function control register (PFCR), and the PF4DDR bit settings. Setting I/O Port MCU Operating Mode Module Name Pin Function A20_OE PF4DDR On-chip ROM disabled extended mode Bus controller A20 output   Bus controller A20 output * 1  PF4 output 0 1 Modes other than on-chip ROM disabled extended mode I/O port PF4 input (initial setting) 0 0 Note: * Valid in external extended mode (EXPE = 1)

Rev. 2.00 Jul. 31, 2008 Page 654 of 1438 REJ09B0365-0200 (5) PF3/A19 The pin function is switched as shown below according to the combination of operating mode, the EXPE bit, port function control register (PFCR), and the PF3DDR bit settings. Setting I/O Port MCU Operating Mode Module Name Pin Function A19_OE PF3DDR On-chip ROM disabled extended mode Bus controller A19 output   Bus controller A19 output * 1  PF3 output 0 1 Modes other than on-chip ROM disabled extended mode I/O port PF3 input (initial setting) 0 0 Note: * Valid in external extended mode (EXPE = 1) (6) PF2/A18 The pin function is switched as shown below according to the combination of operating mode, the EXPE bit, port function control register (PFCR), and the PF2DDR bit settings. Setting I/O Port MCU Operating Mode Module Name Pin Function A18_OE PF2DDR On-chip ROM disabled extended mode Bus controller A18 output   Bus controller A18 output * 1  PF2 output 0 1 Modes other than on-chip ROM disabled extended mode I/O port PF2 input (initial setting) 0 0 Note: * Valid in external extended mode (EXPE = 1)

Rev. 2.00 Jul. 31, 2008 Page 655 of 1438 REJ09B0365-0200 (7) PF1/A17 The pin function is switched as shown below according to the combination of operating mode, the EXPE bit, port function control register (PFCR), and the PF1DDR bit settings. Setting I/O Port MCU Operating Mode Module Name Pin Function A17_OE PF1DDR On-chip ROM disabled extended mode Bus controller A17 output   Bus controller A17 output * 1  PF1 output 0 1 Modes other than on-chip ROM disabled extended mode I/O port PF1 input (initial setting) 0 0 Note: * Valid in external extended mode (EXPE = 1) (8) PF0/A16 The pin function is switched as shown below according to the combination of operating mode, the EXPE bit, port function control register (PFCR), and the PF0DDR bit settings. Setting I/O Port MCU Operating Mode Module Name Pin Function A16_OE PF0DDR On-chip ROM disabled extended mode Bus controller A16 output   Bus controller A16 output * 1  PF0 output 0 1 Modes other than on-chip ROM disabled extended mode I/O port PF0 input (initial setting) 0 0 Note: * Valid in external extended mode (EXPE = 1)

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13.2.12 Port H

(1) PH7/D7, PH6/D6, PH5/D5, PH4/D4, PH3/D3, PH2/D2, PH1/D1, PH0/D0 The pin function is switched as shown below according to the combination of operating mode, the EXPE bit, and the PHnDDR bit settings. Setting MCU Operating Mode I/O Port Module Name Pin Function EXPE PHnDDR Bus controller Data I/O * (initial setting E) 1  PHn output 0 1 I/O port PHn input (initial setting S) 0 0 [Legend] Initial setting E: Initial setting in external extended mode Initial setting S: Initial setting in single-chip mode n: 0 to 7 Note: * Valid in external extended mode (EXPE = 1)

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13.2.13 Port I

(1) PI7/D15, PI6/D14, PI5/D13, PI4/D12, PI3/D11, PI2/D10, PI1/D9, PI0/D8 The pin function is switched as shown below according to the combination of operating mode, bus mode, the EXPE bit, and the PInDDR bit settings. Setting Bus Controller I/O Port Module Name Pin Function 16-Bit Bus Mode PInDDR Bus controller Data I/O * (initial setting E) 1  PIn output 0 1 I/O port PIn input (initial setting S) 0 0 [Legend] Initial setting E: Initial setting in external extended mode Initial setting S: Initial setting in single-chip mode n: 0 to 7 Note: * Valid in external extended mode (EXPE = 1)

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13.2.14 Port J

The pin function of port J can be switched with that of port D according to the combination of operating mode, the EXPE bit, and the PCJKE bit settings. The pin function of port J can be switched according to the PCJKE bit setting in the single-chip mode (EXPE = 0). However, do not change the setting of the PCJKE bit in external extended mode. For detail, see section 13.3.12, Port Function Control Register D (PFCRD). (1) PJ7/TIOCA8/TIOCB8/TCLKH/PO23 The pin function is switched as shown below according to the combination of the PPG register, TPU register, port function control register (PFCR), and PJ7DDR bit settings. Setting PPG TPU I/O Port Module Name Pin Function PO23_OE TIOCB8_OE PD7DDR PPG PO23 output * 1   TPU TIOCB8 output * 0 1  PJ7 output* 0 0 1 I/O port PJ7 input* 0 0 0 Note: * Valid when PCJKE = 1 (2) PJ6/TIOCA8/PO22 The pin function is switched as shown below according to the combination of the PPG register, TPU register, port function control register (PFCR), and the PJ6DDR bit settings. Setting PPG TPU I/O Port Module Name Pin Function PO22_OE TIOCA8_OE PJ6DDR PPG PO22 output * 1   TPU TIOCA8 output * 0 1  PJ6 output* 0 0 1 I/O port PJ6 input* 0 0 0 Note: * Valid when PCJKE = 1

Rev. 2.00 Jul. 31, 2008 Page 659 of 1438 REJ09B0365-0200 (3) PJ5/TIOCA7/TIOCB7/TCLKG/PO21 The pin function is switched as shown below according to the combination of the PPG register, TPU register, port function control register (PFCR), and the PJ5DDR bit settings. Setting PPG TPU I/O Port Module Name Pin Function PO21_OE TIOCB7_OE PJ5DDR PPG PO21 output * 1   TPU TIOCB7 output * 0 1  PJ5 output* 0 0 1 I/O port PJ5 input* 0 0 0 Note: * Valid when PCJKE = 1 (4) PJ4/TIOCA7/PO20 The pin function is switched as shown below according to the combination of the PPG register, TPU register, port function control register (PFCR), and the PJ4DDR bit settings. Setting PPG TPU I/O Port Module Name Pin Function PO20_OE TIOCA7_OE PJ4DDR PPG PO20 output * 1   TPU TIOCA7 output * 0 1  PJ4 output* 0 0 1 I/O port PJ4 input* 0 0 0 Note: * Valid when PCJKE = 1

Rev. 2.00 Jul. 31, 2008 Page 660 of 1438 REJ09B0365-0200 (5) PJ3/PO19/TIOCC6/TIOCD6/TCLKF The pin function is switched as shown below according to the combination of the PPG register, TPU register, port function control register (PFCR), and the PJ3DDR bit settings. Setting PPG TPU I/O Port Module Name Pin Function PO19_OE TIOCD6_OE PJ3DDR PPG PO19 output * 1   TPU TIOCD6 output * 0 1  PJ3 output* 0 0 1 I/O port PJ3 input* 0 0 0 Note: * Valid when PCJKE = 1 (6) PJ2/PO18/TIOCC6/TCLKE The pin function is switched as shown below according to the combination of the PPG register, TPU register, port function control register (PFCR), and the PJ2DDR bit settings. Setting PPG TPU I/O Port Module Name Pin Function PO18_OE TIOCC6_OE PJ2DDR PPG PO18 output * 1   TPU TIOCC6 output * 0 1  PJ2 output* 0 0 1 I/O port PJ2 input* 0 0 0 Note: * Valid when PCJKE = 1

Rev. 2.00 Jul. 31, 2008 Page 661 of 1438 REJ09B0365-0200 (7) PJ1/PO17/TIOCA6/TIOCB6 The pin function is switched as shown below according to the combination of the PPG register, TPU register, port function control register (PFCR), and the PJ1DDR bit settings. Setting PPG TPU I/O Port Module Name Pin Function PO17_OE TIOCB6_OE PJ1DDR PPG PO17 output * 1   TPU TIOCB6 output * 0 1  PJ1 output* 0 0 1 I/O port PJ1 input* 0 0 0 Note: * Valid when PCJKE = 1 (8) PJ0/PO16/TIOCA6 The pin function is switched as shown below according to the combination of the PPG register, TPU register, port function control register (PFCR), and the PJ0DDR bit settings. Setting PPG TPU I/O Port Module Name Pin Function PO16_OE TIOCA6_OE PJ0DDR PPG PO16 output * 1   TPU TIOCA6 output * 0 1  PJ0 output* 0 0 1 I/O port PJ0 input* 0 0 0 Note: * Valid when PCJKE = 1

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13.2.15 Port K

The pin function of port K can be switched with that of port E according to the combination of operating mode, the EXPE bit, and the PCJKE bit settings. The pin function of port K can be switched according to the PCJKE bit setting in the single-chip mode (EXPE = 0). However, do not change the setting of the PCJKE bit in external extended mode. For detail, see section 13.3.12, Port Function Control Register D (PFCRD). (1) PK7/PO31/TIOCA11/TIOCB11 The pin function is switched as shown below according to the combination of the PPG register, TPU register, port function control register (PFCR), and the PK7DDR bit settings. Setting PPG TPU I/O Port Module Name Pin Function PO31_OE TIOCB11_OE PK7DDR PPG PO31 output * 1   TPU TIOCB11 output * 0 1  PK7 output* 0 0 1 I/O port PK7 input* 0 0 0 Note: * Valid when PCJKE = 1 (2) PK6/PO30/TIOCA11 The pin function is switched as shown below according to the combination of the PPG register, TPU register, port function control register (PFCR), and the PK6DDR bit settings. Setting PPG TPU I/O Port Module Name Pin Function PO30_OE TIOCA11_OE PK6DDR PPG PO30 output * 1   TPU TIOCA11 output * 0 1  PK6 output* 0 0 1 I/O port PK6 input* 0 0 0 Note: * Valid when PCJKE = 1

Rev. 2.00 Jul. 31, 2008 Page 663 of 1438 REJ09B0365-0200 (3) PK5/PO29/TIOCA10/TIOCB10 The pin function is switched as shown below according to the combination of the PPG register, TPU register, port function control register (PFCR), and the PK5DDR bit settings. Setting PPG TPU I/O Port Module Name Pin Function PO29_OE TIOCB10_OE PK5DDR PPG PO29 output * 1   TPU TIOCB10 output * 0 1  PK5 output* 0 0 1 I/O port PK5 input* 0 0 0 Note: * Valid when PCJKE = 1 (4) PK4/PO28/TIOCA10 The pin function is switched as shown below according to the combination of the PPG register, TPU register, port function control register (PFCR), and the PK4DDR bit settings. Setting PPG TPU I/O Port Module Name Pin Function PO28_OE TIOCA10_OE PK4DDR PPG PO28 output * 1   TPU TIOCA10 output * 0 1  PK4 output* 0 0 1 I/O port PK4 input* 0 0 0 Note: * Valid when PCJKE = 1

Rev. 2.00 Jul. 31, 2008 Page 664 of 1438 REJ09B0365-0200 (5) PK3/PO27/TIOCC9/TIOCD9 The pin function is switched as shown below according to the combination of the PPG register, TPU register, port function control register (PFCR), and the PK3DDR bit settings. Setting PPG TPU I/O Port Module Name Pin Function PO27_OE TIOCD9_OE PK3DDR PPG PO27 output * 1   TPU TIOCD9 output * 0 1  PK3 output* 0 0 1 I/O port PK3 input* 0 0 0 Note: * Valid when PCJKE = 1 (6) PK2/PO26/TIOCC9 The pin function is switched as shown below according to the combination of the PPG register, TPU register, port function control register (PFCR), and the PK2DDR bit settings. Setting PPG TPU I/O Port Module Name Pin Function PO26_OE TIOCC9_OE PK2DDR PPG PO26 output * 1   TPU TIOCC9 output * 0 1  PK2 output* 0 0 1 I/O port PK2 input* 0 0 0 Note: * Valid when PCJKE = 1

Rev. 2.00 Jul. 31, 2008 Page 665 of 1438 REJ09B0365-0200 (7) PK1/PO25/TIOCA9/TIOCB9 The pin function is switched as shown below according to the combination of the PPG register, TPU register, port function control register (PFCR), and the PK1DDR bit settings. Setting PPG TPU I/O Port Module Name Pin Function PO25_OE TIOCB9_OE PK1DDR PPG PO25 output * 1   TPU TIOCB9 output * 0 1  PK1 output* 0 0 1 I/O port PK1 input* 0 0 0 Note: * Valid when PCJKE = 1 (8) PK0/PO24/TIOCA9 The pin function is switched as shown below according to the combination of the PPG register, TPU register, port function control register (PFCR), and the PK0DDR bit settings. Setting PPG TPU I/O Port Module Name Pin Function PO24_OE TIOCA9_OE PK0DDR PPG PO24 output * 1   TPU TIOCA9 output * 0 1  PK0 output* 0 0 1 I/O port PK0 input* 0 0 0 Note: * Valid when PCJKE = 1

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13.2.16 Port M*

Note: * Supported only by the H8SX/1648G Group and H8SX/1648H Group. (1) PM4 The pin function is switched as shown below according to the PM4DDR bit setting. Setting I/O Port Module Name Pin Function PM4DDR PM4 output 1 I/O port PM4 input (initial setting) (2) PM3 The pin function is switched as shown below according to the PM3DDR bit setting. Setting I/O Port Module Name Pin Function PM3DDR PM3 output 1 I/O port PM3 input (initial setting) (3) PM2 The pin function is switched as shown below according to the PM2DDR bit setting. Setting I/O Port Module Name Pin Function PM2DDR PM2 output 1 I/O port PM2 input (initial setting)

Rev. 2.00 Jul. 31, 2008 Page 667 of 1438 REJ09B0365-0200 (4) PM1 The pin function is switched as shown below according to the PM1DDR bit setting. Setting I/O Port Module Name Pin Function PM1DDR PM1 output 1 I/O port PM1 input (initial setting) (5) PM0 The pin function is switched as shown below according to the PM0DDR bit setting. Setting I/O Port Module Name Pin Function PM0DDR PM0 output 1 I/O port PM0 input (initial setting)

13.2.17 Port N

(1) PN3/SCL3 The pin function is switched as shown below according to the combination of the IIC2 register setting and the PN3DDR bit setting. Setting IIC2 I/O Port Module Name Pin Function SCL3_OE PN3DDR IIC2 SCL3 I/O 1  PN3 output (open-drain output) 0 1 I/O port PN3 input (initial setting) 0 0

Rev. 2.00 Jul. 31, 2008 Page 668 of 1438 REJ09B0365-0200 (2) PN2/SDA3 The pin function is switched as shown below according to the combination of the IIC2 register setting and the PN2DDR bit setting. Setting IIC2 I/O Port Module Name Pin Function SDA3_OE PN2DDR IIC2 SDA3 I/O 1  PN2 output (open-drain output) 0 1 I/O port PN2 input (initial setting) 0 0 (3) PN1/SCL2 The pin function is switched as shown below according to the combination of the IIC2 register setting and the PN1DDR bit setting. Setting IIC2 I/O Port Module Name Pin Function SCL2_OE PN1DDR IIC2 SCL2 I/O 1  PN1 output (open-drain output) 0 1 I/O port PN1 input (initial setting) 0 0

Rev. 2.00 Jul. 31, 2008 Page 669 of 1438 REJ09B0365-0200 (4) PN0/SDA2 The pin function is switched as shown below according to the combination of the IIC2 register setting and the PN0DDR bit setting. Setting IIC2 I/O Port Module Name Pin Function SDA2_OE PN0DDR IIC2 SDA2 I/O 1  PN0 output (open drain output) 0 1 I/O port PN0 input (initial setting) 0 0

Rev. 2.00 Jul. 31, 2008 Page 670 of 1438 REJ09B0365-0200 Table 13.5 Available Output Signals and Settings in Each Port Port Output Specification Signal Name Output Signal Name Signal Selection Register Settings Peripheral Module Settings EDRAK1A_OE* EDRAK1* PFCR8.EDMAS1[A,B] = 00 SYSCR.EXPE=1, EDMDR_1.EDRAKE=1 SCL0_OE SCL0 ICCRA.ICE = 1 EDACK1A_OE* EDACK1* PFCR8.EDMAS1[A,B] = 00 SYSCR.EXPE=1, EDACR_1.AMS=1, EDMDR_1.EDACKE=1 DACK1A_OE DACK1 PFCR7.DMAS1[A,B] = 00 DMAC.DACR_1.AMS = 1, DMDR_1.DACKE = 1 SCK3_OE SCK3 When SCMR.SMIF = 1: SCR.TE = 1 or SCR.RE = 1 while SMR.GM = 0, SCR.CKE[1,0] = 01 or while SMR.GM = 1 When SCMR.SMIF = 0: SCR.TE = 1 or SCR.RE = 1 while SMR.C/A = 0, SCR.CKE[1,0] = 01 or while SMR.C/A = 1, SCR.CKE1 = 0 SDA0_OE SDA0 ICCRA.ICE = 1 ETEND1A_OE* ETEND1* PFCR8.EDMAS1[A,B] = 00 SYSCR.EXPE=1, EDMDR_1.ETENDE = TEND1A_OE TEND1 PFCR7.DMAS1[A,B] = 00 DMDR_1.TENDE = 1 SCL1_OE SCL1 ICCRA.ICE = 1 4 TxD3_OE TxD3 SCR.TE = 1 SDA1_OE SDA1 ICCRA.ICE = 1 3 EDRAK0A_OE* EDRAK0* PFCR8.EDMAS0[A,B] = 00 SYSCR.EXPE=1, EDMDR_0.EDRAKE = EDACK0A_OE* EDACK0* PFCR8.EDMAS0[A,B] = 00 SYSCR.EXPE=1, EDACR_0.AMS = 1, EDMDR_0.EDACKE=1 DACK0A_OE DACK0 PFCR7.DMAS0[A,B] = 00 DMAC_0.DACR.AMS = 1, DMDR_0.DACKE = 1

Rev. 2.00 Jul. 31, 2008 Page 671 of 1438 REJ09B0365-0200 Port Output Specification Signal Name Output Signal Name Signal Selection Register Settings Peripheral Module Settings P1 2 SCK2_OE SCK2 When SCMR.SMIF = 1: SCR.TE = 1 or SCR.RE = 1 while SMR.GM = 0, SCR.CKE[1, 0] = 01 or while SMR.GM = 1 When SCMR.SMIF = 0: SCR.TE = 1 or SCR.RE = 1 while SMR.C/A = 0, SCR.CKE[1, 0] = 01 or while SMR.C/A = 1, SCR.CKE1 = 0 ETEND0A_OE* ETEND0 PFCR8.EDMAS0[A,B] = 00 SYSCR.EXPE=1, EDMDR_0.TENDE = 1 TEND0A_OE TEND0 PFCR7.DMAS0[A,B] = 00 DMDR_0.TENDE= 1 0 TxD2_OE TxD2 SCR.TE = 1 P2 7 TIOCB5_OE TIOCB5 TPU.TIOR_5.IOB3 = 0, TPU.TIOR_5.IOB[1,0] = 01/10/11 PO7_OE PO7 NDERL.NDER7 = 1 6 TIOCA5_OE TIOCA5 TPU.TIOR_5.IOA3 = 0, TPU.TIOR_5.IOA [1,0] = 01/10/11 TMO1_OE TMO1 TMR.TCSR_1,.OS3,2 = 01/10/11 or TMR.TCSR_1, OS[1,0] = 01/10/11 TxD1_OE TxD1 SCR.TE = 1 PO6_OE PO6 NDERL.NDER6 = 1 5 TIOCA4_OE TIOCA4 TPU.TIOR_4.IOA3 = 0, TPU.TIOR_4.IOA[1,0] = 01/10/11 PO5_OE PO5 NDERL.NDER5 = 1 4 TIOCB4_OE TIOCB4 TPU.TIOR_4.IOB3 = 0, TPU.TIOR_4.IOB[1,0] = 01/10/11 SCK1_OE SCK1 When SCMR.SMIF = 1: SCR.TE = 1 or SCR.RE = 1 while SMR.GM = 0, SCR.CKE [1, 0] = 01 or while SMR.GM = 1 When SCMR.SMIF = 0: SCR.TE = 1 or SCR.RE = 1 while SMR.C/A = 0, SCR.CKE [1, 0] = 01 or while SMR.C/A = 1, SCR.CKE 1 = 0 PO4_OE PO4 NDERL.NDER4 = 1

Rev. 2.00 Jul. 31, 2008 Page 672 of 1438 REJ09B0365-0200 Port Output Specification Signal Name Output Signal Name Signal Selection Register Settings Peripheral Module Settings P2 3 TIOCD3_OE TIOCD3 TPU.TMDR.BFB = 0, TPU.TIORL_3.IOD3 = 0, TPU.TIORL_3.IOD[1,0] = 01/10/11 PO3_OE PO3 NDERL.NDER3 = 1 2 TIOCC3_OE TIOCC3 TPU.TMDR.BFA = 0, TPU.TIORL_3.IOC3 = 0, TPU.TIORL_3.IOD[1,0] = 01/10/11 TMO0_OE TMO0 TMR.TCSR_0.OS[3,2] = 01/10/11 or TMR.TCSR_0.OS[1,0] = 01/10/11 TxD0_OE TxD0 SCR.TE = 1 PO2_OE PO2 NDERL.NDER2 = 1 1 TIOCA3_OE TIOCA3 TPU.TIORH_3.IOA3 = 0, TPU.TIORH_3.IOA[1,0] = 01/10/11 PO1_OE PO1 NDERL.NDER1 = 1 0 TIOCB3_OE TIOCB3 TPU.TIORH_3.IOB3 = 0, TPU.TIORH_3.IOB[1,0] = 01/10/11 SCK0_OE SCK0 When SCMR.SMIF = 1: SCR.TE = 1 or SCR.RE = 1 while SMR.GM = 0, SCR.CKE [1, 0] = 01 or while SMR.GM = 1 When SCMR.SMIF = 0: SCR.TE = 1 or SCR.RE = 1 while SMR.C/A = 0, SCR.CKE [1, 0] = 01 or while SMR.C/A = 1, SCR.CKE 1 = 0 PO0_OE PO0 NDERL.NDER0 = 1 P3 EDRAK3_OE* EDRAK3* PFCR8.EDMAS3[A,B]= SYSCR.EXPE=1, EDMDR_3, EDRAKE=1 TIOCB2_OE TIOCB2 TPU.TIOR_2.IOB3 = 0, TPU.TIOR_2.IOB[1,0] = 01/10/11 PO15_OE PO15 NDERH.NDER15 = 1 EDRAK2_OE* EDRAK2* PFCR8.EDMAS2[A,B]= SYSCR.EXPE=1, EDMDR_2, EDRAKE=1 TIOCA2_OE TIOCA2 TPU.TIOR_2.IOA3 = 0, TPU.TIOR_2.IOA[1,0] = 01/10/11 PO14_OE PO14 NDERH.NDER14 = 1

Rev. 2.00 Jul. 31, 2008 Page 673 of 1438 REJ09B0365-0200 Port Output Specification Signal Name Output Signal Name Signal Selection Register Settings Peripheral Module Settings P3 5 EDACK3_OE EDACK3* PFCR8.EDMAS3[A,B]= SYSCR.EXPE=1, EDACR_3.AMS=1, EDMDR_3.EDACKE=1 DACK1B_OE DACK1 PFCR7.DMAS1[A,B] = 01 DMAC.DACR_1.AMS = 1, DMDR_1.DACKE = 1 TIOCB1_OE TIOCB1 TPU.TIOR_1.IOB3 = 0, TPU.TIOR_1.IOB[1,0] = 01/10/11 PO13_OE PO13 NDERH.NDER13 = 1 ETEND3_OE* ETEND3* PFCR8.EDMAS3[A,B] = 00 SYSCR.EXPE=1, EDMDR_3.ETEND=1 4 TEND1B_OE TEND1 PFCR7.DMAS1[A,B] = 01 DMDR_1.TENDE = 1 TIOCA1_OE TIOCA1 TPU.TIOR_1.IOA3 = 0, TPU.TIOR_1.IOA[1,0] = 01/10/11 PO12_OE PO12 NDERH.NDER12 = 1 3 TIOCD0_OE TIOCD0 TPU.TMDR.BFB = 0, TPU.TIORL_0.IOD3 = 0, TPU.TIORL_0.IOD[1,0] = 01/10/11 PO11_OE PO11 NDERH.NDER11 = 1 EDACK2_OE* EDACK2* PFCR8.EDMAS2[A,B] = 00 SYSCR.EXPE=1, EDACR_2.AMS=1, EDMDR_2.EDACKE=1 DACK0B_OE DACK0 PFCR7.DMAS0[A,B] = 01 DMAC.DACR_0.AMS = 1, DMDR_0.DACKE = 1 TIOCC0_OE TIOCC0 TPU.TMDR.BFA = 0, TPU.TIORL_0.IOC3 = 0, TPU.TIORL_0.IOD[1,0] = 01/10/11 PO10_OE PO10 NDERH.NDER10 = 1 ETEND2_OE* ETEND2* PFCR8.EDMAS2[A,B] = 00 SYSCR.EXPE=1, EDMDR_2.ETENDE=1 TEND0B_OE TEND0 PFCR7.DMAS0[A,B] = 01 DMDR_0.TENDE = 1 TIOCB0_OE TIOCB0 TPU.TIORH_0.IOB3 = 0, TPU.TIORH_0.IOB[1,0] = 01/10/11 PO9_OE PO9 NDERH.NDER9 = 1 0 TIOCA0_OE TIOCA0 TPU.TIORH_0.IOA3 = 0, TPU.TIOH_0.IOA[1,0] = 01/10/11 PO8_OE PO8 NDERH.NDER8 = 1

Rev. 2.00 Jul. 31, 2008 Page 674 of 1438 REJ09B0365-0200 Port Output Specification Signal Name Output Signal Name Signal Selection Register Settings Peripheral Module Settings 7 EDRAK1B_OE* EDRAK1* PFCR8.EDMAS1[A,B] = 01 SYSCR.EXPE=1, EDMDR_1.EDRAKE=1 6 EDRAK0B_OE* EDRAK0* PFCR8.EDMAS0[A,B] = 01 SYSCR.EXPE=1, EDMDR_0.EDRAKE=1 EDACK1B_OE* EDACK1* PFCR8.EDMAS1[A,B] = 00 SYSCR.EXPE=1, EDACR_1.AMS=1, EDMDR_1.EDACKE=1 DACK3_OE DACK3 PFCR7.DMAS3[A,B] = 01 DMAC.DACR_3.AMS = 1, DMDR_3.DACKE = 1 TMO3_OE TMO3 TMR.TCSR_3.OS[3,2] = 01/10/11 or TMR.TCSR_3.OS[1,0] = 01/10/11 SCK6_OE SCK6 When SCMR.SMIF = 1: SCR.TE = 1 or SCR.RE = 1 while SMR.GM = 0, SCR.CKE[1,0] = 01 or while SMR.GM = 1 When SCMR.SMIF = 0: SCR.TE = 1 or SCR.RE = 1 while SMR.C/A = 0, SCR.CKE[1,0] = 01 or while SMR.C/A = 1, SCR.CKE1 = 0 ETEND1B_OE* ETEND1* PFCR8.EDMAS1[A,B] = 01 SYSCR.EXPE=1, EDMDR_1.ETENDE=1 TEND3_OE TEND3 PFCR7.DMAS3[A,B] = 01 DMDR_3.TENDE = 1 3 TxD6_OE TxD6 SCR.TE = 1 EDACK0B_OE* EDACK0* PFCR8.EDMAS0[A,B] = 01 SYSCR.EXPE=1, EDACR_0.AMS=1, EDMDR_0.EDACKE=1 DACK2_OE DACK2 PFCR7.DMAS2[A,B] = 01 DMAC.DACR_2.AMS = 1, DMDR_2.DACKE = 1 TMO2_OE TMO2 TMR.TCSR_2.OS[3,2] = 01/10/11 or TMR.TCSR_2.OS[1,0] = 01/10/11 SCK4_OE SCK4 When SCMR.SMIF = 1: SCR.TE = 1 or SCR.RE = 1 while SMR.GM = 0, SCR.CKE [1,0] = 01 or while SMR.GM = 1 When SCMR.SMIF = 0: SCR.TE = 1 or SCR.RE = 1 while SMR.C/A = 0, SCR.CKE [1,0] = 01 or while SMR.C/A = 1, SCR.CKE 1 = 0 ETEND0B_OE* ETEND0* PFCR8.EDMAS0[A,B] = 01 SYSCR.EXPE=1, EDMDR_0.ETENDE=1 TEND2_OE TEND2 PFCR7.DMAS2[A,B] = 01 DMDR_2.TENDE = 1 0 TxD4_OE TxD4 SCR.TE = 1

Rev. 2.00 Jul. 31, 2008 Page 675 of 1438 REJ09B0365-0200 Port Output Specification Signal Name Output Signal Name Signal Selection Register Settings Peripheral Module Settings PA 7 B φ_OE B φ PADDR.PA7DDR = 1, SCKCR.PSTOP1 = 6 AH_OE AH SYSCR.EXPE = 1, MPXCR.MPXEn (n = 7 to 3) = 1 BS-B_OE BS PFCR2.BSS = 0 SYSCR.EXPE = 1, PFCR2.BSE = 1 AS_OE AS SYSCR.EXPE = 1, PFCR2.ASOE = 1 5 RD_OE RD SYSCR.EXPE = 1 4 LUB_OE LUB SYSCR.EXPE = 1, PFCR6.LHWROE = 1 or SRAMCR.BCSELn = 1 LHWR_OE LHWR SYSCR.EXPE = 1, PFCR6.LHWROE = 1 3 LLB_OE LLB SYSCR.EXPE = 1, SRAMCR.BCSELn = LLWR_OE LLWR SYSCR.EXPE = 1 2     1 BACK_OE BACK SYSCR.EXPE = 1,BCR1.BRLE = 1 (RD/ WR)-A_OE RD/ WR PFCR2.RDWRS = 0 SYSCR.EXPE = 1, PFCR2.RDWRE = 1 or SRAMCR.BCSELn = 1 0 BS-A_OE BS PFCR2.BSS = 0 SYSCR.EXPE = 1, PFCR2.BSE = 1 BREQO_OE BREQO SYSCR.EXPE = 1, BCR1.BRLE = 1, BCR1.BREQOE = 1 SDφ_OE* SDφ* MD3 = 1 7 CS7D_OE CS7 PFCR1.CS7S[A,B] = 11 SYSCR.EXPE = 1, PFCR.CS7E = 1 6 (RD/ WR)-B_OE RD/ WR PFCR2.RDWRS = 1 SYSCR.EXPE = 1, PFCR2.RDWRE = 1, or SRAMCR.BCSELn = 1 CS6D_OE CS6 PFCR1.CS6S[A,B] = 11 SYSCR.EXPE = 1, PFCR0.CS6E = 1 CKE_OE* CKE* SYSCR.EXPE = 1, DRAMCR.DRAME=1. DRAMCR.ETYPE=1, DRAMCR.OEE=1 OE_OE* OE* SYSCR.EXPE = 1, DRAMCR.DRAME=1. DRAMCR.DTYPE=0, DRAMCR.OEE=1 CS5D_OE CS5 PFCR1.CS5S[A,B] = 11 SYSCR.EXPE = 1, PFCR0.CS5E = 1 4 WE_OE* WE* SYSCR.EXPE=1,DRAMCR.DRAME=1 PB CS4B_OE CS4 PFCR1.CS4S[A,B] = 01 SYSCR.EXPE = 1, PFCR0.CS4E = 1

Rev. 2.00 Jul. 31, 2008 Page 676 of 1438 REJ09B0365-0200 Port Output Specification Signal Name Output Signal Name Signal Selection Register Settings Peripheral Module Settings

3 CAS_OE*

CAS* SYSCR.EXPE=1,DRAMCR.DRAME=1, DRAMCR.DTYPE=1 CS3A_OE CS3 PFCR2.CS3S = 0 SYSCR.EXPE = 1, PFCR0.CS3E = 1 CS7A_OE CS7 PFCR1.CS7S[A,B] = 00 SYSCR.EXPE = 1, PFCR0.CS7E = 1 2 RAS_OE* RAS* SYSCR.EXPE = 1, DRAMCR.DRAME = 1 CS2A_OE CS2 PFCR2.CS2S = 0 SYSCR.EXPE = 1, PFCR0.CS2E = 1 CS6A_OE CS6 PFCR1.CS6S[A,B] = 00 SYSCR.EXPE = 1, PFCR0.CS6E = 1 1 CS1_OE CS1 SYSCR.EXPE = 1, PFCR0.CS1E = 1 CS2B_OE CS2 PFCR2.CS2S = 1 SYSCR.EXPE = 1, PFCR0.CS2E = 1 CS5A_OE CS5 PFCR1.CS5S[A,B] = 00 SYSCR.EXPE = 1, PFCR0.CS5E = 1 CS6B_OE CS6 PFCR1.CS6S[A,B] = 01 SYSCR.EXPE = 1, PFCR0.CS6E = 1 CS7B_OE CS7 PFCR1.CS7S[A,B] = 01 SYSCR.EXPE = 1, PFCR0.CS7E = 1 0 CS0_OE CS0 SYSCR.EXPE = 1, PFCR0.CS0E = 1 CS4A_OE CS4 PFCR1.CS4S[A,B] = 00 SYSCR.EXPE = 1, PFCR0.CS4E = 1 PB CS5B_OE CS5 PFCR1.CS5S[A,B] = 01 SYSCR.EXPE = 1, PFCR0.CS5E = 1 3 LLCAS_OE* LLCAS SYSCR.EXPE = 1, DRAMCR.DRAME = 1 DRAMCR.DTYPE = 0 DQMLL_OE* DQMLL SYSCR.EXPE = 1, DRAMCR.DRAME = 1 DRAMCR.DTYPE = 1 2 LUCAS_OE* LUCAS SYSCR.EXPE=1,ABWCR.[ABWH2, ABWL2]=x0/01,DRAMCR.DRAME=1, DRAMCR.DTYPE=0 DQMLU_OE* DQMLU SYSCR.EXPE=1,ABWCR.[ABWH2, ABWL2]=x0/01,DRAMCR.DRAME=1, DRAMCR.DTYPE=1 1 CS4C_OE CS4 PFCR1.CS4S[A,B] = 10 SYSCR.EXPE = 1, PFCR0.CS4E = 1 CS5C_OE CS5 PFCR1.CS5S[A,B] = 10 SYSCR.EXPE = 1, PFCR0.CS5E = 1 CS6C_OE CS6 PFCR1.CS6S[A,B] = 10 SYSCR.EXPE = 1, PFCR0.CS6E = 1 CS7C_OE CS7 PFCR1.CS7S[A,B] = 10 SYSCR.EXPE = 1, PFCR0.CS7E = 1 PC 0 CS3B_OE CS3 PFCR2.CS3S = 1 SYSCR.EXPE = 1, PFCR0.CS3E = 1

Rev. 2.00 Jul. 31, 2008 Page 677 of 1438 REJ09B0365-0200 Port Output Specification Signal Name Output Signal Name Signal Selection Register Settings Peripheral Module Settings PD 7 A7_OE A7 SYSCR.EXPE = 1, PDDDR.PD7DDR = 1 6 A6_OE A6 SYSCR.EXPE = 1, PDDDR.PD6DDR = 1 5 A5_OE A5 SYSCR.EXPE = 1, PDDDR.PD5DDR = 1 4 A4_OE A4 SYSCR.EXPE = 1, PDDDR.PD4DDR = 1 3 A3_OE A3 SYSCR.EXPE = 1, PDDDR.PD3DDR = 1 2 A2_OE A2 SYSCR.EXPE = 1, PDDDR.PD2DDR = 1 1 A1_OE A1 SYSCR.EXPE = 1, PDDDR.PD1DDR = 1 0 A0_OE A0 SYSCR.EXPE = 1, PDDDR.PD0DDR = 1 7 A15_OE A15 SYSCR.EXPE = 1, PEDDR.PE7DDR = 1 6 A14_OE A14 SYSCR.EXPE = 1, PEDDR.PE6DDR = 1 5 A13_OE A13 SYSCR.EXPE = 1, PEDDR.PE5DDR = 1 4 A12_OE A12 SYSCR.EXPE = 1, PEDDR.PE4DDR = 1 3 A11_OE A11 SYSCR.EXPE = 1, PEDDR.PE3DDR = 1 2 A10_OE A10 SYSCR.EXPE = 1, PEDDR.PE2DDR = 1 1 A9_OE A9 SYSCR.EXPE = 1, PEDDR.PE1DDR = 1 PE 0 A8_OE A8 SYSCR.EXPE = 1, PEDDR.PE0DDR = 1 PF 7 A23A_OE A23 SYSCR.EXPE = 1, PFCR4.A23E = 1 SCK5_OE SCK5 When SCMR.SMIF = 1: SCR.TE = 1 or SCR.RE = 1 while SMR.GM = 0, SCR.CKE[1,0] = 01or while SMR.GM = 1 When SCMR.SMIF = 0: SCR.TE = 1 or SCR.RE = 1 while SMR.C/A = 0, SCR.CKE[1,0] = 01 or while SMR.C/A = 1, SCR.CKE1 = 0 6 A22A_OE A22 SYSCR.EXPE = 1, PFCR4.A22E = 1 5 A21A_OE A21 SYSCR.EXPE = 1, PFCR4.A21E = 1 TxD5_OE TxD5 SCR.TE = 1 IrTxD_OE IrTxD SCR.TE = 1, IrCR.IrE = 1 4 A20_OE A20 SYSCR.EXPE = 1, PFCR4.A20E = 1 3 A19_OE A19 SYSCR.EXPE = 1, PFCR4.A19E = 1 2 A18_OE A18 SYSCR.EXPE = 1, PFCR4.A18E = 1 1 A17_OE A17 SYSCR.EXPE = 1, PFCR4.A17E = 1

Rev. 2.00 Jul. 31, 2008 Page 678 of 1438 REJ09B0365-0200 Port Output Specification Signal Name Output Signal Name Signal Selection Register Settings Peripheral Module Settings PF 0 A16_OE A16 SYSCR.EXPE = 1, PFCR4.A16E = 1 PH 7 D7_E D7 SYSCR.EXPE = 1 6 D6_E D6 SYSCR.EXPE = 1 5 D5_E D5 SYSCR.EXPE = 1 4 D4_E D4 SYSCR.EXPE = 1 3 D3_E D3 SYSCR.EXPE = 1 2 D2_E D2 SYSCR.EXPE = 1 1 D1_E D1 SYSCR.EXPE = 1 0 D0_E D0 SYSCR.EXPE = 1 PI 7 D15_E D15 SYSCR.EXPE = 1, ABWCR.ABW[H,L]n = 6 D14_E D14 SYSCR.EXPE = 1, ABWCR.ABW[H,L]n = 5 D13_E D13 SYSCR.EXPE = 1, ABWCR.ABW[H,L]n = 4 D12_E D12 SYSCR.EXPE = 1, ABWCR.ABW[H,L]n = 3 D11_E D11 SYSCR.EXPE = 1, ABWCR.ABW[H,L]n = 2 D10_E D10 SYSCR.EXPE = 1, ABWCR.ABW[H,L]n = 1 D9_E D9 SYSCR.EXPE = 1, ABWCR.ABW[H,L]n = 0 D8_E D8 SYSCR.EXPE = 1, ABWCR.ABW[H,L]n = PJ 7 TIOCB8_OE TIOCB8 TPU.TIOR_8.IOB3 = 0, TPU.TIOR_8.IOB[1,0] = 01/10/11 PO23_OE PO23 NDERL_1.NDER23 = 1 TIOCA8_OE TIOCA8 TPU.TIOR_8.IOA3 = 0, TPU.TIOR_8.IOA[1,0] = 01/10/11 PO22_OE PO22 NDERL_1.NDER22 = 1 TIOCB7_OE TIOCB7 TPU.TIOR_7.IOB3 = 0, TPU.TIOR_7.IOB[1,0] = 01/10/11 PO21_OE PO21 NDERL_1.NDER21 = 1

Rev. 2.00 Jul. 31, 2008 Page 679 of 1438 REJ09B0365-0200 Port Output Specification Signal Name Output Signal Name Signal Selection Register Settings Peripheral Module Settings PJ TIOCA7_OE TIOCA7 TPU.TIOR_7.IOA3 = 0, TPU.TIOR_7.IOA[1,0] = 01/10/11 PO20_OE PO20 NDERL_1.NDER20 = 1 TIOCD6_OE TIOCD6 TPU.TMDR_6.BFB = 0, TPU.TIORL_6.IOD3 = 0, TPU.TIORL_6.IOD[1,0] = 01/10/11 PO19_OE PO19 NDERL_1.NDER19 = 1 TIOCC6_OE TIOCC6 TPU.TMDR_6.BFA = 0, TPU.TIORL_6.IOC3 = 0, TPU.TIORL_6.IOC[1,0] = 01/10/11 PO18_OE PO18 NDERL_1.NDER18 = 1 TIOCB6_OE TIOCB6 TPU.TIORH_6.IOB3 = 0, TPU.TIORH_6.IOB[1,0] = 01/10/11 PO17_OE PO17 NDERL_1.NDER17 = 1 TIOCA6_OE TIOCA6 TPU.TIORH_6.IOA3 = 0, TPU.TIORH_6.IOA[1,0] = 01/10/11 PO16_OE PO16 NDERL_1.NDER16 = 1 PK TIOCB11_OE TIOCB11 TPU.TIOR_11.IOB3 = 0, TPU.TIOR_11.IOB[1,0] = 01/10/11 PO31_OE PO31 NDERH_1.NDER31 = 1 TIOCA11_OE TIOCA11 TPU.TIOR_11.IOA3 = 0, TPU.TIOR_11.IOA[1,0] = 01/10/11 PO30_OE PO30 NDERH_1.NDER30 = 1 TIOCB10_OE TIOCB10 TPU.TIOR_10.IOB3 = 0, TPU.TIOR_10.IOB[1,0] = 01/10/11 PO29_OE PO29 NDERH_1.NDER29 = 1 TIOCA10_OE TIOCA10 TPU.TIOR_10.IOA3 = 0, TPU.TIOR_10.IOA[1,0] = 01/10/11 PO28_OE PO28 NDERH_1.NDER28 = 1 TIOCD9_OE TIOCD9 TPU.TMDR_9.BFB = 0, TPU.TIORL_9.IOD3 = 0, TPU.TIORL_9.IOD[1,0] = 01/10/11 PO27_OE PO27 NDERH_1.NDER27 = 1

Rev. 2.00 Jul. 31, 2008 Page 680 of 1438 REJ09B0365-0200 Port Output Specification Signal Name Output Signal Name Signal Selection Register Settings Peripheral Module Settings PK TIOCC9_OE TIOCC9 TPU.TMDR_9.BFA = 0, TPU.TIORL_9.IOC3 = 0, TPU.TIORL_9.IOC[1,0] = 01/10/11 PO26_OE PO26 NDERH_1.NDER26 = 1 TIOCB9_OE TIOCB9 TPU.TIORH_9.IOB3 = 0, TPU.TIORH_9.IOB[1,0] = 01/10/11 PO25_OE PO25 NDERH_1.NDER25 = 1 TIOCA9_OE TIOCA9 TPU.TIORH_9.IOA3 = 0, TPU.TIORH_9.IOA[1,0] = 01/10/11 PO24_OE PO24 NDERH_1.NDER24 = 1 PN 3 SCL3_OE SCL2 ICCRA.ICE = 1 2 SDA3_OE SDA3 ICCRA.ICE = 1 1 SCL2_OE SCL2 ICCRA.ICE = 1 0 SDA2_OE SDA2 ICCRA.ICE = 1 Note: * Supported only by the H8SX/ 1648G Group and H8SX/1648H Group.

Rev. 2.00 Jul. 31, 2008 Page 681 of 1438 REJ09B0365-0200

13.3 Port Function Controller

The port function controller controls the I/O ports. The port function controller incorporates the following registers.

• Port function control register 0 (PFCR0)
• Port function control register 1 (PFCR1)
• Port function control register 2 (PFCR2)
• Port function control register 4 (PFCR4)
• Port function control register 6 (PFCR6)
• Port function control register 7 (PFCR7)
• Port function control register 8 (PFCR8)*
• Port function control register 9 (PFCR9)
• Port function control register A (PFCRA)
• Port function control register B (PFCRB)
• Port function control register C (PFCRC)
• Port function control register D (PFCRD) Note: * Supported only by the H8SX/1648G Group and H8SX/1648H Group.

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13.3.1 Port Function Control Register 0 (PFCR0)

PFCR0 enables/disables the CS output. Bit Bit Name Initial Value R/W Note: * 1 in external extended mode; 0 in other modes. CS7E R/W CS6E R/W CS5E R/W CS4E R/W CS3E R/W CS2E R/W CS1E R/W CS0E Undefined* R/W Bit Bit Name Initial Value R/W Description

7 CS7E 0 R/W

6 CS6E 0 R/W

5 CS5E 0 R/W

4 CS4E 0 R/W

3 CS3E 0 R/W

2 CS2E 0 R/W

1 CS1E 0 R/W

0 CS0E Undefined * R/W

These bits enable/disable the corresponding CSn output. 0: Pin functions as I/O port 1: Pin functions as CSn output pin (n = 7 to 0) Note: * 1 in external extended mode, 0 in other modes.

13.3.2 Port Function Control Register 1 (PFCR1)

PFCR1 selects the CS output pins. Bit Bit Name Initial Value R/W CS7SA R/W CS7SB R/W CS6SA R/W CS6SB R/W CS5SA R/W CS5SB R/W CS4SA R/W CS4SB R/W

Rev. 2.00 Jul. 31, 2008 Page 683 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description CS7SA* CS7SB* R/W R/W CS7 Output Pin Select Selects the output pin for CS7 when CS7 output is enabled (CS7E = 1) 00: Specifies pin PB3 as CS7-A output 01: Specifies pin PB1 as CS7-B output 10: Specifies pin PC1 as CS7-C output 11: Specifies pin PB7 as CS7-D output CS6SA* CS6SB* R/W R/W CS6 Output Pin Select Selects the output pin for CS6 when CS6 output is enabled (CS6E = 1) 00: Specifies pin PB2 as CS6-A output 01: Specifies pin PB1 as CS6-B output 10: Specifies pin PC1 as CS6-C output 11: Specifies pin PB6 as CS6-D output CS5SA* CS5SB* R/W R/W CS5 Output Pin Select Selects the output pin for CS5 when CS5 output is enabled (CS5E = 1) 00: Specifies pin PB1 as CS5-A output 01: Specifies pin PB0 as CS5-B output 10: Specifies pin PC1 as CS5-C output 11: Specifies pin PB5 as CS5-D output CS4SA* CS4SB* R/W R/W CS4 Output Pin Select Selects the output pin for CS4 when CS4 output is enabled (CS4E = 1) 00: Specifies pin PB0 as CS4-A output 01: Specifies pin PB4 as CS4-B output 10: Specifies pin PC1 as CS4-C output 11: Setting prohibited Note: * If multiple CS outputs are specified to a single pin according to the CSn output pin select bits (n = 4 to 7), multiple CS signals are output from the pin. For details, see section 9.5.3, Chip Select Signals.

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13.3.3 Port Function Control Register 2 (PFCR2)

PFCR2 selects the CS output pin, enables/disables bus control I/O, and selects the bus control I/O pins. Bit Bit Name Initial Value R/W CS3S R/W CS2S R/W BSS R/W BSE R/W RDWRS R/W RDWRE R/W ASOE R/W WAITS R/W Bit Bit Name Initial Value R/W Description

7 CS3S *

0 R/W CS3 Output Pin Select

Selects the output pin for CS3 when CS3 output is enabled (CS3E = 1) 0: Specifies pin PB3 as CS3-A output pin 1: Specifies pin PB0 as CS3-B output pin

6 CS2S *

0 R/W CS2 Output Pin Select

Selects the output pin for CS2 when CS2 output is enabled (CS2E = 1) 0: Specifies pin PB2 as CS2-A output pin 1: Specifies pin PB1 as CS2-B output pin

5 BSS 0 R/W BS Output Pin Select

0: Specifies pin PA0 as BS-A output pin 1: Specifies pin PA6 as BS-B output pin

4 BSE 0 R/W BS Output Enable

Enables/disables the BS output 0: Disables the BS output 1: Enables the BS output

3 RDWRS *

0 R/W RD/ WR Output Pin Select

Selects the output pin for RD/WR 0: Specifies pin PA1 as RD/WR-A output pin 1: Specifies pin PB6 as RD/WR-B output pin

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2 RDWRE *

0 R/W RD/ WR Output Enable

Enables/disables the RD/WR output 0: Disables the RD/WR output 1: Enables the RD/WR output

1 ASOE 1 R/W AS Output Enable

Enables/disables the AS output 0: Specifies pin PA6 as I/O port 1: Specifies pin PA6 as AS output pin

0 WAITS 0 R/W WAIT Input Pin Select

Selects the input pin for the wait request signal when accessing external spaces. 0: Specifies pin PA2 as WAIT-A input pin 1: Specifies pin PC0 as WAIT-B input pin Notes: 1. If multiple CS outputs are specified to a single pin according to the CSn output pin select bit (n = 2, 3), multiple CS signals are output from the pin. For details, see section 9.5.3, Chip Select Signals. 2. If an area is specified as a byte cont rol SDRAM space, the pin functions as RD/WR output regardless of the RDWRE bit value.

13.3.4 Port Function Control Register 4 (PFCR4)

PFCR4 enables or disables the address output. Bit Bit Name Initial Value R/W A23E R/W A22E R/W A21E R/W A20E 0/1* R/W A19E 0/1* R/W A18E 0/1* R/W A17E 0/1* R/W A16E 0/1* R/W Bit Bit Name Initial Value R/W Description

7 A23E 0 R/W Address A23 Enable

Enables/disables the address output (A23) 0: Disables the A23 output 1: Enables the A23 output

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6 A22E 0 R/W Address A22 Enable

Enables/disables the address output (A22) 0: Disables the A22 output 1: Enables the A22 output

5 A21E 0 R/W Address A21 Enable

Enables/disables the address output (A21) 0: Disables the A21 output 1: Enables the A21 output

4 A20E 0/1 * R/W Address A20 Enable

Enables/disables the address output (A20) 0: Disables the A20 output 1: Enables the A20 output

3 A19E 0/1 * R/W Address A19 Enable

Enables/disables the address output (A19) 0: Disables the A19 output 1: Enables the A19 output

2 A18E 0/1 * R/W Address A18 Enable

Enables/disables the address output (A18) 0: Disables the A18 output 1: Enables the A18 output

1 A17E 0/1 * R/W Address A17 Enable

Enables/disables the address output (A17) 0: Disables the A17 output 1: Enables the A17 output

0 A16E 0/1 * R/W Address A16 Enable

Enables/disables the address output (A16) 0: Disables the A16 output 1: Enables the A16 output Notes: * The initial value changes depending on the operating mode. The initial value is 1 when the on-chip RO M is disabled, and 0 when the on-chip ROM is enabled.

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13.3.5 Port Function Control Register 6 (PFCR6)

PFCR6 selects the TPU clock input pin. Bit Bit Name Initial Value R/W R/W LHWROE R/W R/W R TCLKS R/W R/W ADTRG1S R/W ADTRG0S R/W Bit Bit Name Initial Value R/W Description 7  1 R/W Reserved This bit is always read as 1. The write value should always be 1.

6 LHWROE 1 R/W LHWR Output Enable

Enables/disables LHWR output (valid in external extended mode). 0: Specifies pin PA4 as I/O port 1: Specifies pin PA4 as LHWR output pin 5  1 R/W Reserved This bit is always read as 1. The write value should always be 1. 4  0 R Reserved This is a read-only bit and cannot be modified.

3 TCLKS 0 R/W TPU External Clock Input Pin Select

Selects the TPU external clock input pins. 0: Specifies pins P32, P33, P35, and P37 as external clock input pins. 1: Specifies pins P14 to P17 as external clock input pins. 2  All 0 R/W Reserved These bits are always read as 0. The write value should always be 0.

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1 ADTRG1S 0 R/W ADTRG1S Input Pin Select

Selects the external trigger input pins of the A/D converter (unit1). 0: Specifies pin P17 as ADTRG1-A input pin. 1: Specifies pin PC0 as ADTRG1-B input pin.

0 ADTRG0S 0 R/W ADTRG0S Input Pin Select

Selects the external trigger input pins of the A/D converter (unit0). 0: Specifies pin P13 as ADTRG0-A input pin. 1: Specifies pin PB6 as ADTRG0-B input pin.

13.3.6 Port Function Control Register 7 (PFCR7)

PFCR7 selects the DMAC I/O pins (DREQ, DACK, and TEND). Bit Bit Name Initial Value R/W DMAS3A R/W DMAS3B R/W DMAS2A R/W DMAS2B R/W DMAS1A R/W DMAS1B R/W DMAS0A R/W DMAS0B R/W Bit Bit Name Initial Value R/W Description DMAS3A DMAS3B R/W R/W DMAC control pin select Selects the I/O port to control DMAC_3. 00: Setting invalid 01: Specifies pins P63 to P65 as DMAC control pins 10: Setting prohibited 11: Setting prohibited DMAS2A DMAS2B R/W R/W DMAC control pin select Selects the I/O port to control DMAC_2. 00: Setting invalid 01: Specifies pins P60 to P62 as DMAC control pins 10: Setting prohibited 11: Setting prohibited

Rev. 2.00 Jul. 31, 2008 Page 689 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description DMAS1A DMAS1B R/W R/W DMAC control pin select Selects the I/O port to control DMAC_1. 00: Specifies pins P14 to P16 as DMAC control pins 01: Specifies pins P33 to P35 as DMAC control pins 10: Setting prohibited 11: Setting prohibited DMAS0A DMAS0B R/W R/W DMAC control pin select Selects the I/O port to control DMAC_0. 00: Specifies pins P10 to P12 as DMAC control pins 01: Specifies pins P30 to P32 as DMAC control pins 10: Setting prohibited 11: Setting prohibited

13.3.7 Port Function Control Register 8 (PFCR8)*

Note: * Supported only by the H8SX/1648G Group and H8SX/1648H Group. PFCR8 selects the EXDMAC I/O pins (EDREQ, EDACK, ETEND, and EDRAK ). Bit Bit name Initial vaue: R/W: EDMAS3A R/W EDMAS3B R/W EDMAS2A R/W EDMAS2B R/W EDMAS1A R/W EDMAS1B R/W EDMAS0A R/W EDMAS0B R/W Bit Bit Name Initial Value R/W Description EDMAS3A EDMAS3B R/W R/W EXDMAC control pin select Selects the I/O port to control EXDMAC_3. 00: Specifies pins P33 to P35, and P37 as EXDMAC control pins 01: Setting prohibited 10: Setting prohibited 11: Setting prohibited

Rev. 2.00 Jul. 31, 2008 Page 690 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description EDMAS2A EDMAS2B R/W R/W EXDMAC control pin select Selects the I/O port to control EXDMAC_2. 00: Specifies pins P30 to P32, and P36 as EXDMAC control pins 01: Setting prohibited 10: Setting prohibited 11: Setting prohibited EDMAS1A EDMAS1B R/W R/W EXDMAC control pin select Selects the I/O port to control EXDMAC_1. 00: Specifies pins P14 to P17 as EXDMAC control pins 01: Specifies pins P63 to P65, and P67 as EXDMAC control pins 10: Setting prohibited 11: Setting prohibited EDMAS0A EDMAS0B R/W R/W EXDMAC control pin select Selects the I/O port to control EXDMAC_0. 00: Specifies pins P10 to P13 as EXDMAC control pins 01: Specifies pins P60 to P62, and P66 as EXDMAC control pins 10: Setting prohibited 11: Setting prohibited

13.3.8 Port Function Control Register 9 (PFCR9)

PFCR9 selects the multiple functions for the TPU I/O pins. Bit Bit Name Initial Value R/W TPUMS5 R/W TPUMS4 R/W TPUMS3A R/W TPUMS3B R/W TPUMS2 R/W TPUMS1 R/W TPUMS0A R/W TPUMS0B R/W

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7 TPUMS5 0 R/W TPU I/O Pin Multiplex Function Select

0: Specifies pin P26 as output compare output and input capture 1: Specifies P27 as input capture input and P26 as output compare

6 TPUMS4 0 R/W TPU I/O Pin Multiplex Function Select

0: Specifies P25 as output compare output and input capture 1: Specifies P24 as input capture input and P25 as output compare

5 TPUMS3A 0 R/W TPU I/O Pin Multiplex Function Select

0: Specifies P21 as output compare output and input capture 1: Specifies P20 as input capture input and P21 as output compare

4 TPUMS3B 0 R/W TPU I/O Pin Multiplex Function Select

0: Specifies P22 as output compare output and input capture 1: Specifies P23 as input capture input and P22 as output compare

3 TPUMS2 0 R/W TPU I/O Pin Multiplex Function Select

0: Specifies P36 as output compare output and input capture 1: Specifies P37 as input capture input and P36 as output compare

2 TPUMS1 0 R/W TPU I/O Pin Multiplex Function Select

0: Specifies P34 as output compare output and input capture 1: Specifies P35 as input capture input and P34 as output compare

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1 TPUMS0A 0 R/W TPU I/O Pin Multiplex Function Select

0: Specifies P30 as output compare output and input capture 1: Specifies P31 as input capture input and P30 as output compare

0 TPUMS0B 0 R/W TPU I/O Pin Multiplex Function Select

0: Specifies P32 as output compare output and input capture 1: Specifies P33 as input capture input and P32 as output compare

13.3.9 Port Function Control Register A (PFCRA)

PFCRA selects the multiple functions for the TPU (unit 1) I/O pins. Do not access this register because writing to or reading from the bits in this register is not effective when the PCJKE bit in PFCRD is cleared to 0. Bit Bit Name Initial Value R/W TPUMS11 R/W TPUMS10 R/W TPUMS9A R/W TPUMS9B R/W TPUMS8 R/W TPUMS7 R/W TPUMS6A R/W TPUMS6B R/W Bit Bit Name Initial Value R/W Description

7 TPUMS11 0 R/W TPU I/O Pin Multiplex Function Select

0: Specifies PK6 as output compare output and input capture 1: Specifies PK7 as input capture input and PK6 as output compare

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6 TPUMS10 0 R/W TPU I/O Pin Multiplex Function Select

0: Specifies PK4 as output compare output and input capture 1: Specifies PK5 as input capture input and PK4 as output compare

5 TPUMS9A 0 R/W TPU I/O Pin Multiplex Function Select

0: Specifies PK0 as output compare output and input capture 1: Specifies PK1 as input capture input and PK0 as output compare

4 TPUMS9B 0 R/W TPU I/O Pin Multiplex Function Select

0: Specifies PK2 as output compare output and input capture 1: Specifies PK3 as input capture input and PK2 as output compare

3 TPUMS8 0 R/W TPU I/O Pin Multiplex Function Select

0: Specifies PJ6 as output compare output and input capture 1: Specifies PJ7 as input capture input and PJ6 as output compare

2 TPUMS7 0 R/W TPU I/O Pin Multiplex Function Select

0: Specifies PJ4 as output compare output and input capture 1: Specifies PJ5 as input capture input and PJ4 as output compare

1 TPUMS6A 0 R/W TPU I/O Pin Multiplex Function Select

0: Specifies PJ0 as output compare output and input capture 1: Specifies PJ1 as input capture input and PJ0 as output compare

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0 TPUMS6B 0 R/W TPU I/O Pin Multiplex Function Select

0: Specifies PJ2 as output compare output and input capture 1: Specifies PJ3 as input capture input and PJ2 as output compare

13.3.10 Port Function Control Register B (PFCRB)

• H8SX/1648 Group, H8SX/1648A Group PFCRB selects the input pins for IRQ15 to IRQ8.
• H8SX/1648L Group PFCRB selects IRQ14 interrupt / LVD interrupt* , and the input pins for the IRQ15 and IRQ13 to IRQ8.
• H8SX/1648G Group PFCRB selects IRQ15, 32KOVI* , and the input pins for IRQ13 to IRQ8.
• H8SX/1648HGroup PFCRB selects IRQ15, 32KOVI* , IRQ14 interrupt / LVD interrupt* , and the input pins for IRQ13 to IRQ8. Bit Bit Name Initial Value: R/W: ITS15 R/W ITS14 R/W* ITS13 R/W ITS12 R/W ITS11 R/W ITS10 R/W ITS9 R/W ITS8 R/W Notes: 1. Supported only by the H8SX/1648L Group and the H8SX/1648H Group. 2. Supported only by the H8SX/1648G Group and the H8SX/1648H Group.

Rev. 2.00 Jul. 31, 2008 Page 695 of 1438 REJ09B0365-0200

• H8SX/1648, and H8SX/1648A Groups Bit Bit Name Initial Value R/W Description

7 ITS15 0 R/W IRQ15 Pin Select

Selects an input pin for IRQ15. 0: Selects pin P27 as IRQ15-A input 1: Selects pin P67 as IRQ15-B input 6  0 R Reserved This bit is always read as 0. The write value should always be 0.

• H8SX/1648L Group Bit Bit Name Initial Value R/W Description

Selects an input pin for IRQ15. 0: Selects pin P27 as IRQ15-A input 1: Selects pin P67 as IRQ15-B input

6 ITS14 0 R/W LVD Interrupt / IRQ14 Interrupt Select

Selects whether the LVD interrupt or IRQ14 interrupt is to be used. 0: Selects pin P26 as IRQ14-A 1: Selects LVD interrupt

• H8SX/1648G Group Bit Bit Name Initial Value R/W Description

7 ITS15 0 R/W 32KOVI / IRQ15 Interrupt Select

Selects whether 32KOVI interrupt or IRQ15 interrupt is to be used. 0: Selects the 32KOVI interrupt in the TM32K 1: Selects pin P67 as IRQ15-B input 6  0 R Reserved This bit is always read as 0. The write value should always be 0.

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• H8SX/1648H Group Bit Bit Name Initial Value R/W Description

Selects whether 32KOVI interrupt or IRQ15 interrupt is to be used. 0: Selects the 32KOVI interrupt in the TM32K 1: Selects pin P67 as IRQ15-B input Selects whether the LVD interrupt or IRQ14 interrupt is to be used. 0: Selects pin P26 as IRQ14-A 1: Selects LVD interrupt

• Each Group in Common Bit Bit Name Initial Value R/W Description

5 ITS13 0 R/W IRQ13 Pin Select

Selects an input pin for IRQ13. 0: Selects pin P25 as IRQ13-A input 1: Selects pin P65 as IRQ13-B input

4 ITS12 0 R/W IRQ12 Pin Select

Selects an input pin for IRQ12. 0: Selects pin P24 as IRQ12-A input 1: Selects pin P64 as IRQ12-B input

3 ITS11 0 R/W IRQ11 Pin Select

Selects an input pin for IRQ11. 0: Selects pin P23 as IRQ11-A input 1: Selects pin P63 as IRQ11-B input

2 ITS10 0 R/W IRQ10 Pin Select

Selects an input pin for IRQ10. 0: Selects pin P22 as IRQ10-A input 1: Selects pin P62 as IRQ10-B input

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1 ITS9 0 R/W IRQ9 Pin Select

Selects an input pin for IRQ9. 0: Selects pin P21 as IRQ9-A input 1: Selects pin P61 as IRQ9-B input

0 ITS8 0 R/W IRQ8 Pin Select

Selects an input pin for IRQ8. 0: Selects pin P20 as IRQ8-A input 1: Selects pin P60 as IRQ8-B input

13.3.11 Port Function Control Register C (PFCRC)

PFCRC selects input pins for IRQ7 to IRQ0. Bit Bit Name Initial Value R/W ITS7 R/W ITS6 R/W ITS5 R/W ITS4 R/W ITS3 R/W ITS2 R/W ITS1 R/W ITS0 R/W Bit Bit Name Initial Value R/W Description

7 ITS7 0 R/W IRQ7 Pin Select

Selects an input pin for IRQ7. 0: Selects pin P17 as IRQ7-A input 1: Selects pin P57 as IRQ7-B input

6 ITS6 0 R/W IRQ6 Pin Select

Selects an input pin for IRQ6. 0: Selects pin P16 as IRQ6-A input 1: Selects pin P56 as IRQ6-B input

5 ITS5 0 R/W IRQ5 Pin Select

Selects an input pin for IRQ5. 0: Selects pin P15 as IRQ5-A input 1: Selects pin P55 as IRQ5-B input

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4 ITS4 0 R/W IRQ4 Pin Select

Selects an input pin for IRQ4. 0: Selects pin P14 as IRQ4-A input 1: Selects pin P54 as IRQ4-B input

3 ITS3 0 R/W IRQ3 Pin Select

Selects an input pin for IRQ3. 0: Selects pin P13 as IRQ3-A input 1: Selects pin P53 as IRQ3-B input

2 ITS2 0 R/W IRQ2 Pin Select

Selects an input pin for IRQ2. 0: Selects pin P12 as IRQ2-A input 1: Selects pin P52 as IRQ2-B input

1 ITS1 0 R/W IRQ1 Pin Select

Selects an input pin for IRQ1. 0: Selects pin P11 as IRQ1-A input 1: Selects pin P51 as IRQ1-B input

0 ITS0 0 R/W IRQ0 Pin Select

Selects an input pin for IRQ0. 0: Selects pin P10 as IRQ0-A input 1: Selects pin P50 as IRQ0-B input

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13.3.12 Port Function Control Register D (PFCRD)

PFCRD enables or disables the port J and port K pin functions. Bit Bit Name Initial Value R/W PCJKE R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description

7 PCJKE * 0 R/W Ports J and K Enable

Enables or disables the port J and K pin functions. 0: Ports J and K are disabled. 1: Port s J and K are enabled (ports D and E are disabled). 6 to 0  0 R/W Reserved These bits are always read as 0 and cannot be modified. The initial value should not be changed. Note: * This bit is only effective in single-chip mode. In other modes, do not change the initial value of this bit.

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13.4 Usage Notes

13.4.1 Notes on Input Buffer Control Register (ICR) Setting

1. When the ICR setting is changed, the LSI may ma lfunction due to an edge occurred internally according to the pin state. Before changing the ICR setting, fix the pin state high or disable the input function corresponding to the pin by the on-chip peripheral module settings. 2. If an input is enabled by setting ICR while multiple input functions are assigned to the pin, the pin state is reflected in all the inputs. Care must be taken for each module settings for unused input functions. 3. When a pin is used as an output, data to be output from the pin will be latched as the pin state if the input function corresponding to the pin is enabled. To use the pin as an output, disable the input function for the pin by setting ICR.

13.4.2 Notes on Port Function Control Register (PFCR) Settings

1. Port function controller controls the I/O port. Before enabling a port function, select the input/output destination. 2. When changing input pins, this LSI may malfunction due to the internal edge generated by the pin level difference before and after the change.

• To change input pins, the following procedure must be performed. A. Disable the input function by the corresponding on-chip peripheral module settings B. Select another input pin by PFCR C. Enable its input function by the corresponding on-chip peripheral module settings 3. If a pin function has both a select bit that modifies the input/output destination and an enable bit that enables the pin function, first specify the input/output destination by the selection bit and then enable the pin function by the enable bit. 4. The value of the PCJKE bit must be set during the initial setting immediately after a power-on. Set the PCJKE bit first and then set other bits in PFCR as required. 5. Do not change the value of th e PCJKE bit once it has been set.

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 701 of 1438 REJ09B0365-0200 Section 14 16-Bit Timer Pulse Unit (TPU) This LSI has two on-chip 16-bit timer pulse units (TPU), unit 0 and unit 1, each comprises six channels. Therefore, this LSI includes twelve channels. Functions of unit 0 and unit 1 are shown in table 14.1 and table 14.2 respectively. Block diagrams of unit 0 and unit 1 are shown in figure 14.1 and figure 14.2 respectively. This section explains unit 0. This explanation is common to unit 1.

14.1 Features

• Maximum 16-pulse input/output
• Selection of eight counter input clocks for each channel
• The following operations can be set for each channel:  Waveform output at compare match  Input capture function  Counter clear operation  Synchronous operations:
• Multiple timer counters (TCNT) can be written to simultaneously
• Simultaneous clearing by compare match and input capture possible
• Simultaneous input/output for registers possible by counter synchronous operation
• Maximum of 15-phase PWM output possible by combination with synchronous operation
• Buffer operation settable for channels 0 and 3
• Phase counting mode settable independently for each of channels 1, 2, 4, and 5
• Cascaded operation
• Fast access via internal 16-bit bus
• 26 interrupt sources
• Automatic transfer of register data
• Programmable pulse generator (PPG) output trigger can be generated (unit 0 only)
• Conversion start trigger for the A/D converter can be generated (unit 0 only)
• Module stop state can be set

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 702 of 1438 REJ09B0365-0200 Table 14.1 TPU (U nit 0) Functions Item Channel 0 Channel 1 Channe l 2 Channel 3 Channel 4 Channel 5 Count clock P φ/1 Pφ/4 Pφ/16 Pφ/64 TCLKA TCLKB TCLKC TCLKD Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/256 TCLKA TCLKB Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/1024 TCLKA TCLKB TCLKC Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/256 Pφ/1024 Pφ/4096 TCLKA Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/1024 TCLKA TCLKC Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/256 TCLKA TCLKC TCLKD General registers (TGR) TGRA_0 TGRB_0 TGRA_1 TGRB_1 TGRA_2 TGRB_2 TGRA_3 TGRB_3 TGRA_4 TGRB_4 TGRA_5 TGRB_5 General registers/ buffer registers TGRC_0 TGRD_0   TGRC_3 TGRD_3   I/O pins TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5 Counter clear function TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture 0 output O O O O O O 1 output O O O O O O Compare match output Toggle output O O O O O O Input capture function O O O O O O Synchronous operation O O O O O O PWM mode O O O O O O Phase counting mode  O O  O O Buffer operation O   O   DTC activation TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 703 of 1438 REJ09B0365-0200 Item Channel 0 Channel 1 Channe l 2 Channel 3 Channel 4 Channel 5 DMAC activation TGRA_0 compare match or input capture TGRA_1 compare match or input capture TGRA_2 compare match or input capture TGRA_3 compare match or input capture TGRA_4 compare match or input capture TGRA_5 compare match or input capture A/D conversion start trigger TGRA_0 compare match or input capture TGRA_1 compare match or input capture TGRA_2 compare match or input capture TGRA_3 compare match or input capture TGRA_4 compare match or input capture TGRA_5 compare match or input capture PPG trigger TGRA_0/ TGRB_0 compare match or input capture TGRA_1/ TGRB_1 compare match or input capture TGRA_2/ TGRB_2 compare match or input capture TGRA_3/ TGRB_3 compare match or input capture   Interrupt sources 5 sources Compare match or input capture 0A Compare match or input capture 0B Compare match or input capture 0C Compare match or input capture 0D Overflow 4 sources Compare match or input capture 1A Compare match or input capture 1B Overflow Underflow 4 sources Compare match or input capture 2A Compare match or input capture 2B Overflow Underflow 5 sources Compare match or input capture 3A Compare match or input capture 3B Compare match or input capture 3C Compare match or input capture 3D Overflow 4 sources Compare match or input capture 4A Compare match or input capture 4B Overflow Underflow 4 sources Compare match or input capture 5A Compare match or input capture 5B Overflow Underflow [Legend] O: Possible : Not possible

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 704 of 1438 REJ09B0365-0200 Table 14.2 TPU (U nit 1) Functions Item Channel 6 Channel 7 Channel 8 Channel 9 Channel 10 Channel 11 Count clock P φ/1 Pφ/4 Pφ/16 Pφ/64 TCLKE TCLKF TCLKG TCLKH Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/256 TCLKE TCLKF Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/1024 TCLKE TCLKF TCLKG Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/256 Pφ/1024 Pφ/4096 TCLKE Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/1024 TCLKE TCLKG Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/256 TCLKE TCLKG TCLKH General registers (TGR) TGRA_6 TGRB_6 TGRA_7 TGRB_7 TGRA_8 TGRB_8 TGRA_9 TGRB_9 TGRA_10 TGRB_10 TGRA_11 TGRB_11 General registers/ buffer registers TGRC_6 TGRD_6   TGRC_9 TGRD_9   I/O pins TIOCA6 TIOCB6 TIOCC6 TIOCD6 TIOCA7 TIOCB7 TIOCA8 TIOCB8 TIOCA9 TIOCB9 TIOCC9 TIOCD9 TIOCA10 TIOCB10 TIOCA11 TIOCB11 Counter clear function TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture 0 output O O O O O O 1 output O O O O O O Compare match output Toggle output O O O O O O Input capture function O O O O O O Synchronous operation O O O O O O PWM mode O O O O O O Phase counting mode  O O  O O Buffer operation O   O   DTC activation TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 705 of 1438 REJ09B0365-0200 Item Channel 6 Channel 7 Channel 8 Channel 9 Channel 10 Channel 11 DMAC activation TGRA_6 compare match or input capture TGRA_7 compare match or input capture TGRA_8 compare match or input capture TGRA_9 compare match or input capture TGRA_10 compare match or input capture TGRA_11 compare match or input capture A/D conversion start trigger PPG trigger TGRA_6/ TGRB_6 compare match TGRA_7/ TGRB_7 compare match TGRA_8/ TGRB_8 compare match TGRA_9/ TGRB_9 compare match   Interrupt sources 5 sources Compare match or input capture 6A Compare match or input capture 6B Compare match or input capture 6C Compare match or input capture 6D Overflow 4 sources Compare match or input capture 7A Compare match or input capture 7B Overflow Underflow 4 sources Compare match or input capture 8A Compare match or input capture 8B Overflow Underflow 5 sources Compare match or input capture 9A Compare match or input capture 9B Compare match or input capture 9C Compare match or input capture 9D Overflow 4 sources Compare match or input capture 10A Compare match or input capture 10B Overflow Underflow 4 sources Compare match or input capture 11A Compare match or input capture 11B Overflow Underflow [Legend] O: Possible : Not possible

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 706 of 1438 REJ09B0365-0200 Channel 3 TMDR TIORL TSR TCR TIORH TIER TGRA TCNT TGRB TGRC TGRD Channel 4 TMDR TSR TCR TIOR TIER TGRA TCNT TGRB Control logic TMDR TSR TCR TIOR TIER TGRA TCNT TGRB Control logic for channels 3 to 5 TMDR TSR TCR TIOR TIER TGRA TCNT TGRB TGRC Channel 1 TMDR TSR TCR TIOR TIER TGRA TCNT TGRB Channel 0 TMDR TSR TCR TIORH TIER Control logic for channels 0 to 2 TGRA TCNT TGRB TGRD TSYRTSTR Input/output pins TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5 Clock input Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/256 Pφ/1024 Pφ/4096 TCLKA TCLKB TCLKC TCLKD Input/output pins TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 Interrupt request signals Channel 3: Channel 4: Channel 5: Interrupt request signals Channel 0: Channel 1: Channel 2: Internal data bus A/D conversion start request signal PPG output trigger signal TIORL Module data bus TGI3A TGI3B TGI3C TGI3D TCI3V TGI4A TGI4B TCI4V TCI4U TGI5A TGI5B TCI5V TCI5U TGI0A TGI0B TGI0C TGI0D TCI0V TGI1A TGI1B TCI1V TCI1U TGI2A TGI2B TCI2V TCI2U Channel 3: Channel 4: Channel 5: Internal clock: External clock: Channel 0: Channel 1: Channel 2: [Legend] TSTR: Timer start register TSYR: Timer synchronous register TCR: Timer control register TMDR: Timer mode register TIOR (H, L): Timer I/O control registers (H, L) TIER: Timer interrupt enable register TSR: Timer status register TGR (A, B, C, D): Timer general registers (A, B, C, D) TCNT: Timer counter Channel 2 Common Channel 5 Bus interface Figure 14.1 Block Diagram of TPU (Unit 0)

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 707 of 1438 REJ09B0365-0200 Channel 9 TMDR TIORL TSR TCR TIORH TIER TGRA TCNT TGRB TGRC TGRD Channel 10 TMDR TSR TCR TIOR TIER TGRA TCNT TGRB Control logic TMDR TSR TCR TIOR TIER TGRA TCNT TGRB Control logic for channels 9 to 11 TMDR TSR TCR TIOR TIER TGRA TCNT TGRB TGRC Channel 7 TMDR TSR TCR TIOR TIER TGRA TCNT TGRB Channel 6 TMDR TSR TCR TIORH TIER Control logic for channels 6 to 8 TGRA TCNT TGRB TGRD TSYRBTSTRB Input/output pins TIOCA9 TIOCB9 TIOCC9 TIOCD9 TIOCA10 TIOCB10 TIOCA11 TIOCB11 Clock input Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/256 Pφ/1024 Pφ/4096 TCLKE TCLKF TCLKG TCLKH Input/output pins TIOCA6 TIOCB6 TIOCC6 TIOCD6 TIOCA7 TIOCB7 TIOCA8 TIOCB8 Interrupt request signals Channel 9: Channel 10: Channel 11: Interrupt request signals Channel 6: Channel 7: Channel 8: Internal data bus TIORL Module data bus TGI9A TGI9B TGI9C TGI9D TCI9V TGI10A TGI10B TCI10V TCI10U TGI11A TGI11B TCI11V TCI11U TGI6A TGI6B TGI6C TGI6D TCI6V TGI7A TGI7B TCI7V TCI7U TGI8A TGI8B TCI8V TCI8U Channel 9: Channel 10: Channel 11: Internal clock: External clock: Channel 6: Channel 7: Channel 8: [Legend] TSTRB: Timer start register TSYRB: Timer synchronous register TCR: Timer control register TMDR: Timer mode register TIOR (H, L): Timer I/O control registers (H, L) TIER: Timer interrupt enable register TSR: Timer status register TGR (A, B, C, D): Timer general registers (A, B, C, D) TCNT: Timer counter Channel 8 Common Channel 11 Bus interface PPG output trigger signal Figure 14.2 Block Diagram of TPU (Unit 1)

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 708 of 1438 REJ09B0365-0200

14.2 Input/Output Pins

Table 14.3 shows TPU pin configurations. Table 14.3 Pin Configuration Unit Channel Symbol I/O Function All TCLKA Input External clock A input pin (Channel 1 and 5 phase counting mode A phase input) TCLKB Input External clock B input pin (Channel 1 and 5 phase counting mode B phase input) TCLKC Input External clock C input pin (Channel 2 and 4 phase counting mode A phase input) TCLKD Input External clock D input pin (Channel 2 and 4 phase counting mode B phase input)

0 TIOCA0 I/O TGRA_0 input capture input/output compare output/PWM output pin

TIOCB0 I/O TGRB_0 input capture input/output compare output/PWM output pin TIOCC0 I/O TGRC_0 input capture input/output compare output/PWM output pin TIOCD0 I/O TGRD_0 input capture input/output compare output/PWM output pin

1 TIOCA1 I/O TGRA_1 input capture input/output compare output/PWM output pin

TIOCB1 I/O TGRB_1 input capture input/output compare output/PWM output pin

2 TIOCA2 I/O TGRA_2 input capture input/output compare output/PWM output pin

TIOCB2 I/O TGRB_2 input capture input/output compare output/PWM output pin

3 TIOCA3 I/O TGRA_3 input capture input/output compare output/PWM output pin

TIOCB3 I/O TGRB_3 input capture input/output compare output/PWM output pin TIOCC3 I/O TGRC_3 input capture input/output compare output/PWM output pin TIOCD3 I/O TGRD_3 input capture input/output compare output/PWM output pin

4 TIOCA4 I/O TGRA_4 input capture input/output compare output/PWM output pin

TIOCB4 I/O TGRB_4 input capture input/output compare output/PWM output pin

5 TIOCA5 I/O TGRA_5 input capture input/output compare output/PWM output pin

TIOCB5 I/O TGRB_5 input capture input/output compare output/PWM output pin

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 709 of 1438 REJ09B0365-0200 Unit Channel Symbol I/O Function All TCLKE Input External clock E input pin (Channel 7 and 11 phase counting mode A phase input) TCLKF Input External clock F input pin (Channel 7 and 11 phase counting mode B phase input) TCLKG Input External clock G input pin (Channel 8 and 10 phase counting mode A phase input) TCLKH Input External clock H input pin (Channel 8 and 10 phase counting mode B phase input)

6 TIOCA6 I/O TGRA_6 input capture input/output compare output/PWM output pin

TIOCB6 I/O TGRB_6 input capture input/output compare output/PWM output pin TIOCC6 I/O TGRC_6 input capture input/output compare output/PWM output pin TIOCD6 I/O TGRD_6 input capture input/output compare output/PWM output pin

7 TIOCA7 I/O TGRA_7 input capture input/output compare output/PWM output pin

TIOCB7 I/O TGRB_7 input capture input/output compare output/PWM output pin

8 TIOCA8 I/O TGRA_8 input capture input/output compare output/PWM output pin

TIOCB8 I/O TGRB_8 input capture input/output compare output/PWM output pin

9 TIOCA9 I/O TGRA_9 input capture input/output compare output/PWM output pin

TIOCB9 I/O TGRB_9 input capture input/output compare output/PWM output pin TIOCC9 I/O TGRC_9 input capture input/output compare output/PWM output pin TIOCD9 I/O TGRD_9 input capture input/output compare output/PWM output pin

10 TIOCA10 I/O TGRA_10 input capture input/output compare output/PWM output pin

TIOCB10 I/O TGRB_10 input capture input/output compare output/PWM output pin

11 TIOCA11 I/O TGRA_11 input capture input/output compare output/PWM output pin

TIOCB11 I/O TGRB_11 input capture input/output compare output/PWM output pin

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 710 of 1438 REJ09B0365-0200

14.3 Register Descriptions

The TPU has the following registers in each channel. Registers in the unit 0 and unit 1 have the same functions except for the bit 7 in TIER, namely, the TTGE bit in unit 0 and a reserved bit in unit 1. This section gives explanations regarding unit 0. Unit 0:

• Channel 0:  Timer control register_0 (TCR_0)  Timer mode register_0 (TMDR_0)  Timer I/O control register H_0 (TIORH_0)  Timer I/O control register L_0 (TIORL_0)  Timer interrupt enable register_0 (TIER_0)  Timer status register_0 (TSR_0)  Timer counter_0 (TCNT_0)  Timer general register A_0 (TGRA_0)  Timer general register B_0 (TGRB_0)  Timer general register C_0 (TGRC_0)  Timer general register D_0 (TGRD_0)
• Channel 1:  Timer control register_1 (TCR_1)  Timer mode register_1 (TMDR_1)  Timer I/O control register _1 (TIOR_1)  Timer interrupt enable register_1 (TIER_1)  Timer status register_1 (TSR_1)  Timer counter_1 (TCNT_1)  Timer general register A_1 (TGRA_1)  Timer general register B_1 (TGRB_1)

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 711 of 1438 REJ09B0365-0200

• Channel 2:  Timer control register_2 (TCR_2)  Timer mode register_2 (TMDR_2)  Timer I/O control register_2 (TIOR_2)  Timer interrupt enable register_2 (TIER_2)  Timer status register_2 (TSR_2)  Timer counter_2 (TCNT_2)  Timer general register A_2 (TGRA_2)  Timer general register B_2 (TGRB_2)
• Channel 3:  Timer control register_3 (TCR_3)  Timer mode register_3 (TMDR_3)  Timer I/O control register H_3 (TIORH_3)  Timer I/O control register L_3 (TIORL_3)  Timer interrupt enable register_3 (TIER_3)  Timer status register_3 (TSR_3)  Timer counter_3 (TCNT_3)  Timer general register A_3 (TGRA_3)  Timer general register B_3 (TGRB_3)  Timer general register C_3 (TGRC_3)  Timer general register D_3 (TGRD_3)
• Channel 4:  Timer control register_4 (TCR_4)  Timer mode register_4 (TMDR_4)  Timer I/O control register _4 (TIOR_4)  Timer interrupt enable register_4 (TIER_4)  Timer status register_4 (TSR_4)  Timer counter_4 (TCNT_4)  Timer general register A_4 (TGRA_4)  Timer general register B_4 (TGRB_4)

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 712 of 1438 REJ09B0365-0200

• Channel 5:  Timer control register_5 (TCR_5)  Timer mode register_5 (TMDR_5)  Timer I/O control register_5 (TIOR_5)  Timer interrupt enable register_5 (TIER_5)  Timer status register_5 (TSR_5)  Timer counter_5 (TCNT_5)  Timer general register A_5 (TGRA_5)  Timer general register B_5 (TGRB_5)
• Common Registers:  Timer start register (TSTR)  Timer synchronous register (TSYR) Unit 1:
• Channel 6:  Timer control register_6 (TCR_6)  Timer mode register_6 (TMDR_6)  Timer I/O control register H_6 (TIORH_6)  Timer I/O control register L_6 (TIORL_6)  Timer interrupt enable register_6 (TIER_6)  Timer status register_6 (TSR_6)  Timer counter_6 (TCNT_6)  Timer general register A_6 (TGRA_6)  Timer general register B_6 (TGRB_6)  Timer general register C_6 (TGRC_6)  Timer general register D_6 (TGRD_6)

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 713 of 1438 REJ09B0365-0200

• Channel 7:  Timer control register_7 (TCR_7)  Timer mode register_7 (TMDR_7)  Timer I/O control register _7 (TIOR_7)  Timer interrupt enable register_7 (TIER_7)  Timer status register_7 (TSR_7)  Timer counter_7 (TCNT_7)  Timer general register A_7 (TGRA_7)  Timer general register B_7 (TGRB_7)
• Channel 8:  Timer control register_8 (TCR_8)  Timer mode register_8 (TMDR_8)  Timer I/O control register_8 (TIOR_8)  Timer interrupt enable register_8 (TIER_8)  Timer status register_8 (TSR_8)  Timer counter_8 (TCNT_8)  Timer general register A_8 (TGRA_8)  Timer general register B_8 (TGRB_8)
• Channel 9:  Timer control register_9 (TCR_9)  Timer mode register_9 (TMDR_9)  Timer I/O control register H_9 (TIORH_9)  Timer I/O control register L_9 (TIORL_9)  Timer interrupt enable register_9 (TIER_9)  Timer status register_9 (TSR_9)  Timer counter_9 (TCNT_9)  Timer general register A_9 (TGRA_9)  Timer general register B_9 (TGRB_9)  Timer general register C_9 (TGRC_9)  Timer general register D_9 (TGRD_9)

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 714 of 1438 REJ09B0365-0200

• Channel 10:  Timer control register_10 (TCR_10)  Timer mode register_10 (TMDR_10)  Timer I/O control register _10 (TIOR_10)  Timer interrupt enable register_10 (TIER_10)  Timer status register_10 (TSR_10)  Timer counter_10 (TCNT_10)  Timer general register A_10 (TGRA_10)  Timer general register B_10 (TGRB_10)
• Channel 11:  Timer control register_11 (TCR_11)  Timer mode register_11 (TMDR_11)  Timer I/O control register_11 (TIOR_11)  Timer interrupt enable register_11 (TIER_11)  Timer status register_11 (TSR_11)  Timer counter_11 (TCNT_11)  Timer general register A_11 (TGRA_11)  Timer general register B_11 (TGRB_11)
• Common Registers:  Timer start register (TSTRB)  Timer synchronous register (TSYRB)

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 715 of 1438 REJ09B0365-0200

14.3.1 Timer Control Register (TCR)

TCR controls the TCNT operation for each channel. The TPU has a total of six TCR registers, one for each channel. TCR register settings should be made only while TCNT operation is stopped. CCLR2 R/W CCLR1 R/W CCLR0 R/W CKEG1 R/W CKEG0 R/W TPSC2 R/W TPSC1 R/W TPSC0 R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description CCLR2 CCLR1 CCLR0 R/W R/W R/W Counter Clear 2 to 0 These bits select the TCNT counter clearing source. See tables 12.4 and 12.5 for details. CKEG1 CKEG0 R/W R/W Clock Edge 1 and 0 These bits select the input clock edge. For details, see table 14.6. When the input clock is counted using both edges, the input clock period is halved (e.g. Pφ/4 both edges = Pφ/2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority. Internal clock edge selection is valid when the input clock is Pφ/4 or slower. This setting is ignored if the input clock is Pφ/1, or when overflow/underflow of another channel is selected. TPSC2 TPSC1 TPSC0 R/W R/W R/W Timer Prescaler 2 to 0 These bits select the TCNT counter clock. The clock source can be selected independently for each channel. See tables 12.7 to 12.12 for details. To select the external clock as the clock source, the DDR bit and ICR bit for the corresponding pin should be set to 0 and 1, respectively. For details, see section 13, I/O Ports.

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 716 of 1438 REJ09B0365-0200 Table 14.4 CCLR2 to CCLR0 (Channels 0 and 3) Channel Bit 7 CCLR2 Bit 6 CCLR1 Bit 5 CCLR0 Description 0 0 0 TCNT clearing disabled 0 0 1 TCNT cleared by TGRA compare match/input capture 0 1 0 TCNT cleared by TGRB compare match/input capture 0 1 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation* 1 0 0 TCNT clearing disabled 1 0 1 TCNT cleared by TGRC compare match/input capture* 1 1 0 TCNT cleared by TGRD compare match/input capture* 0, 3 1 1 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation* Notes: 1. Synchronous operation is select ed by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer re gister, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. Table 14.5 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5) Channel Bit 7 Reserved* Bit 6 CCLR1 Bit 5 CCLR0 Description 0 0 0 TCNT clearing disabled 0 0 1 TCNT cleared by TGRA compare match/input capture 0 1 0 TCNT cleared by TGRB compare match/input capture 1, 2, 4, 5 0 1 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation* Notes: 1. Synchronous operation is select ed by setting the SYNC bit in TSYR to 1. 2. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be modified.

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 717 of 1438 REJ09B0365-0200 Table 14.6 Input Clock Edge Selection Clock Edge Selection Input Clock CKEG1 CKEG0 Internal Clock External Clock 0 0 Counted at falling edge Counted at rising edge 0 1 Counted at rising edge Counted at falling edge 1 x Counted at both edges Counted at both edges [Legend] x: Don't care Table 14.7 TPSC2 to TPSC0 (Channel 0) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 0 0 0 Internal clock: counts on P φ/1 0 0 1 Internal clock: counts on P φ/4 0 1 0 Internal clock: counts on P φ/16 0 1 1 Internal clock: counts on P φ/64 1 0 0 External clock: counts on TCLKA pin input 1 0 1 External clock: counts on TCLKB pin input 1 1 0 External clock: counts on TCLKC pin input 1 1 1 External clock: counts on TCLKD pin input Table 14.8 TPSC2 to TPSC0 (Channel 1) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 0 0 0 Internal clock: counts on P φ/1 0 0 1 Internal clock: counts on P φ/4 0 1 0 Internal clock: counts on P φ/16 0 1 1 Internal clock: counts on P φ/64 1 0 0 External clock: counts on TCLKA pin input 1 0 1 External clock: counts on TCLKB pin input 1 1 0 Internal clock: counts on P φ/256 1 1 1 Counts on TCNT2 overflow/underflow Note: This setting is ignored when channel 1 is in phase counting mode.

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 718 of 1438 REJ09B0365-0200 Table 14.9 TPSC2 to TPSC0 (Channel 2) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 0 0 0 Internal clock: counts on P φ/1 0 0 1 Internal clock: counts on P φ/4 0 1 0 Internal clock: counts on P φ/16 0 1 1 Internal clock: counts on P φ/64 1 0 0 External clock: counts on TCLKA pin input 1 0 1 External clock: counts on TCLKB pin input 1 1 0 External clock: counts on TCLKC pin input 1 1 1 Internal clock: counts on P φ/1024 Note: This setting is ignored when channel 2 is in phase counting mode. Table 14.10 TPSC2 to TPSC0 (Channel 3) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 0 0 0 Internal clock: counts on P φ/1 0 0 1 Internal clock: counts on P φ/4 0 1 0 Internal clock: counts on P φ/16 0 1 1 Internal clock: counts on P φ/64 1 0 0 External clock: counts on TCLKA pin input 1 0 1 Internal clock: counts on P φ/1024 1 1 0 Internal clock: counts on P φ/256 1 1 1 Internal clock: counts on P φ/4096

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 719 of 1438 REJ09B0365-0200 Table 14.11 TPSC2 to TPSC0 (Channel 4) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 0 0 0 Internal clock: counts on P φ/1 0 0 1 Internal clock: counts on P φ/4 0 1 0 Internal clock: counts on P φ/16 0 1 1 Internal clock: counts on P φ/64 1 0 0 External clock: counts on TCLKA pin input 1 0 1 External clock: counts on TCLKC pin input 1 1 0 Internal clock: counts on P φ/1024 1 1 1 Counts on TCNT5 overflow/underflow Note: This setting is ignored when channel 4 is in phase counting mode. Table 14.12 TPSC2 to TPSC0 (Channel 5) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 0 0 0 Internal clock: counts on P φ/1 0 0 1 Internal clock: counts on P φ/4 0 1 0 Internal clock: counts on P φ/16 0 1 1 Internal clock: counts on P φ/64 1 0 0 External clock: counts on TCLKA pin input 1 0 1 External clock: counts on TCLKC pin input 1 1 0 Internal clock: counts on P φ/256 1 1 1 External clock: counts on TCLKD pin input Note: This setting is ignored when channel 5 is in phase counting mode.

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 720 of 1438 REJ09B0365-0200

14.3.2 Timer Mode Register (TMDR)

TMDR sets the operating mode for each channel. The TPU has six TMDR registers, one for each channel. TMDR register settings should be made only while TCNT operation is stopped. BFB R/W BFA R/W MD3 R/W MD2 R/W MD1 R/W MD0 R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description 7, 6  All 1  Reserved These bits are always read as 1 and cannot be modified.

5 BFB 0 R/W Buffer Operation B

Specifies whether TGRB is to normally operate, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: TGRB operates normally 1: TGRB and TGRD used together for buffer operation

4 BFA 0 R/W Buffer Operation A

Specifies whether TGRA is to normally operate, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified. 0: TGRA operates normally 1: TGRA and TGRC used together for buffer operation MD3 MD2 MD1 MD0 R/W R/W R/W R/W Modes 3 to 0 Set the timer operating mode. MD3 is a reserved bit. The write value should always be 0. See table 14.13 for details.

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 721 of 1438 REJ09B0365-0200 Table 14.13 MD3 to MD0 Bit 3 MD3 * Bit 2 MD2 * Bit 1 MD1 Bit 0 MD0 Description 0 0 0 0 Normal operation 0 0 0 1 Reserved 0 0 1 0 PWM mode 1 0 0 1 1 PWM mode 2 0 1 0 0 Phase counting mode 1 0 1 0 1 Phase counting mode 2 0 1 1 0 Phase counting mode 3 0 1 1 1 Phase counting mode 4 1 x x x  [Legend] x: Don't care Notes: 1. MD3 is a reserved bit. The write value should always be 0. 2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2.

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 722 of 1438 REJ09B0365-0200

14.3.3 Timer I/O Cont rol Register (TIOR)

TIOR controls TGR. The TPU has eight TIOR registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5. Care is required since TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. To designate the input capture pin in TIOR, the DDR bit and ICR bit for the corresponding pin should be set to 0 and 1, respectively. For details, see section 13, I/O Ports.

• TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5 IOB3 R/W IOB2 R/W IOB1 R/W IOB0 R/W IOA3 R/W IOA2 R/W IOA1 R/W IOA0 R/W Bit Bit Name Initial Value R/W
• TIORL_0, TORL_3 IOD3 R/W IOD2 R/W IOD1 R/W IOD0 R/W IOC3 R/W IOC2 R/W IOC1 R/W IOC0 R/W Bit Bit Name Initial Value R/W

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 723 of 1438 REJ09B0365-0200

• TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5 Bit Bit Name Initial Value R/W Description IOB3 IOB2 IOB1 IOB0 R/W R/W R/W R/W I/O Control B3 to B0 Specify the function of TGRB. For details, see tables 12.14, 12.16 to 12.18, 12.20 and 12.21. IOA3 IOA2 IOA1 IOA0 R/W R/W R/W R/W I/O Control A3 to A0 Specify the function of TGRA. For details, see tables 12.22, 12.24 to 12.26, 12.28, and 12.29.
• TIORL_0, TIORL_3 Bit Bit Name Initial Value R/W Description IOD3 IOD2 IOD1 IOD0 R/W R/W R/W R/W I/O Control D3 to D0 Specify the function of TGRD. For details, see tables 12.15, and 12.19. IOC3 IOC2 IOC1 IOC0 R/W R/W R/W R/W I/O Control C3 to C0 Specify the function of TGRC. For details, see tables 12.23, and 12.27.

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 724 of 1438 REJ09B0365-0200 Table 14.14 TIORH_0

Description

TGRB_0 Function TIOCB0 Pin Function 0 0 0 0 Output disabled 0 0 0 1 Initial output is 0 output 0 output at compare match 0 0 1 0 Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCB0 pin Input capture at rising edge 1 0 0 1 Capture input source is TIOCB0 pin Input capture at falling edge 1 0 1 x Capture input source is TIOCB0 pin Input capture at both edges 1 1 x x Input capture register Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down* [Legend] x: Don't care Note: * When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and P φ/1 is used as the TCNT_1 count clock, this setting is invalid and input capture is not generated.

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 725 of 1438 REJ09B0365-0200 Table 14.15 TIORL_0 TGRD_0 Function TIOCD0 Pin Function 0 0 0 0 Output disabled 0 0 0 1 Initial output is 0 output 0 output at compare match 0 0 1 0 Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register* Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCD0 pin Input capture at rising edge 1 0 0 1 Capture input source is TIOCD0 pin Input capture at falling edge 1 0 1 x Capture input source is TIOCD0 pin Input capture at both edges 1 1 x x Input capture register* Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down* [Legend] x: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and P φ/1 is used as the TCNT_1 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 726 of 1438 REJ09B0365-0200 Table 14.16 TIOR_1 TGRB_1 Function TIOCB1 Pin Function 0 0 0 0 Output disabled 0 0 0 1 Initial output is 0 output 0 output at compare match 0 0 1 0 Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCB1 pin Input capture at rising edge 1 0 0 1 Capture input source is TIOCB1 pin Input capture at falling edge 1 0 1 x Capture input source is TIOCB1 pin Input capture at both edges 1 1 x x Input capture register TGRC_0 compare match/input capture Input capture at generation of TGRC_0 compare match/input capture [Legend] x: Don't care

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 727 of 1438 REJ09B0365-0200 Table 14.17 TIOR_2 TGRB_2 Function TIOCB2 Pin Function 0 0 0 0 Output disabled 0 0 0 1 Initial output is 0 output 0 output at compare match 0 0 1 0 Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 1 x 0 0 Capture input source is TIOCB2 pin Input capture at rising edge 1 x 0 1 Capture input source is TIOCB2 pin Input capture at falling edge 1 x 1 x Input capture register Capture input source is TIOCB2 pin Input capture at both edges [Legend] x: Don't care

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 728 of 1438 REJ09B0365-0200 Table 14.18 TIORH_3 TGRB_3 Function TIOCB3 Pin Function 0 0 0 0 Output disabled 0 0 0 1 Initial output is 0 output 0 output at compare match 0 0 1 0 Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCB3 pin Input capture at rising edge 1 0 0 1 Capture input source is TIOCB3 pin Input capture at falling edge 1 0 1 x Capture input source is TIOCB3 pin Input capture at both edges 1 1 x x Input capture register Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down* [Legend] x: Don't care Note: * When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and P φ/1 is used as the TCNT_4 count clock, this setting is invalid and input capture is not generated.

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 729 of 1438 REJ09B0365-0200 Table 14.19 TIORL_3 TGRD_3 Function TIOCD3 Pin Function 0 0 0 0 Output disabled 0 0 0 1 Initial output is 0 output 0 output at compare match 0 0 1 0 Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register* Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCD3 pin Input capture at rising edge 1 0 0 1 Capture input source is TIOCD3 pin Input capture at falling edge 1 0 1 x Capture input source is TIOCD3 pin Input capture at both edges 1 1 x x Input capture register* Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down* [Legend] x: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and P φ/1 is used as the TCNT_4 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 730 of 1438 REJ09B0365-0200 Table 14.20 TIOR_4 TGRB_4 Function TIOCB4 Pin Function 0 0 0 0 Output disabled 0 0 0 1 Initial output is 0 output 0 output at compare match 0 0 1 0 Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCB4 pin Input capture at rising edge 1 0 0 1 Capture input source is TIOCB4 pin Input capture at falling edge 1 0 1 x Capture input source is TIOCB4 pin Input capture at both edges 1 1 x x Input capture register Capture input source is TGRC_3 compare match/input capture Input capture at generation of TGRC_3 compare match/input capture [Legend] x: Don't care

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 731 of 1438 REJ09B0365-0200 Table 14.21 TIOR_5 TGRB_5 Function TIOCB5 Pin Function 0 0 0 0 Output disabled 0 0 0 1 Initial output is 0 output 0 output at compare match 0 0 1 0 Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 1 x 0 0 Capture input source is TIOCB5 pin Input capture at rising edge 1 x 0 1 Capture input source is TIOCB5 pin Input capture at falling edge 1 x 1 x Input capture register Capture input source is TIOCB5 pin Input capture at both edges [Legend] x: Don't care

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 732 of 1438 REJ09B0365-0200 Table 14.22 TIORH_0 TGRA_0 Function TIOCA0 Pin Function 0 0 0 0 Output disabled 0 0 0 1 Initial output is 0 output 0 output at compare match 0 0 1 0 Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 1 0 0 1 Capture input source is TIOCA0 pin Input capture at rising edge 1 0 0 0 Capture input source is TIOCA0 pin Input capture at falling edge 1 0 1 x Capture input source is TIOCA0 pin Input capture at both edges 1 1 x x Input capture register Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down* [Legend] x: Don't care Note: * When the bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and P φ/1 is used as the count clock of TCNT_1, this setting is invalid and input capture is not generated.

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 733 of 1438 REJ09B0365-0200 Table 14.23 TIORL_0 TGRC_0 Function TIOCC0 Pin Function 0 0 0 0 Output disabled 0 0 0 1 Initial output is 0 output 0 output at compare match 0 0 1 0 Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register* Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCC0 pin Input capture at rising edge 1 0 0 1 Capture input source is TIOCC0 pin Input capture at falling edge 1 0 1 x Capture input source is TIOCC0 pin Input capture at both edges 1 1 x x Input capture register* Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down* [Legend] x: Don't care Note: 1. When the bits TPSC2 to T PSC0 in TCR_1 are set to B'000 and Pφ/1 is used as the count clock of TCNT_1, this setting is invalid and input capture is not generated. 2. When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 734 of 1438 REJ09B0365-0200 Table 14.24 TIOR_1 TGRA_1 Function TIOCA1 Pin Function 0 0 0 0 Output disabled 0 0 0 1 Initial output is 0 output 0 output at compare match 0 0 1 0 Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCA1 pin Input capture at rising edge 1 0 0 1 Capture input source is TIOCA1 pin Input capture at falling edge 1 0 1 x Capture input source is TIOCA1 pin Input capture at both edges 1 1 x x Input capture register Capture input source is TGRA_0 compare match/input capture Input capture at generation of channel 0/TGRA_0 compare match/input capture [Legend] x: Don't care

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 735 of 1438 REJ09B0365-0200 Table 14.25 TIOR_2 TGRA_2 Function TIOCA2 Pin Function 0 0 0 0 Output disabled 0 0 0 1 Initial output is 0 output 0 output at compare match 0 0 1 0 Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 1 x 0 0 Capture input source is TIOCA2 pin Input capture at rising edge 1 x 0 1 Capture input source is TIOCA2 pin Input capture at falling edge 1 x 1 x Input capture register Capture input source is TIOCA2 pin Input capture at both edges [Legend] x: Don't care

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 736 of 1438 REJ09B0365-0200 Table 14.26 TIORH_3 TGRA_3 Function TIOCA3 Pin Function 0 0 0 0 Output disabled 0 0 0 1 Initial output is 0 output 0 output at compare match 0 0 1 0 Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCA3 pin Input capture at rising edge 1 0 0 1 Capture input source is TIOCA3 pin Input capture at falling edge 1 0 1 x Capture input source is TIOCA3 pin Input capture at both edges 1 1 x x Input capture register Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down* [Legend] x: Don't care Note: * When the bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and P φ/1 is used as the count clock of TCNT_4, this setting is invalid and input capture is not generated.

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 737 of 1438 REJ09B0365-0200 Table 14.27 TIORL_3 TGRC_3 Function TIOCC3 Pin Function 0 0 0 0 Output disabled 0 0 0 1 Initial output is 0 output 0 output at compare match 0 0 1 0 Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register* Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCC3 pin Input capture at rising edge 1 0 0 1 Capture input source is TIOCC3 pin Input capture at falling edge 1 0 1 x Capture input source is TIOCC3 pin Input capture at both edges 1 1 x x Input capture register* Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down* [Legend] x: Don't care Notes: 1. When the bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and P φ/1 is used as the count clock of TCNT_4, this setting is invalid and input capture is not generated. 2. When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 738 of 1438 REJ09B0365-0200 Table 14.28 TIOR_4 TGRA_4 Function TIOCA4 Pin Function 0 0 0 0 Output disabled 0 0 0 1 Initial output is 0 output 0 output at compare match 0 0 1 0 Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCA4 pin Input capture at rising edge 1 0 0 1 Capture input source is TIOCA4 pin Input capture at falling edge 1 0 1 x Capture input source is TIOCA4 pin Input capture at both edges 1 1 x x Input capture register Capture input source is TGRA_3 compare match/input capture Input capture at generation of TGRA_3 compare match/input capture [Legend] x: Don't care

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 739 of 1438 REJ09B0365-0200 Table 14.29 TIOR_5 TGRA_5 Function TIOCA5 Pin Function 0 0 0 0 Output disabled 0 0 0 1 Initial output is 0 output 0 output at compare match 0 0 1 0 Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 1 x 0 0 Input capture source is TIOCA5 pin Input capture at rising edge 1 x 0 1 Input capture source is TIOCA5 pin Input capture at falling edge 1 x 1 x Input capture register Input capture source is TIOCA5 pin Input capture at both edges [Legend] x: Don't care

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 740 of 1438 REJ09B0365-0200

14.3.4 Timer Interrupt Enable Register (TIER)

TIER controls enabling or disabling of interrupt requests for each channel. The TPU has six TIER registers, one for each channel. Bit Bit Name Initial Value R/W TTGE* R/W TCIEU R/W TCIEV R/W TGIED R/W TGIEC R/W TGIEB R/W TGIEA R/W Note: * Bit 7 in TIER of unit 1 is a reserved bit. This bit is always read as 0 and the initial value should not be changed. Bit Bit Name Initial value R/W Description

7 TTGE * 0 R/W A/D Conversion Start Request Enable

Enables/disables generation of A/D conversion start requests by TGRA input capture/compare match. 0: A/D conversion start request generation disabled 1: A/D conversion start request generation enabled 6  1  Reserved This bit is always read as 1 and cannot be modified.

5 TCIEU 0 R/W Underflow Interrupt Enable

Enables/disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1, 2, 4, and 5. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TCIU) by TCFU disabled 1: Interrupt requests (TCIU) by TCFU enabled

4 TCIEV 0 R/W Overflow Interrupt Enable

Enables/disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. 0: Interrupt requests (TCIV) by TCFV disabled 1: Interrupt requests (TCIV) by TCFV enabled

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 741 of 1438 REJ09B0365-0200 Bit Bit Name Initial value R/W Description

3 TGIED 0 R/W TGR Interrupt Enable D

Enables/disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TGID) by TGFD bit disabled 1: Interrupt requests (TGID) by TGFD bit enabled

2 TGIEC 0 R/W TGR Interrupt Enable C

Enables/disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TGIC) by TGFC bit disabled 1: Interrupt requests (TGIC) by TGFC bit enabled

1 TGIEB 0 R/W TGR Interrupt Enable B

Enables/disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. 0: Interrupt requests (TGIB) by TGFB bit disabled 1: Interrupt requests (TGIB) by TGFB bit enabled

0 TGIEA 0 R/W TGR Interrupt Enable A

Enables/disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. 0: Interrupt requests (TGIA) by TGFA bit disabled 1: Interrupt requests (TGIA) by TGFA bit enabled Note: * The bit 7 in TIER of unit 1 is a reserved bit This bit is always read as 0 and the initial value should not be changed.

14.3.5 Timer Status Register (TSR)

TSR indicates the status of each channel. The TPU has six TSR registers, one for each channel. Bit Bit Name Initial Value R/W TCFD R TCFU R/(W)* TCFV R/(W)* TGFD R/(W)* TGFC R/(W)* TGFB R/(W)* TGFA R/(W)* Note: * Only 0 can be written to bits 5 to 0, to clear flags.

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 742 of 1438 REJ09B0365-0200 Bit Bit Name Initial value R/W Description

7 TCFD 1 R Count Direction Flag

Status flag that shows the direction in which TCNT counts in channels 1, 2, 4, and 5. In channels 0 and 3, bit 7 is reserved. It is always read as 1 and cannot be modified. 0: TCNT counts down 1: TCNT counts up 6  1  Reserved This bit is always read as 1 and cannot be modified.

5 TCFU 0 R/(W) * Underflow Flag

Status flag that indicates that a TCNT underflow has occurred when channels 1, 2, 4, and 5 are set to phase counting mode. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified. [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When a 0 is written to TCFU after reading TCFU = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)

4 TCFV 0 R/(W) * Overflow Flag

Status flag that indicates that a TCNT overflow has occurred. [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000) [Clearing condition] When a 0 is written to TCFV after reading TCFV = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 743 of 1438 REJ09B0365-0200 Bit Bit Name Initial value R/W Description

3 TGFD 0 R/(W) * Input Capture/Output Compare Flag D

Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified. [Setting conditions]

• When TCNT = TGRD while TGRD is functioning as output compare register
• When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register [Clearing conditions]
• When DTC is activated by a TGID interrupt while the DISEL bit in MRB of DTC is 0
• When 0 is written to TGFD after reading TGFD = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)

2 TGFC 0 R/(W) * Input Capture/Output Compare Flag C

Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified. [Setting conditions]

• When TCNT = TGRC while TGRC is functioning as output compare register
• When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register [Clearing conditions]
• When DTC is activated by a TGIC interrupt while the DISEL bit in MRB of DTC is 0
• When 0 is written to TGFC after reading TGFC = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 744 of 1438 REJ09B0365-0200 Bit Bit Name Initial value R/W Description

1 TGFB 0 R/(W) * Input Capture/Output Compare Flag B

Status flag that indicates the occurrence of TGRB input capture or compare match. [Setting conditions]

• When TCNT = TGRB while TGRB is functioning as output compare register
• When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register [Clearing conditions]
• When DTC is activated by a TGIB interrupt while the DISEL bit in MRB of DTC is 0
• When 0 is written to TGFB after reading TGFB = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)

0 TGFA 0 R/(W) * Input Capture/Output Compare Flag A

Status flag that indicates the occurrence of TGRA input capture or compare match. [Setting conditions]

• When TCNT = TGRA while TGRA is functioning as output compare register
• When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register [Clearing conditions]
• When DTC is activated by a TGIA interrupt while the DISEL bit in MRB of DTC is 0
• When DMAC is activated by a TGIA interrupt while the DTA bit in DMDR of DTC is 1
• When 0 is written to TGFA after reading TGFA = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Note: * Only 0 can be written to clear the flag.

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 745 of 1438 REJ09B0365-0200

14.3.6 Timer Counter (TCNT)

TCNT is a 16-bit readable/writable counter. The TPU has six TCNT counters, one for each channel. TCNT is initialized to H'0000 by a reset or in hardware standby mode. TCNT cannot be accessed in 8-bit units. TCNT must always be accessed in 16-bit units. Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W

14.3.7 Timer General Register (TGR)

TGR is a 16-bit readable/writable register with a dual function as output compare and input capture registers. The TPU has 16 TGR registers, four each for channels 0 and 3 and two each for channels 1, 2, 4, and 5. TGRC and TGRD for channels 0 and 3 can also be designated for operation as buffer registers. The TGR registers cannot be accessed in 8-bit units; they must always be accessed in 16-bit units. TGR and buffer register combinations during buffer operations are TGRA−TGRC and TGRB−TGRD. Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 746 of 1438 REJ09B0365-0200

14.3.8 Timer Start Register (TSTR)

TSTR starts or stops operation for channels 0 to 5. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. CST5 R/W CST4 R/W CST3 R/W CST2 R/W CST1 R/W CST0 R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial value R/W Description 7, 6  All 0  Reserved The write value should always be 0. CST5 CST4 CST3 CST2 CST1 CST0 R/W R/W R/W R/W R/W R/W Counter Start 5 to 0 These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_5 to TCNT_0 count operation is stopped 1: TCNT_5 to TCNT_0 performs count operation

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 747 of 1438 REJ09B0365-0200

14.3.9 Timer Synchronous Register (TSYR)

TSYR selects independent operation or synchronous operation for the TCNT counters of channels 0 to 5. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. R/W R/W SYNC5 R/W SYNC4 R/W SYNC3 R/W SYNC2 R/W SYNC1 R/W SYNC0 R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial value R/W Description 7, 6  All 0 R/W Reserved The write value should always be 0. SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 R/W R/W R/W R/W R/W R/W Timer Synchronization 5 to 0 These bits select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, synchronous presetting of multiple channels, and synchronous clearing through counter clearing on another channel are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR. 0: TCNT_5 to TCNT_0 operate independently (TCNT presetting/clearing is unrelated to other channels) 1: TCNT_5 to TCNT_0 perform synchronous operation (TCNT synchronous presetting/synchronous clearing is possible)

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 748 of 1438 REJ09B0365-0200

14.4 Operation

14.4.1 Basic Functions

Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, periodic counting, and external event counting. Each TGR can be used as an input capture register or output compare register. (1) Counter Operation When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on. (a) Example of count operation setting procedure Figure 14.3 shows an example of the count operation setting procedure. Select counter clock Operation selection Select counter clearing source Periodic counter Set period Start count <Periodic counter> [1] [2] [4] [3] [5] Free-running counter Start count <Free-running counter> [5] [1] [2] [3] [4] [5] Select output compare register Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. Designate the TGR selected in [2] as an output compare register by means of TIOR. Set the periodic counter cycle in the TGR selected in [2]. Set the CST bit in TSTR to 1 to start the counter operation. Figure 14.3 Example of Counter Operation Setting Procedure

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14.4.2 Synchronous Operation

In synchronous operation, the values in multiple TCNT counters can be rewritten simultaneously (synchronous presetting). Also, multiple TCNT counters can be cleared simultaneously (synchronous clearing) by making the appropriate setting in TCR. Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 5 can all be designated for synchronous operation. (1) Example of Synchronous Operation Setting Procedure Figure 14.11 shows an example of the synchronous operation setting procedure. Synchronous operation selection Set TCNT Synchronous presetting <Synchronous presetting> [1] [2] Synchronous clearing Select counter clearing source <Counter clearing> [3] Start count [5] Set synchronous counter clearing <Synchronous clearing> [4] Start count [5] Clearing source generation channel? No Yes [1] Set the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation to 1. [2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. [3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. [4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. [5] Set the CST bits in TSTR for the relevant channels to 1, to start the count operation. Set synchronous operation Figure 14.11 Example of Synchronous Operation Setting Procedure

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14.4.3 Buffer Operation

Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or a compare match register. Table 14.30 shows the register combinations used in buffer operation. Table 14.30 Register Combinations in Buffer Operation Channel Timer General Re gister Buffer Register TGRA_0 TGRC_0 0 TGRB_0 TGRD_0 TGRA_3 TGRC_3 3 TGRB_3 TGRD_3

• When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 14.13. Buffer register Timer general register TCNTComparator Compare match signal Figure 14.13 Compare Match Buffer Operation

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14.4.4 Cascaded Operation

In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4) counter clock at overflow/underflow of TCNT_2 (TCNT_5) as set in bits TPSC2 to TPSC0 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 14.31 shows the register combinations used in cascaded operation. Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid and the counter operates independently in phase counting mode. Table 14.31 Cascaded Combinations Combination Upper 16 Bits Lower 16 Bits Channels 1 and 2 TCNT_1 TCNT_2 Channels 4 and 5 TCNT_4 TCNT_5 (1) Example of Cascaded Operation Setting Procedure Figure 14.18 shows an example of the setting procedure for cascaded operation. Cascaded operation Set cascading Start count <Cascaded operation> Set bits TPSC2 to TPSC0 in the channel 1 (channel 4) TCR to B'1111 to select TCNT_2 (TCNT_5) overflow/underflow counting. Set the CST bit in TSTR for the upper and lower channels to 1 to start the count operation. [1] [2] [1] [2] Figure 14.18 Cascaded Operation Setting Procedure

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14.4.5 PWM Modes

In PWM mode, PWM waveforms are output from the output pins. 0-, 1-, or toggle-output can be selected as the output level in response to compare match of each TGR. Settings of TGR registers can output a PWM waveform in the range of 0% to 100% duty cycle. Designating TGR compare match as the counter clearing source enables the cycle to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below. 1. PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The outputs specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR are output from the TIOCA and TIOCC pins at compare matches A and C, respectively. The outputs specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR are output at compare matches B and D, respectively. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 8-phase PWM output is possible. 2. PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty cycle registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a synchronous register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty cycle registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 15-phase PWM output is possible by combined use with synchronous operation. The correspondence between PWM output pins and registers is shown in table 14.32.

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 763 of 1438 REJ09B0365-0200 Table 14.32 PWM Output Registers and Output Pins Output Pins Channel Registers PWM Mode 1 PWM Mode 2 TGRA_0 TIOCA0 TGRB_0 TIOCA0 TIOCB0 TGRC_0 TIOCC0 TGRD_0 TIOCC0 TIOCD0 TGRA_1 TIOCA1 1 TGRB_1 TIOCA1 TIOCB1 TGRA_2 TIOCA2 2 TGRB_2 TIOCA2 TIOCB2 TGRA_3 TIOCA3 TGRB_3 TIOCA3 TIOCB3 TGRC_3 TIOCC3 TGRD_3 TIOCC3 TIOCD3 TGRA_4 TIOCA4 4 TGRB_4 TIOCA4 TIOCB4 TGRA_5 TIOCA5 5 TGRB_5 TIOCA5 TIOCB5 Note: In PWM mode 2, PWM output is not possible fo r the TGR register in which the cycle is set.

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14.4.6 Phase Counting Mode

In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be used. This can be used for two-phase encoder pulse input. When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow occurs while TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of whether TCNT is counting up or down. Table 14.33 shows the correspondence between external clock pins and channels. Table 14.33 Clock Input Pins in Phase Counting Mode External Clock Pins Channels A-Phase B-Phase When channel 1 or 5 is set to phase counting mode TCLKA TCLKB When channel 2 or 4 is set to phase counting mode TCLKC TCLKD

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14.5 Interrupt Sources

There are three kinds of TPU interrupt sources: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disable bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priority levels can be changed by the interrupt controller, but the priority within a channel is fixed. For details, see section 7, Interrupt Controller. Table 14.38 lists the TPU interrupt sources. Table 14.38 TPU Interrupts Channel Name Interrupt Source Interrupt Flag DTC Activation DMAC Activation

0 TGI0A TGRA_0 input capture/com pare match TGFA_0 Possible Possible

TGI0B TGRB_0 input capture/compar e match TGFB_0 Possi ble Not possible TGI0C TGRC_0 input capture/compar e match TGFC_0 Possible Not possible TGI0D TGRD_0 input capture/compar e match TGFD_0 Possible Not possible TCI0V TCNT_0 overflow TCFV _0 Not possible Not possible

1 TGI1A TGRA_1 input capture/com pare match TGFA_1 Possible Possible

TGI1B TGRB_1 input capture/compar e match TGFB_1 Possi ble Not possible TCI1V TCNT_1 overflow TCFV _1 Not possible Not possible TCI1U TCNT_1 underflow TCFU _1 Not possible Not possible

2 TGI2A TGRA_2 input capture/com pare match TGFA_2 Possible Possible

TGI2B TGRB_2 input capture/compar e match TGFB_2 Possi ble Not possible TCI2V TCNT_2 overflow TCFV _2 Not possible Not possible TCI2U TCNT_2 underflow TCFU _2 Not possible Not possible

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 775 of 1438 REJ09B0365-0200 Channel Name Interrupt Source Interrupt Flag DTC Activation DMAC Activation

3 TGI3A TGRA_3 input capture/com pare match TGFA_3 Possible Possible

TGI3B TGRB_3 input capture/compar e match TGFB_3 Possi ble Not possible TGI3C TGRC_3 input capture/compar e match TGFC_3 Possible Not possible TGI3D TGRD_3 input capture/compar e match TGFD_3 Possible Not possible TCI3V TCNT_3 overflow TCFV _3 Not possible Not possible

4 TGI4A TGRA_4 input capture/com pare match TGFA_4 Possible Possible

TGI4B TGRB_4 input capture/compar e match TGFB_4 Possi ble Not possible TCI4V TCNT_4 overflow TCFV _4 Not possible Not possible TCI4U TCNT_4 underflow TCFU _4 Not possible Not possible

5 TGI5A TGRA_5 input capture/com pare match TGFA_5 Possible Possible

TGI5B TGRB_5 input capture/compar e match TGFB_5 Possi ble Not possible TCI5V TCNT_5 overflow TCFV _5 Not possible Not possible TCI5U TCNT_5 underflow TCFU _5 Not possible Not possible Note: This table shows the initial state immediat ely after a reset. The relative channel priority levels can be changed by the interrupt controller. (1) Input Capture/Compare Match Interrupt An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. (2) Overflow Interrupt An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of a TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The TPU has six overflow interrupts, one for each channel. (3) Underflow Interrupt An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of a TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The TPU has four underflow interrupts, one each for channels 1, 2, 4, and 5.

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14.6 DTC Activation

The DTC can be activated by the TGR input capture/compare match interrupt for a channel. For details, see section 12, Data Transfer Controller (DTC). A total of 16 TPU input capture/compare match interrupts can be used as DTC activation sources, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5.

14.7 DMAC Activation

The DMAC can be activated by the TGRA input capture/compare match interrupt for a channel. For details, see section 10, DMA Controller (DMAC). In TPU, one in each channel, totally six TGRA input capture/compare match interrupts can be used as DMAC activation sources.

14.8 A/D Converter Activation

Concerning the unit 0 in TPU, the TGRA input capture/compare match for each channel can activate the A/D converter. (However, the A/D converter cannot be activated in unit 1.) If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel, a request to start A/D conversion is sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started. In the TPU, a total of six TGRA input capture/compare match interrupts can be used as A/D converter conversion start sources, one for each channel.

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14.9 Operation Timing

14.9.1 Input/Output Timing

(1) TCNT Count Timing Figure 14.31 shows TCNT count timing in internal clock operation, and figure 14.32 shows TCNT count timing in external clock operation. Pφ Internal clock TCNT input clock TCNT Falling edge Rising edge N − 1N + 1N + 2N Falling edge Figure 14.31 Count Timing in Internal Clock Operation Pφ External clock TCNT input clock TCNT Falling edge Rising edge N − 1N + 1N + 2N Falling edge Figure 14.32 Count Timing in External Clock Operation

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14.9.2 Interrupt Signal Timing

(1) TGF Flag Setting Timing in Case of Compare Match Figure 14.39 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and the TGI interrupt request signal timing. TGR Compare match signal Pφ TCNT input clock TCNT N + 1N N TGF flag TGI interrupt Figure 14.39 TGI Interrupt Timing (Compare Match) (2) TGF Flag Setting Timing in Case of Input Capture Figure 14.40 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and the TGI interrupt request signal timing. TGR Pφ TCNT N Input capture signal TGF flag TGI interrupt N Figure 14.40 TGI Interrupt Timing (Input Capture)

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 783 of 1438 REJ09B0365-0200 (4) Status Flag Clearing Timing After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC or DMAC is activated, the flag is cleared automatically. Figure 14.43 shows the timing for status flag clearing by the CPU, and figures 12.44 and 12.45 show the timing for status flag clearing by the DTC or DMAC. Status flag Pφ Interrupt request signal Address Write T1 T2 TSR address TSR write cycle Figure 14.43 Timing for Status Flag Clearing by CPU The status flag and interrupt request signal are cleared in synchronization with Pφ after the DTC or DMAC transfer has started, as shown in figure 14.44. If conflict occurs for clearing the status flag and interrupt request signal due to activation of multiple DTC or DMAC transfers, it will take up to five clock cycles (Pφ) for clearing them, as shown in figure 14.45. The next transfer request is masked for a longer period of either a period until the current transfer ends or a period for five clock cycles (Pφ) from the beginning of the transfer. Note that in the DTC transfer, the status flag may be cleared during outputting the destination address.

Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Jul. 31, 2008 Page 785 of 1438 REJ09B0365-0200

14.10 Usage Notes

14.10.1 Module Stop Function Setting

Operation of the TPU can be disabled or enabled using the module stop control register. The initial setting is for operation of the TPU to be halted. Register access is enabled by clearing module stop state. For details, see section 27, Power-Down Modes.

14.10.2 Input Clock Restrictions

The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 14.46 shows the input clock conditions in phase counting mode. TCLKA (TCLKC) TCLKB (TCLKD) Overlap Phase difference Pulse width Note: Phase difference, Overlap ≥ 1.5 states Pulse width ≥ 2.5 states Pulse width Phase difference Overlap Pulse width Pulse width Figure 14.46 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode

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14.10.3 Caution on Cycle Setting

When counter clearing by compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: f = Pφ (N + 1) Pφ: Counter frequency Operating frequency TGR set value

14.10.4 Conflict between TCNT Write and Clear Operations

If the counter clearing signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 14.47 shows the timing in this case. Counter clear signal H'0000 Pφ TCNT N Address Write T1 T2 TCNT address TCNT write cycle Figure 14.47 Conflict between TCNT Write and Clear Operations

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14.10.5 Conflict between TCNT Write and Increment Operations

If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 14.48 shows the timing in this case. Pφ TCNT input clock TCNT N Address Write T1 T2 TCNT write cycle M TCNT write data TCNT address Figure 14.48 Conflict between TCNT Write and Increment Operations

14.10.6 Conflict between TGR Write and Compare Match

If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is disabled. A compare match also does not occur when the same value as before is written. Figure 14.49 shows the timing in this case. TGR Compare match signal Pφ TCNT N + 1N Address Write T1 T2 M TGR address TGR write cycle N Disabled TGR write data Figure 14.49 Conflict between TGR Write and Compare Match

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14.10.7 Conflict between Buffer Register Write and Compare Match

If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the write data. Figure 14.50 shows the timing in this case. TGR Compare match signal Pφ N Address Write T1 T2 M TGR write cycle Buffer register address Data written to buffer register M Buffer register Figure 14.50 Conflict between Buffer Register Write and Compare Match

14.10.8 Conflict between TGR Read and Input Capture

If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 14.51 shows the timing in this case. TGR Pφ Input capture signal Address TGR address Read T1 T2 TGR read cycle XM MInternal data bus Figure 14.51 Conflict between TGR Read and Input Capture

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14.10.9 Conflict between TGR Write and Input Capture

If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 14.52 shows the timing in this case. TCNT Pφ Input capture signal Address TGR address Write T1 T2 TGR write cycle M MTGR Figure 14.52 Conflict between TGR Write and Input Capture

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14.10.10 Conflict between Buffer Register Write and Input Capture

If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 14.53 shows the timing in this case. TCNT Pφ Input capture signal Address Buffer register address Write T1 T2 Buffer register write cycle N NTGR Buffer register M M Figure 14.53 Conflict between Buffer Register Write and Input Capture

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14.10.11 Conflict between Overflow/Underflow and Counter Clearing

If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 14.54 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR. Counter clear signal H'0000 Pφ TCNT input clock TCNT TGF flag TCFV flag H'FFFF Disabled Figure 14.54 Conflict between Overflow and Counter Clearing

14.10.12 Conflict between TCNT Write and Overflow/Underflow

If an overflow/underflow occurs due to increment/decrement in the T2 state of a TCNT write cycle, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 14.55 shows the operation timing when there is conflict between TCNT write and overflow. Pφ TCNT H'FFFF TCFV flag Address Write TCNT address M TCNT write data T1 T2 TGR write cycle Figure 14.55 Conflict between TCNT Write and Overflow

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14.10.13 Multiplexing of I/O Pins

In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not be performed from a multiplexed pin.

14.10.14 PPG1 Setting when TPU1 Pin is Used

When the TPU1 pin is used, the NDER bit of the PPG1 pin multiplexed with the TPU1 pin should be cleared to halt the output. For details, see section 13, I/O Ports.

14.10.15 Interrupts and Module Stop Mode

If module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DTC and DMAC activation sources. Interrupts should therefore be disabled before entering module stop mode.

Section 15 Programmable Pulse Generator (PPG) Rev. 2.00 Jul. 31, 2008 Page 793 of 1438 REJ09B0365-0200 Section 15 Programmable Pulse Generator (PPG) The programmable pulse generator (PPG) provides pulse outputs by using the 16-bit timer pulse unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (groups 3 to 0) that can operate both simultaneously and independently. Figures 13.1 and 13.2 show a block diagram of the PPG.

15.1 Features

• 32-bit output data
• Four output groups
• Selectable output trigger signals
• Non-overlapping mode
• Can operate together with the data transfer controller (DTC) and DMA controller (DMAC)
• Inverted output can be set
• Module stop state specifiable Table 15.1 List of PPG Functions Function PPG0 PPG1 Compare match Possible Not possible TPU0 Input capture Possible Not possible Compare match Not possible Possible PPG output trigger TPU1 Input capture Not possible Not possible Non-overlapping mode Possible Possible DTC Possible Possible Output data transfer DMAC Possible Possible Inverted output Possible Possible

Section 15 Programmable Pulse Generator (PPG) Rev. 2.00 Jul. 31, 2008 Page 794 of 1438 REJ09B0365-0200 Compare match signals PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 PO7 PO6 PO5 PO4 PO3 PO2 PO1 PO0 [Legend] PMR: PCR: NDERH: NDERL: PPG output mode register PPG output control register Next data enable register H Next data enable register L NDRH: NDRL: PODRH: PODRL: Next data register H Next data register L Output data register H Output data register L Internal data bus Pulse output pins, group 3 Pulse output pins, group 2 Pulse output pins, group 1 Pulse output pins, group 0 PODRH PODRL NDRH NDRL Control logic NDERH PMR NDERL PCR Figure 15.1 Block Diagram of PPG (Unit 0)

Section 15 Programmable Pulse Generator (PPG) Rev. 2.00 Jul. 31, 2008 Page 795 of 1438 REJ09B0365-0200 Compare match signals PO31 PO30 PO29 PO28 PO27 PO26 PO25 PO24 PO23 PO22 PO21 PO20 PO19 PO18 PO17 PO16 [Legend] PMR_1: PCR_1: NDERH_1: NDERL_1: PPG output mode register_1 PPG output control register_1 Next data enable register H_1 Next data enable register L_1 NDRH_1: NDRL_1: PODRH_1: PODRL_1: Next data register H_1 Next data register L_1 Output data register H_1 Output data register L_1 Internal data bus Pulse output pins, group 7 Pulse output pins, group 6 Pulse output pins, group 5 Pulse output pins, group 4 PODRH_1 PODRL_1 NDRH_1 NDRL_1 Control logic NDERH_1 PMR_1 NDERL_1 PCR_1 Figure 15.2 Block Diagram of PPG (Unit 1)

Section 15 Programmable Pulse Generator (PPG) Rev. 2.00 Jul. 31, 2008 Page 796 of 1438 REJ09B0365-0200

15.2 Input/Output Pins

Table 15.2 shows the PPG pin configuration. Table 15.2 Pin Configuration Unit Pin Name I/O Function PO0 Output PO1 Output PO2 Output PO3 Output Group 0 pulse output PO4 Output PO5 Output PO6 Output PO7 Output Group 1 pulse output PO8 Output PO9 Output PO10 Output PO11 Output Group 2 pulse output PO12 Output PO13 Output PO14 Output PO15 Output Group 3 pulse output

Section 15 Programmable Pulse Generator (PPG) Rev. 2.00 Jul. 31, 2008 Page 797 of 1438 REJ09B0365-0200 Unit Pin Name I/O Function PO16 Output PO17 Output PO18 Output PO19 Output Group 4 pulse output PO20 Output PO21 Output PO22 Output PO23 Output Group 5 pulse output PO24 Output PO25 Output PO26 Output PO27 Output Group 6 pulse output PO28 Output PO29 Output PO30 Output PO31 Output Group 7 pulse output

Section 15 Programmable Pulse Generator (PPG) Rev. 2.00 Jul. 31, 2008 Page 798 of 1438 REJ09B0365-0200

15.3 Register Descriptions

The PPG has the following registers. Unit 0:

• Next data enable register H (NDERH)
• Next data enable register L (NDERL)
• Output data register H (PODRH)
• Output data register L (PODRL)
• Next data register H (NDRH)
• Next data register L (NDRL)
• PPG output control register (PCR)
• PPG output mode register (PMR) Unit 1:
• Next data enable register H_1 (NDERH_1)
• Next data enable register L_1 (NDERL_1)
• Output data register H_1 (PODRH_1)
• Output data register L_1 (PODRL_1)
• Next data register H_1 (NDRH_1)
• Next data register L_1 (NDRL_1)
• PPG output control register_1 (PCR_1)
• PPG output mode register_1 (PMR_1)

Section 15 Programmable Pulse Generator (PPG) Rev. 2.00 Jul. 31, 2008 Page 799 of 1438 REJ09B0365-0200

15.3.1 Next Data Enable Registers H, L (NDERH, NDERL)

NDERH and NDERL enable/disable pulse output on a bit-by-bit basis.

• NDERH NDER15 R/W NDER14 R/W NDER13 R/W NDER12 R/W NDER11 R/W NDER10 R/W NDER9 R/W NDER8 R/W Bit Bit Name Initial Value R/W
• NDERL NDER7 R/W NDER6 R/W NDER5 R/W NDER4 R/W NDER3 R/W NDER2 R/W NDER1 R/W NDER0 R/W Bit Bit Name Initial Value R/W
• NDERH Bit Bit Name Initial Value R/W Description NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 R/W R/W R/W R/W R/W R/W R/W R/W Next Data Enable 15 to 8 When a bit is set to 1, the value in the corresponding NDRH bit is transferred to the PODRH bit by the selected output trigger. Values are not transferred from NDRH to PODRH for cleared bits.

Section 15 Programmable Pulse Generator (PPG) Rev. 2.00 Jul. 31, 2008 Page 800 of 1438 REJ09B0365-0200

• NDERL Bit Bit Name Initial Value R/W Description NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 R/W R/W R/W R/W R/W R/W R/W R/W Next Data Enable 7 to 0 When a bit is set to 1, the value in the corresponding NDRL bit is transferred to the PODRL bit by the selected output trigger. Values are not transferred from NDRL to PODRL for cleared bits.
• NDERH_1 Bit Bit Name Initial Value R/W Description NDER31 NDER30 NDER29 NDER28 NDER27 NDER26 NDER25 NDER24 R/W R/W R/W R/W R/W R/W R/W R/W Next Data Enable 31 to 24 When a bit is set to 1, the value in the corresponding NDRH_1 bit is transferred to the PODRH_1 bit by the selected output trigger. Values are not transferred from NDRH_1 to PODRH_1 for cleared bits.

Section 15 Programmable Pulse Generator (PPG) Rev. 2.00 Jul. 31, 2008 Page 801 of 1438 REJ09B0365-0200

• NDERL_1 Bit Bit Name Initial Value R/W Description NDER23 NDER22 NDER21 NDER20 NDER19 NDER18 NDER17 NDER16 R/W R/W R/W R/W R/W R/W R/W R/W Next Data Enable 23 to 16 When a bit is set to 1, the value in the corresponding NDRL_1 bit is transferred to the PODRL_1 bit by the selected output trigger. Values are not transferred from NDRL_1 to PODRL_1 for cleared bits.

15.3.2 Output Data Registers H, L (PODRH, PODRL)

PODRH and PODRL store output data for use in pulse output. A bit that has been set for pulse output by NDER is read-only and cannot be modified.

• PODRH POD15 R/W POD14 R/W POD13 R/W POD12 R/W POD11 R/W POD10 R/W POD9 R/W POD8 R/W Bit Bit Name Initial Value R/W
• PODRL POD7 R/W POD6 R/W POD5 R/W POD4 R/W POD3 R/W POD2 R/W POD1 R/W POD0 R/W Bit Bit Name Initial Value R/W

Section 15 Programmable Pulse Generator (PPG) Rev. 2.00 Jul. 31, 2008 Page 802 of 1438 REJ09B0365-0200

• PODRH Bit Bit Name Initial Value R/W Description POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8 R/W R/W R/W R/W R/W R/W R/W R/W Output Data Register 15 to 8 For bits which have been set to pulse output by NDERH, the output trigger transfers NDRH values to this register during PPG operation. While NDERH is set to 1, the CPU cannot write to this register. While NDERH is cleared, the initial output value of the pulse can be set.
• PODRL Bit Bit Name Initial Value R/W Description POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0 R/W R/W R/W R/W R/W R/W R/W R/W Output Data Register 7 to 0 For bits which have been set to pulse output by NDERL, the output trigger transfers NDRL values to this register during PPG operation. While NDERL is set to 1, the CPU cannot write to this register. While NDERL is cleared, the initial output value of the pulse can be set.

Section 15 Programmable Pulse Generator (PPG) Rev. 2.00 Jul. 31, 2008 Page 803 of 1438 REJ09B0365-0200

• PODRH_1 Bit Bit Name Initial Value R/W Description POD31 POD30 POD29 POD28 POD27 POD26 POD25 POD24 R/W R/W R/W R/W R/W R/W R/W R/W Output Data Register 31 to 24 For bits which have been set to pulse output by NDERH_1, the output trigger transfers NDRH_1 values to this register during PPG operation. While NDERH_1 is set to 1, the CPU cannot write to this register. While NDERH_1 is cleared, the initial output value of the pulse can be set.
• PODRL_1 Bit Bit Name Initial Value R/W Description POD23 POD22 POD21 POD20 POD19 POD18 POD17 POD16 R/W R/W R/W R/W R/W R/W R/W R/W Output Data Register 23 to 16 For bits which have been set to pulse output by NDERL_1, the output trigger transfers NDRL_1 values to this register during PPG operation. While NDERL_1 is set to 1, the CPU cannot write to this register. While NDERL_1 is cleared, the initial output value of the pulse can be set.

Section 15 Programmable Pulse Generator (PPG) Rev. 2.00 Jul. 31, 2008 Page 804 of 1438 REJ09B0365-0200

15.3.3 Next Data Registers H, L (NDRH, NDRL)

NDRH and NDRL store the next data for pulse output. The NDR addresses differ depending on whether pulse output groups have the same output trigger or different output triggers.

• NDRH Bit Bit Name Initial Value R/W NDR15 R/W NDR14 R/W NDR13 R/W NDR12 R/W NDR11 R/W NDR10 R/W NDR9 R/W NDR8 R/W
• NDRL Bit Bit Name Initial Value R/W NDR7 R/W NDR6 R/W NDR5 R/W NDR4 R/W NDR3 R/W NDR2 R/W NDR1 R/W NDR0 R/W
• NDRH If pulse output groups 2 and 3 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. Bit Bit Name Initial Value R/W Description NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 R/W R/W R/W R/W R/W R/W R/W R/W Next Data Register 15 to 8 The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR.

Section 15 Programmable Pulse Generator (PPG) Rev. 2.00 Jul. 31, 2008 Page 805 of 1438 REJ09B0365-0200 If pulse output groups 2 and 3 have different output triggers, the upper four bits and lower four bits are mapped to different addresses as shown below. Bit Bit Name Initial Value R/W Description NDR15 NDR14 NDR13 NDR12 R/W R/W R/W R/W Next Data Register 15 to 12 The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR. 3 to 0  All 1  Reserved These bits are always read as 1 and cannot be modified. Bit Bit Name Initial Value R/W Description 7 to 4  All 1  Reserved These bits are always read as 1 and cannot be modified. NDR11 NDR10 NDR9 NDR8 R/W R/W R/W R/W Next Data Register 11 to 8 The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR.

Section 15 Programmable Pulse Generator (PPG) Rev. 2.00 Jul. 31, 2008 Page 806 of 1438 REJ09B0365-0200

• NDRL If pulse output groups 0 and 1 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. Bit Bit Name Initial Value R/W Description NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 R/W R/W R/W R/W R/W R/W R/W R/W Next Data Register 7 to 0 The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR. If pulse output groups 0 and 1 have different output triggers, the upper four bits and lower four bits are mapped to different addresses as shown below. Bit Bit Name Initial Value R/W Description NDR7 NDR6 NDR5 NDR4 R/W R/W R/W R/W Next Data Register 7 to 4 The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR. 3 to 0  All 1  Reserved These bits are always read as 1 and cannot be modified. Bit Bit Name Initial Value R/W Description 7 to 4  All 1  Reserved These bits are always read as 1 and cannot be modified. NDR3 NDR2 NDR1 NDR0 R/W R/W R/W R/W Next Data Register 3 to 0 The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR.

Section 15 Programmable Pulse Generator (PPG) Rev. 2.00 Jul. 31, 2008 Page 807 of 1438 REJ09B0365-0200

• NDRH_1 If pulse output groups 6 and 7 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. Bit Bit Name Initial Value R/W Description NDR31 NDR30 NDR29 NDR28 NDR27 NDR26 NDR25 NDR24 R/W R/W R/W R/W R/W R/W R/W R/W Next Data Register 31 to 24 The register contents are transferred to the corresponding PODRH_1 bits by the output trigger specified with PCR_1. If pulse output groups 6 and 7 have different output triggers, the upper four bits and lower four bits are mapped to different addresses as shown below. Bit Bit Name Initial Value R/W Description NDR31 NDR30 NDR29 NDR28 R/W R/W R/W R/W Next Data Register 31 to 28 The register contents are transferred to the corresponding PODRH_1 bits by the output trigger specified with PCR_1. 3 to 0  All 1  Reserved These bits are always read as 1 and cannot be modified. Bit Bit Name Initial Value R/W Description 7 to 4  All 1  Reserved These bits are always read as 1 and cannot be modified. NDR27 NDR26 NDR25 NDR24 R/W R/W R/W R/W Next Data Register 27 to 24 The register contents are transferred to the corresponding PODRH_1 bits by the output trigger specified with PCR_1.

Section 15 Programmable Pulse Generator (PPG) Rev. 2.00 Jul. 31, 2008 Page 808 of 1438 REJ09B0365-0200

• NDRL_1 If pulse output groups 4 and 5 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. Bit Bit Name Initial Value R/W Description NDR23 NDR22 NDR21 NDR20 NDR19 NDR18 NDR17 NDR16 R/W R/W R/W R/W R/W R/W R/W R/W Next Data Register 23 to 16 The register contents are transferred to the corresponding PODRL_1 bits by the output trigger specified with PCR_1. If pulse output groups 4 and 5 have different output triggers, the upper four bits and lower four bits are mapped to different addresses as shown below. Bit Bit Name Initial Value R/W Description NDR23 NDR22 NDR21 NDR20 R/W R/W R/W R/W Next Data Register 23 to 20 The register contents are transferred to the corresponding PODRL_1 bits by the output trigger specified with PCR_1. 3 to 0  All 1  Reserved These bits are always read as 1 and cannot be modified. Bit Bit Name Initial Value R/W Description 7 to 4  All 1  Reserved These bits are always read as 1 and cannot be modified. NDR19 NDR18 NDR17 NDR16 R/W R/W R/W R/W Next Data Register 19 to 16 The register contents are transferred to the corresponding PODRL_1 bits by the output trigger specified with PCR_1.

Section 15 Programmable Pulse Generator (PPG) Rev. 2.00 Jul. 31, 2008 Page 809 of 1438 REJ09B0365-0200

15.3.4 PPG Output Control Register (PCR)

PCR selects output trigger signals on a group-by-group basis. For details on output trigger selection, refer to section 15.3.5, PPG Output Mode Register (PMR). G3CMS1 R/W G3CMS0 R/W G2CMS1 R/W G2CMS0 R/W G1CMS1 R/W G1CMS0 R/W G0CMS1 R/W G0CMS0 R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description G3CMS1 G3CMS0 R/W R/W Group 3 Compare Match Select 1 and 0 These bits select output trigger of pulse output group 3. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3 G2CMS1 G2CMS0 R/W R/W Group 2 Compare Match Select 1 and 0 These bits select output trigger of pulse output group 2. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3 G1CMS1 G1CMS0 R/W R/W Group 1 Compare Match Select 1 and 0 These bits select output trigger of pulse output group 1. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3 G0CMS1 G0CMS0 R/W R/W Group 0 Compare Match Select 1 and 0 These bits select output trigger of pulse output group 0. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3

Section 15 Programmable Pulse Generator (PPG) Rev. 2.00 Jul. 31, 2008 Page 810 of 1438 REJ09B0365-0200

• PCR_1 Bit Bit Name Initial Value R/W Description G3CMS1 G3CMS0 R/W R/W Group 7 Compare Match Select 1 and 0 These bits select output trigger of pulse output group 7. 00: Compare match in TPU channel 6 01: Compare match in TPU channel 7 10: Compare match in TPU channel 8 11: Compare match in TPU channel 9 G2CMS1 G2CMS0 R/W R/W Group 6 Compare Match Select 1 and 0 These bits select output trigger of pulse output group 6. 00: Compare match in TPU channel 6 01: Compare match in TPU channel 7 10: Compare match in TPU channel 8 11: Compare match in TPU channel 9 G1CMS1 G1CMS0 R/W R/W Group 5 Compare Match Select 1 and 0 These bits select output trigger of pulse output group 5. 00: Compare match in TPU channel 6 01: Compare match in TPU channel 7 10: Compare match in TPU channel 8 11: Compare match in TPU channel 9 G0CMS1 G0CMS0 R/W R/W Group 4 Compare Match Select 1 and 0 These bits select output trigger of pulse output group 4. 00: Compare match in TPU channel 6 01: Compare match in TPU channel 7 10: Compare match in TPU channel 8 11: Compare match in TPU channel 9

Section 15 Programmable Pulse Generator (PPG) Rev. 2.00 Jul. 31, 2008 Page 811 of 1438 REJ09B0365-0200

15.3.5 PPG Output Mo de Register (PMR)

PMR selects the pulse output mode of the PPG for each group. If inverted output is selected, a low-level pulse is output when PODRH is 1 and a high-level pulse is output when PODRH is 0. If non-overlapping operation is selected, PPG updates its output values at compare match A or B of the TPU that becomes the output trigger. For details, refer to section 15.4.4, Non-Overlapping Pulse Output. G3INV R/W G2INV R/W G1INV R/W G0INV R/W G3NOV R/W G2NOV R/W G1NOV R/W G0NOV R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description

7 G3INV 1 R/W Group 3 Inversion

Selects direct output or inverted output for pulse output group 3. 0: Inverted output 1: Direct output

6 G2INV 1 R/W Group 2 Inversion

Selects direct output or inverted output for pulse output group 2. 0: Inverted output 1: Direct output

5 G1INV 1 R/W Group 1 Inversion

Selects direct output or inverted output for pulse output group 1. 0: Inverted output 1: Direct output

4 G0INV 1 R/W Group 0 Inversion

Selects direct output or inverted output for pulse output group 0. 0: Inverted output 1: Direct output

Section 15 Programmable Pulse Generator (PPG) Rev. 2.00 Jul. 31, 2008 Page 812 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description

3 G3NOV 0 R/W Group 3 Non-Overlap

Selects normal or non-overlapping operation for pulse output group 3. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel)

2 G2NOV 0 R/W Group 2 Non-Overlap

Selects normal or non-overlapping operation for pulse output group 2. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel)

1 G1NOV 0 R/W Group 1 Non-Overlap

Selects normal or non-overlapping operation for pulse output group 1. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel)

0 G0NOV 0 R/W Group 0 Non-Overlap

Selects normal or non-overlapping operation for pulse output group 0. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel)

Section 15 Programmable Pulse Generator (PPG) Rev. 2.00 Jul. 31, 2008 Page 813 of 1438 REJ09B0365-0200

• PMR_1 Bit Bit Name Initial Value R/W Description

7 G3INV 1 R/W Group 7 Inversion

Selects direct output or inverted output for pulse output group 7. 0: Inverted output 1: Direct output

6 G2INV 1 R/W Group 6 Inversion

Selects direct output or inverted output for pulse output group 6. 0: Inverted output 1: Direct output

5 G1INV 1 R/W Group 5 Inversion

Selects direct output or inverted output for pulse output group 5. 0: Inverted output 1: Direct output

4 G0INV 1 R/W Group 4 Inversion

Selects direct output or inverted output for pulse output group 4. 0: Inverted output 1: Direct output

3 G3NOV 0 R/W Group 7 Non-Overlap

Selects normal or non-overlapping operation for pulse output group 7. 0: Normal operation (output values updated by compare match A on the selected TPU channel) 1: Non-overlapping operation (output values updated by compare match A or B on the selected TPU channel)

Section 15 Programmable Pulse Generator (PPG) Rev. 2.00 Jul. 31, 2008 Page 814 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description

2 G2NOV 0 R/W Group 6 Non-Overlap

Selects normal or non-overlapping operation for pulse output group 6. 0: Normal operation (output values updated by compare match A on the selected TPU channel) 1: Non-overlapping operation (output values updated by compare match A or B on the selected TPU channel)

1 G1NOV 0 R/W Group 5 Non-Overlap

Selects normal or non-overlapping operation for pulse output group 5. 0: Normal operation (output values updated by compare match A on the selected TPU channel) 1: Non-overlapping operation (output values updated by compare match A or B on the selected TPU channel)

0 G0NOV 0 R/W Group 4 Non-Overlap

Selects normal or non-overlapping operation for pulse output group 4. 0: Normal operation (output values updated by compare match A on the selected TPU channel) 1: Non-overlapping operation (output values updated by compare match A or B on the selected TPU channel)

Section 15 Programmable Pulse Generator (PPG) Rev. 2.00 Jul. 31, 2008 Page 815 of 1438 REJ09B0365-0200

15.4 Operation

Figure 15.3 shows a schematic diagram of the PPG. PPG pulse output is enabled when the corresponding bits in NDER are set to 1. An initial output value is determined by its corresponding PODR initial setting. When the compare match event specified by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output values. Sequential output of data of up to 16 bits is possible by writing new output data to NDR before the next compare match. Output trigger signal Pulse output pin Internal data bus Normal output/inverted output C PODRQD NDER Q NDRQD Figure 15.3 Schematic Diagram of PPG

15.4.1 Output Timing

If pulse output is enabled, the NDR contents are transferred to PODR and output when the specified compare match event occurs. Figure 15.4 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. TCNT N N + 1 Pφ TGRA N Compare match A signal NDRH mnPODRH PO8 to PO15 n m n Figure 15.4 Timing of Transfer and Output of NDR Contents (Example)

Section 15 Programmable Pulse Generator (PPG) Rev. 2.00 Jul. 31, 2008 Page 816 of 1438 REJ09B0365-0200

15.4.2 Sample Setup Procedure for Normal Pulse Output

Figures 13.5 and 13.6 show a sample procedure for setting up normal pulse output.

• Sample Setup Procedure for PPG0 Select TGR functions [1] Set TGRA value Set counting operation Select interrupt request Set initial output data Enable pulse output Select output trigger Set next pulse output data Start counter Set next pulse output data Normal PPG output No Yes TPU0 setup PPG0 setup TPU0 setup [2] [3] [4] [5] [6] [7] [8] [9] [10] Compare match? [1] Set TIOR in TPU0 to make TGRA an output compare register (with output disabled). [2] Set the PPG output trigger cycle. [3] Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. [4] Enable the TGIA interrupt in TIER. The DTC or DMAC can also be set up to transfer data to NDR. [5] Set the initial output values in PODR. [6] Set the bits in NDER for the pins to be used for pulse output to 1. [7] Select the TPU compare match event to be used as the output trigger in PCR. [8] Set the next pulse output values in NDR. [9] Set the CST bit in TSTR to 1 to start the TCNT counter. [10] At each TGIA interrupt, set the next Figure 15.5 Setup Procedure for Normal Pulse Output (PPG0)

Section 15 Programmable Pulse Generator (PPG) Rev. 2.00 Jul. 31, 2008 Page 817 of 1438 REJ09B0365-0200

• Sample Setup Procedure for PPG1 Select TGR functions [1] Set TGRA value Set counting operation Select interrupt request Set initial output data Enable pulse output Select output trigger Set next pulse output data Start counter Set next pulse output data Normal PPG output No Yes TPU1 setup PPG1 setup TPU1 setup [2] [3] [4] [5] [6] [7] [8] [9] [10] Compare match? [1] Set TIOR in TPU1 to make TGRA an output compare register (toggle output). [2] Set the PPG output trigger cycle. [3] Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. [4] Enable the TGIA interrupt in TIER. The DTC or DMAC can also be set up to transfer data to NDR. [5] Set the initial output values in PODR. [6] Set the bits in NDER for the pins to be used for pulse output to 1. [7] Select the TPU compare match event to be used as the output trigger in PCR. [8] Set the next pulse output values in NDR. [9] Set the CST bit in TSTR to 1 to start the TCNT counter. [10] At each TGIA interrupt, set the next output values in NDR. Figure 15.6 Setup Procedure for Normal Pulse Output (PPG1)

Section 15 Programmable Pulse Generator (PPG) Rev. 2.00 Jul. 31, 2008 Page 818 of 1438 REJ09B0365-0200

15.4.3 Example of Normal Pulse Output (Example of 5-Phase Pulse Output)

Figure 15.7 shows an example in which pulse output is used for cyclic 5-phase pulse output. TCNT value TCNT TGRA H'0000 NDRH 00 80 C0 40 60 20 30 10 18 08 88PODRH PO15 PO14 PO13 PO12 PO11 Time Compare match C080 C080 40 60 20 30 10 18 08 88 80 C0 40 Figure 15.7 Normal Pulse Output Example (5-Phase Pulse Output) 1. Set up TGRA in TPU which is used as the outp ut trigger to be an output compare register. Set a cycle in TGRA so the counter will be cleared by compare match A. Set the TGIEA bit in TIER to 1 to enable the compare match/input capture A (TGIA) interrupt. 2. Write H'F8 to NDERH, and set bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger. Write output data H'80 in NDRH. 3. The timer counter in the TPU channel starts. When compare match A occurs, the NDRH contents are transferred to PODRH and output. The TGIA interrupt handling routine writes the next output data (H'C0) in NDRH. 4. 5-phase pulse output (one or two phases active at a time) can be obtained subsequently by writing H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88... at successive TGIA interrupts. If the DTC or DMAC is set for activation by the TGIA interrupt, pulse output can be obtained without imposing a load on the CPU.

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15.4.4 Non-Overlapping Pulse Output

During non-overlapping operation, transfer from NDR to PODR is performed as follows:

• At compare match A, the NDR bits are always transferred to PODR.
• At compare match B, the NDR bits are transferred only if their value is 0. The NDR bits are not transferred if their value is 1. Figure 15.8 illustrates the non-overlapping pulse output operation. Compare match A Compare match B Pulse output pin Internal data bus Normal output/inverted output C PODRQD NDER Q NDRQD Figure 15.8 Non-Overlapping Pulse Output Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. The NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlapping margin). This can be accomplished by having the TGIA interrupt handling routine write the next data in NDR, or by having the TGIA interrupt activate the DTC or DMAC. Note, however, that the next data must be written before the next compare match B occurs.

Section 15 Programmable Pulse Generator (PPG) Rev. 2.00 Jul. 31, 2008 Page 821 of 1438 REJ09B0365-0200

15.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output

Figures 13.10 and 13.11 show a sample procedure for setting up non-overlapping pulse output.

• Sample Setup Procedure for PPG0 Select TGR functions [1] Set TGR values Set counting operation Select interrupt request Set initial output data Enable pulse output Select output trigger Set next pulse output data Start counter Set next pulse output data Compare match A? No Yes TPU0 setup PPG0 setup TPU0 setup Non-overlapping pulse output Set non-overlapping groups [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [1] Set TIOR in TPU0 to make TGRA and TGRB output compare registers (with output disabled). [2] Set the pulse output trigger cycle in TGRB and the non-overlapping margin in TGRA. [3] Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. [4] Enable the TGIA interrupt in TIER. The DTC or DMAC can also be set up to transfer data to NDR. [5] Set the initial output values in PODR. [6] Set the bits in NDER for the pins to be used for pulse output to 1. [7] Select the TPU compare match event to be used as the pulse output trigger in PCR. [8] In PMR, select the groups that will operate in non-overlapping mode. [9] Set the next pulse output values in NDR. [10] Set the CST bit in TSTR to 1 to start the TCNT counter. [11] At each TGIA interrupt, set the next output values in NDR. Figure 15.10 Setup Procedure for Non-Overlapping Pulse Output (PPG0)

Section 15 Programmable Pulse Generator (PPG) Rev. 2.00 Jul. 31, 2008 Page 822 of 1438 REJ09B0365-0200

• Sample Setup Procedure for PPG1 Select TGR functions [1] Set TGR values Set counting operation Select interrupt request Set initial output data Enable pulse output Select output trigger Set next pulse output data Start counter Set next pulse output data Compare match A? No Yes TPU1 setup PPG1 setup TPU1 setup Non-overlapping pulse output Set non-overlapping groups [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [1] Set TIOR in TPU1 to make TGRA and TGRB output compare registers (toggle output). [2] Set the pulse output trigger cycle in TGRB and the non-overlapping margin in TGRA. [3] Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. [4] Enable the TGIA interrupt in TIER. The DTC or DMAC can also be set up to transfer data to NDR. [5] Set the initial output values in PODR. [6] Set the bits in NDER for the pins to be used for pulse output to 1. [7] Select the TPU compare match event to be used as the pulse output trigger in PCR. [8] In PMR, select the groups that will operate in non-overlapping mode. [9] Set the next pulse output values in NDR. [10] Set the CST bit in TSTR to 1 to start the TCNT counter. [11] At each TGIA interrupt, set the next output values in NDR. Figure 15.11 Setup Procedure for Non-Overlapping Pulse Output (PPG1)

Section 15 Programmable Pulse Generator (PPG) Rev. 2.00 Jul. 31, 2008 Page 823 of 1438 REJ09B0365-0200

15.4.6 Example of Non-Overlapping Pulse Output (Example of 4-Phase Complementary

Non-Overlapping Pulse Output) Figure 15.12 shows an example in which pulse output is used for 4-phase complementary non- overlapping pulse output. TCNT value TCNT TGRB TGRA H'0000 NDRH 95 65 59 56 95 65 00 95 05 65 41 59 50 56 14 95 05 65PODRH PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Time Non-overlapping margin Figure 15.12 Non-Overlapping Pulse Output Example (4-Phase Complementary)

Section 15 Programmable Pulse Generator (PPG) Rev. 2.00 Jul. 31, 2008 Page 824 of 1438 REJ09B0365-0200 1. Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are output compare registers. Set the cycle in TGRB and the non-overlapping margin in TGRA, and set the counter to be cleared by compare match B. Set the TGIEA bit in TIER to 1 to enable the TGIA interrupt. 2. Write H'FF to NDERH, and set bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger. Set bits G3NOV and G2NOV in PMR to 1 to select non-overlapping pulse output. Write output data H'95 to NDRH. 3. The timer counter in the TPU channel starts. When a compare match with TGRB occurs, outputs change from 1 to 0. When a compare match with TGRA occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed by the value set in TGRA). The TGIA interrupt handling routine writes the next output data (H'65) to NDRH. 4. 4-phase complementary non-overlapping pulse output can be obtained subsequently by writing H'59, H'56, H'95... at successive TGIA interrupts. If the DTC or DMAC is set for activation by a TGIA interrupt, pulse can be output without imposing a load on the CPU.

Section 15 Programmable Pulse Generator (PPG) Rev. 2.00 Jul. 31, 2008 Page 825 of 1438 REJ09B0365-0200

15.4.7 Inverted Pulse Output

If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the inverse of the PODR contents can be output. Figure 15.13 shows the outputs when the G3INV and G2INV bits are cleared to 0, in addition to the settings of figure 15.12. TCNT value TCNT TGRB TGRA H'0000 NDRH 95 65 59 56 95 65 00 95 05 65 41 59 50 56 14 95 05 65PODRL PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Time Figure 15.13 Inverted Pulse Output (Example)

Section 15 Programmable Pulse Generator (PPG) Rev. 2.00 Jul. 31, 2008 Page 826 of 1438 REJ09B0365-0200

15.4.8 Pulse Output Triggered by Input Capture

Pulse output of PPG0 can be triggered by TPU0 input capture as well as by compare match. If TGRA functions as an input capture register in the TPU0 channel selected by PCR, pulse output will be triggered by the input capture signal. Figure 15.14 shows the timing of this output. PPG1 cannot be used to trigger pulse output by input capturer. Pφ N MN TIOC pin Input capture signal NDR PODR MNPO Figure 15.14 Pulse Output Triggered by Input Capture (Example)

Section 15 Programmable Pulse Generator (PPG) Rev. 2.00 Jul. 31, 2008 Page 827 of 1438 REJ09B0365-0200

15.5 Usage Notes

15.5.1 Module Stop State Setting

PPG operation can be disabled or enabled using the module stop control register. The initial value is for PPG operation to be halted. Register access is enabled by clearing the module stop state. For details, refer to section 27, Power-Down Modes.

15.5.2 Operation of Pulse Output Pins

Pins PO0 to PO15 are also used for other peripheral functions such as the TPU. When output by another peripheral function is enabled, the corresponding pins cannot be used for pulse output. Note, however, that data transfer from NDR bits to PODR bits takes place, regardless of the usage of the pins. Pin functions should be changed only under conditions in which the output trigger event will not occur.

15.5.3 TPU Setting when PPG1 is in Use

When using PPG1, output toggling on compare-matches must be specified in the TIOR register of the TPU that acts as the activation source and output must be selected as the PPG1 function.

Section 15 Programmable Pulse Generator (PPG) Rev. 2.00 Jul. 31, 2008 Page 828 of 1438 REJ09B0365-0200

Section 16 8-Bit Timers (TMR) Rev. 2.00 Jul. 31, 2008 Page 829 of 1438 REJ09B0365-0200 Section 16 8-Bit Timers (TMR) This LSI has four units (unit 0 to unit 3) of an on-chip 8-bit timer module that comprise two 8-bit counter channels, totaling eight channels. The 8-bit timer module can be used to count external events and also be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with a desired duty cycle using a compare-match signal with two registers. Figures 14.1 to 14.4 show block diagrams of the 8-bit timer module (unit 0 to unit 3). This section describes unit 0 (channels 0 and 1) and unit 2 (channels 4 and 5), both of which have the same functions. Unit 2 and unit 3 can generate baud rate clock for SCI and have the same functions.

16.1 Features

• Selection of seven clock sources The counters can be driven by one of six internal clock signals (Pφ/2, Pφ/8, Pφ/32, Pφ/64, Pφ/1024, or Pφ/8192) or an external clock input (only internal clock available in units 2 and 3: Pφ, Pφ/2, Pφ/8, Pφ/32, Pφ/64, Pφ/1024, and Pφ/8192).
• Selection of three ways to clear the counters The counters can be cleared on compare match A or B, or by an external reset signal. (This is available only in unit 0 and unit 1.)
• Timer output control by a combination of two compare match signals The timer output signal in each channel is controlled by a combination of two independent compare match signals, enabling the timer to output pulses with a desired duty cycle or PWM output.
• Cascading of two channels Operation as a 16-bit timer is possible, using TMR_0 for the upper 8 bits and TMR_1 for the lower 8 bits (16-bit count mode). TMR_1 can be used to count TMR_0 compare matches (compare match count mode).
• Three interrupt sources Compare match A, compare match B, and overflow interrupts can be requested independently. (This is available only in unit 0 and unit 1.)
• Generation of trigger to start A/D converter conversion (available in unit 0 and unit 1 only)
• Capable of generating baud rate clock for SCI_5 and SCI_6. (This is available only in unit 2 and unit 3). For details, see section 19, Serial Communication Interface (SCI, IrDA, CRC).
• Module stop state specifiable

Section 16 8-Bit Timers (TMR) Rev. 2.00 Jul. 31, 2008 Page 830 of 1438 REJ09B0365-0200 CMIA0 CMIA1 CMIB0 CMIB1 OVI0 OVI1 TMO0 TMO1 TMCI0 TMCI1 TMRI0 TMRI1 TCORA_1: TCNT_1: TCORB_1: TCSR_1: TCR_1: TCCR_1: TCORA_0: TCNT_0: TCORB_0: TCSR_0: TCR_0: TCCR_0: Pφ/2 Pφ/8 Pφ/32 Pφ/64 Pφ/1024 Pφ/8192 Counter clock 1 Counter clock 0 Compare match A1 Compare match A0 Overflow 1 Overflow 0 Counter clear 0 Counter clear 1 Compare match B1 Compare match B0 Comparator A_0 Comparator A_1 TCORA_0 TCORB_0 TCSR_0 TCCR_0 TCORA_1 TCNT_1 TCORB_1 TCSR_1 TCCR_1 TCR_0 TCR_1 TCNT_0 Comparator B_0 Comparator B_1 A/D conversion start request signal* Internal bus Time constant register A_1 Timer counter_1 Time constant register B_1 Timer control/status register_1 Timer control register_1 Timer counter control register_1 Time constant register A_0 Timer counter_0 Time constant register B_0 Timer control/status register_0 Timer control register_0 Timer counter control register_0 Interrupt signals Internal clocks Clock select Control logic External clocks [Legend] Channel 1 (TMR_1) Channel 0 (TMR_0) Note: * For the corresponding A/D converter channels, see section 21, A/D Converter. Figure 16.1 Block Diagram of 8-Bit Timer Module (Unit 0)

Section 16 8-Bit Timers (TMR) Rev. 2.00 Jul. 31, 2008 Page 831 of 1438 REJ09B0365-0200 CMIA2 CMIA3 CMIB2 CMIB3 OVI2 OVI3 TMO2 TMO3 TMCI2 TMCI3 TMRI2 TMRI3 TCORA_3: TCNT_3: TCORB_3: TCSR_3: TCR_3: TCCR_3: TCORA_2: TCNT_2: TCORB_2: TCSR_2: TCR_2: TCCR_2: Pφ/2 Pφ/8 Pφ/32 Pφ/64 Pφ/1024 Pφ/8192 Counter clock 3 Counter clock 2 Compare match A3 Compare match A2 Overflow 3 Overflow 2 Counter clear 2 Counter clear 3 Compare match B3 Compare match B2 Comparator A_2 Comparator A_3 TCORA_2 TCORB_2 TCSR_2 TCCR_2 TCORA_3 TCNT_3 TCORB_3 TCSR_3 TCCR_3 TCR_2 TCR_3 TCNT_2 Comparator B_2 Comparator B_3 A/D conversion start request signal* Internal bus Time constant register A_3 Timer counter_3 Time constant register B_3 Timer control/status register_3 Timer control register_3 Timer counter control register_3 Time constant register A_2 Timer counter_2 Time constant register B_2 Timer control/status register_2 Timer control register_2 Timer counter control register_2 Interrupt signals Internal clocks Clock select Control logic External clocks [Legend] Channel 3 (TMR_3) Channel 2 (TMR_2) Note: * For the corresponding A/D converter channels, see section 21, A/D Converter. Figure 16.2 Block Diagram of 8-Bit Timer Module (Unit 1)

Section 16 8-Bit Timers (TMR) Rev. 2.00 Jul. 31, 2008 Page 832 of 1438 REJ09B0365-0200 CMIA4 CMIB4 CMIA5 CMIB5 TCORA_5: TCNT_5: TCORB_5: TCSR_5: TCR_5: TCCR_5: TCORA_4: TCNT_4: TCORB_4: TCSR_4: TCR_4: TCCR_4: Pφ Pφ/2 Pφ/8 Pφ/32 Pφ/64 Pφ/1024 Pφ/8192 Counter clock 5 Counter clock 4 Compare match A5 Compare match A4 Overflow 5 Overflow 4 TMO4 TMO5 To SCI_5 Counter clear 4 Counter clear5 Compare match B5 Compare match B4 Comparator A_4 Comparator A_5 TCORA_4 TCORB_4 TCSR_4 TCCR_4 TCORA_5 TCNT_5 TCORB_5 TCSR_5 TCCR_5 CMI4 CMI5 TCR_4 TCR_5 TCNT_4 Comparator B_4 Comparator B_5 Internal bus Time constant register A_5 Timer counter_5 Time constant register B_5 Timer control/status register_5 Timer control register_5 Timer counter control register_5 Time constant register A_4 Timer counter_4 Time constant register B_4 Timer control/status register_4 Timer control register_4 Timer counter control register_4 Interrupt signals Internal clocks Clock select Control logic [Legend] Channel 5 (TMR_5) Channel 4 (TMR_4) Note: * For the corresponding A/D converter channels, see section 21, A/D Converter. A/D conversion start request signal* Figure 16.3 Block Diagram of 8-Bit Timer Module (Unit 2)

Section 16 8-Bit Timers (TMR) Rev. 2.00 Jul. 31, 2008 Page 833 of 1438 REJ09B0365-0200 TCORA_7: TCNT_7: TCORB_7: TCSR_7: TCR_7: TCCR_7: TCORA_6: TCNT_6: TCORB_6: TCSR_6: TCR_6: TCCR_6: Pφ Pφ/2 Pφ/8 Pφ/32 Pφ/64 Pφ/1024 Pφ/8192 Counter clock 7 Counter clock 6 Compare match A7 Compare match A6 Overflow 7 Overflow 6 Counter clear 6 Counter clear 7 Compare match B7 Compare match B6 Comparator A_6 Comparator A_7 TCORA_6 TCORB_6 TCSR_6 TCCR_6 TCORA_7 TCNT_7 TCORB_7 TCSR_7 TCCR_7 TCR_6 TCR_7 TCNT_6 Comparator B_6 Comparator B_7 Internal bus Time constant register A_7 Timer counter_7 Time constant register B_7 Timer control/status register_7 Timer control register_7 Timer counter control register_7 Time constant register A_6 Timer counter_6 Time constant register B_6 Timer control/status register_6 Timer control register_6 Timer counter control register_6 Interrupt signals Internal clocks Clock select Control logic [Legend] CMIA6 CMIB6 CMIA7 CMIB7 CMI6 CMI7 Channel 7 (TMR_7) Channel 6 (TMR_6) TMO6 TMO7 To SCI_6 A/D conversion start request signal* Note: * For the corresponding A/D converter channels, see section 21, A/D Converter. Figure 16.4 Block Diagram of 8-Bit Timer Module (Unit 3)

Section 16 8-Bit Timers (TMR) Rev. 2.00 Jul. 31, 2008 Page 834 of 1438 REJ09B0365-0200

16.2 Input/Output Pins

Table 16.1 shows the pin configuration of the TMR. Table 16.1 Pin Configuration Unit Channel Name Symbol I/O Function 0 0 Timer output pin TMO0 Output Outputs compare match Timer clock input pin TMCI0 Input Inputs external clock for counter Timer reset input pin TMRI0 Input Inputs external reset to counter

1 Timer output pin TMO1 Output Outputs compare match

Timer clock input pin TMCI1 Input Inputs external clock for counter Timer reset input pin TMRI1 Input Inputs external reset to counter 1 2 Timer output pin TMO2 Output Outputs compare match Timer clock input pin TMCI2 Input Inputs external clock for counter Timer reset input pin TMRI2 Input Inputs external reset to counter

3 Timer output pin TMO3 Output Outputs compare match

Timer clock input pin TMCI3 Input Inputs external clock for counter Timer reset input pin TMRI3 Input Inputs external reset to counter 2 4     3 6

Section 16 8-Bit Timers (TMR) Rev. 2.00 Jul. 31, 2008 Page 835 of 1438 REJ09B0365-0200

16.3 Register Descriptions

The TMR has the following registers. Unit 0:

• Channel 0 (TMR_0):  Timer counter_0 (TCNT_0)  Time constant register A_0 (TCORA_0)  Time constant register B_0 (TCORB_0)  Timer control register_0 (TCR_0)  Timer counter control register_0 (TCCR_0)  Timer control/status register_0 (TCSR_0)
• Channel 1 (TMR_1):  Timer counter_1 (TCNT_1)  Time constant register A_1 (TCORA_1)  Time constant register B_1 (TCORB_1)  Timer control register_1 (TCR_1)  Timer counter control register_1 (TCCR_1)  Timer control/status register_1 (TCSR_1) Unit 1:
• Channel 2 (TMR_2):  Timer counter_2 (TCNT_2)  Time constant register A_2 (TCORA_2)  Time constant register B_2 (TCORB_2)  Timer control register_2 (TCR_2)  Timer counter control register_2 (TCCR_2)  Timer control/status register_2 (TCSR_2)
• Channel 3 (TMR_3):  Timer counter_3 (TCNT_3)  Time constant register A_3 (TCORA_3)  Time constant register B_3 (TCORB_3)  Timer control register_3 (TCR_3)  Timer counter control register_3 (TCCR_3)  Timer control/status register_3 (TCSR_3)

Section 16 8-Bit Timers (TMR) Rev. 2.00 Jul. 31, 2008 Page 836 of 1438 REJ09B0365-0200 Unit 2:

• Channel 4 (TMR_4):  Timer counter_4 (TCNT_4)  Time constant register A_4 (TCORA_4)  Time constant register B_4 (TCORB_4)  Timer control register_4 (TCR_4)  Timer counter control register_4 (TCCR_4)  Timer control/status register_4 (TCSR_4)
• Channel 5 (TMR_5):  Timer counter_5 (TCNT_5)  Time constant register A_5 (TCORA_5)  Time constant register B_5 (TCORB_5)  Timer control register_5 (TCR_5)  Timer counter control register_5 (TCCR_5)  Timer control/status register_5 (TCSR_5) Unit 3:
• Channel 6 (TMR_6):  Timer counter_6 (TCNT_6)  Time constant register A_6 (TCORA_6)  Time constant register B_6 (TCORB_6)  Timer control register_6 (TCR_6)  Timer counter control register_6 (TCCR_6)  Timer control/status register_6 (TCSR_6)
• Channel 7 (TMR_7):  Timer counter_7 (TCNT_7)  Time constant register A_7 (TCORA_7)  Time constant register B_7 (TCORB_7)  Timer control register_7 (TCR_7)  Timer counter control register_7 (TCCR_7)  Timer control/status register_7 (TCSR_7)

Section 16 8-Bit Timers (TMR) Rev. 2.00 Jul. 31, 2008 Page 837 of 1438 REJ09B0365-0200

16.3.1 Timer Counter (TCNT)

TCNT is an 8-bit readable/writable up-counter. TCNT_0 and TCNT_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. Bits CKS2 to CKS0 in TCR and bits ICKS1 and ICKS0 in TCCR are used to select a clock. TCNT can be cleared by an external reset input signal, compare match A signal, or compare match B signal. Which signal to be used for clearing is selected by bits CCLR1 and CCLR0 in TCR. When TCNT overflows from H'FF to H'00, bit OVF in TCSR is set to 1. TCNT is initialized to H'00. R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT_0 TCNT_1 Bit Bit Name Initial Value R/W

16.3.2 Time Constant Register A (TCORA)

TCORA is an 8-bit readable/writable register. TCORA_0 and TCORA_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. The value in TCORA is continually compared with the value in TCNT. When a match is detected, the corresponding CMFA flag in TCSR is set to 1. Note however that comparison is disabled during the T2 state of a TCORA write cycle. The timer output from the TMO pin can be freely controlled by this compare match signal (compare match A) and the settings of bits OS1 and OS0 in TCSR. TCORA is initialized to H'FF. R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORA_0 TCORA_1 Bit Bit Name Initial Value R/W

Section 16 8-Bit Timers (TMR) Rev. 2.00 Jul. 31, 2008 Page 838 of 1438 REJ09B0365-0200

16.3.3 Time Constant Register B (TCORB)

TCORB is an 8-bit readable/writable register. TCORB_0 and TCORB_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. TCORB is continually compared with the value in TCNT. When a match is detected, the corresponding CMFB flag in TCSR is set to 1. Note however that comparison is disabled during the T2 state of a TCORB write cycle. The timer output from the TMO pin can be freely controlled by this compare match signal (compare match B) and the settings of bits OS3 and OS2 in TCSR. TCORB is initialized to H'FF. R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORB_0 TCORB_1 Bit Bit Name Initial Value R/W

16.3.4 Timer Control Register (TCR)

TCR selects the TCNT clock source and the condition for clearing TCNT, and enables/disables interrupt requests. CMIEB R/W CMIEA R/W OVIE R/W CCLR1 R/W CCLR0 R/W CKS2 R/W CKS1 R/W CKS0 R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description

7 CMIEB 0 R/W Compare Match Interrupt Enable B

Selects whether CMFB interrupt requests (CMIB) are enabled or disabled when the CMFB flag in TCSR is set to 1. * 0: CMFB interrupt requests (CMIB) are disabled 1: CMFB interrupt requests (CMIB) are enabled

Section 16 8-Bit Timers (TMR) Rev. 2.00 Jul. 31, 2008 Page 839 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description

6 CMIEA 0 R/W Compare Match Interrupt Enable A

Selects whether CMFA interrupt requests (CMIA) are enabled or disabled when the CMFA flag in TCSR is set to 1. * 0: CMFA interrupt requests (CMIA) are disabled 1: CMFA interrupt requests (CMIA) are enabled

5 OVIE 0 R/W Timer Overflow Interrupt Enable *

Selects whether OVF interrupt requests (OVI) are enabled or disabled when the OVF flag in TCSR is set to 0: OVF interrupt requests (OVI) are disabled 1: OVF interrupt requests (OVI) are enabled CCLR1 CCLR0 R/W R/W Counter Clear 1 and 0* These bits select the method by which TCNT is cleared. 00: Clearing is disabled 01: Cleared by compare match A 10: Cleared by compare match B 11: Cleared at rising edge (TMRIS in TCCR is cleared to 0) of the external reset input or when the external reset input is high (TMRIS in TCCR is set to 1) * CKS2 CKS1 CKS0 R/W R/W R/W Clock Select 2 to 0* These bits select the clock input to TCNT and count condition. See table 16.2. Notes: 1. To use an external reset or external clock, the DDR and ICR bits in the corresponding pin should be set to 0 and 1, respectively. For details, see section 13, I/O Ports. 2. In unit 2 and unit 3, one interrupt signal is used for CMIEB or CMIEA. For details, see section 16.7, Interrupt Sources. 3. Available only in unit 0 and unit 1.

Section 16 8-Bit Timers (TMR) Rev. 2.00 Jul. 31, 2008 Page 840 of 1438 REJ09B0365-0200

16.3.5 Timer Counter Co ntrol Register (TCCR)

TCCR selects the TCNT internal clock source and controls external reset input. R R R R TMRIS R/W R ICKS1 R/W ICKS0 R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description 7 to 4  All 0 R Reserved These bits are always read as 0. It should not be set to 0.

3 TMRIS 0 R/W Timer Reset Input Select *

Selects an external reset input when the CCLR1 and CCLR0 bits in TCR are B'11. 0: Cleared at rising edge of the external reset 1: Cleared when the external reset is high 2  0 R Reserved This bit is always read as 0. It should not be set to 0. ICKS1 ICKS0 R/W R/W Internal Clock Select 1 and 0 These bits in combination with bits CKS2 to CKS0 in TCR select the internal clock. See table 16.2. Note: * Available only in unit 0 and unit 1. The writ e value should always be 0 in unit 2 and unit

Section 16 8-Bit Timers (TMR) Rev. 2.00 Jul. 31, 2008 Page 841 of 1438 REJ09B0365-0200 Table 16.2 Clock Input to TCNT and Count Condition (Unit 0) TCR TCCR Channel Bit 2 CKS2 Bit 1 CKS1 Bit 0 CKS0 Bit 1 ICKS1 Bit 0 ICKS0 Description TMR_0 0 0 0   Clock input prohibited 0 0 1 0 0 Uses internal clock. Counts at rising edge of P φ/8. 0 1 Uses internal clock. Counts at rising edge of P φ/2. 1 0 Uses internal clock. Counts at falling edge of P φ/8. 1 1 Uses internal clock. Counts at falling edge of P φ/2. 0 1 0 0 0 Uses internal clock. Counts at rising edge of P φ/64. 0 1 Uses internal clock. Counts at rising edge of P φ/32. 1 0 Uses internal clock. Counts at falling edge of P φ/64. 1 1 Uses internal clock. Counts at falling edge of P φ/32. 0 1 1 0 0 Uses internal clock. Counts at rising edge of P φ/8192. 0 1 Uses internal clock. Counts at rising edge of P φ/1024. 1 0 Uses internal clock. Counts at falling edge of P φ/8192. 1 1 Uses internal clock. Counts at falling edge of P φ/1024. 1 0 0   Counts at TCNT_1 overflow signal * TMR_1 0 0 0   Clock input prohibited 0 0 1 0 0 Uses internal clock. Counts at rising edge of P φ/8. 0 1 Uses internal clock. Counts at rising edge of P φ/2. 1 0 Uses internal clock. Counts at falling edge of P φ/8. 1 1 Uses internal clock. Counts at falling edge of P φ/2. 0 1 0 0 0 Uses internal clock. Counts at rising edge of P φ/64. 0 1 Uses internal clock. Counts at rising edge of P φ/32. 1 0 Uses internal clock. Counts at falling edge of P φ/64. 1 1 Uses internal clock. Counts at falling edge of P φ/32. 0 1 1 0 0 Uses internal clock. Counts at rising edge of P φ/8192. 0 1 Uses internal clock. Counts at rising edge of P φ/1024. 1 0 Uses internal clock. Counts at falling edge of P φ/8192. 1 1 Uses internal clock. Counts at falling edge of P φ/1024. 1 0 0   Counts at TCNT_0 compare match A * All 1 0 1   Uses external clock. Counts at rising edge * 1 1 0   Uses external clock. Counts at falling edge * 1 1 1   Uses external clock. Counts at both rising and falling edges* Notes: 1. If the clock input of channel 0 is the T CNT_1 overflow signal and that of channel 1 is the TCNT_0 compare match signal, no incrementing clock is generated. Do not use this setting. 2. To use the external clock, the DDR and I CR bits in the corresponding pin should be set to 0 and 1, respectively. For details, see section 13, I/O Ports.

Section 16 8-Bit Timers (TMR) Rev. 2.00 Jul. 31, 2008 Page 842 of 1438 REJ09B0365-0200 Table 16.3 Clock Input to TCNT and Count Condition (Unit 1) TCR TCCR Channel Bit 2 CKS2 Bit 1 CKS1 Bit 0 CKS0 Bit 1 ICKS1 Bit 0 ICKS0 Description TMR_2 0 0 0   Clock input prohibited 0 0 1 0 0 Uses internal clock. Counts at rising edge of P φ/8. 0 1 Uses internal clock. Counts at rising edge of P φ/2. 1 0 Uses internal clock. Counts at falling edge of P φ/8. 1 1 Uses internal clock. Counts at falling edge of P φ/2. 0 1 0 0 0 Uses internal clock. Counts at rising edge of P φ/64. 0 1 Uses internal clock. Counts at rising edge of P φ/32. 1 0 Uses internal clock. Counts at falling edge of P φ/64. 1 1 Uses internal clock. Counts at falling edge of P φ/32. 0 1 1 0 0 Uses internal clock. Counts at rising edge of P φ/8192. 0 1 Uses internal clock. Counts at rising edge of P φ/1024. 1 0 Uses internal clock. Counts at falling edge of P φ/8192. 1 1 Uses internal clock. Counts at falling edge of P φ/1024. 1 0 0   Counts at TCNT_3 overflow signal * TMR_3 0 0 0   Clock input prohibited 0 0 1 0 0 Uses internal clock. Counts at rising edge of P φ/8. 0 1 Uses internal clock. Counts at rising edge of P φ/2. 1 0 Uses internal clock. Counts at falling edge of P φ/8. 1 1 Uses internal clock. Counts at falling edge of P φ/2. 0 1 0 0 0 Uses internal clock. Counts at rising edge of P φ/64. 0 1 Uses internal clock. Counts at rising edge of P φ/32. 1 0 Uses internal clock. Counts at falling edge of P φ/64. 1 1 Uses internal clock. Counts at falling edge of P φ/32. 0 1 1 0 0 Uses internal clock. Counts at rising edge of P φ/8192. 0 1 Uses internal clock. Counts at rising edge of P φ/1024. 1 0 Uses internal clock. Counts at falling edge of P φ/8192. 1 1 Uses internal clock. Counts at falling edge of P φ/1024. 1 0 0   Counts at TCNT_2 compare match A * All 1 0 1   Uses external clock. Counts at rising edge * 1 1 0   Uses external clock. Counts at falling edge * 1 1 1   Uses external clock. Counts at both rising and falling edges* Notes: 1. If the clock input of channel 2 is the T CNT_3 overflow signal and that of channel 3 is the TCNT_2 compare match signal, no incrementing clock is generated. Do not use this setting. 2. To use the external clock, the DDR and I CR bits in the corresponding pin should be set to 0 and 1, respectively. For details, see section 13, I/O Ports.

Section 16 8-Bit Timers (TMR) Rev. 2.00 Jul. 31, 2008 Page 843 of 1438 REJ09B0365-0200 Table 16.4 Clock Input to TCNT and Count Condition (Unit 2) TCR TCCR Channel Bit 2 CKS2 Bit 1 CKS1 Bit 0 CKS0 Bit 1 ICKS1 Bit 0 ICKS0 Description TMR_4 0 0 0   Clock input prohibited 0 0 1 0 0 Uses internal clock. Counts at rising edge of P φ/8. 0 1 Uses internal clock. Counts at rising edge of P φ/2. 1 0 Uses internal clock. Counts at falling edge of P φ/8. 1 1 Uses internal clock. Counts at falling edge of P φ/2. 0 1 0 0 0 Uses internal clock. Counts at rising edge of P φ/64. 0 1 Uses internal clock. Counts at rising edge of P φ/32. 1 0 Uses internal clock. Counts at falling edge of P φ/64. 1 1 Uses internal clock. Counts at falling edge of P φ/32. 0 1 1 0 0 Uses internal clock. Counts at rising edge of P φ/8192. 0 1 Uses internal clock. Counts at rising edge of P φ/1024. 1 0 Uses internal clock. Counts at rising edge of P φ. 1 1 Uses internal clock. Counts at falling edge of P φ/1024. 1 0 0   Counts at TCNT_5 overflow signal *. TMR_5 0 0 0   Clock input prohibited 0 0 1 0 0 Uses internal clock. Counts at rising edge of P φ/8. 0 1 Uses internal clock. Counts at rising edge of P φ/2. 1 0 Uses internal clock. Counts at falling edge of P φ/8. 1 1 Uses internal clock. Counts at falling edge of P φ/2. 0 1 0 0 0 Uses internal clock. Counts at rising edge of P φ/64. 0 1 Uses internal clock. Counts at rising edge of P φ/32. 1 0 Uses internal clock. Counts at falling edge of P φ/64. 1 1 Uses internal clock. Counts at falling edge of P φ/32. 0 1 1 0 0 Uses internal clock. Counts at rising edge of P φ/8192. 0 1 Uses internal clock. Counts at rising edge of P φ/1024. 1 0 Uses internal clock. Counts at rising edge of P φ. 1 1 Uses internal clock. Counts at falling edge of P φ/1024. 1 0 0   Counts at TCNT_4 compare match A *. All 1 0 1   Setting prohibited 1 1 0   Setting prohibited 1 1 1   Setting prohibited Note: * If the clock input of channel 4 is the TCNT_5 overflow signal and that of channel 5 is the TCNT_4 compare match signal, no incrementing clock is generated. Do not use this setting.

Section 16 8-Bit Timers (TMR) Rev. 2.00 Jul. 31, 2008 Page 844 of 1438 REJ09B0365-0200 Table 16.5 Clock Input to TCNT and Count Condition (Unit 3) TCR TCCR Channel Bit 2 CKS2 Bit 1 CKS1 Bit 0 CKS0 Bit 1 ICKS1 Bit 0 ICKS0 Description TMR_6 0 0 0   Clock input prohibited 0 0 1 0 0 Uses internal clock. Counts at rising edge of P φ/8. 0 1 Uses internal clock. Counts at rising edge of P φ/2. 1 0 Uses internal clock. Counts at falling edge of P φ/8. 1 1 Uses internal clock. Counts at falling edge of P φ/2. 0 1 0 0 0 Uses internal clock. Counts at rising edge of P φ/64. 0 1 Uses internal clock. Counts at rising edge of P φ/32. 1 0 Uses internal clock. Counts at falling edge of P φ/64. 1 1 Uses internal clock. Counts at falling edge of P φ/32. 0 1 1 0 0 Uses internal clock. Counts at rising edge of P φ/8192. 0 1 Uses internal clock. Counts at rising edge of P φ/1024. 1 0 Uses internal clock. Counts at rising edge of P φ. 1 1 Uses internal clock. Counts at falling edge of P φ/1024. 1 0 0   Counts at TCNT_7 overflow signal *. TMR_7 0 0 0   Clock input prohibited 0 0 1 0 0 Uses internal clock. Counts at rising edge of P φ/8. 0 1 Uses internal clock. Counts at rising edge of P φ/2. 1 0 Uses internal clock. Counts at falling edge of P φ/8. 1 1 Uses internal clock. Counts at falling edge of P φ/2. 0 1 0 0 0 Uses internal clock. Counts at rising edge of P φ/64. 0 1 Uses internal clock. Counts at rising edge of P φ/32. 1 0 Uses internal clock. Counts at falling edge of P φ/64. 1 1 Uses internal clock. Counts at falling edge of P φ/32. 0 1 1 0 0 Uses internal clock. Counts at rising edge of P φ/8192. 0 1 Uses internal clock. Counts at rising edge of P φ/1024. 1 0 Uses internal clock. Counts at rising edge of P φ. 1 1 Uses internal clock. Counts at falling edge of P φ/1024. 1 0 0   Counts at TCNT_6 compare match A *. All 1 0 1   Setting prohibited 1 1 0   Setting prohibited 1 1 1   Setting prohibited Note: * If the clock input of channel 6 is the TCNT_7 overflow signal and that of channel 7 is the TCNT_6 compare match signal, no incrementing clock is generated. Do not use this setting.

Section 16 8-Bit Timers (TMR) Rev. 2.00 Jul. 31, 2008 Page 845 of 1438 REJ09B0365-0200

16.3.6 Timer Control/Status Register (TCSR)

TCSR displays status flags, and controls compare match output.

• TCSR_0
• TCSR_1 CMFB R/(W)* CMFA R/(W)* OVF R/(W)* ADTE R/W OS3 R/W OS2 R/W OS1 R/W OS0 R/W CMFB R/(W)* CMFA R/(W)* OVF R/(W)* R OS3 R/W OS2 R/W OS1 R/W OS0 R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Note: * Only 0 can be written to this bit, to clear the flag.
• TCSR_0 Bit Bit Name Initial Value R/W Description

7 CMFB 0 R/(W) *

[Setting condition]

• When TCNT matches TCORB [Clearing conditions]
• When writing 0 after reading CMFB = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
• When the DTC is activated by a CMIB interrupt while the DISEL bit in MRB of the DTC is 0*

Section 16 8-Bit Timers (TMR) Rev. 2.00 Jul. 31, 2008 Page 846 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description

6 CMFA 0 R/(W) *

[Setting condition]

• When TCNT matches TCORA [Clearing conditions]
• When writing 0 after reading CMFA = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
• When the DTC is activated by a CMIA interrupt while the DISEL bit in MRB in the DTC is 0*

5 OVF 0 R/(W) *

[Setting condition] When TCNT overflows from H'FF to H'00 [Clearing condition] When writing 0 after reading OVF = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)

4 ADTE 0 R/W A/D Trigger Enable *

Selects enabling or disabling of A/D converter start requests by compare match A. 0: A/D converter start requests by compare match A are disabled 1: A/D converter start requests by compare match A are enabled OS3 OS2 R/W R/W Output Select 3 and 2* These bits select a method of TMO pin output when compare match B of TCORB and TCNT occurs. 00: No change when compare match B occurs 01: 0 is output when compare match B occurs 10: 1 is output when compare match B occurs 11: Output is inverted when compare match B occurs (toggle output)

Section 16 8-Bit Timers (TMR) Rev. 2.00 Jul. 31, 2008 Page 847 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description OS1 OS0 R/W R/W Output Select 1 and 0* These bits select a method of TMO pin output when compare match A of TCORA and TCNT occurs. 00: No change when compare match A occurs 01: 0 is output when compare match A occurs 10: 1 is output when compare match A occurs 11: Output is inverted when compare match A occurs (toggle output) Notes: 1. Only 0 can be written to bi ts 7 to 5, to clear these flags. 2. Timer output is disabled when bits OS3 to OS0 are all 0. Timer output is 0 until the first compare match occurs after a reset. 3. For the corresponding A/D converter ch annels, see section 21, A/D Converter.

• TCSR_1 Bit Bit Name Initial Value R/W Description

[Setting condition]

• When TCNT matches TCORB [Clearing conditions]
• When writing 0 after reading CMFB = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
• When the DTC is activated by a CMIB interrupt while the DISEL bit in MRB of the DTC is 0*

Section 16 8-Bit Timers (TMR) Rev. 2.00 Jul. 31, 2008 Page 848 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description [Setting condition]

• When TCNT matches TCORA [Clearing conditions]
• When writing 0 after reading CMFA = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
• When the DTC is activated by a CMIA interrupt while the DISEL bit in MRB of the DTC is 0*

[Setting condition] When TCNT overflows from H'FF to H'00 [Clearing condition] Cleared by reading OVF when OVF = 1, then writing 0 to OVF (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 4  1 R Reserved This bit is always read as 1 and cannot be modified. OS3 OS2 R/W R/W Output Select 3 and 2* These bits select a method of TMO pin output when compare match B of TCORB and TCNT occurs. 00: No change when compare match B occurs 01: 0 is output when compare match B occurs 10: 1 is output when compare match B occurs 11: Output is inverted when compare match B occurs (toggle output)

Section 16 8-Bit Timers (TMR) Rev. 2.00 Jul. 31, 2008 Page 849 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description OS1 OS0 R/W R/W Output Select 1 and 0* These bits select a method of TMO pin output when compare match A of TCORA and TCNT occurs. 00: No change when compare match A occurs 01: 0 is output when compare match A occurs 10: 1 is output when compare match A occurs 11: Output is inverted when compare match A occurs (toggle output) Notes: 1. Only 0 can be written to bi ts 7 to 5, to clear these flags. 2. Timer output is disabled when bits OS3 to OS0 are all 0. Timer output is 0 until the first compare match occurs after a reset. 3. Available only in unit 0 and unit 1.

16.4 Operation

16.4.1 Pulse Output

Figure 16.5 shows an example of the 8-bit timer being used to generate a pulse output with a desired duty cycle. The control bits are set as follows: 1. Clear the bit CCLR1 in TCR to 0 and set the bit CCLR0 in TCR to 1 so that TCNT is cleared at a TCORA compare match. 2. Set the bits OS3 to OS0 in TCSR to B'0110, causing the output to change to 1 at a TCORA compare match and to 0 at a TCORB compare match. With these settings, the 8-bit timer provides pulses output at a cycle determined by TCORA with a pulse width determined by TCORB. No software intervention is required. The timer output is 0 until the first compare match occurs after a reset.

Section 16 8-Bit Timers (TMR) Rev. 2.00 Jul. 31, 2008 Page 850 of 1438 REJ09B0365-0200 TCNT H'FF Counter clear TCORA TCORB H'00 TMO Figure 16.5 Example of Pulse Output

16.4.2 Reset Input

Figure 16.6 shows an example of the 8-bit timer being used to generate a pulse which is output after a desired delay time from a TMRI input. The control bits are set as follows: 1. Set both bits CCLR1 and CCLR0 in TCR to 1 and set the TMRIS bit in TCCR to 1 so that TCNT is cleared at the high level input of the TMRI signal. 2. In TCSR, set bits OS3 to OS0 to B'0110, causing the output to change to 1 at a TCORA compare match and to 0 at a TCORB compare match. With these settings, the 8-bit timer provides pulses output at a desired delay time from a TMRI input determined by TCORA and with a pulse width determined by TCORB and TCORA. TCNT TCORB TCORA H'00 TMRI TMO Figure 16.6 Example of Reset Input

Section 16 8-Bit Timers (TMR) Rev. 2.00 Jul. 31, 2008 Page 851 of 1438 REJ09B0365-0200

16.5 Operation Timing

16.5.1 TCNT Count Timing

Figure 16.7 shows the TCNT count timing for internal clock input. Figure 16.8 shows the TCNT count timing for external clock input. Note that the external clock pulse width must be at least 1.5 states for increment at a single edge, and at least 2.5 states for increment at both edges. The counter will not increment correctly if the pulse width is less than these values. Pφ Internal clock TCNT input clock TCNT N – 1 N N + 1 Figure 16.7 Count Timing for Internal Clock Input Pφ External clock input pin TCNT input clock TCNT N – 1 N N + 1 Figure 16.8 Count Timing for External Clock Input

Section 16 8-Bit Timers (TMR) Rev. 2.00 Jul. 31, 2008 Page 852 of 1438 REJ09B0365-0200

16.5.2 Timing of CMFA and CM FB Setting at Compare Match

The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the TCOR and TCNT values match. The compare match signal is generated at the last state in which the match is true, just before the timer counter is updated. Therefore, when the TCOR and TCNT values match, the compare match signal is not generated until the next TCNT clock input. Figure 16.9 shows this timing. Pφ TCNT N N + 1 TCOR N Compare match signal CMF Figure 16.9 Timing of CMF Setting at Compare Match

16.5.3 Timing of Timer Output at Compare Match

When a compare match signal is generated, the timer output changes as specified by the bits OS3 to OS0 in TCSR. Figure 16.10 shows the timing when the timer output is toggled by the compare match A signal. Pφ Compare match A signal Timer output pin Figure 16.10 Timing of Toggled Timer Output at Compare Match A

Section 16 8-Bit Timers (TMR) Rev. 2.00 Jul. 31, 2008 Page 853 of 1438 REJ09B0365-0200

16.5.4 Timing of Counter Clear by Compare Match

TCNT is cleared when compare match A or B occurs, depending on the settings of the bits CCLR1 and CCLR0 in TCR. Figure 16.11 shows the timing of this operation. Pφ N H'00 Compare match signal TCNT Figure 16.11 Timing of Counter Clear by Compare Match

16.5.5 Timing of TC NT External Reset*

TCNT is cleared at the rising edge or high level of an external reset input, depending on the settings of bits CCLR1 and CCLR0 in TCR. The clear pulse width must be at least 2 states. Figure 16.12 and Figure 16.13 shows the timing of this operation. Note: * Clearing by an external reset is available only in units 0 and 1. Pφ Clear signal External reset input pin TCNT N H'00N – 1 Figure 16.12 Timing of Clearance by External Reset (Rising Edge) Pφ Clear signal External reset input pin TCNT N H'00N – 1 Figure 16.13 Timing of Clearance by External Reset (High Level)

Section 16 8-Bit Timers (TMR) Rev. 2.00 Jul. 31, 2008 Page 854 of 1438 REJ09B0365-0200

16.5.6 Timing of Overflow Flag (OVF) Setting

The OVF bit in TCSR is set to 1 when TCNT overflows (changes from H'FF to H'00). Figure 16.14 shows the timing of this operation. Pφ OVF Overflow signal TCNT H'FF H'00 Figure 16.14 Timing of OVF Setting

16.6 Operation with Cascaded Connection

If the bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit counter mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1 (compare match count mode). 16.6.1 16-Bit Counter Mode When the bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. (1) Setting of Compare Match Flags

• The CMF flag in TCSR_0 is set to 1 when a 16-bit compare match event occurs.
• The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare match event occurs. (2) Counter Clear Specification
• If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare match, the 16-bit counter (TCNT_0 and TCNT_1 together) is cleared when a 16-bit compare match event occurs. The 16-bit counter (TCNT0 and TCNT1 together) is cleared even if counter clear by the TMRI0 pin has been set.
• The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot be cleared independently.

Section 16 8-Bit Timers (TMR) Rev. 2.00 Jul. 31, 2008 Page 855 of 1438 REJ09B0365-0200 (3) Pin Output

• Control of output from the TMO0 pin by the bits OS3 to OS0 in TCSR_0 is in accordance with the 16-bit compare match conditions.
• Control of output from the TMO1 pin by the bits OS3 to OS0 in TCSR_1 is in accordance with the lower 8-bit compare match conditions.

16.6.2 Compare Match Count Mode

When the bits CKS2 to CKS0 in TCR_1 are set to B'100, TCNT_1 counts compare match A for channel 0. Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag, generation of interrupts, output from the TMO pin, and counter clear are in accordance with the settings for each channel.

16.7 Interrupt Sources

16.7.1 Interrupt Sources and DTC Activation

• Interrupt in unit 0 and unit 1 There are three interrupt sources for the 8-bit timer (TMR_0 or TMR_1): CMIA, CMIB, and OVI. Their interrupt sources and priorities are shown in table 16.6. Each interrupt source is enabled or disabled by the corresponding interrupt enable bit in TCR or TCSR, and independent interrupt requests are sent for each to the interrupt controller. It is also possible to activate the DTC by means of CMIA and CMIB interrupts (This is available in unit 0 and unit 1 only). Table 16.6 8-Bit Timer (TMR_0 or TMR_1) Interrupt Sources (in Unit 0 and Unit 1) Signal Name Name Interrupt Source Interrupt Flag DTC Activation Priority CMIA0 CMIA0 TCORA_0 compare match CMFA Possible High CMIB0 CMIB0 TCORB_0 compare match CMFB Possible OVI0 OVI0 TCNT_0 overflow OVF Not possible Low CMIA1 CMIA1 TCORA_1 compare match CMFA Possible High CMIB1 CMIB1 TCORB_1 compare match CMFB Possible OVI1 OVI1 TCNT_1 overflow OVF Not possible Low

Section 16 8-Bit Timers (TMR) Rev. 2.00 Jul. 31, 2008 Page 856 of 1438 REJ09B0365-0200

• Interrupt in unit 2 and unit 3 There are two interrupt sources for the 8-bit timer (TMR_4 or TMR_5): CMIA, CMIB. The interrupt signal is CMI only. The interrupt sources are shown in table 16.7. When enabling or disabling is set by the interrupt enable bit in TCR or TCSR, and when either CMIA or CMIB interrupt source is generated, CMI is sent to the interrupt controller. To verify which interrupt source is generated, confirm by checking each flag in TCSR. No overflow-related interrupt signal exists. DTC cannot be activated by this interrupt. Table 16.7 8-Bit Timer (TMR_4 or TMR_5) Interrupt Sources (in Unit 2 and Unit 3) Signal Name Name Interrupt Source Interrupt Flag DTC Activation Priority CMIA4 TCORA_4 compare match CMFA  CMI4 CMIB4 TCORB_4 compare match CMFB Not possible CMIA5 TCORA_5 compare match CMFA  CMI5 CMIB5 TCORB_5 compare match CMFB Not possible

16.7.2 A/D Converter Activation

The A/D converter can be activated by a compare match A for the even channels of each TMR unit. * If the ADTE bit in TCSR is set to 1 when the CMFA flag in TCSR is set to 1 by the occurrence of a compare match A, a request to start A/D conversion is sent to the A/D converter. If the 8-bit timer conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started. Note: * For the corresponding A/D converter channels, see section 21, A/D Converter.

Section 16 8-Bit Timers (TMR) Rev. 2.00 Jul. 31, 2008 Page 857 of 1438 REJ09B0365-0200

16.8 Usage Notes

16.8.1 Notes on Setting Cycle

If the compare match is selected for counter clear, TCNT is cleared at the last state in the cycle in which the values of TCNT and TCOR match. TCNT updates the counter value at this last state. Therefore, the counter frequency is obtained by the following formula. f = φ / (N + 1 ) f: Counter frequency φ: Operating frequency N: TCOR value

16.8.2 Conflict between TCNT Write and Counter Clear

If a counter clear signal is generated during the T2 state of a TCNT write cycle, the clear takes priority and the write is not performed as shown in figure 16.15. Pφ Address TCNT address Internal write signal Counter clear signal TCNT N H'00 T1 T2 TCNT write cycle by CPU Figure 16.15 Conflict between TCNT Write and Clear

Section 16 8-Bit Timers (TMR) Rev. 2.00 Jul. 31, 2008 Page 858 of 1438 REJ09B0365-0200

16.8.3 Conflict between TCNT Write and Increment

If a TCNT input clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the counter is not incremented as shown in figure 16.16. Pφ Address TCNT address Internal write signal TCNT input clock TCNT N M T1 T2 TCNT write cycle by CPU Counter write data Figure 16.16 Conflict between TCNT Write and Increment

16.8.4 Conflict between TCOR Write and Compare Match

If a compare match event occurs during the T2 state of a TCOR write cycle, the TCOR write takes priority and the compare match signal is inhibited as shown in figure 16.17. Pφ Address TCOR address Internal write signal TCNT TCOR N M T1 T2 TCOR write cycle by CPU TCOR write data N N + 1 Compare match signal Inhibited Figure 16.17 Conflict between TCOR Write and Compare Match

Section 16 8-Bit Timers (TMR) Rev. 2.00 Jul. 31, 2008 Page 859 of 1438 REJ09B0365-0200

16.8.5 Conflict between Compare Matches A and B

If compare match events A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output statuses set for compare match A and compare match B, as shown in table 16.8. Table 16.8 Timer Output Priorities Output Setting Priority Toggle output High 1-output 0-output No change Low

16.8.6 Switching of Internal Clocks and TCNT Operation

TCNT may be incremented erroneously depending on when the internal clock is switched. Table 16.9 shows the relationship between the timing at which the internal clock is switched (by writing to the bits CKS1 and CKS0) and the TCNT operation. When the TCNT clock is generated from an internal clock, the rising or falling edge of the internal clock pulse are always monitored. Table 16.9 assumes that the falling edge is selected. If the signal levels of the clocks before and after switching change from high to low as shown in item 3, the change is considered as the falling edge. Therefore, a TCNT clock pulse is generated and TCNT is incremented. This is similar to when the rising edge is selected. The erroneous increment of TCNT can also happen when switching between rising and falling edges of the internal clock, and when switching between internal and external clocks.

Section 16 8-Bit Timers (TMR) Rev. 2.00 Jul. 31, 2008 Page 860 of 1438 REJ09B0365-0200 Table 16.9 Switching of Internal Clock and TCNT Operation No. Timing to Change CKS1 and CKS0 Bits TCNT Clock Operation

1 Switching from low to low *

2 Switching from low to high *

2 Clock before

3 Switching from high to low *

3 Clock before

4 Switching from high to high Clock before

Notes: 1. Includes switching from low to stop, and from stop to low. 2. Includes switching from stop to high. 3. Includes switching from high to stop. 4. Generated because the chan ge of the signal levels is considered as a falling edge; TCNT is incremented.

Section 16 8-Bit Timers (TMR) Rev. 2.00 Jul. 31, 2008 Page 861 of 1438 REJ09B0365-0200

16.8.7 Mode Setting with Cascaded Connection

If 16-bit counter mode and compare match count mode are specified at the same time, input clocks for TCNT_0 and TCNT_1 are not generated, and the counter stops. Do not specify 16-bit counter mode and compare match count mode simultaneously.

16.8.8 Module Stop State Setting

Operation of the TMR can be disabled or enabled using the module stop control register. The initial setting is for operation of the TMR to be halted. Register access is enabled by clearing the module stop state. For details, see section 27, Power-Down Modes.

16.8.9 Interrupts in Module Stop State

If the module stop state is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DTC activation source. Interrupts should therefore be disabled before entering the module stop state.

Section 16 8-Bit Timers (TMR) Rev. 2.00 Jul. 31, 2008 Page 862 of 1438 REJ09B0365-0200

Section 17 32K Timer (TM32K) Rev. 2.00 Jul. 31, 2008 Page 863 of 1438 REJ09B0365-0200 Section 17 32K Timer (TM32K) The 32K timer (TM32K) is supported only by the H8SX/1648G Group and H8SX/1648H Group. The 32K timer (TM32K) is a 24-bit timer. Either 8- or 24- counter operation is selectable. It generates a 32K timer interrupt every time the interrupt period of the counter elapses. Figure 17.1 shows a block diagram of the TM32K.

17.1 Features

• A 32K timer interrupt (32KOVI) is generated at the overflow interval for the counter.
• Eight interrupt overflow cycles of 250 ms, 500 ms, 1 s, 2 s, 30 s, 60 s, approx. 22.7 days, and approx. 45.5 days settable.
• Counter operational except in hardware standby mode or the reset state.
• Canceling software standby mode and deep software standby mode is possible. Clock divider SUBCK/32 SUBCK/64 SUBCK/128 SUBCK/256 SUBCK/16384 SUBCK/32768 Internally divided clock 32KOVI (Interrupt request signal) Subclock (SUBCK) (32.768KHz) EXCKSN TME CKS1/0 TCR32K Module bus Bus interface Counter TK32K Bus TCNT32K1 (8 bits) TCNT32K2 (8 bits) TCNT32K3 (8 bits) [Legend] TCR32K: Timer control register TCNT32K 1 to 3: Timer counter Figure 17.1 Block Diagram of TM32K

Section 17 32K Timer (TM32K) Rev. 2.00 Jul. 31, 2008 Page 864 of 1438 REJ09B0365-0200

17.2 Register Descriptions

The TM32K has the following registers.

• Timer control register (TCR32K)
• Timer counter (TCNT32K1, TCNT32K2, TCNT32K3)

17.2.1 Timer Control Register (TCR32K)

TCR32K enables the timer, stops the subclock oscillator, and selects the clock source to be input to TCNT32K. Change values of the bits when TME=0. Bit BIt Name Initial Value R/W EXCKSN R/W R TME R/W R R OSC32STP R/W CKS1 R/W CKS0 R/W Bit Bit Name Initial Value R/W Description EXCKSN CKS1 CKS0 R/W R/W R/W Extended Clock Select and Clock Select 1, 0 These bits select the internally divided clock source to be input to TCNT32K. The interrupt cycle for SUBCK = 32.768 kHz is indicated in parentheses. When EXCKSN = 1: 00: Clock SUBCK/32 (cycle: 250 ms) 01: Clock SUBCK/64 (cycle: 500 ms) 10: Clock SUBCK/128 (cycle: 1 s) 11: Clock SUBCK/256 (cycle: 2 s) When EXCKSN = 0: 00: Clock SUBCK/16384 (cycle: 30 s) 01: Clock SUBCK/32768 (cycle: 60 s) 10: Clock SUBCK/16384 (cycle: approx. 22.7 days) 11: Clock SUBCK/32768 (cycle: approx. 45.5 days) 6  1 R Reserved This bit is always read as 1 and cannot be modified.

Section 17 32K Timer (TM32K) Rev. 2.00 Jul. 31, 2008 Page 865 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description

5 TME 0 R/W Timer Enable

When this bit is set to 1, TCNT32K starts counting. When this bit is cleared, TCNT32K stops counting and is initialized to H'00_00_00. 4, 3  All 1 R Reserved These bits are always read as 1 and cannot be modified.

2 OSC32STP * 0

0: Starts the subclock oscillator 1: Stops the subclock oscillator Note: * When the CK32K bit in SUBCKCR is 1, 1 cannot be written to this bit.

17.2.2 Timer Counter (TCNT32K1, TCNT32K2, TCNT32K3)

The timer counter is a 24-bit counter for which either 8- or 24-bit operation is selectable. Allocation to the registers of the timer counter differs according to the setting of the EXCKSN bit in TCR32K. (1) EXCKSN = 1 (Initial State) The timer counter operates as an 8-bit counter. Only TCNT32K1 is used and TCNT32K2 and TCNT32K3 become reserved registers. Clearing the TME bit in the timer control register (TCR32K) initializes TCNT32K1 to H'00.

• TCNT32K1 Bit Bit Name Initial value R/W TCNT7 R TCNT6 R TCNT5 R TCNT4 R TCNT3 R TCNT2 R TCNT1 R TCNT0 R
• TCNT32K2 Bit Bit Name Initial value R/W R R R R R R R R

Section 17 32K Timer (TM32K) Rev. 2.00 Jul. 31, 2008 Page 866 of 1438 REJ09B0365-0200

• TCNT32K3 Bit Bit Name Initial value R/W R R R R R R R R (2) EXCKSN = 0 (Counter-Extended Mode) The timer counter operates as a 24-bit counter. TCNT32K1, TCNT32K2, and TCNT32K3 are employed for this purpose. Be sure to read from TCNT32K1 when reading the timer counter.
• TCNT32K1 Bit Bit Name Initial value R/W TCNT23 R TCNT22 R TCNT21 R TCNT20 R TCNT19 R TCNT18 R TCNT17 R TCNT16 R
• TCNT32K2 Bit Bit Name Initial value R/W TCNT15 R TCNT14 R TCNT13 R TCNT12 R TCNT11 R TCNT10 R TCNT9 R TCNT8 R
• TCNT32K3 Bit Bit Name Initial value R/W TCNT7 R TCNT6 R TCNT5 R TCNT4 R TCNT3 R TCNT2 R TCNT1 R TCNT0 R Note: A correct value cannot be read if the counter is read while the subclock oscillator is not in operation (OSC32STP = 1).

Section 17 32K Timer (TM32K) Rev. 2.00 Jul. 31, 2008 Page 867 of 1438 REJ09B0365-0200

17.3 Operation

17.3.1 Basic Operation

Either 8-bit or 24-bit counter operation can be selected for the timer counter. Setting 1 to the TME bit in TCR32K starts the count-up operation. A 32K timer interrupt (32KOVI) is generated by the interrupt cycle. Table 17.1 shows relationships between the timer counter operations according to the setting of bits EXCKSN, CKS1, and CKS0 in TCR32K and the interrupt cycles. Table 17.1 Relationships between Counter Operations and 32KOVI Cycles Setting Division Ratio Selected Counter Interrupt Cycles EXCKSN CKS1 CKS2 Internally Divided CLK TCNT 32K1 TCNT 32K2 TCNT 32K3 Counter value when interrupt generates 32KOVI Cycle 1 0 0 SUBCK/32 √ − − 250 ms 1 0 1 SUBCK/64 √ − − 500 ms 1 1 0 SUBCK/128 √ − − 1 s 1 1 1 SUBCK/256 √ − − TCNT32K1=H'FF 2 s 0 0 0 SUBCK/16384 √ √ √ 30 s 0 0 1 SUBCK/32768 √ √ √ TCNT32K3=H'3B 60 s 0 1 0 SUBCK/16384 √ √ √ Approx. 22.7 days 0 1 1 SUBCK/32768 √ √ √ TCNT32K1 to 3 =H'FFF3B Approx. 45.5 days √ : in use − : not in use

Section 17 32K Timer (TM32K) Rev. 2.00 Jul. 31, 2008 Page 868 of 1438 REJ09B0365-0200

17.3.2 EXCKSN=1 Operation

When the EXCKSN bit in TCR32K is 1, the timer counter operates as an 8-bit counter. Every time the value in TCNT32K1 reaches H'FF, a 32KOVI interrupt is generated. By setting the CKS1 and CKS0 bits in TCR32K, intervals of 250ms, 500ms, 1s, and 2s between interrupts are selectable. H'FF H'00 32KOVI Time 32KOVI 32KOVI 32KOVI 32KOVI: 32K timer interrupt 32KOVI Overflow TCNT32K value 3 clocks of 32Kφ Overflow Overflow Overflow TME = 1 Figure 17.2 EXCKSN = 1 32K Timer Operation

17.3.3 EXCKSN=0 Operation

When the EXCKSN bit in TCR32K is 0, the timer counter operates as a 24-bit counter. The lower- order 8-bits are TCNT32K3, which operates as a free-running up-counter that counts from H'00 to H'3B. The higher-order 16-bits in TCNT32K1 and TCNT32K2 act as an up-counter that counts the number of times TCNT32K3=H'3B. Generation of the 32KOVI interrupt either for all values with TCNT32K3=H'3B or when TCNT32K1 to TCNT32K3=H'FFFF3B can be selected by the setting of the CKS1 bit. This setting in combination with the setting of the CKS0 bit can be used When the EXCKSN bit is 0, the CKS1 bit can be changed while the timer counter is operating because the TME bit is 1. This allows variation of the 32KOV1 interrupt interval while the timer counter is in operation. When the value of the CKS1 bit is from 0 to 1, the higher-order 16-bit counter (TCNT32K1, TCNT32K2) resumes counting after being initialized to H'00_00.

Section 17 32K Timer (TM32K) Rev. 2.00 Jul. 31, 2008 Page 869 of 1438 REJ09B0365-0200 To avert contention between initialization of the up-counter due to the changed value of the bit and counting operation, change the CKS1 bit from 0 to 1 within the 32KOVI interrupt routine. Timing of the operation of changing the CKS1 bit when EXCKSN=0 is shown in figure 17.3. Note that generation of the 32KOVI interrupt will fail once if there is a conflict between the timing with which the CKS1 bit is changed from 1 to 0 and the value of TCNT32K3 becomes H'3B. This is shown in figure 17.4. H'3B H'0000 H'FFFF TCNT32K3 TCNT32K1, TCNT32K2 H'0001 TME = 1 CKS = 0 H'0002 H'0003 H'0001 H'0002 H'0001 H'0002 H'00 32KOVI CKS1 Time Operate in interrupt handling routine 3 cycles of the SUBCK clock width Figure 17.3 Operation of Changing the CKS1 bit when EXCKSN = 0

Section 17 32K Timer (TM32K) Rev. 2.00 Jul. 31, 2008 Page 870 of 1438 REJ09B0365-0200 (SUBCK) TCNT32K3 = H'3B H'3A H'3B H'00 H'01 32KOVI 32KOVI does not generate. CKS1 setting Internal CKS1 Subclock Internally divided clock Timer conter Figure 17.4 Conflict between the CKS1 bit being Changed from 1 to 0 and the 32KOVI

Section 17 32K Timer (TM32K) Rev. 2.00 Jul. 31, 2008 Page 871 of 1438 REJ09B0365-0200

17.4 Interrupt Source

At the interrupt interval, the 32K timer generates a 32K timer-overflow interrupt (32KOVI) that lasts for three cycles of the subclock. Since 32KOVI is internally connected to IRQ15, the IRQ15F bit is set to 1 when an interrupt is generated. For the IRQ15 setting, select an interrupt request generated at the falling edge with ISCR. For details, see section 7, Interrupt Controller. The 32K timer operates in both software-standby and deep-software standby modes. Through generation of the 32K timer interrupt, the timer can provide the trigger for release from software standby and deep-software-standby modes. For details, see section 27, Power-Down Modes. Table 17.2 TM32K Interrupt Source Name Interrupt Source Interrupt Flag DTC Activation Software Standby Mode Reset Deep Software Standby reset IRQ15F Impossible Possible Impossible 32KOVI TCNT32K interrupt DT32KIF Impossible Impossible Possible

Section 17 32K Timer (TM32K) Rev. 2.00 Jul. 31, 2008 Page 872 of 1438 REJ09B0365-0200

17.5 Usage Notes

17.5.1 Changing Values of Bits EXCKSN, CKS1, and CKS0

If bits EXCKSN, CKS1, and CKS0 in TCR32K are written to while the TM32K is operating, errors could occur in the incrementation. The TM32K must be stopped (the TME bit is set to 0) before the values of bits EXCKSN, CKS1, and CKS0 are changed. Note that when the EXCKSN bit is 0, the CKS1 bit can be changed even though the TME bit is 1 (see section 17.3.3, EXCKSN=0 Operation).

17.5.2 Note on Register Initialization

TCR32K, TCNT32K1, TCNT32K2, and TCNT32K3 of the 32K timer are initialized in hardware standby mode or in the pin reset state. A reset from the watchdog timer or deep-software-standby reset does not initialize these registers.

17.5.3 Usage Notes on 32K Timer

• The 32K timer does not operate when the OSC32STP bit is set to 1. Always set the OSC32STP bit to 0 when starting the 32K timer.
• When the OSC32STP bit has been changed from 1 to 0, allow enough time to ensure settling of the oscillation by the subclock oscillator.
• Before stopping the TM32K, clear the TME bit to 0 for one clock (30 µs) or longer by the 32 subclock.
• When switching between subclock and main clock operation, wait for 500 µs or more (until the timer counter is updated next time) before reading the timer counter.

Section 18 Watchdog Timer (WDT) Rev. 2.00 Jul. 31, 2008 Page 873 of 1438 REJ09B0365-0200 Section 18 Watchdog Timer (WDT) The watchdog timer (WDT) is an 8-bit timer that outputs an overflow signal (WDTOVF) if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. At the same time, the WDT can also generate an internal reset signal. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows. Figure 18.1 shows a block diagram of the WDT.

18.1 Features

• Selectable from eight counter input clocks
• Switchable between watchdog timer mode and interval timer mode  In watchdog timer mode If the counter overflows, the WDT outputs WDTOVF. It is possible to select whether or not the entire LSI is reset at the same time.  In interval timer mode If the counter overflows, the WDT generates an interval timer interrupt (WOVI).

Section 18 Watchdog Timer (WDT) Rev. 2.00 Jul. 31, 2008 Page 874 of 1438 REJ09B0365-0200 Overflow Interrupt controlWOVI (interrupt request signal) Internal reset signal* WDTOVF Reset control RSTCSR TCNT TCSR Pφ/2 Pφ/64 Pφ/128 Pφ/512 Pφ/2048 Pφ/8192 Pφ/32768 Pφ/131072 Clock Clock select Internal clocks Bus interfaceModule bus TCSR: TCNT: RSTCSR: Note: * An internal reset signal can be generated by the RSTCSR setting. Timer control/status register Timer counter Reset control/status register WDT [Legend] Internal bus Figure 18.1 Block Diagram of WDT

18.2 Input/Output Pin

Table 18.1 shows the WDT pin configuration. Table 18.1 Pin Configuration Name Symbol I/O Function Watchdog timer overflow* WDTOVF Output Outputs a counter overflow signal in watchdog timer mode Note: * In boundary scan valid mode, counter overflow signal output cannot be used.

Section 18 Watchdog Timer (WDT) Rev. 2.00 Jul. 31, 2008 Page 875 of 1438 REJ09B0365-0200

18.3 Register Descriptions

The WDT has the following three registers. To prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to in a method different from normal registers. For details, see section 18.6.1, Notes on Register Access.

• Timer counter (TCNT)
• Timer control/status register (TCSR)
• Reset control/status register (RSTCSR)

18.3.1 Timer Counter (TCNT)

TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in TCSR is cleared to 0. Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W

18.3.2 Timer Control/Status Register (TCSR)

TCSR selects the clock source to be input to TCNT, and the timer mode. Bit Bit Name Initial Value R/W Note: * Only 0 can be written to this bit, to clear the flag. OVF R/(W)* WT/IT R/W TME R/W R R CKS2 R/W CKS1 R/W CKS0 R/W

Section 18 Watchdog Timer (WDT) Rev. 2.00 Jul. 31, 2008 Page 876 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description

7 OVF 0 R/(W) * Overflow Flag

Indicates that TCNT has overflowed in interval timer mode. Only 0 can be written to this bit, to clear the flag. [Setting condition] When TCNT overflows in interval timer mode (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. [Clearing condition] Cleared by reading TCSR when OVF = 1, then writing 0 to OVF (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)

6 WT/ IT 0 R/W Timer Mode Select

Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode When TCNT overflows, an interval timer interrupt (WOVI) is requested. 1: Watchdog timer mode When TCNT overflows, the WDTOVF signal is output. When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00. 4, 3  All 1 R Reserved These are read-only bits and cannot be modified. CKS2 CKS1 CKS0 R/W R/W R/W Clock Select 2 to 0 Select the clock source to be input to TCNT. The overflow cycle for Pφ = 20 MHz is indicated in parentheses. 000: Clock Pφ/2 (cycle: 25.6 µs) 001: Clock Pφ/64 (cycle: 819.2 µs) 010: Clock Pφ/128 (cycle: 1.6 ms) 011: Clock Pφ/512 (cycle: 6.6 ms) 100: Clock Pφ/2048 (cycle: 26.2 ms) 101: Clock Pφ/8192 (cycle: 104.9 ms) 110: Clock Pφ/32768 (cycle: 419.4 ms) 111: Clock Pφ/131072 (cycle: 1.68 s) Note: * Only 0 can be written to this bit, to clear the flag.

Section 18 Watchdog Timer (WDT) Rev. 2.00 Jul. 31, 2008 Page 877 of 1438 REJ09B0365-0200

18.3.3 Reset Control/Status Register (RSTCSR)

RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal reset signal caused by WDT overflows. WOVF R/(W)* RSTE R/W R/W R R R R R Bit Bit Name Initial Value R/W Note: * Only 0 can be written to this bit, to clear the flag. Bit Bit Name Initial Value R/W Description This bit is set when TCNT overflows in watchdog timer mode. This bit cannot be set in interval timer mode, and only 0 can be written. [Setting condition] When TCNT overflows (changed from H'FF to H'00) in watchdog timer mode [Clearing condition] Reading RSTCSR when WOVF = 1, and then writing 0 to WOVF Specifies whether or not this LSI is internally reset if TCNT overflows during watchdog timer operation. 0: LSI is not reset even if TCNT overflows (Though this LSI is not reset, TCNT and TCSR in WDT are reset) 1: LSI is reset if TCNT overflows

Section 18 Watchdog Timer (WDT) Rev. 2.00 Jul. 31, 2008 Page 878 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description 5  0 R/W Reserved Although this bit is readable/writable, reading from or writing to this bit does not affect operation. 4 to 0  All 1 R Reserved These are read-only bits and cannot be modified. Note: * Only 0 can be written to this bit, to clear the flag.

18.4 Operation

18.4.1 Watchdog Timer Mode

To use the WDT in watchdog timer mode, set both the WT/IT and TME bits in TCSR to 1. During watchdog timer operation, if TCNT overflows without being rewritten because of a system crash or other error, the WDTOVF signal is output. This ensures that TCNT does not overflow while the system is operating normally. Software must prevent TCNT overflows by rewriting the TCNT value (normally H'00 is written) before overflow occurs. This WDTOVF signal can be used to reset the LSI internally in watchdog timer mode. If TCNT overflows when the RSTE bit in RSTCSR is set to 1, a signal that resets this LSI internally is generated at the same time as the WDTOVF signal. If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT overflow, the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0. The WDTOVF signal is output for 133 cycles of Pφ when RSTE = 1 in RSTCSR, and for 130 cycles of Pφ when RSTE = 0 in RSTCSR. The internal reset signal is output for 519 cycles of Pφ. When RSTE = 1, an internal reset signal is generated. Since the system clock control register (SCKCR) is initialized, the multiplication ratio of Pφ becomes the initial value. When RSTE = 0, an internal reset signal is not generated. Neither SCKCR nor the multiplication ratio of Pφ is changed. When TCNT overflows in watchdog timer mode, the WOVF bit in RSTCSR is set to 1. If TCNT overflows when the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated for the entire LSI.

Section 18 Watchdog Timer (WDT) Rev. 2.00 Jul. 31, 2008 Page 879 of 1438 REJ09B0365-0200 TCNT value H'00 Time H'FF WT/IT = 1 TME = 1 H'00 written to TCNT WT/IT = 1 TME = 1 H'00 written to TCNT133 states*2 519 states WDTOVF signal Internal reset signal*1 Notes: 1. If TCNT overflows when the RSTE bit is set to 1, an internal reset signal is generated. 2. 130 states when the RSTE bit is cleared to 0. Overflow WDTOVF and internal reset are generated WOVF = 1 Figure 18.2 Operation in Watchdog Timer Mode

Section 18 Watchdog Timer (WDT) Rev. 2.00 Jul. 31, 2008 Page 880 of 1438 REJ09B0365-0200

18.4.2 Interval Timer Mode

To use the WDT as an interval timer, set the WT/IT bit to 0 and the TME bit to 1 in TCSR. When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time the TCNT overflows. Therefore, an interrupt can be generated at intervals. When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested at the same time the OVF bit in the TCSR is set to 1. TCNT value H'00 Time H'FF WT/IT = 0 TME = 1 WOVI Overflow Overflow Overflow Overflow [Legend] WOVI: Interval timer interrupt request WOVI WOVI WOVI Figure 18.3 Operation in Interval Timer Mode

18.5 Interrupt Source

During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. The OVF flag must be cleared to 0 in the interrupt handling routine. Table 18.2 WDT Interrupt Source Name Interrupt Source Interrupt Flag DTC Activation WOVI TCNT overflow OVF Impossible

Section 18 Watchdog Timer (WDT) Rev. 2.00 Jul. 31, 2008 Page 881 of 1438 REJ09B0365-0200

18.6 Usage Notes

18.6.1 Notes on Register Access

The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. (1) Writing to TCNT, TCSR, and RSTCSR TCNT and TCSR must be written to by a word transfer instruction. They cannot be written to by a byte transfer instruction. For writing, TCNT and TCSR are assigned to the same address. Accordingly, perform data transfer as shown in figure 18.4. The transfer instruction writes the lower byte data to TCNT or TCSR. To write to RSTCSR, execute a word transfer instruction for address H'FFA6. A byte transfer instruction cannot be used to write to RSTCSR. The method of writing 0 to the WOVF bit in RSTCSR differs from that of writing to the RSTE bit in RSTCSR. Perform data transfer as shown in figure 18.4. At data transfer, the transfer instruction clears the WOVF bit to 0, but has no effect on the RSTE bit. To write to the RSTE bit, perform data transfer as shown in figure 18.4. In this case, the transfer instruction writes the value in bit 6 of the lower byte to the RSTE bit, but has no effect on the WOVF bit. TCNT write or writing to the RSTE bit in RSTCSR: TCSR write: Address: H'FFA4 (TCNT) H'FFA6 (RSTCSR) 15 8 7 0 H'5A Write data Address: H'FFA4 (TCSR) 15 8 7 0 H'A5 Write data Writing 0 to the WOVF bit in RSTCSR: Address: H'FFA6 (RSTCSR) 15 8 7 0 H'A5 H'00 Figure 18.4 Writing to TCNT, TCSR, and RSTCSR

Section 18 Watchdog Timer (WDT) Rev. 2.00 Jul. 31, 2008 Page 882 of 1438 REJ09B0365-0200 (2) Reading from TCNT, TCSR, and RSTCSR These registers can be read from in the same way as other registers. For reading, TCSR is assigned to address H'FFA4, TCNT to address H'FFA5, and RSTCSR to address H'FFA7.

18.6.2 Conflict between Timer Counter (TCNT) Write and Increment

If a TCNT clock pulse is generated during the T2 cycle of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 18.5 shows this operation. N M T1 T2 Address Pφ Internal write signal TCNT input clock TCNT TCNT write cycle Counter write data Figure 18.5 Conflict between TCNT Write and Increment

18.6.3 Changing Values of Bits CKS2 to CKS0

If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in the incrementation. The watchdog timer must be stopped (by clearing the TME bit to 0) before the values of bits CKS2 to CKS0 are changed.

18.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode

If the timer mode is switched from watchdog timer mode to interval timer mode while the WDT is operating, errors could occur in the incrementation. The watchdog timer must be stopped (by clearing the TME bit to 0) before switching the timer mode.

Section 18 Watchdog Timer (WDT) Rev. 2.00 Jul. 31, 2008 Page 883 of 1438 REJ09B0365-0200

18.6.5 Internal Reset in Watchdog Timer Mode

This LSI is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during watchdog timer mode operation, but TCNT and TCSR of the WDT are reset. TCNT, TCSR, and RSTCR cannot be written to while the WDTOVF signal is low. Also note that a read of the WOVF flag is not recognized during this period. To clear the WOVF flag, therefore, read TCSR after the WDTOVF signal goes high, then write 0 to the WOVF flag.

18.6.6 System Reset by WDTOVF Signal

If the WDTOVF signal is input to the RES pin, this LSI will not be initialized correctly. Make sure that the WDTOVF signal is not input logically to the RES pin. To reset the entire system by means of the WDTOVF signal, use a circuit like that shown in figure 18.6. Reset input Reset signal to entire system This LSI RES WDTOVF Figure 18.6 Circuit for System Reset by WDTOVF Signal (Example)

18.6.7 Transition to Watchdog Timer Mode or Software Standby Mode

When the WDT operates in watchdog timer mode, a transition to software standby mode is not made even when the SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1. Instead, a transition to sleep mode is made. To transit to software standby mode, the SLEEP instruction must be executed after halting the WDT (clearing the TME bit to 0). When the WDT operates in interval timer mode, a transition to software standby mode is made through execution of the SLEEP instruction when the SSBY bit in SBYCR is set to 1.

Section 18 Watchdog Timer (WDT) Rev. 2.00 Jul. 31, 2008 Page 884 of 1438 REJ09B0365-0200

Section 19 Serial Communication Interface (SCI, IrDA, CRC) Rev. 2.00 Jul. 31, 2008 Page 885 of 1438 REJ09B0365-0200 Section 19 Serial Communication Interface (SCI, IrDA, CRC) This LSI has seven independent serial Communication interface (SCI) channels. The SCI can handle both asynchronous and clock synchronous serial Communication. Asynchronous serial data Communication can be carried out with standard asynchronous Communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial Communication between processors (multiprocessor communication function). The SCI also supports the smart card (smart card) interface supporting ISO/IEC 7816-3 (Identification Card) as an extended asynchronous Communication mode. SCI_5 enables transmitting and receiving IrDA communication waveform based on the IrDA Specifications version 1.0. This LSI incorporates the on-chip CRC (Cyclic Redundancy Check) computing unit that realizes high reliability of high-speed data transfer as SCI extended function. Since the CRC computing unit is not connected to SCI, operation is executed by writing data to registers. Figure 19.1 shows a block diagram of the SCI_0 to SCI_4. Figure 19.2 shows a block diagram of the SCI_5 and SCI_6.

19.1 Features

• Choice of asynchronous or clock synchronous serial Communication mode
• Full-duplex Communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data.
• On-chip baud rate generator allows any bit rate to be selected The external clock can be selected as a transfer clock source (except for the smart card interface).
• Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data)
• Four interrupt sources The interrupt sources are transmit-end, transmit-data-empty, receive-data-full, and receive error. The transmit-data-empty and receive-data-full interrupt sources can activate the DTC or DMAC.
• Module stop state specifiable

Section 19 Serial Communication Interface (SCI, IrDA, CRC) Rev. 2.00 Jul. 31, 2008 Page 886 of 1438 REJ09B0365-0200 Asynchronous Mode:

• Data length: 7 or 8 bits
• Stop bit length: 1 or 2 bits
• Parity: Even, odd, or none
• Receive error detection: Parity, overrun, and framing errors
• Break detection: Break can be detected by reading the RxD pin level directly in case of a framing error
• Enables transfer rate clock input from TMR (SCI_5, SCI_6)
• Average transfer rate generator (SCI_2) 10.667-MHz operation: 115.152 kbps or 460.606 kbps can be selected 16-MHz operation: 115.196 kbps, 460.784 kbps, or 720 kbps can be selected 32-MHz operation: 720 kbps
• Average transfer rate generator (SCI_5, SCI_6) 8-MHz operation: 460.784 kbps can be selected 10.667-MHz operation: 115.152 kbps or 460.606 kbps can be selected 12-MHz operation: 230.263 kbps or 460.526 kbps can be selected 16-MHz operation: 115.196 kbps, 460.784 kbps, 720 kbps, or 921.569 kbps can be selected 24-MHz operation: 115.132 kbps, 460.526 kbps, 720 kbps, or 921.053 kbps can be selected 32-MHz operation: 720 kbps can be selected Clock Synchronous Mode:
• Data length: 8 bits
• Receive error detection: Overrun errors Smart Card Interface:
• An error signal can be automatically transmitted on detection of a parity error during reception
• Data can be automatically re-transmitted on receiving an error signal during transmission
• Both direct convention and inverse convention are supported

Section 19 Serial Communication Interface (SCI, IrDA, CRC) Rev. 2.00 Jul. 31, 2008 Page 887 of 1438 REJ09B0365-0200 Table 19.1 lists the functions of each channel. Table 19.1 Function List of SCI Channels SCI_0, 1, 3, 4 SCI_2 SCI_5, SCI_6 Clock synchronous mode O O O Asynchronous mode O O O TMR clock input — — O Pφ = 8 MHz — — 460.784 kbps Pφ = 10.667 MHz — 460.606 kbps 115.152 kbps 460.606 kbps 115.152 kbps Pφ = 12 MHz — — 460.526 kbps 230.263 kbps Pφ = 16 MHz — 720 kbps 460 784kbps 115.196 kbps 921.569 kbps 720 kbps 460.784 kbps 115.196 kbps Pφ = 24 MHz — — 921.053 kbps 720 kbps 460.526 kbps 115.132 kbps When average transfer rate generator is used Pφ = 32 MHz — 720 kbps 720 kbps

Section 19 Serial Communication Interface (SCI, IrDA, CRC) Rev. 2.00 Jul. 31, 2008 Page 888 of 1438 REJ09B0365-0200 RxD TxD SCK Clock Pφ Pφ/4 Pφ/16 Pφ/64 TEI TXI RXI ERI SCMR SSR SCR SMR SEMR Transmission/ reception control Baud rate generator BRR Module data bus RDR TSRRSR Parity generation Parity check [Legend] RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register TDR Bus interface Internal data bus External clock SCR: Serial control register SSR: Serial status register SCMR: Smart card mode register BRR: Bit rate register SEMR: Serial extended mode register (available only for SCI_2) Average transfer rate generator (SCI_2) Figure 19.1 Block Diagram of SCI_0, 1, 2, 3, and 4

Section 19 Serial Communication Interface (SCI, IrDA, CRC) Rev. 2.00 Jul. 31, 2008 Page 889 of 1438 REJ09B0365-0200 RxD0 TxD0 Clock Pφ Pφ/4 Pφ/16 Pφ/64 TEI TXI RXI ERI SCMR SSR SCR SMR SEMR IrCR* Transmission/ reception control Baud rate generator BRR TMR TMO4, 6 TMO5, 7 Module data bus RDR TSRRSR Parity generation Parity check [Legend] RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register SCR: Serial control register Note: * SCI_5 only. TDR Bus interface Internal data bus Average transfer rate generator SCK SSR: Serial status register SCMR: Smart card mode register BRR: Bit rate register SEMR: Serial extended mode register IrCR: IrDA control register (available only for SCI_5) Figure 19.2 Block Diagram of SCI_5 and SCI_6

Section 19 Serial Communication Interface (SCI, IrDA, CRC) Rev. 2.00 Jul. 31, 2008 Page 890 of 1438 REJ09B0365-0200

19.2 Input/Output Pins

Table 19.2 lists the pin configuration of the SCI. Table 19.2 Pin Configuration Channel Pin Name * I/O Function SCK0 I/O Channel 0 clock input/output RxD0 Input Channel 0 receive data input TxD0 Output Channel 0 transmit data output SCK1 I/O Channel 1 clock input/output RxD1 Input Channel 1 receive data input TxD1 Output Channel 1 transmit data output SCK2 I/O Channel 2 clock input/output RxD2 Input Channel 2 receive data input TxD2 Output Channel 2 transmit data output SCK3 I/O Channel 3 clock input/output RxD3 Input Channel 3 receive data input TxD3 Output Channel 3 transmit data output SCK4 I/O Channel 4 clock input/output RxD4 Input Channel 4 receive data input TxD4 Output Channel 4 transmit data output SCK5 I/O Channel 5 clock input/output RxD5/IrRxD Input Channel 5 receive data input TxD5/IrTxD Output Channel 5 transmit data output SCK6 I/O Channel 6 clock input/output RxD6 Input Channel 6 receive data input TxD6 Output Channel 6 transmit data output Note: * Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the channel designation.

Section 19 Serial Communication Interface (SCI, IrDA, CRC) Rev. 2.00 Jul. 31, 2008 Page 891 of 1438 REJ09B0365-0200

19.3 Register Descriptions

The SCI has the following registers. Some bits in the serial mode register (SMR), serial status register (SSR), and serial control register (SCR) have different functions in different modesnormal serial Communication interface mode and smart card interface mode; therefore, the bits are described separately for each mode in the corresponding register sections. Channel 0:

• Receive shift register_0 (RSR_0)
• Transmit shift register_0 (TSR_0)
• Receive data register_0 (RDR_0)
• Transmit data register_0 (TDR_0)
• Serial mode register_0 (SMR_0)
• Serial control register_0 (SCR_0)
• Serial status register_0 (SSR_0)
• Smart card mode register_0 (SCMR_0)
• Bit rate register_0 (BRR_0) Channel 1:
• Receive shift register_1 (RSR_1)
• Transmit shift register_1 (TSR_1)
• Receive data register_1 (RDR_1)
• Transmit data register_1 (TDR_1)
• Serial mode register_1 (SMR_1)
• Serial control register_1 (SCR_1)
• Serial status register_1 (SSR_1)
• Smart card mode register_1 (SCMR_1)
• Bit rate register_1 (BRR_1)

Section 19 Serial Communication Interface (SCI, IrDA, CRC) Rev. 2.00 Jul. 31, 2008 Page 892 of 1438 REJ09B0365-0200 Channel 2:

• Receive shift register_2 (RSR_2)
• Transmit shift register_2 (TSR_2)
• Receive data register_2 (RDR_2)
• Transmit data register_2 (TDR_2)
• Serial mode register_2 (SMR_2)
• Serial control register_2 (SCR_2)
• Serial status register_2 (SSR_2)
• Smart card mode register_2 (SCMR_2)
• Bit rate register_2 (BRR_2) Channel 3:
• Receive shift register_3 (RSR_3)
• Transmit shift register_3 (TSR_3)
• Receive data register_3 (RDR_3)
• Transmit data register_3 (TDR_3)
• Serial mode register_3 (SMR_3)
• Serial control register_3 (SCR_3)
• Serial status register_3 (SSR_3)
• Smart card mode register_3 (SCMR_3)
• Bit rate register_3 (BRR_3) Channel 4:
• Receive shift register_4 (RSR_4)
• Transmit shift register_4 (TSR_4)
• Receive data register_4 (RDR_4)
• Transmit data register_4 (TDR_4)
• Serial mode register_4 (SMR_4)
• Serial control register_4 (SCR_4)
• Serial status register_4 (SSR_4)
• Smart card mode register_4 (SCMR_4)
• Bit rate register_4 (BRR_4) Channel 5:
• Receive shift register_5 (RSR_5)

Section 19 Serial Communication Interface (SCI, IrDA, CRC) Rev. 2.00 Jul. 31, 2008 Page 893 of 1438 REJ09B0365-0200

• Transmit shift register_5 (TSR_5)
• Receive data register_5 (RDR_5)
• Transmit data register_5 (TDR_5)
• Serial mode register_5 (SMR_5)
• Serial control register_5 (SCR_5)
• Serial status register_5 (SSR_5)
• Smart card mode register_5 (SCMR_5)
• Bit rate register_5 (BRR_5)
• Serial extended mode register_5 (SEMR_5)
• IrDA control register_5 (IrCR) Channel 6:
• Receive shift register_6 (RSR_6)
• Transmit shift register_6 (TSR_6)
• Receive data register_6 (RDR_6)
• Transmit data register_6 (TDR_6)
• Serial mode register_6 (SMR_6)
• Serial control register_6 (SCR_6)
• Serial status register_6 (SSR_6)
• Smart card mode register_6 (SCMR_6)
• Serial extended mode register_6 (SEMR_6)
• Bit rate register_6 (BRR_6)

Section 19 Serial Communication Interface (SCI, IrDA, CRC) Rev. 2.00 Jul. 31, 2008 Page 894 of 1438 REJ09B0365-0200

19.3.1 Receive Shift Register (RSR)

RSR is a shift register which is used to receive serial data input from the RxD pin and converts it into parallel data. When one frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU.

19.3.2 Receive Data Register (RDR)

RDR is an 8-bit register that stores receive data. When the SCI has received one frame of serial data, it transfers the received serial data from RSR to RDR where it is stored. This allows RSR to receive the next data. Since RSR and RDR function as a double buffer in this way, continuous receive operations can be performed. After confirming that the RDRF bit in SSR is set to 1, read RDR only once. RDR cannot be written to by the CPU. Bit Bit Name Initial Value R/W R R R R R R R R

19.3.3 Transmit Data Register (TDR)

TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered structures of TDR and TSR enable continuous serial transmission. If the next transmit data has already been written to TDR when one frame of data is transmitted, the SCI transfers the written data to TSR to continue transmission. Although TDR can be read from or written to by the CPU at all times, to achieve reliable serial transmission, write transmit data to TDR for only once after confirming that the TDRE bit in SSR is set to 1. Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W

Section 19 Serial Communication Interface (SCI, IrDA, CRC) Rev. 2.00 Jul. 31, 2008 Page 895 of 1438 REJ09B0365-0200

19.3.4 Transmit Shift Register (TSR)

TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first automatically transfers transmit data from TDR to TSR, and then sends the data to the TxD pin. TSR cannot be directly accessed by the CPU.

19.3.5 Serial Mode Register (SMR)

SMR is used to set the SCI's serial transfer format and select the baud rate generator clock source. Some bits in SMR have different functions in normal mode and smart card interface mode.

• When SMIF in SCMR = 0 C/A R/W CHR R/W PE R/W O/E R/W STOP R/W MP R/W CKS1 R/W CKS0 R/W Bit Bit Name Initial Value R/W
• When SMIF in SCMR = 1 GM R/W BLK R/W PE R/W O/E R/W BCP1 R/W BCP0 R/W CKS1 R/W CKS0 R/W Bit Bit Name Initial Value R/W Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0): Bit Bit Name Initial Value R/W Description

7 C/ A 0 R/W Communication Mode

0: Asynchronous mode 1: Clock synchronous mode

6 CHR 0 R/W Character Length (valid only in asynchronous mode)

0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length. LSB-first is fixed and the MSB (bit 7) in TDR is not transmitted in transmission. In clock synchronous mode, a fixed data length of 8 bits is used.

Section 19 Serial Communication Interface (SCI, IrDA, CRC) Rev. 2.00 Jul. 31, 2008 Page 896 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description

5 PE 0 R/W Parity Enable (valid only in asynchronous mode)

When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. For a multiprocessor format, parity bit addition and checking are not performed regardless of the PE bit setting.

4 O/ E 0 R/W Parity Mode (valid only when the PE bit is 1 in

asynchronous mode) 0: Selects even parity. 1: Selects odd parity.

3 STOP 0 R/W Stop Bit Length (valid only in asynchronous mode)

Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits In reception, only the first stop bit is checked. If the second stop bit is 0, it is treated as the start bit of the next transmit frame.

2 MP 0 R/W Multiprocessor Mode (valid only in asynchronous mode)

When this bit is set to 1, the multiprocessor function is enabled. The PE bit and O/E bit settings are invalid in multiprocessor mode. CKS1 CKS0 R/W R/W Clock Select 1, 0 These bits select the clock source for the baud rate generator. 00: Pφ clock (n = 0) 01: Pφ/4 clock (n = 1) 10: Pφ/16 clock (n = 2) 11: Pφ/64 clock (n = 3) For the relation between the settings of these bits and the baud rate, see section 19.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR (see section 19.3.9, Bit Rate Register (BRR)).

Section 19 Serial Communication Interface (SCI, IrDA, CRC) Rev. 2.00 Jul. 31, 2008 Page 897 of 1438 REJ09B0365-0200 Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1): Bit Bit Name Initial Value R/W Description

7 GM 0 R/W GSM Mode

Setting this bit to 1 allows GSM mode operation. In GSM mode, the TEND set timing is put forward to 11.0 etu from the start and the clock output control function is appended. For details, see sections 19.7.6, Data Transmission (Except in Block Transfer Mode) and 19.7.8, Clock Output Control. 6 BLK 0 R/W Setting this bit to 1 allows block transfer mode operation. For details, see section 19.7.3, Block Transfer Mode. When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. Set this bit to 1 in smart card interface mode. asynchronous mode) 0: Selects even parity 1: Selects odd parity For details on the usage of this bit in smart card interface mode, see section 19.7.2, Data Format (Except in Block Transfer Mode). BCP1 BCP0 R/W R/W Base clock Pulse 1, 0 These bits select the number of base clock cycles in a 1- bit data transfer time in smart card interface mode. 00: 32 clock cycles (S = 32) 01: 64 clock cycles (S = 64) 10: 372 clock cycles (S = 372) 11: 256 clock cycles (S = 256) For details, see section 19.7.4, Receive Data Sampling Timing and Reception Margin. S is described in section 19.3.9, Bit Rate Register (BRR).

Section 19 Serial Communication Interface (SCI, IrDA, CRC) Rev. 2.00 Jul. 31, 2008 Page 898 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description CKS1 CKS0 R/W R/W Clock Select 1, 0 These bits select the clock source for the baud rate generator. 00: Pφ clock (n = 0) 01: Pφ/4 clock (n = 1) 10: Pφ/16 clock (n = 2) 11: Pφ/64 clock (n = 3) For the relation between the settings of these bits and the baud rate, see section 19.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR (see section 19.3.9, Bit Rate Register (BRR)). Note: etu (Elementary Time Unit): 1-bit transfer time

Section 19 Serial Communication Interface (SCI, IrDA, CRC) Rev. 2.00 Jul. 31, 2008 Page 899 of 1438 REJ09B0365-0200

19.3.6 Serial Control Register (SCR)

SCR is a register that enables/disables the following SCI transfer operations and interrupt requests, and selects the transfer clock source. For details on interrupt requests, see section 19.9, Interrupt Sources. Some bits in SCR have different functions in normal mode and smart card interface mode.

• When SMIF in SCMR = 0 TIE R/W RIE R/W TE R/W RE R/W MPIE R/W TEIE R/W CKE1 R/W CKE0 R/W Bit Bit Name Initial Value R/W
• When SMIF in SCMR = 1 TIE R/W RIE R/W TE R/W RE R/W MPIE R/W TEIE R/W CKE1 R/W CKE0 R/W Bit Bit Name Initial Value R/W Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0): Bit Bit Name Initial Value R/W Description

7 TIE 0 R/W Transmit Interrupt Enable

When this bit is set to 1, a TXI interrupt request is enabled. A TXI interrupt request can be cancelled by reading 1 from the TDRE flag and then clearing the flag to 0, or by clearing the TIE bit to 0.

6 RIE 0 R/W Receive Interrupt Enable

When this bit is set to 1, RXI and ERI interrupt requests are enabled. RXI and ERI interrupt requests can be cancelled by reading 1 from the RDRF, FER, PER, or ORER flag and then clearing the flag to 0, or by clearing the RIE bit to 0.

Section 19 Serial Communication Interface (SCI, IrDA, CRC) Rev. 2.00 Jul. 31, 2008 Page 900 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description

5 TE 0 R/W Transmit Enable

When this bit is set to 1, transmission is enabled. Under this condition, serial transmission is started by writing transmit data to TDR, and clearing the TDRE flag in SSR to 0. Note that SMR should be set prior to setting the TE bit to 1 in order to designate the transmission format. If transmission is halted by clearing this bit to 0, the TDRE flag in SSR is fixed to 1.

4 RE 0 R/W Receive Enable

When this bit is set to 1, reception is enabled. Under this condition, serial reception is started by detecting the start bit in asynchronous mode or the synchronous clock input in clock synchronous mode. Note that SMR should be set prior to setting the RE bit to 1 in order to designate the reception format. Even if reception is halted by clearing this bit to 0, the RDRF, FER, PER, and ORER flags are not affected and the previous value is retained.

3 MPIE 0 R/W Multiprocessor Interrupt Enable (valid only when the MP

bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is disabled. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. For details, see section 19.5, Multiprocessor Communication Function. When receive data including MPB = 0 in SSR is being received, transfer of the received data from RSR to RDR, detection of reception errors, and the settings of RDRF, FER, and ORER flags in SSR are not performed. When receive data including MPB = 1 is received, the MPB bit in SSR is set to 1, the MPIE bit is automatically cleared to 0, and RXI and ERI interrupt requests (in the case where the TIE and RIE bits in SCR are set to 1) and setting of the FER and ORER flags are enabled.

Section 19 Serial Communication Interface (SCI, IrDA, CRC) Rev. 2.00 Jul. 31, 2008 Page 901 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description

2 TEIE 0 R/W Transmit End Interrupt Enable

When this bit is set to 1, a TEI interrupt request is enabled. A TEI interrupt request can be cancelled by reading 1 from the TDRE flag and then clearing the flag to 0 in order to clear the TEND flag to 0, or by clearing the TEIE bit to 0. CKE1 CKE0 R/W R/W Clock Enable 1, 0 (for SCI_0, 1, 3, and 4) These bits select the clock source and SCK pin function.

• Asynchronous mode 00: On-chip baud rate generator The SCK pin functions as I/O port. 01: On-chip baud rate generator The clock with the same frequency as the bit rate is output from the SCK pin. 1x: External clock The clock with a frequency 16 times the bit rate should be input from the SCK pin.
• Clock synchronous mode 0x: Internal clock The SCK pin functions as the clock output pin. 1x: External clock The SCK pin functions as the clock input pin.

Section 19 Serial Communication Interface (SCI, IrDA, CRC) Rev. 2.00 Jul. 31, 2008 Page 902 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description CKE1 CKE0 R/W R/W Clock Enable 1, 0 (for SCI_2) These bits select the clock source and SCK pin function.

• Asynchronous mode 00: On-chip baud rate generator The SCK pin functions as I/O port. 01: On-chip baud rate generator The clock with the same frequency as the bit rate is output from the SCK pin. 1x: External clock or average transfer rate generator When an external clock is used, the clock with a frequency 16 times the bit rate should be input from the SCK pin. When an average transfer rate generator is used.
• Clock synchronous mode 0x: Internal clock The SCK pin functions as the clock output pin. 1x: External clock The SCK pin functions as the clock input pin.

Section 19 Serial Communication Interface (SCI, IrDA, CRC) Rev. 2.00 Jul. 31, 2008 Page 903 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description CKE1 CKE0 R/W R/W Clock Enable 1, 0 (for SCI_5 and SCI_6) These bits select the clock source and SCK pin function.

• Asynchronous mode 00: On-chip baud rate generator The SCK pin functions as I/O port. 01: On-chip baud rate generator The clock with the same frequency as the bit rate is output from the SCK pin. 1x: External clock, TMR clock input or average transfer rate generator When an external clock is used, the clock with a frequency 16 times the bit rate should be input from the SCK pin. When an average transfer rate generator is used. When TMR clock input is used.
• Clock synchronous mode 0x: Internal clock The SCK pin functions as the clock output pin. 1x: External clock The SCK pin functions as the clock input pin. [Legend] x: Don't care

Section 19 Serial Communication Interface (SCI, IrDA, CRC) Rev. 2.00 Jul. 31, 2008 Page 904 of 1438 REJ09B0365-0200 Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1): Bit Bit Name Initial Value R/W Description When this bit is set to 1,a TXI interrupt request is enabled. A TXI interrupt request can be cancelled by reading 1 from the TDRE flag and then clearing the flag to 0, or by clearing the TIE bit to 0. When this bit is set to 1, RXI and ERI interrupt requests are enabled. RXI and ERI interrupt requests can be cancelled by reading 1 from the RDRF, FER, PER, or ORER flag and then clearing the flag to 0, or by clearing the RIE bit to 0. When this bit is set to 1, transmission is enabled. Under this condition, serial transmission is started by writing transmit data to TDR, and clearing the TDRE flag in SSR to 0. Note that SMR should be set prior to setting the TE bit to 1 in order to designate the transmission format. If transmission is halted by clearing this bit to 0, the TDRE flag in SSR is fixed 1. When this bit is set to 1, reception is enabled. Under this condition, serial reception is started by detecting the start bit in asynchronous mode or the synchronous clock input in clock synchronous mode. Note that SMR should be set prior to setting the RE bit to 1 in order to designate the reception format. Even if reception is halted by clearing this bit to 0, the RDRF, FER, PER, and ORER flags are not affected and the previous value is retained. bit in SMR is 1 in asynchronous mode) Write 0 to this bit in smart card interface mode. Write 0 to this bit in smart card interface mode.

Section 19 Serial Communication Interface (SCI, IrDA, CRC) Rev. 2.00 Jul. 31, 2008 Page 905 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description CKE1 CKE0 R/W R/W Clock Enable 1, 0 These bits control the clock output from the SCK pin. In GSM mode, clock output can be dynamically switched. For details, see section 19.7.8, Clock Output Control.

• When GM in SMR = 0 00: Output disabled (SCK pin functions as I/O port.) 01: Clock output 1x: Reserved
• When GM in SMR = 1 00: Output fixed low 01: Clock output 10: Output fixed high 11: Clock output

19.3.7 Serial Status Register (SSR)

SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE, RDRF, ORER, PER, and FER can only be cleared. Some bits in SSR have different functions in normal mode and smart card interface mode.

• When SMIF in SCMR = 0 Bit Bit Name Initial Value R/W TDRE R/(W)* RDRF R/(W)* ORER R/(W)* FER R/(W)* PER R/(W)* TEND R MPB R MPBT R/W Note: * Only 0 can be written, to clear the flag.
• When SMIF in SCMR = 1 Bit Bit Name Initial Value R/W TDRE R/(W)* RDRF R/(W)* ORER R/(W)* ERS R/(W)* PER R/(W)* TEND R MPB R MPBT R/W Note: * Only 0 can be written, to clear the flag.

Section 19 Serial Communication Interface (SCI, IrDA, CRC) Rev. 2.00 Jul. 31, 2008 Page 906 of 1438 REJ09B0365-0200 Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0): Bit Bit Name Initial Value R/W Description

7 TDRE 1 R/(W) * Transmit Data Register Empty

Indicates whether TDR contains transmit data. [Setting conditions]

• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR [Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
• When a TXI interrupt request is issued allowing DMAC or DTC to write data to TDR

6 RDRF 0 R/(W) * Receive Data Register Full

Indicates whether receive data is stored in RDR. [Setting condition]

• When serial reception ends normally and receive data is transferred from RSR to RDR [Clearing conditions]
• When 0 is written to RDRF after reading RDRF = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
• When an RXI interrupt request is issued allowing DMAC or DTC to read data from RDR The RDRF flag is not affected and retains its previous value when the RE bit in SCR is cleared to 0. Note that when the next serial reception is completed while the RDRF flag is being set to 1, an overrun error occurs and the received data is lost.

Section 19 Serial Communication Interface (SCI, IrDA, CRC) Rev. 2.00 Jul. 31, 2008 Page 907 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description

5 ORER 0 R/(W) * Overrun Error

Indicates that an overrun error has occurred during reception and the reception ends abnormally. [Setting condition]

• When the next serial reception is completed while RDRF = 1 In RDR, receive data prior to an overrun error occurrence is retained, but data received after the overrun error occurrence is lost. When the ORER flag is set to 1, subsequent serial reception cannot be performed. Note that, in clock synchronous mode, serial transmission also cannot continue. [Clearing condition]
• When 0 is written to ORER after reading ORER = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Even when the RE bit in SCR is cleared, the ORER flag is not affected and retains its previous value.

Section 19 Serial Communication Interface (SCI, IrDA, CRC) Rev. 2.00 Jul. 31, 2008 Page 908 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description

4 FER 0 R/(W) * Framing Error

Indicates that a framing error has occurred during reception in asynchronous mode and the reception ends abnormally. [Setting condition]

• When the stop bit is 0 In 2-stop-bit mode, only the first stop bit is checked whether it is 1 but the second stop bit is not checked. Note that receive data when the framing error occurs is transferred to RDR, however, the RDRF flag is not set. In addition, when the FER flag is being set to 1, the subsequent serial reception cannot be performed. In clock synchronous mode, serial transmission also cannot continue. [Clearing condition]
• When 0 is written to FER after reading FER = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Even when the RE bit in SCR is cleared, the FER flag is not affected and retains its previous value.

Section 19 Serial Communication Interface (SCI, IrDA, CRC) Rev. 2.00 Jul. 31, 2008 Page 909 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description

3 PER 0 R/(W) * Parity Error

Indicates that a parity error has occurred during reception in asynchronous mode and the reception ends abnormally. [Setting condition]

• When a parity error is detected during reception Receive data when the parity error occurs is transferred to RDR, however, the RDRF flag is not set. Note that when the PER flag is being set to 1, the subsequent serial reception cannot be performed. In clock synchronous mode, serial transmission also cannot continue. [Clearing condition]
• When 0 is written to PER after reading PER = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Even when the RE bit in SCR is cleared, the PER bit is not affected and retains its previous value.

2 TEND 1 R Transmit End

[Setting conditions]

• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of a transmit character [Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When a TXI interrupt request is issued allowing DMAC or DTC to write data to TDR

1 MPB 0 R Multiprocessor Bit

Stores the multiprocessor bit value in the receive frame. When the RE bit in SCR is cleared to 0 its previous state is retained.

0 MPBT 0 R/W Multiprocessor Bit Transfer

Sets the multiprocessor bit value to be added to the transmit frame. Note: * Only 0 can be written, to clear the flag.

Section 19 Serial Communication Interface (SCI, IrDA, CRC) Rev. 2.00 Jul. 31, 2008 Page 910 of 1438 REJ09B0365-0200 Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1): Bit Bit Name Initial Value R/W Description Indicates whether TDR contains transmit data. [Setting conditions]

• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR [Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
• When a TXI interrupt request is issued allowing DMAC or DTC to write data to TDR

Indicates whether receive data is stored in RDR. [Setting condition]

• When serial reception ends normally and receive data is transferred from RSR to RDR [Clearing conditions]
• When 0 is written to RDRF after reading RDRF = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
• When an RXI interrupt request is issued allowing DMAC or DTC to read data from RDR The RDRF flag is not affected and retains its previous value even when the RE bit in SCR is cleared to 0. Note that when the next reception is completed while the RDRF flag is being set to 1, an overrun error occurs and the received data is lost.

Section 19 Serial Communication Interface (SCI, IrDA, CRC) Rev. 2.00 Jul. 31, 2008 Page 911 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description Indicates that an overrun error has occurred during reception and the reception ends abnormally. [Setting condition]

• When the next serial reception is completed while RDRF = 1 In RDR, the receive data prior to an overrun error occurrence is retained, but data received following the overrun error occurrence is lost. When the ORER flag is set to 1, subsequent serial reception cannot be performed. Note that, in clock synchronous mode, serial transmission also cannot continue. [Clearing condition]
• When 0 is written to ORER after reading ORER = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Even when the RE bit in SCR is cleared, the ORER flag is not affected and retains its previous value.

4 ERS 0 R/(W) * Error Signal Status

[Setting condition]

• When a low error signal is sampled [Clearing condition]
• When 0 is written to ERS after reading ERS = 1

Section 19 Serial Communication Interface (SCI, IrDA, CRC) Rev. 2.00 Jul. 31, 2008 Page 912 of 1438 REJ09B0365-0200 Bit Bit Name Initial Value R/W Description Indicates that a parity error has occurred during reception in asynchronous mode and the reception ends abnormally. [Setting condition]

• When a parity error is detected during reception Receive data when the parity error occurs is transferred to RDR, however, the RDRF flag is not set. Note that when the PER flag is being set to 1, the subsequent serial reception cannot be performed. In clock synchronous mode, serial transmission also cannot continue. [Clearing condition]
• When 0 is written to PER after reading PER = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Even when the RE bit in SCR is cleared, the PER flag is not affected and retains its previous value.

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