R5F61525

H8SX1520 RENESAS | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 1.1 Features
• 1.2 Block Diagram
• 1.3 Pin Assignments
• 1.3.1 Pin Assignments
• 1.3.2 Pin Configuration in Each Operating Mode
• 1.3.3 Pin Functions
• 2.1 Features
• 2.2 CPU Operating Modes
• 2.2.1 Normal Mode
• 2.2.2 Middle Mode
• 2.2.3 Advanced Mode
• 2.2.4 Maximum Mode
• 2.3 Instruction Fetch
• 2.4 Address Space
• 2.5 Registers
• 2.5.1 General Registers
• 2.5.2 Program Counter (PC)
• 2.5.3 Condition-Code Register (CCR)
• 2.5.4 Extended Control Register (EXR)
• 2.5.5 Vector Base Register (VBR)
• 2.5.6 Short Address Base Register (SBR)
• 2.5.7 Multiply-Accumulate Register (MAC)
• 2.5.8 Initial Values of CPU Registers
• 2.6.1 General Register Data Formats
• 2.6.2 Memory Data Formats
• 2.7 Instruction Set
• 2.7.1 Instructions and Addressing Modes
• 2.7.2 Table of Instructions Classified by Function
• 2.7.3 Basic Instruction Formats
• 2.8 Addressing Modes and Effective Address Calculation
• 2.8.1 Register Direct—Rn
• 2.8.2 Register Indirect—@ERn

Revision Date: Mar. 14, 2006

32 H8SX/1520Group

Renesas 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series H8SX/1527 R5F61527 H8SX/1525 R5F61525 Rev.3.00 REJ09B0104-0300

Rev. 3.00 Mar. 14, 2006 Page ii of xxxviii

Rev. 3.00 Mar. 14, 2006 Page iii of xxxviii 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third- party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Keep safety first in your circuit designs! Notes regarding these materials

Rev. 3.00 Mar. 14, 2006 Page iv of xxxviii General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a pass- through current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed.

Rev. 3.00 Mar. 14, 2006 Page v of xxxviii Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules

• CPU and System-Control Modules
• On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix 10. Main Revisions and Additions in this Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 11. Index

Rev. 3.00 Mar. 14, 2006 Page vi of xxxviii Preface The H8SX/1520 Group is a single-chip microcomputer made up of the high-speed internal 32-bit H8SX CPU as its core, and the peripheral functions required to configure a system. The H8SX CPU is upward compatible with the H8/300, H8/300H, and H8S CPUs. Target Users: This manual was written for users who will be using the H8SX/1520 Group in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the H8SX/1520 Group to the target users. Refer to the H8SX Family Software Manual for a detailed description of the instruction set. Notes on reading this manual: In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, and peripheral functions. In order to understand the details of the CPU's functions Read the H8SX Family Software Manual. In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 20, List of Registers. Examples: Register name: The following notation is used for cases when the same or a similar function, e.g. 16-bit timer pulse unit or serial communication interface, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) Bit order: The MSB is on the left and the LSB is on the right. Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx. Signal notation: An overbar is added to a low-active signal: xxxx Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/

Rev. 3.00 Mar. 14, 2006 Page vii of xxxviii H8SX/1520 Group manuals: Document Title Document No. H8SX/1520 Group Hardware Manual This manual H8/SX Family Software Manual REJ09B0102

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2.8.3 Register Indirect with Displacement—@(d:2, ERn), @(d:16, ERn),

2.8.4 Index Register Indirect with Displacement—@(d:16,RnL.B), @(d:32,RnL.B),

2.8.5 Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment,

2.8.9 Program-Counter Relative with Index Register— @(RnL.B, PC),

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5.3.3 Interrupt Priority Registers A to G, I, K to O, Q, and R

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10.4.6 Example of Non-Overlapping Pulse Output

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12.4.2 Receive Data Sampling Timing and Reception Margin

12.6.5 Simultaneous Serial Data Transmission and Reception

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12.9.4 Receive Error Flags and Transmit Operations

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Rev. 3.00 Mar. 14, 2006 Page xxxi of xxxviii Appendix

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Rev. 3.00 Mar. 14, 2006 Page xxxiii of xxxviii Tables Section 1 Overview Section 2 CPU Section 3 MCU Operating Modes Section 4 Exception Handling Section 5 Interrupt Controller

Rev. 3.00 Mar. 14, 2006 Page xxxiv of xxxviii Section 6 Bus Controller (BSC) Section 7 DMA Controller (DMAC) Section 8 I/O Ports Section 9 16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Mar. 14, 2006 Page xxxv of xxxviii Section 10 Programmable Pulse Generator (PPG) Section 11 Watchdog Timer (WDT) Section 12 Serial Communication Interface (SCI)

Rev. 3.00 Mar. 14, 2006 Page xxxvi of xxxviii Table 12.8 BRR Settings for Various Bit Rates Table 12.9 Maximum Bit Rate for Each Operating Frequency Section 13 Controller Area Network (HCAN) Section 14 Synchronous Serial Communication Unit (SSU) Section 15 A/D Converter Section 17 Flash Memory (0.18-mm F-ZTAT Version) Table 17.1 Differences between Boot Mode, User Program Mode, User Boot Mode,

Rev. 3.00 Mar. 14, 2006 Page xxxvii of xxxviii Section 18 Clock Pulse Generator Section 19 Power-Down Modes Section 21 Electrical Characteristics Appendix

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Rev. 3.00 Mar. 14, 2006 Page 1 of 804 REJ09B0104-0300 Section 1 Overview

1.1 Features

• 32-bit high-speed H8SX CPU Upward compatible with the H8/300 CPU, H8/300H CPU, and H8S CPU Sixteen 16-bit general registers 87 basic instructions
• Extensive peripheral functions DMA controller (DMAC) 16-bit timer pulse unit (TPU) Programmable pulse generator (PPG)* Watch dog timer (WDT) Serial communication interface (SCI) can be used in asynchronous and clocked synchronous mode Controller area network (HCAN) Synchronous serial communication unit (SSU) 10-bit A/D converter Clock pulse generator Note: * Supported only by the H8SX/1527.
• On-chip memory Product Classification Product Model ROM RAM Flash memory version H8SX/1527 R5F61527 256 kbytes 12 kbytes H8SX/1525 R5F61525 256 kbytes 12 kbytes
• General I/O port 65 input/output ports 17 input ports
• Supports power-down modes
• Small package Package Code Body Size Pin Pitch QFP-100 PRQP0100KB-A (FP-100M) 14.0 × 14.0 mm 0.50 mm

Rev. 3.00 Mar. 14, 2006 Page 2 of 804 REJ09B0104-0300

1.2 Block Diagram

× 4 channels HCAN WDT Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port A Port D Port H Port J Port K Interrupt controller Clock pulse generator [Legend] CPU: Central processing unit DMAC: DMA controller BSC: Bus controller WDT: Watchdog timer TPU: 16-bit timer pulse unit PPG: Programmable pulse generator SCI: Serial communication interface HCAN: Controller area network SSU: Synchronous communication unit TPU (unit 0) × 6 channels TPU (unit 1) × 6 channels On-chip debugging function for E10A A/D (unit 1) × 8 channels A/D (unit 0) × 8 channels SCI × 2 channels PPG SSU × 3 channels Figure 1.1 Block Diagram of H8SX/1527

Rev. 3.00 Mar. 14, 2006 Page 3 of 804 REJ09B0104-0300 H8SX CPU RAM ROM BSC DMAC x 4 channels HCAN WDT Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port A Port D Port H Port J Port K Interrupt controller Clock pulse generator [Legend] CPU: Central processing unit DMAC: DMA controller BSC: Bus controller WDT: Watchdog timer TPU: 16-bit timer pulse unit SCI: Serial communication interface HCAN: Controller area network SSU: Synchronous communication unit TPU (unit 1) x 6 channels On-chip debugging function for E10A A/D (unit 1) x 8 channels A/D (unit 0) x 8 channels SCI x 2 channels SSU x 3 channels Internal bus Peripheral bus Figure 1.2 Block Diagram of H8SX/1525

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1.3 Pin Assignments

1.3.1 Pin Assignments

EMLE* Vss EXTAL XTAL Vcc NMI RES P37/PO15/TIOCA2/TIOCB2/TCLKD/TCK* P36/PO14/TIOCA2/TDI* P35/PO13/TIOCA1/TIOCB1/TCLKC/TMS* P34/PO12/TIOCA1/TRST* P33/PO11/TIOCC0/TIOCD0/TCLKB P32/PO10/TIOCC0/TCLKA P31/PO9/TIOCA0/TIOCB0 P30/PO8/TIOCA0 PA4 PA5 PA6 Vcc PA7/Bφ Vss P23/TIOCC3/TIOCD3/IRQ11-A 75747372717069686766656463626160595857565554535251 P22/TIOCC3/IRQ10-A P21/TIOCA3/IRQ9-A/SCS2 P20/TIOCA3/TIOCB3/IRQ8-A P17/ADTRG1/IRQ7 P16/SCK3/IRQ6 P15/RxD3/IRQ5 P14/TxD3/IRQ4 P13/ADTRG0/IRQ3 P12/IRQ2 VCL P11/IRQ1 Vss P10/IRQ0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 PK7/TIOCA11/TIOCB11 PK6/TIOCA11 PK5/TIOCA10/TIOCB10 PK4/TIOCA10 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 PD4/SSO1 PD5/SSI1 PD6/SSCK1 PD7/SCS1 P60/TxD4/IRQ8-B P61/RxD4/IRQ9-B P62/SCK4/IRQ10-B P63/IRQ11-B/TDO* P64/IRQ12/HTxD P65/IRQ13/HRxD P66/IRQ14 PJ0/TIOCA6 PJ1/TIOCA6/TIOCB6 PJ2/TIOCC6/TCLKE PJ3/TIOCC6/TIOCD6/TCLKF PJ4/TIOCA7 PJ5/TIOCA7/TIOCB7/TCLKG PJ6/TIOCA8 PJ7/TIOCA8/TIOCB8/TCLKH Vss PK0/TIOCA9 Vcc PK1/TIOCA9/TIOCB9 PK2/TIOCC9 PK3/TIOCC9/TIOCD9 PRQP0100KB-A (FP-100M) (top view) Note: * The EMLE (emulator enable) pin enables/disables the on-chip debugging functions. When the EMLE pin is driven high, the TDO, TDI, TCK, TMS, and TRST pins are used specific for the E10A. In this case, other pin functions are disabled. Figure 1.3 Pin Assignments of H8SX/1527

Rev. 3.00 Mar. 14, 2006 Page 5 of 804 REJ09B0104-0300 MD1 P40/AN12 P41/AN13 P42/AN14 P43/AN15 P44/AN8 P45/AN9 P46/AN10 AVcc1 P47/AN11 AVss P50/AN0 AVcc0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 MD0 PD0/SSO0 PD1/SSI0 PD2/SSCK0 PD3/SCS0 100 PA1/SSCK2 PA2/SSI2 PA3/SSO2 EMLE* Vss EXTAL XTAL Vcc NMI RES P37/TCK* P36/TDI* P35/TMS* P34/TRST* P33 P32 P31 P30 PA4 PA5 PA6 Vcc PA7/Bφ Vss P23/IRQ11-A 75747372717069686766656463626160595857565554535251 P22/IRQ10-A P21/IRQ9-A/SCS2 P20/IRQ8-A P17/ADTRG1/IRQ7 P16/SCK3/IRQ6 P15/RxD3/IRQ5 P14/TxD3/IRQ4 P13/ADTRG0/IRQ3 P12/IRQ2 VCL P11/IRQ1 Vss P10/IRQ0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 PK7/TIOCA11/TIOCB11 PK6/TIOCA11 PK5/TIOCA10/TIOCB10 PK4/TIOCA10 1 2 3 4 5 6 7 8 9 101112131415161718192021222324 PD4/SSO1 PD5/SSI1 PD6/SSCK1 PD7/SCS1 P60/TxD4/IRQ8-B P61/RxD4/IRQ9-B P62/SCK4/IRQ10-B P63/IRQ11-B/TDO* P64/IRQ12/HTxD P65/IRQ13/HRxD P66/IRQ14 PJ0/TIOCA6 PJ1/TIOCA6/TIOCB6 PJ2/TIOCC6/TCLKE PJ3/TIOCC6/TIOCD6/TCLKF PJ4/TIOCA7 PJ5/TIOCA7/TIOCB7/TCLKG PJ6/TIOCA8 PJ7/TIOCA8/TIOCB8/TCLKH Vss PK0/TIOCA9 Vcc PK1/TIOCA9/TIOCB9 PK2/TIOCC9 PK3/TIOCC9/TIOCD9 PRQP0100KB-A (FP-100M) (top view) Note: * The EMLE (emulator enable) pin enables/disables the on-chip debugging functions. When the EMLE pin is driven high, the TDO, TDI, TCK, TMS, and TRST pins are used specific for the E10A. In this case, other pin functions are disabled. Figure 1.4 Pin Assignments of H8SX/1525

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1.3.2 Pin Configuration in Each Operating Mode

Table 1.1 Pin Configuration in Each Operating Mode Pin No. Abbreviation in Mode 1, Mode 2, and Mode 3

1 PD4/SSO1

2 PD5/SSI1

3 PD6/SSCK1

4 PD7/ SCS1

5 P60/TxD4/ IRQ8-B

6 P61/RxD4/ IRQ9-B

7 P62/SCK4/ IRQ10-B

8 P63/ IRQ11-B/TDO*

9 P64/ IRQ12/HTxD

10 P65/ IRQ13/HRxD

11 P66/ IRQ14

12 PJ0/TIOCA6

13 PJ1/TIOCA6/TIOCB6

14 PJ2/TIOCC6/TCLKE

15 PJ3/TIOCC6/TIOCD6/TCLKF

16 PJ4/TIOCA7

17 PJ5/TIOCA7/TIOCB7/TCLKG

18 PJ6/TIOCA8

19 PJ7/TIOCA8/TIOCB8/TCLKH

20 Vss

21 PK0/TIOCA9

22 Vcc

23 PK1/TIOCA9/TIOCB9

24 PK2/TIOCC9

25 PK3/TIOCC9/TIOCD9

26 PK4/TIOCA10

27 PK5/TIOCA10/TIOCB10

28 PK6/TIOCA11

29 PK7/TIOCA11/TIOCB11

30 PH0

Rev. 3.00 Mar. 14, 2006 Page 7 of 804 REJ09B0104-0300 Pin No. Abbreviation in Mode 1, Mode 2, and Mode 3

31 PH1

32 PH2

33 PH3

34 PH4

35 PH5

36 PH6

37 PH7

38 P10/ IRQ0

39 Vss

40 P11/ IRQ1

41 VCL

42 P12/ IRQ2

43 P13/ ADTRG0/IRQ3

44 P14/TxD3/ IRQ4

45 P15/RxD3/ IRQ5

46 P16/SCK3/ IRQ6

47 P17/ ADTRG1/IRQ7

48 P20/(TIOCA3/TIOCB3) *

/IRQ8-A

49 P21/(TIOCA3) *

/IRQ9-A/SCS2

50 P22/(TIOCC3) *

/IRQ10-A

51 P23/(TIOCC3/TIOCD3) *

/IRQ11-A

52 Vss

53 PA7/B φ

54 Vcc

55 PA6

56 PA5

57 PA4

58 P30/(PO8/TIOCA0) *

59 P31/(PO9/TIOCA0/TIOCB0) *

60 P32/(PO10/TIOCC0/TCLKA) *

Rev. 3.00 Mar. 14, 2006 Page 8 of 804 REJ09B0104-0300 Pin No. Abbreviation in Mode 1, Mode 2, and Mode 3

61 P33/(PO11/TIO CC0/TIOCD0/TCLKB)*

62 P34/(PO12/TIOCA1) *

/TRST*

63 P35/(PO13/TIOCA1/TIOCB1/TCLKC) *

/TMS*

64 P36/(PO14/TIOCA2) *

/TDI*

65 P37/(PO15/TIOCA2/TIOCB2/TCLKD) *

/TCK*

66 RES

67 NMI

68 Vcc

69 XTAL

70 EXTAL

71 Vss

72 EMLE *

73 PA3/SSO2

74 PA2/SSI2

75 PA1/SSCK2

76 MD1

77 P40/AN12

78 P41/AN13

79 P42/AN14

80 P43/AN15

81 P44/AN8

82 P45/AN9

83 P46/AN10

84 AVcc1

85 P47/AN11

86 AVss

87 P50/AN0

88 AVcc0

89 P51/AN1

90 P52/AN2

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91 P53/AN3

92 P54/AN4

93 P55/AN5

94 P56/AN6

95 P57/AN7

96 MD0

97 PD0/SSO0

98 PD1/SSI0

99 PD2/SSCK0

100 PD3/ SCS0

Notes: 1. Not suppor ted by the H8SX/1525. 2. The EMLE (emulator enable) pin enable s/disables the on-chip debugging functions. When the EMLE pin is driven high, the TDO, TDI, TCK, TMS, and TRST pins are used specific for the E10A. In this case, other pin functions are disabled.

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1.3.3 Pin Functions

Table 1.2 Pin Functions Pin Number Classifi- cation Abbreviation H8SX/1527 H8SX/1525 I/O Description Power supply V CC 22, 54, 68 22, 54, 68 Input Power supply pins. Connect to the system power supply. V CL 41 41 Input Connect to VSS via a 0.1-uF capacitor (place it close to this pin). V SS 20, 39, 52, 20, 39, 52, Input Ground pins. Connect to the system power supply (0 V). Clock XTAL 69 69 Input EXTAL 70 70 Input Pins for a crystal resonator. External clock can be input to the EXTAL pin. For a connection example, see section 18, Clock Pulse Generator. B φ 53 53 Output Supplies the system clock to external devices. Operating mode control MD1 MD0 Input Pins for setting the operating mode. The signal levels of these pins must not be changed during operation. System control RES 66 66 Input Reset signal input pin. This LSI enters the reset state when this signal goes low. EMLE 72 72 Input Input pin for on-chip emulator enable signal. Normally the signal level should be fixed low.

Rev. 3.00 Mar. 14, 2006 Page 11 of 804 REJ09B0104-0300 Pin Number Classifi- cation Abbreviation H8SX/1527 H8SX/1525 I/O Description Interrupts NMI 67 67 Input Non-maskable interrupt request signal. When this pin is not in use, this signal must be fixed high. IRQ14 IRQ13 IRQ12 IRQ11-A/IRQ11-B IRQ10-A/IRQ10-B IRQ9-A/IRQ9-B IRQ8-A/IRQ8-B IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 Input Maskable interrupt request signal. TRST 62 62 Input Debugging interface TMS 63 63 Input Interface pins for debugging by the on-chip emulator. TDO 8 8 Output TDI 64 64 Input TCK 65 65 Input TCLKA TCLKB TCLKC TCLKD Input Input pins for the external clocks. TIOCA0 TIOCB0 TIOCC0 TIOCD0 58, 59 60, 61 I/O Signals for TGRA_0 to TGRD_0. These are used for the input capture inputs/output compare outputs/PWM outputs. 16-bit timer pulse unit (TPU) (unit 0)* TIOCA1 TIOCB1 62, 63 I/O Signals for TGRA_1 and TGRB_1. These are used for the input capture inputs/output compare outputs/PWM outputs.

Rev. 3.00 Mar. 14, 2006 Page 12 of 804 REJ09B0104-0300 Pin Number Classifi- cation Abbreviation H8SX/1527 H8SX/1525 I/O Description TIOCA2 TIOCB2 64, 65 I/O Signals for TGRA_2 and TGRB_2. These are used for the input capture inputs/output compare outputs/PWM outputs. 16-bit timer pulse unit (TPU) (unit 0)* TIOCA3 TIOCB3 TIOCC3 TIOCD3 48, 49 50, 51 I/O Signals for TGRA_3 toTGRD_3. These are used for the input capture inputs/output compare outputs/PWM outputs. TCLKE TCLKF TCLKG TCLKH Input Input pins for the external clocks. 16-bit timer pulse unit (TPU) (unit 1) TIOCA6 TIOCB6 TIOCC6 TIOCD6 12, 13 14, 15 12, 13 14, 15 I/O Signals for TGRA_6 toTGRD_6. These are used for the input capture inputs/output compare outputs/PWM outputs. TIOCA7 TIOCB7 16, 17 16, 17 I/O Signals for TGRA_7 toTGRB_7. These are used for the input capture inputs/output compare outputs/PWM outputs. TIOCA8 TIOCB8 18, 19 18, 19 I/O Signals for TGRA_8 toTGRB_8. These are used for the input capture inputs/output compare outputs/PWM outputs. TIOCA9 TIOCB9 TIOCC9 TIOCD9 21, 23 24, 25 21, 23 24, 25 I/O Signals for TGRA_9 toTGRD_9. These are used for the input capture inputs/output compare outputs/PWM outputs. TIOCA10 TIOCB10 26, 27 26, 27 I/O Signals for TGRA_10 toTGRB_10. These are used for the input capture inputs/output compare outputs/PWM outputs. TIOCA11 TIOCB11 28, 29 28, 29 I/O Signals for TGRA_11 toTGRB_11. These are used for the input capture inputs/output compare outputs/PWM outputs.

Rev. 3.00 Mar. 14, 2006 Page 13 of 804 REJ09B0104-0300 Pin Number Classifi- cation Abbreviation H8SX/1527 H8SX/1525 I/O Description Program- mable pulse generator (PPG)* PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Output Output pins for the pulse signals. TxD3 TxD4 Output Output pins for transmit data. RxD3 RxD4 Input Input pins for receive data. Serial communi- cation interface (SCI) SCK3 SCK4 I/O Input/output pins for clock signals. HTxD 9 9 Output Output pin for CAN bus transmission. Controller area network (HCAN) HRxD 10 10 Input Input pin for CAN bus reception. SSO2 SSO1 SSO0 I/O Input/output pins for data. Synchro- nous serial communi- cation unit (SSU) SSI2 SSI1 SSI0 I/O Input/output pins for data. SSCK2 SSCK1 SSCK0 I/O Input/output pins for clock. SCS2 SCS1 SCS0 100 100 I/O Input/output pins for chip select.

Rev. 3.00 Mar. 14, 2006 Page 14 of 804 REJ09B0104-0300 Pin Number Classifi- cation Abbreviation H8SX/1527 H8SX/1525 I/O Description A/D converter AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 Input Input pins for the analog signals for the A/D converter. ADTRG0 ADTRG1 Input Input pins for the ex ternal trigger signal to start A/D conversion. AV CC0 AVCC1 Input Analog power supply and reference power supply pins for the A/D converter. When the A/D converter is not in use, connect to the system power supply. AV SS 86 86 Input Ground pin for the A/D and D/A converters. Connect to the system power supply (0 V).

Rev. 3.00 Mar. 14, 2006 Page 15 of 804 REJ09B0104-0300 Pin Number Classifi- cation Abbreviation H8SX/1527 H8SX/1525 I/O Description I/O port P17 P16 P15 P14 P13 P12 P11 P10 I/O 8-bit input/output pins. P23 P22 P21 P20 I/O 4-bit input/output pins. P37 P36 P35 P34 P33 P32 P31 P30 I/O 8-bit input/output pins. P47 P46 P45 P44 P43 P42 P41 P40 Input 8-bit input pins.

Rev. 3.00 Mar. 14, 2006 Page 16 of 804 REJ09B0104-0300 Pin Number Classifi- cation Abbreviation H8SX/1527 H8SX/1525 I/O Description I/O port P57 P56 P55 P54 P53 P52 P51 P50 Input 8-bit input pins. P66 P65 P64 P63 P62 P61 P60 I/O 7-bit input/output pins. PA7 53 53 Input 1-bit input pin. PA6 PA5 PA4 PA3 PA2 PA1 I/O 6-bit input/output pins. PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 100 100 I/O 8-bit input/output pins.

Rev. 3.00 Mar. 14, 2006 Page 17 of 804 REJ09B0104-0300 Pin Number Classifi- cation Abbreviation H8SX/1527 H8SX/1525 I/O Description I/O port PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 I/O 8-bit input/output pins. PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 I/O 8-bit input/output pins. PK7 PK6 PK5 PK4 PK3 PK2 PK1 PK0 I/O 8-bit input/output pins. Note: * Supported only by the H8SX/1527.

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Rev. 3.00 Mar. 14, 2006 Page 19 of 804 REJ09B0104-0300 Section 2 CPU The H8SX CPU is a high-speed CPU with an internal 32-bit architecture that is upward- compatible with the H8/300, H8/300H, and H8S CPUs. The H8SX CPU has sixteen 16-bit general registers, can handle a 4-Gbyte linear address space, and is ideal for a realtime control system.

2.1 Features

• Upward-compatible with H8/300, H8/300H, and H8S CPUs  Can execute H8/300, H8/300H, and H8S/2000 object programs
• Sixteen 16-bit general registers  Also usable as sixteen 8-bit registers or eight 32-bit registers
• 87 basic instructions  8/16/32-bit arithmetic and logic instructions  Multiply and divide instructions  Bit field transfer instructions  Powerful bit-manipulation instructions  Bit condition branch instructions  Multiply-and-accumulate instruction
• Eleven addressing modes  Register direct [Rn]  Register indirect [@ERn]  Register indirect with displacement [@(d:2,ERn), @(d:16,ERn), or @(d:32,ERn)]  Index register indirect with displacement [@(d:16,RnL.B), @(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L)]  Register indirect with pre-/post-increment or pre-/post-decrement [@+ERn, @ERn +, @− ERn, or @ERn−]  Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]  Immediate [#xx:3, #xx:4, #xx:8, #xx:16, or #xx:32]  Program-counter relative [@(d:8,PC) or @(d:16,PC)]  Program-counter relative with index register [@(RnL.B,PC), @(Rn.W,PC), or @(ERn.L,PC)]  Memory indirect [@@aa:8]  Extended memory indirect [@@vec:7]

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• Two base registers  Vector base register  Short address base register
• 4-Gbyte address space  Program: 4 Gbytes  Data: 4 Gbytes
• High-speed operation  All frequently-used instructions executed in one or two states  8/16/32-bit register-register add/subtract: 1 state  8 × 8-bit register-register multiply: 1 state  16 ÷ 8-bit register-register divide: 10 states  16 × 16-bit register-register multiply: 1 state  32 ÷ 16-bit register-register divide: 18 states  32 × 32-bit register-register multiply: 5 states  32 ÷ 32-bit register-register divide: 18 states
• Four CPU operating modes  Normal mode  Middle mode  Advanced mode  Maximum mode
• Power-down modes  Transition is made by execution of SLEEP instruction  Choice of CPU operating clocks Notes: 1. Advanced mode is only supported as the CPU operating mode of the H8SX/1520 Group. Normal, middle, and maximum modes are not supported. 2. The multiplier and divider are supported by the H8SX/1520 Group. 3. In the H8SX/1520 Group, an instruction is fetched in 32-bit mode.

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2.2 CPU Operating Modes

The H8SX CPU has four operating modes: normal, middle, advanced and maximum modes. For details on mode settings, see section 3.1, Operating Mode Selection. CPU operating modes Normal mode Maximum mode Maximum 64 kbytes for program and data areas combined Maximum 4 Gbytes for program and data areas combined Maximum 16-Mbyte program area and 64-kbyte data area, maximum 16 Mbytes for program and data areas combined Maximum 16-Mbyte program area and 4-Gbyte data area, maximum 4 Gbytes for program and data areas combined Advanced mode Middle mode Figure 2.1 CPU Operating Modes

2.2.1 Normal Mode

The exception vector table and stack have the same structure as in the H8/300 CPU. Note: Normal mode is not supported in this LSI.

• Address Space The maximum address space of 64 kbytes can be accessed.
• Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When the extended register En is used as a 16-bit register it can contain any value, even when the corresponding general register Rn is used as an address register. (If the general register Rn is referenced in the register indirect addressing mode with pre-/post-increment or pre-/post-decrement and a carry or borrow occurs, however, the value in the corresponding extended register En will be affected.)
• Instruction Set All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid.

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2.2.2 Middle Mode

The program area in middle mode is extended to 16 Mbytes as compared with that in normal mode.

• Address Space The maximum address space of 16 Mbytes can be accessed as a total of the program and data areas. For individual areas, up to 16 Mbytes of the program area or up to 64 kbytes of the data area can be allocated.
• Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When the extended register En is used as a 16-bit register (in other than the JMP and JSR instructions), it can contain any value even when the corresponding general register Rn is used as an address register. (If the general register Rn is referenced in the register indirect addressing mode with pre-/post-increment or pre-/post- decrement and a carry or borrow occurs, however, the value in the corresponding extended register En will be affected.)
• Instruction Set All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid and the upper eight bits are sign-extended.
• Exception Vector Table and Memory Indirect Branch Addresses In middle mode, the top area starting at H'000000 is allocated to the exception vector table. One branch address is stored per 32 bits. The upper eight bits are ignored and the lower 24 bits are stored. The structure of the exception vector table is shown in figure 2.4. The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction code specifies a memory location. Execution branches to the contents of the memory location. In middle mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch address. The upper eight bits are reserved and assumed to be H'00.
• Stack Structure The stack structure of PC at a subroutine branch and that of PC and CCR at an exception handling are shown in figure 2.5. The PC contents are saved or restored in 24-bit units.

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2.2.3 Advanced Mode

The data area is extended to 4 Gbytes as compared with that in middle mode.

• Address Space The maximum address space of 4 Gbytes can be linearly accessed. For individual areas, up to 16 Mbytes of the program area and up to 4 Gbytes of the data area can be allocated.
• Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers.
• Instruction Set All instructions and addressing modes can be used.
• Exception Vector Table and Memory Indirect Branch Addresses In advanced mode, the top area starting at H'00000000 is allocated to the exception vector table. One branch address is stored per 32 bits. The upper eight bits are ignored and the lower 24 bits are stored. The structure of the exception vector table is shown in figure 2.4. H'00000000 H'00000003 H'00000004 Exception vector table Reserved Reset exception vector Reserved H'00000007 H'00000001 H'00000002 H'00000005 H'00000006 Figure 2.4 Exception Vector Table (Middle and Advanced Modes) The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction code specifies a memory location. Execution branches to the contents of the memory location. In advanced mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch address. The upper eight bits are reserved and assumed to be H'00.

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• Stack Structure The stack structure of PC at a subroutine branch and that of PC and CCR at an exception handling are shown in figure 2.5. The PC contents are saved or restored in 24-bit units. (a) Subroutine Branch (b) Exception Handling PC (24 bits) EXR*1 Reserved*1,*3 CCR PC (24 bits) SP SP Notes: 1. When EXR is not used it is not stored on the stack. SP when EXR is not used. Ignored on return. (SP ) *2Reserved Figure 2.5 Stack Structure (Middle and Advanced Modes)

2.2.4 Maximum Mode

The program area is extended to 4 Gbytes as compared with that in advanced mode.

• Address Space The maximum address space of 4 Gbytes can be linearly accessed.
• Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers or as the upper 16-bit segments of 32-bit registers or address registers.
• Instruction Set All instructions and addressing modes can be used.
• Exception Vector Table and Memory Indirect Branch Addresses In maximum mode, the top area starting at H'00000000 is allocated to the exception vector table. One branch address is stored per 32 bits. The structure of the exception vector table is shown in figure 2.6.

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2.3 Instruction Fetch

The H8SX CPU has two modes for instruction fetch: 16-bit and 32-bit modes. It is recommended that the mode be set according to the bus width of the memory in which a program is stored. The instruction-fetch mode setting does not affect operation other than instruction fetch such as data accesses. Note: In the H8SX/1520 Group, an instruction is fetched in 32-bit mode.

2.4 Address Space

Figure 2.8 shows a memory map of the H8SX CPU. The address space differs depending on the CPU operating mode. H'0000 H'000000 H'007FFF H'FF8000 H'FFFFFF H'00000000 H'00FFFFFF H'FFFFFFFF H'00000000 H'FFFFFFFF H'FFFF Normal mode Program area Data area (64 kbytes) Program area Data area (4 Gbytes) Program area (16 Mbytes) Program area (16 Mbytes)Data area (64 kbytes) Data area (4 Gbytes) Middle mode Advanced mode Maximum mode Figure 2.8 Memory Map

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2.5 Registers

The H8SX CPU has the internal registers shown in figure 2.9. There are two types of registers: general registers and control registers. The control registers are the 32-bit program counter (PC), 8-bit extended control register (EXR), 8-bit condition-code register (CCR), 32-bit vector base register (VBR), 32-bit short address base register (SBR), and 64-bit multiply-accumulate register (MAC). T ———— I2 I1 I0EXR 76543210 31 0 15 0 7 0 7 0 R0H R1H R2H R3H R4H R5H R6H R7H R0L R1L R2L R3L R4L R5L R6L R7L General Registers and Extended Registers Control Registers [Legend] Stack pointer Program counter Condition-code register Interrupt mask bit User bit or interrupt mask bit Half-carry flag User bit Negative flag SP: PC: CCR: UI: ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) I UI HUNZVCCCR 7654321 0 Sign extension 63 3241 031 MAC PC (Reserved) 31 012 VBR (Reserved) 31 08 SBR MACL Zero flag Overflow flag Carry flag Extended control register Trace bit Interrupt mask bits Vector base register Short address base register Multiply-accumulate register EXR: I2 to I0: VBR: SBR: MAC: MACH Figure 2.9 CPU Registers

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2.5.1 General Registers

The H8SX CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.10 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). When the general registers are used as 16-bit registers, the ER registers are divided into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. When the general registers are used as 8-bit registers, the R registers are divided into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. The general registers ER (ER0 to ER7), R (R0 to R7), and RL (R0L to R7L) are also used as index registers. The size in the operand field determines which register is selected. The usage of each register can be selected independently. Address registers 32-bit registers 32-bit index registers 16-bit registers General registers E (E0 to E7) 8-bit registers General registers RH (R0H to R7H)16-bit registers 16-bit index registers General registers R (R0 to R7) 8-bit registers 8-bit index registers General registers RL (R0L to R7L) General registers ER (ER0 to ER7) Figure 2.10 Usage of General Registers General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine branches. Figure 2.11 shows the stack.

Rev. 3.00 Mar. 14, 2006 Page 30 of 804 REJ09B0104-0300 Free area Stack area SP (ER7) Figure 2.11 Stack

2.5.2 Program Counter (PC)

PC is a 32-bit counter that indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 16 bits (one word) or a multiple of 16 bits, so the least significant bit is ignored. (When the instruction code is fetched, the least significant bit is regarded as 0.

2.5.3 Condition-Code Register (CCR)

CCR is an 8-bit register that contains internal CPU status information, including an interrupt mask (I) and user (UI, U) bits and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branch conditions for conditional branch (Bcc) instructions. Bit Bit Name Initial Value R/W Description

7 I 1 R/W Interrupt Mask Bit

Masks interrupts when set to 1. This bit is set to 1 at the start of an exception handling.

6 UI Undefined R/W User Bit or Interrupt Mask Bit

Can be written to and read from by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask bit.

Rev. 3.00 Mar. 14, 2006 Page 31 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description

5 H Undefined R/W Half-Carry Flag

NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise.

4 U Undefined R/W User Bit

Can be written to and read from by software using the LDC, STC, ANDC, ORC, and XORC instructions.

3 N Undefined R/W Negative Flag

Stores the value of the most significant bit (regarded as sign bit) of data.

2 Z Undefined R/W Zero Flag

Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.

1 V Undefined R/W Overflow Flag

Set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise.

0 C Undefined R/W Carry Flag

Set to 1 when a carry occurs, and cleared to 0 otherwise. A carry has the following types:  Carry from the result of addition  Borrow from the result of subtraction  Carry from the result of shift or rotation The carry flag is also used as a bit accumulator by bit manipulation instructions.

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2.5.4 Extended Control Register (EXR)

EXR is an 8-bit register that contains the trace bit (T) and three interrupt mask bits (I2 to I0). Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC instructions. For details, see the hardware manual for the corresponding product. Bit Bit Name Initial Value R/W Description

7 T 0 R/W Trace Bit

When this bit is set to 1, a trace exception is generated each time an instruction is executed. When this bit is cleared to 0, instructions are executed in sequence. 6 to 3  All 1 R/W Reserved These bits are always read as 1. R/W R/W R/W Interrupt Mask Bits These bits designate the interrupt mask level (0 to 7).

2.5.5 Vector Base Register (VBR)

VBR is a 32-bit register in which the upper 20 bits are valid. The lower 12 bits of this register are read as 0s. This register is a base address of the vector area for exception handlings other than a reset and a CPU address error (extended memory indirect is also out of the target). The initial value is H'00000000. The VBR contents are changed with the LDC and STC instructions.

2.5.6 Short Address Base Register (SBR)

SBR is a 32-bit register in which the upper 24 bits are valid. The lower eight bits are read as 0s. In 8-bit absolute address addressing mode (@aa:8), this register is used as the upper address. The initial value is H'FFFFFF00. The SBR contents are changed with the LDC and STC instructions.

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2.5.7 Multiply-Accumulate Register (MAC)

MAC is a 64-bit register that stores the results of multiply-and-accumulate operations. It consists of two 32-bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the upper bits are sign extended. The MAC contents are changed with the MAC, CLRMAC, LDMAC, and STMAC instructions.

2.5.8 Initial Values of CPU Registers

Reset exception handling loads the start address from the vector table into the PC, clears the T bit in EXR to 0, and sets the I bits in CCR and EXR to 1. The general registers, MAC, and the other bits in CCR are not initialized. In particular, the initial value of the stack pointer (ER7) is undefined. The SP should therefore be initialized using an MOV.L instruction executed immediately after a reset. 2.6 2Data Formats The H8SX CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.

2.6.1 General Register Data Formats

Figure 2.12 shows the data formats in general registers.

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76543210 D o n ’ t care

Don’t care 7 654321 0 4370 Don’t careUpper Lower LSB MSB LSB 1-bit data 1-bit data 4-bit BCD data 4-bit BCD data Byte data Byte data Word data Word data Longword data RnH RnL RnH RnL RnH RnL Rn En ERn MSB Don’t care Upper Lower 437 0 Don’t care 7 0 Don’t care General register ER General register E General register R General register RH [Legend] ERn: En: Rn: RnH: MSB LSB LSB 1516 MSB En Rn MSB LSB RnL: MSB: LSB: General register RL Most significant bit Least significant bit Figure 2.12 General Register Data Formats

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2.6.2 Memory Data Formats

Figure 2.13 shows the data formats in memory. The H8SX CPU can access word data and longword data which are stored at any addresses in memory. When word data begins at an odd address or longword data begins at an address other than a multiple of 4, a bus cycle is divided into two or more accesses. For example, when longword data begins at an odd address, the bus cycle is divided into byte, word, and byte accesses. In this case, these accesses are assumed to be individual bus cycles. However, instructions to be fetched, word and longword data to be accessed during execution of the stack manipulation, branch table manipulation, block transfer instructions, and MAC instruction should be located to even addresses. When SP (ER7) is used as an address register to access the stack, the operand size should be word size or longword size. 76543210 MSB LSB MSB LSB MSB LSB Data Type Data Format 1-bit data Byte data Word data Longword data Address Address L Address L Address 2M Address 2M + 1 Address 2N Address 2N + 1 Address 2N + 2 Address 2N + 3 Figure 2.13 Memory Data Formats

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2.7 Instruction Set

The H8SX CPU has 87 types of instructions. The instructions are classified by function as shown in table 2.1. The arithmetic operation, logic operation, shift, and bit manipulation instructions are called operation instruction in this manual. Table 2.1 Instruction Classification Function Instructions Size Types Data transfer MOV B/W/L 6 MOVFPE * , MOVTPE* B POP, PUSH * W/L LDM, STM L MOVA B/W * Block transfer EEPMOV B 3 MOVMD B/W/L MOVSD B Arithmetic operations ADD, ADDX, SUB, SUBX, CMP, NEG, INC, DEC B/W/L 27 DAA, DAS B ADDS, SUBS L MULXU, DIVXU, MULXS, DIVXS B/W MULU, DIVU, MULS, DIVS W/L MULU/U, MULS/U L EXTU, EXTS W/L TAS B MAC  LDMAC, STMAC  CLRMAC  Logic operations AND, OR, XOR, NOT B/W/L 4 Shift SHLL, SHLR, SHAL, SHAR, RO TL, ROTR, ROTXL, ROTXR B/W/L 8 Bit manipulation BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST B 20 BSET/EQ, BSET/NE, BCLR/EQ, BCLR/NE, BSTZ, BISTZ B BFLD, BFST B

Rev. 3.00 Mar. 14, 2006 Page 37 of 804 REJ09B0104-0300 Function Instructions Size Types Branch BRA/BS, BRA/BC, BSR/BS, BSR/BC B * Bcc * , JMP, BSR, JSR, RTS  RTS/L L * BRA/S  System control TRAPA, RTE, SLEEP, NOP  10 RTE/L L * LDC, STC, ANDC, ORC, XORC B/W/L Total 87 [Legend] B: Byte size W: Word size L: Longword size @−SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP +, ERn and MOV.L ERn, @−SP. 2. Size of data to be added with a displacement 3. Size of data to specify a branch condition 4. Bcc is the generic designation of a conditional branch instruction. 5. Size of general register to be restored 6. Not available in this LSI.

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2.7.1 Instructions and Addressing Modes

Table 2.2 indicates the combinations of instructions and addressing modes that the H8SX CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes (1) Addressing Mode Classifi- cation Instruction Size #xx Rn @ERn @(d,ERn) @(d, RnL.B/ Rn.W/ ERn.L) @ −ERn/ @ERn +/ @ERn −/ @ +ERn @aa:8 @aa:16/ @aa:32  MOV B/W/L S SD SD SD SD SD SD B S/D S/D MOVFPE, MOVTPE* B S/D S/D * POP, PUSH W/L S/D S/D * LDM, STM L S/D S/D * Data transfer MOVA* B/W S S S S S S EEPMOV B SD * MOVMD B/W/L SD * Block transfer MOVSD B SD * ADD, CMP B S D D D D D D D B S D D D D D D B D S S S S S S B SD SD SD SD SD W/L S SD SD SD SD SD SD SUB B S D D D D D D B S D D D D D D B D S S S S S S B SD SD SD SD SD W/L S SD SD SD SD SD SD B/W/L S SD B/W/L S SD Arithmetic operations ADDX, SUBX B/W/L S SD * INC, DEC B/W/L D ADDS, SUBS L D DAA, DAS B D

Rev. 3.00 Mar. 14, 2006 Page 39 of 804 REJ09B0104-0300 Addressing Mode Classifi- cation Instruction Size #xx Rn @ERn @(d,ERn) @(d, RnL.B/ Rn.W/ ERn.L) @ −ERn/ @ERn +/ @ERn −/ @ +ERn @aa:8 @aa:16/ @aa:32  MULXU, DIVXU B/W S: 4 SD Arithmetic operations MULU, DIVU W/L S:4 SD MULXS, DIVXS B/W S:4 SD MULS, DIVS W/L S:4 SD NEG B D D D D D D D W/L D D D D D D EXTU, EXTS W/L D D D D D D TAS B D MAC  CLRMAC  O LDMAC  S STMAC  D B S D D D D D D B D S S S S S S B SD SD SD SD SD AND, OR, XOR W/L S SD SD SD SD SD SD NOT B D D D D D D D Logic operations W/L D D D D D D Shift SHLL, SHLR B D D D D D D D B/W/L * D D D D D D B/W/L * D B D D D D D D D SHAL, SHAR ROTL, ROTR ROTXL, ROTXR W/L D D D D D D Bit manipu- lation BSET, BCLR, BNOT, BTST, BSET/cc, BCLR/cc B D D D D BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST, BSTZ, BISTZ B D D D D

Rev. 3.00 Mar. 14, 2006 Page 40 of 804 REJ09B0104-0300 Addressing Mode Classifi- cation Instruction Size #xx Rn @ERn @(d,ERn) @(d, RnL.B/ Rn.W/ ERn.L) @ −ERn/ @ERn +/ @ERn −/ @ +ERn @aa:8 @aa:16/ @aa:32  BFLD B D S S S Bit manipu- lation BFST B S D D D Branch BRA/BS, BRA/BC* B S S S BSR/BS, BSR/BC* B S S S LDC (CCR, EXR) B/W * S S S S S * S LDC (VBR, SBR) L S STC (CCR, EXR) B/W * D D D D * D System control STC (VBR, SBR) L D ANDC, ORC, XORC B S SLEEP  O NOP  O [Legend] d: d:16 or d:32 S: Can be specified as a source operand. D: Can be specified as a destination operand. SD: Can be specified as either a s ource or destination operand or both. S/D: Can be specified as either a source or destination operand. S:4: 4-bit immediate data can be specified as a source operand. Notes: 1. Only @aa:16 is available. 2. @ERn + as a source operand and @−ERn as a destination operand 3. Specified by ER5 as a source addre ss and ER6 as a destination address for data transfer. 4. Size of data to be added with a displacement 5. Only @ERn − is available 6. When the number of bits to be shifted is 1, 2, 4, 8, or 16 7. When the number of bits to be shifted is specified by 5-bit immediate data or a general register 8. Size of data to specify a branch condition 9. Byte when immediate or r egister direct, otherwise, word 10. Only @ERn + is available 11. Only @ −ERn is available 12. Not available in this LSI.

Rev. 3.00 Mar. 14, 2006 Page 41 of 804 REJ09B0104-0300 Table 2.2 Combinations of Instructions and Addressing Modes (2) Addressing Mode Classifi- cation Instruction Size @ERn @(d,PC) @(RnL. B/Rn.W/ ERn.L, PC) @aa:24 @ aa:32 @@ aa:8 @@vec:7  Branch BRA/BS, BRA/BC  O BSR/BS, BSR/BC  O Bcc  O BRA  O O BRA/S  O * JMP  O O O O O BSR  O JSR  O O O O O RTS, RTS/L  O TRAPA  O System control RTE, RTE/L  O [Legend] d: d:8 or d:16 Note: * Only @(d:8, PC) is available.

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2.7.2 Table of Instructions Classified by Function

Tables 2.4 to 2.11 summarize the instructions in each functional category. The notation used in these tables is defined in table 2.3. Table 2.3 Operation Notation Operation Notation Description Rd General register (destination) * Rs General register (source) * Rn General register * ERn General register (32-bit register) (EAd) Destination operand (EAs) Source operand EXR Extended control register CCR Condition-code register VBR Vector base register SBR Short address base register N N (negative) flag in CCR Z Z (zero) flag in CCR V V (overflow) flag in CCR C C (carry) flag in CCR PC Program counter SP Stack pointer #IMM Immediate data disp Displacement + Addition − Subtraction × Multiplication ÷ Division ∧ Logical AND ∨ Logical OR ⊕ Logical exclusive OR → Move ∼ Logical not (logical complement) Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7).

Rev. 3.00 Mar. 14, 2006 Page 43 of 804 REJ09B0104-0300 Table 2.4 Data Transfer Instructions Instruction Size Function MOV B/W/L #IMM → (EAd), (EAs) → (EAd) Transfers data between immediate data, general registers, and memory. MOVFPE* B (EAs) → Rd MOVTPE* B Rs → (EAs) POP W/L @SP + → Rn Restores the data from the stack to a general register. PUSH W/L Rn → @−SP Saves general register contents on the stack. LDM L @SP + → Rn (register list) Restores the data from the stack to multiple general registers. Two, three, or four general registers which have serial register numbers can be specified. STM L Rn (register list) → @−SP Saves the contents of multiple general registers on the stack. Two, three, or four general registers which have serial register numbers can be specified. MOVA B/W EA → Rd Zero-extends and shifts the contents of a specified general register or memory data and adds them with a displacement. The result is stored in a general register. Note: * Not available in this LSI.

Rev. 3.00 Mar. 14, 2006 Page 44 of 804 REJ09B0104-0300 Table 2.5 Block Transfer Instructions Instruction Size Function EEPMOV.B EEPMOV.W B Transfers a data block. Transfers byte data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of byte data to be transferred is specified by R4 or R4L. MOVMD.B B Transfers a data block. Transfers byte data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of byte data to be transferred is specified by R4. MOVMD.W W Transfers a data block. Transfers word data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of word data to be transferred is specified by R4. MOVMD.L L Transfers a data block. Transfers longword data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of longword data to be transferred is specified by R4. MOVSD.B B Transfers a data block with zero data detection. Transfers byte data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of byte data to be transferred is specified by R4. When zero data is detected during transfer, the transfer stops and execution branches to a specified address.

Rev. 3.00 Mar. 14, 2006 Page 45 of 804 REJ09B0104-0300 Table 2.6 Arithmetic Operation Instructions Instruction Size Function ADD SUB B/W/L (EAd) ± #IMM → (EAd), (EAd) ± (EAs) → (EAd) Performs addition or subtraction on data between immediate data, general registers, and memory. Immediate byte data cannot be subtracted from byte data in a general register. ADDX SUBX B/W/L (EAd) ± #IMM ± C → (EAd), (EAd) ± (EAs) ± C → (EAd) Performs addition or subtraction with carry on data between immediate data, general registers, and memory. The addressing mode which specifies a memory location can be specified as register indirect with post-decrement or register indirect. INC DEC B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) ADDS SUBS L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd Adds or subtracts the value 1, 2, or 4 to or from data in a general register. DAA DAS B Rd (decimal adjust) → Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 2-digit 4-bit BCD data. MULXU B/W Rd × Rs → Rd Performs unsigned multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits, or 16 bits × 16 bits → 32 bits. MULU W/L Rd × Rs → Rd Performs unsigned multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits, or 16 bits × 16 bits → 32 bits. MULU/U L Rd × Rs → Rd Performs unsigned multiplication on data in two general registers (32 bits × 32 bits → upper 32 bits). MULXS B/W Rd × Rs → Rd Performs signed multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits, or 16 bits × 16 bits → 32 bits. MULS W/L Rd × Rs → Rd Performs signed multiplication on data in two general registers: either 16 bits × 16 bits → 16 bits, or 32 bits × 32 bits → 32 bits. MULS/U L Rd × Rs → Rd Performs signed multiplication on data in two general registers (32 bits × 32 bits → upper 32 bits).

Rev. 3.00 Mar. 14, 2006 Page 46 of 804 REJ09B0104-0300 Instruction Size Function DIVXU B/W Rd ÷ Rs → Rd Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder, or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. DIVU W/L Rd ÷ Rs → Rd Performs unsigned division on data in two general registers: either 16 bits ÷ 16 bits → 16-bit quotient, or 32 bits ÷ 32 bits → 32-bit quotient. DIVXS B/W Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder, or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. DIVS W/L Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 16 bits → 16-bit quotient, or 32 bits ÷ 32 bits → 32-bit quotient. CMP B/W/L (EAd) − #IMM, (EAd) − (EAs) Compares data between immediate data, general registers, and memory and stores the result in CCR. NEG B/W/L 0 − (EAd) → (EAd) Takes the two's complement (arithmetic complement) of data in a general register or the contents of a memory location. EXTU W/L (EAd) (zero extension) → (EAd) Performs zero-extension on the lower 8 or 16 bits of data in a general register or memory to word or longword size. The lower 8 bits to word or longword, or the lower 16 bits to longword can be zero-extended. EXTS W/L (EAd) (sign extension) → (EAd) Performs sign-extension on the lower 8 or 16 bits of data in a general register or memory to word or longword size. The lower 8 bits to word or longword, or the lower 16 bits to longword can be sign-extended. TAS B @ERd − 0, 1 → (<bit 7> of @EAd) Tests memory contents, and sets the most significant bit (bit 7) to 1. MAC  (EAs) × (EAd) + MAC → MAC Performs signed multiplication on memory contents and adds the result to MAC. CLRMAC  0 → MAC Clears MAC to zero.

Rev. 3.00 Mar. 14, 2006 Page 47 of 804 REJ09B0104-0300 Instruction Size Function LDMAC  Rs → MAC Loads data from a general register to MAC. STMAC  MAC → Rd Stores data from MAC to a general register. Table 2.7 Logic Operation Instructions Instruction Size Function AND B/W/L (EAd) ∧ #IMM → (EAd), (EAd) ∧ (EAs) → (EAd) Performs a logical AND operation on data between immediate data, general registers, and memory. OR B/W/L (EAd) ∨ #IMM → (EAd), (EAd) ∨ (EAs) → (EAd) Performs a logical OR operation on data between immediate data, general registers, and memory. XOR B/W/L (EAd) ⊕ #IMM → (EAd), (EAd) ⊕ (EAs) → (EAd) Performs a logical exclusive OR operation on data between immediate data, general registers, and memory. NOT B/W/L ∼ (EAd) → (EAd) Takes the one's complement of the contents of a general register or a memory location.

Rev. 3.00 Mar. 14, 2006 Page 48 of 804 REJ09B0104-0300 Table 2.8 Shift Operation Instructions Instruction Size Function SHLL SHLR B/W/L (EAd) (shift) → (EAd) Performs a logical shift on the contents of a general register or a memory location. The contents of a general register or a memory location can be shifted by 1, 2, 4, 8, or 16 bits. The contents of a general register can be shifted by any bits. In this case, the number of bits is specified by 5-bit immediate data or the lower 5 bits of the contents of a general register. SHAL SHAR B/W/L (EAd) (shift) → (EAd) Performs an arithmetic shift on the contents of a general register or a memory location. 1-bit or 2-bit shift is possible. ROTL ROTR B/W/L (EAd) (rotate) → (EAd) Rotates the contents of a general register or a memory location. 1-bit or 2-bit rotation is possible. ROTXL ROTXR B/W/L (EAd) (rotate) → (EAd) Rotates the contents of a general register or a memory location with the carry bit. 1-bit or 2-bit rotation is possible.

Rev. 3.00 Mar. 14, 2006 Page 49 of 804 REJ09B0104-0300 Table 2.9 Bit Manipulation Instructions Instruction Size Function BSET B 1 → (<bit-No.> of <EAd>) Sets a specified bit in the contents of a general register or a memory location to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BSET/cc B if cc, 1 → (<bit-No.> of <EAd>) If the specified condition is satisfied, this instruction sets a specified bit in a memory location to 1. The bit number can be specified by 3-bit immediate data, or by the lower three bits of a general register. The Z flag status can be specified as a condition. BCLR B 0 → (<bit-No.> of <EAd>) Clears a specified bit in the contents of a general register or a memory location to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR/cc B if cc, 0 → (<bit-No.> of <EAd>) If the specified condition is satisfied, this instruction clears a specified bit in a memory location to 0. The bit number can be specified by 3-bit immediate data, or by the lower three bits of a general register. The Z flag status can be specified as a condition. BNOT B ∼ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>) Inverts a specified bit in the contents of a general register or a memory location. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BTST B ∼ (<bit-No.> of <EAd>) → Z Tests a specified bit in the contents of a general register or a memory location and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BAND B C ∧ (<bit-No.> of <EAd>) → C ANDs the carry flag with a specified bit in the contents of a general register or a memory location and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BIAND B C ∧ [∼ (<bit-No.> of <EAd>)] → C ANDs the carry flag with the inverse of a specified bit in the contents of a general register or a memory location and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BOR B C ∨ (<bit-No.> of <EAd>) → C ORs the carry flag with a specified bit in the contents of a general register or a memory location and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.

Rev. 3.00 Mar. 14, 2006 Page 50 of 804 REJ09B0104-0300 Instruction Size Function BIOR B C ∨ [~ (<bit-No.> of <EAd>)] → C ORs the carry flag with the inverse of a specified bit in the contents of a general register or a memory location and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BXOR B C ⊕ (<bit-No.> of <EAd>) → C Exclusive-ORs the carry flag with a specified bit in the contents of a general register or a memory location and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BIXOR B C ⊕ [~ (<bit-No.> of <EAd>)] → C Exclusive-ORs the carry flag with the inverse of a specified bit in the contents of a general register or a memory location and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BLD B (<bit-No.> of <EAd>) → C Transfers a specified bit in the contents of a general register or a memory location to the carry flag. The bit number is specified by 3-bit immediate data. BILD B ~ (<bit-No.> of <EAd>) → C Transfers the inverse of a specified bit in the contents of a general register or a memory location to the carry flag. The bit number is specified by 3-bit immediate data. BST B C → (<bit-No.> of <EAd>) Transfers the carry flag value to a specified bit in the contents of a general register or a memory location. The bit number is specified by 3-bit immediate data. BSTZ B Z → (<bit-No.> of <EAd>) Transfers the zero flag value to a specified bit in the contents of a memory location. The bit number is specified by 3-bit immediate data. BIST B ∼ C → (<bit-No.> of <EAd>) Transfers the inverse of the carry flag value to a specified bit in the contents of a general register or a memory location. The bit number is specified by 3-bit immediate data.

Rev. 3.00 Mar. 14, 2006 Page 51 of 804 REJ09B0104-0300 Instruction Size Function BISTZ B ∼ Z → (<bit-No.> of <EAd>) Transfers the inverse of the zero flag value to a specified bit in the contents of a memory location. The bit number is specified by 3-bit immediate data. BFLD B (EAs) (bit field) → Rd Transfers a specified bit field in memory location contents to the lower bits of a specified general register. BFST B Rs → (EAd) (bit field) Transfers the lower bits of a specified general register to a specified bit field in memory location contents. Table 2.10 Branch Instructions Instruction Size Function BRA/BS BRA/BC B Tests a specified bit in memory location contents. If the specified condition is satisfied, execution branches to a specified address. BSR/BS BSR/BC B Tests a specified bit in memory location contents. If the specified condition is satisfied, execution branches to a subroutine at a specified address. Bcc  Branches to a specified address if t he specified condition is satisfied. BRA/S  Branches unconditionally to a specif ied address after executing the next instruction. The next instruction should be a 1-word instruction except for the block transfer and branch instructions. JMP  Branches unconditionally to a specified address. BSR  Branches to a subroutine at a specified address. JSR  Branches to a subroutine at a specified address. RTS  Returns from a subroutine. RTS/L  Returns from a subroutine, restori ng data from the stack to multiple general registers.

Rev. 3.00 Mar. 14, 2006 Page 52 of 804 REJ09B0104-0300 Table 2.11 System Control Instructions Instruction Size Function TRAPA  Starts trap-instructi on exception handling. RTE  Returns from an exception-handling routine. RTE/L  Returns from an exception-handling ro utine, restoring data from the stack to multiple general registers. SLEEP  Causes a transition to a power-down state. B/W #IMM → CCR, (EAs) → CCR, #IMM → EXR, (EAs) → EXR Loads immediate data or the contents of a general register or a memory location to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. LDC L Rs → VBR, Rs → SBR Transfers the general register contents to VBR or SBR. B/W CCR → (EAd), EXR → (EAd) Transfers the contents of CCR or EXR to a general register or memory. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. STC L VBR → Rd, SBR → Rd Transfers the contents of VBR or SBR to a general register. ANDC B CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR Logically ANDs the CCR or EXR contents with immediate data. ORC B CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR Logically ORs the CCR or EXR contents with immediate data. XORC B CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR Logically exclusive-ORs the CCR or EXR contents with immediate data. NOP  PC + 2 → PC Only increments the program counter.

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2.7.3 Basic Instruction Formats

The H8SX CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.14 shows examples of instruction formats. op op rn rm NOP, RTS, etc. ADD.B Rn, Rm, etc. MOV.B @(d:16, Rn), Rm, etc. (1) Operation field only (2) Operation field and register fields (3) Operation field, register fields, and effective address extension rn rmop EA (disp) (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc Figure 2.14 Instruction Formats

• Operation Field Indicates the function of the instruction, and specifies the addressing mode and operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields.
• Register Field Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field.
• Effective Address Extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.
• Condition Field Specifies the branch condition of Bcc instructions.

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2.8 Addressing Modes and Effective Address Calculation

The H8SX CPU supports the 11 addressing modes listed in table 2.12. Each instruction uses a subset of these addressing modes. Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.12 Addressing Modes No. Addressing Mode Symbol

1 Register direct Rn

2 Register indirect @ERn

3 Register indirect with displacement @(d:2,ERn)/@(d:16,ERn)/@(d:32,ERn)

4 Index register indirect with displacement @(d:16, RnL.B)/@(d: 16,Rn.W)/@(d:16,ERn.L) @(d:32, RnL.B)/@(d:32,Rn.W)/@(d:32,ERn.L)

5 Register indirect with post-increment @ERn +

Register indirect with pre-decrement @ −ERn Register indirect with pre-increment @ +ERn Register indirect with post-decrement @ERn −

6 Absolute address @aa:8/@aa:16/@aa:24/@aa:32

7 Immediate #xx:3/#xx: 4/#xx:8/#xx:16/#xx:32

8 Program-counter relati ve @(d:8,PC)/@(d:16,PC)

9 Program-counter relative with index regi ster @(RnL.B,PC)/@(Rn.W,PC)/@(ERn.L,PC)

10 Memory indirect @@aa:8

11 Extended memory indirect @@vec:7

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2.8.1 Register Direct—Rn

The operand value is the contents of an 8-, 16-, or 32-bit general register which is specified by the register field in the instruction code. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.

2.8.2 Register Indirect—@ERn

The operand value is the contents of the memory location which is pointed to by the contents of an address register (ERn). ERn is specified by the register field of the instruction code. In advanced mode, if this addressing mode is used in a branch instruction, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00).

2.8.3 Register Indirect with Displacement—@(d:2, ERn), @(d:16, ERn), or

@(d:32, ERn) The operand value is the contents of a memory location which is pointed to by the sum of the contents of an address register (ERn) and a 16- or 32-bit displacement. ERn is specified by the register field of the instruction code. The displacement is included in the instruction code and the 16-bit displacement is sign-extended when added to ERn. This addressing mode has a short format (@(d:2, ERn)). The short format can be used when the displacement is 1, 2, or 3 and the operand is byte data, when the displacement is 2, 4, or 6 and the operand is word data, or when the displacement is 4, 8, or 12 and the operand is longword data.

Rev. 3.00 Mar. 14, 2006 Page 56 of 804 REJ09B0104-0300 2.8.4 Index Register Indirect with Displacement—@(d:16,RnL.B), @(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L) The operand value is the contents of a memory location which is pointed to by the sum of the following operation result and a 16- or 32-bit displacement: a specified bits of the contents of an address register (RnL, Rn, ERn) specified by the register field in the instruction code are zero- extended to 32-bit data and multiplied by 1, 2, or 4. The displacement is included in the instruction code and the 16-bit displacement is sign-extended when added to ERn. If the operand is byte data, ERn is multiplied by 1. If the operand is word or longword data, ERn is multiplied by 2 or 4, respectively. or Post-Decrement—@ERn +, @−ERn, @ +ERn, or @ERn − (1) Register indirect with post-increment—@ERn+ The operand value is the contents of a memory location which is pointed to by the contents of an address register (ERn). ERn is specified by the register field of the instruction code. After the memory location is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access. (2) Register indirect with pre-decrement—@−ERn The operand value is the contents of a memory location which is pointed to by the following operation result: the value 1, 2, or 4 is subtracted from the contents of an address register (ERn). ERn is specified by the register field of the instruction code. After that, the operand value is stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. (3) Register indirect with pre-increment—@+ERn The operand value is the contents of a memory location which is pointed to by the following operation result: the value 1, 2, or 4 is added to the contents of an address register (ERn). ERn is specified by the register field of the instruction code. After that, the operand value is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access.

Rev. 3.00 Mar. 14, 2006 Page 57 of 804 REJ09B0104-0300 (4) Register indirect with post-decrement—@ERn− The operand value is the contents of a memory location which is pointed to by the contents of an address register (ERn). ERn is specified by the register field of the instruction code. After the memory location is accessed, 1, 2, or 4 is subtracted from the address register contents and the remainder is stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. If the contents of a general register which is also used as an address register is written to memory using this addressing mode, data to be written is the contents of the general register after calculating an effective address. If the same general register is specified in an instruction and two effective addresses are calculated, the contents of the general register after the first calculation of an effective address is used in the second calculation of an effective address. Example 1: MOV.W R0, @ER0+ When ER0 before execution is H'12345678, H'567A is written at H'12345678. Example 2: MOV.B @ER0+, @ER0+ When ER0 before execution is H'00001000, H'00001000 is read and the contents is written at H'00001001. After execution, ER0 is H'00001002.

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2.8.6 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32

The operand value is the contents of a memory location which is pointed to by an absolute address included in the instruction code. There are 8-bit (@aa:8), 16-bit (@aa:16), 24-bit (@aa:24), and 32-bit (@aa:32) absolute addresses. To access the data area, the absolute address of 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) is used. For an 8-bit absolute address, the upper 24 bits are specified by SBR. For a 16- bit absolute address, the upper 16 bits are sign-extended. A 32-bit absolute address can access the entire address space. To access the program area, the absolute address of 24 bits (@aa:24) or 32 bits (@aa:32) is used. For a 24-bit absolute address, the upper 8 bits are all assumed to be 0 (H'00). Table 2.13 shows the accessible absolute address ranges. Table 2.13 Absolute Address Access Ranges Absolute Address Normal Mode Middle Mode Advanced Mode Maximum Mode Data area 8 bits (@aa:8) A consecutive 256-byte area (the upper address is set in SBR) 16 bits (@aa:16) H'0000 to H'FFFF H'00000000 to H'00007FFF, H'FFFF8000 to H'FFFFFFFF 32 bits (@aa:32) H'000000 to H'007FFF, H'FF8000 to H'FFFFFF H'00000000 to H'FFFFFFFF Program area 24 bits (@aa:24) H'000000 to H'FFFFFF H'00000000 to H'00FFFFFF 32 bits (@aa:32) H'00000000 to H'00FFFFFF H'00000000 to H'FFFFFFFF

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2.8.7 Immediate—#xx

The operand value is 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) data included in the instruction code. This addressing mode has short formats in which 3- or 4-bit immediate data can be used. When the size of immediate data is less than that of the destination operand value (byte, word, or longword) the immediate data is zero-extended. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, for specifying a bit number. The BFLD and BFST instructions contain 8-bit immediate data in the instruction code, for specifying a bit field. The TRAPA instruction contains 2-bit immediate data in the instruction code, for specifying a vector address.

2.8.8 Program-Counter Relative—@(d:8, PC) or @(d:16, PC):

This mode is used in the Bcc and BSR instructions. The operand value is a 32-bit branch address, which is the sum of an 8- or 16-bit displacement in the instruction code and the 32-bit address of the PC contents. The 8-bit or 16-bit displacement is sign-extended to 32 bits when added to the PC contents. The PC contents to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is −126 to +128 bytes (−63 to +64 words) or −32766 to +32768 bytes (−16383 to +16384 words) from the branch instruction. The resulting value should be an even number. In advanced mode, only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00).

2.8.9 Program-Counter Relative with Index Register—

@(RnL.B, PC), @(Rn.W, PC), or @(ERn.L, PC) This mode is used in the Bcc and BSR instructions. The operand value is a 32-bit branch address, which is the sum of the following operation result and the 32-bit address of the PC contents: the contents of an address register specified by the register field in the instruction code (RnL, Rn, or ERn) is zero-extended and multiplied by 2. The PC contents to which the displacement is added is the address of the first byte of the next instruction. In advanced mode, only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00).

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2.8.10 Memory Indirect—@@aa:8

This mode can be used by the JMP and JSR instructions. The operand value is a branch address, which is the contents of a memory location pointed to by an 8-bit absolute address in the instruction code. The upper bits of an 8-bit absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in other modes). In normal mode, the memory location is pointed to by word-size data and the branch address is 16 bits long. In other modes, the memory location is pointed to by longword-size data. In middle or advanced mode, the first byte of the longword-size data is assumed to be all 0 (H'00). Note that the top part of the address range is also used as the exception handling vector area. A vector address of an exception handling other than a reset or a CPU address error can be changed by VBR. Figure 2.15 shows an example of specification of a branch address using this addressing mode. (a) Normal Mode (b) Advanced Mode Branch addressSpecified by @aa:8 Specified by @aa:8 Reserved Branch address Figure 2.15 Branch Address Specification in Memory Indirect Mode

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2.8.11 Extended Memo ry Indirect—@@vec:7

This mode can be used by the JMP and JSR instructions. The operand value is a branch address, which is the contents of a memory location pointed to by the following operation result: the sum of 7-bit data in the instruction code and the value of H'80 is multiplied by 2 or 4. The address range to store a branch address is H'0100 to H'01FF in normal mode and H'000200 to H'0003FF in other modes. In assembler notation, an address to store a branch address is specified. In normal mode, the memory location is pointed to by word-size data and the branch address is 16 bits long. In other modes, the memory location is pointed to by longword-size data. In middle or advanced mode, the first byte of the longword-size data is assumed to be all 0 (H'00).

2.8.12 Effective Address Calculation

Tables 2.14 and 2.15 show how effective addresses are calculated in each addressing mode. The lower bits of the effective address are valid and the upper bits are ignored (zero extended or sign extended) according to the CPU operating mode. The valid bits in middle mode are as follows:

• The lower 16 bits of the effective address are valid and the upper 16 bits are sign-extended for the transfer and operation instructions.
• The lower 24 bits of the effective address are valid and the upper eight bits are zero-extended for the branch instructions.

Rev. 3.00 Mar. 14, 2006 Page 62 of 804 REJ09B0104-0300 Table 2.14 Effective Address Calculation for Transfer and Operation Instructions 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 15 31 15 31 0 31 0 31 15 0 31 0 1, 2, or 4 31 0 31 0 1, 2, or 4 1, 2, or 4 31 0 7 No. op op rm rn IMM op r op disp disp disp disp aa aa aa disp r op disp r op aa op disp r op disp r op aa op r op r op aa 31 0 1, 2, or 4 Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Immediate Register direct Register indirect Register indirect with 16-bit displacement Register indirect with 32-bit displacement Index register indirect with 16-bit displacement Index register indirect with 32-bit displacement Register indirect with post-increment or post-decrement Register indirect with pre-increment or pre-decrement 8-bit absolute address 16-bit absolute address 32-bit absolute address Sign extension SBR General register contents General register contents Zero extension Contents of general register (RL, R, or ER) Zero extension Contents of general register (RL, R, or ER) Sign extension General register contents General register contents General register contents Sign extension

Rev. 3.00 Mar. 14, 2006 Page 63 of 804 REJ09B0104-0300 Table 2.15 Effective Address Calculation for Branch Instructions 31 0 31 0 31 0 31 0 31 23 0 31 0 31 0 2 or 4 vec op disp op disp op r op aa op r op aa aa aa op aa aa 31 0 31 0 op vec 31 0 31 0 31 0 31 0 31 7 0 disp 31 0 31 0 31 15 0 disp 31 0 31 0 No. Register indirect Program-counter relative with 8-bit displacement 24-bit absolute address 32-bit absolute address Zero extension Contents of general register (RL, R, or ER) General register contents Sign extension Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) PC contents Sign extension PC contents Zero extension Zero extension Memory contents Memory contents Zero extension PC contents Program-counter relative with 16-bit displacement Program-counter relative with index register Memory indirect Extended memory indirect

2.8.13 MOVA Instruction

The MOVA instruction stores the effective address in a general register. 1. Firstly, data is obtained by the addressing mode shown in item 2of table 2.14. 2. Next, the effective address is calculated using the obtained data as the index by the addressing mode shown in item 5 of table 2.14. The obtained data is used instead of the general register. The result is stored in a general register. For details, see H8SX Family Software Manual.

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2.9 Processing States

The H8SX CPU has five main processing states: the reset state, exception-handling state, program execution state, bus-released state, and program stop state. Figure 2.16 indicates the state transitions.

• Reset state In this state the CPU and internal peripheral modules are all initialized and stopped. When the RES input goes low, all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. The reset state can also be entered by a watchdog timer overflow. For details, refer to section 4, Exception Handling.
• Exception-handling state The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to activation of an exception source, such as, a reset, trace, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception handling vector table and branches to that address. For further details, refer to section 4, Exception Handling.
• Program execution state In this state the CPU executes program instructions in sequence.
• Bus-released state In this state, the bus has been released in response to a bus request from the DMA controller (DMAC). While the bus is released, the CPU halts operations.
• Program stop state This is a power-down state in which the CPU stops operating. The program stop state occurs when a SLEEP instruction is executed or the CPU enters software standby mode. For details, refer to section 19, Power-Down Modes.

Rev. 3.00 Mar. 14, 2006 Page 65 of 804 REJ09B0104-0300 A transition to the reset state occurs whenever the RES signal goes low. A transition can also be made to the reset state when the watchdog timer overflows. Note: * Reset state*Exception-handling state Request for exception handling End of exception handling Program execution state Bus-released state Bus request End of bus request Program stop state SLEEP instruction Interrupt request Bus request End of bus request RES = high RES = low Figure 2.16 State Transitions

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Section 3 MCU Operating Modes Rev. 3.00 Mar. 14, 2006 Page 67 of 804 REJ09B0104-0300 Section 3 MCU Operating Modes

3.1 Operating Mode Selection

This LSI has three operating modes (modes 1 to 3). The operating mode is selected by the setting of mode pins (MD1 and MD0). Table 3.1 lists MCU operating mode settings. In this LSI, advanced mode for the CPU operating mode and 16-Mbyte address space are available. LSI initiation mode can be selected from boot mode and user boot mode for programming/erasing the flash memory and single chip initiation mode. Table 3.1 MCU Operating Mode Settings MCU Operating Mode MD1 MD0 CPU Operating Mode Address Space Description On-Chip ROM 1 0 1 Advanced 16 Mbytes User boot mode Enabled 2 1 0 Boot mode Enabled 3 1 1 Single chip initiation mode Enabled In mode 1 and mode 2, which are user boot mode and boot mode, the flash memory can be programmed and erased. For details on user boot mode and boot mode, see section 17, Flash Memory (0.18-µm F-ZTAT Version). In mode 3, this LSI operates in single chip mode.

Section 3 MCU Operating Modes Rev. 3.00 Mar. 14, 2006 Page 68 of 804 REJ09B0104-0300

3.2 Register Descriptions

The following registers are related to the operating mode setting.

• Mode control register (MDCR)
• System control register (SYSCR)

3.2.1 Mode Control Register (MDCR)

MDCR indicates the current operating mode. When MDCR is read, the states of signals input on pins MD1 and MD0 are latched. The latch is released by a reset. Bit Bit Name Initial Value R/W Note: * Determined by pins MD1 and MD0. R R R R MDS3 Undefined* R MDS2 Undefined* R MDS1 Undefined* R MDS0 Undefined* R Bit Bit Name Initial Value R/W R R R R Undefined* R Undefined* R Undefined* R Undefined* R Bit Bit Name Initial Value R/W Descriptions R R R R Reserved These are read-only bits and cannot be modified. MDS3 MDS2 MDS1 MDS0 Undefined* Undefined* Undefined* Undefined* R R R R Mode Select 3 to 0 These bits indicate the operating mode selected by the mode pins (MD1 and MD0) (see table 3.2).

Section 3 MCU Operating Modes Rev. 3.00 Mar. 14, 2006 Page 69 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Descriptions Undefined* Undefined* Undefined* Undefined* R R R R R R R R Reserved These are read-only bits and cannot be modified. Note: * Determined by pins MD1 and MD0. Table 3.2 Settings of Bits MSD3 to MSD0 MDCR MCU Operating Mode MD1 MD0 MDS3 MDS2 MDS1 MDS0 1 0 1 1 1 0 1 2 1 0 1 1 0 0 3 1 1 0 1 0 0

3.2.2 System Control Register (SYSCR)

SYSCR controls MAC saturation operation and enables/disables the on-chip RAM and the flash memory control registers. Bit Bit Name Initial Value R/W R R MACS R/W R R/W R/W R/W RAME R/W Bit Bit Name Initial Value R/W FLSHE R/W R/W R/W R/W R/W R/W R/W R/W

Section 3 MCU Operating Modes Rev. 3.00 Mar. 14, 2006 Page 70 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Descriptions 15, 14  All 1 R Reserved These are read-only bits and cannot be modified.

13 MACS 0 R/W MAC Saturation Operation Control

Selects either saturation operation or non-saturation operation for the MAC instruction. 0: MAC instruction is non-saturation operation 1: MAC instruction is saturation operation 12  1 R Reserved This is a read-only bit and cannot be modified. 11  0 R/W Reserved This bit is always read as 0. The write value should always be 0. 10  1 R/W Reserved This bit is always read as 1. The write value should always be 1. 9  0 R/W Reserved This bit is always read as 0. The write value should always be 0.

8 RAME 1 R/W RAM Enable

Enables or disables the on-chip RAM. This bit is initialized when the reset state is released. Do not write 0 during access to the on-chip RAM. 0: On-chip RAM disabled 1: On-chip RAM enabled

7 FLSHE 0 R/W Flash Memory Control Register Enable

Controls accesses to the flash memory control registers. Setting this bit to 1 enables to read from and write to the flash memory control registers. Clearing this bit to 0 disables the flash memory control registers. At this time, the contents of the flash memory control registers are retained. The write value should be 0 when the LSI is not the flash memory version. 0: Disables the flash memory control registers 1: Enables the flash memory control registers 6 to 2  All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. 1, 0  All 1 R/W Reserved This bit is always read as 1. The write value should always be 1.

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3.3 Operating Mode Descriptions

3.3.1 Mode 1

Mode 1 is the user boot mode for the flash memory. The operations are the same as that in mode 3 other than programming/erasing the flash memory.

3.3.2 Mode 2

Mode 2 is the boot mode for the flash memory. The operations are the same as that in mode 3 other than programming/erasing the flash memory.

3.3.3 Mode 3

Mode 3 is advanced mode in which the address space is 16 Mbytes, and single-chip mode with the on-chip ROM enabled.

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3.4 Address Map

3.4.1 Address Map (Advanced Mode)

Figure 3.1 shows the address map. Mode 1 to mode 3 Single chip initiation mode (advanced mode) On-chip RAM (12 kbytes) On-chip ROM (256 kbytes) Reserved Reserved Reserved On-chip I/O register On-chip I/O register H'000000 H'040000 H'FFC000 H'FF9000 H'FFEA00 H'FFFF00 H'FFFF20 H'FFFFFF Figure 3.1 Address Map (Advanced Mode)

Section 4 Exception Handling Rev. 3.00 Mar. 14, 2006 Page 73 of 804 REJ09B0104-0300 Section 4 Exception Handling

4.1 Exception Handling Types and Priority

As table 4.1 indicates, exception handling is caused by a reset, a trace, an address error, an interrupt, a trap instruction, and illegal instructions (general illegal instruction and slot illegal instruction). Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Exception sources, the stack structure, and operation of the CPU vary depending on the interrupt control mode. For details on the interrupt control mode, see section 5, Interrupt Controller. Table 4.1 Exception Types and Priority Priority Exception Type E xception Handling Start Timing High Reset Exception handling starts at the timing of level change from low to high on the RES pin, or when the watchdog timer overflows. The CPU enters the reset state when the RES pin is low. Illegal instruction Exception hand ling starts when an undefined code is executed. Trace * Exception handling starts a fter execution of the current instruction or exception handling, if the trace (T) bit in EXR is set to 1. Address error After an address error occurs, the exception handling starts on completion of the current instruction execution. Interrupt Exception handling starts after execution of the current instruction or exception handling, if an interrupt request has occurred.* Low Trap instruction* Exception handling starts by execution of a trap instruction (TRAPA). Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not executed after execution of an RTE instruction. 2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. 3. Trap instruction exception handling requests are accepted at all times in the program execution state.

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4.2 Exception Sources and Exception Handling Vector Table

Different vector table address offsets are assigned to different exception sources. The vector table addresses are calculated from the contents of the vector base register (VBR) and vector table address offset of the vector number. The start address of the exception service routine is fetched from the exception handling vector table indicated by this vector table address. Table 4.2 shows the correspondence between the exception sources and vector table address offsets. Table 4.3 shows the calculation method of exception handling vector table addresses. Since the usable modes differ depending on the product, for details on the available modes, see section 3, MCU Operating Modes. Table 4.2 Exception Handling Vector Table Vector Table Address Offset* Exception Source Vector Number Normal Mode * Advanced, Middle, Maximum Modes Reset 0 H'0000 to H'0001 H'0000 to H'0003 Reserved for system use 1 H'000 2 to H'0003 H' 0004 to H'0007

2 H'0004 to H'0005 H'0008 to H'000B

3 H'0006 to H'0007 H'000C to H'000F

Illegal instruction 4 H'0008 to H'0009 H'0010 to H'0013 Trace 5 H'000A to H'000B H'0014 to H'0017 Reserved for system use 6 H'000C to H'000D H'0018 to H'001B Interrupt (NMI) 7 H'000E to H'000F H'001C to H'001F Trap instruction (#0) 8 H'001 0 to H'0011 H'0020 to H'0023 (#1) 9 H'0012 to H'0013 H'0024 to H'0027 (#2) 10 H'0014 to H'0015 H'0028 to H'002B (#3) 11 H'0016 to H'0017 H'002C to H'002F CPU address error 12 H'0018 to H'0019 H'0030 to H'0033 DMA address error*

13 H'001A to H'001B H'0034 to H'0037

Reserved for system use 14 H'001C to H'001D H'007E to H'007F H'0038 to H'003B H'00FC to H'00FF

Section 4 Exception Handling Rev. 3.00 Mar. 14, 2006 Page 75 of 804 REJ09B0104-0300 Vector Table Address Offset* Exception Source Vector Number Normal Mode * Advanced, Middle, Maximum Modes External interrupt IRQ0 64 H'0080 to H'0081 H'0100 to H'0103 IRQ1 65 H'0082 to H'0083 H'0104 to H'0107 IRQ2 66 H'0084 to H'0085 H'0108 to H'010B IRQ3 67 H'0086 to H'0087 H'010C to H'010F IRQ4 68 H'0088 to H'0089 H'0110 to H'0113 IRQ5 69 H'008A to H'008B H'0114 to H'0117 IRQ6 70 H'008C to H'008D H'0118 to H'011B IRQ7 71 H'008E to H'008F H'011C to H'011F IRQ8 72 H'0090 to H'0091 H'0120 to H'0123 IRQ9 73 H'0092 to H'0093 H'0124 to H'0127 IRQ10 74 H'0094 to H'0095 H'0128 to H'012B IRQ11 75 H'0096 to H'0097 H'012C to H'012F IRQ12 76 H'0098 to H'0099 H'0130 to H'0133 IRQ13 77 H'009A to H'009B H'0134 to H'0137 IRQ14 78 H'009C to H'009D H'0138 to H'013B Reserved for system use 79 H'009E to H'009F H'00A0 to H'00A1 H'013C to H'013F H'0140 to H'0143 Internal interrupt* 255 H'00A2 to H'00A3 H'01FE to H'01FF H'0144 to H'0147 H'03FC to H'03FF Notes: 1. Lower 16 bits of the address. 2. Not available in this LSI. 3. A DMA address error is generated within the DMAC. 4. For details on the interrupt vector table, see section 5.5, Interrupt Exception Handling Vector Table.

Section 4 Exception Handling Rev. 3.00 Mar. 14, 2006 Page 76 of 804 REJ09B0104-0300 Table 4.3 Calculation Method of Exception Handling Vector Table Address Exception Source Calculation Method of Vector Table Address Reset, CPU address error Vector table address = (vector table address offset) Other than above Vector table address = VBR + (vector table address offset) [Legend] VBR: Vector base register Vector table address offset: See table 4.2.

4.3 Reset

A reset has priority over any other exception. When the RES pin goes low, all processing halts and this LSI enters the reset state. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms when the power is turned on. When operation is in progress, hold the RES pin low for at least 20 cycles. The chip can also be reset by overflow of the watchdog timer. For details, see section 11, Watchdog Timer (WDT). A reset initializes the internal state of the CPU and the registers of the on-chip peripheral modules. The interrupt control mode is 0 immediately after a reset.

4.3.1 Reset Exception Handling

When the RES pin goes high after being held low for the necessary time, this LSI starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized, VBR is cleared to H'00000000, the T bit is cleared to 0 in EXR, and the I bits are set to 1 in EXR and CCR. 2. The reset exception handling vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figure 4.1 shows an example of the reset sequence.

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4.3.2 Interrupts after Reset

If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx: 32, SP).

4.3.3 On-Chip Peripheral Functions after Reset Release

After the reset state is released, MSTPCRA, MSTPCRB, and MSTPCRC are initialized to H'0FFF, H'FFFF, and H'FF00 respectively, and all modules except the DMAC enter module stop mode. Consequently, on-chip peripheral module registers cannot be read from or written to. Register reading and writing is enabled when module stop mode is canceled. RES High Vector fetch Internal operation First instruction prefetch (1) Reset exception handling vector address (when reset, (1) = H'000000) (2) Start address (contents of reset exception handling vector address) (3) Start address ((3) = (2)) (4) First instruction in the exception handling routine Iφ Internal address bus Internal read signal Internal write signal Internal data bus (1) (2) (4) (3) Figure 4.1 Reset Sequence (On-Chip ROM Enabled Advanced Mode)

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4.4 Traces

Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. Before changing interrupt control modes, the T bit must be cleared to 0. For details on interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is not affected by interrupt masking by CCR. Table 4.4 shows the state of CCR and EXR after execution of trace exception handling. Trace mode is canceled by clearing the T bit in EXR to 0 during the trace exception handling. However, the T bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine by the RTE instruction, trace mode resumes. Trace exception handling is not carried out after execution of the RTE instruction. Interrupts are accepted even within the trace exception handling routine. Table 4.4 Status of CCR and EXR after Trace Exception Handling CCR EXR Interrupt Control Mode I UI I2 to I0 T 0 Trace exception handling cannot be used. 2 1   0 [Legend] 1: Set to 1 0: Cleared to 0 : Retains the previous value.

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4.5 Address Error

4.5.1 Address Error Source

Instruction fetch, stack operation, data read/write, and single-address transfer shown in table 4.5 may cause an address error. Table 4.5 Bus Cycle and Address Error Bus Cycle Type Bus Master Description Address Error Instruction fetch CPU Fetches instructi ons from even addresses No (normal) Fetches instructions from odd addresses Occurs Fetches instructions from areas other than on-chip peripheral module space* No (normal) Fetches instructions from on-chip peripheral module space* Occurs Fetches instructions from external memory space in single-chip mode Occurs Fetches instructions from access reserved area.* Occurs Stack operation CPU Accesses stac k when the stack pointer value is even address No (normal) Accesses stack when the stack pointer value is odd Occurs Data read/write CPU Accesses word dat a from even addresses No (normal) Accesses word data from odd addresses No (normal) Accesses external memory space in single- chip mode Occurs Accesses to reserved area * Occurs Data read/write DMAC Accesses word data from even addresses No (normal) Accesses word data from odd addresses No (normal) Accesses external memory space in single- chip mode Occurs Accesses to reserved area * Occurs

Section 4 Exception Handling Rev. 3.00 Mar. 14, 2006 Page 80 of 804 REJ09B0104-0300 Bus Cycle Type Bus Master Description Address Error Single address transfer DMAC In single address transfer, the device to be accessed with an address is in the external memory space No (normal) In single address transfer, the device to be accessed with an address is not in the external memory space Occurs Notes: 1. For on-chip peripheral module spac e, see section 6, Bus Controller (BSC). 2. For the access reserved area, refer to figure 3.1 in section 3.4, Address Map. An address error will not occur when the reserved area from H'FF8000 to H'FF8FFF is accessed.

4.5.2 Address Error Exception Handling

When an address error occurs, address error exception handling starts after the bus cycle causing the address error ends and current instruction execution completes. The address error exception handling is as follows: 1. The contents of PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. An exception handling vector table address corresponding to the address error is generated, the start address of the exception service routine is loaded from the vector table to PC, and program execution starts from that address. Even though an address error occurs during a transition to an address error exception handling, the address error is not accepted. This prevents an address error from occurring due to stacking for exception handling, thereby preventing infinitive stacking. If the SP contents are not a multiple of 2 when an address error exception handling occurs, the stacked values (PC, CCR, and EXR) are undefined. When an address error occurs, the following is performed to halt the DMAC.

• ERRF bit in DMDR_0 of the DMAC is set to 1
• DTE bits for all the channels of the DMAC are cleared to 0 and the DMAC is forced to halt

Section 4 Exception Handling Rev. 3.00 Mar. 14, 2006 Page 81 of 804 REJ09B0104-0300 Table 4.6 shows the states of CCR and EXR after the address error exception handling. Table 4.6 States of CCR and EXR after Address Error Exception Handling CCR EXR Interrupt Control Mode I UI T I2 to I0 0 1    2 1  0 7 [Legend] 1: Set to 1. 0: Cleared to 0. : Retains the previous value.

4.6 Interrupts

4.6.1 Interrupt Sources

Interrupt sources are NMI, IRQ0 to IRQ14, and on-chip peripheral modules, as shown in table 4.7. Table 4.7 Interrupt Sources Type Source Number of Sources NMI NMI pin (external input) 1 IRQ0 to IRQ14 Pins IRQ0 to IRQ11 (external input) 15 Watchdog timer (WDT) 1 A/D converter 2 On-chip peripheral module 16-bit timer pulse unit (TPU) 52 * /26* DMA controller (DMAC) 8 Serial communications interface (SCI) 8 Synchronous serial communication unit (SSU) 9 Controller area network (HCAN) 4 Notes: 1. The number of interrupts for the H8SX/1527 2. The number of interrupts for the H8SX/1525 Different vector numbers and vector table offsets are assigned to different interrupt sources. For vector number and vector table offset, refer to table 5.2 in section 5.5, Interrupt Exception Handling Vector Table.

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4.6.2 Interrupt Exception Handling

Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to eight priority/mask levels to enable multiple-interrupt control. The source to start interrupt exception handling and the vector address differ depending on the product. For details, refer to section 5, Interrupt Controller. The interrupt exception handling is as follows: 1. The contents of PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. An exception handling vector table address corresponding to the interrupt source is generated, the start address of the exception service routine is loaded from the vector table to PC, and program execution starts from that address.

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4.7 Instruction Exception Handling

There are two types of instructions that cause exception handling: trap instruction and illegal instructions.

4.7.1 Trap Instruction

Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The trap instruction exception handling is as follows: 1. The contents of PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. An exception handling vector table address corresponding to the vector number specified in the TRAPA instruction is generated, the start address of the exception service routine is loaded from the vector table to PC, and program execution starts from that address. A start address is read from the vector table corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.8 shows the state of CCR and EXR after execution of trap instruction exception handling. Table 4.8 Status of CCR and EXR after Trap Instruction Exception Handling CCR EXR Interrupt Control Mode I UI T I2 to I0 0 1    2 1  0  [Legend] 1: Set to 1 0: Cleared to 0 : Retains the previous value.

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4.7.2 Exception Handling by Illegal Instruction

There are two illegal instructions: general illegal instruction and slot illegal instruction. The exception handling by the general illegal instruction starts when an undefined code is decoded. The exception handling by the slot illegal instruction starts when the following instruction which is placed in a delay slot (immediately after a delayed branch instruction) is executed: an instruction which consists of two words or more or which changes the contents of PC. The general illegal and slot illegal instructions are always executable in the program execution state. The exception handling for the general illegal and a slot illegal instructions is as follows: 1. The contents of PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. An exception handling vector table address corresponding to the occurred exception is generated, the start address of the exception service routine is loaded from the vector table to PC, and program execution starts from that address. Table 4.9 shows the state of CCR and EXR after execution of illegal instruction exception handling. Table 4.9 Status of CCR and EXR after Illegal Instruction Exception Handling CCR EXR Interrupt Control Mode I UI T I2 to I0 0 1    2 1  0  [Legend] 1: Set to 1 0: Cleared to 0 : Retains the previous value.

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4.8 Stack Status after Exception Handling

Figure 4.2 shows the stack after completion of exception handling. CCR PC (24 bits) SP EXR Reserved* CCR PC (24 bits) SP Advanced mode Interrupt control mode 0 Interrupt control mode 2 Note: * Ignored on return. Figure 4.2 Stack Status after Exception Handling

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4.9 Usage Note

When performing stack-manipulating access, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by a word transfer instruction or a longword transfer instruction, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers:

• PUSH.W Rn (or MOV.W Rn, @-SP)
• PUSH.L ERn (or MOV.L ERn, @-SP) Use the following instructions to restore registers:
• POP.W Rn (or MOV.W @SP+, Rn)
• POP.L ERn (or MOV.L @SP+, ERn) Performing stack manipulation while SP is set to an odd value leads to an address error. Figure 4.3 shows an example of operation when the SP value is odd. SP CCR : PC : R1L : SP : Condition code register Program counter General register R1L Stack pointer CCR SP SP R1L H'FFFEFA H'FFFEFB H'FFFEFC H'FFFEFD H'FFFEFE H'FFFEFF PC PC TRAPA instruction executed SP set to H'FFFEFF Data saved above SP MOV.B R1L, @-ER7 executed Contents of CCR lost Address [Legend] Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. (Address error occurred) Figure 4.3 Operation when SP Value Is Odd

Section 5 Interrupt Controller Rev. 3.00 Mar. 14, 2006 Page 87 of 804 REJ09B0104-0300 Section 5 Interrupt Controller

5.1 Features

• Two interrupt control modes Any of two interrupt control modes can be set by means of bits INTM1 and INTM0 in the interrupt control register (INTCR).
• Priority can be assigned by the interrupt priority register (IPR) IPR provides for setting interrupt priory. Eight levels can be set for each module for all interrupts except for the interrupt requests listed below. The following six interrupt requests are given priority of 8, therefore they are accepted at all times.  NMI  General illegal instructions  Trace  Trap instructions  CPU address error  DMA address error*
• Independent vector addresses All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine.
• 16 external interrupts NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge detection can be selected for NMI. Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ14 to IRQ0.
• DMAC control DMAC can be activated by means of interrupts.
• CPU priority control function The priority levels can be assigned to the CPU and DMAC. The priority level of the CPU can be automatically assigned on an exception generation. Priority can be given to the CPU interrupt exception handling over that of the DMAC transfer. Note: * A DMA address error is generated within the DMAC.

Section 5 Interrupt Controller Rev. 3.00 Mar. 14, 2006 Page 88 of 804 REJ09B0104-0300 A block diagram of the interrupt controller is shown in figure 5.1. INTCR IPR NMI input IRQ input Internal interrupt sources WOVI to SSTXI2 INTM1, INTM0 NMIEG NMI input unit IRQ input unit Interrupt controller Priority decision unit Source selecter CPU interrupt request CPU vector DMAC activation enable I I2 to I0 CCR EXR CPU DMAC INTCR: CPUPCR: ISCR: IER: Interrupt control register CPU priority control register IRQ sense control register IRQ enable register ISR: SSIER: IPR: IRQ status register Software standby release IRQ enable register Interrupt priority register [Legend] ISCR SSIERIER DMDR CPUPCR DMAC priority control ISR Figure 5.1 Block Diagram of Interrupt Controller

5.2 Input/Output Pins

Table 5.1 shows the pin configuration of the interrupt controller. Table 5.1 Pin Configuration Name I/O Function NMI Input Nonmaskable External Interrupt Rising or falling edge can be selected. IRQ14 to IRQ0 Input Maskable External Interrupts Rising, falling, or both edges, or level sensing, can be selected.

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5.3 Register Descriptions

The interrupt controller has the following registers.

• Interrupt control register (INTCR)
• CPU priority control register (CPUPCR)
• Interrupt priority registers A to G, I, K to O, Q, and R (IPRA to IPRG, IPRI, IPRK to IPRO, IPRQ, and IPRR)
• IRQ enable register (IER)
• IRQ sense control registers H and L (ISCRH, ISCRL)
• IRQ status register (ISR)
• Software standby release IRQ enable register (SSIER)

5.3.1 Interrupt Cont rol Register (INTCR)

INTCR selects the interrupt control mode, and the detected edge for NMI. Bit Bit Name Initial Value R/W R R INTM1 R/W INTM0 R/W NMIEG R/W R R R Bit Bit Name Initial Value R/W Description 7, 6  All 0 R Reserved These are read-only bits and cannot be modified. INTM1 INTM0 R/W R/W Interrupt Control Select Mode 1 and 0 These bits select either of two interrupt control modes for the interrupt controller. 00: Interrupt control mode 0 Interrupts are controlled by I bit in CCR. 01: Setting prohibited. 10: Interrupt control mode 2 Interrupts are controlled by bits I2 to I0 in EXR, and IPR. 11: Setting prohibited.

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3 NMIEG 0 R/W NMI Edge Select

Selects the input edge for the NMI pin. 0: Interrupt request generated at falling edge of NMI input 1: Interrupt request generated at rising edge of NMI input 2 to 0  All 0 R Reserved These are read-only bits and cannot be modified.

5.3.2 CPU Priority Control Register (CPUPCR)

CPUPCR sets whether or not the CPU has priority over the DMAC. The interrupt exception handling by the CPU can be given priority over that of the DMAC transfer. The priority level of the DMAC for each channel is set by the DMAC control register. Note: * When the IPSETE bit is set to 1, the CPU priority is automatically updated, so these bits cannot be modified. CPUPCE R/W R/W R/W R/W IPSETE R/W CPUP0 R/(W)* CPUP2 R/(W)* CPUP1 R/(W)* Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description

7 CPUPCE 0 R/W CPU Priority Control Enable

Controls the CPU priority control function. Setting this bit to 1 enables the CPU priority control over the DMAC. 0: CPU always has the lowest priority 1: CPU priority control enabled 6 to 4  All 0 R/W Reserved This bit is always read as 0. The write value should always be 0.

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3 IPSETE 0 R/W Interrupt Priority Set Enable

Controls the function which automatically assigns the interrupt priority level of the CPU. Setting this bit to 1 automatically sets bits CPUP2 to CPUP0 by the CPU interrupt mask bit (I bit in CCR or bits I2 to I0 in EXR). 0: Bits CPUP2 to CPUP0 are not updated automatically 1: The interrupt mask bit value is reflected in bits CPUP2 to CPUP0 CPUP2 CPUP1 CPUP0 R/(W)* R/(W)* R/(W)* CPU Priority Level 2 to 0 These bits set the CPU priority level. When the CPUPCE is set to 1, the CPU priority control function over the DMAC becomes valid and the priority of CPU processing is assigned in accordance with the settings of bits CPUP2 to CPUP0. 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest) Note: * When the IPSETE bit is set to 1, the CPU priori ty is automatically updated, so these bits cannot be modified.

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5.3.3 Interrupt Priority Registers A to G, I, K to O, Q, and R (IPRA to IPRG, IPRI,

IPRK to IPRO, IPRQ, and IPRR) IPR sets priory (levels 7 to 0) for interrupts other than NMI. Setting a value in the range from B'000 to B'111 in the 3-bit groups of bits 14 to 12, 10 to 8, 6 to 4, and 2 to 0 assigns a priority level to the corresponding interrupt. For the correspondence between the interrupt sources and the IPR settings, see table 5.2. Bit Bit Name Initial Value R/W R IPR14 R/W IPR13 R/W IPR12 R/W R IPR10 R/W IPR9 R/W IPR8 R/W Bit Bit Name Initial Value R/W R IPR6 R/W IPR5 R/W IPR4 R/W R IPR2 R/W IPR1 R/W IPR0 R/W Bit Bit Name Initial Value R/W Description 15  0 R Reserved This is a read-only bit and cannot be modified. IPR14 IPR13 IPR12 R/W R/W R/W Sets the priority level of the corresponding interrupt source. 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest) 11  0 R Reserved This is a read-only bit and cannot be modified.

Section 5 Interrupt Controller Rev. 3.00 Mar. 14, 2006 Page 93 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description IPR10 IPR9 IPR8 R/W R/W R/W Sets the priority level of the corresponding interrupt source. 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest) 7  0 R Reserved This is a read-only bit and cannot be modified. IPR6 IPR5 IPR4 R/W R/W R/W Sets the priority level of the corresponding interrupt source. 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest) 3  0 R Reserved This is a read-only bit and cannot be modified. IPR2 IPR1 IPR0 R/W R/W R/W Sets the priority level of the corresponding interrupt source. 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest)

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5.3.4 IRQ Enable Register (IER)

IER enables or disables interrupt requests IRQ14 to IRQ0. Bit Bit Name Initial Value R/W R/W IRQ14E R/W IRQ13E R/W IRQ12E R/W IRQ11E R/W IRQ10E R/W IRQ9E R/W IRQ8E R/W Bit Bit Name Initial Value R/W IRQ7E R/W IRQ6E R/W IRQ5E R/W IRQ4E R/W IRQ3E R/W IRQ2E R/W IRQ1E R/W IRQ0E R/W Bit Bit Name Initial Value R/W Description 15  0 R/W Reserved This bit is always read as 0. The write value should always be 0.

14 IRQ14E 0 R/W IRQ14 Enable

The IRQ14 interrupt request is enabled when this bit is 1.

13 IRQ13E 0 R/W IRQ13 Enable

The IRQ13 interrupt request is enabled when this bit is 1.

12 IRQ12E 0 R/W IRQ12 Enable

The IRQ12 interrupt request is enabled when this bit is 1.

11 IRQ11E 0 R/W IRQ11 Enable

The IRQ11 interrupt request is enabled when this bit is 1.

10 IRQ10E 0 R/W IRQ10 Enable

The IRQ10 interrupt request is enabled when this bit is 1.

9 IRQ9E 0 R/W IRQ9 Enable

The IRQ9 interrupt request is enabled when this bit is 1.

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8 IRQ8E 0 R/W IRQ8 Enable

The IRQ8 interrupt request is enabled when this bit is 1.

7 IRQ7E 0 R/W IRQ7 Enable

The IRQ7 interrupt request is enabled when this bit is 1.

6 IRQ6E 0 R/W IRQ6 Enable

The IRQ6 interrupt request is enabled when this bit is 1.

5 IRQ5E 0 R/W IRQ5 Enable

The IRQ5 interrupt request is enabled when this bit is 1.

4 IRQ4E 0 R/W IRQ4 Enable

The IRQ4 interrupt request is enabled when this bit is 1.

3 IRQ3E 0 R/W IRQ3 Enable

The IRQ3 interrupt request is enabled when this bit is 1.

2 IRQ2E 0 R/W IRQ2 Enable

The IRQ2 interrupt request is enabled when this bit is 1.

1 IRQ1E 0 R/W IRQ1 Enable

The IRQ1 interrupt request is enabled when this bit is 1.

0 IRQ0E 0 R/W IRQ0 Enable

The IRQ0 interrupt request is enabled when this bit is 1.

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5.3.5 IRQ Sense Control Registers H and L (ISCRH and ISCRL)

ISCRH and ISCRL select the source that generates an interrupt request on pins IRQ14 to IRQ0. Upon changing the setting of ISCR, IRQnF (n = 14 to 0) in ISR is often set to 1 accidentally through an internal operation. In this case, an interrupt exception handling is executed if an IRQn interrupt request is enabled. In order to prevent such an accidental interrupt from occurring, the setting of ISCR should be changed while the IRQn interrupt is disabled, and then the IRQnF in ISR should be cleared to 0.

• ISCRH Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W R/W R/W IRQ14SR R/W IRQ14SF R/W IRQ13SR R/W IRQ13SF R/W IRQ12SR R/W IRQ12SF R/W IRQ11SR R/W IRQ11SF R/W IRQ10SR R/W IRQ10SF R/W IRQ9SR R/W IRQ9SF R/W IRQ8SR R/W IRQ8SF R/W
• ISCRL Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W IRQ7SR R/W IRQ7SF R/W IRQ6SR R/W IRQ6SF R/W IRQ5SR R/W IRQ5SF R/W IRQ4SR R/W IRQ4SF R/W IRQ3SR R/W IRQ3SF R/W IRQ2SR R/W IRQ2SF R/W IRQ1SR R/W IRQ1SF R/W IRQ0SR R/W IRQ0SF R/W

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• ISCRH Bit Bit Name Initial Value R/W Description 15, 14  All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. IRQ14SR IRQ14SF R/W R/W IRQ14 Sense Control Rise IRQ14 Sense Control Fall 00: Interrupt request generated by low level of IRQ14 01: Interrupt request generated at falling edge of IRQ14 10: Interrupt request generated at rising edge of IRQ14 11: Interrupt request generated at both falling and rising edges of IRQ14 IRQ13SR IRQ13SF R/W R/W IRQ13 Sense Control Rise IRQ13 Sense Control Fall 00: Interrupt request generated by low level of IRQ13 01: Interrupt request generated at falling edge of IRQ13 10: Interrupt request generated at rising edge of IRQ13 11: Interrupt request generated at both falling and rising edges of IRQ13 IRQ12SR IRQ12SF R/W R/W IRQ12 Sense Control Rise IRQ12 Sense Control Fall 00: Interrupt request generated by low level of IRQ12 01: Interrupt request generated at falling edge of IRQ12 10: Interrupt request generated at rising edge of IRQ12 11: Interrupt request generated at both falling and rising edges of IRQ12 IRQ11SR IRQ11SF R/W R/W IRQ11 Sense Control Rise IRQ11 Sense Control Fall 00: Interrupt request generated by low level of IRQ11 01: Interrupt request generated at falling edge of IRQ11 10: Interrupt request generated at rising edge of IRQ11 11: Interrupt request generated at both falling and rising edges of IRQ11

Section 5 Interrupt Controller Rev. 3.00 Mar. 14, 2006 Page 98 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description IRQ10SR IRQ10SF R/W R/W IRQ10 Sense Control Rise IRQ10 Sense Control Fall 00: Interrupt request generated by low level of IRQ10 01: Interrupt request generated at falling edge of IRQ10 10: Interrupt request generated at rising edge of IRQ10 11: Interrupt request generated at both falling and rising edges of IRQ10 IRQ9SR IRQ9SF R/W R/W IRQ9 Sense Control Rise IRQ9 Sense Control Fall 00: Interrupt request generated by low level of IRQ9 01: Interrupt request generated at falling edge of IRQ9 10: Interrupt request generated at rising edge of IRQ9 11: Interrupt request generated at both falling and rising edges of IRQ9 IRQ8SR IRQ8SF R/W R/W IRQ8 Sense Control Rise IRQ8 Sense Control Fall 00: Interrupt request generated by low level of IRQ8 01: Interrupt request generated at falling edge of IRQ8 10: Interrupt request generated at rising edge of IRQ8 11: Interrupt request generated at both falling and rising edges of IRQ8

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• ISCRL Bit Bit Name Initial Value R/W Description IRQ7SR IRQ7SF R/W R/W IRQ7 Sense Control Rise IRQ7 Sense Control Fall 00: Interrupt request generated by low level of IRQ7 01: Interrupt request generated at falling edge of IRQ7 10: Interrupt request generated at rising edge of IRQ7 11: Interrupt request generated at both falling and rising edges of IRQ7 IRQ6SR IRQ6SF R/W R/W IRQ6 Sense Control Rise IRQ6 Sense Control Fall 00: Interrupt request generated by low level of IRQ6 01: Interrupt request generated at falling edge of IRQ6 10: Interrupt request generated at rising edge of IRQ6 11: Interrupt request generated at both falling and rising edges of IRQ6 IRQ5SR IRQ5SF R/W R/W IRQ5 Sense Control Rise IRQ5 Sense Control Fall 00: Interrupt request generated by low level of IRQ5 01: Interrupt request generated at falling edge of IRQ5 10: Interrupt request generated at rising edge of IRQ5 11: Interrupt request generated at both falling and rising edges of IRQ5 IRQ4SR IRQ4SF R/W R/W IRQ4 Sense Control Rise IRQ4 Sense Control Fall 00: Interrupt request generated by low level of IRQ4 01: Interrupt request generated at falling edge of IRQ4 10: Interrupt request generated at rising edge of IRQ4 11: Interrupt request generated at both falling and rising edges of IRQ4

Section 5 Interrupt Controller Rev. 3.00 Mar. 14, 2006 Page 100 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description IRQ3SR IRQ3SF R/W R/W IRQ3 Sense Control Rise IRQ3 Sense Control Fall 00: Interrupt request generated by low level of IRQ3 01: Interrupt request generated at falling edge of IRQ3 10: Interrupt request generated at rising edge of IRQ3 11: Interrupt request generated at both falling and rising edges of IRQ3 IRQ2SR IRQ2SF R/W R/W IRQ2 Sense Control Rise IRQ2 Sense Control Fall 00: Interrupt request generated by low level of IRQ2 01: Interrupt request generated at falling edge of IRQ2 10: Interrupt request generated at rising edge of IRQ2 11: Interrupt request generated at both falling and rising edges of IRQ2 IRQ1SR IRQ1SF R/W R/W IRQ1 Sense Control Rise IRQ1 Sense Control Fall 00: Interrupt request generated by low level of IRQ1 01: Interrupt request generated at falling edge of IRQ1 10: Interrupt request generated at rising edge of IRQ1 11: Interrupt request generated at both falling and rising edges of IRQ1 IRQ0SR IRQ0SF R/W R/W IRQ0 Sense Control Rise IRQ0 Sense Control Fall 00: Interrupt request generated by low level of IRQ0 01: Interrupt request generated at falling edge of IRQ0 10: Interrupt request generated at rising edge of IRQ0 11: Interrupt request generated at both falling and rising edges of IRQ0

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5.3.6 IRQ Status Register (ISR)

ISR is an IRQ14 to IRQ0 interrupt request register. Bit Bit Name Initial Value R/W R/(W)* IRQ14F R/(W)* IRQ13F R/(W)* IRQ12F R/(W)* IRQ11F R/(W)* IRQ10F R/(W)* IRQ9F R/(W)* IRQ8F R/(W)* Bit Bit Name Initial Value R/W IRQ7F R/(W)* IRQ6F R/(W)* IRQ5F R/(W)* IRQ4F R/(W)* IRQ3F R/(W)* IRQ2F R/(W)* IRQ1F R/(W)* IRQ0F R/(W)* Note: * Only 0 can be written, to clear the flag. The bit manipulation instructions or memory operation instructions should be used to clear the flag. Bit Bit Name Initial Value R/W Description 15  0 R/(W) * Reserved This bit is always read as 0. The write value should always be 0. IRQ14F IRQ13F IRQ12F IRQ11F IRQ10F IRQ9F IRQ8F IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* [Setting condition]

• When the interrupt selected by ISCR occurs [Clearing conditions]
• Writing 0 after reading IRQnF = 1
• When interrupt exception handling is executed when low-level sensing is selected and IRQn input is high
• When IRQn interrupt exception handling is executed when falling-, rising-, or both-edge sensing is selected Note: * Only 0 can be written, to clear the flag. The bit manipulation instructions or memory operation instructions should be used to clear the flag.

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5.3.7 Software Standby Release IRQ Enable Register (SSIER)

SSIER selects pins used to leave software standby mode from pins IRQ14 to IRQ0. Bit Bit Name Initial Value R/W R/W SSI14 R/W SSI13 R/W SSI12 R/W SSI11 R/W SSI10 R/W SSI9 R/W SSI8 R/W Bit Bit Name Initial Value R/W SSI7 R/W SSI6 R/W SSI5 R/W SSI4 R/W SSI3 R/W SSI2 R/W SSI1 R/W SSI0 R/W Bit Bit Name Initial Value R/W Description 15  0 R/W Reserved This bit is always read as 0. The write value should always be 0. SSI14 SSI13 SSI12 SSI11 SSI10 SSI9 SSI8 SSI7 SSI6 SSI5 SSI4 SSI3 SSI2 SSI1 SSI0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Software Standby Release IRQ Setting These bits select the IRQn pins used to leave software standby mode (n = 14 to 0). 0: IRQn requests are not sampled in software standby mode 1: When an IRQn request occurs in software standby mode, this LSI leaves software standby mode after the oscillation settling time has elapsed

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5.4 Interrupt Sources

5.4.1 External Interrupts

There are sixteen external interrupts: NMI and IRQ14 to IRQ0. These interrupts can be used to leave software standby mode. (1) NMI Interrupts: Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the settings of the CPU interrupt mask bits. The NMIEG bit in INTCR selects whether an interrupt is requested at the rising or falling edge on the NMI pin. When an NMI interrupt is generated, the interrupt controller determines that an error has occurred, and performs the following procedure.

• Sets the ERRF bit in DMDR_0 to 1.
• Clears the DTE bits for all the channels of the DMAC and forcibly halts transfer. (2) IRQn Interrupts: An IRQn interrupt is requested by a signal input on pins IRQ14 to IRQ0. IRQn (n = 14 to 0) have the following features:
• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, on pins IRQn.
• Enabling or disabling of interrupt requests IRQn can be selected by IER.
• The interrupt priority can be set by IPR.
• The status of interrupt requests IRQn is indicated in ISR. ISR flags can be cleared to 0 by software. The bit manipulation instructions or memory operation instructions should be used to clear the flag in ISR. Detection of IRQn interrupts is enabled through the P1ICR, P2ICR, P5ICR, and P6ICR register settings, and does not change regardless of the output setting. However, when a pin is used as an external interrupt input pin, the pin must not be used as an I/O pin for another function by clearing the corresponding DDR bit to 0. A block diagram of interrupts IRQn is shown in figure 5.2.

Section 5 Interrupt Controller Rev. 3.00 Mar. 14, 2006 Page 104 of 804 REJ09B0104-0300 IRQn interrupt request IRQnE IRQnF S R Q Clear signal Edge/level detection circuitInput buffer Corresponding bit in ICR IRQnSF, IRQnSR IRQn input [Legend] n = 14 to 0 Figure 5.2 Block Diagram of Interrupts IRQn When the IRQ sensing control in ISCR is set to a low level of signal IRQn, the level of IRQn should be held low until an interrupt handling starts. Then set the corresponding input signal IRQn to high in the interrupt handling routine and clear the IRQnF to 0. Interrupts may not be executed when the corresponding input signal IRQn is set to high before the interrupt handling begins.

5.4.2 Internal Interrupts

The sources for internal interrupts from on-chip peripheral modules have the following features:

• For each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that enable or disable these interrupts. They can be controlled independently. When the enable bit is set to 1, an interrupt request is issued to the interrupt controller.
• The interrupt priority can be set by means of IPR.
• The DMAC can be activated by a TPU, SCI, HCAN, SSU, or other interrupt request.
• DMAC activation can be controlled by the CPU priority control function over the DMAC.

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5.5 Interrupt Exception Handling Vector Table

Table 5.2 lists interrupt exception handling sources, vector address offsets, and interrupt priority. In the default priority order, a lower vector number corresponds to a higher priority. When interrupt control mode 2 is set, priority levels can be changed by setting the IPR contents. The priority for interrupt sources allocated to the same level in IPR follows the default priority, that is, they are fixed. Table 5.2 Interrupt Sources, Vector Address Offsets, and Interrupt Priority Classification Interrupt Source Vector Number Vector Address Offset* IPR Priority DMAC Activation External pin NMI 7 H'001C  High  IRQ0 64 H'0100 IPRA14 to IPRA12  IRQ1 65 H'0104 IPRA10 to IPRA8  IRQ2 66 H'0108 IPRA6 to IPRA4  IRQ3 67 H'010C IPRA2 to IPRA0  IRQ4 68 H'0110 IPRB14 to IPRB12  IRQ5 69 H'0114 IPRB10 to IPRB8  IRQ6 70 H'0118 IPRB6 to IPRB4  IRQ7 71 H'011C IPRB2 to IPRB0  IRQ8 72 H'0120 IPRC14 to IPRC12  IRQ9 73 H'0124 IPRC10 to IPRC8  IRQ10 74 H'0128 IPRC6 to IPRC4  IRQ11 75 H'012C IPRC2 to IPRC0  IRQ12 76 H'0130 IPRD14 to IPRE12  IRQ13 77 H'0134 IPRD10 to IPRD8  IRQ14 78 H'0138 IPRD6 to IPRD4   Reserved for system use 79 H'013C  

80 H'0140 

WDT WOVI 81 H'0144 IPRE10 to IPRE8   Reserved for system use 82 H'0148  

83 H'014C 

84 H'0150 

85 H'0154 Low 

Section 5 Interrupt Controller Rev. 3.00 Mar. 14, 2006 Page 106 of 804 REJ09B0104-0300 Classification Interrupt Source Vector Number Vector Address Offset* IPR Priority DMAC Activation A/D_0 ADI0 86 H'0158 IPRF10 to IPRF8 High O A/D_1 ADI1 87 H'015C O TPU_0* TGI0A 88 H'0160 IPRF6 to IPRF4 O TGI0B 89 H'0164  TGI0C 90 H'0168  TGI0D 91 H'016C  TCI0V 92 H'0170  TPU_1* TGI1A 93 H'0174 IPRF2 to IPRF0 O TGI1B 94 H'0178  TCI1V 95 H'017C  TCI1U 96 H'0180  TPU_2* TGI2A 97 H'0184 IPRG14 to IPRG12 O TGI2B 98 H'0188  TCI2V 99 H'018C  TCI2U 100 H'0190  TPU_3* TGI3A 101 H'0194 IPRG10 to IPRG8 O TGI3B 102 H'0198  TGI3C 103 H'019C  TGI3D 104 H'01A0  TCI3V 105 H'01A4  TPU_4* TGI4A 106 H'01A8 IPRG6 to IPRG4  TGI4B 107 H'01AC  TCI4V 108 H'01B0  TCI4U 109 H'01B4  TPU_5* TGI5A 110 H'01B8 IPRG2 to IPRG0  TGI5B 111 H'01BC  TCI5V 112 H'01C0  TCI5U 113 H'01C4   Reserved for system use 114 H'01C8 

115 H'01CC 

116 H'01D0 

117 H'01D4 

118 H'01D8 Low 

Section 5 Interrupt Controller Rev. 3.00 Mar. 14, 2006 Page 107 of 804 REJ09B0104-0300 Classification Interrupt Source Vector Number Vector Address Offset* IPR Priority DMAC Activation  Reserved for system use 119 H'01DC High 

120 H'01E0 

121 H'01E4 

122 H'01E8 

123 H'01EC 

124 H'01F0 

125 H'01F4 

126 H'01F8 

127 H'01FC 

DMAC DMTEND0 128 H'0200 IPRI14 to IPRI12  DMTEND1 129 H'0204 IPRI10 to IPRI8  DNTEND2 130 H'0208 IPRI6 to IPRI4  DMTEND3 131 H'020C IPRI2 to IPRI0   Reserved for system use 132 H'0210  

133 H'0214 

134 H'0218 

135 H'021C 

DMAC DMEEND0 136 H'0220 IPRK14 to IPRK12  DMEEND1 137 H'0224  DNEEND2 138 H'0228  DMEEND3 139 H'022C   Reserved for system use 140 H'0230  

141 H'0234 

142 H'0238 

143 H'023C 

144 H'0240 

145 H'0244 

146 H'0248 

147 H'024C 

148 H'0250 

149 H'0254 

150 H'0258 

151 H'025C Low 

Section 5 Interrupt Controller Rev. 3.00 Mar. 14, 2006 Page 108 of 804 REJ09B0104-0300 Classification Interrupt Source Vector Number Vector Address Offset* IPR Priority DMAC Activation  Reserved for system use 152 H'0260  High 

153 H'0264 

154 H'0268 

155 H'026C 

SCI_3 ERI3 156 H'0270 IPRL10 to IPRL8  RXI3 157 H'0274 O TXI3 158 H'0278 O TEI3 159 H'027C  SCI_4 ERI4 160 H'0280 IPRL6 to IPRL4  RXI4 161 H'0284 O TXI4 162 H'0288 O TEI4 163 H'028C  TPU_6 TGI6A 164 H'0290 IPRL2 to IPRL0 O TGI6B 165 H'0294  TGI6C 166 H'0298  TGI6D 167 H'029C  TCI6V 168 H'02A0 IPRM14 to IPRM12  TPU_7 TGI7A 169 H'02A4 IPRM10 to IPRM8 O TGI7B 170 H'02A8  TCI7V 171 H'02AC IPRM6 to IPRM4  TCI7U 172 H'02B0  TPU_8 TGI8A 173 H'02B4 IPRM2 to IPRM0 O TGI8B 174 H'02B8  TCI8V 175 H'02BC IPRN14 to IPRN12  TCI8U 176 H'02C0  TPU_9 TGI9A 177 H'02C4 IPRN10 to IPRN8 O TGI9B 178 H'02C8  TGI9C 179 H'02CC  TGI9D 180 H'02D0  TCI9V 181 H'02D4 IPRN6 to IPRN4 Low 

Section 5 Interrupt Controller Rev. 3.00 Mar. 14, 2006 Page 109 of 804 REJ09B0104-0300 Classification Interrupt Source Vector Number Vector Address Offset* IPR Priority DMAC Activation TPU_10 TGI10A 182 H'02D8 IPRN2 to IPRN0 High O TGI10B 183 H'02DC  Reserved for system use 184 H'02E0  Reserved for system use 185 H'02E4  TCI10V 186 H'02E8 IPRO14 to IPRO12  TCI10U 187 H'02EC  TPU_11 TGI11A 188 H'02F0 IPRO10 to IPRO8 O TGI11B 189 H'02F4  TCI11V 190 H'02F8 IPRO6 to IPRO4  TCI11U 191 H'02FC   Reserved for system use 192 H'0300  

193 H'0304 

194 H'0308 

195 H'030C 

196 H'0310 

197 H'0314 

198 H'0318 

199 H'031C 

200 H'0320 

201 H'0324 

202 H'0328 

203 H'032C 

204 H'0330 

205 H'0334 

206 H'0338 

207 H'033C 

208 H'0340 

209 H'0344 

210 H'0348 

211 H'034C 

212 H'0350 

213 H'0354 Low 

Section 5 Interrupt Controller Rev. 3.00 Mar. 14, 2006 Page 110 of 804 REJ09B0104-0300 Classification Interrupt Source Vector Number Vector Address Offset* IPR Priority DMAC Activation  Reserved for system use 214 H'0358  High 

215 H'035C 

216 H'0360 

217 H'0364 

218 H'0368 

219 H'036C 

HCAN ERS0/OVR0 220 H'0370 IPRQ2 to IPRQ0  RM0 221 H'0374 O RM1 222 H'0378  SLE0 223 H'037C  SSU_0 Reserved for system use 224 H'0380 IPRR14 to IPRR12 

225 H'0384 

226 H'0388 

SSERI0 227 H'038C  SSRXI0 228 H'0390 IPRR10 to IPRR8 O SSTXI0 229 H'0394 O SSU_1 Reserved for system use 230 H'0398  SSERI1 231 H'039C  SSRXI1 232 H'03A0 IPRR6 to IPRR4 O SSTXI1 233 H'03A4 O SSU_2 Reserved for system use 234 H'03A8  SSERI2 235 H'03AC  SSRXI2 236 H'03B0 IPRR2 to IPRR0 O SSTXI2 237 H'03B4 O Reserved for system use 238 H'03B8 

239 H'03BC 

 Reserved for system use 240 H'03C0  

241 H'03C4 

242 H'03C8 

243 H'03CC 

244 H'03D0 

245 H'03D4 Low 

Section 5 Interrupt Controller Rev. 3.00 Mar. 14, 2006 Page 111 of 804 REJ09B0104-0300 Classification Interrupt Source Vector Number Vector Address Offset* IPR Priority DMAC Activation  Reserved for system use 246 H'03D8  High 

247 H'03DC 

248 H'03E0 

249 H'03E4 

250 H'03E8 

251 H'03EC 

252 H'03F0 

253 H'03F4 

254 H'03F8 

255 H'03FC Low 

Note: 1. Lower 16 bits of the start address in advanced mode. 2. Supported only by the H8SX/1527.

Section 5 Interrupt Controller Rev. 3.00 Mar. 14, 2006 Page 112 of 804 REJ09B0104-0300

5.6 Interrupt Control Modes and Interrupt Operation

The interrupt controller has two interrupt control modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by INTCR. Table 5.3 shows the differences between interrupt control mode 0 and interrupt control mode 2. Table 5.3 Interrupt Control Modes Interrupt Control Mode Priority Setting Register Interrupt Mask Bit Description

0 Default I The priority levels of the interrupt sources are

fixed default settings. The interrupts except for NMI is masked by the I bit.

2 IPR I2 to I0 Eight priority levels can be set for interrupt

sources except for NMI with IPR. 8-level interrupt mask control is performed by bits I2 to I0.

5.6.1 Interrupt Control Mode 0

In interrupt control mode 0, interrupt requests except for NMI are masked by the I bit in CCR of the CPU. Figure 5.3 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt request occurs when the corresponding interrupt enable bit is set to 1, the interrupt request is sent to the interrupt controller. 2. If the I bit in CCR is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending. If the I bit is cleared to 0, an interrupt request is accepted. 3. For multiple interrupt requests, the interrupt controller selects the interrupt request with the highest priority, sends the request to the CPU, and holds other interrupt requests pending. 4. When the CPU accepts the interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC and CCR contents are saved to the stack area during the interrupt exception handling. The PC contents saved on the stack is the address of the first instruction to be executed after returning from the interrupt handling routine. 6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI.

Section 5 Interrupt Controller Rev. 3.00 Mar. 14, 2006 Page 113 of 804 REJ09B0104-0300 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Program execution state Interrupt generated? NMI IRQ0 IRQ1 SSTXI2 I = 0 Save PC and CCR I ← 1 Read vector address Branch to interrupt handling routine Yes No Yes Yes Yes No No No Yes Yes No Pending Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0

Section 5 Interrupt Controller Rev. 3.00 Mar. 14, 2006 Page 114 of 804 REJ09B0104-0300

5.6.2 Interrupt Control Mode 2

In interrupt control mode 2, interrupt requests except for NMI are masked by comparing the interrupt mask level (I2 to I0 bits) in EXR of the CPU and the IPR setting. There are eight levels in mask control. Figure 5.4 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt request occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. For multiple interrupt requests, the interrupt controller selects the interrupt request with the highest priority according to the IPR setting, and holds other interrupt requests pending. If multiple interrupt requests has the same priority, an interrupt request is selected according to the default setting shown in table 5.2. 3. Next, the priority of the selected interrupt request is compared with the interrupt mask level set in EXR. When the interrupt request does not have priority over the mask level set, it is held pending, and only an interrupt request with a priority over the interrupt mask level is accepted. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC, CCR, and EXR contents are saved to the stack area during interrupt exception handling. The PC saved on the stack is the address of the first instruction to be executed after returning from the interrupt handling routine. 6. The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority of the accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H'7. 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table.

Section 5 Interrupt Controller Rev. 3.00 Mar. 14, 2006 Page 115 of 804 REJ09B0104-0300 Yes Program execution state Interrupt generated? NMI Level 6 interrupt? Mask level 5 or below? Level 7 interrupt? Mask level 6 or below? Save PC, CCR, and EXR Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Pending Level 1 interrupt? Mask level 0? Yes Yes No Yes Yes Yes No Yes Yes No No No No No No Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2

Section 5 Interrupt Controller Rev. 3.00 Mar. 14, 2006 Page 116 of 804 REJ09B0104-0300

5.6.3 Interrupt Exception Handling Sequence

Figure 5.5 shows the interrupt exception handling sequence. The example is for the case where interrupt control mode 0 is set in maximum mode, and the program area and stack area are in on- chip memory. (12)(10)(6)(4)(2) Instruction prefetch Interrupt acceptance Interrupt level determination Wait for end of instruction (3) (8) Instruction prefetch in interrupt handling routine Internal operationVector fetchStack Internal operation Interrupt request signal Internal address bus Internal read signal Internal write signal Internal data bus Iφ (1) (2) (4) (3) (5) (7) Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) Instruction code (Not executed.) Instruction prefetch address (Not executed.) SP − 2 SP − 4 Saved PC and saved CCR Vector address Start address of interrupt handling routine (vector address contents) Start address of Interrupt handling routine ((11) = (10)) First instruction of interrupt handling routine (6) (8) (9) (10) (11) (12) Figure 5.5 Interrupt Exception Handling

Section 5 Interrupt Controller Rev. 3.00 Mar. 14, 2006 Page 117 of 804 REJ09B0104-0300

5.6.4 Interrupt Response Times

Table 5.4 shows interrupt response times – the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The symbols for execution states used in table 5.4 are explained in table 5.5. This LSI is capable of fast word transfer to on-chip memory, so allocating the program area in on- chip ROM and the stack area in on-chip RAM enables high-speed processing. Table 5.4 Interrupt Response Times Normal Mode * Advanced Mode Maximum Mode Execution State Interrupt Control Mode 0 Interrupt Control Mode 2 Interrupt Control Mode 0 Interrupt Control Mode 2 Interrupt Control Mode 0 Interrupt Control Mode 2 Interrupt priority decision* Number of states until executing instruction ends* 1 to 19 + 2·SI PC, CCR, EXR stacking S K to 2·SK* 2·S K S K to 2·SK* 2·S K 2·S K 2·S K Vector fetch S h Instruction fetch* 2·S I Internal processing* Total (using on-chip memory) 10 to 31 11 to 31 10 to 31 11 to 31 11 to 31 11 to 31 Notes: 1. Two states for an internal interrupt. 2. In the case of the MULXS or DIVXS instruction 3. Prefetch after interrupt acceptance or for an instruction in the interrupt handling routine. 4. Internal operation after interru pt acceptance or after vector fetch 5. Not available in this LSI. 6. When setting the SP value to 4n, the interrupt response time is S K; when setting to 4n + 2, the interrupt response time is 2·SK.

Section 5 Interrupt Controller Rev. 3.00 Mar. 14, 2006 Page 118 of 804 REJ09B0104-0300 Table 5.5 Number of Execution States in Interrupt Handling Routine Object of Access External Device 8-Bit Bus 16-Bit Bus 32-Bit Bus Symbol On-Chip Memory 2-State Access 3-State Access 2-State Access 3-State Access 2-State Access 3-State Access Vector fetch Sh 1 8 12 + 4m 4 6 + 2m 2 3 + m Instruction fetch SI 1 4 6 + 2m 2 3 + m 2 3 + m Stack manipulation SK 2 8 12 + 4m 4 6 + 2m 2 3 + m [Legend] m: Number of wait cycles in an external device access.

5.6.5 DMAC Activation by Interrupt

The DMAC can be activated by an interrupt. In this case, the following options are available:

• Interrupt request to the CPU
• Activation request to the DMAC
• Combination of the above For details on interrupt requests that can be used to activate the DMAC, see table 5.2 and section 7, DMA Controller (DMAC). Figure 5.6 shows a block diagram of the DMAC and interrupt controller. CPU select circuit Select signal IRQ interrupt Interrupt controller DMAC request clear signal I, I2 to I0 Control signal DMAC select circuit DMRSR0 TO DMRSR3 Priority decision DMAC CPUInterrupt request clear signal Interrupt request DMAC activation request signal CPU interrupt request vector number On-chip peripheral module Interrupt request clear signal Interrupt request Figure 5.6 Block Diagram of DMAC and Interrupt Controller

Section 5 Interrupt Controller Rev. 3.00 Mar. 14, 2006 Page 119 of 804 REJ09B0104-0300 (1) Selection of Interrupt Sources The activation source for each DMAC channel is selected by DMRSR. The selected activation source is input to the DMAC through the select circuit. When transfer by an on-chip module interrupt is enabled (DTF1 = 1, DTF0 = 0, and DTE = 1 in DMDR) and the DTA bit in DMDR is set to 1, the interrupt source selected for the DMAC activation source is controlled by the DMAC and cannot be used as a CPU interrupt source. Interrupt sources that are not controlled by the DMAC can be CPU interrupt sources. When the same interrupt source is set as both the DMAC activation source and CPU interrupt source, the DMAC must be given priority over the CPU. If the IPSETE bit in CPUPCR is set to 1, the priority is determined according to the IPR setting. Therefore, the CPUP setting or the IPR setting corresponding to the interrupt source must be set to lower than or equal to the DMAP settings. If the CPU is given priority, the DMAC may not be activated and the data transfer may be performed. (2) Operation Order If the same interrupt is selected as both the DMAC activation source and CPU interrupt source, the respective operations are performed independently. Table 5.6 lists the selection of interrupt sources and interrupt source clear control by means of the setting of the DTA bit in DMDR of the DMAC. Table 5.6 Interrupt Source Selection and Clear Control Setting DMAC Interrupt Source Selection/Clear Control DTA DMAC CPU

0 O √

1 √ X [Legend] √: The corresponding interrupt is used. The interrupt source is cleared. (The interrupt source flag must be cleared in the CPU interrupt handling routine.) O: The corresponding interrupt is used. The interrupt source is not cleared. X: The corresponding interrupt is not available. (3) Usage Note The interrupt sources of the SCI, A/D converter, HCAN and SSU are cleared according to the setting shown in table 5.6, when the DMAC reads/writes the prescribed register.

Section 5 Interrupt Controller Rev. 3.00 Mar. 14, 2006 Page 120 of 804 REJ09B0104-0300

5.7 CPU Priority Control Function Over DMAC

The interrupt controller has a function to control the priority among the DMAC and the CPU by assigning priority levels to the DMAC and CPU. Since the priority level can automatically be assigned to the CPU on an interrupt occurrence, it is possible to execute the CPU interrupt exception handling prior to the DMAC transfer. The priority level of the CPU is assigned by bits CPUP2 to CPUP0 in CPUPCR. The priority level of the DMAC is assigned to each channel by bits DMAP2 to DMAP0 in the DMA mode control registers 0 to 3 (DMDR_0 to DMDR_3). The priority control function over the DMAC is enabled by setting the CPUPCE bit in CPUPCR to 1. When the CPUPCE bit is 1, the DMAC activation source is controlled according to the respective priority level. The priority level of the DMAC can be specified for each channel. The DMAC activation source is controlled according to the priority level of the CPU and the priority level of the DMAC indicated by bits DMAP2 to DMAP0. If the CPU has priority, the DMAC activation source is held. The DMAC is activated when the condition by which the activation source is held is cancelled (CPUCPCE = 1 and value of bits CPUP2 to CPUP0 is greater than that of bits DMAP2 to DMAP0). When the different priority levels of the DMAC are assigned for the channels, the channel having higher priority continues to transfer while the channel having lower priority than the CPU is held. There are two methods for assigning the priority level to the CPU by the IPSETE bit in CPUPCR. Setting the IPSETE bit to 1 enables a function to automatically assign the value of the interrupt mask bit of the CPU to the CPU priority level. Clearing the IPSETE bit to 0 disables the function to automatically assign the priority level. Therefore, the priority level is assigned directly by software rewriting bits CPUP2 to CPUP0. Even if the IPSETE bit is 1, the priority level of the CPU is software assignable by rewriting the interrupt mask bit of the CPU (I bit in CCR or I2 to I0 bits in EXR). The priority level which is automatically assigned when the IPSETE bit is 1 differs according to the interrupt control mode. In interrupt control mode 0, the I bit in CCR of the CPU is reflected in bit CPUP2. Bits CPUP1 and CPUP0 are fixed 0. In interrupt control mode 2, the values of bits I2 to I0 in EXR of the CPU are reflected in bits CPUP2 to CPUP0. Table 5.7 shows the CPU priority control.

Section 5 Interrupt Controller Rev. 3.00 Mar. 14, 2006 Page 121 of 804 REJ09B0104-0300 Table 5.7 CPU Priority Control Control Status Interrupt Control Mode Interrupt Priority Interrupt Mask Bit IPSETE in CPUPCR CPUP2 to CPUP0 Updating of CPUP2 to CPUP0

0 Default I = any 0 B'111 to B'000 Enabled

I = 0 1 B'000 Disabled I = 1 B'100

2 IPR setting I2 to I0 0 B'111 to B'000 Enabled

1 I2 to I0 Disabled

Table 5.8 shows an setting example of the priority control function over the DMAC and the transfer request control state. Although the DMAC priority levels can be assigned for each channel, table 5.8 gives a single channel description. Thus, transfer for each channel can be performed independently by assigning the different priority levels. Table 5.8 Example of Priority Control Function Setting and Control State Transfer Request Control State Interrupt Control Mode CPUPCE in CPUPCR CPUP2 to CPUP0 DMAP2 to DMAP0 DMAC 0 0 Any Any Enabled

1 B'000 B'000 Enabled

B'100 B'000 Masked B'100 B'011 Masked B'100 B'101 Enabled B'000 B'101 Enabled 2 0 Any Any Enabled B'000 B'101 Enabled B'011 B'101 Enabled B'100 B'101 Enabled B'101 B'101 Enabled B'110 B'101 Masked B'111 B'101 Masked B'101 B'101 Enabled B'101 B'101 Enabled

Section 5 Interrupt Controller Rev. 3.00 Mar. 14, 2006 Page 122 of 804 REJ09B0104-0300

5.8 Usage Notes

5.8.1 Conflict between Interrupt Generation and Disabling

When an interrupt enable bit is cleared to 0 to mask the interrupt, the masking becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request with priority over that interrupt, interrupt exception handling will be executed for the interrupt with priority, and another interrupt will be ignored. The same also applies when an interrupt source flag is cleared to 0. Figure 5.7 shows an example in which the TCIEV bit in TIER of the TPU is cleared to 0. The above conflict will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. Internal address bus Internal write signal φ TCIEV TCFV TCIV interrupt signal TIER_0 write cycle by CPU TCIV exception handling TIER_0 address Figure 5.7 Conflict between Interrupt Generation and Disabling

Section 5 Interrupt Controller Rev. 3.00 Mar. 14, 2006 Page 123 of 804 REJ09B0104-0300

5.8.2 Instructions that Disable Interrupts

Instructions that disable interrupts immediately after execution are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends.

5.8.3 Times when Interrupts are Disabled

There are times when interrupt acceptance is disabled by the interrupt controller. The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask level with an LDC, ANDC, ORC, or XORC instruction, and for a period of writing to the registers of the interrupt controller.

5.8.4 Interrupts during Execution of EEPMOV Instruction

Interrupt operation differs between the EEPMOV.B and the EEPMOV.W instructions. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the transfer is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at the end of the individual transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W MOV.W R4,R4 BNE L1

5.8.5 Interrupts during Execution of MOVMD and MOVS D Instructions

With the MOVMD and MOVSD instructions, if an interrupt request is issued during the transfer, interrupt exception handling starts at the end of the individual transfer cycle. The PC value saved on the stack in this case is the address of the MOVMD or MOVSD instruction. The transfer of the remaining data is resumed after returning from the interrupt handling routine.

Section 5 Interrupt Controller Rev. 3.00 Mar. 14, 2006 Page 124 of 804 REJ09B0104-0300

5.8.6 Interrupt Flags of Peripheral Modules

To clear an interrupt request flag of a peripheral module by the CPU, the flag must be read from after being cleared within the interrupt handling routine even if the peripheral module clock is not generated by dividing the system clock. This makes the request signal synchronized with the system clock.

Section 6 Bus Controller (BSC) Rev. 3.00 Mar. 14, 2006 Page 125 of 804 REJ09B0104-0300 Section 6 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that has a bus arbitration function and controls the operation of the internal bus masters; CPU and DMAC.

6.1 Features

• Write data buffer function Write access to an on-chip peripheral module and access to the on-chip memory can be performed in parallel.
• Bus arbitration function Includes a bus arbiter that arbitrates bus mastership between the CPU and DMAC. Bus mastership can be shared between the CPU and DMAC when a conflict occurs.
• Multi-clock function On-chip peripheral functions can be synchronized with the on-chip peripheral module clock (Pφ). A block diagram of the bus controller is shown in figure 6.1. Internal bus control unit Internal data bus [Legend] Internal bus control signals Internal bus arbiter CPU bus mastership acknowledge signal DMAC bus mastership acknowledge signal CPU bus mastership request signal DMAC bus mastership request signal Control register BCR2 BCR2: Bus control register 2 Figure 6.1 Block Diagram of Bus Controller

Section 6 Bus Controller (BSC) Rev. 3.00 Mar. 14, 2006 Page 126 of 804 REJ09B0104-0300

6.2 Register Descriptions

The bus controller has the following registers.

• Bus control register 2 (BCR2)

6.2.1 Bus Control Register 2 (BCR2)

BCR2 is used for bus arbitration control of the CPU and DMAC, and enabling/disabling of the write data buffer function to the peripheral device. Bit Bit Name Initial Value R/W R R R/W IBCCS R/W R R R/W PWDBE R/W Bit Bit Name Initial Value R/W Description 7, 6  All 0 R Reserved These are read-only bits and cannot be modified. 5  0 R/W Reserved This bit is always read as 0. The write value should always be 0.

4 IBCCS 0 R/W Internal Bus Cycle Control Select

Selects the internal bus arbiter function. 0: Releases the bus mastership according to the priority 1: Executes the bus cycles alternatively when a CPU bus mastership request conflicts with a DMAC bus mastership request 3, 2  All 0 R Reserved These are read-only bits and cannot be modified. 1  1 R/W Reserved This bit is always read as 1. The write value should always be 1.

0 PWDBE 0 R/W Peripheral Module Write Data Buffer Enable

Specifies whether or not to use the write data buffer function for the peripheral module write cycles. 0: Write data buffer function not used 1: Write data buffer function used

Section 6 Bus Controller (BSC) Rev. 3.00 Mar. 14, 2006 Page 127 of 804 REJ09B0104-0300

6.3 Bus Configuration

Figure 6.2 shows the internal bus configuration of this LSI. The internal bus of this LSI consists of the following two types.

• Internal system bus 1 A bus that connects the CPU, DMAC, on-chip ROM, on-chip RAM, and internal peripheral bus.
• Internal peripheral bus A bus that accesses registers in the DMAC, bus controller and interrupt controller and registers of peripheral modules such as SCI and timer. CPU P φ synchronization I φ synchronization Bus controller, interrupt controller, power-down controller Peripheral functions On-chip RAM Internal system bus 1 Internal peripheral bus Write data buffer On-chip ROM DMAC Figure 6.2 Internal Bus Configuration

Section 6 Bus Controller (BSC) Rev. 3.00 Mar. 14, 2006 Page 128 of 804 REJ09B0104-0300

6.4 Multi-Clock Function

The internal functions of this LSI operate synchronously with the system clock (Iφ) or the peripheral module clock (Pφ). Table 6.1 shows the synchronization clock and their corresponding functions. Table 6.1 Synchronization Clocks and Their Corresponding Functions Synchronization Clock Function Name Iφ MCU operating mode Interrupt controller Bus controller CPU DMAC Internal memory Clock pulse generator Power down control Pφ I/O ports TPU PPG WDT SCI HCAN SSU A/D The frequency of each synchronization clock (Iφ and Pφ) is specified by the system clock control register (SCKCR) independently. For further details, see section 18, Clock Pulse Generator.

Section 6 Bus Controller (BSC) Rev. 3.00 Mar. 14, 2006 Page 129 of 804 REJ09B0104-0300

6.5 Internal Bus

6.5.1 Access to Internal Address Space

The internal address spaces of this LSI are the on-chip ROM space, on-chip RAM space and register space for the on-chip peripheral modules. The number of cycles necessary for access differs according the space. Table 6.2 shows the number of access cycles for each on-chip memory space. Table 6.2 Number of Access Cycles for On-Chip Memory Spaces Access Space Access Number of Access Cycles On-chip ROM space Read One I φ cycle On-chip RAM space Read One I φ cycle Write Two I φ cycles In access to the registers for on-chip peripheral modules, the number of access cycles differs according to the register to be accessed. When the dividing ratio of the operating clock of a bus master and that of a peripheral module is 1 : n, synchronization cycles using a clock divided by 0 to n-1 are inserted for register access. Table 6.3 Number of Access Cycles for Registers of On-Chip Peripheral Modules Number of Cycles Module to be Accessed Read Write Write Data Buffer Function DMAC registers 2I φ Disabled MCU operating mode, clock pulse generator, power-down control, interrupt controller, and bus controller registers 2Iφ 3I φ Disabled I/O port PFCR registers and WDT registers 2P φ 3P φ Disabled TPU, PPG, SCI, and A/D registers and I/O port registers other than PFCR 2Pφ Enabled HCAN registers 4P φ Enabled SSU registers 3P φ Enabled

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6.6 Write Data Buffer Function

6.6.1 Write Data Buffer Function for Peripheral Module

This LSI has a write data buffer function for the peripheral module. Using the write data buffer function enables external writes and on-chip memory accesses in parallel. The write data buffer function is made available by setting the PWDBE bit in BCR2 to 1. Figure 6.3 shows an example of the timing when the write data buffer function is used. When this function is used, if a peripheral module write continues for two cycles or longer, and there is an internal access next, only the peripheral module write is executed in the first two cycles. However, from the next cycle onward, on-chip memory accesses and the external address space write rather than waiting until it ends are executed in parallel. Peripheral module write Iφ Internal address bus Internal peripheral address bus Internal peripheral data bus Peripheral module address Pφ On-chip memory read Figure 6.3 Example of Timing when Write Data Buffer Function is Used

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6.7 Bus Arbitration

This LSI has bus arbiters that arbitrate bus mastership operations (bus arbitration). The internal bus arbiter handles the CPU and DMAC accesses. The bus arbiters decide priority at the prescribed timing, and permit use of the bus by means of the bus request acknowledge signal.

6.7.1 Operation

The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master. If there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. The priority of the internal bus arbitration: (High) DMAC > CPU (Low) If the DMAC accesses continue, the CPU can be given priority over the DMAC to execute the bus cycles alternatively between them by setting the IBCCS bit in BCR2.

6.7.2 Bus Transfer Timing

Even if a bus request is received from a bus master with a higher priority over that of the bus master that has taken control of the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific timings at which each bus master can release the bus. (1) CPU The CPU is the lowest-priority bus master, and if a bus request is received from the DMAC, the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of the bus is at the end of the bus cycle. In sleep mode, the bus is transferred synchronously with the clock. Note, however, that the bus cannot be transferred in the following cases.

• The word or longword access is performed in some divisions.
• Stack handling is performed in multiple bus cycles.

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• Transfer data read or write by memory transfer instructions, block transfer instructions, or TAS instruction. (In the block transfer instructions, the bus can be transferred in the write cycle and the following transfer data read cycle.)
• From the target read to write in the bit manipulation instructions or memory operation instructions. (In an instruction that performs no write operation according to the instruction condition, up to a cycle corresponding the write cycle) (2) DMAC The DMAC sends the internal bus arbiter a request for the bus when an activation request is generated. Once the DMAC takes control of the bus, it continues the transfer processing cycles, or releases the bus every transfer cycle. The bus cannot be transferred in the following cases.
• Between a read cycle and the corresponding write cycle in dual address mode While the IBCCS bit in BCR2 is cleared to 0, the bus cannot be transferred in the following cases.
• During 1-block data transfer in block transfer mode
• During burst access transfer The DMAC releases the bus when the consecutive transfer cycles completed except the above cycles.

6.8 Bus Controller Operation in Reset

In a reset, this LSI, including the bus controller, enters the reset state immediately, and any executing bus cycle is aborted.

6.9 Usage Notes

All-Module-Clock-Stop Mode: In this LSI, if the ACSE bit in MSTPCR is set to 1 with the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFFFFFF), a transition is made to the all-module-clock-stop mode. For details, see section 19, Power-Down Modes.

Section 7 DMA Controller (DMAC) Rev. 3.00 Mar. 14, 2006 Page 133 of 804 REJ09B0104-0300 Section 7 DMA Controller (DMAC) This LSI includes a 4-channel DMA controller (DMAC).

7.1 Features

• Maximum of 4-G byte address space can be accessed
• Byte, word, or longword can be set as data transfer unit
• Maximum of 4-G bytes (4,294,967,295 bytes) can be set as total transfer size Supports free-running mode in which total transfer size setting is not needed
• DMAC activation methods are auto-request, on-chip module interrupt, and external request. Auto request: CPU activates (cycle stealing or burst access can be selected) On-chip module interrupt: Interrupt requests from on-chip peripheral modules can be selected as an activation source External request*: Low level or falling edge detection of the DREQ signal can be selected (external request is available for all four channels)
• Dual or single address mode can be selected as address mode Dual address mode: Both source and destination are specified by addresses Single address mode*: Either source or destination is specified by the DREQ signal and the other is specified by address
• Normal, repeat, or block transfer can be selected as transfer mode Normal transfer mode: One byte, one word, or one longword data is transferred at a single transfer request Repeat transfer mode: One byte, one word, or one longword data is transferred at a single transfer request Repeat size of data is transferred an d then a transfer address returns to the transfer start address Up to 65536 transfers (65,536 bytes/words/longwords) can be set as repeat size Block transfer mode: One block data is transferred at a single transfer request Up to 65,536 bytes/words/longwords can be set as block size
• Extended repeat area function which repeats the addressees within a specified area using the transfer address with the fixed upper bits (ring buffer transfer can be performed, as an example) is available One bit (two bytes) to 27 bits (128 Mbytes) for transfer source and destination can be set as extended repeat areas

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• Address update can be selected from fixed address, offset addition, and increment or decrement by 1, 2, or 4 Address update by offset addition enables to transfer data at addresses which are not placed continuously
• Word or longword data can be transferred to an address which is not aligned with the respective boundary Data is divided according to its address (byte or word) when it is transferred
• Two types of interrupts can be requested to the CPU A transfer end interrupt is generated after the number of data specified by the transfer counter is transferred. A transfer escape end interrupt is generated when the remaining total transfer size is less than the transfer data size at a single transfer request, when the repeat size of data transfer is completed, or when the extended repeat area overflows. Note: * An external request and single address mode are not supported by the H8SX/1520 Group.

Section 7 DMA Controller (DMAC) Rev. 3.00 Mar. 14, 2006 Page 135 of 804 REJ09B0104-0300 A block diagram of the DMAC is shown in figure 7.1. External pins DREQn* DACKn* TENDn* Interrupt signals requested to the CPU by each channel Internal activation sources Internal activation source detector Controller DMDR_n DMRSR_n DACR_n DOFR_n Internal address bus Internal data bus DSAR_n DDAR_n DTCR_n DBSR_n Module data bus Address buffer Data buffer Operation unit Operation unit ... [Legend] DSAR_n: DMA source address register DREQn: DMA transfer request DDAR_n: DMA destination address register DACKn: DMA transfer acknowledge DOFR_n: DMA offset register TENDn: DMA transfer end DTCR_n: DMA transfer count register n = 0 to 3 DBSR_n: DMA block size register DMDR_n: DMA mode control register DACR_n: DMA address control register DMRSR_n: DMA module request select register Note: * Auto request activation and single address mode are not supported by the H8SX/1520 Group. Figure 7.1 Block Diagram of DMAC

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7.2 Register Descriptions

The DMAC has the following registers. Channel 0

• DMA source address register_0 (DSAR_0)
• DMA destination address register_0 (DDAR_0)
• DMA offset register_0 (DOFR_0)
• DMA transfer count register_0 (DTCR_0)
• DMA block size register_0 (DBSR_0)
• DMA mode control register_0 (DMDR_0)
• DMA address control register_0 (DACR_0)
• DMA module request select register_0 (DMRSR_0) Channel 1
• DMA source address register_1 (DSAR_1)
• DMA destination address register_1 (DDAR_1)
• DMA offset register_1 (DOFR_1)
• DMA transfer count register_1 (DTCR_1)
• DMA block size register_1 (DBSR_1)
• DMA mode control register_1 (DMDR_1)
• DMA address control register_1 (DACR_1)
• DMA module request select register_1 (DMRSR_1) Channel 2
• DMA source address register_2 (DSAR_2)
• DMA destination address register_2 (DDAR_2)
• DMA offset register_2 (DOFR_2)
• DMA transfer count register_2 (DTCR_2)
• DMA block size register_2 (DBSR_2)
• DMA mode control register_2 (DMDR_2)
• DMA address control register_2 (DACR_2)
• DMA module request select register_2 (DMRSR_2)

Section 7 DMA Controller (DMAC) Rev. 3.00 Mar. 14, 2006 Page 137 of 804 REJ09B0104-0300 Channel 3

• DMA source address register_3 (DSAR_3)
• DMA destination address register_3 (DDAR_3)
• DMA offset register_3 (DOFR_3)
• DMA transfer count register_3 (DTCR_3)
• DMA block size register_3 (DBSR_3)
• DMA mode control register_3 (DMDR_3)
• DMA address control register_3 (DACR_3)
• DMA module request select register_3 (DMRSR_3)

7.2.1 DMA Source Addr ess Register (DSAR)

DSAR is a 32-bit readable/writable register that specifies the transfer source address. DSAR updates the transfer source address every time data is transferred. When DDAR is specified as the destination address (the DIRS bit in DACR is 1) in single address mode, DSAR is ignored. Although DSAR can always be read from by the CPU, it must be read from in longwords and must not be written to while data for the channel is being transferred. R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W

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7.2.2 DMA Destination Address Register (DDAR)

DDAR is a 32-bit readable/writable register that specifies the transfer destination address. DDAR updates the transfer destination address every time data is transferred. When DSAR is specified as the source address (the DIRS bit in DACR is 0) in single address mode, DDAR is ignored. Although DDAR can always be read from by the CPU, it must be read from in longwords and must not be written to while data for the channel is being transferred. R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W

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7.2.3 DMA Offset Register (DOFR)

DOFR is a 32-bit readable/writable register that specifies the offset to update the source and destination addresses. Although different values are specified for individual channels, the same values must be specified for the source and destination sides of a single channel. R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W

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7.2.4 DMA Transfer Count Register (DTCR)

DTCR is a 32-bit readable/writable register that specifies the size of data to be transferred (total transfer size). To transfer 1-byte data in total, set H'00000001 in DTCR. When H'00000000 is set in this register, it means that the total transfer size is not specified and data is transferred with the transfer counter stopped (free running mode). When H'FFFFFFFF is set, the total transfer size is 4 Gbytes (4,294,967,295), which is the maximum size. While data is being transferred, this register indicates the remaining transfer size. The value corresponding to its data access size is subtracted every time data is transferred (byte: −1, word: −2, and longword: −4). Although DTCR can always be read from by the CPU, it must be read from in longwords and must not be written to while data for the channel is being transferred. R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W

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7.2.5 DMA Block Size Register (DBSR)

DBSR specifies the repeat size or block size. DBSR is enabled in repeat transfer mode and block transfer mode and is disabled in normal transfer mode. BKSZH31 R/W BKSZH30 R/W BKSZH29 R/W BKSZH28 R/W BKSZH27 R/W BKSZH24 R/W BKSZH26 R/W BKSZH25 R/W Bit Bit Name Initial Value R/W BKSZH23 R/W BKSZH22 R/W BKSZH21 R/W BKSZH20 R/W BKSZH19 R/W BKSZH16 R/W BKSZH18 R/W BKSZH17 R/W Bit Bit Name Initial Value R/W BKSZ15 R/W BKSZ14 R/W BKSZ13 R/W BKSZ12 R/W BKSZ11 R/W BKSZ8 R/W BKSZ10 R/W BKSZ9 R/W Bit Bit Name Initial Value R/W BKSZ7 R/W BKSZ6 R/W BKSZ5 R/W BKSZ4 R/W BKSZ3 R/W BKSZ0 R/W BKSZ2 R/W BKSZ1 R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description 31 to 16 BKSZH31 to BKSZH16 Undefined R/W Specify the repeat size or block size. When H'0001 is set, the repeat or block size is one byte, one word, or one longword. When H'0000 is set, it means the maximum value (refer to table 7.1). While the DMA is in operation, the setting is fixed. 15 to 0 BKSZ15 to BKSZ0 Undefined R/W Indicate the remaining repeat or block size while the DMA is in operation. The value is decremented by 1 every time data is transferred. When the remaining size becomes 0, the value of the BKSZH bits is loaded. Set the same value as the BKSZH bits.

Section 7 DMA Controller (DMAC) Rev. 3.00 Mar. 14, 2006 Page 142 of 804 REJ09B0104-0300 Table 7.1 Data Access Size, Valid Bits, and Settable Size Mode Data Access Size BKSZH Valid Bits BKSZ Valid Bits Settable Size (Byte) Byte 31 to 16 15 to 0 1 to 65,536 Repeat transfer and block transfer Word 2 to 131,072 Longword 4 to 262,144

7.2.6 DMA Mode Control Register (DMDR)

DMDR controls the DMAC operation.

• DMDR_0 DTE R/W DACKE R/W TENDE R/W R/W DREQS R/W R NRD R/W R Bit Bit Name Initial Value R/W ACT R R R R ERRF R/(W)* DTIF R/(W)* R ESIF R/(W)* Bit Bit Name Initial Value R/W DTSZ1 R/W DTSZ0 R/W MDS1 R/W MDS0 R/W TSEIE R/W DTIE R/W R ESIE R/W Bit Bit Name Initial Value R/W DTF1 R/W DTF0 R/W DTA R/W R R DMAP0 R/W DMAP2 R/W DMAP1 R/W Bit Bit Name Initial Value R/W Note: * Only 0 can be written to this bit after having been read as 1, to clear the flag.

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• DMDR_1 to DMDR_3 DTE R/W DACKE R/W TENDE R/W R/W DREQS R/W R NRD R/W R Bit Bit Name Initial Value R/W ACT R R R R R DTIF R/(W)* R ESIF R/(W)* Bit Bit Name Initial Value R/W DTSZ1 R/W DTSZ0 R/W MDS1 R/W MDS0 R/W TSEIE R/W DTIE R/W R ESIE R/W Bit Bit Name Initial Value R/W DTF1 R/W DTF0 R/W DTA R/W R R DMAP0 R/W DMAP2 R/W DMAP1 R/W Bit Bit Name Initial Value R/W Note: * Only 0 can be written to this bit after having been read as 1, to clear the flag.

Section 7 DMA Controller (DMAC) Rev. 3.00 Mar. 14, 2006 Page 144 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description

31 DTE 0 R/W Data Transfer Enable

Enables/disables a data transfer for the corresponding channel. When this bit is set to 1, it indicates that the DMAC is in operation. Setting this bit to 1 starts a transfer when the auto- request is selected. When the on-chip module interrupt or external request is selected, a transfer request after setting this bit to 1 starts the transfer. While data is being transferred, clearing this bit to 0 stops the transfer. In block transfer mode, if writing 0 to this bit while data is being transferred, this bit is cleared to 0 after the current 1-block size data transfer. If an event which stops (sustains) a transfer occurs externally, this bit is automatically cleared to 0 to stop the transfer. Operating modes and transfer methods must not be changed while this bit is set to 1. 0: Disables a data transfer 1: Enables a data transfer (DMA is in operation) [Clearing conditions]

• When the specified total transfer size of transfers is completed
• When a transfer is stopped by an overflow interrupt by a repeat size end
• When a transfer is stopped by an overflow interrupt by an extended repeat size end
• When a transfer is stopped by a transfer size error interrupt
• When clearing this bit to 0 to stop a transfer In block transfer mode, this bit changes after the current block transfer.
• When an address error or an NMI interrupt is requested
• In the reset state or hardware standby mode

Section 7 DMA Controller (DMAC) Rev. 3.00 Mar. 14, 2006 Page 145 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description

30 DACKE 0 R/W DACK Signal Output Enable

Enables/disables the DACK signal output in single address mode. This bit is ignored in dual address mode. 0: Enables DACK signal output 1: Disables DACK signal output

29 TENDE 0 R/W TEND Signal Output Enable

Enables/disables the TEND signal output. 0: Enables TEND signal output 1: Disables TEND signal output 28  0 R/W Reserved This bit is always read as 0. The write value should always be 0.

27 DREQS 0 R/W DREQ Select

Selects whether a low level or the falling edge of the DREQ signal used in external request mode is detected. When a block transfer is performed in external request mode, clear this bit to 0 to select the low level detection. 0: Low level detection 1: Falling edge detection (the first transfer after a transfer enabled is detected on a low level)

26 NRD 0 R/W Next Request Delay

Selects the accepting timing of the next transfer request. 0: Starts accepting the next transfer request after completion of the current transfer 1: Starts accepting the nex t transfer request one cycle after completion of the current transfer 25, 24  All 0 R Reserved These are read-only bits and cannot be modified.

23 ACT 0 R Active State

Indicates the operating state for the channel. 0: Waiting for a transfer request or a transfer disabled state by clearing the DTE bit to 0 1: Active state 22 to 20  All 0 R Reserved These are read-only bits and cannot be modified.

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19 ERRF 0 R/(W) * System Error Flag

Indicates that an address error or an NMI interrupt has been generated. This bit is available only in DMDR_0. Setting this bit to 1 prohibits writing to the DTE bit for all the channels. This bit is reserved in DMDR_1 to DMDR_3. It is always read as 0 and cannot be modified. 0: An address error or an NMI interrupt has not been generated 1: An address error or an NMI interrupt has been generated [Clearing condition]

• When clearing to 0 after reading ERRF = 1 [Setting condition]
• When an address error or an NMI interrupt has been generated However, when an address error or an NMI interrupt has been generated in module stop mode, this bit is not set. 18  0 R Reserved This is a read-only bit and cannot be modified.

17 ESIF 0 R/(W) * Transfer Escape Interrupt Flag

Indicates that a transfer escape end interrupt has been requested. A transfer escape end means that a transfer is terminated before the transfer counter reaches 0. 0: A transfer escape end interrupt has not been requested 1: A transfer escape end interrupt has been requested [Clearing conditions]

• When setting the DTE bit to 1
• When clearing to 0 before reading ESIF = 1 [Setting conditions]
• When a transfer size error interrupt is requested
• When a repeat size end interrupt is requested
• When a transfer end interrupt by an extended repeat area overflow is requested

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16 DTIF 0 R/(W) * Data Transfer Interrupt Flag

Indicates that a transfer end interrupt by the transfer counter has been requested. 0: A transfer end interrupt by the transfer counter has not been requested 1: A transfer end interrupt by the transfer counter has been requested [Clearing conditions]

• When setting the DTE bit to 1
• When clearing to 0 after reading DTIF = 1 [Setting condition]
• When DTCR reaches 0 and the transfer is completed DTSZ1 DTSZ0 R/W R/W Data Access Size 1 and 0 Select the data access size for a transfer. 00: Byte size (eight bits) 01: Word size (16 bits) 10: Longword size (32 bits) 11: Setting prohibited MDS1 MDS0 R/W R/W Transfer Mode Select 1 and 0 Select the transfer mode. 00: Normal transfer mode 01: Block transfer mode 10: Repeat transfer mode 11: Setting prohibited

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11 TSEIE 0 R/W Transfer Size Error Interrupt Enable

Enables/disables a transfer size error interrupt. When the next transfer is requested while this bit is set to 1 and the contents of the transfer counter is less than the size of data to be transferred at a single transfer request, the DTE bit is cleared to 0. At this time, the ESIF bit is set to 1 to indicate that a transfer size error interrupt has been requested. The sources of a transfer size error are as follows:

• In normal or repeat transfer mode, the total transfer size set in DTCR is less than the data access size
• In block transfer mode, the total transfer size set in DTCR is less than the block size 0: Disables a transfer size error interrupt request 1: Enables a transfer size error interrupt request 10  0 R Reserved This is a read-only bit and cannot be modified.

9 ESIE 0 R/W Transfer Escape Interrupt Enable

Enables/disables a transfer escape end interrupt request. When the ESIF bit is set to 1 with this bit set to 1, a transfer escape end interrupt is requested to the CPU. The transfer end interrupt request is cleared by clearing this bit or the ESIF bit to 0. 0: Disables a transfer escape end interrupt 1: Enables a transfer escape end interrupt

8 DTIE 0 R/W Data Transfer End Interrupt Enable

Enables/disables a transfer end interrupt request by the transfer counter. When the DTIF bit is set to 1 with this bit set to 1, a transfer end interrupt is requested to the CPU. The transfer end interrupt request is cleared by clearing this bit or the DTIF bit to 0. 0: Disables a transfer end interrupt 1: Enables a transfer end interrupt

Section 7 DMA Controller (DMAC) Rev. 3.00 Mar. 14, 2006 Page 149 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description DTF1 DTF0 R/W R/W Data Transfer Factor 1 and 0 Select a DMAC activation source. When the on-chip peripheral module setting is selected, the interrupt source should be selected by DMRSR. When the external request setting is selected, the sampling method should be selected by the DREQS bit. 00: Auto request (cycle stealing) 01: Auto request (burst access) 10: On-chip module interrupt 11: External request

5 DTA 0 R/W Data Transfer Acknowledge

This bit is valid while the DMA transfer is performed by the on-chip module interrupt. This bit decides whether the source flag selected by DMRSR is cleared or not. 0: The source flag is not cleared while the DMA transfer is performed by the on-chip module interrupt. Since the source flag is not cleared by the DMA transfer, it should be cleared by the CPU. 1: The source flag is cleared while the DMA transfer is performed by the on-chip module interrupt. Since the source flag is cleared by the DMA transfer, there is no need to request an interrupt to the CPU. 4, 3  All 0 R Reserved These are read-only bits and cannot be modified.

Section 7 DMA Controller (DMAC) Rev. 3.00 Mar. 14, 2006 Page 150 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description DMAP2 DMAP1 DMAP0 R/W R/W R/W DMA Priority Level 2 to 0 Select the priority level of the DMAC. When the CPU has priority over the DMAC, the DMAC masks a transfer request and waits for the timing when the CPU priority becomes lower than the DMAC priority. The priority levels can be set to the individual channels. This bit is valid when the CPUPCE bit in CPUPCR is set to 1. 000: Priority level 0 (low) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (high) Note: * Only 0 can be written to, to clear the flag.

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7.2.7 DMA Address Control Register (DACR)

DACR specifies the operating mode and transfer method. AMS R/W DIRS R/W R R R ARS0 R/W RPTIE R/W ARS1 R/W Bit Bit Name Initial Value R/W R R SAT1 R/W SAT0 R/W R DAT0 R/W R DAT1 R/W Bit Bit Name Initial Value R/W SARIE R/W R R SARA4 R/W SARA3 R/W SARA0 R/W SARA2 R/W SARA1 R/W Bit Bit Name Initial Value R/W DARIE R/W R R DARA4 R/W DARA3 R/W DARA0 R/W DARA2 R/W DARA1 R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description

31 AMS 0 R/W Address Mode Select

Selects address mode from single or dual address mode. In single address mode, the DACK pin is enabled according to the DACKE bit. 0: Dual address mode 1: Single address mode

30 DIRS 0 R/W Single Address Direction Select

Specifies the data transfer direction in single address mode. This bit s ignored in dual address mode. 0: Specifies DSAR as source address 1: Specifies DDAR as destination address 29 to 27  0 R/W Reserved These are read-only bits and cannot be modified.

Section 7 DMA Controller (DMAC) Rev. 3.00 Mar. 14, 2006 Page 152 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description

26 RPTIE 0 R/W Repeat Size End Interrupt Enable

Enables/disables a repeat size end interrupt request. In repeat transfer mode, when the next transfer is requested after completion of a 1-repeat-size data transfer while this bit is set to 1, the DTE bit in DMDR is cleared to 0. At this time, the ESIF bit in DMDR is set to 1 to indicate that a repeat size end interrupt is requested. Even when the repeat area is not specified (ARS1 = 1 and ARS0 = 0), a repeat size end interrupt after a 1-block data transfer can be requested. In addition, in block transfer mode, when the next transfer is requested after 1-block data transfer while this bit is set to 1, the DTE bit in DMDR is cleared to 0. At this time, the ESIF bit in DMDR is set to 1 to indicate that a repeat size end interrupt is requested. 0: Disables a repeat size end interrupt 1: Enables a repeat size end interrupt ARS1 ARS0 R/W R/W Area Select 1 and 0 Specify the block area or repeat area in block or repeat transfer mode. 00: Specify the block area or repeat area on the source address 01: Specify the block area or repeat area on the destination address 10: Do not specify the block area or repeat area 11: Setting prohibited 23, 22  All 0 R Reserved These are read-only bits and cannot be modified. SAT1 SAT0 R/W R/W Source Address Update Mode 1 and 0 Select the update method of the source address (DSAR). When DSAR is not specified as the transfer source in single address mode, this bit is ignored. 00: Source address is fixed 01: Source address is updated by adding the offset 10: Source address is updated by adding 1, 2, or 4 according to the data access size 11: Source address is updated by subtracting 1, 2, or 4 according to the data access size

Section 7 DMA Controller (DMAC) Rev. 3.00 Mar. 14, 2006 Page 153 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description 19, 18  All 0 R Reserved These are read-only bits and cannot be modified. DAT1 DAT0 R/W R/W Destination Address Update Mode 1 and 0 Select the update method of the destination address (DDAR). When DDAR is not specified as the transfer destination in single address mode, this bit is ignored. 00: Destination address is fixed 01: Destination address is updated by adding the offset 10: Destination address is updated by adding 1, 2, or 4 according to the data access size 11: Destination address is updated by subtracting 1, 2, or 4 according to the data access size

15 SARIE 0 R/W Interrupt Enable for Source Address Extended Area

Enables/disables an interrupt request for an extended area overflow on the source address. When an extended repeat area overflow on the source address occurs while this bit is set to 1, the DTE bit in DMDR is cleared to 0. At this time, the ESIF bit in DMDR is set to 1 to indicate an interrupt by an extended repeat area overflow on the source address is requested. When block transfer mode is used with the extended repeat area function, an interrupt is requested after completion of a 1-block size transfer. When setting the DTE bit in DMDR of the channel for which a transfer has been stopped to 1, the transfer is resumed from the state when the transfer is stopped. When the extended repeat area is not specified, this bit is ignored. 0: Disables an interrupt request for an extended area overflow on the source address 1: Enables an interrupt request for an extended area overflow on the source address 14, 13  All 0 R Reserved These are read-only bits and cannot be modified.

Section 7 DMA Controller (DMAC) Rev. 3.00 Mar. 14, 2006 Page 154 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description SARA4 SARA3 SARA2 SARA1 SARA0 R/W R/W R/W R/W R/W Source Address Extended Repeat Area Specify the extended repeat area on the source address (DSAR). With the extended repeat area, the specified lower address bits are updated and the remaining upper address bits are fixed. The extended repeat area size is specified from four bytes to 128 Mbytes in units of byte and a power of 2. When the lower address is overflowed from the extended repeat area by address update, the address becomes the start address and the end address of the area for address addition and subtraction, respectively. When an overflow in the extended repeat area occurs with the SARIE bit set to 1, an interrupt can be requested. Table 7.2 shows the settings and areas of the extended repeat area.

7 DARIE 0 R/W Destination Address Extended Repeat Area Overflow

Enables/disables an interrupt request for an extended area overflow on the destination address. When an extended repeat area overflow on the destination address occurs while this bit is set to 1, the DTE bit in DMDR is cleared to 0. At this time, the ESIF bit in DMDR is set to 1 to indicate an interrupt by an extended repeat area overflow on the destination address is requested. When block transfer mode is used with the extended repeat area function, an interrupt is requested after completion of a 1-block size transfer. When setting the DTE bit in DMDR of the channel for which the transfer has been stopped to 1, the transfer is resumed from the state when the transfer is stopped. When the extended repeat area is not specified, this bit is ignored. 0: Disables an interrupt request for an extended area overflow on the destination address 1: Enables an interrupt request for an extended area overflow on the destination address 6, 5  All 0 R Reserved These are read-only bits and cannot be modified.

Section 7 DMA Controller (DMAC) Rev. 3.00 Mar. 14, 2006 Page 155 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description DARA4 DARA3 DARA2 DARA1 DARA0 R/W R/W R/W R/W R/W Destination Address Extended Repeat Area Specify the extended repeat area on the destination address (DDAR). With the extended repeat area, the specified lower address bits are updated and the remaining upper address bits are fixed. The extended repeat area size is specified from four bytes to 128 Mbytes in units of byte and a power of 2. When the lower address is overflowed from the extended repeat area by address update, the address becomes the start address and the end address of the area for address addition and subtraction, respectively. When an overflow in the extended repeat area occurs with the DARIE bit set to 1, an interrupt can be requested. Table 7.2 shows the settings and areas of the extended repeat area.

Section 7 DMA Controller (DMAC) Rev. 3.00 Mar. 14, 2006 Page 156 of 804 REJ09B0104-0300 Table 7.2 Settings and Areas of Extended Repeat Area SARA4 to SARA0 or DARA4 to DARA0 Extended Repeat Area

00000 Not specified

00001 2 bytes specified as extended repeat area by the lower 1 bit of the address 00010 4 bytes specified as extended repeat area by the lower 2 bits of the address 00011 8 bytes specified as extended repeat area by the lower 3 bits of the address 00100 16 bytes specified as extended repeat area by the lower 4 bits of the address 00101 32 bytes specified as extended repeat area by the lower 5 bits of the address 00110 64 bytes specified as extended repeat area by the lower 6 bits of the address 00111 128 bytes specified as extended repeat area by the lower 7 bits of the address 01000 256 bytes specified as extended repeat area by the lower 8 bits of the address 01001 512 bytes specified as extended repeat area by the lower 9 bits of the address 01010 1 kbyte specified as extended repeat area by the lower 10 bits of the address 01011 2 kbytes specified as extended repeat area by the lower 11 bits of the address 01100 4 kbytes specified as extended repeat area by the lower 12 bits of the address 01101 8 kbytes specified as extended repeat area by the lower 13 bits of the address 01110 16 kbytes specified as extended repeat area by the lower 14 bits of the address 01111 32 kbytes specified as extended repeat area by the lower 15 bits of the address 10000 64 kbytes specified as extended repeat area by the lower 16 bits of the address 10001 128 kbytes specified as extended repeat ar ea by the lower 17 bits of the address 10010 256 kbytes specified as extended repeat ar ea by the lower 18 bits of the address 10011 512 kbytes specified as extended repeat ar ea by the lower 19 bits of the address 10100 1 Mbyte specified as extended repeat area by the lower 20 bits of the address 10101 2 Mbytes specified as extended repeat area by the lower 21 bits of the address 10110 4 Mbytes specified as extended repeat area by the lower 22 bits of the address 10111 8 Mbytes specified as extended repeat area by the lower 23 bits of the address 11000 16 Mbytes specified as extended repeat ar ea by the lower 24 bits of the address 11001 32 Mbytes specified as extended repeat ar ea by the lower 25 bits of the address 11010 64 Mbytes specified as extended repeat ar ea by the lower 26 bits of the address 11011 128 Mbytes specified as extended repeat area by the lower 27 bits of the address 111×× Setting prohibited [Legend] ×: Don't care

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7.2.8 DMA Module Request Select Register (DMRSR)

DMRSR is an 8-bit readable/writable register that specifies the on-chip module interrupt source. The vector number of the interrupt source is specified in eight bits. However, 0 is regarded as no interrupt source. For the vector numbers of the interrupt sources, refer to table 7.4. R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W

7.3 Transfer Modes

Table 7.3 shows the DMAC transfer modes. The transfer modes can be specified to the individual channels. Table 7.3 Transfer Modes Address Register Address Mode Transfer mode Activati on Source Common Function Source Destina- tion Dual address

• Normal transfer
• Repeat transfer
• Block transfer Repeat or block size = 1 to 65,536 bytes, 1 to 65,536 words, or 1 to 65,536 longwords
• Auto request (activated by CPU)
• On-chip module interrupt
• External request
• Total transfer size: 1 to 4 Gbytes or not specified
• Offset addition
• Extended repeat area function DSAR DDAR Single address
• Instead of specifying the source or destination address registers, data is directly transferred from/to the external device using the DACK pin
• The same settings as above are available other than address register setting (e.g., above transfer modes can be specified)
• One transfer can be performed in one bus cycle (the types of transfer modes are the same as those of dual address modes) DSAR/ DACK DACK/ DDAR

Section 7 DMA Controller (DMAC) Rev. 3.00 Mar. 14, 2006 Page 158 of 804 REJ09B0104-0300 When the auto request setting is selected as the activation source, the cycle stealing or burst access can be selected. When the total transfer size is not specified (DTCR = H'00000000), the transfer counter is stopped and the transfer is continued without the limitation of the transfer count.

7.4 Operations

7.4.1 Address Modes

(1) Dual Address Mode In dual address mode, the transfer source address is specified in DSAR and the transfer destination address is specified in DDAR. A transfer at a time is performed in two bus cycles (when the data bus width is less than the data access size or the access address is not aligned with the boundary of the data access size, the number of bus cycles are needed more than two because one bus cycle is divided into multiple bus cycles). In the first bus cycle, data at the transfer source address is read and in the next cycle, the read data is written to the transfer destination address. The read and write cycles are not separated. Other bus cycles (bus cycle by other bus masters, refresh cycle, and external bus release cycle) are not generated between read and write cycles. The TEND signal output is enabled or disabled by the TENDE bit in DMDR. The TEND signal is output in two bus cycles. When an idle cycle is inserted before the bus cycle, the TEND signal is also output in the idle cycle. The DACK signal is not output.

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7.4.2 Transfer Modes

(1) Normal Transfer Mode In normal transfer mode, one data access size of data is transferred at a single transfer request. Up to 4 Gbytes can be specified as a total transfer size by DTCR. DBSR is ignored in normal transfer mode. The TEND signal is output only in the last DMA transfer. Figure 7.7 shows an example of the signal timing in normal transfer mode and figure 7.8 shows the operation in normal transfer mode. Read Write Read Write DMA transfer cycle Last DMA transfer cycle Bus cycle Auto request transfer in dual address mode: External request transfer in single address mode: TEND DMA DMA DREQ Bus cycle DACK Figure 7.7 Example of Signal Timing in Normal Transfer Mode Transfer Total transfer size (DTCR) Address TA Address BA Address TB Address BB Figure 7.8 Operations in Normal Transfer Mode

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7.4.3 Activation Sources

The DMAC is activated by an auto request, an on-chip module interrupt, and an external request. The activation source is specified by bits DTF1 and DTF0 in DMDR. (1) Activation by Auto Request The auto request activation is used when a transfer request from an external device or an on-chip peripheral module is not generated such as a transfer between memory and memory or between memory and an on-chip peripheral module which does not request a transfer. A transfer request is automatically generated inside the DMAC. In auto request activation, setting the DTE bit in DMDR starts a transfer. The bus mode can be selected from cycle stealing and burst modes. (2) Activation by On-Chip Module Interrupt An interrupt request from an on-chip peripheral module (on-chip peripheral module interrupt) is used as a transfer request. When a DMA transfer is enabled (DTE = 1), the DMA transfer is started by an on-chip module interrupt. The activation source of the on-chip module interrupt is selected by the DMA module request select register (DMRSR). The activation sources are specified to the individual channels. Table 7.4 is a list of on-chip module interrupts for the DMAC. The interrupt request selected as an activation source can simultaneously generate interrupt requests to the CPU. For details, see section 5, Interrupt Controller. The DMAC receives interrupt requests by on-chip peripheral modules independent of the interrupt controller. Therefore, the DMAC is not affected by priority given in the interrupt controller. When the DMAC is activated with DTA = 1, the interrupt request flag is automatically cleared by a DMA transfer. If multiple channels use a single transfer request as an activation source, when the channel having priority is activated, the interrupt request flag is cleared. In this case, other channels may not be activated because the transfer request is not held in the DMAC. When the DMAC is activated with DTA = 0, the interrupt request flag is not cleared by the DMAC. Thus it should be cleared by the CPU. When an activation source is selected while DTE = 0, the activation source does not request a transfer to the DMAC. It requests an interrupt to the CPU or DTC. In addition, make sure that an interrupt request flag as an on-chip module interrupt source is cleared to 0 before writing 1 to the DTE bit.

Section 7 DMA Controller (DMAC) Rev. 3.00 Mar. 14, 2006 Page 167 of 804 REJ09B0104-0300 Table 7.4 List of On-chip module interrupts to DMAC On-Chip Module Interrupt Source On-Chip Module DMRSR (Vector Number) ADI0 (A/D conversion end interrupt) A/D_0 86 ADI1 (A/D conversion end interrupt) A/D_1 87 TGI0A (TGI0A input capture/compare match) TPU_0 88 TGI1A (TGI1A input capture/compare match) TPU_1 93 TGI2A (TGI2A input capture/compare match) TPU_2 97 TGI3A (TGI3A input capture/compare match) TPU_3 101 RXI3 (receive data full interrupt for SCI channel 3) SCI_3 157 TXI3 (transmit data empty interrupt for SCI channel 3) SCI_3 158 RXI4 (receive data full interrupt for SCI channel 4) SCI_4 161 TXI4 (transmit data empty interrupt for SCI channel 4) SCI_4 162 TGI6A (TGI6A input capture/compare match) TPU_6 164 TGI7A (TGI7A input capture/compare match) TPU_7 169 TGI8A (TGI8A input capture/compare match) TPU_8 173 TGI9A (TGI9A input capture/compare match) TPU_9 177 TGI10A (TGI10A input capture/compare match) TPU_10 182 TGI11A (TGI11A input capture/compare match) TPU_11 188 RM0 (message reception in Mailbox 0) HCAN 221 SSRXI0 (receive data full interrupt for SSU channel 0) SSU_0 228 SSTXI0 (transmit data empty interrupt or transmit end for SSU channel 0) SSU_0 229 SSRXI1 (receive data full interrupt for SSU channel 1) SSU_1 232 SSTXI1 (transmit data empty interrupt or transmit end for SSU channel 1) SSU_1 233 SSRXI2 (receive data full interrupt for SSU channel 2) SSU_2 236 SSTXI2 (transmit data empty interrupt or transmit end for SSU channel 2) SSU_2 237

Section 7 DMA Controller (DMAC) Rev. 3.00 Mar. 14, 2006 Page 168 of 804 REJ09B0104-0300 (3) Activation by External Request A transfer is started by a transfer request signal (DREQ) from an external device. When a DMA transfer is enabled (DTE = 1), the DMA transfer is started by the DREQ assertion. A transfer request signal is input to the DREQ pin. The DREQ signal is detected on the falling edge or low level. Whether the falling edge or low level detection is used is selected by the DREQS bit in DMDR. To perform a block transfer, select the low level detection. When an external request is selected as an activation source, clear the DDR bit to 0 and set the ICR bit to 1 for the corresponding pin. For details, see section 8, I/O Ports. When a DMA transfer between on-chip peripheral modules is performed, select an activation source form the auto request and on-chip module interrupt (the external request cannot be used).

7.4.4 Bus Access Modes

There are two types of bus access modes: cycle stealing and burst. When an activation source is the auto request, the cycle stealing or burst mode is selected by bit DTF0 in DMDR. When an activation source is the on-chip module interrupt or external request, the cycle stealing mode is selected. (1) Cycle Stealing Mode In cycle stealing mode, the DMAC releases the bus every time one unit of transfers (byte, word, longword, or 1-block size) is completed. After that, when a transfer is requested, the DMAC obtains the bus to transfer 1-unit data and then releases the bus on completion of the transfer. This operation is continued until the transfer end condition is satisfied. When a transfer is requested to another channel during a DMA transfer, the DMAC releases the bus and then transfers data for the requested channel. For details on operations when a transfer is requested to multiple channels, see section 7.4.8, Priority of Channels.

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7.4.5 Extended Repeat Area Function

The source and destination address sides can be specified as the extended repeat area. The contents of the address register repeat addresses within the area specified as the extended repeat area. For example, to use a ring buffer as the transfer target, the contents of the address register should return to the start address of the buffer every time the contents reach the end address of the buffer (overflow on the ring buffer address). This operation can automatically be performed using the extended repeat area function of the DMAC. The extended repeat areas can be specified independently to the source address register (DSAR) and destination address register (DDAR). The extended repeat area on the source address is specified by bits SARA4 to SARA0 in DACR. The extended repeat area on the destination address is specified by bits DARA4 to DARA0 in DACR. The extended repeat area sizes for each side can be specified independently. A DMA transfer is stopped and an interrupt by an extended repeat area overflow can be requested to the CPU when the contents of the address register reach the end address of the extended repeat area. When an overflow on the extended repeat area set in DSAR occurs while the SARIE bit in DACR is set to 1, the ESIF bit in DMDR is set to 1 and the DTE bit in DMDR is cleared to 0 to stop the transfer. At this time, if the ESIE bit in DMDR is set to 1, an interrupt by an extended repeat area overflow is requested to the CPU. When the DARIE bit in DACR is set to 1, an overflow on the extended repeat area set in DDAR occurs, meaning that the destination side is a target. During the interrupt handling, setting the DTE bit in DMDR resumes the transfer. Figure 7.15 shows an example of the extended repeat area operation.

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7.4.6 Address Update Function using Offset

The source and destination addresses are updated by fixing, increment/decrement by 1, 2, or 4, or offset addition. When the offset addition is selected, the offset specified by the offset register (DOFR) is added to the address every time the DMAC transfers the data access size of data. This function realizes a data transfer where addresses are allocated to separated areas. Figure 7.17 shows the address update method. + offset ±1, 2, or 4 Address not updated Data access size added to or subtracted from address (addresses are continuous) Offset is added to address (addresses are not continuous) (a) Address fixed (b) Increment or decrement by 1, 2, or 4 (c) Offset addition Figure 7.17 Address Update Method In item (a), Address fixed, the transfer source or destination address is not updated indicating the same address. In item (b), Increment or decrement by 1, 2, or 4, the transfer source or destination address is incremented or decremented by the value according to the data access size at each transfer. Byte, word, or longword can be specified as the data access size. The value of 1 for byte, 2 for word, and 4 for longword is used for updating the address. This operation realizes the data transfer placed in consecutive areas. In item (c), Offset addition, the address update does not depend on the data access size. The offset specified by DOFR is added to the address every time the DMAC transfers data of the data access size.

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7.4.7 Register during DMA Transfer

The DMAC registers are updated by a DMA transfer. The value to be updated differs according to the other settings and transfer state. The registers to be updated are DSAR, DDAR, DTCR, bits BKSZH and BKSZ in DBSR, and the DTE, ACT, ERRF, ESIF, and DTIF bits in DMDR. (1) DMA Source Address Register When the transfer source address set in DSAR is accessed, the contents of DSAR are output and then are updated to the next address. The increment or decrement can be specified by bits SAT1 and SAT0 in DACR. When SAT1 and SAT0 = B'00, the address is fixed. When SAT1 and SAT0 = B'01, the address is added with the offset. When SAT1 and SAT0 = B'10, the address is incremented. When SAT1 and SAT0 = B'11, the address is decremented. The size of increment or decrement depends on the data access size. The data access size is specified by bits DTSZ1 and DTSZ0 in DMDR. When DTSZ1 and DTSZ0 = B'00, the data access size is byte and the address is incremented or decremented by 1. When DTSZ1 and DTSZ0 = B'01, the data access size is word and the address is incremented or decremented by 2. When DTSZ1 and DTSZ0 = B'10, the data access size is longword and the address is incremented or decremented by 4. Even if the access data size of the source address is word or longword, when the source address is not aligned with the word or longword boundary, the read bus cycle is divided into byte or word cycles. While data of one word or one longword is being read, the size of increment or decrement is changing according to the actual data access size, for example, +1 or +2 for byte or word data. After one word or one longword of data is read, the address when the read cycle is started is incremented or decremented by the value according to bits SAT1 and SAT0. In block or repeat transfer mode, when the block or repeat size of data transfers is completed while the block or repeat area is specified to the source address side, the source address returns to the transfer start address and is not affected by the address update. When the extended repeat area is specified to the source address side, operation follows the setting. The upper address bits are fixed and is not affected by the address update. While data is being transferred, DSAR must be accessed in longwords. If the upper word and lower word are read separately, incorrect data may be read from since the contents of DSAR during the transfer may be updated regardless of the access by the CPU. Moreover, DSAR for the channel being transferred must not be written to.

Section 7 DMA Controller (DMAC) Rev. 3.00 Mar. 14, 2006 Page 177 of 804 REJ09B0104-0300 (2) DMA Destination Address Register When the transfer destination address set in DDAR is accessed, the contents of DDAR are output and then are updated to the next address. The increment or decrement can be specified by bits DAT1 and DAT0 in DACR. When DAT1 and DAT0 = B'00, the address is fixed. When DAT1 and DAT0 = B'01, the address is added with the offset. When DAT1 and DAT0 = B'10, the address is incremented. When DAT1 and DAT0 = B'11, the address is decremented. The incrementing or decrementing size depends on the data access size. The data access size is specified by bits DTSZ1 and DTSZ0 in DMDR. When DTSZ1 and DTSZ0 = B'00, the data access size is byte and the address is incremented or decremented by 1. When DTSZ1 and DTSZ0 = B'01, the data access size is word and the address is incremented or decremented by 2. When DTSZ1 and DTSZ0 = B'10, the data access size is longword and the address is incremented or decremented by 4. Even if the access data size of the destination address is word or longword, when the destination address is not aligned with the word or longword boundary, the write bus cycle is divided into byte and word cycles. While one word or one longword of data is being written, the incrementing or decrementing size is changing according to the actual data access size, for example, +1 or +2 for byte or word data. After the one word or one longword of data is written, the address when the write cycle is started is incremented or decremented by the value according to bits SAT1 and SAT0. In block or repeat transfer mode, when the block or repeat size of data transfers is completed while the block or repeat area is specified to the destination address side, the destination address returns to the transfer start address and is not affected by the address update. When the extended repeat area is specified to the destination address side, operation follows the setting. The upper address bits are fixed and is not affected by the address update. While data is being transferred, DDAR must be accessed in longwords. If the upper word and lower word are read separately, incorrect data may be read from since the contents of DDAR during the transfer may be updated regardless of the access by the CPU. Moreover, DDAR for the channel being transferred must not be written to. (3) DMA Transfer Count Register (DTCR) A DMA transfer decrements the contents of DTCR by the transferred bytes. When byte data is transferred, DTCR is decremented by 1. When word data is transferred, DTCR is decremented by 2. When longword data is transferred, DTCR is decremented by 4. However, when DTCR = 0, the contents of DTCR are not changed since the number of transfers is not counted.

Section 7 DMA Controller (DMAC) Rev. 3.00 Mar. 14, 2006 Page 178 of 804 REJ09B0104-0300 While data is being transferred, all the bits of DTCR may be changed. DTCR must be accessed in longwords. If the upper word and lower word are read separately, incorrect data may be read from since the contents of DTCR during the transfer may be updated regardless of the access by the CPU. Moreover, DTCR for the channel being transferred must not be written to. When a conflict occurs between the address update by DMA transfer and write access by the CPU, the CPU has priority. When a conflict occurs between change from 1, 2, or 4 to 0 in DTCR and write access by the CPU (other than 0), the CPU has priority in writing to DTCR. However, the transfer is stopped. (4) DMA Block Size Register (DBSR) DBSR is enabled in block or repeat transfer mode. Bits 31 to 16 in DBSR function as BKSZH and bits 15 to 0 in DBSR function as BKSZ. The BKSZH bits (16 bits) store the block size and repeat size and its value is not changed. The BKSZ bits (16 bits) function as a counter for the block size and repeat size and its value is decremented every transfer by 1. When the BKSZ value is to change from 1 to 0 by a DMA transfer, 0 is not stored but the BKSZH value is loaded into the BKSZ bits. Since the upper 16 bits of DBSR are not updated, DBSR can be accessed in words. DBSR for the channel being transferred must not be written to. (5) DTE Bit in DMDR Although the DTE bit in DMDR enables or disables data transfer by the CPU write access, it is automatically cleared to 0 according to the DMA transfer state by the DMAC. The conditions for clearing the DTE bit by the DMAC are as follows:

• When the total size of transfers is completed
• When a transfer is completed by a transfer size error interrupt
• When a transfer is completed by a repeat size end interrupt
• When a transfer is completed by an extended repeat area overflow interrupt
• When a transfer is stopped by an NMI interrupt
• When a transfer is stopped by and address error
• Reset state
• Hardware standby mode
• When a transfer is stopped by writing 0 to the DTE bit

Section 7 DMA Controller (DMAC) Rev. 3.00 Mar. 14, 2006 Page 180 of 804 REJ09B0104-0300 (7) ERRF Bit in DMDR When an address error or an NMI interrupt occur, the DMAC clears the DTE bits for all the channels to stop a transfer. In addition, it sets the ERRF bit in DMDR_0 to 1 to indicate that an address error or an NMI interrupt has occurred regardless of whether or not the DMAC is in operation. (8) ESIF Bit in DMDR When an interrupt by an transfer size error, a repeat size end, or an extended repeat area overflow is requested, the ESIF bit in DMDR is set to 1. When both the ESIF and ESIE bits are set to 1, a transfer escape interrupt is requested to the CPU. The ESIF bit is set to 1 when the ACT bit in DMDR is cleared to 0 to stop a transfer after the bus cycle of the interrupt source is completed. The ESIF bit is automatically cleared to 0 and a transfer request is cleared if the transfer is resumed by setting the DTE bit to 1 during interrupt handling. For details on interrupts, see section 7.7, Interrupt Sources. (9) DTIF Bit in DMDR The DTIF bit in DMDR is set to 1 after the total transfer size of transfers is completed. When both the DTIF and DTIE bits in DMDR are set to 1, a transfer end interrupt by the transfer counter is requested to the CPU. The DTIF bit is set to 1 when the ACT bit in DMDR is cleared to 0 to stop a transfer after the bus cycle is completed. The DTIF bit is automatically cleared to 0 and a transfer request is cleared if the transfer is resumed by setting the DTE bit to 1 during interrupt handling. For details on interrupts, see section 7.7, Interrupt Sources.

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7.4.8 Priority of Channels

The channels of the DMAC are given following priority levels: channel 0 > channel 1 > channel 2 > channel3. Table 7.5 shows the priority levels among the DMAC channels. Table 7.5 Priority among DMAC Channels Channel Priority Channel 0 High Channel 1 Channel 2 Channel 3 Low The channel having highest priority other than the channel being transferred is selected when a transfer is requested from other channels. The selected channel starts the transfer after the channel being transferred releases the bus. At this time, when a bus master other than the DMAC requests the bus, the cycle for the bus master is inserted. In a burst transfer or a block transfer, channels are not switched. Figure 7.22 shows a transfer example when multiple transfer requests from channels 0 to 2. Channel 0 Channel 1Bus released Bus released Channel 2 Channel 0 transfer Channel 1 transfer Channel 2 transfer Channel 0 Channel 1 Channel 2Wait Wait Request cleared Request cleared Request cleared Request retained Request retained Request retained Selected SelectedNot selected Address bus Channel 0 Channel 1 Channel 2 Bφ DMAC operation Figure 7.22 Example of Timing for Channel Priority

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7.4.9 DMA Basic Bus Cycle

Figure 7.23 shows an examples of signal timing of a basic bus cycle. In figure 7.23, data is transferred in words from the 16-bit 2-state access space to the 8-bit 3-state access space. When the bus mastership is passed from the DMAC to the CPU, data is read from the source address and it is written to the destination address. The bus is not released between the read and write cycles by other bus requests. DMAC bus cycles follows the bus controller settings. CPU cycle DMAC cycle (one word transfer) CPU cycle Address bus Bφ T1 T2 T1 T2 T3 T1 T2 T3 Source address Destination address RD HighHHWR, HLWR, LHWR LLWR Figure 7.23 Example of Bus Timing of DMA Transfer

Section 7 DMA Controller (DMAC) Rev. 3.00 Mar. 14, 2006 Page 183 of 804 REJ09B0104-0300

7.4.10 Bus Cycles in Dual Address Mode

(1) Normal Transfer Mode (Cycle Stealing Mode) In cycle stealing mode, the bus is released every time one transfer size of data (one byte, one word, or one longword) is completed. One bus cycle or more by the CPU are executed in the bus released cycles. In figure 7.24, the TEND signal output is enabled and data is transferred in words from the external 16-bit 2-state access space to the external 16-bit 2-state access space in normal transfer mode by cycle stealing. DMA read cycle DMA write cycle Address bus DMA read cycle DMA write cycle DMA read cycle DMA write cycle Bφ RD LHWR, LLWR TEND Bus released Bus released Bus released Bus released Last transfer cycle Figure 7.24 Example of Transfer in Normal Transfer Mode by Cycle Stealing In figures 7.25 and 7.26, the TEND signal output is enabled and data is transferred in longwords from the external 16-bit 2-state access space to the external 16-bit 2-state access space in normal transfer mode by cycle stealing. In figure 7.25, the transfer source (DSAR) is not aligned with a longword boundary and the transfer destination (DDAR) is aligned with a longword boundary. In figure 7.26, the transfer source (DSAR) is aligned with a longword boundary and the transfer destination (DDAR) is not aligned with a longword boundary.

Section 7 DMA Controller (DMAC) Rev. 3.00 Mar. 14, 2006 Page 185 of 804 REJ09B0104-0300 (2) Normal Transfer Mode (Burst Mode) In burst mode, one byte, one word, or one longword of data continues to be transferred until the transfer end condition is satisfied. When a burst transfer starts, a transfer request from a channel having priority is suspended until the burst transfer is completed. In figure 7.27, the TEND signal output is enabled and data is transferred in words from the external 16-bit 2-state access space to the external 16-bit 2-state access space in normal transfer mode by burst access. DMA read cycle DMA read cycle DMA write cycle Address bus DMA write cycle DMA read cycle DMA write cycle Bφ RD HHWR, HLWR LHWR, LLWR TEND Bus released Bus released Last transfer cycle Burst transfer High Figure 7.27 Example of Transfer in Normal Transfer Mode by Burst Access

Section 7 DMA Controller (DMAC) Rev. 3.00 Mar. 14, 2006 Page 186 of 804 REJ09B0104-0300 (3) Block Transfer Mode In block transfer mode, the bus is released every time a 1-block size of transfers at a single transfer request is completed. In figure 7.28, the TEND signal output is enabled and data is transferred in words from the external 16-bit 2-state access space to the external 16-bit 2-state access space in block transfer mode. DMA read cycle DMA read cycle DMA write cycle Address bus DMA write cycle DMA read cycle DMA read cycle DMA write cycle DMA write cycle Bφ RD LHWR, LLWR TEND Bus released Bus released Bus released Last block transfer cycleBlock transfer Figure 7.28 Example of Transfer in Block Transfer Mode

Section 7 DMA Controller (DMAC) Rev. 3.00 Mar. 14, 2006 Page 191 of 804 REJ09B0104-0300

7.4.11 Bus Cycles in Single Address Mode

(1) Single Address Mode (Read and Cycle Stealing) In single address mode, one byte, one word, or one longword of data is transferred at a single transfer request and after the transfer the bus is released temporarily. One bus cycle or more by the CPU are executed in the bus released cycles. In figure 7.33, the TEND signal output is enabled and data is transferred in bytes from the external 8-bit 2-state access space to the external device in single address mode (read). Bus released Bus released Bus released DMA read cycle DMA read cycle DMA read cycle DMA read cycle Bφ Address bus Bus released Bus released Last transfer cycle RD TEND DACK Figure 7.33 Example of Transfer in Single Address Mode (Byte Read)

Section 7 DMA Controller (DMAC) Rev. 3.00 Mar. 14, 2006 Page 192 of 804 REJ09B0104-0300 (2) Single Address Mode (Write and Cycle Stealing) In single address mode, data of one byte, one word, or one longword is transferred at a single transfer request and after the transfer the bus is released temporarily. One bus cycle or more by the CPU are executed in the bus released cycles. In figure 7.34, the TEND signal output is enabled and data is transferred in bytes from the external 8-bit 2-state access space to the external device in single address mode (write). Bus released Bus released DMA write cycle Bφ Address bus Bus released Bus released Last transfer cycle HHWR, HLWR TEND DACK DMA write cycle DMA write cycle DMA write cycle LLWR Bus released Figure 7.34 Example of Transfer in Single Address Mode (Byte Write)

Section 7 DMA Controller (DMAC) Rev. 3.00 Mar. 14, 2006 Page 196 of 804 REJ09B0104-0300

7.5 DMA Transfer End

Operations on completion of a transfer differ according to the transfer end condition. DMA transfer completion is indicated that the DTE and ACT bits in DMDR are changed from 1 to 0. (1) Transfer End by DTCR Change from 1, 2, or 4, to 0 When DTCR is changed from 1, 2, or 4 to 0, a DMA transfer for the channel is completed. The DTE bit in DMDR is cleared to 0 and the DTIF bit in DMDR is set to 1. At this time, when the DTIE bit in DMDR is set to 1, a transfer end interrupt by the transfer counter is requested. When the DTCR value is 0 before the transfer, the transfer is not stopped. (2) Transfer End by Transfer Size Error Interrupt When the following conditions are satisfied while the TSEIE bit in DMDR is set to 1, a transfer size error occurs and a DMA transfer is terminated. At this time, the DTE bit in DMR is cleared to 0 and the ESIF bit in DMDR is set to 1.

• In normal transfer mode and repeat transfer mode, when the next transfer is requested while a transfer is disabled due to the DTCR value less than the data access size
• In block transfer mode, when the next transfer is requested while a transfer is disabled due to the DTCR value less than the block size When the TSEIE bit in DMDR is cleared to 0, data is transferred until the DTCR value reaches 0. A transfer size error is not generated. Operation in each transfer mode is shown below.
• In normal transfer mode and repeat transfer mode, when the DTCR value is less than the data access size, data is transferred in bytes
• In block transfer mode, when the DTCR value is less than the block size, the specified size of data in DTCR is transferred instead of transferring the block size of data. The transfer is performed in bytes. (3) Transfer End by Repeat Size End Interrupt In repeat transfer mode, when the next transfer is requested after completion of a 1-repeat size data transfer while the RPTIE bit in DACR is set to 1, a repeat size end interrupt is requested. When the interrupt is requested to complete DMA transfer, the DTE bit in DMDR is cleared to 0 and the ESIF bit in DMDR is set to 1. Under this condition, setting the DTE bit to 1 resumes the transfer. In block transfer mode, when the next transfer is requested after completion of a 1-block size data transfer, a repeat size end interrupt can be requested.

Section 7 DMA Controller (DMAC) Rev. 3.00 Mar. 14, 2006 Page 197 of 804 REJ09B0104-0300 (4) Transfer End by Interrupt on Extended Repeat Area Overflow When an overflow on the extended repeat area occurs while the extended repeat area is specified and the SARIE or DARIE bit in DACR is set to 1, an interrupt by an extended repeat area overflow is requested. When the interrupt is requested, the DMA transfer is terminated, the DTE bit in DMDR is cleared to 0, and the ESIF bit in DMDR is set to 1. In dual address mode, even if an interrupt by an extended repeat area overflow occurs during a read cycle, the following write cycle is performed. In block transfer mode, even if an interrupt by an extended repeat area overflow occurs during a 1- block transfer, the remaining data is transferred. The transfer is not terminated by an extended repeat area overflow interrupt unless the current transfer is complete. (5) Transfer End by Clearing DTE Bit in DMDR When the DTE bit in DMDR is cleared to 0 by the CPU, a transfer is completed after the current DMA cycle and a DMA cycle in which the transfer request is accepted are completed. In block transfer mode, a DMA transfer is completed after 1-block data is transferred. (6) Transfer End by NMI Interrupt When an NMI interrupt is requested, the DTE bits for all the channels are cleared to 0 and the ERRF bit in DMDR_0 is set to 1. When an NMI interrupt is requested during a DMA transfer, the transfer is forced to stop. To perform DMA transfer after an NMI interrupt is requested, clear the ERRF bit to 0 and then set the DTE bits for the channels to 1. The transfer end timings after an NMI interrupt is requested are shown below. (a) Normal Transfer Mode and Repeat Transfer Mode In dual address mode, a DMA transfer is completed after completion of the write cycle for one transfer unit. In single address mode, a DMA transfer is completed after completion of the bus cycle for one transfer unit. (b) Block Transfer Mode A DMA transfer is forced to stop. Since a 1-block size of transfers is not completed, operation is not guaranteed. In dual address mode, the write cycle corresponding to the read cycle is performed. This is similar to (a) in normal transfer mode.

Section 7 DMA Controller (DMAC) Rev. 3.00 Mar. 14, 2006 Page 198 of 804 REJ09B0104-0300 (7) Transfer End by Address Error When an address error occurs, the DTE bits for all the channels are cleared to 0 and the ERRF bit in DMDR_0 is set to 1. When an address error occurs during a DMA transfer, the transfer is forced to stop. To perform a DMA transfer after an address error occurs, clear the ERRF bit to 0 and then set the DTE bits for the channels. The transfer end timing after an address error is the same as that after an NMI interrupt. (8) Transfer End by Hardware Standby Mode or Reset The DMAC is initialized by a reset and a transition to the hardware standby mode. A DMA transfer is not guaranteed.

7.6 Relationship among DMAC and Other Bus Masters

7.6.1 CPU Priority Control Function Over DMAC

The CPU priority control function over DMAC can be used according to the CPU priority control register (CPUPCR) setting. For details, see section 5.7, CPU Priority Control Function Over DMAC. The priority level of the DMAC is specified by bits DMAP2 to DMAP0 and can be specified for each channel. The priority level of the CPU is specified by bits CPUP2 to CPUP0. The value of bits CPUP2 to CPUP0 is updated according to the exception handling priority. If the CPU priority control is enabled by the CPUPCE bit in CPUPCR, when the CPU has priority over the DMAC, a transfer request for the corresponding channel is masked and the transfer is not activated. When another channel has priority over or the same as the CPU, a transfer request is received regardless of the priority between channels and the transfer is activated. If the priority level of the transfer request masked by the CPU priority control function is changed or the CPU priority is changed, the transfer request may be received and the transfer is started. When the CPUPCE bit is cleared to 0, it is regarded as the lowest priority. Transfer requests masked are suspended. If a transfer request is suspended, it is cleared by clearing the DTE bit to 0.

Section 7 DMA Controller (DMAC) Rev. 3.00 Mar. 14, 2006 Page 199 of 804 REJ09B0104-0300

7.6.2 Bus Arbitration among DMAC and Other Bus Masters

When DMA transfer cycles are consecutively performed, bus cycles of other bus masters may be inserted between the transfer cycles. The DMAC can release the bus temporarily to pass the bus to other bus masters. The consecutive DMA transfer cycles may not be divided according to the transfer mode settings to achieve high-speed access. The read and write cycles of a DMA transfer are not separated. Refreshing, external bus release, and on-chip bus master (CPU) cycles are not inserted between the read and write cycles of a DMA transfer. In block transfer mode and an auto request transfer by burst access, bus cycles of the DMA transfer are consecutively performed. For this duration, since the DMAC has priority over the CPU, accesses to the external space is suspended (the IBCCS bit in the bus control register 2 (BCR2) is cleared to 0). When the bus is passed to another channel or an auto request transfer by cycle stealing, bus cycles of the DMAC and on-chip bus master are performed alternatively. When the arbitration function among the DMAC and on-chip bus masters is enabled by setting the IBCCS bit in BCR2, the bus is used alternatively except the bus cycles which are not separated. For details, see section 6, Bus Controller (BSC). A conflict may occur between external space access of the DMAC and a refresh cycle or an external bus release cycle. Even if a burst or block transfer is performed by the DMAC, the transfer is stopped temporarily and a cycle of refresh or external bus release is inserted by the BSC (when the CPU external access does not have priority over a DMAC transfer, the transfer is not operated until the DMAC releases the bus). In dual address mode, the DMAC releases the external bus after the external space write cycle. Since the read and write cycles are not separated, the bus is not released. An internal space (on-chip memory and internal I/O registers) access of the DMAC and an external bus release cycle may be performed at the same time.

Section 7 DMA Controller (DMAC) Rev. 3.00 Mar. 14, 2006 Page 200 of 804 REJ09B0104-0300

7.7 Interrupt Sources

The DMAC interrupt sources are a transfer end interrupt by the transfer counter and a transfer escape end interrupt which is generated when a transfer is terminated before the transfer counter reaches 0. Table 7.6 shows interrupt sources and priority. Table 7.6 Interrupt Sources and Priority Abbr. Interrupt Sources Priority DMTEND0 Transfer end interrupt by channel 0 transfer counter High DMTEND1 Transfer end interrupt by channel 1 transfer counter DMTEND2 Transfer end interrupt by channel 2 transfer counter DMTEND3 Transfer end interrupt by channel 3 transfer counter DMEEND0 Interrupt by channel 0 transfer size error Interrupt by channel 0 repeat size end Interrupt by channel 0 extended repeat area overflow on source address Interrupt by channel 0 extended repeat area overflow on destination address DMEEND1 Interrupt by channel 1 transfer size error Interrupt by channel 1 repeat size end Interrupt by channel 1 extended repeat area overflow on source address Interrupt by channel 1 extended repeat area overflow on destination address DMEEND2 Interrupt by channel 2 transfer size error Interrupt by channel 2 repeat size end Interrupt by channel 2 extended repeat area overflow on source address Interrupt by channel 2 extended repeat area overflow on destination address DMEEND3 Interrupt by channel 3 transfer size error Interrupt by channel 3 repeat size end Interrupt by channel 3 extended repeat area overflow on source address Interrupt by channel 3 extended repeat area overflow on destination address Low Each interrupt is enabled or disabled by the DTIE and ESIE bits in DMDR for the corresponding channel. A DMTEND interrupt is generated by the combination of the DTIF and DTIE bits in DMDR. A DMEEND interrupt is generated by the combination of the ESIF and ESIE bits in DMDR. The DMEEND interrupt sources are not distinguished. The priority among channels are decided by the interrupt controller and it is shown in table 7.6. For details, see section 5, Interrupt Controller.

Section 7 DMA Controller (DMAC) Rev. 3.00 Mar. 14, 2006 Page 201 of 804 REJ09B0104-0300 Each interrupt source is specified by the interrupt enable bit in the register for the corresponding channel. A transfer end interrupt by the transfer counter, a transfer size error interrupt, a repeat size end interrupt, an interrupt by an extended repeat area overflow on the source address, and an interrupt by an extended repeat area overflow on the destination address are enabled or disabled by the DTIE bit in DMDR, the TSEIE bit in DMDR, the RPTIE bit in DACR, SARIE bit in DACR, and the DARIE bit in DACR, respectively. A transfer end interrupt by the transfer counter is generated when the DTIF bit in DMDR is set to 1. The DTIF bit is set to 1 when DTCR becomes 0 by a transfer while the DTIE bit in DMDR is set to 1. An interrupt other than the transfer end interrupt by the transfer counter is generated when the ESIF bit in DMDR is set to 1. The ESIF bit is set to 1 when the conditions are satisfied by a transfer while the enable bit is set to 1. A transfer size error interrupt is generated when the next transfer cannot be performed because the DTCR value is less than the data access size, meaning that the data access size of transfers cannot be performed. In block transfer mode, the block size is compared with the DTCR value for transfer error decision. A repeat size end interrupt is generated when the next transfer is requested after completion of the repeat size of transfers in repeat transfer mode. Even when the repeat area is not specified in the address register, the transfer can be stopped periodically according to the repeat size. At this time, when a transfer end interrupt by the transfer counter is generated, the ESIF bit is set to 1. An interrupt by an extended repeat area overflow on the source and destination addresses is generated when the address exceeds the extended repeat area (overflow). At this time, when a transfer end interrupt by the transfer counter, the ESIF bit is set to 1. Figure 7.38 is a block diagram of interrupts and interrupt flags. To clear an interrupt, clear the DTIF or ESIF bit in DMDR to 0 in the interrupt handling routine or continue the transfer by setting the DTE bit in DMDR after setting the register. Figure 7.39 shows procedure to resume the transfer by clearing a interrupt.

Section 7 DMA Controller (DMAC) Rev. 3.00 Mar. 14, 2006 Page 203 of 804 REJ09B0104-0300

7.8 Notes on Usage

1. DMAC Register Access During Operation Except for clearing the DTE bit in DMDR, the settings for channels being transferred (including waiting state) must not be changed. The register settings must be changed during the transfer prohibited state. 2. Settings of Module Stop Function The DMAC operation can be enabled or disabled by the module stop control register. The DMAC is enabled by the initial value. Setting bit MSTPA13 in MSTPCRA stops the clock supplied to the DMAC and the DMAC enters the module stop state. However, when a transfer for a channel is enabled or when an interrupt is being requested, bit MSTPA13 cannot be set to 1. Clear the DTE bit to 0, clear the DTIF or DTIE bit in DMDR to 0, and then set bit MSTPA13. When the clock is stopped, the DMAC registers cannot be accessed. However, the following register settings are valid in the module stop state. Disable them before entering the module stop state, if necessary.  TENDE bit in DMDR is 1 (the TEND signal output enabled)  DACKE bit in DMDR is 1 (the DACK signal output enabled) 3. Activation by DREQ Falling Edge The DREQ falling edge detection is synchronized with the DMAC internal operation. A. Activation request waiting state: Waiting for detecting the DREQ low level. A transition to 2. is made. B. Transfer waiting state: Waiting for a DMAC transfer. A transition to 3. is made. C. Transfer prohibited state: Waiting for detecting the DREQ high level. A transition to 1. is made. After a DMAC transfer enabled, a transition to 1. is made. Therefore, the DREQ signal is sampled by low level detection at the first activation after a DMAC transfer enabled. 4. Acceptation of Activation Source At the beginning of an activation source reception, a low level is detected regardless of the setting of DREQ falling edge or low level detection. Therefore, if the DREQ signal is driven low before setting DMDR, the low level is received as a transfer request. When the DMAC is activated, clear the DREQ signal of the previous transfer.

Section 7 DMA Controller (DMAC) Rev. 3.00 Mar. 14, 2006 Page 204 of 804 REJ09B0104-0300

Rev. 3.00 Mar. 14, 2006 Page 205 of 804 REJ09B0104-0300 Section 8 I/O Ports Table 8.1 summarizes the port functions. The pins of each port also have other functions such as input/output pins of on-chip peripheral modules or external interrupt input pins. Each I/O port includes a data direction register (DDR) that controls input/output, a data register (DR) that stores output data, a port register (PORT) used to read the pin states, and an input buffer control register (ICR) that controls input buffer on/off. Ports 4 and 5 do not have a DR or a DDR register. Ports D, H, J and K have internal input pull-up MOSs and a pull-up MOS control register (PCR) that controls the on/off state of the input pull-up MOSs. Port 2 includes an open-drain control register (ODR) that controls on/off of the output buffer PMOSs. Ports 1, 2, 3, 6, A, D, H, J, and K can drive a single TTL load and capacitive loads up to 30 pF. All of the I/O ports can drive Darlington transistors when functioning as output ports. Schmitt-trigger inputs are enabled when a port is used as the IRQ and TPU inputs. Table 8.1 Port Functions Function Port Description Bit I/O Input Output Schmitt- Trigger Input* Input Pull-up MOS Function Open- Drain Output Function Port 1 7 P17 ADTRG1/ IRQ7  IRQ7  

6 P16/SCK3 IRQ6  IRQ6

as interrupt inputs, SCI I/Os, and A/D converter inputs 5 P15 RxD3/ IRQ5 IRQ5

4 P14 IRQ4 TxD3 IRQ4

3 P13 ADTRG0/

 IRQ3

2 P12 IRQ2  IRQ2

1 P11 IRQ1  IRQ1

0 P10 IRQ0  IRQ0

Rev. 3.00 Mar. 14, 2006 Page 206 of 804 REJ09B0104-0300 Function Port Description Bit I/O Input Output Schmitt- Trigger Input * Input Pull-up MOS Function Open- Drain Output Function Port 2 3 P23/ TIOCD3 TIOCC3/ IRQ11-A  P23, TIOCC3, TIOCD3, IRQ11-A  O

2 P22/

IRQ10-A  P22, TIOCC3, IRQ10-A General I/O port also functioning as interrupt inputs, TPU I/Os* , and SSU I/Os

1 P21/

IRQ9-A  P21, TIOCA3, IRQ9-A

0 P20/

 P20, TIOCA3, TIOCB3, IRQ8-A Port 3 7 P37/ TIOCB2 TIOCA2/ TCLKD PO15 P37, TIOCA2, TIOCB2, TCLKD  

6 P36/

 PO14 P36, TIOCA2 General I/O port also functioning as PPG outputs* and TPU I/Os

5 P35/

PO13 P35, TIOCA1, TIOCB1, TCLKC

4 P34/

 PO12 P34, TIOCA1

3 P33/

PO11 P33, TIOCC0, TIOCD0, TCLKB

2 P32/

TCLKA PO10 P32, TIOCC0, TCLKA

1 P31/

TIOCA0 PO9 P31, TIOCA0, TIOCB0

0 P30/

 PO8 P30, TIOCA0

Rev. 3.00 Mar. 14, 2006 Page 207 of 804 REJ09B0104-0300 Function Port Description Bit I/O Input Output Schmitt- Trigger Input * Input Pull-up MOS Function Open- Drain Output Function Port 4 7  P47/AN11     6  P46/AN10  General I/O port also functioning as A/D converter inputs 5  P45/AN9  4  P44/AN8  3  P43/AN15  2  P42/AN14  1  P41/AN13  0  P40/AN12  Port 5 7  P57/AN7     6  P56/AN6  General I/O port also functioning as A/D converter inputs 5  P55/AN5  4  P54/AN4  3  P53/AN3  2  P52/AN2  1  P51/AN1  0  P50/AN0  Port 6 6 P66 IRQ14  IRQ14

5 P65 IRQ13/

 IRQ13

4 P64 IRQ12 HTxD IRQ12

as SCI I/Os, interrupt inputs, and HCAN I/Os

3 P63 IRQ11-B  IRQ11-B

2 P62/SCK4 IRQ10-B  IRQ10-B

1 P61 RxD4/

 IRQ9-B

0 P60 IRQ8-B TxD4 IRQ8-B

7  PA7 B φ   O Port A

6 PA6  

Bφ output 5 PA5   Only for SSU

4 PA4  

3 PA3/SSO2  

2 PA2/SSI2  

1 PA1/SSCK2  

Rev. 3.00 Mar. 14, 2006 Page 208 of 804 REJ09B0104-0300 Function Port Description Bit I/O Input Output Schmitt- Trigger Input * Input Pull-up MOS Function Open- Drain Output Function

7 PD7/ SCS1    O O Port D

6 PD6/SSCK1  

5 PD5/SSI1  

4 PD4/SSO1  

3 PD3/ SCS0  

2 PD2/SSCK0  

1 PD1/SSI0  

0 PD0/SSO0  

7 PH7    O  Port H

6 PH6  

5 PH5  

4 PH4  

3 PH3  

2 PH2  

1 PH1  

0 PH0  

7 PJ7/

 PJ7, TIOCA8, TIOCB8, TCLKH O 

6 PJ6/

  PJ6, TIOCA8

5 PJ5/

 PJ5, TIOCA7, TIOCB7, TCLKG

4 PJ4/

  PJ4, TIOCA7

3 PJ3/

 PJ3, TIOCC6, TIOCD6, TCLKF

2 PJ2/

TCLKE  PJ2, TIOCC6, TCLKE

Rev. 3.00 Mar. 14, 2006 Page 209 of 804 REJ09B0104-0300 Function Port Description Bit I/O Input Output Schmitt- Trigger Input * Input Pull-up MOS Function Open- Drain Output Function Port J General I/O port also functioning as TPU I/Os

1 PJ1/

TIOCA6  PJ1, TIOCA6, TIOCB6 O 

0 PJ0/

  PJ0, TIOCA6 Port K General I/O port also functioning as TPU I/Os

7 PK7/

TIOCA11  PK7, TIOCA11, TIOCB11 O 

6 PK6/

  PK6, TIOCA11

5 PK5/

TIOCA10  PK5, TIOCA10, TIOCB10

4 PK4/

  PK4, TIOCA10

3 PK3/

TIOCC9  PK3, TIOCC9, TIOCD9

2 PK2/

  PK2, TIOCC9

1 PK1/

TIOCA9  PK1, TIOCA9, TIOCB9

0 PK0/

  PK0, TIOCA9 Notes: 1. Pins without Schmitt-trigger input buffer have CMOS input buffer. 2. Supported only by the H8SX/1527.

Rev. 3.00 Mar. 14, 2006 Page 210 of 804 REJ09B0104-0300

8.1 Register Descriptions

Table 8.2 lists each port registers. Table 8.2 Register Configuration in Each Port Registers Port Number of Pins DDR DR PORT ICR PCR ODR PHRTIDR Port 1 8 O O O O    Port 2*

4 O O O O  O 

Port 3 8 O O O O    Port 6*

7 O O O O   

Port A* Port D 8 O O O O O   Port H 8 O O O O O  O Port J 8 O O O O O   Port K 8 O O O O O   [Legend] O: Register exists : No register exists Notes: 1. The lower four bits are valid and t he upper four bits are reserved. The write value should always be the initial value. 2. The lower seven bits are valid and the uppe r one bit is reserved. The write value should always be the initial value. 3. The upper seven bits are valid and the lowe r one bit is reserved. The write value should always be the initial value.

Rev. 3.00 Mar. 14, 2006 Page 212 of 804 REJ09B0104-0300

8.1.1 Data Direction Register (PnDDR) (n = 1 to 3, 6, A, D, H, J, and K)

DDR is an 8-bit write-only register that specifies the port input or output for each bit. A read from the DDR is invalid and DDR is always read as an undefined value. When the general I/O port function is selected, the corresponding pin functions as an output port by setting the corresponding DDR bit to 1; the corresponding pin functions as an input port by clearing the corresponding DDR bit to 0. Note: The lower four bits are valid and the upper four bits are reserved for port 2 data direction register (P2DDR). The lower seven bits are valid and the upper one bit is reserved for port 6 data direction register (P6DDR). The upper seven bits are valid and the lower one bit is reserved for port A data direction register (PADDR). Pn7DDR W Pn6DDR W Pn5DDR W Pn4DDR W Pn3DDR W Pn0DDR W Pn2DDR W Pn1DDR W Bit Bit Name Initial Value R/W

8.1.2 Data Register (PnDR) (n = 1 to 3, 6, A, D, H, J, and K)

DR is an 8-bit readable/writable register that stores the output data of the pins to be used as the general output port. The initial value of DR is H'00. Note: The lower four bits are valid and the upper four bits are reserved for port 2 data register (P2DR). The lower seven bits are valid and the upper one bit is reserved for port 6 data register (P6DR). The upper seven bits are valid and the lower one bit is reserved for port A data register (PADR). Pn7DR R/W Pn6DR R/W Pn5DR R/W Pn4DR R/W Pn3DR R/W Pn0DR R/W Pn2DR R/W Pn1DR R/W Bit Bit Name Initial Value R/W

Rev. 3.00 Mar. 14, 2006 Page 213 of 804 REJ09B0104-0300

8.1.3 Port Register (PORTn) (n = 1 to 6, A, D, H, J, and K)

PORT is an 8-bit read-only register that reflects the port pin status. A write to PORT is invalid. When PORT is read, the DR bits that correspond to the respective DDR bits set to 1 are read and the status of each pin whose corresponding DDR bit is cleared to 0 is also read regardless of the ICR value. The initial value of PORT is undefined and is determined based on the port pin status. Note: The lower four bits are valid and the upper four bits are reserved for port 2 register (PORT2). The lower seven bits are valid and the upper one bit is reserved for port 6 register (PORT6). The upper seven bits are valid and the lower one bit is reserved for port A register (PORTA). Pn7 Undefined R Pn6 Undefined R Pn5 Undefined R Pn4 Undefined R Pn3 Undefined R Pn0 Undefined R Pn2 Undefined R Pn1 Undefined R Bit Bit Name Initial Value R/W

8.1.4 Input Buffer Control Register (PnICR) (n = 1 to 6, A, D, H, J, and K)

ICR is an 8-bit readable/writable register that controls the port input buffers. For bits in ICR set to 1, the input buffers of the corresponding pins are valid. For bits in ICR cleared to 0, the input buffers of the corresponding pins are invalid and the input signals are fixed high. When the pin functions as an input for the peripheral modules, the corresponding bits should be set to 1. The initial value should be written to a bit whose corresponding pin is not used as an input or is used as an analog input/output pin. When PORT is read, the pin status is always read regardless of the ICR value. On-chip modules are not affected by the pin status when the ICR value is cleared to 0. If ICR is modified, an internal edge may occur depending on the pin status. Accordingly, ICR should be modified when the corresponding input pins are not used. For example, in IRQ input, modify ICR while the corresponding interrupt is disabled, clear the IRQF flag in ISR of the interrupt controller to 0, and then enable the corresponding interrupt. If an edge occurs after the ICR setting, the edge should be cancelled. The initial value of ICR is H'00.

Rev. 3.00 Mar. 14, 2006 Page 214 of 804 REJ09B0104-0300 Note: The lower four bits are valid and the upper four bits are reserved for port 2 input buffer control register (P2ICR). The lower seven bits are valid and the upper one bit is reserved for port 6 input buffer control register (P6ICR). The upper seven bits are valid and the lower one bit is reserved for port A input buffer control register (PAICR). Pn7ICR R/W Pn6ICR R/W Pn5ICR R/W Pn4ICR R/W Pn3ICR R/W Pn0ICR R/W Pn2ICR R/W Pn1ICR R/W Bit Bit Name Initial Value R/W

8.1.5 Pull-Up MOS Control Register (PnPCR) (n = D, H, J, and K)

PCR is an 8-bit readable/writable register that controls on/off of the port input pull-up MOS. If a bit in PCR is set to 1 while the pin is in input state, the input pull-up MOS corresponding to the bit in PCR is turned on. Table 8.3 shows the input pull-up MOS status. The initial value of PCR is H'00. Pn7PCR R/W Pn6PCR R/W Pn5PCR R/W Pn4PCR R/W Pn3PCR R/W Pn0PCR R/W Pn2PCR R/W Pn1PCR R/W Bit Bit Name Initial Value R/W Table 8.3 Input Pull-Up MOS State Port Pin State Reset Software Standby Mode Other Operation Port D On-chip peripheral mo dule output OFF OFF OFF Port input OFF ON/OFF ON/OFF Port H Port output OFF OFF OFF Port input OFF ON/OFF ON/OFF Port J On-chip peripheral mo dule output OFF OFF OFF Port input OFF ON/OFF ON/OFF Port K On-chip peripheral mo dule output OFF OFF OFF Port input OFF ON/OFF ON/OFF [Legend] OFF: The input pull-up MOS is always off. ON/OFF: If PCR is set to 1, the input pull-up MOS is on; if PCR is cleared to 0, the input pull-up MOS is off.

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8.1.6 Open-Drain Control Register (PnODR) (n = 2)

ODR is an 8-bit readable/writable register that selects the open-drain output function. If a bit in ODR is set to 1, the pin corresponding to that bit in ODR functions as an NMOS open- drain output. If a bit in ODR is cleared to 0, the pin corresponding to that bit in ODR functions as a CMOS output. The initial value of ODR is H'00. Note: The lower four bits are valid and the upper four bits are reserved for port 2 open drain control register (P2ODR). Pn7ODR R/W Pn6ODR R/W Pn5ODR R/W Pn4ODR R/W Pn3ODR R/W Pn0ODR R/W Pn2ODR R/W Pn1ODR R/W Bit Bit Name Initial Value R/W

8.1.7 Port H Realtime Input Data Register (PHRTIDR)

PHRTIDR stores the status of port H using pin IRQ14 as a trigger. The detection method is specified by the IRQ14SR and IRQ14SF bits in the IRQ sense control register H (ISCRH) and is selected from a low level, a falling edge, a rising edge of pin, and both edges of pin IRQ14. For details, see section 5.3.5, IRQ Sense Control Registers H and L (ISCRH and ISCRL). PHRTIDR7 R PHRTIDR6 R PHRTIDR5 R PHRTIDR4 R PHRTIDR3 R PHRTIDR0 R PHRTIDR2 R PHRTIDR1 R Bit Bit Name Initial Value R/W

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8.2 Output Buffer Control

This section describes the output priority of each pin. The name of each peripheral module pin is followed by "_OE". This (for example: MIOCA4_OE) indicates whether the output of the corresponding function is valid (1) or if another setting is specified (0). Table 8.4 lists each port output signal's valid setting. For details on the corresponding output signals, see the register description of each peripheral module. If the name of each peripheral module pin is followed by A or B, the pin function can be modified by the port function control register (PFCR). For details, see section 8.3.3, Port Function Control Register B (PFCRB).

8.2.1 Port 1

(1) P17/ADTRG1/IRQ7 The pin function is switched as shown below according to the P17DDR bit setting. Setting I/O Port Module Name Pin Function P17DDR I/O port P17 output 1 P17 input (initial setting) 0 (2) P16/SCK3/ IRQ6 The pin function is switched as shown below according to the combination of the SCI_3 and P16DDR bit settings. Setting SCI_3 I/O Port Module Name Pin Function SCK3_OE P16DDR SCI_3 SCK3 output 1  I/O port P16 output 0 1 P16 input (initial setting) 0 0

Rev. 3.00 Mar. 14, 2006 Page 217 of 804 REJ09B0104-0300 (3) P15/RxD3/IRQ5 The pin function is switched as shown below according to the P15DDR bit setting. Setting I/O Port Module Name Pin Function P15DDR I/O port P15 output 1 P15 input (initial setting) 0 (4) P14/TxD3/IRQ4 The pin function is switched as shown below according to the combination of the SCI_3 and P14DDR bit settings. Setting SCI_4 I/O Port Module Name Pin Function TxD3_OE P14DDR SCI_3 TxD3 output 1  I/O port P14 output 0 1 P14 input (initial setting) 0 0 (5) P13/ADTRG0/IRQ3 The pin function is switched as shown below according to the P13DDR bit setting. Setting I/O Port Module Name Pin Function P13DDR I/O port P13 output 1 P13 input (initial setting) 0

Rev. 3.00 Mar. 14, 2006 Page 218 of 804 REJ09B0104-0300 (6) P12/IRQ2 The pin function is switched as shown below according to the P12DDR bit setting. Setting I/O Port Module Name Pin Function P12DDR I/O port P12 output 1 P12 input (initial setting) 0 (7) P11/IRQ1 The pin function is switched as shown below according to the P11DDR bit setting. Setting I/O Port Module Name Pin Function P11DDR I/O port P11 output 1 P11 input (initial setting) 0 (8) P10/IRQ0 The pin function is switched as shown below according to the P10DDR bit setting. Setting I/O Port Module Name Pin Function P10DDR I/O port P10 output 1 P10 input (initial setting) 0

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8.2.2 Port 2

(1) P23/TIOCC3/TIOCD3/ IRQ11-A The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_3, and P23DDR bit settings. Setting TPU_3 * I/O Port Module Name Pin Function TIOCD3_OE P23DDR TPU_3* TIOCD3 output 1  I/O port P23 output 0 1 P23 input (initial setting) 0 0 Note: * Supported only by the H8SX/1527. (2) P22/TIOCC3/ IRQ10-A The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_3, and P22DDR bit settings. Setting TPU_3 * I/O Port Module Name Pin Function TIOCD3_OE P22DDR TPU_3* TIOCC3 output 1  I/O port P22 output 0 1 P22 input (initial setting) 0 0 Note: * Supported only by the H8SX/1527.

Rev. 3.00 Mar. 14, 2006 Page 220 of 804 REJ09B0104-0300 (3) P21/TIOCA3/ IRQ9-A/SCS2 The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), SSU_2, TPU_3, and P21DDR bit settings. Setting SSU_2 TPU_3 * I/O Port Module Name Pin Function SCS2_OE TIOCA3_OE P21DDR SSU_2 SCS2 output 1   TPU_3* TIOCA3 output 0 1  I/O port P21 output 0 0 1 P21 input (initial setting) 0 0 0 Note: * Supported only by the H8SX/1527. (4) P20/TIOCA3/TIOCB3/ IRQ8-A The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_3, and P20DDR bit settings. Setting TPU_3 * I/O Port Module Name Pin Function TIOCB3_OE P20DDR TPU_3* TIOCB3 output 1  I/O port P20 output 0 1 P20 input (initial setting) 0 0 Note: * Supported only by the H8SX/1527.

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8.2.3 Port 3

(1) P37/PO15/TIOCA2/TIOCB2/TCLKD The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_2, PPG, and P37DDR bit settings. Setting TPU_2 * PPG * I/O Port Module Name Pin Function TIOCB2_OE PO15_OE P37DDR TPU_2* TIOCB2 output 1   PPG* PO15 output 0 1  I/O port P37 output 0 0 1 P37 input (initial setting) 0 0 0 Note: * Supported only by the H8SX/1527. (2) P36/PO14/TIOCA2 The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_2, PPG, and P36DDR bit settings. Setting TPU_2 * PPG * I/O Port Module Name Pin Function TIOCA2_OE PO14_OE P36DDR TPU_2* TIOCA2 output 1   PPG* PO14 output 0 1  I/O port P36 output 0 0 1 P36 input (initial setting) 0 0 0 Note: * Supported only by the H8SX/1527.

Rev. 3.00 Mar. 14, 2006 Page 222 of 804 REJ09B0104-0300 (3) P35/PO13/TIOCA1/TIOCB1/TCLKC The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_1, PPG, and P35DDR bit settings. Setting TPU_1 * PPG * I/O Port Module Name Pin Function TIOCB1_OE PO13_OE P35DDR TPU_1* TIOCB1 output 1   PPG* PO13 output 0 1  P35 output 0 0 1 I/O port P35 input (initial setting) 0 0 0 Note: * Supported only by the H8SX/1527. (4) P34/PO12/TIOCA1 The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_1, PPG, and P34DDR bit settings. Setting TPU_1 * PPG * I/O Port Module Name Pin Function TIOCA1_OE PO12_OE P34DDR TPU_1* TIOCA1 output 1   PPG* PO12 output 0 1  I/O port P34 output 0 0 1 P34 input (initial setting) 0 0 0 Note: * Supported only by the H8SX/1527.

Rev. 3.00 Mar. 14, 2006 Page 223 of 804 REJ09B0104-0300 (5) P33/PO11/TIOCC0/TIOCD0/TCLKB The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_0, PPG, and P33DDR bit settings. Setting TPU_0 * PPG * I/O Port Module Name Pin Function TIOCD0_OE PO11_OE P33DDR TPU_0* TIOCD0 output 1   PPG* PO11 output 0 1  P33 output 0 0 1 I/O port P33 input (initial setting) 0 0 0 Note: * Supported only by the H8SX/1527. (6) P32/PO10/TIOCC0/TCLKA: The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_0, PPG, and P32DDR bit settings. Setting TPU_0 * PPG * I/O Port Module Name Pin Function TIOCC0_OE PO10_OE P32DDR TPU_0* TIOCC0 output 1   PPG* PO10 output 0 1  P32 output 0 0 1 I/O port P32 input (initial setting) 0 0 0 Note: * Supported only by the H8SX/1527.

Rev. 3.00 Mar. 14, 2006 Page 224 of 804 REJ09B0104-0300 (7) P31/PO9/TIOCA0/TIOCB0 The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_0, PPG, and P31DDR bit settings. Setting TPU_0 * PPG * I/O Port Module Name Pin Function TIOCB0_OE PO9_OE P31DDR TPU_0* TIOCB0 output 1   PPG* PO9 output 0 1  P31 output 0 0 1 I/O port P31 input (initial setting) 0 0 0 Note: * Supported only by the H8SX/1527. (8) P30/PO8/TIOCA0 The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_0, PPG, and P30DDR bit settings. Setting TPU_0 * PPG * I/O Port Module Name Pin Function TIOCA0_OE PO8_OE P30DDR TPU_0* TIOCA0 output 1   PPG* PO8 output 0 1  P30 output 0 0 1 I/O port P30 input (initial setting) 0 0 0 Note: * Supported only by the H8SX/1527.

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8.2.4 Port 6

(1) P66/IRQ14 The pin function is switched as shown below according to the P66DDR bit setting. Setting I/O Port Module Name Pin Function P66DDR P66 output 1 I/O port P66 input (initial setting) 0 (2) P65/IRQ13/HRxD The pin function is switched as shown below according to the P65DDR bit setting. Setting I/O Port Module Name Pin Function P65DDR P65 output 1 I/O port P65 input (initial setting) 0 (3) P64/IRQ12/HTxD The pin function is switched as shown below according to the combination of the HCAN and P64DDR bit settings. Setting HCAN I/O Port Module Name Pin Function HTxD_OE P64DDR HCAN HTxD output 1  I/O port P64 output 0 1 P64 input (initial setting) 0 0

Rev. 3.00 Mar. 14, 2006 Page 226 of 804 REJ09B0104-0300 (4) P63/IRQ11-B The pin function is switched as shown below according to the P63DDR bit setting. Setting I/O Port Module Name Pin Function P63DDR I/O port P63 output 1 P63 input (initial setting) 0 (5) P62/SCK4/ IRQ10-B The pin function is switched as shown below according to the combination of the SCI_4 and P62DDR bit settings. Setting SCI_4 I/O Port Module Name Pin Function SCK4_OE P62DDR SCI_4 SCK4 output 1  I/O port P62 output 0 1 P62 input (initial setting) 0 0 (6) P61/RxD4/IRQ9-B The pin function is switched as shown below according to the P61DDR bit setting. Setting I/O Port Module Name Pin Function P61DDR I/O port P61 output 1 P61 input (initial setting) 0

Rev. 3.00 Mar. 14, 2006 Page 227 of 804 REJ09B0104-0300 (7) P60/TxD4/IRQ8-B The pin function is switched as shown below according to the combination of the SCI_4 and P60DDR bit settings. Setting SCI_4 I/O Port Module Name Pin Function TxD4_OE P60DDR SCI_4 TxD4 output 1  I/O port P60 output 0 1 P60 input (initial setting) 0 0

8.2.5 Port A

(1) PA7 The pin function is switched as shown below according to the PA7DDR bit setting. Setting I/O Port Module Name Pin Function PA7DDR I/O port B φ output 1 PA7 input (initial setting) 0 (2) PA6 The pin function is switched as shown below according to the PA6DDR bit setting. Setting I/O Port Module Name Pin Function PA6DDR I/O port PA6 output 1 PA6 input (initial setting) 0

Rev. 3.00 Mar. 14, 2006 Page 228 of 804 REJ09B0104-0300 (3) PA5 The pin function is switched as shown below according to the PA5DDR bit setting. Setting I/O Port Module Name Pin Function PA5DDR I/O port PA5 output 1 PA5 input (initial setting) 0 (4) PA4 The pin function is switched as shown below according to the PA4DDR bit setting. Setting I/O Port Module Name Pin Function PA4DDR I/O port PA4 output 1 PA4 input (initial setting) 0 (5) PA3/SSO2 The pin function is switched as shown below according to the combination of the SSU_2 and the PA3DDR bit settings. Setting SSU_2 Module Name Pin Function SSO2_OE PA3DDR SSU_2 SSO2 output 1  I/O port PA3 output 0 1 PA3 input (initial setting) 0 0

Rev. 3.00 Mar. 14, 2006 Page 229 of 804 REJ09B0104-0300 (6) PA2/SSI2 The pin function is switched as shown below according to the combination of the SSU_2 and the PA2DDR bit settings. Setting SSU_2 I/O Port Module Name Pin Function SSI2_OE PA2DDR SSU_2 SSI2 output 1  I/O port PA2 output 0 1 PA2 input (initial setting) 0 0 (7) PA1/SSCK2 The pin function is switched as shown below according to the combination of the SSU_2 and the PA1DDR bit settings. Setting SSU_2 I/O Port Module Name Pin Function SSCK2_OE PA1DDR SSU_2 SSCK2 output 1  I/O port PA1 output 0 1 PA1 input (initial setting) 0 0

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8.2.6 Port D

(1) PD7/SCS1 The pin function is switched as shown below according to the combination of the SSU_1 and the PD7DDR bit settings. Setting SSU_2 I/O Port Module Name Pin Function SCS1_OE PD7DDR SSU_1 SCS1 output 1  I/O port PD7 output 0 1 PD7 input (initial setting) 0 0 (2) PD6/SSCK1 The pin function is switched as shown below according to the combination of the SSU_1 and the PD6DDR bit settings. Setting SSU_1 I/O Port Module Name Pin Function SSCK1_OE PD6DDR SSU_1 SSCK1 output 1  I/O port PD6 output 0 1 PD6 input (initial setting) 0 0 (3) PD5/SSI1 The pin function is switched as shown below according to the combination of the SSU_1 and the PD5DDR bit settings. Setting SSU_1 I/O Port Module Name Pin Function SSI1_OE PD5DDR SSU_1 SSI1 output 1  I/O port PD5 output 0 1 PD5 input (initial setting) 0 0

Rev. 3.00 Mar. 14, 2006 Page 231 of 804 REJ09B0104-0300 (4) PD4/SSO1 The pin function is switched as shown below according to the combination of the SSU_1 and the PD4DDR bit settings. Setting SSU_1 I/O Port Module Name Pin Function SSO1_OE PD4DDR SSU_1 SSO1 output 1  I/O port PD4 output 0 1 PD4 input (initial setting) 0 0 (5) PD3/SCS0 The pin function is switched as shown below according to the combination of the SSU_0 and the PD3DDR bit settings. Setting SSU_0 I/O Port Module Name Pin Function SCS0_OE PD3DDR SSU_0 SCS0 output 1  I/O port PD3 output 0 1 PD3 input (initial setting) 0 0 (6) PD2/SSCK0 The pin function is switched as shown below according to the combination of the SSU_0 and the PD2DDR bit settings. Setting SSU_0 I/O Port Module Name Pin Function SSCK0_OE PD2DDR SSU_0 SSCK0 output 1  I/O port PD2 output 0 1 PD2 input (initial setting) 0 0

Rev. 3.00 Mar. 14, 2006 Page 232 of 804 REJ09B0104-0300 (7) PD1/SSI0 The pin function is switched as shown below according to the combination of the SSU_0 and the PD1DDR bit settings. Setting SSU_0 I/O Port Module Name Pin Function SSI0_OE PD1DDR SSU_0 SSI0 output 1  I/O port PD1 output 0 1 PD1 input (initial setting) 0 0 (8) PD0/SSO0 The pin function is switched as shown below according to the combination of the SSU_0 and the PD0DDR bit settings. Setting SSU_0 I/O Port Module Name Pin Function SSO0_OE PD0DDR SSU_0 SSO0 output 1  I/O port PD0 output 0 1 PD0 input (initial setting) 0 0

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8.2.7 Port H

(1) PH7, PH6, PH5, PH4, PH3, PH2, PH1, and PH0 Port H functions as an 8-bit I/O port and also functions as a realtime input port. Using port H as the realtime input port, the pin status of port H is stored in PHRTIDR by the following triggers a low level, a falling edge, a rising edge, or both edges of pin IRQ14. The pin function is switched as shown below according to the PHnDDR bit setting. Setting I/O Port Module Name Pin Function PHnDDR I/O port PHn output 1 PHn input (initial setting) 0 [Legend] n = 7 to 0

8.2.8 Port J

(1) PJ7/TIOCA8/TIOCB8/TCLKH The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_8, and PJ7DDR bit settings. Setting TPU_8 I/O Port Module Name Pin Function TIOCB8_OE PJ7DDR TPU_8 TIOCB8 output 1  I/O port PJ7 output 0 1 PJ7 input (initial setting) 0 0

Rev. 3.00 Mar. 14, 2006 Page 234 of 804 REJ09B0104-0300 (2) PJ6/TIOCA8 The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_8, and PJ6DDR bit settings. Setting TPU_8 I/O Port Module Name Pin Function TIOCA8_OE PJ6DDR TPU_8 TIOCA8 output 1  I/O port PJ6 output 0 1 PJ6 input (initial setting) 0 0 (3) PJ5/TIOCA7/TIOCB7/TCLKG The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_7, and PJ5DDR bit settings. Setting TPU_7 I/O Port Module Name Pin Function TIOCB7_OE PJ5DDR TPU_7 TIOCB7 output 1  I/O port PJ5 output 0 1 PJ5 input (initial setting) 0 0 (4) PJ4/TIOCA7 The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_7, and PJ4DDR bit settings. Setting TPU_7 I/O Port Module Name Pin Function TIOCA7_OE PJ4DDR TPU_7 TIOCA7 output 1  I/O port PJ4 output 0 1 PJ4 input (initial setting) 0 0

Rev. 3.00 Mar. 14, 2006 Page 235 of 804 REJ09B0104-0300 (5) PJ3/TIOCC6/TIOCD6/TCLKF The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_6, and PJ3DDR bit settings. Setting TPU_6 I/O Port Module Name Pin Function TIOCD6_OE PJ3DDR TPU_6 TIOCD6 output 1  I/O port PJ3 output 0 1 PJ3 input (initial setting) 0 0 (6) PJ2/TIOCC6/TCLKE The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_6, and PJ2DDR bit settings. Setting TPU_6 I/O Port Module Name Pin Function TIOCC6_OE PJ2DDR TPU_6 TIOCC6 output 1  I/O port PJ2 output 0 1 PJ2 input (initial setting) 0 0 (7) PJ1/TIOCA6/TIOCB6 The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_6, and PJ1DDR bit settings. Setting TPU_6 I/O Port Module Name Pin Function TIOCB6_OE PJ1DDR TPU_6 TIOCB6 output 1  I/O port PJ1 output 0 1 PJ1 input (initial setting) 0 0

Rev. 3.00 Mar. 14, 2006 Page 236 of 804 REJ09B0104-0300 (8) PJ0/TIOCA6 The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_6, and PJ0DDR bit settings. Setting TPU_6 I/O Port Module Name Pin Function TIOCA6_OE PJ0DDR TPU_6 TIOCA6 output 1  I/O port PJ0 output 0 1 PJ0 input (initial setting) 0 0

8.2.9 Port K

(1) PK7/TIOCA11/TIOCB11 The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_11, and PK7DDR bit settings. Setting TPU_11 I/O Port Module Name Pin Function TIOCB11_OE PK7DDR TPU_11 TIOCB11 output 1  I/O port PK7 output 0 1 PK7 input (initial setting) 0 0 (2) PK6/TIOCA11 The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_11, and PK6DDR bit settings. Setting TPU_11 I/O Port Module Name Pin Function TIOCA11_OE PK6DDR TPU_11 TIOCA11 output 1  I/O port PK6 output 0 1 PK6 input (initial setting) 0 0

Rev. 3.00 Mar. 14, 2006 Page 237 of 804 REJ09B0104-0300 (3) PK5/TIOCA10/TIOCB10 The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_10, and PK5DDR bit settings. Setting TPU_10 I/O Port Module Name Pin Function TIOCB10_OE PK5DDR TPU_10 TIOCB10 output 1  I/O port PK5 output 0 1 PK5 input (initial setting) 0 0 (4) PK4/TIOCA10 The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_10, and PK4DDR bit settings. Setting TPU_10 I/O Port Module Name Pin Function TIOCA10_OE PK4DDR TPU_10 TIOCA10 output 1  I/O port PK4 output 0 1 PK4 input (initial setting) 0 0 (5) PK3/TIOCC9/TIOCD9 The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_9, and PK3DDR bit settings. Setting TPU_9 I/O Port Module Name Pin Function TIOCD9_OE PK3DDR TPU_9 TIOCD9 output 1  I/O port PK3 output 0 1 PK3 input (initial setting) 0 0

Rev. 3.00 Mar. 14, 2006 Page 238 of 804 REJ09B0104-0300 (6) PK2/TIOCC9 The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_9, and PK2DDR bit settings. Setting TPU_9 I/O Port Module Name Pin Function TIOCC9_OE PK2DDR TPU_6 TIOCC9 output 1  I/O port PK2 output 0 1 PK2 input (initial setting) 0 0 (7) PK1/TIOCA6/TIOCB6 The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_9, and PK1DDR bit settings. Setting TPU_9 I/O Port Module Name Pin Function TIOCB9_OE PK1DDR TPU_9 TIOCB9 output 1  I/O port PK1 output 0 1 PK1 input (initial setting) 0 0 (8) PK0/TIOCA9 The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_9, and PK0DDR bit settings. Setting TPU_9 I/O Port Module Name Pin Function TIOCA9_OE PK0DDR TPU_9 TIOCA9 output 1  I/O port PK0 output 0 1 PK0 input (initial setting) 0 0

Rev. 3.00 Mar. 14, 2006 Page 239 of 804 REJ09B0104-0300 Table 8.4 Available Output Signals and Settings in Each Port Port Output Specification Signal Name Output Signal Name Signal Selection Register Settings Peripheral Module Settings P1 6 SCK3_OE SCK3 When SCMR_3.SMIF = 1: SCR_3.TE = 1 or SCR_3.RE = 1 while SMR_3.GM = 0, SCR.CKE [1, 0] = 01 or while SMR.GM = 1 When SCMR_3.SMIF = 0: SCR_3.TE = 1 or SCR_3.RE = 1 while SMR_3.C/A = 0, SCR_3.CKE [1, 0] = 01 or while SMR_3.C/A = 1, SCR_3.CKE 1 = 0 0 TxD3_OE TxD3 SCR.TE = 1 P2 3 TIOCD3_OE * TIOCD3 TPU.TMDR.BFB = 0, TPU.TIORL_3.IOD3 = 0, TPU.TIORL_3.IOD[1,0] = 01/10/11 2 TIOCC3_OE * TIOCC3 TPU.TMDR.BFA = 0, TPU.TIORL_3.IOC3 = 0, TPU.TIORL_3.IOD[1,0] = 01/10/11 1 SCS2_OE SCS2 SSU.SSCRH_2.CSS1 = 1, SSU.SSCRH_2.CSS0 = 0, or SSU.SSCRH_2.CSS1 = 1, SSU.SSCRH_2.CSS0 = 1 while SSU.SSCRL_2.SSUMS = 0, SSU.SSCRH_2.MSS = 1 TIOCA3_OE * TIOCA3 TPU.TIORH_3.IOA3 = 0, TPU.TIORH_3.IOA[1,0] = 01/10/11 0 TIOCB3_OE * TIOCB3 TPU.TIORH_3.IOB3 = 0, TPU.TIORH_3.IOB[1,0] = 01/10/11 P3 7 TIOCB2_OE * TIOCB2 TPU.TIOR_2.IOB3 = 0, TPU.TIOR_2.IOB[1,0] = 01/10/11 PO15_OE * PO15 NDERH.NDER15 = 1 6 TIOCA2_OE * TIOCA2 TPU.TIOR_2.IOA3 = 0, TPU.TIOR_2.IOA[1,0] = 01/10/11 PO14_OE * PO14 NDERH.NDER14 = 1 5 TIOCB1_OE * TIOCB1 TPU.TIOR_1.IOB3 = 0, TPU.TIOR_1.IOB[1,0] = 01/10/11 PO13_OE * PO13 NDERH.NDER13 = 1 4 TIOCA1_OE * TIOCA1 TPU.TIOR_1.IOA3 = 0, TPU.TIOR_1.IOA[1,0] = 01/10/11 PO12_OE * PO12 NDERH.NDER12 = 1 3 TIOCD0_OE * TIOCD0 TPU.TMDR_0.BFB = 0, TPU.TIORL_0.IOD3 = 0, TPU.TIORL_0.IOD[1,0] = 01/10/11 PO11_OE * PO11 NDERH.NDER11 = 1 2 TIOCC0_OE * TIOCC0 TPU.TMDR_0.BFA = 0, TPU.TIORL_0.IOC3 = 0, TPU.TIORL_0.IOD[1,0] = 01/10/11 PO10_OE * PO10 NDERH.NDER10 = 1 1 TIOCB0_OE * TIOCB0 TPU.TIORH_0.IOB3 = 0, TPU.TIORH_0.IOB[1,0] = 01/10/11 PO9_OE * PO9 NDERH.NDER9 = 1

Rev. 3.00 Mar. 14, 2006 Page 240 of 804 REJ09B0104-0300 Port Output Specification Signal Name Output Signal Name Signal Selection Register Settings Peripheral Module Settings P3 0 TIOCA0_OE * TIOCA0 TPU.TIORH_0.IOA3 = 0, TPU.TIORH_0.IOA[1,0] = 01/10/11 PO8_OE * PO8 NDERH.NDER8 = 1 P6 4 HTxD_OE HTxD HCAN MBCR.MBCRn = 0, HCAN.TXRP.TXRn = 1 while HCAN.HCANMON.HCANE = 1, HCAN.HCANMON.TxSTP = 0 (n = 1 to 15) 2 SCK4_OE SCK4 When SCMR_4.SMIF = 1: SCR_4.TE = 1 or SCR_4.RE = 1 while SMR_4.GM = 0, SCR_4.CKE [1, 0] = 01 or while SMR_4.GM = 1 When SCMR_4.SMIF = 0: SCR_4.TE = 1 or SCR_4.RE = 1 while SMR_4.C/A = 0, SCR_4.CKE [1, 0] = 01 or while SMR_4.C/A = 1, SCR_4.CKE 1 = 0 0 TxD4_OE TxD4 SCR.TE = 1 PA 7 B φ_OE B φ PADDR.PA7DDR = 1, SCKCR.PSTOP1 = 0, SCKCR.POSEL1 = 0 3 SSO2_OE SSI02 When SSU.SSCRL_2.SSUMS = 0, SSU.SSCRH_2.MSS = 1: SSU.SSCRH_2.BIDE = 0, SSU.SSER_2.TE = 1 or = 1 When SSU.SSCRL_2.SSUMS = 0, SSU.SSCRH_2.MSS = 0: = 1 When SSU.SSCRL_2.SSUMS = 1: SSU.SSER_2.TE = 1 2 SSI2_OE SSI2 SSU.SSCRL_2SSUMS = 0, SSU.SSCRH_2.MSS = 0 SSU.SSCRH_2.BIDE = 0, SSU.SSER_2.TE = 1 1 SSCK2_OE SSCK2 SSU.SSCRH_2.MSS = 1, SSU.SSCRH_2.SCKS = 1 PD 7 SCS1_OE SCS1 SSU.SSCRH_0.CSS1 = 1, SSU.SSCRH_0.CSS0 = 0 or SSU.SSCRH_0.CSS1 = 1, SSU.SSCRH_0.CSS0 = 1 while SSU.SSCRL_0.SSUMS = 0, SSU.SSCRH_0.MSS = 1 6 SSCK1_OE SSCK1 SSU.SSCRH_1.MSS = 1, SSU.SSCRH_1.SCKS = 1 5 SSI1_OE SSI1 SSU.SSCRL_1.SSUMS = 0, SSU.SSCRH_1.MSS = 0 SSU.SSCRH_1.BIDE = 0, SSU.SSER_1.TE = 1

Rev. 3.00 Mar. 14, 2006 Page 241 of 804 REJ09B0104-0300 Port Output Specification Signal Name Output Signal Name Signal Selection Register Settings Peripheral Module Settings PD 4 SSO1_OE SSO1 When SSU.SSCRL_1.SSUMS = 0, SSU.SSCRH_1.MSS = 1: SSU.SSCRH_1.BIDE = 0, SSU.SSER_1.TE = 1 or = 1 When SSU.SSCRL_1.SSUMS = 0, SSU.SSCRH_1.MSS = 0: = 1 When SSU.SSCRL_1.SSUMS = 1: SSU.SSER_1.TE = 1 3 SCS0_OE SCS0 SSU.SSCRH_0.CSS1 = 1, SSU.SSCRH_0.CSS0 = 0 or SSU.SSCRH_0.CSS1 = 1, SSU.SSCRH_0.CSS0 = 1 while SSU.SSCRL_0.SSUMS = 0, SSU.SSCRH_0.MSS = 1 PD 2 SSCK0_OE SSCK0 SSU.SSCRH_0.MSS = 1, SSU.SSCRH_0.SCKS = 1 1 SSI0_OE SSI0 SSU.SSCRL_0.SSUMS = 0, SSU.SSCRH_0.MSS = 0 SSU.SSCRH_0.BIDE = 0, SSU.SSER_0.TE = 1 0 SSO0_OE SSO0 When SSU.SSCRL_0.SSUMS = 0, SSU.SSCRH_0.MSS = 1: SSU.SSCRH_0.BIDE = 0, SSU.SSER_0.TE = 1 or = 1 When SSU.SSCRL_0.SSUMS = 0, SSU.SSCRH_0.MSS = 0: = 1 When SSU.SSCRL_0.SSUMS = 1: SSU.SSER_0.TE = 1 PJ 7 TIOCB8_OE TIOCB8 TPU.TIOR_8.IOB3 = 0, TPU.TIOR_8.IOB[1, 0] = 01/10/11 6 TIOCA8_OE TIOCA8 TPU.TIOR_8.IOA3 = 0, TPU.TIOR_8.IOA[1, 0] = 01/10/11 5 TIOCB7_OE TIOCB7 TPU.TIOR_7.IOB3 = 0, TPU.TIOR_7.IOB[1, 0] = 01/10/11 4 TIOCA7_OE TIOCA7 TPU.TIOR_7.IOA3 = 0, TPU.TIOR_7.IOA[1, 0] = 01/10/11 3 TIOCD6_OE TIOCD6 TPU.TMDR_6.BFB = 0, TPU.TIORL_6.IOD3 = 0 TPU.TIORL_6.IOD[1, 0] = 01/10/11 2 TIOCC6_OE TIOCC6 TPU.TMDR_6.BFA = 0, TPU.TIORL_6.IOC3 = 0 TPU.TIORL_6.IOC[1, 0] = 01/10/11 1 TIOCB6_OE TIOCB6 TPU.TIORH_6.IOB3 = 0, TPU.TIORH_6.IOB[1, 0] = 01/10/11 0 TIOCA6_OE TIOCA6 TPU.TIORH_6.IOA3 = 0, TPU.TIORH_6.IOA[1, 0] = 01/10/11

Rev. 3.00 Mar. 14, 2006 Page 242 of 804 REJ09B0104-0300 Port Output Specification Signal Name Output Signal Name Signal Selection Register Settings Peripheral Module Settings PK 7 TIOCB11_OE TIOCB11 TPU.TIOR_11.IOB3 = 0, TPU.TIOR_11.IOB[1, 0] = 01/10/11 6 TIOCA11_OE TIOCA11 TPU.TIOR_11.IOA3 = 0, TPU.TIOR_11.IOA[1, 0] = 01/10/11 5 TIOCB10_OE TIOCB10 TPU.TIOR_10.IOB3 = 0, TPU.TIOR_10.IOB[1, 0] = 01/10/11 4 TIOCA10_OE TIOCA10 TPU.TIOR_10.IOA3 = 0, TPU.TIOR_10.IOA[1, 0] = 01/10/11 3 TIOCD9_OE TIOCD9 TPU.TMDR_9.BFB = 0, TPU.TIORL_9.IOD3 = 0 TPU.TIORL_9.IOD[1, 0] = 01/10/11 2 TIOCC9_OE TIOCC9 TPU.TMDR_9.BFA = 0, TPU.TIORL_9.IOC3 = 0 TPU.TIORL_9.IOC[1, 0] = 01/10/11 1 TIOCB9_OE TIOCB9 TPU.TIOR_9.IOB3 = 0, TPU.TIOR_9.IOB[1, 0] = 01/10/11 0 TIOCA9_OE TIOCA9 TPU.TIOR_9.IOA3 = 0, TPU.TIOR_9.IOA[1, 0] = 01/10/11 Note: * Supported only by the H8SX/1527.

Rev. 3.00 Mar. 14, 2006 Page 243 of 804 REJ09B0104-0300

8.3 Port Function Controller

The port function controller controls the I/O ports. The port function controller incorporates the following registers.

• Port function control register 9 (PFCR9)*
• Port function control register A (PFCRA)
• Port function control register B (PFCRB) Note: * PFCR9 is supported only by the H8SX/1527.

8.3.1 Port Function Control Register 9 (PFCR9)

PFCR9 selects the multiple functions for the TPU (unit 0) I/O pins. R/W R/W TPUMS3A R/W TPUMS3B R/W TPUMS2 R/W TPUMS0B R/W TPUMS1 R/W TPUMS0A R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description 7, 6  All 0 R/W Reserved These bits are always read as 0. The write value should always be 0.

5 TPUMS3A 0 R/W TPU I/O Pin Multiplex Function Select

0: Specifies P21 as output compare output and input capture 1: Specifies P20 as input capture input and P21 as output compare

4 TPUMS3B 0 R/W TPU I/O Pin Multiplex Function Select

0: Specifies P22 as output compare output and input capture 1: Specifies P23 as input capture input and P22 as output compare

Rev. 3.00 Mar. 14, 2006 Page 244 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description

3 TPUMS2 0 R/W TPU I/O Pin Multiplex Function Select

0: Specifies P36 as output compare output and input capture 1: Specifies P37 as input capture input and P36 as output compare

2 TPUMS1 0 R/W TPU I/O Pin Multiplex Function Select

0: Specifies P34 as output compare output and input capture 1: Specifies P35 as input capture input and P34 as output compare

1 TPUMS0A 0 R/W TPU I/O Pin Multiplex Function Select

0: Specifies P30 as output compare output and input capture 1: Specifies P31 as input capture input and P30 as output compare

0 TPUMS0B 0 R/W TPU I/O Pin Multiplex Function Select

0: Specifies P32 as output compare output and input capture 1: Specifies P33 as input capture input and P32 as output compare

Rev. 3.00 Mar. 14, 2006 Page 245 of 804 REJ09B0104-0300

8.3.2 Port Function Co ntrol Register A (PFCRA)

PFCRA selects the multiple functions for the TPU (unit 1) I/O pins. TPUMS11 R/W TPUMS10 R/W TPUMS9A R/W TPUMS9B R/W TPUMS8 R/W TPUMS6B R/W TPUMS7 R/W TPUMS6A R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description

7 TPUMS11 0 R/W TPU I/O Pin Multiplex Function Select

0: Specifies PK6 as output compare output and input capture 1: Specifies PK7 as input capture input and PK6 as output compare

6 TPUMS10 0 R/W TPU I/O Pin Multiplex Function Select

0: Specifies PK4 as output compare output and input capture 1: Specifies PK5 as input capture input and PK4 as output compare

5 TPUMS9A 0 R/W TPU I/O Pin Multiplex Function Select

0: Specifies PK0 as output compare output and input capture 1: Specifies PK1 as input capture input and PK0 as output compare

4 TPUMS9B 0 R/W TPU I/O Pin Multiplex Function Select

0: Specifies PK2 as output compare output and input capture 1: Specifies PK3 as input capture input and PK2 as output compare

Rev. 3.00 Mar. 14, 2006 Page 246 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description

3 TPUMS8 0 R/W TPU I/O Pin Multiplex Function Select

0: Specifies PJ6 as output compare output and input capture 1: Specifies PJ7 as input capture input and PJ6 as output compare

2 TPUMS7 0 R/W TPU I/O Pin Multiplex Function Select

0: Specifies PJ4 as output compare output and input capture 1: Specifies PJ5 as input capture input and PJ4 as output compare

1 TPUMS6A 0 R/W TPU I/O Pin Multiplex Function Select

0: Specifies PJ0 as output compare output and input capture 1: Specifies PJ1 as input capture input and PJ0 as output compare

0 TPUMS6B 0 R/W TPU I/O Pin Multiplex Function Select

0: Specifies PJ2 as output compare output and input capture 1: Specifies PJ3 as input capture input and PJ2 as output compare

Rev. 3.00 Mar. 14, 2006 Page 247 of 804 REJ09B0104-0300

8.3.3 Port Function Co ntrol Register B (PFCRB)

PFCRB selects the input pins for IRQ14 to IRQ8. R/W ITS14 R/W ITS13 R/W ITS12 R/W ITS11 R/W ITS8 R/W ITS10 R/W ITS9 R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description 7  0 R/W Reserved This bit is always read as 0. The write value should always be 0.

6 ITS14 0 R/W IRQ14 Pin Select

Selects an input pin for IRQ14. 0: Pin P66 must not be used as IRQ14-A input 1: Pin P66 is used as IRQ14-B input

5 ITS13 0 R/W IRQ13 Pin Select

Selects an input pin for IRQ13. 0: Pin P65 must not be used as IRQ13-A input 1: Pin P65 is used as IRQ13-B input

4 ITS12 0 R/W IRQ12 Pin Select

Selects an input pin for IRQ12. 0: Pin P64 must not be used as IRQ12-A input 1: Pin P64 is used as IRQ12-B input

3 ITS11 0 R/W IRQ11 Pin Select

Selects an input pin for IRQ11. 0: Pin P23 is used as IRQ11-A input 1: Pin P63 is used as IRQ11-B input

Rev. 3.00 Mar. 14, 2006 Page 248 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description

2 ITS10 0 R/W IRQ10 Pin Select

Selects an input pin for IRQ10. 0: Pin P22 is used as IRQ10-A input 1: Pin P62 is used as IRQ10-B input

1 ITS9 0 R/W IRQ9 Pin Select

Selects an input pin for IRQ9. 0: Pin P21 is used as IRQ9-A input 1: Pin P61 is used as IRQ9-B input

0 ITS8 0 R/W IRQ8 Pin Select

Selects an input pin for IRQ8. 0: Pin P20 is used as IRQ8-A input 1: Pin P60 is used as IRQ8-B input

Rev. 3.00 Mar. 14, 2006 Page 249 of 804 REJ09B0104-0300

8.4 Usage Notes

8.4.1 Notes on Input Buffer Control Register (ICR) Setting

• When the ICR setting is changed, the LSI may malfunction due to an edge occurred internally according to the pin states. To change the ICR setting, fix the pin high or disable the input function corresponding to the pin by setting the on-chip module registers.
• If an input is enabled by setting ICR while multiple input functions are assigned to the pin, the pin state is reflected in all the inputs of individual modules. Care must be taken for the settings of unused input function on each module side.
• When a pin is used as an output, data to be output from the pin will be latched as the pin state if the input function corresponding to the pin is enabled. To use the pin as an output, disable the input function for the pin by setting ICR.

8.4.2 Notes on Port Function Control Register (PFCR) Settings

• The PFC controls I/O ports. To specify the function of each pin, specify the input/output destination before enabling the input/output function.
• When the input/output destination is changed by the corresponding selection bit, an edge may occur if the previous pin level differs from the pin level after the change. To change the pin direction correctly, follow the procedure shown below. 1. Disable the input function corresponding to the pin by the on-chip module registers. 2. Select the input function by setting PFCR. 3. Enable the input function.
• If a pin function has both a selection bit that modifies the input/output destination and an enable bit that enables the pin function, first specify the input/output destination by the selection bit and then enable the pin function by the enable bit.

Rev. 3.00 Mar. 14, 2006 Page 250 of 804 REJ09B0104-0300

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 251 of 804 REJ09B0104-0300 Section 9 16-Bit Timer Pulse Unit (TPU) This LSI has two on-chip 16-bit timer pulse units (TPU): unit 0 and unit1. Each unit comprises six 16-bit timer channels, that is, there are 12 timer channels in total. However, the H8SX/1525 does not include unit 0. Table 9.1 shows the unit configuration for each product. Table 9.2 is a list of the functions and figure 9.1 is a block diagram for unit 0. Table 9.3 and figure 9.2 are for unit 1. This section describes unit 0, which has the same functions as the other unit.

9.1 Features

Maximum 16-pulse input/output Selection of eight counter input clocks for each channel

• The following operations can be set for each channel:  Waveform output at compare match*  Input capture function*  Counter clear operation  Synchronous operations:
• Multiple timer counters (TCNT) can be written to simultaneously
• Simultaneous clearing by compare match and input capture possible
• Simultaneous input/output for registers possible by counter synchronous operation
• Maximum of 15-phase PWM output possible by combination with synchronous operation
• Buffer operation settable for channels 0 and 3
• Phase counting mode settable independently for each of channels 1, 2, 4, and 5
• Cascaded operation
• Fast access via internal 16-bit bus
• 26 interrupt sources
• Automatic transfer of register data
• Programmable pulse generator (PPG) output trigger can be generated (supported only by unit 0)
• Conversion start trigger for the A/D converter can be generated (supported only by unit 0)
• Module stop mode can be set

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 252 of 804 REJ09B0104-0300 Note: * The H8SX/1527 does not have pins TIOCA4, TIOCB4, TIOCA5, and TIOCB5 for channels 4 and 5. Therefore, 0-, 1-, or toggle-output waveform and PWM waveform at an input capture input and a compare match cannot be output. Table 9.1 Unit Configuration for Each Product Product Unit Configurati on Channel Configuration H8SX/1527 Unit 0 Channels 0 to 5 Unit 1 Channels 6 to 11 H8SX/1525 Unit 1 Channels 6 to 11 Note: * The H8SX/1525 does not include unit 0. Table 9.2 TPU Functions (Unit 0) Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Count clock P φ/1 Pφ/4 Pφ/16 Pφ/64 TCLKA TCLKB TCLKC TCLKD Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/256 TCLKA TCLKB Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/1024 TCLKA TCLKB TCLKC Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/256 Pφ/1024 Pφ/4096 TCLKA Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/1024 TCLKA TCLKC Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/256 TCLKA TCLKC TCLKD General registers (TGR) TGRA_0 TGRB_0 TGRA_1 TGRB_1 TGRA_2 TGRB_2 TGRA_3 TGRB_3 TGRA_4 TGRB_4 TGRA_5 TGRB_5 General registers/ buffer registers TGRC_0 TGRD_0   TGRC_3 TGRD_3   I/O pins TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4* TIOCB4* TIOCA5* TIOCB5* Counter clear function TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture* TGR compare match or input capture* 0 output O O O O O * O * 1 output O O O O O * O * Compare match output Toggle output O O O O O * O * Input capture function O O O O O * O * Synchronous operation O O O O O O

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 253 of 804 REJ09B0104-0300 Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 PWM mode O O O O O * O * Phase counting mode  O O  O O Buffer operation O   O   DMAC activation TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture* TGR compare match or input capture* A/D converter trigger TGRA_0 compare match or input capture TGRA_1 compare match or input capture TGRA_2 compare match or input capture TGRA_3 compare match or input capture TGRA_4 compare match or input capture* TGRA_5 compare match or input capture* PPG trigger TGRA_0/ TGRB_0 compare match or input capture TGRA_1/ TGRB_1 compare match or input capture TGRA_2/ TGRB_2 compare match or input capture TGRA_3/ TGRB_3 compare match or input capture   Interrupt sources 5 sources Compare match or input capture 0A Compare match or input capture 0B Compare match or input capture 0C Compare match or input capture 0D Overflow 4 sources Compare match or input capture 1A Compare match or input capture 1B Overflow Underflow 4 sources Compare match or input capture 2A Compare match or input capture 2B Overflow Underflow 5 sources Compare match or input capture 3A Compare match or input capture 3B Compare match or input capture 3C Compare match or input capture 3D Overflow 4 sources Compare match or input capture 4A Compare match or input capture 4B Overflow Underflow 4 sources Compare match or input capture 5A Compare match or input capture 5B Overflow Underflow [Legend] O : Possible  : Not possible Notes: 1. The H8SX/1527 does not have pins TIOCA4, TIOCB4, TIOCA5, and TIOCB5 for channels 4 and 5. Therefore, 0-, 1-, or toggle-output waveform and PWM waveform at an input capture input and a compare match cannot be output. 2. The H8SX/1527 does not have the inpu t capture function for channels 4 and 5.

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 254 of 804 REJ09B0104-0300 Table 9.3 TPU Functions (Unit 1) Item Channel 6 Channel 7 Channel 8 Channel 9 Channel 10 Channel 11 Count clock P φ/1 Pφ/4 Pφ/16 Pφ/64 TCLKE TCLKF TCLKG TCLKH Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/256 TCLKE TCLKF Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/1024 TCLKE TCLKF TCLKG Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/256 Pφ/1024 Pφ/4096 TCLKE Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/1024 TCLKE TCLKG Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/256 TCLKE TCLKG TCLKH General registers (TGR) TGRA_6 TGRB_6 TGRA_7 TGRB_7 TGRA_8 TGRB_8 TGRA_9 TGRB_9 TGRA_10 TGRB_10 TGRA_11 TGRB_11 General registers/ buffer registers TGRC_6 TGRD_6   TGRC_9 TGRD_9   I/O pins TIOCA6 TIOCB6 TIOCC6 TIOCD6 TIOCA7 TIOCB7 TIOCA8 TIOCB8 TIOCA9 TIOCB9 TIOCC9 TIOCD9 TIOCA10 TIOCB10 TIOCA11 TIOCB11 Counter clear function TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture 0 output O O O O O O 1 output O O O O O O Compare match output Toggle output O O O O O O Input capture function O O O O O O Synchronous operation O O O O O O PWM mode O O O O O O Phase counting mode  O O  O O Buffer operation O   O   DMAC activation TGRA_6 compare match or input capture TGR_7 compare match or input capture TGR_8 compare match or input capture TGR_9 compare match or input capture TGR_10 compare match or input capture TGR_11 compare match or input capture

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 255 of 804 REJ09B0104-0300 Item Channel 6 Channel 7 Channel 8 Channel 9 Channel 10 Channel 11 Interrupt sources 5 sources Compare match or input capture 6A Compare match or input capture 6B Compare match or input capture 6C Compare match or input capture 6D Overflow 4 sources Compare match or input capture 7A Compare match or input capture 7B Overflow Underflow 4 sources Compare match or input capture 8A Compare match or input capture 8B Overflow Underflow 5 sources Compare match or input capture 9A Compare match or input capture 9B Compare match or input capture 9C Compare match or input capture 9D Overflow 4 sources Compare match or input capture 10A Compare match or input capture 10B Overflow Underflow 4 sources Compare match or input capture 11A Compare match or input capture 11B Overflow Underflow [Legend] O : Possible  : Not possible

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 256 of 804 REJ09B0104-0300 Channel 3 TMDR TIORL TSR TCR TIORH TIER TGRA TCNT TGRB TGRC TGRD Channel 4 TMDR TSR TCR TIOR TIER TGRA TCNT TGRB Control logic TMDR TSR TCR TIOR TIER TGRA TCNT TGRB Control logic for channels 3 to 5 TMDR TSR TCR TIOR TIER TGRA TCNT TGRB TGRC Channel 1 TMDR TSR TCR TIOR TIER TGRA TCNT TGRB Channel 0 TMDR TSR TCR TIORH TIER Control logic for channels 0 to 2 TGRA TCNT TGRB TGRD TSYRTSTR Input/output pins TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4* TIOCB4* TIOCA5* TIOCB5* Clock input Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/256 Pφ/1024 Pφ/4096 TCLKA TCLKB TCLKC TCLKD Input/output pins TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 Interrupt request signals Channel 3: Channel 4: Channel 5: Interrupt request signals Channel 0: Channel 1: Channel 2: Internal data bus A/D conversion start request signal PPG output trigger signal TIORL Module data bus TGI3A TGI3B TGI3C TGI3D TCI3V TGI4A TGI4B TCI4V TCI4U TGI5A TGI5B TCI5V TCI5U TGI0A TGI0B TGI0C TGI0D TCI0V TGI1A TGI1B TCI1V TCI1U TGI2A TGI2B TCI2V TCI2U Channel 3: Channel 4: Channel 5: Internal clock: External clock: Channel 0: Channel 1: Channel 2: [Legend] TSTR: Timer start register TSYR: Timer synchronous register TCR: Timer control register TMDR: Timer mode register TIOR (H, L): Timer I/O control registers (H, L) TIER: Timer interrupt enable register TSR: Timer status register TGR (A, B, C, D): Timer general registers (A, B, C, D) TCNT: Timer counter Channel 2 Common Channel 5 Bus interface Note: * The H8SX/1527 does not have pins TIOCA4, TIOCB4, TIOCA5, and TIOCB5 for channels 4 and 5. Therefore, 0-, 1-, or toggle-output waveform and PWM waveform at an input capture input and a compare match cannot be output. Figure 9.1 Block Diagram of TPU (Unit 0)

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 257 of 804 REJ09B0104-0300 Channel 11 TMDR TIORL TSR TCR TIORH TIER TGRA TCNT TGRB TGRC TGRD Channel 10 TMDR TSR TCR TIOR TIER TGRA TCNT TGRB Control logic TMDR TSR TCR TIOR TIER TGRA TCNT TGRB Control logic for channels 9 to 11 TMDR TSR TCR TIOR TIER TGRA TCNT TGRB TGRC Channel 7 TMDR TSR TCR TIOR TIER TGRA TCNT TGRB Channel 6 TMDR TSR TCR TIORH TIER Control logic for channels 6 to 8 TGRA TCNT TGRB TGRD TSYRBTSTRB Input/output pins TIOCA9 TIOCB9 TIOCC9 TIOCD9 TIOCA10 TIOCB10 TIOCA11 TIOCB11 Clock input Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/256 Pφ/1024 Pφ/4096 TCLKE TCLKF TCLKG TCLKH Input/output pins TIOCA6 TIOCB6 TIOCC6 TIOCD6 TIOCA7 TIOCB7 TIOCA8 TIOCB8 Interrupt request signals Channel 9: Channel 10: Channel 11: Interrupt request signals Channel 6: Channel 7: Channel 8: Internal data bus TIORL Module data bus TGI9A TGI9B TGI9C TGI9D TCI9V TGI10A TGI10B TCI10V TCI10U TGI11A TGI11B TCI11V TCI11U TGI6A TGI6B TGI6C TGI6D TCI6V TGI7A TGI7B TCI7V TCI7U TGI8A TGI8B TCI8V TCI8U Channel 9: Channel 10: Channel 11: Internal clock: External clock: Channel 6: Channel 7: Channel 8: [Legend] TSTRB: Timer start register TSYRB: Timer synchronous register TCR: Timer control register TMDR: Timer mode register TIOR (H, L): Timer I/O control registers (H, L) TIER: Timer interrupt enable register TSR: Timer status register TGR (A, B, C, D): Timer general registers (A, B, C, D) TCNT: Timer counter Channel 8 Common Channel 9 Bus interface Figure 9.2 Block Diagram of TPU (Unit 1)

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 258 of 804 REJ09B0104-0300

9.2 Input/Output Pins

Table 9.4 shows TPU pin configurations. Table 9.4 Pin Configuration Unit Channel Symbol I/O Function

0 All TCLKA Input External clock A input pin

(Channel 1 and 5 phase counting mode A phase input) TCLKB Input External clock B input pin (Channel 1 and 5 phase counting mode B phase input) TCLKC Input External clock C input pin (Channel 2 and 4 phase counting mode A phase input) TCLKD Input External clock D input pin (Channel 2 and 4 phase counting mode B phase input)

0 TIOCA0 I/O TGRA_0 input capture input/output compare output/PWM output pin

TIOCB0 I/O TGRB_0 input capture input/output compare output/PWM output pin TIOCC0 I/O TGRC_0 input capture input/output compare output/PWM output pin TIOCD0 I/O TGRD_0 input capture input/output compare output/PWM output pin

1 TIOCA1 I/O TGRA_1 input capture input/output compare output/PWM output pin

TIOCB1 I/O TGRB_1 input capture input/output compare output/PWM output pin

2 TIOCA2 I/O TGRA_2 input capture input/output compare output/PWM output pin

TIOCB2 I/O TGRB_2 input capture input/output compare output/PWM output pin

3 TIOCA3 I/O TGRA_3 input capture input/output compare output/PWM output pin

TIOCB3 I/O TGRB_3 input capture input/output compare output/PWM output pin TIOCC3 I/O TGRC_3 input capture input/output compare output/PWM output pin TIOCD3 I/O TGRD_3 input capture input/output compare output/PWM output pin

4 TIOCA4 * I/O TGRA_4 input capture input/output compare output/PWM output pin

TIOCB4 * I/O TGRB_4 input capture input/output compare output/PWM output pin

5 TIOCA5 * I/O TGRA_5 input capture input/output compare output/PWM output pin

TIOCB5 * I/O TGRB_5 input capture input/output compare output/PWM output pin

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 259 of 804 REJ09B0104-0300 Unit Channel Symbol I/O Function

1 All TCLKE Input External clock A input pin

(Channel 7 and 11 phase counting mode A phase input) TCLKF Input External clock B input pin (Channel 7 and 11 phase counting mode B phase input) TCLKG Input External clock C input pin (Channel 8 and 10 phase counting mode A phase input) TCLKH Input External clock D input pin (Channel 8 and 10 phase counting mode B phase input)

6 TIOCA6 I/O TGRA_6 input capture input/output compare output/PWM output pin

TIOCB6 I/O TGRB_6 input capture input/output compare output/PWM output pin TIOCC6 I/O TGRC_6 input capture input/output compare output/PWM output pin TIOCD6 I/O TGRD_6 input capture input/output compare output/PWM output pin

7 TIOCA7 I/O TGRA_7 input capture input/output compare output/PWM output pin

TIOCB7 I/O TGRB_7 input capture input/output compare output/PWM output pin

8 TIOCA8 I/O TGRA_8 input capture input/output compare output/PWM output pin

TIOCB8 I/O TGRB_8 input capture input/output compare output/PWM output pin

9 TIOCA9 I/O TGRA_9 input capture input/output compare output/PWM output pin

TIOCB9 I/O TGRB_9 input capture input/output compare output/PWM output pin TIOCC9 I/O TGRC_9 input capture input/output compare output/PWM output pin TIOCD9 I/O TGRD_9 input capture input/output compare output/PWM output pin

10 TIOCA10 I/O TGRA_10 input capture input/output compare output/PWM output pin

TIOCB10 I/O TGRB_10 input capture input/output compare output/PWM output pin

11 TIOCA11 I/O TGRA_11 input capture input/output compare output/PWM output pin

TIOCB11 I/O TGRB_11 input capture input/output compare output/PWM output pin Note: * The H8SX/1527 does not have pins T IOCA4, TIOCB4, TIOCA5, and TIOCB5 for channels 4 and 5.

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 260 of 804 REJ09B0104-0300

9.3 Register Descriptions

The TPU has the following registers in each channel. The registers for unit 0 and unit 1 have the same functions except bit 7 (TTGE bit for unit 0 and reserved bit for unit 1) in TIER. This section describes unit 0 registers. Unit 0

• Channel 0: Timer control register_0 (TCR_0) Timer mode register_0 (TMDR_0) Timer I/O control register H_0 (TIORH_0) Timer I/O control register L_0 (TIORL_0) Timer interrupt enable register_0 (TIER_0) Timer status register_0 (TSR_0) Timer counter_0 (TCNT_0) Timer general register A_0 (TGRA_0) Timer general register B_0 (TGRB_0) Timer general register C_0 (TGRC_0) Timer general register D_0 (TGRD_0)
• Channel 1: Timer control register_1 (TCR_1) Timer mode register_1 (TMDR_1) Timer I/O control register _1 (TIOR_1) Timer interrupt enable register_1 (TIER_1) Timer status register_1 (TSR_1) Timer counter_1 (TCNT_1) Timer general register A_1 (TGRA_1) Timer general register B_1 (TGRB_1)

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 261 of 804 REJ09B0104-0300

• Channel 2: Timer control register_2 (TCR_2) Timer mode register_2 (TMDR_2) Timer I/O control register_2 (TIOR_2) Timer interrupt enable register_2 (TIER_2) Timer status register_2 (TSR_2) Timer counter_2 (TCNT_2) Timer general register A_2 (TGRA_2) Timer general register B_2 (TGRB_2)
• Channel 3: Timer control register_3 (TCR_3) Timer mode register_3 (TMDR_3) Timer I/O control register H_3 (TIORH_3) Timer I/O control register L_3 (TIORL_3) Timer interrupt enable register_3 (TIER_3) Timer status register_3 (TSR_3) Timer counter_3 (TCNT_3) Timer general register A_3 (TGRA_3) Timer general register B_3 (TGRB_3) Timer general register C_3 (TGRC_3) Timer general register D_3 (TGRD_3)
• Channel 4: Timer control register_4 (TCR_4) Timer mode register_4 (TMDR_4) Timer I/O control register _4 (TIOR_4) Timer interrupt enable register_4 (TIER_4) Timer status register_4 (TSR_4) Timer counter_4 (TCNT_4) Timer general register A_4 (TGRA_4) Timer general register B_4 (TGRB_4)

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 262 of 804 REJ09B0104-0300

• Channel 5: Timer control register_5 (TCR_5) Timer mode register_5 (TMDR_5) Timer I/O control register_5 (TIOR_5) Timer interrupt enable register_5 (TIER_5) Timer status register_5 (TSR_5) Timer counter_5 (TCNT_5) Timer general register A_5 (TGRA_5) Timer general register B_5 (TGRB_5)
• Common Registers Timer start register (TSTR) Timer synchronous register (TSYR) Unit 1
• Channel 6: Timer control register_6 (TCR_6) Timer mode register_6 (TMDR_6) Timer I/O control register H_6 (TIORH_6) Timer I/O control register L_6 (TIORL_6) Timer interrupt enable register_6 (TIER_6) Timer status register_6 (TSR_6) Timer counter_6 (TCNT_6) Timer general register A_6 (TGRA_6) Timer general register B_6 (TGRB_6) Timer general register C_6 (TGRC_6) Timer general register D_6 (TGRD_6)

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 263 of 804 REJ09B0104-0300

• Channel 7: Timer control register_7 (TCR_7) Timer mode register_7 (TMDR_7) Timer I/O control register _7 (TIOR_7) Timer interrupt enable register_7 (TIER_7) Timer status register_7 (TSR_7) Timer counter_7 (TCNT_7) Timer general register A_7 (TGRA_7) Timer general register B_7 (TGRB_7)
• Channel 8: Timer control register_8 (TCR_8) Timer mode register_8 (TMDR_8) Timer I/O control register_8 (TIOR_8) Timer interrupt enable register_8 (TIER_8) Timer status register_8 (TSR_8) Timer counter_8 (TCNT_8) Timer general register A_8 (TGRA_8) Timer general register B_8 (TGRB_8)
• Channel 9: Timer control register_9 (TCR_9) Timer mode register_9 (TMDR_9) Timer I/O control register H_9 (TIORH_9) Timer I/O control register L_9 (TIORL_9) Timer interrupt enable register_9 (TIER_9) Timer status register_9 (TSR_9) Timer counter_9 (TCNT_9) Timer general register A_9 (TGRA_9) Timer general register B_9 (TGRB_9) Timer general register C_9 (TGRC_9) Timer general register D_9 (TGRD_9)

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 264 of 804 REJ09B0104-0300

• Channel 10: Timer control register_10 (TCR_10) Timer mode register_10 (TMDR_10) Timer I/O control register _10 (TIOR_10) Timer interrupt enable register_10 (TIER_10) Timer status register_10 (TSR_10) Timer counter_10 (TCNT_10) Timer general register A_10 (TGRA_10) Timer general register B_10 (TGRB_10)
• Channel 11: Timer control register_11 (TCR_11) Timer mode register_11 (TMDR_11) Timer I/O control register_11 (TIOR_11) Timer interrupt enable register_11 (TIER_11) Timer status register_11 (TSR_11) Timer counter_11 (TCNT_11) Timer general register A_11 (TGRA_11) Timer general register B_11 (TGRB_11)
• Common Registers Timer start register (TSTRB) Timer synchronous register (TSYRB)

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 265 of 804 REJ09B0104-0300

9.3.1 Timer Control Register (TCR)

TCR controls the TCNT operation for each channel. The TPU has a total of six TCR registers, one for each channel. TCR register settings should be made only while TCNT operation is stopped. CCLR2 R/W CCLR1 R/W CCLR0 R/W CKEG1 R/W CKEG0 R/W TPSC2 R/W TPSC1 R/W TPSC0 R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description CCLR2 CCLR1 CCLR0 R/W R/W R/W Counter Clear 2 to 0 These bits select the TCNT counter clearing source. See tables 9.5 and 9.6 for details. CKEG1 CKEG0 R/W R/W Clock Edge 1 and 0 These bits select the input clock edge. For details, see table 9.7. When the input clock is counted using both edges, the input clock period is halved (e.g. Pφ/4 both edges = Pφ/2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority. Internal clock edge selection is valid when the input clock is Pφ/4 or slower. This setting is ignored if the input clock is Pφ/1, or when overflow/underflow of another channel is selected. TPSC2 TPSC1 TPSC0 R/W R/W R/W Timer Prescaler 2 to 0 These bits select the TCNT counter clock. The clock source can be selected independently for each channel. See tables 9.8 to 9.13 for details. To select the external clock as the clock source, the DDR bit and ICR bit for the corresponding pin should be set to 0 and 1, respectively. For details, see section 8, I/O Ports.

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 266 of 804 REJ09B0104-0300 Table 9.5 CCLR2 to CCLR0 (Channels 0 and 3) Channel Bit 7 CCLR2 Bit 6 CCLR1 Bit 5 CCLR0 Description 0 0 0 TCNT clearing disabled 0 0 1 TCNT cleared by TGRA compare match/input capture 0 1 0 TCNT cleared by TGRB compare match/input capture 0 1 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation* 1 0 0 TCNT clearing disabled 1 0 1 TCNT cleared by TGRC compare match/input capture* 1 1 0 TCNT cleared by TGRD compare match/input capture* 0, 3 1 1 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation* Notes: 1. Synchronous operation is select ed by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer re gister, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. Table 9.6 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5) Channel Bit 7* Reserved Bit 6 CCLR1 Bit 5 CCLR0 Description 0 0 0 TCNT clearing disabled 0 0 1 TCNT cleared by TGRA compare match/input capture 0 1 0 TCNT cleared by TGRB compare match/input capture 1, 2, 4, 5 0 1 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation* Notes: 1. Synchronous operation is select ed by setting the SYNC bit in TSYR to 1. 2. Bit 7 is reserved in channels 1, 2, 4, and 5. It is a read-only bit and cannot be modified.

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 267 of 804 REJ09B0104-0300 Table 9.7 Input Clock Edge Selection Clock Edge Selection Input Clock CKEG1 CKEG0 Internal Clock External Clock 0 0 Counted at falling edge Counted at rising edge 0 1 Counted at rising edge Counted at falling edge

1 X Counted at both edges Counted at both edges

[Legend] X: Don't care Table 9.8 TPSC2 to TPSC0 (Channel 0) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 0 0 0 Internal clock: counts on P φ/1 0 0 1 Internal clock: counts on P φ/4 0 1 0 Internal clock: counts on P φ/16 0 1 1 Internal clock: counts on P φ/64 1 0 0 External clock: counts on TCLKA pin input 1 0 1 External clock: counts on TCLKB pin input 1 1 0 External clock: counts on TCLKC pin input 1 1 1 External clock: counts on TCLKD pin input Table 9.9 TPSC2 to TPSC0 (Channel 1) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 0 0 0 Internal clock: counts on P φ/1 0 0 1 Internal clock: counts on P φ/4 0 1 0 Internal clock: counts on P φ/16 0 1 1 Internal clock: counts on P φ/64 1 0 0 External clock: counts on TCLKA pin input 1 0 1 External clock: counts on TCLKB pin input 1 1 0 Internal clock: counts on P φ/256 1 1 1 Counts on TCNT2 overflow/underflow Note: This setting is ignored when channel 1 is in phase counting mode.

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 268 of 804 REJ09B0104-0300 Table 9.10 TPSC2 to TPSC0 (Channel 2) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 0 0 0 Internal clock: counts on P φ/1 0 0 1 Internal clock: counts on P φ/4 0 1 0 Internal clock: counts on P φ/16 0 1 1 Internal clock: counts on P φ/64 1 0 0 External clock: counts on TCLKA pin input 1 0 1 External clock: counts on TCLKB pin input 1 1 0 External clock: counts on TCLKC pin input 1 1 1 Internal clock: counts on P φ/1024 Note: This setting is ignored when channel 2 is in phase counting mode. Table 9.11 TPSC2 to TPSC0 (Channel 3) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 0 0 0 Internal clock: counts on P φ/1 0 0 1 Internal clock: counts on P φ/4 0 1 0 Internal clock: counts on P φ/16 0 1 1 Internal clock: counts on P φ/64 1 0 0 External clock: counts on TCLKA pin input 1 0 1 Internal clock: counts on P φ/1024 1 1 0 Internal clock: counts on P φ/256 1 1 1 Internal clock: counts on P φ/4096

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 269 of 804 REJ09B0104-0300 Table 9.12 TPSC2 to TPSC0 (Channel 4) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 0 0 0 Internal clock: counts on P φ/1 0 0 1 Internal clock: counts on P φ/4 0 1 0 Internal clock: counts on P φ/16 0 1 1 Internal clock: counts on P φ/64 1 0 0 External clock: counts on TCLKA pin input 1 0 1 External clock: counts on TCLKC pin input 1 1 0 Internal clock: counts on P φ/1024 1 1 1 Counts on TCNT5 overflow/underflow Note: This setting is ignored when channel 4 is in phase counting mode. Table 9.13 TPSC2 to TPSC0 (Channel 5) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 0 0 0 Internal clock: counts on P φ/1 0 0 1 Internal clock: counts on P φ/4 0 1 0 Internal clock: counts on P φ/16 0 1 1 Internal clock: counts on P φ/64 1 0 0 External clock: counts on TCLKA pin input 1 0 1 External clock: counts on TCLKC pin input 1 1 0 Internal clock: counts on P φ/256 1 1 1 External clock: counts on TCLKD pin input Note: This setting is ignored when channel 5 is in phase counting mode.

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 270 of 804 REJ09B0104-0300

9.3.2 Timer Mode Register (TMDR)

TMDR sets the operating mode for each channel. The TPU has six TMDR registers, one for each channel. TMDR register settings should be made only while TCNT operation is stopped. R R BFB R/W BFA R/W MD3 R/W MD2 R/W MD1 R/W MD0 R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description 7, 6  All 1 R Reserved These are read-only bits and cannot be modified.

5 BFB 0 R/W Buffer Operation B

Specifies whether TGRB is to normally operate, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is reserved. It is a read-only bit and cannot be modified. 0: TGRB operates normally 1: TGRB and TGRD used together for buffer operation

4 BFA 0 R/W Buffer Operation A

Specifies whether TGRA is to normally operate, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved. It is a read-only bit and cannot be modified. 0: TGRA operates normally 1: TGRA and TGRC used together for buffer operation MD3 MD2 MD1 MD0 R/W R/W R/W R/W Modes 3 to 0 Set the timer operating mode. MD3 is a reserved bit. The write value should always be 0. See table 9.14 for details.

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 271 of 804 REJ09B0104-0300 Table 9.14 MD3 to MD0 Bit 3 MD3 * Bit 2 MD2 * Bit 1 MD1 Bit 0 MD0 Description 0 0 0 0 Normal operation 0 0 0 1 Reserved 0 0 1 0 PWM mode 1 0 0 1 1 PWM mode 2 0 1 0 0 Phase counting mode 1 0 1 0 1 Phase counting mode 2 0 1 1 0 Phase counting mode 3 0 1 1 1 Phase counting mode 4

1 X X X 

[Legend] X: Don't care Notes: 1. MD3 is a reserved bit. The write value should always be 0. 2. Phase counting mode cannot be set for channel s 0 and 3. In this case, the write value should always be 0.

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 272 of 804 REJ09B0104-0300

9.3.3 Timer I/O Control Register (TIOR)

TIOR controls TGR. The TPU has eight TIOR registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5. Care is required since TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. To designate the input capture pin in TIOR, the DDR bit and ICR bit for the corresponding pin should be set to 0 and 1, respectively. For details, see section 8, I/O Ports. Note: The H8SX/1527 does not include TIOR_4 and TIOR_5.

• TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5 IOB3 R/W IOB2 R/W IOB1 R/W IOB0 R/W IOA3 R/W IOA2 R/W IOA1 R/W IOA0 R/W Bit Bit Name Initial Value R/W
• TIORL_0, TORL_3 IOD3 R/W IOD2 R/W IOD1 R/W IOD0 R/W IOC3 R/W IOC2 R/W IOC1 R/W IOC0 R/W Bit Bit Name Initial Value R/W

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 273 of 804 REJ09B0104-0300

• TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5 Bit Bit Name Initial Value R/W Description IOB3 IOB2 IOB1 IOB0 R/W R/W R/W R/W I/O Control B3 to B0 Specify the function of TGRB. 9.22. IOA3 IOA2 IOA1 IOA0 R/W R/W R/W R/W I/O Control A3 to A0 Specify the function of TGRA. 9.30.
• TIORL_0, TIORL_3: Bit Bit Name Initial Value R/W Description IOD3 IOD2 IOD1 IOD0 R/W R/W R/W R/W I/O Control D3 to D0 Specify the function of TGRD. For details, see tables 9.16, and 9.20. IOC3 IOC2 IOC1 IOC0 R/W R/W R/W R/W I/O Control C3 to C0 Specify the function of TGRC. For details, see tables 9.24, and 9.28.

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 274 of 804 REJ09B0104-0300 Table 9.15 TIORH_0

Description

TGRB_0 Function TIOCB0 Pin Function 0 0 0 0 Output disabled 0 0 0 1 Initial output is 0 output 0 output at compare match 0 0 1 0 Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCB0 pin Input capture at rising edge 1 0 0 1 Capture input source is TIOCB0 pin Input capture at falling edge 1 0 1 x Capture input source is TIOCB0 pin Input capture at both edges 1 1 x x Input capture register Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down* [Legend] X: Don't care Note: When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and P φ/1 is used as the TCNT_1 count clock, this setting is invalid and input capture is not generated.

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 275 of 804 REJ09B0104-0300 Table 9.16 TIORL_0 TGRD_0 Function TIOCD0 Pin Function 0 0 0 0 Output disabled 0 0 0 1 Initial output is 0 output 0 output at compare match 0 0 1 0 Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register* Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCD0 pin Input capture at rising edge 1 0 0 1 Capture input source is TIOCD0 pin Input capture at falling edge 1 0 1 X Capture input source is TIOCD0 pin Input capture at both edges 1 1 X X Input capture register* Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down* [Legend] X: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and P φ/1 is used as the TCNT_1 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 276 of 804 REJ09B0104-0300 Table 9.17 TIOR_1 TGRB_1 Function TIOCB1 Pin Function 0 0 0 0 Output disabled 0 0 0 1 Initial output is 0 output 0 output at compare match 0 0 1 0 Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCB1 pin Input capture at rising edge 1 0 0 1 Capture input source is TIOCB1 pin Input capture at falling edge 1 0 1 X Capture input source is TIOCB1 pin Input capture at both edges 1 1 X X Input capture register TGRC_0 compare match/input capture Input capture at generation of TGRC_0 compare match/input capture [Legend] X: Don't care

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 277 of 804 REJ09B0104-0300 Table 9.18 TIOR_2 TGRB_2 Function TIOCB2 Pin Function 0 0 0 0 Output disabled 0 0 0 1 Initial output is 0 output 0 output at compare match 0 0 1 0 Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match

1 X 0 0 Capture input source is TIOCB2 pin

Input capture at rising edge

1 X 0 1 Capture input source is TIOCB2 pin

Input capture at falling edge

1 X 1 X

Capture input source is TIOCB2 pin Input capture at both edges [Legend] X: Don't care

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 278 of 804 REJ09B0104-0300 Table 9.19 TIORH_3 TGRB_3 Function TIOCB3 Pin Function 0 0 0 0 Output disabled 0 0 0 1 Initial output is 0 output 0 output at compare match 0 0 1 0 Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCB3 pin Input capture at rising edge 1 0 0 1 Capture input source is TIOCB3 pin Input capture at falling edge 1 0 1 x Capture input source is TIOCB3 pin Input capture at both edges 1 1 x x Input capture register Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down* [Legend] X: Don't care Note: When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and P φ/1 is used as the TCNT_4 count clock, this setting is invalid and input capture is not generated.

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 279 of 804 REJ09B0104-0300 Table 9.20 TIORL_3 TGRD_3 Function TIOCD3 Pin Function 0 0 0 0 Output disabled 0 0 0 1 Initial output is 0 output 0 output at compare match 0 0 1 0 Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register* Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCD3 pin Input capture at rising edge 1 0 0 1 Capture input source is TIOCD3 pin Input capture at falling edge 1 0 1 x Capture input source is TIOCD3 pin Input capture at both edges 1 1 x x Input capture register* Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down* [Legend] X: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and P φ/1 is used as the TCNT_4 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 280 of 804 REJ09B0104-0300 Table 9.21 TIOR_4 TGRB_4 Function TIOCB4 Pin Function 0 0 0 0 Output disabled 0 0 0 1 Initial output is 0 output 0 output at compare match 0 0 1 0 Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCB4 pin Input capture at rising edge 1 0 0 1 Capture input source is TIOCB4 pin Input capture at falling edge 1 0 1 x Capture input source is TIOCB4 pin Input capture at both edges 1 1 x x Input capture register Capture input source is TGRC_3 compare match/input capture Input capture at generation of TGRC_3 compare match/input capture [Legend] X: Don't care

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 281 of 804 REJ09B0104-0300 Table 9.22 TIOR_5 TGRB_5 Function TIOCB5 Pin Function 0 0 0 0 Output disabled 0 0 0 1 Initial output is 0 output 0 output at compare match 0 0 1 0 Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 1 x 0 0 Capture input source is TIOCB5 pin Input capture at rising edge 1 x 0 1 Capture input source is TIOCB5 pin Input capture at falling edge 1 x 1 x Input capture register Capture input source is TIOCB5 pin Input capture at both edges [Legend] X: Don't care

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 282 of 804 REJ09B0104-0300 Table 9.23 TIORH_0 TGRA_0 Function TIOCA0 Pin Function 0 0 0 0 Output disabled 0 0 0 1 Initial output is 0 output 0 output at compare match 0 0 1 0 Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 1 0 0 1 Capture input source is TIOCA0 pin Input capture at rising edge 1 0 0 0 Capture input source is TIOCA0 pin Input capture at rising edge 1 0 1 X Capture input source is TIOCA0 pin Input capture at both edges 1 1 X X Input capture register Capture input source is channel 1/count clock Input capture* at TCNT_1 count-up/count-down [Legend] X: Don't care Note: * When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and P φ/1 is used as the TCNT_1 counter clock, this setting is ignored and an input capture interrupt is not generated.

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 283 of 804 REJ09B0104-0300 Table 9.24 TIORL_0 TGRC_0 Function TIOCC0 Pin Function 0 0 0 0 Output disabled 0 0 0 1 Initial output is 0 output 0 output at compare match 0 0 1 0 Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register* Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCC0 pin Input capture at rising edge 1 0 0 1 Capture input source is TIOCC0 pin Input capture at falling edge 1 0 1 X Capture input source is TIOCC0 pin Input capture at both edges 1 1 X X Input capture register* Capture input source is channel 1/count clock Input capture* at TCNT_1 count-up/count-down [Legend] X: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and P φ/1 is used as the TCNT_1 counter clock, this setting is ignored and an input capture interrupt is not generated. 2. When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 284 of 804 REJ09B0104-0300 Table 9.25 TIOR_1 TGRA_1 Function TIOCA1 Pin Function 0 0 0 0 Output disabled 0 0 0 1 Initial output is 0 output 0 output at compare match 0 0 1 0 Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCA1 pin Input capture at rising edge 1 0 0 1 Capture input source is TIOCA1 pin Input capture at falling edge 1 0 1 X Capture input source is TIOCA1 pin Input capture at both edges 1 1 X X Input capture register Capture input source is TGRA_0 compare match/input capture Input capture at generation of channel 0/TGRA_0 compare match/input capture [Legend] X: Don't care

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 285 of 804 REJ09B0104-0300 Table 9.26 TIOR_2 TGRA_2 Function TIOCA2 Pin Function 0 0 0 0 Output disabled 0 0 0 1 Initial output is 0 output 0 output at compare match 0 0 1 0 Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match

1 X 0 0 Capture input source is TIOCA2 pin

Input capture at rising edge

1 X 0 1 Capture input source is TIOCA2 pin

Input capture at falling edge Capture input source is TIOCA2 pin Input capture at both edges [Legend] X: Don't care

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 286 of 804 REJ09B0104-0300 Table 9.27 TIORH_3 TGRA_3 Function TIOCA3 Pin Function 0 0 0 0 Output disabled 0 0 0 1 Initial output is 0 output 0 output at compare match 0 0 1 0 Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCA3 pin Input capture at rising edge 1 0 0 1 Capture input source is TIOCA3 pin Input capture at falling edge 1 0 1 X Capture input source is TIOCA3 pin Input capture at both edges 1 1 X X Input capture register Capture input source is channel 4/count clock Input capture* at TCNT_4 count-up/count-down [Legend] X: Don't care Note: * When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and P φ/1 is used as the TCNT_4 counter clock, this setting is ignored and an input capture interrupt is not generated.

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 287 of 804 REJ09B0104-0300 Table 9.28 TIORL_3 TGRC_3 Function TIOCC3 Pin Function 0 0 0 0 Output disabled 0 0 0 1 Initial output is 0 output 0 output at compare match 0 0 1 0 Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register* Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCC3 pin Input capture at rising edge 1 0 0 1 Capture input source is TIOCC3 pin Input capture at falling edge 1 0 1 X Capture input source is TIOCC3 pin Input capture at both edges 1 1 X X Input capture register* Capture input source is channel 4/count clock Input capture* at TCNT_4 count-up/count-down [Legend] X: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and P φ/1 is used as the TCNT_4 counter clock, this setting is ignored and an input capture interrupt is not generated. 2. When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 288 of 804 REJ09B0104-0300 Table 9.29 TIOR_4 TGRA_4 Function TIOCA4 Pin Function 0 0 0 0 Output disabled 0 0 0 1 Initial output is 0 output 0 output at compare match 0 0 1 0 Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCA4 pin Input capture at rising edge 1 0 0 1 Capture input source is TIOCA4 pin Input capture at falling edge 1 0 1 X Capture input source is TIOCA4 pin Input capture at both edges 1 1 X X Input capture register Capture input source is TGRA_3 compare match/input capture Input capture at generation of TGRA_3 compare match/input capture [Legend] X: Don't care

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 289 of 804 REJ09B0104-0300 Table 9.30 TIOR_5 TGRA_5 Function TIOCA5 Pin Function 0 0 0 0 Output disabled 0 0 0 1 Initial output is 0 output 0 output at compare match 0 0 1 0 Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match

1 X 0 0 Input capture source is TIOCA5 pin

Input capture at rising edge

1 X 0 1 Input capture source is TIOCA5 pin

Input capture at falling edge Input capture source is TIOCA5 pin Input capture at both edges [Legend] X: Don't care

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 290 of 804 REJ09B0104-0300

9.3.4 Timer Interrupt En able Register (TIER)

TIER controls enabling or disabling of interrupt requests for each channel. The TPU has six TIER registers, one for each channel. Bit Bit Name Initial Value R/W TTGE* R/W R TCIEU R/W TCIEV R/W TGIED R/W TGIEC R/W TGIEB R/W TGIEA R/W Note: * Bit 7 in TIER for unit 1 is a reserved bit and is always read as 0. The write value should always be 0. Bit Bit Name Initial value R/W Description

7 TTGE * 0 R/W A/D Conversion Start Request Enable

Enables/disables generation of A/D conversion start requests by TGRA input capture/compare match. 0: A/D conversion start request generation disabled 1: A/D conversion start request generation enabled 6  1 R Reserved This is a read-only bit and cannot be modified.

5 TCIEU 0 R/W Underflow Interrupt Enable

Enables/disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1, 2, 4, and 5. In channels 0 and 3, bit 5 is reserved. It is a read-only bit and cannot be modified. 0: Interrupt requests (TCIU) by TCFU disabled 1: Interrupt requests (TCIU) by TCFU enabled

4 TCIEV 0 R/W Overflow Interrupt Enable

Enables/disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. 0: Interrupt requests (TCIV) by TCFV disabled 1: Interrupt requests (TCIV) by TCFV enabled

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 291 of 804 REJ09B0104-0300 Bit Bit Name Initial value R/W Description

3 TGIED 0 R/W TGR Interrupt Enable D

Enables/disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is a read- only bit and cannot be modified. 0: Interrupt requests (TGID) by TGFD bit disabled 1: Interrupt requests (TGID) by TGFD bit enabled

2 TGIEC 0 R/W TGR Interrupt Enable C

Enables/disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is a read- only bit and cannot be modified. 0: Interrupt requests (TGIC) by TGFC bit disabled 1: Interrupt requests (TGIC) by TGFC bit enabled

1 TGIEB 0 R/W TGR Interrupt Enable B

Enables/disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. 0: Interrupt requests (TGIB) by TGFB bit disabled 1: Interrupt requests (TGIB) by TGFB bit enabled

0 TGIEA 0 R/W TGR Interrupt Enable A

Enables/disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. 0: Interrupt requests (TGIA) by TGFA bit disabled 1: Interrupt requests (TGIA) by TGFA bit enabled Note: * Bit 7 in TIER for unit 1 is a reserved bit and is always read as 0. The write value should always be 0.

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 292 of 804 REJ09B0104-0300

9.3.5 Timer Status Register (TSR)

TSR indicates the status of each channel. The TPU has six TSR registers, one for each channel. Bit Bit Name Initial Value R/W TCFD R R TCFU R/(W)* TCFV R/(W)* TGFD R/(W)* TGFC R/(W)* TGFB R/(W)* TGFA R/(W)* Note: * Only 0 can be written to bits 5 to 0, to clear flags. Bit Bit Name Initial value R/W Description

7 TCFD 1 R Count Direction Flag

Status flag that shows the direction in which TCNT counts in channels 1, 2, 4, and 5. In channels 0 and 3, bit 7 is reserved. It is a read-only bit and cannot be modified. 0: TCNT counts down 1: TCNT counts up 6  1 R Reserved This is a read-only bit and cannot be modified.

5 TCFU 0 R/(W) * Underflow Flag

Status flag that indicates that a TCNT underflow has occurred when channels 1, 2, 4, and 5 are set to phase counting mode. In channels 0 and 3, bit 5 is reserved. It is a read-only bit and cannot be modified. [Setting condition]

• When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition]
• When a 0 is written to TCFU after reading TCFU = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 293 of 804 REJ09B0104-0300 Bit Bit Name Initial value R/W Description

4 TCFV 0 R/(W) * Overflow Flag

Status flag that indicates that a TCNT overflow has occurred. [Setting condition]

• When the TCNT value overflows (changes from H'FFFF to H'0000) [Clearing condition]
• When a 0 is written to TCFV after reading TCFV = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)

3 TGFD 0 R/(W) * Input Capture/Output Compare Flag D

Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is a read- only bit and cannot be modified. [Setting conditions]

• When TCNT = TGRD while TGRD is functioning as output compare register
• When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register [Clearing conditions]
• When 0 is written to TGFD after reading TGFD = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 294 of 804 REJ09B0104-0300 Bit Bit Name Initial value R/W Description

2 TGFC 0 R/(W) * Input Capture/Output Compare Flag C

Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is a read- only bit and cannot be modified. [Setting conditions]

• When TCNT = TGRC while TGRC is functioning as output compare register
• When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register [Clearing conditions] When 0 is written to TGFC after reading TGFC = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)

1 TGFB 0 R/(W) * Input Capture/Output Compare Flag B

Status flag that indicates the occurrence of TGRB input capture or compare match. [Setting conditions]

• When TCNT = TGRB while TGRB is functioning as output compare register
• When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register [Clearing conditions]
• When 0 is written to TGFB after reading TGFB = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 295 of 804 REJ09B0104-0300 Bit Bit Name Initial value R/W Description

0 TGFA 0 R/(W) * Input Capture/Output Compare Flag A

Status flag that indicates the occurrence of TGRA input capture or compare match. [Setting conditions]

• When TCNT = TGRA while TGRA is functioning as output compare register
• When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register [Clearing conditions]
• When DMAC is activated by a TGIA interrupt while the DTA bit in DMDR of DMAC is 1
• When 0 is written to TGFA after reading TGFA = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Note: * Only 0 can be written to clear the flag.

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 296 of 804 REJ09B0104-0300

9.3.6 Timer Counter (TCNT)

TCNT is a 16-bit readable/writable counter. The TPU has six TCNT counters, one for each channel. TCNT is initialized to H'0000 by a reset or in hardware standby mode. TCNT cannot be accessed in 8-bit units. TCNT must always be accessed in 16-bit units. Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W

9.3.7 Timer General Register (TGR)

TGR is a 16-bit readable/writable register with a dual function as output compare and input capture registers. The TPU has 16 TGR registers, four each for channels 0 and 3 and two each for channels 1, 2, 4, and 5. TGRC and TGRD for channels 0 and 3 can also be designated for operation as buffer registers. The TGR registers cannot be accessed in 8-bit units; they must always be accessed in 16-bit units. TGR and buffer register combinations during buffer operations are TGRA −TGRC and TGRB −TGRD. Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W

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9.3.8 Timer Start Register (TSTR)

TSTR starts or stops operation for channels 0 to 5. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. R/W R/W CST5 R/W CST4 R/W CST3 R/W CST2 R/W CST1 R/W CST0 R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial value R/W Description 7, 6  All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. CST5 CST4 CST3 CST2 CST1 CST0 R/W R/W R/W R/W R/W R/W Counter Start 5 to 0 These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_5 to TCNT_0 count operation is stopped 1: TCNT_5 to TCNT_0 performs count operation

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9.3.9 Timer Synchronous Register (TSYR)

TSYR selects independent operation or synchronous operation for the TCNT counters of channels 0 to 5. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. R/W R/W SYNC5 R/W SYNC4 R/W SYNC3 R/W SYNC2 R/W SYNC1 R/W SYNC0 R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial value R/W Description 7, 6  All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 R/W R/W R/W R/W R/W R/W Timer Synchronization 5 to 0 These bits select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, synchronous presetting of multiple channels, and synchronous clearing through counter clearing on another channel are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR. 0: TCNT_5 to TCNT_0 operate independently (TCNT presetting/clearing is unrelated to other channels) 1: TCNT_5 to TCNT_0 perform synchronous operation (TCNT synchronous presetting/synchronous clearing is possible)

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9.4 Operation

9.4.1 Basic Functions

Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, periodic counting, and external event counting. Each TGR can be used as an input capture register or output compare register. (1) Counter Operation When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on. (a) Example of count operation setting procedure Figure 9.3 shows an example of the count operation setting procedure. Select counter clock Operation selection Select counter clearing source Periodic counter Set period Start count <Periodic counter> [1] [2] [4] [3] [5] Free-running counter Start count <Free-running counter> [5] [1] [2] [3] [4] [5] Select output compare register Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. Designate the TGR selected in [2] as an output compare register by means of TIOR. Set the periodic counter cycle in the TGR selected in [2]. Set the CST bit in TSTR to 1 to start the counter operation. Figure 9.3 Example of Counter Operation Setting Procedure

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9.4.2 Synchronous Operation

In synchronous operation, the values in multiple TCNT counters can be rewritten simultaneously (synchronous presetting). Also, multiple TCNT counters can be cleared simultaneously (synchronous clearing) by making the appropriate setting in TCR. Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 5 can all be designated for synchronous operation. (1) Example of Synchronous Operation Setting Procedure Figure 9.11 shows an example of the synchronous operation setting procedure. Synchronous operation selection Set TCNT Synchronous presetting <Synchronous presetting> [1] [2] Synchronous clearing Select counter clearing source <Counter clearing> [3] Start count [5] Set synchronous counter clearing <Synchronous clearing> [4] Start count [5] Clearing source generation channel? No Yes [1] Set the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation to 1. [2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. [3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. [4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. [5] Set the CST bits in TSTR for the relevant channels to 1, to start the count operation. Set synchronous operation Figure 9.11 Example of Synchronous Operation Setting Procedure

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9.4.3 Buffer Operation

Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or a compare match register. Table 9.31 shows the register combinations used in buffer operation. Table 9.31 Register Combinations in Buffer Operation Channel Timer General Re gister Buffer Register TGRA_0 TGRC_0 0 TGRB_0 TGRD_0 TGRA_3 TGRC_3 3 TGRB_3 TGRD_3

• When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 9.13. Buffer register Timer general register TCNTComparator Compare match signal Figure 9.13 Compare Match Buffer Operation

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9.4.4 Cascaded Operation

In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4) counter clock at overflow/underflow of TCNT_2 (TCNT_5) as set in bits TPSC2 to TPSC0 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 9.32 shows the register combinations used in cascaded operation. Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid and the counter operates independently in phase counting mode. Table 9.32 Cascaded Combinations Combination Upper 16 Bits Lower 16 Bits Channels 1 and 2 TCNT_1 TCNT_2 Channels 4 and 5 TCNT_4 TCNT_5 (1) Example of Cascaded Operation Setting Procedure Figure 9.18 shows an example of the setting procedure for cascaded operation. Cascaded operation Set cascading Start count <Cascaded operation> Set bits TPSC2 to TPSC0 in the channel 1 (channel 4) TCR to B'1111 to select TCNT_2 (TCNT_5) overflow/underflow counting. Set the CST bit in TSTR for the upper and lower channels to 1 to start the count operation. [1] [2] [1] [2] Figure 9.18 Example of Cascaded Operation Setting Procedure

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9.4.5 PWM Modes

In PWM mode, PWM waveforms are output from the output pins. 0-, 1-, or toggle-output can be selected as the output level in response to compare match of each TGR. Settings of TGR registers can output a PWM waveform in the range of 0% to 100% duty cycle. Designating TGR compare match as the counter clearing source enables the cycle to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below. (1) PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The outputs specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR are output from the TIOCA and TIOCC pins at compare matches A and C, respectively. The outputs specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR are output at compare matches B and D, respectively. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 8-phase PWM output is possible.

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 314 of 804 REJ09B0104-0300 (2) PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty cycle registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a cycle register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty cycle registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 15-phase PWM output is possible by combined use with synchronous operation. The correspondence between PWM output pins and registers is shown in table 9.33. Table 9.33 PWM Output Registers and Output Pins Output Pins Channel Registers PWM Mode 1 PWM Mode 2 TGRA_0 TIOCA0 TGRB_0 TIOCA0 TIOCB0 TGRC_0 TIOCC0 TGRD_0 TIOCC0 TIOCD0 TGRA_1 TIOCA1 1 TGRB_1 TIOCA1 TIOCB1 TGRA_2 TIOCA2 2 TGRB_2 TIOCA2 TIOCB2 TGRA_3 TIOCA3 TGRB_3 TIOCA3 TIOCB3 TGRC_3 TIOCC3 TGRD_3 TIOCC3 TIOCD3 TGRA_4 TIOCA4 4 TGRB_4 TIOCA4 TIOCB4 TGRA_5 TIOCA5 5 TGRB_5 TIOCA5 TIOCB5 Note: In PWM mode 2, PWM output is not possible fo r the TGR register in which the cycle is set.

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9.4.6 Phase Counting Mode

In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be used. This can be used for two-phase encoder pulse input. When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow occurs while TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of whether TCNT is counting up or down. Table 9.34 shows the correspondence between external clock pins and channels. Table 9.34 Clock Input Pins in Phase Counting Mode External Clock Pins Channels A-Phase B-Phase When channel 1 or 5 is set to phase counting mode TCLKA TCLKB When channel 2 or 4 is set to phase counting mode TCLKC TCLKD

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 324 of 804 REJ09B0104-0300 (3) Phase Counting Mode Application Example Figure 9.30 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB. Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and TGRC_0 are used for the compare match function and are set with the speed control cycle and position control cycle. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture source, and the pulse width of 2-phase encoder 4-multiplication pulses is detected. TGRA_1 and TGRB_1 for channel 1 are designated for input capture, channel 0 TGRA_0 and TGRC_0 compare matches are selected as the input capture source, and the up/down-counter values for the control cycles are stored. This procedure enables accurate position/speed detection to be achieved.

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 325 of 804 REJ09B0104-0300 TCNT_1 TCNT_0 Channel 1 TGRA_1 (speed cycle capture) TGRA_0 (speed control cycle) TGRB_1 (position cycle capture) TGRC_0 (position control cycle) TGRB_0 (pulse width capture) TGRD_0 (buffer operation) Channel 0 TCLKA TCLKB Edge detection circuit Figure 9.30 Phase Counting Mode Application Example

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9.5 Interrupt Sources

There are three kinds of TPU interrupt sources: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disable bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priority levels can be changed by the interrupt controller, but the priority within a channel is fixed. For details, see section 5, Interrupt Controller. Table 9.39 lists the TPU interrupt sources. Table 9.39 TPU Interrupts Channel Name Interrupt Source Interrupt Flag DMAC Activation

0 TGI0A TGRA_0 input capture/compare match TGFA_0 Possible

TGI0B TGRB_0 input capture/compare match TGFB_0 Not possible TGI0C TGRC_0 input capture/compare match TGFC_0 Not possible TGI0D TGRD_0 input capture/compare match TGFD_0 Not possible TCI0V TCNT_0 overflow TCFV_0 Not possible

1 TGI1A TGRA_1 input capture/compare match TGFA_1 Possible

TGI1B TGRB_1 input capture/compare match TGFB_1 Not possible TCI1V TCNT_1 overflow TCFV_1 Not possible TCI1U TCNT_1 underflow TCFU_1 Not possible

2 TGI2A TGRA_2 input capture/compare match TGFA_2 Possible

TGI2B TGRB_2 input capture/compare match TGFB_2 Not possible TCI2V TCNT_2 overflow TCFV_2 Not possible TCI2U TCNT_2 underflow TCFU_2 Not possible

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3 TGI3A TGRA_3 input capture/compare match TGFA_3 Possible

TGI3B TGRB_3 input capture/compare match TGFB_3 Not possible TGI3C TGRC_3 input capture/compare match TGFC_3 Not possible TGI3D TGRD_3 input capture/compare match TGFD_3 Not possible TCI3V TCNT_3 overflow TCFV_3 Not possible

4 TGI4A * TGRA_4 input capture/compare match TGFA_4 Possible

TGI4B * TGRB_4 input capture/compare match TGFB_4 Not possible TCI4V TCNT_4 overflow TCFV_4 Not possible TCI4U TCNT_4 underflow TCFU_4 Not possible

5 TGI5A * TGRA_5 input capture/compare match TGFA_5 Possible

TGI5B * TGRB_5 input capture/compare match TGFB_5 Not possible TCI5V TCNT_5 overflow TCFV_5 Not possible TCI5U TCNT_5 underflow TCFU_5 Not possible

6 TGI6A TGRA_0 input capture/compare match TGFA_0 Possible

TGI6B TGRB_0 input capture/compare match TGFB_0 Not possible TGI6C TGRC_0 input capture/compare match TGFC_0 Not possible TGI6D TGRD_0 input capture/compare match TGFD_0 Not possible TCI6V TCNT_0 overflow TCFV_0 Not possible

7 TGI7A TGRA_1 input capture/compare match TGFA_1 Possible

TGI7B TGRB_1 input capture/compare match TGFB_1 Not possible TCI7V TCNT_1 overflow TCFV_1 Not possible TCI7U TCNT_1 underflow TCFU_1 Not possible

8 TGI8A TGRA_2 input capture/compare match TGFA_2 Possible

TGI8B TGRB_2 input capture/compare match TGFB_2 Not possible TCI8V TCNT_2 overflow TCFV_2 Not possible TCI8U TCNT_2 underflow TCFU_2 Not possible

9 TGI9A TGRA_3 input capture/compare match TGFA_3 Possible

TGI9B TGRB_3 input capture/compare match TGFB_3 Not possible TGI9C TGRC_3 input capture/compare match TGFC_3 Not possible TGI9D TGRD_3 input capture/compare match TGFD_3 Not possible TCI9V TCNT_3 overflow TCFV_3 Not possible

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10 TGI10A TGRA_4 input capture/ compare match TGFA_4 Possible

TGI10B TGRB_4 input capture/co mpare match TGFB_4 Not possible TCI10V TCNT_4 overflow TCFV_4 Not possible TCI10U TCNT_4 underflow TCFU_4 Not possible

11 TGI11A TGRA_5 input capture/ compare match TGFA_5 Possible

TGI11B TGRB_5 input capture/co mpare match TGFB_5 Not possible TCI11V TCNT_5 overflow TCFV_5 Not possible TCI11U TCNT_5 underflow TCFU_5 Not possible Note: 1. This table shows the init ial state immediately after a reset. The relative channel priority levels can be changed by the interrupt controller. 2. The H8SX/1527 does not have the inpu t capture function for channels 4 and 5. (1) Input Capture/Compare Match Interrupt An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. (2) Overflow Interrupt An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of a TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The TPU has six overflow interrupts, one for each channel. (3) Underflow Interrupt An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of a TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The TPU has four underflow interrupts, one each for channels 1, 2, 4, and 5.

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9.6 DMAC Activation

The DMAC can be activated by the TGR input capture/compare match interrupt for a channel. For details, see section 7, DMA Controller (DMAC). A total of six TPU input capture/compare match interrupts can be used as DMAC activation sources, one for each channel.

9.7 A/D Converter Activation

The TGRA input capture/compare match for each channel of unit 0 can activate the A/D converter (this function is not available for unit 1). If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel, a request to start A/D conversion is sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started. In the TPU, a total of six TGRA input capture/compare match interrupts can be used as A/D converter conversion start sources, one for each channel. The A/D converter cannot be activated by unit 1.

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9.8 Operation Timing

9.8.1 Input/Output Timing

(1) TCNT Count Timing Figure 9.31 shows TCNT count timing in internal clock operation, and figure 9.32 shows TCNT count timing in external clock operation. Pφ Internal clock TCNT input clock TCNT Falling edge Rising edge N − 1N + 1N + 2N Falling edge Figure 9.31 Count Timing in Internal Clock Operation Pφ External clock TCNT input clock TCNT Falling edge Rising edge N − 1N + 1N + 2N Falling edge Figure 9.32 Count Timing in External Clock Operation

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9.8.2 Interrupt Signal Timing

(1) TGF Flag Setting Timing in Case of Compare Match Figure 9.39 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and the TGI interrupt request signal timing. TGR Compare match signal Pφ TCNT input clock TCNT N + 1N N TGF flag TGI interrupt Figure 9.39 TGI Interrupt Timing (Compare Match) (2) TGF Flag Setting Timing in Case of Input Capture Figure 9.40 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and the TGI interrupt request signal timing. TGR Pφ TCNT N Input capture signal TGF flag TGI interrupt N Figure 9.40 TGI Interrupt Timing (Input Capture)

Section 9 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar. 14, 2006 Page 337 of 804 REJ09B0104-0300 Pφ Address Status flag Interrupt request signal Source address Destination address Period of flag clearing Period of interrupt request signal clearing Period in which the next transfer request is masked DMAC read cycle DMAC write cycle Figure 9.45 Timing for Status Flag Clearing by DMAC Activation (2)

9.9 Usage Notes

9.9.1 Module Stop Mode Setting

Operation of the TPU can be disabled or enabled using the module stop control register. The initial setting is for operation of the TPU to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 19, Power-Down Modes.

9.9.2 Input Clock Restrictions

The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 9.46 shows the input clock conditions in phase counting mode. TCLKA (TCLKC) TCLKB (TCLKD) Overlap Phase difference Pulse width Note: Phase difference, Overlap ≥ 1.5 states Pulse width ≥ 2.5 states Pulse width Phase differenceOverlap Pulse width Pulse width Figure 9.46 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode

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9.9.3 Caution on Cycle Setting

When counter clearing by compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: f = Pφ (N + 1) Pφ: Counter frequency Operating frequency TGR set value

9.9.4 Conflict between TCNT Write and Clear Operations

If the counter clearing signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 9.47 shows the timing in this case. Counter clear signal H'0000 Pφ TCNT N Address Write T1 T2 TCNT address TCNT write cycle Figure 9.47 Conflict between TCNT Write and Clear Operations

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9.9.5 Conflict between TCNT Write and Increment Operations

If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 9.48 shows the timing in this case. Pφ TCNT input clock TCNT N Address Write T1 T2 TCNT write cycle M TCNT write data TCNT address Figure 9.48 Conflict between TCNT Write and Increment Operations

9.9.6 Conflict between TGR Write and Compare Match

If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is disabled. A compare match also does not occur when the same value as before is written. Figure 9.49shows the timing in this case. TGR Compare match signal Pφ TCNT N + 1N Address Write T1 T2 M TGR address TGR write cycle N Disabled TGR write data Figure 9.49 Conflict between TGR Write and Compare Match

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9.9.7 Conflict between Buffer Register Write and Compare Match

If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the write data. Figure 9.50 shows the timing in this case. TGR Compare match signal Pφ N Address Write T1 T2 M TGR write cycle Buffer register address Data written to buffer register M Buffer register Figure 9.50 Conflict between Buffer Register Write and Compare Match

9.9.8 Conflict between TGR Read and Input Capture

If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 9.51 shows the timing in this case. TGR Pφ Input capture signal Address TGR address Read T1 T2 TGR read cycle XM MInternal data bus Figure 9.51 Conflict between TGR Read and Input Capture

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9.9.9 Conflict between TGR Write and Input Capture

If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 9.52 shows the timing in this case. TCNT Pφ Input capture signal Address TGR address Write T1 T2 TGR write cycle M MTGR Figure 9.52 Conflict between TGR Write and Input Capture

9.9.10 Conflict between Buffer Register Write and Input Capture

If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 9.53 shows the timing in this case. TCNT Pφ Input capture signal Address Buffer register address Write T1 T2 Buffer register write cycle N NTGR Buffer register M M Figure 9.53 Conflict between Buffer Register Write and Input Capture

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9.9.11 Conflict between Overflow/Underflow and Counter Clearing

If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 9.54 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR. Counter clear signal H'0000 Pφ TCNT input clock TCNT TGF flag TCFV flag H'FFFF Disabled Figure 9.54 Conflict between Overflow and Counter Clearing

9.9.12 Conflict between TCNT Write and Overflow/Underflow

If an overflow/underflow occurs due to increment/decrement in the T2 state of a TCNT write cycle, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 9.55 shows the operation timing when there is conflict between TCNT write and overflow. Pφ TCNT H'FFFF TCFV flag Address Write TCNT address M TCNT write data T1 T2 TGR write cycle Figure 9.55 Conflict between TCNT Write and Overflow

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9.9.13 Multiplexing of I/O Pins

In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not be performed from a multiplexed pin.

9.9.14 Interrupts and Module Stop Mode

If module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DMAC activation source. Interrupts should therefore be disabled before entering module stop mode.

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Section 10 Programmable Pulse Generator (PPG) Rev. 3.00 Mar. 14, 2006 Page 345 of 804 REJ09B0104-0300 Section 10 Programmable Pulse Generator (PPG) The programmable pulse generator (PPG) provides pulse outputs by using the 16-bit timer pulse unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (groups 3 and 2) that can operate both simultaneously and independently. Figure 10.1 shows a block diagram of the PPG.

10.1 Features

• 8-bit output data
• Two output groups
• Selectable output trigger signals
• Non-overlapping mode
• Can operate together with the DMA controller (DMAC)
• Inverted output can be set
• Module stop mode can be set Compare match signals PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 [Legend] PMR: PCR: NDERH: NDERL: PPG output mode register PPG output control register Next data enable register H Next data enable register L Internal data bus Pulse output pins, group 3 Pulse output pins, group 2 Pulse output pins, group 1 Pulse output pins, group 0 PODRH PODRL NDRH NDRL Control logic NDERH PMR NDERL PCR NDRH: NDRL: PODRH: PODRL: Next data register H Next data register L Output data register H Output data register L Figure 10.1 Block Diagram of PPG

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10.2 Input/Output Pins

Table 10.1 shows the PPG pin configuration. Table 10.1 Pin Configuration Pin Name I/O Function PO15 Output PO14 Output PO13 Output PO12 Output Group 3 pulse output PO11 Output PO10 Output PO9 Output PO8 Output Group 2 pulse output

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10.3 Register Descriptions

The PPG has the following registers.

• Next data enable register H (NDERH)
• Next data enable register L (NDERL)
• Output data register H (PODRH)
• Output data register L (PODRL)
• Next data register H (NDRH)
• Next data register L (NDRL)
• PPG output control register (PCR)
• PPG output mode register (PMR)

10.3.1 Next Data Enable Registers H, L (NDERH, NDERL)

NDERH and NDERL enable/disable pulse output on a bit-by-bit basis.

• NDERH NDER15 R/W NDER14 R/W NDER13 R/W NDER12 R/W NDER11 R/W NDER10 R/W NDER9 R/W NDER8 R/W Bit Bit Name Initial Value R/W
• NDERL NDER7 R/W NDER6 R/W NDER5 R/W NDER4 R/W NDER3 R/W NDER2 R/W NDER1 R/W NDER0 R/W Bit Bit Name Initial Value R/W

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• NDERH Bit Bit Name Initial Value R/W Description NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 R/W R/W R/W R/W R/W R/W R/W R/W Next Data Enable 15 to 8 When a bit is set to 1, the value in the corresponding NDRH bit is transferred to the PODRH bit by the selected output trigger. Values are not transferred from NDRH to PODRH for cleared bits.
• NDERL Bit Bit Name Initial Value R/W Description NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 R/W R/W R/W R/W R/W R/W R/W R/W Next Data Enable 7 to 0 When a bit is set to 1, the value in the corresponding NDRL bit is transferred to the PODRL bit by the selected output trigger. Values are not transferred from NDRL to PODRL for cleared bits.

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10.3.2 Output Data Registers H, L (PODRH, PODRL)

PODRH and PODRL store output data for use in pulse output. A bit that has been set for pulse output by NDER is read-only and cannot be modified.

• PODRH POD15 R/W POD14 R/W POD13 R/W POD12 R/W POD11 R/W POD10 R/W POD9 R/W POD8 R/W Bit Bit Name Initial Value R/W
• PODRL POD7 R/W POD6 R/W POD5 R/W POD4 R/W POD3 R/W POD2 R/W POD1 R/W POD0 R/W Bit Bit Name Initial Value R/W
• PODRH Bit Bit Name Initial Value R/W Description POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8 R/W R/W R/W R/W R/W R/W R/W R/W Output Data Register 15 to 8 For bits which have been set to pulse output by NDERH, the output trigger transfers NDRH values to this register during PPG operation. While NDERH is set to 1, the CPU cannot write to this register. While NDERH is cleared, the initial output value of the pulse can be set.

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• PODRL Bit Bit Name Initial Value R/W Description POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0 R/W R/W R/W R/W R/W R/W R/W R/W Output Data Register 7 to 0 For bits which have been set to pulse output by NDERL, the output trigger transfers NDRL values to this register during PPG operation. While NDERL is set to 1, the CPU cannot write to this register. While NDERL is cleared, the initial output value of the pulse can be set.

10.3.3 Next Data Registers H, L (NDRH, NDRL)

NDRH and NDRL store the next data for pulse output. The NDR addresses differ depending on whether pulse output groups have the same output trigger or different output triggers.

• NDRH Bit Bit Name Initial Value R/W NDR15 R/W NDR14 R/W NDR13 R/W NDR12 R/W NDR11 R/W NDR10 R/W NDR9 R/W NDR8 R/W
• NDRL Bit Bit Name Initial Value R/W NDR7 R/W NDR6 R/W NDR5 R/W NDR4 R/W NDR3 R/W NDR2 R/W NDR1 R/W NDR0 R/W

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• NDRH If pulse output groups 2 and 3 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. Bit Bit Name Initial Value R/W Description NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 R/W R/W R/W R/W R/W R/W R/W R/W Next Data Register 15 to 8 The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR. If pulse output groups 2 and 3 have different output triggers, the upper four bits and lower four bits are mapped to different addresses as shown below. Bit Bit Name Initial Value R/W Description NDR15 NDR14 NDR13 NDR12 R/W R/W R/W R/W Next Data Register 15 to 12 The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR. 3 to 0  All 1 R Reserved These are read-only bits and cannot be modified. Bit Bit Name Initial Value R/W Description 7 to 4  All 1 R Reserved These are read-only bits and cannot be modified. NDR11 NDR10 NDR9 NDR8 R/W R/W R/W R/W Next Data Register 11 to 8 The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR.

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• NDRL If pulse output groups 0 and 1 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. Bit Bit Name Initial Value R/W Description NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 R/W R/W R/W R/W R/W R/W R/W R/W Next Data Register 7 to 0 The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR. If pulse output groups 0 and 1 have different output triggers, the upper four bits and lower four bits are mapped to different addresses as shown below. Bit Bit Name Initial Value R/W Description NDR7 NDR6 NDR5 NDR4 R/W R/W R/W R/W Next Data Register 7 to 4 The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR. 3 to 0  All 1 R Reserved These are read-only bits and cannot be modified. Bit Bit Name Initial Value R/W Description 7 to 4  All 1 R Reserved These are read-only bits and cannot be modified. NDR3 NDR2 NDR1 NDR0 R/W R/W R/W R/W Next Data Register 3 to 0 The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR.

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10.3.4 PPG Output Control Register (PCR)

PCR selects output trigger signals on a group-by-group basis. For details on output trigger selection, refer to section 10.3.5, PPG Output Mode Register (PMR). G3CMS1 R/W G3CMS0 R/W G2CMS1 R/W G2CMS0 R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description G3CMS1 G3CMS0 R/W R/W Group 3 Compare Match Select 1 and 0 These bits select output trigger of pulse output group 3. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3 G2CMS1 G2CMS0 R/W R/W Group 2 Compare Match Select 1 and 0 These bits select output trigger of pulse output group 2. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3 3 to 0  All 1 R/W Reserved These bits are always read as 1. The write value should always be 1.

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10.3.5 PPG Output Mo de Register (PMR)

PMR selects the pulse output mode of the PPG for each group. If inverted output is selected, a low-level pulse is output when PODRH is 1 and a high-level pulse is output when PODRH is 0. If non-overlapping operation is selected, PPG updates its output values at compare match A or B of the TPU that becomes the output trigger. For details, refer to section 10.4.4, Non-Overlapping Pulse Output. G3INV R/W G2INV R/W R/W R/W G3NOV R/W G2NOV R/W R/W R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description

7 G3INV 1 R/W Group 3 Inversion

Selects direct output or inverted output for pulse output group 3. 0: Inverted output 1: Direct output

6 G2INV 1 R/W Group 2 Inversion

Selects direct output or inverted output for pulse output group 2. 0: Inverted output 1: Direct output 5, 4  All 1 R/W Reserved These bits are always read as 1. The write value should always be 1.

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3 G3NOV 0 R/W Group 3 Non-Overlap

Selects normal or non-overlapping operation for pulse output group 3. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel)

2 G2NOV 0 R/W Group 2 Non-Overlap

Selects normal or non-overlapping operation for pulse output group 2. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel) 1, 0  All 0 R/W Reserved These bits are always read as 0. The write value should always be 0.

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10.4 Operation

Figure 10.2 shows a schematic diagram of the PPG. PPG pulse output is enabled when the corresponding bits in NDER are set to 1. An initial output value is determined by its corresponding PODR initial setting. When the compare match event specified by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output values. Sequential output of data of up to eight bits is possible by writing new output data to NDR before the next compare match. Output trigger signal Pulse output pin Internal data bus Normal output/inverted output C PODRQD NDER Q NDRQD Figure 10.2 Schematic Diagram of PPG

10.4.1 Output Timing

If pulse output is enabled, the NDR contents are transferred to PODR and output when the specified compare match event occurs. Figure 10.3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. TCNT N N + 1 Pφ TGRA N Compare match A signal NDRH mnPODRH PO8 to PO15 n m n Figure 10.3 Timing of Transfer and Output of NDR Contents (Example)

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10.4.2 Sample Setup Procedure for Normal Pulse Output

Figure 10.4 shows a sample procedure for setting up normal pulse output. Select TGR functions [1] Set TGRA value Set counting operation Select interrupt request Set initial output data Enable pulse output Select output trigger Set next pulse output data Start counter Set next pulse output data Normal PPG output No Yes TPU setup PPG setup TPU setup [2] [3] [4] [5] [6] [7] [8] [9] [10] Compare match? [1] Set TIOR to make TGRA an output compare register (with output disabled). [2] Set the PPG output trigger cycle. [3] Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. [4] Enable the TGIA interrupt in TIER. The DMAC can also be set up to transfer data to NDR. [5] Set the initial output values in PODR. [6] Set the bits in NDER for the pins to be used for pulse output to 1. [7] Select the TPU compare match event to be used as the output trigger in PCR. [8] Set the next pulse output values in NDR. [9] Set the CST bit in TSTR to 1 to start the TCNT counter. [10] At each TGIA interrupt, set the next output values in NDR. Figure 10.4 Setup Procedure for Normal Pulse Output (Example)

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10.4.3 Example of Normal Pulse Output (Example of 5-Phase Pulse Output)

Figure 10.5 shows an example in which pulse output is used for cyclic 5-phase pulse output. TCNT value TCNT TGRA H'0000 NDRH 00 80 C0 40 60 20 30 10 18 08 88PODRH PO15 PO14 PO13 PO12 PO11 Time Compare match C080 C080 40 60 20 30 10 18 08 88 80 C0 40 Figure 10.5 Normal Pulse Output Example (5-Phase Pulse Output) 1. Set up TGRA in TPU which is used as the output trigger to be an output compare register. Set a cycle in TGRA so the counter will be cleared by compare match A. Set the TGIEA bit in TIER to 1 to enable the compare match/input capture A (TGIA) interrupt. 2. Write H'F8 to NDERH, and set bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger. Write output data H'80 in NDRH. 3. The timer counter in the TPU channel starts. When compare match A occurs, the NDRH contents are transferred to PODRH and output. The TGIA interrupt handling routine writes the next output data (H'C0) in NDRH. 4. 5-phase pulse output (one or two phases active at a time) can be obtained subsequently by writing H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88... at successive TGIA interrupts. If the DMAC is set for activation by the TGIA interrupt, pulse output can be obtained without imposing a load on the CPU.

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10.4.4 Non-Overlapping Pulse Output

During non-overlapping operation, transfer from NDR to PODR is performed as follows:

• At compare match A, the NDR bits are always transferred to PODR.
• At compare match B, the NDR bits are transferred only if their value is 0. The NDR bits are not transferred if their value is 1. Figure 10.6 illustrates the non-overlapping pulse output operation. Compare match A Compare match B Pulse output pin Internal data bus Normal output/inverted output C PODRQD NDER Q NDRQD Figure 10.6 Non-Overlapping Pulse Output Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. The NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlapping margin). This can be accomplished by having the TGIA interrupt handling routine write the next data in NDR, or by having the TGIA interrupt activate the DMAC. Note, however, that the next data must be written before the next compare match B occurs.

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10.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output

Figure 10.8 shows a sample procedure for setting up non-overlapping pulse output. Select TGR functions [1] Set TGR values Set counting operation Select interrupt request Set initial output data Enable pulse output Select output trigger Set next pulse output data Start counter Set next pulse output data Compare match A? No Yes TPU setup PPG setup TPU setup Non-overlapping pulse output Set non-overlapping groups [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [1] Set TIOR to make TGRA and TGRB output compare registers (with output disabled). [2] Set the pulse output trigger cycle in TGRB and the non-overlapping margin in TGRA. [3] Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. [4] Enable the TGIA interrupt in TIER. The DMAC can also be set up to transfer data to NDR. [5] Set the initial output values in PODR. [6] Set the bits in NDER for the pins to be used for pulse output to 1. [7] Select the TPU compare match event to be used as the pulse output trigger in PCR. [8] In PMR, select the groups that will operate in non-overlapping mode. [9] Set the next pulse output values in NDR. [10] Set the CST bit in TSTR to 1 to start the TCNT counter. [11] At each TGIA interrupt, set the next output values in NDR. Figure 10.8 Setup Procedure for Non-Overlapping Pulse Output (Example)

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10.4.6 Example of Non-Overlapping Pulse Output (Example of 4-Phase Complementary

Non-Overlapping Pulse Output) Figure 10.9 shows an example in which pulse output is used for 4-phase complementary non- overlapping pulse output. TCNT value TCNT TGRB TGRA H'0000 NDRH 95 65 59 56 95 65 00 95 05 65 41 59 50 56 14 95 05 65PODRH PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Time Non-overlapping margin Figure 10.9 Non-Overlapping Pulse Output Example (4-Phase Complementary)

Section 10 Programmable Pulse Generator (PPG) Rev. 3.00 Mar. 14, 2006 Page 363 of 804 REJ09B0104-0300 1. Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are output compare registers. Set the cycle in TGRB and the non-overlapping margin in TGRA, and set the counter to be cleared by compare match B. Set the TGIEA bit in TIER to 1 to enable the TGIA interrupt. 2. Write H'FF to NDERH, and set bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger. Set bits G3NOV and G2NOV in PMR to 1 to select non-overlapping pulse output. Write output data H'95 to NDRH. 3. The timer counter in the TPU channel starts. When a compare match with TGRB occurs, outputs change from 1 to 0. When a compare match with TGRA occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed by the value set in TGRA). The TGIA interrupt handling routine writes the next output data (H'65) to NDRH. 4. 4-phase complementary non-overlapping pulse output can be obtained subsequently by writing H'59, H'56, H'95... at successive TGIA interrupts. If the DMAC is set for activation by a TGIA interrupt, pulse can be output without imposing a load on the CPU.

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10.4.7 Inverted Pulse Output

If the G3INV and G2INV bits in PMR are cleared to 0, values that are the inverse of the PODR contents can be output. Figure 10.10 shows the outputs when the G3INV and G2INV bits are cleared to 0, in addition to the settings of figure 10.9. TCNT value TCNT TGRB TGRA H'0000 NDRH 95 65 59 56 95 65 00 95 05 65 41 59 50 56 14 95 05 65PODRH PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Time Figure 10.10 Inverted Pulse Output (Example)

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10.4.8 Pulse Output Triggered by Input Capture

Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA functions as an input capture register in the TPU channel selected by PCR, pulse output will be triggered by the input capture signal. Figure 10.11 shows the timing of this output. Pφ N MN TIOC pin Input capture signal NDR PODR MNPO Figure 10.11 Pulse Output Triggered by Input Capture (Example)

10.5 Usage Notes

10.5.1 Module Stop Mode Setting

PPG operation can be disabled or enabled using the module stop control register. The initial value is for PPG operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 19, Power-Down Modes.

10.5.2 Operation of Pulse Output Pins

Pins PO0 to PO8 are also used for other peripheral functions such as the TPU. When output by another peripheral function is enabled, the corresponding pins cannot be used for pulse output. Note, however, that data transfer from NDR bits to PODR bits takes place, regardless of the usage of the pins. Pin functions should be changed only under conditions in which the output trigger event will not occur.

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Section 11 Watchdog Timer (WDT) Rev. 3.00 Mar. 14, 2006 Page 367 of 804 REJ09B0104-0300 Section 11 Watchdog Timer (WDT) The watchdog timer (WDT) is an 8-bit timer that outputs an internal reset signal if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows. Figure 11.1 shows a block diagram of the WDT.

11.1 Features

• Selectable from eight counter input clocks
• Switchable between watchdog timer mode and interval timer mode  In watchdog timer mode If the counter overflows, this LSI can be initialized internally.  In interval timer mode If the counter overflows, the WDT generates an interval timer interrupt (WOVI). Overflow Interrupt control WOVI (interrupt request signal) Internal reset signal* Reset control RSTCSR TCNT TCSR Pφ/2 Pφ/64 Pφ/128 Pφ/512 Pφ/2048 Pφ/8192 Pφ/32768 Pφ/131072 Clock Clock select Internal clocks Bus interfaceModule bus TCSR: TCNT: RSTCSR: Note: * An internal reset signal can be generated by the RSTCSR setting. Timer control/status register Timer counter Reset control/status register WDT [Legend] Internal bus Figure 11.1 Block Diagram of WDT

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11.2 Register Descriptions

The WDT has the following three registers. To prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to in a method different from normal registers. For details, see section 11.5.1, Notes on Register Access.

• Timer counter (TCNT)
• Timer control/status register (TCSR)
• Reset control/status register (RSTCSR)

11.2.1 Timer Counter (TCNT)

TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in TCSR is cleared to 0. Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W

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11.2.2 Timer Control/Status Register (TCSR)

TCSR selects the clock source to be input to TCNT, and the timer mode. Bit Bit Name Initial Value R/W Note: * Only 0 can be written to this bit, to clear the flag. OVF R/(W)* WT/IT R/W TME R/W R R CKS2 R/W CKS1 R/W CKS0 R/W Bit Bit Name Initial Value R/W Description

7 OVF 0 R/(W) * Overflow Flag

Indicates that TCNT has overflowed in interval timer mode. Only 0 can be written to this bit, to clear the flag. [Setting condition]

• When TCNT overflows in interval timer mode (changes from H'FF to H'00)
• When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. [Clearing condition]
• Cleared by reading TCSR when OVF = 1, then writing 0 to OVF (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)

6 WT/ IT 0 R/W Timer Mode Select

Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode When TCNT overflows, an interval timer interrupt (WOVI) is requested. 1: Watchdog timer mode When TCNT overflows while RSTE = 1, this LSI is initialized initially.

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5 TME 0 R/W Timer Enable

When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00. 4, 3  All 1 R Reserved These are read-only bits and cannot be modified. CKS2 CKS1 CKS0 R/W R/W R/W Clock Select 2 to 0 Select the clock source to be input to TCNT. The overflow cycle for Pφ = 20 MHz is indicated in parentheses. 000: Clock Pφ/2 (cycle: 25.6 µs) 001: Clock Pφ/64 (cycle: 819.2 µs) 010: Clock Pφ/128 (cycle: 1.6 ms) 011: Clock Pφ/512 (cycle: 6.6 ms) 100: Clock Pφ/2048 (cycle: 26.2 ms) 101: Clock Pφ/8192 (cycle: 104.9 ms) 110: Clock Pφ/32768 (cycle: 419.4 ms) 111: Clock Pφ/131072 (cycle: 1.68 s) Note: * Only 0 can be written to this bit, to clear the flag.

11.2.3 Reset Control/Status Register (RSTCSR)

RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal reset signal caused by WDT overflows. WOVF R/(W)* RSTE R/W R/W R R R R R Bit Bit Name Initial Value R/W Note: * Only 0 can be written to this bit, to clear the flag.

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7 WOVF 0 R/(W) * Watchdog Timer Overflow Flag

This bit is set when TCNT overflows in watchdog timer mode. This bit cannot be set in interval timer mode, and only 0 can be written. [Setting condition]

• When TCNT overflows (changed from H'FF to H'00) in watchdog timer mode [Clearing condition]
• Reading RSTCSR when WOVF = 1, and then writing 0 to WOVF

6 RSTE 0 R/W Reset Enable

Specifies whether or not this LSI is internally reset if TCNT overflows during watchdog timer operation. 0: LSI is not reset even if TCNT overflows (Though this LSI is not reset, TCNT and TCSR in WDT are reset) 1: LSI is reset if TCNT overflows 5  0 R/W Reserved This bit is always read as 0. The write value should always be 0. 4 to 0  All 1 R Reserved These are read-only bits and cannot be modified. Note: * Only 0 can be written to this bit, to clear the flag.

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11.3 Operation

11.3.1 Watchdog Timer Mode

To use the WDT in watchdog timer mode, set both the WT/IT and TME bits in TCSR to 1. When TCNT overflows in watchdog timer mode, the WOVF bit in RSTCSR is set to 1. When the watchdog timer mode is selected and the RSTE bit in RSTCSR is set to 1, if TCNT overflows without being rewritten because of a system crash or other error, this LSI is initialized internally. This ensures that TCNT does not overflow while the system is operating normally. Software must prevent TCNT overflows by rewriting the TCNT value (normally H'00 is written) before overflow occurs. If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT overflow (TCNT has overflowed), the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0. The internal reset signal is output for 519 cycles of Pφ. When RSTE = 1, a signal to initialize this LSI internally is generated. Since this signal initializes the system click control register (SCKCR), the multiplication ratio of P φ clock is also initialized. When RSTE = 0, the signal is not generated, meaning that the SCKCR value and multiplication ratio of P φ clock remain unchanged. TCNT value H'00 Time H'FF WT/IT = 1 TME = 1 H'00 written to TCNT WT/IT = 1 TME = 1 H'00 written to TCNT 519 cycles Internal reset signal* Notes: * If TCNT overflows when the RSTE bit is set to 1, an internal reset signal is generated. Overflow WOVF = 1 Figure 11.2 Operation in Watchdog Timer Mode

Section 11 Watchdog Timer (WDT) Rev. 3.00 Mar. 14, 2006 Page 373 of 804 REJ09B0104-0300

11.3.2 Interval Timer Mode

To use the WDT as an interval timer, set the WT/IT bit to 0 and the TME bit to 1 in TCSR. When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time the TCNT overflows. Therefore, an interrupt can be generated at intervals. When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested at the same time the OVF bit in the TCSR is set to 1. TCNT value H'00 Time H'FF WT/IT = 0 TME = 1 WOVI Overflow Overflow Overflow Overflow WOVI: Interval timer interrupt request WOVI WOVI WOVI Figure 11.3 Operation in Interval Timer Mode

11.4 Interrupt Source

During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. The OVF flag must be cleared to 0 in the interrupt handling routine. Table 11.1 WDT Interrupt Source Name Interrupt Source Inte rrupt Flag DMAC Activation WOVI TCNT overflow OVF Impossible

Section 11 Watchdog Timer (WDT) Rev. 3.00 Mar. 14, 2006 Page 374 of 804 REJ09B0104-0300

11.5 Usage Notes

11.5.1 Notes on Register Access

The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. (1) Writing to TCNT, TCSR, and RSTCSR TCNT and TCSR must be written to by a word transfer instruction. They cannot be written to by a byte transfer instruction. For writing, TCNT and TCSR are assigned to the same address. Accordingly, perform data transfer as shown in figure 11.4. The transfer instruction writes the lower byte data to TCNT or TCSR. To write to RSTCSR, execute a word transfer instruction for address H'FFA6. A byte transfer instruction cannot be used to write to RSTCSR. The method of writing 0 to the WOVF bit in RSTCSR differs from that of writing to the RSTE bit in RSTCSR. Perform data transfer as shown in figure 11.4. At data transfer, the transfer instruction clears the WOVF bit to 0, but has no effect on the RSTE bit. To write to the RSTE bit, perform data transfer as shown in figure 11.4. In this case, the transfer instruction writes the value in bit 6 of the lower byte to the RSTE bit, but has no effect on the WOVF bit. TCNT write or writing to the RSTE bit in RSTCSR: TCSR write: Address: H'FFA4 (TCNT) H'FFA6 (RSTCSR) 15 8 7 0 H'5A Write data Address: H'FFA4 (TCSR) 15 8 7 0 H'A5 Write data Writing 0 to the WOVF bit in RSTCSR: Address: H'FFA6 (RSTCSR) 15 8 7 0 H'A5 H'00 Figure 11.4 Writing to TCNT, TCSR, and RSTCSR

Section 11 Watchdog Timer (WDT) Rev. 3.00 Mar. 14, 2006 Page 375 of 804 REJ09B0104-0300 (2) Reading from TCNT, TCSR, and RSTCSR These registers can be read from in the same way as other registers. For reading, TCSR is assigned to address H'FFA4, TCNT to address H'FFA5, and RSTCSR to address H'FFA7.

11.5.2 Conflict between Timer Counter (TCNT) Write and Increment

If a TCNT clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 11.5 shows this operation. N M T1 T2 Address Pφ Internal write signal TCNT input clock TCNT TCNT write cycle Counter write data Figure 11.5 Conflict between TCNT Write and Increment

11.5.3 Changing Values of Bits CKS2 to CKS0

If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in the incrementation. The watchdog timer must be stopped (by clearing the TME bit to 0) before the values of bits CKS2 to CKS0 are changed.

11.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode

If the timer mode is switched from watchdog timer mode to interval timer mode while the WDT is operating, errors could occur in the incrementation. The watchdog timer must be stopped (by clearing the TME bit to 0) before switching the timer mode.

Section 11 Watchdog Timer (WDT) Rev. 3.00 Mar. 14, 2006 Page 376 of 804 REJ09B0104-0300

11.5.5 Transition to Watchdog Timer Mode or Software Standby Mode

When the WDT operates in watchdog timer mode, a transition to software standby mode is not made even when the SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1. Instead, a transition to sleep mode is made. To transit to software standby mode, the SLEEP instruction must be executed after halting the WDT (clearing the TME bit to 0). When the WDT operates in interval timer mode, a transition to software standby mode is made through execution of the SLEEP instruction when the SSBY bit in SBYCR is set to 1.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 377 of 804 REJ09B0104-0300 Section 12 Serial Communication Interface (SCI) This LSI has two independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. Asynchronous serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function). The SCI also supports the smart card (IC card) interface conforming to ISO/IEC 7816-3 (Identification Card) as an extended asynchronous communication mode. Figure 12.1 shows a block diagram of the SCI.

12.1 Features

• Choice of asynchronous or clocked synchronous serial communication mode
• Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data.
• On-chip baud rate generator allows any bit rate to be selected The external clock can be selected as a transfer clock source (except for the smart card interface).
• Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data)
• Four interrupt sources The interrupt sources are transmit-end, transmit-data-empty, receive-data-full, and receive error. The transmit-data-empty and receive-data-full interrupt sources can activate the DMAC.
• Module stop mode can be set Asynchronous Mode:
• Data length: 7 or 8 bits
• Stop bit length: 1 or 2 bits
• Parity: Even, odd, or none
• Receive error detection: Parity, overrun, and framing errors
• Break detection: Break can be detected by reading the RxD pin level directly in case of a framing error

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 378 of 804 REJ09B0104-0300 Clocked Synchronous Mode:

• Data length: 8 bits
• Receive error detection: Overrun errors Smart Card Interface:
• An error signal can be automatically transmitted on detection of a parity error during reception
• Data can be automatically re-transmitted on receiving an error signal during transmission
• Both direct convention and inverse convention are supported RxD TxD SCK Clock Pφ Pφ/4 Pφ/16 Pφ/64 TEI TXI RXI ERI SCMR SSR SCR SMR Transmission/ reception control Baud rate generator BRR Module data bus RDR TSRRSR Parity generation Parity check [Legend] RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register TDR Bus interface Internal data bus External clock SCR: Serial control register SSR: Serial status register SCMR: Smart card mode register BRR: Bit rate register Figure 12.1 Block Diagram of SCI

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 379 of 804 REJ09B0104-0300

12.2 Input/Output Pins

Table 12.1 lists the pin configuration of the SCI. Table 12.1 Pin Configuration Channel Pin Name * I/O Function SCK3 I/O Channel 3 clock input/output RxD3 Input Channel 3 receive data input TxD3 Output Channel 3 transmit data output SCK4 I/O Channel 4 clock input/output RxD4 Input Channel 4 receive data input TxD4 Output Channel 4 transmit data output Note: * Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the channel designation.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 380 of 804 REJ09B0104-0300

12.3 Register Descriptions

The SCI has the following registers. Some bits in the serial mode register (SMR), serial status register (SSR), and serial control register (SCR) have different functions in different modes: Normal serial communication interface mode and smart card interface mode. The bits, therefore, are described separately for each mode in the corresponding register sections. Channel 3: Receive shift register_3 (RSR_3) Transmit shift register_3 (TSR_3) Receive data register_3 (RDR_3) Transmit data register_3 (TDR_3) Serial mode register_3 (SMR_3) Serial control register_3 (SCR_3) Serial status register_3 (SSR_3) Smart card mode register_3 (SCMR_3) Bit rate register_3 (BRR_3) Channel 4: Receive shift register_4 (RSR_4) Transmit shift register_4 (TSR_4) Receive data register_4 (RDR_4) Transmit data register_4 (TDR_4) Serial mode register_4 (SMR_4) Serial control register_4 (SCR_4) Serial status register_4 (SSR_4) Smart card mode register_4 (SCMR_4) Bit rate register_4 (BRR_4)

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 381 of 804 REJ09B0104-0300

12.3.1 Receive Shift Register (RSR)

RSR is a shift register which is used to receive serial data input from the RxD pin and converts it into parallel data. When one frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU.

12.3.2 Receive Data Register (RDR)

RDR is an 8-bit register that stores receive data. When the SCI has received one frame of serial data, it transfers the received serial data from RSR to RDR where it is stored. This allows RSR to receive the next data. Since RSR and RDR function as a double buffer in this way, continuous receive operations can be performed. After confirming that the RDRF bit in SSR is set to 1, read RDR only once. RDR cannot be written to by the CPU. Bit Bit Name Initial Value R/W R R R R R R R R

12.3.3 Transmit Data Register (TDR)

TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered structures of TDR and TSR enables continuous serial transmission. If the next transmit data has already been written to TDR when one frame of data is transmitted, the SCI transfers the written data to TSR to continue transmission. Although TDR can be read from or written to by the CPU at all times, to achieve reliable serial transmission, write transmit data to TDR for only once after confirming that the TDRE bit in SSR is set to 1. Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 382 of 804 REJ09B0104-0300

12.3.4 Transmit Shift Register (TSR)

TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first automatically transfers transmit data from TDR to TSR, then sends the data to the TxD pin. TSR cannot be directly accessed by the CPU.

12.3.5 Serial Mode Register (SMR)

SMR is used to set the SCI's serial transfer format and select the baud rate generator clock source. Some bits in SMR have different functions in normal mode and smart card interface mode.

• When SMIF in SCMR = 0 C/A R/W CHR R/W PE R/W O/E R/W STOP R/W MP R/W CKS1 R/W CKS0 R/W Bit Bit Name Initial Value R/W
• When SMIF in SCMR = 1 GM R/W BLK R/W PE R/W O/E R/W BCP1 R/W BCP0 R/W CKS1 R/W CKS0 R/W Bit Bit Name Initial Value R/W Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0): Bit Bit Name Initial Value R/W Description

7 C/ A 0 R/W Communication Mode

0: Asynchronous mode 1: Clocked synchronous mode

6 CHR 0 R/W Character Length (valid only in asynchronous mode)

0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length. LSB-first is fixed and the MSB (bit 7) in TDR is not transmitted in transmission. In clocked synchronous mode, a fixed data length of 8 bits is used.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 383 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description

5 PE 0 R/W Parity Enable (valid only in asynchronous mode)

When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. For a multiprocessor format, parity bit addition and checking are not performed regardless of the PE bit setting.

4 O/ E 0 R/W Parity Mode (valid only when the PE bit is 1 in

asynchronous mode) 0: Selects even parity. 1: Selects odd parity.

3 STOP 0 R/W Stop Bit Length (valid only in asynchronous mode)

Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits In reception, only the first stop bit is checked. If the second stop bit is 0, it is treated as the start bit of the next transmit frame.

2 MP 0 R/W Multiprocessor Mode (valid only in asynchronous mode)

When this bit is set to 1, the multiprocessor function is enabled. The PE bit and O/E bit settings are invalid in multiprocessor mode. CKS1 CKS0 R/W R/W Clock Select 1, 0 These bits select the clock source for the baud rate generator. 00: Pφ clock (n = 0) 01: Pφ/4 clock (n = 1) 10: Pφ/16 clock (n = 2) 11: Pφ/64 clock (n = 3) For the relation between the settings of these bits and the baud rate, see section 12.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR (see section 12.3.9, Bit Rate Register (BRR)).

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 384 of 804 REJ09B0104-0300 Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1): Bit Bit Name Initial Value R/W Description

7 GM 0 R/W GSM Mode

Setting this bit to 1 allows GSM mode operation. In GSM mode, the TEND set timing is put forward to 11.0 etu from the start and the clock output control function is appended. For details, see sections 12.7.6, Data Transmission (Except in Block Transfer Mode) and 12.7.8, Clock Output Control. 6 BLK 0 R/W Setting this bit to 1 allows block transfer mode operation. For details, see section 12.7.3, Block Transfer Mode. When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. Set this bit to 1 in smart card interface mode. asynchronous mode) 0: Selects even parity 1: Selects odd parity For details on the usage of this bit in smart card interface mode, see section 12.7.2, Data Format (Except in Block Transfer Mode). BCP1 BCP0 R/W R/W Basic Clock Pulse 1,0 These bits select the number of basic clock cycles in a 1- bit data transfer time in smart card interface mode. 00: 32 clock cycles (S = 32) 01: 64 clock cycles (S = 64) 10: 372 clock cycles (S = 372) 11: 256 clock cycles (S = 256) For details, see section 12.7.4, Receive Data Sampling Timing and Reception Margin. S is described in section 12.3.9, Bit Rate Register (BRR).

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 385 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description CKS1 CKS0 R/W R/W Clock Select 1,0 These bits select the clock source for the baud rate generator. 00: Pφ clock (n = 0) 01: Pφ/4 clock (n = 1) 10: Pφ/16 clock (n = 2) 11: Pφ/64 clock (n = 3) For the relation between the settings of these bits and the baud rate, see section 12.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR (see section 12.3.9, Bit Rate Register (BRR)). Note: etu (Elementary Time Unit): 1-bit transfer time

12.3.6 Serial Control Register (SCR)

SCR is a register that enables/disables the following SCI transfer operations and interrupt requests, and selects the transfer clock source. For details on interrupt requests, see section 12.8, Interrupt Sources. Some bits in SCR have different functions in normal mode and smart card interface mode.

• When SMIF in SCMR = 0 TIE R/W RIE R/W TE R/W RE R/W MPIE R/W TEIE R/W CKE1 R/W CKE0 R/W Bit Bit Name Initial Value R/W
• When SMIF in SCMR = 1 TIE R/W RIE R/W TE R/W RE R/W MPIE R/W TEIE R/W CKE1 R/W CKE0 R/W Bit Bit Name Initial Value R/W

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7 TIE 0 R/W Transmit Interrupt Enable

When this bit is set to 1, a TXI interrupt request is enabled. A TXI interrupt request can be cancelled by reading 1 from the TDRE flag and then clearing the flag to 0, or by clearing the TIE bit to 0.

6 RIE 0 R/W Receive Interrupt Enable

When this bit is set to 1, RXI and ERI interrupt requests are enabled. RXI and ERI interrupt requests can be cancelled by reading 1 from the RDRF, FER, PER, or ORER flag and then clearing the flag to 0, or by clearing the RIE bit to 0.

5 TE 0 R/W Transmit Enable

When this bit is set to 1, transmission is enabled. Under this condition, serial transmission is started by writing transmit data to TDR, and clearing the TDRE flag in SSR to 0. Note that SMR should be set prior to setting the TE bit to 1 Sin order to designate the transmission format. If transmission is halted by clearing this bit to 0, the TDRE flag in SSR is fixed 1.

4 RE 0 R/W Receive Enable

When this bit is set to 1, reception is enabled. Under this condition, serial reception is started by detecting the start bit in asynchronous mode or the synchronous clock input in clocked synchronous mode. Note that SMR should be set prior to setting the RE bit to 1 in order to designate the reception format. Even if reception is halted by clearing this bit to 0, the RDRF, FER, PER, and ORER flags are not affected and the previous value is retained.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 387 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description

3 MPIE 0 R/W Multiprocessor Interrupt Enable (valid only when the MP

bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is disabled. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. For details, see section 12.5, Multiprocessor Communication Function. When receive data including MPB = 0 in SSR is being received, transfer of the received data from RSR to RDR, detection of reception errors, and the settings of RDRF, FER, and ORER flags in SSR are not performed. When receive data including MPB = 1 is received, the MPB bit in SSR is set to 1, the MPIE bit is automatically cleared to 0, and RXI and ERI interrupt requests (in the case where the TIE and RIE bits in SCR are set to 1) and setting of the FER and ORER flags are enabled.

2 TEIE 0 R/W Transmit End Interrupt Enable

When this bit is set to 1, a TEI interrupt request is enabled. A TEI interrupt request can be cancelled by reading 1 from the TDRE flag and then clearing the flag to 0 in order to clear the TEND flag to 0, or by clearing the TEIE bit to 0. CKE1 CKE0 R/W R/W Clock Enable 1, 0 These bits select the clock source and SCK pin function.

• Asynchronous mode 00: On-chip baud rate generator (SCK pin functions as I/O port.) 01: On-chip baud rate generator (Outputs a clock with the same frequency as the bit rate from the SCK pin.) 1X: External clock (Inputs a clock with a frequency 16 times the bit rate from the SCK pin.)
• Clocked synchronous mode 0X: Internal clock (SCK pin functions as clock output.) 1X: External clock (SCK pin functions as clock input.) Note: X: Don't care

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 388 of 804 REJ09B0104-0300 Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1): Bit Bit Name Initial Value R/W Description When this bit is set to 1,a TXI interrupt request is enabled. A TXI interrupt request can be cancelled by reading 1 from the TDRE flag and then clearing the flag to 0, or by clearing the TIE bit to 0. When this bit is set to 1, RXI and ERI interrupt requests are enabled. RXI and ERI interrupt requests can be cancelled by reading 1 from the RDRF, FER, PER, or ORER flag and then clearing the flag to 0, or by clearing the RIE bit to 0. When this bit is set to 1, transmission is enabled. Under this condition, serial transmission is started by writing transmit data to TDR, and clearing the TDRE flag in SSR to 0. Note that SMR should be set prior to setting the TE bit to 1 in order to designate the transmission format. If transmission is halted by clearing this bit to 0, the TDRE flag in SSR is fixed 1. When this bit is set to 1, reception is enabled. Under this condition, serial reception is started by detecting the start bit in asynchronous mode or the synchronous clock input in clocked synchronous mode. Note that SMR should be set prior to setting the RE bit to 1 in order to designate the reception format. Even if reception is halted by clearing this bit to 0, the RDRF, FER, PER, and ORER flags are not affected and the previous value is retained. bit in SMR is 1 in asynchronous mode) Write 0 to this bit in smart card interface mode. Write 0 to this bit in smart card interface mode.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 389 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description CKE1 CKE0 R/W R/W Clock Enable 1, 0 These bits control the clock output from the SCK pin. In GSM mode, clock output can be dynamically switched. For details, see section 12.7.8, Clock Output Control.

• When GM in SMR = 0 00: Output disabled (SCK pin functions as I/O port.) 01: Clock output 1X: Reserved
• When GM in SMR = 1 00: Output fixed low 01: Clock output 10: Output fixed high 11: Clock output

12.3.7 Serial Status Register (SSR)

SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE, RDRF, ORER, PER, and FER can only be cleared. Some bits in SSR have different functions in normal mode and smart card interface mode.

• When SMIF in SCMR = 0 Bit Bit Name Initial Value R/W TDRE R/(W)* RDRF R/(W)* ORER R/(W)* FER R/(W)* PER R/(W)* TEND R MPB R MPBT R/W Note: * Only 0 can be written, to clear the flag.
• When SMIF in SCMR = 1 Bit Bit Name Initial Value R/W TDRE R/(W)* RDRF R/(W)* ORER R/(W)* ERS R/(W)* PER R/(W)* TEND R MPB R MPBT R/W Note: * Only 0 can be written, to clear the flag.

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7 TDRE 1 R/(W) * Transmit Data Register Empty

Indicates whether TDR contains transmit data. [Setting conditions]

• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR [Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
• When a TXI interrupt request is issued allowing DMAC to write data to TDR

6 RDRF 0 R/(W) * Receive Data Register Full

Indicates whether receive data is stored in RDR. [Setting condition]

• When serial reception ends normally and receive data is transferred from RSR to RDR [Clearing conditions]
• When 0 is written to RDRF after reading RDRF = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
• When an RXI interrupt request is issued allowing DMAC to read data from RDR The RDRF flag is not affected and retains its previous value when the RE bit in SCR is cleared to 0. Note that when the next serial reception is completed while the RDRF flag is being set to 1, an overrun error occurs and the received data is lost.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 391 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description

5 ORER 0 R/(W) * Overrun Error

Indicates that an overrun error has occurred during reception and the reception ends abnormally. [Setting condition]

• When the next serial reception is completed while RDRF = 1 In RDR, receive data prior to an overrun error occurrence is retained, but data received after the overrun error occurrence is lost. When the ORER flag is set to 1, subsequent serial reception cannot be performed. Note that, in clocked synchronous mode, serial transmission also cannot continue. [Clearing condition]
• When 0 is written to ORER after reading ORER = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Even when the RE bit in SCR is cleared, the ORER flag is not affected and retains its previous value.

4 FER 0 R/(W) * Framing Error

Indicates that a framing error has occurred during reception in asynchronous mode and the reception ends abnormally. [Setting condition]

• When the stop bit is 0 In 2-stop-bit mode, only the first stop bit is checked whether it is 1 but the second stop bit is not checked. Note that receive data when the framing error occurs is transferred to RDR, however, the RDRF flag is not set. In addition, when the FER flag is being set to 1, the subsequent serial reception cannot be performed. In clocked synchronous mode, serial transmission also cannot continue. [Clearing condition]
• When 0 is written to FER after reading FER = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Even when the RE bit in SCR is cleared, the FER flag is not affected and retains its previous value.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 392 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description

3 PER 0 R/(W) * Parity Error

Indicates that a parity error has occurred during reception in asynchronous mode and the reception ends abnormally. [Setting condition]

• When a parity error is detected during reception Receive data when the parity error occurs is transferred to RDR, however, the RDRF flag is not set. Note that when the PER flag is being set to 1, the subsequent serial reception cannot be performed. In clocked synchronous mode, serial transmission also cannot continue. [Clearing condition]
• When 0 is written to PER after reading PER = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Even when the RE bit in SCR is cleared, the PER bit is not affected and retains its previous value.

2 TEND 1 R Transmit End

[Setting conditions]

• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of a transmit character [Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When a TXI interrupt request is issued allowing DMAC to write data to TDR

1 MPB 0 R Multiprocessor Bit

Stores the multiprocessor bit value in the receive frame. When the RE bit in SCR is cleared to 0 its previous state is retained.

0 MPBT 0 R/W Multiprocessor Bit Transfer

Sets the multiprocessor bit value to be added to the transmit frame. Note: * Only 0 can be written, to clear the flag.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 393 of 804 REJ09B0104-0300 Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1): Bit Bit Name Initial Value R/W Description Indicates whether TDR contains transmit data. [Setting conditions]

• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR [Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
• When a TXI interrupt request is issued allowing DMAC to write data to TDR

Indicates whether receive data is stored in RDR. [Setting condition]

• When serial reception ends normally and receive data is transferred from RSR to RDR [Clearing conditions]
• When 0 is written to RDRF after reading RDRF = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
• When an RXI interrupt request is issued allowing DMAC to read data from RDR The RDRF flag is not affected and retains its previous value even when the RE bit in SCR is cleared to 0. Note that when the next reception is completed while the RDRF flag is being set to 1, an overrun error occurs and the received data is lost.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 394 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description Indicates that an overrun error has occurred during reception and the reception ends abnormally. [Setting condition]

• When the next serial reception is completed while RDRF = 1 In RDR, the receive data prior to an overrun error occurrence is retained, but data received following the overrun error occurrence is lost. When the ORER flag is set to 1, subsequent serial reception cannot be performed. Note that, in clocked synchronous mode, serial transmission also cannot continue. [Clearing condition]
• When 0 is written to ORER after reading ORER = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Even when the RE bit in SCR is cleared, the ORER flag is not affected and retains its previous value.

4 ERS 0 R/(W) * Error Signal Status

[Setting condition]

• When a low error signal is sampled [Clearing condition]
• When 0 is written to ERS after reading ERS = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 395 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description Indicates that a parity error has occurred during reception in asynchronous mode and the reception ends abnormally. [Setting condition]

• When a parity error is detected during reception Receive data when the parity error occurs is transferred to RDR, however, the RDRF flag is not set. Note that when the PER flag is being set to 1, the subsequent serial reception cannot be performed. In clocked synchronous mode, serial transmission also cannot continue. [Clearing condition]
• When 0 is written to PER after reading PER = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Even when the RE bit in SCR is cleared, the PER flag is not affected and retains its previous value.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 396 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description This bit is set to 1 when no error signal is sent from the receiving side and the next transmit data is ready to be transferred to TDR. [Setting conditions]

• When both the TE and ERS bits in SCR are 0
• When ERS = 0 and TDRE = 1 after a specified time passed after completion of 1-byte data transfer. The set timing depends on the register setting as follows: When GM = 0 and BLK = 0, 2.5 etu after transmission start When GM = 0 and BLK = 1, 1.5 etu after transmission start When GM = 1 and BLK = 0, 1.0 etu after transmission start When GM = 1 and BLK = 1, 1.0 etu after transmission start [Clearing conditions]
• When 0 is written to TEND after reading TEND = 1
• When a TXI interrupt request is issued allowing DMAC to write the next data to TDR

Not used in smart card interface mode. Write 0 to this bit in smart card interface mode. Note: * Only 0 can be written, to clear the flag.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 397 of 804 REJ09B0104-0300

12.3.8 Smart Card Mode Register (SCMR)

SCMR selects smart card interface mode and its format. R R R R R Bit Bit Name Initial Value R/W SDIR R/W SINV R/W SMIF R/W Bit Bit Name Initial Value R/W Description 7 to 4  All 1 R Reserved These are read-only bits and cannot be modified.

3 SDIR 0 R/W Smart Card Data Transfer Direction

Selects the serial/parallel conversion format. 0: Transfer with LSB-first 1: Transfer with MSB-first This bit is valid only when the 8-bit data format is used for transmission/reception; when the 7-bit data format is used, data is always transmitted/received with LSB-first.

2 SINV 0 R/W Smart Card Data Invert

Inverts the transmit/receive data logic level. This bit does not affect the logic level of the parity bit. To invert the parity bit, invert the O/E bit in SMR. 0: TDR contents are transmitted as they are. Receive data is stored as it is in RDR. 1: TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR. 1  1 R Reserved This is a read-only bit and cannot be modified.

0 SMIF 0 R/W Smart Card Interface Mode Select

When this bit is set to 1, smart card interface mode is selected. 0: Normal asynchronous or clocked synchronous mode 1: Smart card interface mode

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 398 of 804 REJ09B0104-0300

12.3.9 Bit Rate Register (BRR)

BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 12.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and clocked synchronous mode, and smart card interface mode. The initial value of BRR is H'FF, and it can be read from or written to by the CPU at all times. Table 12.2 Relationships between N Setting in BRR and Bit Rate B Mode Bit Rate Error Asynchronous mode N = − 1 64 × 2 × B 2n – 1 Pφ × 106 2n – 1 Pφ × 106 Clocked synchronous mode N = − 1 8 × 2 × B 2n – 1 Pφ × 106 Smart card interface mode N = − 1 S × 2 × B Pφ × 106 2n + 1 Error (%) = – 1 × 1002n + 1 Pφ × 106 { } [Legend] B: Bit rate (bit/s) N: BRR setting for baud rate generator (0 ≤ N ≤ 255) Pφ: Operating frequency (MHz) n and S: Determined by the SMR settings shown in the following table. SMR Setting SMR Setting CKS1 CKS0 n BCP1 BCP0 S 0 0 0 0 0 32 0 1 1 0 1 64 1 0 2 1 0 372 1 1 3 1 1 256 Table 12.3 shows sample N settings in BRR in normal asynchronous mode. Table 12.4 shows the maximum bit rate settable for each operating frequency. Tables 12.6 and 12.8 show sample N settings in BRR in clocked synchronous mode and smart card interface mode, respectively. In smart card interface mode, the number of basic clock cycles S in a 1-bit data transfer time can be selected. For details, see section 12.7.4, Receive Data Sampling Timing and Reception Margin. Tables 12.5 and 12.7 show the maximum bit rates with external clock input.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 399 of 804 REJ09B0104-0300 Table 12.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Operating Frequency Pφ (MHz) 8 9.8304 10 12 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 141 0.03 2 174 –0.26 2 177 –0.25 2 212 0.03 150 2 103 0.16 2 127 0.00 2 129 0.16 2 155 0.16 300 1 207 0.16 1 255 0.00 2 64 0.16 2 77 0.16 600 1 103 0.16 1 127 0.00 1 129 0.16 1 155 0.16 1200 0 207 0.16 0 255 0.00 1 64 0.16 1 77 0.16 2400 0 103 0.16 0 127 0.00 0 129 0.16 0 155 0.16 4800 0 51 0.16 0 63 0.00 0 64 0.16 0 77 0.16 9600 0 25 0.16 0 31 0.00 0 32 –1.36 0 38 0.16 19200 0 12 0.16 0 15 0.00 0 15 1.73 0 19 –2.34 31250 0 7 0.00 0 9 –1.70 0 9 0.00 0 11 0.00 38400    0 7 0.00 0 7 1.73 0 9 –2.34 Operating Frequency Pφ (MHz) 12.288 14 14.7456 16 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 217 0.08 2 248 –0.17 3 64 0.70 3 70 0.03 150 2 159 0.00 2 181 0.16 2 191 0.00 2 207 0.16 300 2 79 0.00 2 90 0.16 2 95 0.00 2 103 0.16 600 1 159 0.00 1 181 0.16 1 191 0.00 1 207 0.16 1200 1 79 0.00 1 90 0.16 1 95 0.00 1 103 0.16 2400 0 159 0.00 0 181 0.16 0 191 0.00 0 207 0.16 4800 0 79 0.00 0 90 0.16 0 95 0.00 0 103 0.16 9600 0 39 0.00 0 45 –0.93 0 47 0.00 0 51 0.16 19200 0 19 0.00 0 22 –0.93 0 23 0.00 0 25 0.16 31250 0 11 2.40 0 13 0.00 0 14 –1.70 0 15 0.00 38400 0 9 0.00    0 11 0.00 0 12 0.16

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 400 of 804 REJ09B0104-0300 Table 12.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency Pφ (MHz) 17.2032 18 19.6608 20 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 3 75 0.48 3 79 –0.12 3 86 0.31 3 88 –0.25 150 2 223 0.00 2 233 0.16 2 255 0.00 3 64 0.16 300 2 111 0.00 2 116 0.16 2 127 0.00 2 129 0.16 600 1 223 0.00 1 233 0.16 1 255 0.00 2 64 0.16 1200 1 111 0.00 1 116 0.16 1 127 0.00 1 129 0.16 2400 0 223 0.00 0 233 0.16 0 255 0.00 1 64 0.16 4800 0 111 0.00 0 116 0.16 0 127 0.00 0 129 0.16 9600 0 55 0.00 0 58 –0.69 0 63 0.00 0 64 0.16 19200 0 27 0.00 0 28 1.02 0 31 0.00 0 32 –1.36 31250 0 16 1.20 0 17 0.00 0 19 –1.70 0 19 0.00 38400 0 13 0.00 0 14 –2.34 0 15 0.00 0 15 1.73 Operating Frequency Pφ (MHz) 25 30 33 35 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 3 110 –0.02 3 132 0.13 3 145 0.33 3 154 0.23 150 3 80 –0.47 3 97 –0.35 3 106 0.39 3 113 –0.06 300 2 162 0.15 2 194 0.16 2 214 –0.07 2 227 0.00 600 2 80 –0.47 2 97 –0.35 2 106 0.39 2 113 0.00 1200 1 162 0.15 1 194 0.16 1 214 –0.07 1 227 0.00 2400 1 80 –0.47 1 97 –0.35 1 106 0.39 1 113 0.00 4800 0 162 0.15 0 194 0.16 0 214 –0.07 0 227 0.00 9600 0 80 –0.47 0 97 –0.35 0 106 0.39 0 113 0.00 19200 0 40 –0.76 0 48 –0.35 0 53 –0.54 0 56 0.00 31250 0 24 0.00 0 29 0 0 32 0 0 34 0.00 38400 0 19 1.73 0 23 1.73 0 26 –0.54 0 28 –1.78

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 401 of 804 REJ09B0104-0300 Table 12.4 Maximum Bit Rate for Each Operating Frequency (Asynchronous Mode) Pφ (MHz) Maximum Bit Rate (bit/s) n N P φ (MHz) Maximum Bit Rate (bit/s) n N 8 250000 0 0 17.2032 537600 0 0 9.8304 307200 0 0 18 562500 0 0 10 312500 0 0 19.6608 614400 0 0 12 375000 0 0 20 625000 0 0 12.288 384000 0 0 25 781250 0 0 14 437500 0 0 30 937500 0 0 14.7456 460800 0 0 33 1031250 0 0 16 500000 0 0 35 1093750 0 0 Table 12.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) Pφ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) P φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 8 2.0000 125000 17.2032 4.3008 268800 9.8304 2.4576 153600 18 4.5000 281250 10 2.5000 156250 19.6608 4.9152 307200 12 3.0000 187500 20 5.0000 312500 12.288 3.0720 192000 25 6.2500 390625 14 3.5000 218750 30 7.5000 468750 14.7456 3.6864 230400 33 8.2500 515625 16 4.0000 250000 35 8.7500 546875

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 402 of 804 REJ09B0104-0300 Table 12.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency Pφ (MHz) 8 10 16 20 Bit Rate (bit/s) n N n N n N n N 110 250 3 124   3 249 500 2 249   3 124   1k 2 124   2 249   2.5k 1 199 1 249 2 99 2 124 5k 1 99 1 124 1 199 1 249 10k 0 199 0 249 1 99 1 124 25k 0 79 0 99 0 159 0 199 50k 0 39 0 49 0 79 0 99 100k 0 19 0 24 0 39 0 49 250k 0 7 0 9 0 15 0 19 500k 0 3 0 4 0 7 0 9 1M 0 1 0 3 0 4 2.5M 0 0 * 0 1

5 M 0 0 *

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 403 of 804 REJ09B0104-0300 Operating Frequency Pφ (MHz) 25 30 33 35 Bit Rate (bit/s) n N n N n N n N 110 250 500 3 233 1k 3 97 3 116 3 128 3 136 2.5k 2 155 2 187 2 205 2 218 5k 2 77 2 93 2 102 2 108 10k 1 155 1 187 1 205 1 218 25k 0 249 1 74 1 82 1 87 50k 0 124 0 149 0 164 0 174 100k 0 62 0 74 0 82 0 87 250k 0 24 0 29 0 32 0 34 [Legend] Space : Setting prohibited.  : Can be set, but there will be error. * : Continuous transmission or reception is not possible. Table 12.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) Pφ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) P φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 8 1.3333 1333333.3 20 3.3333 3333333.3 10 1.6667 1666666.7 25 4.1667 4166666.7 12 2.0000 2000000.0 30 5.0000 5000000.0 14 2.3333 2333333.3 33 5.5000 5500000.0 16 2.6667 2666666.7 35 5.8336 5833625.0 18 3.0000 3000000.0

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 404 of 804 REJ09B0104-0300 Table 12.8 BRR Settings for Various Bit Rates (Smart Card Interface Mode, n = 0, S = 372) Operating Frequency Pφ (MHz) 7.1424 10.00 10.7136 13.00 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 9600 0 0 0.00 0 1 30 0 1 25 0 1 8.99 Operating Frequency Pφ (MHz) 14.2848 16.00 18.00 20.00 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 9600 0 1 0.00 0 1 12.01 0 2 15.99 0 2 6.60 Operating Frequency Pφ (MHz) 25.00 30.00 33.00 35.00 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 9600 0 3 12.49 0 3 5.01 0 4 7.59 0 4 1.99 Table 12.9 Maximum Bit Rate for Each Operating Frequency (Smart Card Interface Mode, S = 372) Pφ (MHz) Maximum Bit Rate (bit/s) n N P φ (MHz) Maximum Bit Rate (bit/s) n N 7.1424 9600 0 0 18.00 24194 0 0 10.00 13441 0 0 20.00 26882 0 0 10.7136 14400 0 0 25.00 33602 0 0 13.00 17473 0 0 30.00 40323 0 0 14.2848 19200 0 0 33.00 44355 0 0 16.00 21505 0 0 35.00 47043 0 0

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 405 of 804 REJ09B0104-0300

12.4 Operation in Asynchronous Mode

Figure 12.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transmit/receive data, a parity bit, and finally stop bits (high level). In asynchronous serial communication, the communication line is usually held in the mark state (high level). The SCI monitors the communication line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transmission and reception. LSB Start bit MSB Idle state (mark state) Stop bit Transmit/receive data D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 1 Serial data Parity bit 1 bit 1 or 2 bits 7 or 8 bits 1 bit or none One unit of transfer data (character or frame) Figure 12.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits)

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 406 of 804 REJ09B0104-0300

12.4.1 Data Transfer Format

Table 12.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, see section 12.5, Multiprocessor Communication Function. Table 12.10 Serial Transfer Formats (Asynchronous Mode) PE S 8-bit data STOP S 7-bit data STOP S 8-bit data STOP STOP S 8-bit data P STOP S 7-bit data STOPP S 8-bit data MPB STOP S 8-bit data MPB STOP STOP S 7-bit data STOPMPB S 7-bit data STOPMPB STOP S 7-bit data STOPSTOP CHR MP STOP SMR Settings 123456789 1 0 1 1 1 2 Serial Transmit/Receive Format and Frame Length STOPS 8-bit data P STOP S 7-bit data STOPP STOP [Legend] S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 407 of 804 REJ09B0104-0300

12.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode

In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Since receive data is sampled at the rising edge of the 8th pulse of the basic clock, data is latched at the middle of each bit, as shown in figure 12.3. Thus the reception margin in asynchronous mode is determined by formula (1) below. N | D – 0.5 | M: Reception margin N: Ratio of bit rate to clock (N = 16) D: Duty cycle of clock (D = 0.5 to 1.0) L: Frame length (L = 9 to 12) F: Absolute value of clock frequency deviation Assuming values of F = 0 and D = 0.5 in formula (1), the reception margin is determined by the formula below. However, this is only the computed value, and a margin of 20% to 30% should be allowed in system design. Internal basic clock 16 clocks 8 clocks Receive data (RxD) Synchronization sampling timing Start bit D0 D1 Data sampling timing 15 0 7 15 00 7 Figure 12.3 Receive Data Sampling Timing in Asynchronous Mode

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 408 of 804 REJ09B0104-0300

12.4.3 Clock

Either an internal clock generated by the on-chip baud rate generator or an external clock input to the SCK pin can be selected as the SCI's transfer clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input to the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 12.4. 1 frame D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 SCK TxD Figure 12.4 Phase Relation between Output Clock and Transmit Data (Asynchronous Mode)

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 409 of 804 REJ09B0104-0300

12.4.4 SCI Initialization (Asynchronous Mode)

Before transmitting and receiving data, first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 12.5. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the RDRF, PER, FER, and ORER flags, or RDR. When the external clock is used in asynchronous mode, the clock must be supplied even during initialization. Wait <Initialization completion> Start initialization Set data transfer format in SMR and SCMR [2]Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0) No Yes Set value in BRR Set corresponding bit in ICR to 1 [3] [4] Set TE or RE bit in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits [5] 1-bit interval elapsed [1] Set the bit in ICR for the corresponding pin when receiving data or using an external clock. [2] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock output is selected in asynchronous mode, the clock is output immediately after SCR settings are made. [3] Set the data transfer format in SMR and SCMR. [4] Write a value corresponding to the bit rate to BRR. This step is not necessary if an external clock is used. [5] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. [1] Clear TE and RE bits in SCR to 0 Figure 12.5 Sample SCI Initialization Flowchart

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 410 of 804 REJ09B0104-0300

12.4.5 Serial Data Transmission (Asynchronous Mode)

Figure 12.6 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a TXI interrupt request is generated. Because the TXI interrupt processing routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or multiprocessor bit (may be omitted depending on the format), and stop bit. 4. The SCI checks the TDRE flag at the timing for sending the stop bit. 5. If the TDRE flag is 0, the next transmit data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. 6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. Figure 12.7 shows a sample flowchart for transmission in asynchronous mode. TDRE TEND 1 frame D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 1 1 1 DataStart bit Parity bit Stop bit Start bit Data Parity bit Stop bit TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt processing routine TEI interrupt request generated Idle state (mark state) TXI interrupt request generated Figure 12.6 Example of Operation for Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit)

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 411 of 804 REJ09B0104-0300 No <End> [1] Yes Initialization Start transmission Read TDRE flag in SSR [2] Write transmit data to TDR and clear TDRE flag in SSR to 0 No Yes No Yes Read TEND flag in SSR [3] No Yes [4] Clear DR to 0 and set DDR to 1 Clear TE bit in SCR to 0 TDRE = 1 All data transmitted? TEND = 1 Break output [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a 1 is output for a frame, and transmission is enabled. [2] SCI state check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and clear the TDRE flag to 0. However, the TDRE flag is checked and cleared automatically when the DMAC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port corresponding to the TxD pin to 1, clear DR to 0, then clear the TE bit in SCR to 0. Figure 12.7 Sample Serial Transmission Flowchart

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 412 of 804 REJ09B0104-0300

12.4.6 Serial Data Reception (Asynchronous Mode)

Figure 12.8 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, stores receive data in RSR, and checks the parity bit and stop bit. 2. If an overrun error (when reception of the next data is completed while the RDRF flag in SSR is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 4. If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 5. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt processing routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled. RDRF FER 1 frame D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 0 1 1 DataStart bit Parity bit Stop bit Start bit Data Parity bit Stop bit ERI interrupt request generated by framing error Idle state (mark state) RDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine RXI interrupt request generated Figure 12.8 Example of SCI Operation for Reception (Example with 8-Bit Data, Parity, One Stop Bit)

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 413 of 804 REJ09B0104-0300 Table 12.11 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 12.9 shows a sample flowchart for serial data reception. Table 12.11 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF * ORER FER PER Receive Data Receive Error Type 1 1 0 0 Lost Overrun error 0 0 1 0 Transferred to RDR Framing error 0 0 0 1 Transferred to RDR Parity error 1 1 1 0 Lost Overrun error + framing error 1 1 0 1 Lost Overrun error + parity error 0 0 1 1 Transferred to RDR Framing error + parity error 1 1 1 1 Lost Overrun error + framing error + parity error Note: * The RDRF flag retains the stat e it had before data reception.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 414 of 804 REJ09B0104-0300 Yes <End> [1] No Initialization Start reception [2] No Yes Read RDRF flag in SSR [4] [5] Clear RE bit in SCR to 0 Read ORER, PER, and FER flags in SSR Error processing (Continued on next page) [3] Read receive data in RDR, and clear RDRF flag in SSR to 0 No Yes PER ∨ FER ∨ ORER = 1 RDRF = 1 All data received? [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing and break detection: If a receive error occurs, read the ORER, PER, and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the ORER, PER, and FER flags are all cleared to 0. Reception cannot be resumed if any of these flags are set to 1. In the case of a framing error, a break can be detected by reading the value of the input port corresponding to the RxD pin. [4] SCI state check and receive data read: Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag and RDR, and clear the RDRF flag to 0. However, the RDRF flag is cleared automatically when the DMAC is initiated by an RXI interrupt and reads data from RDR. Figure 12.9 Sample Serial Reception Flowchart (1)

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 415 of 804 REJ09B0104-0300 <End> [3] Error processing Parity error processing Yes No Clear ORER, PER, and FER flags in SSR to 0 No Yes No Yes Framing error processing No Yes Overrun error processing ORER = 1 FER = 1 Break? PER = 1 Clear RE bit in SCR to 0 Figure 12.9 Sample Serial Reception Flowchart (2)

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 416 of 804 REJ09B0104-0300

12.5 Multiprocessor Communication Function

Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station, and a data transmission cycle for the specified receiving station. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 12.10 shows an example of inter-processor communication using the multiprocessor format. The transmitting station first sends data which includes the ID code of the receiving station and a multiprocessor bit set to 1. It then transmits transmit data added with the multiprocessor bit cleared to 0. The receiving station skips data until data with the multiprocessor bit set to 1 is sent. When data with the multiprocessor bit set to 1 is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip data until data with the multiprocessor bit set to 1 is again received. The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1, transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags, RDRF, FER, and ORER in SSR to 1 are prohibited until data with the multiprocessor bit set to 1 is received. On reception of a receive character with the multiprocessor bit set to 1, the MPBR bit in SSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt is generated. When the multiprocessor format is selected, the parity bit setting is invalid. All other bit settings are the same as those in normal asynchronous mode. The clock used for multiprocessor communication is the same as that in normal asynchronous mode.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 417 of 804 REJ09B0104-0300 Transmitting station Receiving station A Receiving station B Receiving station C Receiving station D Communication line Serial data ID transmission cycle = receiving station specification Data transmission cycle = Data transmission to receiving station specified by ID (MPB = 1) (MPB = 0) H'01 H'AA [Legend] MPB: Multiprocessor bit Figure 12.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 418 of 804 REJ09B0104-0300

12.5.1 Multiprocessor Serial Data Transmission

Figure 12.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode. No <End> [1] Yes Initialization Start transmission Read TDRE flag in SSR [2] Write transmit data to TDR and set MPBT bit in SSR No Yes No Yes Read TEND flag in SSR [3] No Yes [4] Clear DR to 0 and set DDR to 1 Clear TE bit in SCR to 0 TDRE = 1 All data transmitted? TEND = 1 Break output? Clear TDRE flag to 0 [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a 1 is output for one frame, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. However, the TDRE flag is checked and cleared automatically when the DMAC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port to 1, clear DR to 0, and then clear the TE bit in SCR to 0. Figure 12.11 Sample Multiprocessor Serial Transmission Flowchart

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12.5.2 Multiprocessor Serial Data Reception

Figure 12.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 12.12 shows an example of SCI operation for multiprocessor format reception. MPIE RDR value 0D 0 D 1 D 71 1 0D 0 D 1 D7 01 1 1 Data (ID1)Start bit MPB Stop bit Start bit Data (Data 1) MPB Stop bit Data (ID2)Start bit Stop bit Start bit Data (Data 2) Stop bit RXI interrupt request (multiprocessor interrupt) generated Idle state (mark state)RDRF RDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine If not this station’s ID, MPIE bit is set to 1 again RXI interrupt request is not generated, and RDR retains its state ID1 (a) Data does not match station’s ID MPIE RDR value 0D 0 D 1 D 71 1 0D 0 D 1 D7 01 1 1MPB MPB RXI interrupt request (multiprocessor interrupt) generated Idle state (mark state)RDRF RDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine Matches this station’s ID, so reception continues, and data is received in RXI interrupt processing routine MPIE bit set to 1 again ID2 (b) Data matches station’s ID Data 2ID1 MPIE = 0 MPIE = 0 Figure 12.12 Example of SCI Operation for Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 420 of 804 REJ09B0104-0300 Yes <End> [1] No Initialization Start reception No Yes [4] Clear RE bit in SCR to 0 Error processing (Continued on next page) [5]No Yes FER ∨ ORER = 1 RDRF = 1 All data received? Set MPIE bit in SCR to 1 [2] Read ORER and FER flags in SSR Read RDRF flag in SSR [3] Read receive data in RDR No Yes This station’s ID? Read ORER and FER flags in SSR Yes No Read RDRF flag in SSR No Yes FER ∨ ORER = 1 Read receive data in RDR RDRF = 1 [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] ID reception cycle: Set the MPIE bit in SCR to 1. [3] SCI state check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station’s ID. If the data is not this station’s ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station’s ID, clear the RDRF flag to 0. [4] SCI state check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. [5] Receive error processing and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the ORER and FER flags are both cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin value. Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (1)

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 421 of 804 REJ09B0104-0300 <End> Error processing Yes No Clear ORER, PER, and FER flags in SSR to 0 No Yes No Yes Framing error processing Overrun error processing ORER = 1 FER = 1 Break? Clear RE bit in SCR to 0 [5] Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (2)

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12.6 Operation in Clocked Synchronous Mode

Figure 12.14 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in transfer data consists of 8-bit data. In data transmission, the SCI outputs data from one falling edge of the synchronization clock to the next. In data reception, the SCI receives data in synchronization with the rising edge of the synchronization clock. After 8-bit data is output, the transmission line holds the MSB output state. In clocked synchronous mode, no parity bit or multiprocessor bit is added. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that the next transmit data can be written during transmission or the previous receive data can be read during reception, enabling continuous data transfer. Don't careDon't care One unit of transfer data (character or frame) Bit 0Serial data Synchronization clock Bit 1 Bit 3 Bit 4 Bit 5 LSB MSB Bit 2 Bit 6 Bit 7 Note: * Holds a high level except during continuous transfer. Figure 12.14 Data Format in Clocked Synchronous Communication (LSB-First)

12.6.1 Clock

Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCK pin can be selected, according to the setting of the CKE1 and CKE0 bits in SCR. When the SCI is operated on an internal clock, the synchronization clock is output from the SCK pin. Eight synchronization clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. Note that in the case of reception only, the synchronization clock is output until an overrun error occurs or until the RE bit is cleared to 0.

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12.6.2 SCI Initialization (Clocked Synchronous Mode)

Before transmitting and receiving data, first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 12.15. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change. When the TE bit is cleared to 0, the TDRE flag is set to 1. However, clearing the RE bit to 0 does not initialize the RDRF, PER, FER, and ORER flags, or RDR. Wait <Transfer start> Start initialization Set data transfer format in SMR and SCMR No Yes Set value in BRR Set corresponding bit in ICR to 1 [2] [3] Set TE or RE bit in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits [5] 1-bit interval elapsed? Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0) [1] [1] Set the bit in ICR for the corresponding pin when receiving data or using an external clock. [2] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. [3] Set the data transfer format in SMR and SCMR. [4] Write a value corresponding to the bit rate to BRR. This step is not necessary if an external clock is used. [5] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. Note: In simultaneous transmit and receive operations, the TE and RE bits should both be cleared to 0 or set to 1 simultaneously. Clear TE and RE bits in SCR to 0 [4] Figure 12.15 Sample SCI Initialization Flowchart

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12.6.3 Serial Data Transmission (Clocked Synchronous Mode)

Figure 12.16 shows an example of the operation for transmission in clocked synchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a TXI interrupt request is generated. Because the TXI interrupt processing routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. 8-bit data is sent from the TxD pin synchronized with the output clock when clock output mode has been specified and synchronized with the input clock when use of an external clock has been specified. 4. The SCI checks the TDRE flag at the timing for sending the last bit. 5. If the TDRE flag is cleared to 0, the next transmit data is transferred from TDR to TSR, and serial transmission of the next frame is started. 6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TxD pin retains the output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. The SCK pin is fixed high. Figure 12.17 shows a sample flowchart for serial data transmission. Even if the TDRE flag is cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1. Make sure to clear the receive error flags to 0 before starting transmission. Note that clearing the RE bit to 0 does not clear the receive error flags.

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12.6.4 Serial Data Reception (Clocked Synchronous Mode)

Figure 12.18 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the receive data in RSR. 2. If an overrun error (when reception of the next data is completed while the RDRF flag in SSR is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt processing routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled. Bit 7Serial data Synchronization clock 1 frame RDRF ORER ERI interrupt request generated by overrun error RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine RXI interrupt request generated Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Figure 12.18 Example of Operation for Reception in Clocked Synchronous Mode Transfer cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 12.19 shows a sample flowchart for serial data reception.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 427 of 804 REJ09B0104-0300 Yes <End> [1] No Initialization Start reception [2] No Yes Read RDRF flag in SSR [4] [5] Clear RE bit in SCR to 0 Error processing (Continued below) [3] Read receive data in RDR and clear RDRF flag in SSR to 0 No Yes ORER = 1 RDRF = 1 All data received Read ORER flag in SSR <End> Error processing Overrun error processing Clear ORER flag in SSR to 0 [3] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Reception cannot be resumed if the ORER flag is set to 1. [4] SCI state check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0 should be finished. However, the RDRF flag is cleared automatically when the DMAC is initiated by a receive data full interrupt (RXI) and reads data from RDR. Figure 12.19 Sample Serial Reception Flowchart

12.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous

Mode) Figure 12.20 shows a sample flowchart for simultaneous serial transmit and receive operations. After initializing the SCI, the following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI has finished transmission and the TDRE and TEND flags are set to 1, clear the TE bit to 0. Then simultaneously set both the TE and RE bits to 1 with a single instruction. To switch from receive mode to simultaneous transmit and receive mode, after checking that the SCI has finished reception, clear the RE bit to 0. Then after checking that the RDRF bit and receive error flags (ORER, FER, and PER) are cleared to 0, simultaneously set both the TE and RE bits to 1 with a single instruction.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 428 of 804 REJ09B0104-0300 Yes <End> [1] No Initialization Start transmission/reception [5] Error processing [3] Read receive data in RDR, and clear RDRF flag in SSR to 0 No Yes ORER = 1 All data received? [2]Read TDRE flag in SSR No Yes TDRE = 1 Write transmit data to TDR and clear TDRE flag in SSR to 0 No Yes RDRF = 1 Read ORER flag in SSR [4]Read RDRF flag in SSR Clear TE and RE bits in SCR to 0 [1] SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. [2] SCI state check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Reception cannot be resumed if the ORER flag is set to 1. [4] SCI state check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial transmission/reception continuation procedure: To continue serial transmission/ reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to TDR and clear the TDRE flag to 0. However, the TDRE flag is checked and cleared automatically when the DMAC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR. Similarly, the RDRF flag is cleared automatically when the DMAC is initiated by a receive data full interrupt (RXI) and reads data from RDR. Note: When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the TE bit and RE bit to 0, then set both these bits to 1 simultaneously. Figure 12.20 Sample Flowchart of Simultaneous Serial Transmission and Reception

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12.7 Operation in Smart Card Interface Mode

The SCI supports the IC card (smart card) interface, conforming to ISO/IEC 7816-3 (Identification Card) standard, as an extended serial communication interface function. Smart card interface mode can be selected using the appropriate register.

12.7.1 Sample Connection

Figure 12.21 shows a sample connection between the smart card and this LSI. As in the figure, since this LSI communicates with the IC card using a single transmission line, interconnect the TxD and RxD pins and pull up the data transmission line to V CC using a resistor. Setting the RE and TE bits to 1 with the IC card not connected enables closed transmission/reception allowing self diagnosis. To supply the IC card with the clock pulses generated by the SCI, input the SCK pin output to the CLK pin of the IC card. A reset signal can be supplied via the output port of this LSI. TxD RxD This LSI VCC I/O Main unit of the device to be connected IC card Data line CLK RST SCK Rx (port) Clock line Reset line Figure 12.21 Pin Connection for Smart Card Interface

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12.7.2 Data Format (Except in Block Transfer Mode)

Figure 12.22 shows the data transfer formats in smart card interface mode.

• One frame contains 8-bit data and a parity bit in asynchronous mode.
• During transmission, at least 2 etu (elementary time unit: time required for transferring one bit) is secured as a guard time after the end of the parity bit before the start of the next frame.
• If a parity error is detected during reception, a low error signal is output for 1 etu after 10.5 etu has passed from the start bit.
• If an error signal is sampled during transmission, the same data is automatically re-transmitted after at least 2 etu. Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp In normal transmission/reception Output from the transmitting station Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp When a parity error is generated Output from the transmitting station DE Output from the receiving station [Legend] Ds: Start bit D0 to D7: Data bits Dp: Parity bit DE: Error signal Figure 12.22 Data Formats in Normal Smart Card Interface Mode For communication with the IC cards of the direct convention and inverse convention types, follow the procedure below. Ds AZ ZAZ Z Z ZA A(Z) (Z) state D0 D1 D2 D3 D4 D5 D6 D7 Dp Figure 12.23 Direct Convention (SDIR = SINV = O/E = 0)

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 431 of 804 REJ09B0104-0300 For the direct convention type, logic levels 1 and 0 correspond to states Z and A, respectively, and data is transferred with LSB-first as the start character, as shown in figure 12.23. Therefore, data in the start character in the figure is H'3B. When using the direct convention type, write 0 to both the SDIR and SINV bits in SCMR. Write 0 to the O/E bit in SMR in order to use even parity, which is prescribed by the smart card standard. Ds AZ ZAA A Z AA A(Z) (Z) state D7 D6 D5 D4 D3 D2 D1 D0 Dp Figure 12.24 Inverse Convention (SDIR = SINV = O/E = 1) For the inverse convention type, logic levels 1 and 0 correspond to states A and Z, respectively and data is transferred with MSB-first as the start character, as shown in figure 12.24. Therefore, data in the start character in the figure is H'3F. When using the inverse convention type, write 1 to both the SDIR and SINV bits in SCMR. The parity bit is logic level 0 to produce even parity, which is prescribed by the smart card standard, and corresponds to state Z. Since the SNIV bit of this LSI only inverts data bits D7 to D0, write 1 to the O/E bit in SMR to invert the parity bit in both transmission and reception.

12.7.3 Block Transfer Mode

Block transfer mode is different from normal smart card interface mode in the following respects.

• Even if a parity error is detected during reception, no error signal is output. Since the PER bit in SSR is set by error detection, clear the PER bit before receiving the parity bit of the next frame.
• During transmission, at least 1 etu is secured as a guard time after the end of the parity bit before the start of the next frame.
• Since the same data is not re-transmitted during transmission, the TEND flag is set 11.5 etu after transmission start.
• Although the ERS flag in block transfer mode displays the error signal status as in normal smart card interface mode, the flag is always read as 0 because no error signal is transferred.

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12.7.4 Receive Data Sampling Timing and Reception Margin

Only the internal clock generated by the on-chip baud rate generator can be used as a transfer clock in smart card interface mode. In this mode, the SCI can operate on a basic clock with a frequency of 32, 64, 372, or 256 times the bit rate according to the BCP1 and BCP0 bit settings (the frequency is always 16 times the bit rate in normal asynchronous mode). At reception, the falling edge of the start bit is sampled using the basic clock in order to perform internal synchronization. Receive data is sampled on the 16th, 32nd, 186th and 128th rising edges of the basic clock so that it can be latched at the middle of each bit as shown in figure 12.25. The reception margin here is determined by the following formula. N | D – 0.5 | M: Reception margin (%) N: Ratio of bit rate to clock (N = 32, 64, 372, 256) D: Duty cycle of clock (D = 0 to 1.0) L: Frame length (L = 10) F: Absolute value of clock frequency deviation Assuming values of F = 0, D = 0.5, and N = 372 in the above formula, the reception margin is determined by the formula below. Internal basic clock 372 clock cycles 186 clock cycles Receive data (RxD) Synchronization sampling timing D0 D1 Data sampling timing 185 371 0371185 00 Start bit Figure 12.25 Receive Data Sampling Timing in Smart Card Interface Mode (When Clock Frequency is 372 Times the Bit Rate)

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12.7.5 Initialization

Before transmitting and receiving data, initialize the SCI using the following procedure. Initialization is also necessary before switching from transmission to reception and vice versa. 1. Clear the TE and RE bits in SCR to 0. 2. Set the ICR bit of the corresponding pin to 1. 3. Clear the error flags ERS, PER, and ORER in SSR to 0. 4. Set the GM, BLK, O/E, BCP1, BCP0, CKS1, and CKS0 bits in SMR appropriately. Also set the PE bit to 1. 5. Set the SMIF, SDIR, and SINV bits in SCMR appropriately. When the DDR corresponding to the TxD pin is cleared to 0, the TxD and RxD pins are changed from port pins to SCI pins, placing the pins into high impedance state. 6. Set the value corresponding to the bit rate in BRR. 7. Set the CKE1 and CKE0 bits in SCR appropriately. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0 simultaneously. When the CKE0 bit is set to 1, the SCK pin is allowed to output clock pulses. 8. Set the TIE, RIE, TE, and RE bits in SCR appropriately after waiting for at least a 1-bit interval. Setting the TE and RE bits to 1 simultaneously is prohibited except for self diagnosis. To switch from reception to transmission, first verify that reception has completed, then initialize the SCI. At the end of initialization, RE and TE should be set to 0 and 1, respectively. Reception completion can be verified by reading the RDRF, PER, or ORER flag. To switch from transmission to reception, first verify that transmission has completed, then initialize the SCI. At the end of initialization, TE and RE should be set to 0 and 1, respectively. Transmission completion can be verified by reading the TEND flag.

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12.7.6 Data Transmission (Except in Block Transfer Mode)

Data transmission in smart card interface mode (except in block transfer mode) is different from that in normal serial communication interface mode in that an error signal is sampled and data can be re-transmitted. Figure 12.26 shows the data re-transfer operation during transmission. 1. If an error signal from the receiving end is sampled after one frame of data has been transmitted, the ERS bit in SSR is set to 1. Here, an ERI interrupt request is generated if the RIE bit in SCR is set to 1. Clear the ERS bit to 0 before the next parity bit is sampled. 2. For the frame in which an error signal is received, the TEND bit in SSR is not set to 1. Data is re-transferred from TDR to TSR allowing automatic data retransmission. 3. If no error signal is returned from the receiving end, the ERS bit in SSR is not set to 1. 4. In this case, one frame of data is determined to have been transmitted including re-transfer, and the TEND bit in SSR is set to 1. Here, a TXI interrupt request is generated if the TIE bit in SCR is set to 1. Writing transmit data to TDR starts transmission of the next data. Figure 12.28 shows a sample flowchart for transmission. All the processing steps are automatically performed using a TXI interrupt request to activate the DMAC. In transmission, the TEND and TDRE flags in SSR are simultaneously set to 1, thus generating a TXI interrupt request if the TIE bit in SCR has been set to 1. This activates the DMAC by a TXI request thus allowing transfer of transmit data if the TXI interrupt request is specified as a source of DMAC activation beforehand. The TDRE and TEND flags are automatically cleared to 0 at data transfer by the DMAC. If an error occurs, the SCI automatically re-transmits the same data. During re- transmission, TEND remains as 0, thus not activating the DMAC. Therefore, the SCI and DMAC automatically transmit the specified number of bytes, including re-transmission in the case of error occurrence. However, the ERS flag is not automatically cleared; the ERS flag must be cleared by previously setting the RIE bit to 1 to enable an ERI interrupt request to be generated at error occurrence. When transmitting/receiving data using the DMAC, be sure to set and enable the DMAC prior to making SCI settings. For DMAC settings, see section 7, DMA Controller (DMAC).

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 436 of 804 REJ09B0104-0300 Initialization No Yes Clear TE bit in SCR to 0 Start transmission Start No No No Yes Yes Yes Yes No End Write data to TDR and clear TDRE flag in SSR to 0 Error processing Error processing TEND = 1? All data transmitted? TEND = 1? ERS = 0? ERS = 0? Figure 12.28 Sample Transmission Flowchart

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 437 of 804 REJ09B0104-0300

12.7.7 Serial Data Reception (Except in Block Transfer Mode)

Data reception in smart card interface mode is similar to that in normal serial communication interface mode. Figure 12.29 shows the data re-transfer operation during reception. 1. If a parity error is detected in receive data, the PER bit in SSR is set to 1. Here, an ERI interrupt request is generated if the RIE bit in SCR is set to 1. Clear the PER bit to 0 before the next parity bit is sampled. 2. For the frame in which a parity error is detected, the RDRF bit in SSR is not set to 1. 3. If no parity error is detected, the PER bit in SSR is not set to 1. 4. In this case, data is determined to have been received successfully, and the RDRF bit in SSR is set to 1. Here, an RXI interrupt request is generated if the RIE bit in SCR is set to 1. Figure 12.30 shows a sample flowchart for reception. All the processing steps are automatically performed using an RXI interrupt request to activate the DMAC. In reception, setting the RIE bit to 1 allows an RXI interrupt request to be generated when the RDRF flag is set to 1. This activates the DMAC by an RXI request thus allowing transfer of receive data if the RXI interrupt request is specified as a source of DMAC activation beforehand. The RDRF flag is automatically cleared to 0 at data transfer by the DMAC. If an error occurs during reception, i.e., either the ORER or PER flag is set to 1, a transmit/receive error interrupt (ERI) request is generated and the error flag must be cleared. If an error occurs, the DMAC is not activated and receive data is skipped, therefore, the number of bytes of receive data specified in the DMAC is transferred. Even if a parity error occurs and the PER bit is set to 1 in reception, receive data is transferred to RDR, thus allowing the data to be read. Note: For operations in block transfer mode, see section 12.4, Operation in Asynchronous Mode. D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) Ds D0 D1 D2 D3 D4Ds (n + 1) th transfer frameRetransfer framenth transfer frame RDRF [1] PER [2] [3] [4] Figure 12.29 Data Re-Transfer Operation in SCI Reception Mode

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 438 of 804 REJ09B0104-0300 Initialization Read data from RDR and clear RDRF flag in SSR to 0 Clear RE bit in SCR to 0 Start reception Start Error processing No No No Yes Yes ORER = 0 and PER = 0? RDRF = 1? All data received? Yes Figure 12.30 Sample Reception Flowchart

12.7.8 Clock Output Control

Clock output can be fixed using the CKE1 and CKE0 bits in SCR when the GM bit in SMR is set to 1. Specifically, the minimum width of a clock pulse can be specified. Figure 12.31 shows an example of clock output fixing timing when the CKE0 bit is controlled with GM = 1 and CKE1 = 0. Given pulse width SCK CKE0 Given pulse width Figure 12.31 Clock Output Fixing Timing

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 439 of 804 REJ09B0104-0300 At power-on and transitions to/from software standby mode, use the following procedure to secure the appropriate clock duty cycle.

• At power-on To secure the appropriate clock duty cycle simultaneously with power-on, use the following procedure. 1. Initially, port input is enabled in the high-impedance state. To fix the potential level, use a pull-up or pull-down resistor. 2. Fix the SCK pin to the specified output using the CKE1 bit in SCR. 3. Set SMR and SCMR to enable smart card interface mode. Set the CKE0 bit in SCR to 1 to start clock output.
• At mode switching  At transition from smart card interface mode to software standby mode 1. Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to the values for the output fixed state in software standby mode. 2. Write 0 to the TE and RE bits in SCR to stop transmission/reception. Simultaneously, set the CKE1 bit to the value for the output fixed state in software standby mode. 3. Write 0 to the CKE0 bit in SCR to stop the clock. 4. Wait for one cycle of the serial clock. In the mean time, the clock output is fixed to the specified level with the duty cycle retained. 5. Make the transition to software standby mode.  At transition from smart card interface mode to software standby mode 6. Clear software standby mode. 7. Write 1 to the CKE0 bit in SCR to start clock output. A clock signal with the appropriate duty cycle is then generated. Software standbyNormal operation Normal operation [6] Figure 12.32 Clock Stop and Restart Procedure

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 440 of 804 REJ09B0104-0300

12.8 Interrupt Sources

12.8.1 Interrupts in Normal Serial Communication Interface Mode

Table 12.12 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt request can activate the DMAC to allow data transfer. The TDRE flag is automatically cleared to 0 at data transfer by the DMAC. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can activate the DMAC to allow data transfer. The RDRF flag is automatically cleared to 0 at data transfer by the DMAC. A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt has priority for acceptance. However, note that if the TDRE and TEND flags are cleared to 0 simultaneously by the TXI interrupt processing routine, the SCI cannot branch to the TEI interrupt processing routine later. Table 12.12 SCI Interrupt Sources Name Interrupt Source Interrupt Flag DMAC Activation Priority ERI Receive error ORER, FER, or PER Not possible High RXI Receive data full RDRF Possible TXI Transmit data empty TDRE Possible TEI Transmit end TEND Not possible Low

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 441 of 804 REJ09B0104-0300

12.8.2 Interrupts in Smart Card Interface Mode

Table 12.13 shows the interrupt sources in smart card interface mode. A transmit end (TEI) interrupt request cannot be used in this mode. Table 12.13 SCI Interrupt Sources Name Interrupt Source Interrupt Flag DMAC Activation Priority ERI Receive error or error signal detection ORER, PER, or ERS Not possible High RXI Receive data full RDRF Possible TXI Transmit data empty TDRE Possible Low Data transmission/reception using the DMAC is also possible in smart card interface mode, similar to in the normal SCI mode. In transmission, the TEND and TDRE flags in SSR are simultaneously set to 1, thus generating a TXI interrupt. This activates the DMAC by a TXI request thus allowing transfer of transmit data if the TXI request is specified as a source of DMAC activation beforehand. The TDRE and TEND flags are automatically cleared to 0 at data transfer by the DMAC. If an error occurs, the SCI automatically re-transmits the same data. During re- transmission, the TEND flag remains as 0, thus not activating the DMAC. Therefore, the SCI and DMAC automatically transmit the specified number of bytes, including re-transmission in the case of error occurrence. However, the ERS flag in SSR, which is set at error occurrence, is not automatically cleared; the ERS flag must be cleared by previously setting the RIE bit in SCR to 1 to enable an ERI interrupt request to be generated at error occurrence. When transmitting/receiving data using the DMAC, be sure to set and enable the DMAC prior to making SCI settings. For DMAC settings, see section 7, DMA Controller (DMAC). In reception, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. This activates the DMAC by an RXI request thus allowing transfer of receive data if the RXI request is specified as a source of DMAC activation beforehand. The RDRF flag is automatically cleared to 0 at data transfer by the DMAC. If an error occurs, the RDRF flag is not set but the error flag is set. Therefore, the DMAC is not activated and an ERI interrupt request is issued to the CPU instead; the error flag must be cleared.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 442 of 804 REJ09B0104-0300

12.9 Usage Notes

12.9.1 Module Stop Mode Setting

Operation of the SCI can be disabled or enabled using the module stop control register. The initial setting is for operation of the SCI to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 19, Power-Down Modes.

12.9.2 Break Detection and Processing

When framing error detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the PER flag may also be set. Note that, since the SCI continues the receive operation even after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again.

12.9.3 Mark State and Break Detection

When the TE bit is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are determined by DR and DDR. This can be used to set the TxD pin to mark state (high level) or send a break during serial data transmission. To maintain the communication line in mark state (the state of 1) until TE is set to 1, set both DDR and DR to 1. Since the TE bit is cleared to 0 at this point, the TxD pin becomes an I/O port, and 1 is output from the TxD pin. To send a break during serial transmission, first set DDR to 1 and DR to 0, and then clear the TE bit to 0. When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin.

12.9.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)

Transmission cannot be started when a receive error flag (ORER, FER, or RER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that the receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 443 of 804 REJ09B0104-0300

12.9.5 Relation between Writing to TDR and TDRE Flag

The TDRE flag in SSR is a status flag which indicates that transmit data has been transferred from TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1. Data can be written to TDR irrespective of the TDRE flag status. However, if new data is written to TDR when the TDRE flag is 0, that is, when the previous data has not been transferred to TSR yet, the previous data in TDR is lost. Be sure to write transmit data to TDR after verifying that the TDRE flag is set to 1.

12.9.6 Restrictions on Using DMAC

• When the external clock source is used as a synchronization clock, update TDR by the DMAC and wait for at least five Pφ clock cycles before allowing the transmit clock to be input. If the transmit clock is input within four clock cycles after TDR modification, the SCI may malfunction (figure 12.33).
• When using the DMAC to read RDR, be sure to set the receive end interrupt (RXI) as the DMAC activation source. t LSB Serial data SCK D1 D3 D4 D5D2 D6 D7 Note: When external clock is supplied, t must be more than four clock cycles. TDRE Figure 12.33 Sample Transmission using DMAC in Clocked Synchronous Mode

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 444 of 804 REJ09B0104-0300

12.9.7 SCI Operations during Mode Transitions

(1) Transmission Before making the transition to module stop mode or software standby mode, stop the transmit operations (TE = TIE = TEIE = 0). TSR, TDR, and SSR are reset. The states of the output pins during module stop mode or software standby mode depend on the port settings, and the pins output a high-level signal after mode cancellation. If the transition is made during data transmission, the data being transmitted will be undefined. To transmit data in the same transmission mode after mode cancellation, set the TE bit to 1, read SSR, write to TDR, clear TDRE in this order, and then start transmission. To transmit data in a different transmission mode, initialize the SCI first. Figure 12.34 shows a sample flowchart for mode transition during transmission. Figures 12.35 and 12.36 show the port pin states during mode transition. (2) Reception Before making the transition to module stop mode or software standby mode, stop the receive operations (RE = 0). RSR, RDR, and SSR are reset. If transition is made during data reception, the data being received will be invalid. To receive data in the same reception mode after mode cancellation, set the RE bit to 1, and then start reception. To receive data in a different reception mode, initialize the SCI first.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 447 of 804 REJ09B0104-0300 Start reception Reception [1] No No Yes Yes Read receive data in RDR Read RDRF flag in SSR Make transition to software standby mode Cancel software standby mode RE = 0 Initialization RE = 1 [2] Change operating mode? RDRF = 1 [1] Data being received will be invalid. [2] Module stop mode is included. Figure 12.37 Sample Flowchart for Mode Transition during Reception

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 448 of 804 REJ09B0104-0300

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 449 of 804 REJ09B0104-0300 Section 13 Controller Area Network (HCAN) The HCAN is a module for controlling a controller area network (CAN) for real time communication in vehicular and industrial equipment systems, etc. For details on CAN specification, refer to Bosch CAN Specification Version 2.0 1991, Robert Bosch GmbH. The block diagram of the HCAN is shown in figure 13.1.

13.1 Features

• CAN version: Bosch 2.0B active compatible  Communication systems: NRZ (Non-Return to Zero) system (with bit-stuffing function)  Broadcast communication system  Transmission path: Bidirectional 2-wire serial communication  Communication speed: Max. 1 Mbps  Data length: 0 to 8 bytes
• Number of channels: 1
• Data buffers: 16 (one receive-only buffer and 15 buffers settable for transmission/reception)
• Data transmission: Two methods  Mailbox (buffer) number order (low-to-high)  Message priority (identifier) reverse-order (high-to-low)
• Data reception: Two methods  Message identifier match (transmit/receive-setting buffers)  Reception with message identifier masked (receive-only)
• CPU interrupts: 12  Error interrupt  Reset processing interrupt  Message reception interrupt  Message transmission interrupt
• HCAN operating modes

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• Support for various modes  Hardware reset  Software reset  Normal status (error-active, error-passive)  Bus off status  HCAN configuration mode  HCAN sleep mode  HCAN halt mode
• Other features  DMAC can be activated by message reception mailbox (HCAN mailbox 0 only)
• Module stop mode can be set Peripheral address bus Peripheral data bus HTxD MBI HRxD CAN Data Link Controller MPI (CDLC) Tx buffer Rx buffer Message buffer Message control, message data, MC0 to MC15, MD0 to MD15 LAFM Mailboxes Microprocessor interface CPU interface Control register Status register HCAN Bosch CAN 2.0B active Figure 13.1 HCAN Block Diagram
• Message Buffer Interface (MBI) The MBI, consisting of mailboxes and a local acceptance filter mask (LAFM), stores CAN transmit/receive messages (identifiers, data, etc.) Transmit messages are written by the CPU. For receive messages, the data received by the CDLC is stored automatically.
• Microprocessor Interface (MPI) The MPI, consisting of a bus interface, control register, status register, etc., controls HCAN internal data, status, and so forth.
• CAN Data Link Controller (CDLC) The CDLC, conforming to the Bosch CAN Ver. 2.0B active standard, performs transmission and reception of messages (data frames, remote frames, error frames, overload frames, inter- frame spacing), as well as CRC checking, bus arbitration, and other functions.

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 451 of 804 REJ09B0104-0300

13.2 Input/Output Pins

Table 13.1 shows the HCAN pin configuration. For the use of these pins, the input buffer control registers (ICR) of the port and the HCAN monitor register (HCANMON) must be specified according to other HCAN settings. In addition, when using HCAN pins, settings must be made in the HCAN configuration mode (during initialization: MCR0 = 1 and GSR3 = 1). Table 13.1 Pin Configuration Name Abbreviation Input/Output Function HCAN transmit data pin HTxD Ou tput CAN bus transmission pin HCAN receive data pin HRxD Input CAN bus reception pin A bus driver is necessary for the interface between the pins and the CAN bus. A Philips PCA82C250 compatible model is recommended.

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 452 of 804 REJ09B0104-0300

13.3 Register Descriptions

The HCAN has the following registers.

• Master control register (MCR)
• General status register (GSR)
• Bit configuration register (BCR)
• Mailbox configuration register (MBCR)
• Transmit wait register (TXPR)
• Transmit wait cancel register (TXCR)
• Transmit acknowledge register (TXACK)
• Abort acknowledge register (ABACK)
• Receive complete register (RXPR)
• Remote request register (RFPR)
• Interrupt register (IRR)
• Mailbox interrupt mask register (MBIMR)
• Interrupt mask register (IMR)
• Receive error counter (REC)
• Transmit error counter (TEC)
• Unread message status register (UMSR)
• Local acceptance filter mask L (LAFML)
• Local acceptance filter mask H (LAFMH)
• Message control (8-bit × 8 registers × 16 sets) (MC0 to MC15)
• Message data (8-bit × 8 registers × 16 sets) (MD0 to MD15)
• HCAN Monitor Register (HCANMON)

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 453 of 804 REJ09B0104-0300

13.3.1 Master Control Register (MCR)

MCR controls the HCAN. MCR7 R/W R MCR5 R/W R R MCR0 R/W MCR2 R/W MCR1 R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description

7 MCR7 0 R/W HCAN Sleep Mode Release

When this bit is set to 1, the HCAN automatically exits HCAN sleep mode on detection of CAN bus operation. 6  0 R Reserved This is a read-only bit and cannot be modified.

5 MCR5 0 R/W HCAN Sleep Mode

When this bit is set to 1, the HCAN enters HCAN sleep mode. When this bit is cleared to 0, HCAN sleep mode is released. 4, 3  All 0 R Reserved These are read-only bits and cannot be modified.

2 MCR2 0 R/W Message Transmission Method

0: Transmission order determined by message identifier priority 1: Transmission order determined by mailbox (buffer) number priority (TXPR1 > TXPR15)

1 MCR1 0 R/W Halt Request

When this bit is set to 1, the HCAN enters HCAN HALT mode. When this bit is cleared to 0, HCAN HALT mode is released.

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 454 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description

0 MCR0 1 R/W Reset Request

When this bit is set to 1, the HCAN enters reset mode. For details, refer to section 13.4.1, Hardware and Software Resets. [Setting conditions]

• Writing 1 (software reset) [Clearing condition]
• When 0 is written to this bit while bit GSR3 in GSR is 1

13.3.2 General Status Register (GSR)

GSR indicates the status of the HCAN. R R R R GSR3 R GSR0 R GSR2 R GSR1 R Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description 7 to 4  All 0 R Reserved These are read-only bits and cannot be modified.

3 GSR3 1 R Reset Status

Indicates whether the HCAN module is in the normal operation state or the reset state. This bit cannot be modified. [Setting conditions]

• When entering configuration mode after the HCAN internal reset has finished
• Sleep mode [Clearing condition]
• When entering the normal operation state after bit MCR0 in MCR is cleared (note that there is delay between clearing bits MCR0 and GSR3.)

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 455 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description

2 GSR2 1 R Message Transmission Status Flag

Indicates whether the module is currently in the message transmission period. This bit cannot be modified. [Setting condition]

• Start of message transmission (SOF) [Clearing condition]
• Third bit of Intermission after EOF (End of Frame)

1 GSR1 0 R Transmit/Receive Warning Flag

This bit cannot be modified. [Clearing condition]

• When TEC < 96 and REC < 96
• When TEC ≥ 256 (bus off state) [Setting condition]
• When TEC ≥ 96 or REC ≥ 96

0 GSR0 0 R Bus Off Flag

This bit cannot be modified. [Setting condition]

• When TEC ≥ 256 (bus off state) [Clearing condition]
• Recovery from bus off state

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 456 of 804 REJ09B0104-0300

13.3.3 Bit Configuration Register (BCR)

BCR sets HCAN bit timing parameters and the baud rate. For details on parameters, refer to section 13.4.2, Initialization after Hardware Reset. BCR7 R/W BCR6 R/W BCR5 R/W BCR4 R/W BCR3 R/W BCR0 R/W BCR2 R/W BCR1 R/W Bit Bit Name Initial Value R/W BCR15 R/W BCR14 R/W BCR13 R/W BCR12 R/W BCR11 R/W BCR8 R/W BCR10 R/W BCR9 R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description BCR7 BCR6 R/W R/W Re-Synchronization Jump Width (SJW) Set the maximum bit synchronization width. 00: 1 time quantum 01: 2 time quanta 10: 3 time quanta 11: 4 time quanta BCR5 BCR4 BCR3 BCR2 BCR1 BCR0 R/W R/W R/W R/W R/W R/W Baud Rate Prescaler (BRP) Set the length of time quanta. 000000: 2 × system clock 000001: 4 × system clock 000010: 6 × system clock 111111: 128 × system clock

7 BCR15 0 R/W Bit Sample Point (BSP)

Sets the point at which data is sampled. 0: Bit sampling at one point (end of time segment 1 (TSEG1)) 1: Bit sampling at three points (end of TSEG1 and preceding and following time quanta)

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 457 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description BCR14 BCR13 BCR12 R/W R/W R/W Time Segment 2 (TSEG2) Set the TSEG2 width within a range of 2 to 8 time quanta. 000: Setting prohibited 001: 2 time quanta 010: 3 time quanta 011: 4 time quanta 100: 5 time quanta 101: 6 time quanta 110: 7 time quanta 111: 8 time quanta BCR11 BCR10 BCR9 BCR8 R/W R/W R/W R/W Time Segment 1 (TSEG1) Set the TSEG1 (PRSEG + PHSEG1) width to between 4 and 16 time quanta. 0000: Setting prohibited 0001: Setting prohibited 0010: Setting prohibited 0011: 4 time quanta 0100: 5 time quanta 0101: 6 time quanta 0110: 7 time quanta 0111: 8 time quanta 1000: 9 time quanta 1001: 10 time quanta 1010: 11 time quanta 1011: 12 time quanta 1100: 13 time quanta 1101: 14 time quanta 1110: 15 time quanta 1111: 16 time quanta

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 458 of 804 REJ09B0104-0300

13.3.4 Mailbox Configuration Register (MBCR)

MBCR sets the transfer direction for each mailbox. MBCR7 R/W MBCR6 R/W MBCR5 R/W MBCR4 R/W MBCR3 R/W R MBCR2 R/W MBCR1 R/W Bit Bit Name Initial Value R/W MBCR15 R/W MBCR14 R/W MBCR13 R/W MBCR12 R/W MBCR11 R/W MBCR8 R/W MBCR10 R/W MBCR9 R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description MBCR7 MBCR6 MBCR5 MBCR4 MBCR3 MBCR2 MBCR1 MBCR15 MBCR14 MBCR13 MBCR12 MBCR11 MBCR10 MBCR9 MBCR8 R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W These bits set the transfer direction for the corresponding mailboxes 1 to 15. MBCRn determines the transfer direction for mailbox n (n =1 to 15). 0: Corresponding mailbox is set for transmission 1: Corresponding mailbox is set for reception Bit 8 is reserved. This is a read-only bit and cannot be modified.

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13.3.5 Transmit Wait Register (TXPR)

TXPR makes transmit messages stored in mailboxes enter the transmit wait state (CAN bus arbitration wait). TXPR7 R/W TXPR6 R/W TXPR5 R/W TXPR4 R/W TXPR3 R/W R TXPR2 R/W TXPR1 R/W Bit Bit Name Initial Value R/W TXPR15 R/W TXPR14 R/W TXPR13 R/W TXPR12 R/W TXPR11 R/W TXPR8 R/W TXPR10 R/W TXPR9 R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description TXPR7 TXPR6 TXPR5 TXPR4 TXPR3 TXPR2 TXPR1 TXPR15 TXPR14 TXPR13 TXPR12 TXPR11 TXPR10 TXPR9 TXPR8 R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W These bits set a transmit wait (CAN bus arbitration wait) for the corresponding mailboxes 1 to 15. When TXPRn (n = 1 to 15) is set to 1, the message in mailbox n becomes the transmit wait state. [Clearing conditions] Completion of message transmission Completion of transmission cancellation Bit 8 is reserved. This is a read-only bit and cannot be modified.

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 460 of 804 REJ09B0104-0300

13.3.6 Transmit Wait Cancel Register (TXCR)

TXCR cancels transmit wait messages in mailboxes. TXCR7 R/W TXCR6 R/W TXCR5 R/W TXCR4 R/W TXCR3 R/W R TXCR2 R/W TXCR1 R/W Bit Bit Name Initial Value R/W TXCR15 R/W TXCR14 R/W TXCR13 R/W TXCR12 R/W TXCR11 R/W TXCR8 R/W TXCR10 R/W TXCR9 R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description TXCR7 TXCR6 TXCR5 TXCR4 TXCR3 TXCR2 TXCR1 TXCR15 TXCR14 TXCR13 TXCR12 TXCR11 TXCR10 TXCR9 TXCR8 R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W These bits cancel the transmit wait message in the corresponding mailboxes 1 to 15. When TXCRn (n = 1 to 15) is set to 1, the transmit wait message in mailbox n is canceled. [Clearing condition]

• Completion of TXPR clearing when transmit message is canceled normally Bit 8 is reserved. This is a read-only bit and cannot be modified.

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 461 of 804 REJ09B0104-0300

13.3.7 Transmit Acknowledge Register (TXACK)

TXACK indicates the normal transmission of transmit messages in mailboxes. TXACK7 R/(W)* TXACK6 R/(W)* TXACK5 R/(W)* TXACK4 R/(W)* TXACK3 R/(W)* R TXACK2 R/(W)* TXACK1 R/(W)* Bit Bit Name Initial Value R/W TXACK15 R/(W)* TXACK14 R/(W)* TXACK13 R/(W)* TXACK12 R/(W)* TXACK11 R/(W)* TXACK8 R/(W)* TXACK10 R/(W)* TXACK9 R/(W)* Bit Bit Name Initial Value R/W Note: * Only 1 can be written to these bits, to clear the flags. Bit Bit Name Initial Value R/W Description TXACK7 TXACK6 TXACK5 TXACK4 TXACK3 TXACK2 TXACK1 TXACK15 TXACK14 TXACK13 TXACK12 TXACK11 TXACK10 TXACK9 TXACK8 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* These bits are status flags that indicate error-free transmission of the transmit message in the corresponding mailboxes 1 to 15. When the message in mailbox n (n = 1 to 15) has been transmitted error-free, TXACKn is set to 1. [Setting condition] Completion of message transmission for corresponding mailbox [Clearing condition] Writing 1 Bit 8 is reserved. This is a read-only bit and cannot be modified. Note: * Only 1 can be written to clear the flag.

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 462 of 804 REJ09B0104-0300

13.3.8 Abort Acknowledge Register (ABACK)

ABACK indicates the normal cancellation of transmit messages in mailboxes. ABACK7 R/(W)* ABACK6 R/(W)* ABACK5 R/(W)* ABACK4 R/(W)* ABACK3 R/(W)* R ABACK2 R/(W)* ABACK1 R/(W)* Bit Bit Name Initial Value R/W ABACK15 R/(W)* ABACK14 R/(W)* ABACK13 R/(W)* ABACK12 R/(W)* ABACK11 R/(W)* ABACK8 R/(W)* ABACK10 R/(W)* ABACK9 R/(W)* Bit Bit Name Initial Value R/W Note: * Only 1 can be written to these bits, to clear the flags. Bit Bit Name Initial Value R/W Description ABACK7 ABACK6 ABACK5 ABACK4 ABACK3 ABACK2 ABACK1 ABACK15 ABACK14 ABACK13 ABACK12 ABACK11 ABACK10 ABACK9 ABACK8 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* These bits are status flags that indicate error-free cancellation (abortion) of the transmit message in the corresponding mailboxes 1 to 15. When the message in mailbox n (n = 1 to 15) has been canceled error-free, ABACKn is set to 1. [Setting condition] Completion of transmit message cancellation for corresponding mailbox [Clearing condition] Writing 1 Bit 8 is reserved. This is a read-only bit and cannot be modified. Note: * Only 1 can be written to clear the flag.

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 463 of 804 REJ09B0104-0300

13.3.9 Receive Complete Register (RXPR)

RXPR indicates the normal reception of messages (data frame or remote frame) in mailboxes. For reception of a remote frame, when a bit in this register is set to 1, the corresponding remote request register (RFPR) bit is also set to 1 simultaneously. RXPR7 R/(W)* RXPR6 R/(W)* RXPR5 R/(W)* RXPR4 R/(W)* RXPR3 R/(W)* RXPR0 R/(W)* RXPR2 R/(W)* RXPR1 R/(W)* Bit Bit Name Initial Value R/W RXPR15 R/(W)* RXPR14 R/(W)* RXPR13 R/(W)* RXPR12 R/(W)* RXPR11 R/(W)* RXPR8 R/(W)* RXPR10 R/(W)* RXPR9 R/(W)* Bit Bit Name Initial Value R/W Note: * Only 1 can be written to these bits, to clear the flags. Bit Bit Name Initial Value R/W Description RXPR7 RXPR6 RXPR5 RXPR4 RXPR3 RXPR2 RXPR1 RXPR0 RXPR15 RXPR14 RXPR13 RXPR12 RXPR11 RXPR10 RXPR9 RXPR8 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* When the message in mailbox n (n = 1 to 15) has been received error-free, RXPRn is set to 1. [Setting condition] Completion of message (data frame or remote frame) reception in corresponding mailbox [Clearing condition] Writing 1 Note: * Only 1 can be written to clear the flag.

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 464 of 804 REJ09B0104-0300

13.3.10 Remote Request Register (RFPR)

RFPR indicates the normal reception of remote frames in mailboxes. When a bit in this register is set to 1, the corresponding receive complete register (RXPR) bit is also set to 1 simultaneously. RFPR7 R/(W)* RFPR6 R/(W)* RFPR5 R/(W)* RFPR4 R/(W)* RFPR3 R/(W)* RFPR0 R/(W)* RFPR2 R/(W)* RFPR1 R/(W)* Bit Bit Name Initial Value R/W RFPR15 R/(W)* RFPR14 R/(W)* RFPR13 R/(W)* RFPR12 R/(W)* RFPR11 R/(W)* RFPR8 R/(W)* RFPR10 R/(W)* RFPR9 R/(W)* Bit Bit Name Initial Value R/W Note: * Only 1 can be written to these bits, to clear the flags. Bit Bit Name Initial Value R/W Description RFPR7 RFPR6 RFPR5 RFPR4 RFPR3 RFPR2 RFPR1 RFPR0 RFPR15 RFPR14 RFPR13 RFPR12 RFPR11 RFPR10 RFPR9 RFPR8 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* When mailbox n (n = 0 to 15) has received the remote frame error-free, RFPRn (n = 1 to 15) is set to 1. [Setting condition] Completion of remote frame reception in corresponding mailbox [Clearing condition] Writing 1 Note: * Only 1 can be written to clear the flag.

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 465 of 804 REJ09B0104-0300

13.3.11 Interrupt Register (IRR)

IRR is an interrupt status flag register. IRR7 R/(W)* IRR6 R/(W)* IRR5 R/(W)* IRR4 R/(W)* IRR3 R/(W)* IRR0 R/(W)* IRR2 R IRR1 R Bit Bit Name Initial Value R/W IRR12 R/(W)* IRR8 R/(W)* IRR9 R Bit Bit Name Initial Value R/W Note: * Only 1 can be written to these bits, to clear the flags. Bit Bit Name Initial Value R/W Description

15 IRR7 0 R/(W) * Overload Frame Interrupt Flag

Status flag indicating that the HCAN transmits the overload frame. [Setting condition] When an overload frame is transmitted in error active/passive state [Clearing condition] Writing 1 (When the CPU is used to clear this flag by writing 1 while the corresponding interrupt is enabled, be sure to read the flag after writing 1 to it.)

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 466 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description

14 IRR6 0 R/(W) * Bus Off Interrupt Flag

Status flag indicating the bus off state caused by the transmit error counter. [Setting condition] When TEC ≥ 256 [Clearing condition] Writing 1 (When the CPU is used to clear this flag by writing 1 while the corresponding interrupt is enabled, be sure to read the flag after writing 1 to it.)

13 IRR5 0 R/(W) * Error Passive Interrupt Flag

Status flag indicating the error passive state caused by the transmit/receive error counter. [Setting condition] When TEC ≥ 128 or REC ≥ 128 [Clearing condition] Writing 1 (When the CPU is used to clear this flag by writing 1 while the corresponding interrupt is enabled, be sure to read the flag after writing 1 to it.)

12 IRR4 0 R/(W) * Receive Overload Warning Interrupt Flag

Status flag indicating the error warning state caused by the receive error counter. [Setting condition] When REC ≥ 96 [Clearing condition]

• Writing 1 (When the CPU is used to clear this flag by writing 1 while the corresponding interrupt is enabled, be sure to read the flag after writing 1 to it.)

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 467 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description

11 IRR3 0 R/(W) * Transmit Overload Warning Interrupt Flag

Status flag indicating the error warning state caused by the transmit error counter. [Setting condition]

• When TEC ≥ 96 [Clearing condition]
• Writing 1 (When the CPU is used to clear this flag by writing 1 while the corresponding interrupt is enabled, be sure to read the flag after writing 1 to it.)

10 IRR2 0 R Remote Frame Request Interrupt Flag When

MBIMR = 0 Status flag indicating that a remote frame has been received in a mailbox (buffer). [Setting condition]

• When remote frame reception is completed, when corresponding MBIMR = 0 [Clearing condition]
• Clearing of all bits in RFPR (remote request register)

9 IRR1 0 R Receive Message Interrupt Flag When

MBIMR = 0 Status flag indicating that a mailbox (buffer) receive message has been received normally. [Setting condition]

• When data frame or remote frame reception is completed, when corresponding MBIMR = 0 [Clearing condition]
• Clearing of all bits in RXPR (receive complete register)

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 468 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description

8 IRR0 1 R/(W) * Reset Interrupt Flag

Status flag indicating that the HCAN module has been reset. This bit cannot be masked by the interrupt mask register (IMR). If this bit is not cleared to 0 after entering power-on reset or returning from software standby mode, interrupt processing will start immediately when the interrupt controller enables interrupts. [Setting condition] When the reset operation has finished after entering power-on reset or software standby mode [Clearing condition] Writing 1 (When the CPU is used to clear this flag by writing 1 while the corresponding interrupt is enabled, be sure to read the flag after writing 1 to it.) 7 to 5  All 0  Reserved These bits are always read as 0. The write value should always be 0.

4 IRR12 0 R/(W) * Bus Operation Interrupt Flag

Status flag indicating detection of a dominant bit due to bus operation when the HCAN module is in HCAN sleep mode. [Setting condition] Bus operation (dominant bit) detection in HCAN sleep mode [Clearing condition] Writing 1 (When the CPU is used to clear this flag by writing 1 while the corresponding interrupt is enabled, be sure to read the flag after writing 1 to it.)

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 469 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description 3, 2  All 0  Reserved These bits are always read as 0. The write value should always be 0.

1 IRR9 0 R Unread Interrupt Flag

Status flag indicating that a receive message has been overwritten before being read. [Setting condition] When UMSR (unread message status register) is set [Clearing condition] Clearing of all bits in UMSR (unread message status register)

0 IRR8 0 R/(W) * Mailbox Empty Interrupt Flag

Status flag indicating that the next transmit message can be stored in the mailbox. [Setting condition]

• When TXPR (transmit wait register) is cleared by completion of transmission or completion of transmission abort [Clearing condition]
• Writing 1 (When the CPU is used to clear this flag by writing 1 while the corresponding interrupt is enabled, be sure to read the flag after writing 1 to it.) Note: * Only 1 can be written to clear the flag.

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 470 of 804 REJ09B0104-0300

13.3.12 Mailbox Interrupt Mask Register (MBIMR)

MBIMR enables or disables interrupt requests by individual mailboxes. MBIMR7 R/W MBIMR6 R/W MBIMR5 R/W MBIMR4 R/W MBIMR3 R/W MBIMR0 R/W MBIMR2 R/W MBIMR1 R/W Bit Bit Name Initial Value R/W MBIMR15 R/W MBIMR14 R/W MBIMR13 R/W MBIMR12 R/W MBIMR11 R/W MBIMR8 R/W MBIMR10 R/W MBIMR9 R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description MBIMR7 MBIMR6 MBIMR5 MBIMR4 MBIMR3 MBIMR2 MBIMR1 MBIMR0 MBIMR15 MBIMR14 MBIMR13 MBIMR12 MBIMR11 MBIMR10 MBIMR9 MBIMR8 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Mailbox Interrupt Mask (MBIMRx) When MBIMRn (n = 1 to 15) is cleared to 0, the interrupt request in mailbox n is enabled. When set to 1, the interrupt request is masked. The interrupt source in a transmit mailbox is TXPR clearing caused by transmission end or transmission cancellation. The interrupt source in a receive mailbox is RXPR setting on reception end.

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 471 of 804 REJ09B0104-0300

13.3.13 Interrupt Mask Register (IMR)

IMR enables or disables interrupt requests by IRR interrupt flags. The reset interrupt flag cannot be masked. IMR7 R/W IMR6 R/W IMR5 R/W IMR4 R/W IMR3 R/W R IMR2 R/W IMR1 R/W Bit Bit Name Initial Value R/W R R R IMR12 R/W R IMR8 R/W R IMR9 R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description

15 IMR7 1 R/W Overload Frame Interrupt Mask

When this bit is cleared to 0, an interrupt request by IRR7 (OVR0) is enabled. When set to 1, it is masked.

14 IMR6 1 R/W Bus Off Interrupt Mask

When this bit is cleared to 0, an interrupt request by IRR6 (ERS0) is enabled. When set to 1, it is masked.

13 IMR5 1 R/W Error Passive Interrupt Mask

When this bit is cleared to 0, an interrupt request by IRR5 (ERS0) is enabled. When set to 1, it is masked.

12 IMR4 1 R/W Receive Overload Warning Interrupt Mask

When this bit is cleared to 0, an interrupt request by IRR4 (OVR0) is enabled. When set to 1, it is masked.

11 IMR3 1 R/W Transmit Overload Warning Interrupt Mask

When this bit is cleared to 0, an interrupt request by IRR3 (OVR0) is enabled. When set to 1, it is masked.

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 472 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description

10 IMR2 1 R/W Remote Frame Request Interrupt Mask

When this bit is cleared to 0, an interrupt request by IRR2 (OVR0) is enabled. When set to 1, it is masked.

9 IMR1 1 R/W Receive Message Interrupt Mask

When this bit is cleared to 0, an interrupt request by IRR1 (RM1) is enabled. When set to 1, it is masked. 8  0 R Reserved This is a read-only bit and cannot be modified. 7 to 5  All 1 R Reserved These are read-only bits and cannot be modified.

4 IMR12 1 R/W Bus Operation Interrupt Mask

When this bit is cleared to 0, an interrupt request by IRR12 (OVR0) is enabled. When set to 1, it is masked. 3, 2  All 1 R Reserved These are read-only bits and cannot be modified.

1 IMR9 1 R/W Unread Interrupt Mask

When this bit is cleared to 0, an interrupt request by IRR9 (OVR0) is enabled. When set to 1, it is masked.

0 IMR8 1 R/W Mailbox Empty Interrupt Mask

When this bit is cleared to 0, an interrupt request by IRR8 (SLE0) is enabled. When set to 1, it is masked.

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 473 of 804 REJ09B0104-0300

13.3.14 Receive Error Counter (REC)

REC functions as a counter indicating the number of receive message errors on the CAN bus. The count value is stipulated in the CAN protocol. R R R R R R R R Bit Bit Name Initial Value R/W

13.3.15 Transmit Error Counter (TEC)

TEC functions as a counter indicating the number of transmit message errors on the CAN bus. The count value is stipulated in the CAN protocol. R R R R R R R R Bit Bit Name Initial Value R/W

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 474 of 804 REJ09B0104-0300

13.3.16 Unread Message Status Register (UMSR)

UMSR indicates that a received message which has not been read is overwritten by a new receive message. In this case, the message which has not been read is lost. UMSR7 R/(W)* UMSR6 R/(W)* UMSR5 R/(W)* UMSR4 R/(W)* UMSR3 R/(W)* UMSR0 R/(W)* UMSR2 R/(W)* UMSR1 R/(W)* Bit Bit Name Initial Value R/W UMSR15 R/(W)* UMSR14 R/(W)* UMSR13 R/(W)* UMSR12 R/(W)* UMSR11 R/(W)* UMSR8 R/(W)* UMSR10 R/(W)* UMSR9 R/(W)* Bit Bit Name Initial Value R/W Note: * Only 1 can be written to these bits, to clear the flags. Bit Bit Name Initial Value R/W Description UMSR7 UMSR6 UMSR5 UMSR4 UMSR3 UMSR2 UMSR1 UMSR0 UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 UMSR9 UMSR8 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* The received message has been overwritten by a new message before being read. [Setting condition]

• When a new message is received before RXPR is cleared [Clearing conditions]
• Writing 1 Note: * Only 1 can be written to clear the flag.

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 475 of 804 REJ09B0104-0300

13.3.17 Local Acceptance Filter Masks (LAFML, LAFMH)

LAFML and LAFMH mask the individual identifier bits of the message to be stored in mailbox 0. For details, refer to section 13.4.4, Message Reception. The relationship between the identifier bits and mask bits are shown in the following.

• LAFML LAFML7 R/W LAFML6 R/W LAFML5 R/W LAFML4 R/W LAFML3 R/W LAFML0 R/W LAFML2 R/W LAFML1 R/W Bit Bit Name Initial Value R/W LAFML15 R/W LAFML14 R/W LAFML13 R/W LAFML12 R/W LAFML11 R/W LAFML8 R/W LAFML10 R/W LAFML9 R/W Bit Bit Name Initial Value R/W
• LAFMH LAFMH7 R/W LAFMH6 R/W LAFMH5 R/W R R LAFMH0 R/W R LAFMH1 R/W Bit Bit Name Initial Value R/W LAFMH15 R/W LAFMH14 R/W LAFMH13 R/W LAFMH12 R/W LAFMH11 R/W LAFMH8 R/W LAFMH10 R/W LAFMH9 R/W Bit Bit Name Initial Value R/W

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• LAFML Bit Bit Name Initial Value R/W Description LAFML7 LAFML6 LAFML5 LAFML4 LAFML3 LAFML2 LAFML1 LAFML0 LAFML15 LAFML14 LAFML13 LAFML12 LAFML11 LAFML10 LAFML9 LAFML8 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W When this bit is set to 1, ID-7 of the receive message identifier is not compared. When this bit is set to 1, ID-6 of the receive message identifier is not compared. When this bit is set to 1, ID-5 of the receive message identifier is not compared. When this bit is set to 1, ID-4 of the receive message identifier is not compared. When this bit is set to 1, ID-3 of the receive message identifier is not compared. When this bit is set to 1, ID-2 of the receive message identifier is not compared. When this bit is set to 1, ID-1 of the receive message identifier is not compared. When this bit is set to 1, ID-0 of the receive message identifier is not compared. When this bit is set to 1, ID-15 of the receive message identifier is not compared. When this bit is set to 1, ID-14 of the receive message identifier is not compared. When this bit is set to 1, ID-13 of the receive message identifier is not compared. When this bit is set to 1, ID-12 of the receive message identifier is not compared. When this bit is set to 1, ID-11 of the receive message identifier is not compared. When this bit is set to 1, ID-10 of the receive message identifier is not compared. When this bit is set to 1, ID-9 of the receive message identifier is not compared. When this bit is set to 1, ID-8 of the receive message identifier is not compared.

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 477 of 804 REJ09B0104-0300

• LAFMH Bit Bit Name Initial Value R/W Description LAFMH7 LAFMH6 LAFMH5 R/W R/W R/W When this bit is set to 1, ID-20 of the receive message identifier is not compared. When this bit is set to 1, ID-19 of the receive message identifier is not compared. When this bit is set to 1, ID-18 of the receive message identifier is not compared. 12 to 10  All 0 R Reserved These are read-only bits and cannot be modified. LAFMH1 LAFMH0 LAFMH15 LAFMH14 LAFMH13 LAFMH12 LAFMH11 LAFMH10 LAFMH9 LAFMH8 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W When this bit is set to 1, ID-17 of the receive message identifier is not compared. When this bit is set to 1, ID-16 of the receive message identifier is not compared. When this bit is set to 1, ID-28 of the receive message identifier is not compared. When this bit is set to 1, ID-27 of the receive message identifier is not compared. When this bit is set to 1, ID-26 of the receive message identifier is not compared. When this bit is set to 1, ID-25 of the receive message identifier is not compared. When this bit is set to 1, ID-24 of the receive message identifier is not compared. When this bit is set to 1, ID-23 of the receive message identifier is not compared. When this bit is set to 1, ID-22 of the receive message identifier is not compared. When this bit is set to 1, ID-21 of the receive message identifier is not compared.

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 478 of 804 REJ09B0104-0300

13.3.18 Message Control (MC0 to MC15)

The message control register sets consist of eight 8-bit registers for one mailbox. The HCAN has 16 sets of these registers. Because message control registers are in RAM, their initial values after power-on are undefined. Be sure to initialize them by writing 0 or 1. Figure 13.2 shows the register names for each mailbox. MC0[1] MC1[1] MC2[1] MC3[1] MC15[1] MC0[2] MC1[2] MC2[2] MC3[2] MC15[2] MC0[3] MC1[3] MC2[3] MC3[3] MC15[3] MC0[4] MC1[4] MC2[4] MC3[4] MC15[4] MC0[5] MC1[5] MC2[5] MC3[5] MC15[5] MC0[6] MC1[6] MC2[6] MC3[6] MC15[6] MC0[7] MC1[7] MC2[7] MC3[7] MC15[7] MC0[8] MC1[8] MC2[8] MC3[8] MC15[8] Mail box 0 Mail box 1 Mail box 2 Mail box 3 Mail box 15 Figure 13.2 Message Control Register Configuration The setting of message control registers are shown below. Figures 13.3 and 13.4 show the correspondence between the identifiers and register bit names. SOF ID-28 ID-27 ID-18 RTR IDE R0 identifier Figure 13.3 Standard Format SOF ID-28 ID-27 ID-18 SRR IDE ID-17 ID-16 ID-0 RTR R1 Standard identifier Extended identifier Figure 13.4 Extended Format

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 479 of 804 REJ09B0104-0300 [Legend] x: Mailbox number (0 to 15) Undefined R/W Undefined R/W Undefined R/W Undefined R/W DLC3 Undefined R/W DLC0 Undefined R/W DLC2 Undefined R/W DLC1 Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W ID-20 Undefined R/W ID-19 Undefined R/W ID-18 Undefined R/W RTR Undefined R/W IDE Undefined R/W ID-16 Undefined R/W Undefined R/W ID-17 Undefined R/W ID-28 Undefined R/W ID-27 Undefined R/W ID-26 Undefined R/W ID-25 Undefined R/W ID-24 Undefined R/W ID-21 Undefined R/W ID-23 Undefined R/W ID-22 Undefined R/W ID-7 Undefined R/W ID-6 Undefined R/W ID-5 Undefined R/W ID-4 Undefined R/W ID-3 Undefined R/W ID-0 Undefined R/W ID-2 Undefined R/W ID-1 Undefined R/W ID-15 Undefined R/W ID-14 Undefined R/W ID-13 Undefined R/W ID-12 Undefined R/W ID-11 Undefined R/W ID-8 Undefined R/W ID-10 Undefined R/W ID-9 Undefined R/W MCx[1] Bit Bit Name Initial Value R/W MCx[2] Bit Bit Name Initial Value R/W MCx[3] Bit Bit Name Initial Value R/W MCx[4] Bit Bit Name Initial Value R/W MCx[5] Bit Bit Name Initial Value R/W MCx[6] Bit Bit Name Initial Value R/W MCx[7] Bit Bit Name Initial Value R/W MCx[8] Bit Bit Name Initial Value R/W

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 480 of 804 REJ09B0104-0300 Register Name Bit Bit Name R/W Description 7 to 4  R/W The initial value of t hese bits is undefined. They must be initialized by writing 0 or 1. MCx[1] 3 to 0 DLC3 to DLC0 R/W Data Length Code Set the data length of a data frame or the data length requested in a remote frame within the range of 0 to 8 bits. 0000: 0 byte 0001: 1 byte 0010: 2 bytes 0011: 3 bytes 0100: 4 bytes 0101: 5 bytes 0110: 6 bytes 0111: 7 bytes 1000: 8 bytes 1***: 8 bytes MCx[2] MCx[3] MCx[4] 7 to 0 7 to 0 7 to 0 R/W R/W R/W The initial value of these bits is undefined; they must be initialized by writing 0 or 1. 7 to 5 ID-20 to ID-18 R/W Sets ID -20 to ID-18 in the identifier.

4 RTR R/W Remote Transmission Request

Used to distinguish between data frames and remote frames. 0: Data frame 1: Remote frame

3 IDE R/W Identifier Extension

Used to distinguish between the standard format and extended format of data frames and remote frames. 0: Standard format 1: Extended format 2  R/W The initial value of th is bit is undefined. It must be initialized by writing 0 or 1. MCx[5] 1 to 0 ID-17 to ID-16 R/W Sets ID-17 and ID-16 in the identifier.

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 481 of 804 REJ09B0104-0300 Register Name Bit Bit Name R/W Description MCx[6] 7 to 0 ID-28 to ID-21 R/W Sets ID-28 to ID-21 in the identifier. MCx[7] 7 to 0 ID-7 to ID-0 R/W Sets ID-7 to ID-0 in the identifier. MCx[8] 7 to 0 ID-15 to ID-8 R/W Sets ID-15 to ID-8 in the identifier. [Legend] x: Mailbox number (0 to 15)

13.3.19 Message Data (MD0 to MD15)

The message data register sets consist of eight 8-bit registers for one mailbox. The HCAN has 16 sets of these registers. Because message data registers are in RAM, their initial values after power- on are undefined. Be sure to initialize them by writing 0 or 1. Figure 13.5 shows the register names for each mailbox. MD0[1] MD1[1] MD2[1] MD3[1] MD15[1] MD0[2] MD1[2] MD2[2] MD3[2] MD15[2] MD0[3] MD1[3] MD2[3] MD3[3] MD15[3] MD0[4] MD1[4] MD2[4] MD3[4] MD15[4] MD0[5] MD1[5] MD2[5] MD3[5] MD15[5] MD0[6] MD1[6] MD2[6] MD3[6] MD15[6] MD0[7] MD1[7] MD2[7] MD3[7] MD15[7] MD0[8] MD1[8] MD2[8] MD3[8] MD15[8] Mail box 0 Mail box 1 Mail box 2 Mail box 3 Mail box 15 Figure 13.5 Message Data Configuration

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 482 of 804 REJ09B0104-0300 [Legend] x: Mailbox number (0 to 15) Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W MDx[1] Bit Bit Name Initial Value R/W MDx[2] Bit Bit Name Initial Value R/W MDx[3] Bit Bit Name Initial Value R/W MDx[4] Bit Bit Name Initial Value R/W MDx[5] Bit Bit Name Initial Value R/W MDx[6] Bit Bit Name Initial Value R/W MDx[7] Bit Bit Name Initial Value R/W MDx[8] Bit Bit Name Initial Value R/W

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 483 of 804 REJ09B0104-0300

13.3.20 HCAN Monito r Register (HCANMON)

HCANMON enables or disables an HCAN receive interrupt, controls transmission stop of the HTxD pin, and reflects the states of the HCAN pins. Undefined TxSTP R/W HCANE R/W Undefined Undefined RxD Undefined R Undefined TxD Undefined R Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description 7  Undefined  Reserved This bit is always read as undefined value and cannot be modified.

6 TxSTP 0 R/W HTxD Transmission Stop

Controls transmission stop of the HTxD pin. 0: Enables transmission from the HTxD pin 1: Fixes an output level of the HTxD pin at 1 and transmission is stopped

5 HCANE 0 R/W HCAN Output Pin Enable

0: P64 is used as an I/O port 1: P64 is used as the HTxD pin. 4 to 2  Undefined  Reserved These bits are always read as undefined values and cannot be modified.

1 TxD Undefined R Transmission pin

The state of the HTxD pin is read. This bit cannot be modified.

0 RxD Undefined R Reception pin

The state of the HRxD pin is read. This bit cannot be modified.

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 484 of 804 REJ09B0104-0300

13.4 Operation

13.4.1 Hardware and Software Resets

The HCAN can be reset by a hardware reset or software reset.

• Hardware Reset At power-on reset or a transition to software standby mode, the HCAN is initialized by automatically setting the MCR reset request bit (MCR0) in MCR and the reset state bit (GSR3) in GSR. At the same time, all internal registers, except for message control and message data registers, are initialized by a hardware reset.
• Software Reset The HCAN can be reset by setting the MCR reset request bit (MCR0) in MCR via software. In a software reset, the error counters (TEC and REC) are initialized, however other registers are not. If bit MCR0 is set while the CAN controller is performing a communication operation (transmission or reception), the initialization state is not entered until message transfer has been completed. The reset status bit (GSR3) in GSR is set on completion of initialization.

13.4.2 Initialization after Hardware Reset

After a hardware reset, the following initialization processing should be carried out: 1. Clearing of bit IRR0 in the interrupt register (IRR) 2. Bit rate setting 3. Mailbox transmit/receive settings 4. Mailbox (RAM) initialization 5. Message transmission method setting These initial settings must be made while the HCAN is in bit configuration mode. Configuration mode is a state in which bit GSR3 in GSR is set to 1 by a reset. Configuration mode is exited by clearing bit MCR0 in MCR to 0; when bit MCR0 is cleared to 0, the HCAN automatically clears bit GSR3 in GSR. There is a delay between clearing bit MCR0 and clearing bit GSR3 because the HCAN needs time to be internally reset. After the HCAN exits configuration mode, the power-up sequence begins, and communication with the CAN bus is possible as soon as 11 consecutive recessive bits have been detected.

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 485 of 804 REJ09B0104-0300 (1) IRR0 Clearing The reset interrupt flag (IRR0) is always set after a power-on reset or recovery from software standby mode. Since an HCAN interrupt is initiated immediately when interrupts are enabled, IRR0 should be cleared. No No Hardware reset MCR0 = 1 (automatic) IRR0 = 1 (automatic) GSR3 = 1 (automatic) MCR0 = 0 GSR3 = 0? Yes GSR3 = 0 & 11 recessive bits received? Can bus communication enabled Yes Bit configuration mode Period in which BCR, MBCR, etc., are initialized : Settings by user : Processing by hardware Initialization of HCAN module Clear IRR0 BCR setting MBCR setting Mailbox initialization Message transmission method initialization IMR setting (interrupt mask setting) MBIMR setting (interrupt mask setting) MC[x] setting (receive identifier setting) LAFM setting (receive identifier mask setting) Figure 13.6 Hardware Reset Flowchart

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 486 of 804 REJ09B0104-0300 MCR0 = 1 GSR3 = 1 (automatic) Initialization of REC and TEC only MCR0 = 0 GSR3 = 0? CAN bus communication enabled Bus idle? Yes Correction Yes Correction : Settings by user : Processing by hardwareNo No No No No BCR setting MBCR setting Mailbox (RAM) initialization Message transmission method initialization OK? IMR setting MBIMR setting MC[x] setting LAFM setting OK? GSR3 = 0 & 11 recessive bits received? Yes Yes Yes GSR3 = 1? No Yes Figure 13.7 Software Reset Flowchart

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 487 of 804 REJ09B0104-0300 (2) Bit Rate and Bit Timing Settings The bit rate and bit timing settings are made in the bit configuration register (BCR). Settings should be made such that all CAN controllers connected to the CAN bus have the same baud rate and bit width. The 1-bit time consists of the total of the settable time quanta (tq). SYNC_SEG PRSEG PHSEG1 PHSEG2 Time segment 2 (TSEG2)Time segment 1 (TSEG1) 1-bit time (8–25 time quanta) 4 to 16 time quanta 2 to 8 time quanta1 time quanta Figure 13.8 Detailed Description of One Bit SYNC_SEG is a segment for establishing the synchronization of nodes on the CAN bus. Normal bit edge transitions occur in this segment. PRSEG is a segment for compensating for the physical delay between networks. PHSEG1 is a buffer segment for correcting phase drift (positive). This segment is extended when synchronization (resynchronization) is established. PHSEG2 is a buffer segment for correcting phase drift (negative). This segment is shortened when synchronization (resynchronization) is established. Limits on the settable value (TSEG1, TSEG2, BRP, BSP, and SJW) are shown in table 13.2. Table 13.2 Limits for the Settable Value Name Abbreviation Min. Value Max. Value Time segment 1 TSEG1 B'0011 * B'1111 Time segment 2 TSEG2 B'001 * B'111 Baud rate prescaler BRP B'000000 B'111111 Bit sample point BSP B'0 B'1 Re-synchronization jump width SJW * B'00 B'11 Notes: 1. SJW is stipulated in the CAN specifications: 3 ≥ SJW ≥ 0 2. The minimum value of TSEG2 is stipulated in the CAN specifications: TSEG2 ≥ SJW 3. The minimum value of TSEG1 is stipulated in the CAN specifications: TSEG1 > TSEG2

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 488 of 804 REJ09B0104-0300 Time quanta (tq) is an integer multiple of the number of system clocks, and is determined by the baud rate prescaler (BRP) as follows. fCLK is the frequency of the peripheral module clock (Pφ). tq = 2 × (BPR setting + 1)/fCLK The following formula is used to calculate the 1-bit time and bit rate. 1-bit time = tq × (3 + TSEG1 + TSEG2) Bit rate = 1/Bit time = f CLK /{2 × (BPR setting + 1) × (3 + TSEG1 + TSEG2)} Note: fCLK = Pφ (peripheral module clock) A BCR value is used for BRP, TSEG1, and TSEG2. Example: With a peripheral module clock (Pφ) of 20 MHz, a BRP setting of B'000000, a TSEG1 setting of B'0100, and a TSEG2 setting of B'011: Table 13.3 Setting Range for TSEG1 and TSEG2 in BCR TSEG2 (BCR14 to BCR12) TSEG1 (BCR11 to BCR8) 001 010 011 100 101 110 111

0011 No Yes No No No No No

0100 Yes * Yes Yes No No No No

0101 Yes * Yes Yes Yes No No No

0110 Yes * Yes Yes Yes Yes No No

0111 Yes * Yes Yes Yes Yes Yes No

1000 Yes * Yes Yes Yes Yes Yes Yes

1001 Yes * Yes Yes Yes Yes Yes Yes

1010 Yes * Yes Yes Yes Yes Yes Yes

1011 Yes * Yes Yes Yes Yes Yes Yes

1100 Yes * Yes Yes Yes Yes Yes Yes

1101 Yes * Yes Yes Yes Yes Yes Yes

1110 Yes * Yes Yes Yes Yes Yes Yes

1111 Yes * Yes Yes Yes Yes Yes Yes

Notes: The time quantum values for T SEG1 and TSEG2 are determined by TSEG value + 1. * Settable when BRP is not B'000000.

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 489 of 804 REJ09B0104-0300 (3) Mailbox Transmit/Receive Settings The HCAN has 16 mailboxes. Mailbox 0 is receive-only, while mailboxes 1 to 15 can be set for transmission or reception. The initial status of mailboxes 1 to 15 is for transmission. Mailbox transmit/receive settings are not initialized by a software reset. Clearing a bit to 0 in the mailbox configuration register (MBCR) designates the corresponding mailbox for transmission use, whereas a setting of 1 in MBCR designates the corresponding mailbox for reception use. When setting mailboxes for reception, in order to improve message reception efficiency, high-priority messages should be set in low-to-high mailbox order. (4) Mailbox (Message Control/Data) Initial Settings Message control/data are held in RAM, and so their initial values are undefined after power is supplied. Initial values must therefore be set in all the mailboxes (by writing 0s or 1s). (5) Setting the Message Transmission Method The following two kinds of message transmission methods are available.

• Transmission order determined by message identifier priority
• Transmission order determined by mailbox number priority Either of the message transmission methods can be selected with the message transmission method bit (MCR2) in the master control register (MCR): When messages are set to be transmitted according to the message identifier priority, if several messages are designated as waiting for transmission (TXPR = 1), the message with the highest priority in the message identifier is stored in the transmit buffer. CAN bus arbitration is then carried out for the message stored in the transmit buffer, and the message is transmitted when the transmission right is acquired. When the TXPR bit is set, the highest-priority message is found and stored in the transmit buffer. When messages are set to be transmitted according to the mailbox number priority, if several messages are designated as waiting for transmission (TXPR = 1), messages are stored in the transmit buffer in low-to-high mailbox order. CAN bus arbitration is then carried out for the message stored in the transmit buffer, and the message is transmitted when the transmission right is acquired.

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13.4.3 Message Transmission

Messages are transmitted using mailboxes 1 to 15. The transmission procedure after initial settings is described below, and a transmission flowchart is shown in figure 13.9. Initialization (after hardware reset only) Clear IRR0 BCR setting MBCR setting Mailbox initialization Message transmission method setting Yes No Yes Yes : Settings by user : Processing by hardware No No Interrupt settings Transmit data setting Arbitration field setting Control field setting Data field setting Message transmission GSR2 = 0 (during transmission only) TXACK = 1 IRR8 = 1 Clear TXACK Clear IRR8 Message transmission wait TXPR setting Bus idle? Transmission completed? IMR8 = 1? Interrupt to CPU End of transmission Figure 13.9 Transmission Flowchart

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 491 of 804 REJ09B0104-0300 (1) CPU interrupt source settings The CPU interrupt source is set by the interrupt mask register (IMR) and mailbox interrupt mask register (MBIMR). Transmission acknowledge and transmission abort acknowledge interrupts can be generated for individual mailboxes in the mailbox interrupt mask register (MBIMR). (2) Arbitration field setting The arbitration field is set by the message control registers MCx[5] to MCx[8] in a transmit mailbox. For a standard format, an 11-bit identifier (ID-28 to ID-18) and the RTR bit are set, and the IDE bit is cleared to 0. For an extended format, a 29-bit identifier (ID-28 to ID-0) and the RTR bit are set, and the IDE bit is set to 1. (3) Control field setting In the control field, the byte length of the data to be transmitted is set within the range of zero to eight bytes. The register to be set is the message control register MCx[1] in a transmit mailbox. (4) Data field setting In the data field, the data to be transmitted is set within the range zero to eight. The registers to be set are the message data registers MDx[1] to MDx[8]. The byte length of the data to be transmitted is determined by the data length code in the control field. Even if data exceeding the value set in the control field is set in the data field, up to the byte length set in the control field will actually be transmitted. (5) Message transmission If the corresponding mailbox transmit wait bit (TXPR1 to TXPR15) in the transmit wait register (TXPR) is set to 1 after message control and message data registers have been set, the message enters transmit wait state. If the message is transmitted error-free, the corresponding acknowledge bit (TXACK1 to TXACK15) in the transmit acknowledge register (TXACK) is set to 1, and the corresponding transmit wait bit (TXPR1 to TXPR15) in the transmit wait register (TXPR) is automatically cleared to 0. Also, if the corresponding bit (MBIMR1 to MBIMR15) in the mailbox interrupt mask register (MBIMR) and the mailbox empty interrupt bit (IRR8) in the interrupt mask register (IMR) are both simultaneously set to enable interrupts, interrupts may be sent to the CPU. If transmission of a transmit message is aborted in the following cases, the message is retransmitted automatically:

• CAN bus arbitration failure (failure to acquire the bus)
• Error during transmission (bit error, stuff error, CRC error, frame error, or ACK error)

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 492 of 804 REJ09B0104-0300 (6) Message transmission cancellation Transmission cancellation can be specified for a message stored in a mailbox as a transmit wait message. A transmit wait message is canceled by setting the bit for the corresponding mailbox (TXCR1 to TXCR15) to 1 in the transmit cancel register (TXCR). Clearing the transmit wait register (TXPR) does not cancel transmission. When cancellation is executed, the transmit wait register (TXPR) is automatically reset, and the corresponding bit is set to 1 in the abort acknowledge register (ABACK), and then an interrupt to the CPU can be requested. Also, if the corresponding bit (MBIMR1 to MBIMR15) in the mailbox interrupt mask register (MBIMR) and the mailbox empty interrupt bit (IRR8) in the interrupt mask register (IMR) are both simultaneously set to enable interrupts, interrupts may be sent to the CPU. However, a transmit wait message cannot be canceled at the following times:

• During internal arbitration or CAN bus arbitration
• During data frame or remote frame transmission

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13.4.4 Message Reception

The reception procedure after initial settings is described below. A reception flowchart is shown in figure 13.11. RXPR IRR1 = 1 No IMR2 = 1? Interrupt to CPU Yes No Yes Yes Yes No : Settings by user : Processing by hardware No Yes Initialization Clear IRR0 BCR setting MBCR setting Mailbox (RAM) initialization Receive data setting Arbitration field setting Local acceptance filter settings Interrupt settings Message reception (Match of identifier in mailbox?) Same RXPR = 1? IMR1 = 1? Data frame? Interrupt to CPU Clear IRR1 End of reception Clear IRR2, IRR1 Unread message No RXPR, RFPR = 1 IRR2 = 1, IRR1 = 1 Message control read Message data read Message control read Message data read Transmission of data frame corresponding to remote frame Figure 13.11 Reception Flowchart

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 495 of 804 REJ09B0104-0300 (1) CPU interrupt source settings CPU interrupt source settings are made in the interrupt mask register (IMR) and mailbox interrupt register (MBIMR). The message to be received is also specified. Data frame and remote frame receive wait interrupt requests can be generated for individual mailboxes in the MBIMR. (2) Arbitration field setting To receive a message, the message identifier must be set in advance in the message control registers (MCx[1] to MCx[8]) for the receiving mailbox. When a message is received, all the bits in the receive message identifier are compared with those in each message control register identifier, and if a complete match is found, the message is stored in the matching mailbox. Mailbox 0 has a local acceptance filter mask (LAFM) that allows Don't Care settings. The LAFM setting can be made only for mailbox 0. By setting the Don't Care for all the bits in the receive message identifier, messages of multiple identifiers can be received. Examples:

• When the identifier of mailbox 1 is 010_1010_1010 (standard format), only one kind of message identifier can be received by mailbox 1: Identifier 1: 010_1010_1010
• When the identifier of mailbox 0 is 010_1010_1010 (standard format) and the LAFM setting is 000_0000_0011 (0: Care, 1: Don't Care), a total of four kinds of message identifiers can be received by mailbox 0: Identifier 1: 010_1010_1000 Identifier 2: 010_1010_1001 Identifier 3: 010_1010_1010 Identifier 4: 010_1010_1011

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 496 of 804 REJ09B0104-0300 (3) Message reception When a message is received, a CRC check is performed automatically. If the result of the CRC check is normal, ACK is transmitted in the ACK field irrespective of whether the message can be received or not.

• Data frame reception If the received message is confirmed to be error-free by the CRC check, the identifier in the mailbox (and also LAFM in the case of mailbox 0 only) and the identifier of the receive message are compared. If a complete match is found, the message is stored in the matching mailbox. The message identifier comparison is carried out on each mailbox in turn, starting with mailbox 0 and ending with mailbox 15. If a complete match is found, the comparison ends at that point, the message is stored in the matching mailbox, and the corresponding receive complete bit (RXPR0 to RXPR15) in the receive complete register (RXPR) is set. However, if the identifier matches that of mailbox 0 LAFM, the mailbox comparison sequence does not end at that point, but continues from mailbox 1. Therefore, the message for mailbox 0 can also be received by another mailbox. Note that the same message cannot be stored in two or more mailbox of the mailboxes 1 to 15. On receiving a message, a CPU interrupt request may be generated according to the settings of the mailbox interrupt mask register (MBIMR) and interrupt mask register (IMR).
• Remote frame reception A mailbox can store two kinds of messages: data frames and remote frames. A remote frame differs from a data frame in the value of the remote transmission request bit (RTR) in the message control register and its 0-byte data field. The data length to be returned in a data frame must be stored in the data length code (DLC) in the message control. When a remote frame (RTR = recessive) is received, the corresponding bit in the remote request wait register (RFPR) is set. Interrupts can be sent to the CPU according to the settings of the corresponding bit (MBIMR0 to MBIMR15) in the mailbox interrupt mask register (MBIMR) and the remote frame request interrupt mask (IRR2) in the interrupt mask register (IMR).

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 497 of 804 REJ09B0104-0300 (4) Unread message overwrite If the receive message identifier matches the mailbox identifier, the receive message is stored in the mailbox regardless of whether the mailbox contains an unread message or not. If a message overwrite occurs, the corresponding bit (UMSR0 to UMSR15) in the unread message register (UMSR) is set. In overwriting an unread message, the unread message register (UMSR) is set when a new message is received before the corresponding bit in the receive complete register (RXPR) has been cleared. If the unread interrupt flag (IRR9) in the interrupt mask register (IMR) is set to enable interrupts at this time, an interrupt can be sent to the CPU. Figure 13.12 shows a flowchart for unread message overwriting. No : Settings by userUnread message overwrite Interrupt to CPU End IMR9 = 1? UMSR = 1 IRR9 = 1 Clear IRR9 Message control/message data read : Processing by hardware Yes Figure 13.12 Unread Message Overwrite Flowchart

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13.4.5 HCAN Sleep Mode

The HCAN is provided with an HCAN sleep mode that places the HCAN module in the sleep state in order to reduce current consumption. Figure 13.13 shows a flowchart of the HCAN sleep mode. IRR12 = 1 Yes MCR5 = 0 Yes Yes MCR5 = 0 Clear sleep mode? GSR3 = 1? Yes No No No Yes (manual) No (automatic) MCR5 = 1 Bus idle? Initialize TEC and REC Bus operation? : Settings by user : Processing by hardware No No No IMR12 = 1? Sleep mode clearing method MCR7 = 0? 11 recessive bits received? CAN bus communication possible CPU interrupt Yes GSR3 = 1? No Yes Figure 13.13 HCAN Sleep Mode Flowchart

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 499 of 804 REJ09B0104-0300 HCAN sleep mode is entered by setting the HCAN sleep mode bit (MCR5) to 1 in the master control register (MCR). If the CAN bus is operating, the transition to HCAN sleep mode is delayed until the bus becomes idle. Either of the following methods of clearing HCAN sleep mode can be selected:

• Clearing by software
• Clearing by CAN bus operation In order to re-enter CAN bus communication enabled state, eleven recessive bits must be received after HCAN sleep mode was cleared. (1) Clearing by software HCAN sleep mode is cleared by writing a 0 to MCR5 from the CPU. (2) Clearing by CAN bus operation The cancellation method is selected by bit MCR7 setting in MCR. Clearing by CAN bus operation occurs automatically when the CAN bus performs an operation and this change is detected. In this case, the first message is not stored in a mailbox; messages will be received normally from the second message onward. When a change is detected on the CAN bus in HCAN sleep mode, the bus operation interrupt flag (IRR12) is set in the interrupt register (IRR). If the bus interrupt mask (IMR12) in the interrupt mask register (IMR) is set to enable interrupts at this time, an interrupt can be sent to the CPU.

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13.4.6 HCAN Halt Mode

The HCAN halt mode is provided to enable mailbox settings to be changed without performing an HCAN hardware or software reset. Figure 13.14 shows a flowchart of the HCAN halt mode. MCR1 = 1 Yes : Settings by user : Processing by hardware NoBus idle? Set MBCR MCR1 = 0 CAN bus communication possible Figure 13.14 HCAN Halt Mode Flowchart HCAN halt mode is entered by setting the halt request bit (MCR1) to 1 in the master control register (MCR). If the CAN bus is operating, the transition to HCAN halt mode is delayed until the bus becomes idle. HCAN halt mode is cleared by clearing MCR1 to 0.

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13.5 Interrupt Sources

Table 13.4 lists the HCAN interrupt sources. These sources can be masked except the reset processing interrupt by power-on reset (IRR0). Masking is implemented using the mailbox interrupt mask register (MBIMR), interrupt mask register (IMR), and IRQ enable register (IER). For details on the interrupt vector of each interrupt source, refer to section 5, Interrupt Controller. Table 13.4 HCAN Interrupt Sources Name Description Interrupt Flag DMAC Activation ERS0/OVR0 Error passi ve interrupt (TEC ≥ 128 or REC ≥ 128) IRR5 Not possible Bus off interrupt (TEC ≥ 256) IRR6 Reset processing interrupt by power-on reset IRR0 Remote frame reception IRR2 Error warning interrupt (TEC ≥ 96) IRR3 Error warning interrupt (REC ≥ 96) IRR4 Overload frame transmission interrupt IRR7 Unread message overwrite IRR9 Detection of CAN bus operation in HCAN sleep mode IRR12 RM0 Mailbox 0 message reception IRR1 Possible RM1 Mailbox 1-15 message reception IRR1 Not possible SLE0 Message transmission/cancellation IRR8 Not possible

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13.6 DMAC Interface

The DMAC can be activated by the reception of a message in HCAN mailbox 0. When the DMAC activation is set and DMAC transfer ends, flags RXPR0 and RFPR0 are automatically cleared. An interrupt request is not sent to the CPU by a reception interrupt from the HCAN. Figure 13.15 shows a DMAC transfer flowchart. DMAC initialization Activation source, source address, destination address, transfer count, and Yes Yes : Settings by user : Processing by hardware No No Message reception in HCAN's mailbox 0 DMAC interrupt enable = 1? DMAC activation End of DMAC transfer? DMAC transfer end bit setting RXPR and RFPR clearing Interrupt to CPU End DMAC interrupt flag clearing Figure 13.15 DMAC Transfer Flowchart

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13.7 CAN Bus Interface

A bus transceiver IC is necessary to connect this LSI to a CAN bus. A Philips PCA82C250 transceiver IC is recommended. If any other product is used, confirm that it is compatible with the PCA82C250. Figure 13.16 shows a sample connection diagram. RS RxD TxD Vref Vcc CANH CANL GND HRxD NC Note: NC: No Connection HTxD This LSI CAN bus 124 Ω 124 Ω Vcc PCA82C250 Figure 13.16 High-Speed Interface Using PCA82C250

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13.8 Usage Notes

13.8.1 Module Stop Mode Setting

HCAN operation can be disabled or enabled using the module stop control register. The HCAN operation is set to be halted initially. Register access is enabled by clearing module stop mode. For details, refer to section 19, Power-Down Modes.

13.8.2 Reset

The HCAN is reset by a power-on reset and a transition to software standby mode. All the registers are initialized by a reset, however mailboxes (message control (MCx[x])/message data (MDx[x])) are not initialized. Mailboxes (message control (MCx[x])/message data (MDx[x])) are initialized after power-on and at this time, their initial values are undefined. Therefore, always initialize mailboxes after a power-on reset, a transition to software standby mode, or a transition to module stop mode. After a power-on reset, recovery from software standby mode, or clearing module stop mode, the reset interrupt flag (IRR0) is automatically set. Since this bit cannot be masked in the interrupt mask register (IMR), an HCAN interrupt will be initiated immediately after an HCAN interrupt is enabled by the interrupt controller without clearing the flag. IRR0 should therefore be cleared at initialization.

13.8.3 HCAN Sleep Mode

The bus operation interrupt flag (IRR12) in the interrupt register (IRR) is set by CAN bus operation in HCAN sleep mode. Therefore, this flag is not used by the HCAN to indicate sleep mode release. Note that the reset status bit (GSR3) in the general status register (GSR) is set even in sleep mode.

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13.8.4 Interrupts

When the mailbox interrupt mask register (MBIMR) is set, the interrupt registers (IRR8, 2, 1) are not set by reception completion, transmission completion, or transmission cancellation of the set mailboxes.

13.8.5 Error Counters

In the case of error active and error passive, REC and TEC perform count up and down normally. In the bus-off state, 11-bit recessive sequences are counted (REC + 1) using REC. When REC reaches 96 during the count, IRR4 and GSR1 are set.

13.8.6 Register Access

Byte or word access can be performed for all HCAN registers. Longword access should be avoided.

13.8.7 Register Hold in Standby Modes

All HCAN registers are initialized in hardware standby mode and software standby mode.

13.8.8 Use on Bit Manipulation Instructions

Since the HCAN status flag is cleared by writing 1, do not use the bit manipulation instructions to clear the flag. To clear the flag, use the MOV instructions and write 1 only to the bit to be cleared.

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13.8.9 HCAN TXCR Operation

1. When the transmit wait cancel register (TXCR) is used to cancel a transmit wait message in a transmit wait mailbox, the corresponding bit to TXCR and the transmit wait register (TXPR) may not be cleared even if transmission is canceled. This occurs when the following conditions are all satisfied.

• The HRxD pin is stacked to 1 because of a CAN bus error, etc.
• There is at least one mailbox waiting for transmission or being transmitted.
• The message transmission in a mailbox being transmitted is canceled by TXCR. If this occurs, transmission is canceled. However, since TXPR and TXCR states are indicated wrongly that a message is being cancelled, transmission cannot be restarted even if the stack state of the HRxD pin is canceled and the CAN bus recovers the normal state. If there are at least two transmission messages, a message which is not being transmitted is canceled and a message being transmitted retains its state. To avoid this, one of the following countermeasures must be executed.
• Transmission must not be canceled by TXCR. When transmission is normally completed after the CAN bus has recovered, TXPR is cleared and the HCAN recovers the normal state.
• To cancel transmission, the corresponding bit to TXCR must be written to 1 continuously until the bit becomes 0. TXPR and TXCR are cleared and the HCAN recovers the normal state. 2. When the bus-off state is entered while TXPR is set and the transmit wait state is entered, the internal state machine does not operate even if TXCR is set during the bus-off state. Therefore transmission cannot be canceled. The message can be canceled when one message is transmitted or a transmission error occurs after the bus-off state is recovered. To clear a message after the bus-off state is recovered, the following countermeasure must be executed.
• A transmit wait message must be cleared by resetting the HCAN during the bus-off period. To reset the HCAN, the module stop bit (MSTPC11 in MSTPCRC) must be set or cleared. In this case, the HCAN is entirely reset. Therefore the initial settings must be made again.

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13.8.10 HCAN Transmission Setting

With the following conditions satisfied, a previous message identifier (ID) may be collapsed when the next transmission is set or transmission is canceled within 50 µs after the previous transmission has been set in the bus idle state.

• When the message set at the second transmission setting has priority over the message set at the first transmission setting
• When the message canceled at the first transmission setting has priority over any messages The following settings should be performed so that a message ID is not collapsed.
• Transmission setting should be performed at a time. The next transmission setting should be set at least 50 µs after completion of transmission of all messages (en bloc transmission).
• Transmission setting should be performed according to the priority.
• Sufficient duration should be taken between transmission setting or cancellation: setting TXPR and setting TXPR or setting TXPR and setting TXCR. Table 13.5 Duration between Transmission Setting Baud Rate (bps) Setting Interval ( µs)

1 M 50

13.8.11 Canceling HCAN Reset and HCAN Sleep Mode

Before canceling an HCAN software reset or HCAN sleep mode (clearing bit MCR0 or MCR5 to 0), confirm that the reset status bit (GSR3) has been set to 1.

13.8.12 Accessing Mailbox in HCAN Sleep Mode

Do not access any Mailbox in HCAN sleep mode. When the access is attempted, the CPU may stop operating. Accessing registers does not cause the CPU to halt. Accessing a Mailbox in other than HCAN sleep mode does not cause the CPU to halt.

Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 508 of 804 REJ09B0104-0300

Section 14 Synchronous Serial Communication Unit (SSU) Rev. 3.00 Mar. 14, 2006 Page 509 of 804 REJ09B0104-0300 Section 14 Synchronous Serial Communication Unit (SSU) This LSI has three independent synchronous serial communication unit (SSU) channels. The SSU has master mode in which this LSI outputs clocks as a master device for synchronous serial communication and slave mode in which clocks are input from an external device for synchronous serial communication. Synchronous serial communication can be performed with devices having different clock polarity and clock phase. Figure 14.1 is a block diagram of the SSU.

14.1 Features

• Choice of SSU mode and clock synchronous mode
• Choice of master mode and slave mode
• Choice of standard mode and bidirectional mode
• Synchronous serial communication with devices with different clock polarity and clock phase
• Choice of 8/16/32-bit width of transmit/receive data
• Full-duplex communication capability The shift register is incorporated, enabling transmission and reception to be executed simultaneously.
• Consecutive serial communication
• Choice of LSB-first or MSB-first transfer
• Choice of a clock source Pφ/4, Pφ/8, Pφ/16, Pφ/32, Pφ/64, Pφ/128, Pφ/256, or an external clock
• Five interrupt sources transmit-end, transmit-data-register-empty, receive-data-full, overrun-error, and conflict error
• Module stop mode can be set* Note: * Module stop mode has usage notes. For details, see section 14.6.2, Notes on Clearing Module Stop Mode.

Section 14 Synchronous Serial Communication Unit (SSU) Rev. 3.00 Mar. 14, 2006 Page 511 of 804 REJ09B0104-0300

14.2 Input/Output Pins

Table 14.1 shows the SSU pin configuration. Table 14.1 Pin Configuration Channel Abbr. * I/O Function

0 SSCK0 I/O Channel 0 SSU clock input/output

SSI0 I/O Channel 0 SSU data input/output SSO0 I/O Channel 0 SSU data input/output SCS0 I/O Channel 0 SSU chip select input/output

1 SSCK1 I/O Channel 1 SSU clock input/output

SSI1 I/O Channel 1 SSU data input/output SSO1 I/O Channel 1 SSU data input/output SCS1 I/O Channel 1 SSU chip select input/output

2 SSCK2 I/O Channel 2 SSU clock input/output

SSI2 I/O Channel 2 SSU data input/output SSO2 I/O Channel 2 SSU data input/output SCS2 I/O Channel 2 SSU chip select input/output Note: * Because channel numbers are omitted in later descriptions, these are shown SSCK, SSI, SSO, and SCS.

Section 14 Synchronous Serial Communication Unit (SSU) Rev. 3.00 Mar. 14, 2006 Page 512 of 804 REJ09B0104-0300

14.3 Register Descriptions

The SSU has the following registers. (1) Channel 0

• SS control register H_0 (SSCRH_0)
• SS control register L_0 (SSCRL_0)
• SS mode register_0 (SSMR_0)
• SS enable register_0 (SSER_0)
• SS status register_0 (SSSR_0)
• SS control register 2_0 (SSCR2_0)
• SS transmit data register 0_0 (SSTDR0_0)
• SS transmit data register 1_0 (SSTDR1_0)
• SS transmit data register 2_0 (SSTDR2_0)
• SS transmit data register 3_0 (SSTDR3_0)
• SS receive data register 0_0 (SSRDR0_0)
• SS receive data register 1_0 (SSRDR1_0)
• SS receive data register 2_0 (SSRDR2_0)
• SS receive data register 3_0 (SSRDR3_0)
• SS shift register_0 (SSTRSR_0)

Section 14 Synchronous Serial Communication Unit (SSU) Rev. 3.00 Mar. 14, 2006 Page 513 of 804 REJ09B0104-0300 (2) Channel 1

• SS control register H_1 (SSCRH_1)
• SS control register L_1 (SSCRL_1)
• SS mode register_1 (SSMR_1)
• SS enable register_1 (SSER_1)
• SS status register_1 (SSSR_1)
• SS control register 2_1 (SSCR2_1)
• SS transmit data register 0_1 (SSTDR0_1)
• SS transmit data register 1_1 (SSTDR1_1)
• SS transmit data register 2_1 (SSTDR2_1)
• SS transmit data register 3_1 (SSTDR3_1)
• SS receive data register 0_1 (SSRDR0_1)
• SS receive data register 1_1 (SSRDR1_1)
• SS receive data register 2_1 (SSRDR2_1)
• SS receive data register 3_1 (SSRDR3_1)
• SS shift register_1 (SSTRSR_1) (3) Channel 2
• SS control register H_2 (SSCRH_2)
• SS control register L_2 (SSCRL_2)
• SS mode register_2 (SSMR_2)
• SS enable register_2 (SSER_2)
• SS status register_2 (SSSR_2)
• SS control register 2_2 (SSCR2_2)
• SS transmit data register 0_2 (SSTDR0_2)
• SS transmit data register 1_2 (SSTDR1_2)
• SS transmit data register 2_2 (SSTDR2_2)
• SS transmit data register 3_2 (SSTDR3_2)
• SS receive data register 0_2 (SSRDR0_2)
• SS receive data register 1_2 (SSRDR1_2)
• SS receive data register 2_2 (SSRDR2_2)
• SS receive data register 3_2 (SSRDR3_2)
• SS shift register_2 (SSTRSR_2)

Section 14 Synchronous Serial Communication Unit (SSU) Rev. 3.00 Mar. 14, 2006 Page 514 of 804 REJ09B0104-0300

14.3.1 SS Control Register H (SSCRH)

SSCRH specifies master/slave device selection, bidirectional mode enable, SSO pin output value selection, SSCK pin selection, and SCS pin selection. MSS R/W BIDE R/W R/W SOL R/W SOLP R/W CSS0 R/W SCKS R/W CSS1 R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description

7 MSS 0 R/W Master/Slave Device Select

Selects that this module is used in master mode or slave mode. When master mode is selected, transfer clocks are output from the SSCK pin. When the CE bit in SSSR is set, this bit is automatically cleared. 0: Slave mode is selected. 1: Master mode is selected.

6 BIDE 0 R/W Bidirectional Mode Enable

Selects that both serial data input pin and output pin are used or one of them is used. However, transmission and reception are not performed simultaneously when bidirectional mode is selected. For details, section 14.4.3, Relationship between Data Input/Output Pins and Shift Register. 0: Standard mode (two pins are used for data input and output) 1: Bidirectional mode (one pin is used for data input and output) 5  0 R/W Reserved This bit is always read as 0. The write value should always be 0.

Section 14 Synchronous Serial Communication Unit (SSU) Rev. 3.00 Mar. 14, 2006 Page 515 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description

4 SOL 0 R/W Serial Data Output Value Select

The serial data output retains its level of the last bit after completion of transmission. The output level before or after transmission can be specified by setting this bit. When specifying the output level, use the MOV instruction after clearing the SOLP bit to 0. Since writing to this bit during data transmission causes malfunctions, this bit should not be changed. 0: Serial data output is changed to low. 1: Serial data output is changed to high.

3 SOLP 1 R/W SOL Bit Write Protect

When changing the output level of serial data, set the SOL bit to 1 or clear the SOL bit to 0 after clearing the SOLP bit to 0 using the MOV instruction. 0: Output level can be changed by the SOL bit 1: Output level cannot be changed by the SOL bit. This bit is always read as 1.

2 SCKS 0 R/W SSCK Pin Select

Selects that the SSCK pin functions as a port or a serial clock pin. When the SSCK pin is used as a serial clock pin, this bit must be set to 1. 0: Functions as an I/O port. 1: Functions as a serial clock. CSS1 CSS0 R/W R/W SCS Pin Select Select that the SCS pin functions as a port or SCS input or output. However, when MSS = 0, the SCS pin functions as an input pin regardless of the CSS1 and CSS0 settings. 00: I/O port 01: Function as SCS input 10: Function as SCS automatic input/output (function as SCS input before and after transfer and output a low level during transfer) 11: Function as SCS automatic output (outputs a high level before and after transfer and outputs a low level during transfer)

Section 14 Synchronous Serial Communication Unit (SSU) Rev. 3.00 Mar. 14, 2006 Page 516 of 804 REJ09B0104-0300

14.3.2 SS Control Register L (SSCRL)

SSCRL selects operating mode, software reset, and transmit/receive data length. R/W SSUMS R/W SRES R/W R/W R/W DATS0 R/W R/W DATS1 R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description 7  0 R/W Reserved This bit is always read as 0. The write value should always be 0.

6 SSUMS 0 R/W Selects transfer mode from SSU mode and clock

synchronous mode. 0: SSU mode 1: Clock synchronous mode

5 SRES 0 R/W Software Reset

Setting this bit to 1 forcibly resets the SSU internal sequencer. After that, this bit is automatically cleared. The ORER, TEND, TDRE, RDRF, and CE bits in SSSR and the TE and RE bits in SSER are also initialized. Values of other bits for SSU registers are held. To stop transfer, set this bit to 1 to reset the SSU internal sequencer. 4 to 2  All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. DATS1 DATS0 R/W R/W Transmit/Receive Data Length Select Select serial data length. 00: 8 bits 01: 16 bits 10: 32 bits 11: Setting prohibited

Section 14 Synchronous Serial Communication Unit (SSU) Rev. 3.00 Mar. 14, 2006 Page 517 of 804 REJ09B0104-0300

14.3.3 SS Mode Register (SSMR)

SSMR selects the MSB first/LSB first, clock polarity, clock phase, and clock rate of synchronous serial communication. MLS R/W CPOS R/W CPHS R/W R/W R/W CKS0 R/W CKS2 R/W CKS1 R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description

7 MLS 0 R/W MSB First/LSB First Select

Selects that the serial data is transmitted in MSB first or LSB first. 0: LSB first 1: MSB first

6 CPOS 0 R/W Clock Polarity Select

Selects the SSCK clock polarity. 0: High output in idle mode, and low output in active mode 1: Low output in idle mode, and high output in active mode

5 CPHS 0 R/W Clock Phase Select (Only for SSU Mode)

Selects the SSCK clock phase. 0: Data changes at the first edge. 1: Data is latched at the first edge. 4, 3  All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. Transfer Clock Rate Select Select the transfer clock rate (prescaler division rate) when an internal clock is selected. CKS2 CKS1 CKS0 R/W R/W R/W 000: Reserved 001: Pφ/4 010: Pφ/8 011: Pφ/16 100: Pφ/32 101: Pφ/64 110: Pφ/128 111: Pφ/256

Section 14 Synchronous Serial Communication Unit (SSU) Rev. 3.00 Mar. 14, 2006 Page 518 of 804 REJ09B0104-0300

14.3.4 SS Enable Register (SSER)

SSER performs transfer/receive control of synchronous serial communication and setting of interrupt enable. TE R/W RE R/W R/W R/W TEIE R/W CEIE R/W TIE R/W RIE R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description

7 TE 0 R/W Transmit Enable

When this bit is set to 1, transmission is enabled.

6 RE 0 R/W Receive Enable

When this bit is set to 1, reception is enabled. 5, 4  All 0 R/W Reserved These bits are always read as 0. The write value should always be 0.

3 TEIE 0 R/W Transmit End Interrupt Enable

When this bit is set to 1, a TEI interrupt request is enabled.

2 TIE 0 R/W Transmit Interrupt Enable

When this bit is set to 1, a TXI interrupt request is enabled.

1 RIE 0 R/W Receive Interrupt Enable

When this bit is set to 1, an RXI interrupt request and an OEI interrupt request are enabled.

0 CEIE 0 R/W Conflict Error Interrupt Enable

When this bit is set to 1, a CEI interrupt request is enabled.

Section 14 Synchronous Serial Communication Unit (SSU) Rev. 3.00 Mar. 14, 2006 Page 519 of 804 REJ09B0104-0300

14.3.5 SS Status Register (SSSR)

SSSR is a status flag register for interrupts. R/W ORER R/W R/W R/W TEND R/W CE R/W TDRE R/W RDRF R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description 7  0  Reserved This bit is always read as 0. The write value should always be 0.

6 ORER 0 R/W Overrun Error

If the next data is received while RDRF = 1, an overrun error occurs, indicating abnormal termination. SSRDR stores 1-frame receive data before an overrun error occurs and loses data to be received later. While ORER = 1, consecutive serial reception cannot be continued. Serial transmission cannot be continued, either. [Setting condition] When one byte of the next reception is completed with RDRF = 1 [Clearing condition] When writing 0 after reading ORER = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 5, 4  All 0 R/W Reserved These bits are always read as 0. The write value should always be 0.

Section 14 Synchronous Serial Communication Unit (SSU) Rev. 3.00 Mar. 14, 2006 Page 520 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description

3 TEND 1 R Transmit End

[Setting condition]

• When the last bit of transmit data is transmitted while the TENDSTS bit in SSCR2 is cleared to 0 and the TDRE bit is set to 1
• After the last bit of transmit data is transmitted while the TENDSTS bit in SSCR2 is set to 1 and the TDRE bit is set to 1 [Clearing conditions]
• When writing 0 after reading TEND = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
• When writing data to SSTDR

2 TDRE 1 R/W Transmit Data Empty

Indicates whether or not SSTDR contains transmit data. [Setting conditions]

• When the TE bit in SSER is 0
• When data is transferred from SSTDR to SSTRSR and SSTDR is ready to be written to. [Clearing conditions]
• When writing 0 after reading TDRE = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
• When writing data to SSTDR with TE = 1

1 RDRF 0 R/W Receive Data Register Full

Indicates whether or not SSRDR contains receive data. [Setting condition]

• When receive data is transferred from SSTRSR to SSRDR after successful serial data reception [Clearing conditions]
• When writing 0 after reading RDRF = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
• When reading receive data from SSRDR

Section 14 Synchronous Serial Communication Unit (SSU) Rev. 3.00 Mar. 14, 2006 Page 521 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description

0 CE 0 R/W Conflict/Incomplete Error

Indicates that a conflict error has occurred when 0 is externally input to the SCS pin with SSUMS = 0 (SSU mode) and MSS = 1 (master mode). If the SCS pin level changes to 1 with SSUMS = 0 (SSU mode) and MSS = 0 (slave mode), an incomplete error occurs because it is determined that a master device has terminated the transfer. Data reception does not continue while the CE bit is set to 1. Serial transmission also does not continue. Reset the SSU internal sequencer by setting the SRES bit in SSCRL to 1 before resuming transfer after incomplete error. [Setting condition]

• When a low level is input to the SCS pin in master mode (the MSS bit in SSCRH is set to 1)
• When the SCS pin is changed to 1 during transfer in slave mode (the MSS bit in SSCRH is cleared to 0) [Clearing condition]
• When writing 0 after reading CE = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)

14.3.6 SS Control Register 2 (SSCR2)

SSCR2 is a register that enables/disables the open-drain outputs of the SSO, SSI, SSCK, and SCS pins, selects the assert timing of the SCS pin, data output timing of the SSO pin, and set timing of the TEND bit. SDOS R/W SSCKOS R/W SCSOS R/W TENDSTS R/W SCSATS R/W R/W SSODTS R/W R/W Bit Bit Name Initial Value R/W

Section 14 Synchronous Serial Communication Unit (SSU) Rev. 3.00 Mar. 14, 2006 Page 522 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description

7 SDOS 0 R/W Serial Data Pin Open Drain Select

Selects whether the serial data output pin is used as a CMOS or an NMOS open drain output. Pins to output serial data differ according to the register setting. For details, 14.4.3, Relationship between Data Input/Output Pins and Shift Register. 0: CMOS output 1: NMOS open drain output

6 SSCKOS 0 R/W SSCK Pin Open Drain Select

Selects whether the SSCK pin is used as a CMOS or an NMOS open drain output. 0: CMOS output 1: NMOS open drain output

5 SCSOS 0 R/W SCS Pin Open Drain Select

Selects whether the SCS pin is used as a CMOS or an NMOS open drain output. 0: CMOS output 1: NMOS open drain output

4 TENDSTS 0 R/W Selects the timing of setting the TEND bit (valid in SSU

and master mode). 0: Sets the TEND bit when the last bit is being transmitted 1: Sets the TEND bit after the last bit is transmitted

3 SCSATS 0 R/W Selects the assertion timing of the SCS pin (valid in

SSU and master mode). 0: Min. values of tLEAD and tLAG are 1/2 × tSUcyc 1: Min. values of tLEAD and tLAG are 3/2 × tSUcyc

2 SSODTS 0 R/W Selects t he data output timing of the SSO pin (valid in

SSU and master mode) 0: While BIDE = 0, MSS = 1, and TE = 1 or while BIDE = 1, TE = 1, and RE = 0, the SSO pin outputs data 1: While BIDE = 0, MSS = 1, and TE = 1 or while BIDE = 1, TE = 1, and RE = 0, the SSO pin outputs data while the SCS pin is driven low

Section 14 Synchronous Serial Communication Unit (SSU) Rev. 3.00 Mar. 14, 2006 Page 523 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description 1, 0  All 0 R/W Reserved These bits are always read as 0. The write value should always be 0.

14.3.7 SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)

SSTDR is an 8-bit register that stores transmit data. When 8-bit data length is selected by bits DATS1 and DATS0 in SSCRL, SSTDR0 is valid. When 16-bit data length is selected, SSTDR0 and SSTDR1 are valid. When 32-bit data length is selected, SSTDR0 to SSTDR3 are valid. Be sure not to access invalid SSTDRs When the SSU detects that SSTRSR is empty, it transfers the transmit data written in SSTDR to SSTRSR and starts serial transmission. If the next transmit data has already been written to SSTDR during serial transmission, the SSU performs consecutive serial transmission. Although SSTDR can always be read from or written to by the CPU and DMAC, to achieve reliable serial transmission, write transmit data to SSTDR after confirming that the TDRE bit in SSSR is set to 1. R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W

Section 14 Synchronous Serial Communication Unit (SSU) Rev. 3.00 Mar. 14, 2006 Page 524 of 804 REJ09B0104-0300 Table 14.2 Correspondence Between DATS Bit Setting and SSTDR DATS[1:0] (SSCRL[1:0]) SSTDR 00 01 10 11 (Setting Invalid)

0 Valid Valid Valid Invalid

1 Invalid Valid Valid Invalid

2 Invalid Invalid Valid Invalid

3 Invalid Invalid Valid Invalid

14.3.8 SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3)

SSRDR is an 8-bit register that stores receive data. When 8-bit data length is selected by bits DATS1 and DATS0 in SSCRL, SSRDR0 is valid. When 16-bit data length is selected, SSRDR0 and SSRDR1 are valid. When 32-bit data length is selected, SSRDR0 to SSRDR3 are valid. Be sure not to access invalid SSRDRs. When the SSU has received 1-byte data, it transfers the received serial data from SSTRSR to SSRDR where it is stored. After this, SSTRSR is ready for reception. Since SSTRSR and SSRDR function as a double buffer in this way, consecutive receive operations can be performed. Read SSRDR after confirming that the RDRF bit in SSSR is set to 1. SSRDR is a read-only register, therefore, cannot be written to by the CPU.

Section 14 Synchronous Serial Communication Unit (SSU) Rev. 3.00 Mar. 14, 2006 Page 525 of 804 REJ09B0104-0300 R R R R R R R R Bit Bit Name Initial Value R/W R R R R R R R R Bit Bit Name Initial Value R/W R R R R R R R R Bit Bit Name Initial Value R/W R R R R R R R R Bit Bit Name Initial Value R/W Table 14.3 Correspondence Between DATS Bit Setting and SSRDR DATS[1:0] (SSCRL[1:0]) SSRDR 00 01 10 11 (Setting Invalid)

14.3.9 SS Shift Register (SSTRSR)

SSTRSR is a shift register that transmits and receives serial data. When data is transferred from SSTDR to SSTRSR, bit 0 of transmit data is bit 0 in the SSTDR contents (MLS = 0: LSB first communication) and is bit 7 in the SSTDR contents (MLS = 1: MSB first communication). The SSU transfers data from the LSB (bit 0) in SSTRSR to the SSO pin to perform serial data transmission. In reception, the SSU sets serial data that has been input via the SSI pin in SSTRSR from the LSB (bit 0). When 1-byte data has been received, the SSTRSR contents are automatically transferred to SSRDR. SSTRSR cannot be directly accessed by the CPU.

Section 14 Synchronous Serial Communication Unit (SSU) Rev. 3.00 Mar. 14, 2006 Page 526 of 804 REJ09B0104-0300

14.4 Operation

14.4.1 Transfer Clock

A transfer clock can be selected from eight internal clocks and an external clock. When using this module, set the SCKS bit in SSCRH to 1 to select the SSCK pin as a serial clock. When the MSS bit in SSCRH is 1, an internal clock is selected and the SSCK pin is used as an output pin. When transfer is started, the clock with the transfer rate set by bits CKS2 to CKS0 in SSMR is output from the SSCK pin. When MSS = 0, an external clock is selected and the SSCK pin is used as an input pin.

14.4.2 Relationship of Clock Phase, Polarity, and Data

The relationship of clock phase, polarity, and transfer data depends on the combination of the CPOS and CPHS bits in SSMR. Figure 14.2 shows the relationship. When SSUMS = 1, the CPHS setting is invalid although the CPOS setting is valid. Setting the MLS bit in SSMR selects that MSB or LSB first communication. When MLS = 0, data is transferred from the LSB to the MSB. When MLS = 1, data is transferred from the MSB to the LSB. SSCK (CPOS = 0) (1) When CPHS = 0 (2) When CPHS = 1 SSCK (CPOS = 1) SSI, SSO SCS Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 SSCK (CPOS = 0) SSCK (CPOS = 1) SSI, SSO SCS Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Figure 14.2 Relationship of Clock Phase, Polarity, and Data

Section 14 Synchronous Serial Communication Unit (SSU) Rev. 3.00 Mar. 14, 2006 Page 527 of 804 REJ09B0104-0300

14.4.3 Relationship between Data Input/Output Pins and Shift Register

The connection between data input/output pins and the SS shift register (SSTRSR) depends on the combination of the MSS and BIDE bits in SSCRH and the SSUMS bit in SSCRL. Figure 14.3 show the relationship. The SSU transmits serial data from the SSO pin and receives serial data from the SSI pin when operating with BIDE = 0 and MSS = 1 (standard, master mode) (see figure 14.3 (1)). The SSU transmits serial data from the SSI pin and receives serial data from the SSO pin when operating with BIDE = 0 and MSS = 0 (standard, slave mode) (see figure 14.3 (2)). The SSU transmits and receives serial data from the SSO pin regardless of master or slave mode when operating with BIDE = 1 (bidirectional mode) (see figures 14.3 (3) and (4)). However, even if both the TE and RE bits are set to 1, transmission and reception are not performed simultaneously. Either the TE or RE bit must be selected. The SSU transmits serial data from the SSO pin and receives serial data from the SSI pin when operating with SSUMS = 1. The SSCK pin outputs the internal clock when MSS = 1 and function as an input pin when MSS = 0 (see figures 14.3 (5) and (6)). SSCK Shift register (SSTRSR) Shift register (SSTRSR) Shift register (SSTRSR) Shift register (SSTRSR) SSO SSI SSCK SSO SSI SSCK SSO SSI SSCK SSO SSI (1) When SSUMS = 0, BIDE = 0 (standard mode), MSS = 1, TE = 1, and RE = 1 SSCK Shift register (SSTRSR) SSO SSI SSCK Shift register (SSTRSR) SSO SSI (2) When SSUMS = 0, BIDE = 0 (standard mode), MSS = 0, TE = 1, and RE = 1 (3) When SSUMS = 0, BIDE = 1 (bidirectional mode), MSS = 0, and either TE or RE = 1 (4) When SSUMS = 0, BIDE = 1 (bidirectional mode), MSS = 1, and either TE or RE = 1 (5) When SSUMS = 1 and MSS = 1 (6) When SSUMS = 1 and MSS = 0 Figure 14.3 Relationship between Data Input/Output Pins and the Shift Register

Section 14 Synchronous Serial Communication Unit (SSU) Rev. 3.00 Mar. 14, 2006 Page 528 of 804 REJ09B0104-0300

14.4.4 Communication Mo des and Pin Functions

The SSU switches the input/output pin (SSI, SSO, SSCK, and SCS) functions according to the communication modes and register settings. When a pin is used as an input pin, set the corresponding bit in the input buffer control register (ICR) to 1. The relationship of communication modes and input/output pin functions are shown in tables 14.2 to 14.4. Table 14.4 Communication Modes and Pin States of SSI and SSO Pins Register Setting Pin State Communication Mode SSUMS BIDE MSS TE RE SSI SSO 0 0 0 0 1  Input SSU communication mode 1 0 Output 

1 Output Input

1 0 1 Input  1 0  Output

1 Input Output

0 1 0 0 1  Input SSU (bidirectional) communication mode 1 0  Output 1 0 1  Input 1 0  Output 1 0 0 0 1 Input  Clock synchronous communication mode 1 0  Output 1 0 1 Input  1 0  Output [Legend] : Not used as SSU pin (can be used as I/O port)

Section 14 Synchronous Serial Communication Unit (SSU) Rev. 3.00 Mar. 14, 2006 Page 529 of 804 REJ09B0104-0300 Table 14.5 Communication Mode s and Pin States of SSCK Pin Register Setting Pin State Communication Mode SSUMS MSS SCKS SSCK SSU communication mode 0 0 0 

1 Input

1 0 

1 Output

1 0 0  Clock synchronous communication mode 1 Input 1 0  [Legend] : Not used as SSU pin (can be used as I/O port) Table 14.6 Communication Modes and Pin States of SCS Pin Register Setting Pin State Communication Mode SSUMS MSS CSS1 CSS0 SCS 0 0 × × Input SSU communication mode 1 0 0  0 1 Input 1 0 Automatic input/output 1 1 Output Clock synchronous communication mode 1 × × ×  [Legend] ×: Don't care : Not used as SSU pin (can be used as I/O port)

Section 14 Synchronous Serial Communication Unit (SSU) Rev. 3.00 Mar. 14, 2006 Page 530 of 804 REJ09B0104-0300

14.4.5 SSU Mode

In SSU mode, data communications are performed via four lines: clock line (SSCK), data input line (SSI or SSO), data output line (SSI or SSO), and chip select line (SCS). In addition, the SSU supports bidirectional mode in which a single pin functions as data input and data output lines. (1) Initial Settings in SSU Mode Figure 14.4 shows an example of the initial settings in SSU mode. Before data transfer, clear both the TE and RE bits in SSER to 0 to set the initial values. Note: Before changing operating modes and communications formats, clear both the TE and RE bits to 0. Although clearing the TE bit to 0 sets the TDRE bit to 1, clearing the RE bit to 0 does not change the values of the RDRF and ORER bits and SSRDR. Those bits retain the previous values. Start setting initial values [1] [2] [3] [4] End Set a bit in ICR to 1 Clear SSUMS in SSCRH to 0 and specify bits DATS1 and DATS0 Specify MSS, BIDE, SOL, SCKS, CSS1, and CSS0 bits in SSCRH Specify MLS, CPOS, CPHS, CKS2, CKS1, and CKS0 bits in SSMR Specify SDOS, SSCKOS, SCSOS, TENDSTS, SCSATS and SSODTS bits in SSCR2 Clear TE and RE bits in SSER to 0 [1] When the pin is used as an input. [2] Specify master/slave mode selection, bidirectional mode enable, SSO pin output value selection, SSCK pin selection, and SCS pin selection. [3] Selects SSU mode and specify transmit/receive data length. [4] Specify MSB first/LSB first selection, clock polarity selection, clock phase selection, and transfer clock rate selection. [5] Enables/disables interrupt request to the CPU. Specify TE, RE, TEIE, TIE, RIE, and CEIE bits in SSER simultaneously[5] Figure 14.4 Example of Initial Settings in SSU Mode

Section 14 Synchronous Serial Communication Unit (SSU) Rev. 3.00 Mar. 14, 2006 Page 531 of 804 REJ09B0104-0300 (2) Data Transmission Figure 14.5 shows an example of transmission operation, and figure 14.6 shows a flowchart example of data transmission. When transmitting data, the SSU operates as shown below. In master mode, the SSU outputs a transfer clock and data. In slave mode, when a low level signal is input to the SCS pin and a transfer clock is input to the SSCK pin, the SSU outputs data in synchronization with the transfer clock. Writing transmit data to SSTDR after the TE bit is set to 1 clears the TDRE bit in SSSR to 0, and the SSTDR contents are transferred to SSTRSR. After that, the SSU sets the TDRE bit to 1 and starts transmission. At this time, if the TIE bit in SSER is set to 1, a TXI interrupt is generated. When 1-frame data has been transferred with TDRE = 0, the SSTDR contents are transferred to SSTRSR to start the next frame transmission. When the 8th bit of transmit data has been transferred with TDRE = 1, the TEND bit in SSSR is set to 1 and the state is retained. At this time, if the TEIE bit is set to 1, a TEI interrupt is generated. After transmission, the output level of the SSCK pin is fixed high when CPOS = 0 and low when CPOS = 1. While the ORER bit in SSSR is set to 1, transmission is not performed. Check that the ORER bit is cleared to 0.

Section 14 Synchronous Serial Communication Unit (SSU) Rev. 3.00 Mar. 14, 2006 Page 532 of 804 REJ09B0104-0300 SCS SSCK (1) When 8-bit data length is selected (SSTDR0 is valid) with CPOS = 0 and CPHS = 0 (2) When 16-bit data length is selected (SSTDR0 and SSTDR1 are valid) with CPOS = 0 and CPHS = 0 (3) When 32-bit data length is selected (SSTDR0 and SSTDR3 are valid) with CPOS = 0 and CPHS = 0 Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit 0 to to to to to to to toBit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit SSO TDRE TEND LSI operation User operation LSI operation User operation LSI operation User operation TXI interrupt generated TEI interrupt generated TEI interrupt generated TXI interrupt generated Data written to SSTDR0 Data written to SSTDR0 and SSTDR1 Data written to SSTDR0 SSTDR1 SCS SSCK TDRE TEND SSO (LSB first) SSO (MSB first) SSO (LSB first) SSO (MSB first) SSTDR0 SSTDR0 SSTDR1 SCS SSCK TDRE TEND SSTDR SSTDR SSTDR SSTDR SSTDR SSTDR SSTDR SSTDR 1 frame 1 frame 1 frame SSTDR0 (LSB first transmission) SSTDR0 (MSB first transmission) 1 frame TXI interrupt generated TEI interrupt generated Data written to SSTDR0 to SSTDR1 TXI interrupt generated TEI interrupt generated Figure 14.5 Example of Transmission Operation (SSU Mode)

Section 14 Synchronous Serial Communication Unit (SSU) Rev. 3.00 Mar. 14, 2006 Page 533 of 804 REJ09B0104-0300 Yes Start [1] [2] [3] [1] Initial setting: Specify the transmit data format. [2] Check that the SSU state and write transmit data: Write transmit data to SSTDR after reading and confirming that the TDRE bit is 1. The TDRE bit is automatically cleared to 0 and transmission is started by writing data to SSTDR. [3] Procedure for consecutive data transmission: To continue data transmission, confirm that the TDRE bit is 1 meaning that SSTDR is ready to be written to. After that, data can be written to SSTDR. The TDRE bit is automatically cleared to 0 by writing data to SSTDR. [4] Procedure for data transmission end: To end data transmission, confirm that the TEND bit is cleared to 0. After completion of transmitting the last bit, clear the TE bit to 0. Note: Hatching boxes represent SSU internal operations. Initial setting Read TDRE in SSSR TDRE = 1? Yes Yes No No No Write transmit data to SSTDR TDRE automatically cleared Data transferred from SSTDR to SSTRSR Set TDRE to 1 to start transmission Consecutive data transmission? Read TEND in SSSR TEND = 1? Clear TEND to 0 Clear TE in SSER to 0 End transmission Yes No Confirm that TEND is cleared to 0 One bit time quantum elapsed?[4] Figure 14.6 Flowchart Example of Data Transmission (SSU Mode)

Section 14 Synchronous Serial Communication Unit (SSU) Rev. 3.00 Mar. 14, 2006 Page 534 of 804 REJ09B0104-0300 (3) Data Reception Figure 14.7 shows an example of reception operation, and figure 14.8 shows a flowchart example of data reception. When receiving data, the SSU operates as shown below. After setting the RE bit to 1 and dummy-reading SSRDR, the SSU starts data reception. In master mode, the SSU outputs a transfer clock and receives data. In slave mode, when a low level signal is input to the SCS pin and a transfer clock is input to the SSCK pin, the SSU receives data in synchronization with the transfer clock. When 1-frame data has been received, the RDRF bit in SSSR is set to 1 and the receive data is stored in SSRDR. At this time, if the RIE bit in SSER is set to 1, an RXI interrupt is generated. The RDRF bit is automatically cleared to 0 by reading SSRDR. When the RDRF bit has been set to 1 at the 8th rising edge of the transfer clock, the ORER bit in SSSR is set to 1. This indicates that an overrun error (OEI) has occurred. At this time, data reception is stopped. While the ORER bit in SSSR is set to 1, reception is not performed. To resume the reception, clear the ORER bit to 0.

Section 14 Synchronous Serial Communication Unit (SSU) Rev. 3.00 Mar. 14, 2006 Page 535 of 804 REJ09B0104-0300 SCS SSCK (1) When 8-bit data length is selected (SSRDR0 is valid) with CPOS = 0 and CPHS = 0 (2) When 16-bit data length is selected (SSRDR0 and SSRDR1 are valid) with CPOS = 0 and CPHS = 0 (3) When 32-bit data length is selected (SSRDR0 to SSRDR3 are valid) with CPOS = 0 and CPHS = 0 SSI RDRF SSRDR1 SCS SSCK RDRF SSRDR0 SSRDR0 SSRDR1 SCS SSCK RDRF SSRDR0 SSRDR3 SSRDR1 SSRDR2 SSRDR2 SSRDR1 SSRDR3 SSRDR0 1 frame 1 frame 1 frame Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit LSI operation Dummy-read SSRDR0 Dummy-readSSRDR0 Read SSRDR0User operation LSI operation User operation LSI operation User operation SSTDR0 (LSB first transmission) SSTDR0 (MSB first transmission) RXI interrupt generated RXI interrupt generated RXI interrupt generated Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit SSI (LSB first) SSI (MSB first) Bit 0 to to to to to to to toBit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit SSI (LSB first) SSI (MSB first) Dummy-readSSRDR0 RXI interrupt generated Figure 14.7 Example of Reception Operation (SSU Mode)

Section 14 Synchronous Serial Communication Unit (SSU) Rev. 3.00 Mar. 14, 2006 Page 537 of 804 REJ09B0104-0300 Yes Start Initial setting[1] [2] [1] Initial setting: Specify the transmit/receive data format. [2] Check the SSU state and write transmit data: Write transmit data to SSTDR after reading and confirming that the TDRE bit in SSSR is 1. The TDRE bit is automatically cleared to 0 and transmission/ reception is started by writing data to SSTDR. [3] Check the SSU state: Read SSSR confirming that the RDRF bit is 1. A change of the RDRF bit (from 0 to 1) can be notified by RXI interrupt. [4] Receive error processing: When a receive error occurs, execute the designated error processing after reading the ORER bit in SSSR. After that, clear the ORER bit to 0. While the ORER bit is set to 1, transmission or reception is not resumed. [5] Procedure for consecutive data transmission/reception: To continue serial data transmission/reception, confirm that the TDRE bit is 1 meaning that SSTDR is ready to be written to. After that, data can be written to SSTDR. The TDRE bit is automatically cleared to 0 by writing data to SSTDR. [4] [5] [3] Read TDRE in SSSR TDRE = 1? Yes Yes Yes Yes No No No No Write transmit data to SSTDR TDRE automatically cleared Data transferred from SSTDR to SSTRSR TDRE set to 1 to start transmission Read SSSR RDRF = 1? No Read TEND in SSSR TEND = 1? Yes No Has the 1 bit transfer period elapsed? ORER = 1? Read receive data in SSRDR RDRF automatically cleared Consecutive data transmission/reception? Clear TEND in SSSR to 0 Clear TE and RE in SSER to 0 Error processing End transmission/reception Note: Hatching boxes represent SSU internal operations. Figure 14.9 Flowchart Example of Simultaneous Transmission/Reception (SSU Mode)

Section 14 Synchronous Serial Communication Unit (SSU) Rev. 3.00 Mar. 14, 2006 Page 538 of 804 REJ09B0104-0300

14.4.6 SCS Pin Control and Conflict Error

When bits CSS1 and CSS0 in SSCRH are specified to B'10 and the SSUMS bit in SSCRL is cleared to 0, the SCS pin functions as an input (Hi-Z) to detect a conflict error. The detection period is from setting the MSS bit in SSCRH to 1 to starting serial transfer and after transfer ends. When a low level signal is input to the SCS pin within the period, a conflict error occurs. At this time, the CE bit in SSSR is set to 1 and the MSS bit is cleared to 0. Note: While the CE bit is set to 1, transmission or reception is not resumed. Clear the CE bit to 0 before resuming the transmission or reception. CE Data written to SSTDR Conflict error detection period Worst time for internally clocking SCS MSS Internal signal for transfer enable SCS output External input to SCS Internal-clocked SCS (Hi-Z) Figure 14.10 Conflict Error Detection Timing (Before Transfer) Pφ SCS MSS CE (Hi-Z) Transfer end Conflict error detection period Internal signal for transfer enable Figure 14.11 Conflict Error Detection Timing (After Transfer End)

Section 14 Synchronous Serial Communication Unit (SSU) Rev. 3.00 Mar. 14, 2006 Page 539 of 804 REJ09B0104-0300

14.4.7 Clock Synchronous Communication Mode

In clock synchronous communication mode, data communications are performed via three lines: clock line (SSCK), data input line (SSI), and data output line (SSO). (1) Initial Settings in Clock Synchronous Communication Mode Figure 14.12 shows an example of the initial settings in clock synchronous communication mode. Before data transfer, clear both the TE and RE bits in SSER to 0 to set the initial values. Note: Before changing operating modes and communications formats, clear both the TE and RE bits to 0. Although clearing the TE bit to 0 sets the TDRE bit to 1, clearing the RE bit to 0 does not change the values of the RDRF and ORER bits and SSRDR. Those bits retain the previous values. Start setting initial values [1] [2] [3] [4] End Set a bit in ICR to 1 Set SSUMS in SSCRL to 1 and specify bits DATS1 and DATS0 Specify MSS and SCKS in SSCRH Specify CPOS, CKS2, CKS1, and CKS0 bits in SSMR Specify TE, RE, TEIE, TIE, RIE, and CEIE bits in SSER simultaneously Specify SDOS, SSCKOS, SCSOS, TENDSTS, SCSATS, and SSODTS bits in SSCR2 Clear TE and RE bits in SSER to 0 [1] When the pin is used as an input. [2] Specify master/slave mode selection and SSCK pin selection. [3] Selects clock synchronous communication mode and specify transmit/receive data length. [4] Specify clock polarity selection and transfer clock rate selection. [5] Enables/disables interrupt request to the CPU. [5] Figure 14.12 Example of Initial Settings in Clock Synchronous Communication Mode

Section 14 Synchronous Serial Communication Unit (SSU) Rev. 3.00 Mar. 14, 2006 Page 541 of 804 REJ09B0104-0300 Yes Start [1] [2] [3] [4][1] Initial setting: Specify the transmit data format. [2] Check that the SSU state and write transmit data: Write transmit data to SSTDR after reading and confirming that the TDRE bit is 1. The TDRE bit is automatically cleared to 0 and transmission is started by writing data to SSTDR. [3] Procedure for consecutive data transmission: To continue data transmission, confirm that the TDRE bit is 1 meaning that SSTDR is ready to be written to. After that, data can be written to SSTDR. The TDRE bit is automatically cleared to 0 by writing data to SSTDR. [4] Procedure for data transmission end: To end data transmission, confirm that the TEND bit is cleared to 0. After completion of transmitting the last bit, clear the TE bit to 0. Note: Hatching boxes represent SSU internal operations. Initial setting Read TDRE in SSSR TDRE = 1? Yes Yes No No No Write transmit data to SSTDR TDRE automatically cleared Data transferred from SSTDR to SSTRSR Set TDRE to 1 to start transmission Consecutive data transmission? Read TEND in SSSR TEND = 1? Clear TE in SSER to 0 End transmission Yes No Confirm that TEND is cleared to 0 One bit time quantum elapsed? Clear TEND to 0 [4] Figure 14.14 Flowchart Example of Transmission Operation (Clock Synchronous Communication Mode)

Section 14 Synchronous Serial Communication Unit (SSU) Rev. 3.00 Mar. 14, 2006 Page 544 of 804 REJ09B0104-0300 Yes Start Initial setting[1] [2] [1] Initial setting: Specify the transmit/receive data format. [2] Check the SSU state and write transmit data: Write transmit data to SSTDR after reading and confirming that the TDRE bit in SSSR is 1. The TDRE bit is automatically cleared to 0 and transmission is started by writing data to SSTDR. [3] Check the SSU state: Read SSSR confirming that the RDRF bit is 1. A change of the RDRF bit (from 0 to 1) can be notified by RXI interrupt. [4] Receive error processing: When a receive error occurs, execute the designated error processing after reading the ORER bit in SSSR. After that, clear the ORER bit to 0. While the ORER bit is set to 1, transmission or reception is not resumed. [5] Procedure for consecutive data transmission/reception: To continue serial data transmission/reception, confirm that the TDRE bit is 1 meaning that SSTDR is ready to be written to. After that, data can be written to SSTDR. The TDRE bit is automatically cleared to 0 by writing data to SSTDR. [4] [5] [3] Read TDRE in SSSR TDRE = 1? Yes Yes Yes No No No Write transmit data to SSTDR TDRE automatically cleared Data transferred from SSTDR to SSTRSR TDRE set to 1 to start transmission Read SSSR RDRF = 1? ORER = 1? Read receive data in SSRDR RDRF automatically cleared Consecutive data transmission/reception? Clear TE and RE in SSER to 0 Error processing End transmission/reception Note: Hatching boxes represent SSU internal operations. Yes No No Read TEND in SSSR TEND = 1? Yes No Has the 1 bit transfer period elapsed? Clear TEND in SSSR to 0 Figure 14.17 Flowchart Example of Simultaneous Transmission/Reception (Clock Synchronous Communication Mode)

Section 14 Synchronous Serial Communication Unit (SSU) Rev. 3.00 Mar. 14, 2006 Page 545 of 804 REJ09B0104-0300

14.5 Interrupt Requests

The SSU interrupt requests are an overrun error, a conflict error, a receive data register full, transmit data register empty, and a transmit end interrupts. Of these interrupt sources, a receive data register full, a transmit data register empty, and a transmit end interrupts can activate the DMAC for data transfer. Since both an overrun error and a conflict error interrupts are allocated to the SSERI vector address, and both a transmit data register empty and a transmit end interrupts are allocated to the SSTXI vector address, the interrupt source should be decided by their flags. Table 14.7 lists the interrupt sources. When an interrupt condition shown in table 14.7 is satisfied, an interrupt is requested. Clear the interrupt source by CPU or DMAC data transfer. Table 14.7 Interrupt Sources Channel Abbreviation Interrupt Source Symbol Interrupt Condition DMAC Activation

0 SSERI0 Overrun error OEI0 (RIE = 1) • (ORER = 1) 

Conflict error CEI0 (CEIE = 1) • (CE = 1)  SSRXI0 Receive data register full RXI0 (RIE = 1) • (RDRF = 1) Yes SSTXI0 Transmit data register empty TXI0 (TIE = 1) • (TDRE = 1) Yes Transmit end TEI0 (TEIE = 1) • (TEND = 1) Yes

1 SSERI1 Overrun error OEI1 (RIE = 1) • (ORER = 1) 

Conflict error CEI1 (CEIE = 1) • (CE = 1)  SSRXI1 Receive data register full RXI1 (RIE = 1) • (RDRF = 1) Yes SSTXI1 Transmit data register empty TXI1 (TIE = 1) • (TDRE = 1) Yes Transmit end TEI1 (TEIE = 1) • (TEND = 1) Yes

2 SSERI2 Overrun error OEI2 (RIE = 1) • (ORER = 1) 

Conflict error CEI2 (CEIE = 1) • (CE = 1)  SSRXI2 Receive data register full RXI2 (RIE = 1) • (RDRF = 1) Yes SSTXI2 Transmit data register empty TXI2 (TIE = 1) • (TDRE = 1) Yes Transmit end TEI2 (TEIE = 1) • (TEND = 1) Yes

Section 14 Synchronous Serial Communication Unit (SSU) Rev. 3.00 Mar. 14, 2006 Page 546 of 804 REJ09B0104-0300

14.6 Usage Note

14.6.1 Setting of Module Stop Mode

The SSU can be enabled/disabled by the module stop control register setting and is disabled by the initial value. Canceling module stop mode enables to access the SSU registers. For details, see section 19, Power-Down Modes.

14.6.2 Notes on Clearing Module Stop Mode

When clearing module stop mode, attention is required to the following. When using the SSU channel 1 (or 2), module stop mode of the SSU channel 1 (or 2) is not cleared without clearing both 1 and 2 bits listed below. 1. Module stop bit for channel 1 (or 2): MSTPC9 (or MSTPC10) 2. Module stop bit for channel 0: MSTPC8 When the SSU channel 0 is not used for the SSU function, I/O port pins that are multiplexed with the SSU channel 0 function can be used as I/O port pins unless module stop mode of SSU channel 0 is cleared and the SSU channel 0 is enabled for transmission and reception.

Rev. 3.00 Mar. 14, 2006 Page 547 of 804 REJ09B0104-0300 Section 15 A/D Converter This LSI includes two units (unit 0 and unit 1) of successive approximation type 10-bit A/D converters that allow up to 16 analog input channels to be selected. Figures 15.1 and 15.2 are block diagrams for unit 0 and unit 1, respectively. This section describes unit 0, which has the same functions as the other unit.

15.1 Features

• 10-bit resolution
• 16 input channels (eight channels for unit 0 and eight channels for unit 1)
• Conversion time: 7.4 µs per channel (at 35-MHz operation)
• Two kinds of operating modes  Single mode: Single-channel A/D conversion  Scan mode: Continuous A/D conversion on 1 to 4 channels, or 1 to 8 channels
• 16 data registers (eight registers for unit 0 and eight registers for unit 1) A/D conversion results are held in a 16-bit data register for each channel
• Sample and hold function
• Three types of conversion start Conversion can be started by software, a conversion start trigger by the 16-bit timer pulse unit (TPU), or an external trigger signal.
• Interrupt source A/D conversion end interrupt (ADI) request can be generated.
• Module stop mode can be set

Rev. 3.00 Mar. 14, 2006 Page 548 of 804 REJ09B0104-0300 Module data bus Control circuit Internal data bus 10-bit D/A Comparator Sample-and- hold circuit ADI0 interrupt signal Bus interface AVCC0 AVSS AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADTRG0 Conversion start trigger from the TPU Successive approximation register Multiplexer [Legend] ADCR_0: A/D control register_0 ADCSR_0: A/D control/status register_0 ADDRA_0: A/D data register A_0 ADDRB_0: A/D data register B_0 ADDRC_0: A/D data register C_0 ADDRD_0: A/D data register D_0 ADDRE_0: A/D data register E_0 ADDRF_0: A/D data register F_0 ADDRG_0: A/D data register G_0 ADDRH_0: A/D data register H_0 ADDRA_0 ADDRB_0 ADDRC_0 ADDRD_0 ADDRE_0 ADDRF_0 ADDRG_0 ADDRH_0 ADCSR_0 ADCR_0 Figure 15.1 Block Diagram of A/D Converter (Unit 0/AD_0)

Rev. 3.00 Mar. 14, 2006 Page 549 of 804 REJ09B0104-0300 AVCC1 AVSS AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 Conversion start trigger from the TPU Module data bus Control circuit Internal data bus 10-bit D/A Comparator Sample-and- hold circuit ADI1 interrupt signal Bus interface ADTRG1 Successive approximation register Multiplexer [Legend] ADCR_1: A/D control register_1 ADCSR_1: A/D control/status register_1 ADDRA_1: A/D data register A_1 ADDRB_1: A/D data register B_1 ADDRC_1: A/D data register C_1 ADDRD_1: A/D data register D_1 ADDRE_1: A/D data register E_1 ADDRF_1: A/D data register F_1 ADDRG_1: A/D data register G_1 ADDRH_1: A/D data register H_1 ADDRA_1 ADDRB_1 ADDRC_1 ADDRD_1 ADDRE_1 ADDRF_1 ADDRG_1 ADDRH_1 ADCSR_1 ADCR_1 Figure 15.2 Block Diagram of A/D Converter (Unit 1/AD_1)

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15.2 Input/Output Pins

Table 15.1 shows the pin configuration of the A/D converter. Table 15.1 Pin Configuration Unit Abbr. Pin Name Symbol I/O Function

0 AD_0 Analog input pin 0 AN0 Input Analog inputs

Analog input pin 1 AN1 Input Analog input pin 2 AN2 Input Analog input pin 3 AN3 Input Analog input pin 4 AN4 Input Analog input pin 5 AN5 Input Analog input pin 6 AN6 Input Analog input pin 7 AN7 Input A/D external trigger input pin 0 ADTRG0 Input External trigger input for starting A/D conversion Analog power supply pin 0 AV CC0 Input Analog block power supply

1 AD_1 Analog input pin 8 AN8 Input Analog inputs

Analog input pin 9 AN9 Input Analog input pin 10 AN10 Input Analog input pin 11 AN11 Input Analog input pin 12 AN12 Input Analog input pin 13 AN13 Input Analog input pin 14 AN14 Input Analog input pin 15 AN15 Input A/D external trigger input pin 1 ADTRG1 Input External trigger input for starting A/D conversion Analog power supply pin 1 AV CC1 Input Analog block power supply Common Analog ground pin AV SS Input Analog block ground

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15.3 Register Descriptions

The A/D converter has the following registers. The registers for unit 0 (A/D_0) and unit 1 (A/D_1) have the same functions. In this descriptions, AN8 to AN15 correspond to AN0 to AN7.

• Unit 0 (A/D_0)  A/D data register A_0 (ADDRA_0)  A/D data register B_0 (ADDRB_0)  A/D data register C_0 (ADDRC_0)  A/D data register D_0 (ADDRD_0)  A/D data register E_0 (ADDRE_0)  A/D data register F_0 (ADDRF_0)  A/D data register G_0 (ADDRG_0)  A/D data register H_0 (ADDRH_0)  A/D control/status register_0 (ADCSR_0)  A/D control register_0 (ADCR_0)
• Unit 1 (A/D_1)  A/D data register A_1 (ADDRA_1)  A/D data register B_1 (ADDRB_1)  A/D data register C_1 (ADDRC_1)  A/D data register D_1 (ADDRD_1)  A/D data register E_1 (ADDRE_1)  A/D data register F_1 (ADDRF_1)  A/D data register G_1 (ADDRG_1)  A/D data register H_1 (ADDRH_1)  A/D control/status register_1 (ADCSR_1)  A/D control register_1 (ADCR_1)

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15.3.1 A/D Data Registers A to H (ADDRA to ADDRH)

There are eight 16-bit read-only ADDR registers, ADDRA to ADDRH, used to store the results of A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown in table 15.2. The converted 10-bit data is stored in bits 15 to 6. The lower 6-bit data is always read as 0. The data bus between the CPU and the A/D converter has a 16-bit width. The data can be read directly from the CPU. ADDR must not be accessed in 8-bit units and must be accessed in 16-bit units. R R R R R R R R R R R R R R R R Bit Bit Name Initial Value R/W Table 15.2 Analog Input Channels and Corresponding ADDR Registers Analog Input Channel A/D Data Regist er Which Stores Conversion Result AN0 ADDRA AN1 ADDRB AN2 ADDRC AN3 ADDRD AN4 ADDRE AN5 ADDRF AN6 ADDRG AN7 ADDRH

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15.3.2 A/D Control/Status Register (ADCSR)

ADCSR controls A/D conversion operations. ADF R/(W)* ADIE R/W ADST R/W R CH3 R/W CH2 R/W CH1 R/W CH0 R/W Bit Bit Name Initial Value R/W Note: * Only 0 can be written to this bit, to clear the flag. Bit Bit Name Initial Value R/W Description

7 ADF 0 R/(W) * A/D End Flag

A status flag that indicates the end of A/D conversion. [Setting conditions]

• When A/D conversion ends in single mode
• When A/D conversion ends on all specified channels in scan mode [Clearing conditions]
• When 0 is written after reading ADF = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
• When the DMAC is activated by an ADI interrupt and ADDR is read

6 ADIE 0 R/W A/D Interrupt Enable

When this bit is set to 1, ADI interrupts by ADF are enabled.

5 ADST 0 R/W A/D Start

Clearing this bit to 0 stops A/D conversion, and the A/D converter enters wait state. Setting this bit to 1 starts A/D conversion. In single mode, this bit is cleared to 0 automatically when A/D conversion on the specified channel ends. In scan mode, A/D conversion continues sequentially on the specified channels until this bit is cleared to 0 by software or a reset. 4  0 R Reserved This is a read-only bit and cannot be modified.

Rev. 3.00 Mar. 14, 2006 Page 554 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description CH3 CH2 CH1 CH0 R/W R/W R/W R/W Channel Select 3 to 0 Selects analog input together with bits SCANE and SCANS in ADCR.

• When SCANE = 0 and SCANS = X 0000: AN0 0001: AN1 0010: AN2 0011: AN3 0100: AN4 0101: AN5 0110: AN6 0111: AN7 1XXX: Setting prohibited
• When SCANE = 1 and SCANS = 0 0000: AN0 0001: AN0 and AN1 0010: AN0 to AN2 0011: AN0 to AN3 0100: AN4 0101: AN4 and AN5 0110: AN4 to AN6 0111: AN4 to AN7 1XXX: Setting prohibited
• When SCANE = 1 and SCANS = 1 0000: AN0 0001: AN0 and AN1 0010: AN0 to AN2 0011: AN0 to AN3 0100: AN0 to AN4 0101: AN0 to AN5 0110: AN0 to AN6 0111: AN0 to AN7 1XXX: Setting prohibited [Legend] X: Don't care Note: * Only 0 can be written to this bit, to clear the flag.

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15.3.3 A/D Control Register (ADCR)

ADCR enables A/D conversion to be started by an external trigger input. TRGS1 R/W TRGS0 R/W SCANE R/W SCANS R/W CKS1 R/W CKS0 R/W R R Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description TRGS1 TRGS0 R/W R/W Timer Trigger Select 1 and 0 These bits select enabling or disabling of the start of A/D conversion by a trigger signal. 00: A/D conversion start by external trigger is disabled 01: A/D conversion start by external trigger from TPU is enabled 10: Setting prohibited 11: A/D conversion start by the ADTRG pin is enabled* SCANE SCANS R/W R/W Scan Mode These bits select the A/D conversion operating mode. 0X: Single mode 10: Scan mode. A/D conversion is performed continuously for channels 1 to 4. 11: Scan mode. A/D conversion is performed continuously for channels 1 to 8. CKS1 CKS0 R/W R/W Clock Select 1 and 0 These bits set the A/D conversion time. Set bits CKS1 and CKS0 only while A/D conversion is stopped (ADST = 0). 00: A/D conversion time = 530 states (max) 01: A/D conversion time = 266 states (max) 10: A/D conversion time = 134 states (max) 11: A/D conversion time = 68 states (max) 1, 0  All 0 R Reserved These are read-only bits and cannot be modified. [Legend] X: Don't care

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15.4 Operation

The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. When changing the operating mode or analog input channel, to prevent incorrect operation, first clear the ADST bit in ADCSR to 0 to halt A/D conversion. The ADST bit can be set to 1 at the same time as the operating mode or analog input channel is changed.

15.4.1 Single Mode

In single mode, A/D conversion is to be performed only once on the analog input of the specified single channel. 1. A/D conversion for the selected channel is started when the ADST bit in ADCSR is set to 1 by software or an external trigger input. 2. When A/D conversion is completed, the A/D conversion result is transferred to the corresponding A/D data register of the channel. 3. When A/D conversion is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. 4. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when A/D conversion ends. The A/D converter enters wait state. If the ADST bit is cleared to 0 during A/D conversion, A/D conversion stops and the A/D converter enters wait state.

Rev. 3.00 Mar. 14, 2006 Page 557 of 804 REJ09B0104-0300 ADIE ADST ADF ADDRA ADDRB ADDRC ADDRD Channel 0 (AN0) operation state Channel 1 (AN1) operation state Channel 2 (AN2) operation state Channel 3 (AN3) operation state Set* Set* Set* A/D conversion start Clear* Clear* Waiting for conversion Waiting for conversion Waiting for conversion Waiting for conversion Waiting for conversion Reading A/D conversion result Reading A/D conversion result A/D conversion 1 A/D conversion 2 A/D conversion result 1 A/D conversion result 2 Waiting for conversion Note: * ↓ indicates the timing of instruction execution by software. Figure 15.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)

15.4.2 Scan Mode

In scan mode, A/D conversion is to be performed sequentially on the analog inputs of the specified channels up to four or eight channels. 1. When the ADST bit in ADCSR is set to 1 by software, TPU, or an external trigger input, A/D conversion starts on the first channel in the group. Consecutive A/D conversion on a maximum of four channels (SCANE and SCANS = B'10) or on a maximum of eight channels (SCANE and SCANS = B'11) can be selected. When consecutive A/D conversion is performed on four channels, A/D conversion starts on AN0 when CH3 and CH2 = B'00, on AN4 when CH3 and CH2 = B'01, on AN8 when CH3 and CH2 = B'10, and on AN12 when CH3 and CH2 = B'11. When consecutive A/D conversion is performed on eight channels, A/D conversion starts on AN0 when CH3 = B'0 and on AN8 when CH3 = B'1. 2. When A/D conversion for each channel is completed, the A/D conversion result is sequentially transferred to the corresponding ADDR of each channel. 3. When A/D conversion of all selected channels is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. A/D conversion of the first channel in the group starts again.

Rev. 3.00 Mar. 14, 2006 Page 558 of 804 REJ09B0104-0300 4. The ADST bit is not cleared automatically, and steps [2] to [3] are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the A/D converter enters wait state. If the ADST bit is later set to 1, A/D conversion starts again from the first channel in the group. ADST ADF ADDRA ADDRB ADDRC ADDRD Set*

1 Clear*1

Clear*1 Waiting for conversionChannel 0 (AN0) operation state Channel 1 (AN1) operation state Channel 2 (AN2) operation state Channel 3 (AN3) operation state Waiting for conversion A/D conver- sion 1 A/D conversion result 3 Waiting for conversion Waiting for conversion Waiting for conversion A/D conversion result 2 A/D conversion result 4 A/D conver- sion 5 A/D conver- sion 4 A/D conversion time Waiting for conversion A/D conver- sion 3 Waiting for conversion Waiting for conversion Waiting for conversion A/D conver- sion 2 A/D conversion result 1 Transfer A/D conversion consecutive execution Notes: 1. ↓ indicates the timing of instruction execution by software. Data being converted is ignored. Figure 15.4 Example of A/D Conversion (Scan Mode, Three Channels (AN0 to AN2) Selected)

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15.4.3 Input Sampling and A/D Conversion Time

The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD ) passes after the ADST bit in ADCSR is set to 1, then starts A/D conversion. Figure 15.5 shows the A/D conversion timing. Table 15.3 indicates the A/D conversion time. As indicated in figure 15.5, the A/D conversion time (t CONV ) includes tD and the input sampling time (tSPL ). The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 15.3. In scan mode, the values given in table 15.3 apply to the first conversion time. The values given in table 15.4 apply to the second and subsequent conversions. In either case, bits CKS1 and CKS0 in ADCR should be set so that the conversion time is within the ranges indicated by the A/D conversion characteristics. (1) (2) tD tSPL tCONV Pφ Address Write signal Input sampling timing ADF [Legend] (1): ADCSR write cycle (2): ADCSR address t D: A/D conversion start delay time tSPL: Input sampling time tCONV: A/D conversion time Figure 15.5 A/D Conversion Timing

Rev. 3.00 Mar. 14, 2006 Page 560 of 804 REJ09B0104-0300 Table 15.3 A/D Conversion Characteristics (Single Mode) CKS1 = 0 CKS1 = 1 CKS0 = 0 CKS0 = 1 CKS0 = 0 CKS0 = 1 A/D conversion start delay time tD 18  33 10  17 6  9 4  5 Input sampling time t SPL  127   63   31   15  A/D conversion time tCONV 515  530 259  266 131  134 67  68 Note: Values in the table are the number of states. Table 15.4 A/D Conversion Characteristics (Scan Mode) CKS1 CKS0 Conversion Time (Number of States) 0 512 (Fixed) 0 1 256 (Fixed) 0 128 (Fixed) 1 1 64 (Fixed)

15.4.4 External Trigger Input Timing

A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to B'11 in ADCR, an external trigger is input from the ADTRG pin. A/D conversion starts when the ADST bit in ADCSR is set to 1 on the falling edge of the ADTRG pin. Other operations, in both single and scan modes, are the same as when the ADST bit has been set to 1 by software. Figure 15.6 shows the timing. Pφ ADTRG Internal trigger signal ADST A/D conversion Figure 15.6 External Trigger Input Timing

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15.5 Interrupt Source

The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. Setting the ADIE bit to 1 when the ADF bit in ADCSR is set to 1 after A/D conversion is completed enables ADI interrupt requests. The DMA controller (DMAC) can be activated by an ADI interrupt. Having the converted data read by the DMAC in response to an ADI interrupt enables continuous conversion to be achieved without imposing a load on software. Table 15.5 A/D Converter Interrupt Source Unit Abbr. Interrupt Source In terrupt Flag DMAC Activation

0 ADI0 A/D_0 conversion end ADF Possible

1 ADI1 A/D_1 conversion end ADF Possible

15.6 A/D Conversion Accuracy Definitions

This LSI's A/D conversion accuracy definitions are given below.

• Resolution The number of A/D converter digital output codes.
• Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 15.7).
• Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 (H'000) to B'0000000001 (H'001) (see figure 15.8).
• Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see figure 15.8).
• Nonlinearity error The error with respect to the ideal A/D conversion characteristic between the zero voltage and the full-scale voltage. Does not include the offset error, full-scale error, or quantization error (see figure 15.8).
• Absolute accuracy The deviation between the digital value and the analog input value. Includes the offset error, full-scale error, quantization error, and nonlinearity error.

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15.7 Usage Notes

15.7.1 Module Stop Mode Setting

Operation of the A/D converter can be disabled or enabled using the module stop control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 19, Power-Down Modes.

15.7.2 Permissible Signal Source Impedance

This LSI's analog input is designed so that the conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 kΩ or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 5 kΩ, charging may be insufficient and it may not be possible to guarantee the A/D conversion accuracy. However, if a large capacitance is provided externally for conversion in single mode, the input load will essentially comprise only the internal input resistance of 10 kΩ, and the signal source impedance is ignored. However, since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/µs or greater) (see figure 15.9). When converting a high-speed analog signal or conversion in scan mode, a low-impedance buffer should be inserted. Equivalent circuit of the A/D converter This LSI 20 pFCin = 15 pF 10 kΩ Low-pass filter C ≤ 0.1 µF Sensor output impedance R ≤ 5 kΩ Sensor input Figure 15.9 Example of Analog Input Circuit

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15.7.3 Influences on Absolute Accuracy

Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute accuracy. Be sure to make the connection to an electrically stable GND such as AVss. Care is also required to insure that digital signals on the board do not interfere with filter circuits and filter circuits do not act as antennas.

15.7.4 Setting Range of Analog Power Supply and Other Pins

If the conditions shown below are not met, the reliability of the LSI may be adversely affected.

• Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVss ≤ VAN ≤ AVcc0 and AVss ≤ VAN ≤ AVcc1.
• Relation between AVcc0, AVcc1, AVss and Vcc, Vss As the relationship between AVcc0, AVcc1, AVss and Vcc, Vss, set AVcc0 = Vcc ± 0.3 V, AVcc1 = Vcc ± 0.3 V, and AVss = Vss. If the A/D converter is not used, set AVcc0 = Vcc, AVcc1 = Vcc, and AVss = Vss.

15.7.5 Notes on Board Design

In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Digital circuitry must be isolated from the analog input pins (AN0 to AN15) and analog power supply (AVcc0 and AVcc1) by the analog ground (AVss). Also, the analog ground (AVss) should be connected at one point to a stable ground (Vss) on the board.

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15.7.6 Notes on No ise Countermeasures

A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN15) should be connected between AVcc0, AVcc1 and AVss as shown in figure 15.10. Also, the bypass capacitors connected to AVcc0 and AVcc1 and the filter capacitor connected to pins AN0 to AN15 must be connected to AVss. If a filter capacitor is connected, the input currents at pins AN0 to AN15 are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (R in), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding the circuit constants. AVCC0 and AVCC1 *1 AN0 to AN15 AVSS Notes: Values are reference values. 2. Rin: Input impedance Rin*2 100 Ω 0.1 µF 0.01 µF10 µF Figure 15.10 Example of Analog Input Protection Circuit Table 15.6 Analog Pin Specifications Item Min Max Unit Analog input capacitance  20 pF Permissible signal source impedance  5 k Ω

Rev. 3.00 Mar. 14, 2006 Page 566 of 804 REJ09B0104-0300 20 pF To A/D converterAN0 to AN15 5 kΩ Note: Values are reference values. Figure 15.11 Analog Input Pin Equivalent Circuit

15.7.7 A/D Input Hold Function in Software Standby Mode

When this LSI enters software standby mode with A/D conversion enabled, the A/D conversion are retained, and the analog current is equal to as during A/D conversion. If the analog power supply current needs to be reduced in software standby mode, clear the ADST, TRGS1, and TRGS0 bits all to 0 to disable A/D conversion.

Rev. 3.00 Mar. 14, 2006 Page 567 of 804 REJ09B0104-0300 Section 16 RAM This LSI has a 12-kbyte on-chip high-speed static RAM. The RAM is connected to the CPU by a 32-bit data bus, enabling 1-state read and 2-state write accesses by the CPU to all byte data, word data, and longword data. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR). For details on SYSCR, refer to section 3.2.2, System Control Register (SYSCR). Product Classification RAM Size RAM Addresses Flash memory version H8SX/1527 12 kbytes H'FF9000 to H'FFBFFF H8SX/1525 12 kbytes H'FF9000 to H'FFBFFF

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Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 569 of 804 REJ09B0104-0300 Section 17 Flash Memory (0.18-µm F-ZTAT Version) The flash memory has the following features. Figure 17.1 is a block diagram of the flash memory.

17.1 Features

• Size Product Classification ROM Size ROM Address H8SX/1527 R5F61527 256 kb ytes H'000000 to H'03FFFF (modes 1 to 3) H8SX/1525 R5F61525
• Two memory MATs The start addresses of two memory spaces (memory MATs) are allocated to the same address. The mode setting in the initiation determines which memory MAT is initiated first. The memory MATs can be switched by using the bank-switching method after initiation.  User MAT initiated at a power-on reset in user mode: 256 kbytes  User boot MAT is initiated at a power-on reset in user boot mode: 10 kbytes
• Programming/erasing interface by the download of on-chip program This LSI has a programming/erasing program. After downloading this program to the on-chip RAM, programming/erasing can be performed by setting the parameters.
• Programming/erasing time Programming time: 3 ms (typ) for 128-byte simultaneous programming, 23.4 µs per byte Erasing time: 1000 ms (typ) per 1 block (64 kbytes)
• Number of programming The number of programming can be up to 100 times at the minimum. (1 to 100 times are guaranteed.)
• Three on-board programming modes Boot mode: Using the on-chip SCI_4, the user MAT and user boot MAT can be programmed/erased. In boot mode, the bit rate between the host and this LSI can be adjusted automatically. User program mode: Using a desired interface, the user MAT can be programmed/erased. User boot mode: Using a desired interface, the user boot program can be made and the user MAT can be programmed/erased.
• Off-board programming mode Programmer mode: Using a PROM programmer, the user MAT and user boot MAT can be programmed/erased.

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• Programming/erasing protection Protection against programming/erasing of the flash memory can be set by hardware protection, software protection, or error protection.
• Flash memory emulation function using the on-chip RAM Realtime emulation of the flash memory programming can be performed by overlaying parts of the flash memory (user MAT) area and the on-chip RAM. FCCS FPCS FECS FKEY FMATS FTDAR RAMER Control unit Memory MAT unit Flash memory User MAT: 256 kbytes User boot MAT: 10 kbytes Operating mode Module bus Mode pins Internal data bus (32 bits) Internal address bus [Legend] FCCS: Flash code control/status register FPCS: Flash program code select register FECS: Flash erase code select register FKEY: Flash key code register FMATS: Flash MAT select register FTDAR: Flash transfer destination address register RAMER: RAM emulation register Note: To read from or write to the registers, the FLSHE bit in SYSCR must be set to 1. Figure 17.1 Block Diagram of Flash Memory

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17.2 Mode Transition Diagram

When the mode pins are set in the reset state and reset start is performed, this LSI enters each operating mode as shown in figure 17.2. Although the flash memory can be read in user mode, it cannot be programmed or erased. The flash memory can be programmed or erased in boot mode, user program mode, user boot mode, and programmer mode. The differences between boot mode, user program mode, user boot mode, and programmer mode are shown in table 17.1. Reset state Programmer mode User mode User program mode User boot mode Boot mode On-board programming mode RES = 0 RES = 0 User mode sett ing User boot mode settingRES = 0 Boot mode setting RES = 0 RES = 0 Programmer mode setting RAM emulation can be available ROM disabled mode RES = 0 ROM disabled mode setting Notes: * In this LSI, the user program mode is defined as the period from the timing when a program concerning programming and erasure is started in user mode to the timing when the program is completed. 1. Programming and erasure is started. 2. Programing and erasure is completed. Figure 17.2 Mode Transition of Flash Memory

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 572 of 804 REJ09B0104-0300 Table 17.1 Differences between Boot Mode, User Program Mode, User Boot Mode, and Programmer Mode Item Boot Mode User Program Mode User Boot Mode Programmer Mode Programming/ erasing environment On-board programming On-board programming On-board programming Off-board programming Programming/ erasing enable MAT

• User MAT
• User boot MAT
• User MAT • User MAT • User MAT
• User boot MAT Programming/ erasing control Command Programming/ erasing interface Programming/ erasing interface Command All erasure O (Automatic) O O O (Automatic) Block division erasure O O × Program data transfer From host via SCI From desired device via RAM From desired device via RAM Via programmer RAM emulation × O O × Reset initiation MAT Embedded program storage area User MAT User boot MAT * Transition to user mode Changing mode and reset Completing Programming/ erasure* Changing mode and reset Notes: 1. All-erasure is performed. Afte r that, the specified block can be erased. 2. First, the reset vector is fetched from the embedded program storage area. After the flash memory related registers are checked, the reset vector is fetched from the user boot MAT. 3. In this LSI, the user programming mode is defined as the period from the timing when a program concerning programming and erasure is started to the timing when the program is completed. For details on a program concerning programming and erasure, see section 17.8.2, User Program Mode.

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17.3 Memory MAT Configuration

The memory MATs of flash memory in this LSI consists of the 256-kbyte user MAT and 10-kbyte user boot MAT. The start addresses of the user MAT and user boot MAT are allocated to the same address. Therefore, when the program execution or data access is performed between the two memory MATs, the memory MATs must be switched by the flash MAT select register (FMATS). The user MAT or user boot MAT can be read in all modes. However, the user boot MAT can be programmed or erased only in boot mode and programmer mode. The size of the user MAT is different from that of the user boot MAT. Addresses which exceed the size of the 10-kbyte user boot MAT should not be accessed. If an attempt is made, data is read as an undefined value. User MAT User boot MAT H'000000 H'03FFFF H'000000 H'0027FF 256 kbytes 10 kbytes Figure 17.3 Memory MAT Configuration

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17.4 Block Structure

Figure 17.4 shows the block structure of the 256-kbyte user MAT. The heavy-line frames indicate the erase blocks. The thin-line frames indicate the programming units and the values inside the frames stand for the addresses. The user MAT is divided into three 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks. The user MAT can be erased in these divided block units. Programming is done in 128-byte units starting from where the lower address is H'00 or H'80. RAM emulation can be performed in the eight 4-kbyte blocks. EB0 Erase unit: 4 kbytes EB1 Erase unit: 4 kbytes EB2 Erase unit: 4 kbytes EB3 Erase unit: 4 kbytes EB4 Erase unit: 4 kbytes EB5 Erase unit: 4 kbytes EB6 Erase unit: 4 kbytes EB7 Erase unit: 4 kbytes EB8 Erase unit: 32 kbytes EB9 Erase unit: 64 kbytes H'000000 H'000001 H'000002 H'00007F H'000FFF H'00107F H'00207F H'00307F H'00407F H'004FFF H'00507F H'005FFF H'001FFF H'002FFF H'003FFF H'01FFFF H'00607F H'006FFF H'00707F H'007FFF H'00807F H'00FFFF H'01007F ← Programming unit: 128 bytes→ ← Programming unit: 128 bytes→ ← Programming unit: 128 bytes→ ← Programming unit: 128 bytes→ ← Programming unit: 128 bytes→ ← Programming unit: 128 bytes→ ← Programming unit: 128 bytes→ ← Programming unit: 128 bytes→ ← Programming unit: 128 bytes→ ← Programming unit: 128 bytes→ H'001000 H'001001 H'001002 H'002000 H'002001 H'002002 H'003000 H'003001 H'003002 H'004000 H'004001 H'004002 H'005000 H'005001 H'005002 H'006000 H'006001 H'006002 H'007000 H'007001 H'007002 H'008000 H'008001 H'008002 H'010000 H'010001 H'010002 H'000F80 H'000F81 H'000F82 H'001F80 H'001F81 H'001F82 H'002F80 H'002F81 H'002F82 H'003F80 H'003F81 H'003F82 H'004F80 H'004F81 H'004F82 H'00FF80 H'00FF81 H'00FF82 H'01FF80 H'01FF81 H'01FF82 H'005F80 H'005F81 H'005F82 H'006F80 H'006F81 H'006F82 H'007F80 H'007F81 H'007F82 EB10 EB11 Erase unit: 64 kbytes H'03FFFF H'02007F H'03007F ← Programming unit: 128 bytes→ ← Programming unit: 128 bytes→ H'020000 H'020001 H'020002 H'030000 H'030001 H'030002 H'02FF80 H'02FF81 H'02FF82 H'03FF80 H'03FF81 H'03FF82 Erase unit: 64 kbytes H'02FFFF Figure 17.4 Block Structure of User MAT

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17.5 Programming/Erasing Interface

Programming/erasing of the flash memory is done by downloading an on-chip programming/erasing program to the on-chip RAM and specifying the start address of the programming destination, the program data, and the erase block number using the programming/erasing interface registers and programming/erasing interface parameters. The procedure program for user program mode and user boot mode is made by the user. Figure 17.5 shows the procedure for creating the procedure program. For details, see section 17.8.2, User Program Mode. Download on-chip program by setting VBR, FKEY, and SCO bit in FCCS Yes No Execute initialization (downloaded program execution) Select on-chip program to be downloaded and specify destination Programming (in 128-byte units) or erasing (in 1-block units) (downloaded program execution) Start procedure program for programming/erasing End procedure program Programming/erasing completed? Figure 17.5 Procedure for Creating Procedure Program

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 576 of 804 REJ09B0104-0300 (1) Selection of On-Chip Program to be Downloaded For programming/erasing, the FLSHE bit in the system control register (SYSCR) must be set to 1 to select user program mode. This LSI has programming/erasing programs which can be downloaded to the on-chip RAM. The on-chip program to be downloaded is selected by the programming/erasing interface registers. The start address of the on-chip RAM where an on-chip program is downloaded is specified by the flash transfer destination address register (FTDAR). (2) Download of On-Chip Program The on-chip program is automatically downloaded by setting the flash key code register (FKEY) and the SCO bit in the flash code control/status register (FCCS) after initializing the vector base register (VBR). The memory MAT is replaced with the embedded program storage area during download. Since the memory MAT cannot be read during programming/erasing, the procedure program must be executed in a space other than the flash memory (for example, on-chip RAM). Since the download result is returned to the programming/erasing interface parameter, whether download is normally executed or not can be confirmed. The VBR contents can be changed after completion of download. (3) Initialization of Programming/Erasing A pulse with the specified period must be applied when programming or erasing. The specified pulse width is made by the method in which wait loop is configured by the CPU instruction. Accordingly, the operating frequency of the CPU needs to be set before programming/erasing. The operating frequency of the CPU is set by the programming/erasing interface parameter. (4) Execution of Programming/Erasing For programming/erasing, the FLSHE bit in SYSCR must be set to 1 to make a transition to user program mode. The start address of the programming destination and the program data are specified in 128-byte units when programming. The block to be erased is specified with the erase block number in erase-block units when erasing. Specifications of the start address of the programming destination, program data, and erase block number are performed by the programming/erasing interface parameters, and the on-chip program is initiated. The on-chip program is executed by using the JSR or BSR instruction and executing the subroutine call of the specified address in the on-chip RAM. The execution result is returned to the programming/erasing interface parameter. The area to be programmed must be erased in advance when programming flash memory. All interrupts are disabled during programming/erasing.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 577 of 804 REJ09B0104-0300 (5) When Programming/Erasing is Executed Consecutively When processing does not end by 128-byte programming or 1-block erasure, consecutive programming/erasing can be realized by updating the start address of the programming destination and program data, or the erase block number. Since the downloaded on-chip program is left in the on-chip RAM even after programming/erasing completes, download and initialization are not required when the same processing is executed consecutively.

17.6 Input/Output Pins

The flash memory is controlled through the input/output pins shown in table 17.2. Table 17.2 Pin Configuration Pin Name I/O Function RES Input Reset MD1 and MD0 Input Set operating mode of this LSI TxD4 Output Serial transmit data output (used in boot mode) RxD4 Input Serial receive data input (used in boot mode)

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17.7 Register Descriptions

The flash memory has the following registers. To access these registers, the FLSHE bit in the system control register (SYSCR) must be set to 1. For details on SYSCR, see section 3.2.2, System Control Register (SYSCR). Programming/Erasing Interface Registers:

• Flash code control/status register (FCCS)
• Flash program code select register (FPCS)
• Flash erase code select register (FECS)
• Flash key code register (FKEY)
• Flash MAT select register (FMATS)
• Flash transfer destination address register (FTDAR) Programming/Erasing Interface Parameters:
• Download pass and fail result parameter (DPFR)
• Flash pass and fail result parameter (FPFR)
• Flash program/erase frequency parameter (FPEFEQ)
• Flash multipurpose address area parameter (FMPAR)
• Flash multipurpose data destination area parameter (FMPDR)
• Flash erase block select parameter (FEBS)
• RAM emulation register (RAMER) There are several operating modes for accessing the flash memory. Respective operating modes, registers, and parameters are assigned to the user MAT and user boot MAT. The correspondence between operating modes and registers/parameters for use is shown in table 17.3.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 579 of 804 REJ09B0104-0300 Table 17.3 Registers/Parameters and Target Modes Register/Parameter Down- load Initiali- zation Program- ming Erasure Read RAM Emulation FKEY O  O O   FMATS   O * O * O * Programming/ erasing interface registers FPFR  O O O   Programming/ erasing interface parameters RAM emulation RAMER      O Notes: 1. The setting is required when programming or erasing the user MAT in user boot mode. 2. The setting may be required according to the combination of initiation mode and read target memory MAT.

17.7.1 Programming/Erasing Interface Registers

The programming/erasing interface registers are 8-bit registers that can be accessed only in bytes. These registers are initialized by a power-on reset. (1) Flash Code Control/Status Register (FCCS) FCCS monitors errors during programming/erasing the flash memory and requests the on-chip program to be downloaded to the on-chip RAM. R R R FLER R R SCO (R)/W R R Bit Bit Name Initial Value R/W

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 580 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description R R R Reserved These are read-only bits and cannot be modified.

4 FLER 0 R Flash Memory Error

Indicates that an error has occurred during programming or erasing the flash memory. When this bit is set to 1, the flash memory enters the error protection state. When this bit is set to 1, high voltage is applied to the internal flash memory. To reduce the damage to the flash memory, the reset must be released after the reset input period (period of RES = 0) of at least 100 µs. 0: Flash memory operates normally (Error protection is invalid) [Clearing condition]

• At a power-on reset 1: An error occurs during programming/erasing flash memory (Error protection is valid) [Setting conditions]
• When an interrupt, such as NMI, occurs during programming/erasing.
• When the flash memory is read during programming/erasing (including a vector read and an instruction fetch).
• When the SLEEP instruction is executed during programming/erasing (including software standby mode).
• When a bus master other than the CPU, such as the DMAC, obtains bus mastership during programming/erasing. 3 to 1  All 0 R Reserved These are read-only bits and cannot be modified.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 581 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description

0 SCO 0 (R)/W * Source Program Copy Operation

Requests the on-chip programming/erasing program to be downloaded to the on-chip RAM. When this bit is set to 1, the on-chip program which is selected by FPCS or FECS is automatically downloaded in the on-chip RAM area specified by FTDAR. In order to set this bit to 1, the RAM emulation mode must be canceled, H'A5 must be written to FKEY, and this operation must be executed in the on-chip RAM. Dummy read of FCCS must be executed twice immediately after setting this bit to 1. All interrupts must be disabled during download. This bit is cleared to 0 when download is completed. During program download initiated with this bit, particular processing which accompanies bank- switching of the program storage area is executed. Before a download request, initialize the VBR contents to H'00000000. After download is completed, the VBR contents can be changed. 0: Download of the programming/erasing program is not requested. [Clearing condition]

• When download is completed 1: Download of the programming/erasing program is requested. [Setting conditions] (When all of the following conditions are satisfied)
• Not in RAM emulation mode (the RAMS bit in RAMER is cleared to 0)
• H'A5 is written to FKEY
• Setting of this bit is executed in the on-chip RAM Note: * This is a write-only bit. This bit is always read as 0.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 582 of 804 REJ09B0104-0300 (2) Flash Program Code Select Register (FPCS) FPCS selects the programming program to be downloaded. R R R R R PPVS R/W R R Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description 7 to 1  All 0 R Reserved These are read-only bits and cannot be modified.

0 PPVS 0 R/W Program Pulse Verify

Selects the programming program to be downloaded. 0: Programming program is not selected. [Clearing condition] When transfer is completed 1: Programming program is selected. (3) Flash Erase Code Select Register (FECS) FECS selects the erasing program to be downloaded. R R R R R EPVB R/W R R Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description 7 to 1  All 0 R Reserved These are read-only bits and cannot be modified.

0 EPVB 0 R/W Erase Pulse Verify Block

Selects the erasing program to be downloaded. 0: Erasing program is not selected. [Clearing condition] When transfer is completed 1: Erasing program is selected.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 583 of 804 REJ09B0104-0300 (4) Flash Key Code Register (FKEY) FKEY is a register for software protection that enables to download the on-chip program and perform programming/erasing of the flash memory. R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description R/W R/W R/W R/W R/W R/W R/W R/W Key Code When H'A5 is written to FKEY, writing to the SCO bit in FCCS is enabled. When a value other than H'A5 is written, the SCO bit cannot be set to 1. Therefore, the on-chip program cannot be downloaded to the on-chip RAM. Only when H'5A is written can programming/erasing of the flash memory be executed. When a value other than H'5A is written, even if the programming/erasing program is executed, programming/erasing cannot be performed. H'A5: Writing to the SCO bit is enabled. (The SCO bit cannot be set to 1 when FKEY is a value other than H'A5.) H'5A: Programming/erasing of the flash memory is enabled. (When FKEY is a value other than H'5A, the software protection state is entered.) H'00: Initial value

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 584 of 804 REJ09B0104-0300 (5) Flash MAT Select Register (FMATS) FMATS selects the user MAT or user boot MAT. Writing to FMATS should be done when a program in the on-chip RAM is being executed. MS7 0/1* R/W MS6 R/W MS5 0/1* R/W MS4 R/W MS3 0/1* R/W MS0 R/W MS2 R/W MS1 0/1* R/W Bit Bit Name Initial Value R/W Note: * This bit is set to 1 in user boot mode, otherwise cleared to 0. Bit Bit Name Initial Value R/W Description MS7 MS6 MS5 MS4 MS3 MS2 MS1 MS0 0/1* 0/1* 0/1* 0/1* R/W R/W R/W R/W R/W R/W R/W R/W MAT Select The memory MATs can be switched by writing a value to FMATS. When H'AA is written to FMATS, the user boot MAT is selected. When a value other than H'AA is written, the user MAT is selected. Switch the MATs following the memory MAT switching procedure in section 17.11, Switching between User MAT and User Boot MAT. The user boot MAT cannot be selected by FMATS in user programming mode. The user boot MAT can be selected in boot mode or programmer mode. H'AA: The user boot MAT is selected. (The user MAT is selected when FMATS is a value other than H'AA.) (Initial value when initiated in user boot mode.) H'00: The user MAT is selected. (Initial value when initiated in a mode except for user boot mode.) Note: * This bit is set to 1 in user boot mode, otherwise cleared to 0.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 585 of 804 REJ09B0104-0300 (6) Flash Transfer Destination Address Register (FTDAR) FTDAR specifies the start address of the on-chip RAM at which to download an on-chip program. FTDAR must be set before setting the SCO bit in FCCS to 1. TDER R/W TDA6 R/W TDA5 R/W TDA4 R/W TDA3 R/W TDA0 R/W TDA2 R/W TDA1 R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description

7 TDER 0 R/W Transfer Destination Address Setting Error

This bit is set to 1 when an error has occurred in setting the start address specified by bits TDA6 to TDA0. A start address error is determined by whether the value set in bits TDA6 to TDA0 is within the range of H'00 to H'02 when download is executed by setting the SCO bit in FCCS to 1. Make sure that this bit is cleared to 0 before setting the SCO bit to 1 and the value of FTDAR to should be within the range of H'00 to H'02. 0: The value specified by bits TDA6 to TDA0 is within the range. 1: The value specified by bits TDA6 to TDA0 is between H'03 and H'FF and download has stopped. TDA6 TDA5 TDA4 TDA3 TDA2 TDA1 TDA0 R/W R/W R/W R/W R/W R/W R/W Transfer Destination Address Specifies the on-chip RAM start address of the download destination. A value between H'00 and H'02, and up to 4 kbytes can be specified as the start address of the on-chip RAM. H'00: H'FF9000 is specified as the start address. H'01: H'FFA000 is specified as the start address. H'02: H'FFB000 is specified as the start address. H'03 to H'7F: Setting prohibited. (Specifying a value from H'03 to H'7F sets the TDER bit to 1 and stops download of the on-chip program.)

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 586 of 804 REJ09B0104-0300

17.7.2 Programming/Erasing Interface Parameters

The programming/erasing interface parameters specify the operating frequency, storage place for program data, start address of programming destination, and erase block number, and exchanges the execution result. These parameters use the general registers of the CPU (ER0 and ER1) or the on-chip RAM area. The initial values of programming/erasing interface parameters are undefined at a power-on reset or a transition to software standby mode. Since registers of the CPU except for R0 are saved in the stack area during download of an on- chip program, initialization, programming, or erasing, allocate the stack area before performing these operations (the maximum stack size is 128 bytes). The return value of the processing result is written in R0. The programming/erasing interface parameters are used in download control, initialization before programming or erasing, programming, and erasing. Table 17.4 shows the usable parameters and target modes. The meaning of the bits in the flash pass and fail result parameter (FPFR) varies in initialization, programming, and erasure. Table 17.4 Parameters and Target Modes Parameter Download Initialization Programming Erasure R/W Initial Value Allocation DPFR O    R/W Undefined On-chip RAM * FPFR  O O O R/W Undefined R0L of CPU FPEFEQ  O   R/W Undefined ER0 of CPU FMPAR   O  R/W Undefined ER1 of CPU FMPDR   O  R/W Undefined ER0 of CPU FEBS    O R/W Undefined ER0 of CPU Note: * A single byte of the start address of the on-chip RAM specified by FTDAR Download Control: The on-chip program is automatically downloaded by setting the SCO bit in FCCS to 1. The on-chip RAM area to download the on-chip program is the 4-kbyte area starting from the start address specified by FTDAR. Download is set by the programming/erasing interface registers, and the download pass and fail result parameter (DPFR) indicates the return value.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 587 of 804 REJ09B0104-0300 Initialization before Programming/Erasing: The on-chip program includes the initialization program. A pulse with the specified period must be applied when programming or erasing. The specified pulse width is made by the method in which wait loop is configured by the CPU instruction. Accordingly, the operating frequency of the CPU must be set. The initial program is set as a parameter of the programming/erasing program which has been downloaded to perform these settings. Programming: When the flash memory is programmed, the start address of the programming destination on the user MAT and the program data must be passed to the programming program. The start address of the programming destination on the user MAT must be stored in general register ER1. This parameter is called the flash multipurpose address area parameter (FMPAR). The program data is always in 128-byte units. When the program data does not satisfy 128 bytes, 128-byte program data is prepared by filling the dummy code (H'FF). The boundary of the start address of the programming destination on the user MAT is aligned at an address where the lower eight bits (A7 to A0) are H'00 or H'80. The program data for the user MAT must be prepared in consecutive areas. The program data must be in a consecutive space which can be accessed using the MOV.B instruction of the CPU and is not in the flash memory space. The start address of the area that stores the data to be written in the user MAT must be set in general register ER0. This parameter is called the flash multipurpose data destination area parameter (FMPDR). For details on the programming procedure, see section 17.8.2, User Program Mode. Erasure: When the flash memory is erased, the erase block number on the user MAT must be passed to the erasing program which is downloaded. The erase block number on the user MAT must be set in general register ER0. This parameter is called the flash erase block select parameter (FEBS). One block is selected from the block numbers of 0 to 11 as the erase block number. For details on the erasing procedure, see section 17.8.2, User Program Mode.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 588 of 804 REJ09B0104-0300 (1) Download Pass and Fail Result Parameter (DPFR: Single Byte of Start Address in On- Chip RAM Specified by FTDAR) DPFR indicates the return value of the download result. The DPFR value is used to determine the download result. SF SS FK Bit Bit Name Bit Bit Name Initial Value R/W Description 7 to 3    Unused These bits return 0.

2 SS  R/W Source Select Error Detect

Only one type can be specified for the on-chip program which can be downloaded. When the program to be downloaded is not selected, more than two types of programs are selected, or a program which is not mapped is selected, an error occurs. 0: Download program selection is normal 1: Download program selection is abnormal

1 FK  R/W Flash Key Register Error Detect

Checks the FKEY value (H'A5) and returns the result. 0: FKEY setting is normal (H'A5) 1: FKEY setting is abnormal (value other than H'A5)

0 SF  R/W Success/Fail

Returns the download result. Reads back the program downloaded to the on-chip RAM and determines whether it has been transferred to the on-chip RAM. 0: Download of the program has ended normally (no error) 1: Download of the program has ended abnormally (error occurs)

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 589 of 804 REJ09B0104-0300 (2) Flash Pass and Fail Parameter (FPFR: General Register R0L of CPU) FPFR indicates the return values of the initialization, programming, and erasure results. The meaning of the bits in FPFR varies depending on the processing. (a) Initialization before programming/erasing FPFR indicates the return value of the initialization result. SF FQ Bit Bit Name Bit Bit Name Initial Value R/W Description 7 to 2    Unused These bits return 0.

1 FQ  R/W Frequency Error Detect

Compares the specified CPU operating frequency with the operating frequencies supported by this LSI, and returns the result. 0: Setting of operating frequency is normal 1: Setting of operating frequency is abnormal Returns the initialization result. 0: Initialization has ended normally (no error) 1: Initialization has ended abnormally (error occurs)

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 590 of 804 REJ09B0104-0300 (b) Programming FPFR indicates the return value of the programming result. MD EE FK SF WD WA Bit Bit Name Bit Bit Name Initial Value R/W Description 7    Unused Returns 0.

6 MD  R/W Programming Mode Related Setting Error Detect

Detects the error protection state and returns the result. When the error protection state is entered, this bit is set to 1. Whether the error protection state is entered or not can be confirmed with the FLER bit in FCCS. For conditions to enter the error protection state, see section 17.9.3, Error Protection. 0: Normal operation (FLER = 0) 1: Error protection stat e, and programming cannot be performed (FLER = 1)

5 EE  R/W Programming Execution Error Detect

Writes 1 to this bit when the specified data could not be written because the user MAT was not erased. If this bit is set to 1, there is a high possibility that the user MAT has been written to partially. In this case, after removing the error factor, erase the user MAT. If FMATS is set to H'AA and the user boot MAT is selected, an error occurs when programming is performed. In this case, both the user MAT and user boot MAT have not been written to. Programming the user boot MAT should be performed in boot mode or programmer mode. 0: Programming has ended normally 1: Programming has ended abnormally (programming result is not guaranteed)

4 FK  R/W Flash Key Register Error Detect

Checks the FKEY value (H'5A) before programming starts, and returns the result. 0: FKEY setting is normal (H'5A) 1: FKEY setting is abnormal (value other than H'5A)

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 591 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description 3    Unused Returns 0.

2 WD  R/W Write Data Address Detect

When an address not in the flash memory area is specified as the start address of the storage destination for the program data, an error occurs. 0: Setting of the star t address of the storage destination for the program data is normal 1: Setting of the star t address of the storage destination for the program data is abnormal

1 WA  R/W Write Address Error Detect

When the following items are specified as the start address of the programming destination, an error occurs.

• An area other than flash memory
• The specified address is not aligned with the 128- byte boundary (lower eight bits of the address are other than H'00 and H'80) 0: Setting of the start address of the programming destination is normal 1: Setting of the start address of the programming destination is abnormal

Returns the programming result. 0: Programming has ended normally (no error) 1: Programming has ended abnormally (error occurs)

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 592 of 804 REJ09B0104-0300 (c) Erasure FPFR indicates the return value of the erasure result. MD EE FK EB SF Bit Bit Name Bit Bit Name Initial Value R/W Description 7    Unused Returns 0.

6 MD  R/W Erasure Mode Related Setting Error Detect

Detects the error protection state and returns the result. When the error protection state is entered, this bit is set to 1. Whether the error protection state is entered or not can be confirmed with the FLER bit in FCCS. For conditions to enter the error protection state, see section 17.9.3, Error Protection. 0: Normal operation (FLER = 0) 1: Error protection stat e, and programming cannot be performed (FLER = 1)

5 EE  R/W Erasure Execution Error Detect

Returns 1 when the user MAT could not be erased or when the flash memory related register settings are partially changed. If this bit is set to 1, there is a high possibility that the user MAT has been erased partially. In this case, after removing the error factor, erase the user MAT. If FMATS is set to H'AA and the user boot MAT is selected, an error occurs when erasure is performed. In this case, both the user MAT and user boot MAT have not been erased. Erasing of the user boot MAT should be performed in boot mode or programmer mode. 0: Erasure has ended normally 1: Erasure has ended abnormally

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 593 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description Checks the FKEY value (H'5A) before erasure starts, and returns the result. 0: FKEY setting is normal (H'5A) 1: FKEY setting is abnormal (value other than H'5A)

3 EB  R/W Erase Block Select Error Detect

Checks whether the specified erase block number is in the block range of the user MAT, and returns the result. 0: Setting of erase block number is normal 1: Setting of erase block number is abnormal 2, 1    Unused These bits return 0. Indicates the erasure result. 0: Erasure has ended normally (no error) 1: Erasure has ended abnormally (error occurs)

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 594 of 804 REJ09B0104-0300 (3) Flash Program/Erase Frequency Parameter (FPEFEQ: General Register ER0 of CPU) FPEFEQ sets the operating frequency of the CPU. The CPU operating frequency available in this LSI ranges from 8 MHz to 40 MHz. Bit Bit Name Bit Bit Name F15 F14 F13 F12 F11 F10 Bit Bit Name Bit Bit Name Bit Bit Name Initial Value R/W Description 31 to 16    Unused These bits should be cleared to 0. 15 to 0 F15 to F0  R/W Frequency Set These bits set the operating frequency of the CPU. When the PLL multiplication function is used, set the multiplied frequency. The setting value must be calculated as follows: 1. The operating frequency shown in MHz units must be rounded in a number of three decimal places and be shown in a number of two decimal places. 2. The value multiplied by 100 is converted to the binary digit and is written to FPEFEQ (general register ER0). For example, when the operating frequency of the CPU is 33.000 MHz, the value is as follows: 1. The number of three decim al places of 33.000 is rounded. 2. The formula of 33.00 × 100 = 3300 is converted to the binary digit and B'0000 1100 1110 0100 (H'0CE4) is set to ER0.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 595 of 804 REJ09B0104-0300 (4) Flash Multipurpose Address Area Parameter (FMPAR: General Register ER1 of CPU) FMPAR stores the start address of the programming destination on the user MAT. When an address in an area other than the flash memory is set, or the start address of the programming destination is not aligned with the 128-byte boundary, an error occurs. The error occurrence is indicated by the WA bit in FPFR. MOA31 MOA30 MOA29 MOA28 MOA27 MOA24 MOA26 MOA25 MOA23 MOA22 MOA21 MOA20 MOA19 MOA16 MOA18 MOA17 MOA15 MOA14 MOA13 MOA12 MOA11 MOA8 MOA10 MOA9 MOA7 MOA6 MOA5 MOA4 MOA3 MOA0 MOA2 MOA1 Bit Bit Name Bit Bit Name Bit Bit Name Bit Bit Name Bit Bit Name Initial Value R/W Description 31 to 0 MOA31 to MOA0  R/W These bits store the st art address of the programming destination on the user MAT. Consecutive 128-byte programming is executed starting from the specified start address of the user MAT. Therefore, the specified start address of the programming destination becomes a 128-byte boundary, and MOA6 to MOA0 are always cleared to 0.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 596 of 804 REJ09B0104-0300 (5) Flash Multipurpose Data Destination Parameter (FMPDR: General Register ER0 of CPU) FMPDR stores the start address in the area which stores the data to be programmed in the user MAT. When the storage destination for the program data is in flash memory, an error occurs. The error occurrence is indicated by the WD bit in FPFR. MOD31 MOD30 MOD29 MOD28 MOD27 MOD24 MOD26 MOD25 MOD23 MOD22 MOD21 MOD20 MOD19 MOD16 MOD18 MOD17 MOD15 MOD14 MOD13 MOD12 MOD11 MOD8 MOD10 MOD9 MOD7 MOD6 MOD5 MOD4 MOD3 MOD0 MOD2 MOD1 Bit Bit Name Bit Bit Name Bit Bit Name Bit Bit Name Bit Bit Name Initial Value R/W Description 31 to 0 MOD31 to MOD0  R/W These bits store the st art address of the area which stores the program data for the user MAT. Consecutive 128-byte data is programmed to the user MAT starting from the specified start address.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 597 of 804 REJ09B0104-0300 (6) Flash Erase Block Select Parameter (FEBS: General Register ER0 of CPU) FEBS specifies the erase block number. Settable values for the erase block numbers range from 0 to 11 (H'00000000 to H'0000000B). A value of 0 corresponds to block EB0 and a value of 11 corresponds to block EB11. An error occurs when a value outside the range (from 0 to 11) is set. R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 598 of 804 REJ09B0104-0300

17.7.3 RAM Emulation Register (RAMER)

RAMER specifies the user MAT area overlaid with part of the on-chip RAM (H'FFA000 to H'FFAFFF) when performing emulation of programming the user MAT. RAMER should be set in user mode or user program mode. To ensure dependable emulation, the memory MAT to be emulated must not be accessed immediately after changing the RAMER contents. When accessed at such a timing, correct operation is not guaranteed. R R R R RAMS R/W RAM0 R/W RAM2 R/W RAM1 R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description 7 to 4  0 R Reserved These are read-only bits and cannot be modified.

3 RAMS 0 R/W RAM Select

Selects the function which emulates the flash memory using the on-chip RAM. 0: Disables RAM emulation function 1: Enables RAM emulation function (all blocks of the user MAT are protected against programming and erasing) RAM2 RAM1 RAM0 R/W R/W R/W Flash Memory Area Select These bits select the user MAT area overlaid with the on-chip RAM when RAMS = 1. The following areas correspond to the 4-kbyte erase blocks. 000: H'000000 to H'000FFF (EB0) 001: H'001000 to H'001FFF (EB1) 010: H'002000 to H'002FFF (EB2) 011: H'003000 to H'003FFF (EB3) 100: H'004000 to H'004FFF (EB4) 101: H'005000 to H'005FFF (EB5) 110: H'006000 to H'006FFF (EB6) 111: H'007000 to H'007FFF (EB7)

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 599 of 804 REJ09B0104-0300

17.8 On-Board Programming Mode

When the mode pins (MD0, MD1, and MD2) are set to on-board programming mode and the reset start is executed, a transition is made to on-board programming mode in which the on-chip flash memory can be programmed/erased. On-board programming mode has three operating modes: boot mode, user boot mode, and user program mode. Table 17.5 shows the pin setting for each operating mode. For details on the state transition of each operating mode for flash memory, see figure 17.2. Table 17.5 On-Board Programming Mode Setting Mode Setting MD1 MD0 User boot mode 0 1 Boot mode 1 0 User program mode 1 1

17.8.1 Boot Mode

Boot mode executes programming/erasing of the user MAT or user boot MAT by means of the control command and program data transmitted from the externally connected host via the on-chip SCI_4. In boot mode, the tool for transmitting the control command and program data, and the program data must be prepared in the host. The serial communication mode is set to asynchronous mode. The system configuration in boot mode is shown in figure 17.6. Interrupts are ignored in boot mode. Configure the user system so that interrupts do not occur. RxD4 TxD4 Software for analyzing control commands (on-chip) Flash memory On-chip RAMSCI_4 This LSI Host Programming tool and program data Control command, program data Response Figure 17.6 System Configuration in Boot Mode

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 600 of 804 REJ09B0104-0300 (1) Serial Interface Setting by Host The SCI_4 is set to asynchronous mode, and the serial transmit/receive format is set to 8-bit data, one stop bit, and no parity. When a transition to boot mode is made, the boot program embedded in this LSI is initiated. When the boot program is initiated, this LSI measures the low period of asynchronous serial communication data (H'00) transmitted consecutively by the host, calculates the bit rate, and adjusts the bit rate of the SCI_4 to match that of the host. When bit rate adjustment is completed, this LSI transmits 1 byte of H'00 to the host as the bit adjustment end sign. When the host receives this bit adjustment end sign normally, it transmits 1 byte of H'55 to this LSI. When reception is not executed normally, initiate boot mode again. The bit rate may not be adjusted within the allowable range depending on the combination of the bit rate of the host and the system clock frequency of this LSI. Therefore, the transfer bit rate of the host and the system clock frequency of this LSI must be as shown in table 17.6. D0 D1 D2 D3 D4 D5 D6 D7 Start bit Stop bit Measure low period (9 bits) (data is H'00) High period of at least 1 bit Figure 17.7 Automatic-Bit-Rate Adjustment Operation Table 17.6 System Clock Frequency for Automatic-Bit-Rate Adjustment Bit Rate of Host System Clock Frequency of This LSI External Clock Frequency 9,600 bps 8 to 18 MHz 4 to 9 MHz 19,200 bps 16 to 18 MHz 8 to 9 MHz

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 601 of 804 REJ09B0104-0300 (2) State Transition Diagram The state transition after boot mode is initiated is shown in figure 17.8. Wait for inquiry setting command Wait for programming/erasing command Bit rate adjustment Processing of read/check command Boot mode initiation (reset by boot mode) H'00, ..., H'00 reception H'00 transmission (adjustment completed) (Bit rate adjustment) Processing of inquiry setting command All user MAT and user boot MAT erasure Wait for program data Wait for erase-block data Read/check command reception Command response (Erasure selection command reception) (Program data transmission) (Erasure selection command reception) (Programming completion) (Erase-block specification) (Erasure completion) Inquiry command reception H'55 reception Inquiry command response Figure 17.8 Boot Mode State Transition Diagram

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 602 of 804 REJ09B0104-0300 1. After boot mode is initiated, the bit rate of the SCI_4 is adjusted with that of the host. 2. Inquiry information about the size, configuration, start address, and support status of the user MAT is transmitted to the host. 3. After inquiries have finished, all user MAT and user boot MAT are automatically erased. 4. When the program preparation notice is received, the state of waiting for program data is entered. The start address of the programming destination and program data must be transmitted after the programming command is transmitted. When programming is finished, the start address of the programming destination must be set to H'FFFFFFFF and transmitted. Then the state of waiting for program data is returned to the state of waiting for programming/erasing command. When the erasure preparation notice is received, the state of waiting for erase block data is entered. The erase block number must be transmitted after the erasing command is transmitted. When the erasure is finished, the erase block number must be set to H'FF and transmitted. Then the state of waiting for erase block data is returned to the state of waiting for programming/erasing command. Erasure must be executed when the specified block is programmed without a reset start after programming is executed in boot mode. When programming can be executed by only one operation, all blocks are erased before entering the state of waiting for programming/erasing command or another command. Thus, in this case, the erasing operation is not required. The commands other than the programming/erasing command perform sum check, blank check (erasure check), and memory read of the user MAT/user boot MAT and acquisition of current status information. Memory read of the user MAT/user boot MAT can only read the data programmed after all user MAT/user boot MAT has automatically been erased. No other data can be read.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 603 of 804 REJ09B0104-0300

17.8.2 User Program Mode

Programming/erasing of the user MAT is executed by downloading an on-chip program. The user boot MAT cannot be programmed/erased in user program mode. The programming/erasing flow is shown in figure 17.9. Since high voltage is applied to the internal flash memory during programming/erasing, a transition to the reset state or hardware standby mode must not be made during programming/erasing. A transition to the reset state or hardware standby mode during programming/erasing may damage the flash memory. If a reset is input, the reset must be released after the reset input period (period of RES = 0) of at least 100 µs. When programming, program data is prepared Programming/erasing procedure program is transferred to the on-chip RAM and executed Programming/erasing start Programming/erasing end Exit RAM emulation mode beforehand. Download is not allowed in emulation mode. When the program data is adjusted in emulation mode, select the download destination specified by FTDAR carefully. Make sure that the download area does not overlap the emulation area. Programming/erasing is executed only in the on-chip RAM. After programming/erasing is finished, protect the flash memory by the hardware protection. Figure 17.9 Programming/Erasing Flow

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 604 of 804 REJ09B0104-0300 (1) On-Chip RAM Address Map when Pr ogramming/Erasing is Executed Parts of the procedure program that is made by the user, like download request, programming/erasing procedure, and decision of the result, must be executed in the on-chip RAM. Since the on-chip program to be downloaded is embedded in the on-chip RAM, make sure the on- chip program and procedure program do not overlap. Figure 17.10 shows the area of the on-chip program to be downloaded. H'FFBFFF Programming/erasing program entry System use area (15 bytes) DPFR (Return value: 1 byte) FTDAR setting FTDAR setting + 32 bytes FTDAR setting + 4 kbytes FTDAR setting + 16 bytes Initialization program entry Initialization + programming program or Initialization + erasing program RAM emulation area or area that can be used by user Area that can be used by user Area to be downloaded (size: 4 kbytes) Unusable area during programming/erasing Figure 17.10 RAM Map when Programming/Erasing is Executed

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 605 of 804 REJ09B0104-0300 (2) Programming Procedure in User Program Mode The procedures for download of the on-chip program, initialization, and programming are shown in figure 17.11. Select on-chip program to be downloaded and specify download destination by FTDAR Set FKEY to H'A5 Set SCO to 1 after initializing VBR and execute download DPFR = 0? Yes No Download error processing Set the FPEFEQ parameter Yes End programming procedure program FPFR = 0? No Disable interrupts and bus master operation other than CPU Clear FKEY to 0 Programming JSR FTDAR setting + 16 Yes FPFR = 0? No Clear FKEY and programming error processing Yes Required data programming is completed? No Set FKEY to H'5A Clear FKEY to 0 10. 11. 12. 13. 14. 15. DownloadInitialization Programming Initialization JSR FTDAR setting + 32 Initialization error processing Set parameters to ER1 and ER0 (FMPAR and FMPDR) Start programming procedure program Figure 17.11 Programming Procedure in User Program Mode The procedure program must be executed in an area other than the flash memory to be programmed. Setting the SCO bit in FCCS to 1 to request download must be executed in the on- chip RAM. The area that can be executed in the steps of the procedure program (on-chip RAM and user MAT) is shown in section 17.8.4, On-Chip Program and Storable Area for Program Data. The following description assumes that the area to be programmed on the user MAT is erased and that program data is prepared in the consecutive area.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 606 of 804 REJ09B0104-0300 The program data for one programming operation is always 128 bytes. When the program data exceeds 128 bytes, the start address of the programming destination and program data parameters are updated in 128-byte units and programming is repeated. When the program data is less than 128 bytes, invalid data is filled to prepare 128-byte program data. If the invalid data to be added is H'FF, the program processing time can be shortened. 1. Select the on-chip program to be downloaded and the download destination. When the PPVS bit in FPCS is set to 1, the programming program is selected. Several programming/erasing programs cannot be selected at one time. If several programs are selected, a download error is returned to the SS bit in the DPFR parameter. The on-chip RAM start address of the download destination is specified by FTDAR. 2. Write H'A5 in FKEY. If H'A5 is not written to FKEY, the SCO bit in FCCS cannot be set to 1 to request download of the on-chip program. 3. After initializing VBR to H'00000000, set the SCO bit to 1 to execute download. To set the SCO bit to 1, all of the following conditions must be satisfied.  RAM emulation mode has been canceled.  H'A5 is written to FKEY.  Setting the SCO bit is executed in the on-chip RAM. When the SCO bit is set to 1, download is started automatically. Since the SCO bit is cleared to 0 when the procedure program is resumed, the SCO bit cannot be confirmed to be 1 in the procedure program. The download result can be confirmed by the return value of the DPFR parameter. To prevent incorrect decision, before setting the SCO bit to 1, set one byte of the on-chip RAM start address specified by FTDAR, which becomes the DPFR parameter, to a value other than the return value (e.g. H'FF). Since particular processing that is accompanied by bank switching as described below is performed when download is executed, initialize the VBR contents to H'00000000. Dummy read of FCCS must be performed twice immediately after the SCO bit is set to 1.  The user-MAT space is switched to the on-chip program storage area.  After the program to be downloaded and the on-chip RAM start address specified by FTDAR are checked, they are transferred to the on-chip RAM.  FPCS, FECS, and the SCO bit in FCCS are cleared to 0.  The return value is set in the DPFR parameter.  After the on-chip program storage area is returned to the user-MAT space, the procedure program is resumed. After that, VBR can be set again.  The values of general registers of the CPU are held.  During download, no interrupts can be accepted. However, since the interrupt requests are held, when the procedure program is resumed, the interrupts are requested.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 607 of 804 REJ09B0104-0300  To hold a level-detection interrupt request, the interrupt must continue to be input until the download is completed.  Allocate a stack area of 128 bytes at the maximum in the on-chip RAM before setting the SCO bit to 1.  If access to the flash memory is requested by the DMAC during download, the operation cannot be guaranteed. Make sure that an access request by the DMAC is not generated. 4. FKEY is cleared to H'00 for protection. 5. The download result must be confirmed by the value of the DPFR parameter. Check the value of the DPFR parameter (one byte of start address of the download destination specified by FTDAR). If the value of the DPFR parameter is H'00, download has been performed normally. If the value is not H'00, the source that caused download to fail can be investigated by the description below.  If the value of the DPFR parameter is the same as that before downloading, the setting of the start address of the download destination in FTDAR may be abnormal. In this case, confirm the setting of the TDER bit in FTDAR.  If the value of the DPFR parameter is different from that before downloading, check the SS bit or FK bit in the DPFR parameter to confirm the download program selection and FKEY setting, respectively. 6. The operating frequency of the CPU is set in the FPEFEQ parameter for initialization. The settable operating frequency of the FPEFEQ parameter ranges from 8 to 40 MHz. When the frequency is set otherwise, an error is returned to the FPFR parameter of the initialization program and initialization is not performed. For details on setting the frequency, see section 17.7.2 (3), Flash Program/Erase Frequency Parameter (FPEFEQ). 7. Initialization is executed. The initialization program is downloaded together with the programming program to the on-chip RAM. The entry point of the initialization program is at the address which is 32 bytes after #DLTOP (start address of the download destination specified by FTDAR). Call the subroutine to execute initialization by using the following steps. MOV.L #DLTOP+32,ER2 ; Set entry address to ER2 JSR @ER2 ; Call initialization routine NOP  The general registers other than ER0 and ER1 are held in the initialization program.  R0L is a return value of the FPFR parameter.  Since the stack area is used in the initialization program, a stack area of 128 bytes at the maximum must be allocated in RAM.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 608 of 804 REJ09B0104-0300  Interrupts can be accepted during execution of the initialization program. Make sure the program storage area and stack area in the on-chip RAM and register values are not overwritten. 8. The return value in the initialization program, the FPFR parameter is determined. 9. All interrupts and the use of a bus master other than the CPU are disabled during programming/erasing. The specified voltage is applied for the specified time when programming or erasing. If interrupts occur or the bus mastership is moved to other than the CPU during programming/erasing, causing a voltage exceeding the specifications to be applied, the flash memory may be damaged. Therefore, interrupts are disabled by setting bit 7 (I bit) in the condition code register (CCR) to B'1 in interrupt control mode 0 and by setting bits 2 to 0 (I2 to I0 bits) in the extend register (EXR) to B'111 in interrupt control mode 2. Accordingly, interrupts other than NMI are held and not executed. Configure the user system so that NMI interrupts do not occur. The interrupts that are held must be executed after all programming completes. When the bus mastership is moved to other than the CPU, such as to the DMAC, the error protection state is entered. Therefore, make sure the DMAC does not acquire the bus. 10. FKEY must be set to H'5A and the user MAT must be prepared for programming. 11. The parameters required for programming are set. The start address of the programming destination on the user MAT (FMPAR parameter) is set in general register ER1. The start address of the program data storage area (FMPDR parameter) is set in general register ER0.  Example of FMPAR parameter setting: When an address other than one in the user MAT area is specified for the start address of the programming destination, even if the programming program is executed, programming is not executed and an error is returned to the FPFR parameter. Since the program data for one programming operation is 128 bytes, the lower eight bits of the address must be H'00 or H'80 to be aligned with the 128-byte boundary.  Example of FMPDR parameter setting: When the storage destination for the program data is flash memory, even if the programming routine is executed, programming is not executed and an error is returned to the FPFR parameter. In this case, the program data must be transferred to the on-chip RAM and then programming must be executed.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 609 of 804 REJ09B0104-0300 12. Programming is executed. The entry point of the programming program is a the address which is 16 bytes after #DLTOP (start address of the download destination specified by FTDAR). Call the subroutine to execute programming by using the following steps. MOV.L #DLTOP+16,ER2 ; Set entry address to ER2 JSR @ER2 ; Call programming routine NOP  The general registers other than ER0 and ER1 are held in the programming program.  R0L is a return value of the FPFR parameter.  Since the stack area is used in the programming program, a stack area of 128 bytes at the maximum must be allocated in RAM. 13. The return value in the programming program, the FPFR parameter is determined. 14. Determine whether programming of the necessary data has finished. If more than 128 bytes of data are to be programmed, update the FMPAR and FMPDR parameters in 128-byte units, and repeat steps 11 to 14. Increment the programming destination address by 128 bytes and update the programming data pointer correctly. If an address which has already been programmed is written to again, not only will a programming error occur, but also flash memory will be damaged. 15. After programming finishes, clear FKEY and specify software protection. If this LSI is restarted by a reset immediately after programming has finished, secure the reset input period (period of RES = 0) of at least 100 µs.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 611 of 804 REJ09B0104-0300 The procedure program must be executed in an area other than the user MAT to be erased. Setting the SCO bit in FCCS to 1 to request download must be executed in the on-chip RAM. The area that can be executed in the steps of the procedure program (on-chip RAM and user MAT) is shown in section 17.8.4, On-Chip Program and Storable Area for Program Data. For the downloaded on-chip program area, see figure 17.10. One erasure processing erases one block. For details on block divisions, refer to figure 17.4. To erase two or more blocks, update the erase block number and repeat the erasing processing for each block. 1. Select the on-chip program to be downloaded and the download destination. When the PPVS bit in FPCS is set to 1, the programming program is selected. Several programming/erasing programs cannot be selected at one time. If several programs are selected, a download error is returned to the SS bit in the DPFR parameter. The on-chip RAM start address of the download destination is specified by FTDAR. For the procedures to be carried out after setting FKEY, see section 17.8.2 (2), Programming Procedure in User Program Mode. 2. Set the FEBS parameter necessary for erasure. Set the erase block number (FEBS parameter) of the user MAT in general register ER0. If a value other than an erase block number of the user MAT is set, no block is erased even though the erasing program is executed, and an error is returned to the FPFR parameter. 3. Erasure is executed. As in programming, the entry point of the erasing program is at the address which is 16 bytes after #DLTOP (start address of the download destination specified by FTDAR). Call the subroutine to execute erasure by using the following steps. MOV.L #DLTOP+16, ER2 ; Set entry address to ER2 JSR @ER2 ; Call erasing routine NOP

• The general registers other than ER0 and ER1 are held in the erasing program.  R0L is a return value of the FPFR parameter.  Since the stack area is used in the erasing program, a stack area of 128 bytes at the maximum must be allocated in RAM. 4. The return value in the erasing program, the FPFR parameter is determined. 5. Determine whether erasure of the necessary blocks has finished. If more than one block is to be erased, update the FEBS parameter and repeat steps 2 to 5. 6. After erasure completes, clear FKEY and specify software protection. If this LSI is restarted by a power-on reset immediately after erasure has finished, secure the reset input period (period of RES = 0) of at least 100 µs.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 613 of 804 REJ09B0104-0300 In figure 17.13, since RAM emulation is performed, the erasing/programming program is downloaded to avoid the 4-kbyte on-chip RAM area (H'FFA000 to H'FFAFFF). Download and initialization are performed only once at the beginning. Note the following when executing the procedure program.

• Be careful not to overwrite data in the on-chip RAM with overlay settings. In addition to the programming program area, erasing program area, and RAM emulation area, areas for the procedure programs, work area, and stack area are reserved in the on-chip RAM. Do not make settings that will overwrite data in these areas.
• Be sure to initialize both the programming program and erasing program. When the FPEFEQ parameter is initialized, also initialize both the erasing program and programming program. Initialization must be executed for both entry addresses: 32 bytes after #DLTOP (start address of download destination for erasing program), and 32 bytes after #DLTOP (start address of download destination for programming program).

17.8.3 User Boot Mode

Branching to a programming/erasing program prepared by the user enables user boot mode which is a user-arbitrary boot mode to be used. Only the user MAT can be programmed/erased in user boot mode. Programming/erasing of the user boot MAT is only enabled in boot mode or programmer mode. (1) Initiation in User Boot Mode When the reset start is executed with the mode pins set to user boot mode, the built-in check routine runs and checks the user MAT and user boot MAT states. While the check routine is running, NMI and all other interrupts cannot be accepted. Next, processing starts from the execution start address of the reset vector in the user boot MAT. At this point, the user boot MAT is selected (FMATS = H'AA) as the execution memory MAT. (2) User MAT Programming in User Boot Mode Figure 17.14 shows the procedure for programming the user MAT in user boot mode. The difference between the programming procedures in user program mode and user boot mode is the memory MAT switching as shown in figure 17.14. For programming the user MAT in user boot mode, additional processing made by setting FMATS is required: switching from the user boot MAT to the user MAT, and switching back to the user boot MAT after programming completes.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 614 of 804 REJ09B0104-0300 Set FKEY to H'A5 DPFR = 0 ? Yes No Download error processing Set the FPEFEQ parameter Initialization JSR FTDAR setting + 32 Yes End programming procedure program FPFR = 0 ? No Initialization error processing Disable interrupts and bus master operation other than CPU Clear FKEY to 0 Set parameter to ER0 and ER1 (FMPAR and FMPDR) Programming JSR FTDAR setting + 16 Yes FPFR = 0 ? No Yes Required data programming is completed? No Set FKEY to H'5A Clear FKEY to 0 DownloadInitialization Programming MAT switchover MAT switchover Set FMATS to value other than H'AA to select user MAT Set SCO to 1 after initializing VBR and execute download Clear FKEY and programming error processing Set FMATS to H'AA to select user boot MAT User-boot-MAT selection state User-MAT selection state User-boot-MAT selection state Note: The MAT must be switched by FMATS to perform the programming error processing in the user boot MAT. Start programming procedure program Select on-chip program to be downloaded and specify download destination by FTDAR Figure 17.14 Procedure for Programming User MAT in User Boot Mode In user boot mode, though the user boot MAT can be seen in the flash memory space, the user MAT is hidden in the background. Therefore, the user MAT and user boot MAT are switched while the user MAT is being programmed. Because the user boot MAT is hidden while the user MAT is being programmed, the procedure program must be executed in an area other than flash memory. After programming completes, switch the memory MATs again to return to the first state.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 615 of 804 REJ09B0104-0300 Memory MAT switching is enabled by setting FMATS. However note that access to a memory MAT is not allowed until memory MAT switching is completed. During memory MAT switching, the LSI is in an unstable state, e.g. if an interrupt occurs, from which memory MAT the interrupt vector is read is undetermined. Perform memory MAT switching in accordance with the description in section 17.11, Switching between User MAT and User Boot MAT. Except for memory MAT switching, the programming procedure is the same as that in user program mode. The area that can be executed in the steps of the procedure program (on-chip RAM and user MAT) is shown in section 17.8.4, On-Chip Program and Storable Area for Program Data.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 617 of 804 REJ09B0104-0300 Memory MAT switching is enabled by setting FMATS. However note that access to a memory MAT is not allowed until memory MAT switching is completed. During memory MAT switching, the LSI is in an unstable state, e.g. if an interrupt occurs, from which memory MAT the interrupt vector is read is undetermined. Perform memory MAT switching in accordance with the description in section 17.11, Switching between User MAT and User Boot MAT. Except for memory MAT switching, the erasing procedure is the same as that in user program mode. The area that can be executed in the steps of the procedure program (on-chip RAM, user MAT, and external space) is shown in section 17.8.4, On-Chip Program and Storable Area for Program Data.

17.8.4 On-Chip Program and Storable Area for Program Data

In the descriptions in this manual, the on-chip programs and program data storage areas are assumed to be in the on-chip RAM. However, they can be executed from part of the flash memory which is not to be programmed or erased as long as the following conditions are satisfied.

• The on-chip program is downloaded to and executed in the on-chip RAM specified by FTDAR. Therefore, this on-chip RAM area is not available for use.
• Since the on-chip program uses a stack area, allocate 128 bytes at the maximum as a stack area.
• Download requested by setting the SCO bit in FCCS to 1 should be executed from the on-chip RAM because it will require switching of the memory MATs.
• In an operating mode in which the external address space is not accessible, such as single-chip mode, the required procedure programs, NMI handling vector table, and NMI handling routine should be transferred to the on-chip RAM before programming/erasing starts (download result is determined).
• The flash memory is not accessible during programming/erasing. Programming/erasing is executed by the program downloaded to the on-chip RAM. Therefore, the procedure program that initiates operation, the NMI handling vector table, and the NMI handling routine should be stored in the on-chip RAM other than the flash memory.
• After programming/erasing starts, access to the flash memory should be inhibited until FKEY is cleared. The reset input state (period of RES = 0) must be set to at least 100 µs when the operating mode is changed and the reset start executed on completion of programming/erasing. Transitions to the reset state are inhibited during programming/erasing. When the reset signal is input, a reset input state (period of RES = 0) of at least 100 µs is needed before the reset signal is released.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 618 of 804 REJ09B0104-0300

• Switching of the memory MATs by FMATS should be needed when programming/erasing of the user MAT is operated in user boot mode. The program which switches the memory MATs should be executed from the on-chip RAM. For details, see section 17.11, Switching between User MAT and User Boot MAT. Make sure you know which memory MAT is currently selected when switching them.
• When the program data storage area is within the flash memory area, an error will occur even when the data stored is normal program data. Therefore, the data should be transferred to the on-chip RAM to place the address that the FMPDR parameter indicates in an area other than the flash memory. In consideration of these conditions, the areas in which the program data can be stored and executed are determined by the combination of the processing contents, operating mode, and bank structure of the memory MATs, as shown in tables 17.7 to 17.11. Table 17.7 Executable Memory MAT Operating Mode Processing Contents User Pr ogram Mode User Boot Mode * Programming See table 17.8 See table 17.10 Erasing See table 17. 9 See table 17.11 Note: * Programming/Erasing is possible to the user MAT.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 619 of 804 REJ09B0104-0300 Table 17.8 Usable Area for Programming in User Program Mode Storable/Executable Area Selected MAT Item On-Chip RAM User MAT User MAT Embedded Program Storage MAT Storage area for program data O ×*   Operation for selecting on-chip program to be downloaded O O O Operation for writing H'A5 to FKEY O O O Execution of writing 1 to SCO bit in FCCS (download) O × O Operation for clearing FKEY O O O Decision of download result O O O Operation for download error O O O Operation for setting initialization parameter O O O Execution of initialization O × O Decision of initialization result O O O Operation for initialization error O O O NMI handling routine O × O Operation for disabling interrupts O O O Operation for writing H'5A to FKEY O O O Operation for setting programming parameter O × O Execution of programming O × O Decision of programming result O × O Operation for programming error O × O Operation for clearing FKEY O × O Note: * Transferring the program data to the on-chip RAM beforehand enables this area to be used.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 620 of 804 REJ09B0104-0300 Table 17.9 Usable Area for Erasure in User Program Mode Storable/Executable Area Selected MAT Item On-Chip RAM User MAT User MAT Embedded Program Storage MAT Operation for selecting on-chip program to be downloaded O O O Operation for writing H'A5 to FKEY O O O Execution of writing 1 to SCO bit in FCCS (download) O × O Operation for clearing FKEY O O O Decision of download result O O O Operation for download error O O O Operation for setting initialization parameter O O O Execution of initialization O × O Decision of initialization result O O O Operation for initialization error O O O NMI handling routine O × O Operation for disabling interrupts O O O Operation for writing H'5A to FKEY O O O Operation for setting erasure parameter O × O Execution of erasure O × O Decision of erasure result O × O Operation for erasure error O × O Operation for clearing FKEY O × O

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 621 of 804 REJ09B0104-0300 Table 17.10 Usable Area for Programming in User Boot Mode Storable/Executable Area Selected MAT Item On-Chip RAM User Boot MAT User MAT User Boot MAT Embedded Program Storage MAT Storage area for program data O ×*    Operation for selecting on-chip program to be downloaded O O O Operation for writing H'A5 to FKEY O O O Execution of writing 1 to SCO bit in FCCS (download) O × O Operation for clearing FKEY O O O Decision of download result O O O Operation for download error O O O Operation for setting initialization parameter O O O Execution of initialization O × O Decision of initialization result O O O Operation for initialization error O O O NMI handling routine O × O Operation for disabling interrupts O O O Switching memory MATs by FMATS O × O Operation for writing H'5A to FKEY O × O Operation for setting programming parameter O × O Execution of programming O × O Decision of programming result O × O Operation for programming error O ×* O Operation for clearing FKEY O × O Switching memory MATs by FMATS O × O Notes: 1. Transferring the program data to the on-chip RAM beforehand enables this area to be used. 2. Switching memory MATs by FMATS by a program in the on-chip RAM enables this area to be used.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 622 of 804 REJ09B0104-0300 Table 17.11 Usable Area for Erasure in User Boot Mode Storable/Executable Area Selected MAT Item On-Chip RAM User Boot MAT User MAT User Boot MAT Embedded Program Storage MAT Operation for selecting on-chip program to be downloaded O O O Operation for writing H'A5 to FKEY O O O Execution of writing 1 to SCO bit in FCCS (download) O × O Operation for clearing FKEY O O O Decision of download result O O O Operation for download error O O O Operation for setting initialization parameter O O O Execution of initialization O × O Decision of initialization result O O O Operation for initialization error O O O NMI handling routine O × O Operation for disabling interrupts O O O Switching memory MATs by FMATS O × O Operation for writing H'5A to FKEY O × O Operation for setting erasure parameter O × O Execution of erasure O × O Decision of erasure result O × O Operation for erasure error O ×* O Operation for clearing FKEY O × O Switching memory MATs by FMATS O × O Note: Switching memory MATs by FMATS by a pr ogram in the on-chip RAM enables this area to be used.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 623 of 804 REJ09B0104-0300

17.9 Protection

There are three types of protection against the flash memory programming/erasing: hardware protection, software protection, and error protection.

17.9.1 Hardware Protection

Programming and erasure of the flash memory is forcibly disabled or suspended by hardware protection. In this state, download of an on-chip program and initialization are possible. However, programming or erasure of the user MAT cannot be performed even if the programming/erasing program is initiated, and the error in programming/erasing is indicated by the FPFR parameter. Table 17.12 Hardware Protection Function to be Protected Item Reset protection • The programming/erasing interface registers are initialized in the reset state (including a reset by the WDT) and the programming/erasing protection state is entered.

• The reset state will not be entered by a reset using the RES pin unless the RES pin is held low until oscillation has settled after a power is initially supplied. In the case of a reset during operation, hold the RES pin low for the RES pulse width given in the AC characteristics. If a reset is input during programming or erasure, data in the flash memory is not guaranteed. In this case, execute erasure and then execute programming again. O O

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 624 of 804 REJ09B0104-0300

17.9.2 Software Protection

The software protection protects the flash memory against programming/erasing by disabling download of the programming/erasing program, using the key code, and by the RAMER setting. Table 17.13 Software Protection Function to be Protected Item The programming/erasing protection state is entered when the SCO bit in FCCS is cleared to 0 to disable download of the programming/erasing programs. O O Protection by FKEY The programming/erasing protection state is entered because download and programming/erasing are disabled unless the required key code is written in FKEY. O O Emulation protection The programming/erasing protection state is entered when the RAMS bit in the RAM emulation register (RAMER) is set to 1. O O

17.9.3 Error Protection

Error protection is a mechanism for aborting programming or erasure when a CPU runaway occurs or operations not according to the programming/erasing procedures are detected during programming/erasing of the flash memory. Aborting programming or erasure in such cases prevents damage to the flash memory due to excessive programming or erasing. If an error occurs during programming/erasing of the flash memory, the FLER bit in FCCS is set to 1 and the error protection state is entered.

• When an interrupt request, such as NMI, occurs during programming/erasing.
• When the flash memory is read from during programming/erasing (including a vector read or an instruction fetch).
• When a SLEEP instruction is executed (including software-standby mode) during programming/erasing.
• When a bus master other than the CPU, such as the DMAC, obtains bus mastership during programming/erasing.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 625 of 804 REJ09B0104-0300 Error protection is canceled by a reset. Note that the reset should be released after the reset input period of at least 100 µs has passed. Since high voltages are applied during programming/erasing of the flash memory, some voltage may remain after the error protection state has been entered. For this reason, it is necessary to reduce the risk of damaging the flash memory by extending the reset input period so that the charge is released. The state-transition diagram in figure 17.16 shows transitions to and from the error protection state. Reset (hardware protection)Programming/erasing mode Error-protection mode Error-protection mode (software standby) Read disabled Programming/erasing enabled FLER = 0 Read disabled Programming/erasing disabled FLER = 0 Read enabled Programming/erasing disabled FLER = 1 Read disabled Programming/erasing disabled FLER = 1 RES = 0 Error occurrence Error occ urred (Software stand by) RES = 0 Software standby mode Cancel software standby mode RES = 0 Programming/erasing interface register is in its initial state. Programming/erasing interface register is in its initial state. Figure 17.16 Transitions to Error Protection State

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 626 of 804 REJ09B0104-0300

17.10 Flash Memory Emulation Using RAM

For realtime emulation of the data written to the flash memory using the on-chip RAM, the on- chip RAM area can be overlaid with several flash memory blocks (user MAT) using the RAM emulation register (RAMER). The overlaid area can be accessed from both the user MAT area specified by RAMER and the overlaid RAM area. The emulation can be performed in user mode and user program mode. Figure 17.17 shows an example of emulating realtime programming of the user MAT. Note: To emulate the flash memory using the RAM, set the RAME bit in the system control register (SYSCR) to 1. Emulation program start Set RAMER Write tuning data to overlaid RAM area Execute application program Tuning OK? Cancel setting in RAMER Program emulation block in user MAT Emulation program end Ye s No Figure 17.17 RAM Emulation Flow

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 628 of 804 REJ09B0104-0300 Flash memory user MAT EB8 to EB11 Download area Tuned data area Area for programming/ erasing program etc. H'00000 H'01000 H'02000 H'03000 H'04000 H'05000 H'06000 H'07000 H'08000 H'3FFFF Specified by FTDAR H'FFA000 H'FFB000 H'FFAFFF H'FFBFFF EB0 EB1 EB2 EB3 EB4 EB5 EB6 EB7 (1) Exit RAM emulation mode. (2) Transfer user-created programming/erasing procedure program. (3) Download the on-chip programming/erasing program to the area specified by FTDAR. FTDAR setting should avoid the tuned data area. (4) Program after erasing, if necessary. Figure 17.19 Programming Tuned Data 1. After tuning program data is completed, clear the RAMS bit in RAMER to 0 to cancel the overlaid RAM. 2. Transfer the user-created procedure program to the on-chip RAM. 3. Start the procedure program and download the on-chip program to the on-chip RAM. The start address of the download destination should be specified by FTDAR so that the tuned data area does not overlay the download area. 4. When block EB0 of the user MAT has not been erased, the programming program must be downloaded after block EB0 is erased. Specify the tuned data saved in the FMPAR and FMPDR parameters and then execute programming. Note: Setting the RAMS bit to 1 makes all the blocks of the user MAT enter the programming/erasing protection state (emulation protection state) regardless of the setting of the RAM2 to RAM0 bits. Under this condition, the on-chip program cannot be downloaded. When data is to be actually programmed and erased, clear the RAMS bit to 0.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 629 of 804 REJ09B0104-0300

17.11 Switching between User MAT and User Boot MAT

It is possible to switch between the user MAT and user boot MAT. However, the following procedure is required because the start addresses of these MATs are allocated to the same address. Switching to the user boot MAT disables programming and erasing. Programming of the user boot MAT should take place in boot mode or programmer mode. 1. Memory MAT switching by FMATS should always be executed from the on-chip RAM. 2. When accessing the memory MAT immediately after switching the memory MATs by FMATS from the on-chip RAM, similarly execute the NOP instruction in the on-chip RAM for eight times (this prevents access to the flash memory during memory MAT switching). 3. If an interrupt request has occurred during memory MAT switching, there is no guarantee of which memory MAT is accessed. Always mask the maskable interrupts before switching memory MATs. In addition, configure the system so that NMI interrupts do not occur during memory MAT switching. 4. After the memory MATs have been switched, take care because the interrupt vector table will also have been switched. If interrupt processing is to be the same before and after memory MAT switching, transfer the interrupt processing routines to the on-chip RAM and specify VBR to place the interrupt vector table in the on-chip RAM. 5. Memory sizes of the user MAT and user boot MAT are different. When accessing the user boot MAT, do not access addresses which exceed the 10-kbyte memory space. If an access is equal to or greater than 10 kbytes, the read values are undefined. <User MAT> <On-chip RAM> <User boot MAT> Procedure for switching to the user boot MAT 1. Inhibit interrupts (mask). 2. Write H'AA to FMATS *. 3. Before access to the user boot MAT, execute the NOP instruction for eight times. Procedure for switching to the user MAT 1. Inhibit interrupts (mask). 2. Write other than H'AA to FMATS *. 3. Before access to the user MAT, execute the NOP instruction for eight times. Procedure for switching to user boot MAT Procedure for switching to user MAT Note: * Set the FLSHE bit in the system control register (SYSCR) to 1 when making access to FMATS. Figure 17.20 Switching between User MAT and User Boot MAT

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 630 of 804 REJ09B0104-0300

17.12 Programmer Mode

Along with its on-board programming mode, this LSI also has a programmer mode as a further mode for the writing and erasing of programs and data. In programmer mode, a general-purpose PROM programmer that supports the device types shown in table 17.14 can be used to write programs to the on-chip ROM without any limitation. Table 17.14 Device Types Supported in Programmer Mode Target Memory MAT Size Device Type User MAT 256 kbytes FZTAT256V5A User boot MAT 10 kbytes FZTATUSBTV5A

17.13 Standard Serial Communication Interface Specifications for Boot

The boot program initiated in boot mode performs serial communication using the host and on- chip SCI_4. The serial communication interface specifications are shown below. The boot program has three states. 1. Bit-rate-adjustment state In this state, the boot program adjusts the bit rate to achieve serial communication with the host. Initiating boot mode enables starting of the boot program and entry to the bit-rate- adjustment state. The program receives the command from the host to adjust the bit rate. After adjusting the bit rate, the program enters the inquiry/selection state. 2. Inquiry/selection state In this state, the boot program responds to inquiry commands from the host. The device name, clock mode, and bit rate are selected. After selection of these settings, the program is made to enter the programming/erasing state by the command for a transition to the programming/erasing state. The program transfers the libraries required for erasure to the on- chip RAM and erases the user MATs and user boot MATs before the transition. 3. Programming/erasing state Programming and erasure by the boot program take place in this state. The boot program is made to transfer the programming/erasing programs to the on-chip RAM by commands from the host. Sum checks and blank checks are executed by sending these commands from the host.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 631 of 804 REJ09B0104-0300 These boot program states are shown in figure 17.21. Transition to programming/erasing Programming/erasing wait Checking Inquiry Response ErasingProgramming Reset Bit-rate-adjustment state Operations for erasing user MATs and user boot MATs Operations for inquiry and selection Operations for programming Operations for checking Operations for erasing Operations for response Inquiry/response wait Figure 17.21 Boot Program States

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 632 of 804 REJ09B0104-0300 (1) Bit-Rate-Adjustment State The bit rate is calculated by measuring the period of transfer of a low-level byte (H'00) from the host. The bit rate can be changed by the command for a new bit rate selection. After the bit rate has been adjusted, the boot program enters the inquiry and selection state. The bit-rate-adjustment sequence is shown in figure 17.22. Host Boot program H'00 (30 times maximum) H'E6 (boot response) Measuring the 1-bit length H'00 (completion of adjustment) H'55 (H'FF (error)) Figure 17.22 Bit-Rate-Adjustment Sequence (2) Communications Protocol After adjustment of the bit rate, the protocol for serial communications between the host and the boot program is as shown below. 1. One-byte commands and one-byte responses These one-byte commands and one-byte responses consist of the inquiries and the ACK for successful completion. 2. n-byte commands or n-byte responses These commands and responses are comprised of n bytes of data. These are selections and responses to inquiries. The program data size is not included under this heading because it is determined in another command. 3. Error response The error response is a response to inquiries. It consists of an error response and an error code and comes two bytes. 4. Programming of 128 bytes The size is not specified in commands. The size of n is indicated in response to the programming unit inquiry.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 633 of 804 REJ09B0104-0300 5. Memory read response This response consists of four bytes of data. Command or response Size Data Checksum Error response Error code Command or response Error response n-byte Command or n-byte response One-byte command or one-byte response Address Command Data (n bytes) Checksum 128-byte programming Size Response Data Checksum Memory read response Figure 17.23 Communication Protocol Format

• Command (one byte): Commands including inquiries, selection, programming, erasing, and checking
• Response (one byte): Response to an inquiry
• Size (one byte): The amount of data for transmission excluding the command, amount of data, and checksum
• Checksum (one byte): The checksum is calculated so that the total of all values from the command byte to the SUM byte becomes H'00.
• Data (n bytes): Detailed data of a command or response
• Error response (one byte): Error response to a command
• Error code (one byte): Type of the error
• Address (four bytes): Address for programming
• Data (n bytes): Data to be programmed (the size is indicated in the response to the programming unit inquiry.)
• Size (four bytes): Four-byte response to a memory read

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 634 of 804 REJ09B0104-0300 (3) Inquiry and Selection States The boot program returns information from the flash memory in response to the host's inquiry commands and sets the device code, clock mode, and bit rate in response to the host's selection command. Table 17.15 lists the inquiry and selection commands. Table 17.15 Inquiry and Selection Commands Command Command Name Description H'20 Supported device inquiry Inquiry regarding device codes H'10 Device selection Sele ction of device code H'21 Clock mode inquiry Inquiry regarding numbers of clock modes and values of each mode H'11 Clock mode selection Indication of the selected clock mode H'22 Multiplication ratio inquiry I nquiry regarding the number of frequency- multiplied clock types, the number of multiplication ratios, and the values of each multiple H'23 Operating clock frequency inquiry I nquiry regarding the maximum and minimum values of the main clock and peripheral clocks H'24 User boot MAT information inquiry Inquiry regarding the number of user boot MATs and the start and last addresses of each MAT H'25 User MAT information inquiry Inquiry regarding the a number of user MATs and the start and last addresses of each MAT H'26 Block for erasing information Inquiry Inquiry regarding the number of blocks and the start and last addresses of each block H'27 Programming unit inquiry Inquiry re garding the unit of program data H'3F New bit rate selection Selection of new bit rate H'40 Transition to programming/erasing state Erasing of user MAT and user boot MAT, and entry to programming/erasing state H'4F Boot program status inquiry Inquiry into the oper ated status of the boot program

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 635 of 804 REJ09B0104-0300 The selection commands, which are device selection (H'10), clock mode selection (H'11), and new bit rate selection (H'3F), should be sent from the host in that order. When two or more selection commands are sent at once, the last command will be valid. All of these commands, except for the boot program status inquiry command (H'4F), will be valid until the boot program receives the programming/erasing transition (H'40). The host can choose the needed commands and make inquiries while the above commands are being transmitted. H'4F is valid even after the boot program has received H'40. (a) Supported Device Inquiry The boot program will return the device codes of supported devices and the product code in response to the supported device inquiry. Command H'20

• Command, H'20, (one byte): Inquiry regarding supported devices Response H'30 Size Number of devices Number of characters Device code Product name
• ·· SUM
• Response, H'30, (one byte): Response to the supported device inquiry
• Size (one byte): Number of bytes to be transmitted, excluding the command, size, and checksum, that is, the amount of data contributes by the number of devices, characters, device codes and product names
• Number of devices (one byte): The number of device types supported by the boot program
• Number of characters (one byte): The number of characters in the device codes and boot program's name
• Device code (four bytes): ASCII code of the supporting product
• Product name (n bytes): Type name of the boot program in ASCII-coded characters
• SUM (one byte): Checksum The checksum is calculated so that the total number of all values from the command byte to the SUM byte becomes H'00.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 636 of 804 REJ09B0104-0300 (b) Device Selection The boot program will set the supported device to the specified device code. The program will return the selected device code in response to the inquiry after this setting has been made. Command H'10 Size Device code SUM

• Command, H'10, (one byte): Device selection
• Size (one byte): Amount of device-code data This is fixed at 4.
• Device code (four bytes): Device code (ASCII code) returned in response to the supported device inquiry
• SUM (one byte): Checksum Response H'06
• Response, H'06, (one byte): Response to the device selection command ACK will be returned when the device code matches. Error response H'90 ERROR
• Error response, H'90, (one byte): Error response to the device selection command
• ERROR : (one byte): Error code H'11: Sum check error H'21: Device code error, that is, the device code does not match (c) Clock Mode Inquiry The boot program will return the supported clock modes in response to the clock mode inquiry. Command H'21
• Command, H'21, (one byte): Inquiry regarding clock mode Response H'31 Size Number of modes Mode ··· SUM
• Response, H'31, (one byte): Response to the clock-mode inquiry
• Size (one byte): Amount of data that represents the number of modes and modes
• Number of clock modes (one byte): The number of supported clock modes H'00 indicates no clock mode or the device allows to read the clock mode.
• Mode (one byte): Values of the supported clock modes (i.e. H'01 means clock mode 1.)
• SUM (one byte): Checksum

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 637 of 804 REJ09B0104-0300 (d) Clock Mode Selection The boot program will set the specified clock mode. The program will return the selected clock- mode information after this setting has been made. The clock-mode selection command should be sent after the device-selection commands. Command H'11 Size Mode SUM

• Command, H'11, (one byte): Selection of clock mode
• Size (one byte): Amount of data that represents the modes
• Mode (one byte): A clock mode returned in reply to the supported clock mode inquiry.
• SUM (one byte): Checksum Response H'06
• Response, H'06, (one byte): Response to the clock mode selection command ACK will be returned when the clock mode matches. Error Response H'91 ERROR
• Error response, H'91, (one byte) : Error response to the clock mode selection command
• ERROR : (one byte): Error code H'11: Checksum error H'22: Clock mode error, that is, the clock mode does not match. Even if the clock mode numbers are H'00 and H'01 by a clock mode inquiry, the clock mode must be selected using these respective values.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 638 of 804 REJ09B0104-0300 (e) Multiplication Ratio Inquiry The boot program will return the supported multiplication and division ratios. Command H'22

• Command, H'22, (one byte): Inquiry regarding multiplication ratio Response H'32 Size Number of types Number of multiplication ratios Multiplica- tion ratio
• ··
• ·· SUM
• Response, H'32, (one byte): Response to the multiplication ratio inquiry
• Size (one byte): The amount of data that represents the number of clock sources and multiplication ratios and the multiplication ratios
• Number of types (one byte): The number of supported multiplied clock types (e.g. when there are two multiplied clock types, which are the main and peripheral clocks, the number of types will be H'02.)
• Number of multiplication ratios (one byte): The number of multiplication ratios for each type (e.g. the number of multiplication ratios to which the main clock can be set and the peripheral clock can be set.)
• Multiplication ratio (one byte) Multiplication ratio: The value of the multiplication ratio (e.g. when the clock-frequency multiplier is four, the value of multiplication ratio will be H'04.) Division ratio: The inverse of the division ratio, i.e. a negative number (e.g. when the clock is divided by two, the value of division ratio will be H'FE. H'FE = D'-2) The number of multiplication ratios returned is the same as the number of multiplication ratios and as many groups of data are returned as there are types.
• SUM (one byte): Checksum

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 639 of 804 REJ09B0104-0300 (f) Operating Clock Frequency Inquiry The boot program will return the number of operating clock frequencies, and the maximum and minimum values. Command H'23

• Command, H'23, (one byte): Inquiry regarding operating clock frequencies Response H'33 Size Number of operating clock frequencies Minimum value of operating clock frequency Maximum value of operating clock frequency
• ·· SUM
• Response, H'33, (one byte): Response to operating clock frequency inquiry
• Size (one byte): The number of bytes that represents the minimum values, maximum values, and the number of frequencies.
• Number of operating clock frequencies (one byte): The number of supported operating clock frequency types (e.g. when there are two operating clock frequency types, which are the main and peripheral clocks, the number of types will be H'02.)
• Minimum value of operating clock frequency (two bytes): The minimum value of the multiplied or divided clock frequency. The minimum and maximum values of the operating clock frequency represent the values in MHz, valid to the hundredths place of MHz, and multiplied by 100. (e.g. when the value is 17.00 MHz, it will be 2000, which is H'07D0.)
• Maximum value (two bytes): Maximum value among the multiplied or divided clock frequencies. There are as many pairs of minimum and maximum values as there are operating clock frequencies.
• SUM (one byte): Checksum

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 640 of 804 REJ09B0104-0300 (g) User Boot MAT Information Inquiry The boot program will return the number of user boot MATs and their addresses. Command H'24

• Command, H'24, (one byte): Inquiry regarding user boot MAT information Response H'34 Size Number of areas Area-start address Area-last address
• ·· SUM
• Response, H'34, (one byte): Response to user boot MAT information inquiry
• Size (one byte): The number of bytes that represents the number of areas, area-start addresses, and area-last address
• Number of Areas (one byte): The number of consecutive user boot MAT areas When user boot MAT areas are consecutive, the number of areas returned is H'01.
• Area-start address (four byte): Start address of the area
• Area-last address (four byte): Last address of the area There are as many groups of data representing the start and last addresses as there are areas.
• SUM (one byte): Checksum (h) User MAT Information Inquiry The boot program will return the number of user MATs and their addresses. Command H'25
• Command, H'25, (one byte): Inquiry regarding user MAT information Response H'35 Size Number of areas Start address area Last address area
• ·· SUM
• Response, H'35, (one byte): Response to the user MAT information inquiry
• Size (one byte): The number of bytes that represents the number of areas, area-start address and area-last address
• Number of areas (one byte): The number of consecutive user MAT areas When the user MAT areas are consecutive, the number of areas is H'01.
• Area-start address (four bytes): Start address of the area

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 641 of 804 REJ09B0104-0300

• Area-last address (four bytes): Last address of the area There are as many groups of data representing the start and last addresses as there are areas.
• SUM (one byte): Checksum (i) Erased Block Information Inquiry The boot program will return the number of erased blocks and their addresses. Command H'26
• Command, H'26, (two bytes): Inquiry regarding erased block information Response H'36 Size Number of blocks Block start address Block last address
• ·· SUM
• Response, H'36, (one byte): Response to the number of erased blocks and addresses
• Size (three bytes): The number of bytes that represents the number of blocks, block-start addresses, and block-last addresses.
• Number of blocks (one byte): The number of erased blocks
• Block start address (four bytes): Start address of a block
• Block last Address (four bytes): Last address of a block There are as many groups of data representing the start and last addresses as there are areas.
• SUM (one byte): Checksum (j) Programming Unit Inquiry The boot program will return the programming unit used to program data. Command H'27
• Command, H'27, (one byte): Inquiry regarding programming unit Response H'37 Size Programming unit SUM
• Response, H'37, (one byte): Response to programming unit inquiry
• Size (one byte): The number of bytes that indicate the programming unit, which is fixed to 2
• Programming unit (two bytes): A unit for programming This is the unit for reception of programming.
• SUM (one byte): Checksum

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 642 of 804 REJ09B0104-0300 (k) New Bit-Rate Selection The boot program will set a new bit rate and return the new bit rate. This selection should be sent after sending the clock mode selection command. Command H'3F Size Bit rate Input frequency Number of multiplication ratios Multiplication ratio 1 Multiplication ratio 2 SUM

• Command, H'3F, (one byte): Selection of new bit rate
• Size (one byte): The number of bytes that represents the bit rate, input frequency, number of multiplication ratios, and multiplication ratio
• Bit rate (two bytes): New bit rate One hundredth of the value (e.g. when the value is 19200 bps, it will be 192, which is H'00C0.)
• Input frequency (two bytes): Frequency of the clock input to the boot program This is valid to the hundredths place and represents the value in MHz multiplied by 100. (E.g. when the value is 20.00 MHz, it will be 2000, which is H'07D0.)
• Number of multiplication ratios (one byte): The number of multiplication ratios to which the device can be set.
• Multiplication ratio 1 (one byte) : The value of multiplication or division ratios for the main operating frequency Multiplication ratio (one byte): The value of the multiplication ratio (e.g. when the clock frequency is multiplied by four, the multiplication ratio will be H'04.) Division ratio: The inverse of the division ratio, as a negative number (e.g. when the clock frequency is divided by two, the value of division ratio will be H'FE. H'FE = D'-2)
• Multiplication ratio 2 (one byte): The value of multiplication or division ratios for the peripheral frequency Multiplication ratio (one byte): The value of the multiplication ratio (e.g. when the clock frequency is multiplied by four, the multiplication ratio will be H'04.) (Division ratio: The inverse of the division ratio, as a negative number (E.g. when the clock is divided by two, the value of division ratio will be H'FE. H'FE = D'-2)
• SUM (one byte): Checksum Response H'06
• Response, H'06, (one byte): Response to selection of a new bit rate When it is possible to set the bit rate, the response will be ACK.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 643 of 804 REJ09B0104-0300 Error Response H'BF ERROR

• Error response, H'BF, (one byte): Error response to selection of new bit rate
• ERROR: (one byte): Error code H'11: Sum checking error H'24: Bit-rate selection error The rate is not available. H'25: Error in input frequency This input frequency is not within the specified range. H'26: Multiplication-ratio error The ratio does not match an available ratio. H'27: Operating frequency error The frequency is not within the specified range. (4) Receive Data Check The methods for checking of receive data are listed below. 1. Input frequency The received value of the input frequency is checked to ensure that it is within the range of minimum to maximum frequencies which matches the clock modes of the specified device. When the value is out of this range, an input-frequency error is generated. 2. Multiplication ratio The received value of the multiplication ratio or division ratio is checked to ensure that it matches the clock modes of the specified device. When the value is out of this range, an input- frequency error is generated. 3. Operating frequency Operating frequency is calculated from the received value of the input frequency and the multiplication or division ratio. The input frequency is input to the LSI and the LSI is operated at the operating frequency. The expression is given below. Operating frequency = Input frequency × Multiplication ratio, or Operating frequency = Input frequency ÷ Division ratio The calculated operating frequency should be checked to ensure that it is within the range of minimum to maximum frequencies which are available with the clock modes of the specified device. When it is out of this range, an operating frequency error is generated. 4. Bit rate

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 644 of 804 REJ09B0104-0300 To facilitate error checking, the value (n) of clock select (CKS) in the serial mode register (SMR), and the value (N) in the bit rate register (BRR), which are found from the peripheral operating clock frequency (φ) and bit rate (B), are used to calculate the error rate to ensure that it is less than 4%. If the error is more than 4%, a bit rate error is generated. The error is calculated using the following expression: φ × 106 When the new bit rate is selectable, the rate will be set in the register after sending ACK in response. The host will send an ACK with the new bit rate for confirmation and the boot program will response with that rate. Confirmation H'06

• Confirmation, H'06, (one byte): Confirmation of a new bit rate Response H'06
• Response, H'06, (one byte): Response to confirmation of a new bit rate The sequence of new bit-rate selection is shown in figure 17.24. Host Boot program Setting a new bit rate H'06 (ACK) Waiting for one-bit period at the specified bit rate H'06 (ACK) with the new bit rate H'06 (ACK) with the new bit rate Setting a new bit rate Setting a new bit rate Figure 17.24 New Bit-Rate Selection Sequence

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 645 of 804 REJ09B0104-0300 (5) Transition to Programming/Erasing State The boot program will transfer the erasing program, and erase the user MATs and user boot MATs in that order. On completion of this erasure, ACK will be returned and will enter the programming/erasing state. The host should select the device code, clock mode, and new bit rate with device selection, clock- mode selection, and new bit-rate selection commands, and then send the command for the transition to programming/erasing state. These procedures should be carried out before sending of the programming selection command or program data. Command H'40

• Command, H'40, (one byte): Transition to programming/erasing state Response H'06
• Response, H'06, (one byte): Response to transition to programming/erasing state The boot program will send ACK when the user MAT and user boot MAT have been erased by the transferred erasing program. Error Response H'C0 H'51
• Error response, H'C0, (one byte): Error response for user boot MAT blank check
• Error code, H'51, (one byte): Erasing error An error occurred and erasure was not completed. (6) Command Error A command error will occur when a command is undefined, the order of commands is incorrect, or a command is unacceptable. Issuing a clock-mode selection command before a device selection or an inquiry command after the transition to programming/erasing state command, are examples. Error Response H'80 H'xx
• Error response, H'80, (one byte): Command error
• Command, H'xx, (one byte): Received command

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 646 of 804 REJ09B0104-0300 (7) Command Order The order for commands in the inquiry selection state is shown below. 1. A supported device inquiry (H'20) should be made to inquire about the supported devices. 2. The device should be selected from among those described by the returned information and set with a device-selection (H'10) command. 3. A clock-mode inquiry (H'21) should be made to inquire about the supported clock modes. 4. The clock mode should be selected from among those described by the returned information and set. 5. After selection of the device and clock mode, inquiries for other required information should be made, such as the multiplication-ratio inquiry (H'22) or operating frequency inquiry (H'23), which are needed for a new bit-rate selection. 6. A new bit rate should be selected with the new bit-rate selection (H'3F) command, according to the returned information on multiplication ratios and operating frequencies. 7. After selection of the device and clock mode, the information of the user boot MAT and user MAT should be made to inquire about the user boot MATs information inquiry (H'24), user MATs information inquiry (H'25), erased block information inquiry (H'26), and programming unit inquiry (H'27). 8. After making inquiries and selecting a new bit rate, issue the transition to programming/erasing state command (H'40). The boot program will then enter the programming/erasing state.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 647 of 804 REJ09B0104-0300 (8) Programming/Erasing State A programming selection command makes the boot program select the programming method, a 128-byte programming command makes it program the memory with data, and an erasing selection command and block erasing command make it erase the block. Table 17.16 lists the programming/erasing commands. Table 17.16 Programming/Erasing Commands Command Command Name Description H'42 User boot MAT programming selection T ransfers the user boot MAT programming program H'43 User MAT programming selection Transfers the user MAT programming program H'50 128-byte programming Programs 128 bytes of data H'48 Erasing selection Trans fers the erasing program H'58 Block erasing Erases a block of data H'52 Memory read Reads the contents of memory H'4A User boot MAT sum check Checks the checksum of the user boot MAT H'4B User MAT sum check Checks the checksum of the user MAT H'4C User boot MAT blank check Checks the blank data of the user boot MAT H'4D User MAT blank check Checks the blank data of the user MAT H'4F Boot program status inquiry I nquires into the boot program's status

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 648 of 804 REJ09B0104-0300

• Programming Programming is executed by the programming selection and 128-byte programming commands. Firstly, the host should send the programming selection command and select the programming method and programming MATs. There are two programming selection commands, and selection is according to the area and method for programming. 1. User boot MAT programming selection 2. User MAT programming selection After issuing the programming selection command, the host should send the 128-byte programming command. The 128-byte programming command that follows the selection command represents the data programmed according to the method specified by the selection command. When more than 128-byte data is programmed, 128-byte commands should repeatedly be executed. Sending a 128-byte programming command with H'FFFFFFFF as the address will stop the programming. On completion of programming, the boot program will wait for selection of programming or erasing. Where the sequence of programming operations that is executed includes programming with another method or of another MAT, the procedure must be repeated from the programming selection command. The sequence for the programming selection and 128-byte programming commands is shown in figure 17.25. Transfer of the programming program Host Boot program Programming selection (H'42, H'43) ACK Programming 128-byte programming (address, data) ACK 128-byte programming (H'FFFFFFFF) ACK Repeat Figure 17.25 Programming Sequence

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 649 of 804 REJ09B0104-0300

• Erasure Erasure is executed by the erasure selection and block erasure commands. Firstly, erasure is selected by the erasure selection command and the boot program then erases the specified block. The command should be repeatedly executed if two or more blocks are to be erased. Sending a block erasure command from the host with the block number H'FF will stop the erasure operating. On completion of erasing, the boot program will wait for selection of programming or erasing. The sequence for the erasure selection and block erasure commands is shown in figure 17.26. Transfer of erasure program Host Boot program Preparation for erasure (H'48) ACK Erasure Erasure (Erasure block number) Erasure (H'FF) ACK ACK Repeat Figure 17.26 Erasure Sequence

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 650 of 804 REJ09B0104-0300 (a) User Boot MAT Programming Selection The boot program will transfer a programming program. The data is programmed to the user boot MATs by the transferred programming program. Command H'42

• Command, H'42, (one byte): User boot-program programming selection Response H'06
• Response, H'06, (one byte): Response to user boot-program programming selection When the programming program has been transferred, the boot program will return ACK. Error Response H'C2 ERROR
• Error response : H'C2 (1 byte): Error response to user boot MAT programming selection
• ERROR : (1 byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed) (b) User MAT Programming Selection The boot program will transfer a program for user MAT programming selection. The data is programmed to the user MATs by the transferred program for programming. Command H'43
• Command, H'43, (one byte): User-program programming selection Response H'06
• Response, H'06, (one byte): Response to user-program programming selection When the programming program has been transferred, the boot program will return ACK. Error Response H'C3 ERROR
• Error response : H'C3 (1 byte): Error response to user boot MAT programming selection
• ERROR : (1 byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed)

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 651 of 804 REJ09B0104-0300 (c) 128-Byte Programming The boot program will use the programming program transferred by the programming selection to program the user boot MATs or user MATs in response to 128-byte programming. Command H'50 Address Data ···

• ·· S U M
• Command, H'50, (one byte): 128-byte programming
• Programming Address (four bytes): Start address for programming Multiple of the size specified in response to the programming unit inquiry
• Program data (128 bytes): Data to be programmed The size is specified in the response to the programming unit inquiry.
• SUM (one byte): Checksum Response H'06
• Response, H'06, (one byte): Response to 128-byte programming On completion of programming, the boot program will return ACK. Error Response H'D0 ERROR
• Error response, H'D0, (one byte): Error response for 128-byte programming
• ERROR: (one byte): Error code H'11: Checksum Error H'2A: Address error The address is not in the MAT. H'53: Programming error A programming error has occurred and programming cannot be continued. The specified address should match the unit for programming of data. For example, when the programming is in 128-byte units, the lower eight bits of the address should be H'00 or H'80. When there are less than 128 bytes of data to be programmed, the host should fill the rest with H'FF. Sending the 128-byte programming command with the address of H'FFFFFFFF will stop the programming operation. The boot program will interpret this as the end of the programming and wait for selection of programming or erasing.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 652 of 804 REJ09B0104-0300 Command H'50 Address SUM

• Command, H'50, (one byte): 128-byte programming
• Programming Address (four bytes): End code is H'FF, H'FF, H'FF, H'FF.
• SUM (one byte): Checksum Response H'06
• Response, H'06, (one byte): Response to 128-byte programming On completion of programming, the boot program will return ACK. Error Response H'D0 ERROR
• Error Response, H'D0, (one byte): Error response for 128-byte programming
• ERROR: (one byte): Error code H'11: Checksum error H'53: Programming error An error has occurred in programming and programming cannot be continued. (d) Erasure Selection The boot program will transfer the erasure program. User MAT data is erased by the transferred erasure program. Command H'48
• Command, H'48, (one byte): Erasure selection Response H'06
• Response, H'06, (one byte): Response for erasure selection After the erasure program has been transferred, the boot program will return ACK. Error Response H'C8 ERROR
• Error Response, H'C8, (one byte): Error response to erasure selection
• ERROR: (one byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed)

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 653 of 804 REJ09B0104-0300 (e) Block Erasure The boot program will erase the contents of the specified block. Command H'58 Size Block number SUM

• Command, H'58, (one byte): Erasure
• Size (one byte): The number of bytes that represents the erase block number This is fixed to 1.
• Block number (one byte): Number of the block to be erased
• SUM (one byte): Checksum Response H'06
• Response, H'06, (one byte): Response to Erasure After erasure has been completed, the boot program will return ACK. Error Response H'D8 ERROR
• Error Response, H'D8, (one byte): Response to Erasure
• ERROR (one byte): Error code H'11: Sum check error H'29: Block number error Block number is incorrect. H'51: Erasure error An error has occurred during erasure. On receiving block number H'FF, the boot program will stop erasure and wait for a selection command. Command H'58 Size Block number SUM
• Command, H'58, (one byte): Erasure
• Size, (one byte): The number of bytes that represents the block number This is fixed to 1.
• Block number (one byte): H'FF Stop code for erasure
• SUM (one byte): Checksum Response H'06
• Response, H'06, (one byte): Response to end of erasure (ACK) When erasure is to be performed after the block number H'FF has been sent, the procedure should be executed from the erasure selection command.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 654 of 804 REJ09B0104-0300 (f) Memory Read The boot program will return the data in the specified address. Command H'52 Size Area Read address Read size SUM

• Command: H'52 (1 byte): Memory read
• Size (1 byte): Amount of data that represents the area, read address, and read size (fixed at 9)
• Area (1 byte) H'00: User boot MAT H'01: User MAT An address error occurs when the area setting is incorrect.
• Read address (4 bytes): Start address to be read from
• Read size (4 bytes): Size of data to be read
• SUM (1 byte): Checksum Response H'52 Read size Data ··· S U M
• Response: H'52 (1 byte): Response to memory read
• Read size (4 bytes): Size of data to be read
• Data (n bytes): Data for the read size from the read address
• SUM (1 byte): Checksum Error Response H'D2 ERROR
• Error response: H'D2 (1 byte): Error response to memory read
• ERROR: (1 byte): Error code H'11: Sum check error H'2A: Address error The read address is not in the MAT. H'2B: Size error The read size exceeds the MAT.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 655 of 804 REJ09B0104-0300 (g) User-Boot Program Sum Check The boot program will return the byte-by-byte total of the contents of the bytes of the user-boot program, as a four-byte value. Command H'4A

• Command, H'4A, (one byte): Sum check for user-boot program Response H'5A Size Checksum of user boot program SUM
• Response, H'5A, (one byte): Response to the sum check of user-boot program
• Size (one byte): The number of bytes that represents the checksum This is fixed to 4.
• Checksum of user boot program (four bytes): Checksum of user boot MATs The total of the data is obtained in byte units.
• SUM (one byte): Sum check for data being transmitted (h) User-Program Sum Check The boot program will return the byte-by-byte total of the contents of the bytes of the user program. Command H'4B
• Command, H'4B, (one byte): Sum check for user program Response H'5B Size Checksum of user program SUM
• Response, H'5B, (one byte): Response to the sum check of the user program
• Size (one byte): The number of bytes that represents the checksum This is fixed to 4.
• Checksum of user boot program (four bytes): Checksum of user MATs The total of the data is obtained in byte units.
• SUM (one byte): Sum check for data being transmitted (i) User Boot MAT Blank Check The boot program will check whether or not all user boot MATs are blank and return the result. Command H'4C
• Command, H'4C, (one byte): Blank check for user boot MAT

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 656 of 804 REJ09B0104-0300 Response H'06

• Response, H'06, (one byte): Response to the blank check of user boot MAT If all user MATs are blank (H'FF), the boot program will return ACK. Error Response H'CC H'52
• Error Response, H'CC, (one byte): Response to blank check for user boot MAT
• Error Code, H'52, (one byte): Erasure has not been completed. (j) User MAT Blank Check The boot program will check whether or not all user MATs are blank and return the result. Command H'4D
• Command, H'4D, (one byte): Blank check for user MATs Response H'06
• Response, H'06, (one byte): Response to the blank check for user MATs If the contents of all user MATs are blank (H'FF), the boot program will return ACK. Error Response H'CD H'52
• Error Response, H'CD, (one byte): Error response to the blank check of user MATs.
• Error code, H'52, (one byte): Erasure has not been completed. (k) Boot Program State Inquiry The boot program will return indications of its present state and error condition. This inquiry can be made in the inquiry/selection state or the programming/erasing state. Command H'4F
• Command, H'4F, (one byte): Inquiry regarding boot program's state Response H'5F Size Status ERROR SUM
• Response, H'5F, (one byte): Response to boot program state inquiry
• Size (one byte): The number of bytes. This is fixed to 2.
• Status (one byte): State of the boot program
• ERROR (one byte): Error status ERROR = 0 indicates normal operation. ERROR = 1 indicates error has occurred.
• SUM (one byte): Sum check

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 657 of 804 REJ09B0104-0300 Table 17.17 Status Code Code Description H'11 Device selection wait H'12 Clock mode selection wait H'13 Bit rate selection wait H'1F Programming/erasing stat e transition wait (bit rate selection is completed) H'31 Programming state for erasure H'3F Programming/erasing selection wait (erasure is completed) H'4F Program data receive wait H'5F Erase block specification wait (erasure is completed) Table 17.18 Error Code Code Description H'00 No error H'11 Sum check error H'12 Program size error H'21 Device code mismatch error H'22 Clock mode mismatch error H'24 Bit rate selection error H'25 Input frequency error H'26 Multiplication ratio error H'27 Operating frequency error H'29 Block number error H'2A Address error H'2B Data length error H'51 Erasure error H'52 Erasure incomplete error H'53 Programming error H'54 Selection processing error H'80 Command error H'FF Bit-rate-adjustment confirmation error

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 658 of 804 REJ09B0104-0300

17.14 Usage Notes

1. The initial state of the product at its shipment is in the erased state. For the product whose revision of erasing is undefined, we recommend to execute automatic erasure for checking the initial state (erased state) and compensating. 2. For the PROM programmer suitable for programmer mode in this LSI and its program version, refer to the instruction manual of the socket adapter. 3. If the socket, socket adapter, or product index does not match the specifications, too much current flows and the product may be damaged. 4. Use a PROM programmer that supports the device with 256-kbyte on-chip flash memory and 5.0-V programming voltage. Do not select HN28F101 and 3.3-V programming voltage with the programmer parameters. Use only the specified socket adapter. 5. Do not remove the chip from the PROM programmer nor input a reset signal during programming/erasing in which a high voltage is applied to the flash memory. Doing so may damage the flash memory permanently. If a reset is input accidentally, the reset must be released after the reset input period of at least 100 µs. 6. The flash memory is not accessible until FKEY is cleared after programming/erasing starts. If the operating mode is changed and this LSI is restarted by a reset immediately after programming/erasing has finished, secure the reset input period (period of RES = 0) of at least 100 µs. Transition to the reset state during programming/erasing is inhibited. If a reset is input accidentally, the reset must be released after the reset input period of at least 100 µs. 7. At powering on or off the Vcc power supply, fix the RES pin to low and set the flash memory to hardware protection state. This power on/off timing must also be satisfied at a power-off and power-on caused by a power failure and other factors. 8. In on-board programming mode or programmer mode, programming of the 128-byte programming-unit block must be performed only once. Perform programming in the state where the programming-unit block is fully erased. 9. When the chip is to be reprogrammed with the programmer after execution of programming or erasure in on-board programming mode, it is recommended that automatic programming is performed after execution of automatic erasure. 10. To program the flash memory, the program data and program must be allocated to addresses which are higher than those of the external interrupt vector table and H'FF must be written to all the system reserved areas in the exception handling vector table. 11. The programming program that includes the initialization routine and the erasing program that includes the initialization routine are each 4 kbytes or less. Accordingly, when the CPU clock frequency is 40 MHz, it takes 42 µs at the maximum to download each program.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 659 of 804 REJ09B0104-0300 12. A programming/erasing program for the flash memory used in a conventional F-ZTAT H8, H8S microcomputer which does not support download of the on-chip program by setting the SCO bit in FCCS to 1 cannot run in this LSI. Be sure to download the on-chip program to execute programming/erasing of the flash memory in this F-ZTAT H8SX microcomputer. 13. Unlike a conventional F-ZTAT H8 or H8S microcomputers, measures against a program crash are not taken by WDT during programming/erasing. When needed, measures should be taken by user. A periodic interrupt generated by the WDT can be used as the measures, as an example. The interrupt generation cycle should take into consideration time to download a programming/erasing program and time to program/erase the flash memory. 14. When downloading the programming/erasing program, do not clear the SCO bit in FCCS to 0 after immediately setting it to 1. Otherwise, download cannot be performed normally. Immediately after executing the instruction to set the SCO bit to 1, dummy read of the FCCS must be executed twice. 15. The contents of some general registers are not saved in a programming/ programming end/erasing program. When needed, save general registers in the procedure program.

Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 660 of 804 REJ09B0104-0300

Section 18 Clock Pulse Generator Rev. 3.00 Mar. 14, 2006 Page 662 of 804 REJ09B0104-0300

18.1 Register Description

The clock pulse generator has the following register.

• System clock control register (SCKCR)

18.1.1 System Clock Control Register (SCKCR)

SCKCR controls Bφ clock output and frequencies of the system, peripheral module, and external clocks, and selects the Bφ clock to be output. Bit Bit Name Initial Value R/W PSTOP1 R/W R/W POSEL1 R/W R/W R/W ICK2 R/W ICK1 R/W ICK0 R/W Bit Bit Name Initial Value R/W R/W PCK2 R/W PCK1 R/W PCK0 R/W R/W BCK2 R/W BCK1 R/W BCK0 R/W Bit Bit Name Initial Value R/W Description

15 PSTOP1 0 R/W B φ Clock Output Enable

Controls φ output on PA7.

• Normal operation 0: Bφ output 1: Fixed high
• Software standby mode X: Fixed high
• Hardware standby mode X: Hi-Z 14  0 R/W Reserved This bit is always read as 0. The write value should always be 0.

Section 18 Clock Pulse Generator Rev. 3.00 Mar. 14, 2006 Page 663 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description

13 POSEL1 0 R/W B φ Output Select 1

Controls the B φ output on PA7. 0: External clock (Bφ) 1: Setting prohibited 12, 11  All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. ICK2 ICK1 ICK0 R/W R/W R/W System Clock (Iφ) Select These bits select the frequency of the system clock provided to the CPU and DMAC. The ratio to the input clock is as follows: 000: ×8 001: ×4 010: ×2 011: ×1 1XX: Setting prohibited The frequency of the peripheral module clock changes to the same frequency as the system clock if the frequency of the system clock is lower than that of the peripheral module clock. 7  0 R/W Reserved This bit is always read as 0. The write value should always be 0.

Section 18 Clock Pulse Generator Rev. 3.00 Mar. 14, 2006 Page 664 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description PCK2 PCK1 PCK0 R/W R/W R/W Peripheral Module Clock (Pφ) Select These bits select the frequency of the peripheral module clock. The ratio to the input clock is as follows: 000: ×8 001: ×4 010: ×2 011: ×1 1XX: Setting prohibited The frequency of the peripheral module clock should be lower than that of the system clock. Though these bits can be set so as to make the frequency of the peripheral module clock higher than that of the system clock, the clocks will have the same frequency in reality. 3  0 R/W Reserved This bit is always read as 0. The write value should always be 0. BCK2 BCK1 BCK0 R/W R/W R/W External clock (Bφ) Select These bits select the frequency of the external clock. The ratio to the input clock is as follows: 000: ×8 001: ×4 010: ×2 011: ×1 1XX: Setting prohibited The frequency of the external clock should be lower than that of the system clock. Though these bits can be set so as to make the frequency of the external clock higher than that of the system clock, the clocks will have the same frequency in reality. Note: X: Don't care

Section 18 Clock Pulse Generator Rev. 3.00 Mar. 14, 2006 Page 665 of 804 REJ09B0104-0300

18.2 Oscillator

Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock.

18.2.1 Connecting Crystal Resonator

A crystal resonator can be connected as shown in the example in figure 18.2. Select the damping resistance Rd according to table 18.1. An AT-cut parallel-resonance type should be used. When the clock is provided by connecting a crystal resonator, a crystal resonator having a frequency of 4 to 9 MHz should be connected. EXTAL XTAL Rd CL2 CL1 10 pF ≤ CL1 = CL2 ≤ 22 pF Figure 18.2 Connection of Crystal Resonator (Example) Table 18.1 Damping Resistance Value Frequency (MHz) 4 6 8 9 Rd (Ω) 500 300 200 100 Figure 18.3 shows an equivalent circuit of the crystal resonator. Use a crystal resonator that has the characteristics shown in table 18.2. XTAL CL AT-cut parallel-resonance type EXTAL LR s Figure 18.3 Crystal Resonator Equivalent Circuit

Section 18 Clock Pulse Generator Rev. 3.00 Mar. 14, 2006 Page 666 of 804 REJ09B0104-0300 Table 18.2 Crystal Resonator Characteristics Frequency (MHz) 4 6 8 9 RS Max. (Ω) 120 100 80 80 C0 Max. (pF) 7 7 7 7

18.2.2 External Clock Input

An external clock signal can be input as shown in the examples in figure 18.4. If the XTAL pin is left open, make sure that parasitic capacitance is no more than 10 pF. When the counter clock is input to the XTAL pin, make sure that the external clock is held high in standby mode. EXTAL XTAL External clock input Open (a) XTAL pin left open EXTAL XTAL External clock input (b) Counter clock input on XTAL pin Figure 18.4 External Clock Input (Examples) For the input conditions of the external clock, refer to table 21.4, Clock Timing, in section 21.3.1, Clock Timing. The input external clock should be from 4 to 9 MHz.

18.3 PLL Circuit

The PLL circuit has the function of multiplying the frequency of the clock from the oscillator by a factor of 8. The frequency multiplication factor is fixed.

18.4 Frequency Divider

The frequency divider divides the PLL clock to generate a 1/2, 1/4, or 1/8 clock. After bits ICK2 to ICK0 and PCK 2 to PCK0 are modified, this LSI operates at the modified frequency.

Section 18 Clock Pulse Generator Rev. 3.00 Mar. 14, 2006 Page 667 of 804 REJ09B0104-0300

18.5 Usage Notes

18.5.1 Notes on Clock Pulse Generator

1. The following points should be noted since the frequency of φ (Iφ: system clock and Pφ: peripheral module clock) supplied to each module changes according to the setting of SCKCR. Select a clock division ratio that is within the operation guaranteed range of clock cycle time tcyc shown in the AC timing of electrical characteristics. When the HCAN and SSU are in use, 8 MHz ≤ Iφ ≤ 40 MHz, and 8 MHz ≤ Pφ ≤ 20 MHz, the following settings are not permitted: Iφ < 8MHz, Iφ > 40 MHz, Pφ < 8MHz, and Pφ > 20 MHz. When the HCAN and SSU are not in use, 8 MHz ≤ Iφ ≤ 40 MHz, and 8 MHz ≤ Pφ ≤ 35 MHz, the following settings are not permitted: Iφ < 8MHz, Iφ > 40 MHz, Pφ < 8MHz, and Pφ > 35 MHz. 2. All the on-chip peripheral modules (except for the DMAC) operate on the Pφ. Therefore, note that the time processing of modules such as a timer and SCI differs before and after changing the clock division ratio. In addition, wait time for clearing software standby mode differs by changing the clock division ratio. For details, see section 19.7.3, Setting Oscillation Settling Time after Clearing Software Standby Mode. 3. The relationship between the system clock and peripheral module clock is Iφ ≥ Pφ. In addition, the system clock setting has priority. Accordingly, Pφ may have the frequency set by bits ICK2 to ICK0 regardless of the settings of bits PCK2 to PCK0. 4. Figure 18.5 shows the clock modification timing. After a value is written to SCKCR, this LSI waits for the current bus cycle to complete. After the current bus cycle completes, each clock frequency will be modified within one cycle (worst case) of the external clock. External clock One cycle (worst case) after the bus cycle completion Operating clock specified in SCKCR Operating clock changed Iφ CPU CPU CPUBus master Figure 18.5 Clock Modification Timing

Section 18 Clock Pulse Generator Rev. 3.00 Mar. 14, 2006 Page 668 of 804 REJ09B0104-0300

18.5.2 Notes on Resonator

Since various characteristics related to the resonator are closely linked to the user's board design, thorough evaluation is necessary on the user's part, using the resonator connection examples shown in this section as a reference. As the parameters for the resonator will depend on the floating capacitance of the resonator and the mounting circuit, the parameters should be determined in consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the maximum rating is not applied to the resonator pin.

18.5.3 Notes on Board Design

When using the crystal resonator, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Other signal lines should be routed away from the oscillation circuit as shown in figure 18.6 to prevent induction from interfering with correct oscillation. CL2 Signal A Signal B CL1 This LSI XTAL EXTAL Inhibited Figure 18.6 Note on Board Design for Oscillation Circuit Figure 18.7 shows a connection example of bypass capacitor. Please be sure to insert bypass capacitor (CB) close to the Vcc and Vss pins and its capacitance meets the characteristics of the user system board.

Section 18 Clock Pulse Generator Rev. 3.00 Mar. 14, 2006 Page 669 of 804 REJ09B0104-0300 VCC (68) VSS (71) VCC (54) VSS (52) CB*2 Note: Numbers in parenthesis are pin numbers. 1. A 0.1- µF capacitor should be used here. 2. CB is a laminated ceramic capacitor. This LSI CB*2 VCL (41) VSS (39) VCC (22) VSS (20) CB*2 C1*1 Figure 18.7 Connection Example of Bypass Capacitor

18.5.4 Notes on Input Clock Frequency

The frequency of the input clock is multiplied in the PLL circuit by a factor of 8. To reduce noises, a lower frequency ranging of 4 to 9 MHz is recommended.

Section 18 Clock Pulse Generator Rev. 3.00 Mar. 14, 2006 Page 670 of 804 REJ09B0104-0300

Section 19 Power-Down Modes Rev. 3.00 Mar. 14, 2006 Page 671 of 804 REJ09B0104-0300 Section 19 Power-Down Modes This LSI has power consumption reduction functions, such as multi-clock function, module stop function, and transition function to power-down mode.

19.1 Features

• Multi-clock function The frequency division ratio is settable independently for the system clock, peripheral module clock, and external bus clock.
• Module stop function The functions for each peripheral modules can be stopped to make a transition to a power- down mode.
• Transition function to power-down mode Transition to a power-down mode is possible to stop the CPU, all the on-chip peripheral modules, and oscillator.
• Three power-down modes Sleep mode All-module-clock-stop mode Software standby mode Table 19.1 shows conditions for making a transition to a power-down mode, states of the CPU and peripheral modules, and clearing method for each mode. After the reset state, since this LSI operates in normal program execution state, the modules, other than the DMAC are stopped. Table 19.1 Operating States Operating State Sleep Mode All-Module -Clock-Stop Mode Software Standby Mode Transition condition Control register + instruction Control register + instruction Control register + instruction Cancellation method Interrupt Interrupt * External interrupt Oscillator Functions Functions Halted CPU Halted (retained) Halted (retained) Halted (retained) Watchdog timer Functions Functions Halted (retained) Other peripheral modules Functions Halted * Halted *

Section 19 Power-Down Modes Rev. 3.00 Mar. 14, 2006 Page 672 of 804 REJ09B0104-0300 Operating State Sleep Mode All-Module -Clock-Stop Mode Software Standby Mode I/O port Functions Retained Retained Notes: "Halted (retained)" in the table means that the internal register values are retained and internal operations are suspended. 1. SCI, HCAN, and SSU enter the reset stat e, and other peripheral modules retain their states. 2. External interrupt and some internal interrupts (watchdog timer) 3. HCAN and SSU enter the re set state, and other peripheral modules retain their states. SLEEP instruction SLEEP instruction All interrupts SLEEP instruction External interrupt*2 Interrupt*1 SSBY = 0 SSBY = 0, ACSE = 1 MSTPCR = H'F[0-F]FFFFFF SSBY = 1 RES pin = high Transition after exception handling Reset state Program execution state Program halted state Sleep mode Notes: 1. NMI, IRQ0 to IRQ14, and watchdog timer interrupts. 2. NMI and IRQ0 to IRQ14. Note that IRQ is valid only when the corresponding bit in SSIER is set to 1. All-module-clock- stop mode Software standby mode Figure 19.1 Mode Transitions

19.2 Register Descriptions

The registers related to the power-down modes are shown below. For details on the system clock control register (SCKCR), refer to section 18.1.1, System Clock Control Register (SCKCR).

• Standby control register (SBYCR)
• Module stop control register A (MSTPCRA)
• Module stop control register B (MSTPCRB)
• Module stop control register C (MSTPCRC)

Section 19 Power-Down Modes Rev. 3.00 Mar. 14, 2006 Page 673 of 804 REJ09B0104-0300

19.2.1 Standby Control Register (SBYCR)

SBYCR controls software standby mode. Bit Bit Name Initial Value R/W SSBY R/W R/W R/W STS4 R/W STS3 R/W STS2 R/W STS1 R/W STS0 R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description

15 SSBY 0 R/W Software Standby

Specifies the transition mode after executing the SLEEP instruction 0: Shifts to sleep mode after the SLEEP instruction is executed 1: Shifts to software standby mode after the SLEEP instruction is executed This bit does not change when clearing the software standby mode by using external interrupts and shifting to normal operation. For clearing, write 0 to this bit. When the WDT is used as the watchdog timer, the setting of this bit is disabled. In this case, a transition is always made to sleep mode or all-module-clock-stop mode after the SLEEP instruction is executed. 14  1 R/W Reserved This bit is always read as 1. The write value should always be 1. 13  0 R/W Reserved This bit is always read as 0. The write value should always be 0.

Section 19 Power-Down Modes Rev. 3.00 Mar. 14, 2006 Page 674 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description STS4 STS3 STS2 STS1 STS0 R/W R/W R/W R/W R/W Standby Timer Select 4 to 0 These bits select the time the MCU waits for the clock to settle when software standby mode is cleared by an external interrupt. With a crystal resonator, refer to table 19.2 and make a selection according to the operating frequency so that the standby time is at least equal to the oscillation settling time. With an external clock, a PLL circuit settling time is necessary. Refer to table 19.2 to set the standby time. While oscillation is being settled, the timer is counted on the Pφ clock frequency. Careful consideration is required in multi-clock mode. 00000: Reserved 00001: Reserved 00010: Reserved 00011: Reserved 00100: Reserved 00101: Standby time = 64 states 00110: Standby time = 512 states 00111: Standby time = 1024 states 01000: Standby time = 2048 states 01001: Standby time = 4096 states 01010: Standby time = 16384 states 01011: Standby time = 32768 states 01100: Standby time = 65536 states 01101: Standby time = 131072 states 01110: Standby time = 262144 states 01111: Standby time = 524288 states 10000: Reserved 10001: Reserved 1001X: Reserved 101XX: Reserved 11XXX: Reserved

Section 19 Power-Down Modes Rev. 3.00 Mar. 14, 2006 Page 675 of 804 REJ09B0104-0300 Bit Bit Name Initial Value R/W Description 7 to 0  All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. Note: The flash memory settling time must be reserved.

19.2.2 Module Stop Control Registers A and B (MSTPCRA and MSTPCRB)

MSTPCRA and MSTPCRB control module stop mode. Setting a bit to 1 makes the corresponding module enter module stop mode, while clearing the bit to 0 clears module stop mode.

• MSTPCRA Bit Bit Name Initial Value R/W ACSE R/W MSTPA14 R/W MSTPA13 R/W MSTPA12 R/W MSTPA11 R/W MSTPA10 R/W MSTPA9 R/W MSTPA8 R/W Bit Bit Name Initial Value R/W MSTPA7 R/W MSTPA6 R/W MSTPA5 R/W MSTPA4 R/W MSTPA3 R/W MSTPA2 R/W MSTPA1 R/W MSTPA0 R/W
• MSTPCRB Bit Bit Name Initial Value R/W MSTPB15 R/W MSTPB14 R/W MSTPB13 R/W MSTPB12 R/W MSTPB11 R/W MSTPB10 R/W MSTPB9 R/W MSTPB8 R/W Bit Bit Name Initial Value R/W MSTPB7 R/W MSTPB6 R/W MSTPB5 R/W MSTPB4 R/W MSTPB3 R/W MSTPB2 R/W MSTPB1 R/W MSTPB0 R/W

Section 19 Power-Down Modes Rev. 3.00 Mar. 14, 2006 Page 676 of 804 REJ09B0104-0300

• MSTPCRA Bit Bit Name Initial Value R/W Module

15 ACSE 0 R/W All-Module-Clock-Stop Mode Enable

Enables/disables all-module-clock-stop mode for reducing current consumption by stopping the bus controller and I/O ports operations when the CPU executes the SLEEP instruction after module stop mode has been set for all the on-chip peripheral modules controlled by MSTPCR. 0: All-module-clock-stop mode disabled 1: All-module-clock-stop mode enabled

14 MSTPA14 0 R/W Reserved

These bits are always read as 0. The write value should always be 0.

13 MSTPA13 0 R/W DMA controller (DMAC)

12 MSTPA12 0 R/W Reserved

These bits are always read as 0. The write value should always be 0. MSTPA11 MSTPA10 MSTPA9 MSTPA8 MSTPA7 MSTPA6 MSTPA5 R/W R/W R/W R/W R/W R/W R/W Reserved These bits are always read as 1. The write value should always be 1.

4 MSTPA4 1 R/W A/D converter (unit 1)

3 MSTPA3 1 R/W A/D converter (unit 0)

2 MSTPA2 1 R/W Reserved

These bits are always read as 1. The write value should always be 1.

1 MSTPA1 1 R/W 16-bit timer pulse unit (TPU channels 11 to 6)

0 MSTPA0 1 R/W 16-bit timer pulse unit (TPU channels 5 to 0) *

Note: * Supported only by the H8SX/1527.

Section 19 Power-Down Modes Rev. 3.00 Mar. 14, 2006 Page 677 of 804 REJ09B0104-0300

• MSTPCRB Bit Bit Name Initial Value R/W Module

15 MSTPB15 1 R/W Programmable pulse generator (PPG) *

These bits are always read as 1. The write value should always be 1.

12 MSTPB12 1 R/W Serial comm unication interface_4 (SCI_4)

11 MSTPB11 1 R/W Serial comm unication interface_3 (SCI_3)

These bits are always read as 1. The write value should always be 1. Note: * Supported only by the H8SX/1527.

Section 19 Power-Down Modes Rev. 3.00 Mar. 14, 2006 Page 678 of 804 REJ09B0104-0300

19.2.3 Module Stop Cont rol Register C (MSTPCRC)

When bits MSTPC1 and MSTPC0 are set to 1, the corresponding on-chip RAM stops. Do not set the corresponding MSTPC1 and MSTPC0 bits to 1 while accessing the on-chip RAM. Bit Bit Name Initial Value R/W MSTPC15 R/W MSTPC14 R/W MSTPC13 R/W MSTPC12 R/W MSTPC11 R/W MSTPC10 R/W MSTPC9 R/W MSTPC8 R/W Bit Bit Name Initial Value R/W MSTPC7 R/W MSTPC6 R/W MSTPC5 R/W MSTPC4 R/W MSTPC3 R/W MSTPC2 R/W MSTPC1 R/W MSTPC0 R/W Bit Bit Name Initial Value R/W Module MSTPC15 MSTPC14 MSTPC13 MSTPC12 R/W R/W R/W R/W Reserved These bits are always read as 1. The write value should always be 1.

11 MSTPC11 1 R/W Controller area network (HCAN)

10 MSTPC10 1 R/W Synchronous serial communication unit 2 (SSU_2)

9 MSTPC9 1 R/W Synchronous serial communication unit 1 (SSU_1)

8 MSTPC8 1 R/W Synchronous serial communication unit 0 (SSU_0)

These bits are always read as 0. The write value should always be 0. MSTPC1 MSTPC0 R/W R/W On-chip RAM (H'FFF9000 to H'FFFBFFF) The write value to MSTPC1 and MSTPC0 should always be the same.

Section 19 Power-Down Modes Rev. 3.00 Mar. 14, 2006 Page 679 of 804 REJ09B0104-0300

19.3 Multi-Clock Function

When bits ICK2 to ICK0, PCK2 to PCK0, and BCK2 to BCK0 in SCKCR are set, a transition is made to multi-clock mode at the end of the bus cycle. In multi-clock mode, the CPU and bus masters operate on the operating clock specified by bits ICK2 to ICK0. The peripheral modules operate on the operating clock specified by bits PCK2 to PCK0. The external bus operates on the operating clock specified by bits BCK2 to BCK0. Even if the frequencies specified by bits PCK2 to PCK0 and BCK2 to BCK0 are higher than the frequency specified by bits ICK2 to ICK0, the specified values are not reflected in the peripheral module and external bus clocks. The peripheral module and external bus clocks are restricted to the operating clock specified by bits ICK2 to ICK0. Multi-clock mode is cleared by clearing all of bits ICK2 to ICK0, PCK2 to PCK0, and BCK2 to BCK0 to 0. A transition is made to normal mode at the end of the bus cycle, and multi-clock mode is cleared. If a SLEEP instruction is executed while the SSBY bit in SBYCR is cleared to 0, this LSI enters sleep mode. When sleep mode is cleared by an interrupt, multi-clock mode is restored. If a SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, this LSI enters software standby mode. When software standby mode is cleared by an external interrupt, multi- clock mode is restored. When the RES pin is driven low, the reset state is entered and multi-clock mode is cleared. The same applies to a reset caused by watchdog timer overflow.

19.4 Module Stop Mode

Module stop mode can be set for individual on-chip peripheral modules. When the corresponding MSTP bit in MSTPCRA, MSTPCRB, or MSTPCRC is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently. When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module starts operating at the end of the bus cycle. In module stop mode, the internal states of modules other than the SCI, HCAN and SSU are retained. After the reset state is cleared, all modules other than the DMAC and on-chip RAM are in module stop mode.

Section 19 Power-Down Modes Rev. 3.00 Mar. 14, 2006 Page 680 of 804 REJ09B0104-0300 The registers of the module for which module stop mode is selected cannot be read from or written to.

19.5 Sleep Mode

19.5.1 Transition to Sleep Mode

When the SLEEP instruction is executed when the SSBY bit in SBYCR is 0, the CPU enters sleep mode. In sleep mode, CPU operation stops but the contents of the CPU's internal registers are retained. Other peripheral functions do not stop.

19.5.2 Clearing Sleep Mode

Sleep mode is exited by any interrupt, signals on the RES pin, and a reset caused by a watchdog timer overflow. 1. Clearing by interrupt When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the CPU. 2. Clearing by RES pin Setting the RES pin level low selects the reset state. After the stipulated reset input duration, driving the RES pin high makes the CPU start the reset exception processing. 3. Clearing by reset caused by watchdog timer overflow Sleep mode is exited by an internal reset caused by a watchdog timer overflow.

19.6 All-Module-Clock-Stop Mode

When the ACSE bit in MSTPCRA is set to 1 and all modules controlled by MSTPCR are stopped (MSTPCRA, MSTPCRB = H'FFFFFFFF, MSTPCRC = H' FF00), executing a SLEEP instruction with the SSBY bit in SBYCR cleared to 0 will cause all modules (except for the watchdog timer), the bus controller, and the I/O ports to stop operating, and to make a transition to all-module- clock-stop mode at the end of the bus cycle. All-module-clock-stop mode is cleared by an external interrupt (NMI or IRQ0 to IRQ14 pins), RES pin input, or an internal interrupt (watchdog timer), and the CPU returns to the normal program execution state via the exception handling state. All-module-clock-stop mode is not cleared if interrupts are disabled or interrupts other than NMI are masked on the CPU side.

Section 19 Power-Down Modes Rev. 3.00 Mar. 14, 2006 Page 681 of 804 REJ09B0104-0300

19.7 Software Standby Mode

19.7.1 Transition to Software Standby Mode

If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby mode is entered. In this mode, the CPU, on-chip peripheral functions, and oscillator all stop. However, the contents of the CPU's internal registers, on-chip RAM data, and the states of on-chip peripheral functions other than the SCI, HCAN, and SSU, and the states of the I/O ports, are retained. In this mode the oscillator stops, allowing power consumption to be significantly reduced. If the WDT is used as a watchdog timer, it is impossible to make a transition to software standby mode. The WDT should be stopped before the SLEEP instruction execution.

19.7.2 Clearing Software Standby Mode

Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ14*), or by means of the RES pin. 1. Clearing by interrupt When an NMI or IRQ0 to IRQ14* interrupt request signal is input, clock oscillation starts, and after the elapse of the time set in bits STS4 to STS0 in SBYCR, stable clocks are supplied to the entire LSI, software standby mode is cleared, and interrupt exception handling is started. When clearing software standby mode with an IRQ0 to IRQ14* interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ11* is generated. Software standby mode cannot be cleared if the interrupt has been masked on the CPU side or has been designated as a DMAC activation source. Note: * By setting the SSIn bit in SSIER to 1, IRQ0 to IRQ14 can be used as a software standby mode clearing source. 2. Clearing by RES pin When the RES pin is driven low, clock oscillation is started. At the same time as clock oscillation starts, clocks are supplied to the entire LSI. Note that the RES pin must be held low until clock oscillation settles. When the RES pin goes high, the CPU begins reset exception handling.

Section 19 Power-Down Modes Rev. 3.00 Mar. 14, 2006 Page 682 of 804 REJ09B0104-0300

19.7.3 Setting Oscillation Settling Time after Clearing Software Standby Mode

Bits STS4 to STS0 in SBYCR should be set as described below. 1. Using a crystal resonator Set bits STS4 to STS0 so that the standby time is at least equal to the oscillation settling time. Table 19.2 shows the standby times for operating frequencies and settings of bits STS4 to STS0. 2. Using an external clock A PLL circuit settling time is necessary. Refer to table 19.2 to set the standby time. Table 19.2 Oscillation Settling Time Settings Pφ* [MHz] STS4 STS3 STS2 STS1 STS0 Standby Time 35 25 20 Unit 0 0 0 0 0 Reserved    µs

1 R e s e r v e d   

1 0 Reserved    1 0 0 Reserved    1 64 1.8 2.6 3.2 1 0 512 14.6 20.5 25.6 1 1024 29.3 41.0 51.2 1 0 0 0 2048 58.5 81.9 102.4 1 4096 0.12 0.16 0.20 ms 1 0 16384 0.47 0.66 0.82 1 32768 0.94 1.31 1.64 1 0 0 65536 1.87 2.62 3.28 1 131072 3.74 5.24 6.55 1 0 262144 7.49 10.49 13.11 1 524288 14.98 20.97 26.21 1 0 0 0 0 Reserved    : Recommended time setting when using a crystal resonator. : Recommended time setting when using an external clock. Note: * P φ is the output from the peripheral module frequency divider.

Section 19 Power-Down Modes Rev. 3.00 Mar. 14, 2006 Page 683 of 804 REJ09B0104-0300 Pφ* [MHz] STS4 STS3 STS2 STS1 STS0 Standby Time 13 10 8 Unit 0 0 0 0 0 Reserved    µs 1 0 Reserved    1 0 0 Reserved    1 64 4.9 6.4 8.0 1 0 512 39.4 51.2 64.0 1 1024 78.8 102.4 128.0 1 0 0 0 2048 157.5 204.8 256.0 1 4096 0.32 0.41 0.51 ms 1 0 16384 1.26 1.64 2.05 1 32765 2.52 3.28 4.10 1 0 0 65536 5.04 6.55 8.19 1 131072 10.08 13.11 16.38 1 0 262144 20.16 26.21 32.77 1 524288 40.33 52.43 65.54 1 0 0 0 0 Reserved    : Recommended time setting when using a crystal resonator. : Recommended time setting when using an external clock. Note: * φ is the output from the peripheral module frequency divider.

Section 19 Power-Down Modes Rev. 3.00 Mar. 14, 2006 Page 684 of 804 REJ09B0104-0300

19.7.4 Software Standby Mode Application Example

Figure 19.2 shows an example in which a transition is made to software standby mode at the falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI pin. In this example, an NMI interrupt is accepted with the NMIEG bit in INTCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Software standby mode is then cleared at the rising edge on the NMI pin. Oscillator Iφ NMI NMIEG SSBY NMI exception handling NMIEG = 1 SSBY = 1 SLEEP instruction Software standby mode (power-down mode) Oscillation settling time t OSC2 NMI exception handling Figure 19.2 Software Standby Mode Application Example

Section 19 Power-Down Modes Rev. 3.00 Mar. 14, 2006 Page 685 of 804 REJ09B0104-0300

19.8 B φ Clock Output Control

Output of the Bφ clock can be controlled by bits PSTOP1 and POSEL1 in SCKCR, and DDR for the corresponding PA7 pin. Clearing both bits PSTOP1 and POSEL1 to 0 enables the Bφ clock output on the PA7 pin. When bit PSTOP1 is set to 1, the Bφ clock output stops at the end of the bus cycle, and the Bφ clock output goes high. When DDR for the PA7 pin is cleared to 0, the Bφ clock output is disabled and the pin becomes an input port. Disabling Bφ output can reduce electromagnetic interference (EMI). Take it into consideration for design of the user system board. Tables 19.3 shows the states of the Bφ pin in each processing state. Table 19.3 Bφ Pin (PA7) State in Each Processing State Register Setting Value Software Standby Mode DDR PSTOP1 POSEL1 Normal Operating State Sleep Mode All-Module- Clock-Stop Mode OPE = 0 OPE = 1

0 X X Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z

1 0 0 Bφ output B φ output B φ output High High 1 0 1 Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited 1 1 X High High High High High

Section 19 Power-Down Modes Rev. 3.00 Mar. 14, 2006 Page 686 of 804 REJ09B0104-0300

19.9 Usage Notes

19.9.1 I/O Port Status

In software standby mode, the I/O port states are retained. Therefore, there is no reduction in current consumption for the output current when a high-level signal is output.

19.9.2 Current Consumptio n during Oscillation Settling Standby Period

Current consumption increases during the oscillation settling standby period.

19.9.3 DMAC Module Stop

Depending on the operating state of the DMAC, bit MSTPA13 may not be set to 1. Setting of the DMAC module stop mode should be carried out only when the DMAC is not activated. For details, refer to section 7, DMA Controller (DMAC).

19.9.4 On-Chip Peripheral Module Interrupts

Relevant interrupt operations cannot be performed in module stop mode. Consequently, if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DMAC activation source. Interrupts should therefore be disabled before entering module stop mode.

19.9.5 Writing to MSTPCRA, MSTPCRB, and MSTPCRC

MSTPCRA, MSTPCRB, and MSTPCRC should onl y be written to by the CPU.

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 687 of 804 REJ09B0104-0300 Section 20 List of Registers The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. Register addresses (address order)

• Registers are listed from the lower allocation addresses.
• Registers are classified according to functional modules.
• Undefined and reserved addresses cannot be accessed. Do not access these addresses; otherwise, the operation when accessing these bits and subsequent operations cannot be guaranteed. 2. Register bits
• Bit configurations of the registers are listed in the same order as the register addresses.
• Reserved bits are indicated by  in the bit name column.
• Space in the bit name field indicates that the entire register is allocated to either the counter or data.
• For the registers of 16 or 32 bits, the MSB is listed first. Byte configuration description order is subject to big endian. 3. Register states in each operating mode
• Register states are listed in the same order as the register addresses.
• For the initialized state of each bit, refer to the register description in the corresponding section.
• The register states shown here are for the basic operating modes. If there is a specific reset for an on-chip peripheral module, refer to the section on that on-chip peripheral module.

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 688 of 804 REJ09B0104-0300

20.1 Register Addresses (Address Order)

Register Name Abbr. Number of Bits Address Module Data Width Access Cycles (Read/Write) Master control register MCR 8 H'FEA00 HCAN 16 4P φ/4Pφ General status register GSR 8 H'FEA01 HCAN 16 4P φ/4Pφ Bit configuration register BCR 16 H'FEA02 HCAN 16 4P φ/4Pφ Mailbox configuration register MBCR 16 H'FEA04 HCAN 16 4P φ/4Pφ Transmit wait register TXPR 16 H'FEA06 HCAN 16 4P φ/4Pφ Transmit wait cancel register TXCR 16 H'FEA08 HCAN 16 4P φ/4Pφ Transmit acknowledge register TXACK 16 H'FEA0A HCAN 16 4P φ/4Pφ Abort acknowledge register ABACK 16 H'FEA0C HCAN 16 4P φ/4Pφ Receive complete register RXPR 16 H'FEA0E HCAN 16 4P φ/4Pφ Remote request register RFPR 16 H'FEA10 HCAN 16 4P φ/4Pφ Interrupt register IRR 16 H'FEA12 HCAN 16 4P φ/4Pφ Mailbox interrupt mask register MBIMR 16 H'FEA14 HCAN 16 4P φ/4Pφ Interrupt mask register IMR 16 H'FEA16 HCAN 16 4P φ/4Pφ Receive error counter REC 8 H'FEA18 HCAN 16 4P φ/4Pφ Transmit error counter TEC 8 H'FEA19 HCAN 16 4P φ/4Pφ Unread message status register UMSR 16 H'FEA1A HCAN 16 4P φ/4Pφ Local acceptance filter mask L LAFML 16 H'FEA1C HCAN 16 4P φ/4Pφ Local acceptance filter mask H LAFMH 16 H'FEA1E HCAN 16 4P φ/4Pφ Message control 0 [1] MC0[1] 8 H'FEA20 HCAN 16 4P φ/4Pφ Message control 0 [2] MC0[2] 8 H'FEA21 HCAN 16 4P φ/4Pφ Message control 0 [3] MC0[3] 8 H'FEA22 HCAN 16 4P φ/4Pφ Message control 0 [4] MC0[4] 8 H'FEA23 HCAN 16 4P φ/4Pφ Message control 0 [5] MC0[5] 8 H'FEA24 HCAN 16 4P φ/4Pφ Message control 0 [6] MC0[6] 8 H'FEA25 HCAN 16 4P φ/4Pφ Message control 0 [7] MC0[7] 8 H'FEA26 HCAN 16 4P φ/4Pφ Message control 0 [8] MC0[8] 8 H'FEA27 HCAN 16 4P φ/4Pφ

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 689 of 804 REJ09B0104-0300 Register Name Abbr. Number of Bits Address Module Data Width Access Cycles (Read/Write) Message control 1 [1] MC1[1] 8 H'FEA28 HCAN 16 4P φ/4Pφ Message control 1 [2] MC1[2] 8 H'FEA29 HCAN 16 4P φ/4Pφ Message control 1 [3] MC1[3] 8 H'FEA2A HCAN 16 4P φ/4Pφ Message control 1 [4] MC1[4] 8 H'FEA2B HCAN 16 4P φ/4Pφ Message control 1 [5] MC1[5] 8 H'FEA2C HCAN 16 4P φ/4Pφ Message control 1 [6] MC1[6] 8 H'FEA2D HCAN 16 4P φ/4Pφ Message control 1 [7] MC1[7] 8 H'FEA2E HCAN 16 4P φ/4Pφ Message control 1 [8] MC1[8] 8 H'FEA2F HCAN 16 4P φ/4Pφ Message control 2 [1] MC2[1] 8 H'FEA30 HCAN 16 4P φ/4Pφ Message control 2 [2] MC2[2] 8 H'FEA31 HCAN 16 4P φ/4Pφ Message control 2 [3] MC2[3] 8 H'FEA32 HCAN 16 4P φ/4Pφ Message control 2 [4] MC2[4] 8 H'FEA33 HCAN 16 4P φ/4Pφ Message control 2 [5] MC2[5] 8 H'FEA34 HCAN 16 4P φ/4Pφ Message control 2 [6] MC2[6] 8 H'FEA35 HCAN 16 4P φ/4Pφ Message control 2 [7] MC2[7] 8 H'FEA36 HCAN 16 4P φ/4Pφ Message control 2 [8] MC2[8] 8 H'FEA37 HCAN 16 4P φ/4Pφ Message control 3 [1] MC3[1] 8 H'FEA38 HCAN 16 4P φ/4Pφ Message control 3 [2] MC3[2] 8 H'FEA39 HCAN 16 4P φ/4Pφ Message control 3 [3] MC3[3] 8 H'FEA3A HCAN 16 4P φ/4Pφ Message control 3 [4] MC3[4] 8 H'FEA3B HCAN 16 4P φ/4Pφ Message control 3 [5] MC3[5] 8 H'FEA3C HCAN 16 4P φ/4Pφ Message control 3 [6] MC3[6] 8 H'FEA3D HCAN 16 4P φ/4Pφ Message control 3 [7] MC3[7] 8 H'FEA3E HCAN 16 4P φ/4Pφ Message control 3 [8] MC3[8] 8 H'FEA3F HCAN 16 4P φ/4Pφ Message control 4 [1] MC4[1] 8 H'FEA40 HCAN 16 4P φ/4Pφ Message control 4 [2] MC4[2] 8 H'FEA41 HCAN 16 4P φ/4Pφ Message control 4 [3] MC4[3] 8 H'FEA42 HCAN 16 4P φ/4Pφ Message control 4 [4] MC4[4] 8 H'FEA43 HCAN 16 4P φ/4Pφ

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 690 of 804 REJ09B0104-0300 Register Name Abbr. Number of Bits Address Module Data Width Access Cycles (Read/Write) Message control 4 [5] MC4[5] 8 H'FEA44 HCAN 16 4P φ/4Pφ Message control 4 [6] MC4[6] 8 H'FEA45 HCAN 16 4P φ/4Pφ Message control 4 [7] MC4[7] 8 H'FEA46 HCAN 16 4P φ/4Pφ Message control 4 [8] MC4[8] 8 H'FEA47 HCAN 16 4P φ/4Pφ Message control 5 [1] MC5[1] 8 H'FEA48 HCAN 16 4P φ/4Pφ Message control 5 [2] MC5[2] 8 H'FEA49 HCAN 16 4P φ/4Pφ Message control 5 [3] MC5[3] 8 H'FEA4A HCAN 16 4P φ/4Pφ Message control 5 [4] MC5[4] 8 H'FEA4B HCAN 16 4P φ/4Pφ Message control 5 [5] MC5[5] 8 H'FEA4C HCAN 16 4P φ/4Pφ Message control 5 [6] MC5[6] 8 H'FEA4D HCAN 16 4P φ/4Pφ Message control 5 [7] MC5[7] 8 H'FEA4E HCAN 16 4P φ/4Pφ Message control 5 [8] MC5[8] 8 H'FEA4F HCAN 16 4P φ/4Pφ Message control 6 [1] MC6[1] 8 H'FEA50 HCAN 16 4P φ/4Pφ Message control 6 [2] MC6[2] 8 H'FEA51 HCAN 16 4P φ/4Pφ Message control 6 [3] MC6[3] 8 H'FEA52 HCAN 16 4P φ/4Pφ Message control 6 [4] MC6[4] 8 H'FEA53 HCAN 16 4P φ/4Pφ Message control 6 [5] MC6[5] 8 H'FEA54 HCAN 16 4P φ/4Pφ Message control 6 [6] MC6[6] 8 H'FEA55 HCAN 16 4P φ/4Pφ Message control 6 [7] MC6[7] 8 H'FEA56 HCAN 16 4P φ/4Pφ Message control 6 [8] MC6[8] 8 H'FEA57 HCAN 16 4P φ/4Pφ Message control 7 [1] MC7[1] 8 H'FEA58 HCAN 16 4P φ/4Pφ Message control 7 [2] MC7[2] 8 H'FEA59 HCAN 16 4P φ/4Pφ Message control 7 [3] MC7[3] 8 H'FEA5A HCAN 16 4P φ/4Pφ Message control 7 [4] MC7[4] 8 H'FEA5B HCAN 16 4P φ/4Pφ Message control 7 [5] MC7[5] 8 H'FEA5C HCAN 16 4P φ/4Pφ Message control 7 [6] MC7[6] 8 H'FEA5D HCAN 16 4P φ/4Pφ Message control 7 [7] MC7[7] 8 H'FEA5E HCAN 16 4P φ/4Pφ Message control 7 [8] MC7[8] 8 H'FEA5F HCAN 16 4P φ/4Pφ

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 691 of 804 REJ09B0104-0300 Register Name Abbr. Number of Bits Address Module Data Width Access Cycles (Read/Write) Message control 8 [1] MC8[1] 8 H'FEA60 HCAN 16 4P φ/4Pφ Message control 8 [2] MC8[2] 8 H'FEA61 HCAN 16 4P φ/4Pφ Message control 8 [3] MC8[3] 8 H'FEA62 HCAN 16 4P φ/4Pφ Message control 8 [4] MC8[4] 8 H'FEA63 HCAN 16 4P φ/4Pφ Message control 8 [5] MC8[5] 8 H'FEA64 HCAN 16 4P φ/4Pφ Message control 8 [6] MC8[6] 8 H'FEA65 HCAN 16 4P φ/4Pφ Message control 8 [7] MC8[7] 8 H'FEA66 HCAN 16 4P φ/4Pφ Message control 8 [8] MC8[8] 8 H'FEA67 HCAN 16 4P φ/4Pφ Message control 9 [1] MC9[1] 8 H'FEA68 HCAN 16 4P φ/4Pφ Message control 9 [2] MC9[2] 8 H'FEA69 HCAN 16 4P φ/4Pφ Message control 9 [3] MC9[3] 8 H'FEA6A HCAN 16 4P φ/4Pφ Message control 9 [4] MC9[4] 8 H'FEA6B HCAN 16 4P φ/4Pφ Message control 9 [5] MC9[5] 8 H'FEA6C HCAN 16 4P φ/4Pφ Message control 9 [6] MC9[6] 8 H'FEA6D HCAN 16 4P φ/4Pφ Message control 9 [7] MC9[7] 8 H'FEA6E HCAN 16 4P φ/4Pφ Message control 9 [8] MC9[8] 8 H'FEA6F HCAN 16 4P φ/4Pφ Message control 10 [1] MC10[1] 8 H'FEA70 HCAN 16 4P φ/4Pφ Message control 10 [2] MC10[2] 8 H'FEA71 HCAN 16 4P φ/4Pφ Message control 10 [3] MC10[3] 8 H'FEA72 HCAN 16 4P φ/4Pφ Message control 10 [4] MC10[4] 8 H'FEA73 HCAN 16 4P φ/4Pφ Message control 10 [5] MC10[5] 8 H'FEA74 HCAN 16 4P φ/4Pφ Message control 10 [6] MC10[6] 8 H'FEA75 HCAN 16 4P φ/4Pφ Message control 10 [7] MC10[7] 8 H'FEA76 HCAN 16 4P φ/4Pφ Message control 10 [8] MC10[8] 8 H'FEA77 HCAN 16 4P φ/4Pφ Message control 11 [1] MC11[1] 8 H'FEA78 HCAN 16 4P φ/4Pφ Message control 11 [2] MC11[2] 8 H'FEA79 HCAN 16 4P φ/4Pφ Message control 11 [3] MC11[3] 8 H'FEA7A HCAN 16 4P φ/4Pφ Message control 11 [4] MC11[4] 8 H'FEA7B HCAN 16 4P φ/4Pφ

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 692 of 804 REJ09B0104-0300 Register Name Abbr. Number of Bits Address Module Data Width Access Cycles (Read/Write) Message control 11 [5] MC11[5] 8 H'FEA7C HCAN 16 4P φ/4Pφ Message control 11 [6] MC11[6] 8 H'FEA7D HCAN 16 4P φ/4Pφ Message control 11 [7] MC11[7] 8 H'FEA7E HCAN 16 4P φ/4Pφ Message control 11 [8] MC11[8] 8 H'FEA7F HCAN 16 4P φ/4Pφ Message control 12 [1] MC12[1] 8 H'FEA80 HCAN 16 4P φ/4Pφ Message control 12 [2] MC12[2] 8 H'FEA81 HCAN 16 4P φ/4Pφ Message control 12 [3] MC12[3] 8 H'FEA82 HCAN 16 4P φ/4Pφ Message control 12 [4] MC12[4] 8 H'FEA83 HCAN 16 4P φ/4Pφ Message control 12 [5] MC12[5] 8 H'FEA84 HCAN 16 4P φ/4Pφ Message control 12 [6] MC12[6] 8 H'FEA85 HCAN 16 4P φ/4Pφ Message control 12 [7] MC12[7] 8 H'FEA86 HCAN 16 4P φ/4Pφ Message control 12 [8] MC12[8] 8 H'FEA87 HCAN 16 4P φ/4Pφ Message control 13 [1] MC13[1] 8 H'FEA88 HCAN 16 4P φ/4Pφ Message control 13 [2] MC13[2] 8 H'FEA89 HCAN 16 4P φ/4Pφ Message control 13 [3] MC13[3] 8 H'FEA8A HCAN 16 4P φ/4Pφ Message control 13 [4] MC13[4] 8 H'FEA8B HCAN 16 4P φ/4Pφ Message control 13 [5] MC13[5] 8 H'FEA8C HCAN 16 4P φ/4Pφ Message control 13 [6] MC13[6] 8 H'FEA8D HCAN 16 4P φ/4Pφ Message control 13 [7] MC13[7] 8 H'FEA8E HCAN 16 4P φ/4Pφ Message control 13 [8] MC13[8] 8 H'FEA8F HCAN 16 4P φ/4Pφ Message control 14 [1] MC14[1] 8 H'FEA90 HCAN 16 4P φ/4Pφ Message control 14 [2] MC14[2] 8 H'FEA91 HCAN 16 4P φ/4Pφ Message control 14 [3] MC14[3] 8 H'FEA92 HCAN 16 4P φ/4Pφ Message control 14 [4] MC14[4] 8 H'FEA93 HCAN 16 4P φ/4Pφ Message control 14 [5] MC14[5] 8 H'FEA94 HCAN 16 4P φ/4Pφ Message control 14 [6] MC14[6] 8 H'FEA95 HCAN 16 4P φ/4Pφ Message control 14 [7] MC14[7] 8 H'FEA96 HCAN 16 4P φ/4Pφ Message control 14 [8] MC14[8] 8 H'FEA97 HCAN 16 4P φ/4Pφ

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 693 of 804 REJ09B0104-0300 Register Name Abbr. Number of Bits Address Module Data Width Access Cycles (Read/Write) Message control 15 [1] MC15[1] 8 H'FEA98 HCAN 16 4P φ/4Pφ Message control 15 [2] MC15[2] 8 H'FEA99 HCAN 16 4P φ/4Pφ Message control 15 [3] MC15[3] 8 H'FEA9A HCAN 16 4P φ/4Pφ Message control 15 [4] MC15[4] 8 H'FEA9B HCAN 16 4P φ/4Pφ Message control 15 [5] MC15[5] 8 H'FEA9C HCAN 16 4P φ/4Pφ Message control 15 [6] MC15[6] 8 H'FEA9D HCAN 16 4P φ/4Pφ Message control 15 [7] MC15[7] 8 H'FEA9E HCAN 16 4P φ/4Pφ Message control 15 [8] MC15[8] 8 H'FEA9F HCAN 16 4P φ/4Pφ Message data 0 [1] MD0[1] 8 H'FEAB0 HCAN 16 4P φ/4Pφ Message data 0 [2] MD0[2] 8 H'FEAB1 HCAN 16 4P φ/4Pφ Message data 0 [3] MD0[3] 8 H'FEAB2 HCAN 16 4P φ/4Pφ Message data 0 [4] MD0[4] 8 H'FEAB3 HCAN 16 4P φ/4Pφ Message data 0 [5] MD0[5] 8 H'FEAB4 HCAN 16 4P φ/4Pφ Message data 0 [6] MD0[6] 8 H'FEAB5 HCAN 16 4P φ/4Pφ Message data 0 [7] MD0[7] 8 H'FEAB6 HCAN 16 4P φ/4Pφ Message data 0 [8] MD0[8] 8 H'FEAB7 HCAN 16 4P φ/4Pφ Message data 1 [1] MD1[1] 8 H'FEAB8 HCAN 16 4P φ/4Pφ Message data 1 [2] MD1[2] 8 H'FEAB9 HCAN 16 4P φ/4Pφ Message data 1 [3] MD1[3] 8 H'FEABA HCAN 16 4P φ/4Pφ Message data 1 [4] MD1[4] 8 H'FEABB HCAN 16 4P φ/4Pφ Message data 1 [5] MD1[5] 8 H'FEABC HCAN 16 4P φ/4Pφ Message data 1 [6] MD1[6] 8 H'FEABD HCAN 16 4P φ/4Pφ Message data 1 [7] MD1[7] 8 H'FEABE HCAN 16 4P φ/4Pφ Message data 1 [8] MD1[8] 8 H'FEABF HCAN 16 4P φ/4Pφ Message data 2 [1] MD2[1] 8 H'FEAC0 HCAN 16 4P φ/4Pφ Message data 2 [2] MD2[2] 8 H'FEAC1 HCAN 16 4P φ/4Pφ Message data 2 [3] MD2[3] 8 H'FEAC2 HCAN 16 4P φ/4Pφ Message data 2 [4] MD2[4] 8 H'FEAC3 HCAN 16 4P φ/4Pφ

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 694 of 804 REJ09B0104-0300 Register Name Abbr. Number of Bits Address Module Data Width Access Cycles (Read/Write) Message data 2 [5] MD2[5] 8 H'FEAC4 HCAN 16 4P φ/4Pφ Message data 2 [6] MD2[6] 8 H'FEAC5 HCAN 16 4P φ/4Pφ Message data 2 [7] MD2[7] 8 H'FEAC6 HCAN 16 4P φ/4Pφ Message data 2 [8] MD2[8] 8 H'FEAC7 HCAN 16 4P φ/4Pφ Message data 3 [1] MD3[1] 8 H'FEAC8 HCAN 16 4P φ/4Pφ Message data 3 [2] MD3[2] 8 H'FEAC9 HCAN 16 4P φ/4Pφ Message data 3 [3] MD3[3] 8 H'FEACA HCAN 16 4P φ/4Pφ Message data 3 [4] MD3[4] 8 H'FEACB HCAN 16 4P φ/4Pφ Message data 3 [5] MD3[5] 8 H'FEACC HCAN 16 4P φ/4Pφ Message data 3 [6] MD3[6] 8 H'FEACD HCAN 16 4P φ/4Pφ Message data 3 [7] MD3[7] 8 H'FEACE HCAN 16 4P φ/4Pφ Message data 3 [8] MD3[8] 8 H'FEACF HCAN 16 4P φ/4Pφ Message data 4 [1] MD4[1] 8 H'FEAD0 HCAN 16 4P φ/4Pφ Message data 4 [2] MD4[2] 8 H'FEAD1 HCAN 16 4P φ/4Pφ Message data 4 [3] MD4[3] 8 H'FEAD2 HCAN 16 4P φ/4Pφ Message data 4 [4] MD4[4] 8 H'FEAD3 HCAN 16 4P φ/4Pφ Message data 4 [5] MD4[5] 8 H'FEAD4 HCAN 16 4P φ/4Pφ Message data 4 [6] MD4[6] 8 H'FEAD5 HCAN 16 4P φ/4Pφ Message data 4 [7] MD4[7] 8 H'FEAD6 HCAN 16 4P φ/4Pφ Message data 4 [8] MD4[8] 8 H'FEAD7 HCAN 16 4P φ/4Pφ Message data 5 [1] MD5[1] 8 H'FEAD8 HCAN 16 4P φ/4Pφ Message data 5 [2] MD5[2] 8 H'FEAD9 HCAN 16 4P φ/4Pφ Message data 5 [3] MD5[3] 8 H'FEADA HCAN 16 4P φ/4Pφ Message data 5 [4] MD5[4] 8 H'FEADB HCAN 16 4P φ/4Pφ Message data 5 [5] MD5[5] 8 H'FEADC HCAN 16 4P φ/4Pφ Message data 5 [6] MD5[6] 8 H'FEADD HCAN 16 4P φ/4Pφ Message data 5 [7] MD5[7] 8 H'FEADE HCAN 16 4P φ/4Pφ Message data 5 [8] MD5[8] 8 H'FEADF HCAN 16 4P φ/4Pφ

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 695 of 804 REJ09B0104-0300 Register Name Abbr. Number of Bits Address Module Data Width Access Cycles (Read/Write) Message data 6 [1] MD6[1] 8 H'FEAE0 HCAN 16 4P φ/4Pφ Message data 6 [2] MD6[2] 8 H'FEAE1 HCAN 16 4P φ/4Pφ Message data 6 [3] MD6[3] 8 H'FEAE2 HCAN 16 4P φ/4Pφ Message data 6 [4] MD6[4] 8 H'FEAE3 HCAN 16 4P φ/4Pφ Message data 6 [5] MD6[5] 8 H'FEAE4 HCAN 16 4P φ/4Pφ Message data 6 [6] MD6[6] 8 H'FEAE5 HCAN 16 4P φ/4Pφ Message data 6 [7] MD6[7] 8 H'FEAE6 HCAN 16 4P φ/4Pφ Message data 6 [8] MD6[8] 8 H'FEAE7 HCAN 16 4P φ/4Pφ Message data 7 [1] MD7[1] 8 H'FEAE8 HCAN 16 4P φ/4Pφ Message data 7 [2] MD7[2] 8 H'FEAE9 HCAN 16 4P φ/4Pφ Message data 7 [3] MD7[3] 8 H'FEAEA HCAN 16 4P φ/4Pφ Message data 7 [4] MD7[4] 8 H'FEAEB HCAN 16 4P φ/4Pφ Message data 7 [5] MD7[5] 8 H'FEAEC HCAN 16 4P φ/4Pφ Message data 7 [6] MD7[6] 8 H'FEAED HCAN 16 4P φ/4Pφ Message data 7 [7] MD7[7] 8 H'FEAEE HCAN 16 4P φ/4Pφ Message data 7 [8] MD7[8] 8 H'FEAEF HCAN 16 4P φ/4Pφ Message data 8 [1] MD8[1] 8 H'FEAF0 HCAN 16 4P φ/4Pφ Message data 8 [2] MD8[2] 8 H'FEAF1 HCAN 16 4P φ/4Pφ Message data 8 [3] MD8[3] 8 H'FEAF2 HCAN 16 4P φ/4Pφ Message data 8 [4] MD8[4] 8 H'FEAF3 HCAN 16 4P φ/4Pφ Message data 8 [5] MD8[5] 8 H'FEAF4 HCAN 16 4P φ/4Pφ Message data 8 [6] MD8[6] 8 H'FEAF5 HCAN 16 4P φ/4Pφ Message data 8 [7] MD8[7] 8 H'FEAF6 HCAN 16 4P φ/4Pφ Message data 8 [8] MD8[8] 8 H'FEAF7 HCAN 16 4P φ/4Pφ Message data 9 [1] MD9[1] 8 H'FEAF8 HCAN 16 4P φ/4Pφ Message data 9 [2] MD9[2] 8 H'FEAF9 HCAN 16 4P φ/4Pφ Message data 9 [3] MD9[3] 8 H'FEAFA HCAN 16 4P φ/4Pφ Message data 9 [4] MD9[4] 8 H'FEAFB HCAN 16 4P φ/4Pφ

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 696 of 804 REJ09B0104-0300 Register Name Abbr. Number of Bits Address Module Data Width Access Cycles (Read/Write) Message data 9 [5] MD9[5] 8 H'FEAFC HCAN 16 4P φ/4Pφ Message data 9 [6] MD9[6] 8 H'FEAFD HCAN 16 4P φ/4Pφ Message data 9 [7] MD9[7] 8 H'FEAFE HCAN 16 4P φ/4Pφ Message data 9 [8] MD9[8] 8 H'FEAFF HCAN 16 4P φ/4Pφ Message data 10 [1] MD10[1] 8 H'FEB00 HCAN 16 4P φ/4Pφ Message data 10 [2] MD10[2] 8 H'FEB01 HCAN 16 4P φ/4Pφ Message data 10 [3] MD10[3] 8 H'FEB02 HCAN 16 4P φ/4Pφ Message data 10 [4] MD10[4] 8 H'FEB03 HCAN 16 4P φ/4Pφ Message data 10 [5] MD10[5] 8 H'FEB04 HCAN 16 4P φ/4Pφ Message data 10 [6] MD10[6] 8 H'FEB05 HCAN 16 4P φ/4Pφ Message data 10 [7] MD10[7] 8 H'FEB06 HCAN 16 4P φ/4Pφ Message data 10 [8] MD10[8] 8 H'FEB07 HCAN 16 4P φ/4Pφ Message data 11 [1] MD11[1] 8 H'FEB08 HCAN 16 4P φ/4Pφ Message data 11 [2] MD11[2] 8 H'FEB09 HCAN 16 4P φ/4Pφ Message data 11 [3] MD11[3] 8 H'FEB0A HCAN 16 4P φ/4Pφ Message data 11 [4] MD11[4] 8 H'FEB0B HCAN 16 4P φ/4Pφ Message data 11 [5] MD11[5] 8 H'FEB0C HCAN 16 4P φ/4Pφ Message data 11 [6] MD11[6] 8 H'FEB0D HCAN 16 4P φ/4Pφ Message data 11 [7] MD11[7] 8 H'FEB0E HCAN 16 4P φ/4Pφ Message data 11 [8] MD11[8] 8 H'FEB0F HCAN 16 4P φ/4Pφ Message data 12 [1] MD12[1] 8 H'FEB10 HCAN 16 4P φ/4Pφ Message data 12 [2] MD12[2] 8 H'FEB11 HCAN 16 4P φ/4Pφ Message data 12 [3] MD12[3] 8 H'FEB12 HCAN 16 4P φ/4Pφ Message data 12 [4] MD12[4] 8 H'FEB13 HCAN 16 4P φ/4Pφ Message data 12 [5] MD12[5] 8 H'FEB14 HCAN 16 4P φ/4Pφ Message data 12 [6] MD12[6] 8 H'FEB15 HCAN 16 4P φ/4Pφ Message data 12 [7] MD12[7] 8 H'FEB16 HCAN 16 4P φ/4Pφ Message data 12 [8] MD12[8] 8 H'FEB17 HCAN 16 4P φ/4Pφ

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 697 of 804 REJ09B0104-0300 Register Name Abbr. Number of Bits Address Module Data Width Access Cycles (Read/Write) Message data 13 [1] MD13[1] 8 H'FEB18 HCAN 16 4P φ/4Pφ Message data 13 [2] MD13[2] 8 H'FEB19 HCAN 16 4P φ/4Pφ Message data 13 [3] MD13[3] 8 H'FEB1A HCAN 16 4P φ/4Pφ Message data 13 [4] MD13[4] 8 H'FEB1B HCAN 16 4P φ/4Pφ Message data 13 [5] MD13[5] 8 H'FEB1C HCAN 16 4P φ/4Pφ Message data 13 [6] MD13[6] 8 H'FEB1D HCAN 16 4P φ/4Pφ Message data 13 [7] MD13[7] 8 H'FEB1E HCAN 16 4P φ/4Pφ Message data 13 [8] MD13[8] 8 H'FEB1F HCAN 16 4P φ/4Pφ Message data 14 [1] MD14[1] 8 H'FEB20 HCAN 16 4P φ/4Pφ Message data 14 [2] MD14[2] 8 H'FEB21 HCAN 16 4P φ/4Pφ Message data 14 [3] MD14[3] 8 H'FEB22 HCAN 16 4P φ/4Pφ Message data 14 [4] MD14[4] 8 H'FEB23 HCAN 16 4P φ/4Pφ Message data 14 [5] MD14[5] 8 H'FEB24 HCAN 16 4P φ/4Pφ Message data 14 [6] MD14[6] 8 H'FEB25 HCAN 16 4P φ/4Pφ Message data 14 [7] MD14[7] 8 H'FEB26 HCAN 16 4P φ/4Pφ Message data 14 [8] MD14[8] 8 H'FEB27 HCAN 16 4P φ/4Pφ Message data 15 [1] MD15[1] 8 H'FEB28 HCAN 16 4P φ/4Pφ Message data 15 [2] MD15[2] 8 H'FEB29 HCAN 16 4P φ/4Pφ Message data 15 [3] MD15[3] 8 H'FEB2A HCAN 16 4P φ/4Pφ Message data 15 [4] MD15[4] 8 H'FEB2B HCAN 16 4P φ/4Pφ Message data 15 [5] MD15[5] 8 H'FEB2C HCAN 16 4P φ/4Pφ Message data 15 [6] MD15[6] 8 H'FEB2D HCAN 16 4P φ/4Pφ Message data 15 [7] MD15[7] 8 H'FEB2E HCAN 16 4P φ/4Pφ Message data 15 [8] MD15[8] 8 H'FEB2F HCAN 16 4P φ/4Pφ HCAN monitor register HCANMON 8 H'FEB40 HCAN 16 4P φ/4Pφ

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 698 of 804 REJ09B0104-0300 Register Name Abbr. Number of Bits Address Module Data Width Access Cycles (Read/Write) SS control register H_0 SSCRH_0 8 H'FF200 SSU_0 16 3P φ/3Pφ SS control register L_0 SSCRL_0 8 H'FF201 SSU_0 16 3P φ/3Pφ SS mode register_0 SSMR_0 8 H'FF202 SSU_0 16 3P φ/3Pφ SS enable register_0 SSER_0 8 H'FF203 SSU_0 16 3P φ/3Pφ SS status register_0 SSSR_0 8 H'FF204 SSU_0 16 3P φ/3Pφ SS control register 2_0 SSCR2_0 8 H'FF205 SSU_0 16 3P φ/3Pφ SS transmit data register 0_0 SSTDR0_0 8 H'FF206 SSU_0 16 3P φ/3Pφ SS transmit data register 1_0 SSTDR1_0 8 H'FF207 SSU_0 16 3P φ/3Pφ SS transmit data register 2_0 SSTDR2_0 8 H'FF208 SSU_0 16 3P φ/3Pφ SS transmit data register 3_0 SSTDR3_0 8 H'FF209 SSU_0 16 3P φ/3Pφ SS receive data register 0_0 SSRDR0_0 8 H'FF20A SSU_0 16 3P φ/3Pφ SS receive data register 1_0 SSRDR1_0 8 H'FF20B SSU_0 16 3P φ/3Pφ SS receive data register 2_0 SSRDR2_0 8 H'FF20C SSU_0 16 3P φ/3Pφ SS receive data register 3_0 SSRDR3_0 8 H'FF20D SSU_0 16 3P φ/3Pφ SS control register H_1 SSCRH_1 8 H'FF210 SSU_1 16 3P φ/3Pφ SS control register L_1 SSCRL_1 8 H'FF211 SSU_1 16 3P φ/3Pφ SS mode register_1 SSMR_1 8 H'FF212 SSU_1 16 3P φ/3Pφ SS enable register_1 SSER_1 8 H'FF213 SSU_1 16 3P φ/3Pφ SS status register_1 SSSR_1 8 H'FF214 SSU_1 16 3P φ/3Pφ SS control register2_1 SSCR2_1 8 H'FF215 SSU_1 16 3P φ/3Pφ SS transmit data register0_1 SSTDR0_1 8 H'FF216 SSU_1 16 3P φ/3Pφ SS transmit data register1_1 SSTDR1_1 8 H'FF217 SSU_1 16 3P φ/3Pφ SS transmit data register2_1 SSTDR2_1 8 H'FF218 SSU_1 16 3P φ/3Pφ SS transmit data register3_1 SSTDR3_1 8 H'FF219 SSU_1 16 3P φ/3Pφ SS receive data register0_1 SSRDR0_1 8 H'FF21A SSU_1 16 3P φ/3Pφ SS receive data register1_1 SSRDR1_1 8 H'FF21B SSU_1 16 3P φ/3Pφ SS receive data register2_1 SSRDR2_1 8 H'FF21C SSU_1 16 3P φ/3Pφ SS receive data register3_1 SSRDR3_1 8 H'FF21D SSU_1 16 3P φ/3Pφ

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 699 of 804 REJ09B0104-0300 Register Name Abbr. Number of Bits Address Module Data Width Access Cycles (Read/Write) SS control register H_2 SSCRH_2 8 H'FF220 SSU_2 16 3P φ/3Pφ SS control register L_2 SSCRL_2 8 H'FF221 SSU_2 16 3P φ/3Pφ SS mode register_2 SSMR_2 8 H'FF222 SSU_2 16 3P φ/3Pφ SS enable register_2 SSER_2 8 H'FF223 SSU_2 16 3P φ/3Pφ SS status register_2 SSSR_2 8 H'FF224 SSU_2 16 3P φ/3Pφ SS control register2_2 SSCR2_2 8 H'FF225 SSU_2 16 3P φ/3Pφ SS transmit data register0_2 SSTDR0_2 8 H'FF226 SSU_2 16 3P φ/3Pφ SS transmit data register1_2 SSTDR1_2 8 H'FF227 SSU_2 16 3P φ/3Pφ SS transmit data register2_2 SSTDR2_2 8 H'FF228 SSU_2 16 3P φ/3Pφ SS transmit data register3_2 SSTDR3_2 8 H'FF229 SSU_2 16 3P φ/3Pφ SS receive data register0_2 SSRDR0_2 8 H'FF22A SSU_2 16 3P φ/3Pφ SS receive data register1_2 SSRDR1_2 8 H'FF22B SSU_2 16 3P φ/3Pφ SS receive data register2_2 SSRDR2_2 8 H'FF22C SSU_2 16 3P φ/3Pφ SS receive data register3_2 SSRDR3_2 8 H'FF22D SSU_2 16 3P φ/3Pφ Port H realtime input data register PHRTIDR 8 H'FF240 PORT 16 3P φ/3Pφ A/D data register A_1 ADDRA_1 16 H'FFA90 A/D_1 16 2P φ/2Pφ A/D data register B_1 ADDRB_1 16 H'FFA92 A/D_1 16 2P φ/2Pφ A/D data register C_1 ADDRC_1 16 H'FFA94 A/D_1 16 2P φ/2Pφ A/D data register D_1 ADDRD_1 16 H'FFA96 A/D_1 16 2P φ/2Pφ A/D data register E_1 ADDRE_1 16 H'FFA98 A/D_1 16 2P φ/2Pφ A/D data register F_1 ADDRF_1 16 H'FFA9A A/D_1 16 2P φ/2Pφ A/D data register G_1 ADDRG_1 16 H'FFA9C A/D_1 16 2P φ/2Pφ A/D data register H_1 ADDRH_1 16 H'FFA9E A/D_1 16 2P φ/2Pφ A/D control/status register_1 ADCSR_1 8 H'FFAA0 A/D_1 16 2P φ/2Pφ A/D control register_1 ADCR_1 8 H'FFAA1 A/D_1 16 2P φ/2Pφ Timer start register TS TRB 8 H'FFB00 TPU 16 2P φ/2Pφ Timer synchronous register TSYRB 8 H'FFB01 TPU 16 2P φ/2Pφ

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 700 of 804 REJ09B0104-0300 Register Name Abbr. Number of Bits Address Module Data Width Access Cycles (Read/Write) Timer control register_6 TCR_6 8 H'FFB10 TPU_6 16 2P φ/2Pφ Timer mode register_6 TMDR_6 8 H'FFB11 TPU_6 16 2P φ/2Pφ Timer I/O control register H_6 TIORH_6 8 H'FFB12 TPU_6 16 2P φ/2Pφ Timer I/O control register L_6 TIORL_6 8 H'FFB13 TPU_6 16 2P φ/2Pφ Timer interrupt enable register_6 TIER_6 8 H'FFB14 TPU_6 16 2P φ/2Pφ Timer status register_6 TSR_6 8 H'FFB15 TPU_6 16 2P φ/2Pφ Timer counter _6 TCNT_6 16 H'FFB16 TPU_6 16 2P φ/2Pφ Timer general register A_6 TGRA_6 16 H'FFB18 TPU_6 16 2P φ/2Pφ Timer general register B_6 TGRB_6 16 H'FFB1A TPU_6 16 2P φ/2Pφ Timer general register C_6 TGRC_6 16 H'FFB1C TPU_6 16 2P φ/2Pφ Timer general register D_6 TGRD_6 16 H'FFB1E TPU_6 16 2P φ/2Pφ Timer control register_7 TCR_7 8 H'FFB20 TPU_7 16 2P φ/2Pφ Timer mode register_7 TMDR_7 8 H'FFB21 TPU_7 16 2P φ/2Pφ Timer I/O control register_7 TIOR_7 8 H'FFB22 TPU_7 16 2P φ/2Pφ Timer interrupt enable register_7 TIER_7 8 H'FFB24 TPU_7 16 2P φ/2Pφ Timer status register_7 TSR_7 8 H'FFB25 TPU_7 16 2P φ/2Pφ Timer counter _7 TCNT_7 16 H'FFB26 TPU_7 16 2P φ/2Pφ Timer general registerA_7 TGRA_7 16 H'FFB28 TPU_7 16 2P φ/2Pφ Timer general registerB_7 TGRB_7 16 H'FFB2A TPU_7 16 2P φ/2Pφ Timer control register_8 TCR_8 8 H'FFB30 TPU_8 16 2P φ/2Pφ Timer mode register_8 TMDR_8 8 H'FFB31 TPU_8 16 2P φ/2Pφ Timer I/O control register_8 TIOR_8 8 H'FFB32 TPU_8 16 2P φ/2Pφ Timer interrupt enable register_8 TIER_8 8 H'FFB34 TPU_8 16 2P φ/2Pφ Timer status register_8 TSR_8 8 H'FFB35 TPU_8 16 2P φ/2Pφ Timer counter _8 TCNT_8 16 H'FFB36 TPU_8 16 2P φ/2Pφ Timer general registerA_8 TGRA_8 16 H'FFB38 TPU_8 16 2P φ/2Pφ Timer general registerB_8 TGRB_8 16 H'FFB3A TPU_8 16 2P φ/2Pφ

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 701 of 804 REJ09B0104-0300 Register Name Abbr. Number of Bits Address Module Data Width Access Cycles (Read/Write) Timer control register_9 TCR_9 8 H'FFB40 TPU_9 16 2P φ/2Pφ Timer mode register_9 TMDR_9 8 H'FFB41 TPU_9 16 2P φ/2Pφ Timer I/O control register H_9 TIORH_9 8 H'FFB42 TPU_9 16 2P φ/2Pφ Timer I/O control register L_9 TIORL_9 8 H'FFB43 TPU_9 16 2P φ/2Pφ Timer interrupt enable register_9 TIER_9 8 H'FFB44 TPU_9 16 2P φ/2Pφ Timer status register_9 TSR_9 8 H'FFB45 TPU_9 16 2P φ/2Pφ Timer counter _9 TCNT_9 16 H'FFB46 TPU_9 16 2P φ/2Pφ Timer general registerA_9 TGRA_9 16 H'FFB48 TPU_9 16 2P φ/2Pφ Timer general registerB_9 TGRB_9 16 H'FFB4A TPU_9 16 2P φ/2Pφ Timer general registerC_9 TGRC_9 16 H'FFB4C TPU_9 16 2P φ/2Pφ Timer general registerD_9 TGRD_9 16 H'FFB4E TPU_9 16 2P φ/2Pφ Timer control register_10 TCR_10 8 H'FFB50 TPU_10 16 2P φ/2Pφ Timer mode register_10 TMDR_10 8 H'FFB51 TPU_10 16 2P φ/2Pφ Timer I/O control register_10 TIOR_10 8 H'FFB52 TPU_10 16 2P φ/2Pφ Timer interrupt enable register_10 TIER_10 8 H'FFB54 TPU_10 16 2P φ/2Pφ Timer status register_10 TSR_10 8 H'FFB55 TPU_10 16 2P φ/2Pφ Timer counter _10 TCNT_10 16 H'FFB56 TPU_10 16 2P φ/2Pφ Timer general registerA_10 TGRA_10 16 H'FFB58 TPU_10 16 2P φ/2Pφ Timer general registerB_10 TGRB_10 16 H'FFB5A TPU_10 16 2P φ/2Pφ Timer control register_11 TCR_11 8 H'FFB60 TPU_11 16 2P φ/2Pφ Timer mode register_11 TMDR_11 8 H'FFB61 TPU_11 16 2P φ/2Pφ Timer I/O control register_11 TIOR_11 8 H'FFB62 TPU_11 16 2P φ/2Pφ Timer interrupt enable register_11 TIER_11 8 H'FFB64 TPU_11 16 2P φ/2Pφ Timer status register_11 TSR_11 8 H'FFB65 TPU_11 16 2P φ/2Pφ Timer counter _11 TCNT_11 16 H'FFB66 TPU_11 16 2P φ/2Pφ Timer general registerA_11 TGRA_11 16 H'FFB68 TPU_11 16 2P φ/2Pφ Timer general registerB_11 TGRB_11 16 H'FFB6A TPU_11 16 2P φ/2Pφ

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 702 of 804 REJ09B0104-0300 Register Name Abbr. Number of Bits Address Module Data Width Access Cycles (Read/Write) Port 1 data direction register P1DDR 8 H'FFB80 I/O port 8 2P φ/2Pφ Port 2 data direction register P2DDR 8 H'FFB81 I/O port 8 2P φ/2Pφ Port 3 data direction register P3DDR 8 H'FFB82 I/O port 8 2P φ/2Pφ Port 6 data direction register P6DDR 8 H'FFB85 I/O port 8 2P φ/2Pφ Port A data direction register PADDR 8 H'FFB89 I/O port 8 2P φ/2Pφ Port D data direction register PDDDR 8 H'FFB8C I/O port 8 2P φ/2Pφ Port 1 input buffer control register P1ICR 8 H'FFB90 I/O port 8 2P φ/2Pφ Port 2 input buffer control register P2ICR 8 H'FFB91 I/O port 8 2P φ/2Pφ Port 3 input buffer control register P3ICR 8 H'FFB92 I/O port 8 2P φ/2Pφ Port 4 input buffer control register P4ICR 8 H'FFB93 I/O port 8 2P φ/2Pφ Port 5 input buffer control register P5ICR 8 H'FFB94 I/O port 8 2P φ/2Pφ Port 6 input buffer control register P6ICR 8 H'FFB95 I/O port 8 2P φ/2Pφ Port A input buffer control register PAICR 8 H'FFB99 I/O port 8 2P φ/2Pφ Port D input buffer control register PDICR 8 H'FFB9C I/O port 8 2P φ/2Pφ Port H register PORTH 8 H'FFBA0 I/O port 8 2P φ/2Pφ Port J register PORTJ 8 H'FFBA2 I/O port 8 2P φ/2Pφ Port K register PORTK 8 H'FFBA3 I/O port 8 2P φ/2Pφ Port H data register PHDR 8 H'FFBA4 I/O port 8 2P φ/2Pφ Port J data register PJDR 8 H'FFBA6 I/O port 8 2P φ/2Pφ Port K data register PKDR 8 H'FFBA7 I/O port 8 2P φ/2Pφ

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 703 of 804 REJ09B0104-0300 Register Name Abbr. Number of Bits Address Module Data Width Access Cycles (Read/Write) Port H data direction register PHDDR 8 H'FFBA8 I/O port 8 2P φ/2Pφ Port J data direction register PJDDR 8 H'FFBAA I/O port 8 2P φ/2Pφ Port K data direction register PKDDR 8 H'FFBAB I/O port 8 2P φ/2Pφ Port H input buffer control register PHICR 8 H'FFBAC I/O port 8 2P φ/2Pφ Port J input buffer control register PJICR 8 H'FFBAE I/O port 8 2P φ/2Pφ Port K input buffer control register PKICR 8 H'FFBAF I/O port 8 2P φ/2Pφ Port D pull-up MOS control register PDPCR 8 H'FFBB4 I/O port 8 2P φ/2Pφ Port H pull-up MOS control register PHPCR 8 H'FFBB8 I/O port 8 2P φ/2Pφ Port J pull-up MOS control register PJPCR 8 H'FFBBA I/O port 8 2P φ/2Pφ Port K pull-up MOS control register PKPCR 8 H'FFBBB I/O port 8 2P φ/2Pφ Port 2 open drain control register P2ODR 8 H'FFBBC I/O port 8 2P φ/2Pφ Port function control register 9 PFCR9 8 H'FFBC9 I/O port 8 2P φ/3Pφ Port function control register A PFCRA 8 H'FFBCA I/O port 8 2P φ/3Pφ Port function control register B PFCRB 8 H'FFBCB I/O port 8 2P φ/3Pφ Software standby release IRQ enable register SSIER 16 H'FFBCE INTC 8 2P φ/3Pφ DMA source address register_0 DSAR_0 32 H'FFC00 DMAC_0 16 2I φ/2Iφ DMA destination address register_0 DDAR_0 32 H'FFC04 DMAC_0 16 2I φ/2Iφ DMA offset register_0 DOFR_0 32 H'FFC08 DMAC_0 16 2I φ/2Iφ DMA transfer count register_0 DTCR_0 32 H'FFC0C DMAC_0 16 2I φ/2Iφ DMA block size register_0 DBSR_0 32 H'FFC10 DMAC_0 16 2I φ/2Iφ DMA mode control register_0 DMDR_0 32 H'FFC14 DMAC_0 16 2I φ/2Iφ DMA address control register_0 DACR_0 32 H'FFC18 DMAC_0 16 2I φ/2Iφ

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 704 of 804 REJ09B0104-0300 Register Name Abbr. Number of Bits Address Module Data Width Access Cycles (Read/Write) DMA source address register_1 DSAR_1 32 H'FFC20 DMAC_1 16 2I φ/2Iφ DMA destination address register_1 DDAR_1 32 H'FFC24 DMAC_1 16 2I φ/2Iφ DMA offset register_1 DOFR_1 32 H'FFC28 DMAC_1 16 2I φ/2Iφ DMA transfer count register_1 DTCR_1 32 H'FFC2C DMAC_1 16 2I φ/2Iφ DMA block size register_1 DBSR_1 32 H'FFC30 DMAC_1 16 2I φ/2Iφ DMA mode control register_1 DMDR_1 32 H'FFC34 DMAC_1 16 2I φ/2Iφ DMA address control register_1 DACR_1 32 H'FFC38 DMAC_1 16 2I φ/2Iφ DMA source address register_2 DSAR_2 32 H'FFC40 DMAC_2 16 2I φ/2Iφ DMA destination address register_2 DDAR_2 32 H'FFC44 DMAC_2 16 2I φ/2Iφ DMA offset register_2 DOFR_2 32 H'FFC48 DMAC_2 16 2I φ/2Iφ DMA transfer count register_2 DTCR_2 32 H'FFC4C DMAC_2 16 2I φ/2Iφ DMA block size register_2 DBSR_2 32 H'FFC50 DMAC_2 16 2I φ/2Iφ DMA mode control register_2 DMDR_2 32 H'FFC54 DMAC_2 16 2I φ/2Iφ DMA address control register_2 DACR_2 32 H'FFC58 DMAC_2 16 2I φ/2Iφ DMA source address register_3 DSAR_3 32 H'FFC60 DMAC_3 16 2I φ/2Iφ DMA destination address register_3 DDAR_3 32 H'FFC64 DMAC_3 16 2I φ/2Iφ DMA offset register_3 DOFR_3 32 H'FFC68 DMAC_3 16 2I φ/2Iφ DMA transfer count register_3 DTCR_3 32 H'FFC6C DMAC_3 16 2I φ/2Iφ DMA block size register_3 DBSR_3 32 H'FFC70 DMAC_3 16 2I φ/2Iφ DMA mode control register_3 DMDR_3 32 H'FFC74 DMAC_3 16 2I φ/2Iφ DMA address control register_3 DACR_3 32 H'FFC78 DMAC_3 16 2I φ/2Iφ

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 705 of 804 REJ09B0104-0300 Register Name Abbr. Number of Bits Address Module Data Width Access Cycles (Read/Write) DMA module request select register_0 DMRSR_0 8 H'FFD20 DMAC_0 16 2I φ/2Iφ DMA module request select register_1 DMRSR_1 8 H'FFD21 DMAC_1 16 2I φ/2Iφ DMA module request select register_2 DMRSR_2 8 H'FFD22 DMAC_2 16 2I φ/2Iφ DMA module request select register_3 DMRSR_3 8 H'FFD23 DMAC_3 16 2I φ/2Iφ Interrupt priority register A IPRA 16 H'FFD40 INTC 16 2I φ/3Iφ Interrupt priority register B IPRB 16 H'FFD42 INTC 16 2I φ/3Iφ Interrupt priority register C IPRC 16 H'FFD44 INTC 16 2I φ/3Iφ Interrupt priority register D IPRD 16 H'FFD46 INTC 16 2I φ/3Iφ Interrupt priority register E IPRE 16 H'FFD48 INTC 16 2I φ/3Iφ Interrupt priority register F IPRF 16 H'FFD4A INTC 16 2I φ/3Iφ Interrupt priority register G IPRG 16 H'FFD4C INTC 16 2I φ/3Iφ Interrupt priority register I IPRI 16 H'FFD50 INTC 16 2I φ/3Iφ Interrupt priority register K IPRK 16 H'FFD54 INTC 16 2I φ/3Iφ Interrupt priority register L IPRL 16 H'FFD56 INTC 16 2I φ/3Iφ Interrupt priority register M IPRM 16 H'FFD58 INTC 16 2I φ/3Iφ Interrupt priority register N IPRN 16 H'FFD5A INTC 16 2I φ/3Iφ Interrupt priority register O IPRO 16 H'FFD5C INTC 16 2I φ/3Iφ Interrupt priority register Q IPRQ 16 H'FFD60 INTC 16 2I φ/3Iφ Interrupt priority register R IPRR 16 H'FFD62 INTC 16 2I φ/3Iφ IRQ sense control register H ISCRH 16 H'FFD68 INTC 16 2I φ/3Iφ IRQ sense control register L ISCRL 16 H'FFD6A INTC 16 2I φ/3Iφ Bus control register 2 BCR2 8 H'FFD94 BSC 16 2I φ/3Iφ RAM emulation register RAMER 8 H'FFD9E BSC 16 2I φ/3Iφ Mode control register MDCR 16 H'FFDC0 SYSTEM 16 2I φ/3Iφ

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 706 of 804 REJ09B0104-0300 Register Name Abbr. Number of Bits Address Module Data Width Access Cycles (Read/Write) System control register SYSCR 16 H'FFDC2 SYSTEM 16 2I φ/3Iφ System clock control register SCKCR 16 H'FFDC4 SYSTEM 16 2I φ/3Iφ Standby control register SBYCR 16 H'FFDC6 SYSTEM 16 2I φ/3Iφ Module stop control register A MSTPCRA 16 H'FFDC8 SYSTEM 16 2I φ/3Iφ Module stop control register B MSTPCRB 16 H'FFDCA SYSTEM 16 2I φ/3Iφ Module stop control register C MSTPCRC 16 H'FFDCC SYSTEM 16 2I φ/3Iφ Serial mode register_3 SMR_3 8 H'FFE88 SCI_3 8 2P φ/2Pφ Bit rate register_3 BRR_3 8 H'FFE89 SCI_3 8 2P φ/2Pφ Serial control register_3 SCR_3 8 H'FFE8A SCI_3 8 2P φ/2Pφ Transmit data register_3 TDR_3 8 H'FFE8B SCI_3 8 2P φ/2Pφ Serial status register_3 SSR_3 8 H'FFE8C SCI_3 8 2P φ/2Pφ Receive data register_3 RDR_3 8 H'FFE8D SCI_3 8 2P φ/2Pφ Smart card mode register_3 SCMR_3 8 H'FFE8E SCI_3 8 2P φ/2Pφ Serial mode register_4 SMR_4 8 H'FFE90 SCI_4 8 2P φ/2Pφ Bit rate register_4 BRR_4 8 H'FFE91 SCI_4 8 2P φ/2Pφ Serial control register_4 SCR_4 8 H'FFE92 SCI_4 8 2P φ/2Pφ Transmit data register_4 TDR_4 8 H'FFE93 SCI_4 8 2P φ/2Pφ Serial status register_4 SSR_4 8 H'FFE94 SCI_4 8 2P φ/2Pφ Receive data register_4 RDR_4 8 H'FFE95 SCI_4 8 2P φ/2Pφ Smart card mode register_4 SCMR_4 8 H'FFE96 SCI_4 8 2P φ/2Pφ Flash code control/status register FCCS 8 H'FFEA8 FLASH 8 2P φ/2Pφ Flash program code select register FPCS 8 H'FFEA9 FLASH 8 2P φ/2Pφ Flash erase code select register FECS 8 H'FFEAA FLASH 8 2P φ/2Pφ Flash key code register FKEY 8 H'FFEAC FLASH 8 2P φ/2Pφ Flash MAT select register FMATS 8 H'FFEAD FLASH 8 2P φ/2Pφ Flash transfer destination address register FTDAR 8 H'FFEAE FLASH 8 2P φ/2Pφ

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 707 of 804 REJ09B0104-0300 Register Name Abbr. Number of Bits Address Module Data Width Access Cycles (Read/Write) Timer control register_4 TCR_4 8 H'FFEE0 TPU_4 * 16 2P φ/2Pφ Timer mode register_4 TMDR_4 8 H'FFEE1 TPU_4 * 16 2P φ/2Pφ Timer I/O control register_4 TIOR_4 8 H'FFEE2 TPU_4 * 16 2P φ/2Pφ Timer interrupt enable register_4 TIER_4 8 H'FFEE4 TPU_4 * 16 2P φ/2Pφ Timer status register_4 TSR_4 8 H'FFEE5 TPU_4 * 16 2P φ/2Pφ Timer counter_4 TCNT_4 16 H'FFEE6 TPU_4 * 16 2P φ/2Pφ Timer general registerA_4 TGRA_4 16 H'FFEE8 TPU_4 * 16 2P φ/2Pφ Timer general registerB_4 TGRB_4 16 H'FFEEA TPU_4 * 16 2P φ/2Pφ Timer control register_5 TCR_5 8 H'FFEF0 TPU_5 * 16 2P φ/2Pφ Timer mode register_5 TMDR_5 8 H'FFEF1 TPU_5 * 16 2P φ/2Pφ Timer I/O control register_5 TIOR_5 8 H'FFEF2 TPU_5 * 16 2P φ/2Pφ Timer interrupt enable register_5 TIER_5 8 H'FFEF4 TPU_5 * 16 2P φ/2Pφ Timer status register_5 TSR_5 8 H'FFEF5 TPU_5 * 16 2P φ/2Pφ Timer counter_5 TCNT_5 16 H'FFEF6 TPU_5 * 16 2P φ/2Pφ Timer general registerA_5 TGRA_5 16 H'FFEF8 TPU_5 * 16 2P φ/2Pφ Timer general registerB_5 TGRB_5 16 H'FFEFA TPU_5 * 16 2P φ/2Pφ Interrupt control register INTCR 8 H'FFF32 INTC 16 2I φ/3Iφ CPU priority control register CPUPCR 8 H'FFF33 INTC 16 2I φ/3Iφ IRQ enable register IER 16 H'FFF34 INTC 16 2I φ/3Iφ IRQ status register ISR 16 H'FFF36 INTC 16 2I φ/3Iφ Port 1 register PORT1 8 H'FFF40 I/O port 8 2P φ/- Port 2 register PORT2 8 H'FFF41 I/O port 8 2P φ/- Port 3 register PORT3 8 H'FFF42 I/O port 8 2P φ/- Port 4 register PORT4 8 H'FFF43 I/O port 8 2P φ/- Port 5 register PORT5 8 H'FFF44 I/O port 8 2P φ/- Port 6 register PORT6 8 H'FFF45 I/O port 8 2P φ/- Port A register PORTA 8 H'FFF49 I/O port 8 2P φ/- Port D register PORTD 8 H'FFF4C I/O port 8 2P φ/-

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 708 of 804 REJ09B0104-0300 Register Name Abbr. Number of Bits Address Module Data Width Access Cycles (Read/Write) Port 1 data register P1DR 8 H'FFF50 I/O port 8 2P φ/2Pφ Port 2 data register P2DR 8 H'FFF51 I/O port 8 2P φ/2Pφ Port 3 data register P3DR 8 H'FFF52 I/O port 8 2P φ/2Pφ Port 6 data register P6DR 8 H'FFF55 I/O port 8 2P φ/2Pφ Port A data register PADR 8 H'FFF59 I/O port 8 2P φ/2Pφ Port D data register PDDR 8 H'FFF5C I/O port 8 2P φ/2Pφ PPG output control register PCR 8 H'FFF76 PPG * 8 2P φ/2Pφ PPG output mode register PMR 8 H'FFF77 PPG * 8 2P φ/2Pφ Next data enable register H NDERH 8 H'FFF78 PPG * 8 2P φ/2Pφ Next data enable register L NDERL 8 H'FFF79 PPG * 8 2P φ/2Pφ Output data register H PODRH 8 H'FFF7A PPG * 8 2P φ/2Pφ Output data register L PODRL 8 H'FFF7B PPG * 8 2P φ/2Pφ Next data register H NDRH 8 H'FFF7C PPG * 8 2P φ/2Pφ Next data register L NDRL 8 H'FFF7D PPG * 8 2P φ/2Pφ Next data register H NDRH 8 H'FFF7E PPG * 8 2P φ/2Pφ Next data register L NDRL 8 H'FFF7F PPG * 8 2P φ/2Pφ A/D data registerA_0 ADDRA_0 16 H'FFF90 A/D_0 16 2P φ/2Pφ A/D data registerB_0 ADDRB_0 16 H'FFF92 A/D_0 16 2P φ/2Pφ A/D data registerC_0 ADDRC_0 16 H'FFF94 A/D_0 16 2P φ/2Pφ A/D data registerD_0 ADDRD_0 16 H'FFF96 A/D_0 16 2P φ/2Pφ A/D data registerE_0 ADDRE_0 16 H'FFF98 A/D_0 16 2P φ/2Pφ A/D data registerF_0 ADDRF_0 16 H'FFF9A A/D_0 16 2P φ/2Pφ A/D data registerG_0 ADDRG_0 16 H'FFF9C A/D_0 16 2P φ/2Pφ A/D data register H_0 ADDRH_0 16 H'FFF9E A/D_0 16 2P φ/2Pφ A/D control/status register_0 ADCSR_0 8 H'FFFA0 A/D_0 16 2P φ/2Pφ A/D control register_0 ADCR_0 8 H'FFFA1 A/D_0 16 2P φ/2Pφ Timer control/status register TCSR 8 H'FFFA4 WDT 2P φ/3Pφ Timer counter TCNT 8 H'FFFA5 WDT 2P φ/3Pφ Reset control/status register RSTCSR 8 H'FFFA7 WDT 2P φ/3Pφ

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 709 of 804 REJ09B0104-0300 Register Name Abbr. Number of Bits Address Module Data Width Access Cycles (Read/Write) Timer start register TSTR 8 H'FFFBC TPU * 16 2P φ/2Pφ Timer synchronous register TSYR 8 H'FFFBD TPU * 16 2P φ/2Pφ Timer control register_0 TCR_0 8 H'FFFC0 TPU_0 * 16 2P φ/2Pφ Timer mode register_0 TMDR_0 8 H'FFFC1 TPU_0 * 16 2P φ/2Pφ Timer I/O control register H_0 TIORH_0 8 H'FFFC2 TPU_0 * 16 2P φ/2Pφ Timer I/O control register L_0 TIORL_0 8 H'FFFC3 TPU_0 * 16 2P φ/2Pφ Timer interrupt enable register_0 TIER_0 8 H'FFFC4 TPU_0 * 16 2P φ/2Pφ Timer status register_0 TSR_0 8 H'FFFC5 TPU_0 * 16 2P φ/2Pφ Timer counter_0 TCNT_0 16 H'FFFC6 TPU_0 * 16 2P φ/2Pφ Timer general register A_0 TGRA_0 16 H'FFFC8 TPU_0 * 16 2P φ/2Pφ Timer general register B_0 TGRB_0 16 H'FFFCA TPU_0 * 16 2P φ/2Pφ Timer general register C_0 TGRC_0 16 H'FFFCC TPU_0 * 16 2P φ/2Pφ Timer general register D_0 TGRD_0 16 H'FFFCE TPU_0 * 16 2P φ/2Pφ Timer control register_1 TCR_1 8 H'FFFD0 TPU_1 * 16 2P φ/2Pφ Timer mode register_1 TMDR_1 8 H'FFFD1 TPU_1 * 16 2P φ/2Pφ Timer I/control register_1 TIOR_1 8 H'FFFD2 TPU_1 * 16 2P φ/2Pφ Timer interrupt enable register_1 TIER_1 8 H'FFFD4 TPU_1 * 16 2P φ/2Pφ Timer status register_1 TSR_1 8 H'FFFD5 TPU_1 * 16 2P φ/2Pφ Timer counter_1 TCNT_1 16 H'FFFD6 TPU_1 * 16 2P φ/2Pφ Timer general register A_1 TGRA_1 16 H'FFFD8 TPU_1 * 16 2P φ/2Pφ Timer general register B_1 TGRB_1 16 H'FFFDA TPU_1 * 16 2P φ/2Pφ Timer control register_2 TCR_2 8 H'FFFE0 TPU_2 * 16 2P φ/2Pφ Timer mode register_2 TMDR_2 8 H'FFFE1 TPU_2 * 16 2P φ/2Pφ Timer I/O control register_2 TIOR_2 8 H'FFFE2 TPU_2 * 16 2P φ/2Pφ Timer interrupt enable register_2 TIER_2 8 H'FFFE4 TPU_2 * 16 2P φ/2Pφ Timer status register_2 TSR_2 8 H'FFFE5 TPU_2 * 16 2P φ/2Pφ

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 710 of 804 REJ09B0104-0300 Register Name Abbr. Number of Bits Address Module Data Width Access Cycles (Read/Write) Timer counter_2 TCNT_2 16 H'FFFE6 TPU_2 * 16 2P φ/2Pφ Timer general registerA_2 TGRA_2 16 H'FFFE8 TPU_2 * 16 2P φ/2Pφ Timer general registerB_2 TGRB_2 16 H'FFFEA TPU_2 * 16 2P φ/2Pφ Timer control register_3 TCR_3 8 H'FFFF0 TPU_3 * 16 2P φ/2Pφ Timer mode register_3 TMDR_3 8 H'FFFF1 TPU_3 * 16 2P φ/2Pφ Timer I/O control register H_3 TIORH_3 8 H'FFFF2 TPU_3 * 16 2P φ/2Pφ Timer I/O control register L_3 TIORL_3 8 H'FFFF3 TPU_3 * 16 2P φ/2Pφ Timer interrupt enable register_3 TIER_3 8 H'FFFF4 TPU_3 * 16 2P φ/2Pφ Timer status register_3 TSR_3 8 H'FFFF5 TPU_3 * 16 2P φ/2Pφ Timer counter_3 TCNT_3 16 H'FFFF6 TPU_3 * 16 2P φ/2Pφ Timer general register A_3 TGRA_3 16 H'FFFF8 TPU_3 * 16 2P φ/2Pφ Timer general register B_3 TGRB_3 16 H'FFFFA TPU_3 * 16 2P φ/2Pφ Timer general register C_3 TGRC_3 16 H'FFFFC TPU_3 * 16 2P φ/2Pφ Timer general register D_3 TGRD_3 16 H'FFFFE TPU_3 * 16 2P φ/2Pφ Notes: 1. The lower 20 bits are indicated. 2. Supported only by the H8SX/1527.

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 711 of 804 REJ09B0104-0300

20.2 Register Bits

Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit and 32-bit registers are shown as 2 or 4 lines, respectively. Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module MCR MCR7  MCR5   MCR2 MCR1 MCR0 HCAN GSR     GSR3 GSR2 GSR1 GSR0 BCR BCR7 BCR6 BCR5 BCR4 BCR3 BCR2 BCR1 BCR0 BCR15 BCR14 BCR13 BCR12 BCR11 BCR10 BCR9 BCR8 MBCR MBCR7 MBCR6 MBCR5 MB CR4 MBCR3 MBCR2 MBCR1  MBCR15 MBCR14 MBCR13 MBCR12 MBCR11 MBCR10 MBCR9 MBCR8 TXPR TXPR7 TXPR6 TXPR5 TXPR4 TXPR3 TXPR2 TXPR1  TXPR15 TXPR14 TXPR 13 TXPR12 TXPR11 TXPR 10 TXPR9 TXPR8 TXCR TXCR7 TXCR6 TXCR5 TX CR4 TXCR3 TXCR2 TXCR1  TXCR15 TXCR14 TXCR13 TXCR12 TXCR11 TXCR10 TXCR9 TXCR8 TXACK TXACK7 TXACK6 TXACK5 T XACK4 TXACK3 TXACK2 TXACK1  TXACK15 TXACK14 TXACK 13 TXACK12 TXACK11 TXAC K10 TXACK9 TXACK8 ABACK ABACK7 ABACK6 ABACK5 ABAC K4 ABACK3 ABACK2 ABACK1  ABACK15 ABACK14 ABACK13 ABACK12 ABACK11 ABACK10 ABACK9 ABACK8 RXPR RXPR7 RXPR6 R XPR5 RXPR4 RXPR3 R XPR2 RXPR1 RXPR0 RXPR15 RXPR14 RXPR 13 RXPR12 RXPR11 RXPR 10 RXPR9 RXPR8 RFPR RFPR7 RFPR6 RFPR5 RFPR 4 RFPR3 RFPR2 RFPR1 RFPR0 RFPR15 RFPR14 RFPR13 RFPR12 RFPR11 RFPR10 RFPR9 RFPR8 IRR IRR7 IRR6 IRR5 IRR4 IRR3 IRR2 IRR1 IRR0    IRR12   IRR9 IRR8 MBIMR MBIMR7 MBIMR6 MBIMR5 MBIMR4 MBIMR3 MBIMR2 MBIMR1 MBIMR0 MBIMR15 MBIMR14 MBIMR 13 MBIMR12 MBIMR11 MBIM R10 MBIMR9 MBIMR8 IMR IMR7 IMR6 IMR5 IMR4 IMR3 IMR2 IMR1     IMR12   IMR9 IMR8 R E C

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 712 of 804 REJ09B0104-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module T E C H C A N UMSR UMSR7 UMSR6 UMSR5 UMSR 4 UMSR3 UMSR2 UMSR1 UMSR0 UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 UMSR9 UMSR8 LAFML LAFML7 LAFML6 LAFML5 LAFM L4 LAFML3 LAFML2 LAFML1 LAFML0 LAFML15 LAFML14 LAFML13 LAFML12 LAFML11 LAFML10 LAFML9 LAFML8 LAFMH LAFMH7 LAFMH6 LAFMH5    LAFMH1 LAFMH0 LAFMH15 LAFMH14 LAFMH13 LAFMH12 LAFMH11 LAFMH10 LAFMH9 LAFMH8 MC0[1]     DLC3 DLC2 DLC1 DLC0 MC0[5] ID-20 ID- 19 ID-18 RTR IDE  ID-17 ID-16 MC0[6] ID-28 ID-27 ID-26 ID- 25 ID-24 ID-23 ID-22 ID-21 MC0[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC0[8] ID-15 ID-14 ID-13 ID- 12 ID-11 ID-10 ID-9 ID-8 MC1[1]     DLC3 DLC2 DLC1 DLC0 MC1[5] ID-20 ID- 19 ID-18 RTR IDE  ID-17 ID-16 MC1[6] ID-28 ID-27 ID-26 ID- 25 ID-24 ID-23 ID-22 ID-21 MC1[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC1[8] ID-15 ID-14 ID-13 ID- 12 ID-11 ID-10 ID-9 ID-8 MC2[1]     DLC3 DLC2 DLC1 DLC0 MC2[5] ID-20 ID- 19 ID-18 RTR IDE  ID-17 ID-16 MC2[6] ID-28 ID-27 ID-26 ID- 25 ID-24 ID-23 ID-22 ID-21 MC2[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC2[8] ID-15 ID-14 ID-13 ID- 12 ID-11 ID-10 ID-9 ID-8

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 713 of 804 REJ09B0104-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module MC3[1]     DLC3 DLC2 DLC1 DLC0 HCAN MC3[5] ID-20 ID- 19 ID-18 RTR IDE  ID-17 ID-16 MC3[6] ID-28 ID-27 ID-26 ID- 25 ID-24 ID-23 ID-22 ID-21 MC3[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC3[8] ID-15 ID-14 ID-13 ID- 12 ID-11 ID-10 ID-9 ID-8 MC4[1]     DLC3 DLC2 DLC1 DLC0 MC4[5] ID-20 ID- 19 ID-18 RTR IDE  ID-17 ID-16 MC4[6] ID-28 ID-27 ID-26 ID- 25 ID-24 ID-23 ID-22 ID-21 MC4[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC4[8] ID-15 ID-14 ID-13 ID- 12 ID-11 ID-10 ID-9 ID-8 MC5[1]     DLC3 DLC2 DLC1 DLC0 MC5[5] ID-20 ID- 19 ID-18 RTR IDE  ID-17 ID-16 MC5[6] ID-28 ID-27 ID-26 ID- 25 ID-24 ID-23 ID-22 ID-21 MC5[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC5[8] ID-15 ID-14 ID-13 ID- 12 ID-11 ID-10 ID-9 ID-8 MC6[1]     DLC3 DLC2 DLC1 DLC0

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 714 of 804 REJ09B0104-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module MC6[5] ID-20 ID- 19 ID-18 RTR IDE  ID-17 ID-16 HCAN MC6[6] ID-28 ID-27 ID-26 ID- 25 ID-24 ID-23 ID-22 ID-21 MC6[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC6[8] ID-15 ID-14 ID-13 ID- 12 ID-11 ID-10 ID-9 ID-8 MC7[1]     DLC3 DLC2 DLC1 DLC0 MC7[5] ID-20 ID- 19 ID-18 RTR IDE  ID-17 ID-16 MC7[6] ID-28 ID-27 ID-26 ID- 25 ID-24 ID-23 ID-22 ID-21 MC7[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC7[8] ID-15 ID-14 ID-13 ID- 12 ID-11 ID-10 ID-9 ID-8 MC8[1]     DLC3 DLC2 DLC1 DLC0 MC8[5] ID-20 ID- 19 ID-18 RTR IDE  ID-17 ID-16 MC8[6] ID-28 ID-27 ID-26 ID- 25 ID-24 ID-23 ID-22 ID-21 MC8[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC8[8] ID-15 ID-14 ID-13 ID- 12 ID-11 ID-10 ID-9 ID-8 MC9[1]     DLC3 DLC2 DLC1 DLC0 MC9[5] ID-20 ID- 19 ID-18 RTR IDE  ID-17 ID-16 MC9[6] ID-28 ID-27 ID-26 ID- 25 ID-24 ID-23 ID-22 ID-21 MC9[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC9[8] ID-15 ID-14 ID-13 ID- 12 ID-11 ID-10 ID-9 ID-8

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 715 of 804 REJ09B0104-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module MC10[1]     DLC3 DLC2 DLC1 DLC0 HCAN MC10[5] ID-20 ID- 19 ID-18 RTR IDE  ID-17 ID-16 MC10[6] ID-28 ID-27 ID-26 ID- 25 ID-24 ID-23 ID-22 ID-21 MC10[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC10[8] ID-15 ID-14 ID-13 ID- 12 ID-11 ID-10 ID-9 ID-8 MC11[1]     DLC3 DLC2 DLC1 DLC0 MC11[5] ID-20 ID- 19 ID-18 RTR IDE  ID-17 ID-16 MC11[6] ID-28 ID-27 ID-26 ID- 25 ID-24 ID-23 ID-22 ID-21 MC11[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC11[8] ID-15 ID-14 ID-13 ID- 12 ID-11 ID-10 ID-9 ID-8 MC12[1]     DLC3 DLC2 DLC1 DLC0 MC12[5] ID-20 ID- 19 ID-18 RTR IDE  ID-17 ID-16 MC12[6] ID-28 ID-27 ID-26 ID- 25 ID-24 ID-23 ID-22 ID-21 MC12[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC12[8] ID-15 ID-14 ID-13 ID- 12 ID-11 ID-10 ID-9 ID-8 MC13[1]     DLC3 DLC2 DLC1 DLC0

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 716 of 804 REJ09B0104-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module MC13[5] ID-20 ID- 19 ID-18 RTR IDE  ID-17 ID-16 HCAN MC13[6] ID-28 ID-27 ID-26 ID- 25 ID-24 ID-23 ID-22 ID-21 MC13[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC13[8] ID-15 ID-14 ID-13 ID- 12 ID-11 ID-10 ID-9 ID-8 MC14[1]     DLC3 DLC2 DLC1 DLC0 MC14[5] ID-20 ID- 19 ID-18 RTR IDE  ID-17 ID-16 MC14[6] ID-28 ID-27 ID-26 ID- 25 ID-24 ID-23 ID-22 ID-21 MC14[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC14[8] ID-15 ID-14 ID-13 ID- 12 ID-11 ID-10 ID-9 ID-8 MC15[1]     DLC3 DLC2 DLC1 DLC0 MC15[5] ID-20 ID- 19 ID-18 RTR IDE  ID-17 ID-16 MC15[6] ID-28 ID-27 ID-26 ID- 25 ID-24 ID-23 ID-22 ID-21 MC15[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC15[8] ID-15 ID-14 ID-13 ID- 12 ID-11 ID-10 ID-9 ID-8 M D 0 [ 1 ] M D 0 [ 2 ] M D 0 [ 3 ] M D 0 [ 4 ] M D 0 [ 5 ] M D 0 [ 6 ] M D 0 [ 7 ] M D 0 [ 8 ]

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 717 of 804 REJ09B0104-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module M D 1 [ 1 ] H C A N M D 1 [ 2 ] M D 1 [ 3 ] M D 1 [ 4 ] M D 1 [ 5 ] M D 1 [ 6 ] M D 1 [ 7 ] M D 1 [ 8 ] M D 2 [ 1 ] M D 2 [ 2 ] M D 2 [ 3 ] M D 2 [ 4 ] M D 2 [ 5 ] M D 2 [ 6 ] M D 2 [ 7 ] M D 2 [ 8 ] M D 3 [ 1 ] M D 3 [ 2 ] M D 3 [ 3 ] M D 3 [ 4 ] M D 3 [ 5 ] M D 3 [ 6 ] M D 3 [ 7 ] M D 3 [ 8 ] M D 4 [ 1 ] M D 4 [ 2 ] M D 4 [ 3 ] M D 4 [ 4 ]

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 718 of 804 REJ09B0104-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module M D 4 [ 5 ] H C A N M D 4 [ 6 ] M D 4 [ 7 ] M D 4 [ 8 ] M D 5 [ 1 ] M D 5 [ 2 ] M D 5 [ 3 ] M D 5 [ 4 ] M D 5 [ 5 ] M D 5 [ 6 ] M D 5 [ 7 ] M D 5 [ 8 ] M D 6 [ 1 ] M D 6 [ 2 ] M D 6 [ 3 ] M D 6 [ 4 ] M D 6 [ 5 ] M D 6 [ 6 ] M D 6 [ 7 ] M D 6 [ 8 ] M D 7 [ 1 ] M D 7 [ 2 ] M D 7 [ 3 ] M D 7 [ 4 ] M D 7 [ 5 ] M D 7 [ 6 ] M D 7 [ 7 ] M D 7 [ 8 ]

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 719 of 804 REJ09B0104-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module M D 8 [ 1 ] H C A N M D 8 [ 2 ] M D 8 [ 3 ] M D 8 [ 4 ] M D 8 [ 5 ] M D 8 [ 6 ] M D 8 [ 7 ] M D 8 [ 8 ] M D 9 [ 1 ] M D 9 [ 2 ] M D 9 [ 3 ] M D 9 [ 4 ] M D 9 [ 5 ] M D 9 [ 6 ] M D 9 [ 7 ] M D 9 [ 8 ] MD10[1] MD10[2] MD10[3] MD10[4] MD10[5] MD10[6] MD10[7] MD10[8] MD11[1] MD11[2] MD11[3] MD11[4]

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 720 of 804 REJ09B0104-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module MD11[5] HCAN MD11[6] MD11[7] MD11[8] MD12[1] MD12[2] MD12[3] MD12[4] MD12[5] MD12[6] MD12[7] MD12[8] MD13[1] MD13[2] MD13[3] MD13[4] MD13[5] MD13[6] MD13[7] MD13[8] MD14[1] MD14[2] MD14[3] MD14[4] MD14[5] MD14[6] MD14[7] MD14[8]

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 721 of 804 REJ09B0104-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module MD15[1] HCAN MD15[2] MD15[3] MD15[4] MD15[5] MD15[6] MD15[7] MD15[8] HCANMON  TxSTP HCANE    TxD RxD SSCRH_0 MSS BIDE  SOL SOLP SCKS CSS1 CSS0 SSU_0 SSCRL_0  SSUMS SRES    DATS1 DATS0 SSMR_0 MLS CPOS CPHS   CKS2 CKS1 CKS0 SSER_0 TE RE   TEIE TIE RIE CEIE SSSR_0  ORER   TEND TDRE RDRF CE SSCR2_0 SDOS SSCKOS SCSO S TENDSTS SCSATS SSODTS   SSTDR0_0 SSTDR1_0 SSTDR2_0 SSTDR3_0 SSRDR0_0 SSRDR1_0 SSRDR2_0 SSRDR3_0 SSCRH_1 MSS BIDE  SOL SOLP SCKS CSS1 CSS0 SSU_1 SSCRL_1  SSUMS SRES    DATS1 DATS0 SSMR_1 MLS CPOS CPHS   CKS2 CKS1 CKS0 SSER_1 TE RE   TEIE TIE RIE CEIE SSSR_1  ORER   TEND TDRE RDRF CE SSCR2_1 SDOS SSCKOS SCSO S TENDSTS SCSATS SSODTS  

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 722 of 804 REJ09B0104-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module SSTDR0_1 SSU_1 SSTDR1_1 SSTDR2_1 SSTDR3_1 SSRDR0_1 SSRDR1_1 SSRDR2_1 SSRDR3_1 SSCRH_2 MSS BIDE  SOL SOLP SCKS CSS1 CSS0 SSU_2 SSCRL_2  SSUMS SRES    DATS1 DATS0 SSMR_2 MLS CPOS CPHS   CKS2 CKS1 CKS0 SSER_2 TE RE   TEIE TIE RIE CEIE SSSR_2  ORER   TEND TDRE RDRF CE SSCR2_2 SDOS SSCKOS SCSOS TENDSTS SCSATS SSODTS   SSTDR0_2 SSTDR1_2 SSTDR2_2 SSTDR3_2 SSRDR0_2 SSRDR1_2 SSRDR2_2 SSRDR3_2 PHRTIDR PHRTIDR PHRTIDR PHRTIDR PHRTIDR PHRTIDR PHRTIDR PHRTIDR PHRTIDR I/O port ADDRA_1 A/D_1 A D D R B _ 1 A D D R C _ 1

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 723 of 804 REJ09B0104-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module ADDRD_1 A/D_1 A D D R E _ 1 A D D R F _ 1 A D D R G _ 1 A D D R H _ 1 ADCSR_1 ADF ADIE ADST  CH3 CH2 CH1 CH0 ADCR_1 TRGS1 TRGS0 SCAN E SCANS CKS1 CKS0   TSTRB   CST5 CST4 CST3 CS T2 CST1 CST0 TPU TSYRB   SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 TCR_6 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_6 TMDR_6   BFB BFA  MD2 MD1 MD0 TIORH_6 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIORL_6 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 TIER_6    TCIEV TGIED TGIEC TGIEB TGIEA TSR_6    TCFV TGFD TGFC TGFB TGFA T C N T _ 6 T G R A _ 6 T G R B _ 6 T G R C _ 6 T G R D _ 6

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 724 of 804 REJ09B0104-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module TCR_7  CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_7 TIOR_7 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIER_7   TCIEU TCIEV   TGIEB TGIEA TSR_7 TCFD  TCFU TCFV   TGFB TGFA T C N T _ 7 T G R A _ 7 T G R B _ 7 TCR_8  CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_8 TIOR_8 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIER_8   TCIEU TCIEV   TGIEB TGIEA TSR_8 TCFD  TCFU TCFV   TGFB TGFA T C N T _ 8 T G R A _ 8 T G R B _ 8 TCR_9 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_9 TMDR_9   BFB BFA  MD2 MD1 MD0 TIORH_9 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIORL_9 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 TIER_9    TCIEV TGIED TGIEC TGIEB TGIEA TSR_9    TCFV TGFD TGFC TGFB TGFA

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 725 of 804 REJ09B0104-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module T C N T _ 9 T P U _ 9 T G R A _ 9 T G R B _ 9 T G R C _ 9 T G R D _ 9 TCR_10  CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_10 TIOR_10 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIER_10   TCIEU TCIEV   TGIEB TGIEA TSR_10 TCFD  TCFU TCFV   TGFB TGFA TCNT_10 TGRA_10 TGRB_10 TCR_11  CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_11 TIOR_11 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIER_11   TCIEU TCIEV   TGIEB TGIEA TSR_11 TCFD  TCFU TCFV   TGFB TGFA TCNT_11 TGRA_11 TGRB_11

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 726 of 804 REJ09B0104-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module P1DDR P17DDR P16DDR P15DDR P14DDR P13D DR P12DDR P11DDR P10DDR I/O port P2DDR     P23DDR P22DDR P21DDR P20DDR P3DDR P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR P6DDR  P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR PADDR PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR  PDDDR PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR P1ICR P17ICR P16ICR P 15ICR P14ICR P13ICR P 12ICR P11ICR P10ICR P2ICR     P23ICR P22ICR P21ICR P20ICR P3ICR P37ICR P36ICR P 35ICR P34ICR P33ICR P 32ICR P31ICR P30ICR P4ICR P47ICR P46ICR P 45ICR P44ICR P43ICR P 42ICR P41ICR P40ICR P5ICR P57ICR P56ICR P 55ICR P54ICR P53ICR P 52ICR P51ICR P50ICR P6ICR  P66ICR P65ICR P64ICR P63I CR P62ICR P 61ICR P60ICR PAICR PA7ICR PA6ICR PA5ICR PA4 ICR PA3ICR PA2ICR PA1ICR  PDICR PD7ICR PD6ICR PD5ICR PD4I CR PD3ICR PD2ICR PD1ICR PD0ICR PORTH PH7 PH6 PH5 PH 4 PH3 PH2 PH1 PH0 PORTJ PJ7 PJ6 PJ5 PJ 4 PJ3 PJ2 PJ1 PJ0 PORTK PK7 PK6 PK5 PK4 PK3 PK2 PK1 PK0 PHDR PH7DR PH6DR PH5DR PH4DR PH3DR PH2DR PH1DR PH0DR PJDR PJ7DR PJ6DR PJ5DR PJ4DR PJ3DR PJ2DR PJ1DR PJ0DR PKDR PK7DR PK6DR PK5DR PK4DR PK3DR PK2DR PK1DR PK0DR PHDDR PH7DDR PH6DDR PH5DDR PH4DDR PH3DDR PH2DDR PH1DDR PH0DDR PJDDR PJ7DDR PJ6DDR PJ5DDR PJ4DDR PJ3DDR PJ2DDR PJ1DDR PJ0DDR PKDDR PK7DDR PK6DDR PK5DDR PK4DDR PK3DDR PK2DDR PK1DDR PK0DDR PHICR PH7ICR PH6ICR PH5ICR PH4I CR PH3ICR PH2ICR PH1ICR PH0ICR PJICR PJ7ICR PJ6ICR PJ5ICR PJ4ICR PJ3ICR PJ2ICR PJ1ICR PJ0ICR PKICR PK7ICR PK6ICR PK5ICR PK4ICR PK3ICR PK2ICR PK1ICR PK0ICR PDPCR PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR PHPCR PH7PCR PH6PCR PH5PCR PH4PCR PH3PCR PH2PCR PH1PCR PH0PCR PJPCR PJ7PCR PJ6PCR PJ5PCR PJ4PCR PJ3PCR PJ2PCR PJ1PCR PJ0PCR PKPCR PK7PCR PK6PCR PK5PCR PK4PCR PK3PCR PK2PCR PK1PCR PK0PCR

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 727 of 804 REJ09B0104-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module P2ODR     P23ODR P22ODR P21ODR P20ODR I/O port PFCR9   TPUMS3A TPUMS3B TPUMS2 TPUMS1 TPUMS0A TPUMS0B PFCRA TPUMS11 TPUMS10 TPUMS9A TPUMS9B TPUMS8 TPUMS7 TPUMS6A TPUMS6B PFCRB  ITS14 ITS13 ITS12 ITS 11 ITS10 ITS9 ITS8 SSIER  SSI14 SSI13 SSI12 SSI11 SSI10 SSI9 SSI8 INTC SSI7 SSI6 SSI5 SSI4 SSI3 SSI2 SSI1 SSI0 D S A R _ 0 D M A C _ 0 D D A R _ 0 D O F R _ 0 D T C R _ 0 DBSR_0 BKSZH31 BKSZH30 BKSZ H29 BKSZH28 BKSZH27 BKSZ H26 BKSZH25 BKSZH24 BKSZH23 BKSZH22 BKSZH 21 BKSZH20 BKSZH19 BKSZH 18 BKSZH17 BKSZH16 BKSZ15 BKSZ14 BKSZ13 BKSZ12 BKSZ11 BKSZ10 BKSZ9 BKSZ8 BKSZ7 BKSZ6 BKSZ5 BKSZ4 BKSZ3 BKSZ2 BKSZ1 BKSZ0 DMDR_0 DTE DACKE TENDE  DREQS NRD   ACT    ERRF  ESIF DTIF DTSZ1 DTSZ0 MDS1 MDS0 TSEIE  ESIE DTIE DTF1 DTF0 DTA   DMAP2 DMAP1 DMAP0

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 728 of 804 REJ09B0104-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module DACR_0 AMS DIRS    RPTIE ARS1 ARS0 DMAC_0   SAT1 SAT0   DAT1 DAT0 SARIE   SARA4 SARA3 SARA2 SARA1 SARA0 DARIE   DARA4 DARA3 DARA2 DARA1 DARA0 D S A R _ 1 D M A C _ 1 D D A R _ 1 D O F R _ 1 D T C R _ 1 DBSR_1 BKSZH31 BKSZH30 BKSZ H29 BKSZH28 BKSZH27 BKSZ H26 BKSZH25 BKSZH24 BKSZH23 BKSZH22 BKSZH 21 BKSZH20 BKSZH19 BKSZH 18 BKSZH17 BKSZH16 BKSZ15 BKSZ14 BKSZ13 BKSZ12 BKSZ11 BKSZ10 BKSZ9 BKSZ8 BKSZ7 BKSZ6 BKSZ5 BKSZ4 BKSZ3 BKSZ2 BKSZ1 BKSZ0 DMDR_1 DTE DACKE TENDE  DREQS NRD   DTSZ1 DTSZ0 MDS1 MDS0 TSEIE  ESIE DTIE DTF1 DTF0 DTA   DMAP2 DMAP1 DMAP0

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 729 of 804 REJ09B0104-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module DACR_1 AMS DIRS    RPTIE ARS1 ARS0 DMAC_1   SAT1 SAT0   DAT1 DAT0 SARIE   SARA4 SARA3 SARA2 SARA1 SARA0 DARIE   DARA4 DARA3 DARA2 DARA1 DARA0 D S A R _ 2 D M A C _ 2 D D A R _ 2 D O F R _ 2 D T C R _ 2 DBSR_2 BKSZH31 BKSZH30 BKSZ H29 BKSZH28 BKSZH27 BKSZ H26 BKSZH25 BKSZH24 BKSZH23 BKSZH22 BKSZH 21 BKSZH20 BKSZH19 BKSZH 18 BKSZH17 BKSZH16 BKSZ15 BKSZ14 BKSZ13 BKSZ12 BKSZ11 BKSZ10 BKSZ9 BKSZ8 BKSZ7 BKSZ6 BKSZ5 BKSZ4 BKSZ3 BKSZ2 BKSZ1 BKSZ0 DMDR_2 DTE DACKE TENDE  DREQS NRD   DTSZ1 DTSZ0 MDS1 MDS0 TSEIE  ESIE DTIE DTF1 DTF0 DTA   DMAP2 DMAP1 DMAP0

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 730 of 804 REJ09B0104-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module DACR_2 AMS DIRS    RPTIE ARS1 ARS0 DMAC_2   SAT1 SAT0   DAT1 DAT0 SARIE   SARA4 SARA3 SARA2 SARA1 SARA0 DARIE   DARA4 DARA3 DARA2 DARA1 DARA0 D S A R _ 3 D M A C _ 3 D D A R _ 3 D O F R _ 3 D T C R _ 3 DBSR_3 BKSZH31 BKSZH30 BKSZ H29 BKSZH28 BKSZH27 BKSZ H26 BKSZH25 BKSZH24 BKSZH23 BKSZH22 BKSZH 21 BKSZH20 BKSZH19 BKSZH 18 BKSZH17 BKSZH16 BKSZ15 BKSZ14 BKSZ13 BKSZ12 BKSZ11 BKSZ10 BKSZ9 BKSZ8 BKSZ7 BKSZ6 BKSZ5 BKSZ4 BKSZ3 BKSZ2 BKSZ1 BKSZ0 DMDR_3 DTE DACKE TENDE  DREQS NRD   DTSZ1 DTSZ0 MDS1 MDS0 TSEIE  ESIE DTIE DTF1 DTF0 DTA   DMAP2 DMAP1 DMAP0

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 731 of 804 REJ09B0104-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module DACR_3 AMS DIRS    RPTIE ARS1 ARS0 DMAC_3   SAT1 SAT0   DAT1 DAT0 SARIE   SARA4 SARA3 SARA2 SARA1 SARA0 DARIE   DARA4 DARA3 DARA2 DARA1 DARA0 DMRSR_0 DMAC_0 DMRSR_1 DMAC_1 DMRSR_2 DMAC_2 DMRSR_3 DMAC_3 IPRA  IPRA14 IPRA13 IPRA12  IPRA10 IPRA9 IPRA8 INTC  IPRA6 IPRA5 IPRA4  IPRA2 IPRA1 IPRA0 IPRB  IPRB14 IPRB13 IPRB12  IPRB10 IPRB9 IPRB8  IPRB6 IPRB5 IPRB4  IPRB2 IPRB1 IPRB0 IPRC  IPRC14 IPRC13 IPRC12  IPRC10 IPRC9 IPRC8 INTC  IPRC6 IPRC5 IPRC4  IPRC2 IPRC1 IPRC0 IPRD  IPRD14 IPRD13 IPRD12  IPRD10 IPRD9 IPRD8  IPRD6 IPRD5 IPRD4     IPRE      IPRE10 IPRE9 IPRE8 IPRF      IPRF10 IPRF9 IPRF8  IPRF6 IPRF5 IPRF4  IPRF2 IPRF1 IPRF0 IPRG  IPRG14 IPRG13 IPRG12  IPRG10 IPRG9 IPRG8  IPRG6 IPRG5 IPRG4  IPRG2 IPRG1 IPRG0 IPRI  IPRI14 IPRI13 IPRI12  IPRI10 IPRI9 IPRI8  IPRI6 IPRI5 IPRI4  IPRI2 IPRI1 IPRI0 IPRK  IPRK14 IPRK13 IPRK12     IPRL      IPRL10 IPRL9 IPRL8  IPRL6 IPRL5 IPRL4  IPRL2 IPRL1 IPRL0 IPRM  IPRM14 IPRM13 IPRM12  IPRM10 IPRM9 IPRM8  IPRM6 IPRM5 IPRM4  IPRM2 IPRM1 IPRM0

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 732 of 804 REJ09B0104-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module IPRN  IPRN14 IPRN13 IPRN12  IPRN10 IPRN9 IPRN8 INTC  IPRN6 IPRN5 IPRN4  IPRN2 IPRN1 IPRN0 IPRO  IPRO14 IPRO13 IPRO12  IPRO10 IPRO9 IPRO8  IPRO6 IPRO5 IPRO4          IPRQ2 IPRQ1 IPRQ0 IPRR  IPRR14 IPRR13 IPRR12  IPRR10 IPRR9 IPRR8  IPRR6 IPRR5 IPRR4  IPRR2 IPRR1 IPRR0 ISCRH   IRQ14SR IRQ14SF IRQ13SR IRQ13SF IRQ12SR IRQ12SF IRQ11SR IRQ11SF IRQ10SR IRQ10SF IRQ9SR IRQ9SF IR Q8SR IRQ8SF ISCRL IRQ7SR IRQ7SF IRQ6SR IRQ6SF IRQ5SR IRQ5SF IRQ4SR IRQ4SF IRQ3SR IRQ3SF IRQ2SR IRQ2SF IRQ1SR IRQ1SF IR Q0SR IRQ0SF BCR2    IBCCS    PWDBE BSC RAMER     RAMS RAM2 RAM1 RAM0 MDCR     MDS3 MDS2 MDS1 MDS0 SYSTEM SCKCR PSTOP1  POSEL1   ICK2 ICK1 ICK0  PCK2 PCK1 PCK0  BCK2 BCK1 BCK0 SBYCR SSBY   STS4 STS3 STS2 STS1 STS0 MSTPCRA ACSE MSTPA14 MSTPA13 MSTPA1 2 MSTPA11 MSTPA10 MSTPA9 MSTPA8 MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 MSTPCRB MSTPB15 MSTPB14 MSTPB13 MST PB12 MSTPB11 MSTPB10 MSTPB9 MSTPB8 MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 MSTPCRC MSTPC15 MSTPC14 MSTPC13 MSTPC 12 MSTPC11 MSTPC10 MSTPC9 MSTPC8 MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTP C2 MSTPC1 MSTPC0 SMR_3* C/ A (GM) CHR (BLK) PE O/ E STOP (BCP1) MP (BCP0) CKS1 CKS0 SCI_3 B R R _ 3

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 733 of 804 REJ09B0104-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module SCR_3* TIE RIE TE RE MPIE TEIE CKE1 CKE0 SCI_3 T D R _ 3 SSR_3* TDRE RDRF ORER FER (ERS) PER TEND MPB MPBT R D R _ 3 SCMR_3     SDIR SINV  SMIF SMR_4* C/ A (GM) CHR (BLK) PE O/ E STOP (BCP1) MP (BCP0) CKS1 CKS0 SCI_4 B R R _ 4 SCR_4* TIE RIE TE RE MPIE TEIE CKE1 CKE0 T D R _ 4 SSR_4* TDRE RDRF ORER FER (ERS) PER TEND MPB MPBT R D R _ 4 SCMR_4     SDIR SINV  SMIF FCCS    FLER    SCO FLASH FKEY K7 K6 K5 K4 K3 K2 K1 K0 FMATS MS7 MS6 MS5 MS4 MS3 MS2 MS1 MS0 FTDAR TDER TDA6 TDA5 TDA4 TDA3 TDA2 TDA1 TDA0 TCR_4  CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_4 * TIOR_4 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIER_4 TTGE  TCIEU TCIEV   TGIEB TGIEA TSR_4 TCFD  TCFU TCFV   TGFB TGFA T C N T _ 4 T G R A _ 4 T G R B _ 4

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 734 of 804 REJ09B0104-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module TCR_5  CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_5 * TIOR_5 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIER_5 TTGE  TCIEU TCIEV   TGIEB TGIEA TSR_5 TCFD  TCFU TCFV   TGFB TGFA T C N T _ 5 T G R A _ 5 T G R B _ 5 INTCR   INTM1 INTM0 NMIEG    INTC CPUPCR CPUPCE    IPSETE CPUP2 CPUP1 CPUP0 IER  IRQ14E IRQ13E IRQ12E IR Q11E IRQ10E IRQ9E IRQ8E IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E ISR  IRQ14F IRQ13F IR Q12F IRQ11F IRQ 10F IRQ9F IRQ8F IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F PORT1 P17 P16 P15 P14 P13 P12 P11 P10 I/O port PORT2     P23 P22 P21 P20 PORT3 P37 P36 P35 P34 P33 P32 P31 P30 PORT4 P47 P46 P45 P44 P43 P42 P41 P40 PORT5 P57 P56 P55 P54 P53 P52 P51 P50 PORT6  P66 P65 P64 P63 P62 P61 P60 PORTA PA7 PA6 PA5 PA4 PA3 PA2 PA1  PORTD PD7 PD6 PD5 PD 4 PD3 PD2 PD1 PD0 P1DR P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR P2DR     P23DR P22DR P21DR P20DR P3DR P37DR P36DR P35DR P34DR P33DR P32DR P31DR P30DR P6DR  P66DR P65DR P64DR P63D R P62DR P61DR P60DR PADR PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR  PDDR PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 735 of 804 REJ09B0104-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module PCR G3CMS1 G3CMS0 G2CMS1 G2CMS0     PPG * PMR G3INV G2INV   G3NOV G2NOV   NDERH NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 NDERL NDER7 NDER6 NDE R5 NDER4 NDER3 NDER2 NDER1 NDER0 PODRH POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8 PODRL POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0 NDRH NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 NDRL NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 ADDRA_0 A/D_0 A D D R B _ 0 A D D R C _ 0 A D D R D _ 0 A D D R E _ 0 A D D R F _ 0 A D D R G _ 0 A D D R H _ 0 ADCSR_0 ADF ADIE ADST  CH3 CH2 CH1 CH0 ADCR_0 TRGS1 TRGS0 SCAN E SCANS CKS1 CKS0   TCSR OVF WT/IT TME   CKS2 CKS1 CKS0 WDT T C N T

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 736 of 804 REJ09B0104-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module TSTR   CST5 CST4 CST3 CS T2 CST1 CST0 TPU * TSYR   SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 TCR_0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_0 * TMDR_0   BFB BFA  MD2 MD1 MD0 TIORH_0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIORL_0 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 TIER_0 TTGE   TCIEV TGIED TGIEC TGIEB TGIEA TSR_0    TCFV TGFD TGFC TGFB TGFA T C N T _ 0 T G R A _ 0 T G R B _ 0 T G R C _ 0 T G R D _ 0 TCR_1  CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_1 * TIOR_1 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIER_1 TTGE  TCIEU TCIEV   TGIEB TGIEA TSR_1 TCFD  TCFU TCFV   TGFB TGFA T C N T _ 1 T G R A _ 1 T G R B _ 1

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 737 of 804 REJ09B0104-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module TCR_2  CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_2 * TIOR_2 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIER_2 TTGE  TCIEU TCIEV   TGIEB TGIEA TSR_2 TCFD  TCFU TCFV   TGFB TGFA T C N T _ 2 T G R A _ 2 T G R B _ 2 TCR_3 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_3 * TMDR_3   BFB BFA  MD2 MD1 MD0 TIORH_3 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIORL_3 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 TIER_3 TTGE   TCIEV TGIED TGIEC TGIEB TGIEA TSR_3    TCFV TGFD TGFC TGFB TGFA T C N T _ 3 T G R A _ 3 T G R B _ 3 T G R C _ 3 T G R D _ 3 Notes: 1. Parts of the bit functions differ in normal mode and the smart card interface mode. 2. Supported only by the H8SX/1527.

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 738 of 804 REJ09B0104-0300

20.3 Register States in Each Operating Mode

Abbreviation Reset Sleep Module Stop All-Module- Clock-Stop Software Standby Hardware Standby MCR Initialized  Initialized Initializ ed Initialized HCAN GSR Initialized  Initialized Initialized Initialized BCR Initialized  Initialized Initialized Initialized MBCR Initialized  Initialized Initialized Initialized TXPR Initialized  Initialized Initialized Initialized TXCR Initialized  Initialized Initialized Initialized TXACK Initialized  Initialized Initialized Initialized ABACK Initialized  Initialized Initialized Initialized RXPR Initialized  Initialized Initialized Initialized RFPR Initialized  Initialized Initialized Initialized IRR Initialized  Initialized Initialized Initialized MBIMR Initialized  Initialized Initialized Initialized IMR Initialized  Initialized Initialized Initialized REC Initialized  Initialized Initialized Initialized TEC Initialized  Initialized Initialized Initialized UMSR Initialized  Initialized Initialized Initialized LAFML Initialized  Initialized Initialized Initialized LAFMH Initialized  Initialized Initialized Initialized

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 739 of 804 REJ09B0104-0300 Register Abbreviation Reset Sleep Module Stop All-Module- Clock-Stop Software Standby Hardware Standby

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 740 of 804 REJ09B0104-0300 Register Abbreviation Reset Sleep Module Stop All-Module- Clock-Stop Software Standby Hardware Standby

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 741 of 804 REJ09B0104-0300 Register Abbreviation Reset Sleep Module Stop All-Module- Clock-Stop Software Standby Hardware Standby

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 742 of 804 REJ09B0104-0300 Register Abbreviation Reset Sleep Module Stop All-Module- Clock-Stop Software Standby Hardware Standby

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 743 of 804 REJ09B0104-0300 Register Abbreviation Reset Sleep Module Stop All-Module- Clock-Stop Software Standby Hardware Standby

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 744 of 804 REJ09B0104-0300 Register Abbreviation Reset Sleep Module Stop All-Module- Clock-Stop Software Standby Hardware Standby

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 745 of 804 REJ09B0104-0300 Register Abbreviation Reset Sleep Module Stop All-Module- Clock-Stop Software Standby Hardware Standby

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 746 of 804 REJ09B0104-0300 Register Abbreviation Reset Sleep Module Stop All-Module- Clock-Stop Software Standby Hardware Standby

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 747 of 804 REJ09B0104-0300 Register Abbreviation Reset Sleep Module Stop All-Module- Clock-Stop Software Standby Hardware Standby HCANMON Initialized  Initialized Initialized Initialized

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 748 of 804 REJ09B0104-0300 Register Abbreviation Reset Sleep Module Stop All-Module- Clock-Stop Software Standby Hardware Standby SSCRH_0 Initialized  Initialized Initialized Initialized SSU_0 SSCRL_0 Initialized  Initialized Initialized Initialized SSMR_0 Initialized  Initialized Initialized Initialized SSER_0 Initialized  Initialized Initialized Initialized SSSR_0 Initialized  Initialized Initialized Initialized SSCR2_0 Initialized  Initialized Initialized Initialized SSTDR0_0 Initialized  Initialized Initialized Initialized SSTDR1_0 Initialized  Initialized Initialized Initialized SSTDR2_0 Initialized  Initialized Initialized Initialized SSTDR3_0 Initialized  Initialized Initialized Initialized SSRDR0_0 Initialized  Initialized Initialized Initialized SSRDR1_0 Initialized  Initialized Initialized Initialized SSRDR2_0 Initialized  Initialized Initialized Initialized SSRDR3_0 Initialized  Initialized Initialized Initialized SSCRH_1 Initialized  Initialized Initialized Initialized SSU_1 SSCRL_1 Initialized  Initialized Initialized Initialized SSMR_1 Initialized  Initialized Initialized Initialized SSER_1 Initialized  Initialized Initialized Initialized SSSR_1 Initialized  Initialized Initialized Initialized SSCR2_1 Initialized  Initialized Initialized Initialized SSTDR0_1 Initialized  Initialized Initialized Initialized SSTDR1_1 Initialized  Initialized Initialized Initialized SSTDR2_1 Initialized  Initialized Initialized Initialized SSTDR3_1 Initialized  Initialized Initialized Initialized SSRDR0_1 Initialized  Initialized Initialized Initialized SSRDR1_1 Initialized  Initialized Initialized Initialized SSRDR2_1 Initialized  Initialized Initialized Initialized SSRDR3_1 Initialized  Initialized Initialized Initialized

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 749 of 804 REJ09B0104-0300 Register Abbreviation Reset Sleep Module Stop All-Module- Clock-Stop Software Standby Hardware Standby SSCRH_2 Initialized  Initialized Initialized Initialized SSU_2 SSCRL_2 Initialized  Initialized Initialized Initialized SSMR_2 Initialized  Initialized Initialized Initialized SSER_2 Initialized  Initialized Initialized Initialized SSSR_2 Initialized  Initialized Initialized Initialized SSCR2_2 Initialized  Initialized Initialized Initialized SSTDR0_2 Initialized  Initialized Initialized Initialized SSTDR1_2 Initialized  Initialized Initialized Initialized SSTDR2_2 Initialized  Initialized Initialized Initialized SSTDR3_2 Initialized  Initialized Initialized Initialized SSRDR0_2 Initialized  Initialized Initialized Initialized SSRDR1_2 Initialized  Initialized Initialized Initialized SSRDR2_2 Initialized  Initialized Initialized Initialized SSRDR3_2 Initialized  Initialized Initialized Initialized PHRTIDR Initialized     I/O port ADDRA_1 Initialized     A/D_1 ADDRB_1 Initialized     ADDRC_1 Initialized     ADDRD_1 Initialized     ADDRE_1 Initialized     ADDRF_1 Initialized     ADDRG_1 Initialized     ADDRH_1 Initialized     ADCSR_1 Initialized     ADCR_1 Initialized     TSTRB Initialized     TPU TSYRB Initialized    

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 750 of 804 REJ09B0104-0300 Register Abbreviation Reset Sleep Module Stop All-Module- Clock-Stop Software Standby Hardware Standby TCR_6 Initialized     TPU_6 TMDR_6 Initialized     TIORH_6 Initialized     TIORL_6 Initialized     TIER_6 Initialized     TSR_6 Initialized     TCNT_6 Initialized     TGRA_6 Initialized     TGRB_6 Initialized     TGRC_6 Initialized     TGRD_6 Initialized     TCR_7 Initialized     TPU_7 TMDR_7 Initialized     TIOR_7 Initialized     TIER_7 Initialized     TSR_7 Initialized     TCNT_7 Initialized     TGRA_7 Initialized     TGRB_7 Initialized     TPU_7 TCR_8 Initialized     TPU_8 TMDR_8 Initialized     TIOR_8 Initialized     TIER_8 Initialized     TSR_8 Initialized     TCNT_8 Initialized     TGRA_8 Initialized     TGRB_8 Initialized    

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 751 of 804 REJ09B0104-0300 Register Abbreviation Reset Sleep Module Stop All-Module- Clock-Stop Software Standby Hardware Standby TCR_9 Initialized     TPU_9 TMDR_9 Initialized     TIORH_9 Initialized     TIORL_9 Initialized     TIER_9 Initialized     TSR_9 Initialized     TCNT_9 Initialized     TGRA_9 Initialized     TGRB_9 Initialized     TGRC_9 Initialized     TGRD_9 Initialized     TCR_10 Initialized     TPU_10 TMDR_10 Initialized     TIOR_10 Initialized     TIER_10 Initialized     TSR_10 Initialized     TCNT_10 Initialized     TGRA_10 Initialized     TGRB_10 Initialized     TCR_11 Initialized     TPU_11 TMDR_11 Initialized     TIOR_11 Initialized     TIER_11 Initialized     TSR_11 Initialized     TCNT_11 Initialized     TGRA_11 Initialized     TGRB_11 Initialized    

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 752 of 804 REJ09B0104-0300 Register Abbreviation Reset Sleep Module Stop All-Module- Clock-Stop Software Standby Hardware Standby P1DDR Initialized     I/O port P2DDR Initialized     P3DDR Initialized     P6DDR Initialized     PADDR Initialized     PDDDR Initialized     P1ICR Initialized     P2ICR Initialized     P3ICR Initialized     P4ICR Initialized     P5ICR Initialized     P6ICR Initialized     PAICR Initialized     PDICR Initialized     PHDR Initialized     PJDR Initialized     PKDR Initialized     PHDDR Initialized     PJDDR Initialized     PKDDR Initialized     PHICR Initialized     PJICR Initialized     PKICR Initialized     PDPCR Initialized     PHPCR Initialized     PJPCR Initialized     PKPCR Initialized    

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 753 of 804 REJ09B0104-0300 Register Abbreviation Reset Sleep Module Stop All-Module- Clock-Stop Software Standby Hardware Standby P2ODR Initialized     I/O port PFCR9 Initialized     PFCRA Initialized     PFCRB Initialized     SSIER Initialized     INTC DSAR_0 Initialized     DMAC_0 DDAR_0 Initialized     DOFR_0 Initialized     DTCR_0 Initialized     DBSR_0 Initialized     DMDR_0 Initialized     DACR_0 Initialized     DSAR_1 Initialized     DMAC_1 DDAR_1 Initialized     DOFR_1 Initialized     DTCR_1 Initialized     DBSR_1 Initialized     DMDR_1 Initialized     DACR_1 Initialized     DSAR_2 Initialized     DMAC_2 DDAR_2 Initialized     DOFR_2 Initialized     DTCR_2 Initialized     DBSR_2 Initialized     DMDR_2 Initialized     DACR_2 Initialized    

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 754 of 804 REJ09B0104-0300 Register Abbreviation Reset Sleep Module Stop All-Module- Clock-Stop Software Standby Hardware Standby DSAR_3 Initialized     DMAC_3 DDAR_3 Initialized     DOFR_3 Initialized     DTCR_3 Initialized     DBSR_3 Initialized     DMDR_3 Initialized     DACR_3 Initialized     DMRSR_0 Initialized     DMAC_0 DMRSR_1 Initialized     DMAC_1 DMRSR_2 Initialized     DMAC_2 DMRSR_3 Initialized     DMAC_3 IPRA Initialized     INTC IPRB Initialized     IPRC Initialized     IPRD Initialized     IPRE Initialized     IPRF Initialized     IPRG Initialized     IPRI Initialized     IPRK Initialized     IPRL Initialized     IPRM Initialized     IPRN Initialized     IPRO Initialized     IPRQ Initialized     IPRR Initialized     ISCRH Initialized     ISCRL Initialized     BCR2 Initialized     BSC RAMER Initialized    

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 755 of 804 REJ09B0104-0300 Register Abbreviation Reset Sleep Module Stop All-Module- Clock-Stop Software Standby Hardware Standby MDCR Initialized     SYSTEM SYSCR Initialized     SCKCR Initialized     SBYCR Initialized     MSTPCRA Initialized     MSTPCRB Initialized     MSTPCRC Initialized     SMR_3 Initialized     SCI_3 BRR_3 Initialized     SCR_3 Initialized     TDR_3 Initialized  Initialized Initialized Initialized SSR_3 Initialized  Initialized Initialized Initialized RDR_3 Initialized  Initialized Initialized Initialized SCMR_3 Initialized     SMR_4 Initialized     SCI_4 BRR_4 Initialized     SCR_4 Initialized     TDR_4 Initialized  Initialized Initialized Initialized SSR_4 Initialized  Initialized Initialized Initialized RDR_4 Initialized  Initialized Initialized Initialized SCMR_4 Initialized     FCCS Initialized     FLASH FPCS Initialized     FECS Initialized     FKEY Initialized     FMATS Initialized     FTDAR Initialized    

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 756 of 804 REJ09B0104-0300 Register Abbreviation Reset Sleep Module Stop All-Module- Clock-Stop Software Standby Hardware Standby TMDR_4 Initialized     TIOR_4 Initialized     TIER_4 Initialized     TSR_4 Initialized     TCNT_4 Initialized     TGRA_4 Initialized     TGRB_4 Initialized     TMDR_5 Initialized     TIOR_5 Initialized     TIER_5 Initialized     TSR_5 Initialized     TCNT_5 Initialized     TGRA_5 Initialized     TGRB_5 Initialized     INTCR Initialized     INTC CPUPCR Initialized     IER Initialized     ISR Initialized    

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 757 of 804 REJ09B0104-0300 Register Abbreviation Reset Sleep Module Stop All-Module- Clock-Stop Software Standby Hardware Standby P1DR Initialized     I/O port P2DR Initialized     P3DR Initialized     P6DR Initialized     PADR Initialized     PDDR Initialized     PCR Initialized     PPG * PMR Initialized     NDERH Initialized     NDERL Initialized     PODRH Initialized     PODRL Initialized     NDRH Initialized     NDRL Initialized     ADDRA_0 Initialized     A/D_0 ADDRB_0 Initialized     ADDRC_0 Initialized     ADDRD_0 Initialized     ADDRE_0 Initialized     ADDRF_0 Initialized     ADDRG_0 Initialized     ADDRH_0 Initialized     ADCSR_0 Initialized     ADCR_0 Initialized     TCSR Initialized     WDT TCNT Initialized     RSTCSR Initialized     TSTR Initialized     TPU * TSYR Initialized    

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 758 of 804 REJ09B0104-0300 Register Abbreviation Reset Sleep Module Stop All-Module- Clock-Stop Software Standby Hardware Standby TMDR_0 Initialized     TIORH_0 Initialized     TIORL_0 Initialized     TIER_0 Initialized     TSR_0 Initialized     TCNT_0 Initialized     TGRA_0 Initialized     TGRB_0 Initialized     TGRC_0 Initialized     TGRD_0 Initialized     TMDR_1 Initialized     TIOR_1 Initialized     TIER_1 Initialized     TSR_1 Initialized     TCNT_1 Initialized     TGRA_1 Initialized     TGRB_1 Initialized     TMDR_2 Initialized     TIOR_2 Initialized     TIER_2 Initialized     TSR_2 Initialized     TCNT_2 Initialized     TGRA_2 Initialized     TGRB_2 Initialized    

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 759 of 804 REJ09B0104-0300 Register Abbreviation Reset Sleep Module Stop All-Module- Clock-Stop Software Standby Hardware Standby TMDR_3 Initialized     TIORH_3 Initialized     TIORL_3 Initialized     TIER_3 Initialized     TSR_3 Initialized     TCNT_3 Initialized     TGRA_3 Initialized     TGRB_3 Initialized     TGRC_3 Initialized     TGRD_3 Initialized     Note: * Supported only by the H8SX/1527.

Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 760 of 804 REJ09B0104-0300

Section 21 Electrical Characteristics Rev. 3.00 Mar. 14, 2006 Page 761 of 804 REJ09B0104-0300 Section 21 Electrical Characteristics

21.1 Absolute Maximum Ratings

Table 21.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage V CC –0.3 to +7.0 V Input voltage (except ports 4 and 5) V in –0.3 to V CC + 0.3 V Input voltage (port 4) V in –0.3 to AV CC1 + 0.3 V Input voltage (port 5) V in –0.3 to AV CC0 + 0.3 V Analog power supply voltage AV CC0 –0.3 to +7.0 V AV CC1 –0.3 to +7.0 V Analog input voltage (port 4) V AN –0.3 to AV CC1 + 0.3 V Analog input voltage (port 5) V AN –0.3 to AV CC0 + 0.3 V Operating temperature T opr Wide-range specifications: –40 to +85* Storage temperature T stg –55 to +125 °C Caution: Permanent damage to the LSI may result if absolute maximum ratings are exceeded. Note: * The operating temperature when programming /erasing the flash memory ranges from 0°C to +85°C for wide-range specification products.

Section 21 Electrical Characteristics Rev. 3.00 Mar. 14, 2006 Page 762 of 804 REJ09B0104-0300

21.2 DC Characteristics

Table 21.2 DC Characteristics (1) V SS = AVSS = 0 V* , Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min. Typ. Max. Unit Test Conditions VT V CC × 0.2   V VT   V CC × 0.7 Schmitt trigger input voltage IRQ input pin, TPU input pin, ports 2, 3, J, K VT – VT V CC × 0.05   MD, RES, NMI V IH V CC − 0.7  V CC + 0.3 V EXTAL V CC × 0.7  V CC + 0.3 Other input pins V CC × 0.7  V CC + 0.3 Port 4 AV CC1 × 0.7  AV CC1 + 0.3 Input high voltage (except Schmitt trigger input pin) Port 5 AV CC0 × 0.7  AV CC0 + 0.3 RES, MD, NMI V IL –0.3  V CC × 0.1 V EXTAL –0.3  V CC × 0.2 Other pins –0.3  V CC × 0.2 Port 4 –0.3  AV CC1 × 0.2 Input low voltage (except Schmitt trigger input pin) Port 5 –0.3  AV CC0 × 0.2 All output pins V OH V CC – 0.5   V I OH = –200 µA Output high voltage V CC – 1.0   I OH = –1 mA Output low voltage All output pins V OL   0.4 V I OL = 1.6 mA Input leakage current RES, NMI, MD |I in|   1.0 µA V in = 0.5 to VCC – 0.5 V Port 4   1.0 V in = 0.5 to AVCC1 – 0.5 V Port 5   1.0 V in = 0.5 to AVCC0 – 0.5 V

Section 21 Electrical Characteristics Rev. 3.00 Mar. 14, 2006 Page 763 of 804 REJ09B0104-0300 Table 21.2 DC Characteristics (2) V SS = AVSS = 0 V* , Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min. Typ. Max. Unit Test Conditions Tri-state leakage current (off state) Ports 1 to 3, 6, A, D, H, J, K | ITSI |   1.0 µA V in = 0.5 to VCC – 0.5 V Input pull-up MOS current Ports D, H, J, K –I p 50  300 µA V in = 0 V Input capacitance All input pins C in   15 pF V in = 0 V f = 1 MHz T a = 25°C Normal operation I CC*  73 85 mA f = 40 MHz Sleep mode  60 70 Current consumption* Standby mode*  50 300 µA T a ≤ 50°C   1 mA 50°C < T a All-module-clock- stop mode*  35 45 Analog power During A/D conversion AICC0  3.5 5 AV CC0 = 5.0 V supply current Standby for A/D conversion  10 100 µA During A/D conversion AICC1  3.5 5 mA AV CC1 = 5.0 V Standby for A/D conversion  10 100 µA RAM standby voltage V RAM 3.0   V Notes: 1. When the A/D conv erter is not used, the AVCC0, AVCC1, and AVSS pins should not be open. Connect the AVCC0 and AVCC1 pins to VCC, and the AVSS pin to VSS. 2. Current consumption values are for V IH = AVCC0 (port 5), AVCC1 (port 4), VCC (others) and VIL = 0 V with all output pins unloaded and all input pull-up MOSs in the off state. 4. I CC depends on VCC and f as follows: ICCmax = 12 (mA) + 0.33 (mA/(MHz × V)) × VCC × f (normal operation) ICCmax = 12 (mA) + 0.26 (mA/(MHz × V)) × VCC × f (sleep mode) 5. The values are for reference.

Section 21 Electrical Characteristics Rev. 3.00 Mar. 14, 2006 Page 764 of 804 REJ09B0104-0300 Table 21.3 Permissible Output Currents V SS = AVSS = 0 V*, Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min. Typ. Max. Unit Permissible output low current (per pin) All output pins I OL   10 mA Permissible output low current (total) Total of all output pins ΣIOL   100 mA Permissible output high current (per pin) All output pins –I OH   2.0 mA Permissible output high current (total) Total of all output pins Σ–IOH   30 mA Caution: To protect the LSI's re liability, do not exceed the output current values in table 21.3. Note: * When the A/D converter is not used, the AV CC0, AVCC1, and AVSS pins should not be open. Connect the AVCC0 and AVCC1 pins to VCC, and the AVSS pin to VSS.

21.3 AC Characteristics

C = 30 pF (all ports) RL = 2.4 kΩ RH = 12 kΩ Input/output timing measurement level: low at 0.8 V and high at 2.0 V Figure 21.1 Output Load Circuit

Section 21 Electrical Characteristics Rev. 3.00 Mar. 14, 2006 Page 765 of 804 REJ09B0104-0300

21.3.1 Clock Timing

Table 21.4 Clock Timing V SS = AVSS = 0 V, Iφ = 8 to 40 MHz, Pφ = 8 to 35 MHz, Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min. Max. Unit. Test Conditions Clock cycle time t cyc 25 125 ns Figure 21.2 Clock high pulse width t CH 5  ns Clock low pulse width t CL 5  ns Clock rising time t Cr  5 ns Clock falling time t Cf  5 ns Oscillation settling time after reset (crystal) tOSC1 20  ms Figure 21.4 Oscillation settling time after leaving software standby mode (crystal) t OSC2 10  ms Figure 21.3 External clock output delay settling time tDEXT 2  ms Figure 21.4 External clock input low pulse width TEXL 45  ns Figure 21.5 External clock input high pulse width TEXH 45  ns External clock input frequency = 4 to 9 MHz External clock rising time T EXr  5 ns External clock falling time T EXf  5 ns tcyc Iφ tCH tCf tCL tCr Figure 21.2 System Bus Clock Timing

Section 21 Electrical Characteristics Rev. 3.00 Mar. 14, 2006 Page 767 of 804 REJ09B0104-0300

21.3.2 Control Signal Timing

Table 21.5 Control Signal Timing V SS = AVSS = 0 V, Iφ = 8 to 40 MHz, Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min. Max. Unit Test Conditions RES setup time t RESS 200  ns Figure 21.6 RES pulse width t RESW 20  t cyc NMI setup time t NMIS 150  ns Figure 21.7 NMI hold time t NMIH 10  ns NMI pulse width (after leaving software standby mode) tNMIW 200  ns IRQ setup time t IRQS 150  ns IRQ hold time t IRQH 10  ns IRQ pulse width (after leaving software standby mode) tIRQW 200  ns Iφ RES tRESS tRESS tRESW Figure 21.6 Reset Input Timing

Section 21 Electrical Characteristics Rev. 3.00 Mar. 14, 2006 Page 768 of 804 REJ09B0104-0300 Iφ NMI IRQi* (i = 0 to 14) IRQ* (edge input) Note: * SSIER must be set to cancel software standby mode. tNMIS tNMIH tIRQS tIRQS tIRQH tNMIW tIRQW IRQ* (level input) Figure 21.7 Interrupt Input Timing

21.3.3 Timing of On-Chip Peripheral Modules

Table 21.6 Timing of On-Chip Peripheral Modules (1) V SS = AVSS = 0 V, Pφ = 8 to 35 MHz, Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min. Max. Unit Test Conditions I/O ports Output data delay time t PWD  40 ns Figure 21.8 Input data setup time t PRS 25  ns Input data hold time t PRH 25  ns Realtime input port data hold time tRTIPH 4  t cyc Figure 21.9 TPU Timer output delay time t TOCD  40 ns Figure 21.10 Timer input setup time t TICS 25  ns Timer clock input setup time t TCKS 25  ns Figure 21.11 Timer clock pulse width Single-edge setting tTCKWH 1.5  t cyc Both-edge setting tTCKWL 2.5  t cyc

Section 21 Electrical Characteristics Rev. 3.00 Mar. 14, 2006 Page 769 of 804 REJ09B0104-0300 Item Symbol Min. Max. Unit Test Conditions PPG Pulse output delay time t POD  40 ns Figure 21.12 SCI Asynchronous t Scyc 4  t cyc Figure 21.13 Input clock cycle Clocked synchronous 6  Input clock pulse width t SCKW 0.4 0.6 t Scyc Input clock rise time t SCKr  20 ns Figure 21.13 Input clock fall time t SCKf  20 ns Measurement voltages: VCC × 0.3 V to VCC × 0.7 V Asynchronous t Scyc 30  t cyc Figure 21.13 Output clock cycle Clocked synchronous 4  Output clock pulse width t SCKW 0.4 0.6 t Scyc Output clock rise time t SCKr  20 ns Figure 21.13 Output clock fall time t SCKf  20 ns Measurement voltages: VCC × 0.3 V to VCC × 0.7 V Transmit data delay time t TXD  40 ns Figure 21.14 Receive data setup time (clocked synchronous) tRXS 40  ns Receive data hold time (clocked synchronous) tRXH 40  ns A/D converter Trigger input setup time t TRGS 30  ns Figure 21.15

Section 21 Electrical Characteristics Rev. 3.00 Mar. 14, 2006 Page 770 of 804 REJ09B0104-0300 Table 21.6 Timing of On-Chip Peripheral Modules (2) V SS = AVSS = 0 V, Pφ = 8 to 20 MHz, Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min. Max. Unit Test Conditions HCAN* Transmit data delay time t HTXD  100 ns Figure 21.16 Receive data setup time t HRXS 100  ns Receive data hold time t HRXH 100  ns SSU Clock cycle time Master tSUcyc 4 256 t cyc Figure 21.17 Slave 4 256 Figure 21.18 Clock high pulse width Master tHI 80  ns Figure 21.19 Slave 80  Figure 21.20 Clock low pulse width Master tLO 80  ns Slave 80  Clock rising time tRISE  20 ns Clock falling time tFALL  20 ns Data input setup time Master tSU 25  ns Slave 30  Data input hold time Master tH 10  ns Slave 10  SCS setup time Master tLEAD 2.5  t cyc Slave 2.5  SCS hold time Master tLAG 2.5  t cyc Slave 2.5  Data output delay time Master tOD  40 ns Slave  40 Data output hold time Master tOH 30  ns Slave 30  Consecutive transmit delay time Master tTD 2.5  t cyc Slave 2.5 

Section 21 Electrical Characteristics Rev. 3.00 Mar. 14, 2006 Page 776 of 804 REJ09B0104-0300

21.4 A/D Conversion Characteristics

Table 21.7 A/D Conversion Characteristics V SS = AVSS = 0 V, Pφ = 8 to 35 MHz, Ta = –40°C to +85°C (wide-range specifications) Item Min. Typ. Max. Unit Resolution 10 10 10 Bit Conversion time 7.4  200 µs Analog input capacitance   20 pF Permissible signal source impedance   5 k Ω Nonlinearity error   ±3.5 LSB Offset error   ±3.5 LSB Full-scale error   ±3.5 LSB Quantization error  ±0.5  LSB Absolute accuracy   ±4.0 LSB

Section 21 Electrical Characteristics Rev. 3.00 Mar. 14, 2006 Page 777 of 804 REJ09B0104-0300

21.5 Flash Memory Characteristics

Table 21.8 Flash Memory Characteristics V SS = AVSS = 0 V, Iφ = 8 to 40 MHz, Pφ = 8 to 35 MHz, Ta = 0°C to +85°C (wide-range specifications) Item Symbol Min. Typ. Max. Unit Test Condition Programming time* t P  3 30 ms/128 bytes Erase time* t E  80 800 ms/4-kbyte block  500 5000 ms/32-kbyte block  1000 10000 ms/64-kbyte block Programming time (total) ΣtP  5 15 s/256 kbytes T a = 25°C, memory filled with 0. Erase time (total) * ΣtE  5 15 s/256 kbytes T a = 25°C Programming/erase time (total) * ΣtPE  10 30 s/256 kbytes T a = 25°C Number of programming N WEC 100 *   Times Data retention time* t DRP 10   Year Notes: 1. Programming time and erase time depend on data in the flash memory. 2. Programming time and erase time do not include time for data transfer. 3. All the characteristics after programming are guaranteed within this value (guaranteed value is from 1 to Min. value). 4. Characteristics when programming is performed within the Min. value

Section 21 Electrical Characteristics Rev. 3.00 Mar. 14, 2006 Page 778 of 804 REJ09B0104-0300

Rev. 3.00 Mar. 14, 2006 Page 779 of 804 REJ09B0104-0300 Appendix A. Port States in Each Pin State Table A.1 Port States in Each Pin State Port Name MCU Operating Mode Reset Software Standby Mode Port 1 All Hi-Z Keep Port 2 All Hi-Z Keep Port 3 All Hi-Z Keep Port 4 All Hi-Z Hi-Z Port 5 All Hi-Z Hi-Z Port 6 All Hi-Z Keep Port A All Hi-Z Keep Port D All Hi-Z Keep Port H All Hi-Z Keep Port J All Hi-Z Keep Port K All Hi-Z Keep

Rev. 3.00 Mar. 14, 2006 Page 780 of 804 REJ09B0104-0300 B. Product Lineup Product Classification Product Model Marking Package (Package Code) H8SX/1527 R5F61527 R5F61527 PRQP0100KB-A (FP-100M) H8SX/1525 R5F61525 R5F61525

Rev. 3.00 Mar. 14, 2006 Page 781 of 804 REJ09B0104-0300 C. Package Dimensions For the package dimensions, data in the Renesas IC Package General Catalog has priority. NOTE) DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. HE L e e D E A HD A bp c x y Z D ZE Reference Symbol Dimension in Millimeters Min Nom Max 1.0 1.0 0.10 0° 8° 0.5 0.12 0.17 0.22 0.17 0.22 0.27 0.00 0.12 0.25 3.05 15.8 16.0 16.2 2.70 0.20 0.15 0.4 0.5 0.6 0.08 16.216.015.8 1.0 *3 p E D E D yM x 5175 251 100 F b H E H D Z Z Terminal cross section pb c b c 2 1 Detail F c L AA L A θ θ P-QFP100-14x14-0.50 1.2g MASS[Typ.] FP-100M/FP-100MVPRQP0100KB-A RENESAS CodeJEITA Package Code Previous Code Figure C.1 Package Dimensions (PRQP0100KB-A)

Rev. 3.00 Mar. 14, 2006 Page 782 of 804 REJ09B0104-0300

Rev. 3.00 Mar. 14, 2006 Page 783 of 804 REJ09B0104-0300 Main Revisions and Additions in this Edition Item Page Revision (See Manual for Details) Section 3 MCU Operating Modes

3.2.2 System Control Register

(SYSCR)

69 Deleted

SYSCR controls MAC saturation operation bus with mode for instruction fetch, and selects enables/disables the on-chip RAM and the flash memory control registers.

3.4.1 Address Map (Advanced

Mode)

72 Amended

(12 kbytes) On-chip ROM (256 kbytes) Reserved H'040000 H'FF9000 Section 4 Exception Handling Figure 4.3 Operation when SP Value Is Odd

86 Amended

TRAPA instruction executed Section 5 Interrupt Controller

5.3.7 Software Standby Release

IRQ Enable Register (SSIER)

102 Amended

These bits select the IRQn pins used to leave software standby mode (n = 14 to 0).

5.6.5 DMAC Activation by

(1) Selection of Interrupt Sources

119 Added

The selected activation source is input to the DMAC through the select circuit. When transfer by an on-chip module interrupt is enabled (DTF1 = 1, DTF0 = 0, and DTE = 1) and the DTA bit in DMDR is set to 1, the interrupt source selected for the DMAC activation source is controlled by the DMAC and cannot be used as a DTC activation source or CPU interrupt source. Amended When the same interrupt source is set as both the DMAC activation source and CPU interrupt source, the DMAC must be given priority over the CPU. If the IPSETE bit in CPUPCR is set to 1, the priority is determined according to the IPR setting. Therefore, the CPUP setting or the IPR setting corresponding to the interrupt source must be set to lower than or equal to the DMAP settings. If the CPU is given priority, the DMAC may not be activated and the data transfer may be performed.

Rev. 3.00 Mar. 14, 2006 Page 784 of 804 REJ09B0104-0300 Item Page Revision (See Manual for Details)

5.8.6 Interrupt Flags of Peripheral

124 Amended

To clear an interrupt request flag of a peripheral module by the CPU, the flag must be read from after being cleared within the interrupt handling routine even if the peripheral module clock is not generated by dividing the system clock. This makes the request signal synchronized with the system clock.

6.6.1 Write Data Buffer Function

This LSI has a write data buffer function for the peripheral module. …, if a peripheral module wr ite continues for two cycles or longer, and there is an internal access next, only the peripheral module write is executed in the first two cycles. Section 7 DMA Controller (DMAC)

7.2.6 DMA Mode Control Register

(DMDR)

• Bit 5

149 Amended

This bit is valid while the DMA transfer is performed by the on-chip module interrupt. This bit decides whether the source flag selected by DMRSR is cleared or not. 0: The source flag is not cleared while the DMA transfer is performed by the on-chip module interrupt. Since the source flag is not cleared by the DMA transfer, it should be cleared by the CPU. 1: The source flag is cleared while the DMA transfer is performed by the on-chip module interrupt. Since the source flag is cleared by the DMA transfer, there is no need to request an interrupt to the CPU. (1) Normal Transfer Mode

162 Deleted

The TEND signal is output only in the last DMA transfer. The DACK signal is output every time a transfer request is received and a transfer starts. (2) Repeat Transfer Mode 163 Amended The TEND and DACK signals are is output only in the last DMA

Rev. 3.00 Mar. 14, 2006 Page 785 of 804 REJ09B0104-0300 Item Page Revision (See Manual for Details) (2) Activation by On-Chip Module Interrupt

166 Added

The interrupt request selected as an activation source can simultaneously generate interrupt requests to the CPU. For details, see section 5, Interrupt Controller. When the DMAC is activated with DTA = 1, the interrupt request flag is automatically cleared by a DMA transfer. When the DMAC is activated with DTA = 0, the interrupt request flag is not cleared by the DMAC. Thus it should be cleared by the CPU. Figure 7.23 Example of Bus Timing of DMA Transfer

182 Amended

HHWR, HLWR, LHWR Section 8 I/O Ports Figure 8.1 Port Block Diagram

211 Amended

[Legend] RDR: DR read RPOR: PORT read RICR: ICR read RPCR: PCR read RODR: ODR read

8.1.5 Pull-Up MOS Control

Register (PnPCR) (n = D, H, J, and K) Table 8.3 Input Pull-Up MOS State

214 Amended

Port D On-chip peripheral module output OFF OFF Port input OFF ON/OFF Port H Port output OFF OFF Port input OFF ON/OFF Port J On-chip peripheral module output OFF OFF Port input OFF ON/OFF Port K On-chip peripheral module output OFF OFF Port input OFF ON/OFF Section 9 16-Bit Timer Pulse Unit (TPU)

• Bit 5 to 0 292 to 295 Added (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)

Rev. 3.00 Mar. 14, 2006 Page 786 of 804 REJ09B0104-0300 Item Page Revision (See Manual for Details) Section 11 Watchdog Timer (WDT)

11.2.2 Timer Control/Status

Register (TCSR)

• Bit 7

370 Added

(When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Section 12 Serial Communication Interface (SCI)

12.3.7 Serial Status Register

(SSR) Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0):

• Bit 7 to 3 390 to 392 Added (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1):
• Bit 7 to 3 393 to 395 Added (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)

12.4.2 Receive Data Sampling

Timing and Reception Margin in Asynchronous Mode

407 Amended

N | D – 0.5 ||

12.9.6 Restrictions on Using

443 Amended

…and wait for at least five P φ clock cycles before… Section 13 Controller Area Network (HCAN)

13.3.2 General Status Register

(GSR)

• Bit 2

456 Amended

[Setting condition]

• Start of message transmission (SOF) [Clearing condition]
• Third bit of Intermission after EOF (End of Frame)
• Bit 15 to 11, 8, 4, 0 465 to 469 Amended (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
• Bit 6, 3 to 0 519 to 521 Amended (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)

Rev. 3.00 Mar. 14, 2006 Page 787 of 804 REJ09B0104-0300 Item Page Revision (See Manual for Details)

14.3.7 SS Transmit Data

Registers 0 to 3 (SSTDR0 to SSTDR3)

523 Added

Be sure not to access invalid SSTDRs. Table 14.2 Correspondence Between DATS Bit Setting and SSTDR

524 Added

14.3.8 SS Receive Data Registers

0 to 3 (SSRDR0 to SSRDR3) Be sure not to access invalid SSRDRs Table 14.3 Correspondence Between DATS Bit Setting and SSRDR

525 Added

Figure 14.4 Example of Initial Settings in SSU Mode

530 Amended

Start setting initial values [4] End Specify MLS, CPOS, CPHS, CKS2, CKS1, and CKS0 bits in SSMR Specify SDOS, SSCKOS, SCSOS, TENDSTS, SCSATS and SSODTS bits in SSCR2 Specify TE, RE, TEIE, TIE, RIE, and CEIE bits in SSER simultaneously[5] Figure 14.6 Flowchart Example of Data Transmission (SSU Mode)

533 Deleted

[1] [2] Initial setting TE = 1 (transmission enabled) Read TDRE in SSSR Figure 14.8 Flowchart Example of Data Reception (SSU Mode)

536 Deleted

[1] [2] Initial setting RE = 1 (receprion started) Dummy-read SRDR

Rev. 3.00 Mar. 14, 2006 Page 788 of 804 REJ09B0104-0300 Item Page Revision (See Manual for Details) Figure 14.9 Flowchart Example of Simultaneous Transmission/Reception (SSU Mode)

537 Amended

Transmission/reception started (TE = 1, RE = 1) [1] [2] Read TDRE in SSSR Yes No No Read TEND in SSSR TEND = 1? Yes No Has the 1 bit transfer period elapsed? Consecutive data transmission/reception? Clear TEND in SSSR to 0 Clear TE and RE in SSER to 0 Error processing End transmission/reception

14.4.7 Clock Synchronous

Figure 14.12 Example of Initial Settings in Clock Synchronous Communication Mode

539 Amended

Start setting initial values [4] End Specify CPOS, CKS2, CKS1, and CKS0 bits in SSMR Specify SDOS, SSCKOS, SCSOS, TENDSTS, SCSATS, and SSODTS bits in SSCR2 Specify TE, RE, TEIE, TIE, RIE, and CEIE bits in SSER simultaneously[5] Figure 14.14 Flowchart Example of Transmission Operation

541 Deleted

[1] [2] Initial setting TE = 1 (transmission enabled) Read TDRE in SSSR

Rev. 3.00 Mar. 14, 2006 Page 789 of 804 REJ09B0104-0300 Item Page Revision (See Manual for Details) Figure 14.16 Flowchart Example of Data Reception

543 Deleted

[1] Initial setting RE = 1 (receprion started) Read SSSR Figure 14.17 Flowchart Example of Simultaneous Transmission/Reception

544 Amended

Transmission/reception started (TE = 1, RE = 1) [1] [2] Read TDRE in SSSR Yes No No Read TEND in SSSR TEND = 1? Yes No Has the 1 bit transfer period elapsed? Consecutive data transmission/reception? Clear TEND in SSSR to 0 Clear TE and RE in SSER to 0 Error processing End transmission/reception Figure 15.1 Block Diagram of A/D Converter (Unit 0/AD_0)

548 Amended

Rev. 3.00 Mar. 14, 2006 Page 790 of 804 REJ09B0104-0300 Item Page Revision (See Manual for Details) Section 15 A/D Converter Figure 15.2 Block Diagram of A/D Converter (Unit 1/AD_1)

549 Added

15.3.2 A/D Control/Status

Register (ADCSR)

• Bit 7

553 Added

(When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Register (ADCSR)

• Bit 5

553 Amended

In scan mode, A/D conversion continues sequentially on the specified channels until this bit is cleared to 0 by software or a reset. Section 16 RAM 567 Amended Product Classification RAM Size RAM Addresses H8SX/1527 12 kbytes H'FF9000 to H'FFBFFF Flash memory version H8SX/1525 12 kbytes H'FF9000 to H'FFBFFF Section 17 Flash Memory (0.18- µm F-ZTAT Version)

569 Amended

Programming time: 3 ms (typ) for 128-byte simultaneous programming, 23.4 µs per byte Erasing time: 1000 ms (typ) per 1 block (64 kbytes) Number of programming The number of programming can be up to 100 times at the minimum. (1 to 100 times are guaranteed.)

17.7.1 Programming/Erasing

(4) Flash Key Code Register (FKEY)

583 Amended

H'5A: Programming/erasing of the flash memory is enabled. (When FKEY is a value other than H'5A, the software protection state is entered.)

Rev. 3.00 Mar. 14, 2006 Page 791 of 804 REJ09B0104-0300 Item Page Revision (See Manual for Details)

17.7.2 Programming/Erasing

Table 17.4 Parameters and Target Modes

586 Amended

FPFR  FPEFEQ  FMPAR  FMPDR  FEBS  (b) Programming

• Bit 4

590 Amended

Checks the FKEY value (H'5A) before erasure starts, and returns the result. (c) Erasure

• Bit 4 593 Amended Checks the FKEY value (H'5A) before erasure starts, and returns the result. (6) Flash Erase Block Select Parameter (FEBS: General Register ER0 of CPU) Amended FEBS specifies the erase block number. Settable values for the erase block numbers range from 0 to 11 (H'00000000 to H'0000000B). A value of 0 corresponds to block EB0 and a value of 11 corresponds to block EB11. An error occurs when a value outside the range (from 0 to 11) is set.

(1) On-Chip RAM Address Map when Programming/Erasing is Executed Figure 17.10 RAM Map when Programming/Erasing is Executed Amended H'FFBFFF Programming/erasing program entry System use area (15 bytes) DPFR (Return value: 1 byte) FTDAR setting FTDAR setting + 32 bytes FTDAR setting + 4 kbytes FTDAR setting + 16 bytes Initialization program entry Initialization + programming program or Initialization + erasing program RAM emulation area or area that can be used by user Area that can be used by user Area to be downloaded (size: 4 kbytes) Unusable area during programming/erasing

Rev. 3.00 Mar. 14, 2006 Page 792 of 804 REJ09B0104-0300 Item Page Revision (See Manual for Details)

606 Amended

Disable interrupts and bus master operation other than CPU Clear FKEY to 0 Programming JSR FTDAR setting + 16 Yes No Clear FKEY and programming error processing Yes Required data programming is completed? No Set FKEY to H'5A 10. 11. 12. 13. 14. 15. Programming Set parameters to ER1 and ER0 (FMPAR and FMPDR) FPFR = 0? (2) Programming Procedure in User Program Mode Figure 17.11 Programming Procedure in User Program Mode 607, 609 Amended 7. Initialization is executed . The initialization program is downloaded together with the programming program to the on-chip RAM. The entry point of the initialization program is at the address which is 32 bytes after #DLTOP (start address of the download destination specified by FTDAR). Call the subroutine to execute initialization by using the following steps.  The general registers other than ER0 and ER1 are held in the initialization program. 12. Programming is executed. The entry point of the programming program is a the address which is 16 bytes after #DLTOP (start address of the download destination specified by FTDAR). Call the subroutine to execute programming by using the following steps.  The general registers other than ER0 and ER1 are held in the programming program.

Rev. 3.00 Mar. 14, 2006 Page 793 of 804 REJ09B0104-0300 Item Page Revision (See Manual for Details)

610 Amended

completed? No Set FKEY to H'5A Erasing Erasing JSR FTDAR setting + 16 FPFR = 0? (3) Erasing Procedure in User Program Mode Figure 17.12 Erasing Procedure in User Program Mode

611 Amended

1. Erasure is executed. As in programming, the entry point of the erasing program is at the address which is 16 bytes after #DLTOP (start address of the download destination specified by FTDAR). Call the subroutine to execute erasure by using the following steps.  The general registers other than ER0 and ER1 are held in the erasing program. (4) Procedure of Erasing, Programming, and RAM Emulation in User Program Mode

613 Amended

• Be sure to initialize both the programming program and erasing program. When the FPEFEQ parameter is initialized, also initialize both the erasing program and programming program. Initialization must be executed for both entry addresses: 32 bytes after #DLTOP (start address of download destination for erasing program), and 32 bytes after #DLTOP (start address of download destination for programming program).

Rev. 3.00 Mar. 14, 2006 Page 794 of 804 REJ09B0104-0300 Item Page Revision (See Manual for Details) Figure 17.14 Procedure for Programming User MAT in User Boot Mode

614 Amended

Set FKEY to H'A5 DPFR = 0 ? Yes No Download error processing Set the FPEFEQ parameter Initialization JSR FTDAR setting + 32 Yes End programming procedure program FPFR = 0 ? No Initialization error processing Disable interrupts and bus master operation other than CPU Clear FKEY to 0 Set parameter to ER0 and ER1 (FMPAR and FMPDR) Programming JSR FTDAR setting + 16 Yes FPFR = 0 ? No Yes Required data programming is completed? No Set FKEY to H'5A Clear FKEY to 0 DownloadInitialization Programming MAT switchover MAT switchover Set FMATS to value other than H'AA to select user MAT Set SCO to 1 after initializing VBR and execute download Clear FKEY and programming error processing Set FMATS to H'AA to select user boot MAT User-boot-MAT selection state User-MAT selection state User-boot-MAT selection state Note: The MAT must be switched by FMATS to perform the programming error processing in the user boot MAT. Start programming procedure program Select on-chip program to be downloaded and specify download destination by FTDAR Figure 17.15 Procedure for Erasing User MAT in User Boot Mode

616 Amended

Set FKEY to H'A5 Yes No Download error processing Set the FPEFEQ parameter End erasing procedure program FPFR = 0 ? Initialization error processing Disable interrupts and bus master operation other than CPU Clear FKEY to 0 Set FEBS parameter Yes No Clear FKEY and erasing error processing Yes Required block erasing is completed? No Set FKEY to H'5A Clear FKEY to 0 DownloadInitialization Erasing Set FMATS to value other than H'AA to select user MAT Set SCO to 1 after initializing VBR and execute download Set FMATS to H'AA to select user boot MAT User-boot-MAT selection state User-MAT selection state User-boot-MAT selection state Note: The MAT must be switched by FMATS to perform the erasing error processing in the user boot MAT. MAT switchover MAT switchover DPFR = 0 ? Initialization JSR FTDAR setting + 32 Programming JSR FTDAR setting + 16 FPFR = 0 ? Select on-chip program to be downloaded and specify download destination by FTDAR

17.11 Switching between User

Figure 17.20 Switching between User MAT and User Boot MAT

629 Added

Procedure for switching to the user boot MAT 2. Write H'AA to FMATS *. Procedure for switching to the user MAT 2. Write other than H'AA to FMATS *. Note: * Set the FLSHE bit in the system control register (SYSCR) to 1 when making access to FMATS.

Rev. 3.00 Mar. 14, 2006 Page 795 of 804 REJ09B0104-0300 Item Page Revision (See Manual for Details)

17.13 Standard Serial

Specifications for Boot Mode (4) Receive Data Check

643 Deleted

1. Operating frequency error (8) Programming/Erasing State 647 Amended Command Command Name Description H'4C User boot MAT blank check Checks the blank data of the user boot MAT H'4D User MAT blank check Checks the blank data of the user MAT H'4C User boot MAT blank check Checks whether the contents of the user boot MAT are blank H'4D User MAT blank check Checks whether the contents of the user MAT are blank H'4F Boot program status inquiry Inquires into the boot program's status

17.14 Usage Notes 658,

1. To program the flash memory, the program data and program must be allocated to addresses which are higher than those of the external interrupt vector table and H'FF must be written to all the system reserved areas in the exception handling vector table. 15. The contents of some general registers are not saved in a programming/ programming end/erasing program. When needed, save general registers in the procedure program. Section 18 Clock Pulse Generator

18.1.1 System Clock Control

Register (SCKCR)

662 Amended

SCKCR controls Bφ clock output and frequencies of the system, peripheral module, and external clocks, and selects the Bφ clock to be output. Bit Bit Name Description

15 PSTOP1 Bφ Clock Output Enable

Controls Bφ output on PA7.

• Normal operation 0: Bφ output 1: Fixed high
• Software standby mode X: Fixed high
• Hardware standby mode X: Hi-Z

Rev. 3.00 Mar. 14, 2006 Page 796 of 804 REJ09B0104-0300 Item Page Revision (See Manual for Details)

18.5.1 Notes on Clock Pulse

667 Deleted

1. When Iφ > Pφ is specified by SCKCR, signals from the peripheral modules must be synchronized with the system clock. When CPU instructions are used to clear the interrupt source flag of a peripheral module, the flag must be read after being cleared to Section 19 Power-Down Modes

19.2.1 Standby Control Register

(SBYCR) 673 to 675 Amended Bit Bit Name Initial Value R/W SSBY R/W R/W R/W STS4 R/W STS3 R/W STS2 R/W STS1 R/W STS0 R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W

15 SSBY 0 R/W

14  1 R/W 13  0 R/W STS4 STS3 STS2 STS1 STS0 R/W R/W R/W R/W R/W Added Bit Bit Name Initial Value R/W Description 7 to 0  All 0 R/W ReservedThese bits are always read as 0. The write value should always be 0.

19.2.3 Module Stop Control

Register C (MSTPCRC)

678 Amended

On-chip RAM (H'FFF9000 to H'FFFBFFF) The write value to MSTPC1 and MSTPC0 should always be the same.

19.7.4 Software Standby Mode

684 Amended

Iφ

Rev. 3.00 Mar. 14, 2006 Page 797 of 804 REJ09B0104-0300 Item Page Revision (See Manual for Details) Section 20 List of Registers

20.1 Register Addresses

(Address Order)

706 Amended

Register Name Abbr. Number of Bits Standby control register SBYCR 16

20.2 Register Bits 732 Amended

 POSEL   ICK2 ICK1 ICK0  PCK2 PCK1 PCK0  BCK2 BCK1 BCK0 SBYCR SSBY   STS4 STS3 STS2 STS1 STS0 Section 21 Electrical Characteristics

761 Amended

Regular specifications: –20 to +75* Operating temperature Topr Wide-range specifications: –40 to +85* Note: * The operating temperature when programming/erasing the flash memory ranges from 0°C to +75°C for regular specification products and from 0°C to +85°C for wide-range specification products. Table 21.2 DC Characteristics (2)

763 Amended

Notes: 4. I CC depends on VCC and f as follows: ICCmax = 12 (mA) + 0.33 (mA/(MHz × V)) × VCC × f (normal operation)

Rev. 3.00 Mar. 14, 2006 Page 798 of 804 REJ09B0104-0300 Item Page Revision (See Manual for Details) Table 21.2 DC Characteristics (1) Table 21.2 DC Characteristics (2) Table 21.4 Clock Timing Table 21.3 Permissible Output Currents Table 21.4 Clock Timing Table 21.5 Control Signal Timing Table 21.6 Timing of On-Chip Peripheral Modules (1) Table 21.6 Timing of On-Chip Peripheral Modules (2) Table 21.7 A/D Conversion Characteristics Table 21.8 Flash Memory Characteristics 762 to 777 Conditions: V CC = 4.5 V to 5.5 V, AVCC0 = 4.5 V to 5.5 V, AVCC1 = 4.5 V to 5.5 V, VSS = AVSS = 0 V*1, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Figure 21.7 Interrupt Input Timing

768 Amended

Iφ NMI IRQi* (i = 0 to 14) IRQ* (edge input) Note: * SSIER must be set to cancel software standby mode. tNMIS tNMIH tIRQS tIRQS tIRQH tNMIW tIRQW IRQ* (level input) Appendix B. Product Lineup 780 Amended PRQP0100KB-A (FP-100M) Figure C.1 Package Dimensions (PRQP0100KB-A)

781 Chaged

Rev. 3.00 Mar. 14, 2006 Page 799 of 804 REJ09B0104-0300 Index Numerics A All-module-clock-stop mode .. 671, 672, 680 Available output signal and settings B C Clock synchronous communication CPU priority control function over D E

Rev. 3.00 Mar. 14, 2006 Page 800 of 804 REJ09B0104-0300 Exception handling by illegal F Flash multipurpose address area Flash multipurpose data destination Flash program/erase frequency G H I Interrupt exception handling sequence ... 116 Interrupt exception handling Interrupt sources and vector address M

Rev. 3.00 Mar. 14, 2006 Page 801 of 804 REJ09B0104-0300 Multiprocessor communication N O P Pin configuration in each operating mode .. 6 Programming/erasing interface Programming/erasing interface register .. 579 Q R Register states in each operating mode ... 738 Registers

Rev. 3.00 Mar. 14, 2006 Page 802 of 804 REJ09B0104-0300

Rev. 3.00 Mar. 14, 2006 Page 803 of 804 REJ09B0104-0300 S Serial communication interface (SCI) .... 377 Standard serial communication interface specifications for boot mode .... 630 Synchronous serial communication T U V W

Rev. 3.00 Mar. 14, 2006 Page 804 of 804 REJ09B0104-0300 Write data buffer function for

Renesas 32-Bit CISC Microcomputer Hardware Manual H8SX/1520 Group Publication Date: Rev.1.00, Mar. 15, 2004 Rev.3.00, Mar. 14, 2006 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp.  2006. Renesas Technology Corp., All rights reserved. Printed in Japan.

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