R5972D STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 35
Technical content
Datasheet sections
- 1 Pin settings
- 1.1 Pin connection
- 1.2 Pin description
- 2 Electrical data
- 2.1 Maximum ratings
- 2.2 Thermal data
- 3 Electrical characteristics
- 4 Datasheet parameters over the temperatur e range
- 5 Functional description
- 5.1 Power supply
- 5.2 Voltages monitor
- 5.3 Current protection
- 5.4 Error amplifier
- 5.5 PWM comparator and power stage
- 5.6 Thermal shutdown
- 6 Additional features and protection
- 6.1 Feedback disconnection
- 6.2 Output overvoltage protection
- 6.3 Zero load
- 7 Closing the loop
- 7.1 Error amplifier and compensation network
- 7.2 LC filter
- 7.3 PWM comparator
Features
General features – 1.5 A DC output current – Operating input voltage from 4 V to 36 V – 3.3 V / (± 2%) reference voltage – Large ambient temperature range: -40 °C to 125 °C – Output voltage adjustable from 1.235 V to V IN – Low dropout operation: 100% duty cycle – 250 kHz internally fixed frequency – Voltage feed-forward – Zero load current operation – Internal current limiting – Inhibit for zero current consumption – Protection against feedback disconnection – Thermal shutdown Aerospace and defense features – Suitable for use in aerospace and defense
applications
– Dedicated traceabilit y and part marking – Production parts approval documents available – Adapted extended life time and obsolescence management – Extended product change notification process – Designed and manufactured to meet sub- ppm quality goals – Advanced mold and frame designs for superior resilience in harsh environments (acceleration, EMI, thermal, humidity) – Extended screening ca pability on request Application Dedicated to aerospace applications
Description
The R5972D is a step-down monolithic power switching regulator with a minimum switch current limit of 1.8 A so it is able to deliver up to 1.5 A DC current to the load depending on the application conditions. The output voltage can be set from
1.235 V to V
IN. The device uses an internal P-channel DMOS transistor (with a typical RDS(on) of 250 m) as a switching element to minimize the size of the external components. An internal oscillator fixes the switching frequency at 250 kHz. The large ambient temperature range makes it ideal for aerospace and defense applications. A pulse-by-pulse current limit with the internal frequency modulation offers an effective constant current short-circuit protection. SO-8
1 Pin settings
1.1 Pin connection
Figure 1. Pin connection (top view)
1.2 Pin description
Table 1. Pin description 4 COMP E/A output for frequency compensation. 8 VCC Unregulated DC input voltage.
2 Electrical data
2.1 Maximum ratings
2.2 Thermal data
Table 2. Absolute maximum ratings I1 Maximum output current Int. limit. Table 3. Thermal data
- Package mounted on evaluation board.
3 Electrical characteristics
TJ = -40 °C to 125 °C, VCC = 12 V, unless otherwise specified. Table 4. Electrical characteristics
- With T J = 85 °C, Ilim_min = 2 A, assured by design, characterization and statistical correlation.8
R5972D Datasheet parameters over the temperature range
4 Datasheet parameters ov er the temperature range
The 100% of the population in the production flow is tested at three different ambient temperatures (-40 C, +25 C, +125 C) to guarantee the datasheet parameters inside the junction temperature range (-40 C, +125 C). The device operation is so guaranteed when the junction temperature is inside the (-40 C, +150 C) temperature range. The designer can estimate the silicon temperature increase respect to the ambient temperature evaluating the internal power losses generated during the device operation (please refer to the Section 2.2). However the embedded thermal protection disables the switching activity to protect the device in case the junction temperature reaches the T SHTDWN (+150 C ± 10 C) temperature. All the datasheet parameters can be guaranteed to a maximum junction temperature of +125 C to avoid triggering the thermal shutdown protection during the testing phase because of self-heating.
5 Functional description
A voltage monitor circuit which checks the input and the internal voltages. the voltage feed-forward function and an input/output synchronization pin. reduces the switching frequency in order to significantly reduce the duty cycle. A transconductance error amplifier. A high-side driver for the internal P-MOS switch. A circuit to implement the thermal protection function. Figure 2. Block diagram
5.1 Power supply
a very low supply voltage noise sensitivity.
5.2 Voltages monitor
Figure 3. Internal circuit
5.3 Current protection
Figure 4. The output power PDMOS transistor is split into two parallel PDMOS transistors.
Figure 4. Current limitation circuitry
5.4 Error amplifier
The error amplifier output is compared to the oscillator sawtooth to perform PWM control.
5.5 PWM comparator and power stage
generate the PWM signal for the driving stage. the faster the rise time, the lower the turn ON losses. However, there is a limit introduced by the recovery time of the recirculation diode. Table 5. Uncompensated error amplifier characteristics
Turn ON overcurrent leads to a decrease in the efficiency and system reliability. Shorter freewheeling diode life. to the parasites elements of the board) that increase the voltage drop across the PDMOS. turn the power switch ON and OFF, based on the PDMOS and the gate clamp status. against any cross conduction between the supply line and ground. Figure 5. Driving circuitry
5.6 Thermal shutdown
Additional features and protection R5972D
6 Additional features and protection
6.1 Feedback disconnection
If the feedback is disconnected, the duty cycle increases towards the maximum allowed value, bringing the output voltage close to the input supply. This condition could destroy the load. To avoid this hazardous condition, the device is turned OFF if the feedback pin is left floating.
6.2 Output overvoltage protection
Overvoltage protection, or OVP, is achieved by using an internal comparator connected to the feedback, which turns OFF the power stage when the OVP threshold is reached. This threshold is typically 30% higher than the feedback voltage. When a voltage divider is required to adjust the output voltage (Figure 13 on page 24), the OVP intervention will be set at: Equation 1 Where R 1 is the resistor connected between the output voltage and the feedback pin, and R2 is between the feedback pin and ground.
6.3 Zero load
Due to the fact that the internal power is a PDMOS, no boostrap capacitor is required and so the device works properly even with no load at the output. In this case it works in burst mode, with a random burst repetition rate. VOVP 1.3 R1 R2+
7 Closing the loop
Figure 6. Block diagram of the loop
7.1 Error amplifier an d compensation network
Figure 7. Error amplifier equivalent circuit and compensation network
7.2 LC filter
The transfer function of the L-C filter is given by: Equation 6 where RLOAD is defined as the ratio between VOUT and IOUT. If RLOAD >> ESR, the previous expression of ALC can be simplified and becomes: Equation 7 The zero of this transfer function is given by: Equation 8 F0 is the zero introduced by the ESR of the output capacitor and it is very important to increase the phase margin of the loop. The poles of the transfer function can be calculated through the following expression: Equation 9 In the denominator of ALC the typical second order system equation can be recognized: Equation 10 If the damping coefficient is very close to zero, the roots of the equation become a double root whose value is n. Similarly for ALC the poles can usually be defined as a double pole whose value is: Equation 11 ALC s RLOAD 1 ESR C OUT s+ s2 LC OUT ESR R LOAD+ s ESR C OUT RLOAD L+ RLOAD++ ALC s
1 ESR C OUT s+
LC OUT s2 ESR C OUT s1++ FO FPLC1 2 n++ FPLC 2 LC OUT
7.3 PWM comparator
The PWM gain is given by the following formula: Equation 12 where VOSCMAX is the maximum value of a sawtooth waveform and VOSCMIN is the minimum value. A voltage feed-forward is implemented to ensure a constant GPWM. This is obtained by generating a sawtooth waveform directly proportional to the input voltage V CC. Equation 13 Where K is equal to 0.076. Therefore the PWM gain is also equal to: Equation 14 This means that even if the input voltage changes, the error amplifier does not change its value to keep the loop in regulation, thus ensuring a better line regulation and line transient response. In summary, the open loop gain can be expressed as: Equation 15 Example 1 Considering R C = 4.7 k, CC = 22 nF and CP = 220 pF, the poles and zeroes of A0 are: FP1 = 9 Hz FP2 = 150 kHz FZ1 = 1.5 kHz If L = 33 µH, COUT = 100 µF and ESR = 80 m, the poles and zeroes of ALC become: FPLC = 3.3 kHz FZESR = 19.89 kHz Finally R1 = 5.6 k and R2 = 3.3 k. The gain and phase bode diagrams are plotted respectively in Figure 8 and Figure 9. GPWM s Vcc VOSCMAX VOSCMIN– KV CC= GPWM s 1 K---- const== Gs GPWM s
8 Application information
8.1 Component selection
Figure 10. Application schematic
internal PDMOS. Considering the range DMIN to DMAX, it is possible to determine the max. IRMS going through the input capacitor. physically larger than other capacitors. a higher RMS current rating for a given physical dimension (due to very low ESR). The drawback is the considerably high cost. Very good, small tantalum capacitors with very low ESR are becoming more available. However, they can occasionally burn if subjected to very high current during charge. can, however, be subjected to high surge current when connected to the power supply. pins is always suggested to adequately filter VCC spikes. The output capacitor is very important to meet the output voltage ripple requirement. current ripple. So, to reduce the output voltage ripple, a low ESR capacitor is required. capacitors in general should be avoided. some tantalum capacitor manufacturers is provided in Table 7. Table 6. List of ceramic capacitors for the R5972D
Table 7. Output capacitor selection
- POSCAP capacitors have some characterist ics which are very similar to tantalum.
Table 8. Inductor selection
8.2 Layout considerations
example is provided in Figure 11. Figure 11. Layout example
8.3 Thermal considerations
related to the RDSON increase compared to an ideal case. Figure 12. Switching losses Where IQ is the quiescent current. 150 °C. We can consider a value of 0.4 . IQ has a typical value of 2.5 mA at VIN = 12 V.
The overall losses are: Equation 25 The junction temperature of device will be: Equation 26 Where TA is the ambient temperature and RthJ-A is the thermal resistance junction to ambient. Considering that the device is mounted on the board with a good ground plane, that it has a thermal resistance junction to ambient (RthJ-A) of about 65 °C/W, and an ambient temperature of about 70 °C: Equation 27
8.4 Short-circuit protection
In overcurrent protection mode, when the peak current reaches the current limit, the device reduces the TON down to its minimum value (approximately 250 nsec) and the switching frequency to approximately one third of its nominal value even when synchronized to an external signal (see Section 5.3: Current protection on page 9). In these conditions, the duty cycle is strongly reduced and, in most applications, this is enough to limit the current to ILIM. In any event, in case of heavy short-circuit at the output (V O = 0 V) and depending on the application conditions (VCC value and parasitic effect of external components) the current peak could reach values higher than ILIM. This can be understood considering the inductor current ripple during the ON and OFF phases: ON phase Equation 28 OFF phase Equation 29 where V D is the voltage drop across the diode, DCRL is the series resistance of the inductor. In short-circuit conditions VOUT is negligible so during TOFF the voltage across the inductor is very small as equal to the voltage drop across parasitic components (typically the DCR of the inductor and the V FW of the freewheeling diode) while during TON the voltage applied the inductor is instead maximized as approximately equal to VIN. PTOT RDSON IOUT 2 DV IN IOUT TSW FSW VIN IQ=++= TJ TA Rth JA– PTOT+= TJ 70 0.615 65 110 C+= IL TON VIN Vout– DCR L RDSON+ I– IL TOFF VD Vout DCR L I++–
considering TON that has been already reduced to its minimum. considering that fSW has been already reduced to one third of the nominal. and diode) must be selected based on this value. the risk of an abrupt inductor saturation. Figure 13. Short-circuit current V
Application information R5972D
8.5 Positive buck-boost regulator
The device can be used to implement a step-up/down converter with a positive output voltage. The output voltage is given by: Equation 32 where the ideal duty cycle D for the buck boost converter is: Equation 33 However, due to power losses in the passive elements, the real duty cycle is always higher than this. The real value (that can be measured in the application) should be used in the following formulas. The peak current flowing in the embedded switch is: Equation 34 while its average current is equal to: Equation 35 This is due to the fact that the current flowing through the internal power switch is delivered to the output only during the OFF phase. The switch peak current must be lower than the minimum current limit of the overcurrent protection (see Table 4 on page 6 for details) while the average current must be lower than the rated DC current of the device. As a consequence, the maximum output current is: Equation 36 where I SW MAX represents the rated current of the device. The current capability is reduced by the term (1 - D) and so, for example, with a duty cycle of 0.5, and considering an average current through the switch of 1.5 A, the maximum output current deliverable to the load is 0.75 A. Figure 16 shows the schematic circuit of this topology for a 12 V output voltage and 5 V input. VOUT VIN D D VOUT ISW ILOAD IRIPPLE ILOAD VIN fSW ISW ILOAD
Figure 16. Positive buck-boost regulator
8.6 Negative buck-b oost regulator
The considerations given in Section 8.5 for the real duty cycle are still valid here. Also the Equation 34 till Equation 36 can be used to calculate the maximum output current. IN - VO, which must be lower than 36 V (the maximum operating input voltage).
Figure 17. Negative buck-boost regulator
8.7 Compensation network with MLCC at the output
the output filter in order to reduce the voltage ripple and the overall size of the application. with this compensation is limited. capacitors at the output (the optimum component value depends on the application).
Figure 18. MLCC compensation network example
9 Typical characteristics
Figure 19. Line regulation Figure 20. Load regulation Figure 21. Output voltage vs. junction Figure 22. Switching frequency vs. junction Figure 23. Quiescent current vs. junction Figure 24. Shutdown current vs. junction
Package information R5972D In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
Figure 29. SO-8 package outline Table 9. SO-8 package mechanical data
- Dimensions D does not include mold fl ash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
shall not exceed 0.15 mm (0.006 inch) in total (both sides).
Table 10. Document revision history 01-Oct-2014 1 In itial release.