H8S2426 RENESAS | Alldatasheet

Document overview

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Technical content

Datasheet sections

  • 1.1 Features
  • 1.1.1 Applications
  • 1.1.2 Overview of Specifications
  • 1.2 List of Products
  • 1.3 Block Diagrams
  • 1.4 Pin Description
  • 1.4.1 Pin Assignments
  • 1.4.2 Pin Assignments in Each Operating Mode
  • 1.4.3 Pin Functions
  • 2.1 Features
  • 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU
  • 2.1.2 Differences from H8/300 CPU
  • 2.1.3 Differences from H8/300H CPU
  • 2.2 CPU Operating Modes
  • 2.2.1 Normal Mode
  • 2.2.2 Advanced Mode
  • 2.3 Address Space
  • 2.4 Registers
  • 2.4.1 General Registers
  • 2.4.2 Program Counter (PC)
  • 2.4.3 Extended Register (EXR)
  • 2.4.4 Condition-Code Register (CCR)
  • 2.4.5 Multiply-Accumulate Register (MAC)
  • 2.4.6 Initial Values of CPU Internal Registers
  • 2.5 Data Formats
  • 2.5.1 General Register Data Formats
  • 2.5.2 Memory Data Formats
  • 2.6 Instruction Set
  • 2.6.1 Table of Instructions Classified by Function
  • 2.6.2 Basic Instruction Formats
  • 2.7 Addressing Modes and Effective Address Calculation
  • 2.7.1 Register Direct—Rn
  • 2.7.2 Register Indirect—@ERn

Revision Date: Sep. 19, 2008

16 Hardware Manual

Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2400 Series H8S/2426 R4F2426 R4S2426 H8S/2426R R4F2426R R4S2426R H8S/2424 R4F2424 R4S2424 Rev.1.00 REJ09B0466-0100 H8S/2426, H8S/2426R, H8S/2424 Group All information contained in this material, including products and product specifications at the time of publication of this material, is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp. website (http://www.renesas.com).

Rev. 1.00 Sep. 19, 2008 Page ii of xxviii

Rev. 1.00 Sep. 19, 2008 Page iii of xxviii 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Notes regarding these materials

Rev. 1.00 Sep. 19, 2008 Page iv of xxviii General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.  The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions may occur due to the false recognition of the pin state as an input signal. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied.  The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited.  The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized.  When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems.  The characteristics of MPU/MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different part numbers, implement a system-evaluation test for each of the products.

Rev. 1.00 Sep. 19, 2008 Page v of xxviii How to Use This Manual 1. Objective and Target Users This manual was written to explain the hardware functions and electrical characteristics of this LSI to the target users, i.e. those who will be using this LSI in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logic circuits, and microcomputers. This manual is organized in the following items: an overview of the product, descriptions of the CPU, system control functions, and peripheral functions, electrical characteristics of the device, and usage notes. When designing an application system that includes this LSI, take all points to note into account. Points to note are given in their contexts and at the final part of each section, and in the section giving usage notes. The list of revisions is a summary of major points of revision or addition for earlier versions. It does not cover all revised items. For details on the revised points, see the actual locations in the manual. The following documents have been prepared for the H8S/2426, H8S/2426R, H8S/2424 Group. Before using any of the documents, please visit our web site to verify that you have the most up-to-date available version of the document. Document Type Contents Document Title Document No. Data Sheet Overview of hardware and electrical characteristics   Hardware Manual Hardware specifications (pin assignments, memory maps, peripheral specifications, electrical characteristics, and timing charts) and descriptions of operation H8S/2426, H8S/2426R, H8S/2424 Group Hardware Manual This manual Software Manual Detailed descriptions of the CPU and instruction set H8S/2600 Series H8S/2000 Series Software Manual REJ09B0139 Application Note Exampl es of applications and sample programs Renesas Technical Update Preliminary report on the specifications of a product, document, etc. The latest versions are available from our web site.

Rev. 1.00 Sep. 19, 2008 Page vi of xxviii 2. Description of Numbers and Symbols Aspects of the notations for register names, bit names, numbers, and symbolic names in this manual are explained below. CMCSR indicates compare match generation, enables or disables interrupts, and selects the counter input clock. Generation of a WDTOVF signal or interrupt initializes the TCNT value to 0.

14.3 Operation

The style "register name"_"instance number" is used in cases where there is more than one instance of the same function or similar functions. [Example] CMCSR_0: Indicates the CMCSR register for the compare-match timer of channel 0. In descriptions involving the names of bits and bit fields within this manual, the modules and registers to which the bits belong may be clarified by giving the names in the forms "module name"."register name"."bit name" or "register name"."bit name". (1) Overall notation (2) Register notation Rev. 0.50, 10/04, page 416 of 914

14.2.2 Compare Match Control/Status Register_0, _1 (CMCSR_0, CMCSR_1)

14.3.1 Interval Count Operation

(4) (3) (2) Binary numbers are given as B'nnnn (B' may be omitted if the number is obviously binary), hexadecimal numbers are given as H'nnnn or 0xnnnn, and decimal numbers are given as nnnn. [Examples] Binary: B'11 or 11 Hexadecimal: H'EFA0 or 0xEFA0 Decimal: 1234 (3) Number notation An overbar on the name indicates that a signal or pin is active-low. [Example] WDTOVF Note: The bit names and sentences in the above figure are examples and have nothing to do with the contents of this manual. (4) Notation for active-low When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in CMCNT and the compare match constant register (CMCOR) match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. When the CKS1 and CKS0 bits are set to B'01 at this time, a f/4 clock is selected.

Rev. 1.00 Sep. 19, 2008 Page vii of xxviii 3. Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described below. Indicates the bit number or numbers. In the case of a 32-bit register, the bits are arranged in order from 31 to 0. In the case of a 16-bit register, the bits are arranged in order from 15 to 0. Indicates the name of the bit or bit field. When the number of bits has to be clearly indicated in the field, appropriate notation is included (e.g., ASID[3:0]). A reserved bit is indicated by "−". Certain kinds of bits, such as those of timer counters, are not assigned bit names. In such cases, the entry under Bit Name is blank. (1) Bit (2) Bit name Indicates the value of each bit immediately after a power-on reset, i.e., the initial value. 0: The initial value is 0 1: The initial value is 1 −: The initial value is undefined (3) Initial value For each bit and bit field, this entry indicates whether the bit or field is readable or writable, or both writing to and reading from the bit or field are impossible. The notation is as follows: R/W: R/(W): The bit or field is readable and writable. The bit or field is readable and writable. However, writing is only performed to flag clearing. The bit or field is readable. "R" is indicated for all reserved bits. When writing to the register, write the value under Initial Value in the bit chart to reserved bits or fields. The bit or field is writable. Note: The bit names and sentences in the above figure are examples, and have nothing to do with the contents of this manual. (4) R/W Describes the function of the bit or field and specifies the values for writing. (5) Description Bit 13 to 11 All 0 R R/W R R Address Identifier These bits enable or disable the pin function. Reserved This bit is always read as 0. Reserved This bit is always read as 1. ASID2 to ASID0 Bit Name Initial Value R/W

Description

[Table of Bits] 14 − 0 R Reserved These bits are always read as 0.

Rev. 1.00 Sep. 19, 2008 Page viii of xxviii 4. Description of Abbreviations The abbreviations used in this manual are listed below.

  • Abbreviations specific to this product Abbreviation Description BSC Bus controller CPG Clock pulse generator INT Interrupt controller SCI Serial communication interface TMR 8-bit timer TPU 16-bit timer pulse unit WDT Watchdog timer
  • Abbreviations other than those listed above Abbreviation Description ACIA Asynchronous communication interface adapter bps Bits per second CRC Cyclic redundancy check DMA Direct memory access DMAC Direct memory access controller GSM Global System for Mobile Communications Hi-Z High impedance IEBus Inter Equipment Bus (IEBus is a trademark of NEC Electronics Corporation.) I/O Input/output IrDA Infrared Data Association LSB Least significant bit MSB Most significant bit NC No connection PLL Phase-locked loop PWM Pulse width modulation SFR Special function register SIM Subscriber Identity Module UART Universal asynchronous receiver/transmitter VCO Voltage-controlled oscillator All trademarks and registered trademarks are the property of their respective owners.

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6.3.3 Wait Control Registers AH, AL, BH, and BL

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6.3.6 Area 0 Burst ROM Interface Control Register (BROMCRH)

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6.8.15 DMAC and EXDMAC Single Address Transfer Mode and

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7.5.13 Relation between DMAC and External Bus Requests,

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12.4.6 Example of Non-Overlapping Pulse Output

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15.4.2 Receive Data Sampling Timing and Reception Margin in

15.6.5 Simultaneous Serial Data Transmission and Reception

15.10.4 Receive Error Flags and Transmit Operations

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24.1.3 Extension Module Stop Control Registers H and L

24.1.4 RAM Module Stop Control Registers H and L

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Rev. 1.00 Sep. 19, 2008 Page 1 of 1270 REJ09B0466-0100 Section 1 Overview

1.1 Features

The H8S/2426 Group, H8S/2426R Group, and H8S/2424 Group are CISC (Complex Instruction Set Computer) microprocessors that integrate an H8S/2600 CPU core, which has an internal 16-bit architecture and is upward-compatible with Renesas Technology original H8/300, H8/300H, and H8S CPUs. The on-chip peripheral functions provided for enabling system configuration at a low cost are the DMA controller, EXDMA controller*, data transfer controller, serial communication interface, I C bus interface 2, synchronous serial communication unit, A/D converter, D/A converter, and various timers. On-chip ROM is flash memory whose size is 256 Kbytes and 128 Kbytes. Note: * Not supported by the H8S/2424 Group.

1.1.1 Applications

Application field examples: PC peripheral equipment, office automation equipment, consumer equipment, etc.

1.1.2 Overview of Specifications

The specifications of this LSI are summarized in table 1.1.

Rev. 1.00 Sep. 19, 2008 Page 2 of 1270 REJ09B0466-0100 Table 1.1 Overview of Specifications Type Module/ Function Description ROM Expanded ROM: Flash memory version,

256 Kbytes and 128 Kbytes

RAM RAM size: 64 Kbytes (in planning) and 48 Kbytes CPU • 16-bit high-speed H8S/2600 CPU (CISC type) Upward-compatible with H8/300, H8/300H, and H8S CPUs on an object level

  • General register mode (Sixteen 16-bit general registers)
  • Eight addressing modes
  • Address space: 4 Gbytes (program: 4 Gbytes, data: 4 Gbytes)
  • Number of basic instructions 69 types (arithmetic and logic, multiply and divide, bit- manipulation, and multiply-and-accumulate instructions)
  • Minimum instruction execution time (ns) 30.3 ns when system clock φ = 33 MHz and Vcc = 3.0 to 3.6 V (ADD instruction)
  • Multiplier is included (16 × 16 → 32 bits)
  • Multiply-and-accumulate instructions are supported (16 × 16 + 32 → 32 bits) CPU Operating mode Advanced mode

Rev. 1.00 Sep. 19, 2008 Page 3 of 1270 REJ09B0466-0100 Type Module/ Function Description CPU MCU operating mode

  • Mode 1: Expanded mode with on-chip ROM disabled, 16-bit bus (MD2 and MD1 pins are low and MD0 pin is high)
  • Mode 2: Expanded mode with on-chip ROM disabled, 8-bit bus (MD2 pin is low, MD1 pin is high, and MD0 pin is low)
  • Mode 3: Boot mode (MD2 pin is low and MD1 and MD0 pins are high)
  • Mode 4: Expanded mode with on-chip ROM enabled, 8-bit bus (MD2 pin is high and MD1 and MD0 pins are low)
  • Mode 7: Single-chip mode (MD2, MD1, and MD0 pins are high)
  • Power-down modes (a power-down mode is entered when the SLEEP instruction is executed) Interrupts (sources) Interrupt controller • External interrupt pins H8S/2426 Group, H8S/2426R Group: 33 pins (NMI, IRQ15-A to IRQ0-A, IRQ15-B to IRQ0-B) H8S/2424 Group: 17 pins (NMI, IRQ7-A to IRQ0-A, IRQ7-B to IRQ0-B)
  • Internal interrupt sources H8S/2426 Group, H8S/2426R Group: 102 sources H8S/2424 Group: 100 sources
  • Two interrupt control modes (specified by the interrupt control register)
  • Eight priority levels can be set (specified by the interrupt priority registers)
  • Independent vector addresses DMA DMA controller (DMAC)
  • DMA transfer is possible on four channels
  • Three activation sources (auto-request, on-chip module interrupt, and external request)
  • Byte or word can be set as the transfer unit
  • Short address mode or full address mode can be selected
  • 16-Mbyte address space can be specified directly

Rev. 1.00 Sep. 19, 2008 Page 4 of 1270 REJ09B0466-0100 Type Module/ Function Description EXDMA controller (EXDMAC)

  • DMA transfer is possible on two channels
  • Two activation sources (auto-request and external request)
  • Two transfer modes (normal mode and block transfer mode)
  • Dual address mode or single address mode can be selected
  • 16-Mbyte address space can be specified directly
  • Repeat area can be set Note: * EXDMAC is supported only by the H8S/2426 Group and H8S/2426R Group. DMA Data transfer controller (DTC)
  • Transfer is possible on any number of channels
  • An interrupt source can trigger data transfer (chain transfer is possible)
  • Three transfer modes (normal mode, repeat mode, and block transfer mode)
  • Byte or word can be set as the transfer unit
  • Activation by software is possible External bus extension Bus controller (BSC)
  • External address space: 16 Mbytes
  • Manages the external address space divided into eight areas Chip select signals (CS0 to CS7) can be output 8-bit access or 16-bit access can be selected 2-state access or 3-state access can be selected Program wait states can be inserted
  • External memory interfaces (burst ROM, DRAM, synchronous DRAM* , address/data multiplexed I/O)
  • Bus arbitration function (bus arbitration of the bus masters CPU, DTC, DMAC, and EXDMAC) Clock Clock pulse generator (CPG)
  • This LSI has a single on-chip clock pulse generator circuit
  • Consists of an oscillator, a system-clock PLL circuit, a divider, and the system clock frequency can be changed System clock (φ) cycle: 8 to 33 MHz
  • Six power-down modes Divided clock mode, sleep mode, module stop function, all module clock stop mode, software standby mode, and hardware standby mode

Rev. 1.00 Sep. 19, 2008 Page 5 of 1270 REJ09B0466-0100 Type Module/ Function Description A/D converter A/D converter (ADC)

  • Two units
  • 10-bit resolution
  • Number of input channels H8S/2426 Group and H8S/2426R Group: 16 channels  Unit 0: 8 channels  Unit 1: 8 channels H8S/2424 Group: 10 channels  Unit 0: 8 channels  Unit 1: 2 channels
  • Sample and hold functionality
  • Conversion time: 4.0 µs per channel (when A/D conversion clock is set to 10 MHz)
  • Two kinds of operating modes (single mode and scan mode)
  • Three types of A/D conversion start (software, trigger by timer (TPU or TMR), or external trigger) D/A converter D/A converter (DAC)
  • Resolution (8 bits) × Number of output channels (2 channels)
  • Conversion time: Maximum 10 µs (with 20-pF load)
  • Output voltage: 0 V to Vref Timer 16-bit timer pulse unit (TPU)
  • 16-bit timer × 12 channels (general pulse timer unit)
  • Eight counter input clocks can be selected for each channel
  • Maximum 16-pulse input/output (when external expanded mode is set)
  • Maximum 32-pulse input/output (when single-chip mode is set)
  • Counter clear operation, simultaneous write to multiple timer counters (TCNT), simultaneous clearing by compare match and input capture, register simultaneous input/output possible by counter synchronous operation, and maximum of 15-phase PWM output by combination with synchronous operation
  • Buffer operation, phase counting mode (two-phase encoder input), and cascaded operation settable for channels
  • Input capture function
  • Output compare function (waveform output at compare match)

Rev. 1.00 Sep. 19, 2008 Page 6 of 1270 REJ09B0466-0100 Type Module/ Function Description 8-bit timer (TMR) • 8-bit timer × 2 channels (operation as a 16-bit timer is also possible)

  • Selection of seven clock sources: Six internal clock signals or an external clock input
  • Pulse output with an arbitrary duty cycle or PWM output Timer Programmable pulse generator (PPG)
  • 16-bit pulse output
  • Pulse outputs are divided into four groups Non-overlap mode is available Inverted output can be specified
  • Can operate together with the data transfer controller (DTC) and DMA controller (DMAC) Watchdog timer Watchdog timer (WDT)
  • 8-bit timer × 1 channel (eight counter input clocks can be selected)
  • Switchable between watchdog timer mode and interval timer mode Serial interface
  • Five channels (asynchronous or clocked synchronous serial communication mode)
  • Full-duplex communication capability
  • Choice of any bit rate and choice of LSB-first or MSB-first Smart Card/SIM Serial communication interface (SCI) SCI supports Smart Card (SIM) interface I C bus interface 2 (IIC2)
  • Four channels
  • Continuous transmission/reception
  • Start and stop conditions generated automatically in master mode
  • Selection of acknowledge output levels when receiving
  • Automatic loading of acknowledge bit when transmitting
  • Bit synchronization/wait function High- function communi- cations Synchronous serial communication unit (SSU)
  • One channel
  • Master mode or slave mode can be selected
  • Standard mode or bidirectional mode can be selected
  • Full-duplex communication capability
  • Consecutive serial communication capability

Rev. 1.00 Sep. 19, 2008 Page 7 of 1270 REJ09B0466-0100 Type Module/ Function Description I/O ports • Input-only pins: 18 (144-pin version), 17 (145-pinersion)* 11 (120-pin version)

  • Input/output pins: 96 (144-pin version or 145-pin version)* 83 (120-pin version)
  • Pull-up resistor pins: 40
  • Open-drain pins: 91 (code: FP-144LV, body size: 20 × 20 mm, pin pitch: 0.50 mm)
  • 145-pin TLP package (PTLG0145JB-A) (body size: 9 × 9 mm, pin pitch: 0.65 mm)
  • 120-pin QFP package (PLQP0120LA-A) (code: FP-120BV, body size: 14 × 14 mm, pin pitch: 0.40 mm)
  • Pb-free package Operating frequency/ power supply voltage
  • Operating frequency: 8 to 33 MHz
  • Power supply voltage: VCC = 3.0 to 3.6 V, AVCC = 3.0 to 3.6 V
  • Current consumption: 55 mA typ. (VCC = 3.3 V, AVCC = 3.3 V, φ = 33 MHz) Operating environment temperature (°C) −20°C to +75°C (regular specifications) Note: 1. Supported only by the H8S/2426R Group. 2. Note that the function of 145-pin version partly differs from that of 144-pin version.

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1.2 List of Products

Table 1.2 lists the products and figure 1.1 shows how to read the product type name. Table 1.2 Products Product Type Name ROM Size RAM Size Package Remarks R4F2426 R4F2426R

256 Kbytes

128 Kbytes

64 Kbytes

48 Kbytes

PTLG0145JB-A* Flash memory version R4F2424 256 Kbytes PLQP0120LA-A Flash memory version Note: * In planning Product type name R4F 2426 Indicates "product original type number": H8S/2426 Indicates the ROM device type: F: On-chip ROM S: ROM-less Indicates the product classification: Microprocessor Indicates "Renesas semiconductor" Indicates memory size classification: On-chip memory size Figure 1.1 Meaning of Product Type Name

Rev. 1.00 Sep. 19, 2008 Page 9 of 1270 REJ09B0466-0100

1.3 Block Diagrams

P47/AN7_0 P46/AN6_0 P45/AN5_0 P44/AN4_0 P43/AN3_0 P42/AN2_0 P41/AN1_0 P40/AN0_0 Vref AVcc AVss PJ1 PJ2*2 P10/PO8/TIOCA0 P11/PO9/TIOCB0 P12/PO10/TIOCC0/TCLKA P13/PO11/TIOCD0/TCLKB P14/PO12/TIOCA1/SSO0-A P15/PO13/TIOCB1/TCLKC/SSI0-A P16/PO14/TIOCA2/EDRAK2/SSCK0-A P17/PO15/TIOCB2/TCLKD/EDRAK3/SCS0-A P65/IRQ13-A/DACK1/TMO1-A P64/IRQ12-A/DACK0/TMO0-A P63/IRQ11-A/TEND1/TMCI1-A P62/IRQ10-A/TEND0/TMCI0-A P61/IRQ9-A/DREQ1/TMRI1-A P60/IRQ8-A/DREQ0/TMRI0-A PG6/BREQ-A/TDI*3 PG5/BACK-A/TMS*3 PG4/BREQO-A/TCK*3 PG3/CS3/RAS3/CAS*1 PG2/CS2/RAS2/RAS PG1/CS1 PG0/CS0 PF7/φ PF6/AS/AH PF5/RD PF4/HWR PF3/LWR/SSO0-C PF2/LCAS/DQML*1/IRQ15-A/SSI0-C PF1/UCAS/DQMU*1/IRQ14-A/SSCK0-C PF0/WAIT-A/ADTRG0-B/SCS0-C ROM (flash memory) RAM WDT EXDMAC TPU × 12 channels IIC2 × 4 channels SCI × 5 channels 8-bit D/A converter (6 channels) 10-bit A/D converter PPG TMR × 2 channels H8S/2600 CPU DTC Port E Port 4 Port 9 PH3/CS7/OE-A/CKE-A*1/IRQ7-B PH2/CS6/IRQ6-B PH1/CS5/RAS5/SDRAMφ*1 PH0/CS4/RAS4/WE*1 Port HPort 2Port 1 DMAC Port A Notes: System clock PLL PA7/A23/IRQ7-A/SSO0-B PA6/A22/IRQ6-A/SSI0-B PA5/A21/IRQ5-A/SSCK0-B PA4/A20/IRQ4-A/SCS0-B PA3/A19/SCK4-B PA2/A18/RxD4-B PA1/A17/TxD4-B PA0/A16 P20/IRQ8-B/PO0-A/TIOCA3-A P21/IRQ9-B/PO1-A/TIOCB3-A P22/IRQ10-B/PO2-A/TIOCC3-A P23/IRQ11-B/PO3-A/TIOCD3-A/TxD4-A P24/IRQ12-B/PO4-A/TIOCA4-A/RxD4-A P25/WAIT-B/IRQ13-B/PO5-A/TIOCB4-A P26/IRQ14-B/PO6/TIOCA5/SDA2/ADTRG1 P27/IRQ15-B/PO7/TIOCB5/SCL2 MD2 MD1 MD0 EXTAL XTAL EMLE STBY RES WDTOVF/TDO* NMI BSCANE*3 P97/AN15_1 P96/AN14_1 P95/AN13_1/DA3 P94/AN12_1/DA2 P93/AN11_1 P92/AN10_1 P91/AN9_1 P90/AN8_1 P85/IRQ5-B/PO5-B/TIOCB4-B/TMO1-B/SCK3/EDACK3 P84/IRQ4-B/EDACK2 P83/IRQ3-B/PO3-B/TIOCD3-B/TMCI1-B/RxD3/ETEND3 P82/IRQ2-B/ETEND2 P81/IRQ1-B/PO1-B/TIOCB3-B/TMRI1-B/TxD3/EDREQ3 P80/IRQ0-B/EDREQ2 P35/OE-B/CKE-B*1/SCK1/SCL0 P34/SCK0/SCK4-A/SDA0 P33/RxD1/SCL1 P32/RxD0/IrRxD/SDA1 P31/TxD1 P30/TxD0/IrTxD P53/IRQ3-A/ADTRG0-A/TRST P52/BACK-B/IRQ2-A/PO4-B/TIOCA4-B/TMO0-B/SCK2 P51/BREQ-B/IRQ1-A/PO2-B/TIOCC3-B/TMCI0-B/RxD2/SCL3 P50/BREQO-B/IRQ0-A/PO0-B/TIOCA3-B/TMRI0-B/TxD2/SDA3 SSU Port J JTAG*3 (boundary scan) 1. Not available in the H8S/2426 Group. 2. Can be used only in FP-144LV. 3. Pins BSCANE, TD1, TMS, TCK, TRST, and TDO can be used only in TLP-145V. (under development) PJ0 Port 3 Port C Port BPort 5 Internal data bus Peripheral address bus Peripheral data bus Interrupt controller Internal address bus Clock pulse generator Bus controller Port 6 Port G Port FPort 8 Figure 1.2 Block Diagram of H8S/2426 Group and H8S/2426R Group

Rev. 1.00 Sep. 19, 2008 Page 10 of 1270 REJ09B0466-0100 PE7/D7/AD7 PE6/D6/AD6 PE5/D5/AD5 PE4/D4/AD4 PE3/D3/AD3 PE2/D2/AD2 PE1/D1/AD1 PE0/D0/AD0 PD7/D15/AD15 PD6/D14/AD14 PD5/D13/AD13 PD4/D12/AD12 PD3/D11/AD11 PD2/D10/AD10 PD1/D9/AD9 PD0/D8/AD8 VCC VCC VCC VCC PLLVCC PLLVSS VSS VSS VSS VSS VSS VSS VCL PB7/A15/TIOCB8/TCLKH PB6/A14/TIOCA8 PB5/A13/TIOCB7/TCLKG PB4/A12/TIOCA7 PB3/A11/TIOCD6/TCLKF PB2/A10/TIOCC6/TCLKE PB1/A9/TIOCB6 PB0/A8/TIOCA6 PC7/A7/TIOCB11 PC6/A6/TIOCA11 PC5/A5/TIOCB10 PC4/A4/TIOCA10 PC3/A3/TIOCD9 PC2/A2/TIOCC9 PC1/A1/TIOCB9 PC0/A0/TIOCA9 P47/IRQ7-B/AN7_0 P46/IRQ6-B/AN6_0 P45/IRQ5-B/AN5_0 P44/IRQ4-B/AN4_0 P43/IRQ3-B/AN3_0 P42/IRQ2-B/AN2_0 P41/IRQ1-B/AN1_0 P40/IRQ0-B/AN0_0 Vref AVCC AVSS P10/DREQ0/PO8/TIOCA0 P11/DREQ1/PO9/TIOCB0 P12/TEND0/PO10/TIOCC0/TCLKA P13/TEND1/PO11/TIOCD0/TCLKB P14/DACK0/PO12/TIOCA1/SSO0-A P15/DACK1/PO13/TIOCB1/TCLKC/SSI0-A P16/PO14/TIOCA2/SSCK0-A P17/PO15/TIOCB2/TCLKD/SCS0-A P85/PO5-B/TIOCB4-B/TMO1-B/SCK3 P83/PO3-B/TIOCD3-B/TMCI1-B/RxD3 P81/PO1-B/TIOCB3-B/TMRI1-B/TxD3 PG6/BREQ-A PG5/BACK-A PG4/BREQO-A/CS4 PG3/CS3/RAS3 PG2/CS2/RAS2 PG1/CS1 PG0/CS0 PF7/φ PF6/AS/AH PF5/RD PF4/HWR PF3/LWR/SSO0-C PF2/CS6/LCAS/SSI0-C PF1/CS5/UCAS/SSCK0-C PF0/WAIT-A/OE-A/ADTRG0-B/SCS0-C RAM WDT PPG H8S/2600 CPU DTC DMAC PA7/A23/CS7/IRQ7-A/SSO0-B PA6/A22/IRQ6-A/SSI0-B PA5/A21/IRQ5-A/SSCK0-B PA4/A20/IRQ4-A/SCS0-B PA3/A19/SCK4-B PA2/A18/RxD4-B PA1/A17/TxD4-B PA0/A16 P20/PO0-A/TIOCA3-A/TMRI0-A P21/PO1-A/TIOCB3-A/TMRI1-A P22/PO2-A/TIOCC3-A/TMCI0-A P23/PO3-A/TIOCD3-A/TMCI1-A/TXD4-A P24/PO4-A/TIOCA4-A/TMO0-A/RXD4-A P25/WAIT-B/PO5-A/TIOCB4-A/TMO1-A P26/PO6/TIOCA5/SDA2/ADTRG1 P27/PO7/TIOCB5/SCL2 MD2 MD1 MD0 EXTAL XTAL EMLE STBY RES WDTOVF NMI P95/AN13_1/DA3 P94/AN12_1/DA2 P35/OE-B/SCK1/SCL0 P34/SCK0/SCK4-A/SDA0 P33/RxD1/SCL1 P32/RxD0/IrRxD/SDA1 P31/TxD1 P30/TxD0/IrTxD P53/IRQ3-A/ADTRG0-A P52/BACK-B/IRQ2-A/PO4-B/TIOCA4-B/TMO0-B/SCK2 P51/BREQ-B/IRQ1-A/PO2-B/TIOCC3-B/TMCI0-B/RxD2/SCL3 P50/BREQO-B/IRQ0-A/PO0-B/TIOCA3-B/TMRI0-B/TxD2/SDA3 SSU Port D ROM (flash memory) TPU × 12 channels IIC2 × 4 channels SCI × 5 channels 8-bit D/A converter 10-bit A/D converter TMR × 2 channels Port E Port 4 Port 9Port 2Port 1 Port A System clock PLL Port 3 Port C Port BPort 5 Internal data bus Periheral address bus Peripheral data bus Interrupt controller Internal address bus Clock pulse generator Bus controller Port G Port FPort 8 Figure 1.3 Block Diagram of H8S/2424 Group

Rev. 1.00 Sep. 19, 2008 Page 11 of 1270 REJ09B0466-0100

1.4 Pin Description

1.4.1 Pin Assignments

P81/IRQ1-B/PO1-B/TIOCB3-B/TMRI1-B/TxD3/EDREQ3 P82/IRQ2-B/ETEND2 PH0/CS4/RAS4/WE*1 PH1/CS5/RAS5/SDRAMφ*1 PG1/CS1 PG0/CS0 P65/IRQ13-A/DACK1/TMO1-A P64/IRQ12-A/DACK0/TMO0-A P63/IRQ11-A/TEND1/TMCI1-A STBY Vss PJ1 PJ0 Vcc Vcc EXTAL XTAL Vss PF7/φ PLLVss RES PLLVcc PF6/AS/AH PF5/RD PF4/HWR PF3/LWR/SSO0-C PF2/LCAS/DQML *1/IRQ15-A/SSI0-C PF1/UCAS/DQMU*1/IRQ14-A/SSCK-C PF0/WAIT-A/ADTRG0-B/SCS0-C P62/IRQ10-A/TEND0/TMCI0-A P61/IRQ9-A/DREQ1/TMRI1-A P60/IRQ8-A/DREQ0/TMRI0-A PD7/D15/AD15 PD6/D14/AD14 PD5/D13/AD13 PD4/D12/AD12 PD3/D11/AD11 PD2/D10/AD10 PD1/D9/AD9 PD0/D8/AD8 108 107 106 105 104 103 102 101 100 73PG2/CS2/RAS2/RAS PG3/CS3/RAS3/CAS*1 AVcc Vref P40/AN0_0 P41/AN1_0 P42/AN2_0 P43/AN3_0 P44/AN4_0 P45/AN5_0 P46/AN6_0 P47/AN7_0 P90/AN8_1 P91/AN9_1 P92/AN10_1 P93/AN11_1 P94/AN12_1/DA2 P95/AN13_1/DA3 P96/AN14_1 P97/AN15_1 AVss PG4/BREQO-A PG5/BACK-A PG6/BREQ-A P50/BREQO-B/IRQ0-A/PO0-B/TIOCA3-B/TMRI0-B/TxD2/SDA3 P51/BREQ-B/IRQ1-A/PO2-B/TIOCC3-B/TMCI0-B/RxD2/SCL3 P52/BACK-B/IRQ2-A/PO4-B/TIOCA4-B/TMO0-B/SCK2 P53/IRQ3-A/ADTRG0-A P35/OE-B/CKE-B *1/SCK1/SCL0 P34/SCK0/SCK4-A/SDA0 P33/RxD1/SCL1 P32/RxD0/IrRxD/SDA1 P31/TxD1 P30/TxD0/IrTxD MD0 MD1 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Vcc PE7/D7/AD7 Vss PE6/D6/AD6 PE5/D5/AD5 PE4/D4/AD4 PE3/D3/AD3 PE2/D2/AD2 PE1/D1/AD1 PE0/D0/AD0 PJ2 P85/IRQ5-B/PO5-B/TIOCB4-B/TMO1-B/SCK3/EDACK3 P84/IRQ4-B/EDACK2 P83/IRQ3-B/PO3-B/TIOCD3-B/TMCI1-B/RxD3/ETEND P27/IRQ15-B/PO7/TIOCB5/SCL2 P26/IRQ14-B/PO6/TIOCA5/SDA2/ADTRG1 P25/WAIT-B/IRQ13-B/PO5-A/TIOCB4-A P24/IRQ12-B/PO4-A/TIOCA4-A/RxD4-A P23/IRQ11-B/PO3-A/TIOCD3/TxD4-A P22/IRQ10-B/PO2-A/TIOCC3-A P21/IRQ9-B/PO1-A/TIOCB3-A P20/IRQ8-B/PO0-A/TIOCA3-A Vss P17/PO15/TIOCB2/TCLKD/EDRAK3/SCS0-A P16/PO14/TIOCA2/EDRAK2/SSCK0-A P15/PO13/TIOCB1/TCLKC/SSI0-A P14/PO12/TIOCA1/SSO0-A P13/PO11/TIOCD0/TCLKB P12/PO10/TIOCC0/TCLKA P11/PO9/TIOCB0 P10/PO8/TIOCA0 VCL NMI WDTOVF PH3/CS7/OE-A/CKE-A*1/IRQ7-B PH2/CS6/IRQ6-B H8S/2426 Group, H8S/2426R Group PLQP0144KA-A FP-144LV (Top view) 0.1 µF (recommended value) Notes: 1. Not available in the H8S/2426 Group. Emulator enable pin. In normal operating mode, this pin should be fixed low. Driving this pin high in the flash-memory version enables the on-chip emulation function. When the on-chip emulation function is in use, pins P53, PG4, PG5, PG6, and WDTOVF are used exclusively as the on-chip emulator pins. The VCL pin should be connected to an external capacitor. Figure 1.4 Pin Assignments for H8S/2426 Group and H8S/2426R Group (1)

Rev. 1.00 Sep. 19, 2008 Page 12 of 1270 REJ09B0466-0100 H8S/2426 Group, H8S/2426R Group PTLG0145JB-A (Perspective top view) A B C D E F G H J K L M N Vss MD1 MD0 P32 P35 P50 AVss P94 P44 P40 MD2 Vcc P31 P34 P51 PG4 P93 P47 P42 AVcc PC0 P80 PC1 P30 P33 P52 PG5 P92 P43 P41 PC4 PC2 PC3 P53 PG6 P97 P96 P95 P63 PJ0 PC7 Vss PC5 PB0 NC Vss Vcc PB3 PC6 PB1 Vss PF7 Vss PB6 PB2 PA0 PB4 PF6 RES Vss PB7 PA3 PB5 PF2 PF4 PA5 PA2 PA7 PA1 P62 PF0 EMLE PA6 P82 PA4 P15 P16 P27 P83 PE4 PD7 PH0 P81 VCL P12 P17 P20 P21 P26 PE3 P90 P45 P46 P91 PE0 BSCANE PD4 123456789 1 0 11 PG2 PG3 Vref PG1 PG0 P65 P64 STBY PJ1 Vcc XTAL EXTAL PF5 PLLVss PF1 PLLVcc P60 PF3 PD6 P61 PD2 PD5 12 13 PH1 PH3 WDTOVF P11 P13 P22 P24 P85 PE6 Vss NMI PH2 P10 P14 Vss P23 P25 P84 PE5 PE2 PE1 PE7 PD3 PD0 Vcc PD1 Note: Connect NC to VSS or leave it open. The VCL pin must be connected to an external capacitor (recommended value: 0.1 µF). * Boundary scan enable pin. When the boundary scan function is used, this pin should be fixed high. At this time, pins P53, PG4 to PG6, and WDTOVF are used exclusively for boundary scan. Therefore, the corresponding pin functions of those pins are not available. When the boundary scan function is not used, this pin should be fixed low. Figure 1.5 Pin Assignments for H8S/2426 Group and H8S/2426R Group (2) (LGA is in Planning)

Rev. 1.00 Sep. 19, 2008 Page 13 of 1270 REJ09B0466-0100 H8S/2424 Group PLQ0120LA-A FP-120BV (Top view) 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 PG2/CS2/RAS2 PG3/CS3/RAS3 AVCC Vref P40/IRQ0-B/AN0_0 P41/IRQ1-B/AN1_0 P42/IRQ2-B/AN2_0 P43/IRQ3-B/AN3_0 P44/IRQ4-B/AN4_0 P45/IRQ5-B/AN5_0 P46/IRQ6-B/AN6_0 P47/IRQ7-B/AN7_0 P94/AN12_1/DA2 P95/AN13_1/DA3 AV SS PG4/BREQO-A/CS4 PG5/BACK-A PG6/BREQ-A P50/BREQO-B/IRQ0-A/PO0-B/TIOCA3-B/TMRI0-B/TxD2/SDA3 P51/BREQ-B/IRQ1-A/PO2-B/TIOCC3-B/TMCI0-B/RxD2/SCL3 P52/BACK-B/IRQ2-A/PO4-B/TIOCA4-B/TMO0-B/SCK2 P53/IRQ3-A/ADTRG0-A P35/OE-B/SCK1/SCL0 P34/SCK0/SCK4-A/SDA0 P33/RxD1/SCL1 P32/RxD0/IrRxD/SDA1 P31/TxD1 P30/TxD0/IrTxD MD0 MD1 VCC PE7/D7/AD7 VSS PE6/D6/AD6 PE5/D5/AD5 PE4/D4/AD4 PE3/D3/AD3 PE2/D2/AD2 PE1/D1/AD1 PE0/D0/AD0 P85/PO5-B/TIOCB4-B/TMO1-B/SCK3 P27/PO7/TIOCB5/SCL2 P26/PO6/TIOCA5/SDA2/ADTRG1 P25/WAIT-B/PO5-A/TIOCB4-A/TMO1-A P24/PO4-A/TIOCA4-A/TMO0-A/RxD4-A P23/PO3-A/TIOCD3-A/TMCI1-A/TxD4-A P22/PO2-A/TIOCC3-A/TMCI0-A P21/PO1-A/TIOCB3-A/TMRI1-A P20/PO0-A/TIOCA3-A/TMRI0-A P17/PO15/TIOCB2/TCLKD/SCS0-A P16/PO14/TIOCA2/SSCK0-A P15/DACK1/PO13/TIOCB1/TCLKC/SSI0-A P14/DACK0/PO12/TIOCA1/SSO0-A P13/TEND1/PO11/TIOCD0/TCLKB P12/TEND0/PO10/TIOCC0/TCLKA P11/DREQ1/PO9/TIOCB0 P10/DREQ0/PO8/TIOCA0 V CL*2 NMI WDTOVF MD2 VCC PC0/A0/TIOCA9 PC1/A1/TIOCB9 PC2/A2/TIOCC9 PC3/A3/TIOCD9 PC4/A4/TIOCA10 V SS PC5/A5/TIOCB10 PC6/A6/TIOCA11 PC7/A7/TIOCB11 PB0/A8/TIOCA6 PB1/A9/TIOCB6 PB2/A10/TIOCC6/TCLKE PB3/A11/TIOCD6/TCLKF PB4/A12/TIOCA7 VSS PB5/A13/TIOCB7/TCLKG PB6/A14/TIOCA8 PB7/A15/TIOCB8/TCLKH PA0/A16 VSS PA1/A17/TxD4-B PA2/A18/RxD4-B PA3/A19/SCK4-B PA4/A20/IRQ4-A/SCS0-B PA5/A21/IRQ5-A/SSCK0-B PA6/A22/IRQ6-A/SSI0-B PA7/A23/CS7/IRQ7-A/SSO0-B EMLE*1 PG1/CS1 PG0/CS0 STBY VSS P81/PO1-B/TIOCB3-B/TMRI1-B/TxD3 P83/PO3-B/TIOCD3-B/TMCI1-B/RxD3 V CC VCC EXTAL XTAL V SS PF7/φ PLLVSS RES PLLV CC PF6/AS/AH PF5/RD PF4/HWR PF3/LWR/SSO0-C PF2/CS6/LCAS/SSI0-C PF1/CS5/UCAS/SSCK0-C PF0/WAIT-A/OE-A/ADTRG0-B/SCS0-C PD7/D15/AD15 PD6/D14/AD14 PD5/D13/AD13 PD4/D12/AD12 PD3/D11/AD11 PD2/D10/AD10 PD1/D9/AD9 PD0/D8/AD8 0.1 µF (recommended value) Notes: 1. Emulator enable pin. In normal operating mode, this pin should be fixed low. Driving this pin high in the flash-memory version enables the on-chip emulation function. When the on-chip emulation function is in use, pins P53, PG4, PG5, PG6, and WDTOVF are used exclusively as the on-chip emulator pins. The V CL pin should be connected to an external capacitor. Figure 1.6 Pin Assignments for H8S/2424 Group

Rev. 1.00 Sep. 19, 2008 Page 14 of 1270 REJ09B0466-0100

1.4.2 Pin Assignments in Each Operating Mode

Table 1.3 Pin Assignments in Each Operating Mode of H8S/2426 Group and H8S/2426R Group Pin No. Pin Name Mode 7 144-Pin* 145-Pin* (LGA-145 in planning) Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Flash Memory Programmer Mode

1 B1 MD2 MD2 MD2 MD2 MD2 Vss

2 A1 Vss Vss Vss Vss Vss Vss

3 C2 P80/ IRQ0-B/

4 B2 Vcc Vcc Vcc Vcc Vcc Vcc

5 C1 A0 A0 PC0/A0 PC0/A0 PC0/TIOCA9 A0

6 C3 A1 A1 PC1/A1 PC1/A1 PC1/TIOCB9 A1

7 D2 A2 A2 PC2/A2 PC 2/A2 PC2/TIOCC9 A2

8 D3 A3 A3 PC3/A3 PC 3/A3 PC3/TIOCD9 A3

9 D1 A4 A4 PC4/A4 PC4/A4 PC4/TIOCA10 A4

10 E2 Vss Vss Vss Vss Vss Vss

11 E3 A5 A5 PC5/A5 PC5/A5 PC5/TIOCB10 A5

12 F2 A6 A6 PC6/A6 PC6/A6 PC6/TIOCA11 A6

13 E1 A7 A7 PC7/A7 PC7/A7 PC7/TIOCB11 A7

14 E4 A8 A8 PB0/A8 PB0/A8 PB0/TIOCA6 A8

15 F3 A9 A9 PB1/A9 PB1/A9 PB1/TIOCB6 A9

16 G2 A10 A10 PB2/A10 PB2/A10 PB2/TIOCC6/

17 F1 A11 A11 PB3/A11 PB3/A11 PB3/TIOCD6/

18 F4 Vss Vss Vss Vss Vss Vss

19 G4 A12 A12 PB4/A12 PB4/A12 PB4/TIOCA7 A12

20 H4 A13 A13 PB5/A13 PB5/A13 PB5/TIOCB7/

21 G1 A14 A14 PB6/A14 PB6/A14 PB6/TIOCA8 A14

22 H2 A15 A15 PB7/A15 PB7/A15 PB7/TIOCB8/

23 G3 A16 A16 PA0/A16 PA0/A16 PA0 A16

24 J4 A17 A17 PA1/A17/TxD4-B PA1/A17/TxD4-B PA1/TxD4-B A17

Rev. 1.00 Sep. 19, 2008 Page 15 of 1270 REJ09B0466-0100 Pin No. Pin Name Mode 7 144-Pin* 145-Pin* (LGA-145 in planning) Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Flash Memory Programmer Mode

25 H1 Vss Vss Vss Vss Vss Vss

26 J2 A18 A18 PA2/A18/RxD4-B PA2/A18/RxD4-B PA2/RxD4-B A18

27 H3 A19 A19 PA3/A19/SCK4-B PA3/A19/RxD4-B PA3/SCK4-B NC

28 K4 A20/ IRQ4-A A20/ IRQ4-A PA4/A20/ IRQ4-A/

29 J1 PA5/A21/

30 K2 PA6/A22/

B PA6/A22/ IRQ6-A/SSI0-B PA6/A22/ IRQ6-A/SSI0-B PA6/A22/ IRQ6-A/SSI0-B PA6/ IRQ6-A/SSI0-B NC

31 J3 PA7/A23/

32 K1 EMLE EMLE EMLE EMLE EMLE Vss

33 L2 P81/ IRQ1-B/

34 K3 P82/ IRQ2-B/

ETEND2* P82/IRQ2-B NC

35 L1 PH0/ CS4/

RAS4/WE* PH0/CS4/ RAS4/WE* PH0/CS4/ RAS4/WE* PH0/CS4/ RAS4/WE* PH0 NC

36 M1 PH1/ CS5/

M * PH1/CS5/ RAS5/SDRAM * PH1/CS5/ RAS5/SDRAM * PH1/CS5/ RAS5/SDRAM * PH1/ SDRAM * NC

37 N2 PH2/ CS6/IRQ

PH2/CS6/IRQ6-B PH2/CS6/IRQ6-B PH2/CS6/IRQ6-B PH2/IRQ6-B NC

38 M2 PH3/ CS7/

OE-A/CKE-A* IRQ7-B PH3/CS7/ OE-A/CKE-A* IRQ7-B PH3/CS7/ OE-A/CKE-A* IRQ7-B PH3/IRQ7-B NC

39 M3 WDTOVF/TD

WDTOVF/TDO* WDTOVF/TDO* WDTOVF/TDO* WDTOVF/TDO* NC

40 N1 NMI NMI NMI NMI NMI Vcc

41 L3 VCL VCL VCL VCL VCL VCL

Rev. 1.00 Sep. 19, 2008 Page 16 of 1270 REJ09B0466-0100 Pin No. Pin Name Mode 7 144-Pin* 145-Pin* (LGA-145 in planning) Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Flash Memory Programmer Mode

42 N3 P10/PO8/TIO

P10/PO8/TIOCA0 P10/PO8/TIOCA0 P10/ PO8/TIOCA0 P10/PO8/TIOCA0 NC

43 M4 P11/PO9/TIO

P11/PO9/TIOCB0 P11/PO9/TIOCB0 P11/ PO9/TIOCB0 P11/PO9/TIOCB0 NC

44 L4 P12/PO10/

45 M5 P13/PO11/

46 N4 P14/PO12/

47 K5 P15/PO13/

48 K6 P16/PO14/

49 L5 P17/PO15/

50 N5 Vss Vss Vss Vss Vss Vss

51 L6 P20/ IRQ8-B/

52 L7 P21/ IRQ9-B/

53 M6 P22/ IRQ10-B/

54 N6 P23/ IRQ11-B/

Rev. 1.00 Sep. 19, 2008 Page 17 of 1270 REJ09B0466-0100 Pin No. Pin Name Mode 7 144-Pin* 145-Pin* (LGA-145 in planning) Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Flash Memory Programmer Mode

55 M7 P24/ IRQ12-B/

56 N7 P25/ WAIT-B/

57 L8 P26/ IRQ14-B/

58 K7 P27/ IRQ15-B/

59 K8 P83/ IRQ3-B/

60 N8 P84/ IRQ4-B/

61 M8 P85/ IRQ5-B/

NC 62 L9 PJ2 * PJ2 * PJ2 * PJ2 * PJ2 * NC

63 K9 PE0/D0 PE0/D0 PE0/D0 PE0/D0 PE0 NC

64 N9 PE1/D1 PE1/D1 PE1/D1 PE1/D1 PE1 NC

65 M9 PE2/D2 PE2/D2 PE2/D2 PE2/D2 PE2 NC

66 L10 PE3/D3 PE3/D3 PE3/D3 PE3/D3 PE3 NC

67 K10 PE4/D4 PE4/D4 PE4/D4 PE4/D4 PE4 NC

68 N10 PE5/D5 PE5/D5 PE5 /D5 PE5/D5 PE5 NC

69 M10 PE6/D6 PE6/D6 PE6 /D6 PE6/D6 PE6 NC

70 M11 Vss Vss Vss Vss Vss Vss

71 N11 PE7/D7 PE7/D7 PE7 /D7 PE7/D7 PE7 NC

Rev. 1.00 Sep. 19, 2008 Page 18 of 1270 REJ09B0466-0100 Pin No. Pin Name Mode 7 144-Pin* 145-Pin* (LGA-145 in planning) Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Flash Memory Programmer Mode

72 N12 Vcc Vcc Vcc Vcc Vcc Vcc

73 M13 D8 D8 D8 D8 PD0 I/O0

74 N13 D9 D9 D9 D9 PD1 I/O1

75 L12 D10 D10 D10 D10 PD2 I/O2

76 M12 D11 D11 D11 D11 PD3 I/O3

77 L11 D12 D12 D12 D12 PD4 I/O4

78 L13 D13 D13 D13 D13 PD5 I/O5

79 K12 D14 D14 D14 D14 PD6 I/O6

80 K11 D15 D15 D15 D15 PD7 I/O7

81 J12 P60/ IRQ8-A/

82 K13 P61/ IRQ9-A/

83 J10 P62/ IRQ10-A/

84 J11 PF0/ WAIT-A/

85 H12 PF1/ UCAS/

DQMU* /IRQ14-A/ SSCK0-C PF1/UCAS/ DQMU* IRQ14-A/ SSCK0-C PF1/UCAS/ DQMU* IRQ14-A/ SSCK0-C PF1/UCAS/ DQMU* IRQ14-A/ SSCK0-C PF1/IRQ14-A/ SSCK0-C NC

86 H10 PF2/ LCAS/

DQML* IRQ15- A/SSI0-C PF2/LCAS/ DQML* IRQ15-A/SSI0-C PF2/LCAS/ DQML* IRQ15-A/SSI0-C PF2/LCAS/ DQML* IRQ15-A/SSI0-C PF2/IRQ15-A/ SSI0-C NC

87 J13 PF3/ LWR/

88 H11 HWR HWR HWR HWR PF4 NC

89 G12 RD RD RD RD PF5 NC

90 G10 PF6/ AS/AH PF6/ AS/AH PF6/ AS/AH PF6/ AS/AH PF6 NC

91 H13 PLLVcc PLLVcc PLLVcc PLLVcc PLLVcc Vcc

92 G11 RES RES RES RES RES RES

93 G13 PLLVss PLLVss PLLVss PLLVss PLLVss Vss

Rev. 1.00 Sep. 19, 2008 Page 19 of 1270 REJ09B0466-0100 Pin No. Pin Name Mode 7 144-Pin* 145-Pin* (LGA-145 in planning) Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Flash Memory Programmer Mode

94 F10 PF7/ φ PF7/ φ PF7/ φ PF7/ φ PF7/ φ NC

95 F11 Vss Vss Vss Vss Vss Vss

96 F12 XTAL XTAL XTAL XTAL XTAL XTAL

97 F13 EXTAL EXTAL EXTAL EXTAL EXTAL EXTAL

98 E11 Vcc Vcc Vcc Vcc Vcc Vcc

99 E13 Vcc Vcc Vcc Vcc Vcc Vcc

100 D11 PJ0 PJ0 PJ0 PJ0 PJ0 NC

101 E12 PJ1 PJ1 PJ1 PJ1 PJ1 NC

102 E10 Vss Vss Vss Vss Vss Vss

103 D13 STBY STBY STBY STBY STBY Vcc

104 D10 P63/ IRQ11-A/

105 D12 P64/ IRQ12-A/

106 C13 P65/ IRQ13-A/

107 C12 PG0/ CS0 PG0/ CS0 PG0/ CS0 PG0/ CS0 PG0 NC

108 B13 PG1/ CS1 PG1/ CS1 PG1/ CS1 PG1/ CS1 PG1 NC

109 A12 PG2/ CS2/

110 A13 PG3/ CS3/

RAS3/CAS* PG3/CS3/ RAS3/CAS* PG3/CS3/ RAS3/CAS* PG3/CS3/ RAS3/CAS* PG3 NC

111 B11 AVcc AVcc AVcc AVcc AVcc Vcc

112 B12 Vref Vref Vr ef Vref Vref Vcc

113 A11 P40/AN0_0 P40/AN0_0 P40/ AN0_0 P40/AN0_0 P40/AN0_0 NC

114 C11 P41/AN1_0 P41/AN1_0 P41/ AN1_0 P41/AN1_0 P41/AN1_0 NC

115 B10 P42/AN2_0 P42/AN2_0 P42/ AN2_0 P42/AN2_0 P42/AN2_0 NC

116 C10 P43/AN3_0 P43/AN3_0 P43/ AN3_0 P43/AN3_0 P43/AN3_0 Vss

117 A10 P44/AN4_0 P44/AN4_0 P44/ AN4_0 P44/AN4_0 P44/AN4_0 Vcc

118 B9 P45/AN5_0 P45/AN5_0 P45/ AN5_0 P45/AN5_0 P45/AN5_0 Vss

119 C9 P46/AN6_0 P46/AN6_0 P46/ AN6_0 P46/AN6_0 P46/AN6_0 NC

120 B8 P47/AN7_0 P47/AN7_0 P47/ AN7_0 P47/AN7_0 P47/AN7_0 NC

Rev. 1.00 Sep. 19, 2008 Page 20 of 1270 REJ09B0466-0100 Pin No. Pin Name Mode 7 144-Pin* 145-Pin* (LGA-145 in planning) Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Flash Memory Programmer Mode

121 A9 P90/AN8_1 P90/AN8_1 P90/ AN8_1 P90/AN8_1 P90/AN8_1 NC

122 D9 P91/AN9_1 P91/AN9_1 P91/ AN9_1 P91/AN9_1 P91/AN9_1 NC

123 C8 P92/AN10_1 P92/AN10_1 P92/ AN10_1 P92/AN10_1 P92/AN10_1 NC

124 B7 P93/AN11_1 P93/AN11_1 P93/ AN11_1 P93/AN11_1 P93/AN11_1 NC

125 A8 P94/AN12_1/

P94/AN12_1/DA2 P94/AN12_1/DA2 P94/ AN12_1/DA2 P94/AN12_1/DA2 NC

126 D8 P95/AN13_1/

P95/AN13_1/DA3 P95/AN13_1/DA3 P95/ AN13_1/DA3 P95/AN13_1/DA3 NC

127 D7 P96/AN14_1 P96/AN14_1 P96/AN14_1 P96/AN14_1 P96/AN14_1 NC

128 D6 P97/AN15_1 P97/AN15_1 P97/AN15_1 P97/AN15_1 P97/AN15_1 NC

129 A7 AVss AVss AVss AVss AVss Vss

130 B6 PG4/ BREQO-

TCK* PG4/BREQO-A/ TCK* PG4/BREQO-A/ TCK* PG4/BREQO-A/ TCK* PG4/TCK* NC

131 C7 PG5/

A/TMS* PG5/BACK/ TMS* PG5/BACK/ TMS* PG5/BACK/ TMS* PG5/TMS* NC

132 D5 PG6/

A/TDI* PG6/ BREQ-A/TDI* PG6/ BREQ-A/TDI* PG6/ BREQ-A/TDI* PG6/TDI* NC

133 A6 P50/ BREQO-

134 B5 P51/ BREQ-B/

Rev. 1.00 Sep. 19, 2008 Page 21 of 1270 REJ09B0466-0100 Pin No. Pin Name Mode 7 144-Pin* 145-Pin* (LGA-145 in planning) Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Flash Memory Programmer Mode

135 C6 P52/ BACK-B/

136 D4 P53/ IRQ3-A/

TRST* P53/IRQ3-A/ ADTRG0-A/ TRST* P53/IRQ3-A/ ADTRG0-A/ TRST* P53/IRQ3-A/ ADTRG0-A/ TRST* P53/IRQ3-A/ ADTRG0-A/ TRST* NC

137 A5 P35/ OE-B/

CKE-B* SCK1/SCL0 P35/OE-B/ CKE-B* SCK1/SCL0 P35/OE-B/ CKE-B* SCK1/SCL0 P35/OE-B/ CKE-B* SCK1/SCL0 P35/SCK1/ SCL0 NC

138 B4 P34/SCK0/

139 C5 P33/RxD1/SC

P33/RxD1/SCL1 P33/RxD1/SCL1 P 33/RxD1/SCL1 P33/RxD1/SCL1 NC

140 A4 P32/RxD0/

141 B3 P31/TxD1 P31/TxD1 P31/ TxD1 P31/TxD1 P31/TxD1 NC

142 C4 P30/TxD0/IrT

P30/TxD0/IrTxD P30/TxD0 /IrTxD P30/TxD0/IrTxD P30/TxD0/IrTxD NC

143 A3 MD0 MD0 MD0 MD0 MD0 Vss

144 A2 MD1 MD1 MD1 MD1 MD1 Vss

 E5 NC NC NC NC NC NC Notes: 1. Not available in the H8S/2426 Group. 2. Can be used only in FP-144LV version. 3. Can be used only in TLP-145V version. 4. The 144-pin code is FP-144LV. 5. The 145-pin code is TLP-145V.

Rev. 1.00 Sep. 19, 2008 Page 22 of 1270 REJ09B0466-0100 Table 1.4 Pin Assignments in Each Operating Mode of H8S/2424 Group Pin No. Pin Name Mode 7 120-PIn Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Flash Memory Programmer Mode

1 MD2 MD2 MD2 MD2 MD2 Vss

2 Vcc Vcc Vcc Vcc Vcc Vcc

3 A0 A0 PC0/A0 PC0/A0 PC0/TIOCA9 A0

4 A1 A1 PC1/A1 PC1/A1 PC1/TIOCB9 A1

5 A2 A2 PC2/A2 PC2/A2 PC2/TIOCC9 A2

6 A3 A3 PC3/A3 PC3/A3 PC3/TIOCD9 A3

7 A4 A4 PC4/A4 PC4/A4 PC4/TIOCA10 A4

8 Vss Vss Vss Vss Vss Vss

9 A5 A5 PC5/A5 PC5/A5 PC5/TIOCB10 A5

10 A6 A6 PC6/A6 PC6/A6 PC6/TIOCA11 A6

11 A7 A7 PC7/A7 PC7/A7 PC7/TIOCB11 A7

12 A8 A8 PB0/A8 PB0/A8 PB0/TIOCA6 A8

13 A9 A9 PB1/A9 PB1/A9 PB1/TIOCB6 A9

14 A10 A10 PB2/A10 PB2/A10 PB2/TIOCC6/

15 A11 A11 PB3/A11 PB3/A11 PB3/TIOCD6/

16 A12 A12 PB4/A12 PB4/A12 PB4/TIOCA7 A12

17 Vss Vss Vss Vss Vss Vss

18 A13 A13 PB5/A13 PB5/A13 PB5/TIOCB7/

19 A14 A14 PB6/A14 PB6/A14 PB6/TIOCA8 A14

20 A15 A15 PB7/A15 PB7/A15 PB7/TIOCB8/

21 A16 A16 PA0/A16 PA0/A16 PA0 A16

22 Vss Vss Vss Vss Vss Vss

23 A17 A17 PA1/A17/TxD4-B PA1 /A17/TxD4-B PA1/TxD4-B A17

24 A18 A18 PA2/A18/RxD4-B PA2 /A18/RxD4-B PA2/RxD4-B A18

25 A19 A19 PA3/A19/SCK4-B PA3/A19/SCK4-B PA3/SCK4-B NC

26 A20/ IRQ4-A A20/ IRQ4-A PA4/A20/ IRQ4-A/

27 PA5/A21/ IRQ5-A/

Rev. 1.00 Sep. 19, 2008 Page 23 of 1270 REJ09B0466-0100 Pin No. Pin Name Mode 7 120-PIn Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Flash Memory Programmer Mode

28 PA6/A22/

29 PA7/A23/ CS7/

30 EMLE EMLE EMLE EMLE EMLE Vss

31 WDTOVF WDTOVF WDTOVF WDTOVF WDTOVF NC

32 NMI NMI NMI NMI NMI Vcc

33 VCL VCL VCL VCL VCL VCL

34 P10/ DREQ0/

35 P11/ DREQ1/

36 P12/ TEND0/

37 P13/ TEND1/

38 P14/ DACK0/

39 P15/ DACK1/

40 P16/PO14/

41 P17/PO15/

42 P20/PO0-A/

43 P21/PO1-A/

44 P22/PO2-A/

Rev. 1.00 Sep. 19, 2008 Page 24 of 1270 REJ09B0466-0100 Pin No. Pin Name Mode 7 120-PIn Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Flash Memory Programmer Mode

45 P23/PO3-A/

46 P24/PO4-A/

47 P25/ WAIT-B/

48 P26/PO6/

49 P27/PO7/

50 P85/PO5-B/

51 PE0/D0 PE0/D0 PE0/D0 PE0/D0 PE0 NC

52 PE1/D1 PE1/D1 PE1/D1 PE1/D1 PE1 NC

53 PE2/D2 PE2/D2 PE2/D2 PE2/D2 PE2 NC

54 PE3/D3 PE3/D3 PE3/D3 PE3/D3 PE3 NC

55 PE4/D4 PE4/D4 PE4/D4 PE4/D4 PE4 NC

56 PE5/D5 PE5/D5 PE5/D5 PE5/D5 PE5 NC

57 PE6/D6 PE6/D6 PE6/D6 PE6/D6 PE6 NC

58 Vss Vss Vss Vss Vss Vss

59 PE7/D7 PE7/D7 PE7/D7 PE7/D7 PE7 NC

60 Vcc Vcc Vcc Vcc Vcc Vcc

61 D8 D8 D8 D8 PD0 I/O0

62 D9 D9 D9 D9 PD1 I/O1

63 D10 D10 D10 D10 PD2 I/O2

64 D11 D11 D11 D11 PD3 I/O3

65 D12 D12 D12 D12 PD4 I/O4

66 D13 D13 D13 D13 PD5 I/O5

67 D14 D14 D14 D14 PD6 I/O6

68 D15 D15 D15 D15 PD7 I/O7

Rev. 1.00 Sep. 19, 2008 Page 25 of 1270 REJ09B0466-0100 Pin No. Pin Name Mode 7 120-PIn Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Flash Memory Programmer Mode

69 PF0/ WAIT-A/

70 PF1/ CS5/UCAS/

71 PF2/ CS6/

72 PF3/ LWR/

73 HWR HWR HWR HWR PF4 NC

74 RD RD RD RD PF5 NC

75 PF6/ AS/AH PF6/ AS/AH PF6/ AS/AH PF6/ AS/AH PF6 NC

76 PLLVcc PLLVcc PLLVcc PLLVcc PLLVcc Vcc

77 RES RES RES RES RES RES

78 PLLVss PLLVss PLLVss PLLVss PLLVss Vss

79 PF7/ φ PF7/ φ PF7/ φ PF7/ φ PF7/ φ NC

80 Vss Vss Vss Vss Vss Vss

81 XTAL XTAL XTAL XTAL XTAL XTAL

82 EXTAL EXTAL EXTAL EXTAL EXTAL EXTAL

83 Vcc Vcc Vcc Vcc Vcc Vcc

84 Vcc Vcc Vcc Vcc Vcc Vcc

85 P83/PO3-B/

86 P81/PO1-B/

87 Vss Vss Vss Vss Vss Vss

88 STBY STBY STBY STBY STBY Vcc

89 PG0/ CS0 PG0/ CS0 PG0/ CS0 PG0/ CS0 PG0 NC

90 PG1/ CS1 PG1/ CS1 PG1/ CS1 PG1/ CS1 PG1 NC

91 PG2/ CS2/RAS2*

PG2/ CS2/RAS2* PG2/ CS2/RAS2* PG2/ CS2/RAS2* PG2 NC

92 PG3/ CS3/RAS3*

PG3/ CS3/RAS3* PG3/ CS3/RAS3* PG3/ CS3/RAS3* PG3 NC

93 AVcc AVcc AVcc AVcc AVcc Vcc

94 Vref Vref Vref Vref Vref Vcc

Rev. 1.00 Sep. 19, 2008 Page 26 of 1270 REJ09B0466-0100 Pin No. Pin Name Mode 7 120-PIn Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Flash Memory Programmer Mode

95 P40/ IRQ0-B/

AN0_0 P40/IRQ0-B/ AN0_0 P40/IRQ0-B/ AN0_0 P40/IRQ0-B/ AN0_0 P40/IRQ0-B/ AN0_0 NC

96 P41/ IRQ1-B/

AN1_0 P41/IRQ1-B/ AN1_0 P41/IRQ1-B/ AN1_0 P41/IRQ1-B/ AN1_0 P41/IRQ1-B/ AN1_0 NC

97 P42/ IRQ2-B/

AN2_0 P42/IRQ2-B/ AN2_0 P42/IRQ2-B/ AN2_0 P42/IRQ2-B/ AN2_0 P42/IRQ2-B/ AN2_0 NC

98 P43/ IRQ3-B/

AN3_0 P43/IRQ3-B/ AN3_0 P43/IRQ3-B/ AN3_0 P43/IRQ3-B/ AN3_0 P43/IRQ3-B/ AN3_0 Vss

99 P44/ IRQ4-B/

AN4_0 P44/IRQ4-B/ AN4_0 P44/IRQ4-B/ AN4_0 P44/IRQ4-B/ AN4_0 P44/IRQ4-B/ AN4_0 Vcc

100 P45/ IRQ5-B/

AN5_0 P45/IRQ5-B/ AN5_0 P45/IRQ5-B/ AN5_0 P45/IRQ5-B/ AN5_0 P45/IRQ5-B/ AN5_0 Vss

101 P46/ IRQ6-B/

AN6_0 P46/IRQ6-B/ AN6_0 P46/IRQ6-B/ AN6_0 P46/IRQ6-B/ AN6_0 P46/IRQ6-B/ AN6_0 NC

102 P47/ IRQ7-B/

AN7_0 P47/IRQ7-B/ AN7_0 P47/IRQ7-B/ AN7_0 P47/IRQ7-B/ AN7_0 P47/IRQ7-B/ AN7_0 NC

103 P94/AN12_1/DA2 P94/AN12_1/ DA2 P94/AN12_1/DA2 P94/AN 12_1/DA2 P94/AN12_1/DA2 NC

104 P95/AN13_1/DA3 P95/AN13_1/ DA3 P95/AN13_1/DA3 P95/AN 13_1/DA3 P95/AN13_1/DA3 NC

105 AVss AVss AVss AVss AVss Vss

106 PG4/ BREQO-A/

107 PG5/ BACK-A PG5/ BACK-A PG5/ BACK-A PG5/ BACK-A PG5 NC

108 PG6/ BREQ-A PG6/ BREQ-A PG6/ BREQ-A PG6/ BREQ-A PG6 NC

109 P50/ BREQO-B/

110 P51/ BREQ-B/

111 P52/ BACK-B/

112 P53/ IRQ3-A/

Rev. 1.00 Sep. 19, 2008 Page 27 of 1270 REJ09B0466-0100 Pin No. Pin Name Mode 7 120-PIn Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Flash Memory Programmer Mode

113 P35/ OE-B/

114 P34/SCK0/

115 P33/RxD1/SCL1 P33/RxD1/SCL1 P33/RxD1 /SCL1 P33/RxD1/SCL1 P33/RxD1/SCL1 NC

116 P32/RxD0/

117 P31/TxD1 P31/TxD1 P31/Tx D1 P31/TxD1 P31/TxD1 NC

118 P30/TxD0/IrTxD P30/TxD0/I rTxD P30/TxD0/IrTxD P30/Tx D0/IrTxD P30/TxD0/IrTxD NC

119 MD0 MD0 MD0 MD0 MD0 Vss

120 MD1 MD1 MD1 MD1 MD1 Vss

Rev. 1.00 Sep. 19, 2008 Page 28 of 1270 REJ09B0466-0100

1.4.3 Pin Functions

Table 1.5 Pin Functions Pin No. H8S/2426, H8S/2426R H8S/2424 Type Symbol FP-144LV TLP-145V FP-120BV I/O Function Power supply VCC 4, 72, 98, B2, N12, E11, E13 2, 60, 83, Input For connection to the power supply. VCC pins should be connected to the system power supply. V SS 2, 10, 18, 25, 50, 70, 95, 102 A1, E2, F4, H1, N5, M11, E10, F11 8, 17, 22, 58, 80, 87 Input For connection to ground. V SS pins should be connected to the system power supply (0 V). PLLV CC 91 H13 76 Input Power supply pin for the on- chip PLL oscillator. PLLV SS 93 G13 78 Input Ground pin for the on-chip PLL oscillator. VCL 41 L3 33 Output This pin must not be connected to the power supply and should be connected to the VSS pin via a 0.1-µF (recommended value) capacitor (place it close to pin). Clock XTAL 96 F12 81 Input For connection to a crystal oscillator. See section 23, Clock Pulse Generator, for typical connection diagrams for a crystal resonator and external clock input. EXTAL 97 F13 82 Input For connection to a crystal oscillator. The EXTAL pin can also input an external clock. See section 23, Clock Pulse Generator, for typical connection diagrams for a crystal resonator and external clock input. φ 94 F10 79 Output Supplies the system clock to external devices.

Rev. 1.00 Sep. 19, 2008 Page 29 of 1270 REJ09B0466-0100 Pin No. H8S/2426, H8S/2426R H8S/2424 Type Symbol FP-144LV TLP-145V FP-120BV I/O Function Clock SDRAM φ*

36 M1  Output When a synchronous DRAM

is connected, this pin is connected to the CLK pin of the synchronous DRAM. For details, refer to section 6, Bus Controller (BSC). Operating mode control MD2 MD1 MD0 144 143 120 119 Input These pins set the operating mode. These pins should not be changed during operation. System control RES 92 G12 77 Input Reset pin. When this pin is driven low, the chip is reset. STBY 103 D13 88 Input When this pin is driven low, a transition is made to hardware standby mode. EMLE 32 K1 30 Input On-chip emulator enable pin. When the on-chip emulator is used, this pin should be fixed high. At this time, pins P53, PG4 to PG6, and WDTOVF are used exclusively by the on-chip emulator. Therefore, the corresponding pin functions of those pins are not available. When the on-chip emulator is not used, this pin should be fixed low. BSCANE *  L9  Input Boundary scan enable pin. When the boundary scan function is used, this pin should be fixed high. At this time, pins P53, PG4 to PG6, and WDTOVF are used exclusively for boundary scan. Therefore, the corresponding pin functions of those pins are not available. When the boundary scan function is not used, this pin should be fixed low.

Rev. 1.00 Sep. 19, 2008 Page 30 of 1270 REJ09B0466-0100 Pin No. H8S/2426, H8S/2426R H8S/2424 Type Symbol FP-144LV TLP-145V FP-120BV I/O Function Address bus A23 to A0 31 to 26, 24 to 19, 17 to 11, 9 to 5 J3, K2, J1, K4, H3, J2, J4, G3, H2, G1, H4, G4, F1, G2, F3, E4, E1, F2, E3, D1, D3, D2, C3, C1 29 to 23, 21 to 18, 16 to 9, 7 to 3 Output These pins output an address. Data bus D15 to D0 80 to 73, 71, 69 to 63 K11, K12, L13, L11, M12, L12, N13, M13, N11, M11, N10, L9, M10, N9, K10, L8 68 to 61, 59, 57 to 51 Input/ output These pins constitute a bidirectional data bus. When an address/data multiplexed I/O space is accessed, an address is also output. Bus control CS7 to CS0 38 to 35, 110 to 107 M2, N2, M1, L1, A13, A12, B13, C12 29, 71, 70, 106, 92 to 89 Output Signals that select division areas 7 to 0 in the external address space AS 90 G10 75 Output When this pin is low, it indicates that address output on the address bus is valid. AH 90 G10 75 Output Signal for holding the address when an address/data multiplexed I/O space is being accessed. RD 89 G12 74 Output When this pin is low, it indicates that the external address space is being read.

Rev. 1.00 Sep. 19, 2008 Page 31 of 1270 REJ09B0466-0100 Pin No. H8S/2426, H8S/2426R H8S/2424 Type Symbol FP-144LV TLP-145V FP-120BV I/O Function Bus control HWR 88 H11 73 Output Strobe signal indicating that an external address space is to be written to, and the upper half (D15 to D8) of the data bus is enabled. Also functions as the write enable signal for accessing the DRAM space. LWR 87 J13 72 Output Strobe signal indicating that an external address space is to be written to, and the lower half (D7 to D0) of the data bus is enabled. BREQ-A BREQ-B 132 134 108 110 Input The external bus master requests the bus to this LSI. BREQO-A BREQO-B 130 133 106 109 Output External bus request signal when the internal bus master accesses an external space in the external bus release state. BACK-A BACK-B 131 135 107 111 Output Indicates the bus is released to the external bus master. UCAS 85 H12 70 Output Upper column address strobe signal for accessing the 16-bit DRAM space. Also functions as the column address strobe signal for accessing the 8-bit DRAM space. LCAS 86 H10 71 Output Lower column address strobe signal for accessing the 16-bit DRAM space. DQMU *

85 H12  Output Upper data mask enable

signal for accessing the 16-bit continuous synchronous DRAM space. Also functions as the data mask enable signal for accessing the 8-bit continuous synchronous DRAM space. DQML *

86 H10  Output Lower-data mask enable

signal for accessing the 16-bit continuous synchronous DRAM interface space.

Rev. 1.00 Sep. 19, 2008 Page 32 of 1270 REJ09B0466-0100 Pin No. H8S/2426, H8S/2426R H8S/2424 Type Symbol FP-144LV TLP-145V FP-120BV I/O Function Bus control RAS/RAS2 RAS3 RAS4* RAS5* 109 110 A12 A13 Output Row address strobe signal for the DRAM when the DRAM interface is set. RAS signal is a row address strobe signal when areas 2 to 5 are set as the continuous DRAM space. RAS*

109 A12  Output Row address strobe signal for

interface is set. CAS*

110 A13  Output Column address strobe signal

interface is set. WE*

35 L1  Output Write enable signal for the

synchronous DRAM interface is set. WAIT-A WAIT-B J11 Input Requests insertion of a wait state in the bus cycles when accessing an external 3-state address space. OE-A OE-B 137 113 Output Output enable signal when accessing the DRAM space. The output pins of OE and (OE) are selected by the port function control register 2 (PFCR2) of port 3. CKE-A * CKE-B* 137 Output Clock enable signal when the synchronous DRAM interface is set. The output pins of CKE and (CKE) are selected by the port function control register 2 (PFCR2) of port 3.

Rev. 1.00 Sep. 19, 2008 Page 33 of 1270 REJ09B0466-0100 Pin No. H8S/2426, H8S/2426R H8S/2424 Type Symbol FP-144LV TLP-145V FP-120BV I/O Function Interrupt signals NMI 40 N1 32 Input Nonmaskable interrupt request pin. This pin should be fixed high when not used. IRQ15-A to IRQ8-A* 86, 85, 106 to 104, 83 to 81 H10, H12, C13, D12, D10, J10, K13, J12 Input IRQ7-A to IRQ0-A 31 to 28, 136 to 133 J3, K2, J1, K4, D4, C6, B5, A6 29 to 26, 112 to 109 IRQ15-B to IRQ8-B* 58 to 51 K7, L8, N7, M7, N6, M6, L7, L6, IRQ7-B to IRQ0-B 38, 37, 61 to 59, 34, 33, 3 M2, N2, M8, N8, K8, K3, L2, C2 102 to 95 These pins request a maskable interrupt. The input pins of IRQn-A and IRQn-B are selected by the IRQ pin select register (ITSR) of the interrupt controller. (n = 0 to 15 for the H8S/2426 Group and H8S/2426R Group, n = 0 to 7 for the H8S/2424 Group) DREQ1 DREQ0 K13 J12 Input These signals request DMAC activation. DMA controller (DMAC) TEND1 TEND0 104 D10 J10 Output These signals indicate the end of DMAC data transfer. DACK1 DACK0 106 105 C13 D12 Output DMAC single address transfer acknowledge signals. EDREQ3 EDREQ2  Input These signals request EXDMAC activation. EXDMA controller (EXDMAC) ETEND3 ETEND2  Output These signals indicate the end of EXDMAC data transfer. EDACK3 EDACK2  Output EXDMAC single address transfer acknowledge signals. EDRAK3 EDRAK2  Output These signals notify an external device of acceptance and start of execution of a DMA transfer request.

Rev. 1.00 Sep. 19, 2008 Page 34 of 1270 REJ09B0466-0100 Pin No. H8S/2426, H8S/2426R H8S/2424 Type Symbol FP-144LV TLP-145V FP-120BV I/O Function 16-bit timer pulse unit (TPU) TCLKH TCLKG TCLKF TCLKE TCLKD TCLKC TCLKB TCLKA Input External clock input pins of the timer. TIOCA0 TIOCB0 TIOCC0 TIOCD0 Input/ output TGRA_0 to TGRD_0 input capture input/output compare output/PWM output pins. TIOCA1 TIOCB1 Input/ output TGRA_1 and TGRB_1 input capture input/output compare output/PWM output pins. TIOCA2 TIOCB2 Input/ output TGRA_2 and TGRB_2 input capture input/output compare output/PWM output pins. TIOCA3-A TIOCB3-A TIOCC3-A TIOCD3-A TIOCA3-B TIOCB3-B TIOCC3-B TIOCD3-B 133 134 109 110 Input/ output TGRA_3 to TGRD_3 input capture input/output compare output/PWM output pins. TIOCA4-A TIOCB4-A TIOCA4-B TIOCB4-B 135 111 Input/ output TGRA_4 and TGRB_4 input capture input/output compare output/PWM output pins. TIOCA5 TIOCB5 Input/ output TGRA_5 and TGRB_5 input capture input/output compare output/PWM output pins.

Rev. 1.00 Sep. 19, 2008 Page 35 of 1270 REJ09B0466-0100 Pin No. H8S/2426, H8S/2426R H8S/2424 Type Symbol FP-144LV TLP-145V FP-120BV I/O Function 16-bit timer pulse unit (TPU) TIOCA6 TIOCB6 TIOCC6 TIOCD6 Input/ output TGRA_6 to TGRD_6 input capture input/output compare output/PWM output pins. TIOCA7 TIOCB7 Input/ output TGRA_7 and TGRB_7 input capture input/output compare output/PWM output pins. TIOCA8 TIOCB8 Input/ output TGRA_8 and TGRB_8 input capture input/output compare output/PWM output pins. TIOCA9 TIOCB9 TIOCC9 TIOCD9 Input/ output TGRA_9 to TGRD_9 input capture input/output compare output/PWM output pins. TIOCA10 TIOCB10 Input/ output TGRA_10 and TGRB_10 input capture input/output compare output/PWM output pins. TIOCA11 TIOCB11 Input/ output TGRA_11 and TGRB_11 input capture input/output compare output/PWM output pins. PO15 to PO8 49 to 42 L5, K6, K5, N4, M5, L4, M4, N3 41 to 34 Output Pulse output pins. Program- mable pulse generator (PPG) PO7 PO6 PO5-A to PO0-A 58 to 51 K7, L8, N7, M7, N6, M6, L7, L6 49 to 42 PO5-B PO4-B PO3-B PO2-B PO1-B PO0-B 135 134 133 111 110 109

Rev. 1.00 Sep. 19, 2008 Page 36 of 1270 REJ09B0466-0100 Pin No. H8S/2426, H8S/2426R H8S/2424 Type Symbol FP-144LV TLP-145V FP-120BV I/O Function 8-bit timer (TMR) TMO0-A TMO1-A TMO0-B TMO1-B 105 106 135 D12 C13 111 Output Waveform output pins with output compare function. TMCI0-A TMCI1-A TMCI0-B TMCI1-B 104 134 J10 D10 110 Input External event input pins. TMRI0-A TMRI1-A TMRI0-B TMRI1-B 133 J12 K13 109 Input Counter reset input pins. Watchdog timer (WDT) WDTOVF 39 M3 31 Output Counter overflow signal output pin in watchdog timer mode. TxD4-A TxD4-B TxD3 TxD2 TxD1 TxD0/ IrTxD 133 141 142 109 117 118 Output Data output pins. Serial commu- nication interface (SCI)/ Smart Card interface (SCI_0 with IrDA function) RxD4-A RxD4-B RxD3 RxD2 RxD1 RxD0/ IrRxD 134 139 140 110 115 116 Input Data input pins. SCK4-A SCK4-B SCK3 SCK2 SCK1 SCK0 138 135 137 138 114 111 113 114 Input/ output Clock input/output pins.

Rev. 1.00 Sep. 19, 2008 Page 37 of 1270 REJ09B0466-0100 Pin No. H8S/2426, H8S/2426R H8S/2424 Type Symbol FP-144LV TLP-145V FP-120BV I/O Function SCL3 SCL2 SCL1 SCL0 134 139 137 110 115 113 Input/ output I C clock input/output pins. I C bus interface 2 (IIC2) SDA3 SDA2 SDA1 SDA0 133 140 138 109 116 114 Input/ output I C data input/output pins. SSO0-A SSO0-B Input/ output Data input/output pins. SSI0-A SSI0-B Input/ output Data input/output pins. Synchro- nous serial commu- nication unit (SSU) SSCK0-A SSCK0-B Input/ output Clock input/output pins. SCS0-A SCS0-B Input/ output Chip select input/output pins. TRST  D4  Input TAP controller reset pin. TMS  C7  Input Control signal input pin for boundary scan. Boundary scan* (JTAG) TDO  M3  Output Data output pin for boundary scan. TDI  D5  Input Data input pin for boundary scan. TCK  B6  Input Clock input pin for boundary scan.

Rev. 1.00 Sep. 19, 2008 Page 38 of 1270 REJ09B0466-0100 Pin No. H8S/2426, H8S/2426R H8S/2424 Type Symbol FP-144LV TLP-145V FP-120BV I/O Function A/D converter AN15_1* AN14_1* 128 127  Input Analog input pins. AN13_1 AN12_1 126 125 104 103 Input Analog input pins. AN11_1 to AN8_1* 124 to 121 B7, C8, D9, A9  Input Analog input pins. AN7_0 to AN0_0 120 to 113 B8, C9, B9, A10, C10, B10, C11, A11 102 to 95 Input Analog input pins. ADTRG0-A ADTRG0-B ADTRG1 136 J11 112 Input Pin for input of an external trigger to start A/D conversion. D/A converter DA3 DA2 126 125 104 103 Output Analog output pins. A/D converter, D/A converter AVCC 111 B11 93 Input Analog power-supply pin for the A/D converter and D/A converter. When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (+3 V). AV SS 129 A7 105 Input Ground pin for the A/D converter and D/A converter. This pin should be connected to the system power supply (0 V). Vref 112 B12 94 Input Reference voltage input pin for the A/D converter and D/A converter. When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (+3 V).

Rev. 1.00 Sep. 19, 2008 Page 39 of 1270 REJ09B0466-0100 Pin No. H8S/2426, H8S/2426R H8S/2424 Type Symbol FP-144LV TLP-145V FP-120BV I/O Function I/O ports P17 to P10 49 to 42 L5, K6, K5, N4, M5, L4, M4, N3 41 to 34 Input/ output 8-bit input/output pins. P27 to P20 58 to 51 K7, L8, N7, M7, N6, M6, L7, L6 49 to 42 Input/ output 8-bit input/output pins. P35 to P30 137 to 142 A5, B4, C5, A4, B3, C4 113 to 118 Input/ output 6-bit input/output pins. P47 to P40 120 to 113 B8, C9, B9, A10, C10, B10, C11, A11 102 to 95 Input 8-bit input pins. P53 to P50 136 to 133 D4, C6, B5, 112 to 109 Input/ output 4-bit input/output pins. P65 to P60 106 to 104, 83 to 81 C13, D12, D10, J10, K13, J12  Input/ output 6-bit input/output pins. P85 P84* P83 P82* P81 P80* Input/ output 6-bit input/output pins in the H8S/2426 Group and H8S/2426R Group. 3-bit input/output pins in the H8S/2424 Group. P97 * P96* P95, P94, P93 to P90* 128 to 121 D6, D7, D8, A8, B7, C8, D9, A9 104, 103 Input 8-bit input/output pins in the H8S/2426 Group and H8S/2426R Group. 2-bit input/output pins in the H8S/2424 Group. PA7 to PA0 31 to 26, 24, 23 J3, K2, J1, K4, H3, J2, J4, G3 29 to 23, Input/ output 8-bit input/output pins. PB7 to PB0 22 to 19, 17 to 14 H2, G1, H4, G4, F1, G2, F3, E4 20 to 18, 16 to 12 Input/ output 8-bit input/output pins. PC7 to PC0 13 to 11, 9 to 5 E1, F2, E3, D1, D3, D2, C3, C1 11 to 9, 7 to 3 Input/ output 8-bit input/output pins.

Rev. 1.00 Sep. 19, 2008 Page 40 of 1270 REJ09B0466-0100 Pin No. H8S/2426, H8S/2426R H8S/2424 Type Symbol FP-144LV TLP-145V FP-120BV I/O Function I/O ports PD7 to PD0 80 to 73 K11, K12, L13, L11, M12, L12, N13, M13 68 to 61 Input/ output 8-bit input/output pins. PE7 to PE0 71, 69 to 63 N11, M10, N10, K10, L10, M9, N9, K9 59, 57 to 51 Input/ output 8-bit input/output pins. PF7 to PF0 94, 90 to 84 F10, G10, G12, H11, J13, H10, H12, J11 79, 75 to 69 Input/ output 8-bit input/output pins. PG6 to PG0 132 to 130, 110 to 107 D5, C7, B6, A13, A12, B13, C12 108 to 106, 92 to 89 Input/ output 7-bit input/output pins. PH3 to PH0* 38 to 35 M2, N2, M1,  Input/ output 4-bit input/output pins. PJ2 * PJ1* PJ0* 101 100 E12 D11  Input 3-bit input pins. Notes: 1. Not supported by the H8S/2426 Group or H8S/2424R Group. 2. Can be used only in the 145-pin version. 3. Not supported by the H8S/2424 Group. 4. Can be used only in the 144-pin version.

Rev. 1.00 Sep. 19, 2008 Page 41 of 1270 REJ09B0466-0100 Section 2 CPU The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2600 CPU. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes.

2.1 Features

  • Upward-compatible with H8/300 and H8/300H CPUs Can execute H8/300 and H8/300H CPUs object programs
  • General-register architecture Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers
  • Sixty-nine basic instructions 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions Multiply-and-accumulate instruction
  • Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn] Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8]
  • 16-Mbyte address space Program: 16 Mbytes Data: 16 Mbytes
  • High-speed operation All frequently-used instructions execute in one or two states 8/16/32-bit register-register add/subtract: 1 state 8 × 8-bit register-register multiply: 2 states

Rev. 1.00 Sep. 19, 2008 Page 42 of 1270 REJ09B0466-0100 16 ÷ 8-bit register-register divide: 12 states 16 × 16-bit register-register multiply: 4 states 32 ÷ 16-bit register-register divide: 20 states

  • Two CPU operating modes Normal mode* Advanced mode Note: * Normal mode is not available in this LSI.
  • Power-down state Transition to power-down state by SLEEP instruction CPU clock speed selection

2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU

The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.

  • Register configuration The MAC register is supported only by the H8S/2600 CPU.
  • Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the H8S/2600 CPU.
  • The number of execution states of the MULXU and MULXS instructions

Rev. 1.00 Sep. 19, 2008 Page 43 of 1270 REJ09B0466-0100 Execution States Instruction Mnemoni c H8S/2600 H8S/2000 MULXU MULXU.B Rs, Rd 2 * 12 MULXU.W Rs, ERd 2 * 20 MULXS MULXS.B Rs, Rd 3 * 13 MULXS.W Rs, ERd 3 * 21 CLRMAC CLRMAC 1 * LDMAC LDMAC ERs, MACH 1 * LDMAC ERs, MACL 1 * STMAC STMAC MACH, ERd 1 * STMAC MACL, ERd 1 * Not supported Note: * The number of execution states is in cremented following a MAC instruction. In addition, there are differences in ad dress space, CCR and EXR register functions, power-down modes, etc., depending on the model.

2.1.2 Differences from H8/300 CPU

In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements.

  • More general registers and control registers Eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been added.
  • Expanded address space Normal mode supports the same 64-Kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 16-Mbyte address space.
  • Enhanced addressing The addressing modes have been enhanced to make effective use of the 16-Mbyte address space.
  • Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Signed multiply and divide instructions have been added. A multiply-and-accumulate instruction has been added. Two-bit shift and rotate instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added.

Rev. 1.00 Sep. 19, 2008 Page 44 of 1270 REJ09B0466-0100

  • Higher speed Basic instructions execute twice as fast. Note: Normal mode is not available in this LSI.

2.1.3 Differences from H8/300H CPU

In comparison to the H8/300H CPU, the H8S/2600 CPU has the following enhancements.

  • Additional control register One 8-bit and two 32-bit control registers have been added.
  • Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. A multiply-and-accumulate instruction has been added. Two-bit shift and rotate instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added.
  • Higher speed Basic instructions execute twice as fast.

Rev. 1.00 Sep. 19, 2008 Page 45 of 1270 REJ09B0466-0100

2.2 CPU Operating Modes

The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-Kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space. The mode is selected by the mode pins.

2.2.1 Normal Mode

The exception vector table and stack have the same structure as in the H8/300 CPU.

  • Address Space The H8S/2600 CPU provides linear access to a maximum 64-Kbyte address space.
  • Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain any value, even when the corresponding general register (Rn) is used as an address register. If the general register is referenced in the register indirect addressing mode with pre-decrement (@–Rn) or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding extended register (En) will be affected.
  • Instruction Set All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid.
  • Exception Vector Table and Memory Indirect Branch Addresses In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The exception vector table in normal mode is shown in figure 2.1. For details of the exception vector table, see section 4, Exception Handling. The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table.
  • Stack Structure When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.2. EXR is not pushed onto the stack in interrupt control mode 0. For details, see section 4, Exception Handling. Note: Normal mode is not available in this LSI.

Rev. 1.00 Sep. 19, 2008 Page 47 of 1270 REJ09B0466-0100

2.2.2 Advanced Mode

  • Address Space Linear access is provided to a 16-Mbyte maximum address space.
  • Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers.
  • Instruction Set All instructions and addressing modes can be used.
  • Exception Vector Table and Memory Indirect Branch Addresses In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.3). For details of the exception vector table, see section 4, Exception Handling. H'00000000 H'00000003 H'00000004 H'0000000B H'0000000C H'00000010 H'00000008 H'00000007 Reserved Reserved Reserved Reset exception vector (Reserved for system use) (Reserved for system use) Exception vector table Exception vector 1 Figure 2.3 Exception Vector Table (Advanced Mode)

Rev. 1.00 Sep. 19, 2008 Page 48 of 1270 REJ09B0466-0100 The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of this range is also used for the exception vector table.

  • Stack Structure In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.4. EXR is not pushed onto the stack in interrupt control mode 0. For details, see section 4, Exception Handling. PC (24 bits) EXR*1 Reserved*1 *3 CCR PC (24 bits) SP SP (SP*2 Reserved (a) Subroutine Branch (b) Exception Handling Notes: 1. When EXR is not used, it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored when returning. Figure 2.4 Stack Structure in Advanced Mode

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2.3 Address Space

Figure 2.5 shows a memory map of the H8S/2600 CPU. The H8S/2600 CPU provides linear access to a maximum 64-Kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes. H'0000 H'FFFF Note: * Normal mode cannot be used in this LSI. H'00000000 H'FFFFFFFF H'00FFFFFF

64 Kbytes 16 Mbytes

(b) Advanced Mode(a) Normal Mode* Figure 2.5 Memory Map Note: Normal mode is not available in this LSI.

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2.4 Registers

The H8S/2600 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8- bit extended register (EXR), an 8-bit condition code register (CCR), and a 64-bit multiply- accumulate register (MAC). TI 2 I 1 I 0EXR 76543210 PC MACH MACL MAC 63 3241 31 0 15 0 7 0 7 0 R0H R1H R2H R3H R4H R5H R6H R7H R0L R1L R2L R3L R4L R5L R6L R7L SP: PC: EXR: I2 to I0: CCR: UI: Stack pointer Program counter Extended register Trace bit Interrupt mask bits Condition-code register Interrupt mask bit User bit or interrupt mask bit* Half-carry flag User bit Negative flag Zero flag Overflow flag Carry flag Multiply-accumulate register ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) IU I HUNZVCCCR 76543210 MAC: General Registers (Rn) and Extended Registers (En) Control Registers (CR) [Legend] Sign extension ---- Note: * UI cannot be used as an interrupt mask bit in this LSI. Figure 2.6 CPU Registers

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2.4.1 General Registers

The H8S/2600 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. The usage of each register can be selected independently. General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.8 shows the stack.  Address registers  32-bit registers  16-bit registers  8-bit registers ER registers (ER0 to ER7) E registers (extended registers) (E0 to E7) R registers (R0 to R7) RH registers (R0H to R7H) RL registers (R0L to R7L) Figure 2.7 Usage of General Registers

Rev. 1.00 Sep. 19, 2008 Page 52 of 1270 REJ09B0466-0100 SP (ER7) Free area Stack area Figure 2.8 Stack

2.4.2 Program Counter (PC)

This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0.)

2.4.3 Extended Register (EXR)

EXR is an 8-bit register that can be manipulated by the LDC, STC, ANDC, ORC, and XORC instructions. When these instructions except for the STC instruction is executed, all interrupts including NMI will be masked for three states after execution is completed. Bit Bit Name Initial Value R/W Description

7 T 0 R/W Trace Bit

When this bit is set to 1, a trace exception is started each time an instruction is executed. When this bit is cleared to 0, instructions are executed in sequence. 6 to 3 — All 1 — Reserved These bits are always read as 1. R/W R/W R/W These bits designate the interrupt mask level (0 to 7). For details, refer to section 5, Interrupt Controller.

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2.4.4 Condition-Code Register (CCR)

This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. Bit Bit Name Initial Value R/W Description

7 I 1 R/W Interrupt Mask Bit

Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 by hardware at the start of an exception-handling sequence. For details, refer to section 5, Interrupt Controller.

6 UI Undefined R/W User Bit or Interrupt Mask Bit

Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit cannot be used as an interrupt mask bit in this LSI.

5 H Undefined R/W Half-Carry Flag

When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise.

4 U Undefined R/W User Bit

Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions.

3 N Undefined R/W Negative Flag

Stores the value of the most significant bit of data as a sign bit.

Rev. 1.00 Sep. 19, 2008 Page 54 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description

2 Z Undefined R/W Zero Flag

Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.

1 V Undefined R/W Overflow Flag

Set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise.

0 C Undefined R/W Carry Flag

Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:

  • Add instructions, to indicate a carry
  • Subtract instructions, to indicate a borrow
  • Shift and rotate instructions, to indicate a carry The carry flag is also used as a bit accumulator by bit manipulation instructions.

2.4.5 Multiply-Accumulate Register (MAC)

This 64-bit register stores the results of multiply-and-accumulate operations. It consists of two 32- bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the upper bits are a sign extension.

2.4.6 Initial Values of CPU Internal Registers

When the reset exception handling loads the start address from the vector address, PC is initialized, the T bit in EXR is cleared to 0, and the I bits in EXR and CCR are set to 1. However, the general registers and the other CCR bits are not initialized. The initial value of SP (ER7) is undefined. SP should therefore be initialized by using the MOV.L instruction immediately after a reset.

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2.5 Data Formats

The H8S/2600 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.

2.5.1 General Register Data Formats

Figure 2.9 shows the data formats in general registers. 7 0 7 0 MSB LSB MSB LSB 70 4 3 Don't care Don't care Don't care 7 04 3 Don't care6543271 0 7 0 Don't care 6543271 0 Don't care RnH RnL RnH RnL RnH RnL Data Type Register Number Data Format Byte data Byte data 4-bit BCD data 4-bit BCD data 1-bit data 1-bit data Upper Lower Upper Lower Figure 2.9 General Register Data Formats (1)

Rev. 1.00 Sep. 19, 2008 Page 56 of 1270 REJ09B0466-0100 15 0 MSB LSB 15 0 MSB LSB 31 16 MSB 15 0 LSBEn Rn ERn En Rn RnH RnL MSB LSB : General register ER : General register E : General register R : General register RH : General register RL : Most significant bit : Least significant bit Data Type Data FormatRegister Number Word data Word data Rn En Longword data Legend: ERn Figure 2.9 General Register Data Formats (2)

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2.5.2 Memory Data Formats

Figure 2.10 shows the data formats in memory. The H8S/2600 CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches. When SP (ER7) is used as an address register to access the stack, the operand size should be word size or longword size. 76 543210 MSB LSB MSB MSB LSB LSB Data Type Address 1-bit data Byte data Word data Address L Address L Address 2M Address 2M+1 Longword data Address 2N Address 2N+1 Address 2N+2 Address 2N+3 Data Format Figure 2.10 Memory Data Formats

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2.6 Instruction Set

The H8S/2600 CPU has 69 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Instruction Classification Function Instructions Size Types Data transfer MOV B/W/L 5 POP * , PUSH* W/L LDM, STM L MOVFPE * , MOVTPE* B ADD, SUB, CMP, NEG B/W/L 23 Arithmetic operations ADDX, SUBX, DAA, DAS B INC, DEC B/W/L ADDS, SUBS L MULXU, DIVXU, MULXS, DIVXS B/W EXTU, EXTS W/L TAS * B MAC, LDMAC, STMAC, CLRMAC — Logic operations AND, OR, XOR, NOT B/W/L 4 Shift SHAL, SHAR, SHLL, SH LR, ROTL, ROTR, ROTXL, ROTXR B/W/L 8 Bit manipulation BSET, BCLR, BNOT , BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR B 14 Branch Bcc * , JMP, BSR, JSR, RTS — 5 System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP — 9 Block data transfer EEPMOV — 1 Total: 69 Legend: B: Byte W: Word L: Longword ERn, @-SP. 2. Bcc is the general name for conditional branch instructions.

Rev. 1.00 Sep. 19, 2008 Page 59 of 1270 REJ09B0466-0100 3. Cannot be used in this LSI. 4. Only register ER0, ER1, ER4, or ER5 s hould be used when using the TAS instruction.

2.6.1 Table of Instructions Classified by Function

Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Operation Notation Symbol Description Rd General register (destination) * Rs General register (source) * Rn General register * ERn General register (32-bit register) MAC Multiply-accumulate register (32-bit register) (EAd) Destination operand (EAs) Source operand EXR Extended register CCR Condition-code register N N (negative) flag in CCR Z Z (zero) flag in CCR V V (overflow) flag in CCR C C (carry) flag in CCR PC Program counter SP Stack pointer #IMM Immediate data disp Displacement + Addition – Subtraction × Multiplication ÷ Division ∧ Logical AND ∨ Logical OR ⊕ Logical exclusive OR

Rev. 1.00 Sep. 19, 2008 Page 60 of 1270 REJ09B0466-0100 Symbol Description → Move ∼ NOT (logical complement) Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Table 2.3 Data Transfer Instructions Instruction Size * Function MOV B/W/L (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B Cannot be used in this LSI. MOVTPE B Cannot be used in this LSI. POP W/L @SP+ → Rn Pops a general register from the stack. POP.W Rn is identical to PUSH W/L Rn → @–SP Pushes a general register onto the stack. PUSH.W Rn is identical to LDM L @SP+ → Rn (register list) Pops two or more general registers from the stack. STM L Rn (register list) → @–SP Pushes two or more general registers onto the stack. Note: * Size refers to the operand size. B: Byte W: Word L: Longword

Rev. 1.00 Sep. 19, 2008 Page 61 of 1270 REJ09B0466-0100 Table 2.4 Arithmetic Operations Instructions (1) Instruction Size * Function ADD SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.) ADDX SUBX B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd Performs addition or subtraction with carry or borrow on byte data in two general registers, or on immediate data and data in a general register. INC DEC B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) ADDS SUBS L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. DAA DAS B Rd (decimal adjust) → Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. MULXU B/W Rd × Rs → Rd Performs unsigned multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits. MULXS B/W Rd × Rs → Rd Performs signed multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits. DIVXU B/W Rd ÷ Rs → Rd Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. Note: * Size refers to the operand size. B: Byte W: Word L: Longword

Rev. 1.00 Sep. 19, 2008 Page 62 of 1270 REJ09B0466-0100 Table 2.4 Arithmetic Operations Instructions (2) Instruction Size * Function DIVXS B/W Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. NEG B/W/L 0 – Rd → Rd Takes the two's complement (arithmetic complement) of data in a general register. EXTU W/L Rd (zero extension) → Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. EXTS W/L Rd (sign extension) → Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. TAS* B @ERd – 0, 1 → (<bit 7> of @ERd) Tests memory contents, and sets the most significant bit (bit 7) to 1. MAC — (EAs) × (EAd) + MAC → MAC Performs signed multiplication on memory contents and adds the result to the multiply-accumulate register. The following operations can be performed: 16 bits × 16 bits + 32 bits → 32 bits, saturating 16 bits × 16 bits + 42 bits → 42 bits, non-saturating CLRMAC — 0 → MAC Clears the multiply-accumulate register to zero. LDMAC STMAC L Rs → MAC, MAC → Rd Transfers data between a general register and a multiply-accumulate register. Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

Rev. 1.00 Sep. 19, 2008 Page 63 of 1270 REJ09B0466-0100 Table 2.5 Logic Operations Instructions Instruction Size * Function AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data. XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. NOT B/W/L ∼ (Rd) → (Rd) Takes the one's complement (logical complement) of general register contents. Note: * Size refers to the operand size. B: Byte W: Word L: Longword Table 2.6 Shift Instructions Instruction Size * Function SHAL SHAR B/W/L Rd (shift) → Rd Performs an arithmetic shift on general register contents. 1-bit or 2-bit shift is possible. SHLL SHLR B/W/L Rd (shift) → Rd Performs a logical shift on general register contents. 1-bit or 2-bit shift is possible. ROTL ROTR B/W/L Rd (rotate) → Rd Rotates general register contents. 1-bit or 2-bit rotation is possible. ROTXL ROTXR B/W/L Rd (rotate) → Rd Rotates general register contents through the carry flag. 1-bit or 2-bit rotation is possible. Note: * Size refers to the operand size. B: Byte W: Word L: Longword

Rev. 1.00 Sep. 19, 2008 Page 64 of 1270 REJ09B0466-0100 Table 2.7 Bit Manipulation Instructions (1) Instruction Size * Function BSET B 1 → (<bit-No.> of <EAd>) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → (<bit-No.> of <EAd>) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BNOT B ~ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>) Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BTST B ~ (<bit-No.> of <EAd>) → Z Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BAND BIAND B B ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BOR BIOR B B ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. Note: * Size refers to the operand size. B: Byte

Rev. 1.00 Sep. 19, 2008 Page 65 of 1270 REJ09B0466-0100 Table 2.7 Bit Manipulation Instructions (2) Instruction Size * Function BXOR BIXOR B B Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BLD BILD B B Transfers a specified bit in a general register or memory operand to the carry flag. Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data. BST BIST B B Transfers the carry flag value to a specified bit in a general register or memory operand. Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data. Note: * Size refers to the operand size. B: Byte

Rev. 1.00 Sep. 19, 2008 Page 66 of 1270 REJ09B0466-0100 Table 2.8 Branch Instructions Instruction Size Function Bcc — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic Description Condition BRA (BT) Always (true) Always BRN (BF) Never (false) Never BHI High C ∨ Z = 0 BLS Low or same C ∨ Z = 1 BCC (BHS) Carry clear (high or same) C = 0 BCS (BLO) Carry set (low) C = 1 BNE Not equal Z = 0 BEQ Equal Z = 1 BVC Overflow clear V = 0 BVS Overflow set V = 1 BPL Plus N = 0 BMI Minus N = 1 BGE Greater or equal N ⊕ V = 0 BLT Less than N ⊕ V = 1 BGT Greater than Z ∨ (N ⊕ V) = 0 BLE Less or equal Z ∨ (N ⊕ V) = 1 JMP — Branches unconditionally to a specified address. BSR — Branches to a subroutine at a specified address. JSR — Branches to a subroutine at a specified address. RTS — Returns from a subroutine.

Rev. 1.00 Sep. 19, 2008 Page 67 of 1270 REJ09B0466-0100 Table 2.9 System Control Instructions Instruction Size * Function TRAPA — Starts trap-instruct ion exception handling. RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. LDC B/W (EAs) → CCR, (EAs) → EXR Moves the contents of a general register or memory, or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. STC B/W CCR → (EAd), EXR → (EAd) Transfers CCR or EXR contents to a general register or memory. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. ANDC B CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR Logically ANDs the CCR or EXR contents with immediate data. ORC B CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR Logically ORs the CCR or EXR contents with immediate data. XORC B CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR Logically exclusive-ORs the CCR or EXR contents with immediate data. NOP — PC + 2 → PC Only increments the program counter. Note: * Size refers to the operand size. B: Byte W: Word

Rev. 1.00 Sep. 19, 2008 Page 68 of 1270 REJ09B0466-0100 Table 2.10 Block Data Transfer Instructions Instruction Size Function EEPMOV.B EEPMOV.W if R4L ≠ 0 then Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next; if R4 ≠ 0 then Repeat @ER5+ → @ER6+ R4–1 → R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed.

2.6.2 Basic Instruction Formats

The H8S/2600 Series instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2.11 shows examples of instruction formats.

  • Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields.
  • Register Field Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field.
  • Effective Address Extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.
  • Condition Field Specifies the branching condition of Bcc instructions.

Rev. 1.00 Sep. 19, 2008 Page 69 of 1270 REJ09B0466-0100 op op rn rm NOP, RTS, etc. ADD.B Rn, Rm, etc. MOV.B @(d:16, Rn), Rm, etc. rn rmop EA (disp) op cc EA (disp) BRA d:16, etc. (1) Operation field only (2) Operation field and register fields (3) Operation field, register fields, and effective address extension (4) Operation field, effective address extension, and condition field Figure 2.11 Instruction Formats (Examples)

2.7 Addressing Modes and Effective Address Calculation

The H8S/2600 CPU supports the eight addressing modes listed in table 2.11. The usable address modes are different in each instruction. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.

Rev. 1.00 Sep. 19, 2008 Page 70 of 1270 REJ09B0466-0100 Table 2.11 Addressing Modes No. Addressing Mode Symbol

1 Register direct Rn

2 Register indirect @ERn

3 Register indirect with displa cement @(d:16,ERn)/@(d:32,ERn)

4 Register indirect with post-increment

Register indirect with pre-decrement @ERn+ @–ERn

5 Absolute address @aa:8/@aa:16/@aa:24/@aa:32

6 Immediate #xx: 8/#xx:16/#xx:32

7 Program-counter relati ve @(d:8,PC)/@(d:16,PC)

8 Memory indirect @@aa:8

2.7.1 Register Direct—Rn

The register field of the instruction code specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.

2.7.2 Register Indirect—@ERn

The register field of the instruction code specifies an address register (ERn) which contains the address of the operand on memory. If the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00).

2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)

A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction code, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added.

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2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn

Register indirect with post-increment—@ERn+: The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even. Register indirect with pre-decrement—@-ERn: The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even.

2.7.5 Absolute Address—@aa:8 /@aa:16 / @aa:24 /@aa:32

The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). Table 2.12 indicates the accessible absolute address ranges. To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address, the upper 16 bits are a sign extension. A 32-bit absolute address can access the entire address space. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Table 2.12 Absolute Address Access Ranges Absolute Address Normal Mode * Advanced Mode Data address 8 bits (@aa:8) H 'FF00 to H'FFFF H'FFFF00 to H'FFFFFF 16 bits (@aa:16) H'0000 to H'FFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF 32 bits (@aa:32) H'000000 to H'FFFFFF Program instruction address 24 bits (@aa:24) Note: * Not available in this LSI.

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2.7.6 Immediate—#xx:8 / #xx:16/ #xx:32

The instruction code contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address.

2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC)

This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is sign-extended and added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is −126 to +128 bytes (–63 to +64 words) or −32766 to +32768 bytes (−16383 to +16384 words) from the branch instruction. The resulting value should be an even number.

2.7.8 Memory Indirect—@@aa:8

This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode the memory operand is a word operand and the branch address is 16 bits long. In advanced mode the memory operand is a longword operand, the first byte of which is assumed to be all 0 (H'00). Note that the first part of the address range is also the exception vector area. For further details, refer to section 4, Exception Handling. If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) Note: Normal mode is not available in this LSI.

Rev. 1.00 Sep. 19, 2008 Page 73 of 1270 REJ09B0466-0100 Specified by @aa:8 Specified by @aa:8Branch address Branch address Reserved (a) Normal Mode* (a) Advanced Mode Note: * Normal mode is not available in this LSI. Figure 2.12 Branch Address Specification in Memory Indirect Mode

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2.7.9 Effective Address Calculation

Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Note: Normal mode is not available in this LSI. Table 2.13 Effective Address Calculation (1) No Offset rop 31 0 31 23

3 Register indirect with displacement

@(d:16,ERn) or @(d:32,ERn) rop disp rop rmop rn 31 0 31 0 rop Don't care 31 2331 0 Don't care 31 0 disp 31 0 31 0 31 2331 0 Don't care 31 2331 0 Don't care Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Register direct (Rn) General register contents General register contents General register contents General register contents Sign extension Register indirect ( @ERn) Register indirect with post-increment or pre-decrement  Register indirect with post-increment @ERn+  Register indirect with pre-decrement @-ERn 1, 2, or 4 1, 2, or 4 Operand Size Byte Word Longword Operand is general register contents.

Rev. 1.00 Sep. 19, 2008 Page 75 of 1270 REJ09B0466-0100 Table 2.13 Effective Address Calculation (2) No op 31 2331 0 Don't careabs @aa:8 7 H'FFFF op 31 2331 0 Don't care @aa:16 op @aa:24 @aa:32 abs 1516 31 2331 0 Don't care 31 2331 0 Don't care abs op abs op IMM #xx:8/#xx:16/#xx:32 824 Addressing Mode and Instruction Format Absolute address Immediate Effective Address Calculation Effective Address (EA) Sign extension Operand is immediate data. 31 23

7 Program-counter relative

@(d:8,PC)/@(d:16,PC) Memory indirect @@aa:8  Normal mode*  Advanced mode 31 0 Don't care 23 0 disp 31 2331 0 Don't care dispop op abs 31 0 absH'000000 015 31 2331 0 Don't care H'00 op abs 31 0 absH'000000 031 Note: * Normal mode is not available in this LSI. PC contents Sign extension Memory contents Memory contents

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2.8 Processing States

The H8S/2600 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state transitions.

  • Reset State The CPU and on-chip peripheral modules are all initialized and stop. When the RES input goes low, all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. For details, refer to section 4, Exception Handling. The reset state can also be entered by a watchdog timer overflow.
  • Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to an exception source, such as, a reset, trace, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. For further details, refer to section 4, Exception Handling.
  • Program Execution State In this state the CPU executes program instructions in sequence.
  • Bus-Released State In a product which has a bus master other than the CPU, such as a direct memory access controller (DMAC) and a data transfer controller (DTC), the bus-released state occurs when the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts operations.
  • Program stop state This is a power-down state in which the CPU stops operating. The program stop state occurs when a SLEEP instruction is executed or the CPU enters hardware standby mode. For further details, refer to section 24, Power-Down Modes.

Rev. 1.00 Sep. 19, 2008 Page 77 of 1270 REJ09B0466-0100 Exception handling state Bus-released state Software standby mode Reset state*1 Sleep mode Power down state*3 Program execution state End of bus request Bus request RES = High STBY = High, RES = Low Reset state Hardware standby mode*2 End of bus requestBus request Request for exception handlingInterrupt request External interrupt request SSBY = 0SLEEP instructionSSBY = 1SL EEP inst ruction End o f exception handling Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever the RES pin goes low. A transition can also be made to the reset state when the watchdog timer overflows. 2. In every state, when the STBY pin becomes low, the hardware standby mode is entered. 3. For details, refer to section 24, Power-Down Modes. Figure 2.13 State Transitions

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2.9 Usage Note

2.9.1 Usage Notes on Bit-wise Operation Instructions

The BSET, BCLR, BNOT, BST, and BIST instructions are used to read data in byte-wise, operate the data in bit-wise, and write the result of the bit-wise operation in bit-wise again. Therefore, special care is necessary to use these instructions for the registers and the ports that include write- only bit. The BCLR instruction can be used to clear the flags in the internal I/O registers to 0. In this time, if it is obvious that the flag has been set to 1 in the interrupt handler, there is no need to read the flag beforehand.

Section 3 MCU Operating Modes Rev. 1.00 Sep. 19, 2008 Page 79 of 1270 REJ09B0466-0100 Section 3 MCU Operating Modes

3.1 Operating Mode Selection

The H8S/2426 Group, H8S/2426R Group, and H8S/2424 Group have five operating modes (modes 1 to 4 and 7). The operating mode is selected by the setting of mode pins (MD2 to MD0). Modes 1, 2, and 4 are externally expanded modes in which the CPU can access an external memory and peripheral devices. In an externally expanded mode, the external address space can be designated as an 8-bit or 16-bit address space for each area by the bus controller at the beginning of program execution. If a 16-bit address space is designated for any one area, the 16- bit bus mode is selected. If an 8-bit address space is designated for all areas, the 8-bit bus mode is selected. Mode 7 is a single-chip activation expanded mode in which the CPU can switch to access an external memory and peripheral devices at the beginning of program execution. Mode 3 is a boot mode in which the flash memory can be programmed or erased. For details on the boot mode, refer to section 21, Flash Memory. The settings for pins MD2 to MD0 should not be changed during LSI operation. Table 3.1 MCU Operating Modes External Data Bus MCU Operating Mode MD2 MD1 MD0 CPU Operating Mode Description On-Chip ROM Initial Value Max. Value 1* 0 0 1 Advanced Expanded mode with on-chip ROM disabled Disabled 16 bits 16 bits 2* 0 1 0 Advanced Expanded mode with on-chip ROM disabled Disabled 8 bits 16 bits 3 0 1 1 Advanced Boot mode Enabled  16 bits 4 1 0 0 Advanced Expanded mode with on-chip ROM enabled Enabled 8 bits 16 bits 7 1 1 1 Advanced Single-chip mode Enabled  16 bits Note: * Only modes 1 and 2 may be used in ROM-less versions.

Section 3 MCU Operating Modes Rev. 1.00 Sep. 19, 2008 Page 80 of 1270 REJ09B0466-0100

3.2 Register Descriptions

The following registers are related to operating mode setting.

  • Mode control register (MDCR)
  • System control register (SYSCR)

3.2.1 Mode Control Register (MDCR)

MDCR monitors the current operating mode of this LSI. Bit Bit Name Initial Value R/W Descriptions 7 to 3  All 0  Reserved These bits are always read as 0 and cannot be modified. MDS2 MDS1 MDS0 R R R Mode Select 2 to 0 These bits indicate the input levels at mode pins MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to pins MD2 to MD0, respectively. These bits are read-only bits and so they cannot be modified. The input levels of the MD2 to MD0 pins are latched into these bits when MDCR is read. These latches are canceled by a reset. Note: * Determined by the settings of pins MD2 to MD0.

3.2.2 System Control Register (SYSCR)

SYSCR selects saturation operation for the MAC instruction, controls CPU access to the flash memory control registers, sets the external bus mode, and enables or disables on-chip RAM.

Section 3 MCU Operating Modes Rev. 1.00 Sep. 19, 2008 Page 81 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Descriptions 7, 6  All 1 R/W Reserved The initial value should not be modified.

5 MACS 0 R/W MAC Saturation Operation Control

Selects either saturation operation or non-saturation operation for the MAC instruction. 0: MAC instruction performs non-saturation operation 1: MAC instruction performs saturation operation 4  0 R/W Reserved The initial value should not be modified.

3 FLSHE 0 R/W Flash Memory Control Register Enable

Controls CPU access to the flash memory control registers (FLMCR1, DFPR, and FLMSTR). If this bit is set to 1, the flash memory control registers can be read from and written to. If this bit is cleared to 0, the flash memory control registers are not selected. At this time, the contents of the flash memory control registers are retained. 0 should be written to this bit in LSIs other than the flash memory version. 0: Flash memory control registers are not selected for addresses H'FFFEB0 to H'FFFEB3 1: Flash memory control registers are selected for addresses H'FFFEB0 to H'FFFEB3 2  0  Reserved This bit is always read as 0 and cannot be modified.

1 EXPE  R/W External Bus Mode Enable

Sets the external bus mode. In modes 1, 2, and 4, this bit is fixed at 1 and cannot be modified. In modes 3 and 7, this bit can be read from and written to. Writing 0 to this bit when its value is 1 should only be carried out when an external bus cycle is not being executed. 0: External address space is disabled 1: External address space is enabled

0 RAME 1 R/W RAM Enable

Enables or disables the on-chip RAM. This bit is initialized when the reset state is canceled. 0: On-chip RAM is disabled 1: On-chip RAM is enabled

Section 3 MCU Operating Modes Rev. 1.00 Sep. 19, 2008 Page 82 of 1270 REJ09B0466-0100

3.3 Operating Mode Descriptions

3.3.1 Mode 1

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A to C function as an address bus, ports D and E function as a data bus, and parts of ports F to H function as bus control signals. The initial bus mode immediately after a reset is 16 bits, with 16-bit access to all areas. However, if 8-bit access is designated for all areas by the bus controller, the bus mode switches to 8 bits.

3.3.2 Mode 2

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A to C function as an address bus, ports D and E function as a data bus, and parts of ports F to H function as bus control signals. The initial bus mode immediately after a reset is 8 bits, with 8-bit access to all areas. However, if 16-bit access is designated for any one of the areas by the bus controller, the bus mode switches to 16 bits and port E functions as a data bus.

3.3.3 Mode 3

This mode is a boot mode of the flash memory. This mode is the same as mode 7, except for the programming and erasure of the flash memory. Mode 3 is only available in the flash memory version.

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3.3.4 Mode 4

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. The program in the on-chip ROM connected to the first half of area 0 is executed. Ports A to C function as input ports immediately after a reset, but can be set to function as an address bus depending on each port register setting. Port D functions as a data bus and parts of ports F to H function as bus control signals. For details on function switching of ports A to C, see section 10, I/O Ports. The initial bus mode immediately after a reset is 8 bits, with 8-bit access to all areas. However, if 16-bit access is designated for any one of the areas by the bus controller, the bus mode switches to 16 bits and port E functions as a data bus. In the flash memory version, user program mode is entered by setting the SWE bit in FMCMDEN to 1.

3.3.5 Mode 7

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled, and the LSI starts up in single-chip mode. External address spaces cannot be used in single-chip mode. The initial mode immediately after a reset is single-chip mode, with all I/O ports available for use as input/output ports. However, setting the EXPE bit in SYSCR to 1 switches the mode to an externally expanded mode in which the external address spaces are enabled. When an externally expanded mode is selected, all areas are initially designated as a 16-bit access space. The functions of pins in ports A to H are the same as those in an externally expanded mode with on-chip ROM enabled. In the flash memory version, user program mode is entered by setting the SWE bit in FMCMDEN to 1.

Section 3 MCU Operating Modes Rev. 1.00 Sep. 19, 2008 Page 84 of 1270 REJ09B0466-0100

3.3.6 Pin Functions

Table 3.2 shows the pin functions in each operating mode. Table 3.2 Pin Functions in Each Operating Mode Port Mode 1 Mode 2 Mode 3 Mode 4 Mode 7 Port A PA7 to PA5 P */A P */A P */A P */A P */A PA4 to PA0 A A Port B A A P */A P */A P */A Port C A A P */A P */A P */A Port D D D P */D D P */D Port E P/D * P */D P */D P */D P */D Port F PF7, PF6 P/C * P/C * P */C P/C * P */C PF5, PF4 C C C PF3 P/C * P/C * P/C * PF2 to PF0 P */C P */C P */C Port G PG6 to PG1 P */C P */C P */C P */C P */C PG0 P/C * P/C * Port H P */C P */C P */C P */C P */C [Legend] P: I/O port A: Address bus output D: Data bus input/output C: Control signals, clock input/output *: Immediately after a reset Note: Port H is not suppor ted in the H8S/2424 Group.

3.4 Memory Map in Each Operating Mode

Figures 3.1 to 3.5 show memory maps in each operating mode.

Section 3 MCU Operating Modes Rev. 1.00 Sep. 19, 2008 Page 85 of 1270 REJ09B0466-0100 H'000000 H'FEC000 H'FFC000 H'FFC800 H'000000 H'FFFA00 External address space Internal I/O registers External address space Internal I/O registers External address space/ Reserved area*2*4 H'FFFFFF H'FFFA00 H'FFFF00 H'FFFF20 H'FFFFFF H'FFFF00 H'FFFF20 H'040000 H'FEC000 H'FFC000 H'FFC800 Reserved area*4 External address space/ Reserved area*2*4 Data flash area 8 Kbytes*7 H'FE8000H'FE8000 H'F02000 H'F00000 RAM: 64 Kbytes*6/48 Kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) ROM: 256 Kbytes RAM: 64 Kbytes*6/48 Kbytes Mode 3 (Boot mode) External address space On-chip ROM On-chip RAM/Reserved area*3*5 External address space/ Reserved area*2*4 External address space/ Reserved area*2*4 Internal I/O registers Internal I/O registers Reserved area*4 Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0. 2. This area is specified as the external address space when EXPE = 1 and the reserved area when EXPE = 0. 3. On-chip RAM is used for flash memory programming. The RAME bit in SYSCR should not be cleared to 0. 4. A reserved area should not be accessed. Reserved area*4 H'080000 Reserved area*4 On-chip RAM*3 H'FF0000 Reserved area*4 H'FF0000 On-chip RAM/External address space*1 5. Area from H'FEC000 to H'FEFFFF in the H8S/24268, H8S/24268R, and H8S/24248 Groups is reserved and should not be accessed. 6. 64-Kbyte version (H8S/24269, H8S/24269R, and H8S/24249) is under development. 7. Data flash is in planning. On-chip RAM/External address space/ Reserved area*1*5 Figure 3.1 Memory Map in Each Operating Mode (ROM: 256-Kbyte Version): H8S/24269, H8S/24269R, H8S/24268, H8S/24268R, H8S/24249, and H8S/24248

Section 3 MCU Operating Modes Rev. 1.00 Sep. 19, 2008 Page 86 of 1270 REJ09B0466-0100 H'000000 H'FFFA00 On-chip ROM On-chip RAM/ External address space*3 H'FFFFFF H'FFFF00 H'FFFF20 H'040000 H'FEC000 H'FFC000 H'FFC800 H'FE8000 H'F02000 H'F00000 H'000000 H'FFFA00 On-chip ROM H'FFFFFF H'FFFF00 H'FFFF20 H'040000 External address space H'FEC000 H'FFC000 H'FFC800 H'FE8000 H'F02000 H'F00000 External address space Internal I/O registers External address space Internal I/O registers External address space/ Reserved area*2*4 Reserved area*4 On-chip RAM/External address space/ Reserved area*1*5 External address space/ Reserved area*2*4 External address space External address space/ Reserved area*2*4 External address space/ Reserved area*2*4 Internal I/O registers Internal I/O registers Reserved area*4 Reserved area*4 Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0. 2. This area is specified as the external address space when EXPE = 1 and the reserved area when EXPE = 0. 3. While EXPE = 1, this area is specified as the external address space when RAME = 0 and the on-chip RAM area when RAME = 1. While EXPE = 0, this area is specified as the on-chip RAM area. 4. A reserved area should not be accessed. Reserved area*4 ROM: 256 Kbytes RAM: 64 Kbytes*6 / 48 Kbytes Mode 4 (Expanded mode with on-chip ROM enabled) ROM: 256 Kbytes RAM: 64 Kbytes*6 / 48 Kbytes Mode 7 (Single-chip activation expanded mode with on-chip ROM enabled) Reserved area*4Reserved area*4 H'080000H'080000 Data flash area 8 Kbytes*7 H'FF0000 H'FF0000 On-chip RAM/ External address space*1 On-chip RAM/External address space/ Reserved area*3*5 Reserved area*4 5. Area from H'FEC000 to H'FEFFFF in the H8S/24268, H8S/24268R, and H8S/24248 Groups is reserved and should not be accessed. 6. 64-Kbyte version (H8S/24269, H8S/24269R, and H8S/24249) is under development. 7. Data flash is in planning. Figure 3.2 Memory Map in Each Operating Mode (ROM: 256-Kbyte Version): H8S/24269, H8S/24269R, H8S/24249, and H8S/24248

Section 3 MCU Operating Modes Rev. 1.00 Sep. 19, 2008 Page 87 of 1270 REJ09B0466-0100 H'000000 H'FFC000 H'FFC800 H'000000 H'FFFA00 External address space Internal I/O registers External address space Internal I/O registers External address space/ Reserved area*2*4 H'FFFFFF H'FFFA00 H'FFFF00 H'FFFF20 H'FFFFFF H'FFFF00 H'FFFF20 H'020000 H'FFC000 H'FFC800 Reserved area*4 External address space/ Reserved area*2*4 Data flash area 8 Kbytes*5 H'FE8000H'FE8000 H'F02000 H'F00000 RAM: 48 Kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) ROM: 128 Kbytes RAM: 48 Kbytes Mode 3 (Boot mode) External address space On-chip ROM External address space/ Reserved area*2*4 External address space/ Reserved area*2*4 Internal I/O registers Internal I/O registers Reserved area*4 Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0. 2. This area is specified as the external address space when EXPE = 1 and the reserved area when EXPE = 0. 3. On-chip RAM is used for flash memory programming. The RAME bit in SYSCR should not be cleared to 0. 4. A reserved area should not be accessed. Reserved area*4 H'080000 Reserved area*4 On-chip RAM*3 H'FF0000 Reserved area*4 H'FF0000 5. Data flash is in planning. On-chip RAM/ External address space*1 Figure 3.3 Memory Map in Each Operating Mode (ROM: 128-Kbyte Version): H8S/24265, H8S/24265R, and H8S/24245

Section 3 MCU Operating Modes Rev. 1.00 Sep. 19, 2008 Page 88 of 1270 REJ09B0466-0100 H'000000 H'FFFA00 On-chip ROM On-chip RAM/External address space*3 H'FFFFFF H'FFFF00 H'FFFF20 H'020000 H'FF0000 H'FFC000 H'FFC800 H'FE8000 H'F02000 H'F00000 H'000000 H'FFFA00 On-chip ROM H'FFFFFF H'FFFF00 H'FFFF20 H'020000 External address space H'FF0000 H'FFC000 H'FFC800 H'FE8000 H'F02000 H'F00000 External address space Internal I/O registers External address space Internal I/O registers External address space/ Reserved area*2*4 Reserved area*4 External address space/ Reserved area*2*4 External address space External address space/ Reserved area*2*4 External address space/ Reserved area*2*4 Internal I/O registers Internal I/O registers Reserved area*4 Reserved area*4 Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0. 2. This area is specified as the external address space when EXPE = 1 and the reserved area when EXPE = 0. 3. While EXPE = 1, this area is specified as the external address space when RAME = 0 and the on-chip RAM area when RAME = 1. While EXPE = 0, this area is specified as the on-chip RAM area. 4. A reserved area should not be accessed. Reserved area*4 ROM: 128 Kbytes RAM: 48 Kbytes Mode 4 (Expanded mode with on-chip ROM enabled) ROM: 128 Kbytes RAM: 48 Kbytes Mode 7 (Single-chip activation expanded mode with on-chip ROM enabled) Reserved area*4Reserved area*4 H'080000H'080000 Data flash area 8 Kbytes*5 On-chip RAM/External address space*1 Reserved area*4 5. Data flash is in planning. Figure 3.4 Memory Map in Each Operating Mode (ROM: 128-Kbyte Version): H8S/24265, H8S/24265R, and H8S/24245

Section 3 MCU Operating Modes Rev. 1.00 Sep. 19, 2008 Page 89 of 1270 REJ09B0466-0100 H'000000 H'FEC000 H'FFC000 H'FFC800 External address space Internal I/O registers External address space Internal I/O registersH'FFFFFF H'FFFA00 H'FFFF00 H'FFFF20 H'FE8000 RAM: 64 Kbytes*4 /48 Kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) External address space Reserved area*2 Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0. 2. A reserved area should not be accessed. Reserved area*2 H'FF0000 On-chip RAM/External address space*1*3 3. Area from H'FEC000 to H'FEFFFF in the H8S/24261, H8S/24261R, and H8S/24241 Groups is reserved and should not be accessed. 4. 64-Kbyte version (H8S/24262, H8S/24262R, and H8S/24242) is in planning. On-chip RAM/External address space/ Reserved area*1*3 Figure 3.5 Memory Map in Each Operating Mode (ROM-Less Version): H8S/24262, H8S/24262R, H8S/24261, H8S/24261R, H8S/24242, and H8S/24241

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Section 4 Exception Handling Rev. 1.00 Sep. 19, 2008 Page 91 of 1270 REJ09B0466-0100 Section 4 Exception Handling

4.1 Exception Handling Types and Priority

As table 4.1 indicates, exception handling may be caused by a reset, trace, interrupt, illegal instruction, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Exception sources, the stack structure, and operation of the CPU vary depending on the interrupt control mode. For details on the interrupt control mode, refer to section 5, Interrupt Controller. Table 4.1 Exception Types and Priority Priority Exception Type Start of Exception Handling High Reset Starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows. The CPU enters the reset state when the RES pin is low. Illegal instruction Starts when exec ution of an illegal instruction code is detected. Trace * Starts when execution of the currently executed instruction or exception handling ends, if the trace (T) bit in the EXR is set to 1. Direct transition * Starts when the direct transiti on occurs by execution of the SLEEP instruction. Interrupt Starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued. * Low Trap instruction * Started by execution of a trap instruction (TRAPA) Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not executed after execution of an RTE instruction. 2. Not available in this LSI. 3. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. 4. Trap instruction exception handling reques ts are accepted at all times in program execution state.

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4.2 Exception Sources and Exception Vector Table

Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Since the usable modes differ depending on the product, for details on each product, refer to section 3, MCU Operating Modes. Table 4.2 Exception Handling Vector Table Vector Address * Exception Source Vector Number Normal Mode * Advanced Mode Power-on reset 0 H'0000 to H'0001 H'0000 to H'0003 Manual reset*

1 H'0002 to H'0003 H'0004 to H'0007

Reserved for system use 2 H'000 4 to H'0005 H'000 8 to H'000B

3 H'0006 to H'0007 H'000C to H'000F

Illegal instruction 4 H'0008 to H'0019 H'0010 to H'0013 Trace 5 H'000A to H'000B H'0014 to H'0017 Interrupt (direct transition)*

6 H'000C to H'000D H'0018 to H'001B

Interrupt (NMI) 7 H'000E to H'000F H'001C to H'001F Trap instruction (#0) 8 H'001 0 to H'0011 H'0020 to H'0023 (#1) 9 H'0012 to H'0013 H'0024 to H'0027 (#2) 10 H'0014 to H'0015 H'0028 to H'002B (#3) 11 H'0016 to H'0017 H'002C to H'002F Reserved for system use 12 H'001 8 to H'0019 H' 0030 to H'0033

13 H'001A to H'001B H'0034 to H'0037

14 H'001C to H'001D H'0038 to H'003B

15 H'001E to H'001F H'003C to H'003F

External interrupt IRQ0 16 H'0020 to H'0021 H'0040 to H'0043 IRQ1 17 H'0022 to H'0023 H'0044 to H'0047 IRQ2 18 H'0024 to H'0025 H'0048 to H'004B IRQ3 19 H'0026 to H'0027 H'004C to H'004F IRQ4 20 H'0028 to H'0029 H'0050 to H'0053 IRQ5 21 H'002A to H'002B H'0054 to H'0057 IRQ6 22 H'002C to H'002D H'0058 to H'005B

Section 4 Exception Handling Rev. 1.00 Sep. 19, 2008 Page 93 of 1270 REJ09B0466-0100 Vector Address * Exception Source Vector Number Normal Mode * Advanced Mode External interrupt IRQ7 23 H'002E to H'002F H'005C to H'005F IRQ8 *

24 H'0030 to H'0031 H'0060 to H'0063

IRQ9 *

25 H'0032 to H'0033 H'0064 to H'0067

IRQ10 *

26 H'0034 to H'0035 H'0068 to H'006B

IRQ11 *

27 H'0036 to H'0037 H'006C to H'006F

IRQ12 *

28 H'0038 to H'0039 H'0070 to H'0073

External interrupt IRQ13 *

29 H'003A to H'003B H'0074 to H'0077

IRQ14 *

30 H'003C to H'003D H'0078 to H'007B

IRQ15 *

31 H'003E to H'003F H'007C to H'007F

Internal interrupt* 157 H'0040 to H'0041 H'013A to H'013B H'0080 to H'0083 H'0274 to H'0277 Notes: 1. Lower 16 bits of the address. 2. Not available in this LSI. 3. Not available in this LSI. It is reserved for system use. 4. For details of internal interrupt vectors, see section 5.5, Interrupt Exception Handling Vector Table. 5. Reserved for system use in the H8S/2424 Group.

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4.3 Reset

A reset has the highest exception priority. When the RES pin goes low, all processing halts and this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at power-up. To reset this LSI during operation, hold the RES pin low for at least 20 states. A reset initializes the internal state of the CPU and the registers of on-chip peripheral modules. This LSI can also be reset by overflow of the watchdog timer. For details see section 14, Watchdog Timer (WDT). The interrupt control mode is 0 immediately after reset.

4.3.1 Reset Exception Handling

When the RES pin goes high after being held low for the necessary time, this LSI starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR. 2. The reset exception handling vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figures 4.1 and 4.2 show examples of the reset sequence.

Section 4 Exception Handling Rev. 1.00 Sep. 19, 2008 Page 95 of 1270 REJ09B0466-0100 RES High Vector fetch Internal processing Prefetch of first program instruction (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction φ Internal address bus Internal read signal Internal write signal Internal data bus (1) (2) (4) (6) (3) (5) Figure 4.1 Reset Sequence (Advanced Mode with On-chip ROM Enabled)

Section 4 Exception Handling Rev. 1.00 Sep. 19, 2008 Page 96 of 1270 REJ09B0466-0100 RES RD HWR, LWR D15 to D0 High * * * φ Address bus Vector fetch Internal processing Prefetch of first program instruction (1) (2) (4) (6) (3) (5) (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction Note: * Seven program wait states are inserted. Figure 4.2 Reset Sequence (Advanced Mode with On-chip ROM Disabled)

4.3.2 Interrupts after Reset

If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx: 32, SP).

4.3.3 On-Chip Peripheral Functions after Reset Release

After reset release, MSTPCR is initialized to H'0FFF, EXMSTPCR is initialized to H'FFFF, and all modules except the DMAC, EXDMAC, and DTC enter module stop mode. Consequently, on-chip peripheral module registers cannot be read or written to. Register reading and writing is enabled when module stop mode is exited.

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4.4 Trace Exception Handling

Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details on interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is not affected by interrupt masking. Table 4.3 shows the state of CCR and EXR after execution of trace exception handling. Trace mode is canceled by clearing the T bit in EXR to 0. The T bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine by the RTE instruction, trace mode resumes. Trace exception handling is not carried out after execution of the RTE instruction. Interrupts are accepted even within the trace exception handling routine. Table 4.3 Status of CCR and EXR after Trace Exception Handling CCR EXR Interrupt Control Mode I UI I2 to I0 T 0 Trace exception handling cannot be used. 2 1 — — 0 [Legend] 1: Set to 1 0: Cleared to 0 —: Retains value prior to execution

4.5 Interrupt Exception Handling

Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to eight priority/mask levels to enable multiplexed interrupt control. The source to start interrupt exception handling and the vector address differ depending on the product. For details, refer to section 5, Interrupt Controller. The interrupt exception handling is as follows: 1. The values in the program counter (PC), condition code register (CCR), and extended register (EXR) are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution starts from that address.

Section 4 Exception Handling Rev. 1.00 Sep. 19, 2008 Page 98 of 1270 REJ09B0466-0100

4.6 Trap Instruction Exception Handling

Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The trap instruction exception handling is as follows: 1. The values in the program counter (PC), condition code register (CCR), and extended register (EXR) are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution starts from that address. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.4 shows the status of CCR and EXR after execution of trap instruction exception handling. Table 4.4 Status of CCR and EXR after Trap Instruction Exception Handling CCR EXR Interrupt Control Mode I UI I2 to I0 T 0 1    2 1   0 Legend: 1: Set to 1 0: Cleared to 0 —: Retains value prior to execution

Section 4 Exception Handling Rev. 1.00 Sep. 19, 2008 Page 99 of 1270 REJ09B0466-0100

4.7 Illegal Instruction Exception Handling

Illegal instruction exception handling starts when the CPU executing an illegal instruction code is detected. Illegal instruction exception handling can be executed at all times in the program execution state. The illegal instruction exception handling is as follows: 1. The values in the PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. An exception handling vector table address corresponding to the exception is generated, the start address of the exception service routine is loaded from the vector table to the PC, and program execution starts from that address. Table 4.5 shows the status of CCR and EXR after execution of illegal instruction exception handling. Table 4.5 Status of CCR and EXR after Illegal Instruction Exception Handling CCR EXR Interrupt Control Mode I UI T I2 to I0 0 1    2 1  0  Legend: 1: Set to 1 0: Cleared to 0 —: Retains value prior to execution Illegal instruction codes will not be searched for in the fields that do not affect instruction definitions, such as the EA extension or register fields. Instruction codes for an instruction formed with several words are detected independently, and combined instruction codes are not detected. Undefined instruction codes must not be executed. The general register contents after execution of an undefined instruction code or illegal instruction exception handling cannot be guaranteed. The stack pointer during illegal instruction exception handling and the PC value that will be saved are also not guaranteed.

Section 4 Exception Handling Rev. 1.00 Sep. 19, 2008 Page 100 of 1270 REJ09B0466-0100

4.8 Stack Status after Exception Handling

Figure 4.3 shows the stack after completion of trap instruction exception handling and interrupt exception handling. CCR CCR*1 PC (16 bits) SP EXR Reserved*1 CCR CCR*1 PC (16 bits) SP CCR PC (24 bits) SP EXR Reserved*1 CCR PC (24 bits) SP Normal Modes*2 Advanced Modes Interrupt control mode 0 Interrupt control mode 2 Interrupt control mode 0 Interrupt control mode 2 Notes: 1. Ignored on return. Normal modes are not available in this LSI. Figure 4.3 Stack Status after Exception Handling

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4.9 Usage Note

When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn (or MOV.W Rn, @-SP) PUSH.L ERn (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W Rn (or MOV.W @SP+, Rn) POP.L ERn (or MOV.L @SP+, ERn) Setting SP to an odd value may lead to a malfunction. Figure 4.4 shows an example of operation when the SP value is odd. SP CCR : PC : R1L : SP : Condition code register Program counter General register R1L Stack pointer CCR SP SP R1L H'FFFEFA H'FFFEFB H'FFFEFC H'FFFEFD H'FFFEFE H'FFFEFF PC PC TRAP instruction executed SP set to H'FFFEFF Data saved above SP MOV.B R1L, @-ER7 Contents of CCR lost Address Legend: Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. Figure 4.4 Operation when SP Value Is Odd

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Section 5 Interrupt Controller Rev. 1.00 Sep. 19, 2008 Page 103 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller

5.1 Features

  • Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the interrupt control register (INTCR).
  • Priorities settable with IPR An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI. NMI is assigned the highest priority level of 8, and can be accepted at all times.
  • Independent vector addresses All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine.
  • External interrupt pins NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge can be selected for NMI. Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQn-A and IRQn-B. Note: n = 15 to 0 for H8S/2426 Group, n = 7 to 0 for H8S/2424 Group
  • DTC and DMAC control DTC and DMAC activations are performed by means of interrupts.

Section 5 Interrupt Controller Rev. 1.00 Sep. 19, 2008 Page 104 of 1270 REJ09B0466-0100 A block diagram of the interrupt controller is shown in figure 5.1. INTCR NMI input IRQ input Internal interrupt sources SWDTEND to SSTXI INTM1 INTM0 NMIEG NMI input unit IRQ input unit ISR ISCRITSR IER IPR Interrupt controller Priority determination Interrupt request Vector number I I2 to I0 CCR EXR CPU Legend: ISCR: IRQ sense control register IER: IRQ enable register ISR: IRQ status register IPR: Interrupt priority register INTCR: Interrupt control register ITSR: IRQ pin select register Figure 5.1 Block Diagram of Interrupt Controller

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5.2 Input/Output Pins

Table 5.1 shows the pin configuration of the interrupt controller. Table 5.1 Pin Configuration Name I/O Function NMI Input Nonmaskable external interrupt Rising or falling edge can be selected. IRQ15-A to IRQ0-A* IRQ15-B to IRQ0-B* Input Maskable external interrupts Rising, falling, or both edges, or level sensing, can be selected. Note: * IRQ7-A to IRQ0-A and IRQ7-B to IRQ0-B in the H8S/2424 Group.

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5.3 Register Descriptions

The interrupt controller has the following registers.

  • Interrupt control register (INTCR)
  • IRQ sense control register H (ISCRH)
  • IRQ sense control register L (ISCRL)
  • IRQ enable register (IER)
  • IRQ status register (ISR)
  • IRQ pin select register (ITSR)
  • Software standby release IRQ enable register (SSIER)
  • Interrupt priority register A (IPRA)
  • Interrupt priority register B (IPRB)
  • Interrupt priority register C (IPRC)
  • Interrupt priority register D (IPRD)
  • Interrupt priority register E (IPRE)
  • Interrupt priority register F (IPRF)
  • Interrupt priority register G (IPRG)
  • Interrupt priority register H (IPRH)
  • Interrupt priority register I (IPRI)
  • Interrupt priority register J (IPRJ)
  • Interrupt priority register K (IPRK)
  • Interrupt priority register L (IPRL)
  • Interrupt priority register M (IPRM)
  • Interrupt priority register N (IPRN)

Section 5 Interrupt Controller Rev. 1.00 Sep. 19, 2008 Page 107 of 1270 REJ09B0466-0100

5.3.1 Interrupt Cont rol Register (INTCR)

INTCR selects the interrupt control mode, and the detected edge for NMI. Bit Bit Name Initial Value R/W Description 7, 6 — All 0 — Reserved These bits are always read as 0 and the initial value should not be changed. INTM1 INTM0 R/W R/W Interrupt Control Select Mode 1 and 0 These bits select either of two interrupt control modes for the interrupt controller. 00: Interrupt control mode 0 Interrupts are controlled by I bit. 01: Setting prohibited. 10: Interrupt control mode 2 Interrupts are controlled by bits I2 to I0, and IPR. 11: Setting prohibited.

3 NMIEG 0 R/W NMI Edge Select

Selects the input edge for the NMI pin. 0: Interrupt request generated at falling edge of NMI input 1: Interrupt request generated at rising edge of NMI input 2 to 0 — All 0 — Reserved These bits are always read as 0 and the initial value should not be changed.

Section 5 Interrupt Controller Rev. 1.00 Sep. 19, 2008 Page 108 of 1270 REJ09B0466-0100

5.3.2 Interrupt Priority Registers A to N (IPRA to IPRN)

IPR are eleven 16-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than NMI. The correspondence between interrupt sources and IPR settings is shown in table 5.2 (Interrupt Sources, Vector Addresses, and Interrupt Priorities). Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 14 to 12, 10 to 8, 6 to 4, and 2 to 0 sets the priority of the corresponding interrupt. IPR should be read in word size. Bit Bit Name Initial Value R/W Description 15 — 0 — Reserved This bit is always read as 0 and the initial value should not be changed. IPR14 IPR13 IPR12 R/W R/W R/W Sets the priority of the corresponding interrupt source. 000: Priority level 0 (Lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (Highest) 11 — 0 — Reserved This bit is always read as 0 and the initial value should not be changed. IPR10 IPR9 IPR8 R/W R/W R/W Sets the priority of the corresponding interrupt source. 000: Priority level 0 (Lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (Highest)

Section 5 Interrupt Controller Rev. 1.00 Sep. 19, 2008 Page 109 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description 7 — 0 — Reserved This bit is always read as 0 and the initial value should not be changed. IPR6 IPR5 IPR4 R/W R/W R/W Sets the priority of the corresponding interrupt source. 000: Priority level 0 (Lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (Highest) 3 — 0 — Reserved This bit is always read as 0 and the initial value should not be changed. IPR2 IPR1 IPR0 R/W R/W R/W Sets the priority of the corresponding interrupt source. 000: Priority level 0 (Lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (Highest)

Section 5 Interrupt Controller Rev. 1.00 Sep. 19, 2008 Page 110 of 1270 REJ09B0466-0100

5.3.3 IRQ Enable Register (IER)

IER controls enabling and disabling of interrupt requests IRQ15 to IRQ0. Bit Bit Name Initial Value R/W Description

15 IRQ15E 0 R/W IRQ15 Enable *

The IRQ15 interrupt request is enabled when this bit is 1.

14 IRQ14E 0 R/W IRQ14 Enable *

The IRQ14 interrupt request is enabled when this bit is 1.

13 IRQ13E 0 R/W IRQ13 Enable *

The IRQ13 interrupt request is enabled when this bit is 1.

12 IRQ12E 0 R/W IRQ12 Enable *

The IRQ12 interrupt request is enabled when this bit is 1.

11 IRQ11E 0 R/W IRQ11 Enable *

The IRQ11 interrupt request is enabled when this bit is 1.

10 IRQ10E 0 R/W IRQ10 Enable *

The IRQ10 interrupt request is enabled when this bit is 1.

9 IRQ9E 0 R/W IRQ9 Enable *

The IRQ9 interrupt request is enabled when this bit is 1.

8 IRQ8E 0 R/W IRQ8 Enable *

The IRQ8 interrupt request is enabled when this bit is 1.

7 IRQ7E 0 R/W IRQ7 Enable

The IRQ7 interrupt request is enabled when this bit is 1.

6 IRQ6E 0 R/W IRQ6 Enable

The IRQ6 interrupt request is enabled when this bit is 1.

Section 5 Interrupt Controller Rev. 1.00 Sep. 19, 2008 Page 111 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description

5 IRQ5E 0 R/W IRQ5 Enable

The IRQ5 interrupt request is enabled when this bit is 1.

4 IRQ4E 0 R/W IRQ4 Enable

The IRQ4 interrupt request is enabled when this bit is 1.

3 IRQ3E 0 R/W IRQ3 Enable

The IRQ3 interrupt request is enabled when this bit is 1.

2 IRQ2E 0 R/W IRQ2 Enable

The IRQ2 interrupt request is enabled when this bit is 1.

1 IRQ1E 0 R/W IRQ1 Enable

The IRQ1 interrupt request is enabled when this bit is 1.

0 IRQ0E 0 R/W IRQ0 Enable

The IRQ0 interrupt request is enabled when this bit is 1. Note: * These bits are reserved in the H8S/2424 Group.

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5.3.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)

ISCR select the source that generates an interrupt request at pins IRQ15 to IRQ0.

  • ISCRH (H8S/2426 Group only) Bit Bit Name Initial Value R/W Description IRQ15SCB IRQ15SCA R/W R/W IRQ15 Sense Control B IRQ15 Sense Control A 00: Interrupt request generated at IRQ15 input low level 01: Interrupt request generated at falling edge of IRQ15 input 10: Interrupt request generated at rising edge of IRQ15 input 11: Interrupt request generated at both falling and rising edges of IRQ15 input IRQ14SCB IRQ14SCA R/W R/W IRQ14 Sense Control B IRQ14 Sense Control A 00: Interrupt request generated at IRQ14 input low level 01: Interrupt request generated at falling edge of IRQ14 input 10: Interrupt request generated at rising edge of IRQ14 input 11: Interrupt request generated at both falling and rising edges of IRQ14 input IRQ13SCB IRQ13SCA R/W R/W IRQ13 Sense Control B IRQ13 Sense Control A 00: Interrupt request generated at IRQ13 input low level 01: Interrupt request generated at falling edge of IRQ13 input 10: Interrupt request generated at rising edge of IRQ13 input 11: Interrupt request generated at both falling and rising edges of IRQ13 input

Section 5 Interrupt Controller Rev. 1.00 Sep. 19, 2008 Page 113 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description IRQ12SCB IRQ12SCA R/W R/W IRQ12 Sense Control B IRQ12 Sense Control A 00: Interrupt request generated at IRQ12 input low level 01: Interrupt request generated at falling edge of IRQ12 input 10: Interrupt request generated at rising edge of IRQ12 input 11: Interrupt request generated at both falling and rising edges of IRQ12 input IRQ11SCB IRQ11SCA R/W R/W IRQ11 Sense Control B IRQ11 Sense Control A 00: Interrupt request generated at IRQ11 input low level 01: Interrupt request generated at falling edge of IRQ11 input 10: Interrupt request generated at rising edge of IRQ11 input 11: Interrupt request generated at both falling and rising edges of IRQ11 input IRQ10SCB IRQ10SCA R/W R/W IRQ10 Sense Control B IRQ10 Sense Control A 00: Interrupt request generated at IRQ10 input low level 01: Interrupt request generated at falling edge of IRQ10 input 10: Interrupt request generated at rising edge of IRQ10 input 11: Interrupt request generated at both falling and rising edges of IRQ10 input

Section 5 Interrupt Controller Rev. 1.00 Sep. 19, 2008 Page 114 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description IRQ9SCB IRQ9SCA R/W R/W IRQ9 Sense Control B IRQ9 Sense Control A 00: Interrupt request generated at IRQ9 input low level 01: Interrupt request generated at falling edge of IRQ9 input 10: Interrupt request generated at rising edge of IRQ9 input 11: Interrupt request generated at both falling and rising edges of IRQ9 input IRQ8SCB IRQ8SCA R/W R/W IRQ8 Sense Control B IRQ8 Sense Control A 00: Interrupt request generated at IRQ8 input low level 01: Interrupt request generated at falling edge of IRQ8 input 10: Interrupt request generated at rising edge of IRQ8 input 11: Interrupt request generated at both falling and rising edges of IRQ8 input

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  • ISCRL Bit Bit Name Initial Value R/W Description IRQ7SCB IRQ7SCA R/W R/W IRQ7 Sense Control B IRQ7 Sense Control A 00: Interrupt request generated at IRQ7 input low level 01: Interrupt request generated at falling edge of IRQ7 input 10: Interrupt request generated at rising edge of IRQ7 input 11: Interrupt request generated at both falling and rising edges of IRQ7 input IRQ6SCB IRQ6SCA R/W R/W IRQ6 Sense Control B IRQ6 Sense Control A 00: Interrupt request generated at IRQ6 input low level 01: Interrupt request generated at falling edge of IRQ6 input 10: Interrupt request generated at rising edge of IRQ6 input 11: Interrupt request generated at both falling and rising edges of IRQ6 input IRQ5SCB IRQ5SCA R/W R/W IRQ5 Sense Control B IRQ5 Sense Control A 00: Interrupt request generated at IRQ5 input low level 01: Interrupt request generated at falling edge of IRQ5 input 10: Interrupt request generated at rising edge of IRQ5 input 11: Interrupt request generated at both falling and rising edges of IRQ5 input

Section 5 Interrupt Controller Rev. 1.00 Sep. 19, 2008 Page 116 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description IRQ4SCB IRQ4SCA R/W R/W IRQ4 Sense Control B IRQ4 Sense Control A 00: Interrupt request generated at IRQ4 input low level 01: Interrupt request generated at falling edge of IRQ4 input 10: Interrupt request generated at rising edge of IRQ4 input 11: Interrupt request generated at both falling and rising edges of IRQ4 input IRQ3SCB IRQ3SCA R/W R/W IRQ3 Sense Control B IRQ3 Sense Control A 00: Interrupt request generated at IRQ3 input low level 01: Interrupt request generated at falling edge of IRQ3 input 10: Interrupt request generated at rising edge of IRQ3 input 11: Interrupt request generated at both falling and rising edges of IRQ3 input IRQ2SCB IRQ2SCA R/W R/W IRQ2 Sense Control B IRQ2 Sense Control A 00: Interrupt request generated at IRQ2 input low level 01: Interrupt request generated at falling edge of IRQ2 input 10: Interrupt request generated at rising edge of IRQ2 input 11: Interrupt request generated at both falling and rising edges of IRQ2 input

Section 5 Interrupt Controller Rev. 1.00 Sep. 19, 2008 Page 117 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description IRQ1SCB IRQ1SCA R/W R/W IRQ1 Sense Control B IRQ1 Sense Control A 00: Interrupt request generated at IRQ1 input low level 01: Interrupt request generated at falling edge of IRQ1 input 10: Interrupt request generated at rising edge of IRQ1 input 11: Interrupt request generated at both falling and rising edges of IRQ1 input IRQ0SCB IRQ0SCA R/W R/W IRQ0 Sense Control B IRQ0 Sense Control A 00: Interrupt request generated at IRQ0 input low level 01: Interrupt request generated at falling edge of IRQ0 input 10: Interrupt request generated at rising edge of IRQ0 input 11: Interrupt request generated at both falling and rising edges of IRQ0 input

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5.3.5 IRQ Status Register (ISR)

ISR is an IRQ15 to IRQ0 interrupt request flag register. Bit Bit Name Initial Value R/W Description IRQ15F* IRQ14F* IRQ13F* IRQ12F* IRQ11F* IRQ10F* IRQ9F* IRQ8F* IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* [Setting condition] When the interrupt source selected by ISCR occurs [Clearing conditions]

  • Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag
  • When interrupt exception handling is executed when low-level detection is set and IRQn input is high
  • When IRQn interrupt exception handling is executed when falling, rising, or both-edge detection is set
  • When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the DTC is cleared to 0 Notes: 1. Only 0 can be wr itten, to clear the flag. 2. These bits are reserved in the H8S/2424 Group.

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5.3.6 IRQ Pin Select Register (ITSR)

ITSR selects input pins IRQ15 to IRQ0.

  • H8S/2426 Group Bit Bit Name Initial Value R/W Description 15 ITS15 0 R/W Selects the IRQ15 input pin. 0: PF2/IRQ15-A selected 1: P27/IRQ15-B selected 14 ITS14 0 R/W Selects the IRQ14 input pin. 0: PF1/IRQ14-A selected 1: P26/IRQ14-B selected 13 ITS13 0 R/W Selects the IRQ13 input pin. 0: P65/IRQ13-A selected 1: P25/IRQ13-B selected 12 ITS12 0 R/W Selects the IRQ12 input pin. 0: P64/IRQ12-A selected 1: P24/IRQ12-B selected 11 ITS11 0 R/W Selects the IRQ11 input pin. 0: P63/IRQ11-A selected 1: P23/IRQ11-B selected 10 ITS10 0 R/W Selects the IRQ10 input pin. 0: P62/IRQ10-A selected 1: P22/IRQ10-B selected 9 ITS9 0 R/W Selects the IRQ9 input pin. 0: P61/IRQ9-A selected 1: P21/IRQ9-B selected 8 ITS8 0 R/W Selects the IRQ8 input pin. 0: P60/IRQ8-A selected 1: P20/IRQ8-B selected 7 ITS7 0 R/W Selects the IRQ7 input pin. 0: PA7/IRQ7-A selected 1: PH3/IRQ7-B selected

Section 5 Interrupt Controller Rev. 1.00 Sep. 19, 2008 Page 120 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description 6 ITS6 0 R/W Selects the IRQ6 input pin. 0: PA6/IRQ6-A selected 1: PH2/IRQ6-B selected 5 ITS5 0 R/W Selects the IRQ5 input pin. 0: PA5/IRQ5-A selected 1: P85/IRQ5-B selected 4 ITS4 0 R/W Selects the IRQ4 input pin. 0: PA4/IRQ4-A selected 1: P84/IRQ4-B selected 3 ITS3 0 R/W Selects the IRQ3 input pin. 0: P53/IRQ3-A selected 1: P83/IRQ3-B selected 2 ITS2 0 R/W Selects the IRQ2 input pin. 0: P52/IRQ2-A selected 1: P82/IRQ2-B selected 1 ITS1 0 R/W Selects the IRQ1 input pin. 0: P51/IRQ1-A selected 1: P81/IRQ1-B selected 0 ITS0 0 R/W Selects the IRQ0 input pin. 0: P50/IRQ0-A selected 1: P80/IRQ0-B selected

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  • H8S/2424 Group Bit Bit Name Initial Value R/W Description 15 to 8 — All 0 R/W Reserved The initial value should not be changed. 7 ITS7 0 R/W Selects the IRQ7 input pin. 0: PA7/IRQ7-A selected 1: P47/IRQ7-B selected 6 ITS6 0 R/W Selects the IRQ6 input pin. 0: PA6/IRQ6-A selected 1: P46/IRQ6-B selected 5 ITS5 0 R/W Selects the IRQ5 input pin. 0: PA5/IRQ5-A selected 1: P45/IRQ5-B selected 4 ITS4 0 R/W Selects the IRQ4 input pin. 0: PA4/IRQ4-A selected 1: P44/IRQ4-B selected 3 ITS3 0 R/W Selects the IRQ3 input pin. 0: P53/IRQ3-A selected 1: P43/IRQ3-B selected 2 ITS2 0 R/W Selects the IRQ2 input pin. 0: P52/IRQ2-A selected 1: P42/IRQ2-B selected 1 ITS1 0 R/W Selects the IRQ1 input pin. 0: P51/IRQ1-A selected 1: P41/IRQ1-B selected 0 ITS0 0 R/W Selects the IRQ0 input pin. 0: P50/IRQ0-A selected 1: P40/IRQ0-B selected

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5.3.7 Software Standby Release IRQ Enable Register (SSIER)

SSIER selects the IRQ pins used to recover from the software standby state. Bit Bit Name Initial Value R/W Description SSI15* SSI14* SSI13* SSI12* SSI11* SSI10* SSI9* SSI8* SSI7 SSI6 SSI5 SSI4 SSI3 SSI2 SSI1 SSI0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Software Standby Release IRQ Setting These bits select the IRQn pins used to recover from the software standby state. 0: IRQn requests are not sampled in the software standby state (Initial value when n = 15 to 3) 1: When an IRQn request occurs in the software standby state, the chip recovers from the software standby state after the elapse of the oscillation settling time (Initial value when n = 2 to 0) Note: * These bits are reserved in the H8S/2424 Group.

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5.4 Interrupt Sources

5.4.1 External Interrupts

The H8S/2426 Group and H8S/2426R Group each have seventeen external interrupts: NMI and IRQ15 to IRQ0. The H8S/2424 Group has nine external interrupts: NMI and IRQ7 to IRQ0. These interrupts can be used to restore the chip from software standby mode. NMI Interrupt: Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG bit in INTCR can be used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin. IRQn Interrupts (n = 0 to 15 for H8S/2426 Group and H8S/2426R Group, n = 0 to 7 for H8S/2424 Group): An IRQn interrupt is requested by an input signal at the IRQn pin. The IRQn interrupts have the following features:

  • Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at the IRQn pin.
  • Enabling or disabling of IRQn interrupt requests can be selected with IER.
  • The interrupt priority level can be set with IPR.
  • The status of IRQn interrupt requests is indicated in ISR. ISR flags can be cleared to 0 by software. When IRQn interrupt requests occur at low level of the IRQn pin, the corresponding IRQ pin should be held low until an interrupt handling starts. Then the corresponding IRQ pin should be set to high in the interrupt handling routine and clear the IRQnF bit in ISR to 0. Interrupts may not be executed when the corresponding IRQ pin is set to high before the interrupt handling starts. Detection of IRQn interrupts does not depend on whether the relevant pin has been set for input or output. However, when a pin is used as an external interrupt input pin, do not clear the corresponding DDR to 0 and use the pin as an I/O pin for another function.

Section 5 Interrupt Controller Rev. 1.00 Sep. 19, 2008 Page 124 of 1270 REJ09B0466-0100 A block diagram of IRQn interrupts is shown in figure 5.2. IRQn interrupt request IRQnE IRQnF S R Q Clear signal Edge/ level detection circuit IRQnSCA, IRQnSCB IRQn input Note: n = 0 to 15 for H8S/2426 Group and H8S/2426R Group, n = 0 to 7 for H8S/2424 Group Figure 5.2 Block Diagram of IRQ Interrupts

5.4.2 Internal Interrupts

The sources for internal interrupts from on-chip peripheral modules have the following features:

  • For each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. They can be controlled independently. When the enable bit is set to 1, an interrupt request is issued to the interrupt controller.
  • The interrupt priority level can be set by means of IPR.
  • The DMAC and DTC can be activated by a TPU, SCI, or other interrupt request.
  • When the DMAC or DTC is activated by an interrupt request, it is not affected by the interrupt control mode or CPU interrupt mask bit.

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5.5 Interrupt Exception Handling Vector Table

Table 5.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. When interrupt control mode 2 is set, priorities among modules can be set by means of the IPR. Modules set at the same priority will conform to their default priorities. Priorities within a module are fixed. Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities Vector Address* Interrupt Source Origin of Interrupt Source Vector Number Advanced Mode IPR Priority DTC Activation DMAC Activation NMI 7 H'001C  High   IRQ0 16 H'0040 IPRA14 to IPRA12  IRQ1 17 H'0044 IPRA10 to IPRA8  IRQ2 18 H'0048 IPRA6 to IPRA4  IRQ3 19 H'004C IPRA2 to IPRA0  IRQ4 20 H'0050 IPRB14 to IPRB12  IRQ5 21 H'0054 IPRB10 to IPRB8  IRQ6 22 H'0058 IPRB6 to IPRB4  IRQ7 23 H'005C IPRB2 to IPRB0  IRQ8*

24 H'0060 IPRC14 to IPRC12 

IRQ9*

25 H'0064 IPRC10 to IPRC8 

IRQ10*

26 H'0068 IPRC6 to IPRC4 

IRQ11*

27 H'006C IPRC2 to IPRC0 

IRQ12*

28 H'0070 IPRD14 to IPRD12 

IRQ13*

29 H'0074 IPRD10 to IPRD8 

IRQ14*

30 H'0078 IPRD6 to IPRD4 

IRQ15*

31 H'007C IPRD2 to IPRD0 

DTC SWDTEND 32 H'0080 IPRE14 to IPRE12  WDT WOVI 33 H'0084 IPRE10 to IPRE8    Reserved for system use

34 H'0088 IPRE6 to IPRE4  

CMI 35 H'008C IPRE2 to IPRE0 Low  

Section 5 Interrupt Controller Rev. 1.00 Sep. 19, 2008 Page 126 of 1270 REJ09B0466-0100 Vector Address* Interrupt Source Origin of Interrupt Source Vector Number Advanced Mode IPR Priority DTC Activation DMAC Activation

36 H'0090    Reserved for

system use 37 H'0094 IPRF14 to IPRF12 High   A/D_0 ADI0 38 H'0098 IPRF10 to IPRF8 Reserved for system use

39 H'009C  

TPU_0 TGI0A 40 H'00A0 IPRF6 to IPRF4 TGI0B 41 H'00A4  TGI0C 42 H'00A8  TGI0D 43 H'00AC IPRF6 to IPRF4  TCI0V 44 H'00B0  

45 H'00B4  

46 H'00B8  

47 H'00BC

  TPU_1 TGI1A 48 H'00C0 IPRF2 to IPRF0 TGI1B 49 H'00C4  TCI1V 50 H'00C8   TCI1U 51 H'00CC   TPU_2 TGI2A 52 H'00D0 IPRG14 to IPRG12 TGI2B 53 H'00D4  TCI2V 54 H'00D8   TCI2U 55 H'00DC   TPU_3 TGI3A 56 H'00E0 IPRG10 to IPRG8 TGI3B 57 H'00E4  TGI3C 58 H'00E8  TGI3D 59 H'00EC  TCI3V 60 H'00F0  

61 H'00F4  

62 H'00F8  

63 H'00FC

Low  

Section 5 Interrupt Controller Rev. 1.00 Sep. 19, 2008 Page 127 of 1270 REJ09B0466-0100 Vector Address* Interrupt Source Origin of Interrupt Source Vector Number Advanced Mode IPR Priority DTC Activation DMAC Activation TPU_4 TGI4A 64 H'0100 IPRG6 to IPRG4 High TGI4B 65 H'0104  TCI4V 66 H'0108   TCI4U 67 H'010C   TPU_5 TGI5A 68 H'0110 IPRG2 to IPRG0 TGI5B 69 H'0114  TCI5V 70 H'0118   TCI5U 71 H'011C   TMR_0 CMIA0 72 H'0120 IPRH14 to IPRH12  CMIB0 73 H'0124  OVI0 74 H'0128   Reserved for system use

75 H'012C IPRH14 to IPRH12  

TMR_1 CMIA1 76 H'0130 IPRH10 to IPRH8  CMIB1 77 H'0134  OVI1 78 H'0138   Reserved for system use

79 H'013C  

DMAC DMTEND0A 80 H'0140 IPRH6 to IPRH4  DMTEND0B 81 H'0144  DMTEND1A 82 H'0148  DMTEND1B 83 H'014C 

84 H'0150 IPRH0 to IPRH0   EXDMAC*

system use 85 H'0154 IPRI14 to IPRI12   EXDMTEND

86 H'0158 IPRI10 to IPRI8  

87 H'015C IPRI6 to IPRI4 Low  

Section 5 Interrupt Controller Rev. 1.00 Sep. 19, 2008 Page 128 of 1270 REJ09B0466-0100 Vector Address* Interrupt Source Origin of Interrupt Source Vector Number Advanced Mode IPR Priority DTC Activation DMAC Activation SCI_0 ERI0 88 H'0160 IPRI2 to IPRI0 High   RXI0 89 H'0164 TXI0 90 H'0168 TEI0 91 H'016C   SCI_1 ERI1 92 H'0170 IPRJ14 to IPRJ12   RXI1 93 H'0174 TXI1 94 H'0178 TEI1 95 H'017C   SCI_2 ERI2 96 H'0180 IPRJ10 to IPRJ8   RXI2 97 H'0184  TXI2 98 H'0188  TEI2 99 H'018C   SCI_3 ERI3 100 H'0190 IPRJ6 to IPRJ4   RXI3 101 H'0194  TXI3 102 H'0198  TEI3 103 H'019C   SCI_4 ERI4 104 H'01A0 IPRJ2 to IPRJ0   RXI4 105 H'01A4  TXI4 106 H'01A8  TEI4 107 H'01AC  

108 H'01B0 IPRK14 to IPRK12  

109 H'01B4  

110 H'01B8  

111 H'01BC  

A/D_1 ADI1 112 H'01C0 IPRK10 to IPRK8 

113 H'01C4  

114 H'01C8  

115 H'01CC Low  

Section 5 Interrupt Controller Rev. 1.00 Sep. 19, 2008 Page 129 of 1270 REJ09B0466-0100 Vector Address* Interrupt Source Origin of Interrupt Source Vector Number Advanced Mode IPR Priority DTC Activation DMAC Activation IIC2_0 IICI0 116 H'01D0 IPRK6 to IPRK4 High   Reserved for system use

117 H'01D4  

IIC2_1 IICI1 118 H'01D8   Reserved for system use

119 H'01DC  

TGI6A 120 H'01E0  TGI6B 121 H'01E4  TGI6C 122 H'01E8  TGI6D 123 H'01EC  TPU_6 TCI6V 124 H'01F0 IPRK2 to IPRK0   TGI7A 125 H'01F4  TGI7B 126 H'01F8  TCI7V 127 H'01FC   TPU_7 TCI7U 128 H'0200 IPRL14 to IPRL12   TGI8A 129 H'0204  TGI8B 130 H'0208  TCI8V 131 H'020C   TPU_8 TCI8U 132 H'0210 IPRL10 to IPRL8   TGI9A 133 H'0214  TGI9B 134 H'0218  TGI9C 135 H'021C  TGI9D 136 H'0220  TPU_9 TCI9V 137 H'0224 IPRL6 to IPRL4   TPU_10 TGI10A 138 H'0228  TGI10B 139 H'022C  TCI10V 140 H'0230   TCI10U 141 H'0234 IPRL2 to IPRL0 Low  

Section 5 Interrupt Controller Rev. 1.00 Sep. 19, 2008 Page 130 of 1270 REJ09B0466-0100 Vector Address* Interrupt Source Origin of Interrupt Source Vector Number Advanced Mode IPR Priority DTC Activation DMAC Activation TGI11A 142 H'0238 High  TGI11B 143 H'023C  TCI11V 144 H'0240   TPU_11 TCI11U 145 H'0244 IPRM14 to IPRM12  

146 H'0248  

147 H'024C  

148 H'0250  

149 H'0254

 

150 H'0258  

151 H'025C  

 Reserved for system use

152 H'0260

  IIC2_2 IICI2 153 H'0264   IIC2_3 IICI3 154 H'0268 IPRM2 to IPRM0   SSERI 155 H'026C   SSRXI 156 H'0270   SSU SSTXI 157 H'0274 IPRN14 to IPRN12    158 H'0278  

159 H'027C  

160 H'0280  

161 H'0284

 

162 H'0288  

163 H'028C  

164 H'0290  

165 H'0294

 

166 H'0298  

167 H'029C  

168 H'02A0  

169 H'02A4

Low  

Section 5 Interrupt Controller Rev. 1.00 Sep. 19, 2008 Page 131 of 1270 REJ09B0466-0100 Vector Address* Interrupt Source Origin of Interrupt Source Vector Number Advanced Mode IPR Priority DTC Activation DMAC Activation  170 H'02A8  High   | | | | Reserved for system use

255 H'03FC Low  

Notes: 1. Lower 16 bits of the start address. 2. Not supported in the H8S/2424 Group.

Section 5 Interrupt Controller Rev. 1.00 Sep. 19, 2008 Page 132 of 1270 REJ09B0466-0100

5.6 Interrupt Control Modes and Interrupt Operation

The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by INTCR. Table 5.3 shows the differences between interrupt control mode 0 and interrupt control mode 2. Table 5.3 Interrupt Control Modes Interrupt Control Mode Priority Setting Registers Interrupt Mask Bits Description

0 Default I The priorities of interrupt sources are fixed at

the default settings. Interrupt sources except for NMI is masked by the I bit.

2 IPR I2 to I0 8 priority leve ls except for NMI can be set with

IPR. 8-level interrupt mask control is performed by bits I2 to I0.

Section 5 Interrupt Controller Rev. 1.00 Sep. 19, 2008 Page 133 of 1270 REJ09B0466-0100

5.6.1 Interrupt Control Mode 0

In interrupt control mode 0, interrupt requests except for NMI are masked by the I bit of CCR in the CPU. Figure 5.3 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending. If the I bit is cleared, an interrupt request is accepted. 3. Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to the priority system is accepted, and other interrupt requests are held pending. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI. 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table.

Section 5 Interrupt Controller Rev. 1.00 Sep. 19, 2008 Page 134 of 1270 REJ09B0466-0100 Program execution status Interrupt generated? NMI IRQ0 IRQ1 SSTXI I = 0 Save PC and CCR I ← 1 Read vector address Branch to interrupt handling routine Yes No Yes Yes Yes No No No Yes Yes No Hold pending Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0

Section 5 Interrupt Controller Rev. 1.00 Sep. 19, 2008 Page 135 of 1270 REJ09B0466-0100

5.6.2 Interrupt Control Mode 2

In interrupt control mode 2, mask control is done in eight levels for interrupt requests except for NMI by comparing the EXR interrupt mask level (I2 to I0 bits) in the CPU and the IPR setting. Figure 5.4 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. When interrupt requests are sent to the interrupt controller, the interrupt with the highest priority according to the interrupt priority levels set in IPR is selected, and lower-priority interrupt requests are held pending. If a number of interrupt requests with the same priority are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5.2 is selected. 3. Next, the priority of the selected interrupt request is compared with the interrupt mask level set in EXR. An interrupt request with a priority no higher than the mask level set at that time is held pending, and only an interrupt request with a priority higher than the interrupt mask level is accepted. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of the accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H'7. 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table.

Section 5 Interrupt Controller Rev. 1.00 Sep. 19, 2008 Page 136 of 1270 REJ09B0466-0100 Yes Program execution status Interrupt generated? NMI Level 6 interrupt? Mask level 5 or below? Level 7 interrupt? Mask level 6 or below? Save PC, CCR, and EXR Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Hold pending Level 1 interrupt? Mask level 0? Yes Yes No Yes Yes Yes No Yes Yes No No No No No No Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2

Section 5 Interrupt Controller Rev. 1.00 Sep. 19, 2008 Page 137 of 1270 REJ09B0466-0100

5.6.3 Interrupt Exception Handling Sequence

Figure 5.5 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory.

Section 5 Interrupt Controller Rev. 1.00 Sep. 19, 2008 Page 138 of 1270 REJ09B0466-0100 Interrupt handling routine instruction prefetch Internal operationVector fetchStack Instruction prefetch Internal operation Interrupt acceptance Interrupt level determination Wait for end of instructionInterrupt request signal Internal address bus Internal read signal Internal write signal Internal data bus φ (3) (1) (2) (4) (3) (5) (7) Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) Instruction code (Not executed.) Instruction prefetch address (Not executed.) SP-2 SP-4 Saved PC and saved CCR Vector address Interrupt handling routine start address (Vector address contents) Interrupt handling routine start address ((13) = (10)(12)) First instruction of interrupt handling routine (6) (8) (9) (11) (10) (12) (13) (14) (8) Figure 5.5 Interrupt Exception Handling

Section 5 Interrupt Controller Rev. 1.00 Sep. 19, 2008 Page 139 of 1270 REJ09B0466-0100

5.6.4 Interrupt Response Times

Table 5.4 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.4 are explained in table 5.5. This LSI is capable of fast word transfer to on-chip memory, and have the program area in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing. Table 5.4 Interrupt Response Times Normal Mode * Advanced Mode No. Execution Status Interrupt control mode 0 Interrupt control mode 2 Interrupt control mode 0 Interrupt control mode 2

1 Interrupt priority determination *

2 Number of wait st ates until executing

instruction ends* 1 to 19 +2·SI 1 to 19+2·SI 1 to 19+2·SI 1 to 19+2·SI

3 PC, CCR, EXR stack save 2·S K 3·S K 2·S K 3·S K

4 Vector fetch S I S I 2·S I 2·S I

5 Instruction fetch *

2·S I 2·S I 2·S I 2·S I

6 Internal processing *

Total (using on-chip memory) 11 to 31 12 to 32 12 to 32 13 to 33 Notes: 1. Two states in case of internal interrupt. 2. Refers to MULXS and DIVXS instructions. 3. Prefetch after interrupt acceptance and interrupt handling routine prefetch. 4. Internal processing after interrupt acceptan ce and internal processing after vector fetch. 5. Not available in this LSI.

Section 5 Interrupt Controller Rev. 1.00 Sep. 19, 2008 Page 140 of 1270 REJ09B0466-0100 Table 5.5 Number of States in Interrupt Handling Routine Execution Statuses Object of Access External Device

8 Bit Bus 16 Bit Bus

Instruction fetch SI 1 4 6+2m 2 3+m Branch address read SJ Stack manipulation SK Legend: m: Number of wait states in an external device access.

5.6.5 DTC and DMAC Acti vation by Interrupt

The DTC and DMAC can be activated by an interrupt. In this case, the following options are available:

  • Interrupt request to CPU
  • Activation request to DTC
  • Activation request to DMAC
  • Selection of a number of the above For details of interrupt requests that can be used to activate the DTC and DMAC, see table 5.2 and section 9, Data Transfer Controller (DTC) and section 7, DMA Controller (DMAC).

Section 5 Interrupt Controller Rev. 1.00 Sep. 19, 2008 Page 141 of 1270 REJ09B0466-0100

5.7 Usage Notes

5.7.1 Conflict between Interrupt Generation and Disabling

When an interrupt enable bit is cleared to 0 to mask interrupts, the masking becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt source flag is cleared to 0. Figure 5.6 shows an example in which the TCIEV bit in the TPU’s TIER_0 register is cleared to 0. The above conflict will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. Internal address bus Internal write signal φ TCIEV TCFV TCIV interrupt signal TIER_0 write cycle by CPU TCIV exception handling TIER_0 address Figure 5.6 Conflict between Interrupt Generation and Disabling

Section 5 Interrupt Controller Rev. 1.00 Sep. 19, 2008 Page 142 of 1270 REJ09B0466-0100

5.7.2 Instructions that Disable Interrupts

Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends.

5.7.3 Times when Interrupts are Disabled

There are times when interrupt acceptance is disabled by the interrupt controller. The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask level with an LDC, ANDC, ORC, or XORC instruction.

5.7.4 Interrupts during Execution of EEPMOV Instruction

Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the transfer is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W MOV.W R4,R4 BNEL1

5.7.5 Change of IRQ Pin Select Register (ITSR) Setting

When the ITSR setting is changed, an edge occurs internally and the IRQnF bit (n = 0 to 15 for H8S/2426 Group, n = 0 to 7 for H8S/2424 Group) of ISR may be set to 1 at the unintended timing if the selected pin level before the change is different from the selected pin level after the change. If the IRQn interrupt request (n = 0 to 15 for H8S/2426 Group, n = 0 to 7 for H8S/2424 Group) is enabled, the interrupt exception handling is executed. To prevent the unintended interrupt, ITSR setting should be changed while the IRQn interrupt request is disabled, then the IRQnF bit should be cleared to 0.

Section 5 Interrupt Controller Rev. 1.00 Sep. 19, 2008 Page 143 of 1270 REJ09B0466-0100

5.7.6 IRQ Status Register (ISR)

Depending on the pin status following a reset, IRQnF may be set to 1. Therefore, always read ISR and clear it to 0 after resets.

Section 5 Interrupt Controller Rev. 1.00 Sep. 19, 2008 Page 144 of 1270 REJ09B0466-0100

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 145 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus controller also has a bus arbitration function, and controls the operation of the bus mastershipthe CPU, DMA controller (DMAC), EXDMA controller (EXDMAC)*, and data transfer controller (DTC). A block diagram of the bus controller is shown in figure 6.1. Note: * Not supported by the H8S/2424 Group.

6.1 Features

  • Manages external address space in area units Manages the external address space divided into eight areas of 2 Mbytes Bus specifications can be set independently for each area Burst ROM, DRAM, synchronous DRAM* , and address/data multiplexed I/O interfaces can be set
  • Basic bus interface Chip select signals (CS0 to CS7) can be output for areas 0 to 7 8-bit access or 16-bit access can be selected for each area 2-state access or 3-state access can be selected for each area Program wait cycles can be inserted for each area Extension cycles can be inserted while CS is asserted for each area Wait cycles can be inserted by the WAIT pin The negation timing of the read strobe signal (RD) can be modified
  • Burst ROM interface Burst ROM interface can be set independently for areas 0 and 1
  • Address/data multiplexed I/O interface Address/data multiplexed I/O interface can be set for areas 6 and 7
  • DRAM interface DRAM interface can be set for areas 2 to 5
  • Synchronous DRAM interface* Continuous synchronous DRAM space can be set for areas 2 to 5

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 146 of 1270 REJ09B0466-0100

  • Idle cycle insertion Idle cycles can be inserted between external read cycles to different areas Idle cycles can be inserted before the write cycle after a read cycle Idle cycles can be inserted before the read cycle after a write cycle
  • Write buffer function External write cycles and internal accesses can be executed in parallel DMAC single address transfers and internal accesses can be executed in parallel
  • Bus arbitration function Includes a bus arbiter that arbitrates bus mastership between the CPU, DMAC, DTC, and EXDMAC* Notes: 1. Not supported by the H8S/2426 Group and H8S/2424 Group. 2. Not supported by the H8S/2424 Group.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 147 of 1270 REJ09B0466-0100 CS7 to CS0 WAIT BREQ BACK BREQO ABWCR ASTCR WTCRAH WTCRAL WTCRBH WTCRBL RDNCR MPXCR DRAMCR DRACCRH DRACCRL REFCR RTCNT RTCOR CSACRH CSACRL BROMCRH BROMCRL BCR Area decoder Internal address bus EXDMAC address bus External bus control signals Internal bus control signals Internal data bus Control registers Address selector External bus arbiter External bus controller Internal bus arbiter Internal bus controller Internal bus master bus request signal EXDMAC bus request signal Internal bus master bus acknowledge signal EXDMAC bus acknowledge signal CPU bus request signal DTC bus request signal DMAC bus request signal CPU bus acknowledge signal DTC bus acknowledge signal DMAC bus acknowledge signal Legend: ABWCR : Bus width control register ASTCR : Access state control register WTCRAH, WTCRAL, WTCRBH, and WTCRBL : Wait control registers AH, AL, BH, and BL RDNCR : Read strobe timing control register CSACRH and CSACRL : CS assertion period control registers H and L BROMCRH : Area 0 burst ROM interface control register BROMCRL : Area 1 burst ROM interface control register BCR : Bus control register MPXCR : Address/data multiplexed I/O control register DRAMCR : DRAM control register DRACCRH and DRACCRL : DRAM access control registers H and L REFCR : Refresh control register RTCNT : Refresh timer counter RTCOR : Refresh time constant register Figure 6.1 Block Diagram of Bus Controller

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 148 of 1270 REJ09B0466-0100

6.2 Input/Output Pins

Table 6.1 shows the pin configuration of the bus controller. Table 6.1 Pin Configuration Name Symbol I/O Function Address strobe AS Output Strobe signal indicating that normal space is accessed and address output on address bus is enabled. Address hold AH Output Signal indicating the timing for latching the address when the address/data multiplexed I/O space is set. Read RD Output Strobe signal indicating that normal space is being read. High write/write enable HWR/WE Output Strobe signal indicating that normal space is written to, and upper half (D15 to D8) of data bus is enabled or DRAM space write enable signal. Low write LWR Output Strobe signal indicating that normal space is written to, and lower half (D7 to D0) of data bus is enabled. Chip select 0 CS0 Output Strobe signal indicating that area 0 is selected. Chip select 1 CS1 Output Strobe signal indicating that area 1 is selected Chip select 2/ row address strobe 2/ row address strobe* CS2/ RAS2/ RAS* Output Strobe signal indicating that area 2 is selected, DRAM row address strobe signal when area 2 is DRAM space or areas 2 to 5 are set as continuous DRAM space, or row address strobe signal of the synchronous DRAM when the synchronous DRAM interface is selected. Chip select 3/ row address strobe 3/ column address strobe* CS3/ RAS3/ CAS* Output Strobe signal indicating that area 3 is selected, DRAM row address strobe signal when area 3 is DRAM space, or column address strobe signal of the synchronous DRAM when the synchronous DRAM interface is selected.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 149 of 1270 REJ09B0466-0100 Name Symbol I/O Function Chip select 4/ row address strobe 4/ write enable* CS4/ RAS4/ WE* Output Strobe signal indicating that area 4 is selected, DRAM row address strobe signal when area 4 is DRAM space, or write enable signal of the synchronous DRAM when the synchronous DRAM interface is selected. Chip select 5/ row address strobe 5/ SDRAMφ* CS5/ RAS5/ SDRAMφ* Output Strobe signal indicating that area 5 is selected, DRAM row address strobe signal when area 5 is DRAM space, or dedicated clock signal for the synchronous DRAM when the synchronous DRAM interface is selected. Chip select 6 CS6 Output Strobe signal indicating that area 6 is selected. Chip select 7 CS7 Output Strobe signal indicating that area 7 is selected. Upper column address strobe/ upper data mask enable* UCAS/ DQMU* Output 16-bit DRAM space upper column address strobe signal, 8-bit DRAM space column address strobe signal, upper data mask signal of 16-bit synchronous DRAM space, or data mask signal of 8-bit synchronous DRAM space. Lower column address strobe/ lower data mask enable* LCAS/ DQML* Output 16-bit DRAM space lower column address strobe signal or lower data mask signal for the 16-bit synchronous DRAM space. Output enable/clock enable OE/ CKE* Output Output enable signal for the DRAM space or clock enable signal for the synchronous DRAM space. Wait WAIT Input Wait request signal when accessing external address space. Bus request BREQ Input Request signal for release of bus to external bus master. Bus request acknowledge BACK Output Acknowledge signal indicating that bus has been released to external bus master. Bus request output BREQO Output External bus request signal used when internal bus master accesses external address space when external bus is released.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 150 of 1270 REJ09B0466-0100 Name Symbol I/O Function Data transfer acknowledge 1 (DMAC) DACK1 Output Data transfer acknowledge signal for single address transfer by DMAC channel Data transfer acknowledge 0 (DMAC) DACK0 DACK0 Data transfer acknowledge signal for single address transfer by DMAC channel Data transfer acknowledge 3* (EXDMAC) EDACK3* Output Data transfer acknowledge signal for single address transfer by EXDMAC channel 3. Data transfer acknowledge 2* (EXDMAC) EDACK2* Output Data transfer acknowledge signal for single address transfer by EXDMAC channel 2. Notes: 1. Not supported by t he H8S/2426 Group and H8S/2424 Group 2. Not supported by the H8S/2424 Group.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 151 of 1270 REJ09B0466-0100

6.3 Register Descriptions

The bus controller has the following registers.

  • Bus width control register (ABWCR)
  • Access state control register (ASTCR)
  • Wait control register AH (WTCRAH)
  • Wait control register AL (WTCRAL)
  • Wait control register BH (WTCRBH)
  • Wait control register BL (WTCRBL)
  • Read strobe timing control register (RDNCR)
  • CS assertion period control register H (CSACRH)
  • CS assertion period control register L (CSACRL)
  • Area 0 burst ROM interface control register (BROMCRH)
  • Area 1 burst ROM interface control register (BROMCRL)
  • Bus control register (BCR)
  • Address/data multiplexed I/O control register (MPXCR)
  • DRAM control register (DRAMCR)
  • DRAM access control register (DRACCR)
  • Refresh control register (REFCR)
  • Refresh timer counter (RTCNT)
  • Refresh time constant register (RTCOR)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 152 of 1270 REJ09B0466-0100

6.3.1 Bus Width Control Register (ABWCR)

ABWCR designates each area in the external address space as either 8-bit access space or 16-bit access space. Bit Bit Name Initial Value * R/W Description ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 R/W R/W R/W R/W R/W R/W R/W R/W Area 7 to 0 Bus Width Control These bits select whether the corresponding area is to be designated as 8-bit access space or 16-bit access space. 0: Area n is designated as 16-bit access space 1: Area n is designated as 8-bit access space (n = 7 to 0) Note: * In modes 2 and 4, ABWCR is initialized to 1. In modes 1 and 7, ABWCR is initialized to 0.

6.3.2 Access State Control Register (ASTCR)

ASTCR designates each area in the external address space as either 2-state access space or 3-state access space. Bit Bit Name Initial Value R/W Description AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 R/W R/W R/W R/W R/W R/W R/W R/W Area 7 to 0 Access State Control These bits select whether the corresponding area is to be designated as 2-state access space or 3-state access space. Wait state insertion is enabled or disabled at the same time. 0: Area n is designated as 2-state access space Wait state insertion in area n access is disabled 1: Area n is designated as 3-state access space Wait state insertion in area n access is enabled (n = 7 to 0)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 153 of 1270 REJ09B0466-0100

6.3.3 Wait Control Registers AH, AL, BH, and BL (WTCRAH, WTCRAL, WTCRBH,

and WTCRBL) WTCRA and WTCRB select the number of program wait states for each area in the external address space. In addition, CAS latency is set when a synchronous DRAM is connected.

  • WTCRAH Bit Bit Name Initial Value R/W Description 15 — 0 R Reserved This bit is always read as 0 and cannot be modified. W72 W71 W70 R/W R/W R/W Area 7 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 7 while AST7 bit in ASTCR = 1. 000: Program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted 101: 5 program wait states inserted 110: 6 program wait states inserted 111: 7 program wait states inserted 11 — 0 R Reserved This bit is always read as 0 and cannot be modified.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 154 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description W62 W61 W60 R/W R/W R/W Area 6 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 6 while AST6 bit in ASTCR = 1. 000: Program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted 101: 5 program wait states inserted 110: 6 program wait states inserted 111: 7 program wait states inserted

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 155 of 1270 REJ09B0466-0100

  • WTCRAL Bit Bit Name Initial Value R/W Description 7 — 0 R Reserved This bit is always read as 0 and cannot be modified. W52 W51 W50 R/W R/W R/W Area 5 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 5 while AST5 bit in ASTCR = 1. 000: Program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted 101: 5 program wait states inserted 110: 6 program wait states inserted 111: 7 program wait states inserted 3 — 0 R Reserved This bit is always read as 0 and cannot be modified. W42 W41 W40 R/W R/W R/W Area 4 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 4 while AST4 bit in ASTCR = 1. 000: Program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted 101: 5 program wait states inserted 110: 6 program wait states inserted 111: 7 program wait states inserted

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  • WTCRBH Bit Bit Name Initial Value R/W Description 15 — 0 R Reserved This bit is always read as 0 and cannot be modified. W32 W31 W30 R/W R/W R/W Area 3 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 3 while AST3 bit in ASTCR = 1. 000: Program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted 101: 5 program wait states inserted 110: 6 program wait states inserted 111: 7 program wait states inserted 11 — 0 R Reserved This bit is always read as 0 and cannot be modified.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 157 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description W22 W21 W20 R/W R/W R/W Area 2 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 2 while AST2 bit in ASTCR = 1. A CAS latency is set when the synchronous DRAM* is connected. The setting of area 2 is reflected to the setting of areas 2 to 5. A CAS latency can be set regardless of whether or not an ASTCR wait state insertion is enabled. 000: Program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted 101: 5 program wait states inserted 110: 6 program wait states inserted 111: 7 program wait states inserted 000: Synchronous DRAM of CAS latency 1 is connected to areas 2 to 5. 001: Synchronous DRAM of CAS latency 2 is connected to areas 2 to 5. 010: Synchronous DRAM of CAS latency 3 is connected to areas 2 to 5. 011: Synchronous DRAM of CAS latency 4 is connected to areas 2 to 5. 1XX: Setting prohibited. Legend: X: Don’t care. Note: * The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424 Group.

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  • WTCRBL Bit Bit Name Initial Value R/W Description 7 — 0 R Reserved This bit is always read as 0 and cannot be modified. W12 W11 W10 R/W R/W R/W Area 1 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 1 while AST1 bit in ASTCR = 1. 000: Program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted 101: 5 program wait states inserted 110: 6 program wait states inserted 111: 7 program wait states inserted 3 — 0 R Reserved This bit is always read as 0 and cannot be modified. W02 W01 W00 R/W R/W R/W Area 0 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 0 while AST0 bit in ASTCR = 1. 000: Program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted 101: 5 program wait states inserted 110: 6 program wait states inserted 111: 7 program wait states inserted

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6.3.4 Read Strobe Timing Control Register (RDNCR)

RDNCR selects the read strobe signal (RD) negation timing in a basic bus interface read access. Bit Bit Name Initial Value R/W Description RDN7 RDN6 RDN5 RDN4 RDN3 RDN2 RDN1 RDN0 R/W R/W R/W R/W R/W R/W R/W R/W Read Strobe Timing Control 7 to 0 These bits set the negation timing of the read strobe in a corresponding area read access. As shown in figure 6.2, the read strobe for an area for which the RDNn bit is set to 1 is negated one half-state earlier than that for an area for which the RDNn bit is cleared to 0. The read data setup and hold time specifications are also one half-state earlier. 0: In an area n read access, the RD is negated at the end of the read cycle 1: In an area n read access, the RD is negated one half-state before the end of the read cycle (n = 7 to 0)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 160 of 1270 REJ09B0466-0100 Bus cycle T1 T2 RD φ Data RD Data RDNn = 0 RDNn = 1 Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space)

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6.3.5 CS Assertion Period Control Registers H, L (CSACRH, CSACRL)

CSACRH and CSACRL select whether or not the assertion period of the basic bus interface chip select signals (CSn) and address signals is to be extended. Extending the assertion period of the CSn and address signals allows flexible interfacing to external I/O devices.

  • CSACRH Bit Bit Name Initial Value R/W Description CSXH7 CSXH6 CSXH5 CSXH4 CSXH3 CSXH2 CSXH1 CSXH0 R/W R/W R/W R/W R/W R/W R/W R/W CS and Address Signal Assertion Period Control 1 These bits specify whether or not the T h cycle is to be inserted (see figure 6.3). When an area for which the CSXHn bit is set to 1 is accessed, a one-state T h cycle, in which only the CSn and address signals are asserted, is inserted before the normal access cycle. 0: In area n basic bus interface access, the CSn and address assertion period (Th) is not extended 1: In area n basic bus interface access, the CSn and address assertion period (Th) is extended (n = 7 to 0)
  • CSACRL Bit Bit Name Initial Value R/W Description CSXT7 CSXT6 CSXT5 CSXT4 CSXT3 CSXT2 CSXT1 CSXT0 R/W R/W R/W R/W R/W R/W R/W R/W CS and Address Signal Assertion Period Control 2 These bits specify whether or not the T t cycle shown in figure 6.3 is to be inserted. When an area for which the CSXTn bit is set to 1 is accessed, a one-state T t cycle, in which only the CSn and address signals are asserted, is inserted after the normal access cycle. 0: In area n basic bus interface access, the CSn and address assertion period (Tt) is not extended 1: In area n basic bus interface access, the CSn and address assertion period (Tt) is extended (n = 7 to 0)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 162 of 1270 REJ09B0466-0100 Th Address φ T1 T2 T3 Tt Bus cycle Data HWR, LWR Write Data RD CS Read Figure 6.3 CS and Address Assertion Period Extension (Example of 3-State Access Space and RDNn = 0)

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6.3.6 Area 0 Burst ROM Interf ace Control Register (BROMCRH)

Area 1 Burst ROM Interface Control Register (BROMCRL) BROMCRH and BROMCRL are used to make bu rst ROM interface settings. Area 0 and area 1 burst ROM interface settings can be made independently in BROMCRH and BROMCRL, respectively. Bit Bit Name Initial Value R/W Description

7 BSRMn 0 R/W Burst ROM Interface Select

Selects the basic bus interface or burst ROM interface. 0: Basic bus interface space 1: Burst ROM interface space BSTSn2 BSTSn1 BSTSn0 R/W R/W R/W Burst Cycle Select These bits select the number of burst cycle states. 000: 1 state 001: 2 states 010: 3 states 011: 4 states 100: 5 states 101: 6 states 110: 7 states 111: 8 states R/W R/W Reserved These bits are always read as 0. The initial value should not be changed. BSWDn1 BSWDn0 R/W R/W Burst Word Number Select These bits select the number of words that can be burst-accessed on the burst ROM interface. 00: Maximum 4 words 01: Maximum 8 words 10: Maximum 16 words 11: Maximum 32 words (n = 1 or 0)

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6.3.7 Bus Control Register (BCR)

BCR is used for idle cycle settings, selection of the external bus released state protocol, enabling or disabling of the write data buffer function, and enabling or disabling of WAIT pin input. Bit Bit Name Initial Value R/W Description

15 BRLE 0 R/W External Bus Release Enable

Enables or disables external bus release. 0: External bus release disabled BREQ, BACK, and BREQO pins can be used as I/O ports 1: External bus release enabled

14 BREQOE 0 R/W BREQO Pin Enable

Controls outputting the bus request signal (BREQO) to the external bus master in the external bus released state, when an internal bus master performs an external address space access, or when a refresh request is generated. 0: BREQO output disabled BREQO pin can be used as I/O port 1: BREQO output enabled 13 — 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0.

12 IDLC 1 R/W Idle Cycle State Number Select

Specifies the number of states in the idle cycle set by ICIS2, ICIS1, and ICIS0. 0: Idle cycle comprises 1 state 1: Idle cycle comprises 2 states

11 ICIS1 1 R/W Idle Cycle Insert 1

When consecutive external read cycles are executed in different areas, an idle cycle can be inserted between the bus cycles. 0: Idle cycle not inserted 1: Idle cycle inserted

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 165 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description

10 ICIS0 1 R/W Idle Cycle Insert 0

When an external read cycle and external write cycle are performed consecutively, an idle cycle can be inserted between the bus cycles. 0: Idle cycle not inserted 1: Idle cycle inserted

9 WDBE 0 R/W Write Data Buffer Enable

The write data buffer function can be used for an external write cycle or DMAC single address transfer cycle. 0: Write data buffer function not used 1: Write data buffer function used

8 WAITE 0 R/W WAIT Pin Enable

Selects enabling or disabling of wait input by the WAIT pin. 0: Wait input by WAIT pin disabled WAIT pin can be used as I/O port 1: Wait input by WAIT pin enabled 7 to 3 — All 0 R/W Reserved These bits can be read from or written to. However, the write value should always be 0.

2 ICIS2 0 R/W Idle Cycle Insert 2

When an external write cycle and external read cycle are performed consecutively, an idle cycle can be inserted between the bus cycles. 0: Idle cycle not inserted 1: Idle cycle inserted 1, 0 — All 0 R/W Reserved These bits can be read from or written to. However, the write value should always be 0.

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6.3.8 Address/Data Multiplexe d I/O Control Register (MPXCR)

MPXCR is used to make address/data multiplexed I/O interface settings. Bit Bit Name Initial Value R/W Description

7 MPXE 0 R/W Address/Data Multiplexed I/O Interface Enable

These bits select the bus interface for areas 6 and 0: Basic bus interface 1: Address/data multiplexed I/O interface 6 to 1  All 0 R/W Reserved These bits can be read from or written to. However, the write value should always be 0.

0 ADDEX 0 R/W Address Output Cycle Extension

Specifies whether a wait cycle is inserted for the address output cycle of the address/data multiplexed I/O interface. 0: No wait cycle inserted 1: One wait cycle inserted

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6.3.9 DRAM Control Register (DRAMCR)

DRAMCR is used to make DRAM/synchronous DRAM interface settings. Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424 Group. Bit Bit Name Initial Value R/W Description

15 OEE 0 R/W OE Output Enable

The OE signal used when EDO page mode DRAM is connected can be output from the (OE) pin. The OE signal is common to all areas designated as DRAM space. When the synchronous DRAM is connected, the CKE signal can be output from the (OE) pin. The CKE signal is common to the continuous synchronous DRAM space. 0: OE/CKE signal output disabled (OE)/(CKE) pin can be used as I/O port 1: OE/CKE signal output enabled

14 RAST 0 R/W RAS Assertion Timing Select

Selects whether, in DRAM access, the RAS signal is asserted from the start of the Tr cycle (rising edge of φ) or from the falling edge of φ. Figure 6.4 shows the relationship between the RAST bit setting and the RAS assertion timing. The setting of this bit applies to all areas designated as DRAM space. 0: RAS is asserted from φ falling edge in Tr cycle 1: RAS is asserted from start of Tr cycle 13 — 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 168 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description

12 CAST 0 R/W Column Address Output Cycle Number Select

Selects whether the column address output cycle in DRAM access comprises 3 states or 2 states. The setting of this bit applies to all areas designated as DRAM space. 0: Column address output cycle comprises 2 states 1: Column address output cycle comprises 3 states 11 — 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 169 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description RMTS2 RMTS1 RMTS0 R/W R/W R/W DRAM/Continuous Synchronous DRAM Space Select These bits designate DRAM/continuous synchronous DRAM space for areas 2 to 5. When continuous DRAM space is set, it is possible to connect large-capacity DRAM exceeding 2 Mbytes per area. In this case, the RAS signal is output from the CS2 pin. When continuous synchronous DRAM space is set, it is possible to connect large-capacity synchronous DRAM exceeding 2 Mbytes per area. In this case, the RAS, CAS, and WE signals are output from CS2, CS3, and CS4 pins, respectively. When synchronous DRAM mode is set, the mode registers of the synchronous DRAM can be set. 000: Normal space 001: Normal space in areas 3 to 5 DRAM space in area 2 010: Normal space in areas 4 and 5 DRAM space in areas 2 and 3 011: DRAM space in areas 2 to 5 100: Continuous synchronous DRAM space (setting possible only in H8S/2426R Group) 101: Synchronous DRAM mode setting (setting possible only in H8S/2426R Group) 110: Setting prohibited 111: Continuous DRAM space in areas 2 to 5

7 BE 0 R/W Burst Access Enable

Selects enabling or disabling of burst access to areas designated as DRAM/continuous synchronous DRAM space. DRAM/continuous synchronous DRAM space burst access is performed in fast page mode. When using EDO page mode DRAM, the OE signal must be connected. 0: Full access 1: Access in fast page mode

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 170 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description

6 RCDM 0 R/W RAS Down Mode

When access to DRAM space is interrupted by an access to normal space, an access to an internal I/O register, etc., this bit selects whether the RAS signal is held low while waiting for the next DRAM access (RAS down mode), or is driven high again (RAS up mode). The setting of this bit is valid only when the BE bit is set to 1. If this bit is cleared to 0 when set to 1 in the RAS down state, the RAS down state is cleared at that point, and RAS goes high. When continuous synchronous DRAM space is set, reading from and writing to this bit is enabled. However, the setting does not affect the operation. 0: RAS up mode selected for DRAM space access 1: RAS down mode selected for DRAM space access

5 DDS 0 R/W DMAC Single Address Transfer Option

Selects whether full access is always performed or burst access is enabled when DMAC single address transfer is performed on the DRAM/synchronous DRAM. When the BE bit is cleared to 0 in DRAMCR, disabling DRAM/synchronous DRAM burst access, DMAC single address transfer is performed in full access mode regardless of the setting of this bit. This bit has no effect on other bus master external accesses or DMAC dual address transfers. 0: Full access is always executed 1: Burst access is enabled

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 171 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description

4 EDDS 0 R/W EXDMAC Single Address Transfer Option

Selects whether full access is always performed or burst access is enabled when EXDMAC single address transfer is performed on the DRAM/synchronous DRAM. When the BE bit is cleared to 0 in DRAMCR, disabling DRAM/synchronous DRAM burst access, EXDMAC single address transfer is performed in full access mode regardless of the setting of this bit. This bit has no effect on other bus master external accesses or EXDMAC dual address transfers. 0: Full access is always executed 1: Burst access is enabled 3 — 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 172 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description MXC2 MXC1 MXC0 R/W R/W R/W Address Multiplex Select These bits select the size of the shift toward the lower half of the row address in row address/column address multiplexing. In burst operation on the DRAM/synchronous DRAM interface, these bits also select the row address bits to be used for comparison. When the MXC2 bit is set to 1 while continuous synchronous DRAM space is set, the address precharge setting command (Precharge-sel) is output to the upper column address. For details, refer to sections 6.7.2 and 6.8.2, Address Multiplexing. DRAM interface 000: 8-bit shift

  • When 8-bit access space is designated: Row address bits A23 to A8 used for comparison
  • When 16-bit access space is designated: Row address bits A23 to A9 used for comparison 001: 9-bit shift
  • When 8-bit access space is designated: Row address bits A23 to A9 used for comparison
  • When 16-bit access space is designated: Row address bits A23 to A10 used for comparison 010: 10-bit shift
  • When 8-bit access space is designated: Row address bits A23 to A10 used for comparison
  • When 16-bit access space is designated: Row address bits A23 to A11 used for comparison

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 173 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description MXC2 MXC1 MXC0 R/W R/W R/W 011: 11-bit shift

  • When 8-bit access space is designated: Row address bits A23 to A11 used for comparison When 16-bit access space is designated: Row address bits A23 to A12 used for comparison Synchronous DRAM interface 100: 8-bit shift
  • When 8-bit access space is designated: Row address bits A23 to A8 used for comparison
  • When 16-bit access space is designated: Row address bits A23 to A9 used for comparison The precharge-sel is A15 to A9 of the column address. 101: 9-bit shift
  • When 8-bit access space is designated: Row address bits A23 to A9 used for comparison
  • When 16-bit access space is designated: Row address bits A23 to A10 used for comparison The precharge-sel is A15 to A10 of the column address. 110: 10-bit shift
  • When 8-bit access space is designated: Row address bits A23 to A10 used for comparison
  • When 16-bit access space is designated: Row address bits A23 to A11 used for comparison The precharge-sel is A15 to A11 of the column address.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 174 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description MXC2 MXC1 MXC0 R/W R/W R/W 111: 11-bit shift

  • When 8-bit access space is designated: Row address bits A23 to A11 used for comparison
  • When 16-bit access space is designated: Row address bits A23 to A12 used for comparison The precharge-sel is A15 to A12 of the column address. Tp Address φ RAST = 0 RAS RAST = 1 RAS Tr Tc1 Tc2 UCAS, LCAS Bus cycle Row address Column address Figure 6.4 RAS Signal Assertion Timing (2-State Column Address Output Cycle, Full Access)

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6.3.10 DRAM Access Co ntrol Register (DRACCR)

DRACCR is used to set the DRAM/synchronous DRAM interface bus specifications. Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424 Group. Bit Bit Name Initial Value R/W Description

15 DRMI 0 R/W Idle Cycle Insertion

An idle cycle can be inserted after a DRAM/synchronous DRAM access cycle when a continuous normal space access cycle follows a DRAM/synchronous DRAM access cycle. Idle cycle insertion conditions, setting of number of states, etc., comply with settings of bits ICIS2, ICIS1, ICIS0, and IDLC in BCR register 0: Idle cycle not inserted 1: Idle cycle inserted 14 — 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. TPC1 TPC0 R/W R/W Precharge State Control These bits select the number of states in the RAS precharge cycle in normal access and refreshing. 00: 1 state 01: 2 states 10: 3 states 11: 4 states

11 SDWCD 0 * R/W CAS Latency Control Cycle Disabled during

Continuous Synchronous DRAM Space Write Access Disables CAS latency control cycle (Tcl) inserted by WTCRB (H) settings during synchronous DRAM write access (see figure 6.5). 0: Enables CAS latency control cycle 1: Disables CAS latency control cycle

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 176 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description 10  0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. RCD1 RCD0 R/W R/W RAS-CAS Wait Control These bits select a wait cycle to be inserted between the RAS assert cycle and CAS assert cycle. A 1- to 4-state wait cycle can be inserted. 00: Wait cycle not inserted 01: 1-state wait cycle inserted 10: 2-state wait cycle inserted 11: 3-state wait cycle inserted 7 to 4  All 0 R/W Reserved These bits can be read from or written to. However, the write value should always be 0.

3 CKSPE * 0 R/W Clock Suspend Enable

Enables clock suspend mode for extend read data during DMAC and EXDMAC single address transfer with the synchronous DRAM interface. 0: Disables clock suspend mode 1: Enables clock suspend mode 2  0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. RDXC1* RDXC0* R/W R/W Read Data Extension Cycle Number Selection Selects the number of read data extension cycle (Tsp) insertion state in clock suspend mode. These bits are valid when the CKSPE bit is set to 00: Inserts 1 state 01: Inserts 2 state 10: Inserts 3 state 11: Inserts 4 state Note: * Not supported by the H8S/ 2426 Group and H8S/2424 Group.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 177 of 1270 REJ09B0466-0100 Tp RAS SDWCD 0 CAS DQMU, DQML WE CKE Data bus Address bus SDRAMφ φ Tr Tc1 Tcl Tc2 PALL ACTV NOP WRIT NOP Tp Tr Tc1 Tc2 Column address Column address Row address Precharge-sel Row address Column address High RAS SDWCD 1 CAS DQMU, DQML WE CKE Data bus Address bus PALL ACTV NOP WRIT Row address Precharge-sel Row address Column address High Figure 6.5 CAS Latency Control Cycle Disable Timing during Continuous Synchronous DRAM Space Write Access (for CAS Latency 2)

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6.3.11 Refresh Control Register (REFCR)

REFCR specifies DRAM/synchronous DRAM interface refresh control. Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424 Group. Bit Bit Name Initial Value R/W Description

15 CMF 0 R/(W) * Compare Match Flag

Status flag that indicates a match between the values of RTCNT and RTCOR. [Clearing conditions]

  • When 0 is written to CMF after reading CMF = 1 while the RFSHE bit is cleared to 0
  • When CBR refreshing is executed while the RFSHE bit is set to 1 [Setting condition] When RTCOR = RTCNT

14 CMIE 0 R/W Compare Match Interrupt Enable

Enables or disables interrupt requests (CMI) by the CMF flag when the CMF flag is set to 1. This bit is valid when refresh control is not performed. When the refresh control is performed, this bit is always cleared to 0 and cannot be modified. 0: Interrupt request by CMF flag disabled 1: Interrupt request by CMF flag enabled RCW1 RCW0 R/W R/W CAS-RAS Wait Control These bits select the number of wait cycles to be inserted between the CAS assert cycle and RAS assert cycle in a DRAM/synchronous DRAM refresh cycle. 00: Wait state not inserted 01: 1 wait state inserted 10: 2 wait states inserted 11: 3 wait states inserted Note: * Only 0 can be written, to clear the flag.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 179 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description 11 — 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. RTCK2 RTCK1 RTCK0 R/W R/W R/W Refresh Counter Clock Select These bits select the clock to be used to increment the refresh counter. When the input clock is selected with bits RTCK2 to RTCK0, the refresh counter begins counting up. 000: Count operation halted 001: Count on φ/2 010: Count on φ/8 011: Count on φ/32 100: Count on φ/128 101: Count on φ/512 110: Count on φ/2048 111: Count on φ/4096

7 RFSHE 0 R/W Refresh Control

Refresh control can be performed. When refresh control is not performed, the refresh timer can be used as an interval timer. 0: Refresh control is not performed 1: Refresh control is performed

6 CBRM 0 R/W CBR Refresh Mode

Selects CBR refreshing performed in parallel with other external accesses, or execution of CBR refreshing alone. When the continuous synchronous DRAM space is set, this bit can be read/written, but the setting contents do not affect operations. 0: External access during CAS-before-RAS refreshing is enabled 1: External access during CAS-before-RAS refreshing is disabled

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 180 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description RLW1 RLW0 R/W R/W Refresh Cycle Wait Control These bits select the number of wait states to be inserted in a DRAM interface CAS-before-RAS refresh cycle/synchronous DRAM interface auto- refresh cycle. This setting applies to all areas designated as DRAM/continuous synchronous DRAM space. 00: No wait state inserted 01: 1 wait state inserted 10: 2 wait states inserted 11: 3 wait states inserted

3 SLFRF 0 R/W Self-Refresh Enable

If this bit is set to 1, DRAM/synchronous DRAM self-refresh mode is selected when a transition is made to the software standby state. This bit is valid when the RFSHE bit is set to 1, enabling refresh operations. It is cleared after recovery from software standby mode. 0: Self-refreshing is disabled 1: Self-refreshing is enabled TPCS2 TPCS1 TPCS0 R/W R/W R/W Self-Refresh Precharge Cycle Control These bits select the number of states in the precharge cycle immediately after self-refreshing. The number of states in the precharge cycle immediately after self-refreshing are added to the number of states set by bits TPC1 and TPC0 in DRACCR. 000: [TPC set value] states 001: [TPC set value + 1] states 010: [TPC set value + 2] states 011: [TPC set value + 3] states 100: [TPC set value + 4] states 101: [TPC set value + 5] states 110: [TPC set value + 6] states 111: [TPC set value + 7] states

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6.3.12 Refresh Time r Counter (RTCNT)

RTCNT is an 8-bit readable/writable up-counter. RTCNT counts up using the internal clock selected by bits RTCK2 to RTCK0 in REFCR. When RTCNT matches RTCOR (compare match), the CMF flag in REFCR is set to 1 and RTCNT is cleared to H'00. If the RFSHE bit in REFCR is set to 1 at this time, a refresh cycle is started. If the RFSHE bit is cleared to 0 and the CMIE bit in REFCR is set to 1, a compare match interrupt (CMI) is generated. RTCNT is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode.

6.3.13 Refresh Time Constant Register (RTCOR)

RTCOR is an 8-bit readable/writable register that sets the period for compare match operations with RTCNT. The values of RTCOR and RTCNT are constantly compared, and if they match, the CMF flag in REFCR is set to 1 and RTCNT is cleared to H'00. RTCOR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode.

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6.4 Bus Control

6.4.1 Area Division

The bus controller divides the 16-Mbyte address space into eight areas, 0 to 7, in 2-Mbyte units, and performs bus control for external address space in area units. Chip select signals (CS0 to CS7) can be output for each area. In normal mode, a part of area 0, 64-Kbyte address space, is controlled. Figure 6.6 shows an outline of the memory map. Area 0 (2 Mbytes) H'000000 H'FFFFFF H'1FFFFF H'200000 Area 1 (2 Mbytes) H'3FFFFF H'400000 Area 2 (2 Mbytes) H'5FFFFF H'600000 Area 3 (2 Mbytes) H'7FFFFF H'800000 Area 4 (2 Mbytes) H'9FFFFF H'A00000 Area 5 (2 Mbytes) H'BFFFFF H'C00000 Area 6 (2 Mbytes) H'DFFFFF H'E00000 Area 7 (2 Mbytes) Figure 6.6 Area Divisions

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6.4.2 Bus Specifications

The external address space bus specifications consist of five elements: bus width, number of access states, number of program wait states, read strobe timing, and chip select (CS) assertion period extension states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller. (1) Bus Width A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a 16-bit access space. If all areas are designated as 8-bit access space, 8-bit bus mode is set; if any area is designated as 16-bit access space, 16-bit bus mode is set. (2) Number of Access States Two or three access states can be selected with ASTCR. An area for which 2-state access is selected functions as a 2-state access space, and an area for which 3-state access is selected functions as a 3-state access space. With the DRAM or synchronous DRAM interface and burst ROM interface, the number of access states may be determined without regard to the setting of ASTCR. When 2-state access space is designated, wait insertion is disabled. When 3-state access space is designated, it is possible to insert program waits by means of the WTCRA and WTCRB, and external waits by means of the WAIT pin. Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424 Group. (3) Number of Program Wait States When 3-state access space is designated by ASTCR, the number of program wait states to be inserted automatically is selected with WTCRA and WTCRB. From 0 to 7 program wait states can be selected. Table 6.2 shows the bus specifications (bus width, and number of access states and program wait states) for each basic bus interface area.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 184 of 1270 REJ09B0466-0100 Table 6.2 Bus Specifications for Each Area (Basic Bus Interface) ABWCR ASTCR WTCRA, WTCRB Bus Speci fications (Basic Bus Interface) ABWn ASTn Wn2 Wn1 Wn0 Bus Width Access States Program Wait States 0 0    16 2 0 1 0 0 0 3 0 1 1 1 0 2 1 3 1 0 0 4 1 5 1 0 6 1 7 1 0    8 2 0 1 0 0 0 3 0 1 1 1 0 2 1 3 1 0 0 4 1 5 1 0 6 1 7 (n = 0 to 7) (4) Read Strobe Timing RDNCR can be used to select either of two negation timings (at the end of the read cycle or one half-state before the end of the read cycle) for the read strobe (RD) used in the basic bus interface space. (5) Chip Select (CS) Assertion Period Extension States Some external I/O devices require a setup time and hold time between address and CS signals and strobe signals such as RD, HWR, and LWR. CSACR can be used to insert states in which only the CS, AS, and address signals are asserted before and after a basic bus space access cycle.

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6.4.3 Memory Interfaces

The memory interfaces in this LSI comprise a basic bus interface that allows direct connection of ROM, SRAM, and so on; an address/data multiplexed I/O interface that allows direct connection of peripheral LSIs that require address/data multiplexing, a DRAM interface that allows direct connection of DRAM; a synchronous DRAM interface that allows direct connection of synchronous DRAM; and a burst ROM interface that allows direct connection of burst ROM. The interface can be selected independently for each area. An area for which the basic bus interface is designated functions as normal space. An area for which the address/data multiplexed I/O interface is designated functions as address/data multiplexed I/O space, an area for which the DRAM interface is designated functions as DRAM space, an area for which the synchronous DRAM interface is designated functions as continuous synchronous DRAM space, and an area for which the burst ROM interface is designated functions as burst ROM space. The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424 Group. (1) Area 0 Area 0 includes on-chip ROM in expanded mode with on-chip ROM enabled and the space excluding on-chip ROM is external address space, and in expanded mode with on-chip ROM disabled, all of area 0 is external address space. When area 0 external space is accessed, the CS0 signal can be output. Either the basic bus interface or burst ROM interface can be selected for the memory interface of area 0. (2) Area 1 In externally expanded mode, all of area 1 is external address space. When area 1 external address space is accessed, the CS1 signal can be output. Either the basic bus interface or burst ROM interface can be selected for the memory interface of area 1.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 186 of 1270 REJ09B0466-0100 (3) Areas 2 to 5 In externally expanded mode, areas 2 to 5 are all external address space. When area 2 to 5 external space is accessed, signals CS2 to CS5 can be output. The basic bus interface, DRAM interface, or synchronous DRAM interface can be selected for the memory interface of areas 2 to 5. With the DRAM interface, signals CS2 and CS5 are used as RAS signals. If areas 2 to 5 are designated as continuous DRAM space, large-capacity (e.g. 64-Mbit) DRAM can be connected. In this case, the CS2 signal is used as the RAS signal for the continuous DRAM space. If areas 2 to 5 are designated as continuous synchronous DRAM space, large-capacity (e.g. 64- Mbit) synchronous DRAM can be connected. In this case, the CS2, CS3, CS4, and CS5 pins are used as the RAS, CAS, WE, and CLK signals for the continuous synchronous DRAM space. The OE pin is used as the CKE signal. (4) Area 6 In externally expanded mode, all of area 6 is external space. When area 6 external space is accessed, the CS6 signal can be output. Either the basic bus interface or address/data multiplexed I/O interface can be used for the memory interface of area 6. (5) Area 7 Area 7 includes the on-chip RAM and internal/O registers. In externally expanded mode, the space excluding the on-chip RAM and internal I/O registers is external address space. The on-chip RAM is enabled when the RAME bit is set to 1 in the system control register (SYSCR); when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding addresses are in external address space. When area 7 external address space is accessed, the CS7 signal can be output. Either the basic bus interface or address/data multiplexed I/O interface can be used for the memory interface of area 7.

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6.4.4 Chip Select Signals

This LSI can output chip select signals (CS0 to CS7) for areas 0 to 7. The signal outputs low when the corresponding external space area is accessed. Figure 6.7 shows an example of CS0 to CS7 signals output timing. Enabling or disabling of CS0 to CS7 signals output is set by the data direction register (DDR) bit for the port corresponding to the CS0 to CS7 pins. In expanded mode with on-chip ROM disabled, the CS0 pin is placed in the output state after a reset. Pins CS1 to CS7 are placed in the input state after a reset and so the corresponding DDR bits and PFCR0 bits should be set to 1 when outputting signals CS1 to CS7. In expanded mode with on-chip ROM enabled, pins CS0 to CS7 are all placed in the input state after a reset and so the corresponding DDR bits and PFCR0 bits should be set to 1 when outputting signals CS0 to CS7. When areas 2 to 5 are designated as DRAM space, outputs CS2 to CS5 are used as RAS signals. When areas 2 to 5 are designated as continuous synchronous DRAM space in the H8S/2426R Group, outputs CS2, CS3, CS4, and CS5 are used as RAS, CAS, WE, and CLK signals. Note: The A23E bit in PFCR1 should be cleared to 0 when CS7 signal is output in the H8S/2424 Group. Bus cycle T1 T2 T3 Area n external addressAddress bus φ CSn Figure 6.7 CSn Signal Output Timing (n = 0 to 7)

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6.5 Basic Bus Interface

The basic bus interface enables direct connection of ROM, SRAM, and so on.

6.5.1 Data Size and Data Alignment

Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external address space, controls whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data size. (1) 8-Bit Access Space Figure 6.8 illustrates data alignment control for the 8-bit access space. With the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of data that can be accessed at one time is one byte: a word access is performed as two byte accesses, and a longword access, as four byte accesses. D15 D8 D7 D0 Upper data bus Lower data bus Byte size Word size 1st bus cycle 2nd bus cycle Longword size 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle Figure 6.8 Access Sizes and Data Alignment Control (8-Bit Access Space) (2) 16-Bit Access Space Figure 6.9 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword access is executed as two word accesses.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 189 of 1270 REJ09B0466-0100 In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address. D15 D8 D7 D0 Upper data bus Lower data bus Byte size Word size 1st bus cycle 2nd bus cycle Longword size

  • Even address Byte size  Odd address Figure 6.9 Access Sizes and Data Alignment Control (16-Bit Access Space)

6.5.2 Valid Strobes

Table 6.3 shows the data buses used and valid strobes for the access spaces. In a read, the RD signal is valid for both the upper and the lower half of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. Table 6.3 Data Buses Used and Valid Strobes Area Access Size Read/ Write Address Valid Strobe Upper Data Bus (D15 to D8) Lower Data Bus (D7 to D0) Byte Read  RD Valid Invalid 8-bit access space Write  HWR Hi-Z Byte Read Even RD Valid Invalid 16-bit access space Odd Invalid Valid Write Even HWR Valid Hi-Z Odd LWR Hi-Z Valid Word Read  RD Valid Valid Write  HWR, LWR Valid Valid Note: Hi-Z: High-impedance state Invalid: Input state; input value is ignored.

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6.5.3 Basic Timing

(1) 8-Bit, 2-State Access Space Figure 6.10 shows the bus timing for an 8-bit, 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is always fixed high. Wait states can be inserted. Bus cycle T1 T2 Address bus φ CSn AS RD D15 to D8 Valid D7 to D0 Invalid Read HWR LWR D15 to D8 Valid D7 to D0 High impedance Write High Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.10 Bus Timing for 8-Bit, 2-State Access Space

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 192 of 1270 REJ09B0466-0100 (3) 16-Bit, 2-State Access Space Figures 6.12 to 6.14 show bus timings for a 16-bit, 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and the lower half (D7 to D0) for odd addresses. Wait states cannot be inserted. Bus cycle T1 T2 Address bus φ CSn AS RD D15 to D8 Valid D7 to D0 Invalid Read HWR LWR D15 to D8 Valid D7 to D0 Write High High impedance Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.12 Bus Timing for 16-Bit, 2-State Access Space (Even Address Byte Access)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 193 of 1270 REJ09B0466-0100 Bus cycle T1 T2 Address bus φ CSn AS RD D15 to D8 Invalid D7 to D0 Valid Read HWR LWR D15 to D8 D7 to D0 Valid Write High High impedance Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.13 Bus Timing for 16-Bit, 2-State Access Space (Odd Address Byte Access)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 194 of 1270 REJ09B0466-0100 Bus cycle T1 T2 Address bus φ CSn AS RD D15 to D8 Valid D7 to D0 Valid Read HWR LWR D15 to D8 Valid D7 to D0 Valid Write Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.14 Bus Timing for 16-Bit, 2-State Access Space (Word Access)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 195 of 1270 REJ09B0466-0100 (4) 16-Bit, 3-State Access Space Figures 6.15 to 6.17 show bus timings for a 16-bit, 3-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and the lower half (D7 to D0) for odd addresses. Wait states can be inserted. Bus cycle T1 T2 Address bus φ CSn AS RD D15 to D8 Valid D7 to D0 Invalid Read HWR LWR D15 to D8 Valid D7 to D0 Write High High impedance Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.15 Bus Timing for 16-Bit, 3-State Access Space (Even Address Byte Access)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 196 of 1270 REJ09B0466-0100 Bus cycle T1 T2 Address bus φ CSn AS RD D15 to D8 Invalid D7 to D0 Valid Read HWR LWR D15 to D8 D7 to D0 Valid Write High High impedance Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.16 Bus Timing for 16-Bit, 3-State Access Space (Odd Address Byte Access)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 197 of 1270 REJ09B0466-0100 Bus cycle T1 T2 Address bus φ CSn AS RD D15 to D8 Valid D7 to D0 Valid Read HWR LWR D15 to D8 Valid D7 to D0 Valid Write Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.17 Bus Timing for 16-Bit, 3-State Access Space (Word Access)

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6.5.4 Wait Control

When accessing external space, this LSI can extend the bus cycle by inserting one or more wait states (Tw ). There are two ways of inserting wait states: program wait insertion and pin wait insertion using the WAIT pin. (1) Program Wait Insertion From 0 to 7 wait states can be inserted automatically between the T2 state and T3 state on an individual area basis in 3-state access space, according to the settings in WTCRA and WTCRB. (2) Pin Wait Insertion Setting the WAITE bit to 1 in BCR enables wait input by means of the WAIT pin. When external space is accessed in this state, a program wait is first inserted in accordance with the settings in WTCRA and WTCRB. If the WAIT pin is low at the falling edge of φ in the last T2 or Tw state, another Tw state is inserted. If the WAIT pin is held low, Tw states are inserted until it goes high. This is useful when inserting seven or more Tw states, or when changing the number of Tw states to be inserted for different external devices. The WAITE bit setting applies to all areas. Figure 6.18 shows an example of wait state insertion timing. The settings after a reset are: 3-state access, insertion of 7 program wait states, and WAIT input disabled.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 199 of 1270 REJ09B0466-0100 By program wait Address bus φ AS RD Data bus Read data Read HWR, LWR Write data Write WAIT Data bus T2 Tw Tw Tw T3 By WAIT pin Notes: 1. Downward arrows indicate the timing of WAIT pin sampling. 2. When RDNn = 0 Figure 6.18 Example of Wait State Insertion Timing

6.5.5 Read Strobe ( RD) Timing

The read strobe (RD) timing can be changed for individual areas by setting bits RDN7 to RDN0 to 1 in RDNCR. Figure 6.19 shows an example of the timing when the read strobe timing is changed in basic bus 3-state access space. When the DMAC or EXDMAC is used in single address mode, note that if the RD timing is changed by setting RDNn to 1, the RD timing will change relative to the rise of DACK or EDACK.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 200 of 1270 REJ09B0466-0100 Bus cycle T1 T2 Address bus φ CSn AS RD Data bus RD DACK, EDACK Data bus RDNn = 0 RDNn = 1 Figure 6.19 Example of Read Strobe Timing

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6.5.6 Extension of Chip Select (CS) Assertion Period

Some external I/O devices require a setup time and hold time between address and CS signals and strobe signals such as RD, HWR, and LWR. Settings can be made in the CSACR register to insert states in which only the CS, AS, and address signals are asserted before and after a basic bus space access cycle. Extension of the CS assertion period can be set for individual areas. With the CS assertion extension period in write access, the data setup and hold times are less stringent since the write data is output to the data bus. Figure 6.20 shows an example of the timing when the CS assertion period is extended in basic bus 3-state access space. Th Address bus φ T1 T2 T3 Tt Bus cycle Data bus HWR, LWR Write Data bus RD CSn AS Read (when RDNn = 0) Read data Write data Figure 6.20 Example of Timing when Chip Select Assertion Period Is Extended

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 202 of 1270 REJ09B0466-0100 Both extension state Th inserted before the basic bus cycle and extension state Tt inserted after the basic bus cycle, or only one of these, can be specified for individual areas. Insertion or non- insertion can be specified for the Th state with the upper 8 bits (CSXH7 to CSXH0) in the CSACR register, and for the Tt state with the lower 8 bits (CSXT7 to CSXT0).

6.6 Address/Data Multiplexed I/O Interface

If areas 6 and 7 of the external address space are specified as address/data multiplexed I/O space in this LSI, the address/data multiplexed I/O interfacing can be performed. In the address/data multiplexed I/O interface, peripheral LSIs that require address/data multiplexing can be connected directly to this LSI.

6.6.1 Setting Address/Data Multiplexed I/O Space

In the address/data multiplexed I/O interface, areas 6 and 7 are designated as the address/data multiplexed I/O space by setting the MPXE bit in MPXCR to 1.

6.6.2 Address/Data Multiplexing

With the address/data multiplexed I/O space, the data bus and address bus are multiplexed. Table 6.4 shows the relation between the bus width and corresponding address output. Table 6.4 Multiplexed Address/Data Data Pins Bus Width Cycle PD7 PD6 PD5 PD4 PD 3 PD2 PD1 PD0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 Address A7 A6 A5 A4 A3 A2 A1 A0         8 bits Data D15 D14 D13 D12 D11 D10 D9 D8         Address A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 16 bits Data D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

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6.6.3 Data Bus

The bus width of the address/data multiplexed I/O space can be specified for either 8-bit access space or 16-bit access space by the ABW7 and ABW6 bits in ABWCRA. For the 8-bit access space, D15 to D8 are valid for both address and data. For the 16-bit access space, D15 to D0 are valid for both address and data. If the address/data multiplexed I/O space is accessed, the corresponding address will be output to the address bus. For details on access size and data alignment, see section 6.5.1, Data Size and Data Alignment.

6.6.4 Address Hold Signal

In the address/data multiplexed I/O space, a hold signal (AH) that indicates the timing for latching the address is output. The AH output pin is multiplexed with the AS output pin. When the external address space is specified as the address/data multiplexed I/O space, the multiplexed pin functions as the AH output pin. Note however that the multiplexed pin will function as the AS output pin until the address/data multiplexed I/O space is specified.

6.6.5 Basic Timing

The bus cycle in the address/data multiplexed I/O interface consists of an address cycle and a data cycle. The data cycle is based on the basic bus interface timing specified by ABWCR, ASTCR, WTCRAH, RDNCR, and CSACR.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 206 of 1270 REJ09B0466-0100 (3) 16-Bit, 2-State Data Access Space Figures 6.23 to 6.25 show bus timings for a 16-bit, 2-state data access space. When a 16-bit access space is accessed, the entire address bus (D15 to D0) is used for all addresses, and the upper half (D15 to D8) of the data bus is used for even addresses and the lower half (D7 to D0) of the data bus is used for odd addresses. Wait states cannot be inserted in the data cycle. CSn AH RD HWR LWR D15 to D8 D7 to D0 D15 to D8 D7 to D0 Tma1 Tma2 T1 T2 Address cycle Data cycle φ Address bus Write Read Address Address Read data Write data Notes: 1. n = 6, 7 2. When RDNn = 0 Address Address Figure 6.23 Bus Timing for 16-Bit, 2-State Data Access Space (Even Address Byte Access)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 207 of 1270 REJ09B0466-0100 CSn AH RD HWR LWR D15 to D8 D7 to D0 D15 to D8 D7 to D0 Tma1 Tma2 T1 T2 Address cycle Data cycle φ Address bus Write Read Address Address Read data Write data Notes: 1. n = 6, 7 2. When RDNn = 0 Address Address Figure 6.24 Bus Timing for 16-Bit, 2-State Data Access Space (Odd Address Byte Access)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 208 of 1270 REJ09B0466-0100 CSn AH RD HWR LWR D15 to D8 D7 to D0 D15 to D8 D7 to D0 Tma1 Tma2 T1 T2 Address cycle Data cycle φ Address bus Write Read Address Address Read data Write data Notes: 1. n = 6, 7 2. When RDNn = 0 Address Address Read data Write data Figure 6.25 Bus Timing for 16-Bit, 2-State Data Access Space (Word Access)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 209 of 1270 REJ09B0466-0100 (4) 16-Bit, 3-State Data Access Space Figures 6.26 to 6.28 show bus timings for a 16-bit, 3-state data access space. When a 16-bit access space is accessed, the entire address bus (D15 to D0) is used for all addresses, and the upper half (D15 to D8) of the data bus is used for even addresses and the lower half (D7 to D0) of the data bus is used for odd addresses. Wait states can be inserted in the data cycle. D15 to D8 D7 to D0 D15 to D8 D7 to D0 HWR LWR CSn AH RD Tma1 T1 T2 T3Tma2 Address cycle Data cycle φ Address bus Write Read Address Address Read data Write data Notes: 1. n = 6, 7 2. When RDNn = 1 Address Address Figure 6.26 Bus Timing for 16-Bit, 3-State Data Access Space (Even Address Byte Access)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 210 of 1270 REJ09B0466-0100 D15 to D8 D7 to D0 D15 to D8 D7 to D0 HWR LWR CSn AH RD Tma1 T1 T2 T3Tma2 Address cycle Data cycle φ Address bus Write Read Address Address Read data Write data Notes: 1. n = 6, 7 2. When RDNn = 1 Address Address Figure 6.27 Bus Timing for 16-Bit, 3-State Data Access Space (Odd Address Byte Access)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 211 of 1270 REJ09B0466-0100 D15 to D8 D7 to D0 D15 to D8 D7 to D0 HWR LWR CSn AH RD Tma1 T1 T2 T3Tma2 Address cycle Data cycle φ Address bus Write Read Address Address Read data Write data Notes: 1. n = 6, 7 2. When RDNn = 1 Address Address Read data Write data Figure 6.28 Bus Timing for 16-Bit, 3-State Data Access Space (Word Access)

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6.6.6 Wait Control

(1) Address Cycle A single address wait cycle Tmaw can be inserted between Tma1 and Tma2 cycles by setting the ADDEX bit in MPXCR to 1. Figure 6.29 shows the access timing when the address cycle is three cycles. D15 to D8 D7 to D0 D15 to D8 D7 to D0 CSn AH RD HWR LWR Tma1 Tmaw Tma2 T1 T2 Address cycle Data cycle φ Address bus Write Read Address Address Read data Write data Notes: 1. n = 6, 7 2. When RDNn = 0 Address Address Figure 6.29 Example of Access Timing with Address Wait

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 213 of 1270 REJ09B0466-0100 (2) Data Cycle In the data cycle, program wait insertion and pin wait insertion by the WAIT pin are enabled in the same way as in the basic bus interface. For details, refer to section 6.5.4, Wait Control. Wait control settings do not affect the address cycles.

6.6.7 Read Strobe ( RD) Timing

In the address/data multiplexed I/O interface, the read strobe timing of data cycles can be modified in the same way as in the basic bus interface. For details, refer to section 6.5.5, Read Strobe (RD) Timing. Figure 6.30 shows an example when the read strobe timing is modified. D15 to D8 D15 to D8 RDNn = 0 RDNn = 1 CSn AH RD RD Tma1 T1 T2 Tma2 Address cycle Data cycle φ Address bus Address Address Read data Note: n = 6, 7 Read data Figure 6.30 Example of Read Strobe Timing

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6.6.8 Extension of Chip Select (CS) Assertion Period in Data Cycle

In the address/data multiplexed I/O interface, extension cycles can be inserted before and after the data cycle. For details, see section 6.5.6, Extension of Chip Select (CS) Assertion Period. Figure 6.31 shows an example of the timing when the chip select assertion period is extended in the data cycle. CSn HWR LWR AH RD D15 to D8 D7 to D0 D15 to D8 D7 to D0 Tma1 Th T1 T2 TtTma2 Address cycle Data cycle φ Address bus Write Read Address Address Read data Write data Notes: 1. n = 6, 7 2. When RDNn = 0 Address Address Read data Write data Figure 6.31 Example of Timing when Chip Select Assertion Period Is Extended in Data Cycle

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 215 of 1270 REJ09B0466-0100 When consecutively reading from the same area connected to a peripheral LSI whose output floating time is long, data outputs from the peripheral LSI may conflict with address outputs from this LSI. The data conflict can be avoided by inserting the CS assertion period extension cycle after the access cycle. Figure 6.32 shows an example of the operation. In the figure, both bus cycles A and B are read access cycles to the same area which is address/data multiplexed I/O space. (a) shows an example of conflict occurring between data outputs from the peripheral LSI whose output floating time is long and address outputs from this LSI because the CS assertion period extension cycle is not inserted. (b) shows an example of the data conflict being avoided by inserting the CS assertion period extension cycle. Bus cycle A Data bus Bus cycle B Output floating time is long Data conflict (b) With CS assertion period extension cycle (CSXTn = 1) WR RD CS Bus cycle A Bus cycle B WR RD CS φ Address bus φ Address bus Data bus (a) Without CS assertion period extension cycle (CSXTn = 0) Figure 6.32 Consecutive Read Accesses to Same Area (Address/Data Multiplexed I/O Space)

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6.7 DRAM Interface

In this LSI, external space areas 2 to 5 can be designated as DRAM space, and DRAM interfacing performed. The DRAM interface allows DRAM to be directly connected to this LSI. A DRAM space of 2, 4, or 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR. Burst operation is also possible, using fast page mode.

6.7.1 Setting DRAM Space

Areas 2 to 5 are designated as DRAM space by setting bits RMTS2 to RMTS0 in DRAMCR. The relation between the settings of bits RMTS2 to RMTS0 and DRAM space is shown in table 6.5. Possible DRAM space settings are: one area (area 2), two areas (areas 2 and 3), four areas (areas 2 to 5), and continuous area (areas 2 to 5). Table 6.5 Relation between Settings of Bits RMTS2 to RMTS0 and DRAM Space RMTS2 RMTS1 RMTS0 Area 5 Area 4 Area 3 Area 2 0 1 Normal space Normal space Normal space DRAM space

0 Normal space Normal space DRAM space DRAM space

1 DRAM space DRAM space DRAM space DRAM space

0 Continuous synchronous DRAM space * 0

1 Mode register settings of synchronous DRAM *

0 Reserved (setting prohibited)

1 Continuous

Note: * Reserved (setting prohibited) in the H8S/2426 Group and H8S/2424 Group. With continuous DRAM space, RAS2 is valid. The bus specifications (bus width, number of wait states, etc.) for continuous DRAM space conform to the settings for area 2.

6.7.2 Address Multiplexing

With DRAM space, the row address and column address are multiplexed. In address multiplexing, the size of the shift of the row address is selected with bits MXC2 to MXC0 in DRAMCR. Table 6.6 shows the relation between the settings of MXC2 to MXC0 and the shift size. The MXC2 bit should be cleared to 0 when the DRAM interface is used.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 217 of 1270 REJ09B0466-0100 Table 6.6 Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing DRAMCR Address Pins MXC2 MXC1 MXC0 Shift Size A23 to A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 8 bits A23 to A16 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 0 1 9 bits A23 to A16 A15 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 0 10 bits A23 to A16 A15 A14 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 1 11 bits A23 to A16 A15 A14 A13 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Row address 1 × × Reserved (setting prohibited) 0 × ×  A23 to A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Column address 1 × × Reserved (setting prohibited) Legend: ×: Don’t care.

6.7.3 Data Bus

If a bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM space. In 16-bit DRAM space, ×16-bit configuration DRAM can be connected directly. In 8-bit DRAM space the upper half of the data bus, D15 to D8, is enabled, while in 16-bit DRAM space both the upper and lower halves of the data bus, D15 to D0, are enabled. Access sizes and data alignment are the same as for the basic bus interface: see section 6.5.1, Data Size and Data Alignment.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 218 of 1270 REJ09B0466-0100

6.7.4 Pins Used for DRAM Interface

Table 6.7 shows the pins used for DRAM interfacing and their functions. Since the CS2 to CS5 pins are in the input state after a reset, set the corresponding DDR to 1 when RAS2 to RAS5 signals are output. Table 6.7 DRAM Interface Pins Pin With DRAM Setting Name I/O Function HWR WE Write enable Output Write enable for DRAM space access CS2 RAS2/RAS Row address strobe 2/ row address strobe Output Row address strobe when area 2 is designated as DRAM space or row address strobe when areas 2 to 5 are designated as continuous DRAM space CS3 RAS3 Row address strobe 3 Output Row address strobe when area 3 is designated as DRAM space CS4 RAS4 Row address strobe 4 Output Row address strobe when area 4 is designated as DRAM space CS5 RAS5 Row address strobe 5 Output Row address strobe when area 5 is designated as DRAM space UCAS UCAS Upper column address strobe Output Upper column address strobe for 16-bit DRAM space access or column address strobe for 8-bit DRAM space access LCAS LCAS Lower column address strobe Output Lower column address strobe signal for 16-bit DRAM space access RD, OE OE Output enable Output Output enable signal for DRAM space access WAIT WAIT Wait Input Wait request signal A15 to A0 A15 to A0 Address pins Output Row address/column address multiplexed output D15 to D0 D15 to D0 Data pi ns I/O Data input/output pins

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 219 of 1270 REJ09B0466-0100

6.7.5 Basic Timing

Figure 6.33 shows the basic access timing for DRAM space. The four states of the basic timing consist of one Tp (precharge cycle) state, one Tr (row address output cycle) state, and the Tc1 and two Tc2 (column address output cycle) states. Tp RASn (CSn) Read Write UCAS, LCAS WE (HWR) OE (RD) Data bus WE (HWR) OE (RD) Data bus Address bus φ Tr Tc1 Tc2 Row address High High Column address Note: n = 2 to 5 Figure 6.33 DRAM Basic Access Timing (RAST = 0, CAST = 0)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 220 of 1270 REJ09B0466-0100 When DRAM space is accessed, the RD signal is output as the OE signal for DRAM. When connecting DRAM provided with an EDO page mode, the OE signal should be connected to the (OE) pin of the DRAM. Setting the OEE bit to 1 in DRAMCR enables the OE signal for DRAM space to be output from a dedicated OE pin. In this case, the OE signal for DRAM space is output from both the RD pin and the (OE) pin, but in external read cycles for other than DRAM space, the signal is output only from the RD pin.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 221 of 1270 REJ09B0466-0100

6.7.6 Column Address Output Cycle Control

The column address output cycle can be changed from 2 states to 3 states by setting the CAST bit to 1 in DRAMCR. Use the setting that gives the optimum specification values (CAS pulse width, etc.) according to the DRAM connected and the operating frequency of this LSI. Figure 6.34 shows an example of the timing when a 3-state column address output cycle is selected. Tp RASn (CSn) Read Write UCAS, LCAS WE (HWR) OE (RD) Data bus WE (HWR) OE (RD) Data bus Address bus φ Tr Tc1 Tc2 Tc3 Row address Column address High High Note: n = 2 to 5 Figure 6.34 Example of Access Timing with 3-State Column Address Output Cycle (RAST = 0)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 222 of 1270 REJ09B0466-0100

6.7.7 Row Address Output State Control

If the RAST bit is set to 1 in DRAMCR, the RAS signal goes low from the beginning of the Tr state, and the row address hold time and DRAM read access time are changed relative to the fall of the RAS signal. Use the optimum setting according to the DRAM connected and the operating frequency of this LSI. Figure 6.35 shows an example of the timing when the RAS signal goes low from the beginning of the Tr state. Tp RASn (CSn) Read Write UCAS, LCAS WE (HWR) OE (RD) Data bus WE (HWR) OE (RD) Data bus Address bus φ Tr Tc1 Tc2 Row address Column address High High Note: n = 2 to 5 Figure 6.35 Example of Access Timing when RAS Signal Goes Low from Beginning of Tr State (CAST = 0)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 223 of 1270 REJ09B0466-0100 If a row address hold time or read access time is necessary, making a setting in bits RCD1 and RCD0 in DRACCR allows from one to three Trw states, in which row address output is maintained, to be inserted between the Tr cycle, in which the RAS signal goes low, and the Tc1 cycle, in which the column address is output. Use the setting that gives the optimum row address signal hold time relative to the falling edge of the RAS signal according to the DRAM connected and the operating frequency of this LSI. Figure 6.36 shows an example of the timing when one T rw state is set. Tp RASn (CSn) Read Write UCAS, LCAS WE (HWR) OE (RD) Data bus WE (HWR) OE (RD) Data bus Address bus φ Tr Trw Tc1 Tc2 Row address Column address High High Note: n = 2 to 5 Figure 6.36 Example of Timing with One Row Address Output Maintenance State (RAST = 0, CAST = 0)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 224 of 1270 REJ09B0466-0100

6.7.8 Precharge State Control

When DRAM is accessed, a RAS precharge time must be secured. With this LSI, one Tp state is always inserted when DRAM space is accessed. From one to four Tp states can be selected by setting bits TPC1 and TPC0 in DRACCR. Set the optimum number of Tp cycles according to the DRAM connected and the operating frequency of this LSI. Figure 6.37 shows the timing when two Tp states are inserted. The setting of bits TPC1 and TPC0 is also valid for Tp states in refresh cycles. Tp1 RASn (CSn) Read Write UCAS, LCAS WE (HWR) OE (RD) Data bus WE (HWR) OE (RD) Data bus Address bus φ Tp2 Tr Tc1 Tc2 Row address Column address High High Note: n = 2 to 5 Figure 6.37 Example of Timing with Two-State Precharge Cycle (RAST = 0, CAST = 0)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 225 of 1270 REJ09B0466-0100

6.7.9 Wait Control

There are two ways of inserting wait states in a DRAM access cycle: program wait insertion and pin wait insertion using the WAIT pin. Wait states are inserted to extend the CAS assertion period in a read access to DRAM space, and to extend the write data setup time relative to the falling edge of CAS in a write access. (1) Program Wait Insertion When the bit in ASTCR corresponding to an area designated as DRAM space is set to 1, from 0 to 7 wait states can be inserted automatically between the Tc1 state and Tc2 state, according to the settings in WTCR. (2) Pin Wait Insertion When the WAITE bit in BCR is set to 1 and the ASTCR bit is set to 1, wait input by means of the WAIT pin is enabled. When DRAM space is accessed in this state, a program wait (Tw ) is first inserted. If the WAIT pin is low at the falling edge of φ in the last Tc1 or Tw state, another Tw state is inserted. If the WAIT pin is held low, Tw states are inserted until it goes high. Figures 6.38 and 6.39 show examples of wait cycle insertion timing in the case of 2-state and 3- state column address output cycles.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 226 of 1270 REJ09B0466-0100 By program wait Tp Address bus φ WAIT Tr Tc1 Tw Tw Tc2 By WAIT pin RASn (CSn) Read Write UCAS, LCAS UCAS, LCAS WE (HWR) OE (RD) Data bus WE (HWR) OE (RD) Data bus Row address Column address High High Note: Downward arrows indicate the timing of WAIT pin sampling. n = 2 to 5 Figure 6.38 Example of Wait State Insertion Timing (2-State Column Address Output)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 227 of 1270 REJ09B0466-0100 By program wait Tp Address bus φ WAIT Tr Tc1 Tw Tw Tc2 Tc3 By WAIT pin RASn (CSn) Read Write UCAS, LCAS UCAS, LCAS WE (HWR) OE (RD) Data bus WE (HWR) OE (RD) Data bus Row address Column address High High Note: Downward arrows indicate the timing of WAIT pin sampling. n = 2 to 5 Figure 6.39 Example of Wait State Insertion Timing (3-State Column Address Output)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 228 of 1270 REJ09B0466-0100

6.7.10 Byte Access Control

When DRAM with a ×16-bit configuration is connected, the 2-CAS access method is used for the control signals needed for byte access. Figure 6.40 shows the control timing for 2-CAS access, and figure 6.41 shows an example of 2-CAS DRAM connection. Tp RASn (CSn) UCAS LCAS WE (HWR) OE (RD) Upper data bus Lower data bus Address bus φ Tr Tc1 Tc2 Note: n = 2 to 5 Row address Column address Write data High High High-Z Figure 6.40 2-CAS Control Timing (Upper Byte Write Access: RAST = 0, CAST = 0)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 229 of 1270 REJ09B0466-0100 This LSI (Address shift size set to 10 bits) RASn (CSn) 2-CAS type 16-Mbit DRAM 1-Mbyte × 16-bit configuration 10-bit column address RAS UCAS UCAS LCAS LCAS HWR (WE) WE RD (OE) OE A9 A8 A10 A9 A8 A7 A7 A6 A6 A5 A5 A4 A4 A3 A3 A2 A2 A1 A1 A0 D15 to D0 D15 to D0 Row address input: A9 to A0 Column address input: A9 to A0 Figure 6.41 Example of 2-CAS DRAM Connection

6.7.11 Burst Operation

With DRAM, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, a fast page mode is also provided which can be used when making consecutive accesses to the same row address. This mode enables fast (burst) access of data by simply changing the column address after the row address has been output. Burst access can be selected by setting the BE bit to 1 in DRAMCR. (1) Burst Access (Fast Page Mode) Figures 6.42 and 6.43 show the operation timing for burst access. When there are consecutive access cycles for DRAM space, the CAS signal and column address output cycles (two states) continue as long as the row address is the same for consecutive access cycles. The row address used for the comparison is set with bits MXC2 to MXC0 in DRAMCR.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 230 of 1270 REJ09B0466-0100 Tp Tr Tc1 Tc2 Tc1 Tc2 RASn (CSn) Read Write UCAS, LCAS WE (HWR) OE (RD) Data bus WE (HWR) OE (RD) Data bus Address bus φ Note: n = 2 to 5 Row address Column address 1 Column address 2 High High Figure 6.42 Operation Timing in Fast Page Mode (RAST = 0, CAST = 0)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 232 of 1270 REJ09B0466-0100 Note, however, that the RAS signal will go high if:  a refresh operation is initiated in the RAS down state  self-refreshing is performed  the chip enters software standby mode  the external bus is released  the RCDM bit or BE bit is cleared to 0 If a transition is made to the all-module-clocks-stopped mode in the RAS down state, the clock will stop with RAS low. To enter the all-module-clocks-stopped mode with RAS high, the RCDM bit must be cleared to 0 before executing the SLEEP instruction. Normal space read DRAM space read Tp Tr Tc1 Tc2 T1 T2 DRAM space read Tc1 Tc2 Note: n = 2 to 5 RASn (CSn) UCAS, LCAS RD OE Data bus Address bus φ Row address Column address 1 Column address 2External address Figure 6.44 Example of Operation Timing in RAS Down Mode (RAST = 0, CAST = 0)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 233 of 1270 REJ09B0466-0100

  • RAS Up Mode To select RAS up mode, clear the RCDM bit to 0 in DRAMCR. Each time access to DRAM space is interrupted and another space is accessed, the RAS signal goes high again. Burst operation is only performed if DRAM space is continuous. Figure 6.45 shows an example of the timing in RAS up mode. Normal space read DRAM space read Tp Tr Tc1 Tc2 Tc1 Tc2 DRAM space read T1 T2 Note: n = 2 to 5 RASn (CSn) UCAS, LCAS RD OE Data bus Address bus φ Row address Column address 1 Column address 2 External address Figure 6.45 Example of Operation Timing in RAS Up Mode (RAST = 0, CAST = 0)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 234 of 1270 REJ09B0466-0100

6.7.12 Refresh Control

This LSI is provided with a DRAM refresh control function. CAS-before-RAS (CBR) refreshing is used. In addition, self-refreshing can be executed when the chip enters the software standby state. Refresh control is enabled when any area is designated as DRAM space in accordance with the setting of bits RMTS2 to RMTS0 in DRAMCR. (1) CAS-before-RAS (CBR) Refreshing To select CBR refreshing, set the RFSHE bit to 1 in REFCR. With CBR refreshing, RTCNT counts up using the input clock selected by bits RTCK2 to RTCK0 in REFCR, and when the count matches the value set in RTCOR (compare match), refresh control is performed. At the same time, RTCNT is reset and starts counting up again from H'00. Refreshing is thus repeated at fixed intervals determined by RTCOR and bits RTCK2 to RTCK0. Set a value in RTCOR and bits RTCK2 to RTCK0 that will meet the refreshing interval specification for the DRAM used. When bits RTCK2 to RTCK0 in REFCR are set, RTCNT starts counting up. RTCNT and RTCOR settings should therefore be completed before setting bits RTCK2 to RTCK0. RTCNT operation is shown in figure 6.46, compare match timing in figure 6.47, and CBR refresh timing in figure 6.48. When the CBRM bit in REFCR is cleared to 0, access to external space other than DRAM space is performed in parallel during the CBR refresh period. RTCOR H'00 Refresh request RTCNT Figure 6.46 RTCNT Operation

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 237 of 1270 REJ09B0466-0100 Depending on the DRAM used, modification of the WE signal may not be permitted during the refresh period. In this case, the CBRM bit in REFCR should be set to 1. The bus controller will then insert refresh cycles in appropriate breaks between bus cycles. Figure 6.50 shows an example of the timing when the CBRM bit is set to 1. In this case the CS signal is not controlled, and retains its value prior to the start of the refresh period. A23 to A0 φ CS AS RD HWR (WE) CAS Normal space access request RAS Refresh period Figure 6.50 Example of CBR Refresh Timing (CBRM = 1)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 238 of 1270 REJ09B0466-0100 (2) Self-Refreshing A self-refresh mode (battery backup mode) is provided for DRAM as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within the DRAM. To select self-refreshing, set the RFSHE bit and SLFRF bit to 1 in REFCR. When a SLEEP instruction is executed to enter software standby mode, the CAS and RAS signals are output and DRAM enters self-refresh mode, as shown in figure 6.51. When software standby mode is exited, the SLFRF bit is cleared to 0 and self-refresh mode is exited automatically. If a CBR refresh request occurs when making a transition to software standby mode, CBR refreshing is executed, and then self-refresh mode is entered. When using self-refresh mode, the OPE bit must not be cleared to 0 in the SBYCR register. TRp TRr UCAS, LCAS Software standby TRc3 HWR (WE) CSn (RASn) φ Note: n = 2 to 5 High Figure 6.51 Self-Refresh Timing

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 239 of 1270 REJ09B0466-0100 In some DRAMs provided with a self-refresh mode, the RAS signal precharge time immediately after self-refreshing is longer than the normal precharge time. A setting can be made in bits TPCS2 to TPCS0 in REFCR to make the precharge time immediately after self-refreshing from 1 to 7 states longer than the normal precharge time. In this case, too, normal precharging is performed according to the setting of bits TPC1 and TPC0 in DRACCR, and therefore a setting should be made to give the optimum post-self-refresh precharge time, including this time. Figure 6.52 shows an example of the timing when the precharge time immediately after self-refreshing is extended by 2 states. DRAM space write TRc3 TRp1 TRp2 Tp Tr Software standby Tc1 Tc2 Note: n = 2 to 5 RASn (CSn) UCAS, LCAS OE (RD) WR (HWR) Data bus Address bus φ Figure 6.52 Example of Timing when Precharge Time after Self-Refreshing Is Extended by 2 States

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 240 of 1270 REJ09B0466-0100 (3) Refreshing and All-Module-Clocks-Stopped Mode In this LSI, if the ACSE bit is set to 1 in MSTPCRH, and then a SLEEP instruction is executed with the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFF, EXMSTPCR = H'FFFF) or for operation of the 8-bit timer module alone (MSTPCR = H'FFFE, EXMSTPCR = H'FFFF), and a transition is made to the sleep state, the all-module-clocks-stopped mode is entered, in which the bus controller and I/O port clocks are also stopped. As the bus controller clock is also stopped in this mode, CBR refreshing is not executed. If DRAM is connected externally and DRAM data is to be retained in sleep mode, the ACSE bit must be cleared to 0 in MSTPCRH.

6.7.13 DMAC and EXDMAC Single Address Transfer Mode and DRAM Interface

When burst mode is selected on the DRAM interface, the DACK and EDACK output timing can be selected with the DDS and EDDS bits in DRAMCR. When DRAM space is accessed in DMAC or EXDMAC single address mode at the same time, these bits select whether or not burst access is to be performed. (1) When DDS = 1 or EDDS = 1 Burst access is performed by determining the address only, irrespective of the bus master. With the DRAM interface, the DACK or EDACK output goes low from the T c1 state. Figure 6.53 shows the DACK or EDACK output timing for the DRAM interface when DDS = 1 or EDDS = 1.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 241 of 1270 REJ09B0466-0100 Tp RASn (CSn) Read Write UCAS, LCAS WE (HWR) OE (RD) Data bus WE (HWR) OE (RD) Data bus DACK or EDACK Address bus φ Tr Tc1 Tc2 Note: n = 2 to 5 Row address Column address High High Figure 6.53 Example of DACK/EDACK Output Timing when DDS = 1 or EDDS = 1 (RAST = 0, CAST = 0)

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6.8 Synchronous DRAM Interface

In the H8S/2426R Group, external address space areas 2 to 5 can be designated as continuous synchronous DRAM space, and synchronous DRAM interfacing performed. The synchronous DRAM interface allows synchronous DRAM to be directly connected to this LSI. A synchronous DRAM space of up to 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR. Synchronous DRAM of CAS latency 1 to 4 can be connected. Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424 Group.

6.8.1 Setting Continuous Synchronous DRAM Space

Areas 2 to 5 are designated as continuous synchronous DRAM space by setting bits RMTS2 to RMTS0 in DRAMCR. The relation between the settings of bits RMTS2 to RMTS0 and synchronous DRAM space is shown in table 6.8. Possible synchronous DRAM interface settings are and continuous area (areas 2 to 5). Table 6.8 Relation between Settings of Bits RMTS2 to RMTS0 and Synchronous DRAM Space RMTS2 RMTS1 RMTS0 Area 5 Area 4 Area 3 Area 2 0 1 Normal space Normal space Normal space DRAM space

0 Continuous synchronous DRAM space 0

1 Mode settings of synchronous DRAM

1 Continuous DRAM space

With continuous synchronous DRAM space, CS2, CS3, CS4 pins are used as RAS, CAS, WE signal. The (OE) pin of the synchronous DRAM is used as the CKE signal, and the CS5 pin is used as synchronous DRAM clock (SDRAMφ). The bus specifications for continuous synchronous DRAM space conform to the settings for area 2. The pin wait and program wait for the continuous synchronous DRAM are invalid. Commands for the synchronous DRAM can be specified by combining RAS, CAS, WE, and address-precharge-setting command (Precharge-sel) output on the upper column addresses.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 244 of 1270 REJ09B0466-0100 Commands that are supported by this LSI are NOP, auto-refresh (REF), self-refresh (SELF), all bank precharge (PALL), row address strobe bank-active (ACTV), read (READ), write (WRIT), and mode-register write (MRS). Commands for bank control cannot be used.

6.8.2 Address Multiplexing

With continuous synchronous DRAM space, the row address and column address are multiplexed. In address multiplexing, the size of the shift of the row address is selected with bits MXC2 to MXC0 in DRAMCR. The address-precharge-setting command (Precharge-sel) can be output on the upper column address. Table 6.9 shows the relation between the settings of MXC2 to MXC0 and the shift size. The MXC2 bit should be set to 1 when the synchronous DRAM interface is used. Table 6.9 Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing DRAMCR Address Pins MXC2 MXC1 MXC0 Shift Size A23 to A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 × × Reserved (setting prohibited) 0 8 bits A23 to A16 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 0 1 9 bits A23 to A16 A15 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 0 10 bits A23 to A16 A15 A14 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 Row address 1 1 11 bits A23 to A16 A15 A14 A13 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 0 × × Reserved (setting prohibited) 0  A23 to A16 P P P P P P P A8 A7 A6 A5 A4 A3 A2 A1 A0 0 1  A23 to A16 P P P P P P A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0  A23 to A16 P P P P P A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Column address 1 1  A23 to A16 P P P P A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Legend: ×: Don’t care. P: Precharge-sel

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 245 of 1270 REJ09B0466-0100

6.8.3 Data Bus

If the ABW2 bit in ABWCR corresponding to an area designated as continuous synchronous DRAM space is set to 1, areas 2 to 5 are designated as 8-bit continuous synchronous DRAM space; if the bit is cleared to 0, the areas are designated as 16-bit continuous synchronous DRAM space. In 16-bit continuous synchronous DRAM space, ×16-bit configuration synchronous DRAM can be connected directly. In 8-bit continuous synchronous DRAM space the upper half of the data bus, D15 to D8, is enabled, while in 16-bit continuous synchronous DRAM space both the upper and lower halves of the data bus, D15 to D0, are enabled. Access sizes and data alignment are the same as for the basic bus interface: see section 6.5.1, Data Size and Data Alignment.

6.8.4 Pins Used for Synchronous DRAM Interface

Table 6.10 shows pins used for the synchronous DRAM interface and their functions. Since the CS2 to CS4 pins are in the input state after a reset, set DDR to 1 when RAS, CAS, and WE signals are output. For details, see section 10, I/O Ports. Set the OEE bit of the DRAMCR register to 1 when the CKE signal is output.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 246 of 1270 REJ09B0466-0100 Table 6.10 Synchronous DRAM Interface Pins Pin With Synchronous DRAM Setting Name I/O Function CS2 RAS Row address strobe Output Row address strobe when areas 2 to 5 are designated as continuous synchronous DRAM space CS3 CAS Column address strobe Output Column address strobe when areas 2 to 5 are designated as continuous synchronous DRAM space CS4 WE Write enable Output Write enable strobe when areas 2 to 5 are designated as continuous synchronous DRAM space CS5 SDRAM φ Clock Output Clock only for synchronous DRAM (OE) (CKE) Clock enable Output Clock enable signal when areas 2 to 5 are designated as continuous synchronous DRAM space UCAS DQMU Upper data mask enable Output Upper data mask enable for 16-bit continuous synchronous DRAM space access/data mask enable for 8-bit continuous synchronous DRAM space access LCAS DQML Lower data mask enable Ou tput Lower data mask enable signal for 16-bit continuous synchronous DRAM space access A15 to A0 A15 to A0 Address pins Output Row address/column address multiplexed output pins D15 to D0 D15 to D0 Data pi ns I/O Data input/output pins

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 247 of 1270 REJ09B0466-0100

6.8.5 Synchronous DRAM Clock

The synchronous clock (SDRAMφ) is output from the CS5 pin. SDRAMφ is shifted by 90° phase from φ. Therefore, a stable margin is ensured for the synchronous DRAM that operates at the rising edge of clocks. Figure 6.55 shows the relationship between φ and SDRAM φ. SDRAMφ φ Tcyc 1/4 Tcyc (90°) Figure 6.55 Relationship between φ and SDRAM φ

6.8.6 Basic Timing

The four states of the basic timing consist of one Tp (precharge cycle) state, one Tr (row address output cycle) state, and the Tc1 and two Tc2 (column address output cycle) states. When areas 2 to 5 are set for the continuous synchronous DRAM space, settings of the WAITE bit of BCR, RAST, CAST, RCDM bits of DRAMCR, and the CBRM bit of REFCR are ignored. Figure 6.56 shows the basic timing for synchronous DRAM.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 248 of 1270 REJ09B0466-0100 Tp SDRAMφ RAS Read CAS WE CKE PALL ACTV READ NOP DQMU, DQML Data bus Address bus φ Tr Tc1 Tc2 Row addressColumn address Column address Precharge-sel Row address High RAS Write CAS WE CKE PALL ACTV NOP WRIT DQMU, DQML Data bus High Figure 6.56 Basic Access Timing of Synchronous DRAM (CAS Latency 1)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 249 of 1270 REJ09B0466-0100

6.8.7 CAS Latency Control

CAS latency is controlled by settings of the W22 to W20 bits of WTCRB. Set the CAS latency count, as shown in table 6.11, by the setting of synchronous DRAM. Depending on the setting, the CAS latency control cycle (Tc1) is inserted. WTCRB can be set regardless of the setting of the AST2 bit of ASTCR. Figure 6.57 shows the CAS latency control timing when synchronous DRAM of CAS latency 3 is connected. The initial value of W22 to W20 is H'7. Set the register according to the CAS latency of synchronous DRAM to be connected. Table 6.11 Setting CAS Latency W22 W21 W20 Description CAS Latency Control Cycle Inserted 0 0 0 Connect synchronous DRAM of CAS latency 1 0 state

1 Connect synchronous DRAM of CAS

1 0 Connect synchronous DRAM of CAS latency 3 2 states 1 0 0 Reserved (must not be used) 

1 Reserved (must not be used) 

1 0 Reserved (must not be used) 

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 250 of 1270 REJ09B0466-0100 Tp SDRAMφ RAS Read CAS WE CKE PALL ACTV READ NOP DQMU, DQML Data bus Address bus φ Tr Tc1 Tcl1 Tcl2 Tc2 Row addressColumn address Column address Precharge-sel Row address High RAS Write CAS WE CKE PALL ACTV NOP NOP WRIT DQMU, DQML Data bus High Figure 6.57 CAS Latency Control Timing (SDWCD = 0, CAS Latency 3)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 251 of 1270 REJ09B0466-0100

6.8.8 Row Address Output State Control

When the command interval specification from the ACTV command to the next READ/WRIT command cannot be satisfied, 1 to 3 states (Trw) that output the NOP command can be inserted between the Tr cycle that outputs the ACTV command and the Tc1 cycle that outputs the column address by setting the RCD1 and RCD0 bits of DRACCR. Use the optimum setting for the wait time according to the synchronous DRAM connected and the operating frequency of this LSI. Figure 6.58 shows an example of the timing when the one Trw state is set. Tp SDRAMφ RAS Read CAS WE CKE PALL ACTV NOP READ NOP DQMU, DQML Data bus Address bus Tr Trw Tc1 Tcl Tc2 Row addressColumn address Column address Precharge-sel Row address High RAS Write CAS WE CKE PALL ACTV NOP NOP WRIT DQMU, DQML Data bus High φ Figure 6.58 Example of Access Timing when Row Address Output Hold State Is 1 State (RCD1 = 0, RCD0 = 1, SDWCD = 0, CAS Latency 2)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 252 of 1270 REJ09B0466-0100

6.8.9 Precharge State Count

When the interval specification from the PALL command to the next ACTV/REF command cannot be satisfied, from one to four Tp states can be selected by setting bits TPC1 and TPC0 in DRACCR. Set the optimum number of Tp cycles according to the synchronous DRAM connected and the operating frequency of this LSI. Figure 6.59 shows the timing when two Tp states are inserted.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 253 of 1270 REJ09B0466-0100 The setting of bits TPC1 and TPC0 is also valid for Tp states in refresh cycles. Tp1 SDRAMφ RAS Read CAS WE CKE PALL NOP ACTV READ NOP DQMU, DQML Data bus Address bus Tp2 Tr Tc1 Tcl Tc2 Row addressColumn address Column address Precharge-sel Row address High RAS Write CAS WE CKE PALL NOP NOP ACTV NOP WRIT DQMU, DQML Data bus High φ Figure 6.59 Example of Timing with Two-State Precharge Cycle (TPC1 = 0, TPC0 = 1, SDWCD = 0, CAS Latency 2)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 254 of 1270 REJ09B0466-0100

6.8.10 Bus Cycle Control in Write Cycle

By setting the SDWCD bit of the DRACCR to 1, the CAS latency control cycle (Tc1) that is inserted by the WTCRB register in the write access of the synchronous DRAM can be disabled. Disabling the CAS latency control cycle can reduce the write-access cycle count as compared to synchronous DRAM read access. Figure 6.60 shows the write access timing when the CAS latency control cycle is disabled. Tp SDRAMφ RAS CAS WE CKE PALL ACTV WRIT NOP DQMU, DQML Data bus Address bus φ Tr Tc1 Tc2 Row addressColumn address Column address Precharge-sel Row address High Figure 6.60 Example of Write Access Timing when CAS Latency Control Cycle Is Disabled (SDWCD = 1)

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6.8.11 Byte Access Control

When synchronous DRAM with a ×16-bit configuration is connected, DQMU and DQML are used for the control signals needed for byte access. Figures 6.61 and 6.62 show the control timing for DQM, and figure 6.63 shows an example of connection of byte control by DQMU and DQML. Tp SDRAMφ φ RAS CAS WE CKE PALL ACTV NOP NOP WRIT DQMU DQML Lower data bus Upper data bus Address bus Tr Tc1 Tcl Tc2 Row addressColumn address Column address Precharge-sel Row address High High High impedance Figure 6.61 DQMU and DQML Control Timing (Upper Byte Write Access: SDWCD = 0, CAS Latency 2)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 256 of 1270 REJ09B0466-0100 Tp SDRAMφ φ RAS CAS WE CKE PALL ACTV READ NOP DQMU DQML Lower data bus Upper data bus Address bus Tr Tc1 Tcl Tc2 Row addressColumn address Column address Precharge-sel Row address High High High impedance Figure 6.62 DQMU and DQML Control Timing (Lower Byte Read Access: CAS Latency 2)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 257 of 1270 REJ09B0466-0100 This LSI (Address shift size set to 8 bits) CS2 (RAS) CS3 (CAS) CS4 (WE) 16-Mbit synchronous DRAM

1 Mword × 16 bits × 4-bank configuration

UCAS (DQMU) LCAS (DQML) A9 A8 A10 A9 A8 A7 A12 A11 Notes: 1. Bank control is not available. 2. The CKE and CS pins must be fixed to 1 when the power supply is input. 3. The CS pin must be fixed to 0 before accessing synchronous DRAM. A21 A12 (BS0) A23 A13 (BS1) CS5 (SDRAMφ) CLK DQML DQMU A11 A10 A7 A6 A6 A5 A5 A4 A4 A3 A3 A2 A2 A1 DCTL I/O PORT D15 to D0 DQ15 to DQ0 OE (CKE) CKE CS Row address input: A11 to A0 Column address input: A7 to A0 Bank select address: A13/A12 Figure 6.63 Example of DQMU and DQML Byte Control

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6.8.12 Burst Operation

With synchronous DRAM, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, burst access is also provided which can be used when making consecutive accesses to the same row address. This access enables fast access of data by simply changing the column address after the row address has been output. Burst access can be selected by setting the BE bit to 1 in DRAMCR. DQM has the 2-cycle latency when synchronous DRAM is read. Therefore, the DQM signal cannot be specified to the Tc2 cycle data output if the Tc1 cycle is executed for second or following column address when the CAS latency is set to 1 to issue the READ command. Do not set the BE bit to 1 when synchronous DRAM of CAS latency 1 is connected. (1) Burst Access Operation Timing Figure 6.64 shows the operation timing for burst access. When there are consecutive access cycles for continuous synchronous DRAM space, the column address output cycles continue as long as the row address is the same for consecutive access cycles. The row address used for the comparison is set with bits MXC2 to MXC0 in DRAMCR.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 259 of 1270 REJ09B0466-0100 Tp SDRAMφ φ RAS Read CAS WE CKE PALL ACTV READ READ NOP NOP DQMU, DQML Data bus Address bus Tr Tc1 Tcl Tc2 Tc1 Tcl Tc2 Row addressColumn address 1 Column address Column address 2 Precharge-sel Row address High RAS Write CAS WE CKE PALL ACTV NOP NOP NOP WRIT WRIT DQMU, DQML Data bus High Figure 6.64 Operation Timing of Burst Access (BE = 1, SDWCD = 0, CAS Latency 2)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 260 of 1270 REJ09B0466-0100 (2) RAS Down Mode Even when burst operation is selected, it may happen that access to continuous synchronous DRAM space is not continuous, but is interrupted by access to another space. In this case, if the row address active state is held during the access to the other space, the read or write command can be issued without ACTV command generation similarly to DRAM RAS down mode. To select RAS down mode, set the BE bit to 1 in DRAMCR regardless of the RCDM bit settings. The operation corresponding to DRAM RAS up mode is not supported by this LSI. Figure 6.65 shows an example of the timing in RAS down mode. Note, however, the next continuous synchronous DRAM space access is a full access if:

  • a refresh operation is initiated in the RAS down state
  • self-refreshing is performed
  • the chip enters software standby mode
  • the external bus is released
  • the BE bit is cleared to 0
  • the mode register of the synchronous DRAM is set There is synchronous DRAM in which time of the active state of each bank is restricted. If it is not guaranteed that other row address are accessed in a period in which program execution ensures the value (software standby, sleep, etc.), auto refresh or self refresh must be set, and the restrictions of the maximum active state time of each bank must be satisfied. When refresh is not used, programs must be developed so that the bank is not in the active state for more than the specified time.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 261 of 1270 REJ09B0466-0100 Tp Address bus External addressColumn address Column address 2 External address Row address Column address Data bus Tr Tc1 Tcl Tc2 Tc1 Tc2 Continuous synchronous DRAM space read Continuous synchronous DRAM space read External space read T2 TclT1 RAS CAS WE CKE High PALL ACTV READ NOP NOPREAD DQMU, DQML Precharge-sel Row address φ Figure 6.65 Example of Operation Timing in RAS Down Mode (BE = 1, CAS Latency 2)

6.8.13 Refresh Control

This LSI is provided with a synchronous DRAM refresh control function. Auto refreshing is used. In addition, self-refreshing can be executed when the chip enters the software standby state. Refresh control is enabled when any area is designated as continuous synchronous DRAM space in accordance with the setting of bits RMTS2 to RMTS0 in DRAMCR.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 262 of 1270 REJ09B0466-0100 (1) Auto Refreshing To select auto refreshing, set the RFSHE bit to 1 in REFCR. With auto refreshing, RTCNT counts up using the input clock selected by bits RTCK2 to RTCK0 in REFCR, and when the count matches the value set in RTCOR (compare match), refresh control is performed. At the same time, RTCNT is reset and starts counting up again from H'00. Refreshing is thus repeated at fixed intervals determined by RTCOR and bits RTCK2 to RTCK0. Set a value in RTCOR and bits RTCK2 to RTCK0 that will meet the refreshing interval specification for the synchronous DRAM used. When bits RTCK2 to RTCK0 are set, RTCNT starts counting up. RTCNT and RTCOR settings should therefore be completed before setting bits RTCK2 to RTCK0. Auto refresh timing is shown in figure 6.66. Since the refresh counter operation is the same as the operation in the DRAM interface, see section 6.7.12, Refresh Control. When the continuous synchronous DRAM space is set, access to external address space other than continuous synchronous DRAM space cannot be performed in parallel during the auto refresh period, since the setting of the CBRM bit of REFCR is ignored.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 263 of 1270 REJ09B0466-0100 TRp SDRAMφ RAS CAS WE CKE PALL NOP REF Address bus TRr TRc1 TRc2 Precharge-sel High φ Figure 6.66 Auto Refresh Timing When the interval specification from the PALL command to the REF command cannot be satisfied, setting the RCW1 and RCW0 bits of REFCR enables one to three wait states to be inserted after the TRp cycle that is set by the TPC1 and TPC0 bits of DRACCR. Set the optimum number of waits according to the synchronous DRAM connected and the operating frequency of this LSI. Figure 6.67 shows the timing when one wait state is inserted. Since the setting of bits TPC1 and TPC0 of DRACCR is also valid in refresh cycles, the command interval can be extended by the RCW1 and RCW0 bits after the precharge cycles.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 264 of 1270 REJ09B0466-0100 TRp1 φ SDRAMφ RAS CAS WE CKE PALL NOP REF NOP Address bus TRp2 TRrw TRr TRc1 TRc2 Precharge-sel High Figure 6.67 Auto Refresh Timing (TPC = 1, TPC0 = 1, RCW1 = 0, RCW0 = 1) When the interval specification from the REF command to the ACTV cannot be satisfied, setting the RLW1 and RLW0 bits of REFCR enables one to three wait states to be inserted in the refresh cycle. Set the optimum number of waits according to the synchronous DRAM connected and the operating frequency of this LSI. Figure 6.68 shows the timing when one wait state is inserted.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 265 of 1270 REJ09B0466-0100 TRp φ SDRAMφ RAS CAS WE CKE PALL REF NOP Address bus TRr TRr1 TRcw TRc2 Precharge-sel High Figure 6.68 Auto Refresh Timing (TPC = 0, TPC0 = 0, RLW1 = 0, RLW0 = 1) (2) Self-Refreshing A self-refresh mode (battery backup mode) is provided for synchronous DRAM as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within the synchronous DRAM. To select self-refreshing, set the RFSHE bit to 1 in REFCR. When a SLEEP instruction is executed to enter software standby mode, the SELF command is issued, as shown in figure 6.69. When software standby mode is exited, the SLFRF bit in REFCR is cleared to 0 and self-refresh mode is exited automatically. If an auto refresh request occurs when making a transition to software standby mode, auto refreshing is executed, and then self-refresh mode is entered. When using self-refresh mode, the OPE bit must not be cleared to 0 in SBYCR.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 266 of 1270 REJ09B0466-0100 TRp SDRAMφ Precharge-sel Address bus TRr CAS Software standby TRc2 WE CKE RAS NOPSELFPALL φ Figure 6.69 Self-Refresh Timing (TPC1 = 1, TPC0 = 0, RCW1 = 0, RCW0 = 0, RLW1 = 0, RLW0 = 0) In some synchronous DRAMs provided with a self-refresh mode, the interval between clearing self-refreshing and the next command is specified. A setting can be made in bits TPCS2 to TPCS0 in REFCR to make the precharge time after self-refreshing from 1 to 7 states longer than the normal precharge time. In this case, too, normal precharging is performed according to the setting of bits TPC1 and TPC0 in DRACCR, and therefore a setting should be made to give the optimum post-self-refresh precharge time, including this time. Figure 6.70 shows an example of the timing when the precharge time after self-refreshing is extended by 2 states.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 267 of 1270 REJ09B0466-0100 TRc2 φ SDRAMφ RAS CAS WE CKE NOP PALL NOP ACTV NOP NOP DQMU, DQML Data bus Address bus TRp1 TRp2 Tp Tr Tc1 Tcl Tc2 Row addressColumn address Column address Precharge-sel Row address Continuous synchronous DRAM space write Software standby Figure 6.70 Example of Timing when Precharge Time after Self-Refreshing Is Extended by 2 States (TPCS2 to TPCS0 = H'2, TPC1 = 0, TPC0 = 0, CAS Latency 2) (3) Refreshing and All-Module-Clocks-Stopped Mode In this LSI, if the ACSE bit is set to 1 in MSTPCRH, and then a SLEEP instruction is executed with the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFF, EXMSTPCR = H'FFFF) or for operation of the 8-bit timer module alone (MSTPCR = H'FFFE, EXMSTPCR = H'FFFF), and a transition is made to the sleep state, the all-module-clocks-stopped mode is entered, in which the bus controller and I/O port clocks are also stopped. As the bus controller clock is also stopped in this mode, auto refreshing is not executed. If synchronous DRAM is connected to the external address space and DRAM data is to be retained in sleep mode, the ACSE bit must be cleared to 0 in MSTPCR. (4) Software Standby When a transition is made to normal software standby, the PALL command is not output. If synchronous DRAM is connected and DRAM data is to be retained in software standby, self- refreshing must be set.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 268 of 1270 REJ09B0466-0100

6.8.14 Mode Register Setting of Synchronous DRAM

To use synchronous DRAM, mode must be set after power-on. To set mode, set the RMTS2 to RMTS0 bits in DRAMCR to H'5 and enable the synchronous DRAM mode register setting. After that, access the continuous synchronous DRAM space in bytes. When the value to be set in the synchronous DRAM mode register is X, value X is set in the synchronous DRAM mode register by writing to the continuous synchronous DRAM space of address H'400000 + X for 8-bit bus configuration synchronous DRAM and by writing to the continuous synchronous DRAM space of address H'400000 + 2X for 16-bit bus configuration synchronous DRAM. The value of the address signal is fetched at the issuance time of the MRS command as the setting value of the mode register in the synchronous DRAM. Mode of burst read/burst write in the synchronous DRAM is not supported by this LSI. For setting the mode register of the synchronous DRAM, set the burst read/single write with the burst length of 1. Figure 6.71 shows the setting timing of the mode in the synchronous DRAM. Tp φ SDRAMφ RAS CAS WE CKE PALL MRS NOP NOP Address bus Tr Tc1 Tc2 Mode setting value Mode setting valuePrecharge-sel High Figure 6.71 Synchronous DRAM Mode Setting Timing

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6.8.15 DMAC and EXDMAC Single Addre ss Transfer Mode and Synchronous DRAM

When burst mode is selected on the synchronous DRAM interface, the DACK and EDACK output timing can be selected with the DDS and EDDS bits in DRAMCR. When continuous synchronous DRAM space is accessed in DMAC/EXDMAC single address mode at the same time, these bits select whether or not burst access is to be performed. The establishment time for the read data can be extended in the clock suspend mode irrespective of the settings of the DDS and EDDS bits. (1) Output Timing of DACK or EDACK When DDS = 1 or EDDS = 1: Burst access is performed by determining the address only, irrespective of the bus master. With the synchronous DRAM interface, the DACK or EDACK output goes low from the Tc1 state. Figure 6.72 shows the DACK or EDACK output timing for the synchronous DRAM interface when DDS = 1 or EDDS = 1.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 270 of 1270 REJ09B0466-0100 Tp φ SDRAMφ RAS Read CAS WE CKE PALL ACTV READ NOP DQMU, DQML Data bus Address bus Tr Tc1 Tcl Tc2 Row addressColumn address Column address Precharge-sel Row address High RAS Write CAS WE CKE PALL ACTV NOP NOP WRIT DQMU, DQML DACK or EDACK Data bus High Figure 6.72 Example of DACK/EDACK Output Timing when DDS = 1 or EDDS = 1

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 271 of 1270 REJ09B0466-0100 When DDS = 0 or EDDS = 0: When continuous synchronous DRAM space is accessed in DMAC or EXDMAC single address transfer mode, full access (normal access) is always performed. With the synchronous DRAM interface, the DACK or EDACK output goes low from the Tr state. In modes other than DMAC or EXDMAC single address transfer mode, burst access can be used when accessing continuous synchronous DRAM space. Figure 6.73 shows the DACK or EDACK output timing for connecting the synchronous DRAM interface when DDS = 0 or EDDS = 0.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 272 of 1270 REJ09B0466-0100 Tp φ SDRAMφ RAS Read CAS WE CKE PALL ACTV READ NOP DQMU, DQML Data bus Address bus Tr Tc1 Tcl Tc2 Row addressColumn address Column address Precharge-sel Row address High RAS Write CAS WE CKE PALL ACTV NOP NOP WRIT DQMU, DQML DACK or RDACK Data bus High Figure 6.73 Example of DACK/EDACK Output Timing when DDS = 0 or EDDS = 0

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 274 of 1270 REJ09B0466-0100

6.9 Burst ROM Interface

In this LSI, external address space areas 0 and 1 can be designated as burst ROM space, and burst ROM interfacing performed. The burst ROM space enables ROM with burst access capability to be accessed at high speed. Areas 1 and 0 can be designated as burst ROM space by means of bits BSRM1 and BSRM0 in BROMCR. Continuous burst accesses of 4, 8, 16, or 32 words can be performed, according to the setting of the BSWD11 and BSWD10 bits in BROMCR. From 1 to 8 states can be selected for burst access. Settings can be made independently for area 0 and area 1. In burst ROM space, burst access covers only CPU read accesses.

6.9.1 Basic Timing

The number of access states in the initial cycle (full access) on the burst ROM interface is determined by the basic bus interface settings in ASTCR, ABWCR, WTCRA, WTCRB, and CSACRH. When area 0 or area 1 is designated as burst ROM space, the settings in RDNCR and CSACRL are ignored. From 1 to 8 states can be selected for the burst cycle, according to the settings of bits BSTS02 to BSTS00 and BSTS12 to BSTS10 in BROMCR. Wait states cannot be inserted. Burst access of up to 32 words is performed, according to the settings of bits BSTS01, BSTS00, BSTS11, and BSTS10 in BROMCR. The basic access timing for burst ROM space is shown in figures 6.75 and 6.76.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 275 of 1270 REJ09B0466-0100 Upper address bus Lower address bus φ CSn AS Data bus T2 T3 T1 T2 T1 Full access RD Burst access Note: n = 1 and 0 Figure 6.75 Example of Burst ROM Access Timing (ASTn = 1, 2-State Burst Cycle)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 276 of 1270 REJ09B0466-0100 Upper address bus Lower address bus φ CSn AS Data bus T2 T1 T1 Full access RD Burst access Note: n = 1 and 0 Figure 6.76 Example of Burst ROM Access Timing (ASTn = 0, 1-State Burst Cycle)

6.9.2 Wait Control

As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) on the burst ROM interface. See section 6.5.4, Wait Control. Wait states cannot be inserted in a burst cycle.

6.9.3 Write Access

When a write access to burst ROM space is executed, burst access is interrupted at that point and the write access is executed in line with the basic bus interface settings. Write accesses are not performed in burst mode even though burst ROM space is designated.

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6.10 Idle Cycle

6.10.1 Operation

When this LSI accesses external address space, it can insert an idle cycle (Ti) between bus cycles in the following three cases: (1) when read accesses in different areas occur consecutively, (2) when a write cycle occurs immediately after a read cycle, and (3) when a read cycle occurs immediately after a write cycle. Insertion of a 1-state or 2-state idle cycle can be selected with the IDLC bit in BCR. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, etc., with a long output floating time, and high-speed memory, I/O interfaces, and so on. (1) Consecutive Reads in Different Areas If consecutive reads in different areas occur while the ICIS1 bit is set to 1 in BCR, an idle cycle is inserted at the start of the second read cycle. Figure 6.77 shows an example of the operation in this case. In this example, bus cycle A is a read cycle for ROM with a long output floating time, and bus cycle B is a read cycle for SRAM, each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in bus cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted, and a data collision is prevented. Address bus φ RD Bus cycle A Data bus T2 T3 T1 T2 Bus cycle B Long output floating time Data collision (a) No idle cycle insertion (ICIS1 = 0) Address bus φ RD Bus cycle A Data bus T2 T3 Ti T1 Bus cycle B (b) Idle cycle insertion (ICIS1 = 1, initial value) CS (area A) CS (area B) CS (area A) CS (area B) Idle cycle Figure 6.77 Example of Idle Cycle Operation (Consecutive Reads in Different Areas)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 280 of 1270 REJ09B0466-0100 (4) Relationship between Chip Select (CS) Signal and Read (RD) Signal Depending on the system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in figure 6.80. In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle A RD signal and the bus cycle B CS signal. Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS signals. In the initial state after reset release, idle cycle insertion (b) is set. Address bus φ RD Bus cycle A T2 T3 T1 T2 Bus cycle B Overlap period between CS (area B) and RD may occur (a) No idle cycle insertion (ICIS1 = 0) Address bus Idle cycle φ Bus cycle A T2 T3 Ti T1 Bus cycle B (b) Idle cycle insertion (ICIS1 = 1, initial value) CS (area A) CS (area B) RD CS (area A) CS (area B) Figure 6.80 Relationship between Chip Select (CS) and Read (RD)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 281 of 1270 REJ09B0466-0100 (5) Idle Cycle in Case of DRAM Space Access after Normal Space Access In a DRAM space access following a normal space access, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC in BCR are valid. However, in the case of consecutive reads in different areas, for example, if the second read is a full access to DRAM space, only a Tp cycle is inserted, and a Ti cycle is not. The timing in this case is shown in figure 6.81. Address bus φ RD External read Data bus T2 T3 Tp Tr DRAM space read Tc1 Tc2 Figure 6.81 Example of DRAM Full Access after External Read (CAST = 0) In burst access in RAS down mode, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC are valid and an idle cycle is inserted. The timing in this case is illustrated in figures 6.82 and 6.83.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 284 of 1270 REJ09B0466-0100 In burst access in RAS down mode, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC are valid and an idle cycle is inserted. However, in read access, note that the timings of DQMU and DQML differ according to the settings of the IDLC bit. The timing in this case is illustrated in figures 6.85 and 6.86. In write access, DQMU and DQML are not in accordance with the settings of the IDLC bit. The timing in this case is illustrated in figure 6.87. Tp Address bus External address Column address 1 Column address 2 External address Row address Column address Idle cycle Data bus Tr Tc1 Tcl Tc2 T3 Tc1 Continuous synchronous DRAM space read External space read Continuous synchronous DRAM space read T2 TiT1 RAS CAS WE RD HWR, LWR CKE High High PALL ACTV READ NOP NOPREAD DQMU, DQML TCl Tc2 Precharge-sel φ Row address Figure 6.85 Example of Idle Cycle Operation in RAS Down Mode (Read in Different Area) (IDLC = 0, CAS Latency 2)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 285 of 1270 REJ09B0466-0100 Tp Address bus Idle cycle Data bus Tr Tc1 Tcl Tc2 T3 Tc1 Continuous synchronous DRAM space read External space read Continuous synchronous DRAM space read T2 Ti TiT1 RAS CAS WE RD HWR, LWR CKE High High PALL ACTV READ NOP NOPREAD DQMU, DQML TCl Tc2 Precharge-sel φ Row address Row address Column address External address External address Column address 1 Column address 2 Figure 6.86 Example of Idle Cycle Operation in RAS Down Mode (Read in Different Area) (IDLC = 1, CAS Latency 2)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 286 of 1270 REJ09B0466-0100 Tp Address bus Idle cycle Data bus Tr Tc1 Tcl Tc2 T3 Tc1 Continuous synchronous DRAM space read External space read Continuous synchronous DRAM space write T2 TiT1 RAS CAS WE RD HWR, LWR CKE High High PALL ACTV READ NOP NOPWRIT DQMU, DQML TCl Tc2 Precharge-sel φ Row address Row address Column address External address External address Column address 1 Column address 2 Figure 6.87 Example of Idle Cycle Operation in RAS Down Mode (Write after Read) (IDLC = 0, CAS Latency 2)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 287 of 1270 REJ09B0466-0100 (7) Idle Cycle in Case of Normal Space Access after DRAM Space Access (a) Normal space access after DRAM space read access While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after DRAM space access is disabled. Idle cycle insertion after DRAM space access can be enabled by setting the DRMI bit to 1. The conditions and number of states of the idle cycle to be inserted are in accordance with the settings of bits ICIS1, ICIS0, and IDLC in BCR are valid. Figures 6.88 and 6.89 show examples of idle cycle operation when the DRMI bit is set to 1. When the DRMI bit is cleared to 0, an idle cycle is not inserted after DRAM space access even if bits ICIS1 and ICIS0 are set to 1. Tp Address bus φ RD RAS UCAS, LCAS External address space read Idle cycle Data bus Tr Tc1 Tc2 T1 DRAM space readDRAM space read T2 Tc2T3 TiTi Tc1 Figure 6.88 Example of Idle Cycle Operation after DRAM Access (Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 288 of 1270 REJ09B0466-0100 Tp Address bus φ RD RAS HWR, LWR UCAS, LCAS External address space write Idle cycle Data bus Tr Tc1 Tc2 T1 DRAM space readDRAM space read T2 Tc2T3Ti Tc1 Figure 6.89 Example of Idle Cycle Operation after DRAM Access (Write after Read) (IDLC = 0, RAST = 0, CAST = 0)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 289 of 1270 REJ09B0466-0100 (b) Normal space access after DRAM space write access While the ICIS2 bit is set to 1 in BCR and a normal space read access occurs after DRAM space write access, idle cycle is inserted in the first read cycle. The number of states of the idle cycle to be inserted is in accordance with the setting of the IDLC bit. It does not depend on the DRMI bit in DRACCR. Figure 6.90 shows an example of idle cycle operation when the ICIS2 bit is set to 1. Tp Address bus φ RD RAS HWR, LWR UCAS, LCAS External space read Idle cycle Data bus Tr Tc1 Tc2 T1 DRAM space readDRAM space read T2 Tc2T3Ti Tc1 Figure 6.90 Example of Idle Cycle Operation after DRAM Write Access (IDLC = 0, ICIS1 = 0, RAST = 0, CAST = 0) (8) Idle Cycle in Case of Normal Space Access after Continuous Synchronous DRAM Space Access: Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424 Group.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 290 of 1270 REJ09B0466-0100 (a) Normal space access after a continuous synchronous DRAM space read access While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after continuous synchronous DRAM space read access is disabled. Idle cycle insertion after continuous synchronous DRAM space read access can be enabled by setting the DRMI bit to 1. The conditions and number of states of the idle cycle to be inserted are in accordance with the settings of bits ICIS1, ICIS0, and IDLC in RCR. Figure 6.91 shows an example of idle cycle operation when the DRMI bit is set to 1. When the DRMI bit is cleared to 0, an idle cycle is not inserted after continuous synchronous DRAM space read access even if bits ICIS1 and ICIS0 are set to 1. Tp Address bus Idle cycle Data bus Tr Tc1 Tcl Tc2 T3 Ti Tc1 Continuous synchronous DRAM space read External space read Continuous synchronous DRAM space read T2Ti T1 RAS CAS WE RD CKE High PALL ACTV READ NOP NOPREAD DQMU, DQML TCl Tc2 Precharge-sel φ External address External address Column address 1 Column address 2Row address Row address Column address Figure 6.91 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space Read Access (Read between Different Area) (IDLC = 0, CAS Latency 2)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 292 of 1270 REJ09B0466-0100 Table 6.12 shows whether there is an idle cycle insertion or not in the case of mixed accesses to normal space and DRAM space/continuous synchronous DRAM space. Table 6.12 Idle Cycles in Mixed Accesses to Normal Space and DRAM Continuous Synchronous DRAM Space Previous Access Next Access ICIS2 ICIS1 ICIS0 DRMI IDLC Idle cycle  0    Disabled  1   0 1 state inserted Normal space read (different area) 1 2 states inserted  0    Disabled  1   0 1 state inserted DRAM*/continuous synchronous DRAM space read 1 2 states inserted   0   Disabled   1  0 1 state inserted Normal space write 1 2 states inserted   0   Disabled   1  0 1 state inserted Normal space read DRAM*/continuous synchronous DRAM space write 1 2 states inserted  0    Disabled  1  0  Disabled 1 0 1 state inserted Normal space read 1 2 states inserted  0    Disabled  1  0  Disabled 1 0 1 state inserted DRAM*/continuous synchronous DRAM space read 1 2 states inserted   0   Disabled   1 0  Disabled 1 0 1 state inserted Normal space write 1 2 states inserted   0   Disabled   1 0  Disabled 1 0 1 state inserted DRAM/continuous synchronous DRAM* space read DRAM*/continuous synchronous DRAM space write 1 2 states inserted

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 293 of 1270 REJ09B0466-0100 Previous Access Next Access ICIS2 ICIS1 ICIS0 DRMI IDLC Idle cycle 0     Disabled 1    0 1 state inserted Normal space read 1 2 states inserted 0     Disabled 1    0 1 state inserted Normal space write DRAM*/continuous synchronous DRAM space read 1 2 states inserted 0     Disabled 1    0 1 state inserted Normal space read 1 2 states inserted 0     Disabled 1    0 1 state inserted DRAM/continuous synchronous DRAM* space write DRAM*/continuous synchronous DRAM space read 1 2 states inserted Note: * Not supported by the H8S/ 2426 Group and H8S/2424 Group.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 294 of 1270 REJ09B0466-0100 Setting the DRMI bit in DRACCR to 1 enables an idle cycle to be inserted in the case of consecutive read and write operations in DRAM/continuous synchronous DRAM space burst access. Figures 6.93 and 6.94 show an example of the timing for idle cycle insertion in the case of consecutive read and write accesses to DRAM/continuous synchronous DRAM space. Tp Address bus Idle cycle Data bus Tr Tc1 Tc2 DRAM space writeDRAM space read Tc2Ti Tc1 RASn (CSn) UCAS, LCAS WE (HWR) OE (RD) Note: n = 2 to 5 φ Figure 6.93 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and Write Accesses to DRAM Space in RAS Down Mode

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 295 of 1270 REJ09B0466-0100 Tp Address bus Idle cycle Data bus Tr Tc1 Tcl Tc2 Continuous synchronous DRAM space write Continuous synchronous DRAM space read Tc2Ti Tc1 RAS CAS WE CKE High PALL ACTV READ NOP WRIT DQMU, DQML Precharge-sel φ External addressColumn address Row address Column address Row address Figure 6.94 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and Write Accesses to Continuous Synchronous DRAM Space in RAS Down Mode (SDWCD = 1, CAS Latency 2)

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 296 of 1270 REJ09B0466-0100

6.10.2 Pin States in Idle Cycle

Table 6.13 shows the pin states in an idle cycle. Table 6.13 Pin States in Idle Cycle Pins Pin State A23 to A0 Contents of following bus cycle D15 to D0 High impedance CSn (n = 7 to 0) High * UCAS, LCAS High * AS/AH High RD High OE High HWR, LWR High DACKn (n = 1, 0) High EDACKn (n = 3 to 0) High Notes: 1. Remains low in DRAM space RAS down mode. 2. Remains low in a DRAM space refresh cycle.

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6.11 Write Data Buffer Function

This LSI has a write data buffer function for the external data bus. Using the write data buffer function enables external writes and DMA single address mode transfers to be executed in parallel with internal accesses. The write data buffer function is made available by setting the WDBE bit to 1 in BCR. Figure 6.95 shows an example of the timing when the write data buffer function is used. When this function is used, if an external address space write or DMA single address mode transfer continues for two states or longer, and there is an internal access next, an external write only is executed in the first state, but from the next state onward an internal access (on-chip memory or internal I/O register read/write) is executed in parallel with the external address space write rather than waiting until it ends. Internal address bus A23 to A0 External write cycle HWR, LWR T2 TW TW T3 On-chip memory read Internal I/O register read Internal read signal CSn D15 to D0 External address Internal memory External space write Internal I/O register address φ Figure 6.95 Example of Timing when Write Data Buffer Function Is Used

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6.12 Bus Release

This LSI can release the external bus in response to a bus request from an external device. In the external bus released state, internal bus masters except the EXDMAC* continue to operate as long as there is no external access. If any of the following requests are issued in the external bus released state, the BREQO signal can be driven low to output a bus request externally.

  • When an internal bus master wants to perform an external access
  • When a refresh request is generated
  • When a SLEEP instruction is executed to place the chip in software standby mode or all- module-clocks-stopped mode Note: * Not supported by the H8S/2424 Group.

6.12.1 Operation

In externally expanded mode, the bus can be released to an external device by setting the BRLE bit to 1 in BCR. Driving the BREQ pin low issues an external bus request to this LSI. When the BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the address bus, data bus, and bus control signals are placed in the high-impedance state, establishing the external bus released state. In the external bus released state, internal bus masters except the EXDMAC can perform accesses using the internal bus. When an internal bus master wants to make an external access, it temporarily defers initiation of the bus cycle, and waits for the bus request from the external bus master to be canceled. If a refresh request is generated in the external bus released state, or if a SLEEP instruction is executed to place the chip in software standby mode or all-module-clocks- stopped mode, refresh control and software standby or all-module-clocks-stopped control is deferred until the bus request from the external bus master is canceled. If the BREQOE bit is set to 1 in BCR, the BREQO pin can be driven low when any of the following requests are issued, to request cancellation of the bus request externally.

  • When an internal bus master wants to perform an external access
  • When a refresh request is generated
  • When a SLEEP instruction is executed to place the chip in software standby mode or all- module-clocks-stopped mode

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 299 of 1270 REJ09B0466-0100 When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the external bus released state is terminated. If an external bus release request and external access occur simultaneously, the order of priority is as follows: (High) External bus release > External access by internal bus master (Low) If a refresh request and external bus release request occur simultaneously, the order of priority is as follows: (High) Refresh > Exte rnal bus release (Low)

6.12.2 Pin States in External Bus Released State

Table 6.14 shows pin states in the external bus released state. Table 6.14 Pin States in Bus Released State Pins Pin State A23 to A0 High impedance D15 to D0 High impedance CSn (n = 7 to 0) High impedance UCAS, LCAS High impedance AS/AH High impedance RD High impedance OE High impedance HWR, LWR High impedance DACKn (n = 1, 0) High EDACKn (n = 3, 2) High

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 300 of 1270 REJ09B0466-0100

6.12.3 Transition Timing

Figure 6.96 shows the timing for transition to the bus released state. CPU cycleExternal bus released state External space access cycle T1 T2 φ Address bus HWR, LWR BREQ BACK BREQO High impedance High impedance High impedance High impedance High impedance [1] Low level of BREQ signal is sampled at rise of φ. [2] Bus control signal returns to be high at end of external space access cycle. At least one state from sampling of BREQ signal. [3] BACK signal is driven low, releasing bus to external bus master. [4] BREQ signal state is also sampled in external bus released state. [5] High level of BREQ signal is sampled. [6] BACK signal is driven high, ending external bus release cycle. [7] When there is external access or refresh request of internal bus master during external bus release while BREQOE bit is set to 1, BREQO signal goes low. [8] Normally BREQO signal goes high 1.5 states after rising edge of BACK signal. Data bus AS RD Figure 6.96 Bus Released State Transition Timing

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 302 of 1270 REJ09B0466-0100

6.13 Bus Arbitration

This LSI has a bus arbiter that arbitrates bus mastership operations (bus arbitration). There are four bus mastersthe CPU, DTC, DMAC, and EXDMAC* that perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal. The selected bus master then takes possession of the bus and begins its operation. Note: * The EXDMAC is not supported by the H8S/2424 Group.

6.13.1 Operation

The bus arbiter detects the bus masters’ bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master. If there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. The order of priority of the bus mastership is as follows: (High) EXDMAC* > DMAC > DTC > CPU (Low) An internal bus access by internal bus masters except the EXDMAC* and external bus release, a refresh when the CBRM bit is 0, and an external bus access by the EXDMAC* can be executed in parallel. If an external bus release request, a refresh request, and an external access by an internal bus master occur simultaneously, the order of priority is as follows: (High) Refresh > EXDMAC* > External bus release (Low) (High) External bus release > External access by internal bus master except EXDMAC* (Low) As a refresh when the CBRM bit in REFCR is cleared to 0 and an external access other than to DRAM space by an internal bus master can be executed simultaneously, there is no relative order of priority for these two operations. Note: * The EXDMAC is not supported by the H8S/2424 Group.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 303 of 1270 REJ09B0466-0100

6.13.2 Bus Transfer Timing

Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific timings at which each bus master can relinquish the bus. (1) CPU The CPU is the lowest-priority bus master, and if a bus request is received from the DTC, DMAC, or EXDMAC*, the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of the bus is as follows:

  • The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the component operations.
  • With bit manipulation instructions such as BSET and BCLR, the sequence of operations is: data read (read), relevant bit manipulation operation (modify), write-back (write). The bus is not transferred during this read-modify-write cycle, which is executed as a series of bus cycles.
  • If the CPU is in sleep mode, the bus is transferred immediately. Note: * The EXDMAC is not supported by the H8S/2424 Group. (2) DTC The DTC sends the bus arbiter a request for the bus when an activation request is generated. The DTC can release the bus after a vector read, a register information read (3 states), a single data transfer, or a register information write (3 states). It does not release the bus during a register information read (3 states), a single data transfer, or a register information write (3 states). (3) DMAC The DMAC sends the bus arbiter a request for the bus when an activation request is generated. In the case of an external request in short address mode or normal mode, and in cycle steal mode, the DMAC releases the bus after a single transfer. In block transfer mode, it releases the bus after transfer of one block, and in burst mode, after completion of the transfer. However, in the event of an EXDMAC or external bus release request, which have a higher priority than the DMAC, the bus may be transferred to the bus master even if block or burst transfer is in progress.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 304 of 1270 REJ09B0466-0100 (4) EXDMAC The EXDMAC sends the bus arbiter a request for the bus when an activation request is generated. As the EXDMAC is used exclusively for transfers to and from the external bus, if the bus is transferred to the EXDMAC, internal accesses by other internal bus masters are still executed in parallel. In normal transfer mode or cycle steal transfer mode, the EXDMAC releases the bus after a single transfer. In block transfer mode, it releases the bus after transfer of one block, and in burst transfer mode, after completion of the transfer. By setting the BGUP bit to 1 in EDMDR, it is possible to specify temporary release of the bus in the event of an external access request from an internal bus master. For details see section 8, EXDMA Controller (EXDMAC). Note: The EXDMAC is not supported by the H8S/2424 Group. (5) External Bus Release When the BREQ pin goes low and an external bus release request is issued while the BRLE bit is set to 1 in BCR, a bus request is sent to the bus arbiter. External bus release can be performed on completion of an external bus cycle.

6.14 Bus Controller Operation in Reset

In a reset, this LSI, including the bus controller, enters the reset state immediately, and any executing bus cycle is aborted.

Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 19, 2008 Page 305 of 1270 REJ09B0466-0100

6.15 Usage Notes

6.15.1 External Bus Release Function and All-Module-Clocks-Stopped Mode

In this LSI, if the ACSE bit is set to 1 in MSTPCR, and then a SLEEP instruction is executed with the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFF, EXMSTPCR = H'FFFF) or for operation of the 8-bit timer module alone (MSTPCR = H'FFFE, EXMSTPCR = H'FFFF), and a transition is made to the sleep state, the all-module-clocks-stopped mode is entered in which the clock is also stopped for the bus controller and I/O ports. In this state, the external bus release function is halted. To use the external bus release function in sleep mode, the ACSE bit in MSTPCR must be cleared to 0. Conversely, if a SLEEP instruction to place the chip in all- module-clocks-stopped mode is executed in the external bus released state, the transition to all- module-clocks-stopped mode is deferred and performed until after the bus is recovered.

6.15.2 External Bus Release Function and Software Standby

In this LSI, internal bus master operation does not stop even while the bus is released, as long as the program is running in on-chip ROM, etc., and no external access occurs. If a SLEEP instruction to place the chip in software standby mode is executed while the external bus is released, the transition to software standby mode is deferred and performed after the bus is recovered. Also, since clock oscillation halts in software standby mode, if BREQ goes low in this mode, indicating an external bus release request, the request cannot be answered until the chip has recovered from the software standby state.

6.15.3 External Bus Release Function and CBR Refreshing/Auto Refreshing

CBR refreshing/auto refreshing cannot be executed while the external bus is released. Setting the BREQOE bit to 1 in BCR beforehand enables the BREQO signal to be output when a CBR refresh/auto refresh request is issued. Note: The auto refresh control function is not supported by the H8S/2426 Group and H8S/2424 Group.

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6.15.4 BREQO Output Timing

When the BREQOE bit is set to 1 and the BREQO signal is output, BREQO may go low before the BACK signal. This will occur if the next external access request or CBR refresh request occurs while internal bus arbitration is in progress after the chip samples a low level of BREQ.

6.15.5 Notes on Usage of the Synchronous DRAM

(1) Connection Clock Be sure to set the clock to be connected to the synchronous DRAM to SDRAMφ. (2) WAIT Pin In the continuous synchronous DRAM space, insertion of the wait state by the WAIT pin is disabled regardless of the setting of the WAITE bit in BCR. (3) Bank Control This LSI cannot carry out the bank control of the synchronous DRAM. All banks are selected. (4) Burst Access The burst read/burst write mode of the synchronous DRAM is not supported. When setting the mode register of the synchronous DRAM, set to the burst read/single write and set the burst length to 1. (5) CAS Latency When connecting a synchronous DRAM having CAS latency of 1, set the BE bit to 0 in the DRAMCR. Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424 Group.

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 307 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) This LSI has a built-in DMA controller (DMAC), which can carry out data transfer on up to 4 channels.

7.1 Features

  • Selectable as short address mode or full address mode Short address mode  Maximum of 4 channels can be used  Dual address mode or single address mode can be selected  In dual address mode, one of the two addresses, transfer source and transfer destination, is specified as 24 bits and the other as 16 bits  In single address mode, transfer source or transfer destination address only is specified as 24 bits  In single address mode, transfer can be performed in one bus cycle  Choice of sequential mode, idle mode, or repeat mode for dual address mode and single address mode Full address mode  Maximum of 2 channels can be used  Transfer source and transfer destination addresses as specified as 24 bits  Choice of normal mode or block transfer mode
  • 16-Mbyte address space can be specified directly
  • Byte or word can be set as the transfer unit
  • Activation sources: internal interrupt, external request, auto-request (depending on transfer mode)  Six compare match/input capture interrupts of 16-bit timer-pulse unit (TPU0 to 5).  Transmission complete interrupt and reception complete interrupt of serial communication interface (SCI_0, SCI_1)  External request  Auto-request
  • Module stop mode can be set

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 308 of 1270 REJ09B0466-0100 A block diagram of the DMAC is shown in figure 7.1. TGI0A TGI1A TGI2A TGI3A TGI4A TGI5A TXI0 RXI0 TXI1 RXI1 ADI ADI0 DREQ0 DREQ1 TEND0 TEND1 DACK0 DACK1 DMTEND0A DMTEND0B DMTEND1A DMTEND1B DMAWER DMACR_1B DMACR_1A DMACR_0B DMACR_0A DMATCR DMABCR MAR_0AH MAR_0BH IOAR_0A ETCR_0A IOAR_0B ETCR_0B MAR_1AH IOAR_1A ETCR_1A MAR_1BH MAR_0AL MAR_0BL MAR_1AL MAR_1BL IOAR_1B ETCR_1B Internal address bus Address buffer Processor Internal interrupts External pins Interrupt signals Control logic Data buffer Internal data bus Legend: DMAWER : DMA write enable register DMATCR : DMA terminal control register DMABCR : DMA band control register (for all channels) DMACR : DMA control register MAR : Memory address register IOAR : I/O address register ETCR : Execute transfer count register Module data bus Channel 0Channel 1 Channel 0AChannel 0BChannel 1AChannel 1B Figure 7.1 Block Diagram of DMAC

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 309 of 1270 REJ09B0466-0100

7.2 Input/Output Pins

Table 7.1 shows the pin configuration of the interrupt controller. Table 7.1 Pin Configuration Channel Pin Name Symbol I/O Function

0 DMA request 0 DREQ0 Input Channel 0 external request

DMA transfer acknowledge 0 DACK0 Output Channel 0 single address transfer acknowledge DMA transfer end 0 TEND0 Output Channel 0 transfer end

1 DMA request 1 DREQ1 Input Channel 1 external request

DMA transfer acknowledge 1 DACK1 Output Channel 1 single address transfer acknowledge DMA transfer end 1 TEND1 Output Channel 1 transfer end

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 310 of 1270 REJ09B0466-0100

7.3 Register Descriptions

  • Memory address register_0AH (MAR_0AH)
  • Memory address register_0AL (MAR_0AL)
  • I/O address register_0A (IOAR_0A)
  • Transfer count register_0A (ECTR_0A)
  • Memory address register_0BH (MAR_0BH)
  • Memory address register_0BL (MAR_0BL)
  • I/O address register_0B (IOAR_0B)
  • Transfer count register_0B (ECTR_0B)
  • Memory address register_1AH (MAR_1AH)
  • Memory address register_1AL (MAR_1AL)
  • I/O address register_1A (IOAR_1A)
  • Transfer count register_1A (ETCR_1A)
  • Memory address register_1BH (MAR_1BH)
  • Memory address register_1BL (MAR_1BL)
  • I/O address register_1B (IOAR_1B)
  • Transfer count register_1B (ETCR_1B)
  • DMA control register_0A (DMACR_0A)
  • DMA control register_0B (DMACR_0B)
  • DMA control register_1A (DMACR_1A)
  • DMA control register_1B (DMACR_1B)
  • DMA band control register H (DMABCRH)
  • DMA band control register L (DMABCRL)
  • DMA write enable register (DMAWER)
  • DMA terminal control register (DMATCR) The functions of MAR, IOAR, ETCR, DMACR, and DMABCR differ according to the transfer mode (short address mode or full address mode). The transfer mode can be selected by means of the FAE1 and FAE0 bits in DMABCRH. The register configurations for short address mode and full address mode of channel 0 are shown in table 7.2.

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 311 of 1270 REJ09B0466-0100 Table 7.2 Short Address Mode and Full Address Mode (Channel 0) FAE0 Description

0 Short address mode specified (channel s 0A and 0B operate independently)

MAR_0AH Specifies transfer source/transfer destination address Specifies transfer destination/transfer source address Specifies number of transfers Specifies transfer size, mode, activation source. Specifies transfer source/transfer destination address Specifies transfer destination/transfer source address Specifies number of transfers Specifies transfer size, mode, activation source. IOAR_0A ETCR_0A DMACR_0A Channel 0B MAR_0BH MAR_0AL MAR_0BL IOAR_0B ETCR_0B DMACR_0B

1 Full address mode specified (channels 0A and 0B operate in combination as channel 0)

MAR_0AH Specifies transfer source address Specifies transfer destination address Not used Not used Specifies number of transfers Specifies number of transfers (used in block transfer mode only) Specifies transfer size, mode, activation source, etc. IOAR_0A ETCR_0A DMACR_0A MAR_0BH MAR_0AL MAR_0BL IOAR_0B ETCR_0B DMACR_0B

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 312 of 1270 REJ09B0466-0100

7.3.1 Memory Address Re gisters (MARA and MARB)

MAR is a 32-bit readable/writable register that specifies the source address (transfer source address) or destination address (transfer destination address). MAR consists of two 16-bit registers MARH and MARL. The upper 8 bits of MARH are reserved: they are always read as 0, and cannot be modified. The DMA has four MAR registers: MAR_0A in channel 0 (channel 0A), MAR_0B in channel 0 (channel 0B), MAR_1A in channel 1 (channel 1A), and MAR_1B in channel 1 (channel 1B). MAR is not initialized by a reset or in standby mode. Short Address Mode: In short address mode, MARA and MARB operate independently. Whether MAR functions as the source address register or as the destination address register can be selected by means of the DTDIR bit in DMACR. MAR is incremented or decremented each time a byte or word transfer is executed, so that the address specified by MAR is constantly updated. Full Address Mode: In full address mode, MARA functions as the source address register, and MARB as the destination address register. MAR is incremented or decremented each time a byte or word transfer is executed, so that the source or destination address is constantly updated.

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7.3.2 I/O Address Registers (IOARA and IOARB)

IOAR is a 16-bit readable/writable register that specifies the lower 16 bits of the source address (transfer source address) or destination address (transfer destination address). The upper 8 bits of the transfer address are automatically set to H'FF. The DMA has four IOAR registers: IOAR_0A in channel 0 (channel 0A), IOAR_0B in channel 0 (channel 0B), IOAR_1A in channel 1 (channel 1A), and IOAR_1B in channel 1 (channel 1B). Whether IOAR functions as the source address register or as the destination address register can be selected by means of the DTDIR bit in DMACR. IOAR is not incremented or decremented each time a data transfer is executed, so the address specified by IOAR is fixed. IOAR is not initialized by a reset or in standby mode. IOAR can be used in short address mode but not in full address mode.

7.3.3 Execute Transf er Count Registers (ETCRA and ETCRB)

ETCR is a 16-bit readable/writable register that specifies the number of transfers. The DMA has four ETCR registers: ETCR_0A in channel 0 (channel 0A), ETCR_0B in channel 0 (channel 0B), ETCR_1A in channel 1 (channel 1A), and ETCR_1B in channel 1 (channel 1B). ETCR is not initialized by a reset or in standby mode.

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 314 of 1270 REJ09B0466-0100 (1) Short Address Mode The function of ETCR in sequential mode and idle mode differs from that in repeat mode. In sequential mode and idle mode, ETCR functions as a 16-bit transfer counter. ETCR is decremented by 1 each time a transfer is performed, and when the count reaches H'00, the DTE bit in DMABCRL is cleared, and transfer ends. In repeat mode, ETCRL functions as an 8-bit transfer counter and ETCRH functions as a transfer count holding register. ETCRL is decremented by 1 each time a transfer is performed, and when the count reaches H'00, ETCRL is loaded with the value in ETCRH. At this point, MAR is automatically restored to the value it had when the count was started. The DTE bit in DMABCRL is not cleared, and so transfers can be performed repeatedly until the DTE bit is cleared by the user. (2) Full Address Mode The function of ETCR in normal mode differs from that in block transfer mode. In normal mode, ETCRA functions as a 16-bit transfer counter. ETCRA is decremented by 1 each time a data transfer is performed, and transfer ends when the count reaches H'0000. ETCRB is not used in normal mode. In block transfer mode, ETCRA functions as an 8-bit block size counter (ETCRAL) and ETCRAH functions as a block size holding register. ETCRAL is decremented by 1 each time a 1-byte or 1- word transfer is performed, and when the count reaches H'00, ETCRAL is loaded with the value in ETCRAH. So by setting the block size in ETCRAH and ETCRAL, it is possible to repeatedly transfer blocks consisting of any desired number of bytes or words. In block transfer mode, ETCRB functions as a 16-bit block transfer counter. ETCRB is decremented by 1 each time a block is transferred, and transfer ends when the count reaches H'0000.

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 315 of 1270 REJ09B0466-0100

7.3.4 DMA Control Registers (DMACRA and DMACRB)

DMACR controls the operation of each DMAC channel. The DMA has four DMACR registers: DMACR_0A in channel 0 (channel 0A), DMACR_0B in channel 0 (channel 0B), DMACR_1A in channel 1 (channel 1A), and DMACR_1B in channel 1 (channel 1B). In short address mode, channels A and B operate independently, and in full address mode, channels A and B operate together. The bit functions in the DMACR registers differ according to the transfer mode. (1) Short Address Mode:

  • DMACR_0A, DMACR_0B, DMACR_1A, and DMARC_1B Bit Bit Name Initial Value R/W Description

7 DTSZ 0 R/W Data Transfer Size

Selects the size of data to be transferred at one time. 0: Byte-size transfer 1: Word-size transfer

6 DTID 0 R/W Data Transfer Increment/Decrement

Selects incrementing or decrementing of MAR after every data transfer in sequential mode or repeat mode. In idle mode, MAR is neither incremented nor decremented. 0: MAR is incremented after a data transfer (Initial value)

  • When DTSZ = 0, MAR is incremented by 1
  • When DTSZ = 1, MAR is incremented by 2 1: MAR is decremented after a data transfer
  • When DTSZ = 0, MAR is decremented by 1
  • When DTSZ = 1, MAR is decremented by 2

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 316 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description

5 RPE 0 R/W Repeat Enable

Used in combination with the DTIE bit in DMABCR to select the mode (sequential, idle, or repeat) in which transfer is to be performed.

  • When DTIE = 0 (no transfer end interrupt) 0: Transfer in sequential mode 1: Transfer in repeat mode
  • When DTIE = 1 (with transfer end interrupt) 0: Transfer in sequential mode 1: Transfer in idle mode

4 DTDIR 0 R/W Data Transfer Direction

Used in combination with the SAE bit in DMABCR to specify the data transfer direction (source or destination). The function of this bit is therefore different in dual address mode and single address mode.

  • When SAE = 0 0: Transfer with MAR as source address and IOAR as destination address 1: Transfer with IOAR as source address and MAR as destination address
  • When SAE = 1 0: Transfer with MAR as source address and DACK pin as write strobe 1: Transfer with DACK pin as read strobe and MAR as destination address

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 317 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description DTF3 DTF2 DTF1 DTF0 R/W R/W R/W R/W Data Transfer Factor 3 to 0 These bits select the data transfer factor (activation source). There are some differences in activation sources for channel A and channel B.

  • Channel A 0000: Setting prohibited 0001: Activated by A/D converter conversion end interrupt 0010: Setting prohibited 0011: Setting prohibited 0100: Activated by SCI channel 0 transmission complete interrupt 0101: Activated by SCI channel 0 reception complete interrupt 0110: Activated by SCI channel 1 transmission complete interrupt 0111: Activated by SCI channel 1 reception complete interrupt 1000: Activated by TPU channel 0 compare match/input capture A interrupt 1001: Activated by TPU channel 1 compare match/input capture A interrupt 1010: Activated by TPU channel 2 compare match/input capture A interrupt 1011: Activated by TPU channel 3 compare match/input capture A interrupt 1100: Activated by TPU channel 4 compare match/input capture A interrupt 1101: Activated by TPU channel 5 compare match/input capture A interrupt 1110: Setting prohibited 1111: Setting prohibited

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 318 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description DTF3 DTF2 DTF1 DTF0 R/W R/W R/W R/W

  • Channel B 0000: Setting prohibited 0001: Activated by A/D converter conversion end interrupt 0010: Activated by DREQ pin falling edge input (detected as a low level in the first transfer after transfer is enabled)* 0011: Activated by DREQ pin low-level input* 0100: Activated by SCI channel 0 transmission complete interrupt 0101: Activated by SCI channel 0 reception complete interrupt 0110: Activated by SCI channel 1 transmission complete interrupt 0111: Activated by SCI channel 1 reception complete interrupt 1000: Activated by TPU channel 0 compare match/input capture A interrupt 1001: Activated by TPU channel 1 compare match/input capture A interrupt 1010: Activated by TPU channel 2 compare match/input capture A interrupt 1011: Activated by TPU channel 3 compare match/input capture A interrupt 1100: Activated by TPU channel 4 compare match/input capture A interrupt 1101: Activated by TPU channel 5 compare match/input capture A interrupt 1110: Setting prohibited 1111: Setting prohibited The same factor can be selected for more than one channel. In this case, activation starts with the highest-priority channel according to the relative channel priorities. For relative channel priorities, see section 7.5.12, Multi-Channel Operation.

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 319 of 1270 REJ09B0466-0100 (2) Full Address Mode

  • DMACR_0A and DMACR_1A Bit Bit Name Initial Value R/W Description

15 DTSZ 0 R/W Data Transfer Size

Selects the size of data to be transferred at one time. 0: Byte-size transfer 1: Word-size transfer SAID SAIDE R/W R/W Source Address Increment/Decrement Source Address Increment/Decrement Enable These bits specify whether source address register MARA is to be incremented, decremented, or left unchanged, when data transfer is performed. 00: MARA is fixed 01: MARA is incremented after a data transfer

  • When DTSZ = 0, MARA is incremented by 1
  • When DTSZ = 1, MARA is incremented by 2 10: MARA is fixed 11: MARA is decremented after a data transfer
  • When DTSZ = 0, MARA is decremented by 1
  • When DTSZ = 1, MARA is decremented by 2 BLKDIR BLKE R/W R/W Block Direction Block Enable These bits specify whether normal mode or block transfer mode is to be used for data transfer. If block transfer mode is specified, the BLKDIR bit specifies whether the source side or the destination side is to be the block area. x0: Transfer in normal mode 01: Transfer in block transfer mode (destination side is block area) 11: Transfer in block transfer mode (source side is block area)

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 320 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description 10 to 8  All 0 R/W Reserved These bits can be read from or written to. However, the write value should always be 0. Legend: x: Don’t care

  • DMACR_0B and DMACR_1B Bit Bit Name Initial Value R/W Description 7  0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. DAID DAIDE R/W R/W Destination Address Increment/Decrement Destination Address Increment/Decrement Enable These bits specify whether destination address register MARB is to be incremented, decremented, or left unchanged, when data transfer is performed. 00: MARB is fixed 01: MARB is incremented after a data transfer
  • When DTSZ = 0, MARB is incremented by 1
  • When DTSZ = 1, MARB is incremented by 2 10: MARB is fixed 11: MARB is decremented after a data transfer
  • When DTSZ = 0, MARB is decremented by 1
  • When DTSZ = 1, MARB is decremented by 2 4 — 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0.

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 321 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description DTF3 DTF2 DTF1 DTF0 R/W R/W R/W R/W Data Transfer Factor 3 to 0 These bits select the data transfer factor (activation source). The factors that can be specified differ between normal mode and block transfer mode.

  • Normal Mode 0000: Setting prohibited 0001: Setting prohibited 0010: Activated by DREQ pin falling edge input (detected as a low level in the first transfer after transfer is enabled)* 0011: Setting prohibited 010x: Setting prohibited 0110: Auto-request (cycle steal) 0111: Auto-request (burst) 1×××: Setting prohibited

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 322 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description DTF3 DTF2 DTF1 DTF0 R/W R/W R/W R/W

  • Block Transfer Mode 0000: Setting prohibited 0001: Activated by A/D converter conversion end interrupt 0010: Activated by DREQ pin falling edge input (detected as a low level in the first transfer after transfer is enabled) 0011: Activated by DREQ pin low-level input 0100: Activated by SCI channel 0 transmission complete interrupt 0101: Activated by SCI channel 0 reception complete interrupt 0110: Activated by SCI channel 1 transmission complete interrupt 0111: Activated by SCI channel 1 reception complete interrupt 1000: Activated by TPU channel 0 compare match/input capture A interrupt 1001: Activated by TPU channel 1 compare match/input capture A interrupt 1010: Activated by TPU channel 2 compare match/input capture A interrupt 1011: Activated by TPU channel 3 compare match/input capture A interrupt 1100: Activated by TPU channel 4 compare match/input capture A interrupt 1101: Activated by TPU channel 5 compare match/input capture A interrupt 1110: Setting prohibited 1111: Setting prohibited The same factor can be selected for more than one channel. In this case, activation starts with the highest-priority channel according to the relative channel priorities. For relative channel priorities, see section 7.5.12, Multi-Channel Operation. Legend: ×: Don’t care

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 323 of 1270 REJ09B0466-0100

7.3.5 DMA Band Control Registers H and L (DMABCRH and DMABCRL)

DMABCR controls the operation of each DMAC channel. The bit functions in the DMABCR registers differ according to the transfer mode. (1) Short Address Mode:

  • DMABCRH Bit Bit Name Initial Value R/W Description

15 FAE1 0 R/W Full Address Enable 1

Specifies whether channel 1 is to be used in short address mode or full address mode. In short address mode, channels 1A and 1B can be used as independent channels. 0: Short address mode 1: Full address mode

14 FAE0 0 R/W Full Address Enable 0

Specifies whether channel 0 is to be used in short address mode or full address mode. In short address mode, channels 0A and 0B can be used as independent channels. 0: Short address mode 1: Full address mode

13 SAE1 0 R/W Single Address Enable 1

Specifies whether channel 1B is to be used for transfer in dual address mode or single address mode. This bit is invalid in full address mode. 0: Dual address mode 1: Single address mode

12 SAE0 0 R/W Single Address Enable 0

Specifies whether channel 0B is to be used for transfer in dual address mode or single address mode. This bit is invalid in full address mode. 0: Dual address mode 1: Single address mode

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 324 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description DTA1B DTA1A DTA0B DTA0A R/W R/W R/W R/W Data Transfer Acknowledge 1B Data Transfer Acknowledge 1A Data Transfer Acknowledge 0B Data Transfer Acknowledge 0A These bits enable or disable clearing when DMA transfer is performed for the internal interrupt source selected by the DTF3 to DTF0 bits in DMACR. If the DTA bit is set to 1 when DTE = 1, the internal interrupt source is cleared automatically by DMA transfer. When DTE = 1 and DTA = 1, the internal interrupt source does not issue an interrupt request to the CPU or DTC. If the DTA bit is cleared to 0 when DTE = 1, the internal interrupt source is not cleared when a transfer is performed, and can issue an interrupt request to the CPU or DTC in parallel. In this case, the interrupt source should be cleared by the CPU or DTC transfer. When DTE = 0, the internal interrupt source issues an interrupt request to the CPU or DTC regardless of the DTA bit setting.

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 325 of 1270 REJ09B0466-0100

  • DMABCRL Bit Bit Name Initial Value R/W Description DTE1B DTE1A DTE0B DTE0A R/W R/W R/W R/W Data Transfer Enable 1B Data Transfer Enable 1A Data Transfer Enable 0B Data Transfer Enable 0A If the DTE bit is cleared to 0 when DTIE = 1, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. When DTE = 0, data transfer is disabled and the DMAC ignores the activation source selected by the DTF3 to DTF0 bits in DMACR. When DTE = 1, data transfer is enabled and the DMAC waits for a request by the activation source selected by the DTF3 to DTF0 bits in DMACR. When a request is issued by the activation source, DMA transfer is executed. [Clearing conditions]
  • When initialization is performed
  • When the specified number of transfers have been completed in a transfer mode other than repeat mode
  • When 0 is written to the DTE bit to forcibly suspend the transfer, or for a similar reason [Setting condition] When 1 is written to the DTE bit after reading DTE = 0

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 326 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description DTIE1B DTIE1A DTIE0B DTIE0A R/W R/W R/W R/W Data Transfer End Interrupt Enable 1B Data Transfer End Interrupt Enable 1A Data Transfer End Interrupt Enable 0B Data Transfer End Interrupt Enable 0A These bits enable or disable an interrupt to the CPU or DTC when transfer ends. If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. A transfer end interrupt can be canceled either by clearing the DTIE bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the transfer counter and address register again, and then setting the DTE bit to 1. (2) Full Address Mode:

  • DMABCRH Bit Bit Name Initial Value R/W Description

Specifies whether channel 1 is to be used in short address mode or full address mode. In full address mode, channels 1A and 1B are used together as channel 1. 0: Short address mode 1: Full address mode Specifies whether channel 0 is to be used in short address mode or full address mode. In full address mode, channels 0A and 0B are used together as channel 0. 0: Short address mode 1: Full address mode

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 327 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description 13, 12 — All 0 R/W Reserved These bits can be read from or written to. However, the write value should always be 0.

11 DTA1 0 R/W Data Transfer Acknowledge 1

These bits enable or disable clearing when DMA transfer is performed for the internal interrupt source selected by the DTF3 to DTF0 bits in DMACR of channel 1. It the DTA1 bit is set to 1 when DTE1 = 1, the internal interrupt source is cleared automatically by DMA transfer. When DTE1 = 1 and DTA1 = 1, the internal interrupt source does not issue an interrupt request to the CPU or DTC. It the DTA1 bit is cleared to 0 when DTE1 = 1, the internal interrupt source is not cleared when a transfer is performed, and can issue an interrupt request to the CPU or DTC in parallel. In this case, the interrupt source should be cleared by the CPU or DTC transfer. When DTE1 = 0, the internal interrupt source issues an interrupt request to the CPU or DTC regardless of the DTA1 bit setting. The state of the DTME1 bit does not affect the above operations. 10 — 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0.

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 328 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description

9 DTA0 0 R/W Data Transfer Acknowledge 0

These bits enable or disable clearing when DMA transfer is performed for the internal interrupt source selected by the DTF3 to DTF0 bits in DMACR of channel 0. It the DTA0 bit is set to 1 when DTE0 = 1, the internal interrupt source is cleared automatically by DMA transfer. When DTE0 = 1 and DTA0 = 1, the internal interrupt source does not issue an interrupt request to the CPU or DTC. It the DTA0 bit is cleared to 0 when DTE0 = 1, the internal interrupt source is not cleared when a transfer is performed, and can issue an interrupt request to the CPU or DTC in parallel. In this case, the interrupt source should be cleared by the CPU or DTC transfer. When DTE0 = 0, the internal interrupt source issues an interrupt request to the CPU or DTC regardless of the DTA0 bit setting. The state of the DTME0 bit does not affect the above operations. 8 — 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0.

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 329 of 1270 REJ09B0466-0100

  • DMABCRL Bit Bit Name Initial Value R/W Description

7 DTME1 0 R/W Data Transfer Master Enable 1

Together with the DTE1 bit, this bit controls enabling or disabling of data transfer on channel 1. When both the DTME1 bit and DTE1 bit are set to 1, transfer is enabled for channel 1. If channel 1 is in the middle of a burst mode transfer when an NMI interrupt is generated, the DTME1 bit is cleared, the transfer is interrupted, and bus mastership passes to the CPU. When the DTME1 bit is subsequently set to 1 again, the interrupted transfer is resumed. In block transfer mode, however, the DTME1 bit is not cleared by an NMI interrupt, and transfer is not interrupted. [Clearing conditions]

  • When initialization is performed
  • When NMI is input in burst mode
  • When 0 is written to the DTME1 bit [Setting condition] When 1 is written to DTME1 after reading DTME1 = 0

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 330 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description

6 DTE1 0 R/W Data Transfer Enable 1

Enables or disables DMA transfer for the activation source selected by the DTF3 to DTF0 bits in DMACR of channel 1. When DTE1 = 0, data transfer is disabled and the activation source is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC. If the DTE1 bit is cleared to 0 when DTIE1 = 1, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU. When DTE1 = 1 and DTME1 = 1, data transfer is enabled and the DMAC waits for a request by the activation source. When a request is issued by the activation source, DMA transfer is executed. [Clearing conditions]

  • When initialization is performed
  • When the specified number of transfers have been completed
  • When 0 is written to the DTE1 bit to forcibly suspend the transfer, or for a similar reason [Setting condition] When 1 is written to the DTE1 bit after reading DTE1 = 0

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 331 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description

5 DTME0 0 R/W Data Transfer Master Enable 0

Together with the DTE0 bit, this bit controls enabling or disabling of data transfer on channel 0. When both the DTME0 bit and DTE0 bit are set to 1, transfer is enabled for channel 0. If channel 0 is in the middle of a burst mode transfer when an NMI interrupt is generated, the DTME0 bit is cleared, the transfer is interrupted, and bus mastership passes to the CPU. When the DTME0 bit is subsequently set to 1 again, the interrupted transfer is resumed. In block transfer mode, however, the DTME0 bit is not cleared by an NMI interrupt, and transfer is not interrupted. [Clearing conditions]

  • When initialization is performed
  • When NMI is input in burst mode
  • When 0 is written to the DTME0 bit [Setting condition] When 1 is written to DTME0 after reading DTME0 = 0

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 332 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description

4 DTE0 0 R/W Data Transfer Enable 0

Enables or disables DMA transfer for the activation source selected by the DTF3 to DTF0 bits in DMACR of channel 0. When DTE0 = 0, data transfer is disabled and the activation source is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC. If the DTE0 bit is cleared to 0 when DTIE0 = 1, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU. When DTE0 = 1 and DTME0 = 1, data transfer is enabled and the DMAC waits for a request by the activation source. When a request is issued by the activation source, DMA transfer is executed. [Clearing conditions]

  • When initialization is performed
  • When the specified number of transfers have been completed
  • When 0 is written to the DTE0 bit to forcibly suspend the transfer, or for a similar reason [Setting condition] When 1 is written to the DTE0 bit after reading DTE0 = 0

3 DTIE1B 0 R/W Data Transfer Interrupt Enable 1B

Enables or disables an interrupt to the CPU or DTC when transfer on channel 1 is interrupted. If the DTME1 bit is cleared to 0 when DTIE1B = 1, the DMAC regards this as indicating a break in the transfer, and issues a transfer break interrupt request to the CPU or DTC. A transfer break interrupt can be canceled either by clearing the DTIE1B bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the DTME1 bit to 1.

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 333 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description

2 DTIE1A 0 R/W Data Transfer End Interrupt Enable 1A

Enables or disables an interrupt to the CPU or DTC when transfer ends. If the DTE1 bit is cleared to 1 when DTIE1A = 1, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. A transfer end interrupt can be canceled either by clearing the DTIE1A bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the transfer counter and address register again, and then setting the DTE1 bit to 1.

1 DTIE0B 0 R/W Data Transfer Interrupt Enable 0B

Enables or disables an interrupt to the CPU or DTC when transfer on channel 1 is interrupted. If the DTME0 bit is cleared to 0 when DTIE0B = 1, the DMAC regards this as indicating a break in the transfer, and issues a transfer break interrupt request to the CPU or DTC. A transfer break interrupt can be canceled either by clearing the DTIE0B bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the DTME0 bit to 1.

0 DTIE0A 0 R/W Data Transfer End Interrupt Enable 0A

Enables or disables an interrupt to the CPU or DTC when transfer ends. If the DTE0 bit is cleared to 0 when DTIE0A = 1, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. A transfer end interrupt can be canceled either by clearing the DTIE0A bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the transfer counter and address register again, and then setting the DTE0 bit to 1.

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 334 of 1270 REJ09B0466-0100

7.3.6 DMA Write Enable Register (DMAWER)

The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the transfer ended using a DTC chain transfer, and then reactivate the DTC. DMAWER applies restrictions for changing all bits of DMACR, and specific bits for DMATCR and DMABCR for the specific channel, to prevent inadvertent rewriting of registers other than those for the channel concerned. The restrictions applied by DMAWER are valid for the DTC. Bit Bit Name Initial Value R/W Description 7 to 4  All 0 — Reserved These bits are always read as 0 and cannot be modified.

3 WE1B 0 R/W Write Enable 1B

Enables or disables writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR. 0: Writes are disabled 1: Writes are enabled

2 WE1A 0 R/W Write Enable 1A

Enables or disables writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR. 0: Writes are disabled 1: Writes are enabled

1 WE0B 0 R/W Write Enable 0B

Enables or disables writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR. 0: Writes are disabled 1: Writes are enabled

0 WE0A 0 R/W Write Enable 0A

Enables or disables writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR. 0: Writes are disabled 1: Writes are enabled

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 336 of 1270 REJ09B0466-0100 MAR, IOAR, and ETCR can always be written to regardless of the DMAWER settings. When modifying these registers, the channel to be modified should be halted.

7.3.7 DMA Terminal Control Register (DMATCR)

DMATCR controls enabling or disabling of output from the DMAC transfer end pin. A port can be set for output automatically, and a transfer end signal output, by setting the appropriate bit. The TEND pin is available only for channel B in short address mode. Except for the block transfer mode, a transfer end signal asserts in the transfer cycle in which the transfer counter contents reaches 0 regardless of the activation source. In the block transfer mode, a transfer end signal asserts in the transfer cycle in which the block counter contents reaches 0. Bit Bit Name Initial Value R/W Description 7, 6  All 0  Reserved These bits are always read as 0 and cannot be modified.

5 TEE1 0 R/W Transfer End Enable 1

Enables or disables transfer end pin 1 (TEND1) output. 0: TEND1 pin output disabled 1: TEND1 pin output enabled

4 TEE0 0 R/W Transfer End Enable 0

Enables or disables transfer end pin 0 (TEND0) output. 0: TEND0 pin output disabled 1: TEND0 pin output enabled 3 to 0  All 0  Reserved These bits are always read as 0 and cannot be modified.

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 337 of 1270 REJ09B0466-0100

7.4 Activation Sources

DMAC activation sources consist of internal interrupt requests, external requests, and auto- requests. The DMAC activation sources that can be specified depend on the transfer mode and channel, as shown in table 7.3. Table 7.3 DMAC Activation Sources Short Address Mode Full Address Mode Activation Source Channels 0A and 1A Channels 0B and Normal Mode Block Transfer Mode ADI0 × TXI0 × RXI0 × TXI1 × RXI1 × TGI0A × TGI1A × TGI2A × TGI3A × TGI4A × Internal interrupts TGI5A × DREQ pin falling edge input × External requests DREQ pin low-level input × Auto-request × × × Legend: : Can be specified ×: Cannot be specified

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 338 of 1270 REJ09B0466-0100

7.4.1 Activation by Internal Interrupt Request

An interrupt request selected as a DMAC activation source can also simultaneously generate an interrupt request for the CPU or DTC. For details, see section 5, Interrupt Controller. With activation by an internal interrupt request, the DMAC accepts the interrupt request independently of the interrupt controller. Consequently, interrupt controller priority settings are irrelevant. If the DMAC is activated by a CPU interrupt source or an interrupt request that is not used as a DTC activation source (DTA = 1), the interrupt request flag is cleared automatically by the DMA transfer. With ADI, TXI, and RXI interrupts, however, the interrupt source flag is not cleared unless the relevant register is accessed in a DMA transfer. If the same interrupt is used as an activation source for more than one channel, the interrupt request flag is cleared when the highest- priority channel is activated. Transfer requests for other channels are held pending in the DMAC, and activation is carried out in order of priority. When DTE = 0 after completion of a transfer, an interrupt request from the selected activation source is not sent to the DMAC, regardless of the DTA bit setting. In this case, the relevant interrupt request is sent to the CPU or DTC. When an interrupt request signal for DMAC activation is also used for an interrupt request to the CPU or DTC activation (DTA = 0), the interrupt request flag is not cleared by the DMAC.

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 339 of 1270 REJ09B0466-0100 Activation by External Request If an external request (DREQ pin) is specified as a DMAC activation source, the relevant port should be set to input mode in advance*. Level sensing or edge sensing can be used for external requests. External request operation in normal mode of short address mode or full address mode is described below. When edge sensing is selected, a byte or word is transferred each time a high-to-low transition is detected on the DREQ pin. The next data transfer may not be performed if the next edge is input before data transfer is completed. When level sensing is selected, the DMAC stands by for a transfer request while the DREQ pin is held high. While the DREQ pin is held low, transfers continue in succession, with the bus being released each time a byte or word is transferred. If the DREQ pin goes high in the middle of a transfer, the transfer is interrupted and the DMAC stands by for a transfer request. Note: * If the relevant port is set as an output pin for another function, DMA transfers using the channel in question cannot be guaranteed.

7.4.2 Activation by Auto-Request

Auto-request is activated by register setting only, and transfer continues to the end. With auto- request activation, cycle steal mode or burst mode can be selected. In cycle steal mode, the DMAC releases the bus to another bus master each time a byte or word is transferred. DMA and CPU cycles are usually repeated alternately. In burst mode, the DMAC keeps possession of the bus until the end of the transfer so that transfer is performed continuously.

7.5 Operation

7.5.1 Transfer Modes

Table 7.4 lists the DMAC transfer modes.

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 340 of 1270 REJ09B0466-0100 Table 7.4 DMAC Transfer Modes Transfer Mode Transfer Source Remarks Short address mode Dual address mode  1-byte or 1-word transfer for a single transfer request  Specify source and destination addresses to transfer data in two bus cycles. (1) Sequential mode  Memory address incremented or decremented by 1 or 2  Number of transfers: 1 to 65,536 (2) Idle mode  Memory address fixed  Number of transfers: 1 to 65,536 (3) Repeat mode  Memory address incremented or decremented by 1 or 2  Continues transfer after sending number of transfers (1 to 256) and restoring the initial value  TPU channel 0 to 5 compare match/input capture A interrupt  SCI transmission complete interrupt  SCI reception complete interrupt  A/D converter conversion end interrupt  External request Single address mode  1-byte or 1-word transfer for a single transfer request  1-bus cycle transfer by means of DACK pin instead of using address for specifying I/O  Sequential mode, idle mode, or repeat mode can be specified  External request  Up to 4 channels can operate independently  External request applies to channel B only  Single address mode applies to channel B only

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 341 of 1270 REJ09B0466-0100 Transfer Mode Transfer Source Remarks Normal mode (1) Auto-request  Transfer request is internally held  Number of transfers (1 to 65,536) is continuously sent  Burst/cycle steal transfer can be selected  Auto-request Full address mode (2) External request  1-byte or 1-word transfer for a single transfer request  Number of transfers: 1 to 65,536  External request  Max. 2-channel operation, combining channels A and B Block transfer mode  Transfer of 1-block, size selected for a single transfer request  Number of transfers: 1 to 65,536  Source or destination can be selected as block area  Block size: 1 to 256 bytes or word  TPU channel 0 to 5 compare match/input capture A interrupt  SCI transmission complete interrupt  SCI reception complete interrupt  A/D converter conversion end interrupt  External request

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7.5.2 Sequential Mode

Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.5 summarizes register functions in sequential mode. Table 7.5 Register Functions in Sequential Mode Function Register DTDIR = 0 DTDIR = 1 Initial Setting Operation 23 0 MAR Source address register Destination address register Start address of transfer destination or transfer source Incremented/ decremented every transfer 23 15 0 IOARH'FF Destination address register Source address register Start address of transfer source or transfer destination Fixed 015 ETCR Transfer counter Number of transfers Decremented every transfer; transfer ends when count reaches H'0000 MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF.

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7.5.3 Idle Mode

Idle mode can be specified by setting the RPE bit in DMACR and DTIE bit in DMABCRL to 1. In idle mode, one byte or word is transferred in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.6 summarizes register functions in idle mode. Table 7.6 Register Functions in Idle Mode Function Register DTDIR = 0 DTDIR = 1 Initial Setting Operation 23 0 MAR Source address register Destination address register Start address of transfer destination or transfer source Fixed 23 15 0 IOARH'FF Destination address register Source address register Start address of transfer source or transfer destination Fixed 015 ETCR Transfer counter Number of transfers Decremented every transfer; transfer ends when count reaches H'0000 MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is neither incremented nor decremented by a data transfer. IOAR specifies the lower 16 bits of the other address. The upper 8 bits of IOAR have a value of H'FF.

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7.5.4 Repeat Mode

Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit in DMABCRL to 0. In repeat mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCRL. On completion of the specified number of transfers, MAR and ETCRL are automatically restored to their original settings and operation continues. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.7 summarizes register functions in repeat mode. Table 7.7 Register Functions in Repeat Mode Function Register DTDIR = 0 DTDIR = 1 Initial Setting Operation 23 0 MAR Source address register Destination address register Start address of transfer destination or transfer source Incremented/ decremented every transfer. Initial setting is restored when the value reaches H'0000 23 15 0 IOARH'FF Destination address register Source address register Start address of transfer source or transfer destination Fixed ETCRAH Holds number of transfers Number of transfers Fixed ETCRAL Transfer counter Number of transfers Decremented every transfer. Loaded with ETCRH value when the value reaches H'00

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 349 of 1270 REJ09B0466-0100 MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The upper 8 bits of IOAR have a value of H'FF. The number of transfers is specified as 8 bits by ETCRH and ETCRL. The maximum number of transfers, when H'00 is set in both ETCRH and ETCRL, is 256. In repeat mode, ETCRL functions as the transfer counter, and ETCRH is used to hold the number of transfers. ETCRL is decremented by 1 each time a data transfer is executed, and when its value reaches H'00, it is loaded with the value in ETCRH. At the same time, the value set in MAR is restored in accordance with the values of the DTSZ and DTID bits in DMACR. The MAR restoration operation is as shown below. MAR = MAR – (–1) DTID

  • 2 DTSZ
  • ETCRH The same value should be set in ETCRH and ETCRL. In repeat mode, operation continues until the DTE bit in DMABCRL is cleared. To end the transfer operation, therefore, the DTE bit should be cleared to 0. A transfer end interrupt request is not sent to the CPU or DTC. By setting the DTE bit to 1 again after it has been cleared, the operation can be restarted from the transfer after that terminated when the DTE bit was cleared.

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7.5.5 Single Address Mode

Single address mode can only be specified for channel B. This mode can be specified by setting the SAE bit in DMABCRH to 1 in short address mode. One address is specified by MAR, and the other is set automatically to the data transfer acknowledge pin (DACK). The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.8 summarizes register functions in single address mode. Table 7.8 Register Functions in Single Address Mode Function Register DTDIR = 0 DTDIR = 1 Initial Setting Operation 23 0 MAR Source address register Destination address register Start address of transfer destination or transfer source See sections 7.5.2, Sequential Mode, 7.5.3, Idle Mode, and 7.5.4, Repeat Mode. DACK pin Write strobe Read strobe (Set automatically by SAE bit in DMABCRH; IOAR is invalid) Strobe for external device 015 ETCR Transfer counter Number of tr ansfers See sections 7.5.2, Sequential Mode, 7.5.3, Idle Mode, and 7.5.4, Repeat Mode. MAR specifies the start address of the transfer source or transfer destination as 24 bits. IOAR is invalid; in its place the strobe for external devices (DACK) is output.

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7.5.6 Normal Mode

In normal mode, transfer is performed with channels A and B used in combination. Normal mode can be specified by setting the FAE bit in DMABCRH to 1 and clearing the BLKE bit in DMACRA to 0. In normal mode, MAR is updated after data transfer of a byte or word in response to a single transfer request, and this is executed the number of times specified in ETCRA. The transfer source is specified by MARA, and the transfer destination by MARB. Table 7.9 summarizes register functions in normal mode. Table 7.9 Register Functions in Normal Mode Register Function Initial Setting Operation 23 0 MARA Source address register Start address of transfer source Incremented/decremented every transfer, or fixed 23 0 MARB Destination address register Start address of transfer destination Incremented/decremented every transfer, or fixed 15 0 ETCRA Transfer counter Number of transfers Decremented every transfer; transfer ends when count reaches H'0000 MARA and MARB specify the start addresses of the transfer source and transfer destination, respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be set separately for MARA and MARB. The number of transfers is specified by ETCRA as 16 bits. ETCRA is decremented by 1 each time a transfer is performed, and when its value reaches H'0000 the DTE bit in DMABCRL is cleared and transfer ends. If the DTIE bit in DMABCRL is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCRA, is 65,536.

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 357 of 1270 REJ09B0466-0100 Transfer requests (activation sources) are external requests and auto-requests. With auto-requests, the DMAC is only activated by register setting, and the specified number of transfers are performed automatically. With auto-requests, cycle steal mode or burst mode can be selected. In cycle steal mode, the bus is released to another bus master each time a transfer is performed. In burst mode, the bus is held continuously until transfer ends.

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7.5.7 Block Transfer Mode

In block transfer mode, data transfer is performed with channels A and B used in combination. Block transfer mode can be specified by setting the FAE bit in DMABCRH and the BLKE bit in DMACRA to 1. In block transfer mode, a data transfer of the specified block size is carried out in response to a single transfer request, and this is executed for the number of times specified in ETCRB. The transfer source is specified by MARA, and the transfer destination by MARB. Either the transfer source or the transfer destination can be selected as a block area (an area composed of a number of bytes or words). Table 7.10 summarizes register functions in block transfer mode. Table 7.10 Register Functions in Block Transfer Mode Register Function Initial Setting Operation 23 0 MARA Source address register Start address of transfer source Incremented/decremented every transfer, or fixed 23 0 MARB Destination address register Start address of transfer destination Incremented/decremented every transfer, or fixed ETCRAH ETCRAL Holds block size Block size counter Block size Block size Fixed Decremented every transfer; ETCRAH value copied when count reaches H'00 015 ETCRB Block transfer counter Number of block transfers Decremented every block transfer; transfer ends when count reaches H'0000 MARA and MARB specify the start addresses of the transfer source and transfer destination, respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be set separately for MARA and MARB. Whether a block is to be designated for MARA or for MARB is specified by the BLKDIR bit in DMACRA. To specify the number of transfers, if M is the size of one block (where M = 1 to 256) and N transfers are to be performed (where N = 1 to 65,536), M is set in both ETCRAH and ETCRAL, and N in ETCRB.

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 362 of 1270 REJ09B0466-0100 ETCRAL is decremented by 1 each time a byte or word transfer is performed. In response to a single transfer request, burst transfer is performed until the value in ETCRAL reaches H'00. ETCRAL is then loaded with the value in ETCRAH. At this time, the value in the MAR register for which a block designation has been given by the BLKDIR bit in DMACRA is restored in accordance with the DTSZ, SAID/DAID, and SAIDE/DA IDE bits in DMACR. ETCRB is decremented by 1 after every block transfer, and when the count reaches H'0000 the DTE bit in DMABCRL is cleared and transfer ends. If the DTIE bit in DMABCRL is set to 1 at this point, an interrupt request is sent to the CPU or DTC.

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7.5.8 Basic Bus Cycles

An example of the basic DMAC bus cycle timing is shown in figure 7.17. In this example, word- size transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the bus is transferred from the CPU to the DMAC, a source address read and destination address write are performed. The bus is not released in response to another bus request, etc., between these read and write operations. As like CPU cycles, DMA cycles conform to the bus controller settings. The address is not output to the external address bus in an access to on-chip memory or an internal I/O register. Address bus φ DMAC cycle (1-word transfer) RD LWR HWR Source address Destination address CPU cycle CPU cycle T1 T2 T3T1 T2 T3T1 T2 Figure 7.17 Example of DMA Transfer Bus Timing

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7.5.9 DMA Transfer (Dual Address Mode) Bus Cycles

(1) Short Address Mode Figure 7.18 shows a transfer example in which TEND output is enabled and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external 8-bit, 2-state access space to internal I/O space. DMA read Address bus φ RD LWR TEND HWR Bus release Last transfer cycle DMA write DMA dead DMA read DMA write DMA read DMA write Bus release Bus release Bus release Figure 7.18 Example of Short Address Mode Transfer A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is released. While the bus is released, one or more bus cycles are executed by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. In repeat mode, when TEND output is enabled, TEND output goes low in the transfer end cycle.

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 371 of 1270 REJ09B0466-0100 DMA read Address bus φ DREQ Idle Write Bus release DMA control Channel Write Transfer source Request Acceptance resumes DMA dead 1 block transfer IdleDead Dead DMA write Bus release DMA read DMA write DMA dead Bus release Transfer source Request Acceptance resumes 1 block transfer Transfer destinationTransfer destination ReadIdleRead Minimum of 2 cycles Minimum of 2 cycles Request clear periodRequest clear period [1] Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts. [4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the dead cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.) Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7.23 Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin high level sampling has been completed by the time the DMA dead cycle ends, acceptance resumes after the end of the dead cycle, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends.

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7.5.10 DMA Transfer (Single Address Mode) Bus Cycles

(1) Single Address Mode (Read) Figure 7.26 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. DMA read Address bus φ DMA dead RD DACK TEND Bus release DMA read DMA read DMA read Bus release Bus release Bus release Bus release Last transfer cycle Figure 7.26 Example of Single Address Mode Transfer (Byte Read) Figure 7.27 shows a transfer example in which TEND output is enabled and word-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device.

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 375 of 1270 REJ09B0466-0100 DMA read Address bus φ DMA read DMA read DMA dead RD TEND DACK Bus release Bus release Bus release Bus release Last transfer cycle Figure 7.27 Example of Single Address Mode (Word Read) Transfer A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is released. While the bus is released, one or more bus cycles are executed by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle.

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 378 of 1270 REJ09B0466-0100 DREQ Bus release DMA single DMA single Address bus φ DMA control Channel [2] DACK Transfer source/ destination Idle Idle Idle Acceptance resumesAcceptance resumes Bus release Bus release Transfer source/ destination Request Request Request clear period Request clear period Minimum of 2 cycles Minimum of 2 cycles SingleSingle [1] Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts. [4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the single cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.) Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7.30 Example of DREQ Pin Falling Edge Activated Single Address Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin high level sampling has been completed by the time the DMA single cycle ends, acceptance resumes after the end of the single cycle, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends.

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 380 of 1270 REJ09B0466-0100 When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared. After the end of the single cycle, acceptance resumes, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends.

7.5.11 Write Data Buffer Function

DMAC internal-to-external dual address transfers and single address transfers can be executed at high speed using the write data buffer function, enabling system throughput to be improved. When the WDBE bit of BCR in the bus controller is set to 1, enabling the write data buffer function, dual address transfer external write cycles or single address transfer and internal accesses (on-chip memory or internal I/O registers) are executed in parallel. Internal accesses are independent of the bus mastership, and DMAC dead cycles are regarded as internal accesses. A low level can always be output from the TEND pin if the bus cycle in which a low level is to be output from the TEND pin is an external bus cycle. However, a low level is not output from the TEND pin if the bus cycle in which a low level is to be output from the TEND pin is an internal bus cycle, and an external write cycle is executed in parallel with this cycle. Figure 7.32 shows an example of dual address transfer using the write data buffer function. The data is transferred from on-chip RAM to external memory. Internal address φ Internal read signal HWR, LWR TEND External address DMA read DMA write DMA read DMA write DMA read DMA write DMA read DMA write DMA dead Figure 7.32 Example of Dual Address Transfer Using Write Data Buffer Function

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 381 of 1270 REJ09B0466-0100 Figure 7.33 shows an example of single address transfer using the write data buffer function. In this example, the CPU program area is in on-chip memory. Internal address φ Internal read signal RD DACK External address DMA read DMA single CPU read DMA single CPU read Figure 7.33 Example of Single Address Transfer Using Write Data Buffer Function When the write data buffer function is activated, the DMAC recognizes that the bus cycle concerned has ended, and starts the next operation. Therefore, DREQ pin sampling is started one state after the start of the DMA write cycle or single address transfer.

7.5.12 Multi-Channel Operation

The DMAC channel priority order is: channel 0 > channel 1, and channel A > channel B. Table 7.11 summarizes the priority order for DMAC channels. Table 7.11 DMAC Chan nel Priority Order Short Address Mode Full Address Mode Priority Channel 0A Channel 0 High Channel 0B Channel 1A Channel 1 Channel 1B Low

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 382 of 1270 REJ09B0466-0100 If transfer requests are issued simultaneously for more than one channel, or if a transfer request for another channel is issued during a transfer, when the bus is released, the DMAC selects the highest-priority channel from among those issuing a request according to the priority order shown in table 7.11. During burst transfer, or when one block is being transferred in block transfer, the channel will not be changed until the end of the transfer. Figure 7.34 shows a transfer example in which transfer requests are issued simultaneously for channels 0A, 0B, and 1. DMA read DMA write DMA read DMA write DMA read DMA write DMA read Address bus φ RD HWR LWR DMA control Channel 0A Channel 0B Channel 1 Idle Write Idle Read Write Idle Read Write Read Request hold Request hold Bus release Channel 0A transfer Bus release Channel 0B transfer Channel 1 transferBus release Request hold Read Selection Non- selection Selection Request clear Request clear Request clear Figure 7.34 Example of Multi-Channel Transfer

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7.5.13 Relation between DMAC and Ext ernal Bus Requests, Refresh Cycles,

When the DMAC accesses external space, contention with a refresh cycle, EXDMAC cycle, or external bus release cycle may arise. In this case, the bus controller will suspend the transfer and insert a refresh cycle, EXDMAC cycle, or external bus release cycle, in accordance with the external bus priority order, even if the DMAC is executing a burst transfer or block transfer. (An external access by the DTC or CPU, which has a lower priority than the DMAC, is not executed until the DMAC releases the external bus.) When the DMAC transfer mode is dual address mode, the DMAC releases the external bus after an external write cycle. The external read cycle and external write cycle are inseparable, and so the bus cannot be released between these two cycles. When the DMAC accesses internal space (on-chip memory or an internal I/O register), the DMAC cycle may be executed at the same time as a refresh cycle, EXDMAC cycle, or external bus release cycle.

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7.5.14 DMAC and NMI Interrupts

When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted. An NMI interrupt does not affect the operation of the DMAC in other modes. In full address mode, transfer is enabled for a channel when both the DTE bit and DTME bit in DMABCRLare set to 1. With burst mode setting, the DTME bit is cleared when an NMI interrupt is requested. If the DTME bit is cleared during burst mode transfer, the DMAC discontinues transfer on completion of the 1-byte or 1-word transfer in progress, then releases the bus, which passes to the CPU. The channel on which transfer was interrupted can be restarted by setting the DTME bit to 1 again. Figure 7.35 shows the procedure for continuing transfer when it has been interrupted by an NMI interrupt on a channel designated for burst mode transfer. Resumption of transfer on interrupted channel Set DTME bit to 1 Transfer continues [1] [2] DTE bit = 1 DTME bit = 0 Transfer ends No Yes [1] [2] Check that DTE = 1 and DTME = 0 in DMABCRL. Write 1 to the DTME bit. Figure 7.35 Example of Procedure for Continuing Transfer on Channel Interrupted by NMI Interrupt

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7.5.15 Forced Termination of DMAC Operation

If the DTE bit in DMABCRL is cleared to 0 for the channel currently operating, the DMAC stops on completion of the 1-byte or 1-word transfer in progress. DMAC operation resumes when the DTE bit is set to 1 again. In full address mode, the same applies to the DTME bit in DMABCRL. Figure 7.36 shows the procedure for forcibly terminating DMAC operation by software. Forced termination of DMAC Clear DTE bit to 0 Forced termination [1] [1] Clear the DTE bit in DMABCRL to 0. To prevent interrupt generation after forced termination of DMAC operation, clear the DTIE bit to 0 at the same time. Figure 7.36 Example of Procedure for Forcibly Terminating DMAC Operation

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7.5.16 Clearing Full Address Mode

Figure 7.37 shows the procedure for releasing and initializing a channel designated for full address mode. After full address mode has been cleared, the channel can be set to another transfer mode using the appropriate setting procedure. Clearing full address mode Stop the channel Initialize DMACR Clear FAE bit to 0 Initialization; operation halted [1] [2] [3] [1] Clear both the DTE bit and DTME bit in DMABCRL to 0, or wait until the transfer ends and the DTE bit is cleared to 0, then clear the DTME bit to 0. Also clear the corresponding DTIE bit to 0 at the same time. [2] Clear all bits in DMACRA and DMACRB to 0. [3] Clear the FAE bit in DMABCRH to 0 Figure 7.37 Example of Procedure for Clearing Full Address Mode

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7.6 Interrupt Sources

The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 7.12 shows the interrupt sources and their priority order. Table 7.12 Interrupt Sources and Priority Order Interrupt Source Interrupt Name Short Addr ess Mode Full Address Mode Interrupt Priority Order DMTEND0A Interrupt due to end of transfer on channel 0A Interrupt due to end of transfer on channel 0 High DMTEND0B Interrupt due to end of transfer on channel 0B Interrupt due to break in transfer on channel 0 DMTEND1A Interrupt due to end of transfer on channel 1A Interrupt due to end of transfer on channel 1 DMTEND1B Interrupt due to end of transfer on channel 1B Interrupt due to break in transfer on channel 1 Low Enabling or disabling of each interrupt source is set by means of the DTIE bit in DMABCRL for the corresponding channel in DMABCRL, and interrupts from each source are sent to the interrupt controller independently. The priority of transfer end interrupts on each channel is decided by the interrupt controller, as shown in table 7.12. Figure 7.38 shows a block diagram of a transfer end/transfer break interrupt. An interrupt is always generated when the DTIE bit is set to 1 while the DTE bit in DMABCRL is cleared to 0. DTE/ DTME DTIE Transfer end/transfer break interrupt Figure 7.38 Block Diagram of Transfer End/Transfer Break Interrupt In full address mode, a transfer break interrupt is generated when the DTME bit is cleared to 0 while the DTIE bit is set to 1. In both short address mode and full address mode, DMABCR should be set so as to prevent the occurrence of a combination that constitutes a condition for interrupt generation during setting.

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7.7 Usage Notes

(1) DMAC Register Access during Operation Except for forced termination of the DMAC, the operating (including transfer waiting state) channel setting should not be changed. The operating channel setting should only be changed when transfer is disabled. Also, DMAC registers should not be written to in a DMA transfer. DMAC register reads during operation (including the transfer waiting state) are described below.

  • DMAC control starts one cycle before the bus cycle, with output of the internal address. Consequently, MAR is updated in the bus cycle before DMA transfer. Figure 7.39 shows an example of the update timing for DMAC registers in dual address transfer mode. [1] Transfer source address register MAR operation (incremented/decremented/fixed) Transfer counter ETCR operation (decremented) Block size counter ETCR operation (decremented in block transfer mode) [2] Transfer destination address register MAR operation (incremented/decremented/fixed) [2']Transfer destination address register MAR operation (incremented/decremented/fixed) Block transfer counter ETCR operation (decremented, in last transfer cycle of a block in block transfer mode) [3] Transfer address register MAR restore operation (in block or repeat transfer mode) Transfer counter ETCR restore (in repeat transfer mode) Block size counter ETCR restore (in block transfer mode) Note: In single address transfer mode, the update timing is the same as [1]. The MAR operation is post-incrementing/decrementing of the DMA internal address value. DMA transfer cycle DMA read DMA readDMA write DMA write DMA dead DMA Internal address φ DMA control DMA register operation DMA last transfer cycle Transfer destination Transfer destinationTransfer source Transfer source Idle Idle IdleRead Read DeadWrite Write [3][2'][2] [1][1] Figure 7.39 DMAC Register Update Timing

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  • If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC register is read as shown in figure 7.40. [2][1] Note: The lower word of MAR is the updated value after the operation in [1]. CPU longword read DMA transfer cycle MAR upper word read MAR lower word read DMA read DMA write DMA internal address φ DMA control DMA register operation Transfe source Transfer destination Idle Read Write Idle Figure 7.40 Contention between DMAC Register Update and CPU Read (2) Module Stop When the MSTP13 bit in MSTPCRH is set to 1, the DMAC clock stops, and the module stop state is entered. However, 1 cannot be written to the MSTP13 bit if any of the DMAC channels is enabled. This setting should therefore be made when DMAC operation is stopped. When the DMAC clock stops, DMAC register accesses can no longer be made. Since the following DMAC register settings are valid even in the module stop state, they should be invalidated, if necessary, before a module stop.
  • Transfer end/break interrupt (DTE = 0 and DTIE = 1)
  • TEND pin enable (TEE = 1)
  • DACK pin enable (FAE = 0 and SAE = 1)

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 390 of 1270 REJ09B0466-0100 (3) Write Data Buffer Function When the WDBE bit of BCR in the bus controller is set to 1, enabling the write data buffer function, dual address transfer external write cycles or single address transfers and internal accesses (on-chip memory or internal I/O registers) are executed in parallel.

  • Write data buffer function and DMAC register setting If the setting of a register that controls external accesses is changed during execution of an external access by means of the write data buffer function, the external access may not be performed normally. Registers that control external accesses should only be manipulated when external reads, etc., are used with DMAC operation disabled, and the operation is not performed in parallel with external access.
  • Write data buffer function and next DMAC operation The DMAC can start its next operation during external access using the write data buffer function. Consequently, the DREQ pin sampling timing, TEND output timing, etc., are different from the case in which the write data buffer function is disabled. Also, internal bus cycles maybe hidden, and not visible. (4) TEND Output If the last transfer cycle is for an internal address, note that even if low-level output at the TEND pin has been set, a low level may not be output at the TEND pin under the following external bus conditions since the last transfer cycle (internal bus cycle) and the external bus cycle are executed in parallel. 1. EXDMAC cycle 2. Write cycle with write buffer mode enabled 3. DMAC single address cycle for a different channel with write buffer mode enabled 4. Bus release cycle 5. CBR refresh cycle Figure 7.41 shows an example in which a low level is not output from the TEND pin in case 2 above. If the last transfer cycle is an external address cycle, a low level is output at the TEND pin in synchronization with the bus cycle. However, if the last transfer cycle and a CBR refresh occur simultaneously, note that although the CBR refresh and the last transfer cycle may be executed consecutively, TEND may also go low in this case for the refresh cycle.

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 391 of 1270 REJ09B0466-0100 Internal address φ Internal read signal External address HWR, LWR Internal write signal TEND Not output DMA read External write by CPU, etc. DMA write Figure 7.41 Example in which Low Level Is Not Output at TEND Pin (5) Activation by Falling Edge on DREQ Pin DREQ pin falling edge detection is performed in synchronization with DMAC internal operations. The operation is as follows: [1] Activation request wait state: Waits for detection of a low level on the DREQ pin, and switches to [2]. [2] Transfer wait state: Waits for DMAC data transfer to become possible, and switches to [3]. [3] Activation request disabled state: Waits for detection of a high level on the DREQ pin, and switches to [1]. After DMAC transfer is enabled, a transition is made to [1]. Thus, initial activation after transfer is enabled is performed on detection of a low level.

Section 7 DMA Controller (DMAC) Rev. 1.00 Sep. 19, 2008 Page 392 of 1270 REJ09B0466-0100 (6) Activation Source Acceptance At the start of activation source acceptance, a low level is detected in both DREQ pin falling edge sensing and low level sensing. Similarly, in the case of an internal interrupt, the interrupt request is detected. Therefore, a request is accepted from an internal interrupt or DREQ pin low level that occurs before write to DMABCRL to enable transfer. When the DMAC is activated, take any necessary steps to prevent an internal interrupt or DREQ pin low level remaining from the end of the previous transfer, etc. (7) Internal Interrupt after End of Transfer When the DTE bit in DMABCRL is cleared to 0 at the end of a transfer or by a forcible termination, the selected internal interrupt request will be sent to the CPU or DTC even if the DTA bit in DMABCRH is set to 1. Also, if internal DMAC activation has already been initiated when operation is forcibly terminated, the transfer is executed but flag clearing is not performed for the selected internal interrupt even if the DTA bit is set to 1. An internal interrupt request following the end of transfer or a forcible termination should be handled by the CPU as necessary. (8) Channel Re-Setting To reactivate a number of channels when multiple channels are enabled, use exclusive handling of transfer end interrupts, and perform DMABCR control bit operations exclusively. Note, in particular, that in cases where multiple interrupts are generated between reading and writing of DMABCR, and a DMABCR operation is performed during new interrupt handling, the DMABCR write data in the original interrupt handling routine will be incorrect, and the write may invalidate the results of the operations by the multiple interrupts. Ensure that overlapping DMABCR operations are not performed by multiple interrupts, and that there is no separation between read and write operations by the use of a bit-manipulation instruction. Also, when the DTE and DTME bits are cleared by the DMAC or are written with 0, they must first be read while cleared to 0 before the CPU can write 1 to them.

Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 393 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) This LSI has a built-in dual-channel external bus transfer DMA controller (EXDMAC). The EXDMAC can carry out high-speed data transfer, in place of the CPU, to and from external devices and external memory with a DACK (DMA transfer notification) facility. Note: This EXDMAC is not supported by the H8S/2424 Group.

8.1 Features

  • Direct specification of 16-Mbyte address space
  • Selection of byte or word transfer data length
  • Maximum number of transfers: 16M (16,777,215)/infinite (free-running)
  • Selection of dual address mode or single address mode
  • Selection of cycle steal mode or burst mode as bus mode
  • Selection of normal mode or block transfer mode as transfer mode
  • Two kinds of transfer requests: external request and auto-request
  • An interrupt request can be sent to the CPU at the end of the specified number of transfers.
  • Repeat area designation function:
  • Operation in parallel with internal bus master:
  • Acceptance of a transfer request and the start of transfer processing can be reported to an external device via the EDRAK pin.
  • Module stop mode can be set.

Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 395 of 1270 REJ09B0466-0100

8.2 Input/Output Pins

Table 8.1 shows the pin configuration of the EXDMAC. Table 8.1 Pin Configuration Channel Name Abbre- viation I/O Function

2 EXDMA transfer request 2 EDREQ2 Input Channel 2 external request

EDACK2 Output Channel 2 single address transfer acknowledge EXDMA transfer end 2 ETEND2 Output Channel 2 transfer end EDREQ2 acceptance acknowledge EDRAK2 Output Notification to external device of channel 2 external request acceptance and start of transfer processing

3 EXDMA transfer request 3 EDREQ3 Input Channel 3 external request

EDACK3 Output Channel 3 single address transfer acknowledge EXDMA transfer end 3 ETEND3 Output Channel 3 transfer end EDREQ3 acceptance acknowledge EDRAK3 Output Notification to external device of channel 3 external request acceptance and start of transfer processing

Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 396 of 1270 REJ09B0466-0100

8.3 Register Descriptions

The EXDMAC has the following registers.

  • EXDMA source address register_2 (EDSAR_2)
  • EXDMA destination address register_2 (EDDAR_2)
  • EXDMA transfer count register_2 (EDTCR_2)
  • EXDMA mode control register_2 (EDMDR_2)
  • EXDMA address control register_2 (EDACR_2)
  • EXDMA source address register_3 (EDSAR_3)
  • EXDMA destination address register_3 (EDDAR_3)
  • EXDMA transfer count register_3 (EDTCR_3)
  • EXDMA mode control register_3 (EDMDR_3)
  • EXDMA address control register_3 (EDACR_3)

8.3.1 EXDMA Source Add ress Register (EDSAR)

EDSAR is a 32-bit readable/writable register that specifies the transfer source address. An address update function is provided that updates the register contents to the next transfer source address each time transfer processing is performed. In single address mode, the EDSAR value is ignored when a device with DACK is specified as the transfer source. The upper 8 bits of EDSAR are reserved; they are always read as 0 and cannot be modified. Only 0 should be written to these bits. EDSAR can be read at all times by the CPU. When reading EDSAR for a channel on which EXDMA transfer processing is in progress, a longword-size read must be executed. Do not write to EDSAR for a channel on which EXDMA transfer is in progress. The initial values of EDSAR are undefined.

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8.3.2 EXDMA Destination Address Register (EDDAR)

EDDAR is a 32-bit readable/writable register that specifies the transfer destination address. An address update function is provided that updates the register contents to the next transfer destination address each time transfer processing is performed. In single address mode, the EDDAR value is ignored when a device with DACK is specified as the transfer destination. The upper 8 bits of EDDAR are reserved; they are always read as 0 and cannot be modified. Only 0 should be written to these bits. EDDAR can be read at all times by the CPU. When reading EDDAR for a channel on which EXDMA transfer processing is in progress, a longword-size read must be executed. Do not write to EDDAR for a channel on which EXDMA transfer is in progress. The initial values of EDDAR are undefined.

8.3.3 EXDMA Transfer Count Register (EDTCR)

EDTCR specifies the number of transfers. The function differs according to the transfer mode. Do not write to EDTCR for a channel on which EXDMA transfer is in progress. (1) Normal Transfer Mode Bit Bit Name Initial Value R/W Description 31 to 24 — All 0 — Reserved These bits are always read as 0 and cannot be modified. 23 to 0 All 0 R/W 24-Bit Transfer Counter These bits specify the number of transfers. Setting H'000001 specifies one transfer. Setting H'000000 means no specification for the number of transfers, and the transfer counter function is halted. In this case, there is no transfer end interrupt by the transfer counter. Setting H'FFFFFF specifies the maximum number of transfers, that is 16,777,215. During EXDMA transfer, this counter shows the remaining number of transfers. This counter can be read at all times. When reading EDTCR for a channel on which EXDMA transfer processing is in progress, a longword-size read must be executed.

Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 398 of 1270 REJ09B0466-0100 (2) Block Transfer Mode Bit Bit Name Initial Value R/W Description 31 to 24 — All 0 — Reserved These bits are always read as 0 and cannot be modified. 23 to 16 Undefined R/W Block Size These bits specify the block size (number of bytes or number of words) for block transfer. Setting H'01 specifies one as the block, while setting H'00 specifies the maximum block size, that is 256. The register value always indicates the specified block size. 15 to 0 Undefined R/W 16-Bit Transfer Counter These bits specify the number of block transfers. Setting H'0001 specifies one block transfer. Setting H'0000 means no specification for the number of transfers, and the transfer counter function is halted. In this case, there is no transfer end interrupt by the transfer counter. Setting H'FFFF specifies the maximum number of block transfers, that is 65,535. During EXDMA transfer, this counter shows the remaining number of block transfers.

Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 399 of 1270 REJ09B0466-0100

8.3.4 EXDMA Mode Control Register (EDMDR)

EDMDR controls EXDMAC operations. Bit Bit Name Initial Value R/W Description

15 EDA 0 R/(W) EXDMA Active

Enables or disables data transfer on the corresponding channel. When this bit is set to 1, this indicates that an EXDMA operation is in progress. When auto request mode is specified (by bits MDS1 and MDS0), transfer processing begins when this bit is set to 1. With external requests, transfer processing begins when a transfer request is issued after this bit has been set to 1. When this bit is cleared to 0 during an EXDMA operation, transfer is halted. If this bit is cleared to 0 during an EXDMA operation in block transfer mode, transfer processing is continued for the currently executing one-block transfer, and the bit is cleared on completion of the currently executing one-block transfer. If an external source that ends (aborts) transfer occurs, this bit is automatically cleared to 0 and transfer is terminated. Do not change the operating mode, transfer method, or other parameters while this bit is set to 1. 0: Data transfer disabled on corresponding channel [Clearing conditions]

  • When the specified number of transfers end
  • When operation is halted by a repeat area overflow interrupt
  • When 0 is written to EDA while EDA = 1 (In block transfer mode, write is effective after end of one-block transfer)
  • Reset, NMI interrupt, hardware standby mode 1: Data transfer enabled on corresponding channel Note: The value written in the EDA bit may not be effective immediately.

Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 400 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description

14 BEF 0 R/(W) * Block Transfer Error Flag

Flag that indicates the occurrence of an error during block transfer. If an NMI interrupt is generated during block transfer, the EXDMAC immediately terminates the EXDMA operation and sets this bit to 1. The address registers indicate the next transfer addresses, but the data for which transfer has been performed within the block size is lost. 0: No block transfer error [Clearing condition] Writing 0 to BEF after reading BEF = 1 1: Block transfer error [Setting condition] NMI interrupt during block transfer

13 EDRAKE 0 R/W EDRAK Pin Output Enable

Enables output from the EDREQ acknowledge/transfer processing start (EDRAK) pin. 0: EDRAK pin output disabled 1: EDRAK pin output enabled

12 ETENDE 0 R/W ETEND Pin Output Enable

Enables output from the EXDMA transfer end (ETEND) pin. 0: ETEND pin output disabled 1: ETEND pin output enabled

11 EDREQS 0 R/W EDREQ Select

Specifies low level sensing or falling edge sensing as the sampling method for the EDREQ pin used in external request mode. 0: Low level sensing (Low level sensing is used for the first transfer after transfer is enabled.) 1: Falling edge sensing

Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 401 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description

10 AMS 0 R/W Address Mode Select

Selects single address mode or dual address mode. When single address mode is selected, the EDACK pin is valid. 0: Dual address mode 1: Single address mode MDS1 MDS0 R/W R/W Mode Select 1 and 0 These bits specify the activation source, bus mode, and transfer mode. 00: Auto request, cycle steal mode, normal transfer mode 01: Auto request, burst mode, normal transfer mode 10: External request, cycle steal mode, normal transfer mode 11: External request, cycle steal mode, block transfer mode

7 EDIE 0 R/W EXDMA Interrupt Enable

Enables or disables interrupt requests. When this bit is set to 1, an interrupt is requested when the IRF bit is set to 1. The interrupt request is cleared by clearing this bit or the IRF bit to 0. 0: Interrupt request is not generated 1: Interrupt request is generated

Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 402 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description

6 IRF 0 R/(W) * Interrupt Request Flag

Flag indicating that an interrupt request has occurred and transfer has ended. 0: No interrupt request [Clearing conditions]

  • Writing 1 to the EDA bit
  • Writing 0 to IRF after reading IRF = 1 1: Interrupt request occurrence [Setting conditions]
  • Transfer end interrupt request generated by transfer counter
  • Source address repeat area overflow interrupt request
  • Destination address repeat area overflow interrupt request

5 TCEIE 0 R/W Transfer Counter End Interrupt Enable

Enables or disables transfer end interrupt requests by the transfer counter. When transfer ends according to the transfer counter while this bit is set to 1, the IRF bit is set to 1, indicating that an interrupt request has occurred. 0: Transfer end interrupt requests by transfer counter are disabled 1: Transfer end interrupt requests by transfer counter are enabled

4 SDIR 0 R/W Single Address Direction

Specifies the data transfer direction in single address mode. In dual address mode, the specification by this bit is ignored. 0: Transfer direction: EDSAR → external device with DACK 1: Transfer direction: External device with DACK→ EDDAR

Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 403 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description

3 DTSIZE 0 R/W Data Transmit Size

Specifies the size of data to be transferred. 0: Byte-size 1: Word-size

2 BGUP 0 R/W Bus Give-Up

When this bit is set to 1, the bus can be transferred to an internal bus master in burst mode or block transfer mode. This setting is ignored in normal mode and cycle steal mode. 0: Bus is not released 1: Bus is transferred if requested by an internal bus master R/W R/W Reserved These bits are always read as 0. The initial values should not be modified. Note: * Only 0 can be written, to clear the flag.

Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 404 of 1270 REJ09B0466-0100

8.3.5 EXDMA Address Control Register (EDACR)

EDACR specifies address register incrementing/decrementing and use of the repeat area function. Bit Bit Name Initial Value R/W Description SAT1 SAT0 R/W R/W Source Address Update Mode These bits specify incrementing/decrementing of the transfer source address (EDSAR). When an external device with DACK is designated as the transfer source in single address mode, the specification by these bits is ignored. 0×: Fixed 10: Incremented (+1 in byte transfer, +2 in word transfer) 11: Decremented (–1 in byte transfer, –2 in word transfer)

13 SARIE 0 R/W Source Address Repeat Interrupt Enable

When this bit is set to 1, in the event of source address repeat area overflow, the IRF bit is set to 1 and the EDA bit cleared to 0 in EDMDR, and transfer is terminated. If the EDIE bit in EDMDR is 1 when the IRF bit in EDMDR is set to 1, an interrupt request is sent to the CPU. When used together with block transfer mode, a source address repeat interrupt is requested at the end of a block-size transfer. If the EDA bit is set to 1 in EDMDR for the channel on which transfer is terminated by a source address repeat interrupt, transfer can be resumed from the state in which it ended. If a source address repeat area has not been designated, this bit is ignored. 0: Source address repeat interrupt is not requested 1: When source address repeat area overflow occurs, the IRF bit in EDMDR is set to 1 and an interrupt is requested

Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 405 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description SARA4 SARA3 SARA2 SARA1 SARA0 R/W R/W R/W R/W R/W Source Address Repeat Area These bits specify the source address (EDSAR) repeat area. The repeat area function updates the specified lower address bits, leaving the remaining upper address bits always the same. A repeat area size of 2 bytes to 8 Mbytes can be specified. The setting interval is a power-of-two number of bytes. When repeat area overflow results from incrementing or decrementing an address, the lower address is the start address of the repeat area in the case of address incrementing, or the last address of the repeat area in the case of address decrementing. If the SARIE bit is set to 1, an interrupt can be requested when repeat area overflow occurs. 00000: Not designated as repeat area 00001: Lower 1 bit (2-byte area) designated as repeat area 00010: Lower 2 bits (4-byte area) designated as repeat area 00011: Lower 3 bits (8-byte area) designated as repeat area 00100: Lower 4 bits (16-byte area) designated as repeat area : : 10011: Lower 19 bits (512-Kbyte area) designated as repeat area 10100: Lower 20 bits (1-Mbyte area) designated as repeat area 10101: Lower 21 bits (2-Mbyte area) designated as repeat area 10110: Lower 22 bits (4-Mbyte area) designated as repeat area 10111: Lower 23 bits (8-Mbyte area) designated as repeat area 11×××: Setting prohibited

Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 406 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description DAT1 DAT0 R/W R/W Destination Address Update Mode These bits specify incrementing/decrementing of the transfer destination address (EDDAR). When an external device with DACK is designated as the transfer destination in single address mode, the specification by these bits is ignored. 0×: Fixed 10: Incremented (+1 in byte transfer, +2 in word transfer) 11: Decremented (–1 in byte transfer, –2 in word transfer)

5 DARIE 0 R/W Destination Addr ess Repeat Interrupt Enable

When this bit is set to 1, in the event of destination address repeat area overflow the IRF bit is set to 1 and the EDA bit cleared to 0 in EDMDR, and transfer is terminated. If the EDIE bit in EDMDR is 1 when the IRF bit in EDMDR is set to 1, an interrupt request is sent to the CPU. When used together with block transfer mode, a destination address repeat interrupt is requested at the end of a block-size transfer. If the EDA bit is set to 1 in EDMDR for the channel on which transfer is terminated by a destination address repeat interrupt, transfer can be resumed from the state in which it ended. If a destination address repeat area has not been designated, this bit is ignored. 0: Destination address repeat interrupt is not requested 1: When destination address repeat area overflow occurs, the IRF bit in EDMDR is set to 1 and an interrupt is requested

Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 407 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description DARA4 DARA3 DARA2 DARA1 DARA0 R/W R/W R/W R/W R/W Destination Address Repeat Area These bits specify the destination address (EDDAR) repeat area. The repeat area function updates the specified lower address bits, leaving the remaining upper address bits always the same. A repeat area size of 2 bytes to 8 Mbytes can be specified. The setting interval is a power- of-two number of bytes. When repeat area overflow results from incrementing or decrementing an address, the lower address is the start address of the repeat area in the case of address incrementing, or the last address of the repeat area in the case of address decrementing. If the DARIE bit is set to 1, an interrupt can be requested when repeat area overflow occurs. 00000: Not designated as repeat area 00001: Lower 1 bit (2-byte area) designated as repeat area 00010: Lower 2 bits (4-byte area) designated as repeat area 00011: Lower 3 bits (8-byte area) designated as repeat area 00100: Lower 4 bits (16-byte area) designated as repeat area : : 10011: Lower 19 bits (512-Kbyte area) designated as repeat area 10100: Lower 20 bits (1-Mbyte area) designated as repeat area 10101: Lower 21 bits (2-Mbyte area) designated as repeat area 10110: Lower 22 bits (4-Mbyte area) designated as repeat area 10111: Lower 23 bits (8-Mbyte area) designated as repeat area 11×××: Setting prohibited Legend: ×: Don’t care

Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 408 of 1270 REJ09B0466-0100

8.4 Operation

8.4.1 Transfer Modes

The transfer modes of the EXDMAC are summarized in table 8.2. Table 8.2 EXDMAC Transfer Modes Address Registers Transfer Mode Transfer Origin Number of Transfers Source Destination Auto request mode  Burst/cycle steal mode Auto request Normal transfer mode External request mode  Cycle steal mode External request 1 to 16,777,215 or no specification Dual address mode Block transfer mode External request mode  Burst transfer of specified block size for a single transfer request  Block size: 1 to 256 bytes or words External request 1 to 65,535 or no specification EDSAR EDDAR Single address mode  Direct data transfer to/from external device using EDACK pin instead of source or destination address register  Above transfer mode can be specified in addition to address register setting  One transfer possible in one bus cycle (Transfer mode variations are the same as in dual address mode.) EDSAR/ EDACK EDACK/ EDDAR The transfer mode can be set independently for each channel. In normal transfer mode, a one-byte or one-word transfer is executed in response to one transfer request. With auto requests, burst or cycle steal transfer mode can be set. In burst transfer mode, continuous, high-speed transfer can be performed until the specified number of transfers have been executed or the transfer enable bit is cleared to 0.

Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 409 of 1270 REJ09B0466-0100 In block transfer mode, a transfer of the specified block size is executed in response to one transfer request. The block size can be from 1 to 256 bytes or words. Within a block, transfer can be performed at the same high speed as in block transfer mode. When the “no specification” setting (EDTCR = H'000000) is made for the number of transfers, the transfer counter is halted and there is no limit on the number of transfers, allowing transfer to be performed endlessly. Incrementing or decrementing the memory address by 1 or 2, or leaving the address unchanged, can be specified independently for each address register. In all transfer modes, it is possible to set a repeat area comprising a power-of-two number of bytes.

8.4.2 Address Modes

(1) Dual Address Mode In dual address mode, both the transfer source and transfer destination are specified by registers in the EXDMAC, and one transfer is executed in two bus cycles. The transfer source address is set in the source address register (EDSAR), and the transfer destination address is set in the transfer destination address register (EDDAR). In a transfer operation, the value in external memory specified by the transfer source address is read in the first bus cycle, and is written to the external memory specified by the transfer destination address in the next bus cycle. These consecutive read and write cycles are indivisible: another bus cycle (external access by an internal bus master, refresh cycle, or external bus release cycle) does not occur between these two cycles. ETEND pin output can be enabled or disabled by means of the ETENDE bit in EDMDR. ETEND is output for two consecutive bus cycles. The EDACK signal is not output. Figure 8.2 shows an example of the timing in dual address mode.

Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 412 of 1270 REJ09B0466-0100 EXDMA cycle EDSAR Address to external memory space RD signal to external memory space Data output from external memory Address bus φ RD WR EDACK ETEND Data bus EXDMA cycle EDDAR Address to external memory space WR signal to external memory space Address bus φ Transfer from external memory to external device with DACK Transfer from external device with DACK to external memory RD WR EDACK ETEND Data bus Data output from external device with DACK Figure 8.4 Example of Timing in Single Address Mode

Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 413 of 1270 REJ09B0466-0100

8.4.3 DMA Transfer Requests

(1) Auto Request Mode In auto request mode, transfer request signals are automatically generated within the EXDMAC in cases where a transfer request signal is not issued from outside, such as in transfer between two memories, or between a peripheral module that is not capable of generating transfer requests and memory. In auto request mode, transfer is started when the EDA bit is set to 1 in EDMDR. In auto request mode, either cycle steal mode or burst mode can be selected as the bus mode. Block transfer mode cannot be used. (2) External Request Mode In external request mode, transfer is started by a transfer request signal (EDREQ) from a device external to this LSI. DMA transfer is started when EDREQ is input while DMA transfer is enabled (EDA = 1). The transfer request source need not be the data transfer source or data transfer destination. The transfer request signal is accepted via the EDREQ pin. Either falling edge sensing or low level sensing can be selected for the EDREQ pin by means of the EDREQS bit in EDMDR (low level sensing when EDREQS = 0, falling edge sensing when EDREQS = 1). Setting the EDRAKE bit to 1 in EDMDR enables a signal confirming transfer request acceptance to be output from the EDRAK pin. The EDRAK signal is output when acceptance and transfer processing has been started in response to a single external request. The EDRAK signal enables the external device to determine the timing of EDREQ signal negation, and makes it possible to provide handshaking between the transfer request source and the EXDMAC. In external request mode, block transfer mode can be used instead of burst mode. Block transfer mode allows continuous execution (burst operation) of the specified number of transfers (the block size) in response to a single transfer request. In block transfer mode, the EDRAK signal is output only once for a one-block transfer, since the transfer request via the EDREQ pin is for a block unit.

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8.4.4 Bus Modes

There are two bus modes: cycle steal mode and burst mode. When the activation source is an auto request, either cycle steal mode or burst mode can be selected. When the activation source is an external request, cycle steal mode is used. (1) Cycle Steal Mode In cycle steal mode, the EXDMAC releases the bus at the end of each transfer of a transfer unit (byte, word, or block). If there is a subsequent transfer request, the EXDMAC takes back the bus, performs another transfer-unit transfer, and then releases the bus again. This procedure is repeated until the transfer end condition is satisfied. If a transfer request occurs in another channel during DMA transfer, the bus is temporarily released, then transfer is performed on the channel for which the transfer request was issued. If there is no external space bus request from another bus master, a one-cycle bus release interval is inserted. For details on the operation when there are requests for a number of channels, see section 8.4.8, Channel Priority Order. Figure 8.5 shows an example of the timing in cycle steal mode. CPU CPU CPU CPUEXDMAC EXDMAC Bus returned temporarily to CPU EDREQ EDRAK Bus cycle Transfer conditions:

  • Single address mode, normal transfer mode
  • EDREQ low level sensing
  • CPU internal bus master is operating in external space Figure 8.5 Example of Timing in Cycle Steal Mode

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8.4.5 Transfer Modes

There are two transfer modes: normal transfer mode and block transfer mode. When the activation source is an external request, either normal transfer mode or block transfer mode can be selected. When the activation source is an auto request, normal transfer mode is used. (1) Normal Transfer Mode In normal transfer mode, transfer of one transfer unit is processed in response to one transfer request. EDTCR functions as a 24-bit transfer counter. The ETEND signal is output only for the last DMA transfer. The EDRAK signal is output each time a transfer request is accepted and transfer processing is started. Figure 8.7 shows examples of DMA transfer timing in normal transfer mode. Read Write Read Write EXDMA transfer cycle Last EXDMA transfer cycle Bus cycle ETEND Transfer conditions: Dual address mode, auto request mode EXDMA EXDMA EDRAK EDREQ Bus cycle EDACK Transfer conditions: Single address mode, external request mode Figure 8.7 Examples of Timing in Normal Transfer Mode

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8.4.6 Repeat Area Function

The EXDMAC has a function for designating a repeat area for source addresses and/or destination addresses. When a repeat area is designated, the address register values repeat within the range specified as the repeat area. Normally, when a ring buffer is involved in a transfer, an operation is required to restore the address register value to the buffer start address each time the address register value is the last address in the buffer (i.e. when ring buffer address overflow occurs), but if the repeat area function is used, the operation that restores the address register value to the buffer start address is performed automatically within the EXDMAC. The repeat area function can be set independently for the source address register and the destination address register. The source address repeat area is specified by bits SARA4 to SARA0 in EDACR, and the destination address repeat area by bits DARA4 to DARA0 in EDACR. The size of each repeat area can be specified independently. When the address register value is the last address in the repeat area and repeat area overflow occurs, DMA transfer can be temporarily halted and an interrupt request sent to the CPU. If the SARIE bit in EDACR is set to 1, when the source address register overflows the repeat area, the IRF bit is set to 1 and the EDA bit cleared to 0 in EDMDR, and transfer is terminated. If EDIE = 1 in EDMDR, an interrupt is requested. If the DARIE bit in EDACR is set to 1, the above applies to the destination address register.

Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 419 of 1270 REJ09B0466-0100 If the EDA bit in EDMDR is set to 1 during interrupt generation, transfer is resumed. Figure 8.9 illustrates the operation of the repeat area function. External memory Repeated Repeat area overflow interrupt can be requested Range of EDSAR values H'23FFFE H'23FFFF H'240000 H'240001 H'240002 H'240003 H'240004 H'240005 H'240006 H'240007 H'240008 H'240009 H'240000 H'240001 H'240002 H'240003 H'240004 H'240005 H'240006 H'240007 When lower 3 bits (8-byte area) of EDSAR are designated as repeat area (SARA4 to SARA0 = 3) Figure 8.9 Example of Repeat Area Function Operation Caution is required when the repeat area overflow interrupt function is used together with block transfer mode. If transfer is always terminated when repeat area overflow occurs in block transfer mode, the block size must be a power of two, or alternatively, the address register value must be set so that the end of a block coincides with the end of the repeat area range.

Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 420 of 1270 REJ09B0466-0100 If repeat area overflow occurs while a block is being transferred in block transfer mode, the repeat interrupt request is held pending until the end of the block, and transfer overrun will occur. Figure 8.10 shows an example in which block transfer mode is used together with the repeat area function. External memory Range of EDSAR values First block transfer Second block transfer H'23FFFE H'23FFFF H'240000 H'240001 H'240002 H'240003 H'240004 H'240005 H'240006 H'240007 H'240008 H'240009 H'240000 H'240001 H'240002 H'240003 H'240004 H'240005 H'240006 H'240007 H'240000 H'240001 H'240002 H'240003 H'240004 H'240000 H'240001 H'240005 H'240006 H'240007 Interrupt requested Block transfer in progress When lower 3 bits (8-byte area) of EDSAR are designated as repeat area (SARA4 to SARA0 = 3), and block size of 5 (EDTCR[23–16] = 5) is set in block transfer mode Figure 8.10 Example of Repeat Area Function Operation in Block Transfer Mode

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8.4.7 Registers during DMA Transfer Operation

EXDMAC register values are updated as DMA transfer processing is performed. The updated values depend on various settings and the transfer status. The following registers and bits are updated: EDSAR, EDDAR, EDTCR, and bits EDA, BEF, and IRF in EDMDR, (1) EXDMA Source Address Register (EDSAR) When the EDSAR address is accessed as the transfer source, after the EDSAR value is output, EDSAR is updated with the address to be accessed next. Bits SAT1 and SAT0 in EDACR specify incrementing or decrementing. The address is fixed when SAT1 = 0, incremented when SAT1 = 1 and SAT0 = 0, and decremented when SAT1 = 1 and SAT0 = 1. The size of the increment or decrement is determined by the size of the data transferred. When the DTSIZE bit in EDMDR = 0, the data is byte-size and the address is incremented or decremented by 1; when DTSIZE = 1, the data is word-size and the address is incremented or decremented by When a repeat area setting is made, the operation conforms to that setting. The upper part of the address set for the repeat area function is fixed, and is not affected by address updating. When EDSAR is read during a transfer operation, a longword access must be used. During a transfer operation, EDSAR may be updated without regard to accesses from the CPU, and the correct values may not be read if the upper and lower words are read separately. In a longword access, the EXDMAC buffers the EDSAR value to ensure that the correct value is output. Do not write to EDSAR for a channel on which a transfer operation is in progress. (2) EXDMA Destination Address Register (EDDAR) When the EDDAR address is accessed as the transfer destination, after the EDDAR value is output, EDDAR is updated with the address to be accessed next. Bits DAT1 and DAT0 in EDACR specify incrementing or decrementing. The address is fixed when DAT1 = 0, incremented when DAT1 = 1 and DAT0 = 0, and decremented when DAT1 = 1 and DAT0 = 1. The size of the increment or decrement is determined by the size of the data transferred. When the DTSIZE bit in EDMDR = 0, the data is byte-size and the address is incremented or decremented by 1; when DTSIZE = 1, the data is word-size and the address is incremented or decremented by When a repeat area setting is made, the operation conforms to that setting. The upper part of the address set for the repeat area function is fixed, and is not affected by address updating.

Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 422 of 1270 REJ09B0466-0100 When EDDAR is read during a transfer operation, a longword access must be used. During a transfer operation, EDDAR may be updated without regard to accesses from the CPU, and the correct values may not be read if the upper and lower words are read separately. In a longword access, the EXDMAC buffers the EDDAR value to ensure that the correct value is output. Do not write to EDDAR for a channel on which a transfer operation is in progress. (3) EXDMA Transfer Count Register (EDTCR) When a DMA transfer is performed, the value in EDTCR is decremented by 1. However, when the EDTCR value is 0, transfers are not counted and the EDTCR value does not change. EDTCR functions differently in block transfer mode. The upper 8 bits, EDTCR[23:16], are used to specify the block size, and their value does not change. The lower 16 bits, EDTCR[15:0], function as a transfer counter, the value of which is decremented by 1 when a DMA transfer is performed. However, when the EDTCR[15:0] value is 0, transfers are not counted and the EDTCR[15:0] value does not change. In normal transfer mode, all of the lower 24 bits of EDTCR may change, so when EDTCR is read by the CPU during DMA transfer, a longword access must be used. During a transfer operation, EDTCR may be updated without regard to accesses from the CPU, and the correct values may not be read if the upper and lower words are read separately. In a longword access, the EXDMAC buffers the EDTCR value to ensure that the correct value is output. In block transfer mode, the upper 8 bits are never updated, so there is no problem with using word access. Do not write to EDTCR for a channel on which a transfer operation is in progress. If there is contention between an address update associated with DMA transfer and a write by the CPU, the CPU write has priority. In the event of contention between an EDTCR update from 1 to 0 and a write (of a nonzero value) by the CPU, the CPU write value has priority as the EDTCR value, but transfer is terminated. Transfer does not end if the CPU writes 0 to EDTCR.

Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 425 of 1270 REJ09B0466-0100 (5) BEF Bit in EDMDR In block transfer mode, the specified number of transfers (equivalent to the block size) is performed in response to a single transfer request. To ensure that the correct number of transfers is carried out, a block-size transfer is always executed, except in the event of a reset, transition to standby mode, or generation of an NMI interrupt. If an NMI interrupt is generated during block transfer, operation is halted midway through a block-size transfer and the EDA bit is cleared to 0, terminating the transfer operation. In this case the BEF bit, which indicates the occurrence of an error during block transfer, is set to 1. (6) IRF Bit in EDMDR The IRF bit in EDMDR is set to 1 when an interrupt request source occurs. If the EDIE bit in EDMDR is 1 at this time, an interrupt is requested. The timing for setting the IRF bit to 1 is when the EDA bit in EDMDR is cleared to 0 and transfer ends following the end of the DMA transfer bus cycle in which the source generating the interrupt occurred. If the EDA bit is set to 1 and transfer is resumed during interrupt handling, the IRF bit is automatically cleared to 0 and the interrupt request is cleared. For details on interrupts, see section 8.5, Interrupt Sources.

8.4.8 Channel Priority Order

The priority order of the EXDMAC channels is: channel 2 > channel 3. Table 8.3 shows the EXDMAC channel priority order. Table 8.3 EXDMAC Channel Priority Order Channel Priority Channel 2 High Channel 3 Low If transfer requests occur simultaneously for a number of channels, the highest-priority channel according to the priority order in table 8.3 is selected for transfer.

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8.4.9 EXDMAC Bus Cycles (Dual Address Mode)

(1) Normal Transfer Mode (Cycle Steal Mode) Figure 8.15 shows an example of transfer when ETEND output is enabled, and word-size, normal transfer mode (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. After one byte or word has been transferred, the bus is released. While the bus is released, one CPU, DMAC, or DTC bus cycle is initiated. DMA read RD HWR ETEND LWR DMA write DMA read DMA write DMA read DMA write Address bus φ Bus release Bus release Bus release Bus release Last transfer cycle Figure 8.15 Example of Normal Transfer Mode (Cycle Steal Mode) Transfer

Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 432 of 1270 REJ09B0466-0100 DMA read DMA write Address bus φ EDREQ Idle Write Bus release Transfer destination DMA control Channel WriteIdle Transfer source Transfer destinationTransfer source Request Request Minimum 3 cycles Acceptance resumed Acceptance resumed Read Bus release DMA read DMA write Bus release One block transfer One block transfer Idle [1] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of φ, and request is held. [2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC. [3], [6] DMA cycle start; EDREQ pin high level sampling is started at rise of φ. [4], [7] When EDREQ pin high level has been sampled, acceptance is resumed after completion of dead cycle. (As in [1], EDREQ pin low level is sampled at rise of φ, and request is held.) Read Request clearance period Request clearance period Minimum 3 cycles Figure 8.19 Example of Block Transfer Mode Transfer Activated by EDREQ Pin Falling Edge EDREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the EDMDR write cycle for setting the transfer-enabled state. When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC, the request is cleared, and EDREQ pin high level sampling for edge sensing is started. If EDREQ pin high level sampling is completed by the end of the DMA write cycle, acceptance resumes after the end of the write cycle, and EDREQ pin low level sampling is performed again; this sequence of operations is repeated until the end of the transfer.

Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 434 of 1270 REJ09B0466-0100 DMA read DMA write Address bus φ EDREQ Idle Write Bus release DMA control Channel WriteIdleRead Bus release DMA read DMA write One block transfer One block transfer Idle Transfer destinationTransfer source Transfer destinationTransfer source Acceptance resumed Acceptance resumed Bus release [1] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of φ, and request is held. [2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC. [3], [6] DMA cycle is started. [4], [7] Acceptance is resumed after completion of dead cycle. (As in [1], EDREQ pin low level is sampled at rise of φ, and request is held.) Minimum 3 cycles Request Request Read Minimum 3 cycles Request clearance period Request clearance period Figure 8.21 Example of Block Transfer Mode Transfer Activated by EDREQ Pin Low Level EDREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the EDMDR write cycle for setting the transfer-enabled state. When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC, the request is cleared. At the end of the write cycle, acceptance resumes and EDREQ pin low level sampling is performed again; this sequence of operations is repeated until the end of the transfer.

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8.4.10 EXDMAC Bus Cycles (Single Address Mode)

(1) Single Address Mode (Read) Figure 8.22 shows an example of transfer when ETEND output is enabled, and byte-size, single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. RD ETEND Address bus φ Bus release Bus release Bus release Last transfer cycle DMA read EDACK DMA readDMA readDMA read Bus releaseBus release Figure 8.22 Example of Single Address Mode (Byte Read) Transfer Figure 8.23 shows an example of transfer when ETEND output is enabled, and word-size, single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. DMA read RD ETEND Address bus φ Bus release Bus release Bus release Last transfer cycle EDACK Bus release DMA readDMA read Figure 8.23 Example of Single Address Mode (Word Read) Transfer

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8.4.11 Examples of Operation Timing in Each Mode

(1) Auto Request/Cycle Steal Mode/Normal Transfer Mode When the EDA bit is set to 1 in EDMDR, an EXDMA transfer cycle is started a minimum of three cycles later. There is a one-cycle bus release interval between the end of a one-transfer-unit EXDMA cycle and the start of the next transfer. If there is a transfer request for another channel of higher priority, the transfer request by the original channel is held pending, and transfer is performed on the higher-priority channel from the next transfer. Transfer on the original channel is resumed on completion of the higher-priority channel transfer. Figures 8.28 to 8.30 show operation timing examples for various conditions. φ pin ETEND Bus cycle CPU operation EDA bit EXDMA read EDA = 1 write 0 01 EXDMA write EXDMA read EXDMA write EXDMA read EXDMA write 3 cycles 1 cycle Last transfer cycle Internal bus space cycles Bus release Bus release Bus release Figure 8.28 Auto Request/Cycle Steal Mode/Normal Transfer Mode (No Contention/Dual Address Mode)

Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 442 of 1270 REJ09B0466-0100 (2) Auto Request/Burst Mode/Normal Transfer Mode When the EDA bit is set to 1 in EDMDR, an EXDMA transfer cycle is started a minimum of three cycles later. Once transfer is started, it continues (as a burst) until the transfer end condition is satisfied. If the BGUP bit is 1 in EDMDR, the bus is transferred in the event of a bus request from another bus master. Transfer requests for other channels are held pending until the end of transfer on the current channel. Figures 8.31 to 8.34 show operation timing examples for various conditions. φ pin ETEND Bus cycle CPU operation EDA bit EXDMA read EXDMA write EXDMA read EXDMA write EXDMA read EXDMA write External space External space External space Repeated Last transfer cycle CPU cycle CPU cycle CPU cycle Figure 8.31 Auto Request/Burst Mode/Normal Transfer Mode (CPU Cycles/Dual Address Mode/BGUP = 0)

Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 444 of 1270 REJ09B0466-0100 φ pin Bus cycle Original channel EDACK Original channel ETEND Other channel transfer request (EDREQ) EXDMA single transfer cycle EXDMA single transfer cycle EXDMA single transfer cycle 1 cycleLast transfer cycle Other channel EXDMA cycleBus release Bus release Bus release Figure 8.34 Auto Request/Burst Mode/Normal Transfer Mode (Contention with Another Channel/Single Address Mode)

Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 445 of 1270 REJ09B0466-0100 (3) External Request/Cycle Steal Mode/Normal Transfer Mode In external request mode, an EXDMA transfer cycle is started a minimum of three cycles after a transfer request is accepted. The next transfer request is accepted after the end of a one-transfer- unit EXDMA cycle. For external bus space CPU cycles, at least two bus cycles are generated before the next EXDMA cycle. If a transfer request is generated for another channel, an EXDMA cycle for the other channel is generated before the next EXDMA cycle. The EDREQ pin sensing timing is different for low level sensing and falling edge sensing. The same applies to transfer request acceptance and transfer start timing. Figures 8.35 to 8.38 show operation timing examples for various conditions. φ pin EDREQ EDRAK ETEND Bus cycle EDA bit Bus release Bus release Bus releaseEXDMA read EXDMA write EXDMA read EXDMA write Last transfer cycle3 cycles Figure 8.35 External Request/Cycle Steal Mode/Normal Transfer Mode (No Contention/Dual Address Mode/Low Level Sensing)

Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 447 of 1270 REJ09B0466-0100 φ pin Original channel EDREQ Original channel EDRAK Other channel EDREQ Other channel EDRAK Bus cycle 3 cycles 1 cycle 1 cycle EXDMA transfer cycle Bus release Other channel transfer cycle EXDMA read EXDMA write EXDMA read EXDMA write Bus release Bus release Figure 8.38 External Request/Cycle Steal Mode/Normal Transfer Mode Contention with Another Channel/Dual Address Mode/Low Level Sensing (4) External Request/Cycle Steal Mode/Block Transfer Mode In block transfer mode, transfer of one block is performed continuously in the same way as in burst mode. The timing of the start of the next block transfer is the same as in normal transfer mode. If a transfer request is generated for another channel, an EXDMA cycle for the other channel is generated before the next block transfer. The EDREQ pin sensing timing is different for low level sensing and falling edge sensing. The same applies to transfer request acceptance and transfer start timing. Figures 8.39 to 8.44 show operation timing examples for various conditions.

Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 448 of 1270 REJ09B0466-0100 φ pin EDREQ EDRAK ETEND Bus cycle EDA bit Bus release Bus releaseEXDMA read EXDMA write EXDMA read EXDMA write EXDMA read EXDMA write EXDMA read EXDMA write EXDMA read EXDMA write Last transfer in block 1-block-size transfer period Last block Last transfer cycle3 cycles Repeated Bus releaseRepeated Figure 8.39 External Request/Cycle Steal Mode/Block Transfer Mode (No Contention/Dual Address Mode/Low Level Sensing/BGUP = 0)

Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 449 of 1270 REJ09B0466-0100 φ pin EDREQ EDRAK EDACK Bus cycle ETEND Bus release Bus release Last transfer in block 1-block-size transfer period Last block Last transfer cycle3 cycles EXDMA single transfer cycle EXDMA single transfer cycle EXDMA single transfer cycle EXDMA single transfer cycle EXDMA single transfer cycle Repeated Repeated Bus release Figure 8.40 External Request/Cycle Steal Mode/Block Transfer Mode (No Contention/Single Address Mode/Falling Edge Sensing/BGUP = 0)

Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 450 of 1270 REJ09B0466-0100 φ pin EDREQ EDRAK EDACK Bus cycle CPU operation ETEND 1-block-size transfer period 1-block-size transfer period Last transfer in block Last transfer in block 2 bus cycles EXDMA single transfer cycle EXDMA single transfer cycle EXDMA single transfer cycle EXDMA single transfer cycle External space External space External space External space External space CPU cycle CPU cycle CPU cycle CPU cycle CPU cycle CPU cycle External space Repeated Repeated Figure 8.41 External Request/Cycle Steal Mode/Block Transfer Mode (CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 0)

Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 451 of 1270 REJ09B0466-0100 φ pin EDREQ EDRAK Bus cycle CPU operation ETEND 1-block-size transfer period 1 bus cycle CPU cycle CPU cycle CPU cycle CPU cycle CPU cycle CPU cycle CPU cycle CPU cycle External space External space External space External space EXDMA read EXDMA write EXDMA read EXDMA read EXDMA write EXDMA read EXDMA write 1 bus cycle1 bus cycle Last transfer in block External space External space External space External space Repeated Figure 8.42 External Request/Cycle Steal Mode/Block Transfer Mode (CPU Cycles/Dual Address Mode/Low Level Sensing/BGUP = 1)

Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 452 of 1270 REJ09B0466-0100 φ pin EDREQ EDRAK Bus cycle CPU operation EDACK ETEND 1-block-size transfer period 1 bus cycle CPU cycle CPU cycle External space External space CPU cycle CPU cycle CPU cycle CPU cycle CPU cycle CPU cycle External space External space External space External space External space External space 1 bus cycle1 bus cycle Last transfer in block EXDMA transfer cycle EXDMA transfer cycle EXDMA transfer cycle EXDMA transfer cycle EXDMA transfer cycle EXDMA transfer cycle EXDMA transfer cycle Repeated Figure 8.43 External Request/Cycle Steal Mode/Block Transfer Mode (CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 1)

Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 453 of 1270 REJ09B0466-0100 φ pin EDREQ EDRAK ETEND Bus cycle Other channel EDREQ Other channel EDRAK Bus release EXDMA read EXDMA write EXDMA read EXDMA write EXDMA read EXDMA write EXDMA read EXDMA write Last transfer in block Last transfer in block 1-block-size transfer period 1-block-size transfer period Other channel EXDMA cycle Bus release Bus release RepeatedRepeated Figure 8.44 External Request/Cycle Steal Mode/Block Transfer Mode (Contention with Another Channel/Dual Address Mode/Low Level Sensing)

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8.4.12 Ending DMA Transfer

The operation for ending DMA transfer depends on the transfer end conditions. When DMA transfer ends, the EDA bit in EDMDR changes from 1 to 0, indicating that DMA transfer has ended. (1) Transfer End by 1 → 0 Transition of EDTCR When the value of EDTCR changes from 1 to 0, DMA transfer ends on the corresponding channel and the EDA bit in EDMDR is cleared to 0. If the TCEIE bit in EDMDR is set at this time, a transfer end interrupt request is generated by the transfer counter and the IRF bit in EDMDR is set to 1. In block transfer mode, DMA transfer ends when the value of bits 15 to 0 in EDTCR changes from 1 to 0. DMA transfer does not end if the EDTCR value has been 0 since before the start of transfer. (2) Transfer End by Repeat Area Overflow Interrupt If an address overflows the repeat area when a repeat area specification has been made and repeat interrupts have been enabled (with the SARIE or DARIE bit in EDACR), a repeat area overflow interrupt is requested. DMA transfer ends, the EDA bit in EDMDR is cleared to 0, and the IRF bit in EDMDR is set to 1. In dual address mode, if a repeat area overflow interrupt is requested during a read cycle, the following write cycle processing is still executed. In block transfer mode, if a repeat area overflow interrupt is requested during transfer of a block, transfer continues to the end of the block. Transfer end by means of a repeat area overflow interrupt occurs between block-size transfers. (3) Transfer End by 0-Write to EDA Bit in EDMDR When 0 is written to the EDA bit in EDMDR by the CPU, etc., transfer ends after completion of the DMA cycle in which transfer is in progress or a transfer request was accepted. In block transfer mode, DMA transfer halts after completion of one-block-size transfer. The EDA bit in EDMDR is not cleared to 0 until all transfer processing has ended. Up to that point, the value of the EDA bit will be read as 1.

Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 455 of 1270 REJ09B0466-0100 (4) Transfer Abort by NMI Interrupt DMA transfer is aborted when an NMI interrupt is generated. The EDA bit is cleared to 0 in all channels. In external request mode, DMA transfer is performed for all transfer requests for which EDRAK has been output. In dual address mode, processing is executed for the write cycle following the read cycle. In block transfer mode, operation is aborted even in the middle of a block-size transfer. As the transfer is halted midway through a block, the BEF bit in EDMDR is set to 1 to indicate that the block transfer was not carried out normally. When transfer is aborted, register values are retained, and as the address registers indicate the next transfer addresses, transfer can be resumed by setting the EDA bit to 1 in EDMDR. If the BEF bit is 1 in EDMDR, transfer can be resumed from midway through a block. (5) Hardware Standby Mode and Reset Input The EXDMAC is initialized in hardware standby mode and by a reset. DMA transfer is not guaranteed in these cases.

8.4.13 Relationship between EXDMAC and Other Bus Masters

The read and write operations in a DMA transfer cycle are indivisible, and a refresh cycle, external bus release cycle, or internal bus master (CPU, DTC, or DMAC) external space access cycle never occurs between the two. When read and write cycles occur consecutively, as in burst transfer or block transfer, a refresh or external bus release state may be inserted after the write cycle. As the internal bus masters are of lower priority than the EXDMAC, external space accesses by internal bus masters are not executed until the EXDMAC releases the bus. The EXDMAC releases the bus in the following cases: 1. When DMA transfer is performed in cycle steal mode 2. When switching to a different channel 3. When transfer ends in burst transfer mode 4. When transfer of one block ends in block transfer mode 5. When burst transfer or block transfer is performed with the BGUP bit in EDMDR set to 1 (however, the bus is not released between read and write cycles)

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8.5 Interrupt Sources

EXDMAC interrupt sources are a transfer end indicated by the transfer counter, and repeat area overflow interrupts. Table 8.4 shows the interrupt sources and their priority order. Table 8.4 Interrupt Sources and Priority Order Interrupt Interrupt sour ce Interrupt Priority EXDMTEND2 Transfer end indicated by channel 2 transfer counter Channel 2 source address repeat area overflow Channel 2 destination address repeat area overflow High EXDMTEND3 Transfer end indicated by channel 3 transfer counter Channel 3 source address repeat area overflow Channel 3 destination address repeat area overflow Low Interrupt sources can be enabled or disabled by means of the EDIE bit in EDMDR for the relevant channel, and can be sent to the interrupt controller independently. The relative priority order of the channels is determined by the interrupt controller (see table 8.4). Figure 8.45 shows the transfer end interrupt logic. A transfer end interrupt is generated whenever the EDIE bit is set to 1 while the IRF bit is set to 1 in EDMDR. Transfer end interrupt IRF bit EDIE bit Figure 8.45 Transfer End Interrupt Logic Interrupt source settings are made individually with the interrupt enable bits in the registers for the relevant channels. The transfer counter’s transfer end interrupt is enabled or disabled by means of the TCEIE bit in EDMDR, the source address register repeat area overflow interrupt by means of the SARIE bit in EDACR, and the destination address register repeat area overflow interrupt by means of the DARIE bit in EDACR. When an interrupt source occurs while the corresponding interrupt enable bit is set to 1, the IRF bit in EDMDR is set to 1. The IRF bit is set by all interrupt sources indiscriminately.

Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 457 of 1270 REJ09B0466-0100 The transfer end interrupt can be cleared either by clearing the IRF bit to 0 in EDMDR within the interrupt handling routine, or by re-setting the transfer counter and address registers and then setting the EDA bit to 1 in EDMDR to perform transfer continuation processing. An example of the procedure for clearing the transfer end interrupt and restarting transfer is shown in figure 8.46. [1] Write set values to the registers (transfer counter, address registers, etc.). [2] Write 1 to the EDA bit in EDMDR to restart EXDMA operation. When 1 is written to the EDA bit, the IRF bit in EDMDR is automatically cleared to 0 and the interrupt source is cleared. [3] The interrupt handling routine is ended with an RTE instruction, etc. [4] Clear the IRF bit to 0 in EDMDR by first reading 1 from it, then writing 0. [5] After the interrupt handling routine is ended with an RTE instruction, etc., interrupt masking is cleared. [6] Write set values to the registers (transfer counter, address registers, etc.). [7] Write 1 to the EDA bit in EDMDR to restart EXDMA operation. End of transfer restart processing Write 1 to EDA bit Change register settings End of interrupt handling routine Clear IRF bit to 0 Transfer restart after end of interrupt handling routine Transfer end interrupt exception handling routine Transfer continuation processing Change register settings Write 1 to EDA bit End of interrupt handling routine (RTE instruction execution) End of transfer restart processing [1] [4] [5] [6] [7] [2] [3] Figure 8.46 Example of Procedure for Restarting Transfer on Channel in which Transfer End Interrupt Occurred

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8.6 Usage Notes

(1) EXDMAC Register Access during Operation Except for clearing the EDA bit to 0 in EDMDR, settings should not be changed for a channel in operation (including the transfer standby state). Transfer must be disabled before changing a setting for an operational channel. (2) Module Stop State When the MSTP14 bit is set to 1 in MSTPCRH, the EXDMAC clock stops and the EXDMAC enters the module stop state. However, 1 cannot be written to the MSTP14 bit when any of the EXDMAC’s channels is enabled for transfer, or when an interrupt is being requested. Before setting the MSTP14 bit, first clear the EDA bit in EDMDR to 0, then clear the IRF or EDIE bit in EDMDR to 0. When the EXDMAC clock stops, EXDMAC registers can no longer be accessed. The following EXDMAC register settings remain valid in the module stop state, and so should be changed, if necessary, before making the module stop transition.

  • ETENDE = 1 in EDMDR ( ETEND pin enable)
  • EDRAKE = 1 in EDMDR ( EDRAK pin enable)
  • AMS = 1 in EDMDR ( EDACK pin enable) (3) EDREQ Pin Falling Edge Activation Falling edge sensing on the EDREQ pin is performed in synchronization with EXDMAC internal operations, as indicated below. [1] Activation request standby state: Waits for low level sensing on EDREQ pin, then goes to [2]. [2] Transfer standby state: Waits for EXDMAC data transfer to become possible, then goes to [3]. [3] Activation request disabled state: Waits for high level sensing on EDREQ pin, then goes to [1]. After EXDMAC transfer is enabled, the EXDMAC goes to state [1], so low level sensing is used for the initial activation after transfer is enabled.

Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 459 of 1270 REJ09B0466-0100 (4) Activation Source Acceptance At the start of activation source acceptance, low level sensing is used for both falling edge sensing and low level sensing on the EDREQ pin. Therefore, a request is accepted in the case of a low level at the EDREQ pin that occurs before execution of the EDMDR write for setting the transfer- enabled state. When the EXDMAC is activated, make sure, if necessary, that a low level does not remain at the EDREQ pin from the previous end of transfer, etc. (5) Enabling Interrupt Requests when IRF = 1 in EDMDR When transfer is started while the IRF bit is set to 1 in EDMDR, if the EDIE bit is set to 1 in EDMDR together with the EDA bit in EDMDR, enabling interrupt requests, an interrupt will be requested since EDIE = 1 and IRF = 1. To prevent the occurrence of an erroneous interrupt request when transfer starts, ensure that the IRF bit is cleared to 0 before the EDIE bit is set to 1. (6) ETEND Pin and CBR Refresh Cycle If the last EXDMAC transfer cycle and a CBR refresh cycle occur simultaneously, note that although the CBR refresh and the last transfer cycle may be executed consecutively, ETEND may also go low in this case for the refresh cycle.

Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 460 of 1270 REJ09B0466-0100

Section 9 Data Transfer Controller (DTC) Rev. 1.00 Sep. 19, 2008 Page 461 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. Figure 9.1 shows a block diagram of the DTC.

9.1 Features

  • Transfer possible over any number of channels
  • Three transfer modes 1. Normal mode One operation transfers one byte or one word of data. Memory address is incremented or decremented by 1 or 2. From 1 to 65,536 transfers can be specified. 2. Repeat mode One operation transfers one byte or one word of data. Memory address is incremented or decremented by 1 or 2. Once the specified number of transfers (1 to 256) has ended, the initial state is restored, and transfer is repeated. 3. Block transfer mode One operation transfers one block of data. The block size is 1 to 256 bytes or words. From 1 to 65,536 transfers can be specified. Either the transfer source or the transfer destination is designated as a block area.
  • One activation source can trigger a number of data transfers (chain transfer)
  • Direct specification of 16-Mbyte address space possible
  • Activation by software is possible
  • Transfer can be set in byte or word units
  • A CPU interrupt can be requested for the interrupt that activated the DTC
  • Module stop mode can be set

Section 9 Data Transfer Controller (DTC) Rev. 1.00 Sep. 19, 2008 Page 462 of 1270 REJ09B0466-0100 The DTC's register information is stored in the on-chip RAM. When the DTC is used, the RAME bit in SYSCR must be set to 1. A 32-bit bus connects the DTC to the on-chip RAM (1 Kbyte), enabling 32-bit/1-state reading and writing of the DTC register information. DTVECR DTC On-chip RAM MRA MRB CRA CRB DAR SAR DTCCR Interrupt request Interrupt controller Internal address bus DTC activation request Register information CPU interrupt request Internal data bus Legend: MRA, MRB CRA, CRB SAR DAR DTCERA to DTCERI DTVECR DTCCR : DTC mode registers A and B : DTC transfer count registers A and B : DTC source address register : DTC destination address register : DTC enable registers A to I : DTC vector register : DTC control register DTCERA to DTCERI Control logic Figure 9.1 Block Diagram of DTC

Section 9 Data Transfer Controller (DTC) Rev. 1.00 Sep. 19, 2008 Page 463 of 1270 REJ09B0466-0100

9.2 Register Descriptions

DTC has the following registers.

  • DTC mode register A (MRA)
  • DTC mode register B (MRB)
  • DTC source address register (SAR)
  • DTC destination address register (DAR)
  • DTC transfer count register A (CRA)
  • DTC transfer count register B (CRB) These six registers cannot be directly accessed from the CPU. When activated, the DTC reads a set of register information that is stored in an on-chip RAM to the corresponding DTC registers and transfers data. After the data transfer, it writes a set of updated register information back to the RAM.
  • DTC enable registers A to I (DTCERA to DTCERI)
  • DTC vector register (DTVECR)
  • DTC control register (DTCCR)

9.2.1 DTC Mode Register A (MRA)

MRA selects the DTC operating mode. Bit Bit Name Initial Value R/W Description SM1 SM0 Undefined Undefined Source Address Mode 1 and 0 These bits specify an SAR operation after a data transfer. 0×: SAR is fixed 10: SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) 11: SAR is decremented after a transfer (by –1 when Sz = 0; by –2 when Sz = 1)

Section 9 Data Transfer Controller (DTC) Rev. 1.00 Sep. 19, 2008 Page 464 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description DM1 DM0 Undefined Undefined Destination Address Mode 1 and 0 These bits specify a DAR operation after a data transfer. 0×: DAR is fixed 10: DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) 11: DAR is decremented after a transfer (by –1 when Sz = 0; by –2 when Sz = 1) MD1 MD0 Undefined Undefined DTC Mode These bits specify the DTC transfer mode. 00: Normal mode 01: Repeat mode 10: Block transfer mode 11: Setting prohibited

1 DTS Undefined — DTC Transfer Mode Select

Specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode. 0: Destination side is repeat area or block area 1: Source side is repeat area or block area

0 Sz Undefined — DTC Data Transfer Size

Specifies the size of data to be transferred. 0: Byte-size transfer 1: Word-size transfer Legend: × : Don't care

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9.2.2 DTC Mode Register B (MRB)

MRB selects the DTC operating mode. Bit Bit Name Initial Value R/W Description

7 CHNE Undefined — DTC Chain Transfer Enable

When this bit is set to 1, a chain transfer will be performed. For details, refer to section 9.5.4, Chain Transfer. In data transfer with CHNE set to 1, determination of the end of the specified number of transfers, clearing of the activation source flag, and clearing of DTCER is not performed.

6 DISEL Undefined — DTC Interrupt Select

When this bit is set to 1, a CPU interrupt request is generated every time after a data transfer ends. When this bit is set to 0, a CPU interrupt request is generated at the time when the specified number of data transfer ends.

5 CHNS Undefined — DTC Chain Transfer Select

Specifies the chain transfer condition. 0: Chain transfer every time 1: Chain transfer only when transfer counter = 0 4 to 0 — Undefined — Reserved These bits have no effect on DTC operation, and should always be written with 0.

9.2.3 DTC Source Address Register (SAR)

SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address.

9.2.4 DTC Destination Address Register (DAR)

DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size transfer, specify an even destination address.

Section 9 Data Transfer Controller (DTC) Rev. 1.00 Sep. 19, 2008 Page 466 of 1270 REJ09B0466-0100

9.2.5 DTC Transfer Count Register A (CRA)

CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65,536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits (CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent when the count reaches H'00.

9.2.6 DTC Transfer Count Register B (CRB)

CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. The CRB is not available in normal and repeat modes.

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9.2.7 DTC Enable Registers A to I (DTCERA to DTCERI)

DTCER which is comprised of registers, DTCERA to DTCERI, is a register that specifies DTC activation interrupt sources. The correspondence between interrupt sources and DTCE bits is shown in table 9.2. For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR for reading and writing. If all interrupts are masked, multiple activation sources can be set at one time (only at the initial setting) by writing data after executing a dummy read on the relevant register. Bit Bit Name Initial Value R/W Description DTCE7 DTCE6 DTCE5 DTCE4 DTCE3 DTCE2 DTCE1 DTCE0 R/W R/W R/W R/W R/W R/W R/W R/W DTC Activation Enable Setting this bit to 1 specifies a relevant interrupt source to a DTC activation source. [Clearing conditions]

  • When the DISEL bit is 1 and the data transfer has ended
  • When the specified number of transfers have ended These bits are not automatically cleared when the DISEL bit is 0 and the specified number of transfers have not ended
  • When 0 is written to DTCE after reading DTCE = 1

9.2.8 DTC Vector Register (DTVECR)

DTVECR sets a vector number for the software activation interrupt. Bit Bit Name Initial Value R/W Description DTVEC7 DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 R/W R/W R/W R/W R/W R/W R/W R/W DTC Software Activation Vectors 7 to 0 These bits specify a vector number for DTC software activation. The vector address is expressed as H'0400 + (vector number × 2). For example, when DTVEC7 to DTVEC0 = H'10, the vector address is H'0420. These bits can be written to only when the SWDTE bit is 0.

Section 9 Data Transfer Controller (DTC) Rev. 1.00 Sep. 19, 2008 Page 468 of 1270 REJ09B0466-0100

9.2.9 DTC Control Register (DTCCR)

DTCCR enables or disables DTC activation by software. Bit Bit Name Initial Value R/W Description

7 SWDTE 0 R/W DTC Software Activation Enable

Setting this bit to 1 activates the DTC. Only 1 can be written to this bit. [Clearing conditions]

  • When the DISEL bit is 0 and the specified number of transfers have not ended
  • When 0 is written to the DISEL bit after a software-activated data transfer end interrupt (SWDTEND) request has been sent to the CPU. When the DISEL bit is 1 and data transfer has ended or when the specified number of transfers have ended, this bit will not be cleared. 6 to 0 — All 0 R Reserved These bits are always read as 0 and cannot be modified.

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9.3 Activation Sources

The DTC operates when activated by an interrupt or by a write to DTVECR or DTCCR by software. An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source or corresponding DTCER bit is cleared. The activation source flag, in the case of RXI0, for example, is the RDRF flag of SCI_0. When an interrupt has been designated a DTC activation source, existing CPU mask level and interrupt controller priorities have no effect. If there is more than one activation source at the same time, the DTC operates in accordance with the default priorities. Table 9.1 shows a relationship between activation sources and DTCER clear conditions. Figure 9.2 shows a block diagram of activation source control. For details see section 5, Interrupt Controller. Table 9.1 Relationship between Activation Sources and DTCER Clearing Activation Source DISEL = 0 and Specified Number of Transfers Has Not Ended DISEL = 1 or Specified Number of Transfers Has Ended Activation by software SWDTE bit is cleared to 0 • SWDTE bit remains set to 1

  • Interrupt request to CPU Activation by an interrupt • Corresponding DTCER bit remains set to 1.
  • Activation source flag is cleared to 0.
  • Corresponding DTCER bit is cleared to 0.
  • Activation source flag remains set to 1.
  • Interrupt that became the activation source is requested to the CPU.

Section 9 Data Transfer Controller (DTC) Rev. 1.00 Sep. 19, 2008 Page 470 of 1270 REJ09B0466-0100 CPU DTC DTCER Source flag cleared On-chip peripheral modules IRQ interrupt Interrupt request Clear Clear controller Clear request Interrupt controller Selection circuit Interrupt mask Select DTVECR DTCCR Figure 9.2 Block Diagram of DTC Activation Source Control

Section 9 Data Transfer Controller (DTC) Rev. 1.00 Sep. 19, 2008 Page 471 of 1270 REJ09B0466-0100

9.4 Location of Register Information and DTC Vector Table

Locate the register information in the on-chip RAM (addresses: H'FFBC00 to H'FFBFFF). Register information should be located at the address that is multiple of four within the range. Locating the register information in address space is shown in figure 9.3. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register information. In the case of chain transfer, register information should be located in consecutive areas as shown in figure 9.3 and the register information start address should be located at the corresponding vector address to the activation source. Figure 9.4 shows correspondences between the DTC vector address and register information. The DTC reads the start address of the register information from the vector address set for each activation source, and then reads the register information from that start address. When the DTC is activated by software, the vector address is obtained from: H'0400 + (DTVECR[7:0] × 2). For example, if DTVECR is H'10, the vector address is H'0420. The configuration of the vector address is the same in both normal* and advanced modes, a 2-byte unit being used in both cases. These two bytes specify the lower bits of the register information start address. Note: * Not available in this LSI. MRAStart address of register information Register information Register information for second transfer in case of chain transfer Chain transfer Lower addresses Four bytes 0123 SAR MRB DAR CRA CRB MRA SAR MRB DAR CRA CRB Figure 9.3 Correspondence between DTC Vector Address and Register Information

Section 9 Data Transfer Controller (DTC) Rev. 1.00 Sep. 19, 2008 Page 472 of 1270 REJ09B0466-0100 DTC vector address Chain transfer Register information start address Register information Figure 9.4 Correspondence between DTC Vector Address and Register Information Table 9.2 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Origin of Activation Source Activation Source Vector Number DTC Vector Address DTCE * Priority Software Write to DTVECR DTVECR H'0400 + (DTVECR[7:0] × 2) — High External pin IRQ0 16 H'0420 DTCEA7 IRQ1 17 H'0422 DTCEA6 IRQ2 18 H'0424 DTCEA5 IRQ3 19 H'0426 DTCEA4 IRQ4 20 H'0428 DTCEA3 IRQ5 21 H'042A DTCEA2 IRQ6 22 H'042C DTCEA1 IRQ7 23 H'042E DTCEA0 IRQ8 *

24 H'0430 DTCEB7

IRQ9 *

25 H'0432 DTCEB6

IRQ10 *

26 H'0434 DTCEB5

IRQ11 *

17 H'0436 DTCEB4

IRQ12 *

18 H'0438 DTCEB3

IRQ13 *

19 H'043A DTCEB2

IRQ14 *

30 H'043C DTCEB1

IRQ15 *

31 H'043E DTCEB0

A/D_0 ADI0 38 H'044C DTCEC6 Low

Section 9 Data Transfer Controller (DTC) Rev. 1.00 Sep. 19, 2008 Page 473 of 1270 REJ09B0466-0100 Origin of Activation Source Activation Source Vector Number DTC Vector Address DTCE * Priority TPU_0 TGI0A 40 H'0450 DTCEC5 High TGI0B 41 H'0452 DTCEC4 TGI0C 42 H'0454 DTCEC3 TGI0D 43 H'0456 DTCEC2 TPU_1 TGI1A 48 H'0460 DTCEC1 TGI1B 49 H'0462 DTCEC0 TPU_2 TGI2A 52 H'0468 DTCED7 TGI2B 53 H'046A DTCED6 TPU_3 TGI3A 56 H'0470 DTCED5 TGI3B 57 H'0472 DTCED4 TGI3C 58 H'0474 DTCED3 TGI3D 59 H'0476 DTCED2 TPU_4 TGI4A 64 H'0480 DTCED1 TGI4B 65 H'0482 DTCED0 TPU_5 TGI5A 68 H'0488 DTCEE7 TGI5B 69 H'048A DTCEE6 TMR_0 CMIA0 72 H'0490 DTCEE3 CMIB0 73 H'0492 DTCEE2 TMR_1 CMIA1 76 H'0498 DTCEE1 CMIB1 77 H'049A DTCEE0 DMAC DMTEND0A 80 H'04A0 DTCEF7 DMTEND0B 81 H'04A2 DTCEF6 DMTEND1A 82 H'04A4 DTCEF5 DMTEND1B 83 H'04A6 DTCEF4 SCI_0 RXI0 89 H'04B2 DTCEF3 TXI0 90 H'04B4 DTCEF2 SCI_1 RXI1 93 H'04BA DTCEF1 TXI1 94 H'04BC DTCEF0 SCI_2 RXI2 97 H'04C2 DTCEG7 TXI2 98 H'04C4 DTCEG6 Low

Section 9 Data Transfer Controller (DTC) Rev. 1.00 Sep. 19, 2008 Page 474 of 1270 REJ09B0466-0100 Origin of Activation Source Activation Source Vector Number DTC Vector Address DTCE * Priority SCI_3 RXI3 101 H'04CA DTCEF5 High TXI3 102 H'04CC DTCEF4 SCI_4 RXI4 105 H'04D2 DTCEG3 TXI4 106 H'04D4 DTCEG2 A/D_1 ADI1 112 H'04E0 DTCEG1 TPU_6 TGI6A 120 H'04F0 DTCEG0 TGI6B 121 H'04F2 DTCEH7 TGI6C 122 H'04F4 DTCEH6 TGI6D 123 H'04F6 DTCEH5 TPU_7 TGI7A 125 H'04FA DTCEH4 TGI7B 126 H'04FC DTCEH3 TPU_8 TGI8A 129 H'0502 DTCEH2 TGI8B 130 H'0504 DTCEH1 TPU_9 TGI9A 133 H'050A DTCEH0 TGI9B 134 H'050C DTCEI7 TGI9C 135 H'050E DTCEI6 TGI9D 136 H'0510 DTCEI5 TPU_10 TGI10A 138 H'0514 DTCEI4 TGI10B 139 H'0516 DTCEI3 TPU_11 TGI11A 142 H'051C DTCEI2 TGI11B 143 H'051E DTCEI1 Low Notes: 1. DTCE bits with no corresponding interr upt are reserved, and 0 should be written to. When clearing the software standby state or all-module-clocks-stop mode with an interrupt, write 0 to the corresponding DTCE bit. 2. Not supported by the H8S/2424 Group.

Section 9 Data Transfer Controller (DTC) Rev. 1.00 Sep. 19, 2008 Page 475 of 1270 REJ09B0466-0100

9.5 Operation

The DTC stores register information in the on-chip RAM. When activated, the DTC reads register information that is already stored in the on-chip RAM and transfers data on the basis of that register information. After the data transfer, it writes updated register information back to the on- chip RAM. Pre-storage of register information in the on-chip RAM makes it possible to transfer data over any required number of channels. There are three transfer modes: normal mode, repeat mode, and block transfer mode. Setting the CHNE bit to 1 makes it possible to perform a number of transfers with a single activation (chain transfer). A setting can also be made to have chain transfer performed only when the transfer counter value is 0. This enables DTC re-setting to be performed by the DTC itself. The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the transfer destination address. After each transfer, SAR and DAR are independently incremented, decremented, or left fixed. Figure 9.5 shows a flowchart of DTC operation, and table 9.3 summarizes the chain transfer conditions (combinations for performing the second and third transfers are omitted).

Section 9 Data Transfer Controller (DTC) Rev. 1.00 Sep. 19, 2008 Page 476 of 1270 REJ09B0466-0100 Start Read DTC vector Next transfer Read register information Data transfer Write register information Clear activation flag CHNE = 1? End No No No No No Yes Yes Yes Yes Yes Transfer counter = 0 or DISEL = 1? Clear DTCER Interrupt exception handling CHNS = 0? DISEL = 1? Transfer counter = 0? Figure 9.5 Flowchart of DTC Operation

Section 9 Data Transfer Controller (DTC) Rev. 1.00 Sep. 19, 2008 Page 477 of 1270 REJ09B0466-0100 Table 9.3 Chain Transfer Conditions 1st Transfer 2nd Transfer CHNE CHNS DISEL CR CHNE CHNS DISEL CR DTC Transfer 0 — 0 Not 0 — — — — Ends at 1st transfer 0 — 0 0 — — — — Ends at 1st transfer 0 — 1 — — — — — Interrupt request to CPU 1 0 — — 0 — 0 Not 0 Ends at 2nd transfer 0 — 0 0 Ends at 2nd transfer 0 — 1 — Interrupt request to CPU 1 1 0 Not 0 — — — — Ends at 1st transfer 1 1 — 0 0 — 0 Not 0 Ends at 2nd transfer 0 — 0 0 Ends at 2nd transfer 0 — 1 — Interrupt request to CPU 1 1 1 Not 0 — — — — Ends at 1st transfer Interrupt request to CPU

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9.5.1 Normal Mode

In normal mode, one operation transfers one byte or one word of data. Table 9.4 lists the register function in normal mode. From 1 to 65,536 transfers can be specified. Once the specified number of transfers has ended, a CPU interrupt can be requested. Table 9.4 Register Function in Normal Mode Name Abbreviation Function DTC source address register SAR Designates source address DTC destination address register DA R Designates destination address DTC transfer count register A CRA Designates transfer count DTC transfer count register B CRB Not used SAR DAR Transfer Figure 9.6 Memory Mapping in Normal Mode

Section 9 Data Transfer Controller (DTC) Rev. 1.00 Sep. 19, 2008 Page 479 of 1270 REJ09B0466-0100

9.5.2 Repeat Mode

In repeat mode, one operation transfers one byte or one word of data. Table 9.5 lists the register function in repeat mode. From 1 to 256 transfers can be specified. Once the specified number of transfers has ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated. In repeat mode the transfer counter value does not reach H'00, and therefore CPU interrupts cannot be requested when DISEL = 0. Table 9.5 Register Function in Repeat Mode Name Abbreviation Function DTC source address register SAR Designates source address DTC destination address register DA R Designates destination address DTC transfer count register AH CRAH Holds number of transfers DTC transfer count register AL CRAL Designates transfer count DTC transfer count register B CRB Not used SAR or DAR DAR or SAR Repeat area Transfer Figure 9.7 Memory Mapping in Repeat Mode

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9.5.3 Block Transfer Mode

In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. Table 9.6 lists the register function in block transfer mode. The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored. The other address register is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified. Once the specified number of transfers has ended, a CPU interrupt is requested. Table 9.6 Register Function in Block Transfer Mode Name Abbreviation Function DTC source address register SAR Designates source address DTC destination address register DA R Designates destination address DTC transfer count register AH CRAH Holds block size DTC transfer count register AL CRA L Designates block size count DTC transfer count register B CRB Designates transfer count First block Transfer Block area Nth block DAR or SAR SAR or DAR Figure 9.8 Memory Mapping in Block Transfer Mode

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9.5.4 Chain Transfer

Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 9.9 shows the operation of chain transfer. When activated, the DTC reads the register information start address stored at the vector address, and then reads the first register information at that start address. The CHNE bit in MRB is checked after the end of data transfer, if the value is 1, the next register information, which is located consecutively, is read and transfer is performed. This operation is repeated until the end of data transfer of register information with CHNE = 0. It is also possible, by setting both the CHNE bit and CHNS bit to 1, to specify execution of chain transfer only when the transfer counter value is 0. In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt source flag for the activation source is not affected. DTC vector address Register information CHNE=1 Register information CHNE=0 Register information start address Source Destination Source Destination Figure 9.9 Operation of Chain Transfer

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9.5.5 Interrupt Sources

An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control. In the case of activation by software, a software activated data transfer end interrupt (SWDTEND) is generated. When the DISEL bit is 1 and one data transfer has ended, or the specified number of transfers has ended, after data transfer ends, the SWDTE bit is held at 1 and an SWDTEND interrupt is generated. The interrupt handling routine should clear the SWDTE bit to 0. When the DTC is activated by software, an SWDTEND interrupt is not generated during a data transfer wait or during data transfer even if the SWDTE bit is set to 1.

9.5.6 Operation Timing

φ DTC activation request DTC request Address Vector read Read Write Data transfer Transfer information write Transfer information read Figure 9.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode)

Section 9 Data Transfer Controller (DTC) Rev. 1.00 Sep. 19, 2008 Page 483 of 1270 REJ09B0466-0100 φ DTC activation request DTC request Address Vector read Read Write Read Write Data transfer Transfer information write Transfer information read Figure 9.11 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2) φ DTC activation request DTC request Address Vector read Read Write Read Write Data transfer Data transfer Transfer information write Transfer information write Transfer information read Transfer information read Figure 9.12 DTC Operation Timing (Example of Chain Transfer)

9.5.7 Number of DTC Execution States

Table 9.7 lists execution status for a single DTC data transfer, and table 9.8 shows the number of states required for each execution status.

Section 9 Data Transfer Controller (DTC) Rev. 1.00 Sep. 19, 2008 Page 484 of 1270 REJ09B0466-0100 Table 9.7 DTC Execution Status Mode Vector Read I Register Information Read/Write J Data Read K Data Write L Internal Operations M Normal 1 6 1 1 3 Repeat 1 6 1 1 3 Block transfer 1 6 N N 3 Legend: N: Block size (initial setting of CRAH and CRAL) Table 9.8 Number of States Required for Each Execution Status Object to be Accessed On- Chip RAM On- Chip ROM On-Chip I/O Registers External Devices Bus width 32 16 8 16 8 16 Access states 1 1 2 2 2 3 2 3 Vector read S I — 1 — — 4 6+2m 2 3+m Register information read/write S J Byte data read S K 1 1 2 2 2 3+m 2 3+m Word data read S K 1 1 4 2 4 6+2m 2 3+m Byte data write S L 1 1 2 2 2 3+m 2 3+m Word data write S L 1 1 4 2 4 6+2m 2 3+m Execution status Internal operation S M 1 The number of execution states is calculated from the formula below. Note that Σ means the sum of all transfers activated by one activation event (the number in which the CHNE bit is set to 1, plus 1). Number of execution states = I · SI + Σ (J · SJ + K · SK + L · SL) + M · SM For example, when the DTC vector address table is located in on-chip ROM, normal mode is set, and data is transferred from the on-chip ROM to an internal I/O register, the time required for the DTC operation is 13 states. The time from activation to the end of the data write is 10 states.

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9.6 Procedures for Using DTC

9.6.1 Activation by Interrupt

The procedure for using the DTC with interrupt activation is as follows: 1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. 2. Set the start address of the register information in the DTC vector address. 3. Set the corresponding bit in DTCER to 1. 4. Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC is activated when an interrupt used as an activation source is generated. 5. After the end of one data transfer, or after the specified number of data transfers have ended, the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to continue transferring data, set the DTCE bit to 1.

9.6.2 Activation by Software

The procedure for using the DTC with software activation is as follows: 1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. 2. Set the start address of the register information in the DTC vector address. 3. Check that the SWDTE bit is 0. 4. Write 1 to SWDTE bit and the vector number to DTVECR. 5. Check the vector number written to DTVECR. 6. After the end of one data transfer, if the DISEL bit is 0 and a CPU interrupt is not requested, the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit to 1. When the DISEL bit is 1, or after the specified number of data transfers have ended, the SWDTE bit is held at 1 and a CPU interrupt is requested.

Section 9 Data Transfer Controller (DTC) Rev. 1.00 Sep. 19, 2008 Page 486 of 1270 REJ09B0466-0100

9.7 Examples of Use of the DTC

9.7.1 Normal Mode

An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. 1. Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the SCI RDR address in SAR, the start address of the RAM area where the data will be received in DAR, and 128 (H'0080) in CRA. CRB can be set to any value. 2. Set the start address of the register information at the DTC vector address. 3. Set the corresponding bit in DTCER to 1. 4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception complete (RXI) interrupt. Since the generation of a receive error during the SCI reception operation will disable subsequent reception, the CPU should be enabled to accept receive error interrupts. 5. Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is automatically cleared to 0. 6. When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt handling routine should perform wrap-up processing.

Section 9 Data Transfer Controller (DTC) Rev. 1.00 Sep. 19, 2008 Page 487 of 1270 REJ09B0466-0100

9.7.2 Chain Transfer

An example of DTC chain transfer is shown in which pulse output is performed using the PPG. Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle updating. Repeat mode transfer to NDR of the PPG is performed in the first half of the chain transfer, and normal mode transfer to the TPU's TGR in the second half. This is because clearing of the activation source and interrupt generation at the end of the specified number of transfers are restricted to the second half of the chain transfer (transfer when CHNE = 0). 1. Perform settings for transfer to NDR of the PPG. Set MRA to source address incrementing (SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), repeat mode (MD1 = 0, MD0 = 1), and word size (Sz = 1). Set the source side as a repeat area (DTS = 1). Set MRB to chain mode (CHNE = 1, DISEL = 0). Set the data table start address in SAR, the NDRH address in DAR, and the data table size in CRAH and CRAL. CRB can be set to any value. 2. Perform settings for transfer to the TPU's TGR. Set MRA to source address incrementing (SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), normal mode (MD1 = MD0 = 0), and word size (Sz = 1). Set the data table start address in SAR, the TGRA address in DAR, and the data table size in CRA. CRB can be set to any value. 3. Locate the TPU transfer register information consecutively after the NDR transfer register information. 4. Set the start address of the NDR transfer register information to the DTC vector address. 5. Set the bit corresponding to TGIA in DTCER to 1. 6. Set TGRA as an output compare register (output disabled) with TIOR, and enable the TGIA interrupt with TIER. 7. Set the initial output value in PODR, and the next output value in NDR. Set bits in DDR and NDER for which output is to be performed to 1. Using PCR, select the TPU compare match to be used as the output trigger. 8. Set the CST bit in TSTR to 1, and start the TCNT count operation. 9. Each time a TGRA compare match occurs, the next output value is transferred to NDR and the set value of the next output trigger period is transferred to TGRA. The activation source TGFA flag is cleared. 10. When the specified number of transfers are completed (the TPU transfer CRA value is 0), the TGFA flag is held at 1, the DTCE bit is cleared to 0, and a TGIA interrupt request is sent to the CPU. Termination processing should be performed in the interrupt handling routine.

Section 9 Data Transfer Controller (DTC) Rev. 1.00 Sep. 19, 2008 Page 488 of 1270 REJ09B0466-0100

9.7.3 Chain Transfer when Counter = 0

By executing a second data transfer, and performing re-setting of the first data transfer, only when the counter value is 0, it is possible to perform 256 or more repeat transfers. An example is shown in which a 128-Kbyte input buffer is configured. The input buffer is assumed to have been set to start at lower address H'0000. Figure 9.13 shows the chain transfer when the counter value is 0. 1. For the first transfer, set the normal mode for input data. Set fixed transfer source address (G/A, etc.), CRA = H'0000 (65,536 times), and CHNE = 1, CHNS = 1, and DISEL = 0. 2. Prepare the upper 8-bit addresses of the start addresses for each of the 65,536 transfer start addresses for the first data transfer in a separate area (in ROM, etc.). For example, if the input buffer comprises H'200000 to H'21FFFF, prepare H'21 and H'20. 3. For the second transfer, set repeat mode (with the source side as the repeat area) for re-setting the transfer destination address for the first data transfer. Use the upper 8 bits of DAR in the first register information area as the transfer destination. Set CHNE = DISEL = 0. If the above input buffer is specified as H'200000 to H'21FFFF, set the transfer counter to 2. 4. Execute the first data transfer 65,536 times by means of interrupts. When the transfer counter for the first data transfer reaches 0, the second data transfer is started. Set the upper 8 bits of the transfer source address for the first data transfer to H'21. The lower 16 bits of the transfer destination address of the first data transfer and the transfer counter are H'0000. 5. Next, execute the first data transfer the 65,536 times specified for the first data transfer by means of interrupts. When the transfer counter for the first data transfer reaches 0, the second data transfer is started. Set the upper 8 bits of the transfer source address for the first data transfer to H'20. The lower 16 bits of the transfer destination address of the first data transfer and the transfer counter are H'0000. 6. Steps 4 and 5 are repeated endlessly. As repeat mode is specified for the second data transfer, an interrupt request is not sent to the CPU.

Section 9 Data Transfer Controller (DTC) Rev. 1.00 Sep. 19, 2008 Page 489 of 1270 REJ09B0466-0100 First data transfer register information Second data transfer register information Chain transfer (counter = 0) Upper 8 bits of DAR Input buffer Input circuit Figure 9.13 Chain Transfer when Counter = 0

Section 9 Data Transfer Controller (DTC) Rev. 1.00 Sep. 19, 2008 Page 490 of 1270 REJ09B0466-0100

9.7.4 Software Activation

An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the destination address is H'2000. The vector number is H'60, so the vector address is H'04C0. 1. Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE = 0). Set the transfer source address (H'1000) in SAR, the destination address (H'2000) in DAR, and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB. 2. Set the start address of the register information at the DTC vector address (H'04C0). 3. Check that the SWDTE bit in DTCCR is 0. Check that there is currently no transfer activated by software. 4. Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'60. 5. Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this indicates that the write failed. This is presumably because an interrupt occurred between steps 3 and 4 and led to a different software activation. To activate this transfer, go back to step 3. 6. If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred. 7. After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear the SWDTE bit to 0 and perform other wrap-up processing.

Section 9 Data Transfer Controller (DTC) Rev. 1.00 Sep. 19, 2008 Page 491 of 1270 REJ09B0466-0100

9.8 Usage Notes

9.8.1 Module Stop Mode Setting

DTC operation can be disabled or enabled using the module stop control register. The initial setting is for DTC operation to be enabled. Register access is disabled by setting module stop mode. Module stop mode cannot be set while the DTC is activated. For details, refer to section 24, Power-Down Modes.

9.8.2 On-Chip RAM

The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. When the DTC is used, the RAME bit in SYSCR must not be cleared to 0.

9.8.3 DTCE Bit Setting

For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts are disabled, multiple activation sources can be set at one time (only at the initial setting) by writing data after executing a dummy read on the relevant register.

9.8.4 DMAC Transfer End Interrupt

When DTC transfer is activated by a DMAC transfer end interrupt, regardless of the transfer counter and DISEL bit, the DMAC's DTE bit is not subject to DTC control, and the write data has priority. Consequently, an interrupt request may not be sent to the CPU when the DTC transfer counter reaches 0.

9.8.5 Chain Transfer

When chain transfer is used, clearing of the activation source or DTCER is performed when the last of the chain of data transfers is executed. SCI and high-speed A/D converter interrupt/activation sources, on the other hand, are cleared when the DTC reads or writes to the prescribed register. Therefore, when the DTC is activated by an interrupt or activation source, if a read/write of the relevant register is not included in the last chained data transfer, the interrupt or activation source will be retained.

Section 9 Data Transfer Controller (DTC) Rev. 1.00 Sep. 19, 2008 Page 492 of 1270 REJ09B0466-0100

Rev. 1.00 Sep. 19, 2008 Page 493 of 1270 REJ09B0466-0100 Section 10 I/O Ports Table 10.1 summarizes the port functions of the H8S/2426 Group and H8S/2426R Group. Table 10.2 summarizes the port functions of the H8S/2424 Group. The pins of each port also have other functions such as input/output or external interrupt input pins of on-chip peripheral modules. Each I/O port includes a data direction register (DDR) that controls input/output, a data register (DR) that stores output data, a port register (PORT) used to read the pin states, and a port function control register (PFCR) used to set input/output destination. Before enabling each input/output pins, select the input/output destination by PFCR. The input-only ports do not have a DR or DDR register. Ports A to E have a built-in pull-up MOS function and a pull-up MOS control register (PCR) to control the on/off state of the input pull-up MOS. Ports 1 to 3, 5 to 8, and A to J include an open-drain control register (ODR) that controls the on/off state of the output buffer PMOS. Ports 1 to 3, 5 (P50 to P53), 6, and 8 can drive a single TTL load and 30-pF capacitive load. Ports A to H can drive a single TTL load and 50-pF capacitive load. All of the I/O ports can drive a Darlington transistor when outputting data. Ports 1 and 2 are Schmitt-triggered inputs.

  • H8S/2426 Group and H8S/2426R Group Ports 5 (P50 to P52), 8 (P81, P83, and P85), B, and C are Schmitt-triggered inputs when used as TPU inputs. Ports 2, 5, 6, 8, A (PA4 to PA7), F (PF1 and PF2), and H (PH2 and PH3) are Schmitt-triggered inputs when used as IRQ inputs. Ports 3 (P32 to P35) and 5 (P50 and P51) are Schmitt-triggered inputs when used as I C inputs. Ports 5 (P50 and P51), 6 (P60 to P63), and 8 (P81 and P83) are Schmitt-triggered inputs when used as 8-bit timer inputs.
  • H8S/2424 Group Ports 5 (P50 to P52), 8 (P81, P83, and P85), B, and C are Schmitt-triggered inputs when used as TPU inputs. Ports 4, 5, 8, and A (PA4 to PA7) are Schmitt-triggered inputs when used as IRQ inputs. Ports 3 (P32 to P35) and 5 (P50 and P51) are Schmitt-triggered inputs when used as I C inputs. Ports 2 (P20 to P23), 5 (P50 and P51), and 8 (P81 and P83) are Schmitt-triggered inputs when used as 8-bit timer inputs.

Rev. 1.00 Sep. 19, 2008 Page 494 of 1270 REJ09B0466-0100 Table 10.1 Port Functions of H8S/2426 Group and H8S/2426R Group Mode 7 Port Description Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Input/ Output Type P17/PO15/TIOCB2/TCLKD/EDRAK3/SCS0-A P17/PO15/TIOCB2/ TCLKD/SCS0-A P16/PO14/TIOCA2/EDRAK2/SSCK0-A P16/PO14/TIOCA2/ SSCK0-A Port 1 General I/O port also functioning as PPG outputs, TPU I/Os, EXDMAC outputs, and SSU I/Os P15/PO13/TIOCB1/TCLKC/SSI0-A P14/PO12/TIOCA1/SSO0-A P13/PO11/TIOCD0/TCLKB P12/PO10/TIOCC0/TCLKA P11/PO9/TIOCB0 P10/PO8/TIOCA0 Schmitt-triggered inputs when used as general input port and TPU inputs. Open-drain output capability. P27/IRQ15-B/PO7/TIOCB5/SCL2 P26/IRQ14-B/PO6/TIOCA5/SDA2/ADTRG1 P25/WAIT-B/IRQ13-B/PO5-A/TIOCB4-A P25/IRQ13-B/PO5-A/ TIOCB4-A Port 2 General I/O port also functioning as PPG outputs, TPU I/Os, interrupt inputs, SCI I/Os, I C I/Os, A/D converter inputs, and bus control signal I/Os P24/IRQ12-B/PO4-A/TIOCA4-A/RxD4-A P23/IRQ11-B/PO3-A/TIOCD3-A/TxD4-A P22/IRQ10-B/PO2-A/TIOCC3-A P21/IRQ9-B/PO1-A/TIOCB3-A P20/IRQ8-B/PO0-A/TIOCA3-A Schmitt-triggered inputs when used as general input port, TPU inputs, interrupt inputs, and I C inputs. Open-drain output capability. 5-V tolerance. P35/OE-B/CKE-B* /SCK1/SCL0 P35/SCK1/SCL0 Port 3 General I/O port also functioning as SCI I/Os, I C I/Os, and bus control signal I/Os P34/SCK0/SCK4-A/SDA0 P33/RxD1/SCL1 P32/RxD0/IrRxD/SDA1 P31/TxD1 P30/TxD0/IrTxD Open-drain output capability. Only P32 to P35 are Schmitt- triggered inputs when used as I C inputs. P32 to P35 have 5-V tolerance. Port 4 General I/O port also functioning as A/D converter analog inputs P47/AN7_0 P46/AN6_0 P45/AN5_0 P44/AN4_0 P43/AN3_0 P42/AN2_0 P41/AN1_0 P40/AN0_0

Rev. 1.00 Sep. 19, 2008 Page 495 of 1270 REJ09B0466-0100 Mode 7 Port Description Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Input/ Output Type P53/IRQ3-A/ADTRG0-A/TRST* P52/BACK-B/IRQ2-A/PO4-B/TIOCA4-B/ TMO0-B/SCK2 P52/IRQ2-A/PO4-B/ TIOCA4-B/TMO0-B/ SCK2 P51/BREQ-B/IRQ1-A/PO2-B/TIOCC3-B/ TMCI0-B/RxD2/SCL3 P51/IRQ1-A/PO2-B/ TIOCC3-B/TMCI0-B/ RxD2/SCL3 Port 5 General I/O port also functioning as interrupt inputs, A/D converter inputs, SCI I/Os, PPG outputs, TPU I/Os, TMR I/Os, I C I/Os, bus control signal I/Os, and JTAG inputs P50/BREQO-B/IRQ0-A/PO0-B/TIOCA3-B/ TMRI0-B/TxD2/SDA3 P50/IRQ0-A/PO0-B/ TIOCA3-B/TMRI0-B/ TxD2/SDA3 Schmitt-triggered inputs when used as IRQ inputs. Only P50 and P51 are Schmitt- triggered inputs when used as I C inputs. Open-drain output capability. Only P50 to P52 are Schmitt- triggered inputs when used as TPU inputs. Only P50 and P51 are Schmitt- triggered inputs when used as 8- bit timer inputs. P50 and P51 have 5-V tolerance. Port 6 General I/O port also functioning as interrupt inputs, TMR I/Os, and DMAC I/Os P65/IRQ13-A/DACK1/TMO1-A P64/IRQ12-A/DACK0/TMO0-A P63/IRQ11-A/TEND1/TMCI1-A P62/IRQ10-A/TEND0/TMCI0-A P61/IRQ9-A/DREQ1/TMRI1-A P60/IRQ8-A/DREQ0/TMRI0-A Schmitt-triggered inputs when used as IRQ inputs. Open-drain output capability. Only P60 to P63 are Schmitt- triggered inputs when used as 8- bit timer inputs. P85/IRQ5-B /PO5-B/TIOCB4-B/TMO1-B/SCK3/ EDACK3 P85/IRQ5-B/PO5-B/ TIOCB4-B/TMO1-B/ SCK3 P84/IRQ4-B/EDACK2 P84/I RQ4-B P83/IRQ3-B/PO3-B/TIOCD3-B/TMCI1-B/RxD3/ ETEND3 P83/IRQ3-B/PO3-B/ TIOCD3-B/TMCI1-B/ RxD3 P82/IRQ2-B/ETEND2 P82/ IRQ2-B P81/IRQ1-B/PO1-B/TIOCB3-B/ TMRI1-B/TxD3/ EDREQ3 P81/IRQ1-B/PO1-B/ TIOCB3-B/TMRI1-B/ TxD3 Port 8 General I/O port also functioning as EXDMAC I/Os, PPG outputs, TPU I/Os, TMR I/Os, SCI I/Os and interrupt inputs P80/IRQ0-B/EDREQ2 P80/ IRQ0-B Schmitt-triggered inputs when used as IRQ inputs. Open-drain output capability. Only P81, P83, and P85 are Schmitt-triggered inputs when used as TPU inputs.

Rev. 1.00 Sep. 19, 2008 Page 496 of 1270 REJ09B0466-0100 Mode 7 Port Description Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Input/ Output Type Port 9 Dedicated input port also functioning as A/D converter analog inputs and D/A converter analog outputs P97/AN15_1 P96/AN14_1 P95/AN13_1/DA3 P94/AN12_1/DA2 P93/AN11_1 P92/AN10_1 P91/AN9_1 P90/AN8_1 Port A General I/O port also functioning as address outputs, interrupt inputs, SSU I/Os, and SCI I/Os PA7/A23/IRQ7-A/ SSO0-B PA6/A22/IRQ6-A/ SSI0-B PA5/A21/IRQ5-A/ SSCK0-B A20/IRQ4-A A19 A18 A17 A16 PA7/A23/IRQ7-A/SSO0-B PA6/A22/IRQ6-A/SSI0-B PA5/A21/IRQ5-A/SSCK0-B PA4/A20/IRQ4-A/SCS0-B PA3/A19/SCK4-B PA2/A18/RxD4-B PA1/A17/TxD4-B PA0/A16 PA7/IRQ7-A/SSO0-B PA6/IRQ6-A/SSI0-B PA5/IRQ5-A/SSCK0-B PA4/IRQ4-A/SCS0-B PA3/SCK4-B PA2/RxD4-B PA1/TxD4-B PA0 Only PA4 to PA7 are Schmitt- triggered inputs when used as IRQ inputs. Built-in input pull- up MOS. Open-drain output capability. Port B General I/O port also functioning as address outputs and TPU I/Os A15 A14 A13 A12 A11 A10 PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB3/A11 PB2/A10 PB1/A9 PB0/A8 PB7/TIOCB8/TCLKH PB6/TIOCA8 PB5/TIOCB7/TCLKG PB4/TIOCA7 PB3/TIOCD6/TCLKF PB2/TIOCC6/TCLKE PB1/TIOCB6 PB0/TIOCA6 Built-in input pull- up MOS. Schmitt-triggered inputs when used as TPU inputs. Open-drain output capability. Port C General I/O port also functioning as address outputs and TPU I/Os PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 PC7/TIOCB11 PC6/TIOCA11 PC5/TIOCB10 PC4/TIOCA10 PC3/TIOCD9 PC2/TIOCC9 PC1/TIOCB9 PC0/TIOCA9 Built-in input pull- up MOS. Schmitt-triggered inputs when used as TPU inputs. Open-drain output capability.

Rev. 1.00 Sep. 19, 2008 Page 497 of 1270 REJ09B0466-0100 Mode 7 Port Description Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Input/ Output Type Port D General I/O port also functioning as data I/Os D15 D14 D13 D12 D11 D10 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Built-in input pull- up MOS. Open-drain output capability. Port E General I/O port also functioning as data I/Os PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 Built-in input pull- up MOS. Open-drain output capability. Port F General I/O port also functioning as interrupt inputs, bus control signal I/Os, SSU I/Os, and A/D converter inputs PF7/φ PF6/AS/AH RD HWR PF3/LWR/SSO0-C PF2/LCAS/DQML/IRQ15-A/SSI0-C PF1/UCAS/DQMU/IRQ14-A/SSCK0-C PF0/WAIT-A/ADTRG0-B/SCS0-C PF7/φ PF6 PF5 PF4 PF3/SSO0-C PF2/IRQ15-A/SSI0-C PF1/IRQ14-A/ SSCK0-C PF0/ADTRG0-B/ SCS0-C Only PF1 and PF2 are Schmitt- triggered inputs when used as IRQ inputs. Open-drain output capability. Port G General I/O port also functioning as bus control signal I/Os and JTAG inputs PG6/BREQ-A/TDI* PG5/BACK-A/TMS* PG4/BREQO-A/TCK* PG3/CS3/RAS3/CAS* PG2/CS2/RAS2/RAS* PG1/CS1 PG0/CS0 PG6/TDI* PG5/TMS* PG4/TCK* PG3 PG2 PG1 PG0 Open-drain output capability. Port H General I/O port also functioning as interrupt inputs and bus control signal I/Os PH3/CS7/OE-A/CKE-A* /IRQ7-B PH2/CS6/IRQ6-B PH1/CS5/RAS5/SDRAMφ* PH0/CS4/RAS4/WE* PH3/IRQ7-B PH2/IRQ6-B PH1/SDRAMφ* PH0 Only PH2 and PH3 are Schmitt- triggered inputs when used as IRQ inputs. Open-drain output capability. Port J General I/O port PJ2 * PJ1 PJ0 Open-drain output capability for only PJ0 and PJ1. 5-V tolerance.

Rev. 1.00 Sep. 19, 2008 Page 498 of 1270 REJ09B0466-0100 Notes: 1. Not supported in the H8S/2426 Group. 2. Not supported in the 145-pin package. 3. Supported only in the 145-pin package. Table 10.2 Port Functions of H8S/2424 Group Mode 7 Port Description Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Input/ Output Type Port 1 General I/O port also functioning as PPG outputs, TPU I/Os, DMAC I/Os, and SSU I/Os P17/PO15/TIOCB2/TCLKD/SCS0-A P16/PO14/TIOCA2/SSCK0-A P15/DACK1/PO13/TIOCB1/TCLKC/SSI0-A P14/DACK0/PO12/TIOCA1/SSO0-A P13/TEND1/PO11/TIOCD0/TCLKB P12/TEND0/PO10/TIOCC0/TCLKA P11/DREQ1/PO9/TIOCB0 P10/DREQ0/PO8/TIOCA0 Schmitt-triggered inputs. Open-drain output capability. P27/PO7/TIOCB5/SCL2 P26/PO6/TIOCA5/SDA2/ADTRG1 P25/WAIT-B/PO5-A/TIOCB4-A/TMO1-A P25/PO5-A/TIOCB4-A/ TMO1-A Port 2 General I/O port also functioning as PPG outputs, TPU I/Os, SCI I/Os, TMR I/Os, I C I/Os, A/D converter inputs, and bus control signal I/Os P24/PO4-A/TIOCA4-A/TMO0-A/RxD4-A P23/PO3-A/TIOCD3-A/TMCI1-A/TxD4-A P22/PO2-A/TIOCC3-A/TMCI0-A P21/PO1-A/TIOCB3-A/TMRI1-A P20/PO0-A/TIOCA3-A/TMRI0 Schmitt-triggered inputs. Open-drain output capability. 5-V tolerance. P35/OE-B/SCK1/SCL0 P35/SCK1/SCL0 Port 3 General I/O port also functioning as SCI I/Os, I C I/Os, and bus control signal I/Os P34/SCK0/SCK4-A/SDA0 P33/RxD1/SCL1 P32/RxD0/IrRxD/SDA1 P31/TxD1 P30/TxD0/IrTxD Open-drain output capability. Only P32 to P35 are Schmitt- triggered inputs when used as I C inputs. P32 to P35 have 5-V tolerance. Port 4 General I/O port also functioning as A/D converter analog inputs and interrupt inputs P47/IRQ7-B/AN7_0 P46/IRQ6-B/AN6_0 P45/IRQ5-B/AN5_0 P44/IRQ4-B/AN4_0 P43/IRQ3-B/AN3_0 P42/IRQ2-B/AN2_0 P41/IRQ1-B/AN1_0 P40/IRQ0-B/AN0_0 Schmitt-triggered inputs when used as IRQ inputs.

Rev. 1.00 Sep. 19, 2008 Page 499 of 1270 REJ09B0466-0100 Mode 7 Port Description Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Input/ Output Type P53/IRQ3-A /ADTRG0-A P52/BACK-B/IRQ2-A /PO4-B/TIOCA4-B/TMO0-B/ SCK2 P52/IRQ2-A/PO4-B/ TIOCA4-B/TMO0-B/ SCK2 P51/BREQ-B/IRQ1-A/PO2-B/TIOCC3-B/TMCI0-B/ RxD2/SCL3 P51/IRQ1-A/PO2-B/ TIOCC3-B/TMCI0-B/ RxD2/SCL3 Port 5 General I/O port also functioning as interrupt inputs, A/D converter inputs, SCI I/Os, PPG outputs, TPU I/Os, TMR I/Os, I C I/Os, and bus control signal I/Os P50/BREQO-B/IRQ0-A/PO0-B/TIOCA3-B/TMRI0-B/ TxD2/SDA3 P50/IRQ0-A/PO0-B/ TIOCA3-B/TMRI0-B/ TxD2/SDA3 Schmitt-triggered inputs when used as IRQ inputs. Only P50 and P51 are Schmitt- triggered inputs when used as I C inputs. Open-drain output capability. Only P50 to P52 are Schmitt- triggered inputs when used as TPU inputs. Only P50 and P51 are Schmitt- triggered inputs when used as 8- bit timer inputs. P50 and P51 have 5-V tolerance. Port 8 General I/O port also functioning as PPG outputs, TPU I/Os, TMR I/Os, and SCI I/Os P85/PO5-B/TIOCB4-B/TMO1-B/SCK3 P83/PO3-B/TIOCD3-B/ TMCI1-B/RxD3 P81/PO1-B/TIOCB3-B/ TMRI1-B/TxD3 Open-drain output capability. Only P81, P83, and P85 are Schmitt-triggered inputs when used as TPU inputs. Only P81 and P83 are Schmitt- triggered inputs when used as 8- bit timer inputs. P81 and P83 have 5-V tolerance. Port 9 Dedicated input port also functioning as A/D converter analog inputs and D/A converter analog outputs P95/AN13_1/DA3 P94/AN12_1/DA2

Rev. 1.00 Sep. 19, 2008 Page 500 of 1270 REJ09B0466-0100 Mode 7 Port Description Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Input/ Output Type PA7/A23/CS7/ IRQ7-A/SSO0-B PA7/A23/CS7/IRQ7A/ SSO0-B PA7/IRQ7-A/SSO0-B PA6/A22/IRQ6-A/ SSI0-B PA6/A22/IRQ6-A/SSI0-B PA6/ IRQ6-A/SSI0-B PA5/A21/IRQ5-A/ SSCK0-B PA5/A21/IRQ5-A/SSCK0-B PA5/ IRQ5-A/SSCK0-B A20/IRQ4-A PA4/A20/ IRQ4-A/SCS0-B PA4/ IRQ4-A/SCS0-B Port A General I/O port also functioning as address outputs, SSU I/Os, SCI I/Os, and bus control signal outputs A19 A18 A17 A16 PA3/A19/SCK4-B PA2/A18/RxD4-B PA1/A17/TxD4-B PA0/A16 PA3/SCK4-B PA2/RxD4-B PA1/TxD4-B PA0 Only PA4 to PA7 are Schmitt- triggered inputs when used as IRQ inputs. Built-in input pull- up MOS. Open-drain output capability. Port B General I/O port also functioning as address outputs and TPU I/Os A15 A14 A13 A12 A11 A10 PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB3/A11 PB2/A10 PB1/A9 PB0/A8 PB7/TIOCB8/TCLKH PB6/TIOCA8 PB5/TIOCB7/TCLKG PB4/TIOCA7 PB3/TIOCD6/TCLKF PB2/TIOCC6/TCLKE PB1/TIOCB6 PB0/TIOCA6 Built-in input pull- up MOS. Schmitt-triggered inputs when used as TPU inputs. Open-drain output capability. Port C General I/O port also functioning as address outputs and TPU I/Os PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 PC7/TIOCB11 PC6/TIOCA11 PC5/TIOCB10 PC4/TIOCA10 PC3/TIOCD9 PC2/TIOCC9 PC1/TIOCB9 PC0/TIOCA9 Built-in input pull- up MOS. Schmitt-triggered inputs when used as TPU inputs. Open-drain output capability. Port D General I/O port also functioning as data I/Os D15 D14 D13 D12 D11 D10 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Built-in input pull- up MOS. Open-drain output capability.

Rev. 1.00 Sep. 19, 2008 Page 501 of 1270 REJ09B0466-0100 Mode 7 Port Description Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Input/ Output Type Port E General I/O port also functioning as data I/Os PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 Built-in input pull- up MOS. Open-drain output capability. Port F General I/O port also functioning as bus control signal I/Os, SSU I/Os, and A/D converter inputs PF7/φ PF6/AS/AH RD HWR PF3/LWR/SSO0-C PF2/CS6/LCAS/SSI0-C PF1/CS5/UCAS/SSCK0-C PF0/WAIT-A/OE-A/ADTRG0-B/SCS0-C PF7/φ PF6 PF5 PF4 PF3/SSO0-C PF2/SSI0-C PF1/SSCK0-C PF0/ADTRG0-B/ SCS0-C Open-drain output capability. Port G General I/O port also functioning as bus control signal I/Os PG6/BREQ-A PG5/BACK-A PG4/BREQO-A/CS4 PG3/CS3/RAS3 PG2/CS2/RAS2 PG1/CS1 PG0/CS0 PG6 PG5 PG4 PG3 PG2 PG1 PG0 Open-drain output capability.

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10.1 Port 1

Port 1 is an 8-bit I/O port that also has other functions. Port 1 has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers.

  • Port 1 data direction register (P1DDR)
  • Port 1 data register (P1DR)
  • Port 1 register (PORT1)
  • Port 1 open drain control register (P1ODR)
  • Port function control register 5 (PFCR5)

10.1.1 Port 1 Data Direction Register (P1DDR)

The individual bits of P1DDR specify input or output for the pins of port 1. P1DDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description

7 P17DDR 0 W

6 P16DDR 0 W

5 P15DDR 0 W

4 P14DDR 0 W

3 P13DDR 0 W

2 P12DDR 0 W

1 P11DDR 0 W

0 P10DDR 0 W

When a pin function is specified as a general purpose I/O, setting this bit to 1 makes the corresponding pin an output port, while clearing this bit to 0 makes the corresponding pin an input port.

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10.1.2 Port 1 Data Register (P1DR)

P1DR stores output data for the port 1 pins. Bit Bit Name Initial Value R/W Description

7 P17DR 0 R/W

6 P16DR 0 R/W

5 P15DR 0 R/W

4 P14DR 0 R/W

3 P13DR 0 R/W

2 P12DR 0 R/W

1 P11DR 0 R/W

0 P10DR 0 R/W

Output data for a pin is stored when the pin function is specified as a general purpose I/O.

10.1.3 Port 1 Register (PORT1)

PORT1 shows the pin states of port 1. PORT1 cannot be modified. Bit Bit Name Initial Value R/W Description

7 P17 * R

6 P16 * R

5 P15 * R

4 P14 * R

3 P13 * R

2 P12 * R

1 P11 * R

0 P10 * R

If this register is read while a P1DDR bit is set to 1, the corresponding P1DR value is read. If this register is read while a P1DDR bit is cleared to 0, the corresponding pin state is read. Note: * Determined by the states of pins P17 to P10.

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10.1.4 Port 1 Open Drain Control Register (P1ODR)

P1ODR specifies the output type of each port 1 pin. Bit Bit Name Initial Value R/W Description

7 P17ODR 0 R/W

6 P16ODR 0 R/W

5 P15ODR 0 R/W

4 P14ODR 0 R/W

3 P13ODR 0 R/W

2 P12ODR 0 R/W

1 P11ODR 0 R/W

0 P10ODR 0 R/W

Setting a P1ODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a P1ODR bit to 0 makes the corresponding pin a CMOS output pin.

10.1.5 Pin Functions

Port 1 pins also function as the pins for PPG outputs, TPU I/Os, EXDMAC I/Os (H8S/2426, H8S/2426R), SSU I/Os, and DMAC I/Os (H8S/2424). The correspondence between the register specification and the pin functions is shown below. (1) Pin Functions of H8S/2426 Group and H8S/2426R Group

  • P17/PO15/TIOCB2/TCLKD/ EDRAK3/SCS0-A The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 2 settings (by bits MD3 to MD0 in TMDR_2, bits IOB3 to IOB0 in TIOR_2, and bits CCLR1 and CCLR0 in TCR_2), bits TPSC2 to TPSC0 in TCR_0 and TCR_5, bit NDER15 in NDERH of the PPG, bit EDRAKE in EDMDR_3 of the EXDMAC, bits MSS, CSS1, and CSS0 in SSCRH and bit SSUMS in SSCRL of the SSU, bits SCS0S1 and SCS0S0 in PFCR5, and bit P17DDR.

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  • Modes 1, 2, 4, and 7 (EXPE = 1) SSU settings Can be used as I/O port Input state Output state EDRAKE 0 1  TPU channel 2 settings (1) in table below (2) in table below   P17DDR  0 1 1  0  NDER15   0 1   P17 input P17 output PO15 output EDRAK3 output TIOCB2 output TIOCB2 input* Pin function TCLKD input* SCS0-A input* SCS0-A output*
  • Mode 7 (EXPE = 0) SSU settings Can be used as I/O port Input state Output state EDRAKE 0  TPU channel 2 settings (1) in table below (2) in table below  P17DDR  0 1 1 0  NDER15   0 1  P17 input P17 output PO15 outputTIOCB2 output TIOCB2 input* Pin function TCLKD input* SCS0-A input* SCS0-A output* Notes: 1. TIOCB2 input when MD3 to MD0 = B'0000 or B'01 ×× and IOB3 = 1. 2. TCLKD input when the setting for either TCR_0 or TCR_5 is TPSC2 to TPSC0 = B'111. TCLKD input when channels 2 and 4 are set to phase counting mode. 3. SCSO-A input when SCS0S1 and SCS0S0 = B'00 in PFCR5, and SSUMS, MSS, CSS1, and CSS0 = B'00××, B'0101, or B'0110. Do not set up for TPU or EXDMAC outputs with SCSO-A input. 4. SCSO-A output when SCS0S1 and SCS0S0 = B'00 in PFCR5, and SSUMS, MSS, CSS1, and CSS0 = B'011×.

Rev. 1.00 Sep. 19, 2008 Page 506 of 1270 REJ09B0466-0100 TPU channel 2 settings MD3 to MD0 B'0000, B'01 ×× B'0010 B'0011 IOB3 to IOB0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111  B' ××00 Other than B' ××00 CCLR1, CCLR0     Other than B'10 B'10 Output function  Output compare output   PWM mode 2 output SCS pin settings SSUMS 0 1 MSS 0 1 × CSS1 × 0 1 × CSS0 × 0 1 0 1 × Pin state Input  Input Automatic I/O Output  Legend: ×: Don’t care : Pin is not used by the SSU (can be used as I/O port)

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  • P16/PO14/TIOCA2/ EDRAK2/SSCK0-A The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 2 settings (by bits MD3 to MD0 in TMDR_2, bits IOA3 to IOA0 in TIOR_2, and bits CCLR1 and CCLR0 in TCR_2), bit NDER14 in NDERH of the PPG, bit EDRAKE in EDMDR_2 of the EXDMAC , bits MSS and SCKS in SSCRH and bit SSUMS in SSCRL of the SSU, bits SSCK0S1 and SSCK0S0 in PFCR5, and bit P16DDR.
  • Modes 1, 2, 4, and 7 (EXPE = 1) SSU settings Can be used as I/O port Input state Output state EDRAKE 0 1  TPU channel 2 settings (1) in table below (2) in table below   P16DDR  0 1 1  0  NDER14   0 1   P16 input P16 output PO14 output EDRAK2 output Pin function TIOCA2 output TIOCA2 input* SSCK0-A input* SSCK0-A output*
  • Mode 7 (EXPE = 0) SSU settings Can be used as I/O port Input state Output state EDRAKE 0  TPU channel 2 settings (1) in table below (2) in table below  P16DDR  0 1 1 0  NDER14   0 1  P16 input P16 output PO14 output Pin function TIOCA2 output TIOCA2 input* SSCK0-A input* SSCK0-A output*

Rev. 1.00 Sep. 19, 2008 Page 508 of 1270 REJ09B0466-0100 TPU channel 2 settings MD3 to MD0 B'0000, B'01 ×× B'001 × B'0010 B'0011 IOA3 to IOA0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B' ××00 CCLR1, CCLR0     Other than B'01 B'01 Output function  Output compare output  PWM * mode 1 output PWM mode 2 output Legend: ×: Don’t care Notes: 1. TIOCA2 input when MD3 to MD0 = B'0000 or B'01 ×× and IOA3 = 1. 2. TIOCB2 output disabled. 3. SSCK0-A input when SSCK0S1 and SSCK0S0 = B'00 in PFCR5, and SSUMS, MSS, and SCKS = B'001 or B'101. Do not set up for TPU or EXDMAC outputs with SSCK0-A input. 4. SSCK0-A output when SSCK0S1 and SSC K0S0 = B'00 in PFCR5, and SSUMS, MSS, and SCKS = B'×11. SSCK pin settings SSUMS 0 1 MSS 0 1 0 1 SCKS 0 1 0 1 0 1 0 1 Pin state  Input  Output  Input  Output Legend: : Pin is not used by the SSU (can be used as I/O port)

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  • P15/PO13/TIOCB1/TCLKC/SSI0-A The pin function is switched as shown below according to the combination of the TPU channel 1 settings (by bits MD3 to MD0 in TMDR_1, bits IOB3 to IOB0 in TIOR_1, and bits CCLR1 and CCLR0 in TCR_1), bits TPSC2 to TPSC0 in TCR_0, TCR_2, TCR_4, and TCR_5, bit NDER13 in NDERH of the PPG, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of the SSU, bits SSI0S1 and SSI0S0 in PFCR5, and bit P15DDR. SSU settings Can be used as I/O port Input state Output state TPU channel 1 settings (1) in table below (2) in table below  P15DDR  0 1 1 0  NDER13   0 1  P15 input P15 output PO13 outputTIOCB1 output TIOCB1 input* Pin function TCLKC input* SSI0-A input* SSI0-A output* Notes: 1. TIOCB1 input when MD3 to MD0 = B'0000 or B'01 ×× and IOB3 to IOB0 = B'10××. 2. TCLKC input when the setting for either TCR_0 or TCR_2 is TPSC2 to TPSC0 = B'111, or when the setting for either TCR_4 or TCR_5 is TPSC2 to TPSC0 = B'101. TCLKC input when phase counting mode is set for channels 2 and 4. 3. SSI0-A input when SSI0S1 and SSI0S0 = B'00 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'001×1 or B'10××1. Do not set up for TPU output with SSI0-A input. 4. SSI0-A output when SSI 0S1 and SSI0S0 = B'00 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'0001×. TPU channel 1 settings MD3 to MD0 B'0000, B'01 ×× B'0010 B'0011 IOB3 to IOB0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111  B' ××00 Other than B' ××00 CCLR1, CCLR0     Other than B'10 B'10 Output function  Output compare output   PWM mode 2 output Legend: ×: Don’t care

Rev. 1.00 Sep. 19, 2008 Page 510 of 1270 REJ09B0466-0100 SSI pin settings SSUMS 0 0 1 BIDE 0 1 0 MSS 0 1 0 1 0 1 TE 0 1 0 1 0 1 0 1 0 1 0 1 RE 1 0 1 1 0 1 1 0 1 0 1 0 1 1 0 1 Pin state  Output Output Input  Input     Input  Input Input  Input Legend: : Pin is not used by the SSU (can be used as I/O port)

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  • P14/PO12/TIOCA1/SSO0-A The pin function is switched as shown below according to the combination of the TPU channel 1 settings (by bits MD3 to MD0 in TMDR_1, bits IOA3 to IOA0 in TIOR_1, and bits CCLR1 and CCLR0 in TCR_1), bit NDER12 in NDERH of the PPG, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of the SSU, bits SSO0S1 and SSO0S0 in PFCR5, and bit P14DDR. SSU settings Can be used as I/O port Input state Output state TPU channel 1 settings (1) in table below (2) in table below  P14DDR  0 1 1 0  NDER12   0 1  P14 input P14 output PO12 output Pin function TIOCA1 output TIOCA1 input* SSO0-A input* SSO0-A output* TPU channel 1 settings MD3 to MD0 B'0000, B'01 ×× B'001 × B'0010 B'0011 IOA3 to IOA0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B'××00 Other than B'××00 CCLR1, CCLR0     Other than B'01 B'01 Output function  Output compare output  PWM * mode 1 output PWM mode 2 output Legend: ×: Don’t care Notes: 1. TIOCA1 input when MD3 to MD0 = B'0000 or B'01 ×× and IOA3 to IOA0 = B'10××. 2. TIOCB1 output disabled. 3. SSO0-A input when SSO0S1 and SSO0S0 = B'00 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'000×1 or B'01×01. Do not set up for TPU output with SSO0-A input. 4. SSO0-A output when SSO0S1 and SSO0S 0 = B'00 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'0011×, B'01×10, or B'10×1×.

Rev. 1.00 Sep. 19, 2008 Page 512 of 1270 REJ09B0466-0100 SSO pin settings SSUMS 0 0 1 BIDE 0 1 0 MSS 0 1 0 1 0 1 TE 0 1 0 1 0 1 0 1 0 1 0 1 RE 1 0 1 1 0 1 1 0 1 0 1 0 1 1 0 1 Pin state Input  Input  Output Output Input Output Input Output  Output Output  Output Output Legend: : Pin is not used by the SSU (can be used as I/O port)

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  • P13/PO11/TIOCD0/TCLKB The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOD3 to IOD0 in TIORL_0, and bits CCLR2 to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_2, bit NDER11 in NDERH of the PPG, and bit P13DDR. TPU channel 0 settings (1) in table below (2) in table below P13DDR  0 1 NDER11   0 1 P13 input P13 output PO11 output TIOCD0 output TIOCD0 input* Pin function TCLKB input* Notes: 1. TIOCD0 input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10××. 2. TCLKB input when the setting for any of TCR_0 to TCR_2 is TPSC2 to TPSC0 = B'101. TCLKB input when phase counting mode is set for channels 1 and 5. TPU channel 0 settings MD3 to MD0 B'0000 B'0010 B'0011 IOD3 to IOD0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111  B' ××00 Other than B' ××00 CCLR2 to CCLR0     Other than B'110 B'110 Output function  Output compare output   PWM mode 2 output Legend: ×: Don’t care

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  • P12/PO10/TIOCC0/TCLKA The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOC3 to IOC0 in TIORL_0, and bits CCLR2 to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_5, bit NDER10 in NDERH of the PPG, and bit P12DDR. TPU channel 0 settings (1) in table below (2) in table below P12DDR  0 1 NDER10   0 1 P12 input P12 output PO10 output TIOCC0 output TIOCC0 input* Pin function TCLKA input* TPU channel 0 settings MD3 to MD0 B'0000 B'001 × B'0010 B'0011 IOC3 to IOC0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B'××00 Other than B'××00 CCLR2 to CCLR0     Other than B'101 B'101 Output function  Output compare output  PWM * mode 1 output PWM mode 2 output Legend: ×: Don’t care Notes: 1. TIOCC0 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10××. 2. TCLKA input when the setting for any of TCR_0 to TCR_5 is TPSC2 to TPSC0 = B'100. TCLKA input when phase counting mode is set for channels 1 and 5. 3. TIOCD0 output disabled. Output disabl ed and settings (2) effective when BFA = 1 or BFB = 1 in TMDR_0.

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  • P11/PO9/TIOCB0 The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOB3 to IOB0 in TIORH_0, and bits CCLR2 to CCLR0 in TCR_0), bit NDER9 in NDERH of the PPG, and bit P11DDR. TPU channel 0 settings (1) in table below (2) in table below P11DDR  0 1 NDER9   0 1 P11 input P11 output PO9 output Pin function TIOCB0 output TIOCB0 input* Note: * TIOCB0 input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10 ××. TPU channel 0 settings MD3 to MD0 B'0000 B'0010 B'0011 IOB3 to IOB0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111  B' ××00 Other than B' ××00 CCLR2 to CCLR0     Other than B'010 B'010 Output function  Output compare output   PWM mode 2 output Legend: ×: Don’t care

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  • P10/PO8/TIOCA0 The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOA3 to IOA0 in TIORH_0, and bits CCLR2 to CCLR0 in TCR_0), bit NDER8 in NDERH of the PPG, and bit P10DDR. TPU channel 0 settings (1) in table below (2) in table below P10DDR  0 1 NDER8   0 1 P10 input P10 output PO8 output Pin function TIOCA0 output TIOCA0 input* TPU channel 0 settings MD3 to MD0 B'0000 B'001 × B'0010 B'0011 IOA3 to IOA0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B'××00 Other than B'××00 CCLR2 to CCLR0     Other than B'001 B'001 Output function  Output compare output  PWM * mode 1 output PWM mode 2 output Legend: ×: Don’t care Notes: 1. TIOCA0 input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10 ××. 2. TIOCB0 output disabled.

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  • P17/PO15/TIOCB2/TCLKD/ SCS0-A The pin function is switched as shown below according to the combination of the TPU channel 2 settings (by bits MD3 to MD0 in TMDR_2, bits IOB3 to IOB0 in TIOR_2, and bits CCLR1 and CCLR0 in TCR_2), bits TPSC2 to TPSC0 in TCR_0 and TCR_5, bit NDER15 in NDERH of the PPG, bits MSS, CSS1, and CSS0 in SSCRH and bit SSUMS in SSCRL of the SSU, bits SCS0S1 and SCS0S0 in PFCR5, and bit P17DDR. SSU settings Can be used as I/O port Input state Output state TPU channel 2 settings (1) in table below (2) in table below  P17DDR  0 1 1 0  NDER15   0 1  P17 input P17 output PO15 output TIOCB2 output TIOCB2 input* Pin function TCLKD input* SCS0-A input* SCS0-A output* Notes: 1. TIOCB2 input when MD3 to MD0 = B'0000 or B'01 ×× and IOB3 = 1. 2. TCLKD input when the setting for either TCR_0 or TCR_5 is TPSC2 to TPSC0 = B'111. TCLKD input when channels 2 and 4 are set to phase counting mode. 3. SCS0-A input when SCS0S1 and SCS0S0 = B'00 in PFCR5, and SSUMS, MSS, CSS1, and CSS0 = B'00××, B'0101, or B'0110. Do not set up for TPU output with SCS0-A input. 4. SCS0-A output when SCS0S1 and SCS0S0 = B'00 in PFCR5, and SSUMS, MSS, CSS1, and CSS0 = B'011×. TPU channel 2 settings MD3 to MD0 B'0000, B'01 ×× B'0010 B'0011 IOB3 to IOB0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111  B' ××00 Other than B' ××00 CCLR1, CCLR0     Other than B'10 B'10 Output function  Output compare output   PWM mode 2 output

Rev. 1.00 Sep. 19, 2008 Page 518 of 1270 REJ09B0466-0100 SCS pin settings SSUMS 0 1 MSS 0 1 × CSS1 × 0 1 × CSS0 × 0 1 0 1 × Pin state Input  Input Automatic I/O Output  Legend: ×: Don’t care : Pin is not used by the SSU (can be used as I/O port)

  • P16/PO14/TIOCA2/SSCK0-A The pin function is switched as shown below according to the combination of the TPU channel 2 settings (by bits MD3 to MD0 in TMDR_2, bits IOA3 to IOA0 in TIOR_2, and bits CCLR1 and CCLR0 in TCR_2), bit NDER14 in NDERH of the PPG, bits MSS and SCKS in SSCRH and bit SSUMS in SSCRL of the SSU, bits SSCK0S1 and SSCK0S0 in PFCR5, and bit P16DDR. SSU settings Can be used as I/O port Input state Output state TPU channel 2 settings (1) in table below (2) in table below  P16DDR  0 1 1 0  NDER14   0 1  P16 input P16 output PO14 outputPin function TIOCA2 output TIOCA2 input* SSCK0-A input* SSCK0-A output*

Rev. 1.00 Sep. 19, 2008 Page 519 of 1270 REJ09B0466-0100 TPU channel 2 settings MD3 to MD0 B'0000, B'01 ×× B'001 × B'0010 B'0011 IOA3 to IOA0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B' ××00 CCLR1, CCLR0     Other than B'01 B'01 Output function  Output compare output  PWM * mode 1 output PWM mode 2 output Legend: ×: Don’t care Notes: 1. TIOCA2 input when MD3 to MD0 = B'0000 or B'01 ×× and IOA3 = 1. 2. TIOCB2 output disabled. 3. SSCK0-A input when SSCK0S1 and SSCK0S0 = B'00 in PFCR5, and SSUMS, MSS, and SCKS = B'001 or B'101. Do not set up for TPU output with SSCK0-A input. 4. SSCK0-A output when SSCK0S1 and SSC K0S0 = B'00 in PFCR5, and SSUMS, MSS, and SCKS = B'×11. SSCK pin settings SSUMS 0 1 MSS 0 1 0 1 SCKS 0 1 0 1 0 1 0 1 Pin state  Input  Output  Input  Output Legend: : Pin is not used by the SSU (can be used as I/O port)

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  • P15/DACK1/PO13/TIOCB1/TCLKC/SSI0-A The pin function is switched as shown below according to the combination of bit SAE1 in DMABCRH of the DMAC, TPU channel 1 settings (by bits MD3 to MD0 in TMDR_1, bits IOB3 to IOB0 in TIOR_1, and bits CCLR1 and CCLR0 in TCR_1), bits TPSC2 to TPSC0 in TCR_0, TCR_2, TCR_4, and TCR_5, bit NDER13 in NDERH of the PPG, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of the SSU, bits SSI0S1 and SSI0S0 in PFCR5, and bit P15DDR. SSU settings Can be used as I/O port Input state Output state SAE1 0 1  TPU channel 1 settings (1) in table below (2) in table below   P15DDR  0 1 1  0  NDER13   0 1   P15 input P15 output PO13 output DACK1 output TIOCB1 output TIOCB1 input* Pin function TCLKC input* SSI0-A input* SSI0-A output* Notes: 1. TIOCB1 input when MD3 to MD0 = B'0000 or B'01 ×× and IOB3 to IOB0 = B'10××. 2. TCLKC input when the setting for either TCR_0 or TCR_2 is TPSC2 to TPSC0 = B'111, or when the setting for either TCR_4 or TCR_5 is TPSC2 to TPSC0 = B'101. TCLKC input when phase counting mode is set for channels 2 and 4. 3. SSI0-A input when SSI0S1 and SSI0S0 = B'00 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'001×1 or B'10××1. Do not set up for TPU or DMAC output with SSI0-A input. 4. SSI0-A output when SSI 0S1 and SSI0S0 = B'00 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'0001×.

Rev. 1.00 Sep. 19, 2008 Page 521 of 1270 REJ09B0466-0100 TPU channel 1 settings MD3 to MD0 B'0000, B'01 ×× B'0010 B'0011 IOB3 to IOB0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111  B' ××00 Other than B' ××00 CCLR1, CCLR0     Other than B'10 B'10 Output function  Output compare output   PWM mode 2 output Legend: ×: Don’t care SSI pin settings SSUMS 0 0 1 BIDE 0 1 0 MSS 0 1 0 1 0 1 TE 0 1 0 1 0 1 0 1 0 1 0 1 RE 1 0 1 1 0 1 1 0 1 0 1 0 1 1 0 1 Pin state  Output Output Input  Input     Input  Input Input  Input Legend: : Pin is not used by the SSU (can be used as I/O port)

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  • P14/DACK0/PO12/TIOCA1/SSO0-A The pin function is switched as shown below according to the combination of bit SAE0 in DMABCRH of the DMAC, TPU channel 1 settings (by bits MD3 to MD0 in TMDR_1, bits IOA3 to IOA0 in TIOR_1, and bits CCLR1 and CCLR0 in TCR_1), bit NDER12 in NDERH of the PPG, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of the SSU, bits SSO0S1 and SSO0S0 in PFCR5, and bit P14DDR. SSU settings Can be used as I/O port Input state Output state SAE0 0 1  TPU channel 1 settings (1) in table below (2) in table below   P14DDR  0 1 1  0  NDER12   0 1   P14 input P14 output PO12 output DACK0 output Pin function TIOCA1 output TIOCA1 input* SSO0-A input* SSO0-A output* TPU channel 1 settings MD3 to MD0 B'0000, B'01 ×× B'001 × B'0010 B'0011 IOA3 to IOA0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B'××00 Other than B'××00 CCLR1, CCLR0     Other than B'01 B'01 Output function  Output compare output  PWM * mode 1 output PWM mode 2 output Legend: ×: Don’t care Notes: 1. TIOCA1 input when MD3 to MD0 = B'0000 or B'01 ×× and IOA3 to IOA0 = B'10××. 2. TIOCB1 output disabled. 3. SSO0-A input when SSO0S1 and SSO0S0 = B'00 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'000×1 or B'01×01. Do not set up for TPU or DMAC output with SSO0-A input. 4. SSO0-A output when SSO0S1 and SSO0S 0 = B'00 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'0011×, B'01×10, or B'10×1×.

Rev. 1.00 Sep. 19, 2008 Page 523 of 1270 REJ09B0466-0100 SSO pin settings SSUMS 0 0 1 BIDE 0 1 0 MSS 0 1 0 1 0 1 TE 0 1 0 1 0 1 0 1 0 1 0 1 RE 1 0 1 1 0 1 1 0 1 0 1 0 1 1 0 1 Pin state Input  Input  Output Output Input Output Input Output  Output Output  Output Output Legend: : Pin is not used by the SSU (can be used as I/O port)

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  • P13/TEND1/PO11/TIOCD0/TCLKB The pin function is switched as shown below according to the combination of bit TEE1 in DMATCR of the DMAC, TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOD3 to IOD0 in TIORL_0, and bits CCLR2 to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_2, bit NDER11 in NDERH of the PPG, and bit P13DDR. TEE1 0 1 TPU channel 0 settings (1) in table below (2) in table below  P13DDR  0 1 1  NDER11   0 1  P13 input P13 output PO11 output TEND1 output TIOCD0 output TIOCD0 input* Pin function TCLKB input* Notes: 1. TIOCD0 input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10××. 2. TCLKB input when the setting for any of TCR_0 to TCR_2 is TPSC2 to TPSC0 = B'101. TCLKB input when phase counting mode is set for channels 1 and 5. TPU channel 0 settings MD3 to MD0 B'0000 B'0010 B'0011 IOD3 to IOD0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111  B' ××00 Other than B' ××00 CCLR2 to CCLR0     Other than B'110 B'110 Output function  Output compare output   PWM mode 2 output Legend: ×: Don’t care

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  • P12/TEND0/PO10/TIOCC0/TCLKA The pin function is switched as shown below according to the combination of bit TEE0 in DMATCR of the DMAC, TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOC3 to IOC0 in TIORL_0, and bits CCLR2 to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_5, bit NDER10 in NDERH of the PPG, and bit P12DDR. TEE0 0 1 TPU channel 0 settings (1) in table below (2) in table below  P12DDR  0 1 1  NDER10   0 1  P12 input P12 output PO10 output TEND0 output TIOCC0 output TIOCC0 input* Pin function TCLKA input* TPU channel 0 settings MD3 to MD0 B'0000 B'001 × B'0010 B'0011 IOC3 to IOC0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B'××00 Other than B'××00 CCLR2 to CCLR0     Other than B'101 B'101 Output function  Output compare output  PWM * mode 1 output PWM mode 2 output Legend: ×: Don’t care Notes: 1. TIOCC0 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10××. 2. TCLKA input when the setting for any of TCR_0 to TCR_5 is TPSC2 to TPSC0 = B'100. TCLKA input when phase counting mode is set for channels 1 and 5. 3. TIOCD0 output disabled. Output disabl ed and settings (2) effective when BFA = 1 or BFB = 1 in TMDR_0.

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  • P11/DREQ1/PO9/TIOCB0 The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOB3 to IOB0 in TIORH_0, and bits CCLR2 to CCLR0 in TCR_0), bit NDER9 in NDERH of the PPG, and bit P11DDR. TPU channel 0 settings (1) in table below (2) in table below P11DDR  0 1 NDER9   0 1 P11 input P11 output PO9 output TIOCB0 output TIOCB0 input* Pin function DREQ1 input Note: * TIOCB0 input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10 ××. TPU channel 0 settings MD3 to MD0 B'0000 B'0010 B'0011 IOB3 to IOB0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111  B' ××00 Other than B' ××00 CCLR2 to CCLR0     Other than B'010 B'010 Output function  Output compare output   PWM mode 2 output Legend: ×: Don’t care

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  • P10/DREQ0/PO8/TIOCA0 The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOA3 to IOA0 in TIORH_0, and bits CCLR2 to CCLR0 in TCR_0), bit NDER8 in NDERH of the PPG, and bit P10DDR. TPU channel 0 settings (1) in table below (2) in table below P10DDR  0 1 NDER8   0 1 P10 input P10 output PO8 output TIOCA0 output TIOCA0 input* Pin function DREQ0 input TPU channel 0 settings MD3 to MD0 B'0000 B'001 × B'0010 B'0011 IOA3 to IOA0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B'××00 Other than B'××00 CCLR2 to CCLR0     Other than B'001 B'001 Output function  Output compare output  PWM * mode 1 output PWM mode 2 output Legend: ×: Don’t care Notes: 1. TIOCA0 input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10 ××. 2. TIOCB0 output disabled.

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10.2 Port 2

Port 2 is an 8-bit I/O port that also has other functions. Port 2 has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers.

  • Port 2 data direction register (P2DDR)
  • Port 2 data register (P2DR)
  • Port 2 register (PORT2)
  • Port 2 open drain control register (P2ODR)
  • Port function control register 3 (PFCR3)

10.2.1 Port 2 Data Direction Register (P2DDR)

The individual bits of P2DDR specify input or output for the pins of port 2. P2DDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description

7 P27DDR 0 W

6 P26DDR 0 W

5 P25DDR 0 W

4 P24DDR 0 W

3 P23DDR 0 W

2 P22DDR 0 W

1 P21DDR 0 W

0 P20DDR 0 W

When a pin function is specified as a general purpose I/O, setting this bit to 1 makes the corresponding pin an output port, while clearing this bit to 0 makes the corresponding pin an input port.

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10.2.2 Port 2 Data Register (P2DR)

P2DR stores output data for the port 2 pins. Bit Bit Name Initial Value R/W Description

7 P27DR 0 R/W

6 P26DR 0 R/W

5 P25DR 0 R/W

4 P24DR 0 R/W

3 P23DR 0 R/W

2 P22DR 0 R/W

1 P21DR 0 R/W

0 P20DR 0 R/W

Output data for a pin is stored when the pin function is specified as a general purpose I/O.

10.2.3 Port 2 Register (PORT2)

PORT2 shows the pin states of port 2. PORT2 cannot be modified. Bit Bit Name Initial Value R/W Description

7 P27 * R

6 P26 * R

5 P25 * R

4 P24 * R

3 P23 * R

2 P22 * R

1 P21 * R

0 P20 * R

If this register is read while a P2DDR bit is set to 1, the corresponding P2DR value is read. If this register is read while a P2DDR bit is cleared to 0, the corresponding pin state is read. Note: * Determined by the states of pins P27 to P20.

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10.2.4 Port 2 Open Drain Control Register (P2ODR)

P2ODR specifies the output type of each port 2 pin. Bit Bit Name Initial Value R/W Description

7 P27ODR 0 R/W

6 P26ODR 0 R/W

5 P25ODR 0 R/W

4 P24ODR 0 R/W

3 P23ODR 0 R/W

2 P22ODR 0 R/W

1 P21ODR 0 R/W

0 P20ODR 0 R/W

Setting a P2ODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a P2ODR bit to 0 makes the corresponding pin a CMOS output pin.

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10.2.5 Pin Functions

Port 2 pins also function as the pins for PPG outputs, TPU I/Os, interrupt inputs (H8S/2426, H8S/2426R), 8-bit timer I/Os (H8S/2424), I C I/Os, and bus control signal inputs. The correspondence between the register specification and the pin functions is shown below. (1) Pin Functions of H8S/2426 Group and H8S/2426R Group

  • P27/PO7/TIOCB5/ IRQ15-B/SCL2 The pin function is switched as shown below according to the combination of the TPU channel 5 settings (by bits MD3 to MD0 in TMDR_5, bits IOB3 to IOB0 in TIOR_5, and bits CCLR1 and CCLR0 in TCR_5), bit NDER7 in NDERL of the PPG, bit ICE in ICCRA_2 of the I C, bit P27DDR, and bit ITS15 in ITSR of the interrupt controller. ICE 0 1 TPU channel 5 settings (1) in table below (2) in table below  P27DDR  0 1 1  NDER7   0 1  P27 input P27 output PO7 output SCL2 I/O TIOCB5 output TIOCB5 input* Pin function IRQ15-B interrupt input* Notes: 1. TIOCB5 input when MD3 to MD0 = B'0000 or B'01 ×× and IOB3 = 1. 2. IRQ15-B input when the ITS15 bit in ITSR is 1.

Rev. 1.00 Sep. 19, 2008 Page 532 of 1270 REJ09B0466-0100 TPU channel 5 settings MD3 to MD0 B'0000, B'01 ×× B'0010 B'0011 IOB3 to IOB0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111  B' ××00 Other than B' ××00 CCLR1, CCLR0     Other than B'10 B'10 Output function  Output compare output   PWM mode 2 output Legend: ×: Don’t care

  • P26/PO6/TIOCA5/ IRQ14-B/SDA2/ADTRG1 The pin function is switched as shown below according to the combination of the TPU channel 5 settings (by bits MD3 to MD0 in TMDR_5, bits IOA3 to IOA0 in TIOR_5, and bits CCLR1 and CCLR0 in TCR_5), bit NDER6 in NDERL of the PPG, bits TRGS1, TRGS0, and EXTRGS in ADCR_1 of the ADC, bit ICE in ICCRA_2 of the I C, bit P26DDR, and bit ITS14 in ITSR of the interrupt controller. ICE 0 1 TPU channel 5 settings (1) in table below (2) in table below  P26DDR  0 1 1  NDER6   0 1  P26 input P26 output PO6 output TIOCA5 output TIOCA5 input* SDA2 I/O IRQ14-B interrupt input* Pin function ADTRG1 input*

Rev. 1.00 Sep. 19, 2008 Page 533 of 1270 REJ09B0466-0100 TPU channel 5 settings MD3 to MD0 B'0000, B'01 ×× B'001 × B'0010 B'0011 IOA3 to IOA0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B'××00 Other than B'××00 CCLR1, CCLR0     Other than B'01 B'01 Output function  Output compare output  PWM * mode 1 output PWM mode 2 output Legend: ×: Don’t care Notes: 1. TIOCA5 input when MD3 to MD0 = B'0000 or B'01 ×× and IOA3 = 1. 2. IRQ14-B input when the ITS14 bit in ITSR is 1. 3. TIOCB5 output disabled. 4. ADTRG1 input when EXTRGS = 0 and TRGS1 = TRGS0 = 1.

  • P25/PO5-A/TIOCB4-A/ IRQ13-B/WAIT-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit WAITE in BCR of the bus controller, TPU channel 4 settings (by bits MD3 to MD0 in TMDR_4, bits IOB3 to IOB0 in TIOR_4, and bits CCLR1 and CCLR0 in TCR_4), bit NDER5 in NDERL of the PPG, bits PPGS, TPUS, and TMRS in PFCR3, bit WAITS in PFCR4, bit P25DDR, and bit ITS13 in ITSR of the interrupt controller.
  • Modes 1, 2, 4, and 7 (EXPE = 1) WAITE 0 1 TPU channel 4 settings (1) in table below (2) in table below  P25DDR  0 1 1  NDER5   0 1  P25 input P25 output PO5-A output * TIOCB4-A output* TIOCB4-A input* WAIT-B input* Pin function IRQ13-B interrupt input*

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  • Mode 7 (EXPE = 0) WAITE  TPU channel 4 settings (1) in table below (2) in table below P25DDR  0 0 1 NDER5    0 P25 input P25 output PO5-A output * TIOCB4-A output* TIOCB4-A input* Pin function IRQ13-B interrupt input* Notes: 1. TIOCB4-A input when MD3 to MD0 = B'0000 or B'01 ×× and IOB3 to IOB0 = B'10××. 2. IRQ13-B input when the ITS13 bit in ITSR is 1. 3. PO5-A output when the PPGS bit in PFCR3 is 0. 4. TIOCB4-A input/output when the TPUS bit in PFCR3 is 0. 5. WAIT-B input when the WAITS bit in PFCR4 is 1. TPU channel 4 settings MD3 to MD0 B'0000, B'01 ×× B'0010 B'0011 IOB3 to IOB0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111  B' ××00 Other than B' ××00 CCLR1, CCLR0     Other than B'10 B'10 Output function  Output compare output   PWM mode 2 output Legend: ×: Don’t care

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  • P24/IRQ12-B/PO4-A/TIOCA4-A/RxD4-A The pin function is switched as shown below according to the combination of the TPU channel 4 settings (by bits MD3 to MD0 in TMDR_4, bits IOA3 to IOA0 in TIOR_4, and bits CCLR1 and CCLR0 in TCR_4), bit NDER4 in NDERL of the PPG, bit RE in SCR_4 of the SCI, bits PPGS and TPUS in PFCR3, bit RXD4S in PFCR4, bit P24DDR, and bit ITS12 in ITSR of the interrupt controller TPU channel 4 settings (1) in table below (2) in table below RE  0 1 P24DDR  0 1  NDER4   0 1  P24 input P24 output PO4-A output * RxD4-A input* TIOCA4-A output* TIOCA4-A input* Pin function IRQ12-B interrupt input* TPU channel 4 settings MD3 to MD0 B'0000, B'01 ×× B'001 × B'0010 B'0011 IOA3 to IOA0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B'××00 Other than B'××00 CCLR1, CCLR0     Other than B'01 B'01 Output function  Output compare output  PWM * mode 1 output PWM mode 2 output Legend: ×: Don’t care Notes: 1. TIOCA4-A input when MD3 to MD0 = B'0000 or B'01 ×× and IOA3 to IOA0 = B'10××. 2. IRQ12-B input when the ITS12 bit in ITSR is 1. 3. TIOCB4 output disabled. 4. PO4-A output when the PPGS bit in PFCR3 is 0. 5. TIOCA4-A input/output when the TPUS bit in PFCR3 is 0. 6. RxD4-A input when the RXD4S bit in PFCR4 is 0.

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  • P23/IRQ11-B/PO3-A/TIOCD3-A/TxD4-A The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOD3 to IOD0 in TIORL_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER3 in NDERL of the PPG, bit TE in SCR_4 of the SCI, bits PPGS and TPUS in PFCR3, bit TXD4S in PFCR4, bit P23DDR, and bit ITS11 in ITSR of the interrupt controller. TPU channel 3 settings (1) in table below (2) in table below TE  0 1 P23DDR  0 1  NDER3   0 1  P23 input P23 output PO3-A output * TxD4-A output* TIOCD3-A output* TIOCD3-A input* Pin function IRQ11-B interrupt input* Notes: 1. TIOCD3-A input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10 ××. 2. IRQ11-B input when the ITS11 bit in ITSR is 1. 3. PO3-A output when the PPGS bit in PFCR3 is 0. 4. TIOCD3-A input/output when the TPUS bit in PFCR3 is 0. 5. TxD4-A output when the TXD4S bit in PFCR4 is 0. TPU channel 3 settings MD3 to MD0 B'0000 B'0010 B'0011 IOD3 to IOD0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111  B' ××00 Other than B' ××00 CCLR2 to CCLR0     Other than B'110 B'110 Output function  Output compare output   PWM mode 2 output Legend: ×: Don’t care

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  • P22/IRQ10-B /PO2-A/TIOCC3-A The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOC3 to IOC0 in TIORL_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER2 in NDERL of the PPG, bits PPGS and TPUS in PFCR3, bit P22DDR, and bit ITS10 in ITSR of the interrupt controller. TPU channel 3 settings (1) in table below (2) in table below P22DDR  0 1 NDER2   0 1 P22 input P22 output PO2-A output * TIOCC3-A output* TIOCC3-A input* Pin function IRQ10-B interrupt input* TPU channel 3 settings MD3 to MD0 B'0000 B'001 × B'0010 B'0011 IOC3 to IOC0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B'××00 Other than B'××00 CCLR2 to CCLR0     Other than B'101 B'101 Output function  Output compare output  PWM * mode 1 output PWM mode 2 output Legend: ×: Don’t care Notes: 1. TIOCC3-A input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10 ××. 2. IRQ10-B input when the ITS10 bit in ITSR is 1. 3. TIOCD3 output disabled. Output disabl ed and settings (2) effective when BFA = 1 or BFB = 1 in TMDR_3. 4. PO2-A output when the PPGS bit in PFCR3 is 0. 5. TIOCC3-A input/output when the TPUS bit in PFCR3 is 0.

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  • P21/IRQ9-B/PO1-A/TIOCB3-A The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOB3 to IOB0 in TIORH_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER1 in NDERL of the PPG, bits PPGS and TPUS in PFCR3, bit P21DDR, and bit ITS9 in ITSR of the interrupt controller. TPU channel 3 settings (1) in table below (2) in table below P21DDR  0 1 NDER1   0 1 P21 input P21 output PO1-A output * TIOCB3-A output* TIOCB3-A input* Pin function IRQ9-B interrupt input* Notes: 1. TIOCB3-A input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10 ××. 2. IRQ9-B input when the ITS9 bit in ITSR is 1. 3. PO1-A output when the PPGS bit in PFCR3 is 0. 4. TIOCB3-A input/output when the TPUS bit in PFCR3 is 0. TPU channel 3 settings MD3 to MD0 B'0000 B'0010 B'0011 IOB3 to IOB0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111  B' ××00 Other than B' ××00 CCLR2 to CCLR0     Other than B'010 B'010 Output function  Output compare output   PWM mode 2 output Legend: ×: Don’t care

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  • P20/PO0-A/TIOCA3-A/ IRQ8-B* The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOA3 to IOA0 in TIORH_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER0 in NDERL of the PPG, bits PPGS and TPUS in PFCR3, bit P20DDR, and bit ITS8 in ITSR of the interrupt controller. TPU channel 3 settings (1) in table below (2) in table below P20DDR  0 1 NDER0   0 1 P20 input P20 output PO0-A output * TIOCA3-A output* TIOCA3-A input* Pin function IRQ8-B interrupt input* TPU channel 3 settings MD3 to MD0 B'0000 B'001 × B'0010 B'0011 IOA3 to IOA0 B'0000, B'0100, B'1××× B'0001 to B'0011 B'0101 to B'0111 B'××00 Other than B'××00 Other than B'××00 CCLR2 to CCLR0     Other than B'001 B'001 Output function  Output compare output  PWM * mode 1 output PWM mode 2 output Legend: ×: Don’t care Notes: 1. TIOCA3-A input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10 ××. 2. IRQ8-B input when the ITS8 bit in ITSR is 1. 3. TIOCB3 output disabled. 4. PO0-A output when the PPGS bit in PFCR3 is 0. 5. TIOCA3-A input/output when the TPUS bit in PFCR3 is 0.

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  • P27/PO7/TIOCB5/SCL2 The pin function is switched as shown below according to the combination of the TPU channel 5 settings (by bits MD3 to MD0 in TMDR_5, bits IOB3 to IOB0 in TIOR_5, and bits CCLR1 and CCLR0 in TCR_5), bit NDER7 in NDERL of the PPG, bit ICE in ICCRA_2 of the I and bit P27DDR. ICE 0 1 TPU channel 5 settings (1) in table below (2) in table below  P27DDR  0 1 1  NDER7   0 1  P27 input P27 output PO7 output SCL2 I/O Pin function TIOCB5 output TIOCB5 input* Note: * TIOCB5 input when MD3 to MD0 = B'0000 or B'01 ×× and IOB3 = 1. TPU channel 5 settings MD3 to MD0 B'0000, B'01 ×× B'0010 B'0011 IOB3 to IOB0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111  B' ××00 Other than B' ××00 CCLR1, CCLR0     Other than B'10 B'10 Output function  Output compare output   PWM mode 2 output Legend: ×: Don’t care

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  • P26/PO6/TIOCA5/SDA2/ ADTRG1 The pin function is switched as shown below according to the combination of the TPU channel 5 settings (by bits MD3 to MD0 in TMDR_5, bits IOA3 to IOA0 in TIOR_5, and bits CCLR1 and CCLR0 in TCR_5), bit NDER6 in NDERL of the PPG, bits TRGS1, TRGS0, and EXTRGS in ADCR_1 of the ADC, bit ICE in ICCRA_2 of the I C, and bit P26DDR. ICE 0 1 TPU channel 5 settings (1) in table below (2) in table below  P26DDR  0 1 1  NDER6   0 1  P26 input P26 output PO6 output TIOCA5 output TIOCA5 input* SDA2 I/O Pin function ADTRG1 input* TPU channel 5 settings MD3 to MD0 B'0000, B'01 ×× B'001 × B'0010 B'0011 IOA3 to IOA0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B'××00 Other than B'××00 CCLR1, CCLR0     Other than B'01 B'01 Output function  Output compare output  PWM * mode 1 output PWM mode 2 output Legend: ×: Don’t care Notes: 1. TIOCA5 input when MD3 to MD0 = B'0000 or B'01 ×× and IOA3 = 1. 2. TIOCB5 output disabled. 3. ADTRG1 input when EXTRGS = 0 and TRGS1 = TRGS0 = 1.

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  • P25/WAIT-B/PO5-A/TIOCB4-A/TMO1-A The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit WAITE in BCR of the bus controller, TPU channel 4 settings (by bits MD3 to MD0 in TMDR_4, bits IOB3 to IOB0 in TIOR_4, and bits CCLR1 and CCLR0 in TCR_4), bits OS3 to OS0* in TCSR_1 of the 8-bit timer, bit NDER5 in NDERL of the PPG, bits PPGS, TPUS, and TMRS in PFCR3, bit WAITS in PFCR4, and bit P25DDR.
  • Modes 1, 2, 4, and 7 (EXPE = 1) WAITE 0 1 TPU channel 4 settings (1) in table below (2) in table below  OS3 to OS0  All 0 Not all 0  P25DDR  0 1 1   NDER5   0 1   P25 input P25 output PO5-A output* TMO1-A output* WAIT-B input* Pin function TIOCB4-A output* TIOCB4-A input*
  • Mode 7 (EXPE = 0) WAITE  TPU channel 4 settings (1) in table below (2) in table below OS3 to OS0  All 0 Not all 0 P25DDR  0 0 1 1 NDER5    0 1 P25 input P25 output PO5-A output * TIO1-A output* Pin function TIOCB4-A output* TIOCB4-A input* Notes: 1. TIOCB4-A input when MD3 to MD0 = B'0000 or B'01 ×× and IOB3 to IOB0 = B'10××. 2. PO5-A output when the PPGS bit in PFCR3 is 0. 3. TIOCB4-A input/output when the TPUS bit in PFCR3 is 0. 4. TMO1-A output when the TMRS bit in PFCR3 is 0. 5. WAIT-B input when the WAITS bit in PFCR4 is 1.

Rev. 1.00 Sep. 19, 2008 Page 543 of 1270 REJ09B0466-0100 TPU channel 4 settings MD3 to MD0 B'0000, B'01 ×× B'0010 B'0011 IOB3 to IOB0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111  B' ××00 Other than B' ××00 CCLR1, CCLR0     Other than B'10 B'10 Output function  Output compare output   PWM mode 2 output Legend: ×: Don’t care

  • P24/PO4-A/TIOCA4-A/TMO0-A/RxD4-A The pin function is switched as shown below according to the combination of bits OS3 to OS0 in TCSR_0 of the 8-bit timer, TPU channel 4 settings (by bits MD3 to MD0 in TMDR_4, bits IOA3 to IOA0 in TIOR_4, and bits CCLR1 and CCLR0 in TCR_4), bit NDER4 in NDERL of the PPG, bit RE in SCR_4 of the SCI, bits PPGS, TPUS, and TMRS in PFCR3, bit RXD4S in PFCR4, and bit P24DDR. TPU channel 4 settings (1) in table below (2) in table below OS3 to OS0  All 0 Not all 0 RE  0 1  P24DDR  0 1 1   NDER4   0 1   P24 input P24 output PO4-A output* RxD4-A input* TMO0-A output* Pin function TIOCA4-A output* TIOCA4-A input*

Rev. 1.00 Sep. 19, 2008 Page 544 of 1270 REJ09B0466-0100 TPU channel 4 settings MD3 to MD0 B'0000, B'01 ×× B'001 × B'0010 B'0011 IOA3 to IOA0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B'××00 Other than B'××00 CCLR1, CCLR0     Other than B'01 B'01 Output function  Output compare output  PWM * mode 1 output PWM mode 2 output Legend: ×: Don’t care Notes: 1. TIOCA4-A input when MD3 to MD0 = B'0000 or B'01 ×× and IOA3 to IOA0 = B'10××. 2. TIOCB4 output disabled. 3. PO4-A output when the PPGS bit in PFCR3 is 0. 4. TIOCA4-A input/output when the TPUS bit in PFCR3 is 0. 5. TMO0-A output when the TMRS bit in PFCR3 is 0. 6. RxD4-A input when the RXD4S bit in PFCR4 is 0.

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  • P23/PO3-A/TIOCD3-A/TMCI1-A/TxD4-A The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOD3 to IOD0 in TIORL_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER3 in NDERL of the PPG, bit TE in SCR_4 of the SCI, bits PPGS, TPUS, and TMRS in PFCR3, bit TXD4S in PFCR4, and bit P23DDR. TPU channel 3 settings (1) in table below (2) in table below TE  0 1 P23DDR  0 1  NDER3   0 1  P23 input P23 output PO3-A output * TxD4-A output* TIOCD3-A output* TIOCD3-A input* Pin function TMCI1-A input* Notes: 1. TIOCD3-A input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10 ××. 2. PO3-A output when the PPGS bit in PFCR3 is 0. 3. TIOCD3-A input/output when the TPUS bit in PFCR3 is 0. 4. TMCI1-A input when the TMRS bit in PFCR3 is 0. 5. TxD4-A output when the TXD4S bit in PFCR4 is 0. TPU channel 3 settings MD3 to MD0 B'0000 B'0010 B'0011 IOD3 to IOD0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111  B' ××00 Other than B' ××00 CCLR2 to CCLR0     Other than B'110 B'110 Output function  Output compare output   PWM mode 2 output Legend: ×: Don’t care

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  • P22/PO2-A/TIOCC3-A/TMCI0-A The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOC3 to IOC0 in TIORL_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER2 in NDERL of the PPG, bits PPGS, TPUS, and TMRS in PFCR3, and bit P22DDR. TPU channel 3 settings (1) in table below (2) in table below P22DDR  0 1 NDER2   0 1 P22 input P22 output PO2-A output * TIOCC3-A output* TIOCC3-A input* Pin function TMCI0-A input* TPU channel 3 settings MD3 to MD0 B'0000 B'001 × B'0010 B'0011 IOC3 to IOC0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B'××00 Other than B'××00 CCLR2 to CCLR0     Other than B'101 B'101 Output function  Output compare output  PWM * mode 1 output PWM mode 2 output Legend: ×: Don’t care Notes: 1. TIOCC3-A input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10 ××. 2. TIOCD3 output disabled. Output disabl ed and settings (2) effective when BFA = 1 or BFB = 1 in TMDR_3. 3. PO2-A output when the PPGS bit in PFCR3 is 0. 4. TIOCC3-A input/output when the TPUS bit in PFCR3 is 0. 5. TMCI0-A input when the TMRS bit in PFCR3 is 0.

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  • P21/PO1-A/TIOCB3-A/TMRI1-A The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOB3 to IOB0 in TIORH_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER1 in NDERL of the PPG, bits PPGS, TPUS, and TMRS in PFCR3, and bit P21DDR. TPU channel 3 settings (1) in table below (2) in table below P21DDR  0 1 NDER1   0 1 P21 input P21 output PO1-A output * TIOCB3-A output* TIOCB3-A input* Pin function TMRI1-A input* Notes: 1. TIOCB3-A input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10 ××. 2. PO1-A output when the PPGS bit in PFCR3 is 0. 3. TIOCB3-A input/output when the TPUS bit in PFCR3 is 0. 4. TMRI1-A input when the TMRS bit in PFCR3 is 0. TPU channel 3 settings MD3 to MD0 B'0000 B'0010 B'0011 IOB3 to IOB0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111  B' ××00 Other than B' ××00 CCLR2 to CCLR0     Other than B'010 B'010 Output function  Output compare output   PWM mode 2 output Legend: ×: Don’t care

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  • P20/PO0-A/TIOCA3-A/TMRI0-A The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOA3 to IOA0 in TIORH_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER0 in NDERL of the PPG, bits PPGS, TPUS, and TMRS in PFCR3, and bit P20DDR. TPU channel 3 settings (1) in table below (2) in table below P20DDR  0 1 NDER0   0 1 P20 input P20 output PO0-A output * TIOCA3-A output* TIOCA3-A input* Pin function TMRI0-A input* TPU channel 3 settings MD3 to MD0 B'0000 B'001 × B'0010 B'0011 IOA3 to IOA0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B'××00 Other than B'××00 CCLR2 to CCLR0     Other than B'001 B'001 Output function  Output compare output  PWM * mode 1 output PWM mode 2 output Legend: ×: Don’t care Notes: 1. TIOCA3-A input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10 ××. 2. TIOCB3 output disabled. 3. PO0-A output when the PPGS bit in PFCR3 is 0. 4. TIOCA3-A input/output when the TPUS bit in PFCR3 is 0. 5. TMRI0-A input when the TMRS bit in PFCR3 is 0.

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10.3 Port 3

Port 3 is a 6-bit I/O port that also has other functions. Port 3 has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers.

  • Port 3 data direction register (P3DDR)
  • Port 3 data register (P3DR)
  • Port 3 register (PORT3)
  • Port 3 open drain control register (P3ODR)
  • Port function control register 2 (PFCR2)

10.3.1 Port 3 Data Direction Register (P3DDR)

The individual bits of P3DDR specify input or output for the pins of port 3. P3DDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description 7, 6  All 0  Reserved

5 P35DDR 0 W

4 P34DDR 0 W

3 P33DDR 0 W

2 P32DDR 0 W

1 P31DDR 0 W

0 P30DDR 0 W

When a pin function is specified as a general purpose I/O, setting this bit to 1 makes the corresponding pin an output port, while clearing this bit to 0 makes the corresponding pin an input port.

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10.3.2 Port 3 Data Register (P3DR)

P3DR stores output data for the port 3 pins. Bit Bit Name Initial Value R/W Description 7, 6  All 0  Reserved These bits are always read as 0 and cannot be modified.

5 P35DR 0 R/W

4 P34DR 0 R/W

3 P33DR 0 R/W

2 P32DR 0 R/W

1 P31DR 0 R/W

0 P30DR 0 R/W

Output data for a pin is stored when the pin function is specified as a general purpose I/O.

10.3.3 Port 3 Register (PORT3)

PORT3 shows the pin states of port 3. PORT3 cannot be modified. Bit Bit Name Initial Value R/W Description 7, 6  Undefined  Reserved If these bits are read, they will return an undefined value.

5 P35 * R

4 P34 * R

3 P33 * R

2 P32 * R

1 P31 * R

0 P30 * R

If this register is read while a P3DDR bit is set to 1, the corresponding P3DR value is read. If this register is read while a P3DDR bit is cleared to 0, the corresponding pin state is read. Note: * Determined by the states of pins P35 to P30.

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10.3.4 Port 3 Open Drain Control Register (P3ODR)

P3ODR specifies the output type of each port 3 pin. Bit Bit Name Initial Value R/W Description 7, 6  All 0  Reserved These bits are always read as 0. Only the initial values should be written to these bits.

5 P35ODR 0 R/W

4 P34ODR 0 R/W

3 P33ODR 0 R/W

2 P32ODR 0 R/W

1 P31ODR 0 R/W

0 P30ODR 0 R/W

When OE-B/CKE-B output is not selected, setting a P3ODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a P3ODR bit to 0 makes the corresponding pin a CMOS output pin.

10.3.5 Pin Functions

Port 3 pins also function as the pins for SCI I/Os, I C I/Os, and bus control signal outputs. The correspondence between the register specification and the pin functions is shown below.

  • P35/OE-B/CKE-B* /SCK1/SCL0 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit ICE in ICCRA_0 of the I C, bit C/A in SMR_1 and bits CKE0 and CKE1 in SCR_1 of the SCI, bits OEE and RMTS2 to RMTS0 in DRAMCR of the bus controller, bit OES in PFCR2, and bit P35DDR.

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  • Modes 1, 2, 4, and 7 (EXPE = 1) OEE 0 1 OES  1 0 RMTS2 to RMTS0   Areas 2 to 5 are DRAM space Areas 2 to 5 are continu- ous SDRAM space ICE 0 1 0 1  CKE1 0 1  0 1   Pin function P35 input P35 output* SCK1 output* SCK1 output* SCK1 input SCL0 I/O* P35 input P35 output* SCK1 output* SCK1 output* SCK1 input SCL0 I/O* OE-B output* CKE-B output*
  • Mode 7 (EXPE = 0) OEE 0 OES  RMTS2 to RMTS0 ICE 0 1 CKE1 0 1  C/A 0 1   CKE0 0 1    P35DDR 0 1     Pin function P35 input P35 output* SCK1 output* SCK1 output* SCK1 input SCL0 I/O* Notes: 1. NMOS open-drain output when P35ODR = 1. 2. NMOS open-drain output regardless of P35ODR. 3. OE-B/CKE-B output when the OES bit in PFCR2 is 0. 4. Not supported in the H8 S/2426 Group and H8S/2424 Group.

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  • P34/SCK0/SCK4-A/SDA0 The pin function is switched as shown below according to the combination of bit ICE in ICCRA_0 of the I C, bit C/A in SMR_0 and bits CKE0 and CKE1 in SCR_0 and SCR_4 of the SCI, and bit P34DDR. ICE 0 1 CKE1 0 1  C/A 0 1   CKE0 0 1    P34DDR 0 1     Pin function P34 input P34 output* SCK0/SCK4-A output* SCK0/SCK4-A output* SCK0/SCK4-A input* SDA0 I/O* Notes: 1. NMOS open-drain output when P34ODR = 1. 2. NMOS open-drain output regardless of P34ODR. 3. Simultaneous output of SCK0 and SCK4 cannot be set. 4. SCK4-A input/output when the SCK4S bit in PFCR4 is 0.
  • P33/RxD1/SCL1 The pin function is switched as shown below according to the combination of bit ICE in ICCRA_1 of the I C, bit RE in SCR_1 of the SCI, and bit P33DDR. ICE 0 1 RE 0 1  P33DDR 0 1   Pin function P33 input P33 output * RxD1 input SCL1 I/O * Notes: 1. NMOS open-drain output when P33ODR = 1. 2. NMOS open-drain output regardless of P33ODR.

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  • P32/RxD0/IrRxD/SDA1 The pin function is switched as shown below according to the combination of bit ICE in ICCRA_1 of the I C, bit RE in SCR_0 of the SCI, and bit P32DDR. ICE 0 1 RE 0 1  P32DDR 0 1   Pin function P32 input P32 output * RxD0/IrRxD input SDA1 I/O * Notes: 1. NMOS open-drain output when P32ODR = 1. 2. NMOS open-drain output regardless of P32ODR.
  • P31/TxD1 The pin function is switched as shown below according to the combination of bit TE in SCR_1 of the SCI and bit P31DDR. TE 0 1 P31DDR 0 1  Pin function P31 input P31 output * TxD1 output * Note: * NMOS open-drain output when P31ODR = 1.
  • P30/TxD0/IrTxD The pin function is switched as shown below according to the combination of bit TE in SCR_0 of the SCI and bit P30DDR. TE 0 1 P30DDR 0 1  Pin function P30 input P30 output * TxD0/IrTxD output * Note: * NMOS open-drain output when P30ODR = 1.

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10.4 Port 4

Port 4 is an 8-bit input-only port that also has other functions, such as analog input pins. Port 4 has the following register.

  • Port 4 register (PORT4)

10.4.1 Port 4 Register (PORT4)

PORT4 is an 8-bit read-only register that shows the pin states of port 4. PORT4 cannot be modified. Bit Bit Name Initial Value R/W Description

7 P47 * R

6 P46 * R

5 P45 * R

4 P44 * R

3 P43 * R

2 P42 * R

1 P41 * R

0 P40 * R

The pin states are always read from this register. Note: * Determined by the states of pins P47 to P40.

10.4.2 Pin Functions

Port 4 also functions as the pins for A/D converter analog inputs and interrupt inputs (the H8S/2424 Group). The correspondence between pins is as follows. (1) Pin Functions of H8S/2426 Group and H8S/2426R Group

  • P40/AN0_0, P41/AN1_0, P42/AN2_0, P43/AN3_0, P44/AN4_0, P45/AN5_0, P46/AN6_0, P47/AN7_0 Pin function ANn_0 input Legend: n = 7 to 0

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  • P47/IRQ7-B/AN7_0 AN7_0 input Pin function IRQ7-B interrupt input*
  • P46/IRQ6-B/AN6_0 AN6_0 input Pin function IRQ6-B interrupt input*
  • P45/IRQ5-B/AN5_0 AN5_0 input Pin function IRQ5-B interrupt input*
  • P44/IRQ4-B/AN4_0 AN4_0 input Pin function IRQ4-B interrupt input*
  • P43/IRQ3-B/AN3_0 AN3_0 input Pin function IRQ3-B interrupt input*
  • P42/IRQ2-B/AN2_0 AN2_0 input Pin function IRQ2-B interrupt input*
  • P41/IRQ1-B/AN1_0 AN1_0 input Pin function IRQ1-B interrupt input*
  • P40/IRQ0-B/AN0_0 AN0_0 input Pin function IRQ0-B interrupt input* Note: * IRQn input when the ITSn bit in ITSR is 1. (n = 7 to 0)

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10.5 Port 5

Port 5 is a 4-bit I/O port. Port 5 has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers.

  • Port 5 data direction register (P5DDR)
  • Port 5 data register (P5DR)
  • Port 5 register (PORT5)
  • Port 5 open drain control register (P5ODR)
  • Port function control register 4 (PFCR4)

10.5.1 Port 5 Data Direction Register (P5DDR)

The individual bits of P5DDR specify input or output for the pins of port 5. P5DDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description 7 to 4  All 0  Reserved

3 P53DDR 0 W

2 P52DDR 0 W

1 P51DDR 0 W

0 P50DDR 0 W

When a pin function is specified as a general purpose I/O, setting this bit to 1 makes the corresponding pin an output port, while clearing this bit to 0 makes the corresponding pin an input port.

10.5.2 Port 5 Data Register (P5DR)

P5DR stores output data for the port 5 pins. Bit Bit Name Initial Value R/W Description 7 to 4  All 0  Reserved These bits are always read as 0 and cannot be modified.

3 P53DR 0 R/W

2 P52DR 0 R/W

1 P51DR 0 R/W

0 P50DR 0 R/W

Output data for a pin is stored when the pin function is specified as a general purpose I/O.

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10.5.3 Port 5 Register (PORT5)

PORT5 shows the pin states of port 5. PORT5 cannot be modified. Bit Bit Name Initial Value R/W Description 7 to 4  Undefined R Reserved If these bits are read, they will return an undefined value.

3 P53 * R

2 P52 * R

1 P51 * R

0 P50 * R

If the P53 to P50 bits are read while a P5DDR bit is set to 1, the corresponding P5DR value is read. If this register is read while a P5DDR bit is cleared to 0, the corresponding pin state is read. Note: * Determined by the states of pins P53 to P50.

10.5.4 Port 5 Open Drain Control Register (P5ODR)

P5ODR specifies the output type of each port 5 pin. Bit Bit Name Initial Value R/W Description 7 to 4  All 0  Reserved These bits are always read as 0. Only the initial values should be written to these bits.

3 P53ODR 0 R/W

2 P52ODR 0 R/W

1 P51ODR 0 R/W

0 P50ODR 0 R/W

When BACK-B/BREQO-B output is not selected, setting a P5ODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a P5ODR bit to 0 makes the corresponding pin a CMOS output pin.

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10.5.5 Pin Functions

Port 5 pins also function as the pins for SCI I/Os, A/D converter inputs, interrupt inputs, I C I/Os, bus control signal I/Os, JTAG inputs, PPG outputs, TPU I/Os, and 8-bit timer I/Os. The correspondence between the register specification and the pin functions is shown below.

  • P53/IRQ3-A/ADTRG0-A/TRST* The pin function is switched as shown below according to the combination of bits TRGS1, TRGS0, and EXTRGS in ADCR_0 of the ADC, bit P53DDR, and bit ITS3 in ITSR of the interrupt controller. P53DDR 0 1 P53 input P53 output ADTRG0-A input* IRQ3-A interrupt input* Pin function TRST input* Notes: 1. ADTRG0-A input when the EXTRGS bit in ADCR0 is 0, and TRGS1 = TRGS0 = 1. 2. IRQ3-A input when the ITS3 bit in ITSR is 0. 3. TRST input when BSCANE pin = 1 and EMLE = 0 in the 145-pin package.

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  • P52/SCK2/IRQ2-A/BACK-B/PO4-B/TIOCA4-B/TMO0-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit BRLE in BCR of the bus controller, bits OS3 to OS0 in TCSR0 of 8-bit timer, bits MD3 to MD0 in TMDR_4 of TPU, bits IOA3 to IOA0 in TIOR_4, TPU channel 4 settings by bits CCLR1 and CCLR0 in TCR_4, bit NDER4 in NDERL of PPG, bit C/A in SMR_2 and bits CKE0 and CKE1 in SCR_2 of the SCI, bits PPGS, TPUS, and TMRS in PFCR3, bit BACKS in PFCR4, bit P52DDR, bit NDER4 in NDERL of the PPG, and bit ITS2 in ITSR of the interrupt controller.
  • Modes 1, 2, 4, and 7 (EXPE = 1) BRLE BACKS BRLE = 0 or BRLE = 1 and BACKS = 0 BRLE = 1 and BACKS = 1 TPU channel 4 settings (1) in table below (2) in table below  OS3 to OS0  All 0 Not all 0  CKE1  0 1   C/A  0 1    P52 input P52 output PO4-B output* SCK2 output SCK2 output SCK2 input TMO0-B output* BACK-B output TIOCA4-B output* TIOCA4-B input* Pin function IRQ2-A interrupt input*

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  • Mode 7 (EXPE = 0) BRLE BACKS TPU channel 4 settings (1) in table below (2) in table below OS3 to OS0  All 0 Not all 0 CKE1  0 1  C/A  0 1   CKE0  0 1    P52 input P52 output PO4-B output* SCK2 output SCK2 output SCK2 input TMO0-B output* TIOCA4-B output* TIOCA4-B input* Pin function IRQ2-A interrupt input* Notes: 1. IRQ2-A input when the ITS2 bit in ITSR is 0. 2. PO4-B output when the PPGS bit in PFCR3 is 1. 3. TIOCA4-B input/output when the TPUS bit in PFCR3 is 1. 4. TMO0-B output when the TMRS bit in PFCR3 is 1. TPU channel 4 settings MD3 to MD0 B'0000, B'01 ×× B'0010 B'001x B'0011 IOB3 to IOB0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 Other than B'××00 B'××00 Other than B' ××00 CCLR1, CCLR0     Other than B'10 B'10 Output function  Output compare output PWM mode 1 output  PWM mode 2 output Legend: ×: Don’t care

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  • P51/RxD2/IRQ1-A/SCL3/BREQ-B/PO2-B/TIOCC3-B/TMCI0-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit BRLE in BCR of the bus controller, bit ICE in ICCRA_3 of the I C, bits MD3 to MD0 in TMDR_3 of TPU, bits IOC3 to IOC0 in TIORL_3, TPU channel 3 settings by bits CCLR2 to CCLR0 in TCR_3, bit NDER2 in NDERL of PPG, bit RE in SCR_2 of the SCI, bit P51DDR, and bit ITS1 in ITSR of the interrupt controller.
  • Modes 1, 2, 4, and 7 (EXPE = 1) BRLE BREQS BRLE = 0 or BRLE = 1 and BREQS = 0 BRLE = 1 and BREQS = 1 ICE 0 1  TPU channel 3 settings (1) in table below (2) in table below   RE  0 1   P51DDR  0 1 1    P51 input P51 output PO2-B output* RxD2 input SCL3 I/O BREQ-B input TIOCC3-B output* TIOCC3-B input* IRQ1-A interrupt input* Pin function TMCI0-B input*

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  • Mode 7 (EXPE = 0) BRLE BREQS ICE 0 1 TPU channel 3 settings (1) in table below (2) in table below  RE  0 1  P51DDR  0 1 1   NDER2   0 1   P51 input P51 output PO2-B output* RxD2 input SCL3 I/O TIOCC3-B output* TIOCC3-B input* IRQ1-A interrupt input* Pin function TMCI0-B input* TPU channel 3 settings MD3 to MD0 B'0000 B'001 × B'0010 B'0011 IOC3 to IOC0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B'××00 Other than B'××00 CCLR2 to CCLR0     Other than B'101 B'101 Output function  Output compare output  PWM * mode 1 output PWM mode 2 output Legend: ×: Don’t care Notes: 1. IRQ1-A input when the ITS1 bit in ITSR is 0. 2. PO2-B output when the PPGS bit in PFCR3 is 1. 3. TIOCC3-B input/output when the TPUS bit in PFCR3 is 1. 4. TMCI0-B input when the TMRS bit in PFCR3 is 1.

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  • P50/TxD2/IRQ0-A/SDA3/BREQO-B* /PO0-B/TIOCA3-B/TMRI0-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit BRLE in BCR of the bus controller, bit ICE in ICCRA_3 of the I C, bits MD3 to MD0 in TMDR_3 of TPU, bits IOA3 to IOA0 in TIORH_3, TPU channel 3 settings by bits CCLR2 to CCLR0 in TCR_3, bit NDER0 in NDERL of PPG, bit TE in SCR_2 of the SCI, bits PPGS, TPUS, and TMRS in PFCR3, bit BREQOS in PFCR4, bit P50DDR, and bit ITS0 in ITSR of the interrupt controller.
  • Modes 1, 2, 4, and 7 (EXPE = 1) BRLE 0 1 BREQOE BREQOS  BREQOE = 0 or BREQOE = 1 and BREQOS = 0 BREQOE = 1 and BREQOS = 1 ICE 0 1 0 1  TPU channel 3 settings (1) in table below (2) in table below  (1) in table below (2) in table below   P50 input P50 output PO0-B output* TxD2 output SDA3 I/O P50 input P50 output PO0-B output* TxD2 output SDA3 I/O BREQO-B output TIOCA3-B output* TIOCA3-B input* TIOCA3-B output* TIOCA3-B input* IRQ0-A interrupt input* Pin function TMRI0-B input*

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  • Mode 7 (EXPE = 0) BRLE  BREQOE BREQOS ICE 0 1 TPU channel 3 settings (1) in table below (2) in table below  TE  0 1  P50DDR  0 1 1   NDER0   0 1   P50 input P50 output PO0-B output* TxD2 output SDA3 I/O TIOCA3-B output* TIOCA3-B input* IRQ0-A interrupt input* Pin function TMRI0-B input* TPU channel 3 settings MD3 to MD0 B'0000 B'001 × B'0010 B'0011 IOA3 to IOA0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B'××00 Other than B'××00 CCLR2 to CCLR0     Other than B'001 B'001 Output function  Output compare output  PWM * mode 1 output PWM mode 2 output Legend: ×: Don’t care Notes: 1. IRQ0-A input when the ITS0 bit in ITSR is 0. 2. PO0-B output when the PPGS bit in PFCR3 is 1. 3. TIOCA3-B input/output when the TPUS bit in PFCR3 is 1. 4. TMRI0-B input when the TMRS bit in PFCR3 is 1.

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10.6 Port 6

Note: Port 6 is not supported in the H8S/2424 Group. Port 6 is a 6-bit I/O port that also has other functions. Port 6 has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers.

  • Port 6 data direction register (P6DDR)
  • Port 6 data register (P6DR)
  • Port 6 register (PORT6)
  • Port 6 open drain control register (P6ODR)
  • Port function control register 3 (PFCR3)

10.6.1 Port 6 Data Direction Register (P6DDR)

The individual bits of P6DDR specify input or output for the pins of port 6. P6DDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description 7, 6  All 0  Reserved

5 P65DDR 0 W

4 P64DDR 0 W

3 P63DDR 0 W

2 P62DDR 0 W

1 P61DDR 0 W

0 P60DDR 0 W

When a pin function is specified as a general purpose I/O, setting this bit to 1 makes the corresponding pin an output port, while clearing this bit to 0 makes the corresponding pin an input port.

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10.6.2 Port 6 Data Register (P6DR)

P6DR stores output data for the port 6 pins. Bit Bit Name Initial Value R/W Description 7, 6  All 0  Reserved These bits are always read as 0 and cannot be modified.

5 P65DR 0 R/W

4 P64DR 0 R/W

3 P63DR 0 R/W

2 P62DR 0 R/W

1 P61DR 0 R/W

0 P60DR 0 R/W

Output data for a pin is stored when the pin function is specified as a general purpose I/O.

10.6.3 Port 6 Register (PORT6)

PORT6 shows the pin states of port 6. PORT6 cannot be modified. Bit Bit Name Initial Value R/W Description 7, 6  Undefined  Reserved If these bits are read, they will return an undefined value.

5 P65 * R

4 P64 * R

3 P63 * R

2 P62 * R

1 P61 * R

0 P60 * R

If this register is read while a P6DDR bit is set to 1, the corresponding P6DR value is read. If this register is read while a P6DDR bit is cleared to 0, the corresponding pin state is read. Note: * Determined by the states of pins P65 to P60.

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10.6.4 Port 6 Open Drain Control Register (P6ODR)

P6ODR specifies the output type of each port 6 pin. Bit Bit Name Initial Value R/W Description 7, 6  All 0  Reserved These bits are always read as 0. Only the initial values should be written to these bits.

5 P65ODR 0 R/W

4 P64ODR 0 R/W

3 P63ODR 0 R/W

2 P62ODR 0 R/W

1 P61ODR 0 R/W

0 P60ODR 0 R/W

Setting a P6ODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a P6ODR bit to 0 makes the corresponding pin a CMOS output pin.

10.6.5 Pin Functions

Port 6 pins also function as 8-bit timer I/Os, interrupt inputs, and DMAC I/Os. The correspondence between the register specification and the pin functions is shown below.

  • P65/IRQ13-A/DACK1/TMO1-A The pin function is switched as shown below according to the combination of bit SAE1 in DMABCRH of the DMAC, bits OS3 to OS0 in TCSR_1 of the 8-bit timer, bit TMRS in PFCR3, bit P65DDR, and bit ITS13 in ITSR of the interrupt controller. SAE1 0 1 OS3 to OS0 All 0 Not all 0  P65DDR 0 1   P65 input P65 output TMO1-A output * DACK1 output Pin function IRQ13-A interrupt input* Notes: 1. IRQ13-A input when the ITS13 bit in ITSR is 0. 2. TMO1-A output when the TMRS bit in PFCR3 is 0.

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  • P64/IRQ12-A/DACK0/TMO0-A The pin function is switched as shown below according to the combination of bit SAE0 in DMABCRH of the DMAC, bits OS3 to OS0 in TCSR_0 of the 8-bit timer, bit TMRS in PFCR3, bit P64DDR, and bit ITS12 in ITSR of the interrupt controller. SAE0 0 1 OS3 to OS0 All 0 Not all 0  P64DDR 0 1   P64 input P64 output TMO0-A output * DACK0 output Pin function IRQ12-A interrupt input* Notes: 1. IRQ12-A input when the ITS12 bit in ITSR is 0. 2. TMO0-A output when the TMRS bit in PFCR3 is 0.
  • P63/IRQ11-A/TEND1/TMCI1-A The pin function is switched as shown below according to the combination of bit TEE1 in DMATCR of the DMAC, bit TMRS in PFCR3, bit P63DDR, and bit ITS11 in ITSR of the interrupt controller. TEE1 0 1 P63DDR 0 1  P63 input P63 output TEND1 output IRQ11-A interrupt input* Pin function TMCI1-A input* Notes: 1. IRQ11-A input when the ITS11 bit in ITSR is 0. 2. When used as the external clock input pin for the TMR, its pin function should be specified to the external clock input by the CKS2 to CKS0 bits in TCR_1. 3. TMCI1-A input when the TMRS bit in PFCR3 is 0.

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  • P62/IRQ10-A/TEND0/TMCI0-A The pin function is switched as shown below according to the combination of bit TEE0 in DMATCR of the DMAC, bit TMRS in PFCR3, bit P62DDR, and bit ITS10 in ITSR of the interrupt controller. TEE0 0 1 P62DDR 0 1  P62 input P62 output TEND0 output IRQ10-A interrupt input* Pin function TMCI0-A input* Notes: 1. IRQ10-A input when the ITS10 bit in ITSR is 0. 2. When used as the external clock input pin for the TMR, its pin function should be specified to the external clock input by the CKS2 to CKS0 bits in TCR_0. 3. TMCI0-A input when the TMRS bit in PFCR3 is 0.
  • P61/IRQ9-A/DREQ1/TMRI1-A The pin function is switched as shown below according to the combination of bit TMRS in PFCR3, bit P61DDR, and bit ITS9 in ITSR of the interrupt controller. P61DDR 0 1 P61 input P61 output TMRI1-A input* DREQ1 input Pin function IRQ9-A interrupt input* Notes: 1. When used as the counter reset input pin for the TMR, both the CCLR1 and CCLR0 bits in TCR_1 should be set to 1. 2. IRQ9-A input when the ITS9 bit in ITSR is 0. 3. TMRI1-A input when the TMRS bit in PFCR3 is 0.

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  • P60/IRQ8-A/DREQ0/TMRI0-A The pin function is switched as shown below according to the combination of bit TMRS in PFCR3, bit P60DDR, and bit ITS8 in ITSR of the interrupt controller. P60DDR 0 1 P60 input P60 output TMRI0-A input* DREQ0 input Pin function IRQ8-A interrupt input* Notes: 1. When used as the counter reset input pin for the TMR, both the CCLR1 and CCLR0 bits in TCR_0 should be set to 1. 2. IRQ8-A input when the ITS8 bit in ITSR is 0. 3. TMRI0-A input when the TMRS bit in PFCR3 is 0.

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10.7 Port 8

Port 8 is a 6-bit I/O port that also has other functions. Port 8 has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers.

  • Port 8 data direction register (P8DDR)
  • Port 8 data register (P8DR)
  • Port 8 register (PORT8)
  • Port 8 open drain control register (P8ODR)
  • Port function control register 3 (PFCR3)

10.7.1 Port 8 Data Direction Register (P8DDR)

The individual bits of P8DDR specify input or output for the pins of port 8. P8DDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description 7, 6  All 0  Reserved

5 P85DDR 0 W

4 P84DDR 0 W

3 P83DDR 0 W

2 P82DDR 0 W

1 P81DDR 0 W

0 P80DDR 0 W

When a pin function is specified as a general purpose I/O, setting this bit to 1 makes the corresponding pin an output port, while clearing this bit to 0 makes the corresponding pin an input port. Bits 4, 2, and 0 are reserved in the H8S/2424 Group.

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10.7.2 Port 8 Data Register (P8DR)

P8DR stores output data for the port 8 pins. Bit Bit Name Initial Value R/W Description 7, 6  All 0  Reserved These bits are always read as 0 and cannot be modified.

5 P85DR 0 R/W

4 P84DR 0 R/W

3 P83DR 0 R/W

2 P82DR 0 R/W

1 P81DR 0 R/W

0 P80DR 0 R/W

Output data for a pin is stored when the pin function is specified as a general purpose I/O. Bits 4, 2, and 0 are reserved in the H8S/2424 Group.

10.7.3 Port 8 Register (PORT8)

PORT8 shows the pin states of port 8. PORT8 cannot be modified. Bit Bit Name Initial Value R/W Description 7, 6  Undefined  Reserved If these bits are read, they will return an undefined value.

5 P85 * R

4 P84 * R

3 P83 * R

2 P82 * R

1 P81 * R

0 P80 * R

If this register is read while a P8DDR bit is set to 1, the corresponding P8DR value is read. If this register is read while a P8DDR bit is cleared to 0, the corresponding pin state is read. Bits 4, 2, and 0 are reserved in the H8S/2424 Group. Note: * Determined by the states of pins P85 to P80.

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10.7.4 Port 8 Open Drain Control Register (P8ODR)

P8ODR specifies the output type of each port 8 pin. Bit Bit Name Initial Value R/W Description 7, 6  All 0  Reserved These bits are always read as 0. Only the initial values should be written to these bits.

5 P85ODR 0 R/W

4 P84ODR 0 R/W

3 P83ODR 0 R/W

2 P82ODR 0 R/W

1 P81ODR 0 R/W

0 P80ODR 0 R/W

Setting a P8ODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a P8ODR bit to 0 makes the corresponding pin a CMOS output pin. Bits 4, 2, and 0 are reserved in the H8S/2424 Group.

10.7.5 Pin Functions

Port 8 pins also function as SCI I/Os, interrupt inputs, EXDMAC I/Os, PPG outputs, TPU I/Os, and 8-bit timer I/Os. The correspondence between the register specification and the pin functions is shown below. (1) Pin Functions of H8S/2426 Group and H8S/2426R Group

  • P85/EDACK3/IRQ5-B/SCK3/PO5-B/TIOCB4-B/TMO1-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 4 settings (by bits MD3 to MD0 in TMDR_4, bits IOB3 to IOB0 in TIOR_4, and bits CCLR1 and CCLR0 in TCR_4), bits OS3 to OS0 in TCSR_1 of the 8-bit timer, bit NDER5 in NDERL of the PPG, bit AMS in EDMDR_3 of the EXDMAC, bit C/A in SMR_3 and bits CKE0 and CKE1 in SCR_3 of the SCI, bits PPGS, TPUS, and TMRS in PFCR3, bit P85DDR, and bit ITS5 in ITSR of the interrupt controller.

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  • Modes 1, 2, 4, and 7 (EXPE = 1) TPU channel 4 settings (1) in table below (2) in table below OS3 to OS0  All 0 Not all 0 AMS  0 1  CKE1  0 1   C/A  0 1    P85 input P85 output PO5-B output* SCK3 output SCK3 output SCK3 input EDACK3 output TMO1-B output* TIOCB4-B output* TIOCB4-B input* Pin function IRQ5-B interrupt input*
  • Mode 7 (EXPE = 0) TPU channel 4 settings (1) in table below (2) in table below OS3 to OS0  All 0 Not all 0 AMS    CKE1  0 1  C/A  0 1   CKE0  0 1    P85 input P85 output PO5-B output* SCK3 output SCK3 output SCK3 input TMO1-B output* TIOCB4-B output* TIOCB4-B input* Pin function IRQ5-B interrupt input* Notes: 1. IRQ5-B input when the ITS5 bit in ITSR is 1. 2. PO5-B output when the PPGS bit in PFCR3 is 1. 3. TIOCB4-B input/output when the TPUS bit in PFCR3 is 1. 4. TMO1-B output when the TMRS bit in PFCR3 is 1.

Rev. 1.00 Sep. 19, 2008 Page 576 of 1270 REJ09B0466-0100 TPU channel 4 settings MD3 to MD0 B'0000, B'01 ×× B'0010 B'0011 IOB3 to IOB0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111  B' ××00 Other than B' ××00 CCLR1, CCLR0     Other than B'10 B'10 Output function  Output compare output   PWM mode 2 output Legend: ×: Don’t care

  • P84/IRQ4-B/EDACK2 The pin function is switched as shown below according to the combination of bit AMS in EDMDR_2 of the EXDMAC, bit P84DDR, and bit ITS4 in ITSR of the interrupt controller. Operating mode 1, 2, 4, 7 (EXPE = 1) 7 (EXPE = 0) AMS 0 1  P84DDR 0 1  0 1 P84 input P84 output EDACK2 output P84 input P84 output Pin function IRQ4-B interrupt input* Note: * IRQ4-B input when the ITS4 bit in ITSR is 1.

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  • P83/ETEND3* /IRQ3-B* /RxD3/PO3-B/TIOCD3-B/TMCI1-B The pin function is switched as shown below according to the combination of bit ETENDE in EDMDR_3 of the EXDMAC, bit RE in SCR_3 of the SCI, TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOD3 to IOD0 in TIORL_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER3 in NDERL of the PPG, bits PPGS, TPUS, and TMRS in PFCR3, bit P83DDR, and bit ITS3 in ITSR of the interrupt controller.
  • Modes 1, 2, 4, and 7 (EXPE = 1) TPU channel 3 settings (1) in table below (2) in table below ETENDE  0 1 RE  0 1  P83DDR  0 1 1   NDER3   0 1   P83 input P83 output PO3-B output* RxD3 input ETEND3 output TIOCD3-B output* TIOCD3-B input* IRQ3-B interrupt input* Pin function TMCI1-B input*

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  • Mode 7 (EXPE = 0) TPU channel 3 settings (1) in table below (2) in table below ETENDE  0 1 RE  0 1  P83DDR  0 1  NDER3   0 1  P83 input P83 output PO3-B output * RxD3 input TIOCD3-B output* TIOCD3-B input* IRQ3-B interrupt input* Pin function TMCI1-B input* Notes: 1. IRQ3-B input when the ITS3 bit in ITSR is 1. 2. PO3-B output when the PPGS bit in PFCR3 is 1. 3. TIOCD3-B input/output when the TPUS bit in PFCR3 is 1. 4. TMCI1-B input when the TMRS bit in PFCR3 is 1. TPU channel 3 settings MD3 to MD0 B'0000 B'0010 B'0011 IOD3 to IOD0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111  B' ××00 Other than B' ××00 CCLR2 to CCLR0     Other than B'110 B'110 Output function  Output compare output   PWM mode 2 output Legend: ×: Don’t care

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  • P82/IRQ2-B/ETEND2 The pin function is switched as shown below according to the combination of bit ETENDE in EDMDR_2 of the EXDMAC, bit P82DDR, and bit ITS2 in ITSR of the interrupt controller. Operating mode 1, 2, 4, 7 (EXPE = 1) 7 (EXPE = 0) ETENDE 0 1  P82DDR 0 1  0 1 P82 input P82 output ETEND2 output P82 input P82 output Pin function IRQ2-B interrupt input* Note: * IRQ2-B input when the ITS2 bit in ITSR is 1.
  • P81/EDREQ3/IRQ1-B/TxD3/PO1-B/TIOCB3-B/TMRI1-B The pin function is switched as shown below according to the combination of bit TE in SCR_3 of the SCI, TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOB3 to IOB0 in TIORH_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER1 in NDERL of the PPG, bits PPGS, TPUS, and TMRS in PFCR3, bit P81DDR, and bit ITS1 in ITSR of the interrupt controller. TPU channel 3 settings (1) in table below (2) in table below TE  0 1 P81DDR  0 1 1  NDER1   0 1  P81 input P81 output PO1-B output * TxD3 output TIOCB3-B output* TIOCB3-B input* EDREQ3 input IRQ1-B interrupt input* Pin function TMRI1-B input* Notes: 1. IRQ1-B input when the ITS1 bit in ITSR is 1. 2. PO1-B output when the PPGS bit in PFCR3 is 1. 3. TIOCB3-B input/output when the TPUS bit in PFCR3 is 1. 4. TMRI1-B input when the TMRS bit in PFCR3 is 1.

Rev. 1.00 Sep. 19, 2008 Page 580 of 1270 REJ09B0466-0100 TPU channel 3 settings MD3 to MD0 B'0000 B'0010 B'0011 IOB3 to IOB0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111  B' ××00 Other than B' ××00 CCLR2 to CCLR0     Other than B'010 B'010 Output function  Output compare output   PWM mode 2 output Legend: ×: Don’t care

  • P80/IRQ0-B/EDREQ2 The pin function is switched as shown below according to the combination of bit P80DDR and bit ITS0 in ITSR of the interrupt controller. P80DDR 0 1 P80 input P80 output EDREQ2 input Pin function IRQ0-B interrupt input* Note: * IRQ0-B input when the ITS0 bit in ITSR is 1.

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  • P85/SCK3/PO5-B/TIOCB4-B/TMO1-B The pin function is switched as shown below according to the combination of the TPU channel 4 settings (by bits MD3 to MD0 in TMDR_4, bits IOB3 to IOB0 in TIOR_4, and bits CCLR1 and CCLR0 in TCR_4), bits OS3 to OS0 in TCSR_1 of the 8-bit timer, bit NDER5 in NDERL of the PPG, bit C/A in SMR_3 and bits CKE0 and CKE1 in SCR_3 of the SCI, bits PPGS, TPUS, and TMRS in PFCR3, and bit P85DDR. TPU channel 4 settings (1) in table below (2) in table below OS3 to OS0  All 0 Not all 0 CKE1  0 1  C/A  0 1   CKE0  0 1    P85 input P85 output PO5-B output* SCK3 output SCK3 output SCK3 input TMO1-B output* Pin function TIOCB4-B output* TIOCB4-B input* Notes: 1. PO5-B output when th e PPGS bit in PFCR3 is 1. 2. TIOCB4-B input/output when the TPUS bit in PFCR3 is 1. 3. TMO1-B output when the TMRS bit in PFCR3 is 1. TPU channel 4 settings MD3 to MD0 B'0000, B'01 ×× B'0010 B'0011 IOB3 to IOB0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111  B' ××00 Other than B' ××00 CCLR1, CCLR0     Other than B'10 B'10 Output function  Output compare output   PWM mode 2 output Legend: ×: Don’t care

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  • P83/PO3-B/TIOCD3-B/TMCI1-B/RxD3 The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOD3 to IOD0 in TIORL_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER3 in NDERL of the PPG, bit RE in SCR_3 of the SCI, bits PPGS, TPUS, and TMRS in PFCR3, and bit P83DDR. TPU channel 3 settings (1) in table below (2) in table below RE  0 1 P83DDR  0 1  NDER3   0 1  P83 input P83 output PO3-B output * RxD3 input TIOCD3-B output* TIOCD3-B input* Pin function TMCI1-B input* Notes: 1. PO3-B output when th e PPGS bit in PFCR3 is 1. 2. TIOCD3-B input/output when the TPUS bit in PFCR3 is 1. 3. TMCI1-B input when the TMRS bit in PFCR3 is 1. TPU channel 3 settings MD3 to MD0 B'0000 B'0010 B'0011 IOD3 to IOD0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111  B' ××00 Other than B' ××00 CCLR2 to CCLR0     Other than B'110 B'110 Output function  Output compare output   PWM mode 2 output Legend: ×: Don’t care

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  • P81/PO1-B/TIOCB3-B/TMRI1-B/TxD3 The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOB3 to IOB0 in TIORH_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER1 in NDERL of the PPG, bit TE in SCR_3 of the SCI, bits PPGS, TPUS, and TMRS in PFCR3, and bit P81DDR. TPU channel 3 settings (1) in table below (2) in table below TE 0 1 P81DDR  0 1  NDER1   0 1  P81 input P81 output PO1-B output * TxD3 output TIOCB3-B output* TIOCB3-B input* Pin function TMRI1-B input* Notes: 1. PO1-B output when th e PPGS bit in PFCR3 is 1. 2. TIOCB3-B input/output when the TPUS bit in PFCR3 is 1. 3. TMRI1-B input when the TMRS bit in PFCR3 is 1. TPU channel 3 settings MD3 to MD0 B'0000 B'0010 B'0011 IOB3 to IOB0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111  B' ××00 Other than B' ××00 CCLR2 to CCLR0     Other than B'010 B'010 Output function  Output compare output   PWM mode 2 output Legend: ×: Don’t care

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10.8 Port 9

Port 9 is an 8-bit input-only port that also has other functions. Port 9 has the following register.

  • Port 9 register (PORT9)

10.8.1 Port 9 Register (PORT9)

PORT9 is an 8-bit read-only register that shows the pin states of port 9. PORT9 cannot be modified. Bit Bit Name Initial Value R/W Description

7 P97 * R

6 P96 * R

5 P95 * R

4 P99 * R

3 P93 * R

2 P92 * R

1 P91 * R

0 P90 * R

The pin states are always read from this register. Bits 7, 6, and 3 to0 are reserved in the H8S/2424 Group. Note: * Determined by the states of pins P97 to P90.

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10.8.2 Pin Functions

Port 9 also functions as the pins for A/D converter analog inputs and D/A converter analog outputs. The correspondence between pins is as follows. (1) Pin Functions of H8S/2426 Group and H8S/2426R Group

  • P97/AN15_1 Pin function AN15_1 input
  • P96/AN14_1 Pin function AN14_1 input
  • P95/AN13_1/DA3 AN13_1 input Pin function DA3 output
  • P94/AN12_1/DA2 AN12_1 input Pin function DA2 output
  • P93/AN11_1 Pin function AN11_1 input
  • P92/AN10_1 Pin function AN10_1 input
  • P91/AN9_1 Pin function AN9_1 input
  • P90/AN8_1 Pin function AN8_1 input

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  • P95/AN13_1/DA3 AN13_1 input Pin function DA3 output
  • P94/AN12_1/DA2 AN12_1 input Pin function DA2 output

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10.9 Port A

Port A is an 8-bit I/O port that also has other functions. Port A has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers.

  • Port A data direction register (PADDR)
  • Port A data register (PADR)
  • Port A register (PORTA)
  • Port A pull-up MOS control register (PAPCR)
  • Port A open-drain control register (PAODR)
  • Port function control register 0 (PFCR0)(the H8S/2424 Group)
  • Port function control register 1 (PFCR1)
  • Port function control register 4 (PFCR4)
  • Port function control register 5 (PFCR5)

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10.9.1 Port A Data Direction Register (PADDR)

The individual bits of PADDR specify input or output for the pins of port A. PADDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description

7 PA7DDR 0 W

6 PA6DDR 0 W

5 PA5DDR 0 W

4 PA4DDR 0 W

3 PA3DDR 0 W

2 PA2DDR 0 W

1 PA1DDR 0 W

0 PA0DDR 0 W

  • Modes 1 and 2 Pins PA4 to PA0 are address outputs. For pins PA7 to PA5, when the corresponding bit of A23E to A21E is set to 1, setting a PADDR bit to 1 makes the corresponding pin an address output, while clearing the bit to 0 makes the corresponding pin an input port. Clearing one of bits A23E to A21E to 0 makes the corresponding pin an I/O port, and its function can be switched with PADDR.
  • Modes 7 (when EXPE = 1) and 4 When the corresponding bit of A23E to A16E is set to 1, setting a PADDR bit to 1 makes the corresponding pin an address output, while clearing the bit to 0 makes the corresponding pin an input port. Clearing one of bits A23E to A16E to 0 makes the corresponding pin an I/O port, and its function can be switched with PADDR.
  • Mode 7 (when EXPE = 0) Port A is an I/O port, and its pin functions can be switched with PADDR.

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10.9.2 Port A Data Register (PADR)

PADR stores output data for the port A pins. Bit Bit Name Initial Value R/W Description

7 PA7DR 0 R/W

6 PA6DR 0 R/W

5 PA5DR 0 R/W

4 PA4DR 0 R/W

3 PA3DR 0 R/W

2 PA2DR 0 R/W

1 PA1DR 0 R/W

0 PA0DR 0 R/W

Output data for a pin is stored when the pin function is specified as a general purpose I/O.

10.9.3 Port A Register (PORTA)

PORTA shows the pin states of port A. PORTA cannot be modified. Bit Bit Name Initial Value R/W Description

7 PA7 * R

6 PA6 * R

5 PA5 * R

4 PA4 * R

3 PA3 * R

2 PA2 * R

1 PA1 * R

0 PA0 * R

If this register is read while a PADDR bit is set to 1, the corresponding PADR value is read. If this register is read while a PADDR bit is cleared to 0, the corresponding pin state is read. Note: * Determined by the states of pins PA7 to PA0.

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10.9.4 Port A Pull-Up MOS Control Register (PAPCR)

PAPCR controls on/off of the input pull-up MOS for port A. Bits 7 to 5 are valid in modes 1 and 2 and all the bits are valid in modes 4 and 7. Bit Bit Name Initial Value R/W Description

7 PA7PCR 0 R/W

6 PA6PCR 0 R/W

5 PA5PCR 0 R/W

4 PA4PCR 0 R/W

3 PA3PCR 0 R/W

2 PA2PCR 0 R/W

1 PA1PCR 0 R/W

0 PA0PCR 0 R/W

When in an input port state, setting the corresponding bit to 1 turns on the input pull-up MOS for that pin.

10.9.5 Port A Open Drain Control Register (PAODR)

PAODR specifies the output type of each port A pin. Bit Bit Name Initial Value R/W Description

7 PA7ODR 0 R/W

6 PA6ODR 0 R/W

5 PA5ODR 0 R/W

4 PA4ODR 0 R/W

3 PA3ODR 0 R/W

2 PA2ODR 0 R/W

1 PA1ODR 0 R/W

0 PA0ODR 0 R/W

When not specified for address output or CS7 output*, setting a PAODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a PAODR bit to 0 makes the corresponding pin a CMOS output pin. Note: * Not supported by the H8S/24 26 Group and the H8S/2426R Group

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10.9.6 Pin Functions

Port A pins also function as the pins for address outputs, interrupt inputs, SSU I/Os, SCI I/Os, and bus control signal outputs. The correspondence between the register specification and the pin functions is shown below.

  • PA7/A23/CS7* /IRQ7-A/SSO0-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of the SSU, bits SSO0S1 and SSO0S0 in PFCR5, bit CS7E in PFCR0 (the H8S/2424 Group), bit A23E in PFCR1, bit PA7DDR, and bit ITS7 in ITSR of the interrupt controller.
  • Modes 1, 2, and 4 A23E 0 1 CS7E* 0 1  SSU settings Can be used as I/O port Input state Output state   PA7DDR 0 1 0  0 1 0 1 PA7 input PA7 output SSO0-B input* SSO0-B output* PA7 input CS7 output* PA7 input A23 output Pin function IRQ7-A interrupt input*
  • Mode 7 (EXPE = 1) A23E 0 1 CS7E* 0 1  SSU settings Can be used as I/O port Input state Output state   PA7DDR 0 1 0  0 1 0 1 PA7 input PA7 output SSO0-B input* SSO0-B output* PA7 input CS7 output* PA7 input A23 outputPin function IRQ7-A interrupt input*

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  • Mode 7 (EXPE = 0) A23E  CS7E* SSU settings Can be used as I/O port Input state Output state PA7DDR 0 1 0  PA7 input PA7 output SSO0-B input * SSO0-B output * Pin function IRQ7-A interrupt input* Notes: 1. IRQ7-A input when the ITS7 bit in ITSR is 0. 2. SSO0-B input when SSO0S1 and SSO0S0 = B'01 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'000×1 or B'01×01. 3. SSO0-B output when SSO0S1 and SSO0S 0 = B'01 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'001××, B'0101×, or B'10×1×. 4. Supported only by the H8S/2424 Group and not supported by the H8S/2426 and H8S/2426R Groups. SSO pin settings SSUMS 0 0 1 BIDE 0 1 0 MSS 0 1 0 1 0 1 TE 0 1 0 1 0 1 0 1 0 1 0 1 RE 1 0 1 1 0 1 1 0 1 0 1 0 1 1 0 1 Pin state Input  Input  Output Output Input Output Input Output  Output Output  Output Output Legend: : Pin is not used by the SSU (can be used as I/O port)

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  • PA6/A22/IRQ6-A/SSI0-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of SSU, bit A22E in PFCR1, bits SSI0S1 and SSI0S0 in PFCR5, bit PA6DDR, and bit ITS6 in ITSR of the interrupt controller.
  • Modes 1, 2, and 4 A22E  SSU settings Can be used as I/O port Input state Output state PA6DDR 0 1 0  0 1 PA6 input PA6 output SSI0-B input* SSI0-B output* PA6 input A22 output Pin function IRQ6-A interrupt input*
  • Mode 7 EXPE 1 0 A22E 0 1  SSU settings Can be used as I/O port Input state Output state  Can be used as I/O port Input state Output state PA6DDR 0 1 0  0 1 0 1 0  PA6 input PA6 output SSI0-B input* SSI0-B output* PA6 input A22 output PA6 input PA6 output SSI0-B input* SSI0-B output* Pin function IRQ6-A interrupt input* Notes: 1. IRQ6-A input when the ITS6 bit in ITSR is 0. 2. SSI0-B input when SSI0S1 and SSI0S0 = B'01 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'001×1 or B'10××1. 3. SSI0-B output when SSI 0S1 and SSI0S0 = B'01 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'0001×.

Rev. 1.00 Sep. 19, 2008 Page 594 of 1270 REJ09B0466-0100 SSI pin settings SSUMS 0 0 1 BIDE 0 1 0 MSS 0 1 0 1 0 1 TE 0 1 0 1 0 1 0 1 0 1 0 1 RE 1 0 1 1 0 1 1 0 1 0 1 0 1 1 0 1 Pin state  Output Output Input  Input     Input  Input Input  Input Legend: : Pin is not used by the SSU (can be used as I/O port)

  • PA5/A21/IRQ5-A/SSCK0-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits MSS and SCKS in SSCRH and bit SSUMS in SSCRL of the SSU, bit A21E in PFCR1, bits SSCK0S1 and SSCK0S0 in PFCR5, bit PA5DDR, and bit ITS5 in ITSR of the interrupt controller
  • Modes 1, 2, and 4 A21E 0 1 SSU settings Can be used as I/O port Input state Output state PA5DDR 0 1 0  0 1 PA5 input PA5 output SSCK0-B input* SSCK0-B output* PA5 input A21 output IRQ5-A interrupt input* Pin function SSCK0-B input*

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  • Mode 7 EXPE 1 0 A21E 0 1  SSU settings Can be used as I/O port Input state Output state  Can be used as I/O port Input state Output state PA5DDR 0 1 0  0 1 0 1 0  PA5 input PA5 output SSCK0-B input* SSCK0-B output* PA5 input A21 output PA5 input PA5 output SSCK0-B input* SSCK0-B output* IRQ5-A interrupt input* Pin function SSCK0-B input* Notes: 1. IRQ5-A input when the ITS5 bit in ITSR is 0. 2. SSCK0-B input when SSCK0S1 and SSCK0S0 = B'00 in PFCR5, and SSUMS, MSS, and SCKS = B'001 or B'101. 3. SSCK0-B output when SSCK0S1 and SSC K0S0 = B'00 in PFCR5, and SSUMS, MSS, and SCKS = B'×11. SSCK pin settings SSUMS 0 1 MSS 0 1 0 1 SCKS 0 1 0 1 0 1 0 1 Pin state  Input  Output  Input  Output Legend: : Pin is not used by the SSU (can be used as I/O port)

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  • PA4/A20/IRQ4-A/SCS0-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits MSS, CSS1, and CSS0 in SSCRH and bit SSUMS in SSCRL of the SSU, bit A20E in PFCR1, bit PA4DDR, and bit ITS4 in ITSR of the interrupt controller. Operating mode 1, 2 4 EXPE   A20E  0 1 SSU settings  Can be used as I/O port Input state Output state PA4DDR  0 1 0  0 1 A20 output PA4 input PA4 output SCS0-B input* SCS0-B output* PA4 input A20 outputPin function IRQ4-A interrupt input* Operating mode EXPE 0 1 A20E  0 1 SSU settings Can be used as I/O port Input state Output state Can be used as I/O port Input state Output state PA4DDR 0 1 0  0 1 0  0 1 PA4 input PA4 output SCS0-B input* SCS0-B output* PA4 input PA4 output SCS0-B input* SCS0-B output* PA4 input A20 output Pin function IRQ4-A interrupt input* Notes: 1. IRQ4-A input when the ITS4 bit in ITSR is 0. 2. SCSO-B input when SCS0S1 and SCS0S0 = B'01 in PFCR5, and SSUMS, MSS, CSS1, and CSS0 = B'00××, B'0101, or B'0110. 3. SCSO-B output when SCS0S1 and SCS0S0 = B'01 in PFCR5, and SSUMS, MSS, CSS1, and CSS0 = B'011×.

Rev. 1.00 Sep. 19, 2008 Page 597 of 1270 REJ09B0466-0100 SCS pin settings SSUMS 0 1 MSS 0 1 × CSS1 × 0 1 × CSS0 × 0 1 0 1 × Pin state Input  Input Automatic I/O Output  Legend: ×: Don’t care : Pin is not used by the SSU (can be used as I/O port)

  • PA3/A19/SCK4-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit C/A in SMR_4 and bits CKE0 and CKE1 in SCR_4 of the SCI, bit A19E in PFCR1, bit SCK4S in PFCR4, and bit PA3DDR. Operating mode 1, 2 4 EXPE   A19E  0 1 CKE1  0 1  C/A  0 1   CKE0  0 1    PA3DDR  0 1    0 1 Pin function A19 output PA3 input PA3 output SCK4-B output* SCK4-B output* SCK4-B input* PA3 input A19 output

Rev. 1.00 Sep. 19, 2008 Page 598 of 1270 REJ09B0466-0100 Operating mode EXPE 0 1 A19E  0 1 CKE1 0 1 0 1  C/A 0 1  0 1   PA3DDR 0 1    0 1    0 1 Pin function PA3 input PA3 output SCK4-B output* SCK4-B output* SCK4-B input* PA3 input PA3 output SCK4-B output* SCK4-B output* SCK4-B input* PA3 input A19 output Note: * SCK4-B input/output when the SCK4S bit in PFCR4 is 1.

  • PA2/A18/RxD4-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit RE in SCR_4 of the SCI, bit A18E in PFCR1, bit RXD4S in PFCR4, and bit PA2DDR. Operating mode 1, 2 4 7 EXPE   0 1 A18E  0 1  0 1 RE  0 1  0 1 0 1  PA2DDR  0 1  0 1 0 1  0 1  0 1 Pin function A18 output PA2 input PA2 output RxD4-B input* PA2 input A18 output PA2 input PA2 output RxD4-B input* PA2 input PA2 output RxD4-B input* PA2 input A18 output Note: * RxD4-B input when the RXD4S bit in PFCR4 is 1.

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  • PA1/A17/TxD4-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit TE in SCR_4 of the SCI, bit A17E in PFCR1, bit TXD4S in PFCR4, and bit PA1DDR. Operating mode 1, 2 4 7 EXPE   0 1 A17E  0 1  0 1 TE  0 1  0 1 0 1  PA1DDR  0 1  0 1 0 1  0 1  0 1 Pin function A17 output PA1 input PA1 output TxD4-B output* PA1 input A17 output PA1 input PA1 output TxD4-B output* PA1 input PA1 output TxD4-B output* PA1 input A17 output Note: * TxD4-A output when the TXD4S bit in PFCR4 is 1.
  • PA0/A16 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit A16E in PFCR1, and bit PA0DDR. Operating mode 1, 2 4 7 EXPE   0 1 A16E  0 1  0 1 PA0DDR  0 1 0 1 0 1 0 1 0 1 Pin function A16 output PA0 input PA0 output PA0 input A16 output PA0 input PA0 output PA0 input PA0 output PA0 input A16 output

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10.9.7 Port A Input Pull-Up MOS States

Port A has a built-in input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be used by pins PA7 to PA5 in modes 1 and 2, and by all pins in modes 4 and 7. The input pull-up MOS can be specified as on or off on a bit-by-bit basis. Table 10.3 summarizes the input pull-up MOS states. Table 10.3 Input Pull-Up MOS States for Port A Mode Reset Hardware Standby Mode Software Standby Mode In Other Operations 4 or 7 PA7 to PA0 Off Off On/Off On/Off 1 or 2 PA7 to PA5 On/Off On/Off PA4 to PA0 Off Off Legend: Off: Input pull-up MOS is always off. On/Off: Input pull-up MOS is on when in input port register state* and PAPCR = 1; otherwise off. Note: * Not available with SSU/SCI input

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10.10 Port B

Port B is an 8-bit I/O port that also has other functions. Port B has the following registers.

  • Port B data direction register (PBDDR)
  • Port B data register (PBDR)
  • Port B register (PORTB)
  • Port B pull-up MOS control register (PBPCR)
  • Port B open drain control register (PBODR)

10.10.1 Port B Data Direction Register (PBDDR)

The individual bits of PBDDR specify input or output for the pins of port B. PBDDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description

7 PB7DDR 0 W

6 PB6DDR 0 W

5 PB5DDR 0 W

4 PB4DDR 0 W

3 PB3DDR 0 W

2 PB2DDR 0 W

1 PB1DDR 0 W

0 PB0DDR 0 W

  • Modes 1 and 2 Port B pins are address outputs regardless of the PBDDR settings.
  • Modes 7 (when EXPE = 1) and 4 Setting a PBDDR bit to 1 makes the corresponding pin an address output, while clearing a PBDDR bit to 0 makes the corresponding pin an input port.
  • Mode 7 (when EXPE = 0) Port B is an I/O port, and its pin functions can be switched with PBDDR.

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10.10.2 Port B Data Register (PBDR)

PBDR stores output data for the port B pins. Bit Bit Name Initial Value R/W Description

7 PB7DR 0 R/W

6 PB6DR 0 R/W

5 PB5DR 0 R/W

4 PB4DR 0 R/W

3 PB3DR 0 R/W

2 PB2DR 0 R/W

1 PB1DR 0 R/W

0 PB0DR 0 R/W

Output data for a pin is stored when the pin function is specified as a general purpose I/O.

10.10.3 Port B Register (PORTB)

PORTB shows the pin states of port B. PORTB cannot be modified. Bit Bit Name Initial Value R/W Description

7 PB7 * R

6 PB6 * R

5 PB5 * R

4 PB4 * R

3 PB3 * R

2 PB2 * R

1 PB1 * R

0 PB0 * R

If this register is read while a PBDDR bit is set to 1, the corresponding PBDR value is read. If this register is read while a PBDDR bit is cleared to 0, the corresponding pin state is read. Note: * Determined by the states of pins PB7 to PB0.

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10.10.4 Port B Pull-Up MOS Control Register (PBPCR)

PBPCR controls on/off of the input pull-up MOS for port B. PBPCR is valid in modes 4 and 7. Bit Bit Name Initial Value R/W Description

7 PB7PCR 0 R/W

6 PB6PCR 0 R/W

5 PB5PCR 0 R/W

4 PB4PCR 0 R/W

3 PB3PCR 0 R/W

2 PB2PCR 0 R/W

1 PB1PCR 0 R/W

0 PB0PCR 0 R/W

When in a input port register state, setting the corresponding bit to 1 turns on the input pull-up MOS for that pin.

10.10.5 Port B Open Drain Control Register (PBODR)

PBODR specifies the output type of each port B pin. Bit Bit Name Initial Value R/W Description

7 PB7ODR 0 R/W

6 PB6ODR 0 R/W

5 PB5ODR 0 R/W

4 PB4ODR 0 R/W

3 PB3ODR 0 R/W

2 PB2ODR 0 R/W

1 PB1ODR 0 R/W

0 PB0ODR 0 R/W

When not specified for address output, setting a PBODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a PBODR bit to 0 makes the corresponding pin a CMOS output pin.

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10.10.6 Pin Functions

Port B pins also function as the pins for TPU I/Os and address outputs. The correspondence between the register specification and the pin functions is shown below.

  • PB7/A15/TIOCB8/TCLKH The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 8 settings (by bits MD3 to MD0 in TMDR_8, bits IOB3 to IOB0 in TIOR_8, and bits CCLR1 and CCLR0 in TCR_8), bits TPSC2 to TPSC0 in TCR_6 and TCR_11, and bit PB7DDR. Operating mode 1, 2 4, 7 (EXPE = 1) 7 (EXPE = 0) TPU channel 8 settings   (1) in table below (2) in table below PB7DDR  0 1  0 1 PB7 input PB7 output TIOCB8 output TIOCB8 input* Pin function A15 output PB7 input A15 output TCLKH input* TPU channel 8 settings MD3 to MD0 B'0000, B'01 ×× B'0010 B'0011 IOB3 to IOB0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111  B' ××00 Other than B' ××00 CCLR1, CCLR0     Other than B'10 B'10 Output function  Output compare output   PWM mode 2 output Legend: ×: Don’t care Notes: 1. TIOCB8 input when MD3 to MD0 = B'0000 or B'01 ×× and IOB3 = 1. 2. TCLKH input when the setting for eit her TCR_6 or TCR_11 is TPSC2 to TPSC0 = B'111. TCLKH input when phase counting mode is set for channels 8 and 10.

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  • PB6/A14/TIOCA8 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 8 settings (by bits MD3 to MD0 in TMDR_8, bits IOA3 to IOA0 in TIOR_8, and bits CCLR1 and CCLR0 in TCR_8), and bit PB6DDR. Operating mode 1, 2 4, 7 (EXPE = 1) 7 (EXPE = 0) TPU channel 8 settings   (1) in table below (2) in table below PB6DDR  0 1  0 1 PB6 input PB6 output Pin function A14 output PB6 input A14 output TIOCA8 output TIOCA8 input* TPU channel 8 settings MD3 to MD0 B'0000, B'01 ×× B'001 × B'0010 B'0011 IOA3 to IOA0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B' ××00 CCLR1, CCLR0     Other than B'01 B'01 Output function  Output compare output  PWM * mode 1 output PWM mode 2 output Legend: ×: Don’t care Notes: 1. TIOCA8 input when MD3 to MD0 = B'0000 or B'01 ×× and IOA3 = 1. 2. TIOCB8 output disabled.

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  • PB5/A13/TIOCB7/TCLKG The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 7 settings (by bits MD3 to MD0 in TMDR_7, bits IOB3 to IOB0 in TIOR_7, and bits CCLR1 and CCLR0 in TCR_7), bits TPSC2 to TPSC0 in TCR_6, TCR_8, TCR_10, and TCR_11, and bit PB5DDR. Operating mode 1, 2 4, 7 (EXPE = 1) 7 (EXPE = 0) TPU channel 7 settings   (1) in table below (2) in table below PB5DDR  0 1  0 1 PB5 input PB5 output TIOCB7 output TIOCB7 input* Pin function A13 output PB5 input A13 output TCLKG input* TPU channel 7 settings MD3 to MD0 B'0000, B'01 ×× B'0010 B'0011 IOB3 to IOB0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111  B' ××00 Other than B' ××00 CCLR1, CCLR0     Other than B'10 B'10 Output function  Output compare output   PWM mode 2 output Legend: ×: Don’t care Notes: 1. TIOCB7 input when MD3 to MD0 = B'0000 or B'01 ×× and IOB3 to IOB0 = B'10××. 2. TCLKG input when the setting for either TCR_6 or TCR_8 is TPSC2 to TPSC0 = B'111, or when the setting for either TCR_10 or TCR_11 is TPSC2 to TPSC0 = B'101. TCLKG input when phase counting mode is set for channels 8 and 10.

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  • PB4/A12/TIOCA7 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 7 settings (by bits MD3 to MD0 in TMDR_7, bits IOA3 to IOA0 in TIOR_7, and bits CCLR1 and CCLR0 in TCR_7), and bit PB4DDR. Operating mode 1, 2 4, 7 (EXPE = 1) 7 (EXPE = 0) TPU channel 7 settings   (1) in table below (2) in table below PB4DDR  0 1  0 1 PB4 input PB4 output Pin function A12 output PB4 input A12 output TIOCA7 output TIOCA7 input* TPU channel 7 settings MD3 to MD0 B'0000, B'01 ×× B'001 × B'0010 B'0011 IOA3 to IOA0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B' ××00 CCLR1, CCLR0     Other than B'01 B'01 Output function  Output compare output  PWM * mode 1 output PWM mode 2 output Legend: ×: Don’t care Notes: 1. TIOCA7 input when MD3 to MD0 = B'0000 or B'01 ×× and IOA3 to IOA0 = B'10××. 2. TIOCB7 output disabled.

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  • PB3/A11/TIOCD6/TCLKF The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 6 settings (by bits MD3 to MD0 in TMDR_6, bits IOD3 to IOD0 in TIORL_6, and bits CCLR2 to CCLR0 in TCR_6), bits TPSC2 to TPSC0 in TCR_6 to TCR_8, and bit PB3DDR. Operating mode 1, 2 4, 7 (EXPE = 1) 7 (EXPE = 0) TPU channel 6 settings   (1) in table below (2) in table below PB3DDR  0 1  0 1 PB3 input PB3 output TIOCD6 output TIOCD6 input* Pin function A11 output PB3 input A11 output TCLKF input* TPU channel 6 settings MD3 to MD0 B'0000 B'0010 B'0011 IOD3 to IOD0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111  B' ××00 Other than B' ××00 CCLR2 to CCLR0     Other than B'110 B'110 Output function  Output compare output   PWM mode 2 output Legend: ×: Don’t care Notes: 1. TIOCD6 input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10××. 2. TCLKF input when the setting for any of TCR_6 to TCR_8 is TPSC2 to TPSC0 = B'101. TCLKF input when phase counting mode is set for channels 7 and 11.

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  • PB2/A10/TIOCC6/TCLKE The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 6 settings (by bits MD3 to MD0 in TMDR_6, bits IOC3 to IOC0 in TIORL_6, and bits CCLR2 to CCLR0 in TCR_6), bits TPSC2 to TPSC0 in TCR_6 to TCR_11, and bit PB2DDR. Operating mode 1, 2 4, 7 (EXPE = 1) 7 (EXPE = 0) TPU channel 6 settings   (1) in table below (2) in table below PB2DDR  0 1  0 1 PB2 input PB2 output TIOCC6 output TIOCC6 input* Pin function A10 output PB2 input A10 output TCLKE input* TPU channel 6 settings MD3 to MD0 B'0000 B'001 × B'0010 B'0011 IOC3 to IOC0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B' ××00 CCLR2 to CCLR0     Other than B'101 B'101 Output function  Output compare output  PWM * mode 1 output PWM mode 2 output Legend: ×: Don’t care Notes: 1. TIOCC6 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10××. 2. TCLKE input when the setting for any of TCR_6 to TCR_11 is TPSC2 to TPSC0 = B'100. TCLKE input when phase counting mode is set for channels 7 and 11. 3. TIOCD6 output disabled. Output disabl ed and settings (2) effective when BFA = 1 or BFB = 1 in TMDR_6.

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  • PB1/A9/TIOCB6 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 6 settings (by bits MD3 to MD0 in TMDR_6, bits IOB3 to IOB0 in TIORH_6, and bits CCLR2 to CCLR0 in TCR_6), and bit PB1DDR. Operating mode 1, 2 4, 7 (EXPE = 1) 7 (EXPE = 0) TPU channel 6 settings   (1) in table below (2) in table below PB1DDR  0 1  0 1 PB1 input PB1 output Pin function A9 output PB1 input A9 output TIOCB6 output TIOCB6 input* TPU channel 6 settings MD3 to MD0 B'0000 B'0010 B'0011 IOB3 to IOB0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111  B' ××00 Other than B' ××00 CCLR2 to CCLR0     Other than B'010 B'010 Output function  Output compare output   PWM mode 2 output Legend: ×: Don’t care Note: * TIOCB6 input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10 ××.

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  • PB0/A8/TIOCA6 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 6 settings (by bits MD3 to MD0 in TMDR_6, bits IOA3 to IOA0 in TIORH_6, and bits CCLR2 to CCLR0 in TCR_6), and bit PB0DDR. Operating mode 1, 2 4, 7 (EXPE = 1) 7 (EXPE = 0) TPU channel 6 settings   (1) in table below (2) in table below PB0DDR  0 1  0 1 PB0 input PB0 output Pin function A8 output PB0 input A8 output TIOCA6 output TIOCA6 input* TPU channel 6 settings MD3 to MD0 B'0000 B'001 × B'0010 B'0011 IOA3 to IOA0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B' ××00 CCLR2 to CCLR0     Other than B'001 B'001 Output function  Output compare output  PWM * mode 1 output PWM mode 2 output Legend: ×: Don’t care Notes: 1. TIOCA6 input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10 ××. 2. TIOCB6 output disabled.

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10.10.7 Port B Input Pull-Up MOS States

Port B has a built-in input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be used in modes 4 and 7. The input pull-up MOS can be specified as on or off on a bit-by-bit basis. In modes 4 and 7, when a PBDDR bit is cleared to 0, setting the corresponding PBPCR bit to 1 turns on the input pull-up MOS for that pin. Table 10.4 summarizes the input pull-up MOS states. Table 10.4 Input Pull-Up MOS States for Port B Mode Reset Hardware Standby Mode Software Standby Mode In Other Operations 1 or 2 Off Off Off Off 4 or 7 On/Off On/Off Legend: Off: Input pull-up MOS is always off. On/Off: Input pull-up MOS is on when in an input port state 0 and PBPCR = 1; otherwise off.

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10.11 Port C

Port C is an 8-bit I/O port that also has other functions. Port C has the following registers.

  • Port C data direction register (PCDDR)
  • Port C data register (PCDR)
  • Port C register (PORTC)
  • Port C pull-up MOS control register (PCPCR)
  • Port C open drain control register (PCODR)

10.11.1 Port C Data Direction Register (PCDDR)

The individual bits of PCDDR specify input or output for the pins of port C. PCDDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description

7 PC7DDR 0 W

6 PC6DDR 0 W

5 PC5DDR 0 W

4 PC4DDR 0 W

3 PC3DDR 0 W

2 PC2DDR 0 W

1 PC1DDR 0 W

0 PC0DDR 0 W

  • Modes 1 and 2 Port C pins are address outputs regardless of the PCDDR settings.
  • Modes 7 (when EXPE = 1) and 4 Setting a PCDDR bit to 1 makes the corresponding pin an address output, while clearing a PCDDR to 0 makes the corresponding pin an input port.
  • Mode 7 (when EXPE = 0) Port C is an I/O port, and its pin functions can be switched with PCDDR.

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10.11.2 Port C Data Register (PCDR)

PCDR stores output data for the port C pins. Bit Bit Name Initial Value R/W Description

7 PC7DR 0 R/W

6 PC6DR 0 R/W

5 PC5DR 0 R/W

4 PC4DR 0 R/W

3 PC3DR 0 R/W

2 PC2DR 0 R/W

1 PC1DR 0 R/W

0 PC0DR 0 R/W

Output data for a pin is stored when the pin function is specified as a general purpose I/O.

10.11.3 Port C Register (PORTC)

PORTC shows the pin states of port C. PORTC cannot be modified. Bit Bit Name Initial Value R/W Description

7 PC7 * R

6 PC6 * R

5 PC5 * R

4 PC4 * R

3 PC3 * R

2 PC2 * R

1 PC1 * R

0 PC0 * R

If this register is read while a PCDDR bit is set to 1, the corresponding PCDR value is read. If this register is read while a PCDDR bit is cleared to 0, the corresponding pin state is read. Note: * Determined by the states of pins PC7 to PC0.

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10.11.4 Port C Pull-Up MOS Control Register (PCPCR)

PCPCR controls on/off of the input pull-up MOS for port C. PCPCR is valid in modes 4 and 7. Bit Bit Name Initial Value R/W Description

7 PC7PCR 0 R/W

6 PC6PCR 0 R/W

5 PC5PCR 0 R/W

4 PC4PCR 0 R/W

3 PC3PCR 0 R/W

2 PC2PCR 0 R/W

1 PC1PCR 0 R/W

0 PC0PCR 0 R/W

When in a input port state, setting the corresponding bit to 1 turns on the input pull-up MOS for that pin.

10.11.5 Port C Open Drain Control Register (PCODR)

PCODR specifies the output type of each port C pin. Bit Bit Name Initial Value R/W Description

7 PC7ODR 0 R/W

6 PC6ODR 0 R/W

5 PC5ODR 0 R/W

4 PC4ODR 0 R/W

3 PC3ODR 0 R/W

2 PC2ODR 0 R/W

1 PC1ODR 0 R/W

0 PC0ODR 0 R/W

When not specified for address output, setting a PCODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a PCODR bit to 0 makes the corresponding pin a CMOS output pin.

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10.11.6 Pin Functions

Port C pins also function as the pins for TPU I/Os and address outputs. The correspondence between the register specification and the pin functions is shown below.

  • PC7/A7/TIOCB11 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 11 settings (by bits MD3 to MD0 in TMDR_11, bits IOB3 to IOB0 in TIOR_11, and bits CCLR1 and CCLR0 in TCR_11), and bit PC7DDR. Operating mode 1, 2 4, 7 (EXPE = 1) 7 (EXPE = 0) TPU channel 11 settings   (1) in table below (2) in table below PC7DDR  0 1  0 1 PC7 input PC7 output Pin function A7 output PC 7 input A7 output TIOCB11 output TIOCB11 input* TPU channel 11 settings MD3 to MD0 B'0000 B'0010 B'0011 IOB3 to IOB0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111  B' ××00 Other than B' ××00 CCLR1, CCLR0     Other than B'10 B'10 Output function  Output compare output   PWM mode 2 output Legend: ×: Don’t care Note: * TIOCB11 input when MD3 to MD0 = B'0000 or B'01 ×× and IOB3 = 1.

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  • PC6/A6/TIOCA11 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 11 settings (by bits MD3 to MD0 in TMDR_11, bits IOA3 to IOA0 in TIOR_11, and bits CCLR1 and CCLR0 in TCR_11), and bit PC6DDR. Operating mode 1, 2 4, 7 (EXPE = 1) 7 (EXPE = 0) TPU channel 11 settings   (1) in table below (2) in table below PC6DDR  0 1  0 1 PC6 input PC6 output Pin function A6 output PC 6 input A6 output TIOCA11 output TIOCA11 input* TPU channel 11 settings MD3 to MD0 B'0000, B'01 ×× B'001 × B'0010 B'0011 IOA3 to IOA0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B' ××00 CCLR1, CCLR0     Other than B'01 B'01 Output function  Output compare output  PWM * mode 1 output PWM mode 2 output Legend: ×: Don’t care Notes: 1. TIOCA11 input when MD3 to MD0 = B'0000 or B'01 ×× and IOA3 = 1. 2. TIOCB11 output disabled.

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  • PC5/A5/TIOCB10 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 10 settings (by bits MD3 to MD0 in TMDR_10, bits IOB3 to IOB0 in TIOR_10, and bits CCLR1 and CCLR0 in TCR_10), and bit PC5DDR. Operating mode 1, 2 4, 7 (EXPE = 1) 7 (EXPE = 0) TPU channel 10 settings   (1) in table below (2) in table below PC5DDR  0 1  0 1 PC5 input PC5 output Pin function A5 output PC 5 input A5 output TIOCB10 output TIOCB10 input* TPU channel 10 settings MD3 to MD0 B'0000, B'01 ×× B'0010 B'0011 IOB3 to IOB0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111  B' ××00 Other than B' ××00 CCLR1, CCLR0     Other than B'10 B'10 Output function  Output compare output   PWM mode 2 output Legend: ×: Don’t care Note: * TIOCB10 input when MD3 to MD0 = B'0000 or B'01 ×× and IOB3 to IOB0 = B'10××.

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  • PC4/A4/TIOCA10 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 10 settings (by bits MD3 to MD0 in TMDR_10, bits IOA3 to IOA0 in TIOR_10, and bits CCLR1 and CCLR0 in TCR_10), and bit PC4DDR. Operating mode 1, 2 4, 7 (EXPE = 1) 7 (EXPE = 0) TPU channel 10 settings   (1) in table below (2) in table below PC4DDR  0 1  0 1 PC4 input PC4 output Pin function A4 output PC 4 input A4 output TIOCA10 output TIOCA10 input* TPU channel 10 settings MD3 to MD0 B'0000, B'01 ×× B'001 × B'0010 B'0011 IOA3 to IOA0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B' ××00 CCLR1, CCLR0     Other than B'01 B'01 Output function  Output compare output  PWM * mode 1 output PWM mode 2 output Legend: ×: Don’t care Notes: 1. TIOCA10 input when MD3 to MD0 = B'0000 or B'01 ×× and IOA3 to IOA0 = B'10××. 2. TIOCB10 output disabled.

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  • PC3/A3/TIOCD9 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 9 settings (by bits MD3 to MD0 in TMDR_9, bits IOD3 to IOD0 in TIORL_9, and bits CCLR2 to CCLR0 in TCR_9), and bit PC3DDR. Operating mode 1, 2 4, 7 (EXPE = 1) 7 (EXPE = 0) TPU channel 9 settings   (1) in table below (2) in table below PC3DDR  0 1  0 1 PC3 input PC3 output Pin function A3 output PC 3 input A3 output TIOCD9 output TIOCD9 input* TPU channel 9 settings MD3 to MD0 B'0000 B'0010 B'0011 IOD3 to IOD0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111  B' ××00 Other than B' ××00 CCLR2 to CCLR0     Other than B'110 B'110 Output function  Output compare output   PWM mode 2 output Legend: ×: Don’t care Note: * TIOCD9 input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10 ××.

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  • PC2/A2/TIOCC9 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 9 settings (by bits MD3 to MD0 in TMDR_9, bits IOC3 to IOC0 in TIORL_9, and bits CCLR2 to CCLR0 in TCR_9), and bit PC2DDR. Operating mode 1, 2 4, 7 (EXPE = 1) 7 (EXPE = 0) TPU channel 9 settings   (1) in table below (2) in table below PC2DDR  0 1  0 1 PC2 input PC2 output Pin function A2 output PC 2 input A2 output TIOCC9 output TIOCC9 input* TPU channel 9 settings MD3 to MD0 B'0000 B'001 × B'0010 B'0011 IOC3 to IOC0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B' ××00 CCLR2 to CCLR0     Other than B'101 B'101 Output function  Output compare output  PWM * mode 1 output PWM mode 2 output Legend: ×: Don’t care Notes: 1. TIOCC9 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10××. 2. TIOCD9 output disabled. Output disabl ed and settings (2) effective when BFA = 1 or BFB = 1 in TMDR_9.

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  • PC1/A1/TIOCB9 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 9 settings (by bits MD3 to MD0 in TMDR_9, bits IOB3 to IOB0 in TIORH_9, and bits CCLR2 to CCLR0 in TCR_9), and bit PC1DDR. Operating mode 1, 2 4, 7 (EXPE = 1) 7 (EXPE = 0) TPU channel 9 settings   (1) in table below (2) in table below PC1DDR  0 1  0 1 PC1 input PC1 output Pin function A1 output PC 1 input A1 output TIOCB9 output TIOCB9 input* TPU channel 9 settings MD3 to MD0 B'0000 B'0010 B'0011 IOB3 to IOB0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111  B' ××00 Other than B' ××00 CCLR2 to CCLR0     Other than B'010 B'010 Output function  Output compare output   PWM mode 2 output Legend: ×: Don’t care Note: * TIOCB9 input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10 ××.

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  • PC0/A0/TIOCA9 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 9 settings (by bits MD3 to MD0 in TMDR_9, bits IOA3 to IOA0 in TIORH_9, and bits CCLR2 to CCLR0 in TCR_9), and bit PC0DDR. Operating mode 1, 2 4, 7 (EXPE = 1) 7 (EXPE = 0) TPU channel 9 settings   (1) in table below (2) in table below PC0DDR  0 1  0 1 PC0 input PC0 output Pin function A0 output PC 0 input A0 output TIOCA9 output TIOCA9 input* TPU channel 9 settings MD3 to MD0 B'0000 B'001 × B'0010 B'0011 IOA3 to IOA0 B'0000, B'0100, B'1××× B'0001 to B'0011, B'0101 to B'0111 B'××00 Other than B' ××00 CCLR2 to CCLR0     Other than B'001 B'001 Output function  Output compare output  PWM * mode 1 output PWM mode 2 output Legend: ×: Don’t care Notes: 1. TIOCA9 input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10 ××. 2. TIOCB9 output disabled.

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10.11.7 Port C Input Pull-Up MOS States

Port C has a built-in input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be used in modes 4 and 7. The input pull-up MOS can be specified as on or off on a bit-by-bit basis. In modes 4 and 7, when a PCDDR bit is cleared to 0, setting the corresponding PCPCR bit to 1 turns on the input pull-up MOS for that pin. Table 10.5 summarizes the input pull-up MOS states. Table 10.5 Input Pull-Up MOS States for Port C Mode Reset Hardware Standby Mode Software Standby Mode In Other Operations 1 or 2 Off Off Off Off 4 or 7 On/Off On/Off Legend: Off: Input pull-up MOS is always off. On/Off: Input pull-up MOS is on when in an input port state and PCPCR = 1; otherwise off.

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10.12 Port D

Port D is an 8-bit I/O port that also has other functions. Port D has the following registers.

  • Port D data direction register (PDDDR)
  • Port D data register (PDDR)
  • Port D register (PORTD)
  • Port D pull-up MOS control register (PDPCR)
  • Port D open drain control register (PDODR)

10.12.1 Port D Data Direction Register (PDDDR)

The individual bits of PDDDR specify input or output for the pins of port D. PDDDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description

7 PD7DDR 0 W

6 PD6DDR 0 W

5 PD5DDR 0 W

4 PD4DDR 0 W

3 PD3DDR 0 W

2 PD2DDR 0 W

1 PD1DDR 0 W

0 PD0DDR 0 W

  • Modes 7 (when EXPE = 1), 1, 2, and 4 Port D is automatically designated for data input/output.
  • Mode 7 (when EXPE = 0) Port D is an I/O port, and its pin functions can be switched with PDDDR.

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10.12.2 Port D Data Register (PDDR)

PDDR stores output data for the port D pins. Bit Bit Name Initial Value R/W Description

7 PD7DR 0 R/W

6 PD6DR 0 R/W

5 PD5DR 0 R/W

4 PD4DR 0 R/W

3 PD3DR 0 R/W

2 PD2DR 0 R/W

1 PD1DR 0 R/W

0 PD0DR 0 R/W

Output data for a pin is stored when the pin function is specified as a general purpose I/O.

10.12.3 Port D Register (PORTD)

PORTD shows the pin states of port D. PORTD cannot be modified. Bit Bit Name Initial Value R/W Description

7 PD7 * R

6 PD6 * R

5 PD5 * R

4 PD4 * R

3 PD3 * R

2 PD2 * R

1 PD1 * R

0 PD0 * R

If this register is read while a PDDDR bit is set to 1, the corresponding PDDR value is read. If this register is read while a PDDDR bit is cleared to 0, the corresponding pin state is read. Note: * Determined by the states of pins PD7 to PD0.

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10.12.4 Port D Pull-Up MOS Control Register (PDPCR)

PDPCR controls on/off of the input pull-up MOS for port D. PDPCR is valid in mode 7. Bit Bit Name Initial Value R/W Description

7 PD7PCR 0 R/W

6 PD6PCR 0 R/W

5 PD5PCR 0 R/W

4 PD4PCR 0 R/W

3 PD3PCR 0 R/W

2 PD2PCR 0 R/W

1 PD1PCR 0 R/W

0 PD0PCR 0 R/W

When PDDDR = 0 (input port), setting the corresponding bit to 1 turns on the input pull-up MOS for that pin.

10.12.5 Port D Open Drain Control Register (PDODR)

PDODR specifies the output type of each port D pin. Bit Bit Name Initial Value R/W Description

7 PD7ODR 0 R/W

6 PD6ODR 0 R/W

5 PD5ODR 0 R/W

4 PD4ODR 0 R/W

3 PD3ODR 0 R/W

2 PD2ODR 0 R/W

1 PD1ODR 0 R/W

0 PD0ODR 0 R/W

When not specified for data output, setting a PDODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a PDODR bit to 0 makes the corresponding pin a CMOS output pin.

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10.12.6 Pin Functions

Port D pins also function as the pins for data I/Os. The correspondence between the register specification and the pin functions is shown below.

  • PD7/D15, PD6/D14, PD5/D13, PD4/D12, PD3/D11, PD2/D10, PD1/D9, PD0/D8 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, and bit PDnDDR. Operating mode 1, 2, 4 7 EXPE  0 1 PDnDDR  0 1  Pin function Data I/O PDn input PDn output Data I/O Legend: n = 7 to 0

10.12.7 Port D Input Pull-Up MOS States

Port D has a built-in input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be used in mode 7. The input pull-up MOS can be specified as on or off on a bit-by-bit basis. In mode 7, when a PDDDR bit is cleared to 0, setting the corresponding PDPCR bit to 1 turns on the input pull-up MOS for that pin. Table 10.6 summarizes the input pull-up MOS states. Table 10.6 Input Pull-Up MOS States for Port D Mode Reset Hardware Standby Mode Software Standby Mode In Other Operations 1, 2, or 4 Off Off Off Off

7 On/Off On/Off

Legend: Off: Input pull-up MOS is always off. On/Off: Input pull-up MOS is on when P DDDR = 0 and PDPCR = 1; otherwise off.

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10.13 Port E

Port E is an 8-bit I/O port that also has other functions. Port E has the following registers.

  • Port E data direction register (PEDDR)
  • Port E data register (PEDR)
  • Port E register (PORTE)
  • Port E pull-up MOS control register (PEPCR)
  • Port E open drain control register (PEODR)

10.13.1 Port E Data Direction Register (PEDDR)

The individual bits of PEDDR specify input or output for the pins of port E. PEDDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description

7 PE7DDR 0 W

6 PE6DDR 0 W

5 PE5DDR 0 W

4 PE4DDR 0 W

3 PE3DDR 0 W

2 PE2DDR 0 W

1 PE1DDR 0 W

0 PE0DDR 0 W

  • Modes 1, 2, and 4 When 8-bit bus mode is selected, port E is an I/O port, and its pin functions can be switched with PEDDR. When 16-bit bus mode is selected, port E is designated for data input/output. For details on 8-bit and 16-bit bus modes, see section 6, Bus Controller (BSC).
  • Mode 7 (when EXPE = 1) When 8-bit bus mode is selected, port E is an I/O port. Setting a PEDDR bit to 1 makes the corresponding pin an output port, while clearing a PEDDR bit to 0 makes the corresponding pin an input port. When 16-bit bus mode is selected, port E is designated for data input/output.
  • Mode 7 (when EXPE = 0) Port E is an I/O port, and its pin functions can be switched with PEDDR.

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10.13.2 Port E Data Register (PEDR)

PEDR stores output data for the port E pins. Bit Bit Name Initial Value R/W Description

7 PE7DR 0 R/W

6 PE6DR 0 R/W

5 PE5DR 0 R/W

4 PE4DR 0 R/W

3 PE3DR 0 R/W

2 PE2DR 0 R/W

1 PE1DR 0 R/W

0 PE0DR 0 R/W

Output data for a pin is stored when the pin function is specified as a general purpose I/O.

10.13.3 Port E Register (PORTE)

PORTE shows the pin states of port E. PORTE cannot be modified. Bit Bit Name Initial Value R/W Description

7 PE7 * R

6 PE6 * R

5 PE5 * R

4 PE4 * R

3 PE3 * R

2 PE2 * R

1 PE1 * R

0 PE0 * R

If this register is read while a PEDDR bit is set to 1, the corresponding PEDR value is read. If this register is read while a PEDDR bit is cleared to 0, the corresponding pin state is read. Note: * Determined by the states of pins PE7 to PE0.

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10.13.4 Port E Pull-Up MOS Control Register (PEPCR)

PEPCR controls on/off of the input pull-up MOS for port E. PEPCR is valid in 8-bit bus mode. Bit Bit Name Initial Value R/W Description

7 PE7PCR 0 R/W

6 PE6PCR 0 R/W

5 PE5PCR 0 R/W

4 PE4PCR 0 R/W

3 PE3PCR 0 R/W

2 PE2PCR 0 R/W

1 PE1PCR 0 R/W

0 PE0PCR 0 R/W

When PEDDR = 0 (input port), setting the corresponding bit to 1 turns on the input pull-up MOS for that pin.

10.13.5 Port E Open Drain Control Register (PEODR)

PEODR specifies the output type of each port E pin. Bit Bit Name Initial Value R/W Description

7 PE7ODR 0 R/W

6 PE6ODR 0 R/W

5 PE5ODR 0 R/W

4 PE4ODR 0 R/W

3 PE3ODR 0 R/W

2 PE2ODR 0 R/W

1 PE1ODR 0 R/W

0 PE0ODR 0 R/W

When not specified for data output, setting a PEODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a PEODR bit to 0 makes the corresponding pin a CMOS output pin.

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10.13.6 Pin Functions

Port E pins also function as the pins for data I/Os. The correspondence between the register specification and the pin functions is shown below.

  • PE7/D7, PE6/D6, PE5/D5, PE4/D4, PE3/D3, PE2/D2, PE1/D1, PE0/D0 The pin function is switched as shown below according to the combination of the operating mode, bus mode, bit EXPE, and bit PEnDDR. Operating mode 1, 2, 4 7 Bus mode All areas are 8-bit space At least one area is 16-bit space  All areas are 8-bit space At least one area is 16-bit space EXPE   0 1 1 PEnDDR 0 1  0 1 0 1  Pin function PEn input PEn output Data I/O PEn input PEn output PEn input PEn output Data I/O Legend: n = 7 to 0

10.13.7 Port E Input Pull-Up MOS States

Port E has a built-in input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be used in 8-bit bus mode. The input pull-up MOS can be specified as on or off on a bit-by-bit basis. In 8-bit bus mode, when a PEDDR bit is cleared to 0, setting the corresponding PEPCR bit to 1 turns on the input pull-up MOS for that pin. Table 10.7 summarizes the input pull-up MOS states. Table 10.7 Input Pull-Up MOS States for Port E Mode Reset Hardware Standby Mode Software Standby Mode In Other Operations 8-bit bus Off Off On/Off On/Off 1, 2, or 4 16-bit bus Off Off Legend: Off: Input pull-up MOS is always off. On/Off: Input pull-up MOS is on when PE DDR = 0 and PEPCR = 1; otherwise off.

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10.14 Port F

Port F is an 8-bit I/O port that also has other functions. Port F has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers.

  • Port F data direction register (PFDDR)
  • Port F data register (PFDR)
  • Port F register (PORTF)
  • Port function control register 0 (PFCR0)
  • Port function control register 2 (PFCR2)
  • Port function control register 4 (PFCR4)
  • Port function control register 5 (PFCR5)
  • Port F open drain control register (PFODR)

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10.14.1 Port F Data Direction Register (PFDDR)

The individual bits of PFDDR specify input or output for the pins of port F. PFDDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description

7 PF7DDR 1/0 * W

6 PF6DDR 0 W

5 PF5DDR 0 W

4 PF4DDR 0 W

3 PF3DDR 0 W

2 PF2DDR 0 W

1 PF1DDR 0 W

0 PF0DDR 0 W

  • Modes 7 (when EXPE = 1), 1, 2, and 4 Pin PF7 functions as the φ output pin when the corresponding PFDDR bit is set to 1, and as an input port when the bit is cleared to 0. Pin PF6 functions as the AS output pin when the ASOE bit is set to 1. When the ASOE bit is cleared to 0, pin PF6 is an I/O port and its function can be switched with PF6DDR. Pins PF5 and PF4 are automatically designated as bus control outputs (RD and HWR). Pin PF3 functions as the LWR output pin when the LWROE bit is set to 1. When the LWROE bit is cleared to 0, pin PF3 is an I/O port and its function can be switched with PF3DDR. Pins PF2 to PF0 function as bus control input/output pins (LCAS, UCAS, and WAIT) when the appropriate bus controller settings are made. Otherwise, these pins are output ports when the corresponding PFDDR bits are set to 1 and are input ports when the bits are cleared to
  • Mode 7 (when EXPE = 0) Pin PF7 functions as the φ output pin when the corresponding PFDDR bit is set to 1, and as an input port when the bit is cleared to 0. Pins PF6 to PF0 are I/O ports, and their functions can be switched with PFDDR.

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10.14.2 Port F Data Register (PFDR)

PFDR stores output data for the port F pins. Bit Bit Name Initial Value R/W Description

7 PF7DR 0 R/W

6 PF6DR 0 R/W

5 PF5DR 0 R/W

4 PF4DR 0 R/W

3 PF3DR 0 R/W

2 PF2DR 0 R/W

1 PF1DR 0 R/W

0 PF0DR 0 R/W

Output data for a pin is stored when the pin function is specified as a general purpose I/O.

10.14.3 Port F Register (PORTF)

PORTF shows the pin states of port F. PORTF cannot be modified. Bit Bit Name Initial Value R/W Description

7 PF7 * R

6 PF6 * R

5 PF5 * R

4 PF4 * R

3 PF3 * R

2 PF2 * R

1 PF1 * R

0 PF0 * R

If this register is read while a PFDDR bit is set to 1, the corresponding PFDR value is read. If this register is read while a PFDDR bit is cleared to 0, the corresponding pin state is read. Note: * Determined by the states of pins PF7 to PF0.

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10.14.4 Port F Open Drain Control Register (PFODR)

PFODR specifies the output type of each port F pin. Bit Bit Name Initial Value R/W Description

7 PF7ODR 0 R/W

6 PF6ODR 0 R/W

5 PF5ODR 0 R/W

4 PF4ODR 0 R/W

3 PF3ODR 0 R/W

2 PF2ODR 0 R/W

1 PF1ODR 0 R/W

0 PF0ODR 0 R/W

When not specified for φ, AS, AH, RD, HWR, LWR, LCAS, UCAS, DQML, DQMU, CS5, CS6, or OE-A output, setting a PFODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a PFODR bit to 0 makes the corresponding pin a CMOS output pin.

10.14.5 Pin Functions

Port F pins also function as the pins for SSU I/Os, A/D converter inputs, interrupt inputs, bus control signal I/Os, and system clock outputs. The correspondence between the register specification and the pin functions is shown below.

  • PF7/φ The pin function is switched as shown below according to bit PF7DDR. Operating mode 1, 2, 4, 7 PF7DDR 0 1 Pin function PF7 input φ output

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  • PF6/AS/AH The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit MPXE in MPXCR of the bus controller, bit ASOE in PFCR2, and bit PF6DDR. Operating mode 1, 2, 4 7 EXPE  0 1 ASOE 1 0  1 0 PF6DDR  0 1 0 1  0 1 Pin function AS/AH* output PF6 input PF6 output PF6 input PF6 output AS/AH* output PF6 input PF6 output Note: * AH output when MPXE = 1, and AS output when MPXE = 0.
  • PF5/RD The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, and bit PF5DDR. Operating mode 1, 2, 4 7 EXPE  0 1 PF5DDR  0 1  Pin function RD output PF5 input PF5 output RD output
  • PF4/HWR The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, and bit PF4DDR. Operating mode 1, 2, 4 7 EXPE  0 1 PF4DDR  0 1  Pin function HWR output PF4 i nput PF4 output HWR output

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  • PF3/LWR/SSO0-C The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of the SSU, bit LWROE in PFCR2, bits SSOS1 and SSOS0 in PFCR5, and bit PF3DDR. Operating mode LWROE 1 0 0 SSU settings  Can be used as I/O port Input state Output state Can be used as I/O port Input state Output state PF3DDR  0 1 0  0 1 0  Pin function LWR output PF3 input PF3 output SSO0-C input* SSO0-C output* PF3 input PF3 output SSO0-C input* SSO0-C output* Notes: 1. SSO0-C input when SSO0S1 and SSO0S 0 = B'10 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'000×1 or B'01×01. 2. SSO0-C output when SSO0S1 and SSO0S 0 = B'10 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'0011×, B'01×10, or B'10×1×. SSO pin settings SSUMS 0 0 1 BIDE 0 1 0 MSS 0 1 0 1 0 1 TE 0 1 0 1 0 1 0 1 0 1 0 1 RE 1 0 1 1 0 1 1 0 1 0 1 0 1 1 0 1 Pin state Input  Input  Output Output Input Output Input Output  Output Output  Output Output Legend: : Pin is not used by the SSU (can be used as I/O port)

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  • PF2/LCAS/DQML/ IRQ15-A/SSI0-C (H8S/2426 Group and H8S/2426R Group) The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of the SSU, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bits SSI0S1 and SSI0S0 in PFCR5, bits ABW5 to ABW2 in ABWCR, and bit PF2DDR.
  • Modes 1, 2, 4, and 7 (EXPE = 1) Areas 2 to 5 Any DRAM/ synchronous DRAM space area is 16-bit bus space All DRAM/synchronous DRAM space areas are 8-bit bus space, or areas 2 to 5 are all normal space SSU settings  Can be used as I/O port I nput state Output state PF2DDR  0 1 0  LCAS output DQML* output PF2 input PF2 output SSI0-C input * SSI0-C output * Pin function IRQ15-A interrupt input*
  • Mode 7 (EXPE = 0) Areas 2 to 5  SSU settings Can be used as I/O port Input state Output state PF2DDR 0 1 0  PF2 input PF2 out put SSI0-C input * SSI0-C output * Pin function IRQ15-A interrupt input* Notes: 1. IRQ15 input when the ITS15 bit in ITSR is 0. 2. SSI0-C input when SSI0S1 and SSI0S0 = B'10 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'001×1 or B'10××1. 3. SSI0-C output when SSI 0S1 and SSI0S0 = B'10 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'0001×.

Rev. 1.00 Sep. 19, 2008 Page 640 of 1270 REJ09B0466-0100 SSI pin settings SSUMS 0 0 1 BIDE 0 1 0 MSS 0 1 0 1 0 1 TE 0 1 0 1 0 1 0 1 0 1 0 1 RE 1 0 1 1 0 1 1 0 1 0 1 0 1 1 0 1 Pin state  Output Output Input  Input     Input  Input Input  Input Legend: : Pin is not used by the SSU (can be used as I/O port)

  • PF2/CS6/LCAS/SSI0-C (H8S/2424 Group) The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of the SSU, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit CS6E in PFCR0, bits SSI0S1 and SSI0S0 in PFCR5, bits ABW5 to ABW2 in ABWCR, and bit PF2DDR.
  • Modes 1, 2, 4, and 7 (EXPE = 1) Areas 2 to 5 Any DRAM/ synchronous DRAM space area is 16-bit bus space All DRAM/synchronous DRAM space areas are 8-bit bus space, or areas 2 to 5 are all normal space CS6E  0 1 SSU settings  Can be used as I/O port Input state Output state PF2DDR  0 1 0  0 1 Pin function LCAS output PF2 input PF2 output SSI0-C input* SSI0-C output* PF2 input CS6 output

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  • Mode 7 (EXPE = 0) Areas 2 to 5  CS6E  SSU settings Can be used as I/O port Input state Output state PF2DDR 0 1 0  Pin function PF2 input PF2 output SSI0-C input * SSI0-C output * Notes: 1. SSI0-C input when SSI0S1 and SSI0S 0 = B'10 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'001×1 or B'10××1. 2. SSI0-C output when SSI 0S1 and SSI0S0 = B'10 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'0001×. SSI pin settings SSUMS 0 0 1 BIDE 0 1 0 MSS 0 1 0 1 0 1 TE 0 1 0 1 0 1 0 1 0 1 0 1 RE 1 0 1 1 0 1 1 0 1 0 1 0 1 1 0 1 Pin state  Output Output Input  Input     Input  Input Input  Input Legend: : Pin is not used by the SSU (can be used as I/O port)

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  • PF1/UCAS/DQMU/ IRQ14-A/SSCK0-C (H8S/2426 Group and H8S/2426R Group) The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits MSS and SCKS in SSCRH and bit SSUMS in SSCRL of the SSU, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bits SSCK0S1 and SSCK0S0 in PFCR5, and bit PF1DDR.
  • Modes 1, 2, 4, and 7 (EXPE = 1) Areas 2 to 5 Any of areas 2 to 5 is DRAM/synchronous DRAM space Areas 2 to 5 are all normal space SSU settings  Can be used as I/O port I nput state Output state PF1DDR  0 1 0  UCAS output DQMU* output PF1 input PF1 output SSCK0-C input* SSCK0-C output* Pin function IRQ14-A interrupt input*
  • Mode 7 (EXPE = 0) Areas 2 to 5  SSU settings Can be used as I/O port Input state Output state PF1DDR 0 1 0  PF1 input PF1 output SSCK0-C input * SSCK0-C output * Pin function IRQ14-A interrupt input* Notes: 1. IRQ14 input when the ITS14 bit in ITSR is 0. 2. SSCK0-C input when SSCK0S1 and SSCK0S0 = B'10 in PFCR5, and SSUMS, MSS, and SCKS = B'001 or B'101. 3. SSCK0-C output when SSCK0S1 and SSCK0S0 = B'10 in PFCR5, and SSUMS, MSS, and SCKS = B'×11. SSCK pin settings SSUMS 0 1 MSS 0 1 0 1 SCKS 0 1 0 1 0 1 0 1 Pin state  Input  Output  Input  Output Legend: : Pin is not used by the SSU (can be used as I/O port)

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  • PF1/CS5/UCAS/SSCK0-C (H8S/2424 Group) The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits MSS and SCKS in SSCRH and bit SSUMS in SSCRL of the SSU, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit CS5E in PFCR0, bits SSCK0S1 and SSCK0S0 in PFCR5, and bit PF1DDR.
  • Modes 2, 4, and 7 (EXPE = 1) Areas 2 to 5 Any of areas 2 to 5 is DRAM space Areas 2 to 5 are all normal space CS5E  0 1 SSU settings  Can be used as I/O port Input state Output state PF1DDR  0 1 0  0 1 Pin function UCAS output PF1 input PF1 output SSCK0-C input* SSCK0-C output* PF1 input CS5 output
  • Mode 7 (EXPE = 0) Areas 2 to 5  CS5E  SSU settings Can be used as I/O port Input state Output state PF1DDR 0 1 0  Pin function PF1 input PF1 output SSCK0-C input * SSCK0-C output * Notes: 1. SSCK0-C input when SSCK0S1 and SSCK0S0 = B'10 in PFCR5, and SSUMS, MSS, and SCKS = B'001 or B'101. 2. SSCK0-C output when SSCK0S1 and SSCK0S0 = B'10 in PFCR5, and SSUMS, MSS, and SCKS = B'×11. SSCK pin settings SSUMS 0 1 MSS 0 1 0 1 SCKS 0 1 0 1 0 1 0 1 Pin state  Input  Output  Input  Output Legend: : Pin is not used by the SSU (can be used as I/O port)

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  • PF0/WAIT-A/ADTRG0-B/SCS0-C (H8S/2426 Group and H8S/2426R Group) The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit WAITE in BCR of the bus controller, bits MSS, CSS1, and CSS0 in SSCRH and bit SSUMS in SSCRL of the SSU, bits TRGS1, TRGS0, and EXTRGS in ADCR_0 of the ADC, bits ADTRG0S and WAITS in PFCR4, bits SCS0S1 and SCS0S0 in PFCR5, and bit PF0DDR.
  • Modes 1, 2, 4, and 7 (EXPE = 1) WAITE 0 1 SSU settings Can be used as I/O port Input state Output state  PF0DDR 0 1 0   PF0 input PF0 output SCS0-C input* SCS0-C output* WAIT-A input* Pin function ADTRG0-B input*
  • Mode 7 (EXPE = 0) WAITE  SSU settings Can be used as I/O port Input state Output state PF0DDR 0 1 0  PF0 input PF0 output SCS0-C input* SCS0-C output* Pin function ADTRG0-B input* Notes: 1. ADTRG0-B input when the ADTRG0S bit in PFCR4 is 1, TRGS1 = TRGS0 = 0, and EXTRGS = 1 2. WAIT-A input when the WAITS bit in PFCR4 is 0. 3. SCSO-C input when SCS0S1 and SCS0S0 = B'10 in PFCR5, and SSUMS, MSS, CSS1, and CSS0 = B'00××, B'0101, or B'0110. 4. SCSO-C output when SCS0S1 and SCS0S0 = B'10 in PFCR5, and SSUMS, MSS, CSS1, and CSS0 = B'011×.

Rev. 1.00 Sep. 19, 2008 Page 645 of 1270 REJ09B0466-0100 SCS pin settings SSUMS 0 1 MSS 0 1 × CSS1 × 0 1 × CSS0 × 0 1 0 1 × Pin state Input  Input Automatic I/O Output  Legend: ×: Don’t care : Pin is not used by the SSU (can be used as I/O port)

  • PF0/WAIT-A/ADTRG0-B/SCS0-C/OE-A (H8S/2424 Group) The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit WAITE in BCR of the bus controller, bit OEE in DRAMCR, bits MSS, CSS1, and CSS0 in SSCRH and bit SSUMS in SSCRL of the SSU, bits TRGS1, TRGS0, and EXTRGS in ADCR_0 of the ADC, bit OES in PFCR2, bits ADTRG0S and WAITS in PFCR4, bits SCS0S1 and SCS0S0 in PFCR5, and bit PF0DDR.
  • Modes 1, 2, 4, and 7 (EXPE = 1) OEE 0 1 RMTS2 to RMTS0   Areas 2 to 5 are DRAM space WAITE 0 1 0 1  SSU settings Can be used as I/O port Input state Output state  Can be used as I/O port Input state Output state   PF0DDR 0 1 0   0 1 0    PF0 input PF0 output SCS0-C input* SCS0-C output* WAIT-A input* PF0 input PF0 output SCS0-C input* SCS0-C output* WAIT-A input* OE-A output Pin function ADTRG0-B input*

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  • Mode 7 (EXPE = 0) OEE  Area 2  WAITE  SSU settings  Input state Output state PF0DDR 0 1 0  PF0 input PF0 output SCS0-C input* SCS0-C output* Pin function ADTRG0-B input* Notes: 1. ADTRG0-B input when the ADTRG0S bit in PFCR4 is 1, TRGS1 = TRGS0 = 0, and EXTRGS = 1 2. WAIT-A input when the WAITS bit in PFCR4 is 0. 3. SCSO-C input when SCS0S1 and SCS0S0 = B'10 in PFCR5, and SSUMS, MSS, CSS1, and CSS0 = B'00××, B'0101, or B'0110. 4. SCSO-C output when SCS0S1 and SCS0S0 = B'10 in PFCR5, and SSUMS, MSS, CSS1, and CSS0 = B'011×. SCS pin settings SSUMS 0 1 MSS 0 1 × CSS1 × 0 1 × CSS0 × 0 1 0 1 × Pin state Input  Input Automatic I/O Output  Legend: ×: Don’t care : Pin is not used by the SSU (can be used as I/O port)

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10.15 Port G

Port G is a 7-bit I/O port that also has other functions. Port G has the following registers.

  • Port G data direction register (PGDDR)
  • Port G data register (PGDR)
  • Port G register (PORTG)
  • Port function control register 0 (PFCR0)
  • Port function control register 4 (PFCR4)
  • Port G open drain control register (PGODR)

10.15.1 Port G Data Direction Register (PGDDR)

The individual bits of PGDDR specify input or output for the pins of port G. PGDDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description 7  0  Reserved

6 PG6DDR 0 W

5 PG5DDR 0 W

4 PG4DDR 0 W

3 PG3DDR 0 W

2 PG2DDR 0 W

1 PG1DDR 0 W

0 PG0DDR 1/0 * W

  • Modes 7 (when EXPE = 1), 1, 2, and 4 Pins PG6 to PG4 function as bus control input/output pins (BREQO, BACK, and BREQ) when the appropriate bus controller settings are made. Otherwise, these pins are I/O ports, and their functions can be switched with PGDDR. When the CS output enable bits (CS3E to CS0E) are set to 1, pins PG3 to PG0 function as CS output pins when the corresponding PGDDR bit is set to 1, and as input ports when the bit is cleared to 0. When the CS output enable bits (CS3E to CS0E) are cleared to 0, pins PG3 to PG0 are I/O ports, and their functions can be switched with PGDDR.
  • Mode 7 (when EXPE = 0) Pins PG6 to PG0 are I/O ports, and their functions can be switched with PGDDR. Note: * PG0DDR is initialized to 1 in modes 1 and 2, and to 0 in modes 4 and 7.

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10.15.2 Port G Data Register (PGDR)

PGDR stores output data for the port G pins. Bit Bit Name Initial Value R/W Description 7  0  Reserved This bit is always read as 0, and cannot be modified.

6 PG6DR 0 R/W

5 PG5DR 0 R/W

4 PG4DR 0 R/W

3 PG3DR 0 R/W

2 PG2DR 0 R/W

1 PG1DR 0 R/W

0 PG0DR 0 R/W

Output data for a pin is stored when the pin function is specified as a general purpose I/O.

10.15.3 Port G Register (PORTG)

PORTG shows the pin states of port G. PORTG cannot be modified. Bit Bit Name Initial Value R/W Description 7  Undefined  Reserved If this bit is read, it will return an undefined value.

6 PG6 * R

5 PG5 * R

4 PG4 * R

3 PG3 * R

2 PG2 * R

1 PG1 * R

0 PG0 * R

If this register is read while a PGDDR bit is set to 1, the corresponding PGDR value is read. If this register is read while a PGDDR bit is cleared to 0, the corresponding pin state is read. Note: * Determined by the states of pins PG6 to PG0.

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10.15.4 Port G Open Drain Control Register (PGODR)

PGODR specifies the output type of each port G pin. Bit Bit Name Initial Value R/W Description 7  0  Reserved This bit is always read as 0. Only the initial value should be written to this bit.

6 PG6ODR 0 R/W

5 PG5ODR 0 R/W

4 PG4ODR 0 R/W

3 PG3ODR 0 R/W

2 PG2ODR 0 R/W

1 PG1ODR 0 R/W

0 PG0ODR 0 R/W

When not specified for BACK-A, BREQO-A, CS0, CS1, CS2, CS3, CS4, RAS2, RAS3, RAS, or CAS output, setting a PGODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a PGODR bit to 0 makes the corresponding pin a CMOS output pin.

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10.15.5 Pin Functions

Port G pins also function as the pins for JTAG inputs and bus control signal I/Os. The correspondence between the register specification and the pin functions is shown below.

  • PG6/BREQ-A/TDI* The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit BRLE in BCR of the bus controller, bit BREQS in PFCR4, and bit PG6DDR. Operating mode 1, 2, 4 7 EXPE  0 1 BRLE BREQS BRLE = 0 or BRLE = 1 and BREQS = 1 BRLE = 1 and BREQS = 0  BRLE = 0 or BRLE = 1 and BREQS = 1 BRLE = 1 and BREQS = 0 PG6DDR 0 1  0 1 0 1  PG6 input PG6 output BREQ-A input PG6 input PG6 output PG6 input PG6 output BREQ-A input Pin function TDI input* Notes: 1. Supported only in the 145-pin package. 2. TDI input when BSCANE pin = 1 in the 145-pin package.

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  • PG5/BACK-A/TMS* The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit BRLE in BCR of the bus controller, bit BACKS in PFCR4, and bit PG5DDR. Operating mode 1, 2, 4 7 EXPE  0 1 BRLE BACKS BRLE = 0 or BRLE = 1 and BACKS = 1 BRLE = 1 and BACKS = 0  BRLE = 0 or BRLE = 1 and BACKS = 1 BRLE = 1 and BACKS = 0 PG5DDR 0 1  0 1 0 1  PG5 input PG5 output BACK-A output PG5 input PG5 output PG5 input PG5 output BACK-A output Pin function TMS input* Notes: 1. Supported only in the 145-pin package. 2. TMS input when BSCANE pin = 1 in the 145-pin package.
  • PG4/BREQO-A/CS4* /TCK* The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit BRLE in BCR of the bus controller, bit BREQOE, bit BREQOS in PFCR4, and bit PG4DDR.
  • Modes 1, 2, 4, and 7 (EXPE = 1) BRLE 0 1 BREQOE BREQOS  BREQOE = 0 or BREQOE = 1 and BREQOS = 1 BREQO = 1 and BREQOS = 0 CS4E 0 1 0 1  PG4DDR 0 1  0 1   PG4 input PG4 output CS4 output* PG4 input PG4 output CS4 output* BREQO-A output Pin function TCK input*

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  • Mode 7 (EXPE = 0) BRLE  BREQOE BREQOS CS4E 0 1 PG4DDR 0 1  PG4 input PG4 output CS4 output* Pin function TCK input* Notes: 1. Not supported in the H8 S/2426 Group and H8S/2426R Group. 2. Supported only in the 145-pin package. 3. TCK input when BSCANE pin = 1 in the 145-pin package.
  • PG3/CS3/RAS3/CAS* The pin function is switched as shown below according to the combination of the operating mode, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit CS3E in PFCR0, and bit PG3DDR. Operating mode 1, 2, 4 7 EXPE  0 1 CS3E 0 1  0 1 RMTS2 to RMTS0  Area 3 is in normal space Area 3 is in DRAM space Areas 2 to 5 are in synchronous DRAM* space   Area 3 is in normal space Area 3 is in DRAM space Areas 2 to 5 are in synchronous DRAM* space PG3DDR 0 1 0 1   0 1 0 1 0 1   Pin function PG3 input PG3 output PG3 input CS3 output RAS3 output CAS* output PG3 input PG3 output PG3 input PG3 output PG3 input CS3 output RAS3 output CAS* output Note: * Not supported in the H8S/2426 Group and H8S/2424 Group.

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  • PG2/CS2/RAS2/RAS* The pin function is switched as shown below according to the combination of the operating mode, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit CS2E in PFCR0, and bit PG2DDR. Operating mode 1, 2, 4 7 EXPE  0 1 CS2E 0 1  0 1 RMTS2 to RMTS0  Area 2 is in normal space Area 2 is in DRAM space Areas 2 to 5 are in synchronous DRAM* space   Area 2 is in normal space Area 2 is in DRAM space Areas 2 to 5 are in synchronous DRAM* space PG2DDR 0 1 0 1   0 1 0 1 0 1   Pin function PG2 input PG2 output PG2 input CS2 output RAS2 output RAS* output PG2 input PG2 output PG2 input PG2 output PG2 input CS2 output RAS2 output RAS* output Note: * Not supported in the H8S/2426 Group and H8S/2424 Group.
  • PG1/CS1, PG0/CS0 The pin function is switched as shown below according to the combination of the operating mode, bit CSnE in PFCR0, and bit PGnDDR. Operating mode 1, 2, 4 7 EXPE  0 1 CSnE 0 1  0 1 PGnDDR 0 1 0 1 0 1 0 1 0 1 Pin function PGn input PGn output PGn input CSn output PGn input PGn output PGn input PGn output PGn input CSn output Legend: n = 1 or 0

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10.16 Port H

Note: Port H is not supported in the H8S/2424 Group. Port H is a 4-bit I/O port that also has other functions. Port H has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers.

  • Port H data direction register (PHDDR)
  • Port H data register (PHDR)
  • Port H register (PORTH)
  • Port function control register 0 (PFCR0)
  • Port function control register 2 (PFCR2)
  • Port H open drain control register (PHODR)

10.16.1 Port H Data Direction Register (PHDDR)

The individual bits of PHDDR specify input or output for the pins of port H. PHDDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description 7 to 4  All 0  Reserved

3 PH3DDR 0 W

2 PH2DDR 0 W

1 PH1DDR 0 W

0 PH0DDR 0 W

  • Modes 7 (when EXPE = 1), 1, 2, and 4 When the OE output enable bit (OEE) and OE output select bit (OES) are set to 1, pin PH3 functions as the OE output pin. Otherwise, when bit CS7E is set to 1, pin PH3 functions as the CS7 output pin when bit PH3DDR is set to 1, and as an input port when the bit is cleared to 0. When bit CS7E is cleared to 0, pin PH3 is an I/O port, and its function can be switched with bit PH3DDR. When areas 2 to 5 are specified as continuous SDRAM space*, OE output is CKE output. When bit CS6E is set to 1, setting bit PH2DDR to 1 makes pin PH2 function as the CS6 output pin, and clearing the bit to 0 makes the pin function as an I/O port. When bit CS6E is cleared to 0, pin PH2 is an I/O port, and its function can be switched with bit PH2DDR.

Rev. 1.00 Sep. 19, 2008 Page 655 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description

0 PH0DDR 0 W Pin PH1 functions as the SDRAM φ* output pin

when the SDPSTP bit is 0 in a product supporting the SDRAM interface. In a product not supporting the SDRAM interface or when the SDPSTP bit is 1, if bit CS5E is set to 1 while area 5 is specified as normal space, pin PH1 functions as the CS5 output pin when bit PH1DDR is set to 1, and functions as an I/O port when the bit is cleared to 0. When bit CS5E is cleared to 0, pin PH1 is an I/O port, and its function can be switched with bit PH1DDR. When area 5 is specified as DRAM space and bit CS5E is set to 1, pin PH1 functions as the RAS5 output pin and as an I/O port when the bit is cleared to 0. Pin PH0 functions as the CS4 output pin when area 4 is specified as normal space and bit PH0DDR is set to 1. If bit PH0DDR is cleared to 0, pin PH0 functions as an I/O port. When bit CS4E is cleared to 0, pin PH0 is an I/O port, and its function can be switched with bit PH0DDR. When area 4 is specified as DRAM space and bit CS4E is set to 1, pin PH0 functions as the RAS4 output pin and as an I/O port when the bit is cleared to 0. When areas 2 to 5 are specified as continuous SDRAM space*, pin PH0 functions as the WE output pin when bit CS4E is set to 1, and as an I/O port when the bit is cleared to 0.

  • Mode 7 (when EXPE = 0) Pins PH3 to PH0 are I/O ports, and their functions can be switched with PHDDR. Pin PH1 functions as the SDRAMφ output pin when the SDPSTP bit is 0 in a product supporting the SDRAM interface. In a product not supporting the SDRAM interface or when the SDPSTP bit is 1, pin PH1 is an I/O port and its function can be switched with PHDDR. Note: * Not supported in the H8S/2426 Group.

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10.16.2 Port H Data Register (PHDR)

PHDR stores output data for the port H pins. Bit Bit Name Initial Value R/W Description 7 to 4  All 0  Reserved These bits are always read as 0 and cannot be modified.

3 PH3DR 0 R/W

2 PH2DR 0 R/W

1 PH1DR 0 R/W

0 PH0DR 0 R/W

Output data for a pin is stored when the pin function is specified as a general purpose I/O.

10.16.3 Port H Register (PORTH)

PORTH shows the pin states of port H. PORTH cannot be modified. Bit Bit Name Initial Value R/W Description 7 to 4  Undefined  Reserved If these bits are read, they will return an undefined value.

3 PH3 * R

2 PH2 * R

1 PH1 * R

0 PH0 * R

If this register is read while a PHDDR bit is set to 1, the corresponding PHDR value is read. If this register is read while a PHDDR bit is cleared to 0, the corresponding pin state is read. Note: * Determined by the states of pins PH3 to PH0.

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10.16.4 Port H Open Drain Control Register (PHODR)

PHODR specifies the output type of each port H pin. Bit Bit Name Initial Value R/W Description 7 to 4  All 0  Reserved These bits are always read as 0. Only the initial values should be written to these bits.

3 PH3ODR 0 R/W

2 PH2ODR 0 R/W

1 PH1ODR 0 R/W

0 PH0ODR 0 R/W

When not specified for CS4, CS5, CS6, CS7, OE- A, CKE-A, RAS4, RAS5, WE, or SDRAMφ* output, setting a PHODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a PHODR bit to 0 makes the corresponding pin a CMOS output pin. Note: * Not supported in the H8S/2426 Group.

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10.16.5 Pin Functions

Port H pins also function as bus control signal I/Os and interrupt inputs. The correspondence between the register specification and the pin functions is shown below.

  • PH3/CS7/OE-A/CKE-A/IRQ7-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit OEE in DRAMCR of the bus controller, bit OES in PFCR2, bit CS7E in PFCR0, and bit PH3DDR.
  • Modes 1, 2, 4, and 7 (EXPE = 1) OEE 0 1 OES 0 0 1 RMTS2 to RMTS0   Areas 2 to 5 are DRAM space Areas 2 to 5 are syn- chronous DRAM space* CS7E 0 1 0 1   PH3DDR 0 1 0 1 0 1 0 1   PH3 input PH3 output PH3 input CS7 output PH3 input PH3 output PH3 input CS7 output OE-A output* CKE-A* output* Pin function IRQ7-B input*
  • Mode 7 (EXPE = 0) OEE  OES  RMTS2 to RMTS0  CS7E  PH3DDR 0 1 PH3 input PH3 output Pin function IRQ7-B input* Notes: 1. IRQ7-B input when the ITS7 bit in ITSR is 1. 2. OE-A/CKE-A output when the OES bit in PFCR2 is 1. 3. Not supported in the H8S/2426 Group.

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  • PH2/CS6/IRQ6-B The pin function is switched as shown below according to the combination of the operating mode, bit CS6E in PFCR0, and bit PH2DDR. Operating mode 1, 2, 4 7 EXPE  0 1 CS6E 0 1  0 1 PH2DDR 0 1 0 1 0 1 0 1 0 1 PH2 input PH2 output PH2 input CS6 output PH2 input PH2 output PH2 input PH2 output PH2 input CS6 output Pin function IRQ6-B interrupt input* Note: * IRQ6-B input when the ITS6 bit in ITSR is 1.
  • PH1/CS5/RAS5/SDRAM φ* The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit SDPSTP in SCKCR of the clock pulse generator, bit CS5E in PFCR0 and bit PH1DDR. SDPSTP 1 0 Operating mode 1, 2, 4 7  EXPE  0 1  OEE 0 1  0 1  OES  0   0  RMTS2 to RMTS0 Area 5 is normal space Area 5 is DRAM space  Area 5 is normal space Area 5 is DRAM space CS5E 0 1 0 1  0 1 0 1  PH1DDR 0 1 0 1 0 1  0 1 0 1 0 1 0 1   Pin function PH1 input PH1 output PH1 input CS5 output PH1 input PH1 output RAS5 output PH1 input PH1 output PH1 input PH1 output PH1 input CS5 output PH1 input PH1 output RAS5 output SDRAMφ output* Note: * Not supported in the H8S/2426 Group.

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  • PH0/CS4/RAS4/WE* The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit CS4E in PFCR0, and bit PH0DDR. Operating mode 1, 2, 4 7 EXPE  0 1 CS4E 0 1  0 1 RMTS2 to RMTS0  Area 4 is normal space Area 4 is DRAM space Areas 2 to 5 are syn- chronous DRAM* space   Area 4 is normal space Area 4 is DRAM space Areas 2 to 5 are syn- chronous DRAM* space PH0DDR 0 1 0 1   0 1 0 1 0 1   Pin function PH0 input PH0 output PH0 input CS4 output RAS4 output WE* output PH0 input PH0 output PH0 input PH0 output PH0 input CS4 output RAS4 output WE* output Note: * Not supported in the H8S/2426 Group.

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10.17 Port J

Note: Port J is not supported in the H8S/2424 Group and in the 145-pin package. Port J is a 3-bit I/O port. Port J has the following registers.

  • Port J data direction register (PJDDR)
  • Port J data register (PJDR)
  • Port J register (PORT3)
  • Port J open drain control register (PJODR)

10.17.1 Port J Data Direction Register (PJDDR)

The individual bits of PJDDR specify input or output for the pins of port J. PJDDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description 7 to 2  All 0  Reserved

1 PJ1DDR 0 W

0 PJ0DDR 0 W

When a pin function is specified as a general purpose I/O, setting this bit to 1 makes the corresponding pin an output port, while clearing this bit to 0 makes the corresponding pin an input port.

10.17.2 Port J Data Register (PJDR)

PJDR stores output data for the port J pins. Bit Bit Name Initial Value R/W Description 7 to 2  All 0  Reserved These bits are always read as 0 and cannot be modified.

1 PJ1DR 0 R/W

0 PJ0DR 0 R/W

Output data for a pin is stored when the pin function is specified as a general purpose I/O.

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10.17.3 Port J Register (PORTJ)

PORTJ shows the pin states of port J. PORTJ cannot be modified. Bit Bit Name Initial Value R/W Description 7 to 3  Undefined  Reserved If these bits are read, they will return an undefined value. 2 PJ2 * R The pin state is always read from this register. Bit 2 is reserved for the 145-pin version.

1 PJ1 * R

0 PJ0 * R

If this register is read, the PJDR values are read for the bits with the corresponding PJDDR bits set to 1. For the bits with the corresponding PJDDR bits cleared to 0, the pin states are read. Note: * Determined by the state of pins PJ0 to PJ2.

10.17.4 Port J Open Drain Control Register (PJODR)

PJODR specifies the output type of each port J pin. Bit Bit Name Initial Value R/W Description 7 to 2  All 0  Reserved These bits are always read as 0. Only the initial values should be written to these bits.

1 PJ1ODR 0 R/W

0 PJ0ODR 0 R/W

Setting a PJODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a PJODR bit to 0 makes the corresponding pin a CMOS output pin.

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10.17.5 Pin Functions

Port J pins function only as I/O ports. The correspondence between the register specification and the pin functions is shown below.

  • PJ2* The PJ2 pin is an input-only pin. Pin function PJ2 input Note: * Not supported in the 145-pin package.
  • PJ1, PJ0 The pin function is switched as shown below according to bit PJnDDR. PJnDDR 0 1 Pin function PJn input PJn output Legend: n = 1 or 0

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10.18 Port Function Control Registers

The port function controller performs I/O port control. The setting of input or output for each pin should be enabled only after the input or output destination has been selected. The port function controller has the following registers.

  • Port function control register 0 (PFCR0)
  • Port function control register 1 (PFCR1)
  • Port function control register 2 (PFCR2)
  • Port function control register 3 (PFCR3)
  • Port function control register 4 (PFCR4)
  • Port function control register 5 (PFCR5)

10.18.1 Port Function Control Register 0 (PFCR0)

PFCR0 switches the functions of the chip select output pins. Bit Bit Name Initial Value R/W Description

7 CS7E 1 R/W

6 CS6E 1 R/W

5 CS5E 1 R/W

4 CS4E 1 R/W

3 CS3E 1 R/W

2 CS2E 1 R/W

1 CS1E 1 R/W

0 CS0E 1 R/W

These bits enable or disable the corresponding CSn output. 0: Pin is designated as I/O port 1: Pin is designated as CSn output pin (n = 7 to 0)

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10.18.2 Port Function Control Register 1 (PFCR1)

PFCR1 enables or disables address output (A23 to A16). Bits 7 to 5 are valid in modes 1 and 2 and all the bits are valid in modes 4 and 7. Bit Bit Name Initial Value R/W Description

7 A23E 1 R/W Address 23 Enable

Enables or disables output for address output 23 (A23). 0: DR output when PA7DDR = 1 1: A23 output when PA7DDR = 1

6 A22E 1 R/W Address 22 Enable

Enables or disables output for address output 22 (A22). 0: DR output when PA6DDR = 1 1: A22 output when PA6DDR = 1

5 A21E 1 R/W Address 21 Enable

Enables or disables output for address output 21 (A21). 0: DR output when PA5DDR = 1 1: A21 output when PA5DDR = 1

4 A20E 1 R/W Address 20 Enable

Enables or disables output for address output 20 (A20). 0: DR output when PA4DDR = 1 1: A20 output when PA4DDR = 1

3 A19E 1 R/W Address 19 Enable

Enables or disables output for address output 19 (A19). 0: DR output when PA3DDR = 1 1: A19 output when PA3DDR = 1

2 A18E 1 R/W Address 18 Enable

Enables or disables output for address output 18 (A18). 0: DR output when PA2DDR = 1 1: A18 output when PA2DDR = 1

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1 A17E 1 R/W Address 17 Enable

Enables or disables output for address output 17 (A17). 0: DR output when PA1DDR = 1 1: A17 output when PA1DDR = 1

0 A16E 1 R/W Address 16 Enable

Enables or disables output for address output 16 (A16). 0: DR output when PA0DDR = 1 1: A16 output when PA0DDR = 1

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10.18.3 Port Function Control Register 2 (PFCR2)

PFCR2 enables or disables AS output, LWR output, and OE output. Bit Bit Name Initial Value R/W Description 7 to 4  All 0  Reserved These bits are always read as 0 and cannot be modified.

3 ASOE 1 R/W AS Output Enable

Enables or disables the AS output pin. 0: PF6 is designated as I/O port 1: PF6 is designated as AS output pin

2 LWROE 1 R/W LWR Output Enable

Enables or disables the LWR output pin. 0: PF3 is designated as I/O port 1: PF3 is designated as LWR output pin

1 OES 1 R/W OE Output Select

Selects the OE/CKE* output pin port when the OEE bit in DRAMCR is set to 1 (enabling OE/CKE* output). 0: P35 is designated as OE-B/CKE-B* output pin. 1: PH3* is designated as OE-A/CKE-A* output pin. 0  0  Reserved This bit is always read as 0. Only the initial value should be written to this bit. Notes: 1. Not supported in the H8S/2424 Group. 2. PH3 becomes PF0 in the H8S/2424 Group.

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10.18.4 Port Function Control Register 3 (PFCR3)

PFCR3 switches the functions of the PPG output pin, TPU input/output pin, and TMR input/output pin. Bit Bit Name Initial Value R/W Description 7  1  Reserved This bit is always read as 1. Only the initial value should be written to this bit.

6 PPGS 0 R/W PPG Pin Select

Selects the output pins of PO5 to PO0. 0: P25/PO5-A, P24/PO4-A, P23/PO3-A, P22/PO2- A, P21/PO1-A, and P20/PO0-A are selected 1: P85/PO5-B, P52/PO4-B, P83/PO3-B, P51/PO2- B, P81/PO1-B, and P50/PO0-B are selected

5 TPUS 0 R/W TPU Pin Select

Selects the output pins of TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, and TIOCB4. 0: P25/TIOCB4-A, P24/TIOCA4-A, P23/TIOCD3-A, P22/TIOCC3-A, P21/TIOCB3-A, and P20/TIOCA3-A are selected 1: P85/TIOCB4-B, P52/TIOCA4-B, P83/TIOCD3-B, P51/TIOCC3-B, P81/TIOCB3-B, and P50/TIOCA3-B are selected

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4 TMRS 0 R/W TMR Pin Select

Selects the output pins of TMO1 and TMO0 and input pins of TMCI1, TMCI0, TMRI1, and TMRI0. 0: [For H8S/2424] P25/TMO1-A, P24/TMO0-A, P23/TMCI1-A, P22/TMCI0-A, P21/TMRI1-A, and P20/TMRI0-A are selected [For H8S/2426, H8S/2426R] P65/TMO1-A, P64/TMO0-A, P63/TMCI1-A, P62/TMCI0-A, P61/TMRI1-A, and P60/TMRI0-A are selected 1: P85/TMO1-B , P52/TMO0-B, P83/TMCI1-B, P51/TMCI0-B, P81/TMRI1-B, and P50/TMRI0-B are selected 3 to 1  All 0  Reserved These bits are always read as 0. Only the initial values should be written to these bits. 0  1  Reserved This bit is always read as 1. Only the initial value should be written to this bit.

10.18.5 Port Function Control Register 4 (PFCR4)

PFCR4 switches the functions of the WAIT input pin, BREQ input pin, BACK output pin, BREQO output pin, TxD4 output pin, RxD4 input pin, and SCK4 input/output pin. Bit Bit Name Initial Value R/W Description

7 WAITS 0 R/W WAIT Pin Select

Selects the WAIT input pin. 0: PF0/WAIT-A is selected 1: P25/WAIT-B is selected

6 BREQS 0 R/W BREQ Pin Select

Selects the BREQ input pin. 0: PG6/BREQ-A is selected 1: P51/BREQ-B is selected

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5 BACKS 0 R/W BACK Pin Select

Selects the BACK output pin. 0: PG5/BACK-A is selected 1: P52/BACK-B is selected

4 BREQOS 0 R/W BREQO Pin Select

Selects the BREQO output pin. 0: PG4/BREQO-A is selected 1: P50/BREQO-B is selected 3  0  Reserved This bit is always read as 0. Only the initial value should be written to this bit.

2 TXD4S 0 R/W TxD4 Pin Select

Selects the TxD4 output pin. 0: P23/TxD4-A is selected 1: PA1/TxD4-B is selected

1 RXD4S 0 R/W RxD4 Pin Select

Selects the RxD4 input pin. 0: P24/RxD4-A is selected 1: PA2/RxD4-B is selected

0 SCK4S 0 R/W SCK4 Pin Select

Selects the SCK4 input/output pin. 0: P34/SCK4-A is selected 1: PA3/SCK4-B is selected

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10.18.6 Port Function Control Register 5 (PFCR5)

PFCR5 switches the functions of the SSU input/output pins. Bit Bit Name Initial Value R/W Description SSO0S1 SSO0S0 R/W R/W SSO0 Pin Select Selects the SSO0 input/output pin. 00: P14/SSO0-A is selected 01: PA7/SSO0-B is selected 10: PF3/SSO0-C is selected 11: Setting prohibited SSI0S1 SSI0S0 R/W R/W SSI0 Pin Select Selects the SSI0 input/output pin. 00: P15/SSI0-A is selected 01: PA6/SSI0-B is selected 10: PF2/SSI0-C is selected 11: Setting prohibited SSCK0S1 SSCK0S0 R/W R/W SSCK0 Pin Select Selects the SSCK0 input/output pin. 00: P16/SSCK0-A is selected 01: PA5/SSCK0-B is selected 10: PF1/SSCK0-C is selected 11: Setting prohibited SCS0S1 SCS0S0 R/W R/W SCS0 Pin Select Selects the SCS0 input/output pin. 00: P17/SCS0-A is selected 01: PA4/SCS0-B is selected 10: PF0/SCS0-C is selected 11: Setting prohibited

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Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 673 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) This LSI has two on-chip 16-bit timer pulse units (TPU: unit 0 and unit 1) which each comprises six 16-bit timer channels, resulting in a total of 12 channels. The functions of unit 0 are listed in table 11.1, and the functions of unit 1 are listed in table 11.2. The block diagram of unit 0 is shown in figure 11.1 and the block diagram of unit 1 is shown in figure 11.2. The descriptions in this section refer to unit 0.

11.1 Features

  • Maximum 16-pulse input/output
  • Selection of 8 counter input clocks for each channel
  • The following operations can be set for each channel:  Waveform output at compare match  Input capture function  Counter clear operation  Synchronous operations: Multiple timer counters (TCNT) can be written to simultaneously Simultaneous clearing by compare match and input capture possible Register simultaneous input/output possible by counter synchronous operation  Maximum of 15-phase PWM output possible by combination with synchronous operation
  • Buffer operation settable for channels 0 and 3
  • Phase counting mode settable independently for each of channels 1, 2, 4, and 5
  • Cascaded operation
  • Fast access via internal 16-bit bus
  • 26 interrupt sources
  • Automatic transfer of register data
  • Programmable pulse generator (PPG) output trigger can be generated
  • A/D converter conversion start trigger can be generated
  • Module stop mode can be set

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 674 of 1270 REJ09B0466-0100 Table 11.1 TPU (U nit 0) Functions Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Count clock φ/1 φ/4 φ/16 φ/64 TCLKA TCLKB TCLKC TCLKD φ/1 φ/4 φ/16 φ/64 φ/256 TCLKA TCLKB φ/1 φ/4 φ/16 φ/64 φ/1024 TCLKA TCLKB TCLKC φ/1 φ/4 φ/16 φ/64 φ/256 φ/1024 φ/4096 TCLKA φ/1 φ/4 φ/16 φ/64 φ/1024 TCLKA TCLKC φ/1 φ/4 φ/16 φ/64 φ/256 TCLKA TCLKC TCLKD General registers (TGR) TGRA_0 TGRB_0 TGRA_1 TGRB_1 TGRA_2 TGRB_2 TGRA_3 TGRB_3 TGRA_4 TGRB_4 TGRA_5 TGRB_5 General registers/ buffer registers TGRC_0 TGRD_0   TGRC_3 TGRD_3   I/O pins TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5 Counter clear function TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture 0 output 1 output Compare match output Toggle output Input capture function Synchronous operation PWM mode Phase counting mode Buffer operation    

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 675 of 1270 REJ09B0466-0100 Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 DTC activation TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture DMAC activation TGRA_0 compare match or input capture TGRA_1 compare match or input capture TGRA_2 compare match or input capture TGRA_3 compare match or input capture TGRA_4 compare match or input capture TGRA_5 compare match or input capture A/D converter trigger TGRA_0 compare match or input capture TGRA_1 compare match or input capture TGRA_2 compare match or input capture TGRA_3 compare match or input capture TGRA_4 compare match or input capture TGRA_5 compare match or input capture PPG trigger TGRA_0/ TGRB_0 compare match or input capture TGRA_1/ TGRB_1 compare match or input capture TGRA_2/ TGRB_2 compare match or input capture TGRA_3/ TGRB_3 compare match or input capture   Interrupt sources 5 sources

  • Compare match or input capture
  • Compare match or input capture
  • Compare match or input capture
  • Compare match or input capture
  • Overflow 4 sources
  • Compare match or input capture
  • Compare match or input capture
  • Overflow
  • Underflow 4 sources
  • Compare match or input capture
  • Compare match or input capture
  • Overflow
  • Underflow 5 sources
  • Compare match or input capture
  • Compare match or input capture
  • Compare match or input capture
  • Compare match or input capture
  • Overflow 4 sources
  • Compare match or input capture
  • Compare match or input capture
  • Overflow
  • Underflow 4 sources
  • Compare match or input capture
  • Compare match or input capture
  • Overflow
  • Underflow [Legend] : Possible
  • : Not possible

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 676 of 1270 REJ09B0466-0100 Table 11.2 TPU (U nit 1) Functions Item Channel 6 Channel 7 Channel 8 Channel 9 Channel Channel Count clock φ/1 φ/4 φ/16 φ/64 TCLKE TCLKF TCLKG TCLKH φ/1 φ/4 φ/16 φ/64 φ/256 TCLKE TCLKF φ/1 φ/4 φ/16 φ/64 φ/1024 TCLKE TCLKF TCLKG φ/1 φ/4 φ/16 φ/64 φ/256 φ/1024 φ/4096 TCLKE φ/1 φ/4 φ/16 φ/64 φ/1024 TCLKE TCLKG φ/1 φ/4 φ/16 φ/64 φ/256 TCLKE TCLKG TCLKH General registers (TGR) TGRA_6 TGRB_6 TGRA_7 TGRB_7 TGRA_8 TGRB_8 TGRA_9 TGRB_9 TGRA_10 TGRB_10 TGRA_11 TGRB_11 General registers/ buffer registers TGRC_6 TGRD_6   TGRC_9 TGRD_9   I/O pins TIOCA6 TIOCB6 TIOCC6 TIOCD6 TIOCA7 TIOCB7 TIOCA8 TIOCB8 TIOCA9 TIOCB9 TIOCC9 TIOCD9 TIOCA10 TIOCB10 TIOCA11 TIOCB11 Counter clear function TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture 0 output 1 output Compare match output Toggle output Input capture function Synchronous operation PWM mode Phase counting mode Buffer operation    

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 677 of 1270 REJ09B0466-0100 Item Channel 6 Channel 7 Channel 8 Channel 9 Channel 10 Channel 11 DTC activation TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture DMAC activation A/D converter trigger TGRA_6 compare match or input capture TGRA_7 compare match or input capture TGRA_8 compare match or input capture TGRA_9 compare match or input capture TGRA_10 compare match or input capture TGRA_11 compare match or input capture PPG trigger TGRA_6/ TGRB_6 compare match or input capture TGRA_7/ TGRB_7 compare match or input capture TGRA_8/ TGRB_8 compare match or input capture TGRA_9/ TGRB_9 compare match or input capture   Interrupt sources 5 sources

  • Compare match or input capture
  • Compare match or input capture
  • Compare match or input capture
  • Compare match or input capture
  • Overflow 4 sources
  • Compare match or input capture
  • Compare match or input capture
  • Overflow
  • Underflow 4 sources
  • Compare match or input capture
  • Compare match or input capture
  • Overflow
  • Underflow 5 sources
  • Compare match or input capture
  • Compare match or input capture
  • Compare match or input capture
  • Compare match or input capture
  • Overflow 4 sources
  • Compare match or input capture 10A
  • Compare match or input capture 10B
  • Overflow
  • Underflow 4 sources
  • Compare match or input capture 11A
  • Compare match or input capture 11B
  • Overflow
  • Underflow [Legend] : Possible : Not possible

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 678 of 1270 REJ09B0466-0100 Channel 3 TMDR TIORL TSR TCR TIORH TIER TGRA TCNT TGRB TGRC TGRD Channel 4 TMDR TSR TCR TIOR TIER TGRA TCNT TGRB Control logic TMDR TSR TCR TIOR TIER TGRA TCNT TGRB Control logic for channels 3 to 5 TMDR TSR TCR TIOR TIER TGRA TCNT TGRB TGRC Channel 1 TMDR TSR TCR TIOR TIER TGRA TCNT TGRB Channel 0 TMDR TSR TCR TIORH TIER Control logic for channels 0 to 2 TGRA TCNT TGRB TGRD TSYRTSTR Input/output pins TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5 Clock input φ/1 φ/4 φ/16 φ/64 φ/256 φ/1024 φ/4096 TCLKA TCLKB TCLKC TCLKD Input/output pins TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 Interrupt request signals Channel 3: Channel 4: Channel 5: Interrupt request signals Channel 0: Channel 1: Channel 2: Internal data bus A/D conversion start request signal PPG output trigger signal TIORL Module data bus TGI3A TGI3B TGI3C TGI3D TCI3V TGI4A TGI4B TCI4V TCI4U TGI5A TGI5B TCI5V TCI5U TGI0A TGI0B TGI0C TGI0D TCI0V TGI1A TGI1B TCI1V TCI1U TGI2A TGI2B TCI2V TCI2U Channel 3: Channel 4: Channel 5: Internal clock: External clock: Channel 0: Channel 1: Channel 2: Legend: TSTR: Timer start register TSYR: Timer synchronous register TCR: Timer control register TMDR: Timer mode register TIOR (H, L): Timer I/O control registers (H, L) TIER: Timer interrupt enable register TSR: Timer status register TGR (A, B, C, D): Timer general registers (A, B, C, D) TCNT: Timer counter Channel 2 Common Channel 5 Bus interface Figure 11.1 Block Diagram of TPU (Unit 0)

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 679 of 1270 REJ09B0466-0100 Channel 9 TMDR TIORL TSR TCR TIORH TIER TGRA TCNT TGRB TGRC TGRD Channel 10 TMDR TSR TCR TIOR TIER TGRA TCNT TGRB Control logic TMDR TSR TCR TIOR TIER TGRA TCNT TGRB Control logic for channels 9 to 11 TMDR TSR TCR TIOR TIER TGRA TCNT TGRB TGRC Channel 7 TMDR TSR TCR TIOR TIER TGRA TCNT TGRB Channel 8 TMDR TSR TCR TIORH TIER Control logic for channels 6 to 8 TGRA TCNT TGRB TGRD TSYRTSTR Input/output pins TIOCA9 TIOCB9 TIOCC9 TIOCD9 TIOCA10 TIOCB10 TIOCA11 TIOCB11 Clock input φ/1 φ/4 φ/16 φ/64 φ/256 φ/1024 φ/4096 TCLKE TCLKF TCLKG TCLKH Input/output pins TIOCA6 TIOCB6 TIOCC6 TIOCD6 TIOCA7 TIOCB7 TIOCA8 TIOCB8 Interrupt request signals Channel 9: Channel 10: Channel 11: Interrupt request signals Channel 6: Channel 7: Channel 8: Internal data bus A/D conversion start request signal PPG output trigger signal TIORL Module data bus TGI9A TGI9B TGI9C TGI9D TCI9V TGI10A TGI10B TCI10V TCI10U TGI11A TGI11B TCI11V TCI11U TGI6A TGI6B TGI6C TGI6D TCI6V TGI7A TGI7B TCI7V TCI7U TGI8A TGI8B TCI8V TCI8U Channel 9: Channel 10: Channel 11: Internal clock: External clock: Channel 6: Channel 7: Channel 8: Legend: TSTR: Timer start register TSYR: Timer synchronous register TCR: Timer control register TMDR: Timer mode register TIOR (H, L): Timer I/O control registers (H, L) TIER: Timer interrupt enable register TSR: Timer status register TGR (A, B, C, D): Timer general registers (A, B, C, D) TCNT: Timer counter Channel 6 Common Channel 11 Bus interface Figure 11.2 Block Diagram of TPU (Unit 1)

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 680 of 1270 REJ09B0466-0100

11.2 Input/Output Pins

Table 11.3 Pin Configuration Unit Channel Symbol I/O Function

0 All TCLKA Input External clock A input pin

(Channel 1 and 5 phase counting mode A phase input) TCLKB Input External clock B input pin (Channel 1 and 5 phase counting mode B phase input) TCLKC Input External clock C input pin (Channel 2 and 4 phase counting mode A phase input) TCLKD Input External clock D input pin (Channel 2 and 4 phase counting mode B phase input)

0 TIOCA0 I/O TGRA_0 input captur e input/output compare output/PWM

TIOCB0 I/O TGRB_0 input captur e input/output compare output/PWM output pin TIOCC0 I/O TGRC_0 input captur e input/output compare output/PWM output pin TIOCD0 I/O TGRD_0 input captur e input/output compare output/PWM output pin

1 TIOCA1 I/O TGRA_1 input captur e input/output compare output/PWM

TIOCB1 I/O TGRB_1 input captur e input/output compare output/PWM output pin

2 TIOCA2 I/O TGRA_2 input captur e input/output compare output/PWM

TIOCB2 I/O TGRB_2 input captur e input/output compare output/PWM output pin

3 TIOCA3 I/O TGRA_3 input captur e input/output compare output/PWM

TIOCB3 I/O TGRB_3 input captur e input/output compare output/PWM output pin TIOCC3 I/O TGRC_3 input captur e input/output compare output/PWM output pin TIOCD3 I/O TGRD_3 input captur e input/output compare output/PWM output pin

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 681 of 1270 REJ09B0466-0100 Unit Channel Symbol I/O Function 0 4 TIOCA4 I/O TGRA_4 input captur e input/output compare output/PWM output pin TIOCB4 I/O TGRB_4 input captur e input/output compare output/PWM output pin

5 TIOCA5 I/O TGRA_5 input captur e input/output compare output/PWM

TIOCB5 I/O TGRB_5 input captur e input/output compare output/PWM output pin

1 All TCLKE Input External clock E input pin

(Channel 7 and 11 phase counting mode A phase input) TCLKF Input External clock F input pin (Channel 7 and 11 phase counting mode B phase input) TCLKG Input External clock G input pin (Channel 8 and 10 phase counting mode A phase input) TCLKH Input External clock H input pin (Channel 8 and 10 phase counting mode B phase input)

6 TIOCA6 I/O TGRA_6 input captur e input/output compare output/PWM

TIOCB6 I/O TGRB_6 input captur e input/output compare output/PWM output pin TIOCC6 I/O TGRC_6 input captur e input/output compare output/PWM output pin TIOCD6 I/O TGRD_6 input captur e input/output compare output/PWM output pin

7 TIOCA7 I/O TGRA_7 input captur e input/output compare output/PWM

TIOCB7 I/O TGRB_7 input captur e input/output compare output/PWM output pin

8 TIOCA8 I/O TGRA_8 input captur e input/output compare output/PWM

TIOCB8 I/O TGRB_8 input captur e input/output compare output/PWM output pin

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 682 of 1270 REJ09B0466-0100 Unit Channel Symbol I/O Function 1 9 TIOCA9 I/O TGRA_9 input captur e input/output compare output/PWM output pin TIOCB9 I/O TGRB_9 input captur e input/output compare output/PWM output pin TIOCC9 I/O TGRC_9 input captur e input/output compare output/PWM output pin TIOCD9 I/O TGRD_9 input captur e input/output compare output/PWM output pin

10 TIOCA10 I/O TGRA_10 input c apture input/output compare

TIOCB10 I/O TGRB_10 input c apture input/output compare output/PWM output pin

11 TIOCA11 I/O TGRA_11 input c apture input/output compare

TIOCB11 I/O TGRB_11 input c apture input/output compare output/PWM output pin

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 683 of 1270 REJ09B0466-0100

11.3 Register Descriptions

The TPU has the following registers in each channel. The descriptions in this section refer to the registers of unit 0. Unit 0: Channel 0

  • Timer control register_0 (TCR_0)
  • Timer mode register_0 (TMDR_0)
  • Timer I/O control register H_0 (TIORH_0)
  • Timer I/O control register L_0 (TIORL_0)
  • Timer interrupt enable register_0 (TIER_0)
  • Timer status register_0 (TSR_0)
  • Timer counter_0 (TCNT_0)
  • Timer general register A_0 (TGRA_0)
  • Timer general register B_0 (TGRB_0)
  • Timer general register C_0 (TGRC_0)
  • Timer general register D_0 (TGRD_0) Channel 1
  • Timer control register_1 (TCR_1)
  • Timer mode register_1 (TMDR_1)
  • Timer I/O control register_1 (TIOR_1)
  • Timer interrupt enable register_1 (TIER_1)
  • Timer status register_1 (TSR_1)
  • Timer counter_1 (TCNT_1)
  • Timer general register A_1 (TGRA_1)
  • Timer general register B_1 (TGRB_1)

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 684 of 1270 REJ09B0466-0100 Channel 2

  • Timer control register_2 (TCR_2)
  • Timer mode register_2 (TMDR_2)
  • Timer I/O control register_2 (TIOR_2)
  • Timer interrupt enable register_2 (TIER_2)
  • Timer status register_2 (TSR_2)
  • Timer counter_2 (TCNT_2)
  • Timer general register A_2 (TGRA_2)
  • Timer general register B_2 (TGRB_2) Channel 3
  • Timer control register_3 (TCR_3)
  • Timer mode register_3 (TMDR_3)
  • Timer I/O control register H_3 (TIORH_3)
  • Timer I/O control register L_3 (TIORL_3)
  • Timer interrupt enable register_3 (TIER_3)
  • Timer status register_3 (TSR_3)
  • Timer counter_3 (TCNT_3)
  • Timer general register A_3 (TGRA_3)
  • Timer general register B_3 (TGRB_3)
  • Timer general register C_3 (TGRC_3)
  • Timer general register D_3 (TGRD_3) Channel 4
  • Timer control register_4 (TCR_4)
  • Timer mode register_4 (TMDR_4)
  • Timer I/O control register_4 (TIOR_4)
  • Timer interrupt enable register_4 (TIER_4)
  • Timer status register_4 (TSR_4)
  • Timer counter_4 (TCNT_4)
  • Timer general register A_4 (TGRA_4)
  • Timer general register B_4 (TGRB_4)

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 685 of 1270 REJ09B0466-0100 Channel 5

  • Timer control register_5 (TCR_5)
  • Timer mode register_5 (TMDR_5)
  • Timer I/O control register_5 (TIOR_5)
  • Timer interrupt enable register_5 (TIER_5)
  • Timer status register_5 (TSR_5)
  • Timer counter_5 (TCNT_5)
  • Timer general register A_5 (TGRA_5)
  • Timer general register B_5 (TGRB_5) Common Registers of Unit 0
  • Timer start register (TSTR)
  • Timer synchronous register (TSYR) Unit 1: Channel 6
  • Timer control register_6 (TCR_6)
  • Timer mode register_6 (TMDR_6)
  • Timer I/O control register H_6 (TIORH_6)
  • Timer I/O control register L_6 (TIORL_6)
  • Timer interrupt enable register_6 (TIER_6)
  • Timer status register_6 (TSR_6)
  • Timer counter_6 (TCNT_6)
  • Timer general register A_6 (TGRA_6)
  • Timer general register B_6 (TGRB_6)
  • Timer general register C_6 (TGRC_6)
  • Timer general register D_6 (TGRD_6)

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 686 of 1270 REJ09B0466-0100 Channel 7

  • Timer control register_7 (TCR_7)
  • Timer mode register_7 (TMDR_7)
  • Timer I/O control register_7 (TIOR_7)
  • Timer interrupt enable register_7 (TIER_7)
  • Timer status register_7 (TSR_7)
  • Timer counter_7 (TCNT_7)
  • Timer general register A_7 (TGRA_7)
  • Timer general register B_7 (TGRB_7) Channel 8
  • Timer control register_8 (TCR_8)
  • Timer mode register_8 (TMDR_8)
  • Timer I/O control register_8 (TIOR_8)
  • Timer interrupt enable register_8 (TIER_8)
  • Timer status register_8 (TSR_8)
  • Timer counter_8 (TCNT_8)
  • Timer general register A_8 (TGRA_8)
  • Timer general register B_8 (TGRB_8) Channel 9
  • Timer control register_9 (TCR_9)
  • Timer mode register_9 (TMDR_9)
  • Timer I/O control register H_9 (TIORH_9)
  • Timer I/O control register L_9 (TIORL_9)
  • Timer interrupt enable register_9 (TIER_9)
  • Timer status register_9 (TSR_9)
  • Timer counter_9 (TCNT_9)
  • Timer general register A_9 (TGRA_9)
  • Timer general register B_9 (TGRB_9)
  • Timer general register C_9 (TGRC_9)
  • Timer general register D_9 (TGRD_9)

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 687 of 1270 REJ09B0466-0100 Channel 10

  • Timer control register_10 (TCR_10)
  • Timer mode register_10 (TMDR_10)
  • Timer I/O control register_10 (TIOR_10)
  • Timer interrupt enable register_10 (TIER_10)
  • Timer status register_10 (TSR_10)
  • Timer counter_10 (TCNT_10)
  • Timer general register A_10 (TGRA_10)
  • Timer general register B_10 (TGRB_10) Channel 11
  • Timer control register_11 (TCR_11)
  • Timer mode register_11 (TMDR_11)
  • Timer I/O control register_11 (TIOR_11)
  • Timer interrupt enable register_11 (TIER_11)
  • Timer status register_11 (TSR_11)
  • Timer counter_11 (TCNT_11)
  • Timer general register A_11 (TGRA_11)
  • Timer general register B_11 (TGRB_11) Common Registers of Unit 1
  • Timer start register B (TSTRB)
  • Timer synchronous register B (TSYRB)

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 688 of 1270 REJ09B0466-0100

11.3.1 Timer Control Register (TCR)

The TCR registers control the TCNT operation for each channel. The TPU has a total of six TCR registers, one for each channel. TCR register settings should be made only when TCNT operation is stopped. Bit Bit Name Initial Value R/W Description CCLR2 CCLR1 CCLR0 R/W R/W R/W Counter Clear 2 to 0 These bits select the TCNT counter clearing source. See tables 11.4 and 11.5 for details. CKEG1 CKEG0 R/W R/W Clock Edge 1 and 0 These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. φ/4 both edges = φ/2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority. Internal clock edge selection is valid when the input clock is φ/4 or slower. This setting is ignored if the input clock is φ/1, or when overflow/underflow of another channel is selected. 00: Count at rising edge 01: Count at falling edge 1×: Count at both edges TPSC2 TPSC1 TPSC0 R/W R/W R/W Time Prescaler 2 to 0 These bits select the TCNT counter clock. The clock source can be selected independently for each channel. See tables 11.6 to 11.11 for details. [Legend] ×: Don’t care

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 689 of 1270 REJ09B0466-0100 Table 11.4 CCLR2 to CCLR0 (Channels 0 and 3) Channel Bit 7 CCLR2 Bit 6 CCLR1 Bit 5 CCLR0 Description 0, 3 0 0 0 TCNT clearing disabled

1 TCNT cleared by TGRA compare match/input

1 0 TCNT cleared by TGRB compare match/input capture

1 TCNT cleared by counter clearing for another

channel performing synchronous clearing/ synchronous operation* 1 0 0 TCNT clearing disabled

1 TCNT cleared by TGRC compare match/input

capture* 1 0 TCNT cleared by TGRD compare match/input capture* channel performing synchronous clearing/ synchronous operation* Notes: 1. Synchronous operation setting is per formed by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer re gister, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. Table 11.5 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5) Channel Bit 7 Reserved* Bit 6 CCLR1 Bit 5 CCLR0 Description 1, 2, 4, 5 0 0 0 TCNT clearing disabled 1 0 TCNT cleared by TGRB compare match/input capture channel performing synchronous clearing/ synchronous operation* Notes: 1. Synchronous operation setting is per formed by setting the SYNC bit in TSYR to 1. 2. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be modified.

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 690 of 1270 REJ09B0466-0100 Table 11.6 TPSC2 to TPSC0 (Channel 0) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 0 0 0 0 Internal clock: counts on φ/1

1 Internal clock: counts on φ/4

1 0 Internal clock: counts on φ/16

1 Internal clock: counts on φ/64

1 0 0 External clock: counts on TCLKA pin input

1 External clock: counts on TCLKB pin input

1 0 External clock: counts on TCLKC pin input

1 External clock: counts on TCLKD pin input

Table 11.7 TPSC2 to TPSC0 (Channel 1) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 1 0 0 0 Internal clock: counts on φ/1 1 0 Internal clock: counts on φ/16 1 0 0 External clock: counts on TCLKA pin input 1 0 Internal clock: counts on φ/256

1 Counts on TCNT2 overflow/underflow

Note: This setting is ignored when channel 1 is in phase counting mode.

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 691 of 1270 REJ09B0466-0100 Table 11.8 TPSC2 to TPSC0 (Channel 2) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 2 0 0 0 Internal clock: counts on φ/1 1 0 Internal clock: counts on φ/16 1 0 0 External clock: counts on TCLKA pin input 1 0 External clock: counts on TCLKC pin input

1 Internal clock: counts on φ/1024

Note: This setting is ignored when channel 2 is in phase counting mode. Table 11.9 TPSC2 to TPSC0 (Channel 3) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 3 0 0 0 Internal clock: counts on φ/1 1 0 Internal clock: counts on φ/16 1 0 0 External clock: counts on TCLKA pin input 1 0 Internal clock: counts on φ/256

1 Internal clock: counts on φ/4096

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 692 of 1270 REJ09B0466-0100 Table 11.10 TPSC2 to TPSC0 (Channel 4) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 4 0 0 0 Internal clock: counts on φ/1 1 0 Internal clock: counts on φ/16 1 0 0 External clock: counts on TCLKA pin input

1 External clock: counts on TCLKC pin input

1 0 Internal clock: counts on φ/1024

1 Counts on TCNT5 overflow/underflow

Note: This setting is ignored when channel 4 is in phase counting mode. Table 11.11 TPSC2 to TPSC0 (Channel 5) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 5 0 0 0 Internal clock: counts on φ/1 1 0 Internal clock: counts on φ/16 1 0 0 External clock: counts on TCLKA pin input 1 0 Internal clock: counts on φ/256 Note: This setting is ignored when channel 5 is in phase counting mode.

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 693 of 1270 REJ09B0466-0100

11.3.2 Timer Mode Register (TMDR)

TMDR registers are used to set the operating mode for each channel. The TPU has six TMDR registers, one for each channel. TMDR register settings should be made only when TCNT operation is stopped. Bit Bit Name Initial Value R/W Description Reserved These bits are always read as 1 and cannot be modified.

5 BFB 0 R/W Buffer Operation B

Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: TGRB operates normally 1: TGRB and TGRD used together for buffer operation

4 BFA 0 R/W Buffer Operation A

Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified. 0: TGRA operates normally 1: TGRA and TGRC used together for buffer operation MD3 MD2 MD1 MD0 R/W R/W R/W R/W Modes 3 to 0 These bits are used to set the timer operating mode. MD3 is a reserved bit. The write value should always be 0. See table 11.12 for details.

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 694 of 1270 REJ09B0466-0100 Table 11.12 MD3 to MD0 Bit 3 MD3 * Bit 2 MD2 * Bit 1 MD1 Bit 0 MD0 Description 0 0 0 0 Normal operation

1 Reserved

1 PWM mode 2

1 0 0 Phase counting mode 1

1 Phase counting mode 2

1 Phase counting mode 4

1 × × ×  [Legend] ×: Don’t care Notes: 1. MD3 is a reserved bit. In a wr ite, it should always be written with 0. 2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2.

11.3.3 Timer I/O Cont rol Register (TIOR)

TIOR registers control the TGR registers. The TPU has eight TIOR registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5. Care is required since TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register.

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 695 of 1270 REJ09B0466-0100 TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5 Bit Bit Name Initial Value R/W Description IOB3 IOB2 IOB1 IOB0 R/W R/W R/W R/W I/O Control B3 to B0 Specify the function of TGRB. For details, see tables 11.13, 11.15, 11.16, 11.17, 11.19, and 11.20. IOA3 IOA2 IOA1 IOA0 R/W R/W R/W R/W I/O Control A3 to A0 Specify the function of TGRA. For details, see tables 11.21, 11.23, 11.24, 11.25, 11.27, and 11.28. TIORL_0, TIORL_3 Bit Bit Name Initial Value R/W Description IOD3 IOD2 IOD1 IOD0 R/W R/W R/W R/W I/O Control D3 to D0 Specify the function of TGRD. For details, see tables 11.14 and 11.18. IOC3 IOC2 IOC1 IOC0 R/W R/W R/W R/W I/O Control C3 to C0 Specify the function of TGRC. For details, see tables 11.22 and 11.26.

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 696 of 1270 REJ09B0466-0100 Table 11.13 TIORH_0 TGRB_0 Function TIOCB0 Pin Function 0 0 0 0 Output disabled

1 Initial output is 0 output

Initial output is 0 output 1 output at compare match Toggle output at compare match 1 0 0 Output disabled

1 Initial output is 1 output

1 0 Initial output is 1 output 1 output at compare match Toggle output at compare match 1 0 0 0 Capture input source is TIOCB0 pin Input capture at rising edge

1 Capture input source is TIOCB0 pin

Input capture at falling edge 1 × Input capture register Capture input source is TIOCB0 pin Input capture at both edges 1 × × Capture input source is channel 1/count clock Input capture at TCNT_1 count- up/count-down* [Legend] ×: Don’t care Note: * When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and φ/1 is used as the TCNT_1 count clock, this setting is invalid and input capture is not generated.

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 697 of 1270 REJ09B0466-0100 Table 11.14 TIORL_0 TGRD_0 Function TIOCD0 Pin Function 0 0 0 0 Output disabled Output compare register* Initial output is 0 output 0 output at compare match 1 0 Initial output is 0 output 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 1 0 Initial output is 1 output 1 output at compare match Toggle output at compare match 1 0 0 0 Capture input source is TIOCD0 pin Input capture at rising edge

1 Capture input source is TIOCD0 pin

Input capture at falling edge 1 × Input capture register* Capture input source is TIOCD0 pin Input capture at both edges 1 × × Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down* [Legend] ×: Don’t care Notes: 1. When bits TPSC2 to T PSC0 in TCR_1 are set to B'000 and φ/1 is used as the TCNT_1 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 698 of 1270 REJ09B0466-0100 Table 11.15 TIOR_1 TGRB_1 Function TIOCB1 Pin Function 0 0 0 0 Output disabled Output compare register Initial output is 0 output 0 output at compare match 1 0 Initial output is 0 output 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 1 0 Initial output is 1 output 1 output at compare match Toggle output at compare match 1 0 0 0 Capture input source is TIOCB1 pin Input capture at rising edge

1 Capture input source is TIOCB1 pin

Input capture at falling edge 1 × Input capture register Capture input source is TIOCB1 pin Input capture at both edges 1 × × TGRC_0 compare match/input capture Input capture at generation of TGRC_0 compare match/input capture [Legend] ×: Don’t care

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 699 of 1270 REJ09B0466-0100 Table 11.16 TIOR_2 TGRB_2 Function TIOCB2 Pin Function 0 0 0 0 Output disabled Output compare register Initial output is 0 output 0 output at compare match 1 0 Initial output is 0 output 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 1 0 Initial output is 1 output 1 output at compare match Toggle output at compare match 1 × 0 0 Capture input source is TIOCB2 pin Input capture at rising edge

1 Capture input source is TIOCB2 pin

Input capture at falling edge 1 × Input capture register Capture input source is TIOCB2 pin Input capture at both edges [Legend] ×: Don’t care

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 700 of 1270 REJ09B0466-0100 Table 11.17 TIORH_3 TGRB_3 Function TIOCB3 Pin Function 0 0 0 0 Output disabled Output compare register Initial output is 0 output 0 output at compare match 1 0 Initial output is 0 output 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 1 0 Initial output is 1 output 1 output at compare match Toggle output at compare match 1 0 0 0 Capture input source is TIOCB3 pin Input capture at rising edge

1 Capture input source is TIOCB3 pin

Input capture at falling edge 1 × Input capture register Capture input source is TIOCB3 pin Input capture at both edges 1 × × Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down* [Legend] ×: Don’t care Note: * When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and φ/1 is used as the TCNT_4 count clock, this setting is invalid and input capture is not generated.

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 701 of 1270 REJ09B0466-0100 Table 11.18 TIORL_3 TGRD_3 Function TIOCD3 Pin Function 0 0 0 0 Output disabled Output compare register* Initial output is 0 output 0 output at compare match 1 0 Initial output is 0 output 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 1 0 Initial output is 1 output 1 output at compare match Toggle output at compare match 1 0 0 0 Capture input source is TIOCD3 pin Input capture at rising edge

1 Capture input source is TIOCD3 pin

Input capture at falling edge 1 × Input capture register* Capture input source is TIOCD3 pin Input capture at both edges 1 × × Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down* [Legend] ×: Don’t care Notes: 1. When bits TPSC2 to T PSC0 in TCR_4 are set to B'000 and φ/1 is used as the TCNT_4 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 702 of 1270 REJ09B0466-0100 Table 11.19 TIOR_4 TGRB_4 Function TIOCB4 Pin Function 0 0 0 0 Output disabled Output compare register Initial output is 0 output 0 output at compare match 1 0 Initial output is 0 output 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 1 0 Initial output is 1 output 1 output at compare match Toggle output at compare match 1 0 0 0 Capture input source is TIOCB4 pin Input capture at rising edge

1 Capture input source is TIOCB4 pin

Input capture at falling edge 1 × Input capture register Capture input source is TIOCB4 pin Input capture at both edges 1 × × Capture input source is TGRC_3 compare match/input capture Input capture at generation of TGRC_3 compare match/input capture [Legend] ×: Don’t care

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 703 of 1270 REJ09B0466-0100 Table 11.20 TIOR_5 TGRB_5 Function TIOCB5 Pin Function 0 0 0 0 Output disabled Output compare register Initial output is 0 output 0 output at compare match 1 0 Initial output is 0 output 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 1 0 Initial output is 1 output 1 output at compare match Toggle output at compare match 1 × 0 0 Capture input source is TIOCB5 pin Input capture at rising edge

1 Capture input source is TIOCB5 pin

Input capture at falling edge 1 × Input capture register Capture input source is TIOCB5 pin Input capture at both edges [Legend] ×: Don’t care

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 704 of 1270 REJ09B0466-0100 Table 11.21 TIORH_0 TGRA_0 Function TIOCA0 Pin Function 0 0 0 0 Output disabled Output compare register Initial output is 0 output 0 output at compare match 1 0 Initial output is 0 output 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 1 0 Initial output is 1 output 1 output at compare match Toggle output at compare match 1 0 0 0 Capture input source is TIOCA0 pin Input capture at rising edge

1 Capture input source is TIOCA0 pin

Input capture at falling edge 1 × Input capture register Capture input source is TIOCA0 pin Input capture at both edges 1 × × Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] ×: Don’t care

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 705 of 1270 REJ09B0466-0100 Table 11.22 TIORL_0 TGRC_0 Function TIOCC0 Pin Function 0 0 0 0 Output disabled Output compare register* Initial output is 0 output 0 output at compare match 1 0 Initial output is 0 output 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 1 0 Initial output is 1 output 1 output at compare match Toggle output at compare match 1 0 0 0 Capture input source is TIOCC0 pin Input capture at rising edge

1 Capture input source is TIOCC0 pin

Input capture at falling edge 1 × Input capture register* Capture input source is TIOCC0 pin Input capture at both edges 1 × × Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] ×: Don’t care Note: * When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 706 of 1270 REJ09B0466-0100 Table 11.23 TIOR_1 TGRA_1 Function TIOCA1 Pin Function 0 0 0 0 Output disabled Output compare register Initial output is 0 output 0 output at compare match 1 0 Initial output is 0 output 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 1 0 Initial output is 1 output 1 output at compare match Toggle output at compare match 1 0 0 0 Capture input source is TIOCA1 pin Input capture at rising edge

1 Capture input source is TIOCA1 pin

Input capture at falling edge 1 × Input capture register Capture input source is TIOCA1 pin Input capture at both edges 1 × × Capture input source is TGRA_0 compare match/input capture Input capture at generation of channel 0/TGRA_0 compare match/input capture [Legend] ×: Don’t care

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 707 of 1270 REJ09B0466-0100 Table 11.24 TIOR_2 TGRA_2 Function TIOCA2 Pin Function 0 0 0 0 Output disabled Output compare register Initial output is 0 output 0 output at compare match 1 0 Initial output is 0 output 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 1 0 Initial output is 1 output 1 output at compare match Toggle output at compare match 1 × 0 0 Capture input source is TIOCA2 pin Input capture at rising edge

1 Capture input source is TIOCA2 pin

Input capture at falling edge 1 × Input capture register Capture input source is TIOCA2 pin Input capture at both edges [Legend] ×: Don’t care

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 708 of 1270 REJ09B0466-0100 Table 11.25 TIORH_3 TGRA_3 Function TIOCA3 Pin Function 0 0 0 0 Output disabled Output compare register Initial output is 0 output 0 output at compare match 1 0 Initial output is 0 output 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 1 0 Initial output is 1 output 1 output at compare match Toggle output at compare match 1 0 0 0 Capture input source is TIOCA3 pin Input capture at rising edge

1 Capture input source is TIOCA3 pin

Input capture at falling edge 1 × Input capture register Capture input source is TIOCA3 pin Input capture at both edges 1 × × Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down [Legend] ×: Don’t care

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 709 of 1270 REJ09B0466-0100 Table 11.26 TIORL_3 TGRC_3 Function TIOCC3 Pin Function 0 0 0 0 Output disabled Output compare register* Initial output is 0 output 0 output at compare match 1 0 Initial output is 0 output 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 1 0 Initial output is 1 output 1 output at compare match Toggle output at compare match 1 0 0 0 Capture input source is TIOCC3 pin Input capture at rising edge

1 Capture input source is TIOCC3 pin

Input capture at falling edge 1 × Input capture register* Capture input source is TIOCC3 pin Input capture at both edges 1 × × Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down [Legend] ×: Don’t care Note: * When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 710 of 1270 REJ09B0466-0100 Table 11.27 TIOR_4 TGRA_4 Function TIOCA4 Pin Function 0 0 0 0 Output disabled Output compare register Initial output is 0 output 0 output at compare match 1 0 Initial output is 0 output 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 1 0 Initial output is 1 output 1 output at compare match Toggle output at compare match 1 0 0 0 Capture input source is TIOCA4 pin Input capture at rising edge

1 Capture input source is TIOCA4 pin

Input capture at falling edge 1 × Input capture register Capture input source is TIOCA4 pin Input capture at both edges 1 × × Capture input source is TGRA_3 compare match/input capture Input capture at generation of TGRA_3 compare match/input capture [Legend] ×: Don’t care

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 711 of 1270 REJ09B0466-0100 Table 11.28 TIOR_5 TGRA_5 Function TIOCA5 Pin Function 0 0 0 0 Output disabled Output compare register Initial output is 0 output 0 output at compare match 1 0 Initial output is 0 output 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 1 0 Initial output is 1 output 1 output at compare match Toggle output at compare match 1 × 0 0 Input capture source is TIOCA5 pin Input capture at rising edge

1 Input capture source is TIOCA5 pin

Input capture at falling edge 1 × Input capture register Input capture source is TIOCA5 pin Input capture at both edges [Legend] ×: Don’t care

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 712 of 1270 REJ09B0466-0100

11.3.4 Timer Interrupt Enable Register (TIER)

TIER registers control enabling or disabling of interrupt requests for each channel. The TPU has six TIER registers, one for each channel. Bit Bit Name Initial value R/W Description

7 TTGE 0 R/W A/D Conversion Start Request Enable

Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match. 0: A/D conversion start request generation disabled 1: A/D conversion start request generation enabled 6 — 1 — Reserved This bit is always read as 1 and cannot be modified.

5 TCIEU 0 R/W Underflow Interrupt Enable

Enables or disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1, 2, 4, and 5. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TCIU) by TCFU disabled 1: Interrupt requests (TCIU) by TCFU enabled

4 TCIEV 0 R/W Overflow Interrupt Enable

Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. 0: Interrupt requests (TCIV) by TCFV disabled 1: Interrupt requests (TCIV) by TCFV enabled

3 TGIED 0 R/W TGR Interrupt Enable D

Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TGID) by TGFD bit disabled 1: Interrupt requests (TGID) by TGFD bit enabled

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 713 of 1270 REJ09B0466-0100 Bit Bit Name Initial value R/W Description

2 TGIEC 0 R/W TGR Interrupt Enable C

Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TGIC) by TGFC bit disabled 1: Interrupt requests (TGIC) by TGFC bit enabled

1 TGIEB 0 R/W TGR Interrupt Enable B

Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. 0: Interrupt requests (TGIB) by TGFB bit disabled 1: Interrupt requests (TGIB) by TGFB bit enabled

0 TGIEA 0 R/W TGR Interrupt Enable A

Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. 0: Interrupt requests (TGIA) by TGFA bit disabled 1: Interrupt requests (TGIA) by TGFA bit enabled

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 714 of 1270 REJ09B0466-0100

11.3.5 Timer Status Register (TSR)

TSR registers indicate the status of each channel. The TPU has six TSR registers, one for each channel. Bit Bit Name Initial value R/W Description

7 TCFD 1 R Count Direction Flag

Status flag that shows the direction in which TCNT counts in channels 1, 2, 4, and 5. In channels 0 and 3, bit 7 is reserved. It is always read as 1 and cannot be modified. 0: TCNT counts down 1: TCNT counts up 6 — 1 — Reserved This bit is always read as 1 and cannot be modified.

5 TCFU 0 R/(W) * Underflow Flag

Status flag that indicates that TCNT underflow has occurred when channels 1, 2, 4, and 5 are set to phase counting mode. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified. [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFU after reading TCFU = 1

4 TCFV 0 R/(W) * Overflow Flag

Status flag that indicates that TCNT overflow has occurred. [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 715 of 1270 REJ09B0466-0100 Bit Bit Name Initial value R/W Description

3 TGFD 0 R/(W) * Input Capture/Output Compare Flag D

Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified. [Setting conditions]

  • When TCNT = TGRD while TGRD is functioning as output compare register
  • When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register [Clearing conditions]
  • When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0
  • When 0 is written to TGFD after reading TGFD = 1

2 TGFC 0 R/(W) * Input Capture/Output Compare Flag C

Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0 and In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified. [Setting conditions]

  • When TCNT = TGRC while TGRC is functioning as output compare register
  • When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register [Clearing conditions]
  • When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0
  • When 0 is written to TGFC after reading TGFC = 1

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 716 of 1270 REJ09B0466-0100 Bit Bit Name Initial value R/W Description

1 TGFB 0 R/(W) * Input Capture/Output Compare Flag B

Status flag that indicates the occurrence of TGRB input capture or compare match. [Setting conditions]

  • When TCNT = TGRB while TGRB is functioning as output compare register
  • When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register [Clearing conditions]
  • When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0
  • When 0 is written to TGFB after reading TGFB = 1

0 TGFA 0 R/(W) * Input Capture/Output Compare Flag A

Status flag that indicates the occurrence of TGRA input capture or compare match. [Setting conditions] When TCNT = TGRA while TGRA is functioning as output compare register When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register [Clearing conditions]

  • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0
  • When DMAC is activated by TGIA interrupt while DTE bit of DMABCR in DTC is 0
  • When 0 is written to TGFA after reading TGFA = 1 Note: * Only 0 can be written, for flag clearing.

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 717 of 1270 REJ09B0466-0100

11.3.6 Timer Counter (TCNT)

The TCNT registers are 16-bit readable/writable counters. The TPU has six TCNT counters, one for each channel. The TCNT counters are initialized to H'0000 by a reset, or in hardware standby mode. The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit.

11.3.7 Timer General Register (TGR)

The TGR registers are 16-bit readable/writable registers with a dual function as output compare and input capture registers. The TPU has 16 TGR registers, four each for channels 0 and 3 and two each for channels 1, 2, 4, and 5. TGRC and TGRD for channels 0 and 3 can also be designated for operation as buffer registers. The TGR registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. TGR buffer register combinations are TGRA–TGRC and TGRB–TGRD.

11.3.8 Timer Start Register (TSTR)

TSTR selects operation/stoppage for channels 0 to 5. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. Bit Bit Name Initial value R/W Description Reserved The write value should always be 0. CST5 CST4 CST3 CST2 CST1 CST0 R/W R/W R/W R/W R/W R/W Counter Start 5 to 0 These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_5 to TCNT_0 count operation is stopped 1: TCNT_5 to TCNT_0 performs count operation

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 718 of 1270 REJ09B0466-0100

11.3.9 Timer Synchronous Register (TSYR)

TSYR selects independent operation or synchronous operation for the TCNT counters of channels 0 to 5. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Bit Bit Name Initial value R/W Description Reserved The write value should always be 0. SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 R/W R/W R/W R/W R/W R/W Timer Synchronization 5 to 0 These bits select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, synchronous presetting of multiple channels, and synchronous clearing through counter clearing on another channel are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR. 0: TCNT_5 to TCNT_0 operates independently (TCNT presetting /clearing is unrelated to other channels) 1: TCNT_5 to TCNT_0 performs synchronous operation (TCNT synchronous presetting/ synchronous clearing is possible)

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 719 of 1270 REJ09B0466-0100

11.3.10 Timer Start Register B (TSTRB)

TSTRB selects operation/stoppage for channels 6 to 11. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. Bit Bit Name Initial value R/W Description Reserved The write value should always be 0. CST11 CST10 CST9 CST8 CST7 CST6 R/W R/W R/W R/W R/W R/W Counter Start 11 to 6 These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_11 to TCNT_6 count operation is stopped 1: TCNT_11 to TCNT_6 performs count operation

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 720 of 1270 REJ09B0466-0100

11.3.11 Timer Synchronous Register B (TSYRB)

TSYRB selects independent operation or synchronous operation for the TCNT counters of channels 6 to 11. A channel performs synchronous operation when the corresponding bit in TSYRB is set to 1. Bit Bit Name Initial value R/W Description Reserved The write value should always be 0. SYNC11 SYNC10 SYNC9 SYNC8 SYNC7 SYNC6 R/W R/W R/W R/W R/W R/W Timer Synchronization 11 to 6 These bits select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, synchronous presetting of multiple channels, and synchronous clearing through counter clearing on another channel are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR. 0: TCNT_11 to TCNT_6 operates independently (TCNT presetting /clearing is unrelated to other channels) 1: TCNT_11 to TCNT_6 performs synchronous operation (TCNT synchronous presetting/ synchronous clearing is possible)

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 721 of 1270 REJ09B0466-0100

11.4 Operation

11.4.1 Basic Functions

Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, periodic counting, and external event counting. Each TGR can be used as an input capture register or output compare register. (1) Counter Operation When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on. (a) Example of count operation setting procedure Figure 11.3 shows an example of the count operation setting procedure.

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 722 of 1270 REJ09B0466-0100 Select counter clock Operation selection Select counter clearing source Periodic counter Set period Start count <Periodic counter> [1] [2] [4] [3] [5] Free-running counter Start count <Free-running counter> [5] [1] [2] [3] [4] [5] Select output compare register Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. Designate the TGR selected in [2] as an output compare register by means of TIOR. Set the periodic counter cycle in the TGR selected in [2]. Set the CST bit in TSTR to 1 to start the counter operation. Figure 11.3 Example of Counter Operation Setting Procedure

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 728 of 1270 REJ09B0466-0100 (b) Example of input capture operation Figure 11.10 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT. TCNT value H'0180 H'0000 TIOCA TGRA Time H'0010 H'0005 Counter cleared by TIOCB input (falling edge) H'0160 H'0005 H'0160 H'0010 TGRB H'0180 TIOCB Figure 11.10 Example of Input Capture Operation

11.4.2 Synchronous Operation

In synchronous operation, the values in multiple TCNT counters can be rewritten simultaneously (synchronous presetting). Also, multiple of TCNT counters can be cleared simultaneously (synchronous clearing) by making the appropriate setting in TCR. Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 5 and 6 to 11 can all be designated for synchronous operation.

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 731 of 1270 REJ09B0466-0100

11.4.3 Buffer Operation

Buffer operation, provided for channels 0, 3, 6, and 9, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or a compare match register. Table 11.29 shows the register combinations used in buffer operation. Table 11.29 Register Combinations in Buffer Operation Unit Channel Timer General Register Buffer Register 0 0 TGRA_0 TGRC_0 TGRB_0 TGRD_0

3 TGRA_3 TGRC_3

TGRB_3 TGRD_3 1 6 TGRA_6 TGRC_6 TGRB_6 TGRD_6

9 TGRA_9 TGRC_9

TGRB_9 TGRD_9

  • When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 11.13. Buffer register Timer general register TCNTComparator Compare match signal Figure 11.13 Compare Match Buffer Operation

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 735 of 1270 REJ09B0466-0100

11.4.4 Cascaded Operation

In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4, channel 7, or channel 10) counter clock at overflow/underflow of TCNT_2 (TCNT_5, TCNT_8, or TCNT_11) as set in bits TPSC2 to TPSC0 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 11.30 shows the register combinations used in cascaded operation. Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid and the counter operates independently in phase counting mode. Table 11.30 Cascaded Combinations Combination Upper 16 Bits Lower 16 Bits Channels 1 and 2 TCNT_1 TCNT_2 Channels 4 and 5 TCNT_4 TCNT_5 Channels 7 and 8 TCNT_7 TCNT_8 Channels 10 and 11 TCNT_10 TCNT_11 (1) Example of Cascaded Operation Setting Procedure Figure 11.18 shows an example of the setting procedure for cascaded operation. Cascaded operation Set cascading Start count <Cascaded operation> Set bits TPSC2 to TPSC0 in the channel 1 (channel 4) TCR to B'1111 to select TCNT_2 (TCNT_5) overflow/underflow counting. Set the CST bit in TSTR for the upper and lower channel to 1 to start the count operation.[1] [2] [1] [2] Figure 11.18 Cascaded Operation Setting Procedure

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 737 of 1270 REJ09B0466-0100

11.4.5 PWM Modes

In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR. Settings of TGR registers can output a PWM waveform in the range of 0–% to 100–% duty cycle. Designating TGR compare match as the counter clearing source enables the cycle to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below.

  • PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The outputs specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR are output from the TIOCA and TIOCC pins at compare matches A and C, respectively. The outputs specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR are output at compare matches B and D, respectively. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 8-phase PWM output is possible.
  • PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty cycle registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty cycle registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 15-phase PWM output is possible by combined use with synchronous operation. The correspondence between PWM output pins and registers is shown in table 11.31.

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 738 of 1270 REJ09B0466-0100 Table 11.31 PWM Output Registers and Output Pins Output Pins Unit Channel Registers PWM Mode 1 PWM Mode 2 0 0 TGRA_0 TIOCA0 TIOCA0 TGRB_0 TIOCB0 TGRC_0 TIOCC0 TIOCC0 TGRD_0 TIOCD0

1 TGRA_1 TIOCA1 TIOCA1

TGRB_1 TIOCB1

2 TGRA_2 TIOCA2 TIOCA2

TGRB_2 TIOCB2

3 TGRA_3 TIOCA3 TIOCA3

TGRB_3 TIOCB3 TGRC_3 TIOCC3 TIOCC3 TGRD_3 TIOCD3

4 TGRA_4 TIOCA4 TIOCA4

TGRB_4 TIOCB4

5 TGRA_5 TIOCA5 TIOCA5

TGRB_5 TIOCB5 1 6 TGRA_6 TIOCA6 TIOCA6 TGRB_6 TIOCB6 TGRC_6 TIOCC6 TIOCC6 TGRD_6 TIOCD6

7 TGRA_7 TIOCA7 TIOCA7

TGRB_7 TIOCB7

8 TGRA_8 TIOCA8 TIOCA8

TGRB_8 TIOCB8

9 TGRA_9 TIOCA9 TIOCA9

TGRB_9 TIOCB9 TGRC_9 TIOCC9 TIOCC9 TGRD_9 TIOCD9

10 TGRA_10 TIOCA10 TIOCA10

TGRB_10 TIOCB10

11 TGRA_11 TIOCA11 TIOCA11

TGRB_11 TIOCB11 Note: In PWM mode 2, PWM output is not possible fo r the TGR register in which the cycle is set.

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 743 of 1270 REJ09B0466-0100

11.4.6 Phase Counting Mode

In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, 5, 7, 8, 10, and 11. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be used. This can be used for two-phase encoder pulse input. When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow occurs while TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of whether TCNT is counting up or down. Table 11.32 shows the correspondence between external clock pins and channels. Table 11.32 Clock Input Pins in Phase Counting Mode External Clock Pins Unit Channels A-Phase B-Phase

0 When channel 1 or 5 is set to phase counting mode TCLKA TCLKB

When channel 2 or 4 is set to phase counting mode TCLKC TCLKD

1 When channel 7 or 11 is set to phase counting mode TCLKE TCLKF

When channel 8 or 10 is set to phase counting mode TCLKG TCLKH

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 745 of 1270 REJ09B0466-0100 Table 11.33 Up/Down-Count Conditions in Phase Counting Mode 1 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) TCLKE (Channels 7 and 11) TCLKG (Channels 8 and 10) TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) TCLKF (Channels 7 and 11) TCLKH (Channels 8 and 10) Operation High level Up-count Low level Low level High level High level Down-count Low level High level Low level [Legend] : Rising edge : Falling edge

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 749 of 1270 REJ09B0466-0100 (3) Phase Counting Mode Application Example Figure 11.30 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB. Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and TGRC_0 are used for the compare match function, and are set with the speed control cycle and position control cycle. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture source, and detection of the pulse width of 2-phase encoder 4-multiplication pulses is performed. TGRA_1 and TGRB_1 for channel 1 are designated for input capture, channel 0 TGRA_0 and TGRC_0 compare matches are selected as the input capture source, and the up/down-counter values for the control cycles are stored. This procedure enables accurate position/speed detection to be achieved.

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 750 of 1270 REJ09B0466-0100 TCNT_1 TCNT_0 Channel 1 TGRA_1 (speed cycle capture) TGRA_0 (speed control cycle) TGRB_1 (position cycle capture) TGRC_0 (position control cycle) TGRB_0 (pulse width capture) TGRD_0 (buffer operation) Channel 0 TCLKA TCLKB Edge detection circuit Figure 11.30 Phase Counting Mode Application Example

11.5 Interrupt Sources

There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disable bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priorities can be changed by the interrupt controller, but the priority order within a channel is fixed. For details, see section 5, Interrupt Controller. Table 11.37 lists the TPU interrupt sources.

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 751 of 1270 REJ09B0466-0100 Table 11.37 TPU Interrupts Unit Channel Name Interrupt Source Interrupt Flag DTC Activation DMAC Activation 0 0 TGI0A TGRA_0 input capture/com pare match TGFA_0 Possible Possible TGI0B TGRB_0 input capture/compar e match TGFB_0 Possi ble Not possible TGI0C TGRC_0 input capture/compar e match TGFC_0 Possible Not possible TGI0D TGRD_0 input capture/compar e match TGFD_0 Possible Not possible TCI0V TCNT_0 overflow TC FV_0 Not possible Not possible

1 TGI1A TGRA_1 input capture/com pare match TGFA_1 Possible Possible

TGI1B TGRB_1 input capture/compar e match TGFB_1 Possi ble Not possible TCI1V TCNT_1 overflow TC FV_1 Not possible Not possible TCI1U TCNT_1 underflow TCFU _1 Not possible Not possible

2 TGI2A TGRA_2 input capture/com pare match TGFA_2 Possible Possible

TGI2B TGRB_2 input capture/compar e match TGFB_2 Possi ble Not possible TCI2V TCNT_2 overflow TC FV_2 Not possible Not possible TCI2U TCNT_2 underflow TCFU _2 Not possible Not possible

3 TGI3A TGRA_3 input capture/com pare match TGFA_3 Possible Possible

TGI3B TGRB_3 input capture/compar e match TGFB_3 Possi ble Not possible TGI3C TGRC_3 input capture/compar e match TGFC_3 Possible Not possible TGI3D TGRD_3 input capture/compar e match TGFD_3 Possible Not possible TCI3V TCNT_3 overflow TC FV_3 Not possible Not possible

4 TGI4A TGRA_4 input capture/com pare match TGFA_4 Possible Possible

TGI4B TGRB_4 input capture/compar e match TGFB_4 Possi ble Not possible TCI4V TCNT_4 overflow TC FV_4 Not possible Not possible TCI4U TCNT_4 underflow TCFU _4 Not possible Not possible

5 TGI5A TGRA_5 input capture/com pare match TGFA_5 Possible Possible

TGI5B TGRB_5 input capture/compar e match TGFB_5 Possi ble Not possible TCI5V TCNT_5 overflow TC FV_5 Not possible Not possible TCI5U TCNT_5 underflow TCFU _5 Not possible Not possible

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 752 of 1270 REJ09B0466-0100 Unit Channel Name Interrupt Source Interrupt Flag DTC Activation DMAC Activation 1 6 TGI6A TGRA_6 input capture/compar e match TGFA_6 Possi ble Not possible TGI6B TGRB_6 input capture/compar e match TGFB_6 Possi ble Not possible TGI6C TGRC_6 input capture/compar e match TGFC_6 Possible Not possible TGI6D TGRD_6 input capture/compar e match TGFD_6 Possible Not possible TCI6V TCNT_6 overflow TC FV_6 Not possible Not possible

7 TGI7A TGRA_7 input capture/compar e match TGFA_7 Possi ble Not possible

TGI7B TGRB_7 input capture/compar e match TGFB_7 Possi ble Not possible TCI7V TCNT_7 overflow TC FV_7 Not possible Not possible TCI7U TCNT_7 underflow TCFU _7 Not possible Not possible

8 TGI8A TGRA_8 input capture/compar e match TGFA_8 Possi ble Not possible

TGI8B TGRB_8 input capture/compar e match TGFB_8 Possi ble Not possible TCI8V TCNT_8 overflow TC FV_8 Not possible Not possible TCI8U TCNT_8 underflow TCFU _8 Not possible Not possible

9 TGI9A TGRA_9 input capture/compar e match TGFA_9 Possi ble Not possible

TGI9B TGRB_9 input capture/compar e match TGFB_9 Possi ble Not possible TGI9C TGRC_9 input capture/compar e match TGFC_9 Possible Not possible TGI9D TGRD_9 input capture/compar e match TGFD_9 Possible Not possible TCI9V TCNT_9 overflow TC FV_9 Not possible Not possible

10 TGI10A TGRA_10 input capture/comp are match TGFA_10 Po ssible Not possible

TGI10B TGRB_10 input capture/comp are match TGFB_10 Po ssible Not possible TCI10V TCNT_10 overflow TC FV_10 Not possible Not possible TCI10U TCNT_10 underflow TC FU_10 Not possible Not possible

11 TGI11A TGRA_11 input capture/comp are match TGFA_11 Po ssible Not possible

TGI11B TGRB_11 input capture/comp are match TGFB_11 Po ssible Not possible TCI11V TCNT_11 overflow TC FV_11 Not possible Not possible TCI11U TCNT_11 underflow TC FU_11 Not possible Not possible Note: This table shows the initia l state immediately after a reset. The relative channel priorities can be changed by the interrupt controller.

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 753 of 1270 REJ09B0466-0100 (1) Input Capture/Comp are Match Interrupt An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 32 input capture/compare match interrupts, four each for channels 0, 3, 6, and 9, and two each for channels 1, 2, 4, 5, 7, 8, 10, and 11. (2) Overflow Interrupt An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The TPU has 12 overflow interrupts, one for each channel. (3) Underflow Interrupt An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The TPU has eight underflow interrupts, one each for channels 1, 2, 4, 5, 7, 8, 10, and 11.

11.6 DTC Activation

The DTC can be activated by the TGR input capture/compare match interrupt for a channel. For details, see section 9, Data Transfer Controller (DTC). A total of 32 TPU input capture/compare match interrupts can be used as DTC activation sources, four each for channels 0, 3, 6, and 9, and two each for channels 1, 2, 4, 5, 7, 8, 10, and 11.

11.7 DMAC Activation

In unit 0 of the TPU, the DMAC can be activated by the TGRA input capture/compare match interrupt for a channel. For details, see section 7, DMA Controller (DMAC). (The DMAC cannot be activated by unit 1.) In unit 0 of the TPU, a total of six TGRA input capture/compare match interrupts can be used as DMAC activation sources, one for each channel.

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 754 of 1270 REJ09B0466-0100

11.8 A/D Converter Activation

The A/D converter can be activated by the TGRA input capture/compare match for a channel. If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel, a request to start A/D conversion is sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started. In the TPU, a total of 12 TGRA input capture/compare match interrupts can be used as A/D converter conversion start sources, one for each channel.

11.9 Operation Timing

11.9.1 Input/Output Timing

(1) TCNT Count Timing Figure 11.31 shows TCNT count timing in internal clock operation, and figure 11.32 shows TCNT count timing in external clock operation. TCNT TCNT input clock Internal clock φ N – 1 N N + 1 N + 2 Falling edge Rising edge Figure 11.31 Count Timing in Internal Clock Operation

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 758 of 1270 REJ09B0466-0100 TGRA, TGRB TCNT Input capture signal TGRC, TGRD N n n N + 1 N N N + 1 φ Figure 11.38 Buffer Operation Timing (Input Capture)

11.9.2 Interrupt Signal Timing

(1) TGF Flag Setting Timing in Case of Compare Match Figure 11.39 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and the TGI interrupt request signal timing. TGR TCNT TCNT input clock N N N + 1 Compare match signal TGF flag TGI interrupt φ Figure 11.39 TGI Interrupt Timing (Compare Match)

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 762 of 1270 REJ09B0466-0100

11.10 Usage Notes

11.10.1 Module Stop Mode Setting

TPU operation can be disabled or enabled using the module stop control register. The initial setting is for TPU operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 24, Power-Down Modes.

11.10.2 Input Clock Restrictions

The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 11.45 shows the input clock conditions in phase counting mode. Overlap Phase diffe- rence Phase diffe- renceOverlap TCLKA (TCLKC) TCLKB (TCLKD) Pulse width Pulse width Pulse width Pulse width Notes: Phase difference and overlap Pulse width : 1.5 states or more : 2.5 states or more Figure 11.45 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 763 of 1270 REJ09B0466-0100

11.10.3 Caution on Cycle Setting

When counter clearing by compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: f = φ (N + 1) Where f: Counter frequency φ: Operating frequency N: TGR set value

11.10.4 Contention between TCNT Write and Clear Operations

If the counter clearing signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 11.46 shows the timing in this case. Counter clearing signal Write signal Address φ TCNT address TCNT TCNT write cycle T1 T2 N H'0000 Figure 11.46 Contention between TCNT Write and Clear Operations

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 764 of 1270 REJ09B0466-0100

11.10.5 Contention between TCNT Write and Increment Operations

If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 11.47 shows the timing in this case. TCNT input clock Write signal Address φ TCNT address TCNT TCNT write cycle T1 T2 NM TCNT write data Figure 11.47 Contention between TCNT Write and Increment Operations

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 765 of 1270 REJ09B0466-0100

11.10.6 Contention between TGR Write and Compare Match

If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is disabled. A compare match also does not occur when the same value as before is written. Figure 11.48 shows the timing in this case. Compare match signal Write signal Address φ TGR address TCNT TGR write cycle T1 T2 NM TGR write data TGR N N + 1 Disabled Figure 11.48 Contention between TGR Write and Compare Match

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 766 of 1270 REJ09B0466-0100

11.10.7 Contention between Buffer Register Write and Compare Match

If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the data prior to the write. Figure 11.49 shows the timing in this case. Compare match signal Write signal Address φ Buffer register address Buffer register TGR write cycle T1 T2 NTGR NM Buffer register write data Figure 11.49 Contention between Buffer Register Write and Compare Match

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 767 of 1270 REJ09B0466-0100

11.10.8 Contention between TGR Read and Input Capture

If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 11.50 shows the timing in this case. Input capture signal Read signal Address φ TGR address TGR TGR read cycle T1 T2 MInternal data bus X M Figure 11.50 Contention between TGR Read and Input Capture

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 768 of 1270 REJ09B0466-0100

11.10.9 Contention between TGR Write and Input Capture

If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 11.51 shows the timing in this case. Input capture signal Write signal Address φ TCNT TGR write cycle T1 T2 MTGR M TGR address Figure 11.51 Contention between TGR Write and Input Capture

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 769 of 1270 REJ09B0466-0100

11.10.10 Contention between Buffer Register Write and Input Capture

If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 11.52 shows the timing in this case. Input capture signal Write signal Address φ TCNT Buffer register write cycle T1 T2 NTGR N M MBuffer register Buffer register address Figure 11.52 Contention between Buffer Register Write and Input Capture

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 770 of 1270 REJ09B0466-0100

11.10.11 Contention between Overflow/Underflow and Counter Clearing

If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 11.53 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR. Counter clearing signal TCNT input clock φ TCNT TGF Disabled TCFV H'FFFF H'0000 Figure 11.53 Contention between Overflow and Counter Clearing

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 771 of 1270 REJ09B0466-0100

11.10.12 Contention between TCNT Write and Overflow/Underflow

If there is an up-count or down-count in the T2 state of a TCNT write cycle, when overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 11.54 shows the operation timing when there is contention between TCNT write and overflow. Write signal Address φ TCNT address TCNT TCNT write cycle T1 T2 H'FFFF M TCNT write data TCFV flag Figure 11.54 Contention between TCNT Write and Overflow

11.10.13 Multiplexing of I/O Pins

In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not be performed from a multiplexed pin.

11.10.14 Interrupts and Module Stop Mode

If module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DMAC or DTC activation source. Interrupts should therefore be disabled before entering module stop mode.

Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 772 of 1270 REJ09B0466-0100

Section 12 Programmable Pulse Generator (PPG) Rev. 1.00 Sep. 19, 2008 Page 773 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) The programmable pulse generator (PPG) provides pulse outputs by using the 16-bit timer pulse unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (groups 3 to 0) that can operate both simultaneously and independently. The block diagram of PPG is shown in figure 12.1.

12.1 Features

  • 16-bit output data
  • Four output groups
  • Selectable output trigger signals
  • Non-overlap mode
  • Can operate together with the data transfer controller (DTC) and the DMA controller (DMAC)
  • Settable inverted output
  • Module stop mode can be set

Section 12 Programmable Pulse Generator (PPG) Rev. 1.00 Sep. 19, 2008 Page 774 of 1270 REJ09B0466-0100 Compare match signals PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 PO7 PO6 PO5 PO4 PO3 PO2 PO1 PO0 Legend: PMR PCR NDERH NDERL NDRH NDRL PODRH PODRL : PPG output mode register : PPG output control register : Next data enable register H : Next data enable register L : Next data register H : Next data register L : Output data register H : Output data register L Internal data bus Pulse output pins, group 3 Pulse output pins, group 2 Pulse output pins, group 1 Pulse output pins, group 0 PODRH PODRL NDRH (NDRHH, NDRHL) NDRL (NDRLH, NDRLL) Control logic NDERH PMR NDERL PCR Figure 12.1 Block Diagram of PPG

Section 12 Programmable Pulse Generator (PPG) Rev. 1.00 Sep. 19, 2008 Page 775 of 1270 REJ09B0466-0100

12.2 Input/Output Pins

Table 12.1 shows the PPG pin configuration. Table 12.1 Pin Configuration Pin Name I/O Function PO15 Output PO14 Output PO13 Output PO12 Output Group 3 pulse output PO11 Output PO10 Output PO9 Output PO8 Output Group 2 pulse output PO7 Output PO6 Output PO5 Output PO4 Output Group 1 pulse output PO3 Output PO2 Output PO1 Output PO0 Output Group 0 pulse output

12.3 Register Descriptions

The PPG has the following registers.

  • Next data enable register H (NDERH)
  • Next data enable register L (NDERL)
  • Output data register H (PODRH)
  • Output data register L (PODRL)
  • Next data register H (NDRH)
  • Next data register L (NDRL)
  • PPG output control register (PCR)
  • PPG output mode register (PMR)

Section 12 Programmable Pulse Generator (PPG) Rev. 1.00 Sep. 19, 2008 Page 776 of 1270 REJ09B0466-0100

12.3.1 Next Data Enable Registers H, L (NDERH, NDERL)

NDERH, NDERL enable or disable pulse output on a bit-by-bit basis. For outputting pulse by the PPG, set the corresponding DDR to 1.

  • NDERH Bit Bit Name Initial Value R/W Description NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 R/W R/W R/W R/W R/W R/W R/W R/W Next Data Enable 15 to 8 When a bit is set to 1, the value in the corresponding NDRH bit is transferred to the PODRH bit by the selected output trigger. Values are not transferred from NDRH to PODRH for cleared bits.
  • NDERL Bit Bit Name Initial Value R/W Description NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 R/W R/W R/W R/W R/W R/W R/W R/W Next Data Enable 7 to 0 When a bit is set to 1, the value in the corresponding NDRL bit is transferred to the PODRL bit by the selected output trigger. Values are not transferred from NDRL to PODRL for cleared bits.

Section 12 Programmable Pulse Generator (PPG) Rev. 1.00 Sep. 19, 2008 Page 777 of 1270 REJ09B0466-0100

12.3.2 Output Data Registers H, L (PODRH, PODRL)

PODRH and PODRL store output data for use in pulse output. A bit that has been set for pulse output by NDER is read-only and cannot be modified.

  • PODRH Bit Bit Name Initial Value R/W Description POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8 R/W R/W R/W R/W R/W R/W R/W R/W Output Data Register 15 to 8 For bits which have been set to pulse output by NDERH, the output trigger transfers NDRH values to this register during PPG operation. While NDERH is set to 1, the CPU cannot write to this register. While NDERH is cleared, the initial output value of the pulse can be set.
  • PODRL Bit Bit Name Initial Value R/W Description POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0 R/W R/W R/W R/W R/W R/W R/W R/W Output Data Register 7 to 0 For bits which have been set to pulse output by NDERL, the output trigger transfers NDRL values to this register during PPG operation. While NDERL is set to 1, the CPU cannot write to this register. While NDERL is cleared, the initial output value of the pulse can be set.

Section 12 Programmable Pulse Generator (PPG) Rev. 1.00 Sep. 19, 2008 Page 778 of 1270 REJ09B0466-0100

12.3.3 Next Data Registers H, L (NDRH, NDRL)

NDRH, NDRL store the next data for pulse output. The NDR addresses differ depending on whether pulse output groups have the same output trigger or different output triggers.

  • NDRH (NDRHH, NDRHL)* If pulse output groups 2 and 3 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. Note: * When pulse output groups 2 and 3 have the same output trigger by PCR settings, the NDRH address is H′FF4C. When they have different output triggers, the NDRH addresses corresponding to the groups 2 and 3 are NDRHH (H′FF4E) and NDRHL (H′FF4C), respectively. Also, when pulse output groups 0 and 1 have the same output trigger by PCR settings, the NDRL address is NDRLH (H′FF4D). When they have different output triggers, the NDRL addresses corresponding to the groups 0 and 1 are NDRLL (H ′FF4F) and H′FF4D, respectively. Bit Bit Name Initial Value R/W Description NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 R/W R/W R/W R/W R/W R/W R/W R/W Next Data Register 15 to 8 The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR. If pulse output groups 2 and 3 have different output triggers, upper 4 bits and lower 4 bits are mapped to the different addresses as shown below. Bit Bit Name Initial Value R/W Description NDR15 NDR14 NDR13 NDR12 R/W R/W R/W R/W Next Data Register 15 to 12 The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR. 3 to 0 — All 1 — Reserved 1 is always read and write is disabled.

Section 12 Programmable Pulse Generator (PPG) Rev. 1.00 Sep. 19, 2008 Page 779 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description 7 to 4 — All 1 — Reserved 1 is always read and write is disabled. NDR11 NDR10 NDR9 NDR8 R/W R/W R/W R/W Next Data Register 11 to 8 The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR.

  • NDRL (NDRLH, NDRLL)* If pulse output groups 0 and 1 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. Note: * When pulse output groups 2 and 3 have the same output trigger by PCR settings, the NDRH address is H¢FF4C. When they have different output triggers, the NDRH addresses corresponding to the groups 2 and 3 are NDRHH (H¢FF4E) and NDRHL (H¢FF4C), respectively. Also, when pulse output groups 0 and 1 have the same output trigger by PCR settings, the NDRL address is NDRLH (H¢FF4D). When they have different output triggers, the NDRL addresses corresponding to the groups 0 and 1 are NDRLL (H¢FF4F) and H¢FF4D, respectively. Bit Bit Name Initial Value R/W Description NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 R/W R/W R/W R/W R/W R/W R/W R/W Next Data Register 7 to 0 The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR.

Section 12 Programmable Pulse Generator (PPG) Rev. 1.00 Sep. 19, 2008 Page 780 of 1270 REJ09B0466-0100 If pulse output groups 0 and 1 have different output triggers, upper 4 bits and lower 4 bits are mapped to the different addresses as shown below. Bit Bit Name Initial Value R/W Description NDR7 NDR6 NDR5 NDR4 R/W R/W R/W R/W Next Data Register 7 to 4 The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR. 3 to 0 — All 1 — Reserved 1 is always read and write is disabled. Bit Bit Name Initial Value R/W Description 7 to 4 — All 1 — Reserved 1 is always read and write is disabled. NDR3 NDR2 NDR1 NDR0 R/W R/W R/W R/W Next Data Register 3 to 0 The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR.

Section 12 Programmable Pulse Generator (PPG) Rev. 1.00 Sep. 19, 2008 Page 781 of 1270 REJ09B0466-0100

12.3.4 PPG Output Control Register (PCR)

PCR selects output trigger signals on a group-by-group basis. For details on output trigger selection, refer to section 12.3.5, PPG Output Mode Register (PMR). Bit Bit Name Initial Value R/W Description G3CMS1 G3CMS0 R/W R/W Group 3 Compare Match Select 1 and 0 Select output trigger of pulse output group 3. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3 G2CMS1 G2CMS0 R/W R/W Group 2 Compare Match Select 1 and 0 Select output trigger of pulse output group 2. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3 G1CMS1 G1CMS0 R/W R/W Group 1 Compare Match Select 1 and 0 Select output trigger of pulse output group 1. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3 G0CMS1 G0CMS0 R/W R/W Group 0 Compare Match Select 1 and 0 Select output trigger of pulse output group 0. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3

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12.3.5 PPG Output Mo de Register (PMR)

PMR selects the pulse output mode of the PPG for each group. If inverted output is selected, a low-level pulse is output when PODRH is 1 and a high-level pulse is output when PODRH is 0. If non-overlapping operation is selected, PPG updates its output values at compare match A or B of the TPU that becomes the output trigger. For details, refer to section 12.4.4, Non-Overlapping Pulse Output. Bit Bit Name Initial Value R/W Description

7 G3INV 1 R/W Group 3 Inversion

Selects direct output or inverted output for pulse output group 3. 0: Inverted output 1: Direct output

6 G2INV 1 R/W Group 2 Inversion

Selects direct output or inverted output for pulse output group 2. 0: Inverted output 1: Direct output

5 G1INV 1 R/W Group 1 Inversion

Selects direct output or inverted output for pulse output group 1. 0: Inverted output 1: Direct output

4 G0INV 1 R/W Group 0 Inversion

Selects direct output or inverted output for pulse output group 0. 0: Inverted output 1: Direct output

Section 12 Programmable Pulse Generator (PPG) Rev. 1.00 Sep. 19, 2008 Page 783 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description

3 G3NOV 0 R/W Group 3 Non-Overlap

Selects normal or non-overlapping operation for pulse output group 3. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel)

2 G2NOV 0 R/W Group 2 Non-Overlap

Selects normal or non-overlapping operation for pulse output group 2. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel)

1 G1NOV 0 R/W Group 1 Non-Overlap

Selects normal or non-overlapping operation for pulse output group 1. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel)

0 G0NOV 0 R/W Group 0 Non-Overlap

Selects normal or non-overlapping operation for pulse output group 0. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel)

Section 12 Programmable Pulse Generator (PPG) Rev. 1.00 Sep. 19, 2008 Page 784 of 1270 REJ09B0466-0100

12.4 Operation

Figure 12.2 shows an overview diagram of the PPG. PPG pulse output is enabled when the corresponding bits in P1DDR, P2DDR, and NDER are set to 1. An initial output value is determined by its corresponding PODR initial setting. When the compare match event specified by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output values. Sequential output of data of up to 16 bits is possible by writing new output data to NDR before the next compare match. Output trigger signal Pulse output pin Internal data bus Normal output/inverted output C PODRQD NDER Q NDRQ D DDR Figure 12.2 Overview Diagram of PPG

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12.4.1 Output Timing

If pulse output is enabled, NDR contents are transferred to PODR and output when the specified compare match event occurs. Figure 12.3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. TCNT φ N N + 1 TGRA N Compare match A signal NDRH mnPODRH PO8 to PO15 n m n Figure 12.3 Timing of Transfer and Output of NDR Contents (Example)

Section 12 Programmable Pulse Generator (PPG) Rev. 1.00 Sep. 19, 2008 Page 786 of 1270 REJ09B0466-0100

12.4.2 Sample Setup Procedure for Normal Pulse Output

Figure 12.4 shows a sample procedure for setting up normal pulse output. Select TGR functions [1] Set TGRA value Set counting operation Select interrupt request Set initial output data Enable pulse output Select output trigger Set next pulse output data Start counter Set next pulse output data Normal PPG output No Yes TPU setup Port and PPG setup TPU setup [2] [3] [4] [5] [6] [7] [8] [9] [10] Compare match? [1] Set TIOR to make TGRA an output compare register (with output disabled). [2] Set the PPG output trigger period. [3] Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR2 to CCLR0. [4] Enable the TGIA interrupt in TIER. The DTC or DMAC can also be set up to transfer data to NDR. [5] Set the initial output values in PODR. [6] Set the DDR and NDER bits for the pins to be used for pulse output to 1. [7] Select the TPU compare match event to be used as the output trigger in PCR. [8] Set the next pulse output values in NDR. [9] Set the CST bit in TSTR to 1 to start the TCNT counter. [10] At each TGIA interrupt, set the next output values in NDR. Figure 12.4 Setup Procedure for Normal Pulse Output (Example)

Section 12 Programmable Pulse Generator (PPG) Rev. 1.00 Sep. 19, 2008 Page 787 of 1270 REJ09B0466-0100

12.4.3 Example of Normal Pulse Output (Example of Five-Phase Pulse Output)

Figure 12.5 shows an example in which pulse output is used for cyclic five-phase pulse output. TCNT value TCNT TGRA H'0000 NDRH 00 80 C0 40 60 20 30 10 18 08 88PODRH PO15 PO14 PO13 PO12 PO11 Time Compare match C080 C080 40 60 20 30 10 18 08 88 80 C0 40 Figure 12.5 Normal Pulse Output Example (Five-Phase Pulse Output) 1. Set up TGRA in TPU which is used as the output trigger to be an output compare register. Set a cycle in TGRA so that the counter will be cleared by compare match A. Set the TGIEA bit in TIER to 1 to enable the compare match/input capture A (TGIA) interrupt. 2. Write H'F8 in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0 bits in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger. Write output data H'80 in NDRH. 3. The timer counter in the TPU channel starts. When compare match A occurs, the NDRH contents are transferred to PODRH and output. The TGIA interrupt handling routine writes the next output data (H'C0) in NDRH. 4. Five-phase pulse output (one or two phases active at a time) can be obtained subsequently by writing H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88... at successive TGIA interrupts. If the DTC or DMAC is set for activation by the TGIA interrupt, pulse output can be obtained without imposing a load on the CPU.

Section 12 Programmable Pulse Generator (PPG) Rev. 1.00 Sep. 19, 2008 Page 788 of 1270 REJ09B0466-0100

12.4.4 Non-Overlapping Pulse Output

During non-overlapping operation, transfer from NDR to PODR is performed as follows:

  • NDR bits are always transferred to PODR bits at compare match A.
  • At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred if their value is 1. Figure 12.6 illustrates the non-overlapping pulse output operation. Compare match A Compare match B Pulse output pin Internal data bus Normal output/inverted output C PODRQD NDER Q NDRQ D DDR Figure 12.6 Non-Overlapping Pulse Output Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. The NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlap margin). This can be accomplished by having the TGIA interrupt handling routine write the next data in NDR, or by having the TGIA interrupt activate the DTC or DMAC. Note, however, that the next data must be written before the next compare match B occurs.

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12.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output

Figure 12.8 shows a sample procedure for setting up non-overlapping pulse output. Select TGR functions [1] Set TGR values Set counting operation Select interrupt request Set initial output data Enable pulse output Select output trigger Set next pulse output data Start counter Set next pulse output data Compare match A? No Yes TPU setup PPG setup TPU setup Non-overlapping pulse output Set non-overlapping groups [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [1] Set TIOR to make TGRA and TGRB an output compare registers (with output disabled). [2] Set the pulse output trigger period in TGRB and the non-overlap period in TGRA. [3] Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR2 to CCLR0. [4] Enable the TGIA interrupt in TIER. The DTC or DMAC can also be set up to transfer data to NDR. [5] Set the initial output values in PODR. [6] Set the DDR and NDER bits for the pins to be used for pulse output to [7] Select the TPU compare match event to be used as the pulse output trigger in PCR. [8] In PMR, select the groups that will operate in non-overlap mode. [9] Set the next pulse output values in NDR. [10] Set the CST bit in TSTR to 1 to start the TCNT counter. [11] At each TGIA interrupt, set the next output values in NDR. Figure 12.8 Setup Procedure for Non-Overlapping Pulse Output (Example)

Section 12 Programmable Pulse Generator (PPG) Rev. 1.00 Sep. 19, 2008 Page 791 of 1270 REJ09B0466-0100

12.4.6 Example of Non-Overlapping Pulse Output (Example of Four-Phase

Complementary Non-Overlapping Output) Figure 12.9 shows an example in which pulse output is used for four-phase complementary non- overlapping pulse output. TCNT value TCNT TGRB TGRA H'0000 NDRH 95 65 59 56 95 65 00 95 05 65 41 59 50 56 14 95 05 65PODRH PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Time Non-overlap margin Figure 12.9 Non-Overlapping Pulse Output Example (Four-Phase Complementary)

Section 12 Programmable Pulse Generator (PPG) Rev. 1.00 Sep. 19, 2008 Page 792 of 1270 REJ09B0466-0100 1. Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are output compare registers. Set the trigger period in TGRB and the non-overlap margin in TGRA, and set the counter to be cleared by compare match B. Set the TGIEA bit in TIER to 1 to enable the TGIA interrupt. 2. Write H'FF in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0 bits in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger. Set the G3NOV and G2NOV bits in PMR to 1 to select non-overlapping output. Write output data H'95 in NDRH. 3. The timer counter in the TPU channel starts. When a compare match with TGRB occurs, outputs change from 1 to 0. When a compare match with TGRA occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed by the value set in TGRA). The TGIA interrupt handling routine writes the next output data (H'65) in NDRH. 4. Four-phase complementary non-overlapping pulse output can be obtained subsequently by writing H'59, H'56, H'95... at successive TGIA interrupts. If the DTC or DMAC is set for activation by the TGIA interrupt, pulse output can be obtained without imposing a load on the CPU.

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12.4.7 Inverted Pulse Output

If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the inverse of the PODR contents can be output. Figure 12.10 shows the outputs when G3INV and G2INV are cleared to 0, in addition to the settings of figure 12.9. TCNT value TCNT TGRB TGRA H'0000 NDRH 95 65 59 56 95 65 00 95 05 65 41 59 50 56 14 95 05 65PODRL PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Time Figure 12.10 Inverted Pulse Output (Example)

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12.4.8 Pulse Output Triggered by Input Capture

Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA functions as an input capture register in the TPU channel selected by PCR, pulse output will be triggered by the input capture signal. Figure 12.11 shows the timing of this output. N MN TIOC pin φ Input capture signal NDR PODR MNPO Figure 12.11 Pulse Output Triggered by Input Capture (Example)

Section 12 Programmable Pulse Generator (PPG) Rev. 1.00 Sep. 19, 2008 Page 795 of 1270 REJ09B0466-0100

12.5 Usage Notes

12.5.1 Module Stop Mode Setting

PPG operation can be disabled or enabled using the module stop control register. The initial value is for PPG operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 24, Power-Down Modes.

12.5.2 Operation of Pulse Output Pins

Pins PO0 to PO15 are also used for other peripheral functions such as the TPU. When output by another peripheral function is enabled, the corresponding pins cannot be used for pulse output. Note, however, that data transfer from NDR bits to PODR bits takes place, regardless of the usage of the pins. Pin functions should be changed only under conditions in which the output trigger event will not occur.

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Section 13 8-Bit Timers (TMR) Rev. 1.00 Sep. 19, 2008 Page 797 of 1270 REJ09B0466-0100 Section 13 8-Bit Timers (TMR) This LSI has an on-chip 8-bit timer module with two channels operating on the basis of an 8-bit counter. The 8-bit timer module can be used to count external events and be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two registers.

13.1 Features

  • Selection of seven clock sources The counters can be driven by one of six internal clock signals (φ/8, φ/64, φ/8192, φ/2, φ/32, or φ/1024) or an external clock input
  • Selection of three ways to clear the counters The counters can be cleared on compare match A or B, or by an external reset signal
  • Timer output control by a combination of two compare match signals The timer output signal in each channel is controlled by a combination of two independent compare match signals, enabling the timer to generate output waveforms with an arbitrary duty cycle or PWM output
  • Provision for cascading of two channels (TMR_0 and TMR_1) Operation as a 16-bit timer is possible, using TMR_0 for the upper 8 bits and TMR_1 for the lower 8 bits (16-bit count mode) TMR_1 can be used to count TMR_0 compare matches (compare match count mode)
  • Three independent interrupts Compare match A and B and overflow interrupts can be requested independently
  • A/D converter conversion start trigger can be generated Figure 13.1 shows a block diagram of the 8-bit timer module (TMR_0 and TMR_1).

Section 13 8-Bit Timers (TMR) Rev. 1.00 Sep. 19, 2008 Page 798 of 1270 REJ09B0466-0100 φ/8 φ/64 φ/8192 φ/2 φ/32 φ/1024 Counter clock 1 Counter clock 0 Compare match A1 Compare match A0 Counter clear 1 CMIA0 CMIB0 OVI0 CMIA1 CMIB1 OVI1 Interrupt signals TMO0 TMRI0 TCORA_0 Comparator A_0 Comparator B_0 TCORB_0 TCSR_0 TCR_0 TCORA_1 Comparator A_1 TCNT_1 Comparator B_1 TCORB_1 TCSR_1 TCR_1 TMCI0 TMCI1 TCNT_0 Overflow 1 Overflow 0 Compare match B1 Compare match B0 TMO1 TMRI1 Counter clear 0 Channel 1 (TMR_1) TCCR_0 TCCR_1 Channel 0 (TMR_0) Internal clock sources Clock select TCORA_0 : Time constant register A_0 TCNT_0 : Timer counter_0 TCORB_0 : Time constant register B_0 TCSR_0 : Timer control/status register_0 TCR_0 : Timer control register_0 TCCR_0 : Timer counter control register_0 TCORA_1 : Time constant register A_1 TCNT_1 : Timer counter_1 TCORB_1 : Time constant register B_1 TCSR_1 : Timer control/status register_1 TCR_1 : Timer control register_1 TCCR_1 : Timer counter control register_1 Internal bus A/D conversion start request signal Control logic Legend: Figure 13.1 Block Diagram of 8-Bit Timer Module

Section 13 8-Bit Timers (TMR) Rev. 1.00 Sep. 19, 2008 Page 799 of 1270 REJ09B0466-0100

13.2 Input/Output Pins

Table 13.1 shows the pin configuration of the 8-bit timer module. Table 13.1 Pin Configuration Channel Name Sy mbol I/O Function

0 Timer output pin TMO0 Output Outputs at compare match

Timer clock input pin TMCI0 Input Inputs external clock for counter Timer reset input pin TMRI0 Input Inputs external reset to counter

1 Timer output pin TMO1 Output Outputs at compare match

Timer clock input pin TMCI1 Input Inputs external clock for counter Timer reset input pin TMRI1 Input Inputs external reset to counter

13.3 Register Descriptions

The 8-bit timer module has the following registers. For details on the module stop control register, refer to section 24.1.2, Module Stop Control Registers H and L (MSTPCRH, MSTPCRL).

  • Timer counter_0 (TCNT_0)
  • Time constant register A_0 (TCORA_0)
  • Time constant register B_0 (TCORB_0)
  • Timer control register_0 (TCR_0)
  • Timer control/status register_0 (TCSR_0)
  • Timer counter control register_0 (TCCR_0)
  • Timer counter_1 (TCNT_1)
  • Time constant register A_1 (TCORA_1)
  • Time constant register B_1 (TCORB_1)
  • Timer control register_1 (TCR_1)
  • Timer control/status register_1 (TCSR_1)
  • Timer counter control register_1 (TCCR_1)

Section 13 8-Bit Timers (TMR) Rev. 1.00 Sep. 19, 2008 Page 800 of 1270 REJ09B0466-0100

13.3.1 Timer Counter (TCNT)

TCNT is 8-bit up-counter. TCNT_0 and TCNT_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. Bits CKS2 to CKS0 in TCR are used to select a clock. TCNT can be cleared by an external reset input or by a compare match signal A or B. Which signal is to be used for clearing is selected by bits CCLR1 and CCLR0 in TCR. When TCNT overflows from H'FF to H'00, OVF in TCSR is set to 1. TCNT is initialized to H'00.

13.3.2 Time Constant Register A (TCORA)

TCORA is 8-bit readable/writable register. TCORA_0 and TCORA_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. The value in TCORA is continually compared with the value in TCNT. When a match is detected, the corresponding CMFA flag in TCSR is set to 1. Note, however, that comparison is disabled during the T2 state of a TCORA write cycle. The timer output from the TMO pin can be freely controlled by this compare match signal (compare match A) and the settings of bits OS1 and OS0 in TCSR. TCORA is initialized to H'FF.

13.3.3 Time Constant Register B (TCORB)

TCORB is 8-bit readable/writable register. TCORB_0 and TCORB_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. TCORB is continually compared with the value in TCNT. When a match is detected, the corresponding CMFB flag in TCSR is set to 1. Note, however, that comparison is disabled during the T 2 state of a TCOBR write cycle. The timer output from the TMO pin can be freely controlled by this compare match signal (compare match B) and the settings of bits OS3 and OS2 in TCSR. TCORB is initialized to H'FF.

Section 13 8-Bit Timers (TMR) Rev. 1.00 Sep. 19, 2008 Page 801 of 1270 REJ09B0466-0100

13.3.4 Timer Control Register (TCR)

TCR selects the clock source and the time at which TCNT is cleared, and controls interrupts. Bit Bit Name Initial Value R/W Description

7 CMIEB 0 R/W Compare Match Interrupt Enable B

Selects whether CMFB interrupt requests (CMIB) are enabled or disabled when the CMFB flag in TCSR is set to 1. 0: CMFB interrupt requests (CMIB) are disabled 1: CMFB interrupt requests (CMIB) are enabled

6 CMIEA 0 R/W Compare Match Interrupt Enable A

Selects whether CMFA interrupt requests (CMIA) are enabled or disabled when the CMFA flag in TCSR is set to 1. 0: CMFA interrupt requests (CMIA) are disabled 1: CMFA interrupt requests (CMIA) are enabled

5 OVIE 0 R/W Timer Overflow Interrupt Enable

Selects whether OVF interrupt requests (OVI) are enabled or disabled when the OVF flag in TCSR is set to 1. 0: OVF interrupt requests (OVI) are disabled 1: OVF interrupt requests (OVI) are enabled CCLR1 CCLR0 R/W R/W Counter Clear 1 and 0 These bits select the method by which TCNT is cleared, in combination with the TMRIS bit in TCCR. See table 13.2. CKS2 CKS1 CKS0 R/W R/W R/W Clock Select 2 to 0 These bits select the clock input to TCNT and the count condition, in combination with the ICKS1 and ICKS0 bits in TCCR. See table 13.3.

Section 13 8-Bit Timers (TMR) Rev. 1.00 Sep. 19, 2008 Page 802 of 1270 REJ09B0466-0100

13.3.5 Timer Counter Co ntrol Register (TCCR)

TCCR selects the TCNT internal clock source and controls the external reset input. Bit Bit Name Initial Value R/W Description 7 to 4 — All 0 R Reserved These bits are always read as 0 and cannot be modified.

3 TMRIS 0 R/W Timer Reset Input Select

Selects the external reset input, in combination with the CCLR1 and CCLR0 bits in TCR. See table 13.2. 2 — 0 R Reserved This bit is always read as 0 and cannot be modified. ICKS1 ICKS0 R/W R/W Internal Clock Select 1, 0 These bits select the internal clock source, in combination with the CKS2 to CKS0 bits in TCR. See table 13.3. Table 13.2 Reset Input to TCNT and Clearing Condition TCR TCCR Bit 1 CCLR1 Bit 0 CCLR0 Bit 3 TMRIS Description 0 0 0 Clearing is disabled 0 1 0 Clear by compare match A 1 0 0 Clear by compare match B 1 1 0 Clear by rising edge of external reset input 0 0 1 Clear by both rising and falling edges of external reset input 0 1 1 Clear by falling edge of external reset input 1 0 1 Clear by low level of external reset input 1 1 1 Clear by high level of external reset input

Section 13 8-Bit Timers (TMR) Rev. 1.00 Sep. 19, 2008 Page 803 of 1270 REJ09B0466-0100 Table 13.3 Clock Input to TCNT and Count Condition TCR TCCR Channel Bit 2 CKS2 Bit 1 CKS1 Bit 0 CKS0 Bit 1 ICKS1 Bit 0 ICKS0 Description TMR_0 0 0 0   Clock input disabled 0 0 1 0 0 Internal clock, counted at rising edge of φ/8 0 1 Internal clock, counted at rising edge of φ/2 1 0 Internal clock, counted at falling edge of φ/8 1 1 Internal clock, counted at falling edge of φ/2 0 1 0 0 0 Internal clock, counted at rising edge of φ/64 0 1 Internal clock, counted at rising edge of φ/32 1 0 Internal clock, counted at falling edge of φ/64 1 1 Internal clock, counted at falling edge of φ/32 0 1 1 0 0 Internal clock, counted at rising edge of φ/8192 0 1 Internal clock, counted at rising edge of φ/1024 1 0 Internal clock, counted at falling edge of φ/8192 1 1 Internal clock, counted at falling edge of φ/1024 1 0 0   Counted at TCNT_1 overflow signal * TMR_1 0 0 0   Clock input disabled 0 0 1 0 0 Internal clock, counted at rising edge of φ/8 0 1 Internal clock, counted at rising edge of φ/2 1 0 Internal clock, counted at falling edge of φ/8 1 1 Internal clock, counted at falling edge of φ/2 0 1 0 0 0 Internal clock, counted at rising edge of φ/64 0 1 Internal clock, counted at rising edge of φ/32 1 0 Internal clock, counted at falling edge of φ/64 1 1 Internal clock, counted at falling edge of φ/32 0 1 1 0 0 Internal clock, counted at rising edge of φ/8192 0 1 Internal clock, counted at rising edge of φ/1024 1 0 Internal clock, counted at falling edge of φ/8192 1 1 Internal clock, counted at falling edge of φ/1024 1 0 0   Counted at TCNT_0 compare match A *

Section 13 8-Bit Timers (TMR) Rev. 1.00 Sep. 19, 2008 Page 804 of 1270 REJ09B0466-0100 TCR TCCR Channel Bit 2 CKS2 Bit 1 CKS1 Bit 0 CKS0 Bit 1 ICKS1 Bit 0 ICKS0 Description All 1 0 1   External clock, counted at rising edge 1 0   External clock, counted at falling edge 1 1   External clock, counted at both rising and falling edges Note: * If the count input of TMR_0 is the TCNT_1 ov erflow signal and that of TMR_1 is the TCNT_0 compare match signal, no incrementing clock is generated. Do not use this setting.

13.3.6 Timer Control/Status Register (TCSR)

TCSR displays status flags, and controls compare match output.

  • TCSR_0 Bit Bit Name Initial Value R/W Description

7 CMFB 0 R/(W) * Compare Match Flag B

[Setting condition]

  • Set when TCNT matches TCORB [Clearing conditions]
  • Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB
  • When DTC is activated by CMIB interrupt while DISEL bit of MRB in DTC is 0

6 CMFA 0 R/(W) * Compare Match Flag A

[Setting condition]

  • Set when TCNT matches TCORA [Clearing conditions]
  • Cleared by reading CMFA when CMFA = 1, then writing 0 to CMFA
  • When DTC is activated by CMIA interrupt while DISEL bit of MRB in DTC is 0

Section 13 8-Bit Timers (TMR) Rev. 1.00 Sep. 19, 2008 Page 805 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description

5 OVF 0 R/(W) * Timer Overflow Flag

[Setting condition] Set when TCNT overflows from H'FF to H'00 [Clearing condition] Cleared by reading OVF when OVF = 1, then writing 0 to OVF

4 ADTE 0 R/W A/D Trigger Enable

Selects enabling or disabling of A/D converter start requests by compare match A. 0: A/D converter start requests by compare match A are disabled 1: A/D converter start requests by compare match A are enabled OS3 OS2 R/W R/W Output Select 3 and 2 These bits select a method of TMO pin output when compare match B of TCORB and TCNT occurs. 00: No change when compare match B occurs 01: 0 is output when compare match B occurs 10: 1 is output when compare match B occurs 11: Output is inverted when compare match B occurs (toggle output) OS1 OS0 R/W R/W Output Select 1 and 0 These bits select a method of TMO pin output when compare match A of TCORA and TCNT occurs. 00: No change when compare match A occurs 01: 0 is output when compare match A occurs 10: 1 is output when compare match A occurs 11: Output is inverted when compare match A occurs (toggle output) Note: Only 0 can be written to, to clear these flags.

Section 13 8-Bit Timers (TMR) Rev. 1.00 Sep. 19, 2008 Page 806 of 1270 REJ09B0466-0100

  • TCSR_1 Bit Bit Name Initial Value R/W Description

[Setting condition]

  • Set when TCNT matches TCORB [Clearing conditions]
  • Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB
  • When DTC is activated by CMIB interrupt while DISEL bit of MRB in DTC is 0

[Setting condition]

  • Set when TCNT matches TCORA [Clearing conditions]
  • Cleared by reading CMFA when CMFA = 1, then writing 0 to CMFA
  • When DTC is activated by CMIA interrupt while DISEL bit of MRB in DTC is 0

[Setting condition]

  • Set when TCNT overflows from H'FF to H'00 [Clearing condition]
  • Cleared by reading OVF when OVF = 1, then writing 0 to OVF 4 — 1 R Reserved This bit is always read as 1 and cannot be modified.

Section 13 8-Bit Timers (TMR) Rev. 1.00 Sep. 19, 2008 Page 807 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description OS3 OS2 R/W R/W Output Select 3 and 2 These bits select a method of TMO pin output when compare match B of TCORB and TCNT occurs. 00: No change when compare match B occurs 01: 0 is output when compare match B occurs 10: 1 is output when compare match B occurs 11: Output is inverted when compare match B occurs (toggle output) OS1 OS0 R/W R/W Output Select 1 and 0 These bits select a method of TMO pin output when compare match A of TCORA and TCNT occurs. 00: No change when compare match A occurs 01: 0 is output when compare match A occurs 10: 1 is output when compare match A occurs 11: Output is inverted when compare match A occurs (toggle output) Note: * Only 0 can be written to, to clear these flags.

Section 13 8-Bit Timers (TMR) Rev. 1.00 Sep. 19, 2008 Page 808 of 1270 REJ09B0466-0100

13.4 Operation

13.4.1 Pulse Output

Figure 13.2 shows an example in which the 8-bit timer is used to generate a pulse output with a selected duty cycle. The control bits are set as follows: [1] In TCR, the CCLR1 bit is cleared to 0 and the CCLR0 bit is set to 1 so that TCNT is cleared at a TCORA compare match. [2] In TCSR, the OS3 to OS0 bits are set to B'0110, causing the output to change to 1 at a TCORA compare match and to 0 at a TCORB compare match. With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with a pulse width determined by TCORB. No software intervention is required. TCNT H'FF Counter clear TCORA TCORB H'00 TMO Figure 13.2 Example of Pulse Output

Section 13 8-Bit Timers (TMR) Rev. 1.00 Sep. 19, 2008 Page 809 of 1270 REJ09B0466-0100

13.4.2 Reset Input

Figure 13.3 shows an example in which the 8-bit timer is used to generate a pulse output with a selected delay in response to the TMRI input. The control bits are set as follows: [1] The CCLR0 bit in TCR is set to 1 and the TMRIS bit in TCCR is set to 1 so that TCNT is cleared at the high level of the TMRI input. [2] In TCSR, bits OS3 to OS0 are set to B'0110, causing the output to change to 1 at a TCORA compare match and to 0 at a TCORB compare match. With these settings, the 8-bit timer provides output of pulses whose delay from the TMRI input is determined by TCORA and the pulse width determined by (TCORB − TCORA). TCORB TCORA H'00 TMRI TMO TCNT Figure 13.3 Example of Reset Input

Section 13 8-Bit Timers (TMR) Rev. 1.00 Sep. 19, 2008 Page 810 of 1270 REJ09B0466-0100

13.5 Operation Timing

13.5.1 TCNT Incrementation Timing

Figure 13.4 shows the count timing for internal clock input. Figure 13.5 shows the count timing for external clock signal. Note that the external clock pulse width must be at least 1.5 states for incrementation at a single edge, and at least 2.5 states for incrementation at both edges. The counter will not increment correctly if the pulse width is less than these values. Internal clock φ Clock input to TCNT TCNT N – 1 N N + 1 Figure 13.4 Count Timing for Internal Clock Input External clock input pin φ Clock input to TCNT TCNT N – 1 N N + 1 Figure 13.5 Count Timing for External Clock Input

Section 13 8-Bit Timers (TMR) Rev. 1.00 Sep. 19, 2008 Page 811 of 1270 REJ09B0466-0100

13.5.2 Timing of CMFA and CMFB Setting when Compare-Match Occurs

The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the TCOR and TCNT values match. The compare match signal is generated at the last state in which the match is true, just before the timer counter is updated. Therefore, when TCOR and TCNT match, the compare match signal is not generated until the next incrementation clock input. Figure 13.6 shows this timing. TCNT φ N N + 1 TCOR N Compare match signal CMF Figure 13.6 Timing of CMF Setting

Section 13 8-Bit Timers (TMR) Rev. 1.00 Sep. 19, 2008 Page 812 of 1270 REJ09B0466-0100

13.5.3 Timing of Timer Output when Compare-Match Occurs

When compare match A or B occurs, the timer output changes as specified by bits OS3 to OS0 in TCSR. Figure 13.7 shows the timing when the output is set to toggle at compare match A. Compare match A signal φ Timer output pin Figure 13.7 Timing of Timer Output

13.5.4 Timing of Compare Match Clear

TCNT is cleared when compare match A or B occurs, depending on the settings of the CCLR1 and CCLR0 bits in TCR and the TMRIS bit in TCCR. Figure 13.8 shows the timing of this operation. N H'00 Compare match signal φ TCNT Figure 13.8 Timing of Compare Match Clear

Section 13 8-Bit Timers (TMR) Rev. 1.00 Sep. 19, 2008 Page 813 of 1270 REJ09B0466-0100

13.5.5 Timing of TC NT External Reset

TCNT is cleared at the rising edge, falling edge, low level, or high level of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR and the TMRIS bit in TCCR. The clear pulse width must be at least 1.5 states for a single edge and at least 2.5 states for both edges. Figure 13.9 shows the timing of this operation. Clear signal External reset input pin φ TCNT N H'00N – 1 Figure 13.9 Timing of Clearance by External Reset

13.5.6 Timing of Overflow Flag (OVF) Setting

The OVF in TCSR is set to 1 when TCNT overflows (changes from H'FF to H'00). Figure 13.10 shows the timing of this operation. OVF Overflow signal TCNT φ H'FF H'00 Figure 13.10 Timing of OVF Setting

Section 13 8-Bit Timers (TMR) Rev. 1.00 Sep. 19, 2008 Page 814 of 1270 REJ09B0466-0100

13.6 Operation with Cascaded Connection

If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit counter mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1 (compare match count mode). In this case, the timer operates as below. 13.6.1 16-Bit Counter Mode When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. [1] Setting of compare match flags

  • The CMF flag in TCSR_0 is set to 1 when a 16-bit compare match event occurs.
  • The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare match event occurs. [2] Counter clear specification
  • If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare match, the 16-bit counters (TCNT_0 and TCNT_1 together) are cleared when a 16-bit compare match event occurs. The 16-bit counters (TCNT0 and TCNT1 together) are cleared even if counter clear by the TMRI0 pin has also been set.
  • The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot be cleared independently. [3] Pin output
  • Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR_0 is in accordance with the 16-bit compare match conditions.
  • Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR_1 is in accordance with the lower 8-bit compare match conditions.

13.6.2 Compare Match Count Mode

When bits CKS2 to CKS0 in TCR_1 are B'100, TCNT_1 counts compare match A’s for channel 0. Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag, generation of interrupts, output from the TMO pin, and counter clear are in accordance with the settings for each channel.

Section 13 8-Bit Timers (TMR) Rev. 1.00 Sep. 19, 2008 Page 815 of 1270 REJ09B0466-0100

13.7 Interrupt Sources

13.7.1 Interrupt Sources and DTC Activation

There are three 8-bit timer interrupt sources: CMIA, CMIB, and OVI. Their relative priorities are shown in table 13.4. Each interrupt source is set as enabled or disabled by the corresponding interrupt enable bit in TCR or TCSR, and independent interrupt requests are sent for each to the interrupt controller. It is also possible to activate the DTC by means of CMIA and CMIB interrupts. Table 13.4 8-Bit Timer Interrupt Sources Name Interrupt Source Interrupt Flag DTC Activation Priority CMIA0 TCORA_0 compare match CMFA Possible High CMIB0 TCORB_0 compare match CMFB Possible OVI0 TCNT_0 overflow OVF Not possible Low CMIA1 TCORA_1 compare match CMFA Possible High CMIB1 TCORB_1 compare match CMFB Possible OVI1 TCNT_1 overflow OVF Not possible Low

13.7.2 A/D Converter Activation

The A/D converter can be activated only by TMR_0 compare match A. If the ADTE bit in TCSR0 is set to 1 when the CMFA flag is set to 1 by the occurrence of TMR_0 compare match A, a request to start A/D conversion is sent to the A/D converter. If the 8-bit timer conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started.

Section 13 8-Bit Timers (TMR) Rev. 1.00 Sep. 19, 2008 Page 816 of 1270 REJ09B0466-0100

13.8 Usage Notes

13.8.1 Contention between TCNT Write and Clear

If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. Figure 13.11 shows this operation. Address φ TCNT address Internal write signal Counter clear signal TCNT N H'00 T1 T2 TCNT write cycle by CPU Figure 13.11 Contention between TCNT Write and Clear

Section 13 8-Bit Timers (TMR) Rev. 1.00 Sep. 19, 2008 Page 817 of 1270 REJ09B0466-0100

13.8.2 Contention between TCNT Write and Increment

If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the counter is not incremented. Figure 13.12 shows this operation. Address φ TCNT address Internal write signal TCNT input clock TCNT N M T1 T2 TCNT write cycle by CPU Counter write data Figure 13.12 Contention between TCNT Write and Increment

Section 13 8-Bit Timers (TMR) Rev. 1.00 Sep. 19, 2008 Page 818 of 1270 REJ09B0466-0100

13.8.3 Contention between TC OR Write and Compare Match

During the T2 state of a TCOR write cycle, the TCOR write has priority and the compare match signal is inhibited even if a compare match event occurs as shown in figure 13.13. Address φ TCOR address Internal write signal TCNT TCOR N M T1 T2 TCOR write cycle by CPU TCOR write data N N + 1 Compare match signal Inhibited Figure 13.13 Contention between TCOR Write and Compare Match

Section 13 8-Bit Timers (TMR) Rev. 1.00 Sep. 19, 2008 Page 819 of 1270 REJ09B0466-0100

13.8.4 Contention between Compare Matches A and B

If compare match events A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output statuses set for compare match A and compare match B, as shown in table 13.5. Table 13.5 Timer Output Priorities Output Setting Priority Toggle output High 1 output 0 output No change Low

13.8.5 Switching of Internal Clocks and TCNT Operation

TCNT may increment erroneously when the internal clock is switched over. Table 13.6 shows the relationship between the timing at which the internal clock is switched (by writing to the CKS1, CKS0, ICKS1, and ICKS0 bits) and the TCNT operation. When the TCNT clock is generated from an internal clock, the rising edge or falling edge of the internal clock pulse is detected. Therefore, when the falling edge is selected, if clock switching causes a change from high to low level, as shown in case 3 in table 13.6, a TCNT clock pulse is generated and the TCNT incremented on the assumption that the switchover is a falling edge. This is the same as when the rising edge is selected. The erroneous incrementation can also happen when switching between the rising edge and falling edge of an internal clock or switching between internal and external clocks.

Section 13 8-Bit Timers (TMR) Rev. 1.00 Sep. 19, 2008 Page 820 of 1270 REJ09B0466-0100 Table 13.6 Switching of Internal Clock and TCNT Operation No. Timing of Switchover by Means of Modifying CKS1, CKS0, ICKS1, and ICKS0 Bits TCNT Clock Operation

1 Switching from

low to low* Clock before switchover Clock after switchover TCNT clock TCNT CKS bit write N N + 1

2 Switching from

low to high*2 Clock before switchover Clock after switchover TCNT clock TCNT CKS bit write N N + 1 N + 2

3 Switching from

high to low*3 Clock before swichover Clock after swichover TCNT clock TCNT CKS bit write N N + 1 N + 2

Section 13 8-Bit Timers (TMR) Rev. 1.00 Sep. 19, 2008 Page 821 of 1270 REJ09B0466-0100 No. Timing of Switchover by Means of Modifying CKS1, CKS0, ICKS1, and ICKS0 Bits TCNT Clock Operation

4 Switching from high

Notes: 1. Includes switching from low to stop, and from stop to low. 2. Includes switching from stop to high. 3. Includes switching from high to stop. 4. Generated on the assump tion that the switchover is a falling edge; TCNT is incremented.

13.8.6 Mode Setting with Cascaded Connection

If 16-bit counter mode and compare match count mode are specified at the same time, input clocks for TCNT_0 and TCNT_1 are not generated, and the counter stops. Do not specify 16-bit counter and compare match count modes simultaneously.

13.8.7 Module Stop Mode Setting

Operation of the TMR can be disabled or enabled using the module stop control register. The initial setting is for operation of the TMR to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 24, Power-Down Modes.

13.8.8 Interrupts in Module Stop Mode

If module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DTC and DMAC activation source. Interrupts should therefore be disabled before entering module stop mode.

Section 13 8-Bit Timers (TMR) Rev. 1.00 Sep. 19, 2008 Page 822 of 1270 REJ09B0466-0100

Section 14 Watchdog Timer (WDT) Rev. 1.00 Sep. 19, 2008 Page 823 of 1270 REJ09B0466-0100 Section 14 Watchdog Timer (WDT) The watchdog timer (WDT) is an 8-bit timer that outputs an overflow signal (WDTOVF) if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. At the same time, the WDT can also generate an internal reset signal. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows. The block diagram of the WDT is shown in figure 14.1.

14.1 Features

  • Selectable from eight counter input clocks
  • Switchable between watchdog timer mode and interval timer mode Watchdog Timer Mode
  • If the counter overflows, the WDT outputs WDTOVF. It is possible to select whether or not the entire chip is reset at the same time. Interval Timer Mode
  • If the counter overflows, the WDT generates an interval timer interrupt (WOVI).

Section 14 Watchdog Timer (WDT) Rev. 1.00 Sep. 19, 2008 Page 824 of 1270 REJ09B0466-0100 Overflow Interrupt controlWOVI (interrupt request signal) Internal reset signal* WDTOVF Reset control RSTCSR TCNT TSCR φ/2 φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768 φ/131072 Clock Clock select Internal clock sources Bus interfaceModule bus TCSR TCNT RSTCSR Note: * An internal reset signal can be generated by the register setting. : Timer control/status register : Timer counter : Reset control/status register WDT Legend: Internal bus Figure 14.1 Block Diagram of WDT

14.2 Input/Output Pin

Table 14.1 shows the WDT pin configuration. Table 14.1 Pin Configuration Name Symbol I/O Function Watchdog timer overflow WDTOVF Output Outputs counter overflow signal in watchdog timer mode

Section 14 Watchdog Timer (WDT) Rev. 1.00 Sep. 19, 2008 Page 825 of 1270 REJ09B0466-0100

14.3 Register Descriptions

The WDT has the following three registers. To prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to in a method different from normal registers. For details, refer to section 14.6.1, Notes on Register Access.

  • Timer counter (TCNT)
  • Timer control/status register (TCSR)
  • Reset control/status register (RSTCSR)

14.3.1 Timer Counter (TCNT)

TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in TCSR is cleared to 0.

14.3.2 Timer Control/Status Register (TCSR)

TCSR selects the clock source to be input to TCNT, and the timer mode. Bit Bit Name Initial Value R/W Description

7 OVF 0 R/(W) * Overflow Flag

Indicates that TCNT has overflowed in interval timer mode. Only a write of 0 is permitted, to clear the flag. [Setting condition] When TCNT overflows in interval timer mode (changes from H'FF to H '00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. [Clearing conditions] Cleared by reading TCSR when OVF = 1, then writing 0 to OVF

Section 14 Watchdog Timer (WDT) Rev. 1.00 Sep. 19, 2008 Page 826 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description

6 WT/ IT 0 R/W Timer Mode Select

Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode When TCNT overflows, an interval timer interrupt (WOVI) is requested. 1: Watchdog timer mode When TCNT overflows, the WDTOVF signal is output.

5 TME 0 R/W Timer Enable

When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00. 4, 3 — All 1 — Reserved These bits are always read as 1 and cannot be modified. CKS2 CKS1 CKS0 R/W R/W R/W Clock Select 2 to 0 Selects the clock source to be input to TCNT. The overflow frequency for φ = 20 MHz is enclosed in parentheses. 000: Clock φ/2 (frequency: 25.6 µs) 001: Clock φ/64 (frequency: 819.2 µs) 010: Clock φ/128 (frequency: 1.6 ms) 011: Clock φ/512 (frequency: 6.6 ms) 100: Clock φ/2048 (frequency: 26.2 ms) 101: Clock φ/8192 (frequency: 104.9 ms) 110: Clock φ/32768 (frequency: 419.4 ms) 111: Clock φ/131072 (frequency: 1.68 s) Note: * Only a write of 0 is permitted, to clear the flag.

Section 14 Watchdog Timer (WDT) Rev. 1.00 Sep. 19, 2008 Page 827 of 1270 REJ09B0466-0100

14.3.3 Reset Control/Status Register (RSTCSR)

RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal reset signal caused by overflows. Bit Bit Name Initial Value R/W Description

7 WOVF 0 R/(W) * Watchdog Timer Overflow Flag

This bit is set when TCNT overflows in watchdog timer mode. This bit cannot be set in interval timer mode, and only 0 can be written. [Setting condition] Set when TCNT overflows (changed from H'FF to H'00) in watchdog timer mode [Clearing condition] Cleared by reading RSTCSR when WOVF = 1, and then writing 0 to WOVF

6 RSTE 0 R/W Reset Enable

Specifies whether or not a reset signal is generated in the chip if TCNT overflows during watchdog timer operation. 0: Reset signal is not generated even if TCNT overflows (Though this LSI is not reset, TCNT and TCSR in WDT are reset) 1: Reset signal is generated if TCNT overflows 5 — 0 R/W Reserved Can be read and written, but does not affect operation. 4 to 0 — All 1 — Reserved These bits are always read as 1 and cannot be modified. Note: * Only a write of 0 is permitted, to clear the flag.

Section 14 Watchdog Timer (WDT) Rev. 1.00 Sep. 19, 2008 Page 828 of 1270 REJ09B0466-0100

14.4 Operation

14.4.1 Watchdog Timer Mode

To use the WDT as a watchdog timer mode, set the WT/IT and TME bits in TCSR to 1. If TCNT overflows without being rewritten because of a system crash or other error, the WDTOVF signal is output. This ensures that TCNT does not overflow while the system is operating normally. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflow occurs. This WDTOVF signal can be used to reset the chip internally in watchdog timer mode. If TCNT overflows when 1 is set in the RSTE bit in RSTCSR, a signal that resets this LSI internally is generated at the same time as the WDTOVF signal. If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT overflow, the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0. The WDTOVF signal is output for 132 states when RSTE = 1, and for 130 states when RSTE = 0. The internal reset signal is output for 518 states. When TCNT overflows in watchdog timer mode, the WOVF bit in RSTCSR is set to 1. If TCNT overflows when 1 is set in the RSTE bit in RSTCSR, an internal reset signal is generated to the entire chip.

Section 14 Watchdog Timer (WDT) Rev. 1.00 Sep. 19, 2008 Page 829 of 1270 REJ09B0466-0100 TCNT count H'00 Time H'FF WT/IT=1 TME=1 H'00 written to TCNT WT/IT=1 TME=1 H'00 written to TCNT 132 states*2 518 states WDTOVF signal Internal reset signal*1 Notes: 1. If TCNT overflows when the RSTE bit is set to 1, an internal reset signal is generated. 2. 130 states when the RSTE bit is cleared to 0. Overflow WDTOVF and internal reset are generated WOVF=1 Figure 14.2 Operation in Watchdog Timer Mode

14.4.2 Interval Timer Mode

To use the WDT as an interval timer, set the WT/IT bit to 0 and TME bit in TCSR to 1. When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time the TCNT overflows. Therefore, an interrupt can be generated at intervals. When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested at the same time the OVF bit in the TCSR is set to 1.

Section 14 Watchdog Timer (WDT) Rev. 1.00 Sep. 19, 2008 Page 830 of 1270 REJ09B0466-0100 TCNT count H'00 Time H'FF WT/IT=0 TME=1 WOVI Overflow Overflow Overflow Overflow Legend: WOVI: Interval timer interrupt request generation WOVI WOVI WOVI Figure 14.3 Operation in Interval Timer Mode

Section 14 Watchdog Timer (WDT) Rev. 1.00 Sep. 19, 2008 Page 831 of 1270 REJ09B0466-0100

14.5 Interrupt Source

During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. Table 14.2 WDT Interrupt Source Name Interrupt Source Interrupt Flag DTC Activation WOVI TCNT overflow OVF Impossible

14.6 Usage Notes

14.6.1 Notes on Register Access

The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. (1) Writing to TCNT, TCSR, and RSTCSR TCNT and TCSR must be written to by a word transfer instruction. They cannot be written to by a byte transfer instruction. TCNT and TCSR both have the same write address. Therefore, satisfy the relative condition shown in figure 14.4 to write to TCNT or TCSR. The transfer instruction writes the lower byte data to TCNT or TCSR according to the satisfied condition. To write to RSTCSR, execute a word transfer instruction for address H'FFBE. A byte transfer instruction cannot perform writing to RSTCSR. The method of writing 0 to the WOVF bit differs from that of writing to the RSTE bit. To write 0 to the WOVF bit, satisfy the lower condition shown in figure 14.4. If satisfied, the transfer instruction clears the WOVF bit to 0, but has no effect on the RSTE bit. To write to the RSTE bit, satisfy the above condition shown in figure 14.4. If satisfied, the transfer instruction writes the value in bit 6 of the lower byte into the RSTE bit, but has no effect on the WOVF bit.

Section 14 Watchdog Timer (WDT) Rev. 1.00 Sep. 19, 2008 Page 832 of 1270 REJ09B0466-0100 TCNT write or Writing to RSTE bit in RSTCSR TCSR write Address: H'FFBC (TCNT) H'FFBE (RSTCSR) 15 8 7 0 H'5A Write data Address: H'FFBC (TCSR) 15 8 7 0 H'A5 Write data Writing 0 to WOVF bit in RSTCSR Address: H'FFBE (RSTCSR) 15 8 7 0 H'A5 H'00 Writing to RSTE bit in RSTCSR Address: H'FFBE (RSTCSR) 15 8 7 0 H'5A Write data Figure 14.4 Writing to TCNT, TCSR, and RSTCSR (2) Reading TCNT, TCSR, and RSTCSR These registers are read in the same way as other registers. The read addresses are H'FFBC for TCSR, H'FFBD for TCNT, and H'FFBF for RSTCSR.

Section 14 Watchdog Timer (WDT) Rev. 1.00 Sep. 19, 2008 Page 833 of 1270 REJ09B0466-0100

14.6.2 Contention between Timer Counter (TCNT) Write and Increment

If a timer counter clock pulse is generated during the next cycle after the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 14.5 shows this operation. Address φ Internal write signal TCNT input clock TCNT N M T1 T2 Next cycle TCNT write cycle Counter write data Figure 14.5 Contention between TCNT Write and Increment

14.6.3 Changing Valu e of CKS2 to CKS0

If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the value of bits CKS2 to CKS0.

14.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode

If the mode is switched from watchdog timer to interval timer, while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before switching the mode.

Section 14 Watchdog Timer (WDT) Rev. 1.00 Sep. 19, 2008 Page 834 of 1270 REJ09B0466-0100

14.6.5 Internal Reset in Watchdog Timer Mode

This LSI is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during watchdog timer mode operation, but TCNT and TCSR of the WDT are reset. TCNT, TCSR, and RSTCR cannot be written to while the WDTOVF signal is low. Also note that a read of the WOVF flag is not recognized during this period. To clear the WOVF flag, therefore, read TCSR after the WDTOVF signal goes high, then write 0 to the WOVF flag.

14.6.6 System Reset by WDTOVF Signal

If the WDTOVF output signal is input to the RES pin, the chip will not be initialized correctly. Make sure that the WDTOVF signal is not input logically to the RES pin. To reset the entire system by means of the WDTOVF signal, use the circuit shown in figure 14.6. Reset input Reset signal to entire system This LSI RES WDTOVF Figure 14.6 Circuit for System Reset by WDTOVF Signal (Example)

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 835 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) This LSI has five independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function) in asynchronous mode. The SCI also supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as an asynchronous serial communication interface extension function. One of the five SCI channels (SCI_0) can generate an IrDA communication waveform conforming to IrDA specification version 1.0. Figure 15.1 shows a block diagram of the SCI.

15.1 Features

  • Choice of asynchronous or clocked synchronous serial communication mode
  • Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data.
  • On-chip baud rate generator allows any bit rate to be selected External clock can be selected as a transfer clock source (except for in Smart Card interface mode).
  • Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data)
  • Four interrupt sources Four interrupt sources  transmit-end, transmit-data-empty, receive-data-full, and receive error  that can issue requests. The transmit-data-empty interrupt and receive data full interrupts can activate the data transfer controller (DTC) or DMA controller (DMAC).
  • Module stop mode can be set

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 836 of 1270 REJ09B0466-0100 Asynchronous Mode

  • Data length: 7 or 8 bits
  • Stop bit length: 1 or 2 bits
  • Parity: Even, odd, or none
  • Receive error detection: Parity, overrun, and framing errors
  • Break detection: Break can be detected by reading the RxD pin level directly in case of a framing error
  • Average transfer rate generator (SCI_2 only): 115.152 or 460.606 kbps at 10.667-MHz operation 115.196, 460.784, or 720 kbps at 16-MHz operation 720 kbps at 32-MHz operation Clocked Synchronous Mode
  • Data length: 8 bits
  • Receive error detection: Overrun errors detected Smart Card Interface
  • Automatic transmission of error signal (parity error) in receive mode
  • Error signal detection and automatic data retransmission in transmit mode
  • Direct convention and inverse convention both supported

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 837 of 1270 REJ09B0466-0100 RxD TxD SCK Clock External clock φ φ/4 φ/16 φ/64 TEI TXI RXI ERI SCMR SSR SCR SMR SEMR Transmission/ reception control Baud rate generator BRR Module data bus RDR TSRRSR Parity generation Parity check TDR Bus interface Internal data bus Average transfer rate generator (SCI_2)

10.667 MHz operation

 115.152 kbps  460.606 kbps

16 MHz operation

 115.196 kbps  460.784 kbps  720 kbps

32 MHz operation

 720 kbps Legend: RSR : Receive shift register RDR : Receive data register TSR : Transmit shift register TDR : Transmit data register SMR : Serial mode register SCR : Serial control register SSR : Serial status register SCMR : Smart card mode register BRR : Bit rate register SEMR : Serial extension mode register (only in SCI_2) Figure 15.1 Block Diagram of SCI

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 838 of 1270 REJ09B0466-0100

15.2 Input/Output Pins

Table 15.1 shows the pin configuration of the serial communication interface. Table 15.1 Pin Configuration Channel Pin Name * I/O Function SCK0 I/O Channel 0 clock input/output RxD0/IrRxD Input Channel 0 rece ive data input (normal/IrDA) TxD0/IrTxD Output Channel 0 transmit data output (normal/IrDA) SCK1 I/O Channel 1 clock input/output RxD1 Input Channel 1 receive data input TxD1 Output Channel 1 transmit data output SCK2 I/O Channel 2 clock input/output RxD2 Input Channel 2 receive data input TxD2 Output Channel 2 transmit data output SCK3 I/O Channel 3 clock input/output RxD3 Input Channel 3 receive data input TxD3 Output Channel 3 transmit data output SCK4 I/O Channel 4 clock input/output RxD4 Input Channel 4 receive data input TxD4 Output Channel 4 transmit data output Note: * Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the channel designation.

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 839 of 1270 REJ09B0466-0100

15.3 Register Descriptions

The SCI has the following registers. The serial mode register (SMR), serial status register (SSR), and serial control register (SCR) are described separately for normal serial communication interface mode and Smart Card interface mode because their bit functions partially differ.

  • Receive shift register_0 (RSR_0)
  • Transmit shift register_0 (TSR_0)
  • Receive data register_0 (RDR_0)
  • Transmit data register_0 (TDR_0)
  • Serial mode register_0 (SMR_0)
  • Serial control register_0 (SCR_0)
  • Serial status register_0 (SSR_0)
  • Smart card mode register_0 (SCMR_0)
  • Bit rate register_0 (BRR_0)
  • IrDA control register_0 (IrCR_0)
  • Receive shift register_1 (RSR_1)
  • Transmit shift register_1 (TSR_1)
  • Receive data register_1 (RDR_1)
  • Transmit data register_1 (TDR_1)
  • Serial mode register_1 (SMR_1)
  • Serial control register_1 (SCR_1)
  • Serial status register_1 (SSR_1)
  • Smart card mode register_1 (SCMR_1)
  • Bit rate register_1 (BRR_1)
  • Receive shift register_2 (RSR_2)
  • Transmit shift register_2 (TSR_2)
  • Receive data register_2 (RDR_2)
  • Transmit data register_2 (TDR_2)
  • Serial mode register_2 (SMR_2)
  • Serial control register_2 (SCR_2)
  • Serial status register_2 (SSR_2)
  • Smart card mode register_2 (SCMR_2)
  • Bit rate register_2 (BRR_2)
  • Serial extension mode register_2 (SEMR_2)

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 840 of 1270 REJ09B0466-0100

  • Receive shift register_3 (RSR_3)
  • Transmit shift register_3 (TSR_3)
  • Receive data register_3 (RDR_3)
  • Transmit data register_3 (TDR_3)
  • Serial mode register_3 (SMR_3)
  • Serial control register_3 (SCR_3)
  • Serial status register_3 (SSR_3)
  • Smart card mode register_3 (SCMR_3)
  • Bit rate register_3 (BRR_3)
  • Receive shift register_4 (RSR_4)
  • Transmit shift register_4 (TSR_4)
  • Receive data register_4 (RDR_4)
  • Transmit data register_4 (TDR_4)
  • Serial mode register_4 (SMR_4)
  • Serial control register_4 (SCR_4)
  • Serial status register_4 (SSR_4)
  • Smart card mode register_4 (SCMR_4)
  • Bit rate register_4 (BRR_4)

15.3.1 Receive Shift Register (RSR)

RSR is a shift register used to receive serial data that is input to the RxD pin and convert it into parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU.

15.3.2 Receive Data Register (RDR)

RDR is an 8-bit register that stores receive data. When the SCI has received one byte of serial data, it transfers the received serial data from RSR to RDR where it is stored. After this, RSR is receive-enabled. Since RSR and RDR function as a double buffer in this way, enables continuous receive operations to be performed. After confirming that the RDRF bit in SSR is set to 1, read RDR for only once. RDR cannot be written to by the CPU.

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 841 of 1270 REJ09B0466-0100

15.3.3 Transmit Data Register (TDR)

TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered structures of TDR and TSR enable continuous serial transmission. If the next transmit data has already been written to TDR during serial transmission, the SCI transfers the written data to TSR to continue transmission. Although TDR can be read or written to by the CPU at all times, to achieve reliable serial transmission, write transmit data to TDR for only once after confirming that the TDRE bit in SSR is set to 1.

15.3.4 Transmit Shift Register (TSR)

TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin starting. TSR cannot be directly accessed by the CPU.

15.3.5 Serial Mode Register (SMR)

SMR is used to set the SCI’s serial transfer format and select the on-chip baud rate generator clock source. Some bit functions of SMR differ in normal serial communication interface mode and Smart Card interface mode. Normal Serial Communication Interface Mode (When SMIF bit in SCMR is 0) Bit Bit Name Initial Value R/W Description

7 C/ A 0 R/W Communication Mode

0: Asynchronous mode 1: Clocked synchronous mode

6 CHR 0 R/W Character Length (enabled only in asynchronous

mode) 0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length. LSB-first is fixed and the MSB (bit 7) of TDR is not transmitted in transmission. In clocked synchronous mode, a fixed data length of 8 bits is used.

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 842 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description

5 PE 0 R/W Parity Enable (enabled only in asynchronous

mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. For a multiprocessor format, parity bit addition and checking are not performed regardless of the PE bit setting.

4 O/ E 0 R/W Parity Mode (enabled only when the PE bit is 1 in

asynchronous mode) 0: Selects even parity. 1: Selects odd parity.

3 STOP 0 R/W Stop Bit Length (enabled only in asynchronous

mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits In reception, only the first stop bit is checked regardless of the STOP bit setting. If the second stop bit is 0, it is treated as the start bit of the next transmit character.

2 MP 0 R/W Multiprocessor Mode (enabled only in

asynchronous mode) When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit and O/E bit settings are invalid in multiprocessor mode. CKS1 CKS0 R/W R/W Clock Select 1 and 0 These bits select the clock source for the on-chip baud rate generator. 00: φ clock (n = 0) 01: φ/4 clock (n = 1) 10: φ/16 clock (n = 2) 11: φ/64 clock (n = 3) For the relation between the bit rate register setting and the baud rate, see section 15.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR (see section 15.3.9, Bit Rate Register (BRR)).

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 843 of 1270 REJ09B0466-0100 Smart Card Interface Mode (When SMIF bit in SCMR is 1) Bit Bit Name Initial Value R/W Description

7 GM 0 R/W GSM Mode

When this bit is set to 1, the SCI operates in GSM mode. In GSM mode, the timing of the TEND setting is advanced by 11.0 etu (Elementary Time Unit: the time for transfer of 1 bit), and clock output control mode addition is performed. For details, refer to section 15.7.8, Clock Output Control.

6 BLK 0 R/W When this bit is set to 1, the SCI operates in block

transfer mode. For details on block transfer mode, refer to section 15.7.3, Block Transfer Mode. mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. In Smart Card interface mode, this bit must be set to 1. asynchronous mode) 0: Selects even parity. 1: Selects odd parity. For details on setting this bit in Smart Card interface mode, refer to section 15.7.2, Data Format (Except for Block Transfer Mode).

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 844 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description BCP1 BCP0 R/W R/W Basic Clock Pulse 1 and 0 These bits, in combination with the BCP2 bit in SCMR, select the number of basic clock cycles in a 1-bit transfer interval in Smart Card interface mode. BCP2 to BCP0 Settings: 000: 93 clock cycles (S = 93) 001: 128 clock cycles (S = 128) 010: 186 clock cycles (S = 186) 011: 512 clock cycles (S = 512) 100: 32 clock cycles (S = 32) (initial value) 101: 64 clock cycles (S = 64) 110: 372 clock cycles (S = 372) 111: 256 clock cycles (S = 256) For details, refer to section 15.7.4, Receive Data Sampling Timing and Reception Margin. S stands for the value of S in BRR (see section 15.3.9, Bit Rate Register (BRR)). CKS1 CKS0 R/W R/W Clock Select 1 and 0 These bits select the clock source for the on-chip baud rate generator. 00: φ clock (n = 0) 01: φ/4 clock (n = 1) 10: φ/16 clock (n = 2) 11: φ/64 clock (n = 3) For the relation between the bit rate register setting and the baud rate, see section 15.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR (see section 15.3.9, Bit Rate Register (BRR)).

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 845 of 1270 REJ09B0466-0100

15.3.6 Serial Control Register (SCR)

SCR performs enabling or disabling of SCI transfer operations and interrupt requests, and selection of the transfer/receive clock source. For details on interrupt requests, refer to section 15.9, Interrupt Sources. Some bit functions of SCR differ in normal serial communication interface mode and Smart Card interface mode. Normal Serial Communication Interface Mode (When SMIF bit in SCMR is 0) Bit Bit Name Initial Value R/W Description

7 TIE 0 R/W Transmit Interrupt Enable

When this bit is set to 1, TXI interrupt request is enabled. TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0, or clearing the TIE bit to 0.

6 RIE 0 R/W Receive Interrupt Enable

When this bit is set to 1, RXI and ERI interrupt requests are enabled. RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or by clearing the RIE bit to 0.

5 TE 0 R/W Transmit Enable

When this bit s set to 1, transmission is enabled. In this state, serial transmission is started when transmit data is written to TDR and the TDRE flag in SSR is cleared to 0. SMR setting must be performed to decide the transfer format before setting the TE bit to 1. The TDRE flag in SSR is fixed at 1 if transmission is disabled by clearing this bit to 0.

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 846 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description

4 RE 0 R/W Receive Enable

When this bit is set to 1, reception is enabled. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in clocked synchronous mode. SMR setting must be performed to decide the transfer format before setting the RE bit to 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states.

3 MPIE 0 R/W Multiprocessor Interrupt Enable (enabled only

when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is prohibited. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. For details, refer to section 15.5, Multiprocessor Communication Function. When receive data including MPB = 0 in SSR is received, receive data transfer from RSR to RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR , is not performed. When receive data including MPB = 1 is received, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is enabled.

2 TEIE 0 R/W Transmit End Interrupt Enable

When this bit is set to 1, TEI interrupt request is enabled. TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0 and clearing the TEND flag to 0, or by clearing the TEIE bit to 0.

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 847 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description CKE1 CKE0 R/W R/W Clock Enable 1 and 0 Selects the clock source and SCK pin function. Asynchronous mode 00: On-chip baud rate generator SCK pin functions as I/O port 01: On-chip baud rate generator (Outputs a clock of the same frequency as the bit rate from the SCK pin.) 1×: External clock (Inputs a clock with a frequency 16 times the bit rate from the SCK pin.) Clocked synchronous mode 0×: Internal clock (SCK pin functions as clock output) 1×: External clock (SCK pin functions as clock input) Legend: ×: Don’t care

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 848 of 1270 REJ09B0466-0100 Smart Card Interface Mode (When SMIF bit in SCMR is 1) Bit Bit Name Initial Value R/W Description When this bit is set to 1, TXI interrupt request is enabled. TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0, or clearing the TIE bit to 0. When this bit is set to 1, RXI and ERI interrupt requests are enabled. RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or by clearing the RIE bit to 0. When this bit is set to 1, transmission is enabled. In this state, serial transmission is started when transmit data is written to TDR and the TDRE flag in SSR is cleared to 0. SMR setting must be performed to decide the transfer format before setting the TE bit to 1. The TDRE flag in SSR is fixed at 1 if transmission is disabled by clearing this bit to 0. When this bit is set to 1, reception is enabled. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in clocked synchronous mode. SMR setting must be performed to decide the transfer format before setting the RE bit to 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states. when the MP bit in SMR is 1 in asynchronous mode) Write 0 to this bit in Smart Card interface mode.

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 849 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description Write 0 to this bit in Smart Card interface mode. CKE1 CKE0 R/W R/W Clock Enable 1 and 0 Enables or disables clock output from the SCK pin. The clock output can be dynamically switched in GSM mode. For details, refer to section 15.7.8, Clock Output Control. When the GM bit in SMR is 0: 00: Output disabled (SCK pin can be used as an I/O port pin) 01: Clock output 1×: Reserved When the GM bit in SMR is 1: 00: Output fixed low 01: Clock output 10: Output fixed high 11: Clock output Legend: ×: Don’t care

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 850 of 1270 REJ09B0466-0100

15.3.7 Serial Status Register (SSR)

SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Some bit functions of SSR differ in normal serial communication interface mode and Smart Card interface mode. Normal Serial Communication Interface Mode (When SMIF bit in SCMR is 0) Bit Bit Name Initial Value R/W Description

7 TDRE 1 R/(W) * Transmit Data Register Empty

Indicates whether TDR contains transmit data. [Setting conditions]

  • When the TE bit in SCR is 0
  • When data is transferred from TDR to TSR, and data writing to TDR is enabled. [Clearing conditions]
  • When 0 is written to TDRE after reading TDRE = 1
  • When the DMAC or DTC is activated by a TXI interrupt request and transfers data to TDR

6 RDRF 0 R/(W) * Receive Data Register Full

Indicates that the received data is stored in RDR. [Setting condition]

  • When serial reception ends normally and receive data is transferred from RSR to RDR [Clearing conditions]
  • When 0 is written to RDRF after reading RDRF = 1
  • When the DMAC or DTC is activated by an RXI interrupt and transferred data from RDR The RDRF flag is not affected and retains its previous value when the RE bit in SCR is cleared to 0. Exercise care because if reception of the next data is completed while the RDRF flag is set to 1, an overrun error occurs and receive data will be lost.

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 851 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description

5 ORER 0 R/(W) * Overrun Error

Indicates that an overrun error occurred while receiving and the reception has ended abnormally. [Setting condition]

  • When the next serial reception is completed while RDRF = 1 The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent serial reception cannot be continued while the ORER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. [Clearing condition]
  • When 0 is written to ORER after reading ORER = 1 The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0.

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 852 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description

4 FER 0 R/(W) * Framing Error

Indicates that a framing error occurred while receiving in asynchronous mode and the reception has ended abnormally. [Setting condition]

  • When the stop bit is 0 In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the FER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. [Clearing condition]
  • When 0 is written to FER after reading FER = The FER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0.

3 PER 0 R/(W) * Parity Error

Indicates that a parity error occurred while receiving in asynchronous mode and the reception has ended abnormally. [Setting condition]

  • When a parity error is detected during reception If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. [Clearing condition]
  • When 0 is written to PER after reading PER = The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0.

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 853 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description

2 TEND 1 R Transmit End

[Setting conditions]

  • When the TE bit in SCR is 0
  • When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character [Clearing conditions]
  • When 0 is written to TDRE after reading TDRE = 1
  • When the DMAC or DTC is activated by a TXI interrupt and writes data to TDR

1 MPB 0 R Multiprocessor Bit

MPB stores the multiprocessor bit in the receive data. When the RE bit in SCR is cleared to 0 its previous state is retained.

0 MPBT 0 R/W Multiprocessor Bit Transfer

MPBT sets the multiprocessor bit to be added to the transmit data. Note: * Only 0 can be written, to clear the flag.

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 854 of 1270 REJ09B0466-0100 Smart Card Interface Mode (When SMIF bit in SCMR is 1) Bit Bit Name Initial Value R/W Description Indicates whether TDR contains transmit data. [Setting conditions]

  • When the TE bit in SCR is 0
  • When data is transferred from TDR to TSR, and data writing to TDR is enabled. [Clearing conditions]
  • When 0 is written to TDRE after reading TDRE = 1
  • When the DMAC or DTC is activated by a TXI interrupt request and transfers data to TDR

Indicates that the received data is stored in RDR. [Setting condition]

  • When serial reception ends normally and receive data is transferred from RSR to RDR [Clearing conditions]
  • When 0 is written to RDRF after reading RDRF = 1
  • When the DMAC or DTC is activated by an RXI interrupt and transferred data from RDR The RDRF flag is not affected and retains its previous value when the RE bit in SCR is cleared to 0. Exercise care because if reception of the next data is completed while the RDRF flag is set to 1, an overrun error occurs and receive data will be lost.

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 855 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description Indicates that an overrun error occurred while receiving and the reception has ended abnormally. [Setting condition]

  • When the next serial reception is completed while RDRF = 1 The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent serial reception cannot be continued while the ORER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. [Clearing condition]
  • When 0 is written to ORER after reading ORER = 1 The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0.

4 ERS 0 R/(W) * Error Signal Status

[Setting condition]

  • When the low level of the error signal is sampled [Clearing conditions]
  • When 0 is written to ERS after reading ERS =

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 856 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description Indicates that a parity error occurred while receiving in asynchronous mode and the reception has ended abnormally. [Setting condition]

  • When a parity error is detected during reception If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. [Clearing condition]
  • When 0 is written to PER after reading PER = The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0.

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 857 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description This bit is set to 1 when no error signal has been sent back from the receiving end and the next transmit data is ready to be transferred to TDR. [Setting conditions]

  • When the TE bit in SCR is 0 and the ERS bit is also 0
  • If the ERS bit is 0 and the TDRE bit is 1 after the specified interval after transmission of 1- byte data Timing to set this bit differs according to the register settings. GM = 0, BLK = 0: 2.5 etu after transmission GM = 0, BLK = 1: 1.5 etu after transmission GM = 1, BLK = 0: 1.0 etu after transmission GM = 1, BLK = 1: 1.0 etu after transmission [Clearing conditions]
  • When 0 is written to TEND after reading TEND = 1
  • When the DMAC or DTC is activated by a TXI interrupt and writes data to TDR

This bit is not used in Smart Card interface mode. Write 0 to this bit in Smart Card interface mode. Note: * Only 0 can be written, to clear the flag.

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 858 of 1270 REJ09B0466-0100

15.3.8 Smart Card Mode Register (SCMR)

SCMR selects Smart Card interface mode and its format. Bit Bit Name Initial Value R/W Description

7 BCP2 1 R/W Basic Clock Pulse 2

Selects, in combination with the BCP1 and BCP0 bits in SMR, the number of basic clock cycles in a 1-bit transfer interval in Smart Card interface mode. For the settings, refer to section 15.3.5, Serial Mode Register (SMR). 6 to 4  All 1  Reserved These bits are always read as 1.

3 SDIR 0 R/W Smart Card Data Transfer Direction

Selects the serial/parallel conversion format. 0: LSB-first in transfer 1: MSB-first in transfer The bit setting is valid only when the transfer data format is 8 bits. For 7-bit data, LSB-first is fixed.

2 SINV 0 R/W Smart Card Data Invert

Specifies inversion of the data logic level. The SINV bit does not affect the logic level of the parity bit. To invert the parity bit, invert the O/E bit in SMR. 0: TDR contents are transmitted as they are. Receive data is stored as it is in RDR. 1: TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR. 1  1  Reserved This bit is always read as 1.

0 SMIF 0 R/W Smart Card Interface Mode Select

This bit is set to 1 to make the SCI operate in Smart Card interface mode. 0: Normal asynchronous mode or clocked synchronous mode 1: Smart Card interface mode

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 859 of 1270 REJ09B0466-0100

15.3.9 Bit Rate Register (BRR)

BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 15.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode, clocked synchronous mode, and Smart Card interface mode. The initial value of BRR is H'FF, and it can be read or written to by the CPU at all times. Table 15.2 Relationships between N Setting in BRR and Bit Rate B Mode Bit Rate Error Asynchronous Mode B = φ × 106 Clocked Synchronous Mode B = φ × 106 Smart Card Interface Mode B = φ × 106 Error (%) = { φ × 106 Note: B: Bit rate (bit/s) N: BRR setting for baud rate generator (0 ≤ N ≤ 255) φ: Operating frequency (MHz) n and S: Determined by the SMR settings shown in the following tables. SMR Setting SCMR Setting SMR Setting CKS1 CKS0 n BCP2 BCP1 BCP0 S 0 0 0 0 0 0 93 0 1 1 0 0 1 128 1 0 2 0 1 0 186 1 1 3 0 1 1 512 1 0 0 32 1 0 1 64 1 1 0 372 1 1 1 256

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 860 of 1270 REJ09B0466-0100 Table 15.3 shows sample N settings in BRR in normal asynchronous mode. Table 15.4 shows the maximum bit rate for each frequency in normal asynchronous mode. Table 15.6 shows sample N settings in BRR in clocked synchronous mode. Table 15.8 shows sample N settings in BRR in Smart Card interface mode. In Smart Card interface mode, S (the number of basic clock cycles in a 1-bit transfer interval) can be selected. For details, refer to section 15.7.4, Receive Data Sampling Timing and Reception Margin. Tables 15.5 and 15.7 show the maximum bit rates with external clock input. Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) Operating Frequency φ (MHz) 8 9.8304 10 12 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 141 0.03 2 174 –0.26 2 177 –0.25 2 212 0.03 150 2 103 0.16 2 127 0.00 2 129 0.16 2 155 0.16 300 1 207 0.16 1 255 0.00 2 64 0.16 2 77 0.16 600 1 103 0.16 1 127 0.00 1 129 0.16 1 155 0.16 1200 0 207 0.16 0 255 0.00 1 64 0.16 1 77 0.16 2400 0 103 0.16 0 127 0.00 0 129 0.16 0 155 0.16 4800 0 51 0.16 0 63 0.00 0 64 0.16 0 77 0.16 9600 0 25 0.16 0 31 0.00 0 32 –1.38 0 38 0.16 19200 0 12 0.16 0 15 0.00 0 15 1.70 0 19 –2.40 31250 0 7 0.00 0 9 –1.73 0 9 0.00 0 11 0.00 38400    0 7 0.00 0 7 1.70 0 9 –2.40

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 861 of 1270 REJ09B0466-0100 Operating Frequency φ (MHz) 12.288 14 14.7456 16 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 217 0.08 2 248 –0.17 3 64 0.69 3 70 0.03 150 2 159 0.00 2 181 0.16 2 191 0.00 2 207 0.16 300 2 79 0.00 2 90 0.16 2 95 0.00 2 103 0.16 600 1 159 0.00 1 181 0.16 1 191 0.00 1 207 0.16 1200 1 79 0.00 1 90 0.16 1 95 0.00 1 103 0.16 2400 0 159 0.00 0 181 0.16 0 191 0.00 0 207 0.16 4800 0 79 0.00 0 90 0.16 0 95 0.00 0 103 0.16 9600 0 39 0.00 0 45 –0.94 0 47 0.00 0 51 0.16 19200 0 19 0.00 0 22 –0.94 0 23 0.00 0 25 0.16 31250 0 11 2.34 0 13 0.00 0 14 –1.73 0 15 0.00 38400 0 9 0.00    0 11 0.00 0 12 0.16 Operating Frequency φ (MHz) 17.2032 18 19.6608 20 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 3 75 0.48 3 79 –0.12 3 86 0.31 3 88 –0.25 150 2 223 0.00 2 233 0.16 2 255 0.00 3 64 0.16 300 2 111 0.00 2 116 0.16 2 127 0.00 2 129 0.16 600 1 223 0.00 1 233 0.16 1 255 0.00 2 64 0.16 1200 1 111 0.00 1 116 0.16 1 127 0.00 1 129 0.16 2400 0 223 0.00 0 233 0.16 0 255 0.00 1 64 0.16 4800 0 111 0.00 0 116 0.16 0 127 0.00 0 129 0.16 9600 0 55 0.00 0 58 –0.69 0 63 0.00 0 64 0.16 19200 0 27 0.00 0 28 1.01 0 31 0.00 0 32 –1.38 31250 0 16 1.20 0 17 0.00 0 19 –1.73 0 19 0.00 38400 0 13 0.00 0 14 –2.40 0 15 0.00 0 15 1.70

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 862 of 1270 REJ09B0466-0100 Operating Frequency φ (MHz) 25 30 33 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) 110 3 110 –0.02 3 132 0.13 3 145 0.33 150 3 80 0.47 3 97 –0.35 3 106 0.39 300 2 162 –0.15 2 194 0.16 2 214 –0.07 600 2 80 0.47 2 97 –0.35 2 106 0.39 1200 1 162 –0.15 1 194 0.16 1 214 –0.07 2400 1 80 0.47 1 97 –0.35 1 106 0.39 4800 0 162 –0.15 0 194 0.16 0 214 –0.07 9600 0 80 0.47 0 97 –0.35 0 106 0.39 19200 0 40 –0.76 0 48 –0.35 0 53 –0.54 31250 0 24 0.00 0 29 0.00 0 32 0.00 38400 0 19 1.70 0 23 1.70 0 26 –0.54 Table 15.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) φ (MHz) Maximum Bit Rate (bit/s) n N 8 250000 0 0 9.8304 307200 0 0 10 312500 0 0 12 375000 0 0 12.288 384000 0 0 14 437500 0 0 14.7456 460800 0 0 16 500000 0 0 17.2032 537600 0 0 18 562500 0 0 19.6608 614400 0 0 20 625000 0 0 25 781250 0 0 30 937500 0 0 33 1031250 0 0

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 863 of 1270 REJ09B0466-0100 Table 15.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) φ (MHz) External Input Clock (MH z) Maximum Bit Rate (bit/s) 8 2.0000 125000 9.8304 2.4576 153600 10 2.5000 156250 12 3.0000 187500 12.288 3.0720 192000 14 3.5000 218750 14.7456 3.6864 230400 16 4.0000 250000 17.2032 4.3008 268800 18 4.5000 281250 19.6608 4.9152 307200 20 5.0000 312500 25 6.2500 390625 30 7.5000 468750 33 8.2500 515625

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 864 of 1270 REJ09B0466-0100 Table 15.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency φ (MHz) 8 10 16 20 25 30 33 Bit Rate (bit/s) n N n N n N n N n N n N n N 110 250 3 124   3 249 500 2 249   3 124   3 233 1 k 2 124   2 249   3 97 3 116 3 128 2.5 k 1 199 1 249 2 99 2 124 2 155 2 187 2 205 5 k 1 99 1 124 1 199 1 249 2 77 2 93 2 102 10 k 0 199 0 249 1 99 1 124 1 155 1 187 1 205 25 k 0 79 0 99 0 159 0 199 0 249 1 74 1 82 50 k 0 39 0 49 0 79 0 99 0 124 0 149 0 164 100 k 0 19 0 24 0 39 0 49 0 62 0 74 0 82 250 k 0 7 0 9 0 15 0 19 0 24 0 29 0 32 500 k 0 3 0 4 0 7 0 9   0 14  

2.5 M 0 0* 0 1   0 2  

Legend: Blank: Cannot be set. : Can be set, but there will be a degree of error. *: Continuous transfer is not possible. Table 15.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 8 1.3333 1333333.3 18 3.0000 3000000.0 10 1.6667 1666666.7 20 3.3333 3333333.3 12 2.0000 2000000.0 25 4.1667 4166666.7 14 2.3333 2333333.3 30 5.0000 5000000.0 16 2.6667 2666666.7 33 5.5000 5500000.0

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 865 of 1270 REJ09B0466-0100 Table 15.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode) (when n = 0 and S = 372) Operating Frequency φ (MHz) 10.00 10.7136 13.00 14.2848 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Erro r (%) 9600 0 1 30.00 0 1 25.00 0 1 8.99 0 1 0.00 Operating Frequency φ (MHz) 16.00 18.00 20.00 25.00 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Erro r (%) 9600 0 1 12.01 0 2 15.99 0 2 6.66 0 3 12.4 Operating Frequency φ (MHz) 30.00 33.00 Bit Rate (bit/s) n N Error (%) n N Error (%) 9600 0 3 5.01 0 4 7.59 Table 15.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) (when S = 372) φ (MHz) Maximum Bit Rate (bit/s) n N φ (MHz) Maximum Bit Rate (bit/s) n N 10.00 13441 0 0 18.00 24194 0 0 10.7136 14400 0 0 20.00 26882 0 0 13.00 17473 0 0 25.00 33602 0 0 14.2848 19200 0 0 30.00 40323 0 0 16.00 21505 0 0 33.00 44355 0 0

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 866 of 1270 REJ09B0466-0100

15.3.10 IrDA Control Register (IrCR)

IrCR selects the function of SCI_0. Bit Bit Name Initial Value R/W Description

7 IrE 0 R/W IrDA Enable

Specifies normal SCI mode or IrDA mode for SCI_0 input/output. 0: Pins TxD0/IrTxD and RxD0/IrRxD function as TxD0 and RxD0 1: Pins TxD0/IrTxD and RxD0/IrRxD function as IrTxD and IrRxD IrCKS2 IrCKS1 IrCKS0 R/W R/W R/W IrDA Clock Select 2 to 0 Specifies the high pulse width in IrTxD output pulse encoding when the IrDA function is enabled. 000: Pulse width = B × 3/16 (3/16 of bit rate) 001: Pulse width = φ/2 010: Pulse width = φ/4 011: Pulse width = φ/8 100: Pulse width = φ/16 101: Pulse width = φ/32 110: Pulse width = φ/64 111: Pulse width = φ/128

3 IrTxINV 0 R/W IrTx Data Invert

Specifies the logic level of the IrTxD output to be inverted. When inversion is performed, the high pulse width specified by bits 6 to 4 becomes the low pulse width. 0: Transmit data is used as IrTxD output without change 1: Transmit data is inverted before used as IrTxD output

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 867 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description

2 IrRxINV 0 R/W IrRx Data Invert

Specifies the logic level of the IrRxD output to be inverted. When inversion is performed, the high pulse width specified by bits 6 to 4 becomes the low pulse width. 0: Transmit data is used as IrRxD output without change 1: Transmit data is inverted before used as IrRxD output 1, 0  All 0  Reserved These bits are always read as 0 and cannot be modified.

15.3.11 Serial Extension Mode Register (SEMR)

SEMR selects the clock source in asynchronous mode. The basic clock can be automatically set by selecting the average transfer rate. Bit Bit Name Initial Value R/W Description 7 to 4  Undefined  Reserved If these bits are read, an undefined value will be returned and cannot be modified.

3 ABCS 0 R/W Asynchronous basic clock selection (valid only in

asynchronous mode) Selects the basic clock for 1-bit period in asynchronous mode. 0: Operates on a basic clock with a frequency of 16 times the transfer rate. 1: Operates on a basic clock with a frequency of 8 times the transfer rate.

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 868 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description ACS2 ACS1 ACS0 R/W R/W R/W Asynchronous clock source selection (valid when CKE1 = 1 in asynchronous mode) Selects the clock source for the average transfer rate. The basic clock can be automatically set by selecting the average transfer rate in spite of the value of ABCS. 000: External clock input 001: Selects 115.152 kbps which is the average transfer rate dedicated for φ= 10.667 MHz. (Operates on a basic clock with a frequency of 16 times the transfer rate.) 010: Selects 460.606 kbps which is the average transfer rate dedicated for φ= 10.667 MHz. (Operates on a basic clock with a frequency of 8 times the transfer rate.) 011: Selects 720 kbps which is the average transfer rate dedicated for φ = 32 MHz. (Operates on a basic clock with a frequency of 16 times the transfer rate.) 100: Reserved 101: Selects 115.196 kbps which is the average transfer rate dedicated for φ = 16 MHz (Operates on a basic clock with a frequency of 16 times the transfer rate.) 110: Selects 460.784 kbps which is the average transfer rate dedicated for φ = 16 MHz (Operates on a basic clock with a frequency of 16 times the transfer rate.) 111: Selects 720 kbps which is the average transfer rate dedicated for φ = 16 MHz (Operates on a basic clock with a frequency of 8 times the transfer rate.) Note that the average transfer rate does not correspond to the frequency other than 10.667, 16, or 32 MHz.

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 869 of 1270 REJ09B0466-0100

15.4 Operation in Asynchronous Mode

Figure 15.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transfer data, a parity bit, and finally stop bits (high level). In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. In asynchronous serial communication, the communication line is usually held in the mark state (high level). The SCI monitors the communication line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double- buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. LSB Start bit MSB Idle state (mark state) Stop bit(s) Transmit/receive data D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 1 Serial data Parity bit 1 bit 1 or 2 bits 7 or 8 bits 1 bit, or none One unit of transfer data (character or frame) Figure 15.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits)

15.4.1 Data Transfer Format

Table 15.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, refer to section 15.5, Multiprocessor Communication Function.

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 870 of 1270 REJ09B0466-0100 Table 15.10 Serial Transfer Formats (Asynchronous Mode) PE S 8-bit data STOP S 7-bit data STOP S 8-bit data STOP STOP S 8-bit data P STOP S 7-bit data STOPP S 8-bit data MPB STOP S 8-bit data MPB STOP STOP S 7-bit data STOPMPB S 7-bit data STOPMPB STOP S 7-bit data STOPSTOP CHR MP STOP SMR Settings 123456789 1 0 1 1 1 2 Serial Transfer Format and Frame Length STOPS 8-bit data P STOP S 7-bit data STOPP STOP Legend: S : Start bit STOP : Stop bit P : Parity bit MPB : Multiprocessor bit

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 871 of 1270 REJ09B0466-0100

15.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode

In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched at the middle of each bit by sampling the data at the rising edge of the 8th pulse of the basic clock as shown in figure 15.3. Thus the reception margin in asynchronous mode is given by formula (1) below. D – 0.5 N ... Formula (1) Where M: Reception Margin N: Ratio of bit rate to clock (N = 16) D: Clock duty cycle (D = 0.5 to 1.0) L: Frame length (L = 9 to 12) F: Absolute value of clock rate deviation Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin is given by formula below. However, this is only the computed value, and a margin of 20% to 30% should be allowed in system design. Internal base clock 16 clocks 8 clocks Receive data (RxD) Synchronization sampling timing Start bit D0 D1 Data sampling timing 15 0 7 15 00 7 Figure 15.3 Receive Data Sampling Timing in Asynchronous Mode

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 872 of 1270 REJ09B0466-0100

15.4.3 Clock

Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 15.4. 1 frame SCK TxD D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 Figure 15.4 Relation between Output Clock and Transfer Data Phase (Asynchronous Mode)

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 873 of 1270 REJ09B0466-0100

15.4.4 SCI Initialization (Asynchronous Mode)

Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as shown in figure 15.5. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. When the external clock is used in asynchronous mode, the clock must be supplied even during initialization. Wait <Initialization completed> Start of initialization Set data transfer format in SMR and SCMR [1]Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) No Yes Set value in BRR Clear TE and RE bits in SCR to 0 [2] [3] Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits [4] 1-bit interval elapsed? [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock is selected in asynchronous mode, it is output immediately after SCR settings are made. [2] Set the data transfer format in SMR and SCMR. [3] Write a value corresponding to the bit rate to BRR. (Not necessary if an external clock is used.) [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. Figure 15.5 Sample SCI Initialization Flowchart

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 874 of 1270 REJ09B0466-0100

15.4.5 Data Transmission (Asynchronous Mode)

Figure 15.6 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt request (TXI) is generated. Because the TXI interrupt routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or multiprocessor bit (may be omitted depending on the format), and stop bit. 4. The SCI checks the TDRE flag at the timing for sending the stop bit. 5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. 6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the “mark state” is entered in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. Figure 15.7 shows a sample flowchart for transmission in asynchronous mode. TDRE TEND 1 frame D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 1 1 1 DataStart bit Parity bit Stop bit Start bit Data Parity bit Stop bit TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt handling routine TEI interrupt request generated Idle state (mark state) TXI interrupt request generated Figure 15.6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit)

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 875 of 1270 REJ09B0466-0100 No <End> [1] Yes Initialization Start of transmission Read TDRE flag in SSR [2] Write transmit data to TDR and clear TDRE flag in SSR to 0 No Yes No Yes Read TEND flag in SSR [3] No Yes [4] Clear DR to 0 and set DDR to 1 Clear TE bit in SCR to 0 TDRE = 1? All data transmitted? TEND = 1? Break output? [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DMAC or DTC is activated by a transmit-data- empty interrupt (TXI) request, and data is written to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port corresponding to the TxD pin to 1, clear DR to 0, then clear the TE bit in SCR to 0. Figure 15.7 Sample Serial Transmission Flowchart

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 876 of 1270 REJ09B0466-0100

15.4.6 Serial Data Reception (Asynchronous Mode)

Figure 15.8 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2. If an overrun error (when reception of the next data is completed while the RDRF flag is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 4. If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 5. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled. RDRF FER 1 frame D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 0 1 1 DataStart bit Parity bit Stop bit Start bit Data Parity bit Stop bit RXI interrupt request generated ERI interrupt request generated by framing error Idle state (mark state) RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine Figure 15.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit)

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 877 of 1270 REJ09B0466-0100 Table 15.11 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 15.9 shows a sample flowchart for serial data reception. Table 15.11 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF * ORER FER PER Receive Data Receive Error Type 1 1 0 0 Lost Overrun error 0 0 1 0 Transferred to RDR Framing error 0 0 0 1 Transferred to RDR Parity error 1 1 1 0 Lost Overrun error + framing error 1 1 0 1 Lost Overrun error + parity error 0 0 1 1 Transferred to RDR Framing error + parity error 1 1 1 1 Lost Overrun error + framing error + parity error Note: * The RDRF flag retains its st ate before data reception.

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 878 of 1270 REJ09B0466-0100 Yes <End> [1] No Initialization Start of reception [2] No Yes Read RDRF flag in SSR [4] [5] Clear RE bit in SCR to 0 Read ORER, PER, and FER flags in SSR Error handling (Continued on next page) [3] Read receive data in RDR, and clear RDRF flag in SSR to 0 No Yes PER ∨ FER ∨ ORER = 1? RDRF = 1? All data received? SCI initialization: The RxD pin is automatically designated as the receive data input pin. Receive error handling and break detection: If a receive error occurs, read the ORER, PER, and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the ORER, PER, and FER flags are all cleared to 0. Reception cannot be resumed if any of these flags are set to 1. In the case of a framing error, a break can be detected by reading the value of the input port corresponding to the RxD pin. SCI status check and receive data read : Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. Serial reception continuation procedure: To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag, read RDR, and clear the RDRF flag to 0. The RDRF flag is cleared automatically when the DMAC or DTC is activated by an RXI interrupt and the RDR value is read. [1] [2] [3] [4] [5] Figure 15.9 Sample Serial Reception Data Flowchart (1)

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 879 of 1270 REJ09B0466-0100 <End> [3] Error handling Parity error handling Yes No Clear ORER, PER, and FER flags in SSR to 0 No Yes No Yes Framing error handling No Yes Overrun error handling ORER = 1? FER = 1? Break? PER = 1? Clear RE bit in SCR to 0 Figure 15.9 Sample Serial Reception Data Flowchart (2)

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 880 of 1270 REJ09B0466-0100

15.5 Multiprocessor Communication Function

Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station, and a data transmission cycle to the specified receiving station. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 15.10 shows an example of inter-processor communication using the multiprocessor format. The transmitting station first sends communication data with a 1 multiprocessor bit added to the ID code of the receiving station. It then sends transmit data as data with a 0 multiprocessor bit added. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip data until data with a 1 multiprocessor bit is again received. The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1, transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags, RDRF, FER, and ORER to 1 are inhibited until data with a 1 multiprocessor bit is received. On reception of receive character with a 1 multiprocessor bit, the MPBR bit in SSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt is generated. When the multiprocessor format is selected, the parity bit setting is invalid. All other bit settings are the same as those in normal asynchronous mode. The clock used for multiprocessor communication is the same as that in normal asynchronous mode.

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 881 of 1270 REJ09B0466-0100 Transmitting station Receiving station A (ID = 01) Receiving station B (ID = 02) Receiving station C (ID = 03) Receiving station D (ID = 04) Serial communication line Serial data ID transmission cycle = receiving station specification Data transmission cycle = data transmission to receiving station specified by ID (MPB= 1) (MPB= 0) H'01 H'AA Legend: MPB: Multiprocessor bit Figure 15.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)

15.5.1 Multiprocessor Serial Data Transmission

Figure 15.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode.

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 882 of 1270 REJ09B0466-0100 No <End> [1] Yes Initialization Start of transmission Read TDRE flag in SSR [2] Write transmit data to TDR and set MPBT bit in SSR No Yes No Yes Read TEND flag in SSR [3] No Yes [4] Clear DR to 0 and set DDR to 1 Clear TE bit in SCR to 0 TDRE = 1? All data transmitted? TEND = 1? Break output? Clear TDRE flag to 0 SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DMAC or DTC is activated by a transmit-data-empty interrupt (TXI) request, and data is written to TDR. Break output at the end of serial transmission: To output a break in serial transmission, set the port DDR to 1, clear DR to 0, then clear the TE bit in SCR to 0. [1] [2] [3] [4] Figure 15.11 Sample Multiprocessor Serial Transmission Flowchart

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 883 of 1270 REJ09B0466-0100

15.5.2 Multiprocessor Serial Data Reception

Figure 15.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is received. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 15.12 shows an example of SCI operation for multiprocessor format reception.

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 884 of 1270 REJ09B0466-0100 MPIE RDR value

0 D0 D1 D7 1 1 0 D0 D1 D7 01

Data (ID1)Start bit MPB Stop bit Start bit Data (Data1) MPB Stop bit RXI interrupt request (multiprocessor interrupt) generated MPIE = 0 Idle state (mark state) RDRF RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine If not this station’s ID, MPIE bit is set to 1 again RXI interrupt request is not generated, and RDR retains its state ID1 (a) Data does not match station’s ID MPIE RDR value Data (ID2)Start bit MPB Stop bit Start bit Data (Data2) MPB Stop bit RXI interrupt request (multiprocessor interrupt) generated MPIE = 0 Idle state (mark state) RDRF RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine Matches this station’s ID, so reception continues, and data is received in RXI interrupt handling routine MPIE bit set to 1 again ID2 (b) Data matches station’s ID Data2ID1 Figure 15.12 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 885 of 1270 REJ09B0466-0100 Yes <End> [1] No Initialization Start of reception No Yes [4] Clear RE bit in SCR to 0 Error handling (Continued on next page) [5]No Yes FER ∨ ORER = 1? RDRF = 1? All data received? Set MPIE bit in SCR to 1 [2] Read ORER and FER flags in SSR Read RDRF flag in SSR [3] Read receive data in RDR No Yes This station's ID? Read ORER and FER flags in SSR Yes No Read RDRF flag in SSR No Yes FER ∨ ORER = 1? Read receive data in RDR RDRF = 1? SCI initialization: The RxD pin is automatically designated as the receive data input pin. ID reception cycle: Set the MPIE bit in SCR to 1. SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station’s ID. If the data is not this station’s ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station’s ID, clear the RDRF flag to 0. SCI status check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. Receive error handling and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error handling, ensure that the ORER and FER flags are both cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin value. [1] [2] [3] [4] [5] Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (1)

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 886 of 1270 REJ09B0466-0100 <End> Error handling Yes No Clear ORER, PER, and FER flags in SSR to 0 No Yes No Yes Framing error handling Overrun error handling ORER = 1? FER = 1? Break? Clear RE bit in SCR to 0 [5] Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (2)

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15.6 Operation in Clocked Synchronous Mode

Figure 15.14 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. One character of communication data consists of 8-bit data. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. In clocked synchronous mode, the SCI receives data in synchronization with the rising edge of the serial clock. After 8-bit data is output, the transmission line holds the MSB state. In clocked synchronous mode, no parity or multiprocessor bit is added. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Don’t careDon’t care One unit of transfer data (character or frame) Bit 0Serial data Serial clock Bit 1 Bit 3 Bit 4 Bit 5 LSB MSB Bit 2 Bit 6 Bit 7 Note: * High except in continuous transfer Figure 15.14 Data Format in Clocked Synchronous Communication (For LSB-First)

15.6.1 Clock

Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCK pin can be selected, according to the setting of CKE1 and CKE0 bits in SCR. When the SCI is operated on an internal clock, the serial clock is output from the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high.

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15.6.2 SCI Initialization (Clocked Synchronous Mode)

Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 15.15. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. Wait <Transfer start> Start of initialization Set data transfer format in SMR and SCMR No Yes Set value in BRR Clear TE and RE bits in SCR to 0 [2] [3] Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits Note: In simultaneous transmit and receive operations, the TE and RE bits should both be cleared to 0 or set to 1 simultaneously. [4] 1-bit interval elapsed? Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) [1] [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE, to 0. [2] Set the data transfer format in SMR and SCMR. [3] Write a value corresponding to the bit rate to BRR. (Not necessary if an external clock is used.) [4] Wait at least one bit interval, then set the TE and RE bits in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enable the TxD and RxD pins to be used. Figure 15.15 Sample SCI Initialization Flowchart

15.6.3 Serial Data Transmission (Clocked Synchronous Mode)

Figure 15.16 shows an example of SCI operation for transmission in clocked synchronous mode. In serial transmission, the SCI operates as described below.

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 890 of 1270 REJ09B0466-0100 No <End> [1] Yes Initialization Start of transmission Read TDRE flag in SSR [2] Write transmit data to TDR and clear TDRE flag in SSR to 0 No Yes No Yes Read TEND flag in SSR [3] Clear TE bit in SCR to 0 TDRE = 1? All data transmitted? TEND = 1? [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DMAC or DTC is activated by a transmit-data- empty interrupt (TXI) request and data is written to TDR. Figure 15.17 Sample Serial Transmission Flowchart

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15.6.4 Serial Data Reception (Clocked Synchronous Mode)

Figure 15.18 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the received data in RSR. 2. If an overrun error (when reception of the next data is completed while the RDRF flag is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled. Bit 7Serial data Serial clock 1 frame RDRF ORER Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine RXI interrupt request generated ERI interrupt request generated by overrun error Figure 15.18 Example of SCI Operation in Reception Transfer cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 15.19 shows a sample flowchart for serial data reception.

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 892 of 1270 REJ09B0466-0100 Yes <End> [1] No Initialization Start of reception [2] No Yes Read RDRF flag in SSR [4] [5] Clear RE bit in SCR to 0 Error processing (Continued below) [3] Read receive data in RDR, and clear RDRF flag in SSR to 0 No Yes ORER = 1? RDRF = 1? All data received? Read ORER flag in SSR [1] [2] [3] [4] [5] SCI initialization: The RxD pin is automatically designated as the receive data input pin. Receive error handling: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error handling, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. Serial reception continuation procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. The RDRF flag is cleared automatically when the DMAC or DTC is activated by a receive- data-full interrupt (RXI) request and the RDR value is read. <End> Error handling Overrun error handling [3] Clear ORER flag in SSR to 0 Figure 15.19 Sample Serial Reception Flowchart

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15.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous

Mode) Figure 15.20 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations after the SCI is initialized. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0. Then simultaneously set TE and RE to 1 with a single instruction. To switch from receive mode to simultaneous transmit and receive mode, after checking that the SCI has finished reception, clear RE to 0. Then after checking that the RDRF and receive error flags (ORER, FER, and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single instruction.

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 894 of 1270 REJ09B0466-0100 Yes <End> [1] No Initialization Start of transmission/reception [5] Error handling [3] Read receive data in RDR, and clear RDRF flag in SSR to 0 No Yes ORER = 1? All data received? [2]Read TDRE flag in SSR No Yes TDRE = 1? Write transmit data to TDR and clear TDRE flag in SSR to 0 No Yes RDRF = 1? Read ORER flag in SSR [4]Read RDRF flag in SSR Clear TE and RE bits in SCR to 0 Note: When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the TE and RE bits to 0, then set both these bits to 1 simultaneously. [1] [2] [3] [4] [5] SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. Receive error handling: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error handling, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. Serial transmission/reception continuation procedure: To continue serial transmission/ reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to TDR and clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DMAC or DTC is activated by a transmit-data- empty interrupt (TXI) request and data is written to TDR. Also, the RDRF flag is cleared automatically when the DMAC or DTC is activated by a receive-data-full interrupt (RXI) request and the RDR value is read. Figure 15.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations

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15.7 Operation in Smart Card Interface Mode

The SCI supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Switching between the normal serial communication interface and the Smart Card interface is carried out by means of a register setting.

15.7.1 Pin Connection Example

Figure 15.21 shows an example of connection with the Smart Card. In communication with an IC card, since both transmission and reception are carried out on a single data transmission line, the TxD pin and RxD pin should be connected with the LSI pin. The data transmission line should be pulled up to the VCC power supply with a resistor. If an IC card is not connected, and the TE and RE bits are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out. When the clock generated on the SCI is used by an IC card, the SCK pin output is input to the CLK pin of the IC card. This LSI port output is used as the reset signal. TxD RxD This LSI VCC I/O Connected equipment IC card Data line CLK RST SCK Rx (port) Clock line Reset line Figure 15.21 Schematic Diagram of Smart Card Interface Pin Connections

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15.7.2 Data Format (Except for Block Transfer Mode)

Figure 15.22 shows the transfer data format in Smart Card interface mode.

  • One frame consists of 8-bit data plus a parity bit in asynchronous mode.
  • In transmission, a guard time of at least 2 etu (Elementary Time Unit: time for transfer of 1 bit) is left between the end of the parity bit and the start of the next frame.
  • If a parity error is detected during reception, a low error signal level is output for one etu period, 10.5 etu after the start bit.
  • If an error signal is sampled during transmission, the same data is retransmitted automatically after the elapse of 2 etu or longer. Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp When there is no parity error Transmitting station output Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp When a parity error occurs Transmitting station output DE Receiving station output : Start bit : Data bits : Parity bit : Error signal Legend: Ds D0 to D7 Dp DE Figure 15.22 Normal Smart Card Interface Data Format Data transfer with the types of IC cards (direct convention and inverse convention) are performed as described in the following. Ds AZ ZAZ Z Z ZA A(Z) (Z) State D0 D1 D2 D3 D4 D5 D6 D7 Dp Figure 15.23 Direct Convention (SDIR = SINV = O/E = 0)

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 897 of 1270 REJ09B0466-0100 As in the above sample start character, with the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. The start character data above is H'3B. For the direct convention type, clear the SDIR and SINV bits in SCMR to 0. According to the Smart Card regulations, clear the O/E bit in SMR to 0 to select even parity mode. Ds AZ ZAA A Z AA A(Z) (Z) State D7 D6 D5 D4 D3 D2 D1 D0 Dp Figure 15.24 Inverse Convention (SDIR = SINV = O/E = 1) With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to state Z, and transfer is performed in MSB-first order. The start character data above is H'3F. For the inverse convention type, set the SDIR and SINV bits in SCMR to 1. According to the Smart Card regulations, even parity mode is the logic 0 level of the parity bit, and corresponds to state Z. In this LSI, the SINV bit inverts only data bits D7 to D0. Therefore, set the O/E bit in SMR to 1 to invert the parity bit for both transmission and reception.

15.7.3 Block Transfer Mode

Operation in block transfer mode is the same as that in normal Smart Card interface, except for the following points.

  • In reception, though the parity check is performed, no error signal is output even if an error is detected. However, the PER bit in SSR is set to 1 and must be cleared before receiving the parity bit of the next frame.
  • In transmission, a guard time of at least 1 etu is left between the end of the parity bit and the start of the next frame.
  • In transmission, because retransmission is not performed, the TEND flag is set to 1, 11.5 etu after transmission start.
  • As with the normal Smart Card interface, the ERS flag indicates the error signal status, but since error signal transfer is not performed, this flag is always cleared to 0.

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 898 of 1270 REJ09B0466-0100

15.7.4 Receive Data Sampling Timing and Reception Margin

Only the internal clock generated by the on-chip baud rate generator is used as transmit/receive clock in Smart Card interface. In Smart Card interface mode, the SCI operates on a basic clock with a frequency of 32, 64, 372, 256, 93, 128, 186, or 512 times the bit rate (fixed at 16 times in normal asynchronous mode) as determined by bits BCP2 to BCP0. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. As shown in figure 15.25, by sampling receive data at the rising-edge of the 16th, 32nd, 186th, 128th, 46th, 64th, 93rd, or 256th pulse of the basic clock, data can be latched at the middle of the bit. The reception margin is given by the following formula. D – 0.5 N Where M: Reception margin (%) N: Ratio of bit rate to clock (N = 32, 64, 372, 256, 93, 128, 186, or 512) D: Clock duty cycle (D = 0 to 1.0) L: Frame length (L = 10) F: Absolute value of clock frequency deviation Assuming values of F = 0, D = 0.5 and N = 372 in the above formula, the reception margin formula is as follows. = 49.866%

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 899 of 1270 REJ09B0466-0100 Internal basic clock 372 clocks 186 clocks Receive data (RxD) Synchronization sampling timing D0 D1 Data sampling timing 185 371 0371185 00 Start bit Figure 15.25 Receive Data Sampling Timing in Smart Card Mode (Using Clock of 372 Times the Bit Rate)

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 900 of 1270 REJ09B0466-0100

15.7.5 Initialization

Before transmitting and receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. 1. Clear the TE and RE bits in SCR to 0. 2. Clear the error flags ERS, PER, and ORER in SSR to 0. 3. Set the GM, BLK, O/E, BCP1, BCP0, CKS1, and CKS0 bits in SMR, and the BCP2 bit in SCMR. Set the PE bit to 1. 4. Set the SMIF, SDIR, and SINV bits in SCMR. When the SMIF bit is set to 1, the TxD and RxD pins are both switched from ports to SCI pins, and are placed in the high-impedance state. 5. Set the value corresponding to the bit rate in BRR. 6. Set the CKE0 and CKE1 bits in SCR. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0. If the CKE0 bit is set to 1, the clock is output from the SCK pin. 7. Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE bit and RE bit at the same time, except for self-diagnosis. To switch from receive mode to transmit mode, after checking that the SCI has finished reception, initialize the SCI, and clear RE to 0 and set TE to 1. Whether SCI has finished reception can be checked with the RDRF, PER, or ORER flag. To switch from transmit mode to receive mode, after checking that the SCI has finished transmission, initialize the SCI, and clear TE to 0 and set RE to 1. Whether SCI has finished transmission can be checked with the TEND flag.

15.7.6 Data Transmission (Except for Block Transfer Mode)

As data transmission in Smart Card interface mode involves error signal sampling and retransmission processing, the operations are different from those in normal serial communication interface mode (except for block transfer mode). Figure 15.26 illustrates the retransfer operation when the SCI is in transmit mode. 1. If an error signal is sampled from the receiving end after transmission of one frame is completed, the ERS bit in SSR is set to 1. If the RIE bit in SCR is set at this time, an ERI interrupt request is generated. The ERS bit in SSR should be cleared to 0 before the next parity bit is sampled. 2. The TEND bit in SSR is not set for a frame for which an error signal is received. Data is retransferred from TDR to TSR, and retransmitted automatically. 3. If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set.

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 902 of 1270 REJ09B0466-0100 The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag generation timing is shown in figure 15.27. Ds D0 D1 D2 D3 D4 D5 D6 D7 DpI/O data 12.5 etu TXI (TEND interrupt) 11.0 etu DE Guard time When GM = 0 When GM = 1 : Start bit : Data bits : Parity bit : Error signal Legend: Ds D0 to D7 Dp DE Note: etu (Elementary Time Unit): Time for transfer of 1 bit Figure 15.27 TEND Flag Generation Timing in Transmission Operation

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 903 of 1270 REJ09B0466-0100 Initialization No Yes Clear TE bit to 0 Start transmission Start No No No Yes Yes Yes Yes No End Write data to TDR, and clear TDRE flag in SSR to 0 Error processing Error processing TEND = 1? All data transmitted ? TEND = 1? ERS = 0? ERS = 0? Figure 15.28 Example of Transmission Processing Flow

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 904 of 1270 REJ09B0466-0100

15.7.7 Serial Data Reception (Except for Block Transfer Mode)

Data reception in Smart Card interface mode uses the same operation procedure as for normal serial communication interface mode. Figure 15.29 illustrates the retransfer operation when the SCI is in receive mode. 1. If an error is found when the received parity bit is checked, the PER bit in SSR is automatically set to 1. If the RIE bit in SCR is set at this time, an ERI interrupt request is generated. The PER bit in SSR should be cleared to 0 before the next parity bit is sampled. 2. The RDRF bit in SSR is not set for a frame in which an error has occurred. 3. If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1. 4. The receive operation is judged to have been completed normally, and the RDRF flag in SSR is automatically set to 1. If the RIE bit in SCR is set at this time, an RXI interrupt request is generated. Figure 15.30 shows a flowchart for reception. The sequence of receive operations can be performed automatically by specifying the DTC or DMAC to be activated with an RXI interrupt source. In a receive operation, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. If the RXI request is designated beforehand as a DTC or DMAC activation source, the DTC or DMAC will be activated by the RXI request, and transfer of the receive data will be carried out. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DTC or DMAC. If an error occurs in receive mode and the ORER or PER flag is set to 1, a transfer error interrupt (ERI) request will be generated, and so the error flag must be cleared to 0. In the event of an error, the DTC or DMAC is not activated and receive data is skipped. Therefore, receive data is transferred for only the specified number of bytes in the event of an error. Even when a parity error occurs in receive mode and the PER flag is set to 1, the data that has been received is transferred to RDR and can be read from there. Note: For details on receive operations in block transfer mode, refer to section 15.4, Operation in Asynchronous Mode.

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 906 of 1270 REJ09B0466-0100

15.7.8 Clock Output Control

When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE1 and CKE0 in SCR. At this time, the minimum clock pulse width can be made the specified width. Figure 15.31 shows the timing for fixing the clock output level. In this example, GM is set to 1, CKE1 is cleared to 0, and the CKE0 bit is controlled. Specified pulse width SCK CKE0 Specified pulse width Figure 15.31 Timing for Fixing Clock Output Level When turning on the power or switching between Smart Card interface mode and software standby mode, the following procedures should be followed in order to maintain the clock duty cycle. Powering On: To secure the clock duty cycle from power-on, the following switching procedure should be followed. 1. The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor to fix the potential. 2. Fix the SCK pin to the specified output level with the CKE1 bit in SCR. 3. Set SMR and SCMR, and switch to Smart Card mode operation. 4. Set the CKE0 bit in SCR to 1 to start clock output. When Changing from Smart Card Interface Mode to Software Standby Mode: 1. Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to the value for the fixed output state in software standby mode. 2. Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt transmit/receive operation. At the same time, set the CKE1 bit to the value for the fixed output state in software standby mode. 3. Write 0 to the CKE0 bit in SCR to halt the clock.

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 907 of 1270 REJ09B0466-0100 4. Wait for one serial clock cycle. During this interval, clock output is fixed at the specified level, with the duty cycle preserved. 5. Make the transition to the software standby state. When Returning to Smart Card Interface Mode from Software Standby Mode: 6. Exit the software standby state. 7. Write 1 to the CKE0 bit in SCR and output the clock. Signal generation is started with the normal duty cycle. Software standbyNormal operation Normal operation [6] Figure 15.32 Clock Halt and Restart Procedure

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 908 of 1270 REJ09B0466-0100

15.8 IrDA Operation

When the IrDA function is enabled with bit IrE in IrCR, the SCI_0 TxD0 and RxD0 signals are subjected to waveform encoding/decoding conforming to IrDA specification version 1.0 (IrTxD and IrRxD pins). By connecting these pins to an infrared transceiver/receiver, it is possible to implement infrared transmission/reception conforming to the IrDA specification version 1.0 system. In the IrDA specification version 1.0 system, communication is started at a transfer rate of 9600 bps, and subsequently the transfer rate can be varied as necessary. As the IrDA interface in this LSI does not include a function for varying the transfer rate automatically, the transfer rate setting must be changed by software. Figure 15.33 shows a block diagram of the IrDA function. IrDA Pulse encoder Pulse decoder TxD0/IrTxD RxD0/IrRxD SCI0 TxD RxD IrCR Figure 15.33 Block Diagram of IrDA

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 909 of 1270 REJ09B0466-0100 (1) Transmission In transmission, the output signal (UART frame) from the SCI is converted to an IR frame by the IrDA interface (see figure 15.34). When the serial data is 0, a high pulse of 3/16 the bit rate (interval equivalent to the width of one bit) is output (initial value). The high-level pulse can be varied according to the setting of bits IrCKS2 to IrCKS0 in IrCR. In the specification, the high pulse width is fixed at a minimum of 1.41 µs, and a maximum of (3/16 + 2.5%) × bit rate or (3/16 × bit rate) + 1.08 µs. When system clock φ is 20 MHz, 1.6 µs can be set for a high pulse width with a minimum value of 1.41 µs. When the serial data is 1, no pulse is output. UART frame Data IR frame Data 000 0 011 1 11 00 0 0 011 1 11 Start bit Transmit Receive Stop bit Start bit Stop bit Bit cycle Pulse width 1.6 µs to 3/16 bit cycle Figure 15.34 IrDA Transmit/Receive Operations

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 910 of 1270 REJ09B0466-0100 (2) Reception In reception, IR frame data is converted to a UART frame by the IrDA interface, and input to the SCI. When a high pulse is detected, 0 data is output, and if there is no pulse during a one-bit interval, 1 data is output. Note that a pulse shorter than the minimum pulse width of 1.41 µs will be identified as a 0 signal. (3) High Pulse Width Selection Table 15.12 shows possible settings for bits IrCKS2 to IrCKS0 (minimum pulse width), and operating frequencies of this LSI and bit rates, for making the pulse width shorter than 3/16 times the bit rate in transmission. Table 15.12 Settings of IrCKS2 to IrCKS0 Bits Bit Rate (bps) (Above)/Bit Period × 3/16 (µs) (Below) 2400 9600 19200 38400 57600 115200 Operating Frequency 8 100 100 100 100 100 100 9.8304 100 100 100 100 100 100 10 100 100 100 100 100 100 12 101 101 101 101 101 101 12.288 101 101 101 101 101 101 14 101 101 101 101 101 101 14.7456 101 101 101 101 101 101 16 101 101 101 101 101 101 16.9344 101 101 101 101 101 101 17.2032 101 101 101 101 101 101 18 101 101 101 101 101 101 19.6608 101 101 101 101 101 101 20 101 101 101 101 101 101 25 110 110 110 110 110  30 110 110 110 110 110  33 110 110 110 110 110  Legend: : A bit rate setting cannot be made on the SCI side.

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 911 of 1270 REJ09B0466-0100

15.9 Interrupt Sources

15.9.1 Interrupts in Normal Serial Communication Interface Mode

Table 15.13 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC or DMAC to perform data transfer. The TDRE flag is cleared to 0 automatically when data transfer is performed by the DTC or DMAC. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt request can activate the DTC or DMAC to perform data transfer. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DTC or DMAC. A TEI interrupt is generated when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI interrupt and a TXI interrupt are generated simultaneously, the TXI interrupt has priority for acceptance. However, note that if the TDRE and TEND flags are cleared simultaneously by the TXI interrupt routine, the SCI cannot branch to the TEI interrupt routine later.

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 912 of 1270 REJ09B0466-0100 Table 15.13 SCI Interrupt Sources Channel Name Interrupt Source Interrupt Flag DTC Activation DMAC Activation Priority ERI0 Receive Error ORER, FER, PER Not possible Not possible High RXI0 Receive Data Full RDRF Possible Possible TXI0 Transmit Data Empt y TDRE Possible Possible TEI0 Transmission End TEND Not possible Not possible ERI1 Receive Error ORER, FER, PER Not possible Not possible RXI1 Receive Data Full RDRF Possible Possible TXI1 Transmit Data Empt y TDRE Possible Possible TEI1 Transmission End TEND Not possible Not possible ERI2 Receive Error ORER, FER, PER Not possible Not possible RXI2 Receive Data Full RDRF Possible Not possible TXI2 Transmit Data Empty TDRE Possible Not possible TEI2 Transmission End TEND Not possible Not possible ERI3 Receive Error ORER, FER, PER Not possible Not possible RXI3 Receive Data Full RDRF Possible Not possible TXI3 Transmit Data Empty TDRE Possible Not possible TEI3 Transmission End TEND Not possible Not possible ERI4 Receive Error ORER, FER, PER Not possible Not possible RXI4 Receive Data Full RDRF Possible Not possible TXI4 Transmit Data Empty TDRE Possible Not possible TEI4 Transmission End TEND No t possible Not possible Low

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 913 of 1270 REJ09B0466-0100

15.9.2 Interrupts in Smart Card Interface Mode

Table 15.14 shows the interrupt sources in Smart Card interface mode. The transmit end interrupt (TEI) request cannot be used in this mode. Table 15.14 Interrupt Sources Channel Name Interrupt Source Interrupt Flag DTC Activation DMAC Activation Priority ERI0 Receive Error, detection ORER, PER, ERS Not possible Not possible High RXI0 Receive Data Full RDRF Possible Possible TXI0 Transmit Data Empt y TEND Possible Possible ERI1 Receive Error, detection ORER , PER, ERS Not possible Not possible RXI1 Receive Data Full RDRF Possible Possible TXI1 Transmit Data Empt y TEND Possible Possible ERI2 Receive Error, detection ORER , PER, ERS Not possible Not possible RXI2 Receive Data Full RDRF Possible Not possible TXI2 Transmit Data Empty TEND Possible Not possible ERI3 Receive Error, detection ORER , PER, ERS Not possible Not possible RXI3 Receive Data Full RDRF Possible Not possible TXI3 Transmit Data Empty TEND Possible Not possible ERI4 Receive Error, detection ORER , PER, ERS Not possible Not possible RXI4 Receive Data Full RDRF Possible Not possible TXI4 Transmit Data Empty TEND Possible Not possible Low In Smart Card interface mode, as in normal serial communication interface mode, transfer can be carried out using the DTC or DMAC. In transmit operations, the TDRE flag is also set to 1 at the same time as the TEND flag in SSR, and a TXI interrupt is generated. If the TXI request is designated beforehand as a DTC or DMAC activation source, the DTC or DMAC will be activated by the TXI request, and transfer of the transmit data will be carried out. The TDRE and TEND flags are automatically cleared to 0 when data transfer is performed by the DTC or DMAC. In the event of an error, the SCI retransmits the same data automatically. During this period, the TEND flag remains cleared to 0 and the DTC or DMAC is not activated. Therefore, the SCI and DTC or DMAC will automatically transmit the specified number of bytes in the event of an error, including retransmission. However, the ERS flag is not cleared automatically when an error occurs, and so the RIE bit should be set to 1 beforehand so that an ERI request will be generated in the event of an error, and the ERS flag will be cleared.

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 914 of 1270 REJ09B0466-0100 When performing transfer using the DTC or DMAC, it is essential to set and enable the DTC or DMAC before carrying out SCI setting. For details on the DTC or DMAC setting procedures, refer to section 9, Data Transfer Controller (DTC) or section 7, DMA Controller (DMAC). In receive operations, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. If the RXI request is designated beforehand as a DTC or DMAC activation source, the DTC or DMAC will be activated by the RXI request, and transfer of the receive data will be carried out. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DTC or DMAC. If an error occurs, an error flag is set but the RDRF flag is not. Consequently, the DTC or DMAC is not activated, but instead, an ERI interrupt request is sent to the CPU. Therefore, the error flag should be cleared.

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 915 of 1270 REJ09B0466-0100

15.10 Usage Notes

15.10.1 Module Stop Mode Setting

SCI operation can be disabled or enabled using the module stop control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 24, Power-Down Modes.

15.10.2 Break Detection and Processing

When framing error detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the PER flag may also be set. Note that, since the SCI continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again.

15.10.3 Mark State and Break Sending

When TE is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are determined by DR and DDR. This can be used to set the TxD pin to mark state or send a break during serial data transmission. To maintain the communication line at mark state until TE is set to 1, set both DDR and DR to 1. Since TE is cleared to 0 at this point, the TxD pin becomes an I/O port, and 1 is output from the TxD pin. To send a break during serial transmission, first set DDR to 1 and clear DR to 0, and then clear TE to 0. When TE is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin.

15.10.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)

Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0.

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 916 of 1270 REJ09B0466-0100

15.10.5 Relation between Writes to TDR and the TDRE Flag

The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1. Data can be written to TDR regardless of the state of the TDRE flag. However, if new data is written to TDR when the TDRE flag is cleared to 0, the data stored in TDR will be lost since it has not yet been transferred to TSR. It is therefore essential to check that the TDRE flag is set to 1 before writing transmit data to TDR.

15.10.6 Restrictions on Use of DMAC or DTC

  • When an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 φ clock cycles after TDR is updated by the DMAC or DTC. Incorrect operation may occur if the transmit clock is input within 4 φ clocks after TDR is updated. (Figure 15.35)
  • When RDR is read by the DMAC or DTC, be sure to set the activation source to the relevant SCI receive-data-full interrupt (RXI). t LSB Serial data SCK D1 D3 D4 D5D2 D6 D7 Note: When operating on an external clock, set t > 4 clocks. TDRE Figure 15.35 Example of Synchronous Transmission Using DTC

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 917 of 1270 REJ09B0466-0100

15.10.7 Operation in Case of Mode Transition

  • Transmission Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module stop mode or software standby mode transition. TSR, TDR, and SSR are reset. The output pin states in module stop mode or software standby mode depend on the port settings, and become high-level output after the relevant mode is cleared. If a transition is made during transmission, the data being transmitted will be undefined. When transmitting without changing the transmit mode after the relevant mode is cleared, transmission can be started by setting TE to 1 again, and performing the following sequence: SSR read → TDR write → TDRE clearance. To transmit with a different transmit mode after clearing the relevant mode, the procedure must be started again from initialization. Figure 15.36 shows a sample flowchart for mode transition during transmission. Port pin states during mode transition are shown in figures 15.37 and 15.38. Operation should also be stopped (by clearing TE, TIE, and TEIE to 0) before making a transition from transmission by DTC transfer to module stop mode or software standby mode transition. To perform transmission with the DTC after the relevant mode is cleared, setting TE and TIE to 1 will set the TXI flag and start DTC transmission.
  • Reception Receive operation should be stopped (by clearing RE to 0) before making a module stop mode or software standby mode transition. RSR, RDR, and SSR are reset. If a transition is made during reception, the data being received will be invalid. To continue receiving without changing the reception mode after the relevant mode is cleared, set RE to 1 before starting reception. To receive with a different receive mode, the procedure must be started again from initialization. Figure 15.39 shows a sample flowchart for mode transition during reception.

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 918 of 1270 REJ09B0466-0100 Read TEND flag in SSR TE = 0 Transition to software standby mode Exit from software standby mode Change operating mode? No All data transmitted? TEND = 1 Yes Yes Yes <Transmission> No No [1] [3] [2] TE = 1Initialization <Start of transmission> [1] Data being transmitted is interrupted. After exiting software standby mode, normal CPU transmission is possible by setting TE to 1, reading SSR, writing TDR, and clearing TDRE to 0, but note that if the DTC has been activated, the remaining data in DTCRAM will be transmitted when TE and TIE are set to 1. [2] If TIE and TEIE are set to 1, clear them to 0 in the same way. [3] Includes module stop mode. Figure 15.36 Sample Flowchart for Mode Transition during Transmission

Section 15 Serial Communication Interface (SCI, IrDA) Rev. 1.00 Sep. 19, 2008 Page 920 of 1270 REJ09B0466-0100 RE = 0 Transition to software standby mode Read receive data in RDR Read RDRF flag in SSR Exit from software standby mode Change operating mode? No RDRF = 1 Yes Yes <Reception> No [1] [2] RE = 1Initialization <Start of reception> [1] Receive data being received becomes invalid. [2] Includes module stop mode. Figure 15.39 Sample Flowchart for Mode Transition during Reception

C Bus Interface 2 (IIC2) Rev. 1.00 Sep. 19, 2008 Page 921 of 1270 REJ09B0466-0100 Section 16 I C Bus Interface 2 (IIC2) This LSI has a four-channel I C bus interface. The I C bus interface conforms to and provides a subset of the Philips I C bus (inter-IC bus) interface functions. The register configuration that controls the I C bus differs partly from the Philips configuration, however. Figure 16.1 shows a block diagram of the I C bus interface 2. Figure 16.2 shows an example of I/O pin connections to external circuits.

16.1 Features

  • Continuous transmission/reception Since the shift register, transmit data register, and receive data register are independent from each other, the continuous transmission/reception can be performed.
  • Start and stop conditions generated automatically in master mode
  • Selection of acknowledge output levels when receiving
  • Automatic loading of acknowledge bit when transmitting
  • Bit synchronization/wait function In master mode, the state of SCL is monitored per bit, and the timing is synchronized automatically. If transmission/reception is not yet possible, set the SCL to low until preparations are completed.
  • Six interrupt sources Transmit-data-empty (including slave-address match), transmit-end, receive-data-full (including slave-address match), arbitration lost, NACK detection, and stop condition detection
  • Direct bus drive Two pins, SCL and SDA pins function as NMOS open-drain outputs.

C Bus Interface 2 (IIC2) Rev. 1.00 Sep. 19, 2008 Page 922 of 1270 REJ09B0466-0100 SCL ICCRA Transfer clock generation circuit Address comparator Interrupt generator Interrupt request Bus state decision circuit Arbitration decision circuit Noise canceler Noise canceler Output control Output control Transmission/ reception control circuit ICCRB ICMR ICSR ICEIR ICDRR ICDRS ICDRT I2C bus control register A I2C bus control register B I2C mode register I2C status register I2C interrupt permission register I2C transmission data register I2C reception data register I2C bus shift register Slave address register Legend: ICCRA ICCRB ICMR ICSR ICIER ICDRT ICDRR ICDRS SAR SAR SDA Internal data bus Figure 16.1 Block Diagram of I C Bus Interface 2

C Bus Interface 2 (IIC2) Rev. 1.00 Sep. 19, 2008 Page 923 of 1270 REJ09B0466-0100 Vcc Vcc SCL in SCL out SCL SDA in SDA out SDA SCL (Master) (Slave 1) (Slave 2) SDA SCL in SCL out SCL SDA in SDA out SDA SCL in SCL out SCL SDA in SDA out SDA Figure 16.2 External Circuit Connections of I/O Pins

16.2 Input/Output Pins

Table 16.1 shows the pin configuration of the I C bus interface 2. Table 16.1 Pin Configuration Name Abbreviation I/O Function Serial clock pin SCL0 I/O IIC2_0 serial clock input/output Serial data pin SDA0 I/O IIC 2_0 serial data input/output Serial clock pin SCL1 I/O IIC2_1 serial clock input/output Serial data pin SDA1 I/O IIC 2_1 serial data input/output Serial clock pin SCL2 I/O IIC2_2 serial clock input/output Serial data pin SDA2 I/O IIC 2_2 serial data input/output Serial clock pin SCL3 I/O IIC2_3 serial clock input/output Serial data pin SDA3 I/O IIC 2_3 serial data input/output Note: The pin symbols are represented as SCL an d SDA; channel numbers are omitted in this manual.

C Bus Interface 2 (IIC2) Rev. 1.00 Sep. 19, 2008 Page 924 of 1270 REJ09B0466-0100

16.3 Register Descriptions

C bus interface has the following registers. Channel 0

  • I C bus control register A_0 (ICCRA_0)
  • I C bus control register B_0 (ICCRB_0)
  • I C bus mode register_0 (ICMR_0)
  • I C bus interrupt enable register_0 (ICIER_0)
  • I C bus status register_0 (ICSR_0)
  • Slave address register_0 (SAR_0)
  • I C bus transmit data register_0 (ICDRT_0)
  • I C bus receive data register_0 (ICDRR_0)
  • I C bus shift register_0 (ICDRS_0) Channel 1
  • I C bus control register A_1 (ICCRA_1)
  • I C bus control register B_1 (ICCRB_1)
  • I C bus mode register_1 (ICMR_1)
  • I C bus interrupt enable register_1 (ICIER_1)
  • I C bus status register_1 (ICSR_1)
  • Slave address register_1 (SAR_1)
  • I C bus transmit data register_1 (ICDRT_1)
  • I C bus receive data register_1 (ICDRR_1)
  • I C bus shift register_1 (ICDRS_1)

C Bus Interface 2 (IIC2) Rev. 1.00 Sep. 19, 2008 Page 925 of 1270 REJ09B0466-0100 Channel 2

  • I C bus control register A_2 (ICCRA_2)
  • I C bus control register B_2 (ICCRB_2)
  • I C bus mode register_2 (ICMR_2)
  • I C bus interrupt enable register_2 (ICIER_2)
  • I C bus status register_2 (ICSR_2)
  • Slave address register_2 (SAR_2)
  • I C bus transmit data register_2 (ICDRT_2)
  • I C bus receive data register_2 (ICDRR_2)
  • I C bus shift register_2 (ICDRS_2) Channel 3
  • I C bus control register A_3 (ICCRA_3)
  • I C bus control register B_3 (ICCRB_3)
  • I C bus mode register_3 (ICMR_3)
  • I C bus interrupt enable register_3 (ICIER_3)
  • I C bus status register_3 (ICSR_3)
  • Slave address register_3 (SAR_3)
  • I C bus transmit data register_3 (ICDRT_3)
  • I C bus receive data register_3 (ICDRR_3)
  • I C bus shift register_3 (ICDRS_3)

C Bus Interface 2 (IIC2) Rev. 1.00 Sep. 19, 2008 Page 926 of 1270 REJ09B0466-0100 16.3.1 I C Bus Control Register A (ICCRA) ICCRA is an 8-bit readable/writable register that enables or disables the I C bus interface, controls transmission or reception, and selects master or slave mode, transmission or reception, and transfer clock frequency in master mode. Bit Bit Name Initial Value R/W Description

7 ICE 0 R/W I

0: This module is halted. 1: This bit is enabled for transfer operations. (SCL and SDA pins are bus drive state.)

6 RCVD 0 R/W Reception Disable

This bit enables or disables the next operation when TRS is 0 and ICDRR is read. 0: Enables next reception 1: Disables next reception MST TRS R/W R/W Master/Slave Select Transmit/Receive Select When arbitration is lost in master mode, MST and TRS are both reset by hardware, causing a transition to slave receive mode. Modification of the TRS bit should be made between transfer frames. In addition, TRS is set to 1 automatically in slave receive mode if the seventh bit of the start condition matches the slave address set in SAR and the eighth bit is set to 1. Operating modes are described below according to MST and TRS combination. 00: Slave receive mode 01: Slave transmit mode 10: Master receive mode 11: Master transmit mode CKS3 CKS2 CKS1 CKS0 R/W R/W R/W R/W Transfer Clock Select 3 to 0 In the master mode, these bits should be set according to the necessary transfer rate (see table 16.2). In the slave mode, they are used to secure the data setup time in transmit mode. The data setup time is 10 tcyc if CKS3 is cleared to 0 and 20 tcyc if CKS3 is set to 1.

C Bus Interface 2 (IIC2) Rev. 1.00 Sep. 19, 2008 Page 927 of 1270 REJ09B0466-0100 Table 16.2 Transfer Rate Bit 3 Bit 2 Bit 1 Bit 0 Transfer Rate CKS3 CKS2 CKS1 CKS0 Clock φ = 8 MHz φ = 10 MHz φ = 20 MHz φ = 25 MHz φ = 33 MHz 0 φ/28 286 kHz 357 kHz 714 kHz * 893 kHz * 1179 kHz * 0 1 φ/40 200 kHz 250 kHz 500 kHz * 625 kHz * 825 kHz * 0 φ/48 167 kHz 208 kHz 417 kHz * 521 kHz * 688 kHz * 1 φ/64 125 kHz 156 kHz 313 kHz 391 kHz 516 kHz * 0 φ/168 47.6 kHz 59.5 kHz 119 kHz 149 kHz 196 kHz 0 1 φ/100 80.0 kHz 100 kHz 200 kHz 250 kHz 330 kHz 0 φ/112 71.4 kHz 89.3 kHz 179 kHz 223 kHz 295 kHz 1 φ/128 62.5 kHz 78.1 kHz 156 kHz 195 kHz 258 kHz 0 φ/56 143 kHz 179 kHz 357 kHz 446 kHz * 589 kHz * 0 1 φ/80 100 kHz 125 kHz 250 kHz 313 kHz 413 kHz * 0 φ/96 83.3 kHz 104 kHz 208 kHz 260 kHz 344 kHz 1 φ/128 62.5 kHz 78.1 kHz 156 kHz 195 kHz 258 kHz 1 φ/200 40.0 kHz 50.0 kHz 100 kHz 125 kHz 165 kHz 0 φ/224 35.7 kHz 44.6 kHz 89. 3 kHz 112 kHz 147 kHz 1 φ/256 31.3 kHz 39.1 kHz 78. 1 kHz 97.7 kHz 129 kHz Note: * Correct operation cannot be guaranteed sinc e the transfer rate is beyond the I2C bus interface specification (normal mode: maximum 100 kHz, high-speed mode: maximum 400 kHz).

C Bus Interface 2 (IIC2) Rev. 1.00 Sep. 19, 2008 Page 928 of 1270 REJ09B0466-0100 16.3.2 I C Bus Control Register B (ICCRB) ICCRB is an 8-bit readable/writable register that issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls reset in I C control. Bit Bit Name Initial Value R/W Description

7 BBSY 0 R/W Bus Busy

This bit enables to confirm whether the I C bus is occupied or released and to issue start and stop conditions in master mode. This bit is set to 1 when the SDA level changes from high to low under the condition of SCL = high, assuming that the start condition has been issued. This bit is cleared to 0 when the SDA level changes from low to high under the condition of SCL = high, assuming that the stop condition has been issued. Write 1 to BBSY and 0 to SCP to issue a start condition. Follow this procedure when also re- transmitting a start condition. Write 0 to BBSY and 0 to SCP to issue a stop condition. To issue a start/stop condition, use the MOV instruction.

6 SCP 1 R/W Start Condition/Stop Condition Prohibit

The SCP bit controls the issue of start/stop conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP. This bit is always read as 1. If 1 is written, the data is not stored. 5 SDAO 1 R This bit monitors SDA output level. When reading and SDA0 is 1, the SDA pin outputs high. When reading and SDA0 is 0, the SDA pin outputs low. The write value should always be 1. 4  1 R/W Reserved The write value should always be 1. 3 SCLO 1 R This bit monitors SCL output level. When reading and SCLO is 1, the SCL pin outputs high. When reading and SCLO is 0, the SCL pin outputs low. 2  1  Reserved This bit is always read as 1.

C Bus Interface 2 (IIC2) Rev. 1.00 Sep. 19, 2008 Page 929 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description

1 IICRST 0 R/W IIC Control Part Reset

This bit resets control parts except for I C registers. If this bit is set to 1 when hang-up is occurred because of communication failure during I C operation, I C control part can be reset without setting ports and initializing registers. 0  1  Reserved This bit is always read as 1. 16.3.3 I C Bus Mode Register (ICMR) ICMR controls the master mode wait and selects the number of transfer bits. Bit Bit Name Initial Value R/W Description 7  0  Reserved The write value should always be 0.

6 WAIT 0 R/W Wait Insertion

This bit selects whether to insert a wait after data transfer except for the acknowledge bit. When WAIT is set to 1, after the fall of the clock for the final data bit, low period is extended for two transfer clocks. If WAIT is cleared to 0, data and acknowledge bits are transferred consecutively with no wait inserted. The setting of this bit is invalid in slave mode. 5, 4  All 1  Reserved These bits are always read as 1.

3 BCWP 1 R/W BC Write Protect

This bit controls the BC2 to BC0 modifications. When modifying BC2 to BC0, this bit should be cleared to 0 and use the MOV instruction. 0: When writing, values of BC2 to BC0 are set. 1: When reading, 1 is always read. When writing, settings of BC2 to BC0 are invalid.

C Bus Interface 2 (IIC2) Rev. 1.00 Sep. 19, 2008 Page 930 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description BC2 BC1 BC0 R/W R/W R/W Bit Counter 2 to 0 These bits specify the number of bits to be transferred next. When read, the remaining number of transfer bits is indicated. The data is transferred with one addition acknowledge bit. Bit BC2 to BC0 settings should be made during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000, the setting should be made while the SCL line is low. The value returns to 000 at the end of a data transfer, including the acknowledge bit. 000: 9 bits 001: 2 bits 010: 3 bits 011: 4 bits 100: 5 bits 101: 6 bits 110: 7 bits 111: 8 bits

C Bus Interface 2 (IIC2) Rev. 1.00 Sep. 19, 2008 Page 931 of 1270 REJ09B0466-0100 16.3.4 I C Bus Interrupt Enable Register (ICIER) ICIER is an 8-bit readable/writable register that enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits to be received. Bit Bit Name Initial Value R/W Description When the TDRE bit in ICSR is set to 1, this bit enables or disables the transmit data empty interrupt (TXI). 0: Transmit data empty interrupt request (TXI) is disabled. 1: Transmit data empty interrupt request (TXI) is enabled.

6 TEIE 0 R/W Transmit End Interrupt Enable

This bit enables or disables the transmit end interrupt (TEI) at the rising of the ninth clock while the TDRE bit in ICSR is 1. TEI can be canceled by clearing the TEND bit or the TEIE bit to 0. 0: Transmit end interrupt request (TEI) is disabled. 1: Transmit end interrupt request (TEI) is enabled.

5 RIE 0 R/W Receive Interrupt Enable

This bit enables or disables the receive data full interrupt request (RXI) when a received data is transferred from ICDRS to ICDRR and the RDRF bit in ICSR is set to 1. RXI can be canceled by clearing the RDRF or RIE bit to 0. 0: Receive data full interrupt request (RXI) is disabled. 1: Receive data full interrupt request (RXI) is enabled.

C Bus Interface 2 (IIC2) Rev. 1.00 Sep. 19, 2008 Page 932 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description

4 NAKIE 0 R/W NACK Receive Interrupt Enable

This bit enables or disables the NACK receive interrupt request (NAKI) when the NACKF and AL bits in ICSR are set to 1. NAKI can be canceled by clearing the NACKF, AL, or NAKIE bit to 0. 0: NACK receive interrupt request (NAKI) is disabled. 1: NACK receive interrupt request (NAKI) is enabled.

3 STIE 0 R/W Stop Condition Detection Interrupt Enable

0: Stop condition detection interrupt request (STPI) is disabled. 1: Stop condition detection interrupt request (STPI) is enabled.

2 ACKE 0 R/W Acknowledge Bit Judgement Select

0: The value of the acknowledge bit is ignored, and continuous transfer is performed. 1: If the acknowledge bit is 1, continuous transfer is interrupted.

1 ACKBR 0 R Receive Acknowledge

In transmit mode, this bit stores the acknowledge data that are returned by the receive device. This bit cannot be modified. 0: Receive acknowledge = 0 1: Receive acknowledge = 1

0 ACKBT 0 R/W Transmit Acknowledge

In receive mode, this bit specifies the bit to be sent at the acknowledge timing. 0: 0 is sent at the acknowledge timing. 1: 1 is sent at the acknowledge timing.

C Bus Interface 2 (IIC2) Rev. 1.00 Sep. 19, 2008 Page 933 of 1270 REJ09B0466-0100 16.3.5 I C Bus Status Register (ICSR) ICSR is an 8-bit readable/writable register that performs confirmation of interrupt request flags and status. Bit Bit Name Initial Value R/W Description

7 TDRE 0 R/W Transmit Data Register Empty

[Setting condition]

  • When data is transferred from ICDRT to ICDRS and ICDRT becomes empty.
  • When TRS has been set.
  • When a start condition (including retransmission) has been issued.
  • When a transition from the receive mode to the transmit mode has been made in the slave mode.
  • [Clearing conditions]
  • When 0 is written in TDRE after reading TDRE = 1.
  • When data is written in ICDRT.

6 TEND 0 R/W Transmit End

[Setting condition]

  • When the ninth clock of SCL is rose while the TDRE flag is 1. [Clearing conditions]
  • When 0 is written in TEND after reading TEND = 1.
  • When data is written in ICDRT.

5 RDRF 0 R/W Receive Data Register Full

[Setting condition]

  • When a received data is transferred from ICDRS to ICDRR. [Clearing conditions]
  • When 0 is written in RDRF after reading RDRF = 1.
  • When data is read from ICDRR.

C Bus Interface 2 (IIC2) Rev. 1.00 Sep. 19, 2008 Page 934 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description

4 NACKF 0 R/W No Acknowledge Detection Flag

[Setting condition]

  • When no acknowledge is detected from the receive device in transmission while the ACKE bit in ICIER is 1. [Clearing condition]
  • When 0 is written in NACKF after reading NACKF = 1.

3 STOP 0 R/W Stop Condition Detection Flag

[Setting condition]

  • In master mode, when a stop condition is detected after frame transfer.
  • In slave mode, when a stop condition is detected after the general call address or the first byte slave address, next to detection of start condition, accords with the address set in SAR. [Clearing condition]
  • When 0 is written in STOP after reading STOP =

2 AL 0 R/W Arbitration Lost Flag

This flag indicates that arbitration was lost in master mode. When two or more master devices attempt to seize the bus at nearly the same time, if the I C bus interface detects data differing from the data it sent, it sets AL to 1 to indicate that the bus has been taken by another master. [Setting conditions]

  • If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode.
  • When the SDA pin outputs high in master mode while a start condition is detected. [Clearing condition]
  • When 0 is written in AL after reading AL =1.

C Bus Interface 2 (IIC2) Rev. 1.00 Sep. 19, 2008 Page 935 of 1270 REJ09B0466-0100 Bit Bit Name Initial Value R/W Description

1 AAS 0 R/W Slave Addr ess Recognition Flag

In slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR. [Setting condition]

  • When the slave address is detected in slave receive mode.
  • When the general call address is detected in slave receive mode. [Clearing condition]
  • When 0 is written in AAS after reading AAS=1

0 ADZ 0 R/W General Call Address Recognition Flag

This bit is valid in slave receive mode. [Setting condition]

  • When the general call address is detected in slave receive mode. [Clearing conditions]
  • When 0 is written in ADZ after reading ADZ=1.

16.3.6 Slave Address Register (SAR)

SAR is an 8-bit readable/writable register that sets slave address. When the chip is in slave mode, if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device. Bit Bit Name Initial Value R/W Description 7 to 1 SVA6 to SVA0 All 0 R/W Slave Address 6 to 0 These bits set a unique address in bits SVA6 to SVA0, differing from the addresses of other slave devices connected to the I C bus. 0  0 R/W Reserved This bit is readable/writable. The write value should always be 0.

C Bus Interface 2 (IIC2) Rev. 1.00 Sep. 19, 2008 Page 936 of 1270 REJ09B0466-0100 16.3.7 I C Bus Transmit Data Register (ICDRT) ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the space in the I C bus shift register (ICDRS), it transfers the transmit data which is written in ICDRT to ICDRS and starts transferring data. If the next transfer data is written to ICDRT during transferring data of ICDRS, continuous transfer is possible. The initial value of ICDRT is H'FF. 16.3.8 I C Bus Receive Data Register (ICDRR) ICDRR is an 8-bit register that stores the receive data. When data of one byte is received, ICDRR transfers the received data from ICDRS to ICDRR and the next data can be received. ICDRR is a receive-only register, therefore the CPU cannot be written to this register. The initial value of ICDRR is H'FF. 16.3.9 I C Bus Shift Register (ICDRS) ICDRS is a register that is used to transfer/receive data. In transmission, data is transferred from ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred from ICDRS to ICDRR after data of one byte is received. This register cannot be read from the CPU.

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16.4 Operation

16.4.1 I C Bus Format Figure 16.3 shows the I C bus formats. Figure 16.4 shows the I C bus timing. The first frame following a start condition always consists of 8 bits. S SLA R/ W A DATA A A/ A P 11 1 1n7 1 m (a) I2C bus format (b) I2C bus format (start condition retransmission) n: transfer bit count (n = 1 to 8) m: transfer frame count (m ≥ 1) S SLA R/ W A DATA 1 n17 1 m1 S SLA R/ W A DATA A/ A P 11 1 n27 1 m2 1 11 A/A n1 and n2: transfer bit count (n1 and n2 = 1 to 8) m1 and m2: transfer frame count (m1 and m2 ≥ 1) Figure 16.3 I C Bus Formats SDA SCL S 1-7 SLA R/W A 1-7 DATA 89 1 - 7 89 A DATA P A Figure 16.4 I C Bus Timing

C Bus Interface 2 (IIC2) Rev. 1.00 Sep. 19, 2008 Page 938 of 1270 REJ09B0466-0100 Legend: S: Start condition. The master device drives SDA from high to low while SCL is high. SLA: Slave address R/W: Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0. A: Acknowledge. The receiving device drives SDA to low. DATA: Transferred data P: Stop condition. The master device drives SDA from low to high while SCL is high.

16.4.2 Master Transmit Operation

C bus format master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The transmission procedure and operations in master transmit mode are described below. 1. Set the ICE bit in ICCRA to 1. Set the WAIT bit in ICMR and the CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) 2. Read the BBSY flag in ICCRB to confirm that the bus is free. Set the MST and TRS bits in ICCRA to select master transmit mode. Then, write 1 to BBSY and 0 to SCP using MOV instruction. (Start condition issued) This generates the start condition. 3. After confirming that TDRE in ICSR has been set, write the transmit data (the first byte data show the slave address and R/W) to ICDRT. After this, when TDRE is cleared to 0, data is transferred from ICDRT to ICDRS. TDRE is set again. 4. When transmission of one byte data is completed while TDRE is 1, TEND in ICSR is set to 1 at the rise of the 9th transmit clock pulse. Read the ACKBR bit in ICIER, and confirm that the slave device has been selected. Then, write second byte data to ICDRT, and clear TDRE and TEND. When ACKBR is 1, the slave device has not been acknowledged, so issue the stop condition. To issue the stop condition, write 0 to BBSY and SCP using MOV instruction. SCL is fixed low until the transmit data is prepared or the stop condition is issued. 5. The transmit data after the second byte is written to ICDRT every time TDRE is set, thus clearing TDRE. 6. Write the number of bytes to be transmitted to ICDRT. Wait until TEND is set (the end of last byte data transmission) while TDRE is 1, or wait for NACK (NACKF in ICSR = 1) from the receive device while ACKE in ICIER is 1. Then, issue the stop condition to clear TEND or NACKF. 7. When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode.

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16.4.3 Master Receive Operation

In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. The reception procedure and operations in master receive mode are shown below. 1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCRA to 0 to switch from master transmit mode to master receive mode. Then, clear the TDRE bit to 0. 2. When ICDRR is read (dummy data read), reception is started, and the receive clock is output, and data received, in synchronization with the internal clock. The master device outputs the level specified by ACKBT in ICIER to SDA, at the 9th receive clock pulse. 3. After the reception of first frame data is completed, the RDRF bit in ICST is set to 1 at the rise of 9th receive clock pulse. At this time, the received data is read by reading ICDRR. 4. The continuous reception is performed by reading ICDRR and clearing RDRF to 0 every time RDRF is set. If 8th receive clock pulse falls after reading ICDRR by the other processing while RDRF is 1, SCL is fixed low until ICDRR is read. 5. If next frame is the last receive data, set the RCVD bit in ICCR1 to 1 before reading ICDRR. This enables the issuance of the stop condition after the next reception. 6. When the RDRF bit is set to 1 at rise of the 9th receive clock pulse, read ICDRR. Then, clear RCVD. 7. When the STOP bit in ICSR is set to 1, read ICDRR and clear RDRF to 0. Then clear the RCVD bit to 0. 8. The operation returns to the slave receive mode.

C Bus Interface 2 (IIC2) Rev. 1.00 Sep. 19, 2008 Page 941 of 1270 REJ09B0466-0100 TDRE TEND ICDRS ICDRR [1] Clear TDRE after clearing TEND and TRS [2] Read ICDRR (dummy read) [3] Read ICDRR A 21 34567899 A TRS RDRF SCL (master output) SDA (master output) SDA (slave output) Bit 7 Master transmit mode Master receive mode Bit 7Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 User processing Data 1 Data 1 Figure 16.7 Master Receive Mode Operation Timing 1

C Bus Interface 2 (IIC2) Rev. 1.00 Sep. 19, 2008 Page 942 of 1270 REJ09B0466-0100 RDRF RCVD ICDRS ICDRR Data n-1 Data n Data nData n-1 [5] Read ICDRR after setting RCVD. [6] Issue stop condition [7] Read ICDRR and clear RCVD [8] Set slave receive mode 19 23456789 A A/A SCL (master output) SDA (master output) SDA (slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 User processing Figure 16.8 Master Receive Mode Operation Timing 2

16.4.4 Slave Transmit Operation

In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. The transmission procedure and operations in slave transmit mode are described below. 1. Set the ICE bit in ICCRA to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0 bits in ICCRA to 1. (Initial setting) Set the MST and TRS bits in ICCRA to select slave receive mode, and wait until the slave address matches. 2. When the slave address matches in the first frame following detection of the start condition, the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th clock pulse. At this time, if the 8th bit data (R/W) is 1, the TRS in ICCRA and TDRE in ICSR are set to 1, and the mode changes to slave transmit mode automatically. The continuous transmission is performed by clearing TDRE after writing transmit data to ICDRT every time TDRE is set. 3. If TDRE is set after writing last transmit data to ICDRT, wait until TEND in ICSR is set to 1, with TDRE = 1. When TEND is set, clear TEND. 4. Clear TRS for the end processing, and read ICDRR (dummy read). SCL is free. 5. Clear TDRE.

C Bus Interface 2 (IIC2) Rev. 1.00 Sep. 19, 2008 Page 943 of 1270 REJ09B0466-0100 TDRE TEND ICDRS ICDRR A 21 34567899 A TRS ICDRT SCL (master output) Slave receive mode Slave transmit mode SDA (master output) SDA (slave output) SCL (slave output) Bit 7 Bit 7 Data 1 Data 1 Data 2 Data 3 Data 2 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 [2] Write data to ICDRT (data 1). [2] Write data to ICDRT (data 2). [2] Write data to ICDRT (data 3).User processing Figure 16.9 Slave Transmit Mode Operation Timing 1

C Bus Interface 2 (IIC2) Rev. 1.00 Sep. 19, 2008 Page 944 of 1270 REJ09B0466-0100 TDRE Data n TEND ICDRS ICDRR 19 2345678 9 TRS ICDRT A SCL (master output) SDA (master output) SDA (slave output) SCL (slave output) Bit 7 Slave transmit mode Slave receive mode Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 [3] Clear TEND [5] Clear TDRE [4] Read ICDRR (dummy read) after clearing TRS User processing A/A Figure 16.10 Slave Transmit Mode Operation Timing 2

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16.4.5 Slave Receive Operation

In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The reception procedure and operations in slave receive mode are described below. 1. Set the ICE bit in ICCRA to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0 bits in ICCRA to 1. (Initial setting) Set the MST and TRS bits in ICCRA to select slave receive mode, and wait until the slave address matches. 2. When the slave address matches in the first frame following detection of the start condition, the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read) and RDRF is cleared. (Since the read data show the slave address and R/W, it is not used.) 3. Clear RDRF after reading ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be returned to the master device, is reflected to the next transmit frame. 4. The last byte data is read by reading ICDRR.

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16.4.6 Noise Canceler

The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 16.13 shows a block diagram of the noise canceler circuit. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. If they do not agree, the previous value is held. C QD March detector Internal SCL or SDA signal SCL or SDA input signal Sampling clock Sampling clock System clock period Latch Latch C QD Figure 16.13 Block Diagram of Noise Canceler

16.4.7 Example of Use

Flowcharts in respective modes that use the I C bus interface are shown in figures 16.14 to 16.17.

C Bus Interface 2 (IIC2) Rev. 1.00 Sep. 19, 2008 Page 948 of 1270 REJ09B0466-0100 BBSY=0 ?No TEND=1 ?No Yes Start [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [13] [14] [15] Initialize Set MST = 1 and TRS = 1 in ICCRA. Write BBSY = 1 and SCP = 0. Write transmit data in ICDRT Write BBSY = 0 and SCP = 0 Set MST = 0 and TRS = 0 in ICCRA Read BBSY in ICCRB Read TEND in ICSR Read ACKBR in ICIER Master receive mode Yes ACKBR=0 ? Write transmit data in ICDRT Read TDRE in ICSR Read TEND in ICSR Clear TEND in ICSR Read STOP in ICSR Clear TDRE in ICSR End Write transmit data in ICDRT Transmit mode? No Yes TDRE=1 ? Final byte? STOP=1 ? No No No No No Yes Yes TEND=1 ? Yes Yes Yes [1] Test the status of the SCL and SDA lines. [2] Select master transmit mode. [3] Start condition issuance. [4] Select transmit data for the first byte (slave address + R/W). [5] Wait for 1 byte to be transmitted. [6] Test the acknowledge bit, transferred from the specified slave device. [7] Set transmit data for the second and subsequent data (except for the final byte). [8] Wait for ICDRT empty. [9] Set the final byte of transmit data. [10] Wait for the completion of transmission for the final byte. [11] Clear TEND flag. [12] Clear STOP flag. [13] Stop condition issuance. [14] Wait for the generation of the stop condition. [15] Set slave receive mode. Clear TDRE. [12]Clear STOP in ICSR Figure 16.14 Sample Flowchart for Master Transmit Mode

C Bus Interface 2 (IIC2) Rev. 1.00 Sep. 19, 2008 Page 949 of 1270 REJ09B0466-0100 No Yes RDRF=1 ?No Yes RDRF=1 ? Last receive - 1? Mater receive mode Clear TEND in ICSR Set TRS = 0 (ICCRA) Clear TDRE of ICSR Set ACKBT = 0 (ICIER) Dummy read ICDRR Read RDRF in ICSR Read ICDRR Set ACKBT = 1 (ICIER) Set RCVD = 1 (ICCRA) Read ICDRR Read RDRF in ICSR Write BBSY = 0 and SCP = 0 Read STOP of ICSR Read ICDRR Set RCVD = 0 (ICCRA) Set MST = 0 (ICCRA) End Note: * Ensure that no interrupts are received while steps [1] through [3] are being processed. Additional information: If only one byte is received, steps [2] through [6] are omitted following step [1], and processing jumps to step [7]. Step [8] is ICDDR dummy read. No Yes STOP=1 ?No Yes [1] Clear TEND, select master receive mode, and then clear TDRE. * [2] Set acknowledge to the transmitting device. * [3] Dummy read ICDDR. * [4] Wait for 1 byte to be received. [5] Check if the (last receive - 1). [6] Read the receive data. [7] Set acknowledge of the final byte. Disable continuous receive (RCVD = 1). [8] Read receive data of (final byte - 1). [9] Wait for the final byte to be received. [10] Clear STOP flag. [11] Stop condition issuance. [12] Wait for the generation of stop condition. [13] Read the receive data of the final byte. [14] Clear RCVD to 0. [15] Set slave receive mode. [1] [2] [3] [4] [5] [6] [7] [8] Clear STOP in ICSR [10] [9] [11] [12] [13] [14] [15] Figure 16.15 Sample Flowchart for Master Receive Mode

C Bus Interface 2 (IIC2) Rev. 1.00 Sep. 19, 2008 Page 950 of 1270 REJ09B0466-0100 TDRE=1 ? Yes Yes No Slave transmit mode Clear AAS in ICSR Write transmit data in ICDRT Read TDRE in ICSR End of transmission? Write transmit data in ICDRT Read TEND in ICSR Clear TEND in ICSR Set TRS=0 in ICCRA Dummy read ICDRR Clear TDRE in ICSR End [1] Clear the flag AAS. [2] Set transmit data for ICDRT (except for the last data). [3] Wait for ICDRT empty. [4] Set the last byte of the transmit data. [5] Wait the transmission end of the last byte. [6] Clear the flag TEND. [7] Set slave receive mode. [8] Dummy read ICDRR to release the SCL line. [9] Clear the flag TDRE. No No Yes TEND=1 ? [1] [2] [3] [4] [5] [6] [7] [8] [9] Figure 16.16 Sample Flowchart for Slave Transmit Mode

C Bus Interface 2 (IIC2) Rev. 1.00 Sep. 19, 2008 Page 951 of 1270 REJ09B0466-0100 No Yes RDRF=1 ?No Yes RDRF=1 ? Last receive - 1? Slave receive mode Clear AAS in ICSR Set ACKBT=0 in ICIER Dummy read ICDRR Read RDRF in ICSR Read ICDRR Set ACKBT=1 in ICIER Read ICDRR Read RDRF in ICSR Read ICDRR End No Yes [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [1] Clear the flag AAS. [2] Set the acknowledge for the transmit device. [3] Dummy read ICDRR. [4] Wait the reception end of 1 byte. [5] Check if the (last receive - 1). [6] Read the received data. [7] Set the acknowledge for the last byte. [8] Read the received data of the (last byte - 1). [9] Wait the reception end of the last byte. [10] Read the received data of the last byte. Additional information: If only one byte is received, steps [2] through [6] are omitted following step [1], and processing jumps to step [7]. Step [8] is ICDRR dummy read. Figure 16.17 Sample Flowchart for Slave Receive Mode

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16.5 Interrupt Request

There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK detection, STOP recognition, and arbitration lost. Table 16.3 shows the contents of each interrupt request. Table 16.3 Interrupt Requests Interrupt Request Abbreviat ion Interrupt Condition Transmit Data Empty TXI (TDRE=1) • (TIE=1) Transmit End TEI (TEND=1) • (TEIE=1) Receive Data Full RXI (RDRF=1) • (RIE=1) STOP Recognition STPI (STOP=1) • (STIE=1) NACK Detection Arbitration Lost NAKI {(NACKF=1)+(AL=1)} • (NAKIE=1) Interrupt exception handling is performed when the interrupt conditions listed in table 16.3 are set to 1 and the CPU is ready to accept interrupts. During exception handling, the interrupt sources should be cleared. Note, however, that TDRE and TEND are automatically cleared by writing transmit data to ICDRT, and RDRF is automatically cleared by reading data from ICDRR. In particular, if TDRE is set at the same time transmit data is written to ICDRT, and then TDRE is cleared again, an extra byte of data may be transmitted.

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16.6 Bit Synchronous Circuit

In master mode,

  • When SCL is driven to low by the slave device
  • When the rising speed of SCL is lower by the load of the SCL line (load capacitance or pull-up resistance) This module has a possibility that high level period may be short in the two states described above. Therefore it monitors SCL and communicates by bit with synchronization. Figure 16.18 shows the timing of the bit synchronous circuit and table 16.4 shows the time when SCL output changes from low to Hi-Z then SCL is monitored. SCL VIH SCL monitor timing reference clock Internal SCL Figure 16.18 Timing of the Bit Synchronous Circuit Table 16.4 Time for monitoring SCL CKS3 CKS2 Time for monitoring SCL 0 7.5 tcyc 0 1 19.5 tcyc 0 17.5 tcyc 1 1 41.5 tcyc

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16.7 Usage Notes

  1. Issue (retransmit) the start/stop conditions after the fall of the ninth clock is confirmed. Check SCLO in the I C control register B (IICRB) to confirm the fall of the ninth clock. When the start/stop conditions are issued (retransmitted) at the specific timing under the following condition (i) or (ii), such conditions may not be output successfully. This does not occur in other cases. (i) When the rising of SCL falls behind the time specified in section 16.6, Bit Synchronous Circuit, by the load of the SCL bus (load capacitance or pull-up resistance) (ii) When the bit synchronous circuit is activated by extending the low period of eighth and ninth clocks, that is driven by the slave device 2. Control WAIT in the I C bus mode register (ICMR) to be set to 0. When WAIT is set to 1, and SCL is driven low for two or more transfer clocks by the slave device at the eighth and ninth clocks, the high period of ninth clock may be shortened. This does not occur in other cases.

Rev. 1.00 Sep. 19, 2008 Page 955 of 1270 REJ09B0466-0100 Section 17 A/D Converter This LSI includes two units (units 0 and 1) of successive approximation type 10-bit A/D converter. In the H8S/2426 group and H8S/2426R group, the A/D converter units 0 and 1 allow up to eight analog input channels to be selected. In the H8S/2424 group, unit 0 allows up to eight analog input channels to be selected while unit 1 allows up to two channels. Figures 17.1 and 17.2 show block diagrams of the A/D converter units 0 and 1, respectively.

17.1 Features

  • 10-bit resolution
  • Input channels: H8S/2426 group and H8S/2426R group: Eight channels (total of 16 channels for the two units) H8S/2424 group: Eight channels for unit 0 and two channels for unit 1 (total of 10 channels for the two units)
  • Conversion cycle: 64 cycles or 40 cycles (A/D conversion clock)
  • Two kinds of operating modes  Single mode: Single-channel A/D conversion  Scan mode: Continuous A/D conversion on 1 to 4 channels, or 1 to 8 channels*
  • Separate A/D conversion clock specifiable for each unit (Pφ, Pφ/2, Pφ/4, or Pφ/8)
  • Eight data registers for A/D converter unit 0 and eight data registers for unit 1* (total of 16 data registers for the two units) Results of A/D conversion are held in a 16-bit data register for each channel.
  • Sample and hold functionality
  • Three types of conversion start Conversion can be started by software, a conversion start trigger by the 16-bit timer pulse unit (TPU) or 8-bit timer (TMR), or an external trigger signal.
  • Interrupt source A/D conversion end interrupt (ADI) request can be generated.
  • Module stop state specifiable Notes: 1. Continuous A/D conversion on 1 to 2 channels in the H8S/2424 group. 2. Two data registers for unit 1 (total of ten data registers for the two units) in the H8S/2424 group.

Rev. 1.00 Sep. 19, 2008 Page 956 of 1270 REJ09B0466-0100 Module data bus Control circuit Internal data bus 10-bit A/D Comparator Sample-and- hold circuit ADI0 interrupt signal Bus interface AVCC Vref AVSS AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADTRG0-A Conversion start trigger from TPU (units 0, 1) or TMR Successive approximation register Multiplexer [Legend] ADCR_0: A/D control register_0 ADCSR_0: A/D control/status register_0 ADDRA_0: A/D data register A_0 ADDRB_0: A/D data register B_0 ADDRC_0: A/D data register C_0 ADDRD_0: A/D data register D_0 ADDRE_0: A/D data register E_0 ADDRF_0: A/D data register F_0 ADDRG_0: A/D data register G_0 ADDRH_0: A/D data register H_0 ADDRA_0 ADDRB_0 ADDRC_0 ADDRD_0 ADDRE_0 ADDRF_0 ADDRG_0 ADDRH_0 ADCSR_0 ADCR_0 ADTRG0-B Figure 17.1 Block Diagram of A/D Converter Unit 0 (AD_0)

Rev. 1.00 Sep. 19, 2008 Page 957 of 1270 REJ09B0466-0100 Module data bus Control circuit Internal data bus 10-bit A/D Comparator Sample-and- hold circuit ADI1 interrupt signal Bus interface AVCC Vref AVSS Conversion start trigger from TPU (units 0, 1) Note: * The H8S/2424 group does not have these pins. Successive approximation register Multiplexer [Legend] ADCR_1: A/D control register_1 ADCSR_1: A/D control/status register_1 ADDRA_1: A/D data register A_1 ADDRB_1: A/D data register B_1 ADDRC_1: A/D data register C_1 ADDRD_0: A/D data register D_1 ADDRE_0: A/D data register E_1 ADDRF_0: A/D data register F_1 ADDRG_0: A/D data register G_1 ADDRH_0: A/D data register H_1 ADDRA_1 ADDRB_1 ADDRC_1 ADDRD_1 ADDRE_1 ADDRF_1 ADDRG_1 ADDRH_1 ADCSR_1 ADCR_1 ADTRG1-A AN8* AN9* AN10* AN11* AN12 AN13 AN14* AN15* Figure 17.2 Block Diagram of A/D Converter Unit 1 (AD_1)

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17.2 Input/Output Pins

Tables 17.1 and 17.2 show the pin configuration of the A/D converter. Table 17.1 Pin Configuration (H8S/2426 Group and H8S/2426R Group) Unit Symbol Pin Name Symbol I/O Function Analog input pin 0 AN0 Input Analog input pin 1 AN1 Input Analog input pin 2 AN2 Input Analog input pin 3 AN3 Input Analog input pin 4 AN4 Input Analog input pin 5 AN5 Input Analog input pin 6 AN6 Input Analog input pin 7 AN7 Input Analog inputs A/D external trigger input pin 0_A ADTRG0-A Input External trigger input pin 0_A for starting A/D conversion*

0 AD_0

input pin 0_B ADTRG0-B Input External trigger input pin 0_B for starting A/D conversion* Analog input pin 8 AN8 Input Analog input pin 9 AN9 Input Analog input pin 10 AN10 Input Analog input pin 11 AN11 Input Analog input pin 12 AN12 Input Analog input pin 13 AN13 Input Analog input pin 14 AN14 Input Analog input pin 15 AN15 Input Analog inputs 1 AD_1 A/D external trigger input pin 1 ADTRG1 Input External trigger input pin A for starting A/D conversion Analog power supply pin AV CC Input Analog block power supply Analog ground pin AV SS Input Analog block ground Common Reference voltage pin Vref Input A/D conversion reference voltage Note: * Selectable by setting of the TRGS 1, TRGS0, and EXTRGS bits in ADCR.

Rev. 1.00 Sep. 19, 2008 Page 959 of 1270 REJ09B0466-0100 Table 17.2 Pin Configuration (H8S/2424 Group) Unit Abbr. Pin Name Symbol I/O Function Analog input pin 0 AN0 Input Analog input pin 1 AN1 Input Analog input pin 2 AN2 Input Analog input pin 3 AN3 Input Analog input pin 4 AN4 Input Analog input pin 5 AN5 Input Analog input pin 6 AN6 Input Analog input pin 7 AN7 Input Analog inputs A/D external trigger input pin 0_A ADTRG0-A Input External trigger input pin 0_A for starting A/D conversion* input pin 0_B ADTRG0-B Input External trigger input pin 0_B for starting A/D conversion* Analog input pin 12 AN12 Input Analog input pin 13 AN13 Input Analog inputs 1 AD_1 A/D external trigger input pin 1 ADTRG1 Input External trigger input pin A for starting A/D conversion Analog power supply pin AV CC Input Analog block power supply Analog ground pin AV SS Input Analog block ground Common Reference voltage pin Vref Input A/D conversion reference voltage Note: * Selectable by setting of the TRGS 1, TRGS0, and EXTRGS bits in ADCR.

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17.3 Register Descriptions

The A/D converter has the following registers. Unit 0 (A/D_0) registers:

  • A/D data register A_0 (ADDRA_0)
  • A/D data register B_0 (ADDRB_0)
  • A/D data register C_0 (ADDRC_0)
  • A/D data register D_0 (ADDRD_0)
  • A/D data register E_0 (ADDRE_0)
  • A/D data register F_0 (ADDRF_0)
  • A/D data register G_0 (ADDRG_0)
  • A/D data register H_0 (ADDRH_0)
  • A/D control/status register_0 (ADCSR_0)
  • A/D control register_0 (ADCR_0) Unit 1 (A/D_1) registers:
  • A/D data register A_1 (ADDRA_1)
  • A/D data register B_1 (ADDRB_1)
  • A/D data register C_1 (ADDRC_1)
  • A/D data register D_1 (ADDRD_1)
  • A/D data register E_1 (ADDRE_1)
  • A/D data register F_1 (ADDRF_1)
  • A/D data register G_1 (ADDRG_1)
  • A/D data register H_1 (ADDRH_1)
  • A/D control/status register_1 (ADCSR_1)
  • A/D control register_1 (ADCR_1)

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17.3.1 A/D Data Registers A to H (ADDRA to ADDRH)

There are eight 16-bit read-only ADDR registers, ADDRA to ADDRH, used to store the results of A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown in tables 17.3 and 17.4. The converted 10-bit data is stored in bits 15 to 6. The lower 6-bit data is always read as 0. The data bus between the CPU and the A/D converter has a 16-bit width. The data can be read directly from the CPU. ADDR must not be accessed in 8-bit units and must be accessed in 16-bit units. Table 17.3 Analog Input Channels and Corresponding ADDR Registers (H8S/2426 Group and H8S/2426R Group) Analog Input Channel Analog Input Channel Channel Set 0 (CH3 = 0) Data Register Storing Conversion Result Channel Set 0 (CH3 = 0) Data Register Storing Conversion Result AN0 ADDRA_0 AN8 ADDRA_1 AN1 ADDRB_0 AN9 ADDRB_1 AN2 ADDRC_0 AN10 ADDRC_1 AN3 ADDRD_0 AN11 ADDRD_1 AN4 ADDRE_0 AN12 ADDRE_1 AN5 ADDRF_0 AN13 ADDRF_1 AN6 ADDRG_0 AN14 ADDRG_1 AN7 ADDRH_0 AN15 ADDRH_1

Rev. 1.00 Sep. 19, 2008 Page 962 of 1270 REJ09B0466-0100 Table 17.4 Analog Input Channels and Corresponding ADDR Registers (H8S/2424 Group) Analog Input Channel Analog Input Channel Channel Set 0 (CH3 = 0) Data Register Storing Conversion Result Channel Set 0 (CH3 = 0) Data Register Storing Conversion Result AN0 ADDRA_0   AN1 ADDRB_0   AN2 ADDRC_0   AN3 ADDRD_0   AN4 ADDRE_0 AN12 ADDRE_1 AN5 ADDRF_0 AN13 ADDRF_1 AN6 ADDRG_0  

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17.3.2 A/D Control/Status Register for Unit 0 (ADCSR_0)

ADCSR_0 controls A/D conversion operations. Bit Bit Name Initial Value R/W Description

7 ADF 0 R/(W) * A/D End Flag

A status flag that indicates the end of A/D conversion. [Setting conditions]

  • Completion of A/D conversion in single mode
  • Completion of A/D conversion on all specified channels in scan mode [Clearing conditions]
  • Writing of 0 after reading ADF = 1
  • Reading from ADDR after activation of the DMAC or DTC by an ADI interrupt

6 ADIE 0 R/W A/D Interrupt Enable

Setting this bit to 1 enables ADI interrupts by ADF.

5 ADST 0 R/W A/D Start

Clearing this bit to 0 stops A/D conversion, and the A/D converter enters wait state. Setting this bit to 1 starts A/D conversion. In single mode, this bit is cleared to 0 automatically when A/D conversion on the specified channel ends. In scan mode, A/D conversion continues sequentially on the specified channels until this bit is cleared to 0 by software, a reset, or hardware standby mode. While the ADSTCLR bit in ADCR is set to 1, the ADST bit is cleared to 0 automatically when A/D conversion on all selected channels ends, and then A/D conversion stops. The timing to clear the ADST bit automatically differs from that of ADF setting; the ADST bit is cleared before the ADF bit is set.

4 EXCKS 0 R/W Clock Extension Select

Specifies the A/D conversion time in combination with the CKS1 and CKS0 bits in ADCR. Be sure to set these three bits at one time. For details, see the description of the ADCR resisters.

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