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© Semiconductor Components Industries, LLC, 2010 November, 2010 − Rev. P2

1 Publication Order Number:

Solution for Voice Capture Devices Introduction BelaSigna® R261 is a complete system−on−chip (SoC) solution that provides advanced dual−microphone noise reduction in voice capture applications such as laptops, mobile phones, webcams, tablet computers and other applications that will benefit from improved voice clarity. Featuring a novel approach to removing mechanical, stationary and non−stationary noise, the chip preserves voice naturalness for greater speech intelligibility even when the talker is further away or not optimally aligned with microphones providing unmatched freedom of movement for end −users. Designed to be compatible with a wide range of codecs, baseband chips and microphones without the need for calibration, BelaSigna R261 is easy to integrate, improving manufacturers’ speed to market. Additional features include the ability to customize multiple voice capture modes and tune the algorithm to the unique needs of a manufacturer’s device. The chip includes a highly optimized DSP−based application cont roller with industry −leading energy efficiency and is packaged in two highly compact 5.3 mm

2 WLCSPs

to fit into even the most sized−constrained architectures and allow the use of the cheapest printed circuit board design technologies. Key Features

  • Advanced Two−Microphone Noise Reduction Algorithm
  • Preserves V oice Naturalness
  • Supports Close−Talk and Far−Talk
  • Conference Mode enables 360 Degrees Voice Pick−up
  • Configurable Algorithm Performance
  • Ultra Low Power Consumption
  • Ultra Miniature Form Factor
  • Complete System−on−Chip (SoC)
  • Highly Flexible Clocking Architecture
  • Hardware Configuration Interfaces
  • Prototyping Tools
  • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant Typical Applications
  • Laptop Computers
  • Mobile Phones
  • Tablet PCs
  • Webcams
  • Any Portable Audio Application with V oice Pick−up This document contains information on a new product. Specifications and information herein are subject to change without notice. http://onsemi.com BR261 W30 ALYW MARKING DIAGRAMS WLCSP−30 W SUFFIX CASE 567CT See detailed ordering and shipping information in the package dimensions section on page 28 of this data sheet.

ORDERING INFORMATION

BR261 = BelaSigna R261 W30 = 30 −ball version W26 = 26 −ball version A = Assembly Location L = Wafer Lot YW = Date Code Year & Week = Pb−Free Package = A1 Corner Indicator WLCSP−26 W SUFFIX CASE 567CY BR261 W26 ALYW

Table 1. ABSOLUTE MAXIMUM RATINGS

  1. Time limit at maximum voltage must be less than 100 ms.

NOTE: Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. − ESD Charge Discharge Model (CDM) tested per ESD−STM 5−3−1−1999. Table 2. ELECTRICAL CHARACTERISTICS (The typical parameters in Table 2 were measured at 20°C with a clean

Table 2. ELECTRICAL CHARACTERISTICS (continued) (The typical parameters in Table 2 were measured at 20°C with a clean

2.048 MHz

2.4 MHz

2.8 MHz

3.072 MHz

0 VBATRC

19.2 MHz

26 MHz

  1. Many other clock frequencies are available through custom configuration of the internal PLL and clocking subsystem. See later in this

document and in the BelaSigna R261 Configuration and Communications Guide for more information on custom mode usage.

Table 3. PIN CONNECTIONS

  • Pins C5, D4, D6 and E5 are not available on the WLCSP26 package.

All pins are available on the WLCSP30 package.

Figure 1. Typical Application Diagram for 30−ball WLCSP Package Option

Figure 2. Typical Application Diagram for 26−ball WLCSP Package Option

coupling, isolate the input traces from the output traces. of the power regulator as illustrated in Figure 3. Figure 3. Schematic of Ground Scheme

Figure 4. Analog Portion of BelaSigna R261 (Bumps facing up) consideration, see Table 4 and Table 5. connect to the star point with separate traces. as possible to the power pads. Table 4. Non−critical signals are outlined in Table 5. More in the Power Supply Unit section.

Table 4. CRITICAL SIGNALS

Table 5. NON−CRITICAL SIGNALS frequency of the resulting high−pass filter could be too high. traces strictly away from output traces. same to provide matched impedances. Table 6. UNUSED PIN RECOMMENDATIONS

The architecture of BelaSigna R261 is shown in Figure 5. Figure 5. BelaSigna R261 Architecture: A Complete Audio Processing System criterion, with no constraints on the number of sources vs. parameters via this mechanism.

  • The two microphones are facing the user’s mouth
  • The microphone centers are located within 10 to 25 mm from each other As mentioned, other configurations that differ from the above guidelines can be supported through the use of the custom mode, as described earlier. BelaSigna R261 does not require any acoustic microphone calibration procedure. The selection of the microphones should be made in cooperation with ON Semiconductor, such as the built −in algorithm can operate seamlessly. The following guidelines can be used for a pre−selection:
  • Two omni−directional microphones with similar characteristics should be used
  • The microphone sensitivity should be −42 dB (where 0 dB = 1 V/Pa, at 1 kHz)
  • The microphones are two terminal microphones
  • The microphone power supply is either 1 V , or 2 V if it has to be provided by BelaSigna R261
  • The dynamic range of BelaSigna R261 on its analog input channels is 2.0 V peak−to−peak, after amplification by the default gain value of 30 dB using BelaSigna R261’s input preamplifiers
  • When higher sensitivity microphones have to be used, the preamp gain will be adjustable to match the 2.0 Vpp input voltage swing on BelaSigna R261, but this will require a custom tuning operation, as described later. Operating Modes The default application in ROM on BelaSigna R261 has five Operating Modes. The Operating Modes are summarized in Table 7.

Table 7. OPERATING MODES SUMMARY cessed signals are sent to the audio outputs. puts. The inputs are passed directly to the audio outputs. clock source, thereby allowing the external clock to be disabled. Note that LOUT1 is not available on the 26−ball WLCSP package. by using the SLEEP_CTRL pin. SLEEP_CTRL pin is toggled again. see the Sleep Control section below. to be disabled when the chip is asleep. This is BelaSigna R261’s lowest power operating mode. mode like Active, Bypass or Line−Out.

based on the pin voltage levels. using this reduced ball package variant. Table 8. BOOT CONTROL OPTIONS laSigna R261 Configuration and Communications Guide” for more information. termined by CONFIG_SEL and ATT_SEL pins. and Communications Guide” for more information. pins will not be driven by any external hardware component. interface, which is also multiplexed with the SPI port. information on this particular use case. time during the 10 ms low period of the signal. Figure 6. ALGO_CTRL Timing Diagram configuration options of BelaSigna R261’s output stage.

Table 9. CLOCKING, OUTPUT STAGE AND ALGORITHM CONFIGURATION OPTIONS

2.048 X X

26 X X

available on the WLCSP−26 package option. your local technical support for more information. as an analog input or a line-out. Figure 9. Input Stage The BelaSigna R261 output stage is shown in Figure 10.

pre−configured by the ROM −based application. Table 13. ANALOG STEREO OUTPUT SIGNALS between 13 kHz (default) and 26 kHz. transducer without the need for a separate power amplifier. as described for the analog outputs.

  • When using the analog outputs, VBATRCVR must be connected to VDDA on the application PCB
  • When using the output driver, VBATRCVR must be connected to VBAT on the application PCB and must be decoupled with an external capacitor When interfacing BelaSigna R261 with other processors like codecs or baseband chipsets, it is not recommended to use the output driver, but rather the analog outputs. Clock Generation Circuitry BelaSigna R261 is equipped with a fully configurable and flexible clocking system, which allows for a large number of clocking configurations for various different use cases. Computing applications would typically require the use of a DMIC interface, which imposes constraints on the BelaSigna R261 clocking system, such as it provides full synchronization between an incoming DMIC clock and the DMIC data that the chip will produce. The input frequencies that these systems usually operate with are in the range of 2.048 to 3.072 MHz. Mobile phone applications would typically use much higher clock frequencies; historically, baseband systems have been using 13 MHz or 26 MHz, or even 19.2 MHz or 38.4 MHz. The variety of clocking use cases that BelaSigna R261 must support forced the integration of a phase locked loop as one of the components of BelaSigna R261’s clock generation circuitry. This highly configurable PLL is shown in Figure 12, in the context of the BelaSigna R261 clocking architecture.

Figure 12. Clocking Circuitry Communications Guide for more information. be used directly by the system, bypassing the internal PLL. when the sampling rate accuracy isn’t important. Configuration and Communications Guide.

operation can no longer be guaranteed. operation under all battery conditions. are asynchronously reset to their default values. threshold. The relevant parameters are shown in Table 15. Table 15. POWER MANAGEMENT PARAMETERS

  1. The internal regulators are enabled and allowed to
  2. The internal charge pump is enabled and allowed
  3. SYSCLK is connected to all of the system
  4. The system runs the ROM application

(POR_TIME), a signal will enable the charge pump. signal, and thus enabling the digital core. clock, and take the appropriate actions whenever it disappears. See the system monitoring section for more information. interface with BelaSigna R261. ALGO_CTRL, SPI_SERI/SLEEP_CTRL and BOOT_SEL. other GPIOs, as defined in the Booting Control section. pins have a weak pull−down to ground. details on the behavior of these GPIO ports. operates in slave mode and the slave address is 0x61.

use of these other functions. high speed PCM interface, as well as a high speed UART. the use of these interfaces, should this be required. Table 16. LONG TERM STORAGE CONDITIONS wards storage in vacuum moisture bag with desiccant and humidity card. Storage in nitrogen cabinet allowed. for the re−flow and the assembly that is being re −flowed. Table 17. RE−FLOW INFORMATION with the protocol software provided by ONSemiconductor.

http://onsemi.com PACKAGE DIMENSIONS WLCSP30, 2.233x2.388 CASE 567CT−01 ISSUE A SEATING PLANE 0.10 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. DIM A MIN MAX 0.84 MILLIMETERS D 2.388 BSC E b 0.24 0.29 eA 0.252 BSC 1.00 ÈÈ ÈÈ D E A B PIN A1 REFERENCE eA A0.05 BC 0.03 C 0.05 C 30X b 123 A B C 0.10 C A C 0.17 0.23

2.233 BSC

eB 0.310 BSC PITCH 0.25 30X DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* 0.504 0.310

0.10 C2X

A2 0.72 REF RECOMMENDED PACKAGE OUTLINE 456 789 D E F G

http://onsemi.com PACKAGE DIMENSIONS WLCSP26, 2.388x2.233 CASE 567CY−01 ISSUE O SEATING PLANE 0.10 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. DIM A MIN MAX 0.84 MILLIMETERS D 2.388 BSC E b 0.24 0.29 eD 0.252 BSC 1.00 ÈÈ ÈÈ D E A B PIN A1 REFERENCE eD A0.05 BC 0.03 C 0.05 C 26X b 123 A B C 0.10 C A C 0.17 0.23 eE 0.310 BSC PITCH 0.25 26X DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* 0.504 0.35 A2 0.72 REF RECOMMENDED PACKAGE OUTLINE 456 789 D E F G

  1. the solder mask opening should be >0.3 mm in
  2. the copper pad will have 0.25 mm diameter, and
  3. solder mask thickness should be less than 1 mil

thick above the copper surface. Table 18. ORDERING INFORMATION Specification Brochure, BRD8011/D. arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. BelaSigna is a registered trademark of Semiconductor Components Industries, LLC.