R1QCA7218AB

R1Q4A7236ABB RENESAS | Alldatasheet

Document overview

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• PDF pages: 36

Technical content

Features

႑ Power Supply

• 1.8 V for core (VDD), 1.4 V to VDD for I/O (VDDQ)

႑ Clock

• Fast clock cycle time for high bandwidth
• Two input clocks (K and /K) for precise DDR timing at clock rising edges only
• Two input clocks for output data (C and /C) to minimize clock skew and flight time mismatches
• Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems
• Clock-stop capability with μs restart

႑ I/O

• Common data input/output bus
• Pipelined double data rate operation
• HSTL I/O
• User programmable output impedance
• DLL/PLL circuitry for wide output data valid window and future frequency scaling

႑ Function

• Two-tick burst for low DDR transaction size
• Internally self-timed write control
• Simple control logic for easy depth expansion
• JTAG 1149.1 compatible test access port

႑ Package

• 165 FBGA package (13 x 15 x 1.4 mm) R1Q4A7236ABB R1Q4A7218ABB 72-Mbit DDRII SRAM 2-word Burst Notes: 1. QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, Samsung, and Renesas Electronics Corp. (QDR Co-Development Team) 2. The specifications of this device are subject to change without notice. Please contact your nearest Renesas Electronics Sales Office regarding specifications. 3. Refer to "http://www.renesas.com/products/memory/fast_sram/qdr_sram/index.jsp" for the latest and detailed information. 4. Descriptions about x9 parts in this datasheet are just for reference. R10DS0166EJ0011 R10DS0166EJ0011

R1Q4A7236ABB / R1Q4A7218ABB Series Rev. 0.11 : 2013.01.15 PAGE:2 Part Number Definition Common Part Number Definition Table Column No. 0 1 2 3 4 5 6 7 8 9 10 11 - 12 13 14 15 16 Example R1Q4A7218ABB- 30RB0 The above part number is just example for 72M DDRII B2 x18 333MHz, 13x15mm PKG, Pb-free part. No. - Comments No. - Comments No. - Comments 0-1 R1 Renesas Memory Prefix 4 A Vdd = 1.8 V 60 Frequency = 167MHz Q2 QDR II B2[*1] (L15)[*2] 36 Density = 36Mb 50 Frequency = 200MHz Q3 QDR II B4 (L15) 72 Density = 72Mb 40 Frequency = 250MHz Q4 DDR II B2 (L15) 44 Density = 144Mb 36 Frequency = 275MHz Q5 DDR II B4 (L15) 88 Density = 288Mb 33 Frequency = 300MHz Q6 DDR II B2 SIO[*3] (L15) 09 Data width = 9bit 30 Frequency = 333MHz QA QDR II+ B4 L25[*2] 18 Data width = 18bit 27 Frequency = 375MHz QB DDR II+ B2 L25 36 Data width = 36bit 25 Frequency = 400MHz QC DDR II+ B4 L25 R 1st Generation 22 Frequency = 450MHz QD QDR II+ B4 L25 w/ODT[*4] A 2nd Generation 20 Frequency = 500MHz QE DDR II+ B2 L25 w/ODT B 3rd Generation 19 Frequency = 533MHz QF DDR II+ B4 L25 w/ODT C 4th Generation 18 Frequency = 550MHz QG QDR II+ B4 L20 D 5th Generation QH DDR II+ B2 L20 E 6th Generation QJ DDR II+ B4 L20 F 7th Generation QK QDR II+ B4 L20 w/ODT BG PKG= BGA 15x17 mm QL DDR II+ B2 L20 w/ODT BB PKG= BGA 13x15 mm A Pb -and Tray QM DDR II+ B4 L20 w/ODT B Pb-free and Tray QN QDR II+ B2 L20 TP b -and Tape&Reel QP QDR II+ B2 L20 w/ODT S Pb-free and Tape&Reel Note1: [*1] B=Burst length (B2: Burst length=2, B4: Burst length=4) [*2] L=Read Latency (L15: Read Latency = 1.5 cycle, L20: 2.0 cycle, L25: 2.5 cycle) [*3] SIO=Separate I/O [*4] ODT=On die termination Note2: Package Marking Name Pb-parts: Marking Name = Part Number(0-14) Pb-free parts: Marking Name = Part Number(0-14) + "PB-F" (Example) R1QAA4436RBG-20R Pb-F ----- Pb-parts (Example) R1QAA4436RBG-20R PB-F ----- Pb-free parts Note3: Pb -free: RoHS Compliance Level = 5/6 Pb-free: RoHS Compliance Level = 6/6 Note4: R1Q*A series support both "Commercial" and "Industrial" temperatures by "Industrial" temperature parts. R Commercial temp. Ta range = 0é to 70é 12-13 2-3 5-6 7-8 - 16 0 to 9, A to Z or None Renesas internal use 10-11 -- - Industrial temp. Ta range = -40é to 85éI R10DS0166EJ0011

R1Q4A7236ABB / R1Q4A7218ABB Series Rev. 0.11 : 2013.01.15 PAGE:3 hinS=11111.1111.1111.1111.1111--- 00000.0000.0000.0000.0000--- 00000.0000.0000.0000.0000---072M Notes: 1. "v" represents the package size. If "v" = "G" then size is 15 x 17 mm, and if "v" = "B" then 13 x 15 mm. 2. "yy" represents the speed bin. "R1QAA7236ABB-20" can operate at 500 MHz(max) of frequency, for example. 3. The part which is not listed above is not supported, as of the day when this datasheet was issued, in spite of the existence of the part number or datasheet. 533 500 450 400 375 333 333 300 250 200 yy ă - 1 9- 2 0- 2 2- 2 5- 2 7- 3 0- 3 0- 3 3- 4 0- 5 0 1 x 9 R1Q 2 A72 09 A B v- yy -40 -50 2x 1 8 R 1 Q 2 A 7 2 1 8 A B v- yy 3x 3 6 R 1 Q 2 A 7 2 3 6 A B v- yy 5x 1 8 R 1 Q 3 A 7 2 1 8 A B v- yy 6x 3 6 R 1 Q 3 A 7 2 3 6 A B v- yy 8x 1 8 R 1 Q 4 A 7 2 1 8 A B v- yy 9x 3 6 R 1 Q 4 A 7 2 3 6 A B v- yy 11 x18 R1Q 5 A72 18 A B v- yy 12 x36 R1Q 5 A72 36 A B v- yy 14 x18 R1Q 6 A72 18 A B v- yy 15 x36 R1Q 6 A72 36 A B v- yy 17 x18 R1Q A A72 18 A B v- yy 18 x36 R1Q A A72 36 A B v- yy 20 x18 R1Q B A72 18 A B v- yy 21 x36 R1Q B A72 36 A B v- yy 23 x18 R1Q C A72 18 A B v- yy 24 x36 R1Q C A72 36 A B v- yy 26 x18 R1Q D A72 18 A B v- yy 27 x36 R1Q D A72 36 A B v- yy 29 x18 R1Q E A72 18 A B v- yy 30 x36 R1Q E A72 36 A B v- yy 32 x18 R1Q F A72 18 A B v- yy 33 x36 R1Q F A72 36 A B v- yy 35 x18 R1Q G A72 18 A B v- yy 36 x36 R1Q G A72 36 A B v- yy 38 x18 R1Q H A72 18 A B v- yy 39 x36 R1Q H A72 36 A B v- yy 41 x18 R1Q J A72 18 A B v- yy 42 x36 R1Q J A72 36 A B v- yy 44 x18 R1Q K A72 18 A B v- yy 45 x36 R1Q K A72 36 A B v- yy 47 x18 R1Q L A72 18 A B v- yy 48 x36 R1Q L A72 36 A B v- yy 50 x18 R1Q M A72 18 A B v- yy 51 x36 R1Q M A72 36 A B v- yy -30 -30 QDR II+ / DDR II+ QDR II / DDR II -30 -30 -40 -50 -33 Frequency (max) (MHz) Cycle Time (min) (ns) No Yes No ODT Part Number Ą -19 -19 -19 -19 -22 -22 -22 -22 -19 -19 1.5 No 2.5 2.5 Yes QDRII DDRII SIO B2 DDRII+ DDRII B4QDRII+ QDRII+ B4 2.0 DDRII+ 2.0 DDRII+ QDRII+ B4 DDRII+ QDRII+ B4 No Product Type Burst Length Latency (Cycle) Organi- zation -20 -20 -20 -20 -20 -20 -40 -40 -40 -40 -22 -22 -25 -25 -25 -33 -25 -33 -33 -25 -25 72M QDR/DDR SRAM (R1Q*A72 Series) Lineup - Renesas supports or plans to support the parts listed below. R10DS0166EJ0011

R1Q4A7236ABB / R1Q4A7218ABB Series Rev. 0.11 : 2013.01.15 PAGE:4 R1Q4A7218 (Top) / R1QB(H)A7218 (Mid) / R1QE(L)A7218 (Bottom) 123456789 1 0 1 1 A /CQ SA SA R-/W /BW1 /K NC /LD SA SA CQ B NC DQ9 NC SA NC K /BW0 SA NC NC DQ8 C N CN CN CV SS SA SA0 NC NC SA V SS NC DQ7 NC D NC NC DQ10 V SS VSS VSS VSS VSS NC NC NC EN C N C D Q 1 1 V DDQ VSS VSS VSS VDDQ NC NC DQ6 F NC DQ12 NC V DDQ VDD VSS VDD VDDQ NC NC DQ5 G NC NC DQ13 V DDQ VDD VSS VDD VDDQ NC NC NC H/ D O F F V REF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J N CN CN C V DDQ VDD VSS VDD VDDQ NC DQ4 NC K NC NC DQ14 V DDQ VDD VSS VDD VDDQ NC NC DQ3 L NC DQ15 NC V DDQ VSS VSS VSS VDDQ NC NC DQ2 M N CN CN CV SS VSS VSS VSS VSS NC DQ1 NC N NC NC DQ16 V SS SA SA SA V SS NC NC NC P NC NC DQ17 SA SA C QVLD QVLD SA SA NC NC DQ0 RT D O T C K S AS AS A NC ODT SA SA SA TMS TDI (Top View) Notes: 1. Address expansion order for future higher density SRAMs: 10A ĺ 2A ĺ 7A ĺ 5B. 2. NC pins can be left floating or connected to 0V ᨺ V DDQ. R1Q4A7236 (Top) / R1QB(H)A7236 (Mid) / R1QE(L)A7236 (Bottom) 123456789 1 0 1 1 A /CQ NC SA R-/W /BW2 /K /BW1 /LD SA SA CQ B NC DQ27 DQ18 SA /BW3 K /BW0 SA NC NC DQ8 C NC NC DQ28 V SS SA SA0 NC NC SA V SS NC DQ17 DQ7 D NC DQ29 DQ19 V SS VSS VSS VSS VSS NC NC DQ16 E NC NC DQ20 V DDQ VSS VSS VSS VDDQ NC DQ15 DQ6 F NC DQ30 DQ21 V DDQ VDD VSS VDD VDDQ NC NC DQ5 G NC DQ31 DQ22 V DDQ VDD VSS VDD VDDQ NC NC DQ14 H/ D O F F V REF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC DQ32 V DDQ VDD VSS VDD VDDQ NC DQ13 DQ4 K NC NC DQ23 V DDQ VDD VSS VDD VDDQ NC DQ12 DQ3 L NC DQ33 DQ24 V DDQ VSS VSS VSS VDDQ NC NC DQ2 MN C N C D Q 3 4 V SS VSS VSS VSS VSS NC DQ11 DQ1 N NC DQ35 DQ25 V SS SA SA SA V SS NC NC DQ10 P NC NC DQ26 SA SA C QVLD QVLD SA SA NC DQ9 DQ0 RT D O T C K S AS AS A NC ODT SA SA SA TMS TDI (Top View) Notes: 1. Address expansion order for future higher density SRAMs: 10A ĺ 2A ĺ 7A ĺ 5B. 2. NC pins can be left floating or connected to 0V ᨺ V DDQ. Pin Arrangement Top ĸR1Q4A7236 Mid ĸR1QB(H)A7236 Bottom ĸR1QE(L)A7236 R10DS0166EJ0011

R1Q4A7236ABB / R1Q4A7218ABB Series Rev. 0.11 : 2013.01.15 PAGE:5 R1Q4A7209 (Top) / R1QB(H)A7209 (Mid) / R1QE(L)A7209 (Bottom) 123456789 1 0 1 1 A /CQ SA SA R-/W NC /K NC /LD SA SA CQ B N CN CN CS AN C K / B W S AN CN C D Q 4 C N CN CN CV SS SA SA SA V SS NC NC NC D N CN CN CV SS VSS VSS VSS VSS NC NC NC EN C N C D Q 5 V DDQ VSS VSS VSS VDDQ NC NC DQ3 F N CN CN C V DDQ VDD VSS VDD VDDQ NC NC NC GN C N C D Q 6 V DDQ VDD VSS VDD VDDQ NC NC NC H/ D O F F V REF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J N CN CN C V DDQ VDD VSS VDD VDDQ NC DQ2 NC K N CN CN C V DDQ VDD VSS VDD VDDQ NC NC NC LN C D Q 7 N C V DDQ VSS VSS VSS VDDQ NC NC DQ1 M N CN CN CV SS VSS VSS VSS VSS NC NC NC N N CN CN CV SS SA SA SA V SS NC NC NC P NC NC DQ8 SA SA C QVLD QVLD SA SA NC NC DQ0 RT D O T C K S AS AS A NC ODT SA SA SA TMS TDI (Top View) Notes: 1. Address expansion order for future higher density SRAMs: 10A ĺ 2A ĺ 7A ĺ 5B. 2. NC pins can be left floating or connected to 0V ᨺ V DDQ. 3. Note that 6C is not SA0 and 7C is not SA1 in x9 product. Thus ×9 product does not permit random start address on the two least significant address bits. SA0, SA1 = 0 at the start of each address. Pin Arrangement Just Reference R10DS0166EJ0011

R1Q4A7236ABB / R1Q4A7218ABB Series Rev. 0.11 : 2013.01.15 PAGE:6 Pin Descriptions Name I/O type Descriptions Notes SAx Input Synchronous address inputs: These inputs are registered and must meet the setup and hold times around the rising edge of K. All transactions operate on a burst-of-four words (two clock periods of bus activity). SA0 and SA1 are used as the lowest two address bits for burst READ and burst WRITE operations permitting a random burst start address on ×18 and ×36 of DDR II (not II+) devices. These inputs are ignored when device is deselected or once burst operation is in progress. /LD Input Synchronous load: This input is brought low when a bus cycle sequence is to be defined. This definition includes address and READ / WRITE direction. All transactions operate on a burst-of-four data (two clock periods of bus activity). R-/W Input Synchronous read / write Input: When /LD is low, this input designates the access type (READ when R-/W is high, WRITE when R-/W is low) for the loaded address. R-/W must meet the setup and hold times around the rising edge of K. /BW x Input Synchronous byte writes: When low, these inputs cause their respective byte to be registered and written during WRITE cycles. These signals are sampled on the same edge as the corresponding data and must meet setup and hold times around the rising edges of K and /K for each of the two rising edges comprising the WRITE cycle. See Byte Write Truth Table for signal to data relationship. K, /K Input Input clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data on the rising edge of K and the rising edge of /K. /K is ideally 180 degrees out of phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges. These balls cannot remain V REF level. C, /C (II only) Input Output clock: This clock pair provides a user-controlled means of tuning device output data. The rising edge of /C is used as the output timing reference for the first and third output data. The rising edge of C is used as the output timing reference for second and fourth output data. Ideally, /C is 180 degrees out of phase with C. C and /C may be tied high to force the use of K and /K as the output reference clocks instead of having to provide C and /C clocks. If tied high, C and /C must remain high and not to be toggled during device operation. These balls cannot remain V REF level. /DOFF Input DLL/PLL disable: When low, this input causes the DLL/PLL to be bypassed for stable, low frequency operation. TMS TDI Input IEEE1149.1 test inputs: 1.8 V I/O levels. These balls may be left not connected if the JTAG function is not used in the circuit. TCK Input IEEE1149.1 clock input: 1.8 V I/O levels. This ball must be tied to VSS if the JTAG function is not used in the circuit. Notes: 1. R1Q2, R1Q3, R1Q4, R1Q5, R1Q6 series have C and /C pins. R1QA, R1QB, R1QC, R1QD, R1QE, R1QF, R1QG, R1QH, R1QJ, R1QK, R1QL, R1QM, R1QN, R1QP series do not have C, /C pins. In the series, K and /K are used as the output reference clocks instead of C and /C. Therefore, hereafter, C and /C represent K and /K in this document. hinS=00111.0011.0011.0011.0011 00111.0011.0011.0011.0011---DDR R10DS0166EJ0011

R1Q4A7236ABB / R1Q4A7218ABB Series Rev. 0.11 : 2013.01.15 PAGE:7 Name I/O type Descriptions Notes ZQ Input Output impedance matching input: This input is used to tune the device outputs to the system data bus impedance. DQ and CQ output impedance are set to 0.2 × RQ, where RQ is a resistor from this ball to ground. This ball can be connected directly to VDDQ, which enables the minimum impedance mode. This ball cannot be connected directly to VSS or left unconnected. In ODT (On Die Termination) enable devices, the ODT termination values tracks the value of RQ. The ODT range is selected by ODT control input. ODT (II+ only) Input ODT control: When low; [Option 1] Low range mode is selected. The impedance range is between 52 Ω and 105 Ω (Thevenin equivalent), which follows 0.3 × RQ for 175 Ω ” RQ ” 350 Ω. [Option 2] ODT is disabled. When high; High range mode is selected. The impedance range is between 105 Ω and 150 Ω (Thevenin equivalent), which follows 0.6 × RQ for 175 Ω ” RQ ” 250 Ω. When floating; [Option 1] High range mode is selected. [Option 2] ODT is disabled. DQ0 to DQn Input output Synchronous data I/Os: Input data must meet setup and hold times around the rising edges of K and /K. Output data is synchronized to the respective C and /C, or to the respective K and /K if C and /C are tied high. The ×9 device uses DQ0 ~DQ8. DQ9~DQ35 should be treated as NC pin. The ×18 device uses DQ0~DQ17. DQ18~DQ35 should be treated as NC pin. The ×36 device uses DQ0~DQ35. CQ, /CQ Output Synchronous echo clock outputs: The edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. These signals run freely and do not stop when DQ tri- states. TDO Output IEEE 1149.1 test output: 1.8 V I/O level. QVLD (II+ only) Output Valid output indicator: The Q Valid indicates valid output data. QVLD is edge aligned with CQ and /CQ. V DD Supply Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions for range. 2 VDDQ Supply Power supply: Isolated output buffer supply. Nominally 1.5 V. See DC Characteristics and Operating Conditions for range. 2 VSS Supply Power supply: Ground. 2 VREF ⎯ HSTL input reference voltage: Nominally VDDQ/2, but may be adjusted to improve system noise margin. Provides a reference voltage for the HSTL input buffers. NC ⎯ No connect: These pins can be left floating or connected to 0V ᨺ V DDQ. Notes: 1. Renesas status: Option 1 = Available, Option 2 = Possible. 2. All power supply and ground balls must be connected for proper operation of the device. R10DS0166EJ0011

R1Q4A7236ABB / R1Q4A7218ABB Series Rev. 0.11 : 2013.01.15 PAGE:8 Block Diagram (R1QxA7236 / R1QxA7218 series, x=4) /LD /BWx K /36 /36 DQ K C,/C or K,/K ZQ CQ, /CQ /36 R-/W SA0 SA0' Memory Array Write Register Output Register Output Select Output Buffer Write Driver Sense Amp MUX Burst Logic Output Control Logic SA0'' SA0''' SA /LD R-/W K Address Registry and Logic Data Registry and Logic Notes 1. C and /C pins do not exist in II+ series parts. C or K Block Diagram (R1QxA7236 / R1QxA7218 / R1QyA7209 series, x=B,E,H,L, y=4,B,E,H,L) /LD /BWx K /36 /18 20/21/22 36/18/9 36/18/9 DQ 20/21/22 K C,/C or K,/K ZQ CQ, /CQ Memory Array Write Register Output Register Output Select Output Buffer Write Driver Sense Amp MUX 4/2/1 R-/W /36 /18 /36 /18 SA /LD R-/W K Address Registry and Logic Data Registry and Logic Notes 1. C and /C pins do not exist in II+ series parts. C or K R10DS0166EJ0011

R1Q4A7236ABB / R1Q4A7218ABB Series Rev. 0.11 : 2013.01.15 PAGE:9 hinS=11111.1111.1111.1111.1111--- 72M_36M Status Power Up & Unstable Stage NOP & Set-up Stage Normal Operation VDD SET-UP Cycle VDDQ VREF /DOFF 2. Double clock mode K, /K Fix High (=Vddq) C, /C Status Power Up & Unstable Stage NOP & Set-up Stage Normal Operation VDD SET-UP Cycle VDDQ VREF /DOFF 1. Single clock mode (C and /C pins fixed High) K, /K Fix High (=Vddq) General Description Power-up and Initialization Sequence -V DD must be stable before K, /K clocks are applied. - Recommended voltage application sequence : VSS ĺVDD ĺVDDQ & VREF ĺ VIN. (0 V to VDD, VDDQ < 200 ms) - Apply VREF after VDDQ or at the same time as VDDQ. - Then execute either one of the following three sequences. 1. Single Clock Mode (C and /C tied high) - Drive /DOFF high (/DOFF can be tied high from the start). - Then provide stable clocks (K, /K) for at least 1024 cycles (II series) or 20 us (II+ series). These meet the QDR common specification of 20 us. When the operating frequency is less than 180 MHz, 2048 cycles are required (II series). 2. Double Clock Mode (C and /C control outputs) (II series only) - Drive /DOFF high (/DOFF can be tied high from the start) - Then provide stable clocks (K, /K , C, /C) for at least 1024 cycles (II series). This meets the QDR common specification of 20 us. When the operating frequency is less than 180 MHz, 2048 cycles are required (II series). 3. DLL/PLL Off Mode (/DOFF tied low) - In the "NOP and setup stage", provide stable clocks (K, /K) for at least 1024 cycles (II series) or 20 us (II+ series). These meet the QDR common specification of 20 us. R10DS0166EJ0011

R1Q4A7236ABB / R1Q4A7218ABB Series Rev. 0.11 : 2013.01.15 PAGE:10 Common DLL/PLL Constraints 1. DLL/PLL uses K clock as its synchronizing input. The input should have low phase jitter which is specified as tKC var. 2. The lower end of the frequency at which the DLL/PLL can operate is 120 MHz. (Please refer to AC Characteristics table for detail.) 3. When the operating frequency is changed or /DOFF level is changed, setup cycles are required again. Programmable Output Impedance 1. Output buffer impedance can be programmed by terminating the ZQ ball to VSS through a precision resistor (RQ). The value of RQ is five times the output impedance desired. The allowable range of RQ to guarantee impedance matching with a tolerance of 15% is 250 Ω typical. The total external capacitance of ZQ ball must be less than 7.5 pF. R10DS0166EJ0011

R1Q4A7236ABB / R1Q4A7218ABB Series Rev. 0.11 : 2013.01.15 PAGE:11 K Truth Table Operation K /LD R-/W DQ Write Cycle: Load address, input write data on consecutive K and /K rising edges Ĺ LL Data in Input data D(A1) D(A2) Input clock K(t+1)Ĺ /K(t+1)Ĺ Read Cycle: Load address, output read data on consecutive C and /C rising edges Ĺ LH Data out Output data Q(A1) Q(A2) Input clock for Q RL *8=1.5 /C(t+1) Ĺ C(t+2)Ĺ RL=2.0 C(t+2) Ĺ /C(t+2)Ĺ RL=2.5 /C(t+2) Ĺ C(t+3)Ĺ NOP (No operation) Ĺ H × High-Z Standby (Clock stopped) Stopped ×× Previous state Notes: 1. H: high level, L: low level, ×: don’t care, Ĺ: rising edge. 2. Data inputs are registered at K and /K rising edges. Data outputs are delivered at C and /C rising edges, except if C and /C are high, then data outputs are delivered at K and /K rising edges. 3. /LD and R-/W must meet setup/hold times around the rising edges (low to high) of K and are registered at the rising edge of K. 4. This device contains circuitry that will ensure the outputs will be in high-Z during power-up. 5. Refer to state diagram and timing diagrams for clarification. 6. When clocks are stopped, the following cases are recommended; the case of K = low, /K = high, C = low and /C = high, or the case of K = high, /K = low, C = high and /C = low. This condition is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 7. A1 refers to the address input during a WRITE or READ cycle. A2 refers to the next internal burst address in accordance with the linear burst sequence. 8. RL = Read Latency (unit = cycle). Burst Sequence Linear Burst Sequence Table (R1Q4Aww36 / R1Q4Aww18 series ) SA0 SA0 Notes External address 0 1 1st internal burst address 1 0 R10DS0166EJ0011

R1Q4A7236ABB / R1Q4A7218ABB Series Rev. 0.11 : 2013.01.15 PAGE:12 Byte Write Truth Table( x 36 ) Operation K /K /BW0 /BW1 /BW2 /BW3 Write D0 to D35 Ĺ -LLLL - Ĺ LLLL Write D0 to D8 Ĺ - LHHH - Ĺ LHHH Write D9 to D17 Ĺ -HLH H - Ĺ HLHH Write D18 to D26 Ĺ -H HLH - Ĺ HHLH Write D27 to D35 Ĺ -H H HL - Ĺ HHHL Write nothing Ĺ - HHHH - Ĺ HHHH Notes: 1. H: high level, L: low level, Ĺ: rising edge. 2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied. Common Byte Write Truth Table( x 18 ) Operation K /K /BW0 /BW1 Write D0 to D17 Ĺ -L L - Ĺ LL Write D0 to D8 Ĺ -L H - Ĺ LH Write D9 to D17 Ĺ -H L - Ĺ HL Write nothing Ĺ -H H - Ĺ HH Notes: 1. H: high level, L: low level, Ĺ: rising edge. 2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied. Byte Write Truth Table( x 9 ) Operation K /K /BW Write D0 to D8 Ĺ -L - Ĺ L Write nothing Ĺ -H - Ĺ H Notes: 1. H: high level, L: low level, Ĺ: rising edge. 2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied. Just Reference except R1Q2A**09 series R10DS0166EJ0011

R1Q4A7236ABB / R1Q4A7218ABB Series Rev. 0.11 : 2013.01.15 PAGE:13 Notes: 1. SA0 is internally advanced in accordance with the burst order table. Bus cycle is terminated at the end of this sequence (burst count = 2). 2. State machine control timing sequence is controlled by K. Bus Cycle State Diagram NOP Write Double Count = Count + 2 Load New Address Count = 0 Power Up /LD = H Supply voltage provided /LD = L R-/W = L /LD = L Count = 2 /LD = H & Count = 2 Read Double Count = Count + 2 R-/W = H /LD = L Count = 2 /LD = H & Count = 2 R10DS0166EJ0011

R1Q4A7236ABB / R1Q4A7218ABB Series Rev. 0.11 : 2013.01.15 PAGE:14 Absolute Maximum Ratings Parameter Symbol Rating Unit Notes Input voltage on any ball V IN −0.5 to VDD + 0.5 (2.5 V max.) V1 , 4 Input/output voltage V I/O −0.5 to VDDQ + 0.5 (2.5 V max.) V1 , 4 Core supply voltage V DD −0.5 to 2.5 V 1, 4 Output supply voltage V DDQ −0.5 to VDD V1 , 4 Junction temperature Tj +125 (max) °C5 Storage temperature T STG −55 to +125 °C Notes: 1. All voltage is referenced to V SS. 2. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted the Operation Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. 3. These CMOS memory circuits have been designed to meet the DC and AC specifications shown in the tables after thermal equilibrium has been established. 4. The following supply voltage application sequence is recommended: V SS, VDD, VDDQ, VREF then VIN. Remember, according to the Absolute Maximum Ratings table, VDDQ is not to exceed 2.5 V, whatever the instantaneous value of VDDQ. 5. Some method of cooling or airflow should be considered in the system. (Especially for high frequency or ODT parts) Common Recommended DC Operating Conditions Parameter Symbol Min Typ Max Unit Notes Power supply voltage -- core V DD 1.7 1.8 1.9 V 1 Power supply voltage -- I/O V DDQ 1.4 1.5 V DD V1 , 2 Input reference voltage -- I/O V REF 0.68 0.75 0.95 V 3 Input high voltage V IH (DC) VREF + 0.1 ⎯ VDDQ + 0.3 V 1, 4, 5 Input low voltage V IL (DC) −0.3 ⎯ VREF − 0.1 V 1, 4, 5 Notes: 1. At power-up, V DD and VDDQ are assumed to be a linear ramp from 0V to VDD(min.) or VDDQ(min.) within 200ms. During this time VDDQ < VDD and VIH < VDDQ. During normal operation, VDDQ must not exceed VDD. 2. Please pay attention to Tj not to exceed the temperature shown in the absolute maximum ratings table due to current from VDDQ. 3. Peak to peak AC component superimposed on V REF may not exceed 5% of VREF. 4. These are DC test criteria. The AC V IH / VIL levels are defined separately to measure timing parameters. 5. Overshoot: V IH (AC) ≤ VDDQ + 0.5 V for t ≤ tKHKH/2 Undershoot: VIL (AC) ≥− 0.5 V for t ≤ tKHKH/2 During normal operation, VIH(DC) must not exceed VDDQ and VIL(DC) must not be lower than VSS. R10DS0166EJ0011

R1Q4A7236ABB / R1Q4A7218ABB Series Rev. 0.11 : 2013.01.15 PAGE:15 hinS=11111.1111.1111.1111.1111--- 00000.0000.0000.0000.0000--- 00000.0000.0000.0000.0000---072M DC Characteristics (VDD =1 . 8 V±0.1V , VDDQ =1 . 5 V , VREF = 0.75V) Operating Supply Current (Write / Read) Symbol = IDD. Unit = mA. See Notes 1, 2 and 3 in the page after next. 533 500 450 400 375 333 333 300 250 200 yy ă - 1 9- 2 0- 2 2- 2 5- 2 7- 3 0- 3 0- 3 3- 4 0- 5 0 1 x 9 R1Q 2 A72 09 A B v- yy 760 670 2x 1 8 R 1 Q 2 A 7 2 1 8 A B v- yy 890 780 3x 3 6 R 1 Q 2 A 7 2 3 6 A B v- yy 950 830 5x 1 8 R 1 Q 3 A 7 2 1 8 A B v- yy 880 820 730 6x 3 6 R 1 Q 3 A 7 2 3 6 A B v- yy 910 850 750 8x 1 8 R 1 Q 4 A 7 2 1 8 A B v- yy 750 700 630 9x 3 6 R 1 Q 4 A 7 2 3 6 A B v- yy 810 760 680 11 x18 R1Q 5 A72 18 A B v- yy 660 630 590 12 x36 R1Q 5 A72 36 A B v- yy 700 670 630 14 x18 R1Q 6 A72 18 A B v- yy 750 700 630 15 x36 R1Q 6 A72 36 A B v- yy 810 760 680 17 x18 R1Q A A72 18 A B v- yy 1220 1160 1070 18 x36 R1Q A A72 36 A B v- yy 1280 1220 1130 20 x18 R1Q B A72 18 A B v- yy 1030 990 920 21 x36 R1Q B A72 36 A B v- yy 1110 1060 990 23 x18 R1Q C A72 18 A B v- yy 820 790 750 24 x36 R1Q C A72 36 A B v- yy 880 850 800 26 x18 R1Q D A72 18 A B v- yy 1220 1160 1070 27 x36 R1Q D A72 36 A B v- yy 1280 1220 1130 29 x18 R1Q E A72 18 A B v- yy 1030 990 920 30 x36 R1Q E A72 36 A B v- yy 1110 1060 990 32 x18 R1Q F A72 18 A B v- yy 820 790 750 33 x36 R1Q F A72 36 A B v- yy 880 850 800 35 x18 R1Q G A72 18 A B v- yy 1070 980 36 x36 R1Q G A72 36 A B v- yy 1150 1060 38 x18 R1Q H A72 18 A B v- yy 920 850 39 x36 R1Q H A72 36 A B v- yy 990 910 41 x18 R1Q J A72 18 A B v- yy 750 710 42 x36 R1Q J A72 36 A B v- yy 800 760 44 x18 R1Q K A72 18 A B v- yy 1070 980 45 x36 R1Q K A72 36 A B v- yy 1150 1060 47 x18 R1Q L A72 18 A B v- yy 920 850 48 x36 R1Q L A72 36 A B v- yy 990 910 50 x18 R1Q M A72 18 A B v- yy 750 710 51 x36 R1Q M A72 36 A B v- yy 800 760 QDR II+ / DDR II+ QDR II / DDR II Frequency (max) (MHz) Cycle Time (min) (ns) No Yes No ODT Part Number Ą 1.5 No Organi- zation 2.5 2.5 Yes QDRII DDRII SIO B2 DDRII+ DDRII B4QDRII+ QDRII+ B4 2.0 DDRII+ 2.0 DDRII+ QDRII+ B4 DDRII+ QDRII+ B4 No Product Type Burst Length Latency (Cycle) Notes: 1. "v" represents the package size. If "v" = "G" then size is 15 x 17 mm, and if "v" = "B" then 13 x 15 mm. 2. "yy" represents the speed bin. "R1QAA7236ABB-20" can operate at 500 MHz(max) of frequency, for example. R10DS0166EJ0011

R1Q4A7236ABB / R1Q4A7218ABB Series Rev. 0.11 : 2013.01.15 PAGE:16 hinS=11111.1111.1111.1111.1111--- 00000.0000.0000.0000.0000--- 00000.0000.0000.0000.0000---072M Standby Supply Current (NOP) Symbol = ISB1. Unit = mA. See Notes 2, 4 and 5 in the next page. 533 500 450 400 375 333 333 300 250 200 yy ă - 1 9- 2 0- 2 2- 2 5- 2 7- 3 0- 3 0- 3 3- 4 0- 5 0 1 x 9 R1Q 2 A72 09 A B v- yy 570 510 2x 1 8 R 1 Q 2 A 7 2 1 8 A B v- yy 670 600 3x 3 6 R 1 Q 2 A 7 2 3 6 A B v- yy 710 630 5x 1 8 R 1 Q 3 A 7 2 1 8 A B v- yy 630 590 520 6x 3 6 R 1 Q 3 A 7 2 3 6 A B v- yy 650 610 540 8x 1 8 R 1 Q 4 A 7 2 1 8 A B v- yy 650 610 560 9x 3 6 R 1 Q 4 A 7 2 3 6 A B v- yy 710 670 610 11 x18 R1Q 5 A72 18 A B v- yy 540 510 480 12 x36 R1Q 5 A72 36 A B v- yy 570 540 500 14 x18 R1Q 6 A72 18 A B v- yy 650 610 560 15 x36 R1Q 6 A72 36 A B v- yy 710 670 610 17 x18 R1Q A A72 18 A B v- yy 870 830 780 18 x36 R1Q A A72 36 A B v- yy 910 870 810 20 x18 R1Q B A72 18 A B v- yy 870 840 780 21 x36 R1Q B A72 36 A B v- yy 960 920 860 23 x18 R1Q C A72 18 A B v- yy 690 660 630 24 x36 R1Q C A72 36 A B v- yy 730 710 670 26 x18 R1Q D A72 18 A B v- yy 870 830 780 27 x36 R1Q D A72 36 A B v- yy 910 870 810 29 x18 R1Q E A72 18 A B v- yy 870 840 780 30 x36 R1Q E A72 36 A B v- yy 960 920 860 32 x18 R1Q F A72 18 A B v- yy 690 660 630 33 x36 R1Q F A72 36 A B v- yy 730 710 670 35 x18 R1Q G A72 18 A B v- yy 780 720 36 x36 R1Q G A72 36 A B v- yy 830 770 38 x18 R1Q H A72 18 A B v- yy 780 720 39 x36 R1Q H A72 36 A B v- yy 860 790 41 x18 R1Q J A72 18 A B v- yy 630 590 42 x36 R1Q J A72 36 A B v- yy 670 630 44 x18 R1Q K A72 18 A B v- yy 780 720 45 x36 R1Q K A72 36 A B v- yy 830 770 47 x18 R1Q L A72 18 A B v- yy 780 720 48 x36 R1Q L A72 36 A B v- yy 860 790 50 x18 R1Q M A72 18 A B v- yy 630 590 51 x36 R1Q M A72 36 A B v- yy 670 630 QDR II+ / DDR II+ QDR II / DDR II Frequency (max) (MHz) Cycle Time (min) (ns) No Yes No ODT Part Number Ą 1.5 No Organi- zation 2.5 2.5 Yes QDRII DDRII SIO B2 DDRII+ DDRII B4QDRII+ QDRII+ B4 2.0 DDRII+ 2.0 DDRII+ QDRII+ B4 DDRII+ QDRII+ B4 No Product Type Burst Length Latency (Cycle) Notes: 1. "v" represents the package size. If "v" = "G" then size is 15 x 17 mm, and if "v" = "B" then 13 x 15 mm. 2. "yy" represents the speed bin. "R1QAA7236ABB-20" can operate at 500 MHz(max) of frequency, for example. R10DS0166EJ0011

R1Q4A7236ABB / R1Q4A7218ABB Series Rev. 0.11 : 2013.01.15 PAGE:17 Common Leakage Currents & Output Voltage Parameter Symbol Min Max Unit Test condition Notes Input leakage current I LI −22 μA1 0 Output leakage current I LO −55 μA1 1 Output high voltage VOH (Low) VDDQ − 0.2 V DDQ V| I OH| ≤ 0.1 mA 8, 9 VOH VDDQ/2 − 0.12 VDDQ/2 + 0.12 V Note 6 8, 9 Output low voltage VOL (Low) VSS 0.2 V I OL ≤ 0.1 mA 8, 9 VOL VDDQ/2 − 0.12 VDDQ/2 + 0.12 V Note 7 8, 9 Notes: 1. All inputs (except ZQ, V REF) are held at either VIH or VIL. 2. I OUT = 0 mA. VDD = VDD max, tKHKH = tKHKH min. 3. Operating supply currents (I DD) are measured at 100% bus utilization. IDD of QDR family is current of device with 100% write and 100% read cycle. IDD of DDR family is current of device with 100% write cycle (if IDD(Write) > IDD(Read)) or 100% read cycle (if IDD(Write) < IDD(Read)). 4. All address / data inputs are static at either V IN > VIH or VIN < VIL. 5. Reference value. (Condition = NOP currents are valid when entering NOP after all pending READ and WRITE cycles are completed. ) 6. Outputs are impedance-controlled. |I OH| = (VDDQ/2)/(RQ/5) for values of 175 Ω≤ RQ ≤ 350 Ω. 7. Outputs are impedance-controlled. I OL = (VDDQ/2)/(RQ/5) for values of 175 Ω≤ RQ ≤ 350 Ω. 8. AC load current is higher than the shown DC values. AC I/O curves are available upon request. 9. HSTL outputs meet JEDEC HSTL Class I and Class II standards. 10. 0 ≤ V IN ≤ VDDQ for all input balls (except VREF, ZQ, TCK, TMS, TDI ball). If R1QD, R1QE, R1QF, R1QK, R1QL, R1QM, R1QP series, balls with ODT do not follow this spec. 11. 0 ≤ VOUT ≤ VDDQ (except TDO ball), output disabled. R10DS0166EJ0011

R1Q4A7236ABB / R1Q4A7218ABB Series Rev. 0.11 : 2013.01.15 PAGE:18 00000.0000.0000.0000.0000---72M_36M AC Test Conditions Input waveform (Rise/fall time ≤ 0.3 ns) 1.25V 0.25V 0.75V 0.75V Test points Output waveform VDDQ/2 Test points V DDQ/2 Capacitance (Ta = +25°C, Frequency = 1.0MHz, VDD =1 . 8 V , VDDQ =1 . 5 V ) Parameter Symbol Min Typ Max Unit Test condition Notes Input capacitance (SA, /R, /W, /BW, D(separate)) CIN ⎯ 45 p F V IN = 0 V 1, 2 Clock input capacitance (K, /K, C, /C) C CLK ⎯ 45 p F V CLK = 0 V 1, 2 Output capacitance (Q(separate), DQ(common), CQ, /CQ) CI/O ⎯ 56 p F V I/O = 0 V 1, 2 Notes: 1. These parameters are sampled and not 100% tested. 2. Except JTAG (TCK, TMS, TDI, TDO) pins. Thermal Resistance Parameter Symbol Airflow Typ Unit Test condition Notes Junction to Ambient șJA 1 m/s 11.0 °C/W EIA/JEDEC JESD51 1Junction to Case șJC -4 . 4 Notes: 1. These parameters are calculated under the condition. These are reference values. 2. Tj = Ta + șJA ™ Pd Tj = Tc + șJC ™ Pd where Tj : junction temperature when the device has achieved a steady-state after application of Pd (rC) Ta : ambient temperature ( rC) Tc : temperature of external surface of the package or case ( rC) șJA : thermal resistance from junction-to-ambient ( rC/W) șJC : thermal resistance from junction-to-case (package) (rC/W) Pd : power dissipation that produced change in junction temperature (W) (cf.JESD51-2A) R10DS0166EJ0011

R1Q4A7236ABB / R1Q4A7218ABB Series Rev. 0.11 : 2013.01.15 PAGE:19 Common AC Operating Conditions Parameter Symbol Min Typ Max Unit Notes Input high voltage V IH (AC) VREF + 0.2 ⎯⎯ V 1, 2, 3, 4 Input low voltage V IL (AC) ⎯⎯ VREF – 0.2 V 1, 2, 3, 4 Notes: 1. All voltages referenced to V SS (GND). During normal operation, VDDQ must not exceed VDD. 2. These conditions are for AC functions only, not for AC parameter test. 3. Overshoot: V IH (AC) ≤ VDDQ + 0.5 V for t ≤ tKHKH/2 Undershoot: VIL (AC) ≥− 0.5 V for t ≤ tKHKH/2 Control input signals may not have pulse widths less than tKHKL (min) or operate at cycle rates less than tKHKH (min). 4. To maintain a valid level, the transitioning edge of the input must: a. Sustain a constant slew rate from the current AC level through the target AC level, VIL (AC) or VIH (AC). b. Reach at least the target AC level. c. After the AC target level is reached, continue to maintain at least the target DC level, VIL (DC) or VIH (DC). Output load conditions Output load and voltage conditions 50Ω ZQ Q VREF 250Ω Z0 = 50Ω SRAM VDDQ / 2 = 0.75V VDDQ / 2 = 0.75V VDD VDDQ VSS 1.8V±0.1V 1.5V R10DS0166EJ0011

R1Q4A7236ABB / R1Q4A7218ABB Series Rev. 0.11 : 2013.01.15 PAGE:20 hinS=11111.0000.0000.0000.0000--- 11111.0000.0000.0000.0000--- AC Characteristics (QDR-II, DDR-II series) (VDD =1 . 8 V±0.1V , VDDQ =1 . 5 V , VREF = 0.75V) Parameter Symbol -30 -33 -40 -50 ⎯ ⎯ Unit NotesMin Max Min Max Min Max Min Max Min Max Min Max Clock Average clock cycle time (K, /K, C, /C) Clock high time Clock low time Clock to /clock /Clock to clock Clock to data clock (K to C, /K to /C) tKHCH 0 1.35 0 1.49 0 1.80 0 2.20 ⎯ ⎯ ⎯ ⎯ ns DLL/PLL Timing Clock phase jitter (K, /K, C, /C) tKC var ⎯ 0.20 ⎯ 0.20 ⎯ 0.20 ⎯ 0.20 ⎯ ⎯ ⎯ ⎯ ns 3 Lock time (K, C) tKC lock 1024 ⎯ 1024 ⎯ 1024 ⎯ 1024 ⎯ ⎯ ⎯ ⎯ ⎯ Cy- cle 2 K static to DLL/PLL reset tKC reset 30 ⎯ 30 ⎯ 30 ⎯ 30 ⎯ ⎯ ⎯ ⎯ ⎯ ns 7 Output Times C, /C high to output valid tCHQV ⎯ 0.45 ⎯ 0.45 ⎯ 0.45 ⎯ 0.45 ⎯ ⎯ ⎯ ⎯ ns 9 C, /C high to output hold tCHQX −0.45 ⎯ −0.45 ⎯ −0.45 ⎯ −0.45 ⎯ ⎯ ⎯ ⎯ ⎯ ns 9 C, /C high to echo clock valid C, /C high to echo clock hold tCHCQX −0.45 ⎯ −0.45 ⎯ −0.45 ⎯ −0.45 ⎯ ⎯ ⎯ ⎯ ⎯ ns 9 CQ, /CQ high to output valid CQ, /CQ high to output hold C, /C high to output high-Z tCHQZ ⎯ 0.45 ⎯ 0.45 ⎯ 0.45 ⎯ 0.45 ⎯ ⎯ ⎯ ⎯ ns 5, 6, 9 C, /C high to output low-Z tCHQX1 −0.45 ⎯ −0.45 ⎯ −0.45 ⎯ −0.45 ⎯ ⎯ ⎯ ⎯ ⎯ ns 5, 9 R10DS0166EJ0011

R1Q4A7236ABB / R1Q4A7218ABB Series Rev. 0.11 : 2013.01.15 PAGE:21 hinS=11111.0000.0000.0000.0000--- 11111.0000.0000.0000.0000--- Parameter Symbol Unit NotesMin Max Min Max Min Max Min Max Min Max Min Max Setup Times Address valid to K rising edge tAVKH ns 1tAVKH Control inputs valid to K rising edge tIVKH ns 1tIVKH Data-in valid to K, /K rising edge Hold Times K rising edge to address hold tKHAX ns 1tKHAX K rising edge to control inputs hold tKHIX ns 1tKHIX K, /K rising edge to data-in hold Notes: 1. This is a synchronous device. All addresses, data and control lines must meet the specified setup and hold times for all latching clock edges. 2. V DD and VDDQ slew rate must be less than 0.1 V DC per 50 ns for DLL/PLL lock retention. DLL/PLL lock time begins once VDD , VDDQ and input clock are stable. It is recommended that the device is kept inactive during these cycles. This specification meets the QDR common spec. of 20 us. 3. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 4. Echo clock is very tightly controlled to data valid / data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guardbands and test setup variations. 5. Transitions are measured ±100 mV from steady-state voltage. 6. At any given voltage and temperature t CHQZ is less than tCHQX1 and tCHQV. 7. These parameters are sampled. 8. When x18 and x36 configuration except QDRII-B2 are operated at less than 180MHz, DLL/PLL should be disabled (/DOFF=L). Please contact Renesas if these devices are always used at less than 180MHz with DLL/PLL operation. 9. t CHQV,t CHQX,t CHCQV,t CHCQX,t CHQZ,t CHQX1 spec of R1Q3A and R1Q4A series is determined by the actual frequency regardless of Part Number (Marking Name). The following is the spec for the actual frequency. tCHQV,t CHCQV,t CHQZ = 0.45 ns for • 200 MHz and 0.50 ns for < 200 MHz tCHQX,t CHCQX,t CHQX1 = -0.45 ns for • 200 MHz and -0.50 ns for < 200 MHz Remarks: 1. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise noted. 2. Control input signals may not be operated with pulse widths less than t KHKL (min). 3. If C, /C are tied high, K, /K become the references for C, /C timing parameters. 4. V DDQ is +1.5 V DC. VREF is +0.75 V DC. 5. Control signals are /R, /W (QDR series), /LD, R-/W (DDR series), /BW, /BW0, /BW1, /BW2 and /BW3. Setup and hold times of /BWx signals must be the same as those of Data-in signals. R10DS0166EJ0011

R1Q4A7236ABB / R1Q4A7218ABB Series Rev. 0.11 : 2013.01.15 PAGE:22 R1Q4 1 2 3 4 5 6 7 8 9 10 11 12 13 K, /K Q00Qx1 Q01 Q10 Q11 Q20 Q21 Q30 NOP READ (burst of 2) READ (burst of 2) WRITE (burst of 2)NOP NOP tKHAXtAVKH /LD:R-/W SA tCHQV -tCHQX tCHQV -tCHQX tCQHQV -tCQHQX -tCHQX1 tCHCQV -tCHCQX tCHCQV -tCHCQX tKHKH tKHKL tKLKH tKH/KH t/KHKH tKHKH tKHKL tKLKH tKH/KH t/KHKH tKHCH tKHCH DQ CQ /CQ C K tKHIXtIVKH WRITE (burst of 2) READ (burst of 2) 00 0101 01 1x 1x 00 D40 D41 D50 D51 D60 D61 D70 D71Q31 tCHQZ A6A4 tKHDX tDVKH tKHDX tDVKH Q80 Notes: 1. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, etc. 2. Outputs are disabled (high-Z) N clock cycle after the last read cycle. Here, N = Read Latency + Burst Length × 0.5. 3. In this example, if address A8 = A7, then data Q80 = D70, Q81 = D71, etc. Write data is forwarded immediately as read results. 4. To control read and write operations, /BW signals must operate at the same timing as Data-in signals. 5. The second NOP cycle is not necessary for correct device operation; however, at high clock frequencies it may be required to prevent bus contention. READ (burst of 2) READ (burst of 2) WRITE (burst of 2) WRITE (burst of 2) 01 01 00 00 READ (burst of 2) A1 A3 A5 A8A7 A9 Timing Waveforms (DDRII, B2, Read Latency = 1.5 cycle) R10DS0166EJ0011

R1Q4A7236ABB / R1Q4A7218ABB Series Rev. 0.11 : 2013.01.15 PAGE:23 JTAG Specification These products support a limited set of JTAG functions as in IEEE standard 1149.1. Disabling the Test Access Port It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfering with normal operation of the device, TCK must be tied to VSS to preclude mid level inputs. TDI and TMS are internally pulled up and may be unconnected, or may be connected to VDD through a pull up resistor. TDO should be left unconnected. Test Access Port (TAP) Pins Symbol I/O Pin assignments Description Notes TCK 2R Test clock input. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS 10R Test mode select. This is the command input for the TAP controller state machine. TDI 11R Test data input. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP controller state machine and the instruction that is currently loaded in the TAP instruction. TDO 1R Test data output. Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. Notes: The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high for five rising edges of TCK. The TAP controller state is also reset on SRAM POWER-UP. Common R10DS0166EJ0011

R1Q4A7236ABB / R1Q4A7218ABB Series Rev. 0.11 : 2013.01.15 PAGE:24 TAP DC Operating Characteristics (VDD =1 . 8 V±0.1V) Parameter Symbol Min Typ Max Unit Notes Input high voltage V IH +1.3 ⎯ VDD + 0.3 V Input low voltage V IL −0.3 ⎯+ 0.5 V Input leakage current I LI −5.0 ⎯+ 5.0 μA0 V ≤ VIN ≤ VDD Output leakage current I LO −5.0 ⎯+ 5.0 μA 0 V ≤ VIN ≤ VDD, output disabled Output low voltage VOL1 ⎯⎯ 0.2 V I OLC = 100 μA VOL2 ⎯⎯ 0.4 V I OLT = 2 mA Output high voltage VOH1 1.6 ⎯⎯ V| I OHC| = 100 μA VOH2 1.4 ⎯⎯ V| I OHT| = 2 mA Notes: 1. All voltages referenced to V SS (GND). 2. At power-up, V DD and VDDQ are assumed to be a linear ramp from 0V to VDD(min.) or VDDQ(min.) within 200ms. During this time VDDQ < VDD and VIH < VDDQ. During normal operation, VDDQ must not exceed VDD. Common R10DS0166EJ0011

R1Q4A7236ABB / R1Q4A7218ABB Series Rev. 0.11 : 2013.01.15 PAGE:25 TAP AC Test Conditions Parameter Symbol Conditions Unit Notes Input timing measurement reference levels V REF 0.9 V Input pulse levels V IL, VIH 0 to 1.8 V Input rise/fall time tr, tf ≤ 1.0 ns Output timing measurement reference levels 0.9 V Test load termination supply voltage (VTT) 0.9 V Output load See figures Common External Load at Test 50Ω VTT = 0.9V TDO Z 0 = 50Ω DUT 20pF 1.8V Input waveform 0.9V 0.9V Test points Output waveform 0.9V Test points 0.9V Output load condition R10DS0166EJ0011

R1Q4A7236ABB / R1Q4A7218ABB Series Rev. 0.11 : 2013.01.15 PAGE:26 TAP AC Operating Characteristics (VDD =1 . 8 V±0.1V) Parameter Symbol Min Typ Max Unit Notes Test clock (TCK) cycle time t THTH 50 ⎯⎯ ns TCK high pulse width t THTL 20 ⎯⎯ ns TCK low pulse width t TLTH 20 ⎯⎯ ns Test mode select (TMS) setup t MVTH 5 ⎯⎯ ns TMS hold t THMX 5 ⎯⎯ ns Capture setup t CS 5 ⎯⎯ ns 1 Capture hold t CH 5 ⎯⎯ ns 1 TDI valid to TCK high t DVTH 5 ⎯⎯ ns TCK high to TDI invalid t THDX 5 ⎯⎯ ns TCK low to TDO unknown t TLQX 0 ⎯⎯ ns TCK low to TDO valid t TLQV ⎯⎯ 10 ns Notes: 1. t CS + tCH defines the minimum pause in RAM I/O pad transitions to assure pad data capture. Common R10DS0166EJ0011

R1Q4A7236ABB / R1Q4A7218ABB Series Rev. 0.11 : 2013.01.15 PAGE:27 Test Access Port Registers Register name Length Symbol Notes Instruction register 3 bits IR [2:0] Bypass register 1 bit BP ID register 32 bits ID [31:0] Boundary scan register 109 bits BS [109:1] TAP Controller Timing Diagram TCK TDI TMS TDO PI (SRAM) tTHTLtTHTH tTLTH tMVTH tTHMX tDVTH tTHDX tCS tCH tTLQV tTLQX Common R10DS0166EJ0011

R1Q4A7236ABB / R1Q4A7218ABB Series Rev. 0.11 : 2013.01.15 PAGE:28 TAP Controller Instruction Set IR2 IR1 IR0 Instruction Description Notes 0 0 0 EXTEST The EXTEST instruction allows circuitry external to the component package to be tested. Boundary scan register cells at output balls are used to apply test vectors, while those at input balls capture test results. Typically, the first test vector to be applied using the EXTEST instruction will be shifted into the boundary scan register using the PRELOAD instruction. Thus, during the Update-IR state of EXTEST, the output driver is turned on and the PRELOAD data is driven onto the output balls. 1, 2, 3, 5 0 0 1 IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in capture-DR mode and places the ID register between the TDI and TDO balls in shift- DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. 0 1 0 SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z), moving the TAP controller into the capture-DR state loads the data in the RAMs input into the boundary scan register, and the boundary scan register is connected between TDI and TDO when the TAP controller is moved to the shift-DR state. 3, 4, 5 0 1 1 RESERVED The RESERVED instructions are not implemented but are reserved for future use. Do not use these instructions.

100 SAMPLE

(/PRELOAD) When the SAMPLE instruction is loaded in the instruction register, moving the TAP controller into the capture-DR state loads the data in the RAMs input and I/O buffers into the boundary scan register. Because the RAM clock(s) are independent from the TAP clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state). Although allowing the TAP to SAMPLE metastable input will not harm the device, repeatable results cannot be expected. Moving the controller to shift-DR state then places the boundary scan register between the TDI and TDO balls. 3, 5 1 0 1 RESERVED - 1 1 0 RESERVED - 1 1 1 BYPASS The BYPASS instruction is loaded in the instruction register when the bypass register is placed between TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. Notes: 1. Data in output register is not guaranteed if EXTEST instruction is loaded. 2. After performing EXTEST, power-up conditions are required in order to return part to normal operation. 3. RAM input signals must be stabilized for long enough to meet the TAPs input data capture setup plus hold time (t CS plus tCH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the boundary scan register. 4. Clock recovery initialization cycles are required after boundary scan. 5. For R1QD, R1QE, R1QF, R1QK, R1QL, R1QM, R1QP series, ODT is disabled in EXTEST, SAMPLE-Z or SAMPLE mode. Common R10DS0166EJ0011

R1Q4A7236ABB / R1Q4A7218ABB Series Rev. 0.11 : 2013.01.15 PAGE:29 Boundary Scan Order Bit # Ball ID Signal names Bit # Ball ID Signal names x9 x18 x36 x9 x18 x36

16 R /C or NC

/C or NC or ODT /C or NC or ODT 36 10E NC NC DQ15

26 P C

C or QVLD C or QVLD 37 10D NC NC NC 3 6 N S AS AS A 3 8 9 E N CN CN C 4 7 P S AS AS A 3 9 1 0 C N C D Q 7 D Q 1 7 5 7N SA SA SA 40 11D NC NC DQ16 6 7 R S AS AS A 4 1 9 C N CN CN C 7 8 R S AS AS A 4 2 9 D N CN CN C 8 8 P S AS AS A 4 3 1 1 B D Q 4 D Q 8 D Q 8 9 9R SA SA SA 44 11C NC NC DQ7 10 11P DQ0 DQ0 DQ0 45 9B NC NC NC 11 10P NC NC DQ9 46 10B NC NC NC 12 10N NC NC NC 47 11A CQ CQ CQ 13 9P NC NC NC 48 10A SA SA SA 14 10M NC DQ1 DQ11 49 9A SA SA SA 1 5 1 1 N N CN C D Q 1 0 5 0 8 B S AS AS A 16 9M NC NC NC 51 7C SA SA SA 17 9N NC NC NC 52 6C SA SA0 or NC SA0 or NC 18 11L DQ1 DQ2 DQ2 53 8A /LD /LD /LD 19 11M NC NC DQ1 54 7A NC NC /BW1 20 9L NC NC NC 55 7B /BW /BW0 /BW0 21 10L NC NC NC 56 6B K K K 2 2 1 1 K N C D Q 3 D Q 3 5 7 6 A / K/ K/ K 23 10K NC NC DQ12 58 5B NC NC /BW3 24 9J NC NC NC 59 5A NC /BW1 /BW2 25 9K NC NC NC 60 4A R-/W R-/W R-/W 26 10J DQ2 DQ4 DQ13 61 5C SA SA SA 27 11J NC NC DQ4 62 4B SA SA SA 2 8 1 1 H Z QZ QZ Q 6 3 3 A S AS AS A 29 10G NC NC NC 64 2A SA SA NC 30 9G NC NC NC 65 1A /CQ /CQ /CQ 3 1 1 1 F N CD Q 5 D Q 5 6 6 2 B N CD Q 9 D Q 2 7 3 2 1 1 G N CN C D Q 1 4 6 7 3 B N CN C D Q 1 8 33 9F NC NC NC 68 1C NC NC NC 34 10F NC NC NC 69 1B NC NC NC 35 11E DQ3 DQ6 DQ6 70 3D NC DQ10 DQ19 R10DS0166EJ0011

R1Q4A7236ABB / R1Q4A7218ABB Series Rev. 0.11 : 2013.01.15 PAGE:30 Boundary Scan Order Bit # Ball ID Signal names Bit # Ball ID Signal names x9 x18 x36 x9 x18 x36 71 3C NC NC DQ28 91 2L DQ7 DQ15 DQ33 72 1D NC NC NC 92 3L NC NC DQ24 73 2C NC NC NC 93 1M NC NC NC 74 3E DQ5 DQ11 DQ20 94 1L NC NC NC 75 2D NC NC DQ29 95 3N NC DQ16 DQ25 76 2E NC NC NC 96 3M NC NC DQ34 77 1E NC NC NC 97 1N NC NC NC 78 2F NC DQ12 DQ30 98 2M NC NC NC 79 3F NC NC DQ21 99 3P DQ8 DQ17 DQ26 80 1G NC NC NC 100 2N NC NC DQ35 81 1F NC NC NC 101 2P NC NC NC 82 3G DQ6 DQ13 DQ22 102 1P NC NC NC 83 2G NC NC DQ31 103 3R SA SA SA 84 1H /DOFF /DOFF /DOFF 104 4R SA SA SA 85 1J NC NC NC 105 4P SA SA SA 86 2J NC NC NC 106 5P SA SA SA 87 3K NC DQ14 DQ23 107 5N SA SA SA 88 3J NC NC DQ32 108 5R SA SA SA 89 2K NC NC NC 109 ⎯ INTER- NAL INTER- NAL INTER- NAL Notes: In boundary scan mode, 1. Clock balls (K, /K, C, /C) are referenced to each other and must be at opposite logic levels for reliable operation. 2. CQ and /CQ data are synchronized to the respective C and /C (except EXTEST, SAMPLE-Z). 3. If C and /C tied high, CQ is generated with respect to K and /CQ is generated with respect to /K (except EXTEST, SAMPLE-Z). R10DS0166EJ0011

R1Q4A7236ABB / R1Q4A7218ABB Series Rev. 0.11 : 2013.01.15 PAGE:31 TAP Controller State Diagram Notes: The value adjacent to each state transition in this figure represents the signal present at TMS at the time of a rising edge at TCK. No matter what the original state of the controller, it will enter Test-Logic-Reset when TMS is held high for at least five rising edges of TCK. Select IR Scan Capture IR Shift IR Exit1 IR Pause IR Exit2 IR Update IR Select DR Scan Capture DR Shift DR Exit1 DR Pause DR Exit2 DR Update DR Run Test/Idle 010 1 Test Logic Reset Common ID Register 䊼 䊼 # 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 S y m b o l R R R0C M M M A W W01Q Q Q B O S0010001000111 RRR Q 000 0 001 1 010 Q 011 0 CQ MMM B 010 0 011 1 101 O 110 0 WW 1 Density = 72Mb Density = 36Mb Latency=1.5 (@II), Latency=2.0 (@II+) Latency=2.5 (@II+) Burst Length = 2 word burst Revison 0 II (QDR-II, DDR-II) Revison 1 Revison 2 Revison 3 Start bit (0) ăŇ Revision number (31 :29) Type number (28 : 12) x36 36M&72M w/o ODT, 144M,288M 36M&72M w/ ODT 144M&288M w/o ODT, 36M,72M 144M&288M w/ ODT Burst Length = 4 word burst Density = 144Mb Density = 288Mb Common I/O Separate I/O Vendor JEDEC code x18 (11 : 1) II+ (QDR-II+, DDR-II+) DDR QDR with ODT without ODT R10DS0166EJ0011

R1Q4A7236ABB / R1Q4A7218ABB Series Rev. 0.11 : 2013.01.15 PAGE:32 Package Dimensions and Marking Information Both Pb parts and Pb-free parts are available. hinS=11111.1111.1111.1111.1111--- 11111.1111.1111.1111.1111--- 00000.0000.0000.0000.0000---72M_36M -y S - Øx(M) S AB Top View Side View Bottom View Marking Information 1st row : Vender name (R ENESAS) 2nd row: Part number 3rd row : Y : Year code WW : Week code XXXX : Renesas internal use 4th row : Country name (JAPAN) + "None" --- Pb -free parts + "PB-F" --- Pb-free parts S A ZE ZD ABCDEFGHJKLMNPR 123456789 1 0 1 1 [e] [e] Øb Index Mark A D Index Mark (Laser Mark) B E R1Q4A7218ABB-30R YWWXXXX JAPAN PB-F This part number or mark is just one example. P-LBGA165-13x15-1.00 PLBG0165FE-A 165FHG 0.5g Reference Symbol Dimension in mm Min Nom Max D 12.9 13.0 13.1 E 14.9 15.0 15.1 A - - 1.4 A1 0.31 0.36 0.41 [e] - 1.0 - b 0.45 0.5 0.6 x - - 0.2 y - - 0.15 ZD - 2.5 - ZE - 1.5 - R10DS0166EJ0011

R1Q4A7236ABB / R1Q4A7218ABB Series Rev. 0.11 : 2013.01.15 PAGE:33 hinS=00100.0000.0000.0000.0000--- 00000.0000.0000.0000.0000--- 00000.0000.0000.0000.0000---72M_DDRII_B4 Appendix Example of DC/AC characteristics data tKHKH (Clock cycle time) Shmoo (Ta=70 degC) 6+/' 05 05 05 05 05 05 8QNVCIG 8 2222222222222222222222222222222222 8 2222222222222222222222222222222222 2 2CU U 8 2222222 222222222222222 222222222222222 222222222 52'% 8 2222222 222222222222222 222222222222222 222222222 8 2222222 222222222222222 222222222222222 222222222 8 2222222 222222222222222 222222222222222 222222222 8 2222222 222222222222222 222222222222222 222222222 8 2222222222222222222222222222222222 8 2222222222222222222222222222222222 05 05 05 05 05 05 tKHKH tCHQV (C, /C high to output valid) Shmoo (Ta=70 degC) 6+/' 25 25 25 25 25 25 8QNVCIG 8 22222222222222222222222222222222 8 22222222222222222222222222222222 2 2CU U 8 222222222222222222222222222 222222222 52'% 8 222222222222222222222222222 222222222 8 222222222222222222222222222 222222222 8 222222222222222222222222222 222222222 8 222222222222222222222222222 222222222 8 22222222222222222222222222222222 8 22222222222222222222222222222222 25 25 25 25 25 25 tCHQV Vdd Vdd Parts Number : R1Q4A7218RBG-30R IDD (Operating supply current) - tKHKH (Ta=70 degC) ᵒᵎᵎ ᵔᵎᵎ ᵖᵎᵎ ᵏᵎᵎᵎ ᵐᵌᵓ ᵑᵌᵓ ᵒᵌᵓ ᵓᵌᵓ ᶒᵩᵦᵩᵦᴾᵆᶌᶑᵇ ᵧᶂᶂᴾᵆᶋᵟᵇ ᵱᵮᵣᵡ ᵴᶂᶂᵛᵏᵌᵕᵴ ᵴᶂᶂᵛᵏᵌᵖᵴ ᵴᶂᶂᵛᵏᵌᵗᵴ ᵫᶃᵿᶑᶓᶐᶃᶂᴾᶂᵿᶒᵿ R10DS0166EJ0011

R1Q4A7236ABB / R1Q4A7218ABB Series Rev. 0.11 : 2013.01.15 PAGE:34 hinS=11111.1111.1111.1111.1111--- 11111.1111.1111.1111.1111--- 00000.0000.0000.0000.0000---72M_36M

Revision History

Rev. Date Description Revision History (1) 4GX &CVG %QOOGPV 4GXC +PKVKCNKUUWG 4GXD %QTTGEVGFV[RQUKP&%%JCTCEVGTKUVKEU 81*81.8&&3dăd 4GXE #FFGF5RGGF$KP6CDNG #FFGF1&6VKOKPIEJCTVVQ3&4++ CPF&&4++ UGTKGU %QTTGEVGFV[RQUKP)GPGTCN&GUETKRVKQP 7RFCVGF4GEQOOGPFGF&%1RGTCVKPI%QPFKVKQPU 8TGH᳸8ă᳸ UGTKGU #FFGFEQOOGPVVQ6JGTOCN4GUKUVCPEGUGEVKQP 6JGUGCTGTGHGTGPEGXCNWGU 4GXG #FFGF)GPGTCVKQP0WODGT6CDNG %JCPIGF/CTMKPI0COGKP2CTV0WODGT&GHKPKVKQP6CDNG #FFGFOCTMKPIKPHQTOCVKQPVQ2CEMCIG&KOGPUKQP+PHQTOCVKQPUGEVKQP %QTTGEVGF1&61P1HHVKOKPIKP1&6RKPVCDNG 7RFCVGFOKPKOWOHTGSWGPE[QH3&4++ CPF&&4++ UGTKGU %JCPIGFRKPPCOGKP2KP#TTCPIGOGPVQH&&4++ UGTKGU 5#5#ă0% #FFGFVJGTQYVQ-6TWVJ6CDNG 4.CPF4. 7RFCVGF5'672E[ENGU UGTKGU&..NQEMVKOGWUăE[ENG #FFGFEQOOGPVVQ1&6QPQHH6KOKPI%JCTVUGEVKQP 1&6QPQHHUYKVEJKPI VKOKPIUCTGGFIGCNKIPGFYKVJ%3QT%3 7RFCVGF6JGTOCN4GUKUVCPEG 4GXJ #FFGFURGGFDKPVQ3&4++$ZZUGTKGU 7RFCVGF2CEMCIG&KOGPUKQPU /CUUăI# OCZ ăOO 7RFCVGF1RGTCVKPI5VCPFD[5WRRN[%WTTGPVU #FFGFEQOOGPVVQ2QYGTWRCPF+PKVKCNK\\CVKQP5GSWGPEGUGEVKQP #RRN[8TGH CHVGT8FFSQTCVVJGUCOGVKOGCU8FFS 7RFCVGF5RGGF$KP6CDNG #FFGF4GPGUCU3&454#/*QOGRCIG74.VQPQVGUQHHTQPVRCIG 7RFCVGF2QYGTWRCPF+PKVKCNK\\CVKQP5GSWGPEG 7RFCVGF&..%QPUVTCKPVU 7RFCVGF1RGTCVKPI5WRRN[%WTTGPVCPF5VCPFD[5WRRN[%WTTGPV 7RFCVGF6JGTOCN4GUKUVCPEG %JCPIGFTGOCTMUQH#%%JCTCEVGTKUVKEUQP%QPVTQNUKIPCNU %JCPIGFEQORCP[PCOG4'0'5#5NQIQCPFDCUGEQNQTHTQOVJQUGQH4GPGUCU 6GEJPQNQI[VQ4GPGUCU'NGEVTQPKEU %JCPIGFXGPFGTPCOGOCTMKPIKP2CEMCIG&KOGPUKQPUCPF/CTMKPI+PHQTOCVKQP UGEVKQP #FFGF#IGPGTCVKQPVQ/UGTKGU %JCPIGFVJGRKPFGUETKRVKQPHQT0%RKP %JCPIGFPQVGQH6#2%QPVTQNNGT+PUVTWEVKQP5GV %NQEMTGEQXGT[ KPKVKCNK\\CVKQPE[ENGUCTGTGSWKTGFCHVGTDQWPFCT[UECP %JCPIGF8FFSTCPIGQH++ UGTKGU 8FFSd8ă8᳸8FF #FFGF0QVGCPF0QVGVQ#%%JCTCEVGTKUVKEUVCDNGHQT++ UGTKGU 7RFCVGF5RGGF$KP6CDNGHQT/ #FFGF0QVGVQ)GPGTCVKQP0WODGT6CDNG 7RFCVGF5RGGF$KP6CDNGHQT/CPF/ 4GXE 7RFCVGF1RGTCVKPI5WRRN[%WTTGPVCPF5VCPFD[5WRRN[%WTTGPV6CDNGHQT/ CPF/ 4GXC %JCPIGF+PKVKCNK\\CVKQP5GSWGPEG +PKVKCNE[ENGQH++ UGTKGUE[ENGU ăWU 4GXC #FFGF0QVGVQ#%%JCTCEVGTKUVKEUVCDNGHQT++UGTKGU 7RFCVGF#%%JCTCEVGTKUVKEUHQTVJGUGTKGUQH4. 7RFCVGF5RGGF$KP6CDNGHQT/// #FFGF430#432#UGTKGUVQ/3&4NKPGWR %JCPIGF,6#)+&4GIKUVGT +&%QFG //YQ1&6// //Y1&6 //YQ1&6// //Y1&6 ă ă 4GXC 4GXD 4GXD 4GXC 4GXC 4GXF 4GX᳠ 4GXC 4GXI 4GXK 4GXC R10DS0166EJ0011

R1Q4A7236ABB / R1Q4A7218ABB Series Rev. 0.11 : 2013.01.15 PAGE:35 hinS=11111.1111.1111.1111.1111--- 11111.1111.1111.1111.1111--- 00000.0000.0000.0000.0000---72M_36M Revision History (2) R10DS0166EJ0011

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