R1QBA3636CBB

R1QBA3636CBB_15 RENESAS | Alldatasheet

Document overview

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Technical content

Features

႑ Power Supply

• 1.8 V for core (VDD), 1.4 V to VDD for I/O (VDDQ)

႑ Clock

 Fast clock cycle time for high bandwidth  Two input clocks (K and /K) for precise DDR timing at clock rising edges only  Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems  Clock-stop capability with Ps restart

႑ I/O

 Common data input/output bus  Pipelined double data rate operation  HSTL I/O  User programmable output impedance  DLL/PLL circuitry for wide output data valid wi ndow and future frequency scaling  Data valid pin (QVLD) to indicate valid data on the output

႑ Function

 Two-tick burst for low DDR transaction size  Internally self-timed write control  Simple control logic for easy depth expansion  JTAG 1149.1 compatible test access port

႑ Package

 165 FBGA package (13 x 15 x 1.4 mm)

Description

The R1Q#A3636 is a 1,048,576-word by 36-bit and the R1Q#A3618 is a 2,097,152-word by 18-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products are suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration. These products are packaged in 165-pin plastic FBGA package. # = B: Latency =2.5, w/o ODT # = H: Latency =2.0, w/o ODT # = E: Latency =2.5, w/ ODT # = L: Latency =2.0, w/ ODT 36-Mbit DDRII+ SRAM 2-word Burst R1QBA3636CBB / R1QBA3618CBB / R1QBA3609CBB R1QEA3636CBB / R1QEA3618CBB / R1QEA3609CBB R1QHA3636CBB / R1QHA3618CBB / R1QHA3609CBB R1QLA3636CBB / R1QLA3618CBB / R1QLA3609CBB Notes: 1. QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, Samsung, and Renesas Electronics Corp. (QDR Co-Development Team) 2. The specifications of this device are subject to ch ange without notice. Please contact your nearest Renesas Electronics Sales Office regarding specifications. 3. Refer to "http://www.renesas.com/products/memory/fast_sram/qdr_sram/qdr_sram_root.jsp" for the latest and detailed information. 4. Descriptions about x9 parts in this datasheet are just for reference. R10DS0193EJ0010 R10DS0193EJ0010

PAGE : 2 Rev. 0.10b : 2012.03.12 R1QBA36C / R1QEA36C Series Part Number Definition Common 0Q %QOOGPVU 0Q %QOOGPVU 0Q %QOOGPVU 4 4GPGUCU/GOQT[2TGHKZ # 8FF8 (TGSWGPE[/*\\ 3 3&4++$= ? &GPUKV[/D (TGSWGPE[/*\\ 3 3&4++$ &GPUKV[/D (TGSWGPE[/ *\\ 3 &&4++$ &GPUKV[/D (TGSWGPE[/ *\\ 3 &&4++$ &GPUKV[/D (TGSWGPE[/ *\\ 3 &&4++$5+1= &CVCYKFVJDKV (TGSWGPE[/*\\ 3# 3&4++ $.= ? &CVCYKFVJDKV (TGSWGPE[/*\\ 3$ &&4++ $. &CVCYKFVJDKV (TGSWGPE[/*\\ 3% &&4++ $. 4 UV)GPGTCVKQP (TGSWGPE[/*\\ 3& 3&4++ $.Y1&6 ? # PF)GPGTCVKQP (TGSWGPE[/*\\ 3' &&4++ $.Y1&6 $ TF)GPGTCVKQP (TGSWGPE[/*\\ 3( &&4++ $.Y1&6 % VJ)GPGTCVKQP (TGSWGPE[/*\\ 3) 3&4++ $. & VJ)GPGTCVKQP 3* &&4++ $. ' VJ)GPGTCVKQP 3, &&4++ $. ( VJ)GPGTCVKQP 3- 3&4++ 3. &&4++ $.Y1&6 $# # 2D HTGGCPF6TC[ 3/ &&4++ $.Y1&6 $$ $ 2DHTGGCPF6TC[ 30 3&4++ $. 6 2D HTGGCPF6CRG4GGN 32 3&4++ $.Y1&6 5 2DHTGGCPF6CRG4GGN 0QVG ?$$WTUVNGPIVJ $WTUVNGPIVJ$ $WTUVNGPIV J ?.4GCF.CVGPE[ 4GCF.CVGPE[E[ENG. E[ENG. E[ENG ?5+15GRCTCVG+1 ?1&61PFKGVGTOKPCVKQP 0QVG 2CEMCIG/CTMKPI0COG 2DHTGGRCTVU /CTMKPI0COG2CTV0WODGT 2DHTGGRCTVU /CTMKPI0COG2CTV0WODGT 2$( 'ZCORNG 43##4$)42D(2DHTGGRCTVU 'ZCORNG 43##4$)42$(2DHTGGRCTVU 0QVG 2D HTGG 4Q*5%QORNKCPEG.GXGN 2DHTGG 4Q*5%QORNKCPEG.GXGN 0QVG #UGTKGUUWRRQTVDQVJ%QOOGTEKCNCPF+PFWUVTKCNV GORGTCVWTGU D[+PFWUVTKCNVGORGTCVWTGRCTVU 4 %QOOGTEKCNVGOR 6CTCPIGé᳸é +PFWUVTKCNVGOR 6CTCPIGé᳸é+ \#\< QT0QPG 4GPGUCUKPVGTPCNWUG 2-)$)#ZOO Part Number Definition Table The above part number is just example for 144M QDRII B2 x18 250MHz, 15x17mm PKG, Pb-free part. 0BR04-GBR8144A2Q1RExample 1615141312-11109876543210Column No. R10DS0193EJ0010

PAGE : 3 Rev. 0.10b : 2012.03.12 R1QBA36C / R1QEA36C Series hinS=00000.0000.0000.0000.0000--- 00000.1111.1111.1111.1111--- 00000.0000.0000.0000.0000---036M-II+ 533 500 450 400 375 333 333 300 250 200 yy ă - 1 9- 2 0- 2 2- 2 5- 2 7- 3 0- 3 0- 3 3- 4 0- 5 0 17 x18 R1Q A A36 18 C B v- yy 18 x36 R1Q A A36 36 C B v- yy 20 x18 R1Q B A36 18 C B v- yy 21 x36 R1Q B A36 36 C B v- yy 23 x18 R1Q C A36 18 C B v- yy 24 x36 R1Q C A36 36 C B v- yy 26 x18 R1Q D A36 18 C B v- yy 27 x36 R1Q D A36 36 C B v- yy 29 x18 R1Q E A36 18 C B v- yy 30 x36 R1Q E A36 36 C B v- yy 32 x18 R1Q F A36 18 C B v- yy 33 x36 R1Q F A36 36 C B v- yy 35 x18 R1Q G A36 18 C B v- yy 36 x36 R1Q G A36 36 C B v- yy 38 x18 R1Q H A36 18 C B v- yy 39 x36 R1Q H A36 36 C B v- yy 41 x18 R1Q J A36 18 C B v- yy 42 x36 R1Q J A36 36 C B v- yy 44 x18 R1Q K A36 18 C B v- yy 45 x36 R1Q K A36 36 C B v- yy 47 x18 R1Q L A36 18 C B v- yy 48 x36 R1Q L A36 36 C B v- yy 50 x18 R1Q M A36 18 C B v- yy 51 x36 R1Q M A36 36 C B v- yy -25 -25 -25 -25 -25 -25 -20 -20 -22 -22 Organi- zation -20 -20 -20 -20 No Product Type Burst Length Latency (Cycle)2.0 DDRII+ QDRII+ B4 DDRII+ QDRII+ B4 QDRII+ B4 2.0 DDRII+ Yes DDRII+ B4QDRII+ -19 -19 2.5 2.5B2 -19 -19 -19 -19 -22 -22 -22 -22 Frequency (max) (MHz) Cycle Time (min) (ns) No Yes No ODT Part Number Ą QDR II+ / DDR II+ QDR II / DDR II 36M QDR II+ / DDR II+ SRAM Lineup - Renesas supports or plans to support the parts listed below. Notes: 1. "v" represents the package size. If "v" = "G" then size is 15 x 17 mm, and if "v" = "B" then 13 x 15 mm. 2. "yy" represents the speed bin. "R1QAA3636CBG-20" can operate at 500 MHz(max) of frequency, for example. 3. The part which is not listed above is not supported, as of the day when this datasheet was issued, in spite of the existence of the part number or datasheet. R10DS0193EJ0010

PAGE : 4 Rev. 0.10b : 2012.03.12 R1QBA36C / R1QEA36C Series R1Q4A3618 (Top) / R1QB(H)A3618 (Mid) / R1QE(L)A3618 (Bottom) 1110987654321 (Top View) Notes: 1. Address expansion order for future higher density SRAMs: 10A ൺ 2A ൺ 7A ൺ 5B. 2. NC pins can be left floating or connected to 0V ᨺ VDDQ. TDI DQ0 NC NC DQ2 DQ3 NC ZQ NC DQ5 DQ6 NC NC DQ8 CQ TMS NC NC DQ1 NC NC DQ4 V REF NC NC NC NC DQ7 NC SA SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA SA SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA /LD SA SA SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA /BW0 NC NC ODT C QVLD QVLD SA V SS VSS VSS VSS VSS VSS VSS VSS VSS SA0 NC NC K SA SA SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA NC /BW1 SA SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA R-/W SA DQ17 DQ16 NC NC DQ14 NC VDDQ DQ13 NC DQ11 DQ10 NC NC SA TCK NC NC NC DQ15 NC NC VREF NC DQ12 NC NC NC DQ9 NC TDO NC NC NC NC NC NC /DOFF NC NC NC NC NC NC /CQ R P N M L K J H G F E D C B A R1Q4A3636 (Top) / R1QB(H)A3636 (Mid) / R1QE(L)A3636 (Bottom) 1110987654321 (Top View) Notes: 1. Address expansion order for future higher density SRAMs: 10A ൺ 2A ൺ 7A ൺ 5B. 2. NC pins can be left floating or connected to 0V ᨺ VDDQ. TDI DQ0 DQ10 DQ1 DQ2 DQ3 DQ4 ZQ DQ14 DQ5 DQ6 DQ16 DQ7 DQ8 CQ TMS DQ9 NC DQ11 NC DQ12 DQ13 V REF NC NC DQ15 NC DQ17 NC NC SA NC NC NC NC NC NC V DDQ NC NC NC NC NC NC SA SA SA V SS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA /LD SA SA SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA /BW0 /BW1 NC ODT C QVLD QVLD SA V SS VSS VSS VSS VSS VSS VSS VSS VSS SA0 NC NC K SA SA SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA /BW3 /BW2 SA SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA R-/W SA DQ26 DQ25 DQ34 DQ24 DQ23 DQ32 V DDQ DQ22 DQ21 DQ20 DQ19 DQ28 DQ18 SA TCK NC DQ35 NC DQ33 NC NC V REF DQ31 DQ30 NC DQ29 NC DQ27 NC TDO NC NC NC NC NC NC /DOFF NC NC NC NC NC NC /CQ R P N M L K J H G F E D C B A Pin Arrangement Top ൸R1Q4A3636 Mid ൸R1QB(H)A3636 Bottom ൸R1QE(L)A3636 R10DS0193EJ0010

PAGE : 5 Rev. 0.10b : 2012.03.12 R1QBA36C / R1QEA36C Series R1Q4A3609 (Top) / R1QB(H)A3609 (Mid) / R1QE(L)A3609 (Bottom) 1110987654321 (Top View) Notes: 1. Address expansion order for future higher density SRAMs: 10A ൺ 2A ൺ 7A ൺ 5B. 2. NC pins can be left floating or connected to 0V ᨺ VDDQ. 3. Note that 6C is not SA0 and 7C is not SA1 in x9 product. Thus u9 product does not permit random start address on the two least significant address bits. SA0, SA1 = 0 at the start of each address. TDI DQ0 NC NC DQ1 NC NC ZQ NC NC DQ3 NC NC DQ4 CQ TMS NC NC NC NC NC DQ2 VREF NC NC NC NC NC NC SA SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA SA SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA /LD SA SA SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA /BW NC NC ODT C QVLD QVLD SA V SS VSS VSS VSS VSS VSS VSS VSS VSS SA K SA SA SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA NC NC SA SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA R-/W SA DQ8 NC NC NC NC NC V DDQ DQ6 NC DQ5 NC NC NC SA TCK NC NC NC DQ7 NC NC VREF NC NC NC NC NC NC NC TDO NC NC NC NC NC NC /DOFF NC NC NC NC NC NC /CQ R P N M L K J H G F E D C B A Pin Arrangement Just Reference R10DS0193EJ0010

PAGE : 6 Rev. 0.10b : 2012.03.12 R1QBA36C / R1QEA36C Series Notes: 1. R1Q2, R1Q3, R1Q4, R1Q5, R1Q6 series have C and /C pins. R1QA, R1QB, R1QC, R1QD, R1QE, R1QF, R1QG, R1QH, R1QJ, R1QK, R1QL, R1QM, R1QN, R1QP series do not have C, /C pins. In the series, K and /K are used as the output reference clocks instead of C and /C. Therefore, hereafter, C and /C represent K and /K in this document. Pin Descriptions Notes IEEE1149.1 clock input: 1.8 V I/O levels. This ball must be tied to VSS if the JTAG function is not used in the circuit.InputTCK IEEE1149.1 test inputs: 1.8 V I/O levels. These balls may be left not connected if the JTAG function is not used in the circuit.InputTMS TDI DLL/PLL disable: When low, this input causes the DLL/PLL to be bypassed for stable, low frequency operation.Input/DOFF Output clock: This clock pair provides a user-controlled means of tuning device output data. The rising edge of /C is used as the output timing reference for the first and third output data. The rising edge of C is used as the output timing reference for second and fourth output data. Ideally, /C is 180 degrees out of phase with C. C and /C may be tied high to force the use of K and /K as the output reference clocks instead of having to provide C and /C clocks. If tied high, C and /C must remain high and not to be toggled during device operation. These balls cannot remain V REF level. InputC, /C (II only) Input clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data on the rising edge of K and the rising edge of /K. /K is ideally 180 degrees out of phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges. These balls cannot remain V REF level. InputK, /K Synchronous byte writes: When low, these inputs cause their respective byte to be registered and written during WRITE cycles. These signals are sampled on the same edge as the corresponding data and must meet setup and hold times around the rising edges of K and /K for each of the two rising edges comprising the WRITE cycle. See Byte Write Truth Table for signal to data relationship. Input/BWx Synchronous read / write Input: When /LD is low, this input designates the access type (READ when R-/W is high, WRITE when R-/W is low) for the loaded address. R-/W must meet the setup and hold times around the rising edge of K. InputR-/W Synchronous load: This input is brought low when a bus cycle sequence is to be defined. This definition includes address and READ / WRITE direction. All transactions operate on a burst-of-four data (two clock periods of bus activity). Input/LD Synchronous address inputs: These inputs are registered and must meet the setup and hold times around the rising edge of K. All transactions operate on a burst-of-four words (two clock periods of bus activity). SA0 and SA1 are used as the lowest two address bits for burst READ and burst WRITE operations permitting a random burst start address on u18 and u36 of DDR II (not II+) devices. These inputs are ignored when device is deselected or once burst operation is in progress. InputSAx DescriptionsI/O typeName hinS=00111.0011.0011.0011.0011 00111.0011.0011.0011.0011---DDR R10DS0193EJ0010

PAGE : 7 Rev. 0.10b : 2012.03.12 R1QBA36C / R1QEA36C Series ODT control: When low; [Option 1] Low range mode is selected. The impedance range is between 52 : and 105 : (Thevenin equivalent), which follows 0.3 u RQ for 175 : ื RQ ื 350 :. [Option 2] ODT is disabled. When high; High range mode is selected. The impedance range is between 105 : and 150 : (Thevenin equivalent), which follows 0.6 u RQ for 175 : ื RQ ื 250 :. When floating; [Option 1] High range mode is selected. [Option 2] ODT is disabled. InputODT (II+ only) Output impedance matching input: This input is used to tune the device outputs to the system data bus impedance. DQ and CQ output impedance are set to 0.2 u RQ, where RQ is a resistor from this ball to ground. This ball can be connected directly to VDDQ, which enables the minimum impedance mode. This ball cannot be connected directly to VSS or left unconnected. In ODT (On Die Termination) enable devices, the ODT termination values tracks the value of RQ. The ODT range is selected by ODT control input. InputZQ Valid output indicator: The Q Valid indicates valid output data. QVLD is edge aligned with CQ and /CQ.OutputQVLD (II+ only) No connect: These pins can be left floating or connected to 0V ᨺ VDDQ.NC Notes: 1. Renesas status: Option 1 = Available, Option 2 = Possible. 2. All power supply and ground balls must be connected for proper operation of the device. Notes HSTL input reference voltage: Nominally VDDQ/2, but may be adjusted to improve system noise margin. Provides a reference voltage for the HSTL input buffers. VREF Power supply: Ground.SupplyVSS Power supply: Isolated output buffer supply. Nominally 1.5 V. See DC Characteristics and Operating Conditions for range. SupplyVDDQ Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions for range. SupplyVDD IEEE 1149.1 test output: 1.8 V I/O level.OutputTDO Synchronous echo clock outputs: The edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. These signals run freely and do not stop when DQ tri- states. OutputCQ, /CQ Synchronous data I/Os: Input data must meet setup and hold times around the rising edges of K and /K. Output data is synchronized to the respective C and /C, or to the respective K and /K if C and /C are tied high. The u9 device uses DQ0~DQ8. DQ9~DQ35 should be treated as NC pin. The u18 device uses DQ0~DQ17. DQ18~DQ35 should be treated as NC pin. The u36 device uses DQ0~DQ35. Input output DQ0 to DQn DescriptionsI/O typeName R10DS0193EJ0010

PAGE : 8 Rev. 0.10b : 2012.03.12 R1QBA36C / R1QEA36C Series Block Diagram (R1QxA3636 / R1QxA3618 series, x=4) /LD /BWx K /36 /36 DQ K C,/C or K,/K ZQ CQ, /CQ /36 R-/W SA0 SA0' Memory Array Write Register Output Register Output Select Output Buffer Write Driver Sense Amp MUX Burst Logic Output Control Logic SA0'' SA0''' SA /LD R-/W K Address Registry and Logic Data Registry and Logic Notes 1. C and /C pins do not exist in II+ series parts. C or K Block Diagram (R1QxA3636 / R1QxA3618 / R1QyA3609 series, x=B,E,H,L, y=4,B,E,H,L) /LD /BWx K /36 /18 19/20/21 36/18/9 36/18/9 DQ 19/20/21 K C,/C or K,/K ZQ CQ, /CQ Memory Array Write Register Output Register Output Select Output Buffer Write Driver Sense Amp MUX 4/2/1 R-/W /36 /18 /36 /18 SA /LD R-/W K Address Registry and Logic Data Registry and Logic Notes 1. C and /C pins do not exist in II+ series parts. C or K R10DS0193EJ0010

PAGE : 9 Rev. 0.10b : 2012.03.12 R1QBA36C / R1QEA36C Series hinS=11111.1111.1111.1111.1111--- 72M_36M Status Power Up & Unstable Stage NOP & Set-up Stage Normal Operation VDD SET-UP Cycle VDDQ VREF /DOFF 2. Double clock mode K, /K Fix High (=Vddq) C, /C Status Power Up & Unstable Stage NOP & Set-up Stage Normal Operation VDD SET-UP Cycle VDDQ VREF /DOFF 1. Single clock mode (C and /C pins fixed High) K, /K Fix High (=Vddq) General Description Power-up and Initialization Sequence -V DD must be stable before K, /K clocks are applied. - Recommended voltage application sequence : VSS ൺVDD ൺVDDQ & VREF ൺ VIN. (0 V to VDD, VDDQ < 200 ms) -A p p l y VREF after VDDQ or at the same time as VDDQ. - Then execute either one of the following three sequences. 1. Single Clock Mode (C and /C tied high) - Drive /DOFF high (/DOFF can be tied high from the start). - Then provide stable clocks (K, /K) for at least 1024 cycles (II series) or 20 us (II+ series). These meet the QDR common specification of 20 us. When the operating frequency is less than 180 MHz, 2048 cycles are required (II series). 2. Double Clock Mode (C and /C control outputs) (II series only) - Drive /DOFF high (/DOFF can be tied high from the start) - Then provide stable clocks (K, /K , C, /C) for at least 1024 cycles (II series). This meets the QDR common specification of 20 us. When the operating frequency is less than 180 MHz, 2048 cycles are required (II series). 3. DLL/PLL Off Mode (/DOFF tied low) - In the "NOP and setup stage", provide stable clocks (K, /K) for at least 1024 cycles (II series) or 20 us (II+ series). These meet the QDR common specification of 20 us. R10DS0193EJ0010

PAGE : 10 Rev. 0.10b : 2012.03.12 R1QBA36C / R1QEA36C Series Common DLL/PLL Constraints 1. DLL/PLL uses K clock as its synchronizing input. The input should have low phase jitter which is specified as tKC var. 2. The lower end of the frequency at which the DLL/PLL can operate is 120 MHz. (Please refer to AC Characteristics table for detail.) 3. When the operating frequency is changed or /DOFF level is changed, setup cycles are required again. Programmable Output Impedance 1. Output buffer impedance can be programmed by terminating the ZQ ball to VSS through a precision resistor (RQ). The value of RQ is five times the output impedance desired. The allowable range of RQ to guarantee impedance matching with a tolerance of 15% is 250 :typical. The total external capacitance of ZQ ball must be less than 7.5 pF. R10DS0193EJ0010

PAGE : 11 Rev. 0.10b : 2012.03.12 R1QBA36C / R1QEA36C Series IIP QVLD (Valid data indicator) (R1QA, R1QB, R1QC, R1QD, R1QE, R1QF, R1QG, R1QH, R1QJ, R1QK, R1QL, R1QM R1QN, R1QP series) 1. QVLD is provided on the QDR-II+ and DDR-II+ to simplify data capture on high speed systems. The Q Valid indicates valid output data. QVLD is activated half cycle before the read data for the receiver to be ready for capturing the data. QVLD is inactivated half cycle before the read finish for the receiver to stop capturing the data. QVLD is edge aligned with CQ and /CQ. 3:(ODT disable)0.6 u RQFloating 2, 5:0.6 u RQ0.6 u RQHigh Thevenin equivalent resistance (RTHEV) Unit ODT range (ODT disable) Option 2 Notes: 1. Allowable range of RQ for Option 1 to guarantee impedance matching a tolerance of r20 % is 2. Allowable range of RQ to guarantee impedance matching a tolerance of r 20 % is 3. Allowable range of RQ for Option 1 to guarantee impedance matching a tolerance of r 20 % is 4. At option 1, ODT control pin is connected to VDDQ through 3.5 k:. Therefore it is recommended to connect it to VSS through less than 100 : to make it low. 5. At option 2, ODT control pin is connected to VSS through 3.5 k:. Therefore it is recommended to connect it to VDDQ through less than 100 : to make it high. 6. Renesas status: Option 1 = Available, Option 2 = Possible. If you need devices with option 2, please contact Renesas sales office. 1, 40.3 u RQLow Notes Option 1ODT control pin ODT (On Die Termination) (R1QD, R1QE, R1QF, R1QK, R1QL, R1QM, R1QP series) 1. To reduce reflection which produces noise and lowers signal quality, the signals should be terminated, especially at high frequency. Renesas offers ODT on the input signals to QDR-II+ and DDR-II+ family of devices. (See the ODT pin table) 2. In ODT enable devices, the ODT termination values tracks the value of RQ. The ODT range is selected by ODT control input. (See the ODT range table) 3. In DDR-II+ devices having common I/O bus, ODT is automatically enabled when the device inputs data and disabled when the device outputs data. 4. There is no difference in AC timing characteristics between the SRAMs with ODT and SRAMs without ODT. 5. There is no increase in the IDD of SRAMs with ODT, however, there is an increase in the IDDQ (current consumption from the I/O voltage supply) with ODT. R10DS0193EJ0010

PAGE : 12 Rev. 0.10b : 2012.03.12 R1QBA36C / R1QEA36C Series IIP Thevenin termination Output Buffer SRAM with ODT 2 u RTHEV 2 u RTHEV VDDQ Other LSI Input Buffer VSS ZQ VSS RQ ODT pin = Low or FloatingODT pin = High Off: First Read Command + Read Latency - 0.5 cycle On: Last Read Command + Read Latency + BL/2 cycle + 0.5 cycle (See below timing chart) 2Always OffDQ0 ~D Qn in common I/O devices Always OffAlways OnK, /K Always OffAlways On/BWx Always Off ODT On/Off timing ODT pin (R1QD, R1QE, R1QF, R1QK, R1QL, R1QM, R1QP series) Option 2 Notes: 1. Separate I/O devices are R1QD, R1QK, R1QP series. 2. Common I/O devices are R1QE, R1QF, R1QL, R1QM series. 3. Renesas status: Option 1 = Available, Option 2 = Possible. If you need devices with option 2, please contact Renesas sales office. 1Always OnD0 ~D n in separate I/O devices Notes Option 1 Pin name R10DS0193EJ0010

PAGE : 13 Rev. 0.10b : 2012.03.12 R1QBA36C / R1QEA36C Series IIP NOP Command Read (B2) Ra K, /K Status Qa Qb Qb Rc Qc Qc Qd Qd NOP NOP NOP Write (B2) We De De Df Df Dg Dg Dh Dh Wg Write (B2) QaDQ DQ ODT Disabled QjQi Ri Qi Read (B2) Enabled DisabledEnabled ODT on/off Timing Chart for R1QE series (DDR II+, Burst Length=2, Read Latency=2.5 cycle) Read (B2) Read (B2) Read (B2) Rb Rd Wf Wh Rj Read (B2) Write (B2) Write (B2) NOP Command Read (B4) Ra K, /K Status Qa Qa Qa Rc Qc Qc Qc Qc NOP NOP NOP Write (B4) We De De De De Dg Dg Dg Dg Wg Write (B4) QaDQ DQ ODT Disabled QiQi Ri Qi Read (B4) Enabled DisabledEnabled ODT on/off Timing Chart for R1QF series (DDR II+, Burst Length=4, Read Latency=2.5 cycle) - Read (B4) - -- - NOP Command Read (B2) Ra K, /K Status Qa Qb Qb Rc Qc Qc Qd Qd NOP NOP Write (B2) We De De Df Df Dg Dg Dh Dh Wg Write (B2) QaDQ DQ ODT Disabled QjQi Ri Qi Read (B2) Enabled DisabledEnabled ODT on/off Timing Chart for R1QL series (DDR II+, Burst Length=2, Read Latency=2.0 cycle) Read (B2) Read (B2) Read (B2) Rb Rd Wf Wh Rj Read (B2) Write (B2) Write (B2) Qj Read (B2) Rk Qk Qk NOP Command Read (B4) Ra K, /K Status Qa Qa Qa Rc Qc Qc Qc Qc NOP NOP Write (B4) We De De De De Dg Dg Dg Dg Wg Write (B4) QaDQ DQ ODT Disabled QiQi Ri Qi Read (B4) Enabled DisabledEnabled ODT on/off Timing Chart for R1QM series (DDR II+, Burst Length=4, Read Latency=2.0 cycle) - Read (B4) - -- - Qi Read (B4) Rk Qk Qk Notes 1. ODT on/off switching timings are edge aligned with CQ or /CQ. R10DS0193EJ0010

PAGE : 14 Rev. 0.10b : 2012.03.12 R1QBA36C / R1QEA36C Series C(t+3)൹/C(t+2)൹RL=2.5 /C(t+2)൹C(t+2)൹RL=2.0 RL*8=1.5 Q(A2)Q(A1)Output data D(A2)D(A1)Input data C(t+2)൹/C(t+1)൹Input clock for Q /K(t+1)൹K(t+1)൹Input clock Data out Data in Standby (Clock stopped) NOP (No operation) Read Cycle: Load address, output read data on consecutive C and /C rising edges Write Cycle: Load address, input write data on consecutive K and /K rising edges Operation K Truth Table Notes: 1. H: high level, L: low level, u: don’t care, ൹: rising edge. 2. Data inputs are registered at K and /K rising edges. Data outputs are delivered at C and /C rising edges, except if C and /C are high, then data outputs are delivered at K and /K rising edges. 3. /LD and R-/W must meet setup/hold times around the rising edges (low to high) of K and are registered at the rising edge of K. 4. This device contains circuitry that will en sure the outputs will be in high-Z during power-up. 5. Refer to state diagram and timing diagrams for clarification. 6. When clocks are stopped, the following cases are recommended; the case of K = low, /K = high, C = low and /C = high, or the case of K = high, /K = low, C = high and /C = low. This condition is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 7. A1 refers to the address input during a WRITE or READ cycle. A2 refers to the next internal burst address in accordance with the linear burst sequence. 8. RL = Read Latency (unit = cycle). HL൹ High-ZuH൹ Previous stateuuStopped LL൹ DQR-/W/LDK NotesSA0SA0 1st internal burst address External address Burst Sequence Linear Burst Sequence Table (R1Q4Aww36 / R1Q4Aww18 series ) R10DS0193EJ0010

PAGE : 15 Rev. 0.10b : 2012.03.12 R1QBA36C / R1QEA36C Series Write nothing Write D27 to D35 Write D18 to D26 Write D9 to D17 Write D0 to D8 Write D0 to D35 Operation HHHH-൹ HHHH൹- LHHH-൹ LHHH൹- HLHH-൹ HLHH൹- HHLH-൹ HHLH൹- HHHL-൹ HHHL൹- /BW3/BW1 Byte Write Truth Table ( x 36 ) Notes: 1. H: high level, L: low level, ൹: rising edge. 2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied. LLLL൹- LLLL-൹ /BW2/BW0/KK Common Write nothing Write D9 to D17 Write D0 to D8 Write D0 to D17 Operation HH-൹ HH൹- LH-൹ LH൹- HL-൹ HL൹- Byte Write Truth Table ( x 18 ) Notes: 1. H: high level, L: low level, ൹: rising edge. 2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied. LL൹- LL-൹ /BW1/BW0/KK Write nothing Write D0 to D8 Operation H-൹ H൹- Byte Write Truth Table ( x 9 ) Notes: 1. H: high level, L: low level, ൹: rising edge. 2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied. L൹- L-൹ /BW/KK Just Reference except R1Q2A**09 series R10DS0193EJ0010

PAGE : 16 Rev. 0.10b : 2012.03.12 R1QBA36C / R1QEA36C Series Notes: 1. SA0 is internally advanced in accordance with the burst order table. Bus cycle is terminated at the end of this sequence (burst count = 2). 2. State machine control timing sequence is controlled by K. Bus Cycle State Diagram NOP Write Double Count = Count + 2 Load New Address Count = 0 Power Up /LD = H Supply voltage provided /LD = L R-/W = L /LD = L Count = 2 /LD = H & Count = 2 Read Double Count = Count + 2 R-/W = H /LD = L Count = 2 /LD = H & Count = 2 R10DS0193EJ0010

PAGE : 17 Rev. 0.10b : 2012.03.12 R1QBA36C / R1QEA36C Series Absolute Maximum Ratings Notes: 1. All voltage is referenced to V SS. 2. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted the Operation Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. 3. These CMOS memory circuits have been designed to meet the DC and AC specifications shown in the tables after thermal equilibrium has been established. 4. The following supply voltage application sequence is recommended: V SS, VDD, VDDQ, VREF then VIN. Remember, according to the Absolute Maximum Ratings table, VDDQ is not to exceed 2.5 V, whatever the instantaneous value of VDDQ. 5. Some method of cooling or airflow should be considered in the system. (Especially for high frequency or ODT parts) qC qC V V V V Unit 1, 40.5 to VDDQ + 0.5 (2.5 V max.)VI/OInput/output voltage 1, 40.5 to 2.5VDDCore supply voltage 1, 40.5 to VDDVDDQOutput supply voltage 5+125 (max)TjJunction temperature 55 to +125TSTGStorage temperature 1, 40.5 to VDD + 0.5 (2.5 V max.)VINInput voltage on any ball NotesRatingSymbolParameter Common Recommended DC Operating Conditions 0.75 1.5 1.8 Typ VREF 0.1 VDDQ + 0.3 0.95 VDD 1.9 Max Notes: 1. At power-up, V DD and VDDQ are assumed to be a linear ramp from 0V to VDD(min.) or VDDQ(min.) within 200ms. During this time VDDQ < VDD and VIH < VDDQ. During normal operation, VDDQ must not exceed VDD. 2. Please pay attention to Tj not to exceed the temperature shown in the absolute maximum ratings table due to current from VDDQ. 3. Peak to peak AC component superimposed on V REF may not exceed 5% of VREF. 4. These are DC test criteria. The AC V IH / VIL levels are defined separately to measure timing parameters. 5. Overshoot: V IH (AC) d VDDQ + 0.5 V for t d tKHKH/2 Undershoot: VIL (AC) t 0.5 V for t d tKHKH/2 During normal operation, VIH(DC) must not exceed VDDQ and VIL(DC) must not be lower than VSS. V V V V V Unit 1, 21.4VDDQPower supply voltage -- I/O 30.68VREFInput reference voltage -- I/O 1, 4, 5VREF + 0.1VIH (DC)Input high voltage 1, 4, 50.3VIL (DC)Input low voltage 11.7VDDPower supply voltage -- core NotesMinSymbolParameter R10DS0193EJ0010

PAGE : 18 Rev. 0.10b : 2012.03.12 R1QBA36C / R1QEA36C Series hinS=00000.0000.0000.0000.0000--- 00000.1111.1111.1111.1111--- 00000.0000.0000.0000.0000---036M-II+ DC Characteristics (VDD =1 . 8 Vr0.1V, VDDQ = 1.5V, VREF = 0.75V) Operating Supply Current (Write / Read) Symbol = IDD. Unit = mA. See Notes 1, 2 and 3 in the page after next. Notes: 1. "v" represents the package size. If "v" = "G" then size is 15 x 17 mm, and if "v" = "B" then 13 x 15 mm. 2. "yy" represents the speed bin. "R1QAA3636CBG-20" can operate at 500 MHz(max) of frequency, for example. 533 500 450 400 375 333 333 300 250 200 yy ă - 1 9- 2 0- 2 2- 2 5- 2 7- 3 0- 3 0- 3 3- 4 0- 5 0 17 x18 R1Q A A36 18 C B v- yy 1220 1160 1070 18 x36 R1Q A A36 36 C B v- yy 1280 1220 1130 20 x18 R1Q B A36 18 C B v- yy 1030 990 920 21 x36 R1Q B A36 36 C B v- yy 1110 1060 990 23 x18 R1Q C A36 18 C B v- yy 820 790 750 24 x36 R1Q C A36 36 C B v- yy 880 850 800 26 x18 R1Q D A36 18 C B v- yy 1220 1160 1070 27 x36 R1Q D A36 36 C B v- yy 1280 1220 1130 29 x18 R1Q E A36 18 C B v- yy 1030 990 920 30 x36 R1Q E A36 36 C B v- yy 1110 1060 990 32 x18 R1Q F A36 18 C B v- yy 820 790 750 33 x36 R1Q F A36 36 C B v- yy 880 850 800 35 x18 R1Q G A36 18 C B v- yy 1070 980 36 x36 R1Q G A36 36 C B v- yy 1150 1060 38 x18 R1Q H A36 18 C B v- yy 920 850 39 x36 R1Q H A36 36 C B v- yy 990 910 41 x18 R1Q J A36 18 C B v- yy 750 710 42 x36 R1Q J A36 36 C B v- yy 800 760 44 x18 R1Q K A36 18 C B v- yy 1070 980 45 x36 R1Q K A36 36 C B v- yy 1150 1060 47 x18 R1Q L A36 18 C B v- yy 920 850 48 x36 R1Q L A36 36 C B v- yy 990 910 50 x18 R1Q M A36 18 C B v- yy 750 710 51 x36 R1Q M A36 36 C B v- yy 800 760 QDR II+ / DDR II+ QDR II / DDR II Frequency (max) (MHz) Cycle Time (min) (ns) No Yes No ODT Part Number Ą Organi- zation 2.5 2.5B2 Yes DDRII+ B4QDRII+ QDRII+ B4 2.0 DDRII+ 2.0 DDRII+ QDRII+ B4 DDRII+ QDRII+ B4 No Product Type Burst Length Latency (Cycle) R10DS0193EJ0010

PAGE : 19 Rev. 0.10b : 2012.03.12 R1QBA36C / R1QEA36C Series hinS=00000.0000.0000.0000.0000--- 00000.1111.1111.1111.1111--- 00000.0000.0000.0000.0000---036M-II+ Standby Supply Current (NOP) Symbol = ISB1. Unit = mA. See Notes 2, 4 and 5 in the next page. 533 500 450 400 375 333 333 300 250 200 yy ă - 1 9- 2 0- 2 2- 2 5- 2 7- 3 0- 3 0- 3 3- 4 0- 5 0 17 x18 R1Q A A36 18 C B v- yy 870 830 780 18 x36 R1Q A A36 36 C B v- yy 910 870 810 20 x18 R1Q B A36 18 C B v- yy 870 840 780 21 x36 R1Q B A36 36 C B v- yy 960 920 860 23 x18 R1Q C A36 18 C B v- yy 690 660 630 24 x36 R1Q C A36 36 C B v- yy 730 710 670 26 x18 R1Q D A36 18 C B v- yy 870 830 780 27 x36 R1Q D A36 36 C B v- yy 910 870 810 29 x18 R1Q E A36 18 C B v- yy 870 840 780 30 x36 R1Q E A36 36 C B v- yy 960 920 860 32 x18 R1Q F A36 18 C B v- yy 690 660 630 33 x36 R1Q F A36 36 C B v- yy 730 710 670 35 x18 R1Q G A36 18 C B v- yy 780 720 36 x36 R1Q G A36 36 C B v- yy 830 770 38 x18 R1Q H A36 18 C B v- yy 780 720 39 x36 R1Q H A36 36 C B v- yy 860 790 41 x18 R1Q J A36 18 C B v- yy 630 590 42 x36 R1Q J A36 36 C B v- yy 670 630 44 x18 R1Q K A36 18 C B v- yy 780 720 45 x36 R1Q K A36 36 C B v- yy 830 770 47 x18 R1Q L A36 18 C B v- yy 780 720 48 x36 R1Q L A36 36 C B v- yy 860 790 50 x18 R1Q M A36 18 C B v- yy 630 590 51 x36 R1Q M A36 36 C B v- yy 670 630 QDR II+ / DDR II+ QDR II / DDR II Frequency (max) (MHz) Cycle Time (min) (ns) No Yes No ODT Part Number Ą Organi- zation 2.5 2.5B2 Yes DDRII+ B4QDRII+ QDRII+ B4 2.0 DDRII+ 2.0 DDRII+ QDRII+ B4 DDRII+ QDRII+ B4 No Product Type Burst Length Latency (Cycle) Notes: 1. "v" represents the package size. If "v" = "G" then size is 15 x 17 mm, and if "v" = "B" then 13 x 15 mm. 2. "yy" represents the speed bin. "R1QAA3636CBG-20" can operate at 500 MHz(max) of frequency, for example. R10DS0193EJ0010

PAGE : 20 Rev. 0.10b : 2012.03.12 R1QBA36C / R1QEA36C Series Common Leakage Currents & Output Voltage 8, 9|IOH| d 0.1 mAVVDDQVDDQ 0.2VOH (Low)Output high voltage 8, 9Note 6VVDDQ/2 0.12 VDDQ/2 0.12VOH VDDQ/2 0.12 0.2 Max V V PA PA Unit Notes: 1. All inputs (except ZQ, V REF) are held at either VIH or VIL. 2. I OUT = 0 mA. VDD = VDD max, tKHKH = tKHKH min. 3. Operating supply currents (I DD) are measured at 100% bus utilization. IDD of QDR family is current of device with 100% write and 100% read cycle. IDD of DDR family is current of device with 100% write cycle (if IDD(Write) > IDD(Read)) or 100% read cycle (if IDD(Write) < IDD(Read)). 4. All address / data inputs are static at either V IN > VIH or VIN < VIL. 5. Reference value. (Condition = NOP currents are valid when entering NOP after all pending READ and WRITE cycles are completed. ) 6. Outputs are impedance-controlled. |I OH| = (VDDQ/2)/(RQ/5) for values of 175 :d RQ d 350 :. 7. Outputs are impedance-controlled. I OL = (VDDQ/2)/(RQ/5) for values of 175 :d RQ d 350 :. 8. AC load current is higher than the shown DC values. AC I/O curves are available upon request. 9. HSTL outputs meet JEDEC HSTL Class I and Class II standards. 10. 0 d VIN d VDDQ for all input balls (except VREF, ZQ, TCK, TMS, TDI ball). If R1QD, R1QE, R1QF, R1QK, R1QL, R1QM, R1QP series, balls with ODT do not follow this spec. 11. 0 d VOUT d VDDQ (except TDO ball), output disabled. Note 7 IOL d 0.1 mA Test condition 115ILOOutput leakage current 8, 9VSS VOL (Low)Output low voltage 8, 9VDDQ/2 0.12VOL 102ILIInput leakage current NotesMinSymbolParameter R10DS0193EJ0010

PAGE : 21 Rev. 0.10b : 2012.03.12 R1QBA36C / R1QEA36C Series Common AC Test Conditions Input waveform (Rise/fall time d 0.3 ns) 1.25V 0.25V 0.75V 0.75V Test points Output waveform VDDQ/2 Test points V DDQ/2 pF pF pF Unit Capacitance (Ta = +25qC, Frequency = 1.0MHz, VDD =1 . 8 V , VDDQ =1 . 5 V ) Typ Max Notes: 1. These parameters are sampled and not 100% tested. 2. Except JTAG (TCK, TMS, TDI, TDO) pins. VI/O = 0 V VCLK = 0 V VIN = 0 V Test condition 1, 2CCLKClock input capacitance (K, /K, C, /C) 1, 2CI/O Output capacitance (Q(separate), DQ(common), CQ, /CQ) 1, 2CIN Input capacitance (SA, /R, /W, /BW, D(separate)) NotesMinSymbolParameter -4 . 4 11.0 Typ EIA/JEDEC JESD51 Test condition qC/W Unit Thermal Resistance 1 m/s Airflow Notes: 1. These parameters are calculated under the condition. These are reference values. 2. Tj = Ta + ˥ JA ™ Pd Tj = Tc + ˥JC ™ Pd where Tj : junction temperature when the device has achieved a steady-state after application of Pd (rC) Ta : ambient temperature ( rC) Tc : temperature of external surface of the package or case ( rC) ˥JA : thermal resistance from junction-to-ambient ( rC/W) ˥JC : thermal resistance from junction-to-case (package) (rC/W) Pd : power dissipation that produced change in junction temperature (W) (cf.JESD51-2A) ˥JCJunction to Case 1˥JAJunction to Ambient NotesSymbolParameter R10DS0193EJ0010

PAGE : 22 Rev. 0.10b : 2012.03.12 R1QBA36C / R1QEA36C Series Common V V Unit AC Operating Conditions Typ VREF – 0.2 Max Notes: 1. All voltages referenced to V SS (GND). During normal operation, VDDQ must not exceed VDD. 2. These conditions are for AC functions only, not for AC parameter test. 3. Overshoot: V IH (AC) d VDDQ + 0.5 V for t d tKHKH/2 Undershoot: VIL (AC) t 0.5 V for t d tKHKH/2 Control input signals may not have pulse widths less than tKHKL (min) or operate at cycle rates less than tKHKH (min). 4. To maintain a valid level, the transitioning edge of the input must: a. Sustain a constant slew rate from the current AC level through the target AC level, VIL (AC) or VIH (AC). b. Reach at least the target AC level. c. After the AC target level is reached, continue to maintain at least the target DC level, VIL (DC) or VIH (DC). 1, 2, 3, 4VIL (AC)Input low voltage 1, 2, 3, 4VREF + 0.2VIH (AC)Input high voltage NotesMinSymbolParameter Output load conditions Output load and voltage conditions 50: ZQ Q VREF 250: Z0 = 50: SRAM VDDQ / 2 = 0.75V VDDQ / 2 = 0.75V VDD VDDQ VSS 1.8Vr0.1V 1.5V R10DS0193EJ0010

PAGE : 23 Rev. 0.10b : 2012.03.12 R1QBA36C / R1QEA36C Series hinS=00000.0111.0111.0000.0000--- 00000.0111.0111.0000.0000--- CQ high to QVLD valid K, /K high to output low-Z K, /K high to output high-Z CQ, /CQ high to output hold CQ, /CQ high to output valid K, /K high to echo clock hold K, /K high to echo clock valid K, /K high to output hold K, /K high to output valid Output Times K static to DLL/PLL reset Lock time (K) Clock phase jitter (K, /K) DLL/PLL Timing /Clock to clock (/K to K) Clock to /clock (K to /K) Clock low time (K, /K) Clock high time (K, /K) Average clock cycle time (K, /K) Clock Parameter AC Characteristics (Read Latency = 2.5 cycle) (VDD =1 . 8 Vr0.1V, VDDQ = 1.5V, VREF = 0.75V) tQVLD tCHQX1 tCHQZ tCQHQX tCQHQV tCHCQX tCHCQV tCHQX tCHQV tKC reset tKC lock tKC var t/KHKH tKH/KH tKLKH tKHKL tKHKH Symbol 0.15 0.45 0.15 0.45 0.45 0.425 0.425 0.40 0.40 1.875 Min -19 0.15 0.45 0.15 0.45 0.45 0.15 4.00 Max 0.15 0.45 0.15 0.45 0.45 0.425 0.425 0.40 0.40 2.00 Min -20 0.15 0.45 0.15 0.45 0.45 0.15 4.00 Max 0.15 0.45 0.15 0.45 0.45 0.425 0.425 0.40 0.40 2.22 Min -22 0.15 0.45 0.15 0.45 0.45 0.15 4.00 Max 0.20 0.45 0.20 0.45 0.45 0.425 0.425 0.40 0.40 2.50 Min -25 0.20 0.45 0.20 0.45 0.45 0.20 4.00 Max 0.20 0.45 0.20 0.45 0.45 0.425 0.425 0.40 0.40 2.66 Min -27 0.20 0.45 0.20 0.45 0.45 0.20 4.00 Max 0.20 0.45 0.20 0.45 0.45 0.425 0.425 0.40 0.40 3.00 Min -30 0.20 0.45 0.20 0.45 0.45 0.20 4.00 Max ns ns ns ns ns ns ns ns ns ns us ns Cy- cle Cy- cle Cy- cle Cy- cle ns Unit 5, 6 4, 7 4, 7 Notes R10DS0193EJ0010

PAGE : 24 Rev. 0.10b : 2012.03.12 R1QBA36C / R1QEA36C Series hinS=00000.0111.0111.0000.0000--- 00000.0111.0111.0000.0000--- Notes: 1. This is a synchronous device. All addresses, data and control lines must meet the specified setup and hold times for all latching clock edges. 2. V DD and VDDQ slew rate must be less than 0.1 V DC per 50 ns for DLL/PLL lock retention. DLL/PLL lock time begins once VDD , VDDQ and input clock are stable. It is recommended that the device is kept inactive during these cycles. This specification meets the QDR common spec. of 20 us. 3. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 4. Echo clock is very tightly controlled to data valid / data hold. By design, there is a r0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guardbands and test setup variations. 5. Transitions are measured r100 mV from steady-state voltage. 6. At any given voltage and temperature t CHQZ is less than tCHQX1 and tCHQV. 7. These parameters are sampled. 8. t AVKH, tIVKH, tKHAX, tKHIX spec is determined by the actual frequency regardless of Part Number (Marking Name). The following is the spec for the actual frequency. 0.30 ns for ื533MHz & >500MHz 0.33 ns for ื500MHz & >450MHz 0.40 ns for ื450MHz & ุ250MHz 9. t DVKH, tKHDX spec is determined by the actual frequency regardless of Part Number (Marking Name). The following is the spec for the actual frequency. 0.20 ns for ื533MHz & >500MHz 0.22 ns for ื500MHz & >450MHz 0.25 ns for ื450MHz & >400MHz 0.28 ns for ื400MHz & ุ250MHz Remarks: 1. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise noted. 2. Control input signals may not be operated with pulse widths less than t KHKL (min). 4. Control signals are /R, /W (QDR series), /LD, R-/W (DDR series), /BW, /BW0, /BW1, /BW2 and /BW3. Setup and hold times of /BWx signals must be the same as those of Data-in signals. K, /K rising edge to data-in hold K rising edge to control inputs hold K rising edge to address hold Hold Times Data-in valid to K, /K rising edge Control inputs valid to K rising edge Address valid to K rising edge Setup Times Parameter tKHDX tKHIX (QDRII+ B4 & DDRII+) tKHIX (QDRII+ B2) tKHAX (QDRII+ B4 & DDRII+) tKHAX (QDRII+ B2) tDVKH tIVKH (QDRII+ B4 & DDRII+) tIVKH (QDRII+ B2) tAVKH (QDRII+ B4 & DDRII+) tAVKH (QDRII+ B2) Symbol 0.20 0.30 0.30 0.20 0.30 0.30 Min -19 Max 0.22 0.33 0.33 0.22 0.33 0.33 Min -20 Max 0.25 0.40 0.40 0.25 0.40 0.40 Min -22 Max 0.28 0.40 0.40 0.28 0.40 0.40 Min -25 Max 0.28 0.40 0.40 0.28 0.40 0.40 Min -27 Max 0.28 0.40 0.40 0.28 0.40 0.40 Min -30 Max ns ns ns ns ns ns Unit 1, 9 1, 8 1, 8 1, 9 1, 8 1, 8 Notes R10DS0193EJ0010

PAGE : 25 Rev. 0.10b : 2012.03.12 R1QBA36C / R1QEA36C Series hinS=00000.0010.0010.0000.0000--- R1QB_RL=2.5R tQVLD -tQVLD tQVLD -tQVLD 1 2 3 4 5 6 7 8 9 10 11 12 13 K, /K NOP READ (burst of 2) READ (burst of 2) WRITE (burst of 2)NOP NOP tKHAXtAVKH /LD:R-/W SA tKHKH tKHKL tKLKH tKH/KH t/KHKH K tKHIXtIVKH WRITE (burst of 2) READ (burst of 2) 00 0001 01 1x 1x 1x A2 A6A4 Notes: 1. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, etc. 2. Outputs are disabled (high-Z) N clock cycle after the last read cycle. Here, N = Read Latency + Burst Length u 0.5. 3. In this example, if address A8 = A7, then data Q80 = D70, Q81 = D71, etc. Write data is forwarded immediately as read results. 4. To control read and write operations, /BW signals must operate at the same timing as Data-in signals. 5. The third NOP cycle is not necessary for correct device operation; however, at high clock frequencies it may be required to prevent bus contention. READ (burst of 2) READ (burst of 2) WRITE (burst of 2) WRITE (burst of 2) 01 01 00 00 01 A1 A3 A5 A8A7 tCHCQV -tCHCQX tCHCQV -tCHCQX Q00Qx1 Q01 Q10 Q11 Q20 Q21 Q30 tCHQV -tCHQX tCHQV -tCHQX tCQHQV -tCQHQX -tCHQX1 Q31 tCHQZ Qx0Qx1 DQ CQ /CQ QVLD D40 D41 D50 D51 D60 D61 D70 D71 tKHDX tDVKH tKHDX tDVKH NOP Timing Waveforms (DDRII+, B2, Read Latency = 2.5 cycle) R10DS0193EJ0010

PAGE : 26 Rev. 0.10b : 2012.03.12 R1QBA36C / R1QEA36C Series JTAG Specification These products support a limited set of JTAG functions as in IEEE standard 1149.1. Disabling the Test Access Port It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfering with normal operation of the device, TCK must be tied to VSS to preclude mid level inputs. TDI and TMS are internally pulled up and may be unconnected, or may be connected to VDD through a pull up resistor. TDO should be left unconnected. 11R 10R Pin assignments Test mode select. This is the command input for the TAP controller state machine.TMS Test data input. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP controller state machine and the instruction that is currently loaded in the TAP instruction. TDI Test data output. Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. TDO Test Access Port (TAP) Pins Notes: The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high for five rising edges of TCK. The TAP controller state is also reset on SRAM POWER-UP. Notes Test clock input. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK.TCK DescriptionSymbol I/O Common R10DS0193EJ0010

PAGE : 27 Rev. 0.10b : 2012.03.12 R1QBA36C / R1QEA36C Series

0 V d VIN d VDD,

output disabledPA5.05.0ILOOutput leakage current IOLC = 100 PAV0.2VOL1Output low voltage IOLT = 2 mAV0.4VOL2 5.0 0.5 VDD + 0.3 Max V0.3VILInput low voltage 0 V d VIN d VDDPA5.0ILIInput leakage current |IOHC| = 100 PAV1.6VOH1Output high voltage |IOHT| = 2 mAV1.4VOH2 TAP DC Operating Characteristics (VDD =1 . 8 Vr0.1V) Typ V Unit Notes: 1. All voltages referenced to V SS (GND). 2. At power-up, V DD and VDDQ are assumed to be a linear ramp from 0V to VDD(min.) or VDDQ(min.) within 200ms. During this time VDDQ < VDD and VIH < VDDQ. During normal operation, VDDQ must not exceed VDD. Notes +1.3VIHInput high voltage MinSymbolParameter Common R10DS0193EJ0010

PAGE : 28 Rev. 0.10b : 2012.03.12 R1QBA36C / R1QEA36C Series V0.9VREFInput timing measurement reference levels Notes V V ns V Unit 0.9Output timing measurement reference levels 0.9Test load termination supply voltage (VTT) 0 to 1.8VIL, VIHInput pulse levels d 1.0tr, tfInput rise/fall time See figuresOutput load TAP AC Test Conditions ConditionsSymbolParameter Common External Load at Test 50: VTT = 0.9V TDO Z 0 = 50: DUT 20pF 1.8V Input waveform 0.9V 0.9V Test points Output waveform 0.9V Test points 0.9V Output load condition R10DS0193EJ0010

PAGE : 29 Rev. 0.10b : 2012.03.12 R1QBA36C / R1QEA36C Series ns5tTHMXTMS hold 1ns5tCSCapture setup 1ns5tCHCapture hold ns5tDVTHTDI valid to TCK high ns5tTHDXTCK high to TDI invalid ns0tTLQXTCK low to TDO unknown Max ns20tTHTLTCK high pulse width ns20tTLTHTCK low pulse width ns5tMVTHTest mode select (TMS) setup nstTLQVTCK low to TDO valid TAP AC Operating Characteristics (VDD =1 . 8 Vr0.1V) Typ ns Unit Notes: 1. t CS + tCH defines the minimum pause in RAM I/O pad transitions to assure pad data capture. Notes 50tTHTHTest clock (TCK) cycle time MinSymbolParameter Common R10DS0193EJ0010

PAGE : 30 Rev. 0.10b : 2012.03.12 R1QBA36C / R1QEA36C Series Notes BS [109:1]109 bitsBoundary scan register BP1 bitBypass register ID [31:0]32 bitsID register Test Access Port Registers IR [2:0] Symbol 3 bitsInstruction register LengthRegister name TAP Controller Timing Diagram TCK TDI TMS TDO PI (SRAM) tTHTLtTHTH tTLTH tMVTH tTHMX tDVTH tTHDX tCS tCH tTLQV tTLQX Common R10DS0193EJ0010

PAGE : 31 Rev. 0.10b : 2012.03.12 R1QBA36C / R1QEA36C Series 3, 5 When the SAMPLE instruction is loaded in the instruction register, moving the TAP controller into the capture-DR state loads the data in the RAMs input and I/O buffers into the boundary scan register. Because the RAM clock(s) are independent from the TAP clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state). Although allowing the TAP to SAMPLE metastable input will not harm the device, repeatable results cannot be expected. Moving the controller to shift-DR state then places the boundary scan register between the TDI and TDO balls. SAMPLE (/PRELOAD)001 -RESERVED101 -RESERVED011 The BYPASS instruction is loaded in the instruction register when the bypass register is placed between TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. BYPASS111 The RESERVED instructions are not implemented but are reserved for future use. Do not use these instructions. If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z), moving the TAP controller into the capture-DR state loads the data in the RAMs input into the boundary scan register, and the boundary scan register is connected between TDI and TDO when the TAP controller is moved to the shift-DR state. The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in capture-DR mode and places the ID register between the TDI and TDO balls in shift- DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. The EXTEST instruction allows circuitry external to the component package to be tested. Boundary scan register cells at output balls are used to apply test vectors, while those at input balls capture test results. Typically, the first test vector to be applied using the EXTEST instruction will be shifted into the boundary scan register using the PRELOAD instruction. Thus, during the Update-IR state of EXTEST, the output driver is turned on and the PRELOAD data is driven onto the output balls. 3, 4, 5SAMPLE-Z010 RESERVED110 TAP Controller Instruction Set EXTEST Instruction Notes: 1. Data in output register is not guaranteed if EXTEST instruction is loaded. 2. After performing EXTEST, power-up conditions are required in order to return part to normal operation. 3. RAM input signals must be stabilized for long enough to meet the TAPs input data capture setup plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the boundary scan register. 4. Clock recovery initialization cycles are required after boundary scan. 5. For R1QD, R1QE, R1QF, R1QK, R1QL, R1QM, R1QP series, ODT is disabled in EXTEST, SAMPLE-Z or SAMPLE mode. 1, 2, 3, 5 Notes 000 IR0IR1IR2 Common R10DS0193EJ0010

PAGE : 32 Rev. 0.10b : 2012.03.12 R1QBA36C / R1QEA36C Series Bit # Boundary Scan Order 11E 10F 11G 11F 10G 11H 11J 10J 10K 11K 10L 11M 11L 11N 10M 10N 10P 11P Ball ID DQ3 NC NC NC NC NC NC ZQ NC DQ2 NC NC NC NC NC NC NC DQ1 NC NC NC NC NC NC NC DQ0 SA SA SA SA SA SA SA C or QVLD /C or NC or ODT Signal names DQ6 NC NC NC DQ5 NC NC ZQ NC DQ4 NC NC NC DQ3 NC NC NC DQ2 NC NC NC DQ1 NC NC NC DQ0 SA SA SA SA SA SA SA C or QVLD /C or NC or ODT x18 DQ6 NC NC DQ14 DQ5 NC NC ZQ DQ4 DQ13 NC NC DQ12 DQ3 NC NC DQ1 DQ2 NC NC DQ10 DQ11 NC NC DQ9 DQ0 SA SA SA SA SA SA SA C or QVLD /C or NC or ODT x36 Bit # 10A 11A 10B 11C 11B 11D 10C 10D 10E Ball ID NC NC NC NC NC /CQ NC SA SA SA R-/W NC NC K /BW NC /LD SA SA SA SA SA CQ NC NC NC DQ4 NC NC NC NC NC NC NC Signal names DQ10 NC NC NC DQ9 /CQ NC SA SA SA R-/W /BW1 NC K /BW0 NC /LD SA0 or NC SA SA SA SA CQ NC NC NC DQ8 NC NC NC DQ7 NC NC NC x18 DQ19 NC NC DQ18 DQ27 /CQ NC SA SA SA R-/W /BW2 /BW3 K /BW0 /BW1 /LD SA0 or NC SA SA SA NC CQ NC NC DQ7 DQ8 NC NC DQ16 DQ17 NC NC DQ15 x36 R10DS0193EJ0010

PAGE : 33 Rev. 0.10b : 2012.03.12 R1QBA36C / R1QEA36C Series Notes: In boundary scan mode, 1. Clock balls (K, /K, C, /C) are referenced to each other and must be at opposite logic levels for reliable operation. 2. CQ and /CQ data are synchronized to the respective C and /C (except EXTEST, SAMPLE-Z). 3. If C and /C tied high, CQ is generated with respect to K and /CQ is generated with respect to /K (except EXTEST, SAMPLE-Z). Bit # Boundary Scan Order Ball ID NC NC NC NC NC NC /DOFF NC DQ6 NC NC NC NC NC NC NC DQ5 NC NC NC Signal names NC NC NC DQ14 NC NC /DOFF NC DQ13 NC NC NC DQ12 NC NC NC DQ11 NC NC NC x18 NC NC DQ32 DQ23 NC NC /DOFF DQ31 DQ22 NC NC DQ21 DQ30 NC NC DQ29 DQ20 NC NC DQ28 x36 109 108 107 106 105 104 103 102 101 100 Bit # Ball ID INTER- NAL SA SA SA SA SA SA NC NC NC DQ8 NC NC NC NC NC NC NC DQ7 Signal names INTER- NAL SA SA SA SA SA SA NC NC NC DQ17 NC NC NC DQ16 NC NC NC DQ15 x18 INTER- NAL SA SA SA SA SA SA NC NC DQ35 DQ26 NC NC DQ34 DQ25 NC NC DQ24 DQ33 x36 R10DS0193EJ0010

PAGE : 34 Rev. 0.10b : 2012.03.12 R1QBA36C / R1QEA36C Series TAP Controller State Diagram Notes: The value adjacent to each state transition in this figure represents the signal present at TMS at the time of a rising edge at TCK. No matter what the original state of the controller, it will enter Test-Logic-Reset when TMS is held high for at least five rising edges of TCK. Select IR Scan Capture IR Shift IR Exit1 IR Pause IR Exit2 IR Update IR Select DR Scan Capture DR Shift DR Exit1 DR Pause DR Exit2 DR Update DR Run Test/Idle 010 1 Test Logic Reset Common ID Register 㸣 㸣 # 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 S y m b o l R R R0C M M M A W W01 Q Q Q B O S0010001000111 RRR Q 000 0 001 1 010 Q 011 0 CQ MMM B 010 0 011 1 101 O 110 0 WW 1 Density = 72Mb Density = 36Mb Latency=1.5 (@II), Latency=2.0 (@II+) Latency=2.5 (@II+) Burst Length = 2 word burst Revison 0 II (QDR-II, DDR-II) Revison 1 Revison 2 Revison 3 Start bit (0) ăŇ Revision number (31 :29) Type number (28 : 12) x36 36M&72M w/o ODT, 144M,288M 36M&72M w/ ODT 144M&288M w/o ODT, 36M,72M 144M&288M w/ ODT Burst Length = 4 word burst Density = 144Mb Density = 288Mb Common I/O Separate I/O Vendor JEDEC code x18 (11 : 1) II+ (QDR-II+, DDR-II+) DDR QDR with ODT without ODT R10DS0193EJ0010

PAGE : 35 Rev. 0.10b : 2012.03.12 R1QBA36C / R1QEA36C Series Package Dimensions and Marking Information Both Pb parts and Pb-free parts are available. hinS=11111.1111.1111.1111.1111--- 11111.1111.1111.1111.1111--- 00000.0000.0000.0000.0000---72M_36M Sy- ABSØx(M)- Top View Side View Bottom View Marking Information 1st row : Vender name (R ENESAS) 2nd row: Part number 3rd row : Y : Year code WW : Week code XXXX : Renesas internal use 4th row : Country name (JAPAN) + "None" --- Pb -free parts + "PB-F" --- Pb-free parts S A ZE ZD ABCDEFGHJKLMNPR 1 2 3 4 5 6 7 8 9 10 11 [e] [e] Øb Index Mark A D Index Mark (Laser Mark) B E R1Q2A7209ABG-40R YWWXXXX JAPAN PB-F This part number or mark is just one example. 0.5g Mass (typ.) 165FHG Previous Code PLBG0165FE-AP-LBGA165-13x15-1.00 Renesas CodeJEITA Package Code MaxNomMin -1.5-ZE -2.5-ZD 0.15--y 0.60.50.45b -1.0-[e] 0.410.360.31A1 1.4--A 15.115.014.9E 13.113.012.9D 0.2--x Dimension in mmReference Symbol R10DS0193EJ0010

PAGE : 36 Rev. 0.10b : 2012.03.12 R1QBA36C / R1QEA36C Series hinS=11111.1111.1111.1111.1111--- 11111.1111.1111.1111.1111--- 00000.0000.0000.0000.0000---72M_36M

Revision History

DescriptionDateRev. Revision History (1) 4GX &CVG %QOOGPV 4GXC +PKVKCNKUUWG 4GXD %QTTGEVGFV[RQUKP&%%JCTCEVGTKUVKEU 81*81.8&&3dăd 4GXE #FFGF5RGGF$KP6CDNG #FFGF1&6VKOKPIEJCTVVQ3&4++ CPF&&4++ UGTKGU %QTTGEVGFV[RQUKP)GPGTCN&GUETKRVKQP 7RFCVGF4GEQOOGPFGF&%1RGTCVKPI%QPFKVKQPU 8TGH᳸8ă᳸ UGTKGU #FFGFEQOOGPVVQ6JGTOCN4GUKUVCPEGUGEVKQP 6JGUGCTGTGHGTGPEGXCNWGU 4GXG #FFGF)GPGTCVKQP0WODGT6CDNG %JCPIGF/CTMKPI0COGKP2CTV0WODGT&GHKPKVKQP6CDNG #FFGFOCTMKPIKPHQTOCVKQPVQ2CEMCIG&KOGPUKQP+PHQTOCVKQPUGEVKQP %QTTGEVGF1&61P1HHVKOKPIKP1&6RKPVCDNG 7RFCVGFOKPKOWOHTGSWGPE[QH3&4++ CPF&&4++ UGTKGU %JCPIGFRKPPCOGKP2KP#TTCPIGOGPVQH&&4++ UGTKGU 5#5#ă0% #FFGFVJGTQYVQ-6TWVJ6CDNG 4.CPF4. 7RFCVGF5'672E[ENGU UGTKGU&..NQEMVKOGWUăE[ENG #FFGFEQOOGPVVQ1&6QPQHH6KOKPI%JCTVUGEVKQP 1&6QPQHHUYKVEJKPI VKOKPIUCTGGFIGCNKIPGFYKVJ%3QT%3 7RFCVGF6JGTOCN4GUKUVCPEG 4GXJ #FFGFURGGFDKPVQ3&4++$ZZUGTKGU 7RFCVGF2CEMCIG&KOGPUKQPU /CUUăI# OCZ ăOO 7RFCVGF1RGTCVKPI5VCPFD[5WRRN[%WTTGPVU #FFGFEQOOGPVVQ2QYGTWRCPF+PKVKCNK\\CVKQP5GSWGPEGUGEVKQP #RRN[8TGH CHVGT8FFSQTCVVJGUCOGVKOGCU8FFS 7RFCVGF5RGGF$KP6CDNG #FFGF4GPGUCU3&454#/*QOGRCIG74.VQPQVGUQHHTQPVRCIG 7RFCVGF2QYGTWRCPF+PKVKCNK\\CVKQP5GSWGPEG 7RFCVGF&..%QPUVTCKPVU 7RFCVGF1RGTCVKPI5WRRN[%WTTGPVCPF5VCPFD[5WRRN[%WTTGPV 7RFCVGF6JGTOCN4GUKUVCPEG %JCPIGFTGOCTMUQH#%%JCTCEVGTKUVKEUQP%QPVTQNUKIPCNU %JCPIGFEQORCP[PCOG4'0'5#5NQIQCPFDCUGEQNQTHTQOVJQUGQH4GPGUCU 6GEJPQNQI[VQ4GPGUCU'NGEVTQPKEU %JCPIGFXGPFGTPCOGOCTMKPIKP2CEMCIG&KOGPUKQPUCPF/CTMKPI+PHQTOCVKQP UGEVKQP #FFGF#IGPGTCVKQPVQ/UGTKGU %JCPIGFVJGRKPFGUETKRVKQPHQT0%RKP %JCPIGFPQVGQH6#2%QPVTQNNGT+PUVTWEVKQP5GV %NQEMTGEQXGT[ KPKVKCNK\\CVKQPE[ENGUCTGTGSWKTGFCHVGTDQWPFCT[UECP %JCPIGF8FFSTCPIGQH++ UGTKGU 8FFSd8ă8᳸8FF #FFGF0QVGCPF0QVGVQ#%%JCTCEVGTKUVKEUVCDNGHQT++ UGTKGU 7RFCVGF5RGGF$KP6CDNGHQT/ #FFGF0QVGVQ)GPGTCVKQP0WODGT6CDNG 7RFCVGF5RGGF$KP6CDNGHQT/CPF/ 4GXE 7RFCVGF1RGTCVKPI5WRRN[%WTTGPVCPF5VCPFD[5WRRN[%WTTGPV6CDNGHQT/ CPF/ 4GXC %JCPIGF+PKVKCNK\\CVKQP5GSWGPEG +PKVKCNE[ENGQH++ UGTKGUE[ENGU ăWU 4GXC #FFGF0QVGVQ#%%JCTCEVGTKUVKEUVCDNGHQT++UGTKGU 7RFCVGF#%%JCTCEVGTKUVKEUHQTVJGUGTKGUQH4. 7RFCVGF5RGGF$KP6CDNGHQT/// #FFGF430#432#UGTKGUVQ/3&4NKPGWR %JCPIGF,6#)+&4GIKUVGT +&%QFG //YQ1&6// //Y1&6 //YQ1&6// //Y1&6 ă ă 4GXC 4GXD 4GXD 4GXC 4GXC 4GXF 4GX᳠ 4GXC 4GXI 4GXK 4GXC R10DS0193EJ0010

PAGE : 37 Rev. 0.10b : 2012.03.12 R1QBA36C / R1QEA36C Series hinS=11111.1111.1111.1111.1111--- 11111.1111.1111.1111.1111--- 00000.0000.0000.0000.0000---72M_36M Revision History (2) 4GX &CVG %QOOGPV #FFGF0QVGVQV38.&KP#%%JCTCEVGTKUVKEUVCDNGHQT++ UGTKGU %JCPIGFFGUETKRVKQPQHV38.&KP#%%JCTCEVGTKUVKEUVCDNGHQT4.UGTKGU %3JKIJVQ38.&XCNKFă%3JKIJVQ38.&XCNKF 7RFCVGF4GOCTMUQH#%%JCTCEVGTKUVKEUVCDNG 7RFCVGFV-*-* OCZ KP#%%JCTCEVGTKUVKEUVCDNGHQT3&4++ $UGTKGU #FFGFZOORCEMCIGNKPGWRVQ/++ /++++ UGTKGU 7RFCVGF2CEMCIG&KOGPUKQPUHQTZOORCEMCIG 7RFCVGF6JGTOCN4GUKUVCPEGHQTZOORCEMCIG %JCPIGF6KVNG 1TFGTKPI+PHQTOCKQPă2CTV0WODGT&GHKPKVKQPŴ5RGGF $KP6CDNGă4GPGUCU /3&4&&454#/.KPGWR 4GXC 7RFCVGF5RGEKHKECVKQPHQT1&61RVKQP 4GXC 7RFCVGF2CTV0WODGT&GHKPKVKQPVCDNG #FFGF0QVG 4GXD 7RFCVGF2CTV0WODGT&GHKPKVKQPVCDNG #FFGFFGHKPKVKQPVQ0Q 4GXC 4GXD R10DS0193EJ0010

PAGE : 38 Rev. 0.10b : 2012.03.12 R1QBA36C / R1QEA36C Series © 2012 Renesas Electronics Corporation. All rights reserved. Renesas Electronics Hong Kong Limited Unit 1601-1613, 16/F., Tower 2, Grand Century Place,

193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong

Tel: +852-2886-9318, Fax: +852 2886-9022/9044 Renesas Electronics Taiwan Co., Ltd. 7F, No. 363 Fu Shing North Road Taipei, Taiwan, R.O.C. Tel: +886-2-8175-9600, Fax: +886 2-8175-9670 Renesas Electronics Singapore Pte. Ltd. 1 harbourFront Avenue, #06-10, keppel Bay Tower, Singapore 098632 Tel: +65-6213-0200, Fax: +65-6278-8001 Renesas Electronics Malaysia Sdn.Bhd. Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Renesas Electronics Korea Co., Ltd. 11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea Renesas Sales Offices http://www.renesas.com --- Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A. Renesas Electronics Canada Limited

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Renesas Electronics Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K Tel: +44-1628-585-100, Fax: +44-1628-585-900 Renesas Electronics Europe GmbH Arcadiastrasse 10, 40472 Düsseldorf, Germany Renesas Electronics (China) Co., Ltd. 7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China Tel: +86-10-8235-1155, Fax: +86-10-8235-7679 Renesas Electronics (Shanghai) Co., Ltd. Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898 Renesas Electronics Corporation Headquarters: Nippon Bldg., 2-6-2, Ote-machi, Chiyoda-ku, Tokyo 100-0004, Japan NOTES: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the us e of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circu it examples, is current as of the date this document is issued. Such information, however,is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whats oever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the tota l system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. The products described in this document are intended for usage in general electronics applications (computer, personal equipm ent, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). The products are not designed, manufactured, t ested or warranted for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. Unintended usage of the pr oducts shall be made at the customer’s own risk. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Electronics Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum ra ting, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or a ffixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Ren esas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Common