R1Q5A3618ABG40RT0

R1Q2A3636B RENESAS | Alldatasheet

Document overview

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Technical content

Features

• 1.8 V ± 0.1 V power supply for core (VDD)
• 1.4 V to VDD power supply for I/O (VDDQ)
• DLL circuitry for wide output data valid window and future frequency scaling
• Separate independent read and write data ports with concurrent transactions
• 100% bus utilization DDR read and write operation
• Two-tick burst for low DDR transaction size
• Two input clocks (K and /K) for precise DDR timing at clock rising edges only
• Two output clocks (C and /C) for precise flight time and clock skew matching-clock and data delivered together to receiving device
• Internally self-timed write control
• Clock-stop capability with µs restart
• User programmable impedance output
• Fast clock cycle time: 4.0 ns (250 MHz)/5.0 ns (200 MHz)/6.0 ns (167 MHz)
• Simple control logic for easy depth expansion
• JTAG boundary scan Notes: QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, NEC, Samsung, and Renesas Technology Corp. Preliminary: The specifications of this device are subject to change without notice. Please contact your nearest Renesas Technology's Sales Dept. regarding specifications.

R1Q2A3636B/R1Q2A3618B/R1Q2A3609B REJ03C0341-0003 Rev.0.03 Apr. 11, 2008 Page 2 of 24

Ordering Information

Part Number Organization Cycle time Clock frequency Package Notes R1Q2A3636BBG-40R 4.0 ns 250 MHz R1Q2A3636BBG-50R 5.0 ns 200 MHz R1Q2A3636BBG-60R 1-M word × 36-bit 6.0 ns 167 MHz R1Q2A3618BBG-40R 4.0 ns 250 MHz R1Q2A3618BBG-50R 5.0 ns 200 MHz R1Q2A3618BBG-60R 2-M word × 18-bit 6.0 ns 167 MHz R1Q2A3609BBG-40R 4.0 ns 250 MHz R1Q2A3609BBG-50R 5.0 ns 200 MHz R1Q2A3609BBG-60R 4-M word × 9-bit 6.0 ns 167 MHz Plastic FBGA 165-pin PLBG0165FB-A Notes: 1. Part Number (0:1) R1 : Renesas Memory prefix (9) R : 1 stGeneration (2:3) Q2 : QDRII 2-word Burst SRAM A : 2 ndGeneration Q3 : QDRII 4-word Burst SRAM B : 3 rdGeneration Q4 : DDRII 2-word Burst SRAM (10:11) BG : Package type=BGA Q5 : DDRII 4-word Burst SRAM (12:13) 60 : Cycle time=6.0 ns Q6 : DDRII 2-word Burst SRAM 50 : Cycle time=5.0 ns Separate I/O 40 : Cycle time=4.0 ns (4) A : VDD=1.8V 33 : Cycle time=3.3 ns (5:6) 36 : Density = 36Mb (14) R : Temperature range= 0°C ∼70°C 72 : Density = 72Mb I : Temperature range= -40°C ∼85°C (7:8) 36 : Organization = x36 ( 15) B : Pb-free 18 : Organization = x18 T : Tape&Reel 09 : Organization = x9 S : Pb-free and Tape&Reel None : Standard (Pb and Tray) (16) 0 ∼9 , A ∼Z :Renesas internal use 2. Marking Name

R1Q2A3636B/R1Q2A3618B/R1Q2A3609B REJ03C0341-0003 Rev.0.03 Apr. 11, 2008 Page 3 of 24 Pin Arrangement R1Q2A3636B series 1 2 3 4 5 6 7 8 9 10 11 A /CQ VSS NC /W /BW2 /K /BW1 /R SA NC CQ B Q27 Q18 D18 SA /BW3 K /BW0 SA D17 Q17 Q8 C D27 Q28 D19 VSS SA SA SA VSS D16 Q7 D8 D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7 E Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6 F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5 G D30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5 H /DOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J D31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 D4 K Q32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3 L Q33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2 M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2 N D34 D26 Q25 VSS SA SA SA VSS Q10 D9 D1 P Q35 D35 Q26 SA SA C SA SA Q9 D0 Q0 R TDO TCK SA SA SA /C SA SA SA TMS TDI (Top View) R1Q2A3618B series 1 2 3 4 5 6 7 8 9 10 11 A /CQ VSS SA /W /BW1 /K NC /R SA NC CQ B NC Q9 D9 SA NC K /BW0 SA NC NC Q8 C NC NC D10 VSS SA SA SA VSS NC Q7 D8 D NC D11 Q10 VSS VSS VSS VSS VSS NC NC D7 E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6 F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5 G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5 H /DOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4 K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3 L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2 M NC NC D16 VSS VSS VSS VSS VSS NC Q1 D2 N NC D17 Q16 VSS SA SA SA VSS NC NC D1 P NC NC Q17 SA SA C SA SA NC D0 Q0 R TDO TCK SA SA SA /C SA SA SA TMS TDI (Top View)

R1Q2A3636B/R1Q2A3618B/R1Q2A3609B REJ03C0341-0003 Rev.0.03 Apr. 11, 2008 Page 4 of 24 R1Q2A3609B series 1 2 3 4 5 6 7 8 9 10 11 A /CQ VSS SA /W NC /K NC /R SA SA CQ B NC NC NC SA NC K /BW SA NC NC Q4 C NC NC NC VSS SA SA SA VSS NC NC D4 D NC D5 NC VSS VSS VSS VSS VSS NC NC NC E NC NC Q5 VDDQ VSS VSS VSS VDDQ NC D3 Q3 F NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC G NC D6 Q6 VDDQ VDD VSS VDD VDDQ NC NC NC H /DOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC NC VDDQ VDD VSS VDD VDDQ NC Q2 D2 K NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC L NC Q7 D7 VDDQ VSS VSS VSS VDDQ NC NC Q1 M NC NC NC VSS VSS VSS VSS VSS NC NC D1 N NC D8 NC VSS SA SA SA VSS NC NC NC P NC NC Q8 SA SA C SA SA NC D0 Q0 R TDO TCK SA SA SA /C SA SA SA TMS TDI (Top View) Notes: 1. Address expansion order for future higher density SRAMs (i.e. 72Mb → 144Mb →288Mb): (9A → 3A → 10A) → 2A → 7A → 5B.

R1Q2A3636B/R1Q2A3618B/R1Q2A3609B REJ03C0341-0003 Rev.0.03 Apr. 11, 2008 Page 5 of 24 Pin Description Name I/O type Descriptions Notes SA Input Synchronous address inputs: These inputs are registered and must meet the setup and hold times around the rising edge of K for READ cycles and must meet the setup and hold times around the rising edge of /K for WRITE cycles. All transactions operate on a burst-of-two words (one clock period of bus activity). These inputs are ignored when device is deselected. /R Input Synchronous read: When low, this input causes the address inputs to be registered and a READ cycle to be initiated. This input must meet setup and hold times around the rising edge of K. /W Input Synchronous write: When low, this input causes the address inputs to be registered and a WRITE cycle to be initiated. This input must meet setup and hold times around the rising edge of K. /BWx Input Synchronous byte writes: When low, these inputs cause their respective byte to be registered and written during WRITE cycles. These signals must meet setup and hold times around the rising edges of K and /K for each of the two rising edges comprising the WRITE cycle. See Byte Write Truth Table for signal to data relationship. K, /K Input Input clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data on the rising edge of K and the rising edge of /K. /K is ideally 180 degrees out of phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges. These balls cannot remain VREF level. C, /C Input Output clock: This clock pair provides a user-controlled means of tuning device output data. The rising edge of /C is used as the output timing reference for first output data. The rising edge of C is used as the output timing reference for second output data. Ideally, /C is 180 degrees out of phase with C. C and /C may be tied high to force the use of K and /K as the output reference clocks instead of having to provide C and /C clocks. If tied high, C and /C must remain high and not to be toggled during device operation. These balls cannot remain V REF level. /DOFF Input DLL disable: When low, this input causes the DLL to be bypassed for /DOFF Input stable, low frequency operation. ZQ Input Output impedance matching input: This input is used to tune the device outputs to the system data bus impedance. Q and CQ output impedance are set to 0.2 × RQ, where RQ is a resistor from this ball to ground. This ball can be connected directly to VDDQ, which enables the minimum impedance mode. This ball cannot be connected directly to VSS or left unconnected. TMS TDI Input IEEE1149.1 test inputs: 1.8 V I/O levels. These balls may be left not TMS Input connected if the JTAG function is not used in the circuit. TCK Input IEEE1149.1 clock input: 1.8 V I/O levels. This ball must be tied to VSS if the JTAG function is not used TCK Input in the circuit. D0 to Dn Input Synchronous data inputs: Input data must meet setup and hold times around the rising edges of K and /K during WRITE operations. See Pin Arrangement figures for ball site location of individual signals. The ×9 device uses D0 to D8. Remaining signals are not used. The ×18 device uses D0 to D17. Remaining signals are not used. The ×36 device uses D0 to D35. CQ, /CQ Output Synchronous echo clock outputs: The edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. These signals run freely and do not stop when Q tristates. TDO Output IEEE 1149.1 test output: 1.8 V I/O level. Q0 to Qn Output Synchronous data outputs: Output data is synchronized to the respective C and /C, or to the respective K and /K if C and /C are tied high. This bus operates in response to /R commands. See Pin Arrangement figures for ball site location of individual signals. The ×9 device uses Q0 to Q8. Remaining signals are not used. The ×18 device uses Q0 to Q17. Remaining signals are not used. The ×36 device uses Q0 to Q35.

R1Q2A3636B/R1Q2A3618B/R1Q2A3609B REJ03C0341-0003 Rev.0.03 Apr. 11, 2008 Page 6 of 24 Name I/O type Descriptions Notes VDD Supply Power supply: 1.8 V nominal. See DC Characteristics and Operating VDD Supply Conditions for range. See DC Characteristics and Operating Conditions for range. VSS Supply Power supply: Ground. VREF  HSTL input reference voltage: Nominally VDDQ/2, but may be adjusted to improve system noise margin. Provides a reference voltage for the HSTL input buffers. NC  No connect: These signals are not internally connected. These signals can be left floating or connected to ground to improve package heat dissipation. Notes: 1. All power supply and ground balls must be connected for proper operation of the device. Block Diagram (R1Q2A3636B / R1Q2A3618B / R1Q2A3609B series) Address Registry and Logic Data Registry and Logic Memory Array Write Register Address K /BWx D (Data in) K /36 /18 Output Register /36 /18 Output Select Output Buffer 19/20/21 36/18/9 36/18/9 Q (Data out) Write Driver Sense Amp 19/20/21 K CC , / C or K, /K ZQ CQ /CQ MUX /36 /18 4/2/1

R1Q2A3636B/R1Q2A3618B/R1Q2A3609B REJ03C0341-0003 Rev.0.03 Apr. 11, 2008 Page 7 of 24 General Description Power-up and Initialization Sequence The following supply voltage application sequence is recommended: VSS, VDD, VDDQ, VREF then VIN. After the stable power, there are three possible sequences. 1. Sequence when DLL disable (/DOFF pin fixed low) Just after the stable power and clock (K, /K, C, /C), 1024 NOP cycles (min.) are required for all operations, including JTAG functions, to become normal. 2a. Sequence controlled by /DOFF pin when DLL enable Just after the stable power and clock (K, /K, C, /C), take /DOFF to be high. The additional 1024 NOP cycles (min.) are required to lock the DLL and for all operations to become normal. 2b. Sequence controlled by Clock (/DOFF pin fixed high) when DLL enable If /DOFF pin is fixed high with unstable clock, the clock (K, /K, C, /C) must be stopped for 30ns (min.). During stop clock stage, C pin must tie low for 30 ns (min.). C, /C, K and /K cannot remain VREF level. The additional 1024 NOP cycles (min.) are required to lock the DLL and for all operations to become normal. Notes: 1. After K or C clock is stopped, clock recovery cy cles (1024 NOP cycles (min.)) are required for read/write operations to become normal. 2. When DLL is enable and the operating frequency is changed, DLL reset should be required again. After DLL reset again, the 1024 NOP cycles (min.) are needed to lock the DLL. 1. Sequence when DLL disable (/DOFF pin fixed low) Status Power Up Unstable Clock Stage Stable Clock Stage NOP Stage Normal Operation VDD C, /C, K, /K VDDQ VREF VIN 1024cycle min. 2a. Sequence controlled by /DOFF pin when DLL enable Status Power Up Unstable Clock Stage Stable Clock Stage NOP & DLL Locking Stage Normal Operation VDD C, /C, K, /K 1024cycle min. VDDQ VREF /DOFF

R1Q2A3636B/R1Q2A3618B/R1Q2A3609B REJ03C0341-0003 Rev.0.03 Apr. 11, 2008 Page 8 of 24 2b. Sequence controlled by Clock (/DOFF pin fixed high) when DLL enable Status Power Up Unstable Clock Stage Stop Clock Stage NOP & DLL Locking Stage Normal Operation VDD C, /C, K, /K 30ns min. 1024cycle min. VDDQ VREF /DOFF DLL Constraints 1. DLL uses either K or C clock as its synchronizing input, the input should have low phase jitter which is specified as TKC var. 2. The lower end of the frequency at which the DLL can operate is 119MHz. Programmable Output Impedance 1. Output buffer impedance can be programmed by terminating the ZQ ball to V SS through a precision resistor (RQ). The value of RQ is five times the output impedance desired. The allowable range of RQ to guarantee impedance matching with a tolerance of 10% is 250 Ω typical. The total external capacitance of ZQ ball must be less than 7.5 pF.

R1Q2A3636B/R1Q2A3618B/R1Q2A3609B REJ03C0341-0003 Rev.0.03 Apr. 11, 2008 Page 9 of 24 K Truth Table Operation K /R /W D or Q Data in Input data D(A+0) D(A+1) Write Cycle: Load address, input write data on consecutive K and /K rising edges ↑ × L Output clock K(t) ↑ /K(t) ↑ Data out Output data Q(A+0) Q(A+1) Read Cycle: Load address, output read data on consecutive C and /C rising edges ↑ L × Output clock /C(t+1) ↑ C(t+2) ↑ NOP (No operation) ↑ H H D = × or Q = High-Z Standby (Clock stopped) Stopped × × Previous state Notes: 1. H: high level, L: low level, ×: don’t care, ↑: rising edge. 2. Data inputs are registered at K and /K rising e dges. Data outputs are delivered at C and /C rising edges, except if C and /C are high, then data outputs are delivered at K and /K rising edges. 3. /R and /W must meet setup/hold times around the ri sing edges (low to high) of K and are registered at the rising edge of K. 4. This device contains circuitry that will en sure the outputs will be in high-Z during power-up. 5. Refer to state diagram and timing diagrams for clarification. 6. When clocks are stopped, the following cases are reco mmended; the case of K = low, /K = high, C = low and /C = high, or the case of K = high, /K = low, C = high and /C = low. This condition is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.

R1Q2A3636B/R1Q2A3618B/R1Q2A3609B REJ03C0341-0003 Rev.0.03 Apr. 11, 2008 Page 10 of 24 Byte Write Truth Table (x36) Operation K /K /BW0 /BW1 /BW2 /BW3 Write D0 to D35 ↑  L L L L  ↑ L L L L Write D0 to D8 ↑  L H H H  ↑ L H H H Write D9 to D17 ↑  H L H H  ↑ H L H H Write D18 to D26 ↑  H H L H  ↑ H H L H Write D27 to D35 ↑  H H H L  ↑ H H H L Write nothing ↑  H H H H  ↑ H H H H Notes: 1. H: high level, L: low level, ↑: rising edge. 2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied. Byte Write Truth Table (x18) Operation K /K /BW0 /BW1 Write D0 to D17 ↑  L L  ↑ L L Write D0 to D8 ↑  L H  ↑ L H Write D9 to D17 ↑  H L  ↑ H L Write nothing ↑  H H  ↑ H H Notes: 1. H: high level, L: low level, ↑: rising edge. 2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied. Byte Write Truth Table (x9) Operation K /K /BW Write D0 to D8 ↑  L  ↑ L Write nothing ↑  H  ↑ H Notes: 1. H: high level, L: low level, ↑: rising edge. 2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied.

R1Q2A3636B/R1Q2A3618B/R1Q2A3609B REJ03C0341-0003 Rev.0.03 Apr. 11, 2008 Page 11 of 24 Bus Cycle State Diagram Read Port NOP RInit = 0 Read DoubleLoad New Read Address Power Up /R = H Write Port NOP /W = H Supply voltage provided Supply voltage provided /R = L Always /R = L /R = H Write Double at /K↑ Load New Write Address at /K↑/W = L Always /W = L /W = H Notes: 1. The address is concatenated wi th one additional internal LSB to facilitate burst operation. The address order is always fixed as: xxx…xxx+0, xxx…xxx+1. Bus cycle is terminated at the end of this sequence (burst count = 2). 2. Read and write state machines can be active simultaneously. 3. State machine control timing sequence is controlled by K.

R1Q2A3636B/R1Q2A3618B/R1Q2A3609B REJ03C0341-0003 Rev.0.03 Apr. 11, 2008 Page 12 of 24 Absolute Maximum Ratings Parameter Symbol Rating Unit Notes Input voltage on any ball V IN −0.5 to VDD + 0.5 (2.5 V max.) V 1, 4 Input/output voltage V I/O −0.5 to VDDQ + 0.5 (2.5 V max.) V 1, 4 Core supply voltage V DD −0.5 to 2.5 V 1, 4 Output supply voltage V DDQ −0.5 to VDD V 1, 4 Junction temperature Tj +125 (max) °C Storage temperature T STG −55 to +125 °C Notes: 1. All voltage is referenced to V SS. 2. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted the Operation Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. 3. These CMOS memory circuits have been designed to meet the DC and AC specifications shown in the tables after thermal equilibrium has been established. 4. The following supply voltage a pplication sequence is recommended: VSS, VDD, VDDQ, VREF then VIN. Remember, according to the Absolute Maximum Ratings table, VDDQ is not to exceed 2.5 V, whatever the instantaneous value of VDDQ. Recommended DC Operating Conditions (Ta = 0 to +70°C) Parameter Symbol Min Typ Max Unit Notes Power supply voltage --core V DD 1.7 1.8 1.9 V Power supply voltage --I/O V DDQ 1.4 1.5 V DD V Input reference voltage --I/O V REF 0.68 0.75 0.95 V 1 Input high voltage V IH (DC) V REF + 0.1  V DDQ + 0.3 V 2, 3 Input low voltage V IL (DC) −0.3  V REF − 0.1 V 2, 3 Notes: 1. Peak to peak AC component superimposed on V REF may not exceed 5% of VREF. 2. Overshoot: V IH (AC) ≤ VDDQ + 0.5 V for t ≤ tKHKH/2 Undershoot: V IL (AC) ≥ −0.5 V for t ≤ tKHKH/2 Power-up: V IH ≤ VDDQ + 0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms During normal operation, V DDQ must not exceed VDD. Control input signals may not have pulse widths less than t KHKL (min) or operate at cycle rates less than tKHKH (min). During normal operation, V IH(DC) must not exceed VDDQ and VIL(DC) must not be lower than VSS. 3. These are DC test criteria. The AC V IH / VIL levels are defined separately to measure timing parameters. DC Characteristics (Ta = 0 to +70°C, VDD = 1.8V ± 0.1V) −40 −50 −60 Parameter Symbol Max Max Max Unit Notes (×9) I DD 600 550 500 mA 1, 2, 3 (×18) I DD 650 600 550 mA 1, 2, 3 Operating supply current (READ / WRITE) (×36) I DD 700 650 600 mA 1, 2, 3 Standby supply current (NOP) (×9 / ×18 / ×36) I SB1 350 340 330 mA 2, 4, 5

R1Q2A3636B/R1Q2A3618B/R1Q2A3609B REJ03C0341-0003 Rev.0.03 Apr. 11, 2008 Page 13 of 24 Parameter Symbol Min Max Unit Test conditions Notes Input leakage current I LI −2 2 µA 10 Output leakage current I LO −5 5 µA 11 Output high voltage V OH (Low) V DDQ −0.2 V DDQ V |I OH| ≤ 0.1 mA 8, 9 V OH V DDQ/2 −0.08 V DDQ/2 +0.08 V Note 6 8, 9 Output low voltage V OL (Low) V SS 0.2 V I OL ≤ 0.1 mA 8, 9 V OL V DDQ/2 −0.08 V DDQ/2 +0.08 V Note 7 8, 9 Notes: 1. All inputs (except ZQ, V REF) are held at either VIH or VIL. 2. I OUT = 0 mA. VDD = VDD max, tKHKH = tKHKH min. 3. Operating supply currents are measured at 100% bus utilization. 4. All address / data inputs are static at either VIN > VIH or VIN < VIL. 5. Reference value (Condition=NOP currents are valid when entering NOP after all pending READ and WRITE cycles are completed.) 6. Outputs are im pedance-controlled. |IOH| = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω. 7. Outputs are im pedance-controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω. 8. AC load current is higher than the shown DC values. AC I/O curves are available upon request. 9. HSTL outputs meet JEDEC HSTL Class I standards. 10. 0 ≤ VIN ≤ VDDQ for all input balls (except VREF, ZQ, TCK, TMS, TDI ball). 11. 0 ≤ VOUT ≤ VDDQ (except TDO ball), output disabled. Thermal Resistance Parameter Symbol Typ Unit Notes Junction to Ambient θJA 24.5 °C/W Junction to Case θJC 5.6 °C/W Note: These parameters are calculated under the condition of wind velocity = 1 m/s. Capacitance (Ta = +25°C, f=1.0MHz, VDD = 1.8V, VDDQ = 1.5V) Parameter Symbol Min Typ Max Unit Test conditions Notes Input capacitance C IN  2 3 pF V IN = 0 V 1, 2 Clock input capacitance C CLK  2 3 pF V CLK = 0 V 1, 2 Input/output capacitance (D, Q, ZQ) C I/O  3 4.5 pF V I/O = 0 V 1, 2 Notes: 1. These parameters ar e sampled and not 100% tested. 2. Except JTAG (TCK, TMS, TDI, TDO) pins. AC Test Conditions (Ta = 0 to +70°C, VDD = 1.8V ±0.1V) Input waveform (Rise/fall time ≤ 0.3 ns) 1.25 V 0.25 V 0.75 V 0.75 V Test points

R1Q2A3636B/R1Q2A3618B/R1Q2A3609B REJ03C0341-0003 Rev.0.03 Apr. 11, 2008 Page 14 of 24 Output waveform VDDQ /2 Test points V DDQ /2 Output load condition 50 Ω 0.75 V ZQ Q VREF 250 Ω Z0 = 50 ΩSRAM VDDQ /2 AC Operating Conditions Parameter Symbol Min Typ Max Unit Notes Input high voltage V IH (AC) V REF + 0.2   V 1, 2, 3, 4 Input low voltage V IL (AC)   V REF − 0.2 V 1, 2, 3, 4 Notes: 1. All voltages referenced to V SS (GND). 2. These conditions are for AC functi ons only, not for AC parameter test. 3. Overshoot: V IH (AC) ≤ VDDQ + 0.5 V for t ≤ tKHKH/2 Undershoot: V IL (AC) ≥ −0.5 V for t ≤ tKHKH/2 Power-up: V IH ≤ VDDQ + 0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms During normal operation, V DDQ must not exceed VDD. Control input signals may not have pulse widths less than tKHKL (min) or operate at cycle rates less than tKHKH (min). 4. To maintain a valid level, the transitioning edge of the input must: a. Sustain a constant slew rate from the cu rrent AC level through the target AC level, VIL (AC) or VIH (AC). b. Reach at least the target AC level. c. After the AC target level is reached, cont inue to maintain at least the target DC level, V IL (DC) or VIH (DC).

R1Q2A3636B/R1Q2A3618B/R1Q2A3609B REJ03C0341-0003 Rev.0.03 Apr. 11, 2008 Page 15 of 24 AC Characteristics (Ta = 0 to +70°C, VDD = 1.8V ± 0.1V) −40 −50 −60 Parameter Symbol Min Max Mi n Max Min Max Unit Notes Average clock cycle time (K, /K, C, /C) Clock phase jitter (K, /K, C, /C) tKC var  0.20  0.20  0.20 ns 3 Clock high time (K, /K, C, /C) tKHKL 1.60  2.00  2.40  ns Clock low time (K, /K, C, /C) tKLKH 1.60  2.00  2.40  ns Clock to /clock (K to /K, C to /C) tKH/KH 1.80  2.20  2.70  ns /Clock to clock (/K to K, /C to C) t/KHKH 1.80  2.20  2.70  ns Clock to data clock (K to C, /K to /C) tKHCH 0 1.10 0 1.60 0 2.10 ns DLL lock time (K, C) t KC lock 1,024  1,024  1,024  Cycle 2 K static to DLL reset t KC reset 30  30  30  ns 7 C, /C high to output valid t CHQV  0.45  0.45  0.50 ns C, /C high to output hold t CHQX −0.45  −0.45  −0.50  ns C, /C high to echo clock valid t CHCQV  0.45  0.45  0.50 ns C, /C high to echo clock hold t CHCQX −0.45  −0.45  −0.50  ns CQ, /CQ high to output valid t CQHQV  0.30  0.35  0.40 ns 4, 7 CQ, /CQ high to output hold t CQHQX −0.30  −0.35  −0.40  ns 4, 7 C, /C high to output high-Z t CHQZ  0.45  0.45  0.50 ns 5 C, /C high to output low-Z t CHQX1 −0.45  −0.45  −0.50  ns 5 Address valid to K, /K rising edge tAVKH 0.35  0.40  0.50  ns 1 Control inputs valid to K rising edge tIVKH 0.35  0.40  0.50  ns 1 Data-in valid to K, /K rising edge t DVKH 0.35  0.40  0.50  ns 1 K, /K rising edge to address hold t KHAX 0.35  0.40  0.50  ns 1 K, /K rising edge to control inputs hold tKHIX 0.35  0.40  0.50  ns 1 K, /K rising edge to data-in hold t KHDX 0.35  0.40  0.50  ns 1 Notes: 1. This is a synchronous devic e. All addresses, data and control lines must meet the specified setup and hold times for all latching clock edges. 2. V DD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable. It is recommended that the device is kept inactive during these cycles. 3. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 4. Echo clock is very tightly controlled to data valid / dat a hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guardbands and test setup variations. 5. Transitions are measured ±100 mV from steady-state voltage. 6. At any given voltage and temperature t CHQZ is less than tCHQX1 and tCHQZ less than tCHQV. 7. These parameters are sampled. Remarks: 1. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise noted. 2. Control input signals may not be op erated with pulse widths less than tKHKL (min). 3. If C, /C are tied high, K, /K become the references for C, /C timing parameters. 4. V DDQ is +1.5 V DC. 5. Control signals are /R, /W, /BW, /BW0, /BW1, /BW2 and /BW3. BWn signals must operate at the same timing as Data in.

R1Q2A3636B/R1Q2A3618B/R1Q2A3609B REJ03C0341-0003 Rev.0.03 Apr. 11, 2008 Page 16 of 24 Timing Waveforms Read and Write Timing 1 2 34 56 78 91 0 11 12 13 14 15 16 17 K Q00 Q01 Q20 Q21 Q40 Q41 Q60 Q61 tKHDXtDVKH tKHDXtDVKH Address Data in tCHQV -tCHQX tCHQV -tCHQX tCQHQV -tCQHQX -tCHQX1 tCHQZ tCHCQV -tCHCQX tCHCQV -tCHCQX tKHKH tKHKL tKLKH tKH/KH t/KHKH tKHKH tKHKL tKLKH tKH/KH t/KHKH tKHCH tKHCH Data out CQ /CQ C tKHAXtAVKH tKHIXtIVKH READ WRITE NOP NOP READ WRITE READ WRITE NOP WRITE READ WRITE NOP NOP NOP NOP tKHIXtIVKH A2A1 A4A3 A5 A7A6 A8 D10 D11 D30 D31 D50 D51 D70 D71 D80 D81 Notes: 1. Q00 refers to output from address A0+0. Q01 re fers to output from the next internal burst address following A0, i.e., A0+1. 2. Outputs are disable (high-Z) one clock cycle after a NOP. 3. In this example, if address A0 = A1, then data Q 00 = D10, Q01 = D11. Write data is forwarded immediately as read results. 4. To control read and write operations, /BW signal s must operate at the same timing as Data in.

R1Q2A3636B/R1Q2A3618B/R1Q2A3609B REJ03C0341-0003 Rev.0.03 Apr. 11, 2008 Page 17 of 24 JTAG Specification These products support a limited set of JTAG functions as in IEEE standard 1149.1. Disabling the Test Access Port It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfering with normal operation of the device, TCK must be tied to VSS to preclude mid level inputs. TDI and TMS are designed so an undriven input will produce a response identical to the application of a logic 1,and may be left unconnected. But they may also be tied to V DD through a 1kΩ resistor.TDO should be left unconnected. Test Access Port (TAP) Pins Symbol I/O Pin assignments Description Notes TCK 2R Test clock input. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS 10R Test mode select. This is the command input for the TAP controller state machine. TDI 11R Test data input. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP controller state machine and the instruction that is currently loaded in the TAP instruction. TDO 1R Test data output. Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. Notes: The device does not have TRST (TAP reset). The Te st-Logic Reset state is entered while TMS is held high for five rising edges of TCK. The TAP controller state is also reset on SRAM POWER-UP. TAP DC Operating Characteristics (Ta = 0 to +70°C, VDD = 1.8V ± 0.1V) Parameter Symbol Min Typ Max Unit Notes Input high voltage V IH +1.3  V DD + 0.3 V Input low voltage V IL −0.3  +0.5 V Input leakage current I LI −5.0  +5.0 µA 0 V ≤ VIN ≤ VDD Output leakage current I LO −5.0  +5.0 µA 0 V ≤ VIN ≤ VDD, output disabled Output low voltage V OL1   0.2 V I OLC = 100 µA V OL2   0.4 V I OLT = 2 mA Output high voltage V OH1 1.6   V |I OHC| = 100 µA V OH2 1.4   V |I OHT| = 2 mA Notes: 1. All voltages referenced to V SS (GND). 3. In “EXTEST” mode and “SAMPLE” mode, V DDQ is nominally 1.5 V. 4. ZQ: V IH = VDDQ.

R1Q2A3636B/R1Q2A3618B/R1Q2A3609B REJ03C0341-0003 Rev.0.03 Apr. 11, 2008 Page 18 of 24 TAP AC Test Conditions Parameter Symbol Conditions Unit Notes Temperature Ta 0 ≤ Ta ≤ +70 °C Input timing measurement reference levels V REF 0.9 V Input pulse levels V IL, VIH 0 to 1.8 V Input rise/fall time tr, tf ≤ 1.0 ns Output timing measurement reference levels 0.9 V Test load termination supply voltage (VTT) 0.9 V Output load See figures Input waveform 1.8 V 0 V 0.9 V 0.9 V Test points Output waveform 0.9 V Test points 0.9 V Output load condition External Load at Test 50 Ω VTT = 0.9 V TDO Z0 = 50 Ω DUT 20 pF

R1Q2A3636B/R1Q2A3618B/R1Q2A3609B REJ03C0341-0003 Rev.0.03 Apr. 11, 2008 Page 19 of 24 TAP AC Operating Characteristics (Ta = 0 to +70°C, VDD = 1.8V ±0.1V) Parameter Symbol Min Typ Max Unit Notes Test clock (TCK) cycle time t THTH 100   ns TCK high pulse width t THTL 40   ns TCK low pulse width t TLTH 40   ns Test mode select (TMS) setup t MVTH 10   ns TMS hold t THMX 10   ns Capture setup t CS 10   ns 1 Capture hold t CH 10   ns 1 TDI valid to TCK high t DVTH 10   ns TCK high to TDI invalid t THDX 10   ns TCK low to TDO unknown t TLQX 0   ns TCK low to TDO valid t TLQV   20 ns Notes: 1. t CS + tCH defines the minimum pause in RAM I/O pad transitions to assure pad data capture. TAP Controller Timing Diagram TCK TDI TMS TDO PI (SRAM) tTHTLtTHTH tTLTH tMVTH tTHMX tDVTH tTHDX tCS tCH tTLQV tTLQX

R1Q2A3636B/R1Q2A3618B/R1Q2A3609B REJ03C0341-0003 Rev.0.03 Apr. 11, 2008 Page 20 of 24 Test Access Port Registers Register name Length Symbol Notes Instruction register 3 bits IR [2:0] Bypass register 1 bits BP ID register 32 bits ID [31:0] Boundary scan register 109 bits BS [109:1] TAP Controller Instruction Set IR2 IR1 IR0 Instruction Description Notes 0 0 0 EXTEST The EXTEST instruction allows circuitry external to the component package to be tested. Boundary scan register cells at output balls are used to apply test vectors, while those at input balls capture test results. Typically, the first test vector to be applied using the EXTEST instruction will be shifted into the boundary scan register using the PRELOAD instruction. Thus, during the Update-IR state of EXTEST, the output driver is turned on and the PRELOAD data is driven onto the output balls. 1, 2, 3 0 0 1 IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in capture-DR mode and places the ID register between the TDI and TDO balls in shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. 0 1 0 SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z), moving the TAP controller into the capture-DR state loads the data in the RAMs input into the boundary scan register, and the boundary scan register is connected between TDI and TDO when the TAP controller is moved to the shift-DR state. 3, 4 0 1 1 RESERVED The RESERVED instructions are not implemented but are reserved for future use. Do not use these instructions. 1 0 0 SAMPLE (/PRELOAD) When the SAMPLE instruction is loaded in the instruction register, moving the TAP controller into the capture-DR state loads the data in the RAMs input and I/O buffers into the boundary scan register. Because the RAM clock(s) are independent from the TAP clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state). Although allowing the TAP to SAMPLE metastable input will not harm the device, repeatable results cannot be expected. Moving the controller to shift-DR state then places the boundary scan register between the TDI and TDO balls. 1 0 1 RESERVED 1 1 0 RESERVED 1 1 1 BYPASS The BYPASS instruction is loaded in the instruction register when the bypass register is placed between TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. Notes: 1. Data in output register is no t guaranteed if EXTEST instruction is loaded. 2. After performing EXTEST, power-up conditions are re quired in order to return part to normal operation. 3. RAM input signals must be stabilized for long enough to meet the TAPs input data capture setup plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the boundary scan register. 4. Clock recovery initialization cycles are re quired to return from the SAMPLE-Z instruction.

R1Q2A3636B/R1Q2A3618B/R1Q2A3609B REJ03C0341-0003 Rev.0.03 Apr. 11, 2008 Page 21 of 24 Boundary Scan Order Signal names Signal names Bit # Ball ID x9 x18 x36 Bit # Ball ID x9 x18 x36 1 6R /C /C /C 50 8B SA SA SA 2 6P C C C 51 7C SA SA SA 3 6N SA SA SA 52 6C SA SA SA 4 7P SA SA SA 53 8A /R /R /R 5 7N SA SA SA 54 7A NC NC /BW1 6 7R SA SA SA 55 7B /BW /BW0 /BW0 7 8R SA SA SA 56 6B K K K 8 8P SA SA SA 57 6A /K /K /K 9 9R SA SA SA 58 5B NC NC /BW3 10 11P Q0 Q0 Q0 59 5A NC /BW1 /BW2 11 10P D0 D0 D0 60 4A /W /W /W 12 10N NC NC D9 61 5C SA SA SA 13 9P NC NC Q9 62 4B SA SA SA 14 10M NC Q1 Q1 63 3A SA SA NC 15 11N NC D1 D1 64 2A V SS V SS V SS 16 9M NC NC D10 65 1A /CQ /CQ /CQ 17 9N NC NC Q10 66 2B NC Q9 Q18 18 11L Q1 Q2 Q2 67 3B NC D9 D18 19 11M D1 D2 D2 68 1C NC NC D27 20 9L NC NC D11 69 1B NC NC Q27 21 10L NC NC Q11 70 3D NC Q10 Q19 22 11K NC Q3 Q3 71 3C NC D10 D19 23 10K NC D3 D3 72 1D NC NC D28 24 9J NC NC D12 73 2C NC NC Q28 25 9K NC NC Q12 74 3E Q5 Q11 Q20 26 10J Q2 Q4 Q4 75 2D D5 D11 D20 27 11J D2 D4 D4 76 2E NC NC D29 28 11H ZQ ZQ ZQ 77 1E NC NC Q29 29 10G NC NC D13 78 2F NC Q12 Q21 30 9G NC NC Q13 79 3F NC D12 D21 31 11F NC Q5 Q5 80 1G NC NC D30 32 11G NC D5 D5 81 1F NC NC Q30 33 9F NC NC D14 82 3G Q6 Q13 Q22 34 10F NC NC Q14 83 2G D6 D13 D22 35 11E Q3 Q6 Q6 84 1H /DOFF /DOFF /DOFF 36 10E D3 D6 D6 85 1J NC NC D31 37 10D NC NC D15 86 2J NC NC Q31 38 9E NC NC Q15 87 3K NC Q14 Q23 39 10C NC Q7 Q7 88 3J NC D14 D23 40 11D NC D7 D7 89 2K NC NC D32 41 9C NC NC D16 90 1K NC NC Q32 42 9D NC NC Q16 91 2L Q7 Q15 Q24 43 11B Q4 Q8 Q8 92 3L D7 D15 D24 44 11C D4 D8 D8 93 1M NC NC D33 45 9B NC NC D17 94 1L NC NC Q33 46 10B NC NC Q17 95 3N NC Q16 Q25 47 11A CQ CQ CQ 96 3M NC D16 D25 48 10A SA NC NC 97 1N NC NC D34 49 9A SA SA SA 98 2M NC NC Q34

R1Q2A3636B/R1Q2A3618B/R1Q2A3609B REJ03C0341-0003 Rev.0.03 Apr. 11, 2008 Page 22 of 24 Signal names Signal names Bit # Ball ID x9 x18 x36 Bit # Ball ID x9 x18 x36 99 3P Q8 Q17 Q26 105 4P SA SA SA 100 2N D8 D17 D26 106 5P SA SA SA 101 2P NC NC D35 107 5N SA SA SA 102 1P NC NC Q35 108 5R SA SA SA 103 3R SA SA SA 109  INTERNAL INTERNAL INTERNAL 104 4R SA SA SA Notes: In boundary scan mode, 1. Clock balls (K, /K, C, /C) are referenced to each other and must be at opposite logic levels for reliable operation. 2. CQ and /CQ data are synchronized to the re spective C and /C (except EXTEST, SAMPLE-Z). 3. If C and /C tied high, CQ is generated with respec t to K and /CQ is generated with respect to /K (except EXTEST, SAMPLE-Z). 4. ZQ must be driven to V DDQ supply to ensure consistent results.

R1Q2A3636B/R1Q2A3618B/R1Q2A3609B REJ03C0341-0003 Rev.0.03 Apr. 11, 2008 Page 23 of 24 ID Register Part Revision number (31:29) Type number (28:12) Vendor JEDEC code (11:1) Start bit (0)   0 0MMM 0WW0 10Q0 B0S0   R1Q2A3636B 000 0 0010 0110 1010 0010 0100 0100 011 1 R1Q2A3618B 000 0 0010 0100 1010 0010 0100 0100 011 1 R1Q2A3609B 000 0 0010 0000 1010 0010 0100 0100 011 1 Notes: 1. Type number MMM :Density 011:72Mb, 010:36Mb, 001:18Mb WW :Organization 11: x 36, 10: x 18, 00: x 9, 01: x 8 Q :QDR/DDR 1: QDR, 0: DDR B :Burst lengths 1: 4-word burst, 0: 2-word burst S :I/O 1: Separate I/O, 0: Common I/O TAP Controller State Diagram Select IR Scan Capture IR Shift IR Exit1 IR Pause IR Exit2 IR Update IR Select DR Scan Capture DR Shift DR Exit1 DR Pause DR Exit2 DR Update DR Run Test/Idle 010 1 Test Logic Reset Notes: The value adjacent to each state transition in this figure represents the signal present at TMS at the time of a rising edge at TCK. No matter what the original state of the controll er, it will enter Test-Logic-Reset when TMS is held high for at least five rising edges of TCK.

R1Q2A3636B/R1Q2A3618B/R1Q2A3609B REJ03C0341-0003 Rev.0.03 Apr. 11, 2008 Page 24 of 24 Package Dimensions R1Q2A3636B/R1Q2A3618B/ R1Q2A3609B (PLBG0165FB-A) 1y S yS S BA A 23456789 1 0 1 1 B C D E F G H J K L M N P R INDEX A A PLBG0165FB-AP-LBGA165-15x17-1.00 D E SD SE ZD ZE MASS[Typ.] 0.7gBP-165A RENESAS CodeJEITA Package Code Previous Code 0.25y1 w v 0.20 17.00 1.46 0.370.320.27 0.550.500.45 1.00 0.15 15.00 y x b A Reference Symbol Dimension in Millimeters Min Nom Max e 17.10 15.1014.90 16.90 1.34 1.40 SAB S e e φ0.07 bφ M φ × M D E

Revision History R1Q2A3636B/R1Q2A3618B/R1Q2A3609B Data Sheet Contents of Modification Rev. Date Page Description 0.01 Jan.31, 2008  Initial issue 0.02 Feb.29,2008 P7 P14 DLL Constraints 2.the lower end of the frequency at which the DLL can operate is 119MHz AC characteristics Average clock cycle time is enlarged t KHKH(-40)(max) 8.40ns, tKHKH(-50)(max) 8.40ns, tKHKH(-60)(max) 8.40ns 0.03 Apr.11,2008 P2 Ordering Infomatuon: Adding Part Number and Marking Name 1.Part Number (9) R: 1stGeneration,A: 2ndGeneration,B: 3rdGeneration (10:11) BG: Package type=BGA (12:13) 60: Cycle time=6.0 ns,50 : Cycle time=5.0 ns,40: Cycle time=4.0 ns 3 3 : C y c l e t i m e = 3 . 3 n s (14) R: Temperature range= 0°C∼ 70°C,I: Temperature range= -40°C∼ 85°C (15) B: Pb-free,T: Tape&Reel,S: Pb-free and Tape&Reel None: Standard (Pb and Tray) (16) 0 to 9 , A to Z: Renesas internal use 2.Marking Name (Example)

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Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2377-3473 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Renesas Technology Singapore Pte. Ltd.

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Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 RENESAS SALES OFFICES © 2008. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .7.2