R1LV0416CBG-I RENESAS | Alldatasheet
Document overview
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Technical content
Features
- Single 2.5 V and 3.0 V supply: 2.2 V to 3.6 V
- Fast access time: 55/70 ns (max)
- Power dissipation: Active: 5.0 mW/MHz (typ)(VCC = 2.5 V) : 6.0 mW/MHz (typ) (V CC = 3.0 V) Standby: 1.25 µW (typ) (VCC = 2.5 V) : 1.5 µW (typ) (VCC = 3.0 V)
- Completely static memory. No clock or timing strobe required
- Access and cycle times are equal.
- Common data input and output. Three state output
- Battery backup operation. 2 chip selection for battery backup
- Temperature range: −40 to +85°C
Ordering Information
Type No. Access time Package R1LV0416CBG-5SI 55 ns 48-ball CSP with 0.75 mm ball pitch (48FHH) R1LV0416CBG-7LI 70 ns Preliminary: The specifications of this device are subject to change without notice. Please contact your nearest Renesas Technology’s Sales Dept. regarding specifications.
Rev.0.01, Jan.11.2005, page 2 of 14 Pin Arrangement (Top view) 48-ball CSP A B C D E F G H 1 2 3 4 5 6 LB# I/O8 I/O9 VSS VCC I/O14 I/O15 NC OE# UB# I/O10 I/O11 I/O12 I/O13 NC A17 NC A14 A12 A16 A15 A13 A10 CS1# I/O1 I/O3 I/O4 I/O5 WE# A11 CS2 I/O0 I/O2 VCC VSS I/O6 I/O7 NC Pin Description Pin name Function A0 to A17 Address input I/O0 to I/O15 Data input/output CS1# (CS1) Chip select 1 CS2 Chip select 2 WE# (WE) Write enable OE# (OE) Output enable LB# (LB) Lower byte select UB# (UB) Upper byte select VCC Power supply VSS Ground NC No connection
Rev.0.01, Jan.11.2005, page 3 of 14 Block Diagram I/O0 I/O15 CS2 WE# OE# A4 A3 A2 A5 A0 V V CC SS Row decoder Memory matrix 2,048 x 2,048 Column I/O Column decoderInput data control Control logic A12 A11 A10 A13 A14 A15 A16 A17 CS1# LB# UB# LSB MSB LSB MSB
Rev.0.01, Jan.11.2005, page 4 of 14 Operation Table CS1# CS2 WE# OE# UB# LB# I/O0 to I/O7 I/O8 to I/O15 Operation H × × × × × High-Z High-Z Standby × L × × × × High-Z High-Z Standby × × × × H H High-Z High-Z Standby L H H L L L Dout Dout Read L H H L H L Dout High-Z Lower byte read L H H L L H High-Z Dout Upper byte read L H L × L L Din Din Write L H L × H L Din High-Z Lower byte write L H L × L H High-Z Din Upper byte write L H H H × × High-Z High-Z Output disable Note: H: V IH, L: VIL, ×: VIH or VIL Absolute Maximum Ratings Parameter Symbol Value Unit Power supply voltage relative to VSS V CC −0.5 to +4.6 V Terminal voltage on any pin relative to VSS V T −0.5*1 to VCC + 0.3*2 V Power dissipation P T 0.7 W Operating temperature Topr −40 to +85 °C Storage temperature range Tstg −65 to +150 °C Storage temperature range under bias Tbias −40 to +85 °C Notes: 1. V T min: −3.0 V for pulse half-width ≤ 30 ns. 2. Maximum voltage is +4.6 V. DC Operating Conditions (Ta = −40 to +85°C) Parameter Symbol Min Typ Max Unit Note Supply voltage V CC 2.2 2.5/3.0 3.6 V V SS 0 0 0 V Input high voltage V CC = 2.2 V to 2.7 V V IH 2.0 V CC + 0.3 V V CC = 2.7 V to 3.6 V V IH 2.2 V CC + 0.3 V Input low voltage V CC = 2.2 V to 2.7 V V IL −0.2 0.4 V 1 V CC = 2.7 V to 3.6 V V IL −0.3 0.6 V 1 Note: 1. V IL min: −3.0 V for pulse half-width ≤ 30 ns.
Rev.0.01, Jan.11.2005, page 5 of 14 DC Characteristics Parameter Symbol Min Typ Max Unit Test conditions Input leakage current |I LI| 1 µA Vin = V SS to VCC Output leakage current |I LO| 1 µA CS1# = V IH or CS2 = VIL or OE# = VIH or WE# = VIL or LB# = UB# = VIH, VI/O = VSS to VCC Operating current I CC 5*1 20 mA CS1# = V IL, CS2 = VIH, Others = VIH/VIL, II/O = 0 mA Average operating current I CC1 8*1 25 mA Min. cycle, duty = 100%, II/O = 0 mA, CS1# = VIL, CS2 = VIH, Others = VIH/VIL I CC2 2*1 5 mA Cycle time = 1 µs, duty = 100%, I I/O = 0 mA, CS1# ≤ 0.2 V, CS2 ≥ VCC − 0.2 V VIH ≥ VCC − 0.2 V, VIL ≤ 0.2 V Standby current I SB 0.1*1 0.3 mA CS2 = V IL to +85°C I SB1 10 µA Vin ≥ 0 V to +70°C I SB1 8 µA (1) 0 V ≤ CS2 ≤ 0.2 V or to +40°C I SB1 0.7*2 3 µA (2) CS1# ≥ VCC − 0.2 V, −5SI to +25°C I SB1 0.5*1 2.5 µA CS2 ≥ VCC − 0.2 V or to +85°C I SB1 20 µA (3) LB# = UB# ≥ VCC − 0.2 V, to +70°C I SB1 16 µA CS2 ≥ VCC − 0.2 V, to +40°C I SB1 0.7*2 10 µA CS1# ≤ 0.2 V Standby current −7LI to +25°C I SB1 0.5*1 10 µA Output high voltage V CC =2.2 V to 2.7 V V OH 2.0 — — V I OH = −0.5 mA V CC =2.7 V to 3.6 V V OH 2.4 — — V I OH = −1 mA V CC =2.2 V to 3.6 V V OH2 V CC − 0.2 — — V I OH = −100 µA Output low voltage V CC =2.2 V to 2.7 V V OL — — 0.4 V I OL = 0.5 mA V CC =2.7 V to 3.6 V V OL — — 0.4 V I OL = 2 mA V CC =2.2 V to 3.6 V V OL2 — — 0.2 V I OL = 100 µA Notes: 1. Typical values are at V CC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed. 2. Typical values are at V CC = 3.0 V, Ta = +40°C and specified loading, and not guaranteed. Capacitance (Ta = +25°C, f = 1.0 MHz) Parameter Symbol Min Typ Max Unit Test conditions Note Input capacitance Cin 8 pF Vin = 0 V 1 Input/output capacitance C I/O 10 pF V I/O = 0 V 1 Note: 1. This parameter is sampled and not 100% tested.
Rev.0.01, Jan.11.2005, page 6 of 14 AC Characteristics (Ta = −40 to +85°C, VCC = 2.2 V to 3.6 V, unless otherwise noted.) Test Conditions
- Input pulse levels: VIL = 0.4 V, VIH = 2.2 V (VCC = 2.2 V to 2.7 V) : V IL = 0.4 V, VIH = 2.4 V (VCC = 2.7 V to 3.6 V)
- Input rise and fall time: 5 ns
- Input/output timing reference levels: 1.1 V (VCC = 2.2 V to 2.7 V) : 1.4 V (V CC = 2.7 V to 3.6 V)
- Output load: See figures (Including scope and jig) Dout 30pF VTM VTM = 2.3 V R1 = 3070 Ω R2 = 3150 Ω 50pF Dout RL=500 Ω 1.4 V Output load (A) (VCC = 2.2 V to 2.7 V) Output load (B) (VCC = 2.7 V to 3.6 V) Read Cycle R1LV0416CBG-I -5SI -7LI Parameter Symbol Min Max Min Max Unit Notes Read cycle time t RC 55 70 ns Address access time t AA 55 70 ns Chip select access time t ACS1 55 70 ns t ACS2 55 70 ns Output enable to output valid t OE 35 40 ns Output hold from address change t OH 10 10 ns LB#, UB# access time t BA 55 70 ns Chip select to output in low-Z t CLZ1 10 10 ns 2, 3 t CLZ2 10 10 ns 2, 3 LB#, UB# disable to low-Z t BLZ 5 5 ns 2, 3 Output enable to output in low-Z t OLZ 5 5 ns 2, 3 Chip deselect to output in high-Z t CHZ1 0 20 0 25 ns 1, 2, 3 t CHZ2 0 20 0 25 ns 1, 2, 3 LB#, UB# disable to high-Z t BHZ 0 20 0 25 ns 1, 2, 3 Output disable to output in high-Z t OHZ 0 20 0 25 ns 1, 2, 3
Rev.0.01, Jan.11.2005, page 7 of 14 Write Cycle R1LV0416CBG-I -5SI -7LI Parameter Symbol Min Max Min Max Unit Notes Write cycle time t WC 55 70 ns Address valid to end of write t AW 50 60 ns Chip selection to end of write t CW 50 60 ns 5 Write pulse width t WP 40 50 ns 4 LB#, UB# valid to end of write t BW 50 55 ns Address setup time t AS 0 0 ns 6 Write recovery time t WR 0 0 ns 7 Data to write time overlap t DW 25 30 ns Data hold from write time t DH 0 0 ns Output active from end of write t OW 5 5 ns 2 Output disable to output in high-Z t OHZ 0 20 0 25 ns 1, 2, 3 Write to output in high-Z t WHZ 0 20 0 25 ns 1, 2 Notes: 1. t CHZ, tOHZ, tWHZ and tBHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. At any given temper ature and voltage condition, tHZ max is less than tLZ min both for a given device and from device to device. 4. A write occures during the overl ap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A write begins at the latest transition among CS1# going low, CS2 going high, WE# going low and LB# going low or UB# going low. A write ends at the earliest transition among CS1# going high, CS2 going low, WE# going high and LB# going high or UB# going high. tWP is measured from the beginning of write to the end of write. 5. t CW is measured from the later of CS1# going low or CS2 going high to the end of write. 6. t AS is measured from the address valid to the beginning of write. 7. t WR is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle.
Rev.0.01, Jan.11.2005, page 8 of 14 Timing Waveform Read Timing Waveform (WE# = VIH) tAA tACS1 tACS2 tCLZ2 tCLZ1 tBLZ tBA tOH t RC Valid data Address Dout Valid address High impedance CS1# CS2 LB#, UB# OE# *1, 2, 3 *1, 2, 3 *2, 3 *2, 3 *2, 3 *1, 2, 3 tOLZ*2, 3 *1, 2, 3 tOE tCHZ1 tCHZ2 tBHZ tOHZ
Rev.0.01, Jan.11.2005, page 9 of 14 Write Timing Waveform (1) (WE# Clock) Address WE# tWC tAW tWP*4 tWR*7 tCW*5 tCW*5 tBW tAS*6 tOW*2tWHZ*1, 2 tDW tDH Valid address Valid data CS1# LB#, UB# Dout Din High impedance CS2
Rev.0.01, Jan.11.2005, page 10 of 14 Write Timing Waveform (2) (CS# Clock, OE# = VIH) Address WE# tWC tAW tWP*4 tWR*7tCW*5 tCW*5 tBW tAS*6 tDW tDH Valid address Valid data LB#, UB# Dout Din High impedance CS2 CS1#
Rev.0.01, Jan.11.2005, page 11 of 14 Write Timing Waveform (3) (LB#, UB# Clock, OE# = VIH) Address WE# tWC tAW tWP*4 tCW*5 tCW*5 tBW tWR*7 tDW tDH Valid address Valid data LB#, UB# Dout Din High impedance CS2 CS1# tAS*6
Rev.0.01, Jan.11.2005, page 12 of 14 Low VCC Data Retention Characteristics (Ta = −40 to +85°C) Parameter Symbol Min Typ Max Unit Test conditions *3 VCC for data retention V DR 2.0 V Vin ≥ 0V (1) 0 V ≤ CS2 ≤ 0.2 V or (2) CS2 ≥ VCC − 0.2 V, CS1# ≥ VCC − 0.2 V or (3) LB# = UB# ≥ VCC − 0.2 V, CS2 ≥ VCC − 0.2 V, CS1# ≤ 0.2 V to +85°C I CCDR 10 µA to +70°C I CCDR 8 µA to +40°C I CCDR 0.7 *2 3 µA −5SI to +25°C I CCDR 0.5 *1 2.5 µA to +85°C I CCDR 20 µA to +70°C I CCDR 16 µA to +40°C I CCDR 0.7 *2 10 µA Data retention current −7LI to +25°C I CCDR 0.5 *1 10 µA VCC = 3.0 V, Vin ≥ 0V (1) 0 V ≤ CS2 ≤ 0.2 V or (2) CS2 ≥ VCC − 0.2 V, CS1# ≥ VCC − 0.2 V or (3) LB# = UB# ≥ VCC − 0.2 V, CS2 ≥ VCC − 0.2 V, CS1# ≤ 0.2 V Chip deselect to data retention time t CDR 0 ns See retention waveform Operation recovery time t R t RC*4 ns Notes: 1. Typical values are at V CC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed. 2. Typical values are at V CC = 3.0 V, Ta = +40°C and specified loading, and not guaranteed. 3. CS2 controls address buffer, WE# buffer, CS1# buffe r, OE# buffer, LB#, UB# buffer and Din buffer. If CS2 controls data retention mode, Vin levels (address, WE#, OE#, CS1#, LB#, UB#, I/O) can be in the high impedance state. If CS1# controls data retention mode, CS2 must be CS2 ≥ VCC − 0.2 V or 0 V ≤ CS2 ≤ 0.2 V. The other input levels (address, WE#, OE#, LB#, UB#, I/O) can be in the high impedance state. 4. t RC = read cycle time.
Rev.0.01, Jan.11.2005, page 13 of 14 Low VCC Data Retention Timing Waveform (1) (CS1# Controlled) (VCC = 2.2 V to 2.7 V) CCV 2.2 V 2.0 V 0 V CS1# tCDR tR CS1# V – 0.2 VCC≥ DRV Data retention mode Low VCC Data Retention Timing Waveform (2) (CS1# Controlled) (VCC = 2.7 V to 3.6 V) CCV 2.2 V 2.7 V 0 V CS1# tCDR tR CS1# V – 0.2 VCC≥ DRV Data retention mode Low VCC Data Retention Timing Waveform (3) (CS2 Controlled) (VCC = 2.2 V to 2.7 V) CCV 2.2 V 0.4 V 0 V CS2 CDR tR 0 V CS2 0.2 V DRV Data retention modet < < Low VCC Data Retention Timing Waveform (4) (CS2 Controlled) (VCC = 2.7 V to 3.6 V) CCV 2.7 V 0.6 V 0 V CS2 CDR tR 0 V CS2 0.2 V DRV Data retention modet < <
Rev.0.01, Jan.11.2005, page 14 of 14 Low VCC Data Retention Timing Waveform (5) (LB#, UB# Controlled) (VCC = 2.2 V to 2.7 V) CCV 2.2 V 2.0 V 0 V LB#, UB# tCDR tR LB#, UB# V – 0.2 VCC≥ DRV Data retention mode Low VCC Data Retention Timing Waveform (6) (LB#, UB# Controlled) (VCC = 2.7 V to 3.6 V) CCV 2.2 V 2.7 V 0 V LB#, UB# tCDR tR LB#, UB# V – 0.2 VCC≥ DRV Data retention mode
Revision History R1LV0416CBG-I Series Contents of Modification Rev. Date Page Description 0.01 Jan.11.2005 Initial issue
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