R1LV0408D RENESAS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 14
Technical content
Features
- Single 3 V supply: 2.7 V to 3.6 V
- Access tim e: 55/70 ns (max)
- Power dissipation: Standby: 3 µW (typ)
- Equal access and cycle times
- C ommon data input and output. Three state output
- Directly TTL compatible. All inputs and outputs
- B attery backup operation. Rev.1.00, May.24.2007, page 1 of 12
Ordering Information
Type No. Access time Package R1LV0408DSP-5S% 55 ns R1LV0408DSP-7L% 70 ns 525-mil 32-pin plastic SOP (32P2M-A) R1LV0408DSB-5S% 55 ns R1LV0408DSB-7L% 70 ns 400-mil 32-pin plastic TSOP II (32P3Y-H) R1LV0408DSA-5S% 55 ns R1LV0408DSA-7L% 70 ns 8mm × 13.4mm STSOP (32P3K-B) %: Temperature version; see table below. % Tem perature R ange R 0 to +70°C I −40 to +85°C Rev.1.00, May.24.2007, page 2 of 12
WE# A18 A15 V A17 A16 A14 A12 OE# A10 CS# I/O7 I/O6 I/O5 I/O4 I/O3 V I/O2 I/O1 I/O0 SS A18 A16 A14 A12 I/O0 I/O1 I/O2 VSS V A15 A17 WE# A13 A11 OE# A10 CS# I/O7 I/O6 I/O5 I/O4 I/O3 CC (Top view) 32-pin SOP 32-pin TSOP 32-pin STSOP (Top view) Pin Description Pin name Function A0 to A18 Address input I/O0 to I/O7 Data input/output CS# (CS) Chip select OE# (OE) Output enable WE# (WE) Write enable VCC Power supply VSS Ground Rev.1.00, May.24.2007, page 3 of 12
CS# WE# OE# A0 A1 A2 A3 A17A5 V V CC SS Row Decoder Memory Matrix 2,048 2,048 Column I/O Column DecoderInput Data Control Timing Pulse Generator Read/Write Control A4 A18 A10 A11 A12 A13 A14 A15 A16 LSB MSB LSB MSB Rev.1.00, May.24.2007, page 4 of 12
W E# C S# O E# M ode VCC current I/O0 to I/O7 Ref. cycle × H × Not selected ISB, ISB1 High-Z H L H Output disable ICC High-Z H L L Read ICC Dout Read cycle L L H Write ICC Din Write cycle (1) L L L Write ICC Din Write cycle (2) Note: H: VIH, L: VIL, ×: VIH or VIL Absolute Maximum Ratings Param eter Sym bol Value U nit Power supply voltage relative to VSS VCC −0.5 to +4.6 V Terminal voltage on any pin relative to VSS VT −0.5* to VCC + 0.5* V Power dissipation PT 0.7 W R ver. 0 to +70 Operating temperature Topr I ver. −40 to +85 Storage temperature range Tstg −65 to +150 °C R ver. 0 to +70 Storage temperature range under bias Tbias I ver. −40 to +85 Notes: 1. VT min: −3.0 V for pulse half-width ≤ 30 ns. 2. Maximum voltage is +4.6 V. DC Operating Conditions Param eter Sym bol M in Typ M ax U nit VCC 2.7 3.0 3.6 V Supply voltage VSS 0 0 0 V Input high voltage VIH 2.2 VCC + 0.3 V Input low voltage VIL −0.3* 0.6 V R ver. Ta 0 +70 Ambient temperature range I ver. −40 +85 Note: 1. VIL min: −3.0 V for pulse half-width ≤ 30 ns. Rev.1.00, May.24.2007, page 5 of 12
Param eter Sym bol M in Typ Max U nit Test conditions Input leakage current |ILI| 1 µA Vin = VSS to VCC Output leakage current |ILO| 1 µA CS# = VIH or OE# = VIH or WE# = VIL or VI/O = VSS to VCC Operating current ICC 10 mA CS# = VIL, Others = VIH/ VIL, II/O = 0 mA ICC1 25 mA Min. cycle, duty = 100%, CS# = VIL, Others = VIH/VIL II/O = 0 mA Average operating current ICC2 5 mA Cycle time = 1 µs, duty = 100%, II/O = 0 mA, CS# ≤ 0.2 V, VIH ≥ VCC − 0.2 V, VIL ≤ 0.2 V Standby current ISB 0.1* 0.3 mA CS# = VIH to +85°C ISB1 10 µA to +70°C ISB1 8 µA to +40°C ISB1 3 µA −5S% to +25°C ISB1 1* 2.5 µA to +85°C ISB1 20 µA to +70°C ISB1 16 µA to +40°C ISB1 10 µA Standby current −7L% to +25°C ISB1 1* 10 µA Vin ≥ 0 V, CS# ≥ VCC − 0.2 V Average values VOL 0.4 V IOL = 2.1 mA Output low voltage VOL2 0.2 V IOL = 100 µA VOH 2.4 V IOH = −1.0 mA Output high voltage VOH2 VCC − 0.2 V IOH = −0.1 mA Note: 1. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed. Capacitance (Ta = +25°C , f = 1.0 MH z) Param eter Sym bol M in Typ M ax U nit Test conditions Note Input capacitance Cin 8 pF Vin = 0 V 1 Input/output capacitance CI/O 10 pF VI/O = 0 V 1 Note: 1. This parameter is sampled and not 100% tested. Rev.1.00, May.24.2007, page 6 of 12
(Ta = 0 to +70°C / −40 to +85°C, VCC = 2.7 V to 3.6 V) Test Conditions
- Input pulse levels: VIL = 0.4 V, VIH = 2.4 V
- Input rise and fall time: 5 ns
- Input and output tim ing reference levels: 1.5 V
- Output load: 1 TTL Gate + CL (50 pF) (R1LV0408D-5S %)
1 TTL Gate + CL (100 pF) (R1LV0408D-7L%)
(Including scope and jig) Note: Temperature range depends on R/I-version. Please see table on page 2. Read Cycle R1LV0408D -5S% -7L% Param eter Sym bol M in M ax M in M ax U nit N otes Read cycle time tRC 55 70 ns Address access time tAA 55 70 ns Chip select access time tCO 55 70 ns Output enable to output valid tOE 30 35 ns Chip select to output in low-Z tLZ 10 10 ns 2 Output enable to output in low-Z tOLZ 5 5 ns 2 Chip deselect to output in high-Z tHZ 0 20 0 25 ns 1, 2 Output disable to output in high-Z tOHZ 0 20 0 25 ns 1, 2 Output hold from address change tOH 10 10 ns Rev.1.00, May.24.2007, page 7 of 12
-5S% -7L% Param eter Sym bol M in M ax M in M ax U nit N otes Write cycle time tWC 55 70 ns Chip selection to end of write tCW 50 60 ns 4 Address setup time tAS 0 0 ns 5 Address valid to end of write tAW 50 60 ns Write pulse width tWP 40 50 ns 3, 12 Write recovery time tWR 0 0 ns 6 Write to output in high-Z tWHZ 0 20 0 25 ns 1, 2, 7 Data to write time overlap tDW 25 30 ns Data hold from write time tDH 0 0 ns Output active from end of write tOW 5 5 ns 2 Output disable to output in high-Z tOHZ 0 20 0 25 ns 1, 2, 7 Notes: 1. tHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. A write occurs during the overlap (tWP) of a low CS# and a low WE#. A write begins at the later transition of CS# going low or WE# going low. A write ends at the earlier transition of CS# going high or WE# going high. tWP is measured from the beginning of write to the end of write. 4. tCW is measured from CS# going low to the end of write. 5. tAS is measured from the address valid to the beginning of write. 6. tWR is measured from the earlier of WE# or CS# going high to the end of write cycle. 7. During this period, I/O pins are in the output state so that the input signals of the opposite phase to the outputs must not be applied. 8. If the CS# low transition occurs simultaneously with the WE# low transition or after the WE# transition, the output remain in a high impedance state. 9. Dout is the same phase of the write data of this write cycle. 10. Dout is the read data of next address. 11. If CS# is low during this period, I/O pins are in the output state. Therefore, the input signals of the opposite phase to the outputs must not be applied to them. 12. In the write cycle with OE# low fixed, tWP must satisfy the following equation to avoid a problem of data bus contention. tWP ≥ tDW min + tWHZ max Rev.1.00, May.24.2007, page 8 of 12
Read T iming Waveform (WE# = VIH) tAA tCO tRC tLZ tOE tOLZ tHZ tOHZ Valid data Valid address High impedance Address CS# OE# Dout tOH Rev.1.00, May.24.2007, page 9 of 12
Write Timing Waveform (1) (OE# Clock) tWC tCW tWPtAS tOHZ tDW tDH tAW tWR Address OE# CS# WE# Dout Din Valid data Valid address High impedance Rev.1.00, May.24.2007, page 10 of 12
Write Timing Waveform (2) (OE# Low Fixed) Address CS# WE# Dout Din tWC tCW tWR tAW tWP tAS tWHZ tOW tOH tDW tDH *11 *9 *10 Valid data Valid address High impedance Rev.1.00, May.24.2007, page 11 of 12
Rev.1.00, May.24.2007, page 12 of 12 Low VCC Data Retention Characteristics (Ta = 0 to +70°C / −40 to +85°C) Param eter Sym bol Min Typ Max U nit Test conditions VCC for data retention VDR 2 V CS# ≥ VCC − 0.2 V, Vin ≥ 0 V to +85°C ICCDR 10 µA to +70°C ICCDR 8 µA to +40°C ICCDR 3 µA −5S% to +25°C ICCDR 1* 2.5 µA to +85°C ICCDR 20 µA to +70°C ICCDR 16 µA to +40°C ICCDR 10 µA Data retention current −7L% to +25°C ICCDR 1* 10 µA VCC = 3.0 V, Vin ≥ 0 V CS# ≥ VCC − 0.2 V Average values Chip deselect to data retention time tCDR 0 ns Operation recovery time tR 5 ms See retention waveform VCC 2.7 V 2.2 V 0 V CS# tCDR tR CS# ≥ VCC – 0.2 V VDR Data retention mode Note: 1. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed. Low VCC Data Retention Timing Waveform (CS# Controlled)
Revision History R1LV0408D Series Data Sheet Contents of Modification Rev. Date Page Description 0.01 Dec. 25, 2006 Initial issue 1.00 May. 24, 2007 6 DC Characteristics ISB1 (-5S%) (to +25°C) max: 3 µA to 2.5 µA Low VCC Data Retention Characteristics ICCDR (-5S%) (to +25°C) max: 3 µA to 2.5 µA Deletion of note 2
Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 RENESAS SALES OFFICES © 2007. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .7.0