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Technical content
Features
Single 2.7V~3.6V power supply Small stand-by current: 1µA (3.0V, typical) No clocks, No refresh All inputs and outputs are TTL compatible. Easy memory expansion by CS1# and CS2 Common Data I/O Three-state outputs: OR-tie Capability OE# prevents data contention on the I/O bus
Ordering Information
Orderable part name Access time Temperature range Package Shipping container R1LV0208BSA-5SI#B1 55 ns -40 ~ +85°C 8mm×13.4mm 32-pin plastic sTSOP Tray R1LV0208BSA-5SI#S1 Embossed tape R10DS0272EJ0100 Rev.1.00 2017.1.27
R10DS0272EJ0100 Rev.1.00 Page 2 of 11 2017.1.27 Pin Arrangement Pin Description Pin name Function Vcc Power supply Vss (GND) Ground A0 to A17 Address input DQ0 to DQ7 Data input/output CS1# Chip select 1 CS2 Chip select 2 WE# Write enable OE# Output enable A11 A13 WE# CS2 A15 Vcc A17 A16 A14 A12 OE# A10 CS1# DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 32-pin sTSOP
R10DS0272EJ0100 Rev.1.00 Page 3 of 11 2017.1.27 Block Diagram CS1# WE# OE# A17 DQ0 DQ1 DQ7 Vcc Vss COLUMN DECODER DQ BUFFER ADDRESS BUFFER ROW DECODER SENSE / WRITE AMPLIFIER CLOCK GENERATOR MEMORY ARRAY 256k-word x8-bit CS2
R10DS0272EJ0100 Rev.1.00 Page 4 of 11 2017.1.27 Operation Table CS1# CS2 WE# OE# DQ0~7 Operation X L X X High-Z Stand-by H X X X High-Z Stand-by L H L X Din Write L H H L Dout Read L H H H High-Z Output disable Note 1. H: V IH L : VIL X : VIH or VIL Absolute Maximum Parameter Symbol Value unit Power supply voltage relative to Vss Vcc -0.5 to +4.6 V Terminal voltage on any pin relative to Vss V T - 0 . 5 *1 to Vcc+0.5*2 V Power dissipation P T 0 . 7 W Operation temperature Topr -40 to +85 °C Storage temperature range Tstg -65 to 150 °C Storage temperature range under bias Tbias -40 to +85 °C Note 1. –3.0V for pulse ≤ 30ns (full width at half maximum) 2. Maximum voltage is +4.6V.
R10DS0272EJ0100 Rev.1.00 Page 5 of 11 2017.1.27 DC Operating Conditions Parameter Symbol Min. Typ. Max. Unit Note Supply voltage Vcc 2.7 3.0 3.6 V Vss 0 0 0 V Input high voltage V IH 2.0 - Vcc+0.3 V Input low voltage V IL -0.3 - 0.6 V 1 Ambient temperature range Ta -40 - +85 °C Note 1. –3.0V for pulse ≤ 30ns (full width at half maximum) DC Characteristics Parameter Symbol Min. Typ. Max. Unit Test conditions Input leakage current | I LI | - - 1 A Vin = Vss to Vcc Output leakage current | ILO | - - 1 A CS1# =VIH or CS2 =VIL or OE# =VIH, VI/O =Vss to Vcc Average operating current ICC1 - 1 5 2 5 m A Min. cycle, duty =100%, II/O = 0mA, CS1# =VIL, CS2 =VIH, Others = VIH/VIL ICC2 - 2 5 m A Cycle =1s, duty =100%, II/O = 0mA, CS1# ≤ 0.2V, CS2 ≥ Vcc-0.2V, VIH ≥ Vcc-0.2V, VIL ≤ 0.2V Standby current ISB - - 0 . 3 3 m A (1) CS1# =VIH, Others =VIH/VIL or (2) CS2 =VIL, Others =VIH/VIL Standby current ISB1 - 1 *1 2 A ~+25°C Vin = Vss to Vcc, (1) CS2 ≤ 0.2V or (2) CS1# ≥ Vcc-0.2V, C S 2 ≥ V c c - 0 . 2 V - - 3 A ~+40°C - - 8 A ~+70°C - - 10 A ~+85°C Output high voltage VOH 2.4 - - V I OH = -0.5mA VOH2 Vcc Output low voltage VOL - - 0.4 V I OL = 2mA Note 1. Typical parame ter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested. Capacitance (Vcc = 2.7V ~ 3.6V, f = 1MHz, Ta = -40 ~ +85°C) Parameter Symbol Min. Typ. Max. Unit Test conditions Note Input capacitance C in - - 8 pF Vin =0V 1 Input / output capacitance C I/O - - 1 0 p F V I/O =0V 1 Note 1. This parameter is sa mpled and not 100% tested.
R10DS0272EJ0100 Rev.1.00 Page 6 of 11 2017.1.27 AC Characteristics Test Conditions (Vcc = 2.7V ~ 3.6V, Ta = -40 ~ +85°C) Input pulse levels: VIL = 0.4V, VIH = 2.2V Input rise and fall time: 5ns Input and output timing reference level: 1.5V Output load: See figures (Including scope and jig) DQ 1.5V RL = 500 ohm CL = 30 pF
R10DS0272EJ0100 Rev.1.00 Page 7 of 11 2017.1.27 Read Cycle Parameter Symbol Min. Max. Unit Note Read cycle time t RC 5 5 - n s Address access time t AA - 5 5 n s Chip select access time tACS1 - 5 5 n s tACS2 - 5 5 n s Output enable to output valid t OE - 3 0 n s Output hold from address change t OH 1 0 - n s Chip select to output in low-Z tCLZ1 1 0 - n s 2 , 3 tCLZ2 1 0 - n s 2 , 3 Output enable to output in low-Z t OLZ 5 - ns 2,3 Chip deselect to output in high-Z tCHZ1 0 20 ns 1,2,3 tCHZ2 0 20 ns 1,2,3 Output disable to output in high-Z t OHZ 0 20 ns 1,2,3 Write Cycle Parameter Symbol Min. Max. Unit Note Write cycle time t WC 5 5 - n s Address valid to end of write t AW 5 0 - n s Chip select to end of write t CW 5 0 - n s 5 Write pulse width t WP 4 5 - n s 4 Address setup time t AS 0 - n s 6 Write recovery time t WR 0 - n s 7 Data to write time overlap t DW 2 5 - n s Data hold from write time t DH 0 - ns Output enable from end of write t OW 5 - n s 2 Output disable to output in high-Z t OHZ 0 2 0 n s 1 , 2 Write to output in high-Z t WHZ 0 2 0 n s 1 , 2 Note 1. t CHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is samp led and not 100% tested. 3. At any given temperature and voltage condition, t HZ max is less than t LZ min both for a given device and from device to device. 4. A write occurs during the ov erlap of a low CS1#, a high CS2, a low WE#. A write begins at the latest transition among CS1# going low, CS2 going high and WE# going low. A write ends at the earliest transition among CS1# going high, CS2 going low and WE# going high. tWP is measured from the beginning of write to the end of write. 5 . t CW is measured from the later of CS1# going low or CS2 going high to end of write. 6 . t AS is measured the address valid to the beginning of write. 7 . t WR is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle. 8. Don’t apply inverted phase si gnal externally when DQ pin is output mode.
R10DS0272EJ0100 Rev.1.00 Page 8 of 11 2017.1.27 Timing Waveforms Read Cycle tAA CS1# A0~17 tOH tCLZ1 tACS1 tOE tOLZ tCHZ1 OE# WE# DQ0~7 VIH tOHZ High impedance WE# = “H” level tRC Valid Data CS2 tCLZ2 tACS2 tCHZ2
R10DS0272EJ0100 Rev.1.00 Page 9 of 11 2017.1.27 Write Cycle (1) (WE# CLOCK) CS1# tCW tOW tWC DQ0~7 tDW t DH Valid Data tOHZ OE# WE# tAW tAS t WP t WR tWHZ tOLZ A0~17 CS2 tCW
R10DS0272EJ0100 Rev.1.00 Page 10 of 11 2017.1.27 Write Cycle (2) (CS1#, CS2 CLOCK) CS1# A0~17 tCW tWC tAW tAS t WR OE# WE# DQ0~7 VIH OE# = “H” level tDW t DH tWP Valid Data CS2 tCW t WR tAS
R10DS0272EJ0100 Rev.1.00 Page 11 of 11 2017.1.27 Low Vcc Data Retention Characteristics Parameter Symbol Min. Typ. Max. Unit Test conditions *2 VCC for data retention V DR 2.0 - 3.6 V Vin ≥ 0V, (1) 0V ≤ CS2 ≤ 0.2V or (2) CS1# ≥ Vcc-0.2V, CS2 ≥ Vcc-0.2V Data retention current I CCDR - 1 *1 2 A ~+25°C Vcc=3.0V, Vin ≥ 0V, (1) 0V ≤ CS2 ≤ 0.2V or (2) CS1# ≥ Vcc-0.2V, CS2 ≥ Vcc-0.2V - - 3 A ~+40°C - - 8 A ~+70°C - - 10 A ~+85°C Chip deselect time to data retention t CDR 0 - - n s See retention waveform. Operation recovery time t R 5 - - m s Note 1. Typical parame ter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested. 2. CS2 controls address buffer, WE# buffer, CS1# buffer, OE# b uffer and Din buffer. If CS2 controls data retention mode, Vin levels (address, WE#, CS1#, OE#, DQ) can be in the high impedance state. If CS1# controls data retention mode, CS2 must be CS2 ≥ Vcc-0.2 V or 0V ≤ CS2 ≤ 0.2V. The other input levels (address, WE# ,OE#, DQ) can be in the high impedance state. Low Vcc Data Retention Timing Waveforms CS1# Vcc (1) CS1# Controlled tCDR t R 2.7V 2.7V 2.2V 2.2V VDR CS1# ≥ Vcc - 0.2V CS2 Vcc (2) CS2 Controlled tCDR t R 2.7V 2.7V 0.2V 0.2V VDR 0V ≤ CS2 ≤ 0.2V
All trademarks and registered trademarks are the property of their respective owners. Revision History R1LV0208BSA Data Sheet Rev. Date
Description
1.00 2017.1.27 - First Edition issued
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