RAA788150_V01 RENESAS | Alldatasheet
Document overview
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- PDF pages: 33
Technical content
Datasheet sections
- 1.1 Typical Operating Circuit
- 2.1 Pin Assignments
- 2.2 Pin Descriptions
- 3.1 Absolute Maximum Ratings
- 3.2 Recommended Operating Conditions
- 3.3 Thermal Information
- 3.4 Electrical Specifications
- 6.1 Overview
- 6.2 Functional Block Diagram
- 6.3 Operating Modes
- 6.4 Device Features
- 7.1 Network Design
- 7.2 Transient Protection
- 7.3 Layout Guidelines
Features
▪ High VOD: 3.1V (Typ) into RD = 54Ω ▪ ±5kV EFT immunity of bus I/O pins ▪ ±16.5kV ESD protection on bus I/O pins ▪ Supported data rates: 115kbps, 1Mbps, 20Mbps ▪ Full fail-safe outputs for open or shorted inputs ▪ Hot plug capability ▪ 1/8 Unit Load ▪ Allows for up to 512 transceivers on the bus ▪ Low supply current (driver disabled): 550µA ▪ Ultra-low shutdown current: 70nA
Applications
▪ Industrial networks in factory automation ▪ Building automation: lighting, elevators, HVAC ▪ Industrial process control networks ▪ Security camera networks ▪ Networks with star topology ▪ Long-haul networks in coal mines and oil rigs ▪ High node-count networks ▪ Automated utility e-meter reading systems Figure 1. Typical Driver Output Performance of RAA78815xE Transceivers
1.1 Typical Operating Circuit
2.1 Pin Assignments
Figure 2. Typical Operating Circuits of Half-Duplex and Full-Duplex Transceivers
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2.2 Pin Descriptions
1 1 2 RO Receiver output: If A-B ≥ -50mV, RO is high; If A-B ≤ -200mV, RO is low. RO is fail-safe High if A and B are unconnected (open) or shorted. 2 2 3 RE Receiver output enable. RO is enabled when RE is low; RO is high impedance when RE is high. 3 3 4 DE Driver output enable. The driver outputs, Y and Z, are enabled by bringing DE high. They are high impedance when DE is low. 4 4 5 DI Driver input. A low on DI forces output Y low and output Z high. Similarly, a high on DI forces output Y high and output Z low. 5 5 6, 7 GND Ground connection. 6 – – A/Y Non-inverting receiver input and non-inverting driver output. Pin is an input if DE = 0; pin is an output if DE = 1. 7 – – B/Z Inverting receiver input and inverting driver output. Pin is an input if DE = 0; pin is an output if DE = 1. – 6 9 Y Non-inverting driver output. – 7 10 Z Inverting driver output. – 8 11 B Inverting receiver input. – 9 12 A Non-inverting receiver input. 8 10 – VCC System power supply input (4.5V to 5.5V). – – 1, 8, 13 NC No connection.
R15DS0005EU0103 Rev.1.03 Page 5 Oct 2, 2023 RAA788150, RAA788152, RAA788153, RAA788155, RAA788156, RAA788158 Datasheet 3. Specifications
3.1 Absolute Maximum Ratings
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product reliability and result in failures not covered by warranty.
3.2 Recommended Op erating Conditions
3.3 Thermal Information
Parameter[1] 1. Absolute Maximum ratings mean the device is not damaged if operated under these conditions. It does not guarantee performance. Minimum Maximum Unit VCC to Ground -7 V Input Voltages at DI, DE, RE -0.3 V CC + 0.3 V Bus I/O Voltages at A/Y, B/Z, A, B, Y, Z -9 13 V Transient Pulse Voltages through 100Ω at A/Y, B/Z, A, B, Y, Z[2] 2. Tested according to TIA/EIA-485-A, Section 4.2.6 (±100V for 15µs at a 1% duty cycle). -± 1 0 0 V RO -0.3 V CC + 0.3 V Short-Circuit Duration at Y, Z Continuous EFT Rating See EFT Performance. ESD Rating See ESD Performance. Parameter Minimum Maximum Unit Supply Voltage 4.5 5.5 V Temperature Range -40 +85 °C Bus Pin Common-Mode Voltage Range -7 +12 V Thermal Resistance (Typical) θ JA (°C/W)[1] 1. θJA is measured with the component mounted on a high-effective thermal conductivity test board in free air. See TB379 for details.
8 Ld SOIC 105
8 Ld MSOP 140
10 Ld MSOP 130
14 Ld SOIC 130
Parameter Minimum Maximum Unit Maximum Junction Temperature (Plastic Package) - +150 °C Maximum Storage Temperature Range -65 +150 °C Pb-Free Reflow Profile [1] 1. Pb-free PDIPs can be used for through-hole wa ve solder processing only. They are not intended for use in Reflow solder processing applications. See TB493
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3.4 Electrical Specifications
Test Conditions: VCC = 4.5V to 5.5V; unless otherwise specified. Typical values are at VCC = 5V, TA = +25°C[1]. Parameter Symbol Test Conditions Temp (°C) Min [2] Typ Max [2] Unit DC Characteristics Driver Differential Output Voltage (No load) VOD1 Full - - V CC V Driver Differential Output Voltage (Loaded) VOD2 RL = 100Ω (RS-422) (Figure 3)F u l l 2 . 8 3 . 6 - V RL = 54Ω (RS-485) (Figure 3)F u l l 2 . 43 . 1 V CC V RL = 15Ω (Eight 120Ω terminations)[3] +25 - 1.65 - V RL = 60Ω, -7V ≤ VCM ≤ 12V (Figure 4) Full 2.4 3 - V Change in Magnitude of Driver Differential Output Voltage ΔVOD RL = 54Ω or 100Ω (Figure 3) Full - 0.01 0.2 V Driver Common-Mode Output Voltage VOC RL = 54Ω or 100Ω (Figure 3)F u l l - - 3 . 1 5 V Change in Magnitude of Driver Common-Mode Output Voltage ΔV OC RL = 54Ω or 100Ω (Figure 3) Full - 0.01 0.2 V Logic Input High Voltage V IH DE, DI, RE Full 2 - - V Logic Input Low Voltage V IL DE, DI, RE Full - - 0.8 V DI Input Hysteresis Voltage V HYS +25 - 100 - mV Logic Input Current I IN1 DE, DI, RE Full -2 - 2 µA Input Current (A, B, A/Y , B/Z) IIN2 DE = 0V, VCC = 0V or 5.5V VIN = 12V Full - 70 125 µA VIN = -7V Full -75 55 - µA Output Leakage Current (Y , Z) (Full Duplex Versions Only) IIN3 RE = 0V, DE = 0V, VCC =0 V or 5.5V VIN = 12V Full - 1 40 µA VIN = -7V Full -40 -9 - µA Output Leakage Current (Y, Z) in Shutdown Mode (Full Duplex) I IN4 RE = VCC, DE = 0V, VCC = 0V or 5.5V VIN = 12V Full - 1 20 µA VIN = -7V Full -20 -9 - µA Driver Short-Circuit Current, VO = High or Low IOSD1 DE = VCC, -7V ≤ VY or VZ ≤ 12V[4] Full - - ±250 mA Receiver Differential Threshold Voltage VTH -7V ≤ VCM ≤ 12V Full -200 -90 -50 mV Receiver Input Hysteresis ΔVTH VCM = 0V +25 - 20 - mV Receiver Output High Voltage VOH IO = -8mA, VID = -50mV Full V CC - 1.2 4.3 - V Receiver Output Low Voltage VOL IO = -8mA, VID = -200mV Full - 0.25 0.4 V Receiver Output Low Current IOL VO = 1V, VID = -200mV Full 20 28 - mA
R15DS0005EU0103 Rev.1.03 Page 7 Oct 2, 2023 RAA788150, RAA788152, RAA788153, RAA788155, RAA788156, RAA788158 Datasheet Three-State (High Impedance) Receiver Output Current I OZR 0.4V ≤ VO ≤ 2.4V Full -1 0.03 1 µA Receiver Input Resistance R IN -7V ≤ VCM ≤ 12V Full 96 160 - k Ω Receiver Short-Circuit Current IOSR 0V ≤ VO ≤ VCC Full ±7 65 ±85 mA Supply Current No-Load Supply Current[5] ICC Half duplex versions, DE = VCC, RE = X, DI = 0V or VCC Full - 650 800 µA All versions, DE = 0V, RE = 0V, or full duplex versions, DE = VCC, RE = X. DI = 0V or VCC Full - 550 700 µA Shutdown Supply Current I SHDN DE = 0V, RE = VCC, DI = 0V or VCC Full - 0.07 3 µA EFT Performance RS-485 Pins (A, Y, B, Z, A/Y, B/Z) IEC61000-4-4, Electrical Fast Transient Immunity 5kHz +25 ±5 kV 100kHz +25 ±5 kV ESD Performance RS-485 Pins (A, Y, B, Z, A/Y, B/Z) IEC61000-4-2, Air-Gap Discharge Method Half duplex +25 - ±16.5 - kV Full duplex +25 - ±10 - kV IEC61000-4-2, Contact Discharge Method +25 - ±9 - kV Human Body Model, from bus pins to GND +25 - ±16.5 - kV All Pins Human Body Model, per MIL-STD-883 Method 3015 +25 - ±7 - kV Charged Device Model per JS-002-2014 +25 - 1250 - V Machine Model per JESD22-A115C +25 - 400 - V Driver Switching Characteristics (115kbps Versions; RAA788150, RAA788152) Driver Differential Output Delay t PLH, tPHL RDIFF = 54Ω, CL = 100pF (Figure 5) Full 500 970 1300 ns Driver Differential Output Skew tSKEW RDIFF = 54Ω, CL = 100pF (Figure 5) Full - 12 50 ns Driver Differential Rise or Fall Time tR, tF RDIFF = 54Ω, CL = 100pF (Figure 5) Full 700 1100 1600 ns Maximum Data Rate f MAX CD = 820pF[6] (Figure 7) Full 115.2 2000 - kbps Driver Enable to Output High tZH RL = 500Ω, CL = 100pF, SW = GND[7] (Figure 6) Full - 300 600 ns Test Conditions: VCC = 4.5V to 5.5V; unless otherwise specified. Typical values are at VCC = 5V, TA = +25°C[1]. Parameter Symbol Test Conditions Temp (°C) Min [2] Typ Max [2] Unit
R15DS0005EU0103 Rev.1.03 Page 8 Oct 2, 2023 RAA788150, RAA788152, RAA788153, RAA788155, RAA788156, RAA788158 Datasheet Driver Enable to Output Low t ZL RL = 500Ω, CL = 100pF, SW = VCC[7] (Figure 6) Full - 130 500 ns Driver Disable from Output Low tLZ RL = 500Ω, CL = 15pF, SW = VCC (Figure 6) Full - 50 65 ns Driver Disable from Output High tHZ RL = 500Ω, CL = 15pF, SW = GND (Figure 6) Full - 35 60 ns Time to Shutdown t SHDN [8] Full 60 160 600 ns Driver Enable from Shutdown to Output High tZH(SHDN) RL = 500Ω, CL = 100pF, SW = GND[8][9] (Figure 6) Full - - 250 ns Driver Enable from Shutdown to Output Low tZL(SHDN) RL = 500Ω, CL = 100pF, SW = VCC[8][9] (Figure 6) Full - - 250 ns Driver Switching Characteristics (1Mbps Versions; RAA788153, RAA788155) Driver Differential Output Delay tPLH, tPHL RDIFF = 54Ω, CL = 100pF (Figure 5) Full 150 270 400 ns Driver Differential Output Skew tSKEW RDIFF = 54Ω, CL = 100pF (Figure 5) Full - 3 10 ns Driver Differential Rise or Fall Time tR, tF RDIFF = 54Ω, CL = 100pF (Figure 5) Full 150 325 450 ns Maximum Data Rate f MAX CD = 820pF[6] (Figure 7) Full 1 8 - Mbps Driver Enable to Output High tZH RL = 500Ω, CL = 100pF, SW = GND[7] (Figure 6) Full - 110 200 ns Driver Enable to Output Low t ZL RL = 500Ω, CL = 100pF, SW = VCC[7] (Figure 6) Full - 60 200 ns Driver Disable from Output Low tLZ RL = 500Ω, CL = 15pF, SW = VCC (Figure 6) Full - 50 65 ns Driver Disable from Output High tHZ RL = 500Ω, CL = 15pF, SW = GND (Figure 6) Full - 35 60 ns Time to Shutdown[8] tSHDN Full 60 160 600 ns Driver Enable from Shutdown to Output High tZH(SHDN) RL = 500Ω, CL = 100pF, SW = GND [8][9] (Figure 6) Full - - 250 ns Driver Enable from Shutdown to Output Low tZL(SHDN) RL = 500Ω, CL = 100pF, SW = VCC[8][9] (Figure 6) Full - - 250 ns Driver Switching Characteristics (20Mbps Versions; RAA788156, RAA788158) Driver Differential Output Delay tPLH, tPHL RDIFF = 54Ω, CL = 100pF (Figure 5) Full - 21 30 ns Driver Differential Output Skew tSKEW RDIFF = 54Ω, CL = 100pF (Figure 5) Full - 0.2 3 ns Driver Differential Rise or Fall Time tR, tF RDIFF = 54Ω, CL = 100pF (Figure 5) Full - 12 16 ns Maximum Data Rate f MAX CD = 470pF[6] (Figure 7) Full 20 55 - Mbps Driver Enable to Output High tZH RL = 500Ω, CL = 100pF, SW = GND[7] (Figure 6) Full - 30 45 ns Test Conditions: VCC = 4.5V to 5.5V; unless otherwise specified. Typical values are at VCC = 5V, TA = +25°C[1]. Parameter Symbol Test Conditions Temp (°C) Min [2] Typ Max [2] Unit
R15DS0005EU0103 Rev.1.03 Page 9 Oct 2, 2023 RAA788150, RAA788152, RAA788153, RAA788155, RAA788156, RAA788158 Datasheet Driver Enable to Output Low t ZL RL = 500Ω, CL = 100pF, SW = VCC[7] (Figure 6) Full - 28 45 ns Driver Disable from Output Low tLZ RL = 500Ω, CL = 15pF, SW = VCC (Figure 6) Full - 50 65 ns Driver Disable from Output High tHZ RL = 500Ω, CL = 15pF, SW = GND (Figure 6) Full - 38 60 ns Time to Shutdown[8] tSHDN Full 60 160 600 ns Driver Enable from Shutdown to Output High tZH(SHDN) RL = 500Ω, CL = 100pF, SW = GND[8][9] (Figure 6) Full - - 200 ns Driver Enable from Shutdown to Output Low tZL(SHDN) RL = 500Ω, CL = 100pF, SW = VCC[8][9] (Figure 6) Full - - 200 ns Receiver Switching Characteristics (115kbps and 1Mbps Versions; RAA788150 through RAA788155) Maximum Data Rate[6] fMAX (Figure 8) Full 1 12 - Mbps Receiver Input to Output Delay tPLH, tPHL (Figure 8) Full - 100 150 ns Receiver Skew | tPLH - tPHL |t SKD (Figure 8)F u l l - 4 1 0 n s Receiver Enable to Output Low tZL RL = 1kΩ, CL = 15pF, SW = VCC[10] (Figure 9) Full - 9 20 ns Receiver Enable to Output High tZH RL = 1kΩ, CL = 15pF, SW = GND[10] (Figure 9) Full - 7 20 ns Receiver Disable from Output Low tLZ RL = 1kΩ, CL = 15pF, SW = VCC (Figure 9) Full - 8 15 ns Receiver Disable from Output High tHZ RL = 1kΩ, CL = 15pF, SW = GND (Figure 9) Full - 8 15 ns Time to Shutdown[8] tSHDN Full 60 160 600 ns Receiver Enable from Shutdown to Output High tZH(SHDN) RL = 1kΩ, CL = 15pF, SW = GND (Figure 9)[8][11] Full - - 200 ns Receiver Enable from Shutdown to Output Low tZL(SHDN) RL = 1kΩ, CL = 15pF, SW = VCC (Figure 9)[8][11] Full - - 200 ns Receiver Switching Characteristics (20Mbps Versions; RAA788156, RAA788158) Maximum Data Rate[6] fMAX (Figure 8) Full 20 30 - Mbps Receiver Input to Output Delay tPLH, tPHL (Figure 8) Full - 33 45 ns Receiver Skew | tPLH - tPHL |t SKD (Figure 8) Full - 2.5 5 ns Receiver Enable to Output Low tZL RL = 1kΩ, CL = 15pF, SW = VCC[10] (Figure 9) Full - 8 15 ns Receiver Enable to Output High tZH RL = 1kΩ, CL = 15pF, SW = GND[10] (Figure 9) Full - 7 15 ns Receiver Disable from Output Low tLZ RL = 1kΩ, CL = 15pF, SW = VCC (Figure 9) Full - 8 15 ns Receiver Disable from Output High tHZ RL = 1kΩ, CL = 15pF, SW = GND (Figure 9) Full - 8 15 ns Test Conditions: VCC = 4.5V to 5.5V; unless otherwise specified. Typical values are at VCC = 5V, TA = +25°C[1]. Parameter Symbol Test Conditions Temp (°C) Min [2] Typ Max [2] Unit
R15DS0005EU0103 Rev.1.03 Page 10 Oct 2, 2023 RAA788150, RAA788152, RAA788153, RAA788155, RAA788156, RAA788158 Datasheet Time to Shutdown[8] tSHDN Full 60 160 600 ns Receiver Enable from Shutdown to Output High tZH(SHDN) RL = 1kΩ, CL = 15pF, SW = GND[8][11] (Figure 9) Full - - 200 ns Receiver Enable from Shutdown to Output Low tZL(SHDN) RL = 1kΩ, CL = 15pF, SW = VCC[8][11] (Figure 9) Full - - 200 ns 1. All currents in to device pins are posit ive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. 2. Parameters with MIN and/or MAX limits are 100% tested at +25° C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 3. See Figure 11 for more information and for performance over temperature. 4. Applies to peak current. See Typical Performance Curves for more information. 5. Supply current specification is va lid for loaded drivers when DE = 0V. 6. Limits established by characterization and are not production tested. 7. Keep RE = 0 to prevent the device from entering SHDN. 8. Transceivers are put into shutdown by bringing RE high and DE low. If the inputs are in this state for less than 60ns, the parts are ensured not to enter shutdown. If the inputs are in this state for at least 600ns, the parts are ensured to have entered shutdown. See Low Current Shutdown Mode. 9. Keep RE = VCC, and set the DE signal low time >600ns to ensure that the device enters SHDN. 10. The RE signal high time must be short enough (typically <100ns) to prevent the device from entering SHDN. 11. Set the RE signal high time >600ns to ensure that the device enters SHDN. Test Conditions: VCC = 4.5V to 5.5V; unless otherwise specified. Typical values are at VCC = 5V, TA = +25°C[1]. Parameter Symbol Test Conditions Temp (°C) Min [2] Typ Max [2] Unit
Figure 9. Measurement of Receiver Enable and Disable Times
6.1 Overview
suitable for data transmission up to 115kbps, 1Mbps, and 20Mbps. as low as 70nA can be accomplished by disabling both the driver and receiver for more than 600ns.
6.2 Functional Block Diagram
6.3 Operating Modes
6.3.1 Driver Operation
follow the logic states at the data input, DI. through a 1kΩ to 10kΩ pull-down resistor to ground. Figure 22. Block Diagram Figure 23. Block Diagram Table 1. Driver Truth Table Note: See Shutdown mode explanation in Low Current Shutdown Mode.
6.3.2 Receiver Operation
voltage at the differential receiver inputs, A and B. Here, the bus voltage is defined as VAB = VA - VB. -200mV, the state of RO is undetermined; therefore, it could be high or low. recommended to connect RO, using a 1kΩ to 10kΩ pull-up resistor to VCC. 10kΩ pull-down resistor to ground.
6.4 Device Features
6.4.1 Large Output Signal Swing
shows that the VOD at 54Ω is more than 50% higher than that of a standard transceiver. Table 2. Receiver Truth Table Note: See Shutdown mode explanation in Low Current Shutdown Mode. Figure 24. V-I Characteristic of RAA78815x vs Standard Figure 25. Unit Load and Transceiver Drive of
R15DS0005EU0103 Rev.1.03 Page 18 Oct 2, 2023 RAA788150, RAA788152, RAA788153, RAA788155, RAA788156, RAA788158 Datasheet Figure 25 compares the maximum number of unit loads and bus transceivers when choosing an RAA78815x over a standard transceiver. The RS-485 standard specifies a minimum total common-mode load resistance of RCM =3 7 5Ω between each signal conductor and ground. Because one unit load (1UL) is equivalent to 12kΩ, the total common-mode resistance of 375Ω yields 12kΩ/375Ω = 32ULs. For an RAA78815x transceiver however, RCM can be as small as 188Ω, resulting in a total common-mode load of 12kΩ/188Ω = 64ULs. This means the driver of an RAA78815x transceiver can drive up to 64 x 1UL transceivers or 512 x 1/8UL transceivers. The advantages of such superior drive capability are as follows: ▪ Up to 900mV higher noise immunity (2.4V vs 1.5V VOD) ▪ Up to twice the maximum cable length of standard transceivers (~8000ft vs 4000ft) ▪ The design of star configurations or other multi-terminated nonstandard network topologies
6.4.2 Driver Overload Protection
The RS-485 specification requires drivers to survive worst case bus contentions undamaged. The RAA78815x transceivers meet this requirement through driver output short-circuit current limits and on-chip thermal shutdown circuitry. The driver output stages incorporate short-circuit current limiters that ensure that the output current never exceeds the RS-485 specification, even at the common-mode voltage range extremes. In the event of a major short-circuit conditions, the devices also include a thermal shutdown feature that disables the drivers whenever the temperature becomes excessive. This eliminates the power dissipation, allowing the die to cool. The drivers automatically re-enable after the die temperature drops about 15°C. If the contention persists, the thermal shutdown/re-enable cycle repeats until the fault is cleared. The receivers stay operational during thermal shutdown.
6.4.3 Full-Failsafe Receiver
The differential receivers of the RAA78815x family are full-failsafe, meaning their outputs turn logic high when: ▪ The receiver inputs are open (floating) because of a faulty bus node connector ▪ The receiver inputs are shorted because of an insulation break of the bus cable ▪ The receiver input voltage is close to 0V because of a terminated bus not being actively driven Full-failsafe switching is accomplished by offsetting the maximum receiver input threshold to -50mV. Figure 26 shows that, in addition to the threshold offset, the receiver also has an input hysteresis, ΔVTH, of 20mV. The combination of offset and hysteresis allows the receiver to maintain its output high, even in the presence of 140mVP-P differential noise, without the need for external failsafe biasing resistors.
6.4.4 Low Current Shutdown Mode
footnotes, [1] to [11], in the Electrical Specifications.
6.4.5 Hot Plug Function
released. This gives the controller the chance to stabilize and drive the RS-485 enable lines to the proper states.
6.4.6 High EFT Immunity
coupled onto RS-485 data lines using a capacitive clamp (Figure 27). Figure 26. Full-Failsafe Performance with High Noise Immunity Figure 27. Test Setup with Capacitive Clamp Figure 28. EFT Test Timing
have been tested with both repetition frequencies, 5kHz and 100kHz. performance. The ATE pass criterion requires that a device shows no parametric shift at all. IEC61000-4-4 standard (Table 3, Test Level X).
6.4.7 High ESD Protection
in the test severity, as both standards aim for different application environments. connector pins when plugging or unplugging cables. Table 3. EFT Test Level Category for RAA78815x Transceivers Figure 29. Generator Models for HBM and IEC ESD Tests Figure 30. Difference in Rise-time and Charge Currents
7.1 Network Design
distance between network nodes, and line termination. which can be half-duplex or full-duplex (Figure 31 and Figure 32). should match the characteristic cable impedance, Z0. driver outputs of the slave nodes with the receiver input of the master node. bus cable lengths of a few hundred feet to maintain signal integrity. discussion applies to both half-and full-duplex network designs.
7.1.1 Cable Type
signals, which are effectively rejected by the differential receivers. Figure 31. Half-Duplex Bus Figure 32. Full-Duplex Bus
7.1.2 Cable Length vs Data Rate
cover almost twice the distance of standard compliant RS-485 transceivers.
7.1.3 Topologies and Stub Lengths
the actual electrical link between transceiver and cable trunk. Figure 33. Single Pair STP Cable for RS-485 Applications Figure 34. Data Rate vs Cable Length Guidelines in Feet and Meters
22 AWG
Figure 35. Stub Lengths in Daisy Chain (left) and Backbone (right) Topologies lengths associated with the corresponding transceivers, as shown in Table 4. lengths and low radiated emission in the presence of increased stub inductance.
7.1.4 Minimum Distance between Nodes
anywhere on the bus, requires the bus impedance at the mismatches to be or 0.4 x 120 Ω =4 8Ω. Table 4. Stub Length as Function of Driver Rise Time
▪ CC is the distributed cable or PCB trace capacitance per unit length. transceiver, known as the stub, is electrically short. depending on their construction. 11pF/ft for low capacitance, unshielded, twisted-pair cable up to 22pF/ft for backplanes.
7.1.5 Failsafe Biasing Termination
to 140mVP-P of differential noise on a passive bus without needing external failsafe biasing. terminated with the cable characteristic impedance Z0 (Figure 37, left circuit). Figure 36. Minimum Distance between Bus Nodes as Function of Cable and Load Capacitance
For more details on failsafe biasing, see TB509.
7.2 Transient Protection
external transient protection. device satisfying this requirement is the 400W TVS, SM712. resistors (RS) are used to prevent the two protection schemes from interacting with one another. value should be equal to or less than 20Ω to minimize the attenuation of the bus voltage during normal operation. Figure 39 shows the schematic of a 1kV surge protection example for the RAA788152 and its bill of materials. Figure 39. IEC61000-4-5 Level 2 (1kV) Surge Protection and Associated Bill of Materials
7.3 Layout Guidelines
high-frequency layout techniques must be applied during PCB design.
- For your PCB design to be successful, start with the design of the protection circuit in mind.
- Place the protection circui try close to the bus connector to prevent noise transients from penetrating your
- Use VCC and ground planes to provide low-inductance. High-frequency currents follow the path of least
inductance and not the path of least impedance.
- Design the protection components into the direction of the signal path. Do not force the transient currents to
divert from the signal path to reach the protection device.
- Apply 100nF to 220nF bypass capacitors as close as po ssible to the VCC pins of the transceiver, UART, and
controller ICs on the board.
- Use at least two vias for VCC and ground connections of bypass capacitors and protection devices to minimize
the effective via-inductance.
- Use 1k Ω to 10kΩ pull-up/down resistors for the transceiver enable lines to limit noise currents into these lines
- Insert pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified
transceiver and prevent it from latching up.
7.3.1 Layout Example
Figure 40. RAA788152 Layout Example
R15DS0005EU0103 Rev.1.03 Page 28 Oct 2, 2023 RAA788150, RAA788152, RAA788153, RAA788155, RAA788156, RAA788158 Datasheet 8. Package Outline Drawings For the most recent package outline drawing, see M8.15. M8.15
8 Lead Narrow Body Small Outline Plastic Package
Rev 7, 9/2023
R15DS0005EU0103 Rev.1.03 Page 29 Oct 2, 2023 RAA788150, RAA788152, RAA788153, RAA788155, RAA788156, RAA788158 Datasheet For the most recent package outline drawing, see M8.118. M8.118
8 Lead Mini Small Outline Plastic Package
Rev 5, 5/2021 DETAIL "X" SIDE VIEW 2 TYPICAL RECOMMENDED LAND PATTERN TOP VIEW PIN# 1 ID 0.25 - 0.36 DETAIL "X" 0.10 ± 0.05 (4.40) (3.00) (5.80) H C
1.10 MAX
0.09 - 0.20 3°±3° GAUGE PLANE 0.25
0.95 REF
0.55 ± 0.15 B
0.08 C A-B D
3.0±0.05 0.85±010 SEATING PLANE A
0.65 BSC
3.0±0.05 4.9±0.15 (0.40) (1.40) (0.65) D SIDE VIEW 1 Dimensioning and tolerancing conform to JEDEC MO-187-AA Plastic interlead protrusions of 0.15mm max per side are not Dimensions in ( ) are for reference only. Dimensions are measured at Datum Plane "H". Plastic or metal protrusions of 0.15mm max per side are not Dimensions are in millimeters. NOTES: and AMSEY14.5m-1994. included. included. 0.10 CM
R15DS0005EU0103 Rev.1.03 Page 30 Oct 2, 2023 RAA788150, RAA788152, RAA788153, RAA788155, RAA788156, RAA788158 Datasheet For the most recent package outline drawing, see M10.118. M10.118
10 Lead Mini Small Outline Plastic Package
Rev 2, 5/2021 DETAIL "X" SIDE VIEW 2 TYPICAL RECOMMENDED LAND PATTERN TOP VIEW PIN# 1 ID 0.18 - 0.27 DETAIL "X" 0.10 ± 0.05 (4.40) (3.00) (5.80) H C 0.09 - 0.20 3°±3° GAUGE PLANE 0.25 0.55 ± 0.15 B 3.0±0.05 0.85±010 SEATING PLANE A
0.50 BSC
3.0±0.05 4.9±0.15 (0.29) (1.40) (0.50) D SIDE VIEW 1 Dimensioning and tolerancing conform to JEDEC MO-187-BA Plastic interlead protrusions of 0.15mm max per side are not Dimensions in ( ) are for reference only. Dimensions are measured at Datum Plane "H". Plastic or metal protrusions of 0.15mm max per side are not Dimensions are in millimeters. NOTES: and AMSEY14.5m-1994. included. included. 0.10 CM
R15DS0005EU0103 Rev.1.03 Page 31 Oct 2, 2023 RAA788150, RAA788152, RAA788153, RAA788155, RAA788156, RAA788158 Datasheet For the most recent package outline drawing, see M14.15. M14.15
14 Lead Narrow Body Small Outline Plastic Package
Rev 2, 6/20 A D
0.25 A-BMC
C 0.10 C 5 B D
0.10 A-BC
0.20 C 2X
0.10 DC 2X
H 0.10 C 3 6 ID MARK PIN NO.1 (0.35) x 45° SEATING PLANE GAUGE PLANE 0.25 (5.40) (1.50) 1.27 0.31-0.51 4° ± 4° DETAIL"A" 0.22±0.03 0.10-0.25
1.25 MIN
1.75 MAX
(1.27) (0.6) 6.0 8.65 3.9 14 8 Dimensioning and tolerancing conform to AMSEY14.5m-1994. Dimension does not include interlead flash or protrusions. Dimensions in ( ) for Reference Only. Interlead flash or protrusions shall not exceed 0.25mm per side. Datums A and B to be determined at Datum H. Dimensions are in millimeters. NOTES: The pin #1 indentifier may be either a mold or mark feature. 6. Does not include dambar protrusion. Allowable dambar protrusion 7. Reference to JEDEC MS-012-AB. shall be 0.10mm total in excess of lead width at maximum condition. DETAIL "A"SIDE VIEW TYPICAL RECOMMENDED LAND PATTERN TOP VIEW
R15DS0005EU0103 Rev.1.03 Page 32 Oct 2, 2023 RAA788150, RAA788152, RAA788153, RAA788155, RAA788156, RAA788158 Datasheet 9. Ordering Information Part Number[1][2] 1. These Pb-free plastic packaged products em ploy special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. For Moisture Sensitivity Level (M SL), see the Product Options on the RAA788150, RAA788152, RAA788153, RAA788155, RAA788156, and RAA788158 product pages (click the packaging icon). For more information about MSL, see TB363. Part Marking Package Description (RoHS Compliant) Pkg. Dwg. # Carrier Type (Units)[3] 3. See TB347 for details about reel specifications. Temp. Range RAA7881502GSP#AB0 RAA788 1502GSP 14 Ld SOIC M14.15 Tube -40 to +85°C RAA7881502GSP#HB0 Reel, 2.5k RAA7881502GSU#AB0 81502 10 Ld MSOP M10.118 Tube RAA7881502GSU#HB0 Reel, 2.5k RAA7881522GSP#AB0 7881522 8 Ld SOIC M8.15 Tube RAA7881522GSP#HB0 Reel, 2.5k RAA7881522GSU#AB0 81522 8 Ld MSOP M8.118 Tube RAA7881522GSU#HB0 Reel, 2.5k RAA7881532GSP#AB0 RAA788 1532GSP 14 Ld SOIC M14.15 Tube RAA7881532GSP#HB0 Reel, 2.5k RAA7881532GSU#AB0 81532 10 Ld MSOP M10.118 Tube RAA7881532GSU#HB0 Reel, 2.5k RAA7881552GSP#AB0 7881552 8 Ld SOIC M8.15 Tube RAA7881552GSP#HB0 Reel, 2.5k RAA7881552GSU#AB0 81552 8 Ld MSOP M8.118 Tube RAA7881552GSU#HB0 Reel, 2.5k RAA7881562GSP#AB0 RAA788 1562GSP 14 Ld SOIC M14.15 Tube RAA7881562GSP#HB0 Reel, 2.5k RAA7881562GSU#AB0 81562 10 Ld MSOP M10.118 Tube RAA7881562GSU#HB0 Reel, 2.5k RAA7881582GSP#AB0 7881582 8 Ld SOIC M8.15 Tube RAA7881582GSP#HB0 Reel, 2.5k RAA7881582GSU#AB0 81582 8 Ld MSOP M8.118 Tube RAA7881582GSU#HB0 Reel, 2.5k
Table 5. Key Differences of Device Features 1.03 Oct 2, 2023 Updated M8.15 POD to the latest revision (corrected typo). Updated Ordering Information table. Updated Note 2 in the ordering information table. 1.00 Jun 15, 2021 Initial release.