QW0040AB/PSC-5138-01

Renesas Technology Corp

8 Channel System PMIC supporting DDR VTT Mar 25, 2025

Manufacturer: Renesas Technology Corp

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DA9281 RENESAS | Alldatasheet

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8 Channel System PMIC supporting DDR VTT

R16DS0528EJ0301 Rev. 3.01 Mar 25, 2025 CFR0011-120-00 Page 1 © 2025 Renesas Electronics DA9281 is an 8-channel power management integrated circuit (PMIC) with 4 buck regulators, 3 LDOs and 1 voltage buffer to support DDR VTT termination. Key functions for power applications, such as soft- start, selectable preset output voltage, flexible power-up and power-down sequences are provided on chip and are programmable via the I2C interface with non-volatile memory defaults. All 8 channels have an output discharge function and protections features such as over-current protection (OCP), over voltage protection (OVP), and under voltage protection (UVP). Key Features ▪ 4.5 V to 5.5 V input voltage ▪ BUCK (CH1 to CH4)

Output current 5.0 A at 0.8 to 3.0 V (CH1)
Output current 2.5 A at 0.8 to 3.3 V (CH2)
Output current 2.5 A at 0.8 to 3.6 V (CH3)
Output current 2.5 A at 0.8 to 3.3 V (CH4)
Operation frequency 2 MHz
Discharge function
Soft-start function ▪ LDO (CH6 to CH8)
Output current 0.2 A at 2.5 V (CH6)
Output current 0.2 A at 1.8/3.3 V (CH7)
Output current 1.6 A at 1.8 V (CH8)
Discharge function
Soft-start function ▪ Termination Voltage Regulator (CH5)
Output current -0.5 A to 0.5 A at CH4 = 1.2 V or CH4 = 1.35 V
Discharge function
Soft-start function ▪ I2C digital interface ▪ Protection features: OCP, OVP, UVP for all channels ▪ Parameters of output voltage can be changed by I2C control ▪ Programmable sequencer by I2C control ▪ -40 °C to +85 °C ambient temperature range ▪ QFN-40 5 mm x 5 mm 0.4 mm pitch package

Figure 1. System Diagram

R16DS0528EJ0301 Rev. 3.01 Mar 25, 2025 CFR0011-120-00 Page 3

R16DS0528EJ0301 Rev. 3.01 Mar 25, 2025 CFR0011-120-00 Page 7 1. Terms and Definitions OCP Over-current protection OVP Over-voltage protection PMIC Power management integrated circuit POR Power on reset TSD Thermal shutdown sequence UVLO Under-voltage lockout UVP Under-voltage protection VTT Termination voltage regulator

2.1 Block Diagram

Figure 2. Block Diagram

R16DS0528EJ0301 Rev. 3.01 Mar 25, 2025 CFR0011-120-00 Page 9 3. Pin Information

3.1 Pin Assignments

Noisy groundDigital signal Analog signalSwitching signal, high current Static signal, high current EN VOUT1 AVCC ANGD SDA SCL LX3 LX3 VOUT5_FB VOUT7 VIN7 VIN6 VOUT6 VOUT2 VIN2 VIN2 11 DA9281 (Transparent top view) Pin 1 PGND plane VIN3 VOUT3 VIN8 VOUT8 VOUT8 PGND VIN3 VIN8 LX1 LX1 LX1 LX1 PGND LX4 LX4 VIN4 Quiet ground LX2 LX2 VIN5 VOUT5 VIN4 VOUT4 VIN1 VIN1 Figure 3. 40 Lead QFN 0.4 mm Pitch Package Pinout Diagram (Top View)

3.2 Pin Descriptions

Table 1. Pin Description

Description

1,2 VIN3 PWR Input voltage for CH3 buck converter

3 VOUT3 AI Output voltage feedback of CH3 buck converter

4,5 VIN8 PWR Input voltage for CH8 LDO 6,7 VOUT8 PWR Output voltage of CH8 LDO

8 PGND GND Power ground

9,10 LX2 PWR SW node of CH2 buck converter 11,12 VIN2 PWR Input voltage for CH2 buck converter

13 VOUT2 AI Output voltage feedback of CH2 buck converter

14 VOUT6 PWR Output voltage of CH6 LDO

15 VIN6 PWR Input voltage for CH6 LDO

16 VIN7 PWR Input voltage for CH7 LDO

17 VOUT7 PWR Output voltage of CH7 LDO

18 VOUT5_FB AI Output voltage feedback of CH5 regulator

19 VOUT5 PWR Output voltage of CH5 regulator

R16DS0528EJ0301 Rev. 3.01 Mar 25, 2025 CFR0011-120-00 Page 10 Pin Number Pin Name Type (Table

20 VIN5 PWR Input voltage for CH5 regulator

21 VOUT4 AI Output voltage feedback of CH4 buck converter

22,23 VIN4 PWR Input voltage for CH4 buck converter 24,25 LX4 PWR SW node of CH4 buck converter

26 PGND GND Power ground

27-30 LX1 PWR SW node of CH1 buck converter 31,32 VIN1 PWR Input voltage for CH1 buck converter

33 VOUT1 AI Output voltage feedback of CH1 buck converter

34 EN DI Enable pin

35 SCL DI 2-wire I2C clock

36 SDA DIO 2-wire I2C data input/output

37 AGND GND Quiet analog ground

38 AVCC PWR Quiet analog supply

39,40 LX3 PWR SW node of CH3 buck converter EPAD41 PGND GND Common ground for all channels Table 2. Pin Type Definition

4.1 Absolute Maximum Ratings

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Rating conditions for extended periods may affect device reliability. conditions can adversely impact product reliability and result in failures not covered by warranty. Table 3. Absolute Maximum Ratings Note 1 Voltage must not exceed 6.0 V. Note 2 Voltage must not exceed 6.0 V and must not exceed VAVCC + 0.3 V.

4.2 Recommended Operating Conditions

Table 4. Recommended Operating Conditions

4.3 Electrical Characteristics

4.3.1 Current Consumption Characteristics

Table 5. Current Consumption Characteristics

4.3.2 Supervisory Characteristics

Table 6. Supervisory Characteristics

4.3.3 CH1 Buck Converter Characteristics

Unless otherwise noted, the following is valid for -40 °C ≤ TA ≤ +85 °C, 4.5 V ≤ VIN1 ≤ 5.5 V. Table 7. CH1 Buck Converter Characteristics

R16DS0528EJ0301 Rev. 3.01 Mar 25, 2025 CFR0011-120-00 Page 16 Parameter Description Conditions Min Typ Max Unit RPD_FB Feedback pull-down resistor VOUT = 0.5 V Disabled by OTP 15 Ω η100 Efficiency VIN1 = 5.0 V VOUT = 0.8 V IOUT = 10 mA to 100 mA Note 1 75 % η3000 Efficiency VIN1 = 5.0 V VOUT = 0.8 V IOUT = 100 mA to 3 A 80 % η4000 Efficiency VIN1 = 5.0 V VOUT = 0.8 V IOUT = 3 A to 4 A 75 % Η5000 Efficiency VIN1 = 5.0 V VOUT = 0.8 V IOUT = 4 A to 5 A 70 % Note 1 VIN1 current only.

4.3.4 CH2 Buck Converter Characteristics

Unless otherwise noted, the following is valid for -40 °C ≤ TA ≤ +85 °C, 4.5 V ≤ VIN2 ≤ 5.5 V. Table 8. CH2 Buck Converter Characteristics

R16DS0528EJ0301 Rev. 3.01 Mar 25, 2025 CFR0011-120-00 Page 18 Parameter Description Conditions Min Typ Max Unit RPD_FB Feedback pull-down resistor VOUT = 0.5V Disabled by OTP 30 Ω η100 Efficiency VIN2 = 5.0 V VOUT = 2.5 V IOUT = 1 mA to 100 mA Note 1 90 % η1000 Efficiency VIN2 = 5.0 V VOUT = 2.5 V IOUT = 100 mA to 1 A 90 % η2000 Efficiency VIN2 = 5.0 V VOUT = 2.5 V IOUT = 1 A to 2 A 85 % η2500 Efficiency VIN2 = 5.0 V VOUT = 2.5 V IOUT = 2 A to 2.5 A 85 % Note 1 VIN2 current only

4.3.5 CH3 Buck Converter Characteristics

Unless otherwise noted, the following is valid for -40 °C ≤ TA ≤ +85 °C, 4.5 V ≤ VIN3 ≤ 5.5 V. Table 9. CH3 Buck Converter Characteristics

R16DS0528EJ0301 Rev. 3.01 Mar 25, 2025 CFR0011-120-00 Page 20 Parameter Description Conditions Min Typ Max Unit RPD_FB Feedback pull-down resistor VOUT = 0.5V Disabled by OTP 30 Ω η100 Efficiency VIN3 = 5.0 V VOUT = 1.2 V IOUT = 1 mA to 100 mA Note 1 85 % η1000 Efficiency VIN3 = 5.0 V VOUT = 1.2 V IOUT = 100 mA to 1 A 85 % η2000 Efficiency VIN3 = 5.0 V VOUT = 1.2 V IOUT = 1 A to 2 A 80 % η2500 Efficiency VIN3 = 5.0 V VOUT = 1.2 V IOUT = 2 A to 2.5 A 75 % Note 1 VIN3 current only

4.3.6 CH4 Buck Converter Characteristics

Unless otherwise noted, the following is valid for -40 °C ≤ TA ≤ +85 °C, 4.5 V ≤ VIN4 ≤ 5.5 V. Table 10. CH4 Buck Converter Characteristics

R16DS0528EJ0301 Rev. 3.01 Mar 25, 2025 CFR0011-120-00 Page 22 Parameter Description Conditions Min Typ Max Unit RPD_FB Feedback pull-down resistor VOUT = 0.5 V Disabled by OTP 30 Ω η100 Efficiency VIN4 = 5.0 V VOUT = 1.2 V IOUT = 1 mA to 100 mA Note 1 85 % η1000 Efficiency VIN4 = 5.0 V VOUT = 1.2 V IOUT = 100 mA to 1 A 85 % η2000 Efficiency VIN4 = 5.0 V VOUT = 1.2 V IOUT = 1 A to 2 A 80 % η2500 Efficiency VIN4 = 5.0 V VOUT = 1.2 V IOUT = 2 A to 2.5 A 75 % Note 1 VIN4 current only

4.3.7 CH5 Voltage Regulator Characteristics

Unless otherwise noted, the following is valid for -40 °C ≤ TA ≤ +85 °C, 1.176 V ≤ VIN5 ≤ 1.377 V. Table 11. CH5 Voltage Regulator Characteristics Note 1 CH5 start-up triggered by CH4 soft-start completion.

4.3.8 CH6 LDO Characteristics

Unless otherwise noted, the following is valid for -40 °C ≤ TA ≤ +85 °C, 4.5 V ≤ VIN6 ≤ 5.5 V. Table 12. CH6 LDO Characteristics

4.3.9 CH7 LDO Characteristics

Unless otherwise noted, the following is valid for -40 °C ≤ TA ≤ +85 °C, 4.5 V ≤ VIN7 ≤ 5.5 V. Table 13. CH7 LDO Characteristics

4.3.10 CH8 LDO Characteristics

Unless otherwise noted, the following is valid for -40 °C ≤ TA ≤ +85 °C, 1.98 V ≤ VIN8 ≤ 2.12 V. Table 14. CH8 LDO Characteristics Note 1 Difference between input and output of the LDO should exceed this parameter.

4.3.11 Digital I/O Characteristics

Table 15. Digital I/O Electrical Characteristics Note 1 Input range compatible with 1.8 V and 3.3 V logic. Note 2 The applied voltage on the EN pin shall not exceed VINX limits.

4.4 Timing Characteristics

Table 16. I2C Characteristics tRISE SCL and SDA rise time. tFALL SCL and SDA fall time.

DA9281 is an 8-channel PMIC optimized for supplying system, I/O, and peripheral rails. discharge function and protection features such as OCP, UVP and OVP. DA9281 features a programmable power sequencer that handles start-up and shutdown sequences. These functions are programmed using the I2C interface.

6.1 POWER_OFF, SHUTDOWN, OPERATING, UVLO, and Thermal Shutdown

6.1.1 State Diagram

VIN UVLO
POR (triggers immediate SD)
TSD (triggers immediate SD) Non-FSM fault (single CH shutdown only)
any UVPs
any OVPs
These are cleared only with EN rising edge SEQ SHDN OFF (!UVLO) AND (EN high) AND (!flag_uvlo_latched) AND (!TSD) AND (!POR) SEQ OFF_BLANKING_TIMER expired OR (EN && !FAULT) flag_uvlo_latched
used when UVLO latch-off option is used
set once UVLO trips while EN is high (ignore UVLO trip when EN=0)
cleared when EN goes low SEQ skipped in case of TSD or POR (immediate SD)

Figure 24. State Transitions Diagram

6.1.2 Mode Description

and in addition the EN pin needs to be high. is left immediately towards SHDN in case of a fault (VIN UVLO, POR, TSD) or if the EN pin is set low. ▪ SHDN: In SHDN the SEQ sub-FSM takes care of disabling the channels according to their configured timing.

6.2 Startup and Shutdown Sequences

6.2.1 CH1, CH2, CH3, CH4 Soft Start-Up

To limit in-rush current from VINx, the buck converters (CH1 to CH4) perform a soft start-up after being enabled. Table 17. CH<x> Slew Rates

6.2.2 Normal Startup Sequence

Figure 25. Normal Startup Sequence

6.2.3 Normal Shutdown Sequence

Figure 26. Normal Shutdown Sequence

6.2.4 UVLO Falling Shutdown

Figure 27. UVLO Falling Shutdown Sequence 1

Figure 28. UVLO Falling Shutdown Sequence 2

6.2.5 POR Falling Shutdown

Figure 29. POR Falling Shutdown

6.2.6 TSD Thermal Shutdown Sequence

Figure 30. TSD Shutdown

6.2.7 Restart Sequence POR Released

Figure 31. Restart Sequence after POR Released

6.2.8 Restart Sequence TSD Released

Figure 32. Restart Sequence after TSD Released

R16DS0528EJ0301 Rev. 3.01 Mar 25, 2025 CFR0011-120-00 Page 43

6.3 Supervisory and Protection Functions

6.3.1 Under-Voltage Lockout

DA9281 has an under-voltage lockout (UVLO) function circuit to monitor the input voltage state at the AVCC power supply and control internal circuit operation. Whilst operating, the supply voltage at AVCC decreases and when it falls below UVLO detection voltage falling threshold (3.8 V typ. as default), all channels (buck regulators (CH1-CH4), LDOs (CH6, CH7, and CH8) and VTT regulator (CH5)) are sequentially disabled and then the output capacitors are discharged using pull -down resistances, in order to prevent malfunction. The following behavior when AVCC increases after UVLO is programmable ( UVLO latch-off turned “off” or “on” is set by OTP). The current sample device is set to UVLO latch-off turned “on”. For details, please consult your Renesas local sales representative. ▪ With UVLO latch-off turned “off”: When the power supply voltage at AVCC increases and exceeds the UVLO release voltage including hysteresis (100 mV typ.), UVLO is released, and then all channels restart automatically. ▪ With UVLO latch-off turned “on”: The chip cannot restart directly, but the enable pin EN needs to be pulled “low” first to clear the UVLO flag. Only then, with EN “high”, the chip will power up the channels again.

6.3.2 Thermal Shutdown

DA9281 has a Thermal Shutdown (TSD) function circuit to monitor the terminal temperature on the device and to control internal circuit operation. Whilst operating, the terminal temperature increases and when it exceeds thermal rising threshold (140 °C typ.) all channels (buck regulators (CH1-CH4), LDOs (CH6, CH7, and CH8) and VTT regulator (CH5)) are disabled immediately and then the output capacitors are discharged using pull down resistances, in order to prevent malfunction. When the terminal temperature decreases and becomes lower than thermal hysteresis (15 °C typ.), TSD is released, and then all channels restart.

6.3.3 Over-Current Protection

All channels (from CH1 to CH8) on DA9281 have an OCP function circuit to monitor over-current. This function automatically limits the output current when it exceeds the regulated (current limit) value. If it returns to the regulated (current limit) value or less than current limit value, it automatically returns to normal operation. Although the shutdown operation is not executed by this function, if the current is exceeding the regulated (current limit) value, the output voltage will fall with the function (over-current limitation). As a result, UVP may be detected and the output is shut down.

6.3.4 Under-Voltage Protection

All channels (from CH1 to CH8) on DA9281 have an UVP function circuit to monitor under-voltage. Channels CH1 to CH8 output is shut down after detecting voltage lower than the reference voltage ( 70 % typ.) for the regulation period time (100 µs typ.) To restart the channel after UVP, the EN pin must be first set to “low”. The channels can power up again from the rising edge of the EN pin.

6.3.5 Over-Voltage Protection

Channels CH1 to CH8 on DA9281 have an OVP function circuit to monitor over-voltage. Channels CH1 to CH8 output is shut down after detecting voltage higher than the reference voltage (1 20 % typ.) for the regulation period time (100 µs typ.). To restart the channel after OVP, the EN pin must be first set to “low”. The channels can power up again from the rising edge of the EN pin.

6.3.6 DC-DC Latch Off Protection

by the EN pin, the example shown is CH1 DC-DC. Figure 33. DC-DC Shutdown due to OCP/UVP

6.3.7 LDO Latch Off Protection

EN pin, the example shown is CH6 LDO. Figure 34. LDO Shutdown due to OCP/UVP

6.3.8 UVP Behavior during Soft-Start

During Soft-Start of all channels CH1-CH8, the UVP are masked so that no incorrect UVP flags are generated. plus 100 µs minimum observe time before the flag is raised. An example is shown in Figure 35.

Figure 35. UVP Behavior during Soft-Start

6.4 I2C Communication

slave device. For detailed information about each register, see Section 7. The DA9281 8-bit SLAVE address is 0xA2h (default). The I2C data pin, SDA, is open drain allowing multiple devices to share a communication line. and address are transferred with MSB transmitted first for both read and write operations. Figure 36. I2C Start (S) and Stop (P) A Not Acknowledge signal is given by the logic 1, not pulling down the SDA line. address, and the data. The transaction is terminated with a STOP.

The following registers are password protected.

7.1 Register Map

Table 18. Register Map

R16DS0528EJ0301 Rev. 3.01 Mar 25, 2025 CFR0011-120-00 Page 48 Address Register Description 0x0E PMC_CONTROL_02 Sequence enable for CH1, CH2, CH3, CH4, CH5, CH6, CH7, CH8 0x0F PMC_CH1_VOUT_INT VOUT setting for CH1 0x10 PMC_CH2_VOUT_INT VOUT setting for CH2 0x11 PMC_CH3_VOUT_INT VOUT setting for CH3 0x12 PMC_CH4_VOUT_INT VOUT setting for CH4 0x14 PMC_CONFIG_00 I2C slave address 0x1F PMC_CONFIG_0B Sequencer enable 0x41 OTP_VARIANT_ID Silicon revision 0x42 OTP_CUSTOMER_ID OTP file version 0x43 OTP_CONFIG_ID OTP variant 0x4C BUCK_BUCK_OTP_04 Divider mode enable for CH1 0x4D BUCK_BUCK_OTP_05 Divider mode enable for CH2 0x4E BUCK_BUCK_OTP_06 Divider mode enable for CH3 0x4F BUCK_BUCK_OTP_07 Divider mode enable for CH4

7.2 Register Details

Table 19. Register Details

0 R/W RESERVED - 0x0

6 R/W CH2_DISCH 0: Discharge Disable

5 R/W CH3_DISCH 0: Discharge Disable

4 R/W CH4_DISCH 0: Discharge Disable

3 R/W CH5_DISCH 0: Hi-Z

2 R/W CH6_DISCH 0: Discharge Disable

1 R/W CH7_DISCH 0: Discharge Disable

0 R/W CH8_DISCH 0: Discharge Disable

R16DS0528EJ0301 Rev. 3.01 Mar 25, 2025 CFR0011-120-00 Page 50 Address Register Bit Type Function Detail Default [3:2] R/W CH3_SS 00: 0.4 ms 01: 0.6 ms 10: 0.8 ms 11: Reserved 0x1 [1:0] R/W CH4_SS 00: 0.4 ms 01: 0.6 ms 10: 0.8 ms 11: Reserved 0x1 0x04 PMC_SOFT_START_2 [7:6] R/W CH5_SS 00: 0.4 ms 01: 0.6 ms 10: 0.8 ms 11: Reserved 0x1 [5:4] R/W CH6_SS 00: 0.4 ms 01: 0.6 ms 10: 0.8 ms 11: Reserved 0x1 [3:2] R/W CH7_SS 00: 0.4 ms 01: 0.6 ms 10: 0.8 ms 11: Reserved 0x1 [1:0] R/W CH8_SS 00: 0.4 ms 01: 0.6 ms 10: 0.8 ms 11: Reserved 0x1 0x05 PMC_ENABLE_DELAY_1 [7:6] R/W CH1_ENDLY 00: 0.0 ms 01: 0.8 ms 10: 1.6 ms 11: 2.4 ms 0x0 [5:4] R/W CH2_ENDLY 00: 0.0 ms 01: 0.8 ms 10: 1.6 ms 11: 2.4 ms 0x0 [3:2] R/W CH3_ENDLY 00: 0.0 ms 01: 0.8 ms 10: 1.6 ms 11: 2.4 ms 0x0 [1:0] R/W CH4_ENDLY 00: 0.0 ms 01: 0.8 ms 10: 1.6 ms 11: 2.4 ms 0x0 0x06 PMC_ENABLE_DELAY_2 [7:6] R/W RESERVED - 0x0 [5:4] R/W CH6_ENDLY 00: 0.0 ms 01: 0.8 ms 10: 1.6 ms 11: 2.4 ms 0x0 [3:2] R/W CH7_ENDLY 00: 0.0 ms 01: 0.8 ms 10: 1.6 ms 11: 2.4 ms 0x0

R16DS0528EJ0301 Rev. 3.01 Mar 25, 2025 CFR0011-120-00 Page 51 Address Register Bit Type Function Detail Default [1:0] R/W CH8_ENDLY 00: 0.0 ms 01: 0.8 ms 10: 1.6 ms 11: 2.4 ms 0x0 0x07 PMC_DISENDLY 7 R/W CH1_DISENDLY 0: 0 ms 1: 10 ms 0x0

6 R/W CH2_DISENDLY 0: 0 ms

1: 10 ms 0x0

5 R/W CH3_DISENDLY 0: 0 ms

1: 10 ms 0x0

4 R/W CH4_DISENDLY 0: 0 ms

1: 10 ms 0x0

3 R/W RESERVED - 0x0

2 R/W CH6_DISENDLY 0: 0 ms

1: 10 ms 0x0

1 R/W CH7_DISENDLY 0: 0 ms

1: 10 ms 0x0

0 R/W CH8_DISENDLY 0: 0ms

1: 10ms 0x0 0x08 PMC_PROT_STATUS_1 [7:6] R CH1_STATUS 00: Normal 01: Reserved 10: UVP 11: OVP 0x0 [5:4] R CH2_STATUS 00: Normal 01: Reserved 10: UVP 11: OVP 0x0 [3:2] R CH3_STATUS 00: Normal 01: Reserved 10: UVP 11: OVP 0x0 [1:0] R CH4_STATUS 00: Normal 01: Reserved 10: UVP 11: OVP 0x0 0x09 PMC_PROT_STATUS_2 [7:6] R CH5_STATUS 00: Normal 01: Reserved 10: UVP 11: OVP 0x0 [5:4] R CH6_STATUS 00: Normal 01: Reserved 10: UVP 11: OVP 0x0 [3:2] R CH7_STATUS 00: Normal 01: Reserved 10: UVP 11: OVP 0x0 [1:0] R CH8_STATUS 00: Normal 01: Reserved 0x0

R16DS0528EJ0301 Rev. 3.01 Mar 25, 2025 CFR0011-120-00 Page 52 Address Register Bit Type Function Detail Default 10: UVP 11: OVP 0x0A PMC_STATUS_00 7 R S_CH1_PG CH1 PG status 0x0

6 R S_CH2_PG CH2 PG status 0x0

5 R S_CH3_PG CH3 PG status 0x0

4 R S_CH4_PG CH4 PG status 0x0

3 R RESERVED - 0x0

2 R S_UVLO VIN UV status 0x0

1 R S_VDD_FAULT VDD_FAULT status 0x0

0 R S_TEMP_CRIT Thermal shutdown status 0x0

0x0C PMC_CONTROL_00 7 R/W CH1_EN CH1 enable 0x0

6 R/W CH2_EN CH2 enable 0x0

5 R/W CH3_EN CH3 enable 0x0

4 R/W CH4_EN CH4 enable 0x0

3 R/W CH5_EN CH5 enable 0x0

2 R/W CH6_EN CH6 enable 0x0

1 R/W CH7_EN CH7 enable 0x0

0 R/W CH8_EN CH8 enable 0x0

0x0D PMC_CONTROL_01 7 R/W RESERVED - 0x0

6 R/W RESERVED - 0x0

5 R/W RESERVED - 0x0

4 R/W RESERVED - 0x0

3 R/W CH1_MODE CH1 Mode

0: Auto-mode 1: Force-PWM 0x0

2 R/W CH2_MODE CH2 Mode

0: Auto-mode 1: Force-PWM 0x0

1 R/W CH3_MODE CH3 Mode

0: Auto-mode 1: Force-PWM 0x0

0 R/W CH4_MODE CH4 Mode

0: Auto-mode 1: Force-PWM 0x0 0x0E PMC_CONTROL_02 7 R/W CH1_SEQ_DIS 0: Enabled by sequencer 1: Not enabled by sequencer 0x0