SDA3002 ETC1 | Alldatasheet
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© No external integrator required @ Noise-immune message transmission © Software-controlled integration time constant I @ Microprocessor-compatible k Maximum ratings Supply voltage range Vs | -0.3107.5 |v F Inputs 1 Q1, Q2, Iner v 0.3 to Vs v : IFO, CPL v, -03t0Ve+05 | V : PLE vi -0.3 107.8 v 1 FF Mi =0.3toVs+05 | V | Outputs | PD Va 0.3 to Vs v : Yo Va -0.3 to 33 v : ——— dau -7 mA ] 8S, VHF, UHF, 8d Ii, standard Va -0.3 0 16 v : LOCK Ty -1t05 mA ; Junction temperature I 140 °C 1 Storage temperature range Tag 40 to 125 °c ; Thermal resistance : (system-air) Rinse 80 Kw j Operating range 1 ‘Supply voltage Vs | 4.5107.15 v 1 input frequency tafe | 16 MHz i Divider factor N | 1024 to 16383 Resistance for Iner R | 80 Ka Tree = (Vs —0.8) Bi | I Tuning voltage Yo 0.3 to 33 v open callector Ambient temperature Ta | oto 70 °C 1 230 |
SDA 3002 | Characteristics Vs = 5 V; Ty = 25°C ! min typ | max : Supply current Is 15 | 22 (35 mA : Signal inputs F/F 1 Input voltage View | | | Vs +0.2| V 7 Vier 38 v Input current le | | 50 pA j Vig 5. : input sensitivity at sine push-pull; f=16 MHz Yieoe wo | 1200 | mv (peak-to-peak) 1 Inputs (IFO, CPL, PLE) | Input voltage Vou 24 | | os v Vou Input current | Veu=5V Ion | fa HA : Ve. =0.4V Tou 550 | pA ; Band select outputs | | j Reverse current lon | 10 A ' Vay 15V | : Current drain by 05 | 3 mA i 2V5 V3 S15V ; Tuning section PD, Vp, Ines, LOCK 1 Charge pump current Ia £250 £550 | pA | Ipump 10 X Inge: Vs = 5 V Tuning voltage Visi | 03 |v : Tis. 1.5mA ! Reverse current Is | 20 yA : Ves = 33.V | : Reference current In 30 40 HA : ext. R=120 kQ: Vs =5V j Output voltage Vion 145 v j int RL=3kQ : au =—100 pA : Tio, 100 pA Via | 07 v | IFO, PLE i Set-up time for enable ve 2 us data yo |? bs Hold time for: enable tue 2 Hs data ~* tho | 2 us CPL : H pulse width tow | 2 hs | L pulse width te 2 hs ; 214 F
Circuit description | Triggered by the ECL inputs F/F a switchable 32/33 counter operates a8 4 14-bit synchronous ; divider in the dual modulus method when combined with a § and 9-bit programmable ! synchronous counter. In this combination the 8-bit counter controls the switch-over from : 32 to 33 (block diagram 1). Dividing ratios of N = 1024 to 16383 are possible, ; The 18-bit deep shift register with latch is subdivided into 14 bits for storing the dividing 1 ratio N, as well as 1 bit for selecting the pump current and 1 bit for a standard switch-over. : The remaining 2 bits contro! the 4 band selection outputs. The message is inserted over ; the serial data input IFO with the H-L slope of the shift clock CPL, when the enable | input is set at H. Beginning with LSB, the complement of the dividing ratio is inserted in : binary code, then the select bit 2 for the pump current and the control bit 2'5 for standard TV switch-over are added. The band selection control bits 2'° and 2'” complete this process (refer to table). An integrated control circuit checks the world length (18 bits) of the data message The 18-bit latch accepts the data from the shift register during the L state of the enable input PLE. A. 4 MHz crystal controlled clock oscillator has been integrated in the IC. An internal reference divider divides the output signal of the crystal oscillator (fosc = 4 MHz) by 4096 resulting in 0.97656 kHz (reference signal), providing a frequency resolution of 62.5 kHz by means of the asynchronous permanent divider (dividing factor 64). In a digital phase detector the divided VCO input signal is compared with the reference : signal. If the trailing edge of the VCO input signal appears before the trailing edge of the 1 reference signal, the output DOWN of the phase detector will be in the H state for the : Guration of the phase difference. However, if above signal sequence is reversed, the output uP 1 will be in the H state instead. The outputs UP/DOWN control the two current sources ; T+and [- (charge pump). In case both outputs are in the L state, the charge pump output : ‘will be in the high impedance mode (TRISTATE). Information with respect to either the i Hy or L state will be provided at the LOCK output by the logical “NOR” of the outputs 1 UP/DOWN. 1 The output current of the charge pump (source current = drain current) is adjusted by an 1 external resistor between pin Ine: ANd Voc. In addition, this output current can be generated | by the control bit for the pump current at the same value or ata value increased by a factor i of 10 (refer to table). i The current pulses generated by the charge pump are integrated into the tuning voltage : by means of an active low pass filter (on-chip loop amplifier and external RC circuit) j The de output signal of the low pass filter is available at Vp and is used as tuning voltage ; for the VCO. In order to provide tuning voltages higher than Vo. = 6 V, the output stage : of the amplifier consists of a transistor with an open collector. The external collector re- i sistor can be connected to voltage up to 33 V. j To switch voltages higher than Vo, = 5 V, the band selection outputs (Bd I/ll, VHF, UHF, Standard, BS) include current drains with open collectors. It is therefore possible to directly | connect transistors operating as band selection switches without the use of current limiting resistors (please refer to application circuit). 215 : i
Pin | Symbol Function | 1 | Qi Crystal :
2 Q2 Crystal :
3 Standard Standard switchover output 1
4 BS Band selection output BS 1
5 | VHF Band selection output VHF :
6 UHF | Band selection output UHF 3
7 Bd WII | Band selection output I/Ill :
8 | PLE Enable input for shift register
9 GND Ground
10 CPL Shift clock pulse input
12 | LOCK | Lock output
13 PD Amplifier input/charge pump output
14 | Teer Current adjustment for charge pump 15 | Vp | Tuning voltage output :
16 F Signal input ;
17 F Signal input F
18 | Vs | Supply voltage ; i I 216 |
SDA 3002 | Truth table Pump current | IFO-Bit | Bit Output | 2 2° Standard : I= Iyer L L 1=10X Ince | H H [ IFO-Bit Band selection outputs") Meaning ; 2 27 | Bd V/lll VHF =-UHF BS. 7 LoL HOH OL H | UHF L4H HOOL HH | VHF/BdI HOO L L HH | VHF/Bd Il HoH L L HOOL BS : Pulse diagram i cPL ! a ULL I ! = ! ttt : pie {| | rrr ; hyd ot 7 rod Wilt : WOHCHHHUCCUUCHHA CALE : jLSB MB} | | ! N= 1930 A _ E \\ rire | p qezuys gn First Bit Last Bit ; i 7) L=condvetive; H= blocking
i SDA 3002 ) Computation for loop filter Pp =Prescaler Loop bandwidth: wa /"_I, x Kvco N — =Progr. divider : C.xPXN Jp =Pump current : Attenuation: €=0.5xw_xRxC, Kyco = Tuner slope ] R, C, =Loop filter 1 Example for channel 47 ; P= 64; N=11520; /, = 200 WA; Kyco = 18.7 MH2/V; R=33kQ; C, = 330 nF : (on = 124H2; fq 20 Hz; £=0.675 | Standard dimensioning: C, = Cys Block diagram ‘i G, p4Ink | Ys GND 18 pF Lock R Filter, ! a jaz po] 338 330nF 1 | 0,9765625 kHz j | \\ 32V 3 » | oO 22x80] : iba | F SDA 3002 & Yo : Cy Voltage ' ar 3 120k I {| | ETT \\cPL_ PLE IFO, Standard BS VHF UHF Bil Intertace to WP | j 218 1 oo 1 bT—rhiehs a Oc a i
90% 90% IFO 10% W%7 _-| No = tio 90% 90% PLE | el tee vette tow rr 90% ay f ow CPL y 0,6 V- 0,6V 10%: tox 219
Test and measurement circuits Test circuit 1 Test circuit 2 sv
18 Bus input PLE, CPL, IFO
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1 I: 2 —
18pF GQ sv © Crystal Oscillator Test circuit 5 Sv 10* Iner 5kQ Ty ° I ' [J he Me 33V ag T | 7 + ® a []ezks - ¥ s + \\ vs hs Tq , 9 Tuning Parts | own 30k0| [Jus f Inputs/Outouts] | []aouse | Ieee! fey, | | lee ---- ” : fy : Ms re) 221
Dimensional proposal: R,= 120 k& (J, = 35/350 pA) Ro= 22kQ;R,. Ry= 22 k2 Loop filter: R= 33kQ; C,=330 nF; C,=47 nF Filter (in tuner) Ry= 10kQ; C;=47 nF Gd, he “ m . - Rr ll Ves \\% ? 4 MHz ? [a 18pF « an, a2] FY FY Place Fitte : Po Lock A fe Serial rie PLE Interface tone Yo CPL aa < Standard BS GND 222