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© Semiconductor Components Industries, LLC, 2011 April, 2011 − Rev. 5

1 Publication Order Number:

Q32M210 is a precision, mixed−signal 32−bit microcontroller. The microcontroller is built on the high performance ARM® Cortex/C0116−M3 processor. The microcontroller incorporates a highly configurable sensor interface designed to work directly with a wide range of sensors having multiple characteristics, including specialized electrochemical sensors. The sensor interface includes dual programmable gain amplifiers, dual 16 −bit Analog −to−Digital converters, triple 10 −bit Digital−to−Analog converters (for voltage waveform generation and other applications) and three uncommitted, low −noise opamps with configurable signal multiplexing. Flexible connectivity to external non−volatile memory, personal computers, wireless devices, LCD displays and a wide range of other peripherals is enabled by several digital interfaces including I 2C, USB (2.0 full−speed compliant) and a high−speed SPI/SQI interface. The microcontroller features flexible clocking options as well as intelligent failure monitoring of power and application interruptions required by high performance, portable, battery operated applications. All necessary clocks including an internal oscillator, real −time clock and a dedicated clock for USB operation are available on −chip (external crystals required for RTC and USB). An embedded power management unit, which incorporates several low power modes, allows application developers to minimize both standby and active power under a wide range of operating conditions. The ultra −low sleep current makes the microcontroller ideal for applications that remain inactive for long periods of time. A large on −chip non −volatile flash memory (256 kB) combined with on −chip SRAM (48 kB) supports complex applications and simplifies application development. The flash contains built −in hardware error checking and correction (ECC) for application reliability. Additionally, a configurable DMA unit which supports independent peripheral −to−memory, memory −to−memory, and memory−to− peripheral channels provides flexible, low power data transfers without processor intervention. A suite of industry−standard development tools, hands−on training and full technical support are available to reduce design cycle time and speed time−to−market.

  • The Q32M210 Microcontroller is Pb−Free, Halogen Free/BFR Free and RoHS Compliant http://onsemi.com TLLGA−140 DUAL−ROW CASE 513AL MARKING DIAGRAM See detailed ordering and shipping information in the package dimensions section on page 50 of this data sheet.

ORDERING INFORMATION

Q32M210 = Device Code A = Assembly Site WL = Wafer Lot YY = Year WW = Work Week G = Pb −Free Package Q32M210 AWLYYWWG

Figure 1. Functional Overview

http://onsemi.com FUNCTIONAL OVERVIEW Operating Modes Three low−power operating modes are available 1. Run mode – used during normal program execution; the entire device is fully operational in run mode 2. Standby mode – used for lower current consumption, with paused program execution and fast wakeup 3. Sleep mode – used for ultra low current consumption, with no program execution and restart after wakeup Each mode is designed to provide the lowest possible current consumption, while maintaining power to specific parts of the device. Run Mode Run mode provides a low power mode where the entire system is fully functional. In run mode, the device enables the on−chip VDDD Digital Supply Regulator to provide power to the ARM Cortex−M3 Processor. The processor is clocked from either an internal or an external clock source. The program can be executed from the internal flash or SRAM. The application can selectively enable or disable sensor interface components, including supply regulators and references, as required. The application may also adjust the device clock frequency through the internal oscillator or through clock divisors to minimize power consumption. The digital and analog interfaces may be configured as required in run mode. Internal clock dividers provide all the necessary clocks to the sensor interface and peripherals. While in run mode, the application may switch into either sleep mode or standby mode. Standby Mode Standby mode provides a low power mode where the digital system state is retained. In standby mode, the ARM Cortex−M3 Processor execution is paused. The VDDD Digital Supply Regulator voltage is reduced. The contents of all the registers and SRAM are retained. The power supervisor automatically disables and powers down the sensor interface components, including the analog supply regulators and references. The application may selectively enable or disable the RTC, RTC alarm, and the Wakeup controller. The internal oscillator is automatically disabled. When in standby mode, the device may be switched into run mode by either the RTC alarm or by up to four external events (through the Wakeup controller). Sleep Mode Sleep mode provides an ultra−low power mode where the system is waiting for a wakeup event. In sleep mode, the power supervisor automatically disables and powers down the digital and analog supply regulators, the internal oscillator, and all the sensor interface components. The application may selectively enable or disable the RTC, RTC alarm, and the Wakeup controller. When in sleep mode, the device may be switched into run mode by either the RTC alarm or by up to four external events (through the Wakeup controller). After exiting sleep mode, the system state is reset and execution starts from the beginning of the ROM program. A general purpose retention register is available to store state. The retention register contents are retained after exiting sleep mode. This register may be used by the application to quickly restore its state. Power Supply The device can powered from a single battery supply such as a 2032 lithium coin cell. The device supplies all required regulated voltages and references on−chip. This allows the device to operate directly from a single battery supply without the need for external regulators or switches. VBAT and VBATA The main power supply input for the device is VBAT. The supplied voltage to VBAT is typically 3.3 V but it can be supplied with any voltage between 1.8 V and 3.6 V . The device will operate reliably across this entire power supply range. This flexibility allows for a wide range of battery types to be directly connected to the device. The sensor interface power supply for the device is VBA TA. VBATA is typically 3.3 V but it can be supplied with any voltage between 1.8 V and 3.6 V . The sensor interface will operate reliably across this entire power supply range however the performance of the sensor interface may be reduced when VBATA drops below 2.2 V . VBA TA also powers the IF5 pins. In a typical application, VBATA and VBAT are both connected directly to the battery supply. To increase the useful operating life of the battery VBATA may be externally connected to the on −chip charge pump output (VDBL) instead of the battery. In this configuration the sensor interface power supply remains nominally 3.5 V even as the battery voltage drops. VBA T is monitored by the built −in power supervisor. VBA TA is not directly monitored but may be measured through the sensor interface. Regulators All required voltages for normal device operation are generated on−chip. VDDD The VDDD Digital Supply Regulator (VDDD) provides a nominal 1.8 V power supply for the ARM Cortex −M3 Processor, digital peripheral and memories, including the on−chip flash. VDDD is generated on−chip and is connected to the digital components internally. It is also available externally. Flash memory reads and writes require only a

http://onsemi.com minimum voltage of 1.8 V . No external power management circuitry is required to support flash access. VADC The V ADC Analog Supply Regulator (V ADC) provides a nominal 1.8 V power supply for the ADCs and PGAs. This separate supply ensures noise immunity between the analog and digital subsystems. V ADC may be enabled or disabled as required to save power. VDBL The VDBL Charge Pump (VDBL) provides a nominal

3.5 V power supply under any normal operating range

battery voltage. VDBL is powered from the dedicated on−chip Charge Pump Supply Regulator (VCP). This separate supply ensures noise immunity between VDBL, the other on−chip power supplies as well as from the battery. VDBL is normally used to power an LCD segment display and associated backlight or any other external devices requiring a fixed, high voltage rail. VDBL may also be used to power the sensor interface. This is useful when a fixed, higher voltage rail is required for the sensor interface compared to the battery voltage. ILV An on−chip programmable current sink (ILV) is available to adjust the amount of current from VDBL through an LED backlight. In a typical configuration an LED is connected between VDBL and ILV . The application controls the LED brightness by adjusting the current setting. VREF Precision Voltage Reference The device provides an on −chip low −temperature drift reference voltage, VREF. VREF is factory calibrated to 0.9 V . VREF is available externally and is also connected internally to the ADCs and DACs for their reference voltages. I/O Pin Supplies The device’s I/O pins are powered from multiple supplies. This allows the device to match its I/O voltage levels to external devices as required. One bank of digital I/O pins is powered from VDDIO0. The voltage applied to VDDIO0 determines the logic level for the associated pins. A second bank of mixed signal I/O pins is powered from VDDIO1. The voltage applied to VDDIO1 determines the digital logic level for the associated pin. When the mixed signal I/O pins are configured for LCD operation, VDDIO1 must be at or above VLCD supply voltage for proper operation. The USB pins USBDP and USBDN are powered directly from VDDUSB. The IF5 pins are powered directly from VBATA. All analog signal pins are powered directly from VBATA. Power Supervisor, Power−on Reset, and Brown−Out Protection The device contains a dedicated hardware power supervisor for monitoring the supply voltages. The power supervisor ensures the device operates deterministically, and without any unexpected behavior during all supply conditions. The power supervisor releases the internal Power −on Reset (POR) when the supply voltage on VBAT exceeds the minimum threshold for proper operation. The release of POR enables the VDDD Digital Supply Regulator. The power supervisor continues to monitor VBAT. If VBAT drops below the minimum threshold for proper operation the device is reset. No external circuitry is required for proper device startup. All required start −up delays and reset thresholds are generated on −chip. The RSTB pin may be left floating during startup. The ARM Cortex−M3 Processor and all digital subsystem components including the flash, SRAM, and peripherals will operate reliability down to a nominal VDDD supply voltage of 1.8 V . In run mode, the power supervisor continually monitors VDDD. If VDDD drops below the minimum threshold for proper operation the device is reset. The power supervisor is automatically disabled in sleep mode and standby mode to save power. Supply Monitor During run mode, the actual voltage levels for VBAT, VBATA, VREF, and V ADC can be measured through either one of the ADC channels. This allows the application to determine the actual supply levels and appropriately handle the graceful shutdown of the system when the battery approaches its useful end−of−life. Additional voltages may be monitored through one of the auxiliary inputs. In a system configuration where the sensor interface may be supplied from either the battery or the VDBL Charge Pump, the application can use the measured VBAT voltage level to determine whether to enable VDBL or continue to supply the sensor interface from the battery. External Reset The device contains an external reset pin (RSTB). When RSTB is asserted, the digital subsystem including the ARM Cortex−M3 Processor is reset. The real−time clock counters are not reset by an external reset. The RSTB function is only available in run mode. Asserting the RSTB pin during the Power−on Reset sequence will prevent the ARM Cortex−M3 Processor from running. The system will be held in reset until the pin is released. RSTB can be left floating. System Wakeup Wakeup occurs when the device is switched from standby mode or sleep mode into run mode. This can be accomplished through one of the wakeup mechanisms. The wakeup controller allows for up to four external events to wake up the system. Two IF5 pins (IF5.0, IF5.1) will wakeup the system when a High−to−Low transition is detected. Two IF5 pins (IF5.2, IF5.3) will wakeup the system when a Low− to−High transition is detected. The RTC Alarm can also be configured to wakeup the system at a predetermined time.

http://onsemi.com Clocking The device contains several clock generators and clock I/O capability. After Power−on Reset, the device selects the internal oscillator as the system clock source. The default clock frequency at POR is 3 MHz. After boot, the application may select another frequency or switch to another clock source. The device may select the real −time crystal oscillator (32.768 kHz) as the clock source, when low operating frequencies are required to save power. Internal Oscillator The device contains a reconfigurable, factory calibrated internal oscillator. The calibration settings are stored in the on−chip flash. Settings are available for all integer frequencies in the normal operating range (1 MHz to 16 MHz). Finer calibration is possible. The default setting after Power−on Reset is 3 MHz. The application can switch to any operating frequency after entering run mode. External Clock The device contains an external clock I/O pin (EXT_CLK). EXT_CLK may be used as a clock source for the entire system or as a clock output. The application may switch to use an externally supplied clock or output a clock after boot. If neither function is desired EXT_CLK may be left floating. An external clock detection circuit is included that will automatically switch the system to the internal oscillator, if the external clock is selected, but no clock signal is detected. When EXT_CLK is used as an output, the frequency of the output clock can be divided before EXT_CLK is output. Real−Time Clock The device contains an ultra low−power real−time clock (RTC). The RTC includes a real −time crystal oscillator, read−write RTC counters, and a configurable alarm. The real−time crystal oscillator utilizes a 32.768 kHz external crystal. The RTC may be enabled or disabled in each of the three operating modes. The RTC is powered directly from VBAT. This allows the RTC to continue to run when the VDDD Digital Supply Regulator voltage is reduced in standby mode or disabled in sleep mode and thus the system date and time information are always maintained. The RTC is reset after the initial Power −on Reset but remains operational through a digital reset (RSTB or watchdog) and operating mode switching. The alarm function can be configured to wake −up the system from standby mode or sleep mode at a pre−determined time. The alarm will also generate an interrupt to the ARM Cortex−M3 Processor. The alarm can be configured for absolute mode or relative mode. In relative mode, the alarm is automatically reloaded after each alarm trigger. This is useful for extremely low −duty−cycle applications that require periodic polling. USB Crystal Oscillator The device contains a dedicated USB crystal oscillator. The oscillator requires an external 48 MHz crystal for compliance with the USB interface specification. The clock output is used internally for the USB PHY and USB core. During USB operation the ARM Cortex −M3 Processor and all other system blocks continue to run on the slower system clock. This allows the device to achieve low system current even while the USB interface is active. The USB Crystal Oscillator can be enabled or disabled. Clock Divisors On−chip clock divisors and prescalers are available to provide selectable frequencies to the ARM Cortex −M3 Processor, sensor interface, peripherals and external interfaces. These divided clocks are derived from the root clock source and may be configured independently. This adjustability allows the optimum clock frequency to be selected for each system component. Sensor Interface Opamps Three uncommitted low −noise opamps are available. Each opamp is directly powered from the VBATA supply for achieving high input dynamic range for sensor interface signals. Each of the opamp’s positive and negative terminals is brought out to a dedicated input pin on the device. Each opamp output terminal is connected to two dedicated output pins. An internal switch selects between output to one or both of the output pins, allowing for dynamic reconfigurability of the external opamp feedback network. Signal Multiplexing A comprehensive input multiplexing scheme allows for flexible interconnection of a wide range of sensors and external circuits to be connected to the sensor interface. The input multiplexing consists of:

  • An 8:1 analog multiplexer – Connects one of 8 low−leakage input pins to an opamp negative terminal
  • A 3:1 analog multiplexer – Connects one of 3 low−leakage input pins to an alternate sensor node (ALT0) and optionally to an opamp negative terminal
  • A 5:1 analog multiplexer – Connects one of 5 low−leakage input pins to an alternate sensor node (ALT1) and optionally to an opamp negative terminal Each multiplexer signal path features low Ron characteristics providing nearly transparent signal routing for any external sensor. The input multiplexer configuration may be changed on−the−fly by the application. Dual PGA and ADC Two independent 16−bit Analog−to−Digital Converters (ADCs) are available. The ADCs provide a very high resolution, a high degree of linearity, as well as low gain and offset temperature drifts. Each ADC is coupled with a

http://onsemi.com Programmable Gain Amplifier (PGA) allowing signals to be sampled without external buffering. The ADC data rate is reconfigurable and a wide range of data rates are possible. Each ADC conversion takes a fixed time resulting in a deterministic, periodic sampling. Lower data rates may be configured to achieve a higher effective dynamic range. The ADCs operate rail−to−rail from 0 V to VADC (1.8 V) using the internal VREF Precision V oltage Reference (0.9 V). Unsigned or two’s complement output samples are provided to the ARM Cortex −M3 Processor and synchronized to the periodic ADC interrupt. The DMA may also be used to transfer samples directly from the ADC to SRAM. Each PGA and ADC has 16 multiplexed inputs allowing a wide range of sensor interface signals to be measured. In addition, power supply voltages are available as measurement inputs for application level supply monitoring. Programmable Gain Amplifiers A PGA is used to directly feed each of the ADC inputs. The PGAs operate in either single −ended mode or differential mode. Single −ended operation is obtained by setting one PGA input to VSS. Differential operation is obtained by routing signals to each of the two PGA inputs. The resulting voltage is amplified, anti −alias filtered, and output into the ADC. A wide range of gain steps from 0 dB to 36 dB allow for optimal adjustment of the PGA output to match the dynamic range of the ADC. PGA1 operates in one of three input modes. Each input mode provides a different common −mode voltage range with linearity characteristics and tradeoffs. The application may choose different PGA1 operating modes depending on the type of measurement being made. PGA0 operates in a single input mode only. Automatic Voltage Detection Automatic voltage detection is available on PGA0. When enabled, the PGA0 will output an interrupt to the ARM Cortex−M3 Processor when the PGA0 output voltage exceeds the configured threshold. To save power the ADCs may be disabled while waiting for the detection signal. Auxiliary Inputs Three auxiliary inputs provide a direct connection to the PGA and ADC multiplexers. External voltages such as thermistor networks may be connected to any of these high impedance inputs for direct measurement with the ADC. Triple DAC Three independent 10−bit DACs are available. Each DAC output is individually controlled by the ARM Cortex −M3 Processor. The DACs provide a high degree of linearity, low gain and offset temperature drift, and are monotonic within the normal operating range. The dynamic range of DAC0 is reconfigurable. The 10−bit output range may be mapped into one of three ranges: 1 x VREF, 2 x VREF, or 3 x VREF. This reconfigurable dynamic mapping allows a tradeoff between LSB resolution and dynamic range. The dynamic range of DAC1 and DAC2 is fixed to 2 x VREF. Temperature Sensor The device contains a built −in temperature sensor. The temperature sensor works by generating a differential voltage that varies linearly with temperature. The voltage is routed into the PGA resulting in a single −ended output voltage measurable by the ADC. The temperature sensor is calibrated during factory production by ON Semiconductor. The calibration value is stored in the flash. The device junction temperature may be determined based on the calibration factor and converted ADC output value. SPST Switches The device contains four analog general −purpose, low−leakage, low−Ron, single−pole single−throw switches (SPSTs). Each SPST consists of 2 ports – A and B. The SPST connection is determined by the application and may be changed in real −time. Port A can be connected or disconnected from Port B. The SPSTs can be used for routing both power supplies and signals. Each SPST is designed to conduct a continuous current of up to ± 10 mA. This provides sufficient current bandwidth to supply power to external devices such as LCD displays or wireless transceivers. When routing signals through the SPST, the low−leakage characteristics allow the switch to create a high isolation between a measurement node and the sensor interface. The application may connect the measurement node to the sensor interface through the SPST as required. The low −leakage characteristics allow the SPST to be added to the signal chain without interfering with the impedance properties of the measurement node. Multi−Switches The device contains four analog general −purpose, low−leakage, low −Ron multi −switches (MSWs). Each MSW consists of 3 ports – Port A, Port B, and Port C (Common). The MSW connection is determined by the application and may be changed in real −time. The MSW may be configured to connect A to C, B to C, A and B to C, or neither to C. A signal of interest may be connected to the common port, and selectively routed to A, B, or A and B. Alternately, two signals of interest may be connected to A and B, respectively, and either one selectively routed to C. The MSWs may be used for routing both power supplies and signals. Each MSW is designed to conduct a continuous current of up to 10 mA. This provides sufficient current bandwidth to supply power to external devices such as LCD displays or wireless transceivers. The MSWs may be configured to switch based on the on−chip reconfigurable pulse −width modulator (PWM).

http://onsemi.com The PWM On/Off duty cycle time can be configured by the application allowing the MSWs to act as a power regulator. ARM Cortex−M3 Processor The ARM Cortex −M3 processor is a 32 −bit RISC controller specifically designed to meet the needs of advanced, high−performance, low−power applications. The ARM Cortex −M3 processor provides outstanding computational performance and exceptional system response to interrupts while providing small core footprint, industry leading code density enabling smaller memories, reduced pin count and low power consumption. The Q32M210 implementation of the ARM Cortex−M3 Processor contains all necessary peripherals and bus systems to provide a complete device optimized for battery powered sensor interface applications. Memories Flash Memory 256 kB flash is available for storage of application code and data. Flash memory can be written one or more words at a time. Each page must be erased between writes to a flash word. The flash memory can be erased as a set all at once or in individual 2 kB pages. An additional reserved block of flash memory is used to store factory calibration information provided by ON Semiconductor. This block can not be written by the application. The ARM Cortex −M3 processor executes application code directly from flash with zero wait states. Flash Error Checking and Correction A dedicated hardware block performs real −time error checking and correction of the flash. Additional parity bits are stored automatically for each word in the flash. The hardware ECC is able to detect up to 2−bit errors per word or detect and correct 1 −bit error per word. The hardware ECC operates as each word is read from the flash. An interrupt can be generated upon correction of a bit error and a bus fault will be generated when a bit error is detected, but cannot be corrected. SRAM 48 kB of low −power SRAM is available for storage of intermediate data as well as application code. ROM An on−chip ROM includes boot functionality as well as firmware routines supporting writing to flash in an application. External Interrupt Controller Eight configurable external interrupt sources may be connected to any eight GPIO pins on the device. This is in addition to a dedicated interrupt for the wakeup controller. Each interrupt may be individually configured for positive edge triggering, negative edge triggering, high level triggering, or low level triggering. A dedicated non −maskable interrupt (NMI) pin is connected directly to the ARM Cortex −M3 Processor. A logic high level on this pin will trigger the interrupt handler for the NMI. DMA A flexible DMA unit supports low overhead data exchange between system blocks. Memory−to−Peripheral, Peripheral−to−Memory , and Memory−to−Memory modes are available. Four simultaneous DMA channels can be established with configurable sources and sinks. The DMA can be used with the UART, SPI, SQI, I 2C, USB, and PCM interfaces, as well as the ADCs and DACs. The DMA operates in the background allowing the ARM Cortex−M3 Processor to execute other applications or to reduce its operating frequency to conserve power. General−Purpose Timers The device contains four general −purpose timers. Each timer features a 12 −bit countdown mode, an external interrupt to the ARM Cortex −M3 Processor, a dedicated prescaler, and the ability to poll the counter value. These four general−purpose timers are in addition to the 24 −bit SYSTICK timer included as part of the ARM Cortex −M3 Processor. CRC Engine A 16−bit hardware CRC engine is available. The CRC engine may be used to ensure data integrity of application code and data. The CRC engine’s input port and output port are directly accessible from the ARM Cortex−M3 Processor. The starting vector may be set to any value. Subsequently, data words of multiple bit lengths can be added to the CRC. The 16−bit CRC−CCITT polynomial is used. Watchdog Timer The device contains a digital watchdog timer. The watchdog timer is intended to prevent an indefinite system hang when an application error occurs. The application must periodically refresh the watchdog counter during operation. If a watchdog timeout occurs an initial alert interrupt is generated. If a subsequent watchdog timeout occurs, a system reset is generated. The initial alert may be used to gracefully shut down the system. Dual UART Two general−purpose UART interfaces are available. The UARTs support the standard RS232 protocol and baud rates at the VDDIO0 voltage level. The UART format is fixed at one start bit, eight data bits, and one stop bit. The baud rate is configurable over a wide range of baud rates up to 250 kbaud using a 1 MHz source clock. The UART interfaces may be used either directly from the ARM Cortex −M3 Processor or through the DMA Controller.

http://onsemi.com Dual SPI Two SPI interfaces are available supporting both master and slave operation. Each synchronous 4 −wire interface provides a clock, chip select, serial data in, and serial data out connection. The SPI interface can be used to interface with external devices such as non −volatile memories, displays, and wireless transceivers. The SPI interfaces can be used either directly from the ARM Cortex−M3 Processor or through the DMA Controller SQI The primary SPI interface can be configured to operate in SQI (serial quad interface) mode. In SQI mode 4 bits are interchanged simultaneously instead of 1 bit in SPI mode. In this way, the throughput of the interface is increased by a factor of 4 for the same clock frequency. The SQI interface is typically used to access large, external NVM arrays. I2C The I 2C interface supports both master and slave operation. The interface operates at normal speed (100 kbit/sec) and high speed (400 kbit/sec). On −chip pull−up resistors are available on the SDA and SCL pins. The I 2C interface can be used either directly from the ARM Cortex −M3 Processor or through the DMA Controller. The I2C slave address is programmable by the application. PCM The pulse−code modulation (PCM) interface provides a data connection between the device and external devices such as Bluetooth or audio processors. The PCM interface can operate both in master and slave mode. The master device of a PCM transfer generates the frame signal. The PCM interface can be used either directly from the ARM Cortex−M3 Processor or through the DMA controller. Two DMA channels are used with the PCM interface – one for RX, and one for TX. The PCM interface supports a wide variety of interface protocols by reconfiguring the frame type and width, word size and clock polarities. The PCM interface supports the I2S data format directly for connecting to an I2S compatible audio device. Audio data can be streamed to and from the audio device over the PCM interface in I2S mode. GPIO GPIO pins can be configured as input or output signals. The pins are powered from VDDIO0, VDDIO1, or VBA TA providing flexibility in the I/O voltage levels available. Different I/O voltage levels may be supplied to VDDIO0 and VDDIO1 within the normal operating range. GPIO functionality is shared with alternate functions on most GPIO pins. The GPIO or alternate function is selected through the application. USB The USB interface provides connectivity between the ARM Cortex −M3 Processor and a USB host. The USB interface operates as a USB Full Speed Device (12 Mbit/sec). The USB physical interface (PHY) is powered directly from VDDUSB. A minimum supply of 3 V is required. Typically VDDUSB will be powered from the +5 V provided by the USB bus regulated down to 3.3 V . The interface requires a 48 MHz clock which is provided through the USB crystal oscillator. An external 48 MHz crystal is required for this interface to operate. The USB interface operates on a separate clock domain allowing the rest of the system to continue to run on the slower internal oscillator or external clock source. This enables reduced power consumption, since the ARM Cortex−M3 Processor can operate at a lower frequency than the USB clock when USB is operational. The USB interface interfaces to the ARM Cortex −M3 Processor through memory −mapped control registers and interrupts. The DMA may be used to transfer data between the USB interface and the SRAM directly. LCD The device provides an on −chip LCD driver capable of driving up to 112 display segments of a 1/3 bias, 1/4 duty cycle LCD display. The interface consists of four common (COM) lines and twenty −eight (28) segment (SEG) lines. The drive voltages are sourced from VLCD and consist of four voltages (0 V , 1/3 x VLCD, 2/3 x VLCD, and VLCD). LCD Backlight The LCD backlight driver provides an application controlled current sink. It is programmable to sink nominally between 0 mA to 10 mA. An LCD backlight may be connected between VDBL and ILV . The current passing through the LED is regulated based on the current setting set by the application. JTAG The device contains a dedicated JTAG port for interfacing to the ARM Cortex −M3 Processor and memories. The device implements the standard JTAG −DP protocol provided by ARM, providing compatibility with many external debugging systems.

Figure 2. Pin Definition and Descriptions

Table 1. PIN DEFINITIONS

  1. Types: D – Digital, M – Mixed signal, A – Analog, S – Supply
  2. Direction: I − Input, O – Output, I/O – Input or Output
  3. PU – Pull −up, PD – Pull−down. Most Pull−up and Pull−downs may be disconnected in firmware
  4. Primary function is the power −on default. Alternate functions may be selected in firmware
  5. TEST must be connected to VSS for proper device operation
  6. All pins with the same name must be shorted together for proper device operation
  7. IF5.0 can be used as an analog external input to programmable gain amplifiers
  1. Types: D – Digital, M – Mixed signal, A – Analog, S – Supply
  2. Direction: I − Input, O – Output, I/O – Input or Output
  3. PU – Pull −up, PD – Pull−down. Most Pull−up and Pull−downs may be disconnected in firmware
  4. Primary function is the power −on default. Alternate functions may be selected in firmware
  5. TEST must be connected to VSS for proper device operation
  6. All pins with the same name must be shorted together for proper device operation
  7. IF5.0 can be used as an analog external input to programmable gain amplifiers
  1. Types: D – Digital, M – Mixed signal, A – Analog, S – Supply
  2. Direction: I − Input, O – Output, I/O – Input or Output
  3. PU – Pull −up, PD – Pull−down. Most Pull−up and Pull−downs may be disconnected in firmware
  4. Primary function is the power −on default. Alternate functions may be selected in firmware
  5. TEST must be connected to VSS for proper device operation
  6. All pins with the same name must be shorted together for proper device operation
  7. IF5.0 can be used as an analog external input to programmable gain amplifiers
  1. Types: D – Digital, M – Mixed signal, A – Analog, S – Supply
  2. Direction: I − Input, O – Output, I/O – Input or Output
  3. PU – Pull −up, PD – Pull−down. Most Pull−up and Pull−downs may be disconnected in firmware
  4. Primary function is the power −on default. Alternate functions may be selected in firmware
  5. TEST must be connected to VSS for proper device operation
  6. All pins with the same name must be shorted together for proper device operation
  7. IF5.0 can be used as an analog external input to programmable gain amplifiers

Table 2. DETAILED PIN DESCRIPTIONS

components are required to ensure proper device operation and performance. Table 3. REQUIRED AND RECOMMENDED EXTERNAL CONNECTIONS AND COMPONENTS Table 4. ABSOLUTE MAXIMUM RATINGS

Table 5. RECOMMENDED OPERATING CONDITIONS Table 6. ESD AND LATCH−UP CHARACTERISTICS

  1. Characteristics are obtained through device qualification and characterization and not tested in production

Table 7. NORMAL OPERATION CONFIGURATION Table 8. SYSTEM (Typical operating conditions (Ta = 25°C, VBAT = VBATA = 3.3 V, VDDIO0 = VDDIO1 = VDDD, 16−bit/32−bit mixed

  1. VBAT powers the VDDD regulator (for the digital core, peripherals, internal oscillator), VCP regulator (for the charge−pump)
  2. VDDIO0 powers I2C (SCL, SDA), IF0, IF1, IF2, IF3, NMI, RSTB, EXTCLK, JTAG

(16−bit or 32−bit), program and data storage in flash or SRAM).

Table 9. DIGITAL I/O PINS (IF0, IF1, IF2, IF3, JTAG, EXTCLK, RSTB, NMI, SCL, SDA) Table 10. LCD I/O PINS (IF4) (Typical operating conditions (Ta = 25°C, VDDIO1 = VBAT, GPIO Mode, Pull−up / Pull−down Enabled)

Table 11. WAKEUP I/O PINS (IF5) (Typical operating conditions (Ta = 25°C, Pull−up / Pull−down Enabled, GPIO mode) unless Table 12. USB I/O (USBD+, USBD−) (Typical operating conditions (Ta = 25°C, Full−speed Mode, VDDUSB = 3.3 V) unless

Table 13. FLASH MEMORY Table 14. SPI Table 15. I2C Table 16. PCM

Table 17. LCD (IF4, VLCD1, VLCD0, ILV) (Typical operating conditions (Ta = 25°C, VBATA = 3.3 V, VLCD = VDDIO1 = 3.5 V), Table 18. DACs (DAC0, DAC1, DAC2) (Typical operating conditions (Ta = 25°C, VBATA = 3.3 V, DAC0 Mode 1, Code Range = 200

Table 19. INTERNAL OSCILLATOR (Typical operating conditions (Ta = 25°C, VBAT = 3.3 V, Frequency = 3.0 MHz), unless

Table 20. REAL−TIME CLOCK (Typical operating conditions (Ta = 25°C, VBAT = 3.3 V), unless otherwise noted. • denotes Table 21. USB CLOCK (Typical operating conditions (Ta = 25°C, VBAT = 3.3 V), unless otherwise noted. • denotes characterized Table 22. SWITCHES (SPST0, SPST1, SPST2, SPST3, ALT0, ALT1, MSW0, MSW1, MSW2, MSW3, IN0, IN1, IN2, IN3,

Table 23. POWER SUPERVISOR (Typical operating conditions (Ta = 25°C), unless otherwise noted. • denotes characterized over first user instruction in flash. The actual wakeup time will be affected by the number of entries in the NVIC table for the application. Table 24. VDDD DIGITAL SUPPLY REGULATOR (Typical operating conditions (Ta = 25°C, VBAT = 3.3 V), unless otherwise Table 25. VADC ANALOG SUPPLY REGULATOR (Typical operating conditions (Ta = 25°C, VBATA = 3.3 V, No load), unless

Table 26. VCP CHARGE PUMP SUPPLY REGULATOR (Typical operating conditions (Ta = 25°C, VBAT = 3.3 V, No load), unless

  • 2 mV/mA Power Supply Rejection Ratio PSRR DC 60 dB 1 kHz 60 Start−up time Within 0.1% of final value 500 /C0109sec

Table 27. VDBL CHARGE PUMP (Typical operating conditions (Ta = 25°C, VBATA = 3.3 V, No load, CP_CLK = 125 kHz), unless Characteristics plot for more information.

Table 28. VREF PRECISION VOLTAGE REFERENCE (Typical operating conditions (Ta = 25°C, VBATA = 3.3 V, No load), unless Table 29. OPAMPS (A0, A1, A2) (Typical operating conditions (Ta = 25°C, VBATA = 3.3 V, Unity gain, VCM = VBATA/2) unless

Table 30. ADCs (PGA0 and ADC0, PGA1 and ADC1)

Table 31. PGA0 VOLTAGE COMPARATOR Table 32. TEMPERATURE SENSOR

Figure 16. DAC INL vs. Input Code Figure 17. DAC DNL vs. Input Code

0.4 T = 25°C

Figure 18. DAC Low Code Behavior Figure 19. Temperature Sensor vs.

Figure 25. Clocking

Figure 26. Sensor Interface A0_IN0 through A0_IN2 to be connected to the ALT0 pin. connected to the negative terminal of opamp A0. power supplies, voltage references, and other system blocks. 0.7 V . The output swings to a maximum of VBATA−50 mV . or spikes that may appear on the power supply.

Figure 27. Dual PGAs +ADCs

  • VSS – Ground
  • VBA T/2 – Battery voltage divided by 2
  • VBA TA/2 – Battery voltage for sensor interface divided by 2
  • VREF – Precision voltage reference
  • V ADC/2 – V ADC Analog Supply Regulator voltage divided by 2
  • A0_OUT – Output of opamp A0
  • A1_OUT – Output of opamp A1
  • A2_OUT – Output of opamp A2
  • A0_REF – Positive terminal input of opamp A0
  • A1_REF – Positive terminal input of opamp A1
  • A2_REF – Positive terminal input of opamp A2
  • VWAKEUP – V oltage from IF5.0
  • VTS – Temperature sensor voltage reading
  • AUX_IN0 – Auxiliary input 0
  • AUX_IN1 – Auxiliary input 1
  • AUX_IN2 – Auxiliary input 2 The MUX selects two of the inputs for Va and Vb (the inputs to PGA Input A and PGA Input B, respectively). The output of the PGA is the differential voltage between Va and Vb with a selectable gain applied. In many sensor configurations it is desirable to select Va as the output of an opamp, and Vb as the corresponding positive terminal input of the same opamp. The output of the PGA in this configuration is the difference in voltage between the opamp positive terminal input and output which is directly related to the sensor impedance and external feedback resistor value. The Vb bias voltage is subtraced off resulting in a net differential voltage of 0 V when the sensor impedance is high. The PGA is equipped with an anti −aliasing filter. An internal resistance coupled with an external capacitor applied to the AAF pin creates a first order low−pass filter. The −3 dB cut−off frequency is programmable to allow for flexible bandwidth of the PGA output. The bandwidth may be adjusted by reconfiguring the internal resistance and selecting the appropriate AAF capacitor. The ADC has a resolution of 16−bits with an input voltage range between 0 V and 1.8 V . The ADC operates by oversampling the PGA output voltage to reduce noise and to obtain superior linearity. The reference voltage for conversions is the on −chip VREF Precision V oltage Reference at 0.9 V . The selection of the number format is configured by the application. The output number format of the ADC can be mapped in two ways:
  1. 2’s Complement – A 0 V input corresponds to

0x8000, and a maximum input results in 0x7FFF.

  1. Unsigned – A 0 V input corresponds to 0x0000,

and a maximum input results in 0xFFFF. obtained by reconfiguring the ADC clock and configuration. frequencies (50/60 Hz) at this rate. in the signal dynamic range. ensure adequate filtering and signal bandwidth. is connected to a hardware gain and offset correction unit. automatically adjusted by these factors. for a specific voltage level to occur. Figure 28. Triple DACs opamps and auxiliary analog inputs. resolution per LSB but the largest output range.

Figure 33. Entering Standby Mode

Figure 34. Glucose Meter Application

http://onsemi.com Table 33. Symbol Description Suggested Part Number(s) Recom- mended Value Unit Toler- ance CVREF VREF filtering capacitor 0805 Taiyo Yuden JMK21213J226MG−T 22 /C0109F ± 20% CVDDD VDDD regulator filtering capacitor 0805 Panasonic ECJ−2FB0J226M 22 /C0109F ± 20% CLCD VLCD filtering capacitor 0603 Taiyo Yuden LMK107B7105KA−T 1 /C0109F ± 10% CLCD1 VLCD1 filtering capacitor 0402 Panasonic ECJ−0EB1H102K 1 nF ± 10% CLCD0 VLCD0 filtering capacitor 0402 Panasonic ECJ−0EB1H102K 1 nF ± 10% CVADC VADC regulator filtering capacitor 0805 Taiyo Yuden JMK21213J226MG−T 22 /C0109F ± 20% CVDBL Charge pump output filtering capacitor

0603 Taiyo Yuden JMK107BJ106MA−T 10 /C0109F ± 20%

CPUMP Charge pump capacitor 0603 Taiyo Yuden LMK107B7105KA−T 1 /C0109F ± 10% CVCP Charge pump regulated output filtering capacitor

0805 Taiyo Yuden JMK21213J226MG−T 22 /C0109F ± 20%

CVBAT VBAT supply filtering capacitor 0805 Taiyo Yuden JMK21213J226MG−T 22 /C0109F ± 20% RFB Feedback resistor for transimpedance amplifier Application specific RCAL Calibration resistor for transimpedance amplifier Application specific CAAF0 Anti−aliasing filter capacitor 0603 Taiyo Yuden LMK107B7105KA−T 1 /C0109F ± 10% CBACKLIGHT LED Backlight capacitor 0603 Taiyo Yuden LMK107B7105KA−T 1 /C0109F ± 20% USB_XTAL USB Crystal (optional – only required for USB operation) Abracon ABM10−48.000MHZ−E20−T NDK1612AA−48.000M

48 MHz ± 20 ppm

RTC_XTAL RTC Crystal ABRACON ABS07−32.768KHZ−9−T 32.768 kHz ± 20 ppm E2 EEPROM (optional) CAT24C16 16 kbit EEPROM CAT24C32 32 kbit EEPROM CAT24C64 64 kbit EEPROM CAT24C128 128 kbit EEPROM CAT24C256 256 kbit EEPROM RTEMP Fixed value resistor for external temperature sensing Panasonic ERJ−3EKF2003V 200 k/C0087± 1% RTHERM Thermistor for external temperature sensing Application specific RIREF Resistor for current reference Vishay Dale CRCW0402300KFKED 300 k/C0087± 1% ESD0 ESD Protection Diode ON Semiconductor ESD9L3.3ST5G 15 kV (IEC 61000−4−2) ESD1 ESD Protection Diode ON Semiconductor ESD9L3.3ST5G 15 kV IEC 61000−4−2) ESD2 ESD Protection Diode ON Semiconductor ESD9L3.3ST5G 15 kV (IEC 61000−4−2) ESD3 ESD Protection Diode ON Semiconductor ESD9L3.3ST5G 15 kV (IEC 61000−4−2) ESD4 ESD Protection Diode ON Semiconductor ESD9L3.3ST5G 15 kV (IEC 61000−4−2) ESD5 ESD Protection Diode ON Semiconductor ESD9L3.3ST5G 15 kV (IEC 61000−4−2)

Figure 35. USB Application Table 34. USB APPLICATION CONFIGURATION

0805 Taiyo Yuden JMK21213J226MG-T 22 /C0109F ± 20%

Q32M210 with the supplied sample applications. Kit/C0116 software release (included) for evaluation purposes. /C0109C/USB/C0116 software stack product from partner Micrium.

http://onsemi.com PACKAGE DIMENSIONS ÉÉÉ ÉÉÉ ÉÉÉ TLLGA140 10x10, 0.5P , Dual−Row, Staggered−Pad CASE 513AL−01 ISSUE O C0.15 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS 3. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. AD E B C0.08 A D2 L C0.15 SEATING C0.10 C 140X e B17 A20 A39 B33 B49 A58 b140X A0.10 BC 0.05 C DIM MIN MAX MILLIMETERS A 0.50 0.60 A1 --- 0.05 b 0.25 0.35 D 10.00 BSC D2 5.70 5.90 E 10.00 BSC E2 5.70 5.90 e 0.50 BSC L 0.25 0.35 PIN ONE LOCATION PLANE NOTE 3 TOP VIEW SIDE VIEW BOTTOM VIEW DETAIL A 140X L A39 B33 140X b e e e/2 DIMENSION: MILLIMETERS 10.10 0.50 PITCH 40X 0.48 100X 0.35 40X 0.480.25 100X 0.35 10.10 5.95 5.95 0.50 PITCH *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* RECOMMENDED A1 A76 B64 A0.15 BC A0.15 BC e/2 DETAIL A

Table 35. TAPE & REEL INFORMATION Table 36. ORDERING INFORMATION degradation or loss of functionality. products or services visit our web site at http://onsemi.com. arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. ARM is the registered trademark and Cortex is the trademark of ARM limited in the EU and other countries.