PZ3032 PHILIPS | Alldatasheet
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/C0109 /C0110 /C0114 PZ3032 32 macrocell CPLD Product specification 1997 Feb 20 INTEGRATED CIRCUITS IC27 Data Handbook
Philips Semiconductors Product specification PZ303232 macrocell CPLD
21997 Feb 20 853–1852 17780
FEATURES
- Industry’s first TotalCMOS PLD – both CMOS design and process technologies
- Fast Zero Power (FZP ) design technique provides ultra-low power and very high speed
- High speed pin-to-pin delays of 8ns
- Ultra-low static power of less than 35µA
- Dynamic power that is 70% lower at 50MHz than competing devices
- 100% routable with 100% utilization while all pins and all macrocells are fixed
- Deterministic timing model that is extremely simple to use
- 2 clocks with programmable polarity at every macrocell
- Support for complex asynchronous clocking
- Innovative XPLA architecture combines high speed with extreme flexibility
- 1000 erase/program cycles guaranteed
- 20 years data retention guaranteed
- Logic expandable to 37 product terms
- PCI compliant
- Advanced 0.5µ E2CMOS process
- Security bit prevents unauthorized access
- Design entry and verification using industry standard and Philips CAE tools
- Reprogrammable using industry standard device programmers
- Innovative Control Term structure provides either sum terms or product terms in each logic block for: – Programmable 3-State buffer – Asynchronous macrocell register preset/reset
- Programmable global 3-State pin facilitates ‘bed of nails’ testing without using logic resources
- Available in both PLCC and TQFP packages
Table 1. PZ3032 Features
DESCRIPTION
The PZ3032 CPLD (Complex Programmable Logic Device) is the first in a family of Fast Zero Power (FZP ) CPLDs from Philips Semiconductors. These devices combine high speed and zero power in a 32 macrocell CPLD. With the FZP design technique, the PZ3032 offers true pin-to-pin speeds of 8ns, while simultaneously delivering power that is less than 35µA at standby without the need for ‘turbo bits’ or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any competing CPLD – 70% lower at 50MHz. These devices are the first TotalCMOS PLDs, as they use both a CMOS process technology and the patented full CMOS FZP design technique. For 5V applications, Philips also offers the high speed PZ5032 CPLD that offers pin-to-pin speeds of 6ns. The Philips FZP CPLDs introduce the new patent-pending XPLA (eXtended Programmable Logic Array) architecture. The XPLA architecture combines the best features of both PLA and PAL type structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. The XPLA structure in each logic block provides a fast 8ns PAL path with 5 dedicated product terms per output. This PAL path is joined by an additional PLA structure that deploys a pool of 32 product terms to a fully programmable OR array that can allocate the PLA product terms to any output in the logic block. This combination allows logic to be allocated efficiently throughout the logic block and supports as many as 37 product terms on an output. The speed with which logic is allocated from the PLA array to an output is only 2.5ns, regardless of the number of PLA product terms used, which results in worst case t PD ’s of only 10.5ns from any pin to any other pin. In addition, logic that is common to multiple outputs can be placed on a single PLA product term and shared across multiple outputs via the OR array, effectively increasing design density. The PZ3032 CPLDs are supported by industry standard CAE tools (Cadence, Mentor, Synopsys, Synario, Viewlogic, OrCAD), using text (Abel, VHDL, Verilog) and/or schematic entry. Design verification uses industry standard simulators for functional and timing simulation. Development is supported on personal computer, Sparc, and HP platforms. Device fitting uses either Minc or Philips Semiconductors-developed tools. The PZ3032 CPLD is reprogrammable using industry standard device programmers from vendors such as Data I/O, BP Microsystems, SMS, and others. PAL is a registered trademark of Advanced Micro Devices, Inc.
Philips Semiconductors Product specification PZ303232 macrocell CPLD
1997 Feb 20 3
ORDERING INFORMATION
ORDER CODE DESCRIPTION DESCRIPTION DRAWING NUMBER PZ3032–8A44 44-pin PLCC, 8ns tPD Commercial temp range, 3.3 volt power supply, ± 10% SOT187-2 PZ3032–10A44 44-pin PLCC, 10ns tPD Commercial temp range, 3.3 volt power supply, ± 10% SOT187-2 PZ3032–12A44 44-pin PLCC, 12ns tPD Commercial temp range, 3.3 volt power supply, ± 10% SOT187-2 PZ3032I10A44 44-pin PLCC, 10ns tPD Industrial temp range, 3.3 volt power supply, ± 10% SOT187-2 PZ3032I12A44 44-pin PLCC, 12ns tPD Industrial temp range, 3.3 volt power supply, ± 10% SOT187-2 PZ3032–8BC 44-pin TQFP, 8ns tPD , Commercial temp range, 3.3 volt power supply, ± 10% SOT376-1 PZ3032–10BC 44-pin TQFP, 10ns tPD Commercial temp range, 3.3 volt power supply, ± 10% SOT376-1 PZ3032–12BC 44-pin TQFP, 12ns tPD Commercial temp range, 3.3 volt power supply, ± 10% SOT376-1 PZ3032I10BC 44-pin TQFP, 10ns tPD Industrial temp range, 3.3 volt power supply, ± 10% SOT376-1 PZ3032I12BC 44-pin TQFP, 12ns tPD Industrial temp range, 3.3 volt power supply, ± 10% SOT376-1 XPLA ARCHITECTURE Figure 1 shows a high level block diagram of a 64 macrocell device implementing the XPLA architecture. The XPLA architecture consists of logic blocks that are interconnected by a Zero-power Interconnect Array (ZIA). The ZIA is a virtual crosspoint switch. Each logic block is essentially a 36V16 device with 36 inputs from the ZIA and 16 macrocells. Each logic block also provides 32 ZIA feedback paths from the macrocells and I/O pins. From this point of view, this architecture looks like many other CPLD architectures. What makes the CoolRunner family unique is what is inside each logic block and the design technique used to implement these logic blocks. The contents of the logic block will be described next. Logic Block Architecture Figure 2 illustrates the logic block architecture. Each logic block contains control terms, a PAL array, a PLA array, and 16 macrocells. The 6 control terms can individually be configured as either SUM or PRODUCT terms, and are used to control the preset/reset and output enables of the 16 macrocells’ flip-flops. The PAL array consists of a programmable AND array with a fixed OR array, while the PLA array consists of a programmable AND array with a programmable OR array. The PAL array provides a high speed path through the array, while the PLA array provides increased product term density. Each macrocell has 5 dedicated product terms from the PAL array. The pin-to-pin t PD of the PZ3032 device through the PAL array is 8ns. This performance is the fastest 3 volt CPLD available today. If a macrocell needs more than 5 product terms, it simply gets the additional product terms from the PLA array. The PLA array consists of 32 product terms, which are available for use by all 16 macrocells. The additional propagation delay incurred by a macrocell using 1 or all 32 PLA product terms is just 2.5ns. So the total pin-to-pin t PD for the PZ3032 using 6 to 37 product terms is 10.5ns (8ns for the PAL + 2.5ns for the PLA). LOGIC BLOCKI/O MC0 MC1 MC15 I/O MC0 MC1 MC15 LOGIC BLOCKI/O MC0 MC1 MC15 I/O MC0 MC1 MC15 SP00439 ZIA LOGIC BLOCK LOGIC BLOCK Figure 1. Philips XPLA CPLD Architecture
1997 Feb 20 4
36 ZIA INPUTS
Figure 2. Philips Logic Block Architecture
1997 Feb 20 5
asynchronous clock (driven by a macrocell equation). Testing” or “Bed-of-Nails Testing”. Figure 3. PZ3032 Macrocell Architecture
1997 Feb 20 6
there are three main timing parameters, including tPD , tSU , and tCO . account for the time to propagate through the PLA array. vs. Frequency of our PZ3032 TotalCMOS CPLD. Figure 4. CoolRunner Timing Model Figure 5. IDD vs. Frequency @ VDD = 3.3V Table 2. IDD vs Frequency
Philips Semiconductors Product specification PZ303232 macrocell CPLD
1997 Feb 20 7
ABSOLUTE MAXIMUM RATINGS 1 SYMBOL PARAMETER MIN. MAX. UNIT VDD Supply voltage –0.5 7.0 V VI Input voltage –1.2 VDD +0.5 V VOUT Output voltage –0.5 VDD +0.5 V IIN Input current –30 30 mA IOUT Output current –100 100 mA TJ Maximum junction temperature –40 150 °C Tstr Storage temperature –65 150 °C NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification is not implied. OPERATING RANGE PRODUCT GRADE TEMPERATURE VOLTAGE Commercial 0 to +70°C 3.3 ±10% V Industrial –40 to +85°C 3.3 ±10% V
Philips Semiconductors Product specification PZ303232 macrocell CPLD
1997 Feb 20 8
DC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES Commercial: 0°C ≤ Tamb ≤ +70°C; 3.0V ≤ VDD ≤ 3.6V SYMBOL PARAMETER TEST CONDITIONS MIN. MAX. UNIT VIL Input voltage low VDD = 3.0V 0.8 V VIH Input voltage high VDD = 3.6V 2.0 V VI Input clamp voltage VDD = 3.0V, IIN = –18mA –1.2 V VOL Output voltage low VDD = 3.0V, IOL = 8mA 0.5 V VOH Output voltage high VDD = 3.0V, IOH = –8mA 2.4 V IIL Input leakage current low VDD = 3.6V (except CKO), VIN = 0V –10 10 µA IIH Input leakage current high VDD = 3.6V, VIN = 3.0V –10 10 µA IIL Clock input leakage current VDD = 3.6V, VIN = 0.4V –10 10 µA IOZL 3-Stated output leakage current low VDD = 3.6V, VIN = 0.4V –10 10 µA IOZH 3-Stated output leakage current high VDD = 3.6V, VIN = 3.0V –10 10 µA IDDQ Standby current VDD = 3.6V, Tamb = 0°C 35 µA IDDD 1 Dynamic current VDD = 3.6V, Tamb = 0°C @ 1MHz 0.5 mAIDDD 1 Dynamic current VDD = 3.6V, Tamb = 0°C @ 50MHz 18 mA IOS Short circuit output current 1 pin at a time for no longer than 1 second–5 –100 mA C IN Input pin capacitance Tamb = 25°C, f = 1MHz 8 pF C CLK Clock input capacitance Tamb = 25°C, f = 1MHz 5 12 pF C I/O I/O pin capacitance Tamb = 25°C, f = 1MHz 10 pF NOTE: 1. This parameter measured with a 16–bit, loadable up/down counter loaded into every logic block, with all outputs enabled and unloaded. Inputs are tied to VDD or ground. This parameter guaranteed by design and characterization, not testing. AC ELECTRICAL CHARACTERISTICS 1 FOR COMMERCIAL GRADE DEVICES Commercial: 0°C ≤ Tamb ≤ +70°C; 3.0V ≤ VDD ≤ 3.6V SYMBOL PARAMETER –8 –10 –12 UNITSYMBOL PARAMETER UNIT tPD_PAL Propagation delay time, input (or feedback node) to output through PAL2 8 2 10 2 12 ns tPD_PLA Propagation delay time, input (or feedback node) to output through PAL & PLA3 10.5 3 13 3 15 ns tCO Clock to out delay time 2 7 2 9 2 11 ns tSU_PAL Setup time (from input or feedback node) through PAL 6.5 8.5 10.5 ns tSU_PLA Setup time (from input or feedback node) through PAL + PLA 9 11.5 13.5 ns tH Hold time 0 0 0 ns tCH Clock High time 3 4 5 ns tCL Clock Low time 3 4 5 ns tR Input rise time 20 20 20 ns tF Input fall time 20 20 20 ns fMAX1 Maximum FF toggle rate2 (1/tCH + tCL ) 167 125 100 MHz fMAX2 Maximum internal frequency2 (1/tSUPAL + tCF ) 83 63 50 MHz fMAX3 Maximum external frequency2 (1/tSUPAL + tCO ) 74 57 47 MHz tBUF Output buffer delay time 1.5 1.5 1.5 ns tPDF_PAL Input (or feedback node) to internal feedback node delay time through PAL6.5 8.5 10.5 ns tPDF_PLA Input (or feedback node) to internal feedback node delay time through PAL + PLA9 11.5 13.5 ns tCF Clock to internal feedback node delay time 5.5 7.5 9.5 ns tINIT Delay from valid VDD to valid reset 50 50 50 µs tER Input to output disable3 15 17 19 ns tEA Input to output valid 15 17 19 ns tRP Input to register preset 16 18 20 ns tRR Input to register reset 19 21 23 ns NOTES: 1. Specifications measured with one output switching. See Figure 6 and Table 3 for derating. 2. This parameter guaranteed by design and characterization, not by test. 3. Output C L = 5pF.
Philips Semiconductors Product specification PZ303232 macrocell CPLD
1997 Feb 20 9
DC ELECTRICAL CHARACTERISTICS FOR INDUSTRIAL GRADE DEVICES Industrial: –40°C ≤ Tamb ≤ +85°C; 3.0V ≤ VDD ≤ 3.6V SYMBOL PARAMETER TEST CONDITIONS MIN. MAX. UNIT VIL Input voltage low VDD = 3.0V 0.8 V VIH Input voltage high VDD = 3.6V 2.0 V VI Input clamp voltage VDD = 3.0V, IIN = –18mA –1.2 V VOL Output voltage low VDD = 3.0V, IOL = 8mA 0.5 V VOH Output voltage high VDD = 3.0V, IOH = –8mA 2.4 V IIL Input leakage current low VDD = 3.6V (except CKO), VIN = 0.4V –10 10 µA IIH Input leakage current high VDD = 3.6V, VIN = 3.0V –10 10 µA IIL Clock input leakage current VDD = 3.6V, VIN = 0.4V –10 10 µA IOZL 3-Stated output leakage current low VDD = 3.6V, VIN = 0.4V –10 10 µA IOZH 3-Stated output leakage current high VDD = 3.6V, VIN = 3.0V –10 10 µA IDDQ Standby current VDD = 3.6V, Tamb = –40°C 45 µA IDDD 1 Dynamic current VDD = 3.6V, Tamb = –40°C @ 1MHz 0.5 mAIDDD 1 Dynamic current VDD = 3.6V, Tamb = –40°C @ 50MHz 18 mA IOS Short circuit output current 1 pin at a time for no longer than 1 second–5 –120 mA C IN Input pin capacitance Tamb = 25°C, f = 1MHz 8 pF C CLK Clock input capacitance Tamb = 25°C, f = 1MHz 5 12 pF C I/O I/O pin capacitance Tamb = 25°C, f = 1MHz 10 pF NOTE: 1. This parameter measured with a 16–bit, loadable up/down counter loaded into every logic block, with all outputs enabled and unloaded. Inputs are tied to VDD or ground. This parameter guaranteed by design and characterization, not testing. AC ELECTRICAL CHARACTERISTICS 1 FOR INDUSTRIAL GRADE DEVICES Industrial: –40°C ≤ Tamb ≤ +85°C; 3.0V ≤ VDD ≤ 3.6V SYMBOL PARAMETER I10 I12 UNITSYMBOL PARAMETER MIN. MAX. MIN. MAX. UNIT tPD_PAL Propagation delay time, input (or feedback node) to output through PAL2 10 2 12 ns tPD_PLA Propagation delay time, input (or feedback node) to output through PAL & PLA3 12.5 3 15 ns tCO Clock to out delay time 2 9 2 11 ns tSU_PAL Setup time (from input or feedback node) through PAL 8 10.5 ns tSU_PLA Setup time (from input or feedback node) through PAL + PLA 10.5 13.5 ns tH Hold time 0 0 ns tCH Clock High time 4 5 ns tCL Clock Low time 4 5 ns tR Input rise time 20 20 ns tF Input fall time 20 20 ns fMAX1 Maximum FF toggle rate2 (1/tCH + tCL ) 125 100 MHz fMAX2 Maximum internal frequency2 (1/tSUPAL + tCF ) 64.5 50 MHz fMAX3 Maximum external frequency2 (1/tSUPAL + tCO ) 58.8 47 MHz tBUF Output buffer delay time 1.5 1.5 ns tPDF_PAL Input (or feedback node) to internal feedback node delay time through PAL 8 10.5 ns tPDF_PLA Input (or feedback node) to internal feedback node delay time through PAL + PLA10.5 13.5 ns tCF Clock to internal feedback delay time 7.5 9.5 ns tINIT Delay from valid VDD to valid reset 50 50 µs tER Input to output disable3 16 19 ns tEA Input to output valid 16 19 ns tRP Input to register preset 17 20 ns tRR Input to register reset 20 23 ns NOTES: 1. Specifications measured with one output switching. See Figure 6 and Table 3 for derating. 2. This parameter guaranteed by design and characterization, not by test. 3. Output C L = 5pF.
1997 Feb 20 10
The test load circuit and load values for the AC Electrical Characteristics are illustrated below. measured 0.5V from steady-state active level. Figure 6. tPD_PAL vs. Outputs switching Table 3. tPD_PAL vs. # of Outputs switching inputs and outputs, unless otherwise specified.
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1 IN1
2 IN3
4 I/O–A0–CK1
5 I/O–A1
6 I/O–A2
7 I/O–A3
8 I/O–A4
9 I/O–A5
10 GND
11 I/O–A6
12 I/O–A7
13 I/O–A8
14 I/O–A9
16 I/O–A10
17 I/O–A11
18 I/O–A12
19 I/O–A13
20 I/O–A14
21 I/O–A15
23 V DD
24 I/O–B15
25 I/O–B14
26 I/O–B13
27 I/O–B12
28 I/O–B11
29 I/O–B10
30 GND
31 I/O–B9
32 I/O–B8
33 I/O–B7
34 I/O–B6
36 I/O–B5
37 I/O–B4
38 I/O–B3
39 I/O–B2
40 I/O–B1
41 I/O–B0
42 GND
43 IN0–CK0
44 IN2–gtsn
1 I/O–A3
2 I/O–A4
3 I/O–A5
4 GND
5 I/O–A6
6 I/O–A7
7 I/O–A8
8 I/O–A9
10 I/O–A10
11 I/O–A11
12 I/O–A12
13 I/O–A13
14 I/O–A14
15 I/O–A15
16 GND
18 I/O–B15
19 I/O–B14
20 I/O–B13
21 I/O–B12
22 I/O–B11
23 I/O–B10
24 GND
25 I/O–B9
26 I/O–B8
27 I/O–B7
28 I/O–B6
30 I/O–B5
31 I/O–B4
32 I/O–B3
33 I/O–B2
34 I/O–B1
35 I/O–B0
36 GND
37 IN0/CK0
38 IN2–gtsn
39 IN1
40 IN3
42 I/O–A0–CK1
43 I/O–A1
44 I/O–A2
changes approximately 5% for a 100% change in power. not be similar to the actual circuit board, especially in size. Figure 7. Average Effect of Airflow on Θ JA
Philips Semiconductors Product specification PZ303232 macrocell CPLD
1997 Feb 20 12
PLCC44: plastic leaded chip carrier; 44 leads SOT187-2
Philips Semiconductors Product specification PZ303232 macrocell CPLD
1997 Feb 20 13
TQFP44: plastic thin quad flat package; 44 leads; body 10 x 10 x 1.0 mm SOT376-1
Philips Semiconductors Product specification PZ303232 macrocell CPLD
1997 Feb 20 14
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Preliminary Specification Product Specification Formative or in Design Preproduction Product Full Production This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Copyright Philips Electronics North America Corporation 1997 All rights reserved. Printed in U.S.A. /C0109 /C0110 /C0114