PXTR200DQCR

XTR200 TI | Alldatasheet

Document overview

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Technical content

XTR200 Precision, 3-Wire, Current-and-Voltage Transmitter

1 Features

• Mode pin for selectable current or voltage output – Current output transfer function set by a single external resistor – Voltage output mode has a fixed gain of 3.75V/V
• Integrated output transistor eliminates external components
• Capable of output voltages within 1mV of ground on a single supply
• Wide supply voltage range: 8V to 60V
• Wide specified temperature range: –40°C to +125°C
• Low input offset voltage: ±200μV
• Low input offset voltage drift: ±0.5μV/°C
• Excellent span error (current mode): 0.01%
• Excellent gain error (voltage mode): 0.007%
• Output error flag (EF)
• Output disable (OD)
• Extremely small 3mm × 2mm WSON package

2 Applications

• Position sensor
• Pressure transmitter
• Temperature transmitter
• Flow transmitter
• Analog output module
• AC drive control module
• CPU (PLC controller)
• HVAC valve and actuator control
• Constant-current sensor biasing
• Resistance Temperature Detector (RTD) biasing
• High-side current source

3 Description

The XTR200 is a high-voltage, precision, output driver for 3-wire current or voltage systems, designed for standard industrial signal levels such as 0mA to 20mA, 4mA to 20mA, and 0V to 10V. The mode pin configures the device for either current or voltage output and eliminates the need to change external components to switch between modes. In current- output mode, the ratio between input voltage and output current is set by a single resistor, R SET. In voltage-output mode, the XTR200 has a fixed gain of 3.75V/V which is set by integrated, high-precision, thin-film, resistors. The device integrates a low-leakage PMOS output transistor and short-circuit current protection, further reducing the need for external components. An external PNP or PMOS transistor can be used with the XTR200 to reduce on-chip power dissipation. The on-chip short-circuit protection also protects external transistors from damaging overcurrent events. The XTR200 error flag pin ( EF) indicates several temperature or output fault conditions. The output disable pin (OD) places the output pin into a high- impedance state with very low leakage. The XTR200 is available in a small 3mm × 2mm, 10-pin WSON surface-mount package.

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) XTR200 DQC (WSON, 10) 3mm × 2mm (1) For more information, see Section 10. (2) The package size (length × width) is a nominal value and includes pins, where applicable. DAC VSP GNDSET OUTINPUT MODE EF OD 1.5k 100k 100k IS VG LDO GPIO GPIO GPIO 24V 0-10V 0-20mA 3.3V MSPM0G150x XTR200 Simplified Schematic of XTR200 Used in a Three-Wire Output Circuit XTR200 SBOSAL6A – JUNE 2025 – REVISED SEPTEMBER 2025 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

10 Mechanical, Packaging, and Orderable

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4 Pin Configurations and Functions

Table 4-1. Pin Functions PIN TYPE DESCRIPTION NO. NAME

1 INPUT Input Input voltage

2 MODE Input Selects current output mode (high) or voltage output mode (low)

3 EF Output Error flag (active low)

4 OD Input Output disable (active high)

5 VSP Power Positive supply

6 OUT Output Output current or voltage signal

7 IS Output Source or emitter connection for optional external transistor

8 VG Output Gate or base drive for optional external transistor

9 GND Ground Negative supply

10 SET Input Sets the voltage-to-current transfer ratio

Pad Thermal pad — Connect exposed thermal pad to GND www.ti.com XTR200 SBOSAL6A – JUNE 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: XTR200

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VSP Power supply voltage (referenced to GND pin) GND - 0.5 65 V INPUT, SET Signal input pins Voltage (referenced to GND pin) GND - 0.5 5.5 V Current 10 mA MODE, OD, EF Digital I/O pins Voltage (referenced to GND pin) GND - 0.5 5.5 V Current 10 mA IS, VG, OUT Output pins Voltage (referenced to GND pin) GND - 0.5 VSP + 0.5 V Output pins Output current limit Continuous TJ Operating junction temperature –50 150 °C TA Specified temperature –40 125 °C Tstg Storage temperature –55 125 °C Lead temperature (soldering, 10s) 300 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) 4000 V Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) 1500 (1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Supply voltage, Vs = (V+) – (V–) 8 24 60 V Specified temperature –40 125 °C

5.4 Thermal Information

THERMAL METRIC(1) XTR200 UNIT10 PINS DQC (DFN-10) RθJA Junction-to-ambient thermal resistance 69.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 71.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 13.9 °C/W RθJB Junction-to-board thermal resistance 36.7 °C/W ψJT Junction-to-top characterization parameter 3.1 °C/W ψJB Junction-to-board characterization parameter 36.6 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note . XTR200 SBOSAL6A – JUNE 2025 – REVISED SEPTEMBER 2025 www.ti.com

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5.5 Electrical Characteristics

at TA = 25°C, VSP = 24V, Current-Output Mode: RSET = 1.5kΩ, RL = 250Ω, CL = 10pF, Voltage-Output Mode: RL = 1kΩ, CL = 10pF unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT Input voltage range 0 5 V VOS Input offset voltage ±200 ±800 µV TA = –40°C to +125°C ±1000 dVOS/dT Input offset voltage drift TA = –40°C to +125°C ±0.5 ±3 µV/°C PSRR Power supply rejection ratio ±0.4 ±2 µV/V TA = –40°C to +125°C ±3 IB Input bias current VIN = 3V ±5 pA VIN = 5V TA = –40°C to +105°C 5 nA VIN = 3V TA = –40°C to +125°C 10 nA ZIN Input impedance 50 || 7 GΩ || pF en Input voltage noise density f = 1kHz Current-output mode 53 nV/√Hz Voltage-output mode 34 Input voltage noise f = 0.1Hz to 10Hz Current-output mode 7.6 µVp-p Voltage-output mode 4 In Input current noise density f = 1kHz 3 fA/√Hz CURRENT OUTPUT IOUT Output current equation IOUT = 10 * (VIN / RSET) Output current headroom VSP = 8V IOUT = 25mA 2.2 2.3 V Output current, linear range 0.01 25 mA RO Output resistance 47 GΩ ILEAK Output leakage Output Disabled 0.35 nA TA = –40°C to +125°C 10 dIO/dT Output current drift(1) TA = –40°C to +125°C IOUT = 4mA ±6 ±35 nA/℃ IOUT = 20mA ±15 ±60 Nonlinearity IOUT from 0.1mA to 25mA ±0.001 ±0.003 % Span error(2) IOUT from 0.1mA to 25mA ±0.01 ±0.065 % VSP from 12V to 40V ±0.0001 ±0.0003 %/V Span error drift TA = –40°C to +125°C ±1 ±2 ppm/℃ IOS Offset current(3) VIN = 0V ±2 ±10 µAIOUT = 4mA ±2 ±12 TA = –40°C to +125°C ±14 dIOS/dVS Offset current vs supply IOUT = 4mA VSP from 12V to 40V ±6 ±30 nA/V VOLTAGE OUTPUT VOUT Output voltage equation VOUT = VIN * 3.75 Output voltage headroom VOUT = 10V IOUT = 25mA 2.15 2.3 V Maximum output voltage VIN = 5V 18.75 V Minimum output voltage VIN = 0V 0.4 3 mV TA = –40°C to +125°C 4 Gain error VOUT from 10mV to 10V ±0.007 ±0.04 % Gain error drift TA = –40°C to +125°C ±0.1 ±0.5 ppm/℃ Nonlinearity VOUT from 10mV to 10V ±0.00025 ±0.0006 % ILIM Short circuit current limit 30 40 45 mA TA = –40°C to +125°C 49 www.ti.com XTR200 SBOSAL6A – JUNE 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: XTR200

5.5 Electrical Characteristics (continued)

at TA = 25°C, VSP = 24V, Current-Output Mode: RSET = 1.5kΩ, RL = 250Ω, CL = 10pF, Voltage-Output Mode: RL = 1kΩ, CL = 10pF unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DYNAMIC RESPONSE Small signal bandwidth Current-output mode 3 MHz Voltage-output mode 260 kHz Slew rate Current-output mode 5.5 mA/µs Voltage-output mode 1 V/µs ERROR FLAG Output voltage Logic Low 0.3 0.8 V Logic High 3.15 3.3 4 V Current-sinking capability 3 mA Internal pull-up current 4 µA Thermal warning temperature EF Output Low 145 150 155 ℃ MODE Input logic threshold (high) Current-output mode 1.3 1.65 V Input logic threshold (low) Voltage-output mode 0.8 1.3 V Internal pull-up current 4 µA OUTPUT DISABLE Input logic threshold (high) Output Disabled 1.3 1.65 V Input logic threshold (low) Output Enabled 0.8 1.3 V Internal pullup current 4 µA POWER SUPPLY IQ Quiescent current Current-output mode 325 450 μA TA = –40°C to 125°C 550 (1) Does not include initial error or TCR of RSET. (2) Span is the change in output current resulting from a full-scale change in input voltage (3) Offset current is the deviation from the current ratio of ISET to IOUT XTR200 SBOSAL6A – JUNE 2025 – REVISED SEPTEMBER 2025 www.ti.com

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5.6 Typical Characteristics

at TA = 25°C and VSP = 24V, Current-Output Mode: RSET = 1.5kΩ, RL = 250Ω, CL = 10pF, Voltage-Output Mode: RL = 1kΩ, CL = 10pF (unless otherwise noted) Figure 5-1. Offset Voltage Distribution Figure 5-2. Offset Voltage Drift Distribution Figure 5-3. Span Error Distribution S p a n E r r o r D r i f t ( p p m /  C ) Population (%) 1 0 1 5 2 0 2 5 3 0 3 5 4 0 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 2 Figure 5-4. Span Error Drift Distribution Figure 5-5. Gain Error Distribution G a i n E r r o r D r i f t ( p p m /  C ) Population (%) 1 0 1 5 2 0 2 5 3 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Figure 5-6. Gain Error Drift Distribution www.ti.com XTR200 SBOSAL6A – JUNE 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: XTR200

5.6 Typical Characteristics (continued)

at TA = 25°C and VSP = 24V, Current-Output Mode: RSET = 1.5kΩ, RL = 250Ω, CL = 10pF, Voltage-Output Mode: RL = 1kΩ, CL = 10pF (unless otherwise noted) O u t p u t C u r r e n t D r i f t ( n A /  C ) Population (%) 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 -30 -25 -20 -15 -10 IOUT = 4mA Figure 5-7. Output Current Drift Distribution O u t p u t C u r r e n t D r i f t ( n A /  C ) Population (%) 1 0 1 5 2 0 2 5 3 0 3 5 -40 -35 -30 -25 -20 -15 -10 IOUT = 20mA Figure 5-8. Output Current Drift Distribution Figure 5-9. Current-Output Mode Nonlinearity Distribution N o n l i n e a r i t y ( % ) Population (%) 1 0 1 5 2 0 0.00005 0.0001 0.00015 0.0002 0.00025 0.0003 0.00035 0.0004 0.00045 0.0005 Figure 5-10. Voltage-Output Mode Nonlinearity Distribution P o w e r S u p p l y R e j e c t i o n R a t i o (  V / V ) Population (%) 1 0 1 5 2 0 2 5 3 0 3 5 4 0 -1.5 -1.25 -0.75 -0.5 -0.25 0.25 0.5 0.75 1.25 1.5 Figure 5-11. Power Supply Rejection Ratio Distribution Q u i e s c e n t C u r r e n t (  A ) Population (%) 1 0 1 5 2 0 2 5 3 0 3 5 270 280 290 300 310 320 330 340 350 360 370 Figure 5-12. Quiescent Current Distribution XTR200 SBOSAL6A – JUNE 2025 – REVISED SEPTEMBER 2025 www.ti.com

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at TA = 25°C and VSP = 24V, Current-Output Mode: RSET = 1.5kΩ, RL = 250Ω, CL = 10pF, Voltage-Output Mode: RL = 1kΩ, CL = 10pF (unless otherwise noted) O u t p u t L e a k a g e C u r r e n t ( n A ) Population (%) 1 0 1 5 2 0 2 5 3 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 Output disabled Figure 5-13. Output Leakage Current Distribution M i n i m u m O u t p u t V o l t a g e ( m V ) Population (%) 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 0.25 0.5 0.75 1.25 1.5 1.75 Voltage-output mode, VIN = 0V Figure 5-14. Minimum Output Voltage Distribution S h o r t C i r c u i t C u r r e n t ( m A ) Population (%) 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 6 0 Figure 5-15. Short-Circuit Current Limit Distribution S u p p l y V o l t a g e ( V ) Quiescent Current (A) 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 6 0 3 0 0 3 1 0 3 2 0 3 3 0 3 4 0 3 5 0 3 6 0 3 7 0 Figure 5-16. Quiescent Current vs Supply Voltage Figure 5-17. Quiescent Current vs Temperature T e m p e r a t u r e ( ° C ) Short Circuit Current (mA) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 3 5 3 6 3 7 3 8 3 9 4 0 Figure 5-18. Short-Circuit Current vs Temperature www.ti.com XTR200 SBOSAL6A – JUNE 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: XTR200

at TA = 25°C and VSP = 24V, Current-Output Mode: RSET = 1.5kΩ, RL = 250Ω, CL = 10pF, Voltage-Output Mode: RL = 1kΩ, CL = 10pF (unless otherwise noted) T e m p e r a t u r e ( ° C ) Input Bias Current (nA) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 0 . 0 0 0 2 0 . 0 0 1 0 . 0 1 0 . 1 1 0 VIN = 3V Figure 5-19. Input Bias Current vs Temperature I n p u t V o l t a g e ( V ) Input Bias Current (pA) 0 . 1 1 0 1 0 0 5 0 0 Figure 5-20. Input Bias Current vs Input Voltage T e m p e r a t u r e (  C ) Input Offset Voltage (V) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 - 6 0 0 - 5 0 0 - 4 0 0 - 3 0 0 - 2 0 0 - 1 0 0 1 0 0 2 0 0 3 0 0 4 0 0 5 0 0 6 0 0 30 typical units Figure 5-21. Input Offset Voltage vs Temperature O u t p u t C u r r e n t ( m A ) Nonlinearity (%) 0 5 1 0 1 5 2 0 2 5 - 0 . 0 0 1 5 - 0 . 0 0 1 - 0 . 0 0 0 5 0 . 0 0 0 5 0 . 0 0 1 0 . 0 0 1 5 5 typical units Figure 5-22. Current-Output Mode Nonlinearity, 0.1mA to 25mA O u t p u t C u r r e n t ( m A ) Nonlinearity (%) 4 8 1 2 1 6 2 0 - 0 . 0 0 1 - 0 . 0 0 0 5 0 . 0 0 0 5 0 . 0 0 1 5 typical units Figure 5-23. Current-Output Mode Nonlinearity, 4mA to 20mA O u t p u t V o l t a g e ( V ) Nonlinearity (%) 0 1 2 3 4 5 6 7 8 9 1 0 - 0 . 0 0 1 - 0 . 0 0 0 5 0 . 0 0 0 5 0 . 0 0 1 5 typical units Figure 5-24. Voltage-Output Mode Nonlinearity, 10mV to 10V XTR200 SBOSAL6A – JUNE 2025 – REVISED SEPTEMBER 2025 www.ti.com

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at TA = 25°C and VSP = 24V, Current-Output Mode: RSET = 1.5kΩ, RL = 250Ω, CL = 10pF, Voltage-Output Mode: RL = 1kΩ, CL = 10pF (unless otherwise noted) T e m p e r a t u r e (  C ) Span Error (%) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 0 . 0 0 5 0 . 0 1 0 . 0 1 5 0 . 0 2 0 . 0 2 5 Figure 5-25. Span Error vs Temperature T e m p e r a t u r e (  C ) Gain Error (%) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 0 . 0 0 2 5 0 . 0 0 5 0 . 0 0 7 5 0 . 0 1 Figure 5-26. Gain Error vs Temperature T e m p e r a t u r e (  C ) Headroom (V) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 . 8 1 . 9 2 . 1 2 . 2 2 . 3 2 . 4 2 . 5 2 . 6 VSP = 8V, IOUT = 25mA Figure 5-27. Current-Output Mode Headroom vs Temperature T e m p e r a t u r e (  C ) Headroom (V) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 . 8 1 . 9 2 . 1 2 . 2 2 . 3 2 . 4 2 . 5 VOUT = 10V, IOUT = 25mA Figure 5-28. Voltage-Output Mode Headroom vs Temperature VIN = 0.6V Figure 5-29. Input Voltage Noise VIN = 0.6V Figure 5-30. Current-Output Mode 0.1 to 10Hz Noise www.ti.com XTR200 SBOSAL6A – JUNE 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: XTR200

at TA = 25°C and VSP = 24V, Current-Output Mode: RSET = 1.5kΩ, RL = 250Ω, CL = 10pF, Voltage-Output Mode: RL = 1kΩ, CL = 10pF (unless otherwise noted) T i m e ( 1 s / d i v ) Input Voltage Noise (1V/div) VIN = 0.6V Figure 5-31. Voltage-Output Mode 0.1 to 10Hz Noise F r e q u e n c y ( H z ) Gain (dB) - 4 0 - 3 0 - 2 0 - 1 0 1 0 2 0 1 0 0 1 k 1 0 k 1 0 0 k 1 M 1 0 M C a p a c i t i v e L o a d 1 0 p F 1 n F 1 0 n F RSET = 1.5kΩ, RL = 250Ω Gain(dB) = 20×log10(10×RL/RSET) Figure 5-32. Current-Output Mode Gain vs Frequency F r e q u e n c y ( H z ) Gain (dB) - 4 0 - 3 0 - 2 0 - 1 0 1 0 2 0 1 0 0 1 k 1 0 k 1 0 0 k 1 M 1 0 M C a p a c i t i v e L o a d 1 0 p F 1 n F 1 0 n F Figure 5-33. Voltage-Output Mode Gain vs Frequency F r e q u e n c y ( H z ) PSRR (dB) 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 1 0 1 0 0 1 k 1 0 k 1 0 0 k 1 M C u r r e n t - o u t p u t m o d e V o l t a g e - o u t p u t m o d e Figure 5-34. Power Supply Rejection Ratio T i m e ( 1 0  s / d i v ) Input Voltage (2.5V/div) Output Current (10mA/div) I n p u t v o l t a g e O u t p u t c u r r e n t ( 2 0 p F l o a d ) O u t p u t c u r r e n t ( 1 0 n F l o a d ) 0mA to 25mA step response Figure 5-35. Current-Output Mode Large Signal Step Response T i m e ( 1 0  s / d i v ) Input Voltage (2.5V/div) Output Current (10mA/div) I n p u t v o l t a g e O u t p u t c u r r e n t ( 2 0 p F l o a d ) O u t p u t c u r r e n t ( 1 0 n F l o a d ) 0.5mA to 25mA step response Figure 5-36. Current-Output Mode Large Signal Step Response XTR200 SBOSAL6A – JUNE 2025 – REVISED SEPTEMBER 2025 www.ti.com

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at TA = 25°C and VSP = 24V, Current-Output Mode: RSET = 1.5kΩ, RL = 250Ω, CL = 10pF, Voltage-Output Mode: RL = 1kΩ, CL = 10pF (unless otherwise noted) T i m e ( 2 5  s / d i v ) Voltage (5V/div) I n p u t v o l t a g e O u t p u t v o l t a g e ( 2 0 p F l o a d ) O u t p u t v o l t a g e ( 1 0 n F l o a d ) Figure 5-37. Voltage-Output Mode Large Signal Step Response T i m e ( 2  s / d i v ) OD Pin Voltage (3V/div) Output Current (5mA/div) O D p i n O u t p u t c u r r e n t Figure 5-38. Current-Output Mode Enable Transient Response T i m e ( 2  s / d i v ) OD Pin Voltage (3V/div) Output Current (5mA/div) O D P i n O u t p u t C u r r e n t Figure 5-39. Current-Output Mode Disable Transient Response T i m e ( 5 0  s / d i v ) Voltage (2V/div) O D p i n O u t p u t v o l t a g e Figure 5-40. Voltage-Output Mode Enable Transient Response Figure 5-41. Voltage-Output Mode Disable Transient Response T i m e ( 2  s / d i v ) Output Current (2mA/div) Error Flag Voltage (1V/div) O p e n - c i r c u i t l o a d O u t p u t c u r r e n t E r r o r f l a g Figure 5-42. Error Flag Transient Response www.ti.com XTR200 SBOSAL6A – JUNE 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: XTR200

6 Detailed Description

6.1 Overview

The XTR200 is an output driver intended for 3-wire systems with analog current or voltage outputs. The XTR200 is designed to deliver the commonly-used industrial signaling ranges of 0mA to 20mA, 4mA to 20mA, or 0V to 10V on a single supply and with minimal additional components. The performance is specified for a nominal supply voltage of 24V, but sustained supply voltages up to 60V are acceptable, with an absolute maximum supply voltage rating of 65V. Furthermore, the XTR200 is specified over the full industrial temperature range of –40°C to +125°C. The XTR200 has two modes of normal operation. In current-output mode, the voltage-to-current ratio is defined by an external resistor, RSET; therefore, the input voltage range can be freely set in accordance with application requirements. In voltage-output mode, the XTR200 has a fixed gain of 3.75V/V, which produces a 0V to 10V output from a 0V to 2.67V input voltage achievable by many common digital-to-analog converters (DACs) and microcontrollers. Error detection circuitry activates a logic output (error flag pin, EF) in case the correct current or voltage output is unachievable, the die temperature is too high, or the power supply voltage is too low. Use the output disable (OD) pin during power-on, multiplexing, and other conditions where a high-impedance output is required. The OD pin contains an internal pullup that causes the XTR200 to power up in output-disabled mode unless the OD pin is tied low. The XTR200 integrates an output PMOS capable of driving the full rated load current across a wide range of supply voltages. However, the device can also be configured to use an external PNP or PMOS transistor to deliver the majority of the load current and reduce the on-chip power dissipation. Both the internal PMOS and optional external transistors are protected by integrated short circuit protection circuitry.

6.2 Functional Block Diagram

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6.3 Feature Description

6.3.1 Explanation of Pin Functions

INPUT: This input is a conventional, noninverting, high-impedance input of an operational amplifier (op amp). This pin is designed for voltages from 0V to 5V. The internal circuitry is protected by clamp diodes to ground and an internal 5V reference. Applying voltages beyond 0V to 5V causes a large amount of current to flow through the clamp diodes and potentially damage the device. An external series resistor can be used to limit current through the clamp diodes if voltages beyond the 0V to 5V range are expected. MODE: This input determines the output mode of the XTR200. Applying a voltage greater than 1.65V selects current-output mode. A voltage less than 0.8V above ground selects voltage-output mode. This pin has a 4 μA internal pullup current source to 3.3V. EF : The active ‑low error flag (logic output) indicates the fault conditions listed in the Error Flag section. This pin has a 4 μA internal pullup current source to 3.3V. The pin can be used with a pullup resistor to an external voltage source for different voltage levels. Leave the pin unconnected if not used. OD: This control input has a 4 μA internal pullup current source disabling the output. Pulling the pin low, within 0.8V of GND, is required to activate the output. Control OD to reduce output glitches during power on and power off. If not used, connect this pin to ground to enable the output continuously. SET: The total resistance connected between this pin and the ground reference sets the voltage-to-current transfer ratio. Additional series resistance introduced by improper PCB layout degrades precision. The voltage on this pin must not exceed 5V. IS: This output pin is connected to the source or emitter of an external transistor (PMOS or PNP) if one is used. If no external transistor is used, short this pin to the VG pin for proper functionality. VG: This output pin drives the gate or base of an external transistor. Short this pin to the IS pin if no external transistor is used. VSP: This is the positive power supply for the internal circuitry of the XTR200. The XTR200 tolerates supply voltages up to a maximum of 65V, which allows the XTR200 to operate in harsh industrial environments. Use a bypass capacitor (e.g. 100nF) and optionally a damping inductor or a small resistor (5 Ω) to decouple the XTR200 supply from the noise typically found on industrial 24V supplies. GND: The GND pin is both the negative power supply and the reference voltage point for the internal circuitry of the XTR200. The input voltage, logic levels, and R SET voltage are measured with respect to this point. Provide a low-impedance connection to the system ground for reliable operation. OUT: This pin delivers load current from the internal PMOS transistor. If using an external transistor, connect the OUT pin to the collector or drain of the external PNP or PMOS transistor.

6.3.2 Using an External Transistor

The XTR200 integrates an output transistor capable of delivering the specified output current to a wide range of load resistances. However, in applications with high supply voltages, using an external transistor reduces the power dissipated in the XTR200. The Power Supply Recommendations section provides useful information on supply voltage and PCB temperature limitations when using the internal output transistor. Establish that the external transistor is rated for the maximum anticipated supply voltage and is capable of dissipating the power generated by the load current and the voltage drop across the transistor. Figure 6-1 and Figure 6-2 display the current flow when using an external PNP or PMOS transistor with the XTR200. A portion of the load current flows through the internal 1k Ω resistor between the IS and VG pins, producing a voltage which turns on the external transistor. The voltage between the IS and VG pins is limited to approximately 2V by a clamp circuit represented by a Zener diode in the diagram. A small portion of the output load current still flows through the internal PMOS of the XTR200 but is recombined with the current through the external transistor. When using an external PNP transistor, the base current is recirculated through the internal PMOS (Q2) and does not degrade the accuracy of the output current. www.ti.com XTR200 SBOSAL6A – JUNE 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: XTR200

All load current flows through the on-chip 50 Ω resistor in the XTR200 which is used to measure output current and detect fault conditions. For this reason, using an external transistor does not change the transfer function of the XTR200 or increase the maximum output current. External transistors are protected from short-circuit faults by the same circuitry which protects the internal output PMOS. VSP OUT VG IS XTR200 RLOAD Figure 6-1. Current Pathways for an External PNP Transistor VSP OUT VG IS XTR200 RLOAD Figure 6-2. Current Pathways for an External PMOS Transistor

6.3.3 Error Flag

The XTR200 has internal circuitry that detects the error states listed in Table 6-1. When an error state is detected, the error flag EF (an open-drain logic output), pulls low. This digital output can be pulled up to an external logic voltage through a resistor. The internal pullup current is 4μA to an internal 3.3V reference. Table 6-1. Error States Indicated by Error Flag Error State Description Output short Short-circuit current limit reached in voltage-output mode Output open Unable to reach correct output current in current-output mode. This fault condition is only detectable with an input voltage of >350mV and a supply voltage of >10V. Output saturation Insufficient headroom between load voltage and supply voltage to achieve correct voltage or current output. This fault condition is only detectable with a supply voltage of >10V. SET pin short SET pin current exceeding 1/10th of the output short circuit current limit Power supply under voltage Power supply voltage under 8V High die temperature Die temperature exceeding 150°C XTR200 SBOSAL6A – JUNE 2025 – REVISED SEPTEMBER 2025 www.ti.com

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Product Folder Links: XTR200

6.4 Device Functional Modes

6.4.1 Current-Output Mode

Applying a voltage greater than 1.65V to the MODE pin places the XTR200 into current-output mode. In current-output mode, the XTR200 acts as a voltage-controlled current source. Figure 6-3 shows the internal configuration of the XTR200, as well as the current flow inside the device. When a voltage is applied to the input, amplifier A1 drives the gate of NMOS transistor Q1, which causes a current I SET to flow through the external resistor RSET. The voltage at the SET pin is fed back to the inverting input of amplifier A1 through switch SW1. This feedback loop forces the voltage at the SET pin to equal the input voltage, as shown in Equation 1. I SE T = V IN R SET (1) ISET also flows through the 500 Ω resistor connected between the drain of Q1 and the power supply, VSP. Amplifier A2 senses the voltage drop across this 500Ω resistor and drives the gate of the PMOS output transistor Q2 through switch SW4. This action creates an equal voltage drop across the 50 Ω resistor at the inverting input connected between the source of Q2 and VSP. To produce an equal voltage at the input terminals of amplifier A2, 10 times more current must flow through the 50Ω resistor, as shown in Equation 2 I O UT = 10 × I S ET (2) The general equation for the transfer function in current-output mode is: I O UT = 10 × V IN R SET (3) 500 110k 40k SET MODE INPUT VSP OUT VG IS GND OD XTR200 RSET SW1 SW2 SW3 SW4 EF >2V –VIN ISET IOUT Figure 6-3. XTR200 Internal Configuration and Current Flow in Current-Output Mode

6.4.2 Voltage-Output Mode

Pulling the MODE pin low places the XTR200 into voltage-output mode. Figure 6-4 shows the internal configuration of the device in voltage-output mode. Amplifier A2 is now bypassed and the inverted output of amplifier A1 controls the output transistor Q2 through switch SW4. Switches SW2 and SW3 close the feedback loop through the on-chip voltage divider consisting of 110k Ω and 40kΩ resistors. These resistors are fabricated using a high-precision thin-film deposition and precision layout techniques to deliver extremely low gain error over the full temperature range. www.ti.com XTR200 SBOSAL6A – JUNE 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: XTR200

The on-chip, precision voltage divider determines the transfer function in voltage output mode: V OUT = V IN × 3.75 (4) In voltage-output mode, the gate of transistor Q1 is connected to ground and no current flows from the SET pin. A resistor present at the SET pin, R SET, does not affect voltage output operation. This allows the XTR200 to operate in voltage or current output mode without changing external components. 500 110k 40k SET MODE VSP OUT VG IS GND OD XTR200 RSET SW1 SW2 SW3 SW4 INPUT EF –VIN Figure 6-4. XTR200 Internal Configuration in Voltage-Output Mode

6.4.3 Output Disabled

Applying a voltage greater than 1.65V above ground to the OD pin disables the output of the XTR200. Power supply voltages less than 7.4V also disable the output of the device. Figure 6-5 shows the internal configuration of the XTR200 with the output disabled. In this mode, the gate of the internal output PMOS transistor, Q2, is shorted to the source through an internal switch to make the OUT pin high impedance. The gate of the internal NMOS transistor, Q1, is also shorted to ground so that the SET pin is high impedance. The OUT pin is tolerant of voltages less than the power supply voltage in this state. 500 SET MODE VSP OUT VG IS GND OD XTR200 RSET INPUT EF –>1.65V Figure 6-5. XTR200 Internal Configuration with Output Disabled XTR200 SBOSAL6A – JUNE 2025 – REVISED SEPTEMBER 2025 www.ti.com

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Product Folder Links: XTR200

6.4.4 Thermal Shutdown

The error flag pin ( EF) of the XTR200 indicates a die temperature above 150°C as a warning of a fault condition. If the die temperature continues to rise, the XTR200 enters into a thermal shutdown state when the die temperature exceeds 160°C. In the thermal shutdown state, the output is disabled (high impedance) until the die temperature cools below 150°C. If the external fault condition which initially produced the high die temperature has not been remedied, the device oscillates in and out of the thermal shutdown state until the fault is removed.

7 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

7.1 Application Information

7.1.1 Input Voltage

The linear input voltage range extends from 0V to 5V. The input voltage is referenced to the grounding point of RSET. Verify that R SET is not distorted from other currents. Assuming a 3V full-scale input signal for a 20mA output current, R SET is 1.5k Ω. A resistance uncertainty of just 1.5 Ω already degrades the accuracy to below 0.1%. Select a precision, low-drift resistor for best performance because resistor drift directly converts into drift of the output current. Design the layout carefully to minimize any series resistance with R SET and the input reference point. Do not drive the input negative (referred to GND) greater than 500mV. Higher negative voltages turn on the internal protection diodes. Insert a resistor in series with the input if negative signals can occur during power on, power off, or other transient conditions. Use a voltage divider to add an offset voltage to the input voltage for a 4mA to 20mA signaling range as shown in Figure 7-1. In this approach, an offset voltage is derived from a voltage reference and voltage divider, such that the XTR200 delivers 4mA to the load when the DAC output voltage is 0V, preserving DAC resolution. VSP GNDSET OUTINPUT MODE EF OD RSET IS VG XTR200 DAC RLOAD 4mAR2 R1Voltage Reference VCC VCC 0V VOS VREF Figure 7-1. Adding an Offset Voltage to the XTR200 Input for 4mA to 20mA Signaling Use Equation 5 to calculate the offset voltage, VOS, required for a 4mA output. V OS = 4 mA × R S ET 10 (5) When the necessary offset voltage is calculated, calculate the values of R1 and R2 using the equation: www.ti.com XTR200 SBOSAL6A – JUNE 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: XTR200

V OS = V REF × R 2 R 1 + R 2 (6) Consider the minimum output voltage of the DAC when designing this circuit. Some DACs do not reach all the way to 0V.

7.1.2 Miswiring Protection

On occasion, miswiring faults occur when field transmitters are installed in industrial environments. If the OUT pin of the XTR200 is mistakenly connected to the power supply, and the VSP pin is grounded, the on-chip ESD diode between these pins is forward biased. The forward bias causes a large current to flow and damage the IC. Figure 7-2 shows the addition of a miswiring protection diode in series with the XTR200 power supply. This diode prevents reverse current from flowing out of the VSP pin through the ESD diode. The supply bypass capacitor, CBYP, placed at the VSP pin provides a low-impedance pathway to ground for high-frequency ESD events that forward bias the on-chip ESD diode. Include the forward voltage drop of the miswiring protection diode when calculating the minimum supply voltage to provide the necessary headroom for the XTR200. ESD Diode ESD Diode RLOAD Miswiring Protection Diode VSP GND OUT XTR200 CBYP VSupply Figure 7-2. Basic Miswiring Protection Diode in Series with Supply Figure 7-3 shows a basic reverse polarity protection circuit to protect the XTR200 in the event the ground voltage exceeds the supply or load voltage. In normal operation, the NMOS transistor is turned on via resistors R1 and R2. Select resistor values which produce an appropriate gate voltage for the NMOS from the range of expected power supply voltages. Zener diode ZD1 protects the NMOS gate from over-voltage. If V Supply is low but the voltage at the ground is high (reverse polarity condition) the NMOS is turned off, preventing current flow through the on-chip ESD diodes. Select an NMOS transistor with low RDS(ON) to minimize ground potential differences. Miswiring Protection DiodeCBYP VSupply NMOSZD1 ESD Diode ESD Diode VSP GND OUT XTR200 Figure 7-3. Basic Reverse Polarity Protection Figure 7-3 does not protect the XTR200 in the case that the ground connection is shorted to the power supply but the load is still grounded. Figure 7-4 adds additional protective circuitry to limit current through the ESD diode XTR200 SBOSAL6A – JUNE 2025 – REVISED SEPTEMBER 2025 www.ti.com

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Product Folder Links: XTR200

7.1.3 Power Dissipation in Current Output Mode

In current-output mode, the combination of low load resistances and relatively high output currents causes increased power dissipation in the XTR200 when using the internal output transistor. Equation 7 calculates the power dissipated in the XTR200. P D = V SP I Q + V SP − I O R SE T I O 10 + V SP − I O R L I O (7) Where:

• VSP: Supply voltage in volts
• IQ: Quiescent power supply current in amps (typically 325μA)
• IO: Output current in amps
• RSET: SET resistor value in ohms
• RL: Load resistor value in ohms Equation 7 has three terms. The first term represents the operating dissipation of the XTR200 internal circuitry and is a function of the power supply voltage and the quiescent power supply current. The second term represents the power dissipated in the SET pathway of the XTR200 and is a function of the supply voltage, the SET current (1/10th the output current) and the SET resistor, RSET. The last, and most significant, term of the equation represents the power dissipation in the output circuitry of the XTR200 and is a function of the supply voltage, output current, and load resistance. Use the calculated power dissipation with the method Estimating Junction Temperature shows to estimate the XTR200 junction temperature for a given use case. Figure 7-6 shows the power dissipation of an XTR200 in current output mode using the internal transistor, a 24V supply, and a 1.33k Ω R SET for various load resistances. Power dissipation in the XTR200 is highest for low resistance loads and high output currents. Power dissipation decreases once the load voltage exceeds the voltage drop across the output circuitry of the XTR200, as seen in the 500 Ω load case above 26mA of output current. O u t p u t C u r r e n t ( m A ) XTR200 Power Dissipation (mW) 0 5 1 0 1 5 2 0 2 5 3 0 1 0 0 2 0 0 3 0 0 4 0 0 5 0 0 6 0 0 7 0 0 8 0 0

0 O h m s

Figure 7-6. XTR200 Power Dissipation vs Output Current and Load Resistance (VSP = 24V, RSET = 1.33kΩ)

7.1.4 Estimating Junction Temperature

The JEDEC standard now recommends using psi ( Ψ) thermal metrics to estimate the junction temperatures of the device when in-circuit on a typical PCB board application. These metrics are not thermal resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi metrics are determined as significantly independent of the copper area available for heat-spreading. XTR200 SBOSAL6A – JUNE 2025 – REVISED SEPTEMBER 2025 www.ti.com

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Product Folder Links: XTR200

The Thermal Information table lists the primary thermal metrics, which are the junction-to-top characterization parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two methods for calculating the junction temperature (T J), as described in the following equations. Use the junction-to-top characterization parameter ( ψJT) with the temperature at the center-top of device package (T T) to calculate the junction temperature. Use the junction-to-board characterization parameter ( ψJB) with the PCB surface temperature 1mm from the device package (TB) to calculate the junction temperature. T J = T T + Ψ JT × P D (8) where

• PD is the dissipated power
• TT is the temperature at the center-top of the device package T J = T B + Ψ JB × P D (9) where
• TB is the PCB surface temperature measured 1mm from the device package and centered on the package edge For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package Thermal Metrics application note. www.ti.com XTR200 SBOSAL6A – JUNE 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: XTR200

7.2 Typical Applications

7.2.1 Analog Output Circuit for Field Transmitters

The XTR200 is designed as a fully-integrated output driver for field transmitters that transmit analog information in standard industrial ranges of 0mA to 20mA, 4mA to 20mA, and 0V to 10V. Figure 7-7 shows a simplified schematic of the output circuitry of a field transmitter. A digital-to-analog converter (DAC) provides the input signal to the XTR200 while a microcontroller controls the MODE and Output Disable (OD) pins and monitors the error flag pin. The XTR200 can run directly from the loop supply, which is specified for a range of 18V to 36V. The device is configured to use the internal output transistor to drive the load by shorting the IS and VG pins together. VSP GNDSET OUTINPUT MODE EF OD RSET 1.33k IS VG 18V-36V XTR200 DAC GPIO_1 GPIO_2 GPIO_3 0.1μF CBYP VSUPPLY 0V-3V RLOAD µC 0mA-22mA 0V-11.25V Figure 7-7. XTR200 Configured to Provide Standard Industrial Current and Voltage Outputs

7.2.1.1 Design Requirements

The design requirements for this application are listed in Table 7-1. These are chosen to closely represent the design requirements of industrial field transmitters. Although the standard ranges for transmitting information are 0mA to 20mA, 4mA to 20mA, and 0V to 10V, currents above 20mA and voltages above 10V are often used to indicate error conditions. This is why the design requirements specify output currents up to 22mA and output voltages up to 11.25V. Table 7-1. Design Parameters Parameter Value Input voltage range 0V to 3V Power supply voltage 18V to 36V Output current range 0mA to 22mA Output voltage range 0V to 11.25V Operating temperature range –40°C to 85°C Load Resistance (Current Output) 0Ω to 500Ω Load Resistance (Voltage Output) >1000Ω XTR200 SBOSAL6A – JUNE 2025 – REVISED SEPTEMBER 2025 www.ti.com

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Product Folder Links: XTR200

7.2.1.2 Detailed Design Procedure

The only calculation required to complete the circuit design is a single external component, R SET. Resistor RSET determines the voltage-to-current transfer function of the circuit. The value of R SET is calculated using the maximum input voltage and the maximum output current as shown in Equation 10. R SET = 10 × V IN M AX I OUT M AX = 10 × 3V 22 mA = 1363.64 Ω 1.33 k Ω (10) A value of 1.33k Ω is chosen for R SET as this is a standard 1% resistor value that is very close to the calculated value of 1363.64 Ω and can still provide the required maximum output current of 22mA. Select a resistor with a low temperature coefficient and tight value tolerance to minimize the error introduced by this external component. No calculations are required to set the output voltage transfer function. The XTR200 has a fixed gain of 3.75V/V in voltage-output mode which is sufficient for a variety of DAC output voltage ranges. Consider the headroom requirement of the XTR200 when evaluating the load resistance and power supply voltage ranges. The worst case scenario is a minimum supply voltage of 18V and the maximum output current (22mA) into the maximum load resistor (500 Ω). In this case, the load voltage is 11V and the headroom (the difference between supply voltage and load voltage) is 7V. This case is well above the 2.5V headroom requirement of the XTR200 and sufficient for proper operation. The required maximum power supply voltage, 36V, is well within the limits recommended in Power Supply Recommendations when using the internal transistor. Figure 7-7 also shows a 0.1 μF bypass capacitor, C BYP, on the power supply pin, VSP, of the XTR200. The bypass capacitor location is a good design practice and helps provide a low-impedance supply for the XTR200 and filter out any residual noise on the power supply.

7.2.1.3 Application Curves

Figure 7-8 and Figure 7-9 show the output current and voltage transfer functions of the circuit. The calculated value of R SET, 1.33kΩ, gives a maximum output current of 22.56mA for an input voltage of 3V. The maximum output voltage is 11.25V for an input voltage of 3V. I n p u t V o l t a g e ( V ) Output Current (mA) 0 0 . 5 1 1 . 5 2 2 . 5 3 1 0 1 2 1 4 1 6 1 8 2 0 2 2 2 4 Figure 7-8. Output Current Transfer Function I n p u t V o l t a g e ( V ) Output Voltage (V) 0 0 . 5 1 1 . 5 2 2 . 5 3 1 0 1 1 1 2 Figure 7-9. Output Voltage Transfer Function www.ti.com XTR200 SBOSAL6A – JUNE 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: XTR200

7.2.2 Additional Applications

The XTR200 is useful in a variety of applications beyond voltage and current transmission. The wide supply and output current ranges, high output impedance, and excellent integration make the device well suited for sensor excitation as well as current monitoring in server power supply applications. Current Sources for RTD Measurements Resistance temperature detectors, or RTDs, are sensors which measure temperature through a change in resistance. RTDs are typically biased using a constant current source and then the temperature-dependent voltage across the sensor can be measured. Figure 7-10 illustrates a 2-wire ratiometric RTD measurement system employing the XTR200 as a current source. The excitation current produced by the XTR200, I EXC, flows through the RTD as well as a reference resistor, RREF, which produces the reference voltage for the ADC. VSP GND SET OUT INPUT MODE EF ODIS VG VCC XTR200 ADCRRTD RREF RSET VREF IEXC IEXC REFP REFN AINN AINP VDD VDD Figure 7-10. XTR200 Used as an Excitation Current Source in a 2-Wire, Ratiometric, RTD Measurement A 3-wire RTD measurement, for lead resistance cancellation, is shown in Figure 7-11. Using a single input voltage source for the two XTR200s, and matching the R SET resistors maintains good matching between the two excitation currents. VSP GND SET OUT INPUT MODE EF ODIS VG VCC XTR200 ADC RLEAD1 RLEAD2 RRTD RLEAD3 RREF VSP GND SET OUT INPUT MODE EF OD RSET IS VG VCC XTR200 RSET IEXC1 IEXC2 IEXC1 + IEXC2 REFP REFN AINN AINP VDD VREF VDD VDD Figure 7-11. XTR200s Used as Matched Current Sources in a 3-Wire RTD Measurement for Lead Resistance Cancellation XTR200 SBOSAL6A – JUNE 2025 – REVISED SEPTEMBER 2025 www.ti.com

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Product Folder Links: XTR200

Current Monitor (Imon) Output for Modular Hardware System-Common Redundant Power Supplies (M- CRPS) The M-CRPS specification requires that server power supplies have a current monitor (Imon) output for the 12V bus. The Imon output produces a scaled down replica of the current flowing on the 12V bus with a ratio of either 10μA/A or 0-2mA indicating 0-200% of rated output current. Figure 7-14 shows an example implementation of the Imon function using an INA241A5 current shunt monitor amplifier and an XTR200. The INA241A5 outputs a voltage of 0V to 2V, corresponding to 0-100A flowing through the 100 μΩ shunt resistor. An optional low-pass filter composed of RFILT and CFILT are shown on the output of the INA241A5 to allow for bandwidth limiting. 100µ VSP GNDSET OUTINPUT MODE EF OD 20k IS VG XTR200 12V 20k GND INA241A5 VS IN+ IN- REF1 REF2 OUT RFILT 12V CFILT 28.7k 13.3k 100n Low-Leakage Diode (e.g. BAS716) 3.8V To Load 12V TLV9301 To MCU GPIO High: 0mA-2mA Low: 10µA/A 0V-2V 12V To MCU GPIO for presence functionality Imon Output 0mA-2mA or 10µA/A 12V Supply Bus 0A-100A (0% to 200% of rated current) Figure 7-14. Simplified Diagram of Current Monitor (Imon) Output for the M-CRPS Specification The XTR200 converts the 0V to 2V output of the INA241A5 to an output current with a transfer function determined by the 2, 20k Ω RSET resistors. If the gate of the NMOS is low, the XTR200 outputs 10 μA per Amp of current flowing on the 12V bus. If the gate of the NMOS is high, then the 2, 20k Ω resistors are connected in parallel and the transfer function is 0-2mA corresponding to 0-200% of rated output current. Diode D1 and op amp U3 form a clamping circuit which clamps the output voltage to 3.3V when the voltage drop across diode D2 is accounted for. Diode D2 prevents reverse current flow in systems with multiple Imon signals connected in parallel. D2 must be a low-leakage diode to meet the requirement of <500nA leakage at 85°C. Q1, Q2, R2, and R3 implement "presence" functionality required for backwards compatibility with older power supplies. The standards document suggests a low-leakage PJFET for Q1, such as the MMBFJ177L. XTR200 SBOSAL6A – JUNE 2025 – REVISED SEPTEMBER 2025 www.ti.com

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Product Folder Links: XTR200

7.3 Power Supply Recommendations

The XTR200 operates over a supply voltage range of 8V to 60V. However, consider the environmental temperature, load current, and load resistance in the overall system design. Figure 7-15 shows the thermally- limited maximum supply voltage of the XTR200 over a range of PCB temperatures. Figure 7-15 shows a worst-case scenario of 22mA output current into a 0 Ω load using the internal output transistor, IS and VG pins shorted. The black curve shows the supply voltage resulting in a 125°C junction temperature (the maximum specified temperature of the XTR200) for the given PCB temperature. The red curve shows the supply voltages resulting in a 150°C junction temperature (maximum operating temperature of the XTR200) for a given PCB temperature. At approximately 150°C, the Error Flag pin (EF) voltage goes low, warning of high junction temperature. The XTR200 thermal shutdown circuitry disables the output for junction temperatures above 160°C. When the junction temperature falls back below 150°C, the output is re-enabled. For PCB temperatures below 70°C, the maximum recommended supply voltage is limited by the voltage rating of the XTR200 internal circuitry rather than thermal considerations. If high-temperature and high-supply-voltage operation is required, use an external transistor to deliver the load current as described in Using an External Transistor. P C B T e m p e r a t u r e ( ° C ) Maximum Supply Voltage (V) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 J u n c t io n T e m p e r a t u r e : 1 2 5 ° C J u n c t io n T e m p e r a t u r e : 1 5 0 ° C Figure 7-15. Maximum Recommended Supply Voltage vs PCB Temperature (Internal Output Transistor) Consider the headroom specification of the XTR200 when determining the working power supply range of a system. The term headroom defines the difference between the supply voltage of the XTR200 and the load voltage as shown in Figure 7-16 . Above the minimum supply voltage, 8V, confirm that the XTR200 supply voltage is at least 2.5V above the load voltage. VSP GNDSET OUTINPUT MODE EF OD IS VG XTR200 RLOAD VSUPPLY VHEADROOM 2.5V ILOAD VLOAD + Figure 7-16. XTR200 Headroom www.ti.com XTR200 SBOSAL6A – JUNE 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: XTR200

7.4 Layout

7.4.1 Layout Guidelines

Figure 7-17 shows an example layout for the XTR200. For particular requirements of an application or PCB assembly process, refine the layout. To maximize the performance of the device:

• Place the RSET resistor as close as possible to the SET and GND pins to minimize trace resistance in series with the RSET resistor.
• When using the integrated output transistor, short the IS and VG pins together as close as possible to the device. This reduces trace resistance to maximize output headroom and prevent noise coupling into the output signal.
• Place power supply bypass capacitors near the power supply pin, between the device and any vias used for the supply connection. Provide a low impedance connection to ground for bypass capacitors.
• Connect the thermal pad to a ground plane or pour and, if possible, extend the ground pour beyond the device to maximize power dissipation. Soldering the exposed pad significantly improves board-level reliability during temperature cycling, key push, package shear, and similar board-level tests. Even with applications that have low power dissipation, solder the exposed pad to the PCB to provide structural integrity and long-term reliability. Physical dimensions for the package and pad are shown in Mechanical, Packaging, and Orderable Information.

7.4.2 Layout Example

close to VSP pin to minimize impedance to ground Place RSET resistor close to SET and GND pins to minimize parasitic impedances When using integrated output transistor, connect VG and IS pins directly at the IC Connect the thermal pad to a large ground plane to improve power dissipation Figure 7-17. Layout Example XTR200 SBOSAL6A – JUNE 2025 – REVISED SEPTEMBER 2025 www.ti.com

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Product Folder Links: XTR200

8 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below.

8.1 Device Support

8.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

8.2 Documentation Support

8.2.1 Related Documentation

For related documentation see the following:

• Texas Instruments, XTR200 Evaluation Module User's Guide
• Texas Instruments, How to Select Amplifiers for Pressure Transmitter Applications application brief
• Texas Instruments, Special Function Amplifiers Precision Labs video series on Current Loop Transmitters

8.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

8.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

8.5 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

8.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

8.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

9 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (June 2025) to Revision A (September 2025) Page www.ti.com XTR200 SBOSAL6A – JUNE 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: XTR200

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. XTR200 SBOSAL6A – JUNE 2025 – REVISED SEPTEMBER 2025 www.ti.com

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www.ti.com PACKAGE OUTLINE C 0.3 0.2 0.35 0.25 0.84 0.1 0.05 0.008X 0.5

0.8 MAX

2.4 0.1 10X 0.35 0.25 10X 0.3 0.2 A 3.1 2.9 B 2.1 1.9 (0.2) TYP 4218281/B 11/2016 WSON - 0.8mm max heightDQC0010A PLASTIC SMALL OUTLINE - NO LEAD PIN 1 INDEX AREA 0.08 SEATING PLANE X0.2)(45 PIN 1 ID

0.1 C A B

0.05 C SEE OPTIONAL TERMINAL DETAIL SYMM SYMM NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. OPTIONAL TERMINAL TYPICAL SCALE 4.500 www.ti.com XTR200 SBOSAL6A – JUNE 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: XTR200

www.ti.com EXAMPLE BOARD LAYOUT 10X (0.5) 8X (0.5) (0.84) (2.4) ( 0.2) TYP VIA (0.95)

0.07 MIN

0.07 MAX

(1.9) 10X (0.25) (R0.05) TYP 4218281/B 11/2016 SYMM WSON - 0.8mm max heightDQC0010A PLASTIC SMALL OUTLINE - NO LEAD SYMM 5 6 SCALE: 30X LAND PATTERN EXAMPLE NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING METAL SOLDER MASK DEFINED METAL SOLDER MASK OPENING NON SOLDER MASK SOLDER MASK DETAILS DEFINED (PREFERRED) XTR200 SBOSAL6A – JUNE 2025 – REVISED SEPTEMBER 2025 www.ti.com

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www.ti.com EXAMPLE STENCIL DESIGN 10X (0.5) 8X (0.5) (1.08) (0.8) (1.9) 10X (0.25) (R0.05) TYP (0.64) 4218281/B 11/2016 NOTES: (continued) WSON - 0.8mm max heightDQC0010A PLASTIC SMALL OUTLINE - NO LEAD 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM SYMM TYP METAL 5 6 BASED ON 0.125 mm THICK STENCIL SOLDER PASTE EXAMPLE EXPOSED PAD 11: 86% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE: 30X www.ti.com XTR200 SBOSAL6A – JUNE 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: XTR200

10.1 Tape and Reel Information

Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant XTR200 SBOSAL6A – JUNE 2025 – REVISED SEPTEMBER 2025 www.ti.com

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TAPE AND REEL BOX DIMENSIONS Width (mm) W L H Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) XTR200DQCR WSON DQC 10 3000 210 185 35 www.ti.com XTR200 SBOSAL6A – JUNE 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: XTR200

www.ti.com 26-Aug-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) PXTR200DQCR Active Preproduction WSON (DQC) | 10 1 | LARGE T&R - Call TI Call TI -40 to 125 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

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