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Data Sheet: Technical Data Document Number: PXN20 Rev. 1, 09/2011 © Freescale Semiconductor, Inc., 2011. All rights reserved. PXN20 PXN21 MAPBGA–208 17 mm x 17 mm
- PXN20 features:
- 32-bit CPU core complex (e200z650) – Compliant with Power Architecture embedded category – 32 KB unified cache with line locking and eight-entry store buffer16 – Execution speed static to 116 MHz
- 32-bit I/O processor (e200z0) – Execution speed static to 1/2 CPU core speed (58 MHz)
- 2 MB on-chip flash – Supports read during program and erase operations, and multiple blocks allowing EEPROM emulation
- 512 KB + 80 KB (592 KB) on-chip ECC SRAM (PXN20)
- 128 KB on-chip ECC SRAM (PXN21)
- 16-entry Memory Protection Unit (PXN21 only)
- Direct memory access controller – 16-channel on PXN20 – 32-channel on PXN21
- Fast ethernet controller – Supports 10-Mbps and 100-Mbps IEEE 802.3 MII, 10-Mbps 7-wire interface – IEEE 802.3 MAC (complia nt with IEEE 802.3 1998 edition)
- Media Local Bus (MLB) interface (PXN20 only) – Supports 16 logical channels, max speed 1024 Fs
- Interrupt controller (INTC) supports 316 external interrupt vectors (22 are reserved)
- System clocks – Frequency-modulated phase-locked loop (FMPLL) – 4–4 0M H z c r y s t a l o s c i l l a t o r ( X T A L ) – 32 kHz crystal oscillator (XTAL) – Dedicated 16 MHz and 128 kHz internal RC oscillators
- Analog to Digital Converter (ADC) module – 10-bit A/D resolution – 32 external channels – 36 internal channels (PXN20) – 64 internal channels (PXN21)
- Cross-Triggering Unit (PXN21 only) – Internal conversion triggering for ADC – Triggerable by internal timers or eMIOS200
- Deserial Serial Periph eral Interface (DSPI) – Four individual DSPI modules – Full duplex, synchronous transfers – Master or slave operation
- Inter-IC communication (I 2C) interface – Four individual I 2C modules – Multi-master operation
- Serial Communication Interface (eSCI) module – Two-channel DMA interface – Configurable as LIN bus master
- eMIOS200 timed input/output – 24 channels, 16-bit timers (PXN20) – 32 channels, 16-bit timers (PXN21)
- Controller Area Network (FlexCAN) module – Compliant with CAN protocol specification, Version 2.0B active – 64 mailboxes, each configurab le as transmit or receive
- Dual-channel FlexRay controller – Full implementation of FlexRay Protocol Specification 2.1, RevA – 128 message buffers
- JTAG controller (PXN20 only) – Compliant with the IEEE 1149.1-2001
- Nexus Development Interface (NDI) – Available in 256 MAPBGA package only – Compliant with IEEE-ISTO 5001-2003 – Nexus class 3 development support on e200z650 – Nexus class 2+ development support on e200z0
- Internal voltage regulator allows operation from single
3.3 V or 5 V supply
PXN20 Microcontroller Data Sheet
PXS30 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor2 Table of Contents
Ordering information
PXN20 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 3
1 Ordering information
1.1 Orderable parts
Table 1 shows the orderable part numbers for the PXN20 family. Figure 1. PXN20 orderable part number description
1.2 PXN20 family feature set
Table 1. PXN20 orderable part number summary Table 2. PXN20 family feature set Note: Not all options are available on all devices. See Table 1 for more information.
PXN20 Microcontroller Data Sheet, Rev. 1 CPU Execution Speed Static, 116 MHz Static, 116 MHz Input/Output Processor (IOP) e200z0 e200z0 IOP Execution Speed 1/2 CPU execution speed 1/2 CPU execution speed Flash with ECC 2 MB 2 MB Data Flash Block 8x16 KB 8x16 KB RAM with ECC 592 KB 128 KB Memory Protection Unit (MPU) No 16 entry Direct Memory Access Unit (eDMA) 16 Channel 32 Channel Ethernet (FEC) Y es No MediaLB (MLB-DIM) Y es No FlexRay Controller Y es (128 Message Buffers) No Analog-to-Digital Converter (ADC) 36 internal channels, 10-bit Supports 32 external channels 64 internal channels, 10-bit Supports 32 external channels Total Timer I/O (eMIOS200) 24 channels, 16-bit 32 channels, 16-bit Cross Trigger Unit (CTU) No Y es Asynchronous Serial Interfaces (UART) 6 12 Synchronous Serial Interfaces (SPI) 4 4 Controller Area Network (CAN) Controller 6 5 Inter-Integrated Circuit (I 2C) Controller 4 4 Frequency Modulated PLL (FMPLL) Y es Y es 4 – 40 MHz XTAL Oscillator Y es Y es
16 MHz IRC Oscillator Y es Y es
32 kHz XTAL Oscillator Y es Y es 128 kHz IRC Oscillator Y es Y es Real Time Counter/ Autonomous Periodic Interrupts (RTC/API) Ye s Ye s Periodic Interrupt Timer (PIT) 8 8 System Timer Module (STM) Y es Y es Software Watchdog Timer (SWT) Y es Y es General-Purpose I/O (GPIO) 155 155 Clock Monitor (FMPLL) Y es Y es JTAG Y es Y es Nexus Debug (Only supported on emulation package) Nexus3 (e200Z6) Nexus2+ (e200Z0) Nexus3 (e200Z6) Nexus2+ (e200Z0) Production Package 208 MAPBGA 208 MAPBGA Emulation Package (for development use only) 256 MAPBGA 256 MAPBGA Table 2. PXN20 family feature set (continued)
2 PXN20 block diagrams
Figure 2 shows a top-level block diagram of the PXN20 device. Figure 2. PXN20 block diagram
32 KB Cache
16 MHz
Figure 3 shows a top level block diagram for the PXN21 device. Figure 3. PXN21 block diagram
3 Pin assignments
Figure 4 shows the 208-ball MAPBGA pin assignments. Figure 4. PXN20 208-ball MAPBGA (full diagram)
208 MAPBGA Ball Map
3.2 Pin muxing and reset states
SIU_PCRn[PA] bit in the order: general-purpose input/output (GPIO), function 1, function 2, and function 3 (see Figure 5). the respective value in the PA bit field is reserved. Figure 5. Supported functions example Table 3. PXN20 signal properties
Table 3. PXN20 signal properties (continued)
1 The primary signal name is used as the pin label on the BGA map for identification purposes. 3 The GPIO number is the same as the corresponding pad configuration register (SIU_PCRn) number. indicates that this value for PC is reserved on this pin, and should not be used.
PXN20 Microcontroller Data Sheet, Rev. 1 Pin assignments Freescale Semiconductor24 5 The pad type is indicated by one or more of the following abbreviations: A–analog, F—fast speed , H–high voltage, I—input-only, M–medium speed, S–slow speed. For example, pad type SH designates a slow high-voltage pad. 6 The Status During Reset pin is sampled after the internal POR is negated. Prior to exiting POR, the signal has a high impedance. The terminology used in this column is: O – output, I – input, Up – weak pull up enabled, Down – weak pulldown enabled, Low – output driven low, High – output driven high. A dash on the left side of the slash denotes that both the input and output buffers for the pin are off. A dash on the right side of the slash denotes that there is no weak pull up/down enabled on the pin. The signal name to the left or right of the slash indicates the pin is enabled. 7 The Function After Reset of a GPI function is general purpose input. A dash on the left side of the slash denotes that both the input and output buffers for the pin are off. A dash on the right side of the slash denotes that there is no weak pull up/down enabled on the pin. 8 Pullup is enabled only when JCOMP is negated. 9 Tie to VSS for normal operation.
3.2.1 Power and ground supply summary
Table 4. PXN20 power/ground 2 Base current to external NPN power transistor. Voltage may vary.
PXN20 Microcontroller Data Sheet, Rev. 1
Electrical characteristics
4 Electrical characteristics
This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the PXN20.
4.1 Maximum ratings
Table 5. Absolute maximum ratings1 cause permanent damage to the device. 2 Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance. 3 2.0 V for 10 hours cumulative time, 1.2 V +10% for time remaining. 4 5.3 V for 10 hours cumulative time, 3.3 V +10% for time remaining. 5 6.4 V for 10 hours cumulative time, 5.0 V +10% for time remaining. 6 VRC cannot be 100mV higher than VDDA. VDDSYN and VDD33 cannot be 100 mV higher than VRC. 7 All functional non-supply I/O pins are clamped to VSS and VDDEx.
9 DC Input Voltage 9
12 V SS to VSSA Differential Voltage V SS –V SSA –100 100 mV
13 V SS to VSSSYN Differential Voltage V SS –V SSSYN –100 100 mV
14 Maximum DC Digital Input Current 12 (per pin, applies to all
15 Maximum DC Analog Input Current 13 (per pin, applies to all
18 Moisture Sensitivity Level 15 MSL — 3
PXN20 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 27
4.2 Thermal characteristics
4.2.1 General notes for specification s at maximum junction temperature
An estimation of the chip junction temperature, TJ, can be obtained from the equation: TJ =T A +( RJA PD) Eqn. 1 8 VDDEx are separate power segments and may be powered independently with no differential voltage constraints between the power segments. 9 AC signal over and undershoot of the input voltages of up to ±2.0 V is permitted for a cumulative duration of 60 hours over the complete lifetime of the device (injection current does not need to be limited for this duration). 10 Internal structures will hold the input voltage above –1.0 V if the injection current limit of 2 mA is met. 11 Internal structures hold the input voltage below this maximum voltage on all pads powered by VDDE supplies, if the maximum injection current specification is met (25 mA for all pins) and VDDE is within Operating Voltage specifications. 12 Total injection current for all pins (including both digital and analog) must not exceed 25 mA. 13 Total injection current for all analog input pins must not exceed 15 mA. 14 Solder profile per CDF-AEC-Q100. 15 Moisture sensitivity per JEDEC test method A112. Table 6. Thermal characteristics
208 MAPBGA 256 MAPBGA
1 Junction to Ambient 1, 2
2 Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
2 Junction to Ambient 1, 3
3 Per JEDEC JESD51-6 with the board horizontal.
3 Junction to Ambient 1, 3
4 Junction to Ambient 1, 3
5 Junction to Board 4
the top surface of the board near the package.
6 Junction to Case 5
SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature.
7 Junction to Package Top 6
PXN20 Microcontroller Data Sheet, Rev. 1 where: TA = ambient temperature for the package (oC) RJA = junction to ambient thermal resistance (oC/W) PD = power dissipation in the package (W) The supplied thermal resistances are provided based on JEDEC JESD51 series of standards to provide consistent values for estimations and comparisons. The difference between the values determined on the single-layer (1s) board and on the four-layer board with two signal layers and a power and a ground plane (2s2p) clearly demonstrate that the effective thermal resistance of the component is not a constant. It depends on the construction of the application board (number of planes), the effective size of the board which cools the component, how well the component is thermally and electrically connected to the planes, and the power being dissipated by adjacent components. Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance between through vias leave the planes virtually disconnected, the thermal performance is also greatly reduced. As a general rule, the value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the application board has one oz. (35 micron nominal thickness) internal planes, the components are well separated, and the overall power dissipation on the board is less than 0.02 W/cm The thermal performance of any component depends strongly on the power dissipation of surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. At a known board temperature, the junction temperature is estimated using the following equation: TJ =T B +( RJB PD) Eqn. 2 where: TJ = junction temperature (oC) TB = board temperature at the package perimeter (oC/W) RJB = junction to board thermal resistance (oC/W) per JESD51-8 PD = power dissipation in the package (W) When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. The application board should be similar to the thermal test condition, with the component soldered to a board with internal planes. Historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: R JA =R JC +R CA Eqn. 3 where: RJA = junction to ambient thermal resistance (oC/W) RJC = junction to case thermal resistance (oC/W) RCA = case to ambient thermal resistance (oC/W) RJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RCA. For instance, the user can change the air flow around the device, add a heat sink, change the
PXN20 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 29 mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for packages with heat sinks where some 90% of the heat flow is through the case to the heat sink to ambient. For most packages, a better model is required. A more accurate two-resistor thermal model can be constructed from the junction to board thermal resistance and the junction to case thermal resistance. The junction to case covers the situation where a heat sink will be used or where a substantial amount of heat is dissipated from the top of the package. The junction to board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. This model can be used for either hand estimations or for a computational fluid dynamics (CFD) thermal model. To determine the junction temperature of the device in the application after prototypes are available, the Thermal Characterization Parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ =T T +( JT PD) Eqn. 4 where: TT = thermocouple temperature on top of the package (oC) JT = thermal characterization parameter (oC/W) PD = power dissipation in the package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. References: Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134 (408) 943-6900 MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or 303-397-7956. JEDEC specifications are available on the WEB at http://www.jedec.org. 1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54. 2. G . Kromann, S. Shidore, and S. Addison, “Thermal Mo deling of a PBGA for Air-Cooled Applications,” Electronic Packaging and Production, pp. 53–58, March 1998. 3. B. Joiner and V . Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212–220.
PXN20 Microcontroller Data Sheet, Rev. 1
4.3 ESD characteristics
4.4 VRC electrical specifications
4.5 DC electrical specifications
Table 7. ESD ratings1, 2 1 All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. temperature followed by hot temperature, unless specified otherwise in the device specification. Table 8. VRC electrical specifications 1 Assumes “typical usage” currents which will vary with application. Table 9. DC electrical specifications
3.0 V or
PXN20 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 31 6 3.3–5.0 V External I/O Supply Voltage 2 VDDE1 VDDE2 VDDE3 VDDE4 3.0 3.0 3.0 3.0 5.5 5.5 5.5 5.5 V 7 2.5 V – 3.3 V External I/O Supply Voltage (MLB) V DDEMLB 3 2.375 3.6 V
9 Pad Input High Voltage
Hysteresis disabled (IHA/SH/SHA/MH/MHA)4, 5 Hysteresis disabled (F) VIH 0.65 VDDE 0.55 VDDE 0.55 VDDE VDDE +0 . 3 V
10 Pad Input Low Voltage
Hysteresis disabled (IHA/SH/SHA/MH/MHA)4, 5 Hysteresis disabled (F) VIL VSS –0 . 3 0.35 VDDE 0.40 VDDE 0.40 VDDE V 11 Pad Input Hysteresis V HYS 0.1 VDDE V 12 Analog (IHA) Input Voltage V INDC VSSA –0 . 3 V DDA +0 . 3 V 13 Pad Output High Voltage 6, 7, 8 V OH 0.8 VDDE —V 14 Pad Output Low Voltage 8 VOL —0 . 2 VDDE V
15 Input Capacitance (Digital Pins: Pad type F , MH, SH) 4 C IN —7 p F
16 Input Capacitance (Analog Pins: Pad type IHA) 4, 5 CIN_A —1 0 p F
17 Input Capacitance (Shared digital/analog pins: MHA, SHA) 4 CIN_M —1 2 p F
18 I/O Weak Pull Up/Down Absolute Current 4, 9
Pad F: 2.375 V – 3.6 V Pad SH/MH/IHA: 3.0 V – 3.6 V Pad SH/MH/IHA: 4.5 V – 5.5 V IACT 180 200 19 I/O Input Leakage Current 10 IINACT_D –2.5 2.5 A 20 DC Injection Current (per pin) I IC –1.0 1.0 mA
21 Analog Input Current, Channel Off 11 (Analog pins IHA)4, 5 IINACT_A –150 150 nA
22 Analog Reference High Voltage V RH VDDA –5 0 0 V DDA mV
23 Analog Reference Low Voltage V RL VSSA VSSA +5 0 0 m V
24 V SS to VSSA Differential Voltage V SS –V SSA –100 100 mV
25 V SSSYN to VSS Differential Voltage V SSSYN –V SS –100 100 mV
26 Slew rate on V DDA, VDDEx, VDDSYN, VDD33, and VRC power supply
VRamp —1 0 0 V / m s
27 Capacitive Supply Load (V DD)V Load 8— µ F
28 Capacitive Supply Load (V DD33, VDDSYN)V Load 1— µ F
1 When VRCSEL = VSSA (low), VDDSYN and VDD33 are externally supplied. When VRCSEL = VDDA (high), VDDSYN and VDD33 are generated by internal voltage regulators. When VRCSEL = VSSA (low), VDDSYN and VDD33 cannot be 100 mV higher than VRC.
PXN20 Microcontroller Data Sheet, Rev. 1
4.6 Operating current specifications
2 VDDE1 – VDDE4 are separate power segments and may be powered independently with no differential voltage constraints between the power segments. VDDE1 – VDDE3 pad power segments contain ADC analog input channels and thus the input analog signal level may be clamped to the VDDE level, resulting in inaccurate ADC results if the VDDE voltage level is less than VDDA. 3 When VRCSEL = VDDA (high), the internally generated VDD33 voltage may be used to power VDDEMLB as long as the PK[0:2] pads remain in the disabled default state with their output buffers, input buffers, and pull devices disabled. 4 The pad type is indicated by one or more of the following abbreviations: A–analog, F—fast speed, H–high voltage, I—input-only, M–medium speed, S–slow speed. For example, pad type SH designates a slow high-voltage pad. 5 The IHA pads are related to VDDA.
6 Characterization Based Capability:
IOH_F = {12, 20, 30, 40} mA and IOL_F = {24, 40, 50, 65} mA for {00, 01,10, 11} drive mode with VDDE = 3.0 V; IOH_F = {7, 13, 18, 25} mA and IOL_F = {18, 30, 35, 50} mA for {00, 01, 10, 11} drive mode with VDDE =2 . 2 5 V ; IOH_F = {3, 7, 10, 15} mA and IOL_F = {12, 20, 27, 35} mA for {00, 01, 10, 11} drive mode with VDDE =1 . 6 2 V .
7 Characterization Based Capability:
IOH_S = {6, 11.6} mA and IOL_S = {9.2, 17.7} mA for {slow, medium} I/O with VDDEH = 4.5 V; 8 All VOL/VOH values 100% tested with ±2 mA load. 9 Absolute value of current, measured at VIL and VIH. 10 Weak pull up/down inactive. Measured at VDDE = 5.25 V. Applies to pad types: SH and MH. Leakage specification guaranteed only when power supplies are within specified operating conditions. 11 Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each 8 to 12 oC, in the ambient temperature range of 50 to 125 oC. Applies to pad types: pad_a and pad_ae. Table 10. Operating currents
PXN20 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 33 5V DDSYN Current VDD33 @ 3 . 0V–3 . 6V Run mode Sleep mode – Optional4 4–40 MHz osc enabled w/ no clock – Optional4 4–40 MHz osc enabled w/ clock IDDSYN +150 +300 +350 +400 mA 6V RC Current (excluding IDD, IDD33, IDDSYN)5 VRC @ 3.135 V – 5.5 V Run mode Sleep mode – Optional4 16MIRC enabled IRC +40 +60 mA 7V DD Current VDD @ 1.08 V – 1.32 V Run mode (Maximum @ 116 MHz)6 Sleep mode – Optional4 128KIRC enabled – Optional4 16MIRC enabled – Optional4 32 kHz osc enabled – Optional4 4–40 MHz osc enabled w/ no clock – Optional4 4–40 MHz osc enabled w/ clock – Optional4 32 KB RAM – Optional4 64 KB RAM – Optional4 128 KB RAM IDD 200 100 +200 +150 +10 +20 +40 340 900 +10 +220 +20 +20 +200 +150 +300 +600 mA 1 Typ – Nominal voltage levels and functional activity. Max – Maximum voltage levels and functional activity. 2 Static state of pins is when input pins are disabled or not being toggled and driven to a valid input level, output pins are not toggling or driving against any current loads, and internal pull devices are disabled or not pulling against any current loads. 3 Dynamic current from pins is application-specific and depends on active pull devices, switching outputs, output capacitive and current loads, and switching inputs. Refer to Table 11 for more information. 4 Optional currents are values that should be added to their respective current specifications to obtain the actual value for that specification when the optional function is active. The plus sign (+) in the Typ and Max columns indicates these optional currents. For example, VDDSYN in Sleep mode draws 1 .A (typ). With the optional 4–40 MHz osc enabled w/ no clock, add 150 .A for a total of 151 .A (typ). 5 VRC Current excluding the current supply to VDD33, VDDSYN and VDD from VRC. 6 Maximum supply current transition: 50mA per 20S observation window. Table 10. Operating currents (continued)
PXN20 Microcontroller Data Sheet, Rev. 1
4.7 I/O pad current specifications
The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The power consumption is the sum of all output pin currents for a particular segment. The output pin current can be calculated from Table 11 based on the voltage, frequency, and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in Table 11. Table 11. I/O pad average IDDE specifications1 1 These are typical values that are estimated from simulation and not tested. Currents apply to output pins only. 2 Slow = SH or SHA; Medium = MH or MHA; Fast = F; Input = IHA. See Table 3.
19 Input
PXN20 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 35
4.7.1 I/O pad V DD33 current specifications
The power consumption of the VDD33 supply is dependent on the usage of the pins on all I/O segments. The power consumption is the sum of all input and output pin VDD33 currents for all I/O segments. The output pin VDD33 current can be calculated from Table 12 based on the voltage, frequency, and load on all Pad F pins. The input pin VDD33 current can be calculated from Table 12 based on the voltage, frequency, and load on all Pad MH pins. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in Table 12. Table 12. I/O pad average IDD33 specifications1 1 These are typical values that are estimated from simulation and not tested. Currents apply to output pins only. 2 Slow = SH or SHA; Medium = MH or MHA; Fast = F; Input = IHA. See Table 3.
9 Input I
Table 13. IDD33 pad average DC current1 1 These are typical values that are estimated from simulation and not tested. Currents apply to output pins only. 2 Slow = SH or SHA; Medium = MH or MHA; Fast = F; Input = IHA. See Table 3.
PXN20 Microcontroller Data Sheet, Rev. 1
4.8 Low voltage characteristics
4.9 Oscillators electrical characteristics
Table 14. Low voltage monitors
1 Power-on-Reset Assert Level 1
3 Low Voltage Monitor Synthesizer
4 Disabled when VRCSEL =V SSA. Table 15. 3.3 V high frequency external oscillator
1 Frequency Range f ref 4 1 40 MHz
2 Duty Cycle of reference tDC 40 60 %
3 EXTAL Input High Voltage
4 EXTAL Input Low Voltage
5 XTAL Current 4 IXTAL 13 m A
6 Total On-chip stray capacitance on XTAL C S_XTAL —3 p F
7 Total On-chip stray capacitance on EXTAL C S_EXTAL —3 p F
PXN20 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 37
8 Crystal manufacturer’s recommended
9 Discrete load capacitance to be connected
CPCB_EXTAL pF
10 Discrete load capacitance to be connected
PCB_XTAL pF
11 Startup Time t startup —1 0 m s
1 When PLL frequency modulation is active, reference frequencies less than 8 MHz will distort the modulated waveform and the effects of this on emissions is not characterized. 2 This parameter is meant for those who do not use quartz crystals or resonators, but instead use CAN oscillators in crystal mode. In that case, Vextal –V xtal 400 mV criteria has to be met for oscillator’s comparator to produce output clock. 3 This parameter is meant for those who do not use quartz crystals or resonators, but instead use CAN oscillators in crystal mode. In that case, Vxtal –V extal 400 mV criteria has to be met for oscillator’s comparator to produce output clock. 4 Ixtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded. 5 CPCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively. Table 16. 5 V low frequency (32 kHz) external oscillator
1 Frequency Range f ref32 32 40 kHz
2 Duty Cycle of reference t dc32 40 60 %
3 XTAL32 Current 1
1 Ixtal32 is the oscillator bias current out of the XTAL32 pin with both EXTAL32 and XTAL32 pins grounded.
4 Crystal manufacturer’s recommended
5 Startup Time t Startup —2 s
Table 17. 5 V High Frequency (16 MHz) internal RC oscillator
1 Frequency before trim 1
1 Across process, voltage, and temperature.
2 Frequency after loading factory trim 2
2 Across voltage and temperature.
3 Application trim resolution 3
3 Fixed voltage and temperature.
4 Application frequency trim step 3 fs — — 300 — kHz
5 Startup Time t Startup — — — 500 ns
Table 15. 3.3 V high frequency external oscillator (continued)
PXN20 Microcontroller Data Sheet, Rev. 1
4.10 FMPLL electrical characteristics
Table 18. 5V low frequency (128 kHz) internal RC oscillator 1 Across process, voltage, and temperature. 2 Across voltage and temperature. 3 Fixed voltage and temperature.
4 Application frequency trim step 3 Fs128 — — 4 — kHz
5 Startup Time S t128 —— — 1 0 0 s
Table 19. FMPLL electrical specifications1 1 VDDSYN = 3.0 V to 3.6 V, VSS =V SSSYN =0V , TA =T L to TH.
1 System Frequency 2 fSYS — 116 MHz
2 PLL Reference Frequency Range f REF 44 0 M H z
3 PLL Frequency f PLL MHz
4 Loss of Reference Frequency 3 fLOR 100 2000 kHz
5 Self Clocked Mode Frequency f SCM 16 64 MHz
6 PLL Lock Time4 tLPLL — 400 s
7 Duty Cycle of Reference tDC 40 60 %
10 CLKOUT Period Jitter,5 Measured at fSYS Max
11 CLKOUT Jitter at 50 µs period CJitter –250 250 ns
12 Peak-to-Peak Frequency Modulation Range Limit 6,7
14 VCO Frequency9 fVCO 192 600 MHz
PXN20 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 39
4.11 ADC electrical characteristics
4.12 Flash memory electrical characteristics
2 The maximum frequency value is with frequency modulation disabled. If frequency modulation is enabled, the maximum frequency value should be de-rated by the percentage of modulation enabled so that the maximum frequency is not exceeded. 3 “Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self clocked mode. 4 This specification applies to the period required for the PLL to re-lock after changing the MFD frequency control bits in the synthesizer control register (SYNCR). From power up with crystal oscillator reference, lock time will be additive with crystal startup time. 5 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of Cjitter +C mod. 6 Modulation depth selected must not result in fPLL value greater than the fPLL maximum specified value. 7 Maximum and minimum variations from programmed modulation depth are 2%, 3%, and 4% peak-to-peak. Use only these settings. 8 Depth tolerance is the programmed modulation depth ±0.25% of fSYS. 9 See the Block Guide for VCO frequency synthesis equations. 10 Modulation rates less than 400 kHz will result in exceedingly long FM calibration durations. Modulation rates greater than 1 MHz will result in reduced calibration accuracy. Table 20. ADC conversion specifications (operating)
3 Analog Input Voltage AV IN VRL VRH V
5 Maximum ADC Clock Frequency F MAX —6 0 M H z
6 Sampling Time
11 Total Unadjusted Error
1 TUE assumes no pin activity on pins adjacent to analog channel or output driver activity on corresponding VDDE segment. Table 21. Flash program and erase specifications1
1 Double Word (64 bits) Program Time 4 tdwprogram —— 5 0 0 s
2 Page (128 bits and 256 bits) Program Time 4 tpprogram — 160 500 s
PXN20 Microcontroller Data Sheet, Rev. 1
4.13 Pad AC specifications
6 256 KB Block Pre-program and Erase Time t 256kpperase — 5200 15,000 ms
7 Wait States Relative to System Frequency 5
PFCRPn[RWSC] = PFCRPn[APC] = 0b000; PFCRPn[WWSC] = 0b01 PFCRPn[RWSC] = PFCRPn[APC] = 0b001; PFCRPn[WWSC] = 0b01 PFCRPn[RWSC] = PFCRPn[APC] = 0b010; PFCRPn[WWSC] = 0b01 PFCRPn[RWSC] = PFCRPn[APC] = 0b011 – 0b111; PFCRPn[WWSC] = 0b01 trwsc fSYS max MHz
8 Recovery Time t Recover —— 4 5 s
1 Typical program and erase times assume nominal supply values and operation at 25oC. 2 Initial factory condition: 100program/erase cycles, nominal supply values and operation at 25 oC. 3 The maximum time is at worst case conditions after the specified number of program/erase cycles. This maximum value is characterized but not guaranteed. 4 Actual hardware programming time. This does not include software overhead. 5 Wait state timing is based on the system clock frequency and thus is same for all masters. Table 22. Flash EEPROM Module Life (Full Temperature Range)
1 Number of Program/Erase cycles per block for 16 KB and 64 KB blocks
2 Number of Program/Erase cycles per block for 128 KB blocks over the
3 Minimum Data Retention at 85 °C ambient temperature2
2 Ambient temperature averaged over duration of application, not to exceed product operating temperature range. Table 23. Pad AC specifications (5.0 V, 2.5 V)1
1 Slow7
Table 21. Flash program and erase specifications1 (continued)
PXN20 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 41
2 Medium
01 20/35 8.7/16.6 50 41/64 24/35 200 11 12/11 5.3/5.9 50 32/34 21/23 200
3 Fast8
2.7 1.5 01 20 10 30 11 50 1 These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at TH. 2 Slow = SH or SHA; Medium = MH or MHA; Fast = F; Input = IHA. See Table 3. 3 SRC/DSC are bit fields in the Pad Configuration Registers. SRC—Slew Rate Control (slow and medium pad types only), DSC—Drive Strength Control (fast pad type only). 4 This parameter is supplied for reference and is not guaranteed by design and not tested. 5 This parameter is guaranteed by characterization before qualification rather than 100% tested. 6 Delay and rise/fall are measured to 20% or 80% of the respective signal. 7 Add a maximum of one system clock to the output delay for delay with respect to system clock. 8 Output delay is shown in. Add a maximum of one system clock to the output delay for delay with respect to system clock. Table 24. De-rated pad AC specifications (3.3 V, 3.3 V)1 Table 23. Pad AC specifications (5.0 V, 2.5 V)1 (continued)
PXN20 Microcontroller Data Sheet, Rev. 1 Figure 6. Pad output delay 2 Slow = SH or SHA; Medium = MH or MHA; Fast = F; Input = IHA. See Table 3. DSC—Drive Strength Control (fast pad type only). 4 This parameter is supplied for reference and is not guaranteed by design and not tested. 5 Delay and rise/fall are measured to 20% or 80% of the respective signal. 6 This parameter is guaranteed by characterization before qualification rather than 100% tested. 7 Add a maximum of one system clock to the output delay for delay with respect to system clock. Table 24. De-rated pad AC specifications (3.3 V, 3.3 V)1 (continued)
PXN20 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 43
4.14 AC timing
4.14.1 Reset and boot configuration pins
Figure 7. Reset and boot configuration timing
4.14.2 External interrupt (IRQ) and no n-maskable interrupt (NMI) pins
Figure 8. IRQ and NMI timing Table 25. Reset and boot configuration timing
1 RESET Pulse Width t RPW 150 — ns
2 BOOTCFG Setup Time after RESET Valid t RCSU — 100 s
3 BOOTCFG Hold Time from RESET Valid t RCH 0— s
Table 26. IRQ/NMI timing
1 IRQ/NMI Pulse Width Low t IPWL 3— t SYS
2 IRQ/NMI Pulse Width High T IPWH 3— t SYS
3 IRQ/NMI Edge to Edge Time 1
1 Applies when IRQ/NMI pins are configured for rising edge or falling edge events, but not both.
PXN20 Microcontroller Data Sheet, Rev. 1 4.14.3 JTAG (IEEE 1149.1) interface Figure 9. JTAG test clock input timing Table 27. JTAG interface timing1
1 TCK Cycle Time t JCYC 100 — ns
2 TCK Clock Pulse Width (Measured at V DDE/2) t JDC 40 60 ns
3 TCK Rise and Fall Times (40% – 70%) t TCKRISE —3 n s
4 TMS, TDI Data Setup Time t TMSS, tTDIS 5— n s
5 TMS, TDI Data Hold Time t TMSH, tTDIH 25 — ns
6 TCK Low to TDO Data Valid t TDOV —2 5 n s
7 TCK Low to TDO Data Invalid t TDOI 0— n s
8 TCK Low to TDO High Impedance t TDOHZ —2 0 n s
9 JCOMP Assertion Time t JCMPPW 100 — ns
10 JCOMP Setup Time to TCK Low t JCMPS 40 — ns
11 TCK Falling Edge to Output Valid t BSDV —5 0 n s
12 TCK Falling Edge to Output Valid out of High Impedance t BSDVZ —5 0 n s
13 TCK Falling Edge to Output High Impedance t BSDHZ —5 0 n s
14 Boundary Scan Input Valid to TCK Rising Edge t BSDST 50 — ns
15 TCK Rising Edge to Boundary Scan Input Invalid t BSDHT 50 — ns
PXN20 Microcontroller Data Sheet, Rev. 1 Figure 12. JTAG boundary scan timing
PXN20 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 47
4.14.4 Enhanced Modular I/O Subsystem (eMIOS)
Figure 13. eMIOS timing Table 28. eMIOS timing1 1 eMIOS timing specified at VDDE = 3.0 – 5.5 V, TA =T L to TH, and CL = 30 pF with SRC = 0b11. and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).
PXN20 Microcontroller Data Sheet, Rev. 1
4.14.5 Deserial Serial Peripheral Interface (DSPI)
Table 29. DSPI timing
116 MHz1
1 116 MHz timing specified at CL = 50 pF with SRC = 0b11.
1 DSPI Cycle Time
2 PCS to SCK Delay
2 The maximum value is programmable in DSPI_CTARn[PSSCK] and DSPI_CTARn[CSSCK].
3 After SCK Delay 3
3 The maximum value is programmable in DSPI_CTARn[PASC] and DSPI_CTARn[ASC].
5 Slave Access Time
6 Slave SOUT Disable Time
7 PCSx to PCSS time t PCSC 0— n s
9 Data Setup Time for Inputs
4 This number is calculated assuming the SMPL_PT bit field in DSPI_MCR is set to 0b10.
10 Data Hold Time for Inputs
11 Data Valid (after SCK edge)
12 Data Hold Time for Outputs
PXN20 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 53
4.14.6 MLB Interface
4.14.6.1 Media Local Bus DC Electrical Characteristics
Table 30 provides the DC electrical characteristics for the Media Local Bus interface. Table 30. Media Local Bus DC Electrical Characteristics
4.14.6.2 Media Local Bus (MLB) AC electrical characteristics
Table 31 and Table 32 provide the AC electrical characteristics for the Media Local Bus interface. Table 31. MLB timing for MLB speed 256 Fs or 512 Fs
512 Fs PLL unlocked
2 MLBCLK rise time t
3 MLBCLK fall time t mckf —— 3n s V IH to VIL
4 MLBCLK cycle time t mckc —8 1
256 Fs PLL unlocked
7 MLBCLK pulse width variation 2 tmpwv —— 2 n s p - p —
8 MLBSIG/MLBDAT input valid to
9 MLBSIG/MLBDAT input hold from
PXN20 Microcontroller Data Sheet, Rev. 1
10 MLBSIG/MLBDAT output high
tmcfdz 0— t mckl ns —
11 Bus Hold time 3 tmdzh 4— — n s —
12 MLBSIG/MLBDAT output valid from
tmcrdv —— 8n s — Ground = 0.0V Load Capacitance = 60 pF , SIU_PCR144–SIU_PCR146[DSC] = 0b11. MLB speed of 256 Fs or 512 Fs (Fs = 48 kHz) Unless otherwise noted, all timing parameters are specified from the valid voltage threshold in Table 30. 1 The Controller can shut off MLBCLK to place MLB in a low-power state. 2 Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in ns peak-to-peak (ns p-p). 3 The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed. Table 32. MLB timing for MLB speed 1024 Fs
1024 Fs PLL unlocked
2 MLBCLK rise time t mckr —— 1n s V IL to VIH
3 MLBCLK fall time t mckf —— 1n s V IH to VIL
11 Bus Hold time 3 tmdzh 2— — n s
Load Capacitance = 40 pF , SIU_PCR144–SIU_PCR146[DSC] = 0b00. Unless otherwise noted, timing parameters are specified from the valid voltage threshold in Table 30. Table 31. MLB timing for MLB speed 256 Fs or 512 Fs (continued)
PXN20 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 55 Figure 23. Media Local Bus (MLB) timing
4.14.7 Fast Ethernet Controller (FEC) interface
MII signals use CMOS signal levels compatible with devices operating at either 5.0 V or 3.3 V . Signals are not TTL compatible. They follow the CMOS electrical characteristics.
4.14.7.1 MII receive signal timing (R XD[3:0], RX_DV, RX_ER, and RX_CLK)
requirement. In addition, the system clock frequency must exceed four times the RX_CLK frequency. 1 The Controller can shut off MLBCLK to place MLB in a low-power state. edge, measured in ns peak-to-peak (ns p-p). time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed. Table 33. MII receive signal timing
PXN20 Microcontroller Data Sheet, Rev. 1 Figure 24. MII receive signal timing diagram
4.14.7.2 MII transmit signal timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)
requirement. In addition, the system clock frequency must exceed four times the TX_CLK frequency. TX_CLK, and the timing is the same in either case. This options allows the use of non-compliant MII PHYs. Refer to the Ethernet chapter for details of this option and how to enable it. Figure 25. MII transmit signal timing diagram
4.14.7.3 MII async inputs signal timing (CRS and COL)
Table 34. MII transmit signal timing1 1 Output pads configured with SRC = 0b11. Table 35. MII Async Inputs Signal Timing1 1 Output pads configured with SRC = 0b11.
PXN20 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 57 Figure 26. MII async inputs timing diagram
4.14.7.4 MII serial management channel timing (MDIO and MDC)
The FEC functions correctly with a maximum MDC frequency of 2.5 MHz. Figure 27. MII serial management channel timing diagram Table 36. MII serial management channel timing1 1 Output pads configured with SRC = 0b11.
5 Package characteristics
5.1 Package mechanical data
Figure 28. 208 MAPBGA package mechanical drawing
Figure 29. 208 MAPBGA package detail
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6 Revision history
Figure 37 describes the changes made to this document between revisions. Table 37. Revision history