PXAS37KBBE

XA-S3 PHILIPS | Alldatasheet

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Technical content

/C0080 /C0115 /C0111/C0110/C0111 /C0115 XA-S3 XA 16-bit microcontroller

32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D,

low voltage (2.7 V–5.5 V), I2C, 2 UARTs,

16 MB address range

Supersedes data of 2000 Aug 22

2000 Dec 01

Philips Semiconductors Preliminary specification XA-S3 XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2C, 2 UARTs, 16 MB address range

22000 Dec 01

The XA-S3 device is a member of Philips Semiconductors’ XA (eXtended Architecture) family of high performance 16-bit single-chip microcontrollers. The XA-S3 device combines many powerful peripherals on one chip. With its high performance A/D converter, timers/counters, watchdog, Programmable Counter Array (PCA), I 2C interface, dual UARTs, and multiple general purpose I/O ports, it is suited for general multipurpose high performance embedded control functions. Specific features of the XA-S3

• 2.7 V to 5.5 V operation.
• 32 K bytes of on-chip EPROM/ROM program memory.
• 1024 bytes of on-chip data RAM.
• Supports off-chip addressing up to 16 megabytes (24 address lines). A clock output reference is added to simplify external bus interfacing.
• High performance 8-channel 8-bit A/D converter with automatic channel scan and repeated read functions. Completes a conversion in 4.46 microseconds at 30 MHz. Alternate operating mode allows 10-bit conversion results.
• Three standard counter/timers with enhanced features. All timers have a toggle output capability.
• Watchdog timer.
• 5-channel 16-bit Programmable Counter Array (PCA).
• I2C-bus serial I/O port with byte-oriented master and slave functions.
• Two enhanced UARTs with independent baud rates.
• Seven software interrupts.
• Active low reset output pin indicates all reset occurrences (external reset, watchdog reset and the RESET instruction). A reset source register allows program determination of the cause of the most recent reset.
• 50 I/O pins, each with 4 programmable output configurations.
• 30 MHz operating frequency at 2.7–5.5 V VDD .
• Power saving operating modes: Idle and Power-down. Wake-up from power-down via an external interrupt is supported.
• 68-pin PLCC and 80-pin PQFP packages.

ORDERING INFORMATION

ROMless ROM EPROM TEMPERATURE RANGE ( °C) AND PACKAGE FREQ. (MHz) DRAWING NUMBER PXAS30KBA PXAS33KBA PXAS37KBA OTP 0 to +70, Commercial 68-pin Plastic Leaded Chip Carrier

30 SOT188-3

PXAS30KBBE PXAS33KBBE PXAS37KBBE OTP 0 to +70, Commercial 80-pin Plastic Low Profile Quad Flat Pack

30 SOT315-1

PXAS30KFA PXAS33KFA PXAS37KFA OTP –40°C to +85°C, Industrial 68-pin Plastic Leaded Chip Carrier PXAS30KFBE PXAS33KFBE PXAS37KFBE OTP –40°C to +85°C, Industrial 80-pin Plastic Low Profile Quad Flat Pack

Philips Semiconductors Preliminary specification XA-S3 XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2C, 2 UARTs, 16 MB address range

2000 Dec 01 3

P1.3/A3 P5.7/AD7/SDA 30 31 32 33 34 35 36 P4.7/A21 P3.0/RxD0 P3.1/TxD0 P3.2/INT0 P3.3/INT1 P3.5/T1/BUSW P3.4/T0 37 3828 29 P3.6/WRL P3.7/RD VSS RSTOUT PLASTIC LEADED CHIP CARRIER SU00936 V DD EA /WAIT/VPP P5.0/AD0 P5.1/AD1 P5.3/AD3 P5.2/AD2 39 40 41 42 43 P5.5/AD5 P5.6/AD6/SCL P1.0/A0/WRH P1.5/TxD1 P1.6/T2 P1.7/T2EX P6.0/A22 P2.1/A13D9 P2.0/A12D8 P0.7/A11D7 P0.6/A10D6 P0.5/A9D5 V DD VSS P0.4/A8D4 P0.3/A7D3 RST P0.2/A6D2 CLKOUT PSEN ALE/PROG P0.1/A5D1 P6.1/A23 P0.0/A4D0 7654321 68 6798 66 65 64 63 62 P4.6/A20 P4.5/CEX4 P4.4/CEX3 P4.3/CEX2 P4.2/CEX1 P4.1/CEX0 P4.0/ECI XTAL1 XTAL2 P2.7/A19D15 P2.6/A18D14 P2.5/A17D13 P2.4/A16D12 P2.3/A15D11 P2.2/A14D10 V DD P5.4/AD4 P1.4/RxD1 V SS AVREF– AVREF+ AVDD AV SS P1.1/A1 P1.2/A2

Philips Semiconductors Preliminary specification XA-S3 XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2C, 2 UARTs, 16 MB address range

2000 Dec 01 4

P2.2/A14D10 P2.3/A15D11 P2.4/A16D12 P2.5/A17D13 P2.6/A18D14 P2.7/A19D15 XTAL2 XTAL1 V DD 23 24 25 26 27 28 29 NC P4.7/A21 P3.0/RxD0 P3.1/TxD0 P3.2/INT0 P3.4/T0 P3.3/INT1 30 3121 22 P3.5/T1/BUSW P3.6/WRL RSTOUT P3.7/RD LOW PROFILE PLASTIC QUAD FLAT PACK SU00937 V SS VSS VDD VDD P5.0/AD0 EA /WAIT/VPP P5.1/AD1 P5.2/AD2 P5.3/AD3 32 33 34 35 36 NC P5.4/AD4 P5.5/AD5 P5.6/AD6/SCL P5.7/AD7/SDA AVSS AVSS P1.0/A0/WRH P1.1/A1 P1.2/A2 P1.3/A3 P1.4/RxD1 NC P2.1/A13D9 P2.0/A12D8 P0.7/A11D7 P0.6/A10D6 V SS P0.5/A9D5 VSS VDD P0.4/A8D4 VDD P0.3/A7D3 P0.2/A6D2 RST CLKOUT ALE/PROG PSEN P0.1/A5D1 P0.0/A4D0 P6.1/A23 78 77 76 75 74 73 72 71 7080 79 69 68 67 66 65 37 38 39 40 P1.5/TxD1 P1.6/T2 P1.7/T2EX P6.0/A22 64 63 62 61 AV REF– AV REF+ AV DD AV DD V SS V SS V DD P4.0/ECI P4.1/CEX0 P4.2/CEX1 P4.3/CEX2 P4.4/CEX3 P4.5/CEX4 P4.6/A20 NC

Philips Semiconductors Preliminary specification XA-S3 XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2C, 2 UARTs, 16 MB address range

2000 Dec 01 5

AV REF– AV SS CLKOUT ALE PSEN RSTOUT RST EA /WAIT TxD0 INT0 INT1 T1/BUSW WRL RD RxD0 RxD1 TxD1 T2EX WRH /A0 A23 A22 ADDRESS AND DATA BUS SU00847A

Philips Semiconductors Preliminary specification XA-S3 XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2C, 2 UARTs, 16 MB address range

2000 Dec 01 6

Timer 0, 1 I2C UART 1 UART 0 XA CPU Core Timer 2 Watchdog Timer Port 0 Port 1 Port 2

1024 Bytes

Philips Semiconductors Preliminary specification XA-S3 XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2C, 2 UARTs, 16 MB address range

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TYPE NAME AND FUNCTIONMNEMONIC PLCC LQFP TYPE NAME AND FUNCTION VSS 1, 20, 55 12, 13, 53, 54, 69, 70 I Ground: 0 V reference. VDD 2, 21, 54 14, 15, 51, 52, 71, 72 I Power Supply: This is the power supply voltage for normal, idle, and power down operation. RST 50 47 I Reset: A low on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor to begin execution at the address contained in the reset vector. RSTOUT 19 11 O Reset Output: This pin outputs a low whenever the XA-S3 processor is reset for any reason. This includes an external reset via the RST pin, watchdog reset, and the RESET instruction. ALE/PROG 47 44 I/O Address Latch Enable/Program Pulse: A high output on the ALE pin signals external circuitry to latch the address portion of the multiplexed address/data bus. A pulse on ALE occurs only when it is needed in order to process a bus cycle. PSEN 48 45 O Program Store Enable: The read strobe for external program memory. When the microcontroller accesses external program memory, PSEN is driven low in order to enable memory devices. PSEN is only active when external code accesses are performed. EA /WAIT/VPP 22 16 I External Access/Bus Wait: The EA input determines whether the internal program memory of the microcontroller is used for code execution. The value on the EA pin is latched as the external reset input is released and applies during later execution. When latched as a 0, external program memory is used exclusively. When latched as a 1, internal program memory will be used up to its limit, and external program memory used above that point. After reset is released, this pin takes on the function of bus WAIT input. If WAIT is asserted high during an external bus access, that cycle will be extended until WAIT is released. XTAL1 68 68 I Crystal 1: Input to the inverting amplifier used in the oscillator circuit and input to the internal clock generator circuits. XTAL2 67 67 I Crystal 2: Output from the oscillator amplifier. CLKOUT 49 46 O Clock Output: This pin outputs a buffered version of the internal CPU clock. The clock output may be used in conjunction with the external bus to synchronize WAIT state generators, etc. The clock output may be disabled by software. AV DD 33 28, 29 I Analog Power Supply: Positive power supply input for the A/D converter. AV SS 34 30, 31 I Analog Ground. AV REF+ 32 27 I A/D Positive Reference Voltage: High end reference for the A/D converter. AV REF– 31 26 I A/D Negative Reference Voltage: Low end reference for the A/D converter. 51–53, 56–58 42, 43, 48–50, 55–57 I/O Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type. Port 0 latches have 1s written to them and are configured in the quasi-bidirectional mode during reset. The operation of port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for details. When the external program/data bus is used, Port 0 becomes the multiplexed low data/instruction byte and address lines 4 through 11.

Philips Semiconductors Preliminary specification XA-S3 XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2C, 2 UARTs, 16 MB address range

2000 Dec 01 8

MNEMONIC NAME AND FUNCTION TYPE PIN NUMBER MNEMONIC NAME AND FUNCTION TYPE LQFPPLCC P1.0 – P1.7 35–42 32–39 I/O Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type. Port 1 latches have 1s written to them and are configured in the quasi-bidirectional mode during reset. The operation of port 1 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for details. Port 1 also provides various special functions as described below: 35 32 O A0/WRH (P1.0) Address bit 0 of the external address bus when the eternal data bus is configured for an 8-bit width. When the external data bus is configured for a 16-bit width, this pin becomes the high byte write strobe. 36 33 O A1 (P1.1): Address bit 1 of the external address bus. 37 34 O A2 (P1.2): Address bit 2 of the external address bus. 38 35 O A3 (P1.3): Address bit 3 of the external address bus. 39 36 I RxD1 (P1.4): Serial port 1 receiver input. 40 37 O TxD1 (P1.5): Serial port 1 transmitter output. 41 38 I/O T2 (P1.6): Timer/counter 2 external count input or overflow output. 42 39 O T2EX (P1.7): Timer/counter 2 reload/capture/direction control. P2.0 – P2.7 59–66 58, 59, 61–66 I/O Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type. Port 2 latches have 1s written to them and are configured in the quasi-bidirectional mode during reset. The operation of port 2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for details. When the external program/data bus is used in 16-bit mode, Port 2 becomes the multiplexed high data/instruction byte and address lines 12 through 19. When the external data/address bus is used in 8-bit mode, the number of address lines that appear on Port 2 is user programmable in groups of 4 bits. P3.0 – P3.7 11–18 3–10 I/O Port 3: Port 3 is an 8-bit I/O port with a user-configurable output type. Port 3 latches have 1s written to them and are configured in the quasi-bidirectional mode during reset. The operation of port 3 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for details. Port 3 also provides the various special functions as described below: 11 3 I RxD0 (P3.0): Receiver input for serial port 0. 12 4 O TxD0 (P3.1): Transmitter output for serial port 0. 13 5 I INT0 (P3.2): External interrupt 0 input. 14 6 I INT1 (P3.3): External interrupt 1 input. 15 7 I/O T0 (P3.4): Timer/counter 0 external count input or overflow output. 16 8 I/O T1 / BUSW (P3.5): Timer/counter 1 external count input or overflow output. The value on this pin is latched as an external chip reset is completed and defines the default external data bus width. 17 9 O WRL (P3.6): External data memory low byte write strobe. 18 10 O RD (P3.7): External data memory read strobe. P4.0 – P4.7 3–10 73–79, 2 I/O Port 4: Port 4 is an 8-bit I/O port with a user-configurable output type. Port 4 latches have 1s written to them and are configured in the quasi-bidirectional mode during reset. The operation of Port 4 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for details. Port 4 also provides various special functions as described below: 3 73 I ECI (P4.0): PCA External clock input. 4 74 I/O CEX0 (P4.1): Capture/compare external I/O for PCA module 0. 5 75 I/O CEX1 (P4.2): Capture/compare external I/O for PCA module 1. 6 76 I/O CEX2 (P4.3): Capture/compare external I/O for PCA module 2. 7 77 I/O CEX3 (P4.4): Capture/compare external I/O for PCA module 3. 8 78 I/O CEX4 (P4.5): Capture/compare external I/O for PCA module 4. 9 79 O A20 (P4.6): Address bit 20 of the external address bus. 10 2 O A21 (P4.7): Address bit 21 of the external address bus.

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configuration and the DC Electrical Characteristics for details. inputs must be configured by the user to the high impedance mode. 23 17 I AD0 (P5.0): A/D channel 0 input. 24 18 I AD1 (P5.1): A/D channel 1 input. 25 19 I AD2 (P5.2): A/D channel 2 input. 26 20 I AD3 (P5.3): A/D channel 3 input. 27 22 I AD4 (P5.4): A/D channel 4 input. 28 23 I AD5 (P5.5): A/D channel 5 input. 29 24 I/O AD6/SCL (P5.6): A/D channel 6 input. I2C serial clock input/output. 30 25 I/O AD7/SDA (P5.7): A/D channel 7 input. I2C serial data input/output. configuration and the DC Electrical Characteristics for details. 43 40 O A22 (P6.0): Address bit 22 of the external address bus. 44 41 O A23 (P6.1): Address bit 23 of the external address bus. Table 1. Special Function Registers

Philips Semiconductors Preliminary specification XA-S3 XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2C, 2 UARTs, 16 MB address range

2000 Dec 01 10

ResetBIT FUNCTIONS AND ADDRESSESSFR NAME ValueLSBMSBAddressDESCRIPTION CCAPM2# PCA module 2 mode 493 – ECOM2 CAPP2 CAPN2 MAT2 TOG2 PWM2 ECCF2 00h CCAPM3# PCA module 3 mode 494 – ECOM3 CAPP3 CAPN3 MAT3 TOG3 PWM3 ECCF3 00h CCAPM4# PCA module 4 mode 495 – ECOM4 CAPP4 CAPN4 MAT4 TOG4 PWM4 ECCF4 00h CCAP0H# PCA module 0 capture high byte497 xx CCAP1H# PCA module 1 capture high byte499 xx CCAP2H# PCA module 2 capture high byte49B xx CCAP3H# PCA module 3 capture high byte49D xx CCAP4H# PCA module 4 capture high byte49F xx CCAP0L# PCA module 0 capture low byte496 xx CCAP1L# PCA module 1 capture low byte498 xx CCAP2L# PCA module 2 capture low byte49A xx CCAP3L# PCA module 3 capture low byte49C xx CCAP4L# PCA module 4 capture low byte49E xx CS Code segment 443 00h DS Data segment 441 00h ES Extra segment 442 00h 367 366 365 364 363 362 361 360 I2CON#* I2C control register 42C CR2 ENA STA STO SI AA CR1 CR0 00h I2STAT# I2C status register 46C I2C Status Code/Vector 0 0 0 F8h I2DAT# I2C data register 46D xx I2ADDR# I2C address register 46E I2C Slave Address GC 00h 33F 33E 33D 33C 33B 33A 339 338 IEH* Interrupt enable high byte 427 – – – – ETI1 ERI1 ETI0 ERI0 00h 337 336 335 334 333 332 331 330 IEL#* Interrupt enable low byte 426 EA EAD EPC ET2 ET1 EX1 ET0 EX0 00h 377 376 375 374 373 372 371 370 IELB#* Interrupt enable B low byte 42E – – EI2 EC4 EC3 EC2 EC1 EC0 00h IPA0 Interrupt priority A0 4A0 – PT0 – PX0 00h IPA1 Interrupt priority A1 4A1 – PT1 – PX1 00h IPA2# Interrupt priority A2 4A2 – PPC – PT2 00h IPA3# Interrupt priority A3 4A3 – – – PAD 00h IPA4 Interrupt priority A4 4A4 – PTI0 – PRI0 00h IPA5 Interrupt priority A5 4A5 – PTI1 – PRI1 00h IPB0# Interrupt priority B0 4A8 – PC1 – PC0 00h IPB1# Interrupt priority B1 4A9 – PC3 – PC2 00h IPB2# Interrupt priority B2 4AA – PI2 – PC4 00h 387 386 385 384 383 382 381 380 P0* Port 0 430 A11D7 A10D6 A9D5 A8D4 A7D3 A6D2 A5D1 A4D0 FFh 38F 38E 38D 38C 38B 38A 389 388 P1* Port 1 431 T2EX T2 TxD1 RxD1 A3 A2 A1 A0/WRH FFh 397 396 395 394 393 392 391 390 P2* Port 2 432 A19D15 A18D14 A17D13 A16D12 A15D11 A14D10 A13D9 A12D8 FFh 39F 39E 39D 39C 39B 39A 399 398 P3* Port 3 433 RD WRL T1 T0 INT1 INT0 TxD0 RxD0 FFh 3A7 3A6 3A5 3A4 3A3 3A2 3A1 3A0 P4#* Port 4 434 A21 A20 CEX4 CEX3 CEX2 CEX1 CEX0 ECI FFh

Philips Semiconductors Preliminary specification XA-S3 XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2C, 2 UARTs, 16 MB address range

2000 Dec 01 11

ResetBIT FUNCTIONS AND ADDRESSESSFR NAME ValueLSBMSBAddressDESCRIPTION 3AF 3AE 3AD 3AC 3AB 3AA 3A9 3A8 P5#* Port 5 435 AD7/SDA AD6/SCL AD5 AD4 AD3 AD2 AD1 AD0 FFh 3B1 3B0 P0CFGA Port 0 configuration A 470 Note 5 P1CFGA Port 1 configuration A 471 Note 5 P2CFGA Port 2 configuration A 472 Note 5 P3CFGA Port 3 configuration A 473 Note 5 P4CFGA# Port 4 configuration A 474 Note 5 P5CFGA# Port 5 configuration A 475 Note 5 P6CFGA# Port 6 configuration A 476 – – – – – – Note 5 P0CFGB Port 0 configuration B 4F0 Note 5 P1CFGB Port 1 configuration B 4F1 Note 5 P2CFGB Port 2 configuration B 4F2 Note 5 P3CFGB Port 3 configuration B 4F3 Note 5 P4CFGB# Port 4 configuration B 4F4 Note 5 P5CFGB# Port 5 configuration B 4F5 Note 5 P6CFGB# Port 6 configuration B 4F6 – – – – – – Note 5 227 226 225 224 223 222 221 220 PCON* Power control register 404 – – – – – – PD IDL 00h 20F 20E 20D 20C 20B 20A 209 208 PSWH* Program status word (high byte)401 SM TM RS1 RS0 IM3 IM2 IM1 IM0 Note 2 207 206 205 204 203 202 201 200 PSWL* Program status word (low byte)400 C AC – – – V N Z Note 2 217 216 215 214 213 212 211 210 PSW51* 80C51 compatible PSW 402 C AC F0 RS1 RS0 V F1 P Note 3 RSTSRC# Reset source register 463 – – – – – R_WD R_CMD R_EXT Note 7 RTH0 Timer 0 reload register, high byte455 00h RTH1 Timer 1 reload register, high byte457 00h RTL0 Timer 0 reload register, low byte454 00h RTL1 Timer 1 reload register, low byte456 00h 307 306 305 304 303 302 301 300 S0CON* Serial port 0 control register420 SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 00h 30F 30E 30D 30C 30B 30A 309 308 S0STAT#* Serial port 0 extended status421 – – – ERR0 FE0 BR0 OE0 STINT0 00h S0BUF Serial port 0 data buffer register460 xx S0ADDR Serial port 0 address register461 00h S0ADEN Serial port 0 address enable 462 00h 327 326 325 324 323 322 321 320 S1CON* Serial port 1 control register424 SM0_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 00H 32F 32E 32D 32C 32B 32A 329 328 S1STAT#* Serial port 1 extended status425 – – – ERR1 FE1 BR1 OE1 STINT1 00h S1BUF Serial port 1 data buffer register464 xx S1ADDR Serial port 1 address register465 00h

Philips Semiconductors Preliminary specification XA-S3 XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2C, 2 UARTs, 16 MB address range

2000 Dec 01 12

ResetBIT FUNCTIONS AND ADDRESSESSFR NAME ValueLSBMSBAddressDESCRIPTION S1ADEN Serial port 1 address enable 466 00h SCR System configuration register440 – – – – PT1 PT0 CM PZ 00h 21F 21E 21D 21C 21B 21A 219 218 SSEL* Segment selection register 403 ESWEN R6SEG R5SEG R4SEG R3SEG R2SEG R1SEG R0SEG 00h SWE Software interrupt enable 47A – SWE7 SWE6 SWE5 SWE4 SWE3 SWE2 SWE1 00h 357 356 355 354 353 352 351 350 SWR* Software interrupt request 42A – SWR7 SWR6 SWR5 SWR4 SWR3 SWR2 SWR1 00h 2C7 2C6 2C5 2C4 2C3 2C2 2C1 2C0 T2CON* Timer 2 control register 418 TF2 EXF2 RCLK0 TCLK0 EXEN2 TR2 C/T2 CP/RL2 00h 2CF 2CE 2CD 2CC 2CB 2CA 2C9 2C8 T2MOD* Timer 2 mode control 419 – – RCLK1 TCLK1 – – T2OE DCEN 00h TH2 Timer 2 high byte 459 00h TL2 Timer 2 low byte 458 00h T2CAPH Timer 2 capture, high byte 45B 00h T2CAPL Timer 2 capture, low byte 45A 00h 287 286 285 284 283 282 281 280 TCON* Timer 0 and 1 control register410 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00h TH0 Timer 0 high byte 451 00h TH1 Timer 1 high byte 453 00h TL0 Timer 0 low byte 450 00h TL1 Timer 1 low byte 452 00h TMOD Timer 0 and 1 mode control 45C GATE C/T M1 M0 GATE C/T M1 M0 00h 28F 28E 28D 28C 28B 28A 289 288 TSTAT* Timer 0 and 1 extended status411 – – – – – T1OE – T0OE 00h 2FF 2FE 2FD 2FC 2FB 2FA 2F9 2F8 WDCON* Watchdog control register 41F PEW2 PRE1 PRE0 – – WDRUN WDTOF – Note 6 WDL Watchdog timer reload 45F 00h WFEED1 Watchdog feed 1 45D xx WFEED2 Watchdog feed 2 45E xx NOTES: * SFRs are bit addressable. # SFRs are modified from or added to XA-G3 SFRs. 1. At reset, the BCR is loaded with the binary value 00000a11, where “a’ is the value on the BUSW pin. This defaults the address bus size to 24 bits. 2. SFR is loaded from the reset vector. 3. All bits except F1, F0, and P are loaded from the reset vector. Those bits are all 0. 4. Unimplemented bits in SFRs are X (unknown) at all times. Ones should not be written to these bits since they may be used for other purposes in future XA derivatives. The reset value shown for these bits is 0. 5. Port configurations default to quasi-bidirectional when the XA begins execution from internal code memory after reset, based on the condition found on the EA pin. Thus, all PnCFGA registers will contain FF, and PnCFGB register will contain 00 when the XA begins execution using internal code memory. When the XA begins execution using external code memory, the default configuration for pins that are associated with the external bus will be push-pull. The PnCFGA and PnCFGB register contents will reflect this difference. 6. The WDCON reset value is E6 for a Watchdog reset, E4 for all other reset causes. 7. The RSTSRC register reflects the cause of the last XA-S3 reset. One bit will be set to 1, the others will be cleared to 0. 8. The XA guards writes to certain bits (typically interrupt flags) that may be altered directly by a peripheral function. This prevents loss of an interrupt or other status if a bit was written directly by a peripheral action during the time between the read and write portions of an instruction that performs a read-modify-write operation. Examples of such instructions are: and s0con,#$fb clr tr0 setb ti_0 XA-S3 SFR bits that are guarded in this manner are: ADINT (in ADCON); CF, CCF4, CCF3, CCF2, CCF1, and CCF0 (in CCON); SI (in I2CON); TI_0 and RI_0 (in S0CON); TI_1 and RI_1 (in S1CON); FE0, BR0, and OE0 (in S0STAT); FE1, BR1, and OE1 (in S1STAT); TF2 (in T2CON); TF1, TF0, IE1, and IE0 (in TCON); and WDTOF (in WDCON). 9. The XA-S3 implements an 8-bit SFR bus, as stated in Chapter 8 of the XA User Guide. All SFR accesses must be 8-bit operations. Attempts to write 16 bits to an SFR will actually write only the lower 8 bits. Sixteen bit SFR reads will return undefined data in the upper byte.

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Figure 1. XA-S3 program memory map Figure 2. XA-S3 data memory map

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Details of XA-S3 functions will be described in the following sections. resolution. The A/D input range is limited to 0 to AVDD (3.3 V max.). A/D inputs must be set to the “off” (high impedance, input only) mode. order to provide the fastest possible conversion. complete a conversion, and the timing must be set differently in ADCFG. skipped. The ADCS register is detailed in Figure 2. channels have been converted once. pending interrupt. ADINT must be cleared by software. the ADCFG register, as shown in Figure 3, Table 2 and Table 3. conversions with a lower external source driving the A/D inputs. increasing A/D conversion times. ADCON.7 — Reserved for future use. Should not be set to 1 by user programs. ADCON.6 — Reserved for future use. Should not be set to 1 by user programs. ADCON.5 — Reserved for future use. Should not be set to 1 by user programs. ADCON.4 — Reserved for future use. Should not be set to 1 by user programs. ADCON.3 ADRES Selects 8-bit (0) or 10-bit (1) conversion mode. ADCON.2 ADMOD A/D mode select. 1 = continuous scan of selected inputs after a start of the A/D. 0 = single scan of selected inputs after a start of the A/D. converted in either the single scan or continuous scan modes. Must be cleared by software. Figure 1. A/D Control Register (ADCON)

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ADCS.7 ADCS7 A/D channel 7 select bit. ADCS.6 ADCS6 A/D channel 6 select bit. ADCS.5 ADCS5 A/D channel 5 select bit. ADCS.4 ADCS4 A/D channel 4 select bit. ADCS.3 ADCS3 A/D channel 3 select bit. ADCS.2 ADCS2 A/D channel 2 select bit. ADCS.1 ADCS1 A/D channel 1 select bit. ADCS.0 ADCS0 A/D channel 0 select bit. Figure 2. A/D Channel Select Register (ADCS) ADCFG.7 — Reserved for future use. Should not be set to 1 by user programs. ADCFG.6 — Reserved for future use. Should not be set to 1 by user programs. ADCFG.5 — Reserved for future use. Should not be set to 1 by user programs. ADCFG.4 — Reserved for future use. Should not be set to 1 by user programs. ADCFG.3–0 ADCFG A/D timing configuration (see text and table). Figure 3. A/D Timing Configuration Register (ADCFG) Table 2. A/D Timing Configuration

1. These settings provide additional A/D input sampling time, in order to allow accurate readings with a higher external source impedance.

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Table 3. A/D Timing Configuration for 10-bit Mode equivalent resistance and capacitance related to the A/D inputs. different A/D timing configuration. causes the analog input to present a varying load to the pin. Figure 4. A/D Input: Equivalent Circuit

2000 Dec 01 17

of additional A/D error to the number of samples that are averaged. A/D accuracy should be de-rated by ±1.25 LSB. Figure 5. A/D accuracy by number of averaging samples I2CON.7 CR2 I 2C Rate Control, with CR1 and CR0. See text and table. I2CON.6 ENA Enable I 2C port. When ENA = 1, the I2C port is enabled. generating a Start condition. I2CON.4 STO Stop flag. Setting STO to 1 causes the I 2C interface to attempt to generate a Stop condition. software needs to respond. SI causes an I2C interrupt if enabled and of sufficient priority. acknowledge pulses for various conditions (see text). I2CON.1 CR1 I 2C Rate Control, with CR2 and CR0. See text and table. I2CON.0 CR0 I 2C Rate Control, with CR2 and CR1. See text and table. Figure 6. I2C Control Register (I2CON)

Philips Semiconductors Preliminary specification XA-S3 XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2C, 2 UARTs, 16 MB address range

2000 Dec 01 18

The I2C interface on the XA-S3 is identical to the standard byte-style I2C interface found on devices such as the 8xC552 except for the rate selection. The I2C interface conforms to the 100 kHz I2C specification, but may be used at rates up to 400 kHz (non-conforming). Important: Before the I2C interface may be used, the port pins P5.6 and 5.7, which correspond to the I2C functions SCL and SDA respectively, must be set to the open drain mode. The processor interfaces to the I2C logic via the following four special function registers: I2CON (I2C control register), I2STA (I2C status register), I2DAT (I2C data register), and I2ADR (I2C slave address register). The I2C control logic interfaces to the external I2C bus via two port 5 pins: P5.6/SCL (serial clock line) and P5.7/SDA (serial data line). The Control Register, I2CON This register is shown in Figure 6. Two bits are affected by the I2C hardware: the SI bit is set when a serial interrupt is requested, and the STO bit is cleared when a STOP condition is present on the I2C bus. The STO bit is also cleared when ENA = “0”. ENA, the I2C Enable Bit ENA = 0: When ENA is “0”, the SDA and SCL outputs are not driven. SDA and SCL input signals are ignored, SIO1 is in the “not addressed” slave state, and the STO bit in I2CON is forced to “0”. No other bits are affected. P5.6 and P5.7 may be used as open drain I/O ports. ENA = 1: When ENA is “1”, SIO1 is enabled. The P5.6 and P5.7 port latches must be set to logic 1. ENA should not be used to temporarily release the I 2C-bus since, when ENA is reset, the I2C-bus status is lost. The AA flag should be used instead (see description of the AA flag in the following text). In the following text, it is assumed the ENA = “1”. STA, the START flag STA = 1: When the STA bit is set to enter a master mode, the I2C hardware checks the status of the I2C bus and generates a START condition if the bus is free. If the bus is not free, the I2C interface waits for a STOP condition (which will free the bus) and generates a START condition after a delay of a half clock period of the internal serial clock generator. If STA is set while the I 2C interface is already in a master mode and one or more bytes are transmitted or received, the hardware transmits a repeated START condition. STA may be set at any time. STA may also be set when the I 2C interface is an addressed slave. STA = 0: When the STA bit is reset, no START condition or repeated START condition will be generated. STO, the STOP flag STO = 1: When the STO bit is set while the I2C interface is in a master mode, a STOP condition is transmitted to the I2C bus. When the STOP condition is detected on the bus, the hardware clears the STO flag. In a slave mode, the STO flag may be set to recover from an error condition. In this case, no STOP condition is transmitted to the I2C bus. However, the hardware behaves as if a STOP condition has been received and switches to the defined “not addressed” slave receiver mode. The STO flag is automatically cleared by hardware. If the STA and STO bits are both set, then a STOP condition is transmitted to the I2C bus if the interface is in a master mode (in a slave mode, the hardware generates an internal STOP condition which is not transmitted). The I2C interface then transmits a START condition. STO = 0: When the STO bit is reset, no STOP condition will be generated. SI, the Serial Interrupt flag SI = 1:When the SI flag is set, and the EA (interrupt system enable) and EI2 (I2C interrupt enable) bits are also set, an I2C interrupt is requested. SI is set by hardware when one of 25 of the 26 possible I2C interface states is entered. The only state that does not cause SI to be set is state F8H, which indicates that no relevant state information is available. While SI is set, the low period of the serial clock on the SCL line is stretched, and the serial transfer is suspended. A high level on the SCL line is unaffected by the serial interrupt flag. SI must be reset by software. SI = 0:When the SI flag is reset, no serial interrupt is requested, and there is no stretching of the serial clock on the SCL line. AA, the Assert Acknowledge flag AA = 1: If the AA flag is set, an acknowledge (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when:

• The “own slave address” has been received.
• The general call address has been received while the general call bit (GC) in I2ADR is set.
• A data byte has been received while the I2C interface is in the master receiver mode.
• A data byte has been received while the I2C interface is in the addressed slave receiver mode. AA = 0: If the AA flag is reset, a not acknowledge (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line when:
• A data byte has been received while the I2C interface is in the master receiver mode.
• A data byte has been received while the I2C interface is in the addressed slave receiver mode. When the I2C interface is in the addressed slave transmitter mode, state C8H will be entered after the last serial data byte is transmitted. When SI is cleared, the I 2C interface leaves state C8H, enters the not addressed slave receiver mode, and the SDA line remains at a high level. In state C8H, the AA flag can be set again for future address recognition. When the I2C interface is in the not addressed slave mode, its own slave address and the general call address are ignored. Consequently, no acknowledge is returned, and a serial interrupt is not requested. Thus, the hardware can be temporarily released from the I 2C bus while the bus status is monitored. While the hardware is released from the bus, START and STOP conditions are detected, and serial data is shifted in. Address recognition can be resumed at any time by setting the AA flag. If the AA flag is set when the part’s own slave address or the general call address has been partly received, the address will be recognized at the end of the byte transmission.

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Table 4 are unimportant when the I2C hardware is in a slave mode. the incoming clock frequency. serial interrupt is requested (SI = “1”). Table 4. I2C Rate Control

8 MHz 12 MHz 16 MHz 20 MHz 24 MHz 30 MHz

1. The XA-S3 I2C interface does not conform to the 400kHz I2C specification (which applies to rates greater than 100kHz) in all details, but

may be used with care where higher rates are required by the application.

1. The timer 1 overflow is used to clock the I2C interface. The resulting bit rate is 1/2 of the timer overflow rate.

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also be used as baud rate generators for either or both of the UARTs. These are identical to the standard XA-G3 timer 0 and 1. This is identical to the standard XA-G3 timer 2. configuration is shown in Figure 7.

0 X TCLK (Osc/4, Osc/16, or Osc/64)

In the CMOD SFR are three additional bits associated with the PCA. each PCA module may generate a separate interrupt. flags for the PCA timer (CF) and each module (refer to Figure 11). and the module’s capture/compare register. ECOM (CCAPMn.6) when set enables the comparator function. these registers are used to control the duty cycle of the output.

16 BITS

Figure 7. Programmable Counter Array (PCA)

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Figure 8. PCA Timer/Counter Figure 9. PCA Interrupt System

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it to be gated off during idle. WDTE Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it. CPS1 PCA Count Pulse Select bit 1. CPS0 PCA Count Pulse Select bit 0. 0, and its active value will be 1. The value read from a reserved bit is indeterminate. Figure 10. CMOD: PCA Counter Mode Register set. CF may be set by either hardware or software but can only be cleared by software. – Not implemented, reserved for future use*. CCF4 PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF3 PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF2 PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF1 PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF0 PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. Each of CCF4 through CCF0 generates its own interrupt, and has its own interrupt vector. 0, and its active value will be 1. The value read from a reserved bit is indeterminate. Figure 11. CCON: PCA Counter Control Register

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– Not implemented, reserved for future use*. ECOMn Enable Comparator. ECOMn = 1 enables the comparator function. CAPPn Capture Positive, CAPPn = 1 enables positive edge capture. CAPNn Capture Negative, CAPNn = 1 enables negative edge capture. in CCON to be set, flagging an interrupt. PWMn Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse width modulated output. ECCFn Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate an interrupt. and its active value will be 1. The value read from a reserved bit is indeterminate. Figure 12. CCAPMn: PCA Modules Compare/Capture Registers Figure 13. PCA Module Modes (CCAPMn Register) SFR are set then an interrupt will be generated. Refer to Figure 14.

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Figure 14. PCA Capture Mode Figure 15. PCA Compare Mode

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Figure 16. PCA High Speed Output Mode Figure 17. PCA PWM Mode

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Figure 18. PCA Watchdog Timer m(Module 4 only) generated. This will not cause the RST pin to be driven low.

1. periodically change the compare value so it will never match the
2. periodically change the PCA timer value so it will never match
3. disable the watchdog by clearing the WDTE bit before a match

occurs and then re-enable it. astray, a match will eventually occur and cause an internal reset.

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; Main program goes here, but CALL WATCHDOG periodically. Figure 19. PCA Watchdog Timer Initialization Code EPROM, ROM, and ROMless parts, as in the XA-G3. service routine. Baud rate sources may be timer 1 or timer 2. enhanced UART used on the XA-G3. overflow rate (in UART modes 1 and 3). RB8 in Special Function Register SnCON. The baud rate is variable. in Special Function Register SnCON, while the stop bit is ignored. The baud rate is programmable to 1/32 of the oscillator frequency. bits (LSB first), a programmable 9th data bit, and a stop bit (1). rate. The baud rate in Mode 3 is variable. initiated in the other modes by the incoming start bit if REN_n = 1.

Philips Semiconductors Preliminary specification XA-S3 XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2C, 2 UARTs, 16 MB address range

2000 Dec 01 28

Serial Port Control Register The serial port control and status register is the Special Function Register SnCON, shown in Figure 21. This register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (TB8_n and RB8_n), and the serial port interrupt bits (TI_n and RI_n). TI Flag In order to allow easy use of the double buffered UART transmitter feature, the TI_n flag is set by the UART hardware under two conditions. The first condition is the completion of any byte transmission. This occurs at the end of the stop bit in modes 1, 2, or 3, or at the end of the eighth data bit in mode 0. The second condition is when SnBUF is written while the UART transmitter is idle. In this case, the TI_n flag is set in order to indicate that the second UART transmitter buffer is still available. Typically, UART transmitters generate one interrupt per byte transmitted. In the case of the XA UART, one additional interrupt is generated as defined by the stated conditions for setting the TI_n flag. This additional interrupt does not occur if double buffering is bypassed as explained below. Note that if a character oriented approach is used to transmit data through the UART, there could be a second interrupt for each character transmitted, depending on the timing of the writes to SBUF. For this reason, it is generally better to bypass double buffering when the UART transmitter is used in character oriented mode. This is also true if the UART is polled rather than interrupt driven, and when transmission is character oriented rather than message or string oriented. The interrupt occurs at the end of the last byte transmitted when the UART becomes idle. Among other things, this allows a program to determine when a message has been transmitted completely. The interrupt service routine should handle this additional interrupt. The recommended method of using the double buffering in the application program is to have the interrupt service routine handle a single byte for each interrupt occurrence. In this manner the program essentially does not require any special considerations for double buffering. Unless higher priority interrupts cause delays in the servicing of the UART transmitter interrupt, the double buffering will result in transmitted bytes being tightly packed with no intervening gaps. 9-bit Mode Please note that the ninth data bit (TB8) is not double buffered. Care must be taken to insure that the TB8 bit contains the intended data at the point where it is transmitted. Double buffering of the UART transmitter may be bypassed as a simple means of synchronizing TB8 to the rest of the data stream. Bypassing Double Buffering The UART transmitter may be used as if it is single buffered. The recommended UART transmitter interrupt service routine (ISR) technique to bypass double buffering first clears the TI_n flag upon entry into the ISR, as in standard practice. This clears the interrupt that activated the ISR. Secondly, the TI_n flag is cleared immediately following each write to SnBUF. This clears the interrupt flag that would otherwise direct the program to write to the second transmitter buffer. If there is any possibility that a higher priority interrupt might become active between the write to SnBUF and the clearing of the TI_n flag, the interrupt system may have to be temporarily disabled during that sequence by clearing, then setting the EA bit in the IEL register. CLOCKING SCHEME/BAUD RATE GENERATION The XA UARTS clock rates are determined by either a fixed division (modes 0 and 2) of the oscillator clock or by the Timer 1 or Timer 2 overflow rate (modes 1 and 3). The clock for the UARTs in XA runs at 16x the Baud rate. If the timers are used as the source for Baud Clock, since maximum speed of timers/Baud Clock is Osc/4, the maximum baud rate is timer overflow divided by 16 i.e. Osc/64. In Mode 0, it is fixed at Osc/16. In Mode 2, however, the fixed rate is Osc/32.

00 Osc/4

01 Osc/16

for all Timers T0,1,2 controlled by PT1, PT0 10 Osc/64controlled by PT1, PT0 bits in SCR 11 reserved Baud Rate for UART Mode 0: Baud_Rate = Osc/16 Baud Rate calculation for UART Mode 1 and 3: Baud_Rate = Timer_Rate/16 Timer_Rate = Osc/(N*(Timer_Range– Timer_Reload_Value)) where N = the TCLK prescaler value: 4, 16, or 64. and Timer_Range = 256 for timer 1 in mode 2. 65536 for timer 1 in mode 0 and timer 2 in count up mode. The timer reload value may be calculated as follows: Timer_Reload_Value = Timer_Range–(Osc/(Baud_Rate*N*16)) NOTES: 1.. The maximum baud rate for a UART in mode 1 or 3 is Osc/64. 2.. The lowest possible baud rate (for a given oscillator frequency and N value) may be found by using a timer reload value of 0. 3.. The timer reload value may never be larger than the timer range. 4.. If a timer reload value calculation gives a negative or fractional result, the baud rate requested is not possible at the given oscillator frequency and N value. Baud Rate for UART Mode 2: Baud_Rate = Osc/32 Using Timer 2 to Generate Baud Rates Timer T2 is a 16-bit up/down counter in XA. As a baud rate generator, timer 2 is selected as a clock source for either/both UART0 and UART1 transmitters and/or receivers by setting TCLKn and/or RCLKn in T2CON and T2MOD. As the baud rate generator, T2 is incremented as Osc/N where N = 4, 16 or 64 depending on TCLK as programmed in the SCR bits PT1, and PTO. So, if T2 is the source of one UART, the other UART could be clocked by either T1 overflow or fixed clock, and the UARTs could run independently with different baud rates. T2CON bit5 bit4 0x418 RCLK0 TCLK0 T2MOD bit5 bit4 0x419 RCLK1 TCLK1 Prescaler Select for Timer Clock (TCLK) SCR bit3 bit2 0x440 PT1 PT0

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SnSTAT.3 FEn Framing Error flag is set when the receiver fails to see a valid STOP bit at the end of the frame. a user program may poll. Cleared by software. received while RI in SnCON is still set. Cleared by software. only way it can be cleared is by a software write to this register. Figure 20. Serial Port Extended Status (SnSTAT) Register Table 5. Interrupt Vector Locations for UARTs its SM2 bit and prepare to receive the data bytes that will be coming. go on about their business, ignoring the coming data bytes. interrupt will not be activated unless a valid stop bit is received. address which the master will use for addressing each of the slaves.

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necessary to make bit 2 = 1 to exclude slave 2. broadcast address will be FF hexadecimal. UART drivers which do not make use of this feature. valid stop bit was not received. In Mode 0, SM2 should be 0. SnCON.4 REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception. double buffered. See text for details. received. In Mode 0, RB8 is not used. SnCON.1 TI Transmit interrupt flag. Set when another byte may be written to the UART transmitter. See text for details. Must be cleared by software. in the other modes (except see SM2). Must be cleared by software. Figure 21. Serial Port Control (SnCON) Register

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Figure 22. UART Framing Error Detection – WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS. Figure 23. UART Multiprocessor Communication, Automatic Address Recognition drain, quasi-bidirectional, push-pull, and off. CLKD bit that has been added to the BCR register. Active low reset input, the same as the XA-G3. system that the XA-S3 has been reset. Watchdog reset. Figure 24 shows the fields in the RSTSRC register.

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RSTSRC.7 — Reserved for future use. Should not be set to 1 by user programs. RSTSRC.6 — Reserved for future use. Should not be set to 1 by user programs. RSTSRC.5 — Reserved for future use. Should not be set to 1 by user programs. RSTSRC.4 — Reserved for future use. Should not be set to 1 by user programs. RSTSRC.3 — Reserved for future use. Should not be set to 1 by user programs. RSTSRC.2 R_WD Indicates that the last reset was caused by a watchdog timer overflow. RSTSRC.1 R_CMD Indicates that the last reset was caused by execution of the RESET instruction. Figure 24. Reset source register (RSTSRC)

• External interrupts 0 and 1 (2)
• Timer 0, 1, and 2 interrupts (3)
• PCA: 1 global and 5 channel interrupts (6)
• A/D interrupt (1)
• UART 0 transmitter and receiver interrupts (2)
• UART 1 transmitter and receiver interrupts (2)
• I2C interrupt (1)
• Software interrupts (7) There are a total of 17 hardware interrupt sources, enable bits, priority bit sets, etc. The XA-S3 supports a total of 17 maskable event interrupt sources (for the various XA peripherals), seven software interrupts, 5 exception interrupts (plus reset), and 16 traps. The maskable event interrupts share a global interrupt disable bit (the EA bit in the IEL register) and each also has a separate individual interrupt enable bit (in the IEL or IEH registers). Only three bits of the IPA register values are used on the XA-S3. Each event interrupt can be set to occur at one of 8 priority levels via bits in the Interrupt Priority (IP) registers, IPA0 through IPA5. The value 0 in the IPA field gives the interrupt priority 0, in effect disabling the interrupt. A value of 1 gives the interrupt a priority of 9, the value 2 gives priority 10, etc. The result is the same as if all four bits were used and the top bit set for all values except 0. Details of the priority scheme may be found in the XA User Guide. The complete interrupt vector list for the XA-S3, including all 4 interrupt types, is shown in the following tables. The tables include the address of the vector for each interrupt, the related priority register bits (if any), and the arbitration ranking for that interrupt source. The arbitration ranking determines the order in which interrupts are processed if more than one interrupt of the same priority occurs simultaneously. EXCEPTION/TRAPS PRECEDENCE DESCRIPTION VECTOR ADDRESS ARBITRATION RANKING Reset (h/w, watchdog, s/w) 0000–0003 0 (High) Breakpoint 0004–0007 1 Trace 0008–000B 1 Stack Overflow 000C–000F 1 Divide by 0 0010–0013 1 User RETI 0014–0017 1 TRAP 0–15 (software) 0040–007F 1

Philips Semiconductors Preliminary specification XA-S3 XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2C, 2 UARTs, 16 MB address range

2000 Dec 01 33

DESCRIPTION FLAG BIT VECTOR ADDRESS ENABLE BIT INTERRUPT PRIORITY ARBITRATION RANKING External Interrupt 0 IE0 0080–0083 EX0 IPA0.2–0 (PX0) 2 Timer 0 Interrupt TF0 0084–0087 ET0 IPA0.6–4 (PT0) 3 External Interrupt 1 IE1 0088–008B EX1 IPA1.2–0 (PX1) 4 Timer 1 Interrupt TF1 008C–008F ET1 IPA1.6–4 (PT1) 5 Timer 2 Interrupt TF2 (EXF2) 0090–0093 ET2 IPA2.2–0 (PT2) 6 PCA Interrupt CCF0–CCF4, CF 0094–0097 EPC IPA2.6–4 (PPC) 7 A/D Interrupt ADINT 0098–009B EAD IPA3.2–0 (PAD) 8 Serial Port 0 Rx RI_0 00A0–00A3 ERI0 IPA4.2–0 (PRI0) 9 Serial Port 0 Tx TI_0 00A4–00A7 ETI0 IPA4.6–4 (PTI0) 10 Serial Port 1 Rx RI_1 00A8–00AB ERI1 IPA5.2–0 (PRI1) 11 Serial Port 1 Tx TI_1 00AC–00AF ETI1 IPA5.6–4 (PTI1) 12 PCA channel 0 CCF0 00C0–00C3 EC0 IPB0.2–0 (PC0) 17 PCA channel 1 CCF1 00C4–00C7 EC1 IPB0.6–4 (PC1) 18 PCA channel 2 CCF2 00C8–00CB EC2 IPB1.2–0 (PC2) 19 PCA channel 3 CCF3 00CC–00CF EC3 IPB1.6–4 (PC3) 20 PCA channel 4 CCF4 00D0–00D3 EC4 IPB2.2–0 (PC4) 21 I2C Interrupt SI 00D4–00D7 EI2 IPB2.6–4 (PI2) 22 SOFTWARE INTERRUPTS DESCRIPTION FLAG BIT VECTOR ADDRESS ENABLE BIT INTERRUPT PRIORITY Software Interrupt 1 SWR1 0100–0103 SWE1 (fixed at 1) Software Interrupt 2 SWR2 0104–0107 SWE2 (fixed at 2) Software Interrupt 3 SWR3 0108–010B SWE3 (fixed at 3) Software Interrupt 4 SWR4 010C–010F SWE4 (fixed at 4) Software Interrupt 5 SWR5 0110–0113 SWE5 (fixed at 5) Software Interrupt 6 SWR6 0114–0117 SWE6 (fixed at 6) Software Interrupt 7 SWR7 0118–011B SWE7 (fixed at 7)

Philips Semiconductors Preliminary specification XA-S3 XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2C, 2 UARTs, 16 MB address range

2000 Dec 01 34

Operating temperature under bias –55 to +125 °C Storage temperature range –65 to +150 °C Voltage on EA/VPP pin to VSS 0 to +13.0 V Voltage on any other pin to VSS –0.5 to VDD +0.5 V V Maximum IOL per I/O pin 15 mA Power dissipation (based on package heat transfer, not device power consumption) 1.5 W DC ELECTRICAL CHARACTERISTICS VDD = 2.7 V to 5.5 V, unless otherwise specified. Tamb = 0 to +70°C for commercial, Tamb = –40°C to +85°C for industrial, unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS LIMITS UNITSYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IDD Power supply current, operating 5.0 V, 30 MHz 80 mA IID Power supply current, Idle mode 5.0 V, 30 MHz 35 mA IPD Power supply current, Power Down mode 5.0 V, 3.0 V 5 100 µA 5.0 V, 3.0 V, –40 to +85°C 150 µA VRAM RAM keep-alive voltage 1.5 V VIL Input low voltage –0.5 0.22 VDD V VIH Input high voltage, except XTAL1, RST VDD = 5.0 V 2.2 V VDD = 3.0 V 2.0 V VIH1 Input high voltage to XTAL1, RST For both 3.0 V and 5.0 V0.7 VDD V VOL Output low voltage, all ports, ALE, PSEN4, CLKOUT IOL = 3.2 mA, VDD = 5.0 V 0.5 V IOL = 1.0 mA, VDD = 3.0 V 0.4 V VOH1 Output high voltage, all ports, ALE, PSEN2, CLKOUT IOH = –100 µA, VDD = 4.5 V 2.4 V IOH = –30 µA, VDD = 2.7 V 2.0 V VOH2 Output high voltage, all ports ALE, PSEN3, CLKOUT IOH = –3.2 mA, VDD = 4.5 V 2.4 V IOH = –1.0 mA, VDD = 2.7 V 2.2 V C IO Input/Output pin capacitance1 15 pF IIL Logical 0 input current, all ports7 VIN = 0.45 V –50 µA ILI Input leakage current, all ports6 VIN = VIL or VIH ±10 µA ITL Logical 1 to 0 transition current, all ports5 At VDD = 5.5 V –650 µA At VDD = 2.7 V –250 µA NOTES: 1. Maximum 15pF for EA/VPP. 2. Ports in quasi-bidirectional mode with weak pullup (applies to ALE, PSEN only during RESET). 3. Ports in PUSH-PULL mode, both pullup and pulldown assumed to be the same strength. 4. In all output modes. 5. Port pins source a transition current when used in quasi-bidirectional mode and externally driven from 1 to 0. This current is highest when V IN is approximately 2 V. 6. Measured with port in high impedance mode. 7. Measured with port in quasi-bidirectional mode. 8. Under steady state (non-transient) conditions, I OL must be externally limited as follows: Maximum IOL per port pin: 15 mA Maximum IOL per 8-bit port: 26 mA Maximum total IOL for all outputs: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.

Philips Semiconductors Preliminary specification XA-S3 XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2C, 2 UARTs, 16 MB address range

2000 Dec 01 35

8-BIT MODE A/D CONVERTER DC ELECTRICAL CHARACTERISTICS Tamb = 0 to +70°C for commercial, Tamb = –40 to +85°C for industrial, unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS LIMITS UNITSYMBOL PARAMETER TEST CONDITIONS MIN MAX UNIT AV DD Analog supply voltage 2.7 3.3 V AIDD Analog supply current (operating) Port 5 = 0 to AVDD 2.5 mA AIID Analog supply current (Idle mode) 2.5 µA AIPD Analog supply current (Power-Down mode)Commercial temperature range 100 µA Industrial temperature range 150 µA AV IN Analog input voltage AV SS –0.2 AV DD +0.2 V R REF Resistance between VREF+ and VREF– 125 225 kΩ C IA Analog input capacitance 15 pF DL e Differential non-linearity1, 2, 3 ±1 LSB ILe Integral non-linearity1, 4 ±1 LSB OS e Offset error1, 5 ±2.5 LSB G e Gain error1, 6 ±1 % Ae Absolute voltage error1, 7 ±3 LSB M CTC Channel-to-channel matching ±1 LSB C t Crosstalk between inputs of port8 0 – 100 kHz –60 dB NOTES: 1. Conditions: AVREF– = 0 V; AVREF+ = 3.07 V. 2. The differential non-linearity (DLe) is the difference between the actual step width and the ideal step width. See Figure 25. 3. The ADC is monotonic, there are no missing codes. 4. The integral non-linearity (IL e) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 25. 5. The offset error (OSe) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and the straight line which fits the ideal transfer curve. See Figure 25. 6. The gain error (Ge) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error), and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. See Figure 25. 7. The absolute voltage error (Ae) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. 8. This should be considered when both analog and digital signals are input simultaneously to Port 5. Parameter is guaranteed by design.

Philips Semiconductors Preliminary specification XA-S3 XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2C, 2 UARTs, 16 MB address range

2000 Dec 01 36

10-BIT10 MODE A/D CONVERTER DC ELECTRICAL CHARACTERISTICS Tamb = 0 to +70°C for commercial, Tamb = –40 to +85°C for industrial, unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS LIMITS UNITSYMBOL PARAMETER TEST CONDITIONS MIN MAX UNIT AV DD Analog supply voltage 2.7 3.3 V AIDD Analog supply current (operating) Port 5 = 0 to AVDD 2.5 mA AIID Analog supply current (Idle mode) 2.5 µA AIPD Analog supply current (Power-Down mode)Commercial temperature range 100 µA Industrial temperature range 150 µA AV IN Analog input voltage AV SS –0.2 AV DD +0.2 V R REF Resistance between VREF+ and VREF– 125 225 kΩ C IA Analog input capacitance 15 pF DL e Differential non-linearity1, 2, 3 ±1 9 LSB ILe Integral non-linearity1, 4 ±2.5 9 LSB OS e Offset error1, 5 ±6 9 LSB G e Gain error1, 6 ±1 9 % Ae Absolute voltage error (with averaging)1, 7 ±8 9 LSB M CTC Channel-to-channel matching ±1 LSB C t Crosstalk between inputs of port8 0 – 100 kHz –60 dB NOTES: 1. Conditions: AVREF– = 0 V; AVREF+ = 3.07 V. 2. The differential non-linearity (DLe) is the difference between the actual step width and the ideal step width. See Figure 25. 3. The ADC is monotonic, there are no missing codes. 4. The integral non-linearity (IL e) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 25. 5. The offset error (OSe) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and the straight line which fits the ideal transfer curve. See Figure 25. 6. The gain error (Ge) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error), and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. See Figure 25. 7. The absolute voltage error (Ae) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. 8. This should be considered when both analog and digital signals are input simultaneously to Port 5. Parameter is guaranteed by design. 9. 10-bit mode only. 10. 10-bit mode is only operational up to f C = 20 MHz.

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1 LSB

1 LSB = AV REF+ – AV REF–

(1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential non-linearity (DLe). (4) Integral non-linearity (ILe). (5) Center of a step of the actual transfer curve. Figure 25. ADC Conversion Characteristic

Philips Semiconductors Preliminary specification XA-S3 XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2C, 2 UARTs, 16 MB address range

2000 Dec 01 38

AC ELECTRICAL CHARACTERISTICS (5 V) VDD = 4.5 V to 5.5 V; Tamb = 0 to +70°C for commercial, Tamb = –40°C to +85°C for industrial. SYMBOL FIGURE PARAMETER LIMITS UNITSYMBOL FIGURE PARAMETER MIN MAX UNIT External Clock fC 32 Oscillator frequency 0 30 MHz tC 32 Clock period and CPU timing cycle 1/fC ns tCHCX 32 Clock high-time (Note 7) tC * 0.5 ns tCLCX 32 Clock low time (Note 7) tC * 0.4 ns tCLCH 32 Clock rise time (Note 7) 5 ns tCHCL 32 Clock fall time (Note 7) 5 ns Address Cycle tLHLL 26, 28, 30 ALE pulse width (programmable) (V1 * tC ) – 6 ns tAVLL 26, 28, 30 Address valid to ALE de-asserted (set-up) (V1 * tC ) – 12 ns tLLAX 26, 28, 30 Address hold after ALE de-asserted (tC /2) – 10 ns Code Read Cycle tPLPH 26 PSEN pulse width (V2 * tC ) – 10 ns tLLPL 26 ALE de-asserted to PSEN asserted (tC /2) – 7 ns tAVIVA 26 Address valid to instruction valid, ALE cycle (access time) (V3 * tC ) – 36 ns tAVIVB 27 Address valid to instruction valid, non-ALE cycle (access time) (V4 * tC ) – 29 ns tPLIV 26 PSEN asserted to instruction valid (enable time) (V2 * tC ) – 29 ns tPHIX 26 Instruction hold after PSEN de-asserted 0 ns tPHIZ 26 Bus 3-State after PSEN de-asserted tC – 8 ns tIXUA 26 Hold time of unlatched part of address after instruction latched0 ns Data Read Cycle tRLRH 28 RD pulse width (V7 * tC ) – 10 ns tLLRL 28 ALE de-asserted to RD asserted (tC /2) – 7 ns tAVDVA 28 Address valid to data input valid, ALE cycle (access time) (V6 * tC ) – 36 ns tAVDVB 29 Address valid to data input valid, non-ALE cycle (access time) (V5 * tC ) – 29 ns tRLDV 28 RD low to valid data in (enable time) (V7 * tC ) – 29 ns tRHDX 28 Data hold time after RD de–asserted 0 ns tRHDZ 28 Bus 3-State after RD de-asserted (disable time) tC – 8 ns tDXUA 28 Hold time of unlatched part of address after data latched 0 ns Data Write Cycle tWLWH 30 WR pulse width (V8 * tC ) – 10 ns tLLWL 30 ALE falling edge to WR asserted (V12 * tC ) – 10 ns tQVWX 30 Data valid before WR asserted (data set-up time) (V13 * tC ) – 22 ns tWHQX 30 Data hold time after WR de-asserted (Note 6) (V11 * tC ) – 5 ns tAVWL 30 Address valid to WR asserted (address set-up time) (Note 5)(V9 * tC ) – 22 ns tUAWH 30 Hold time of unlatched part of address after WR is de-asserted (V11 * tC ) – 7 ns Wait Input tWTH 31 WAIT stable after bus strobe (RD, WR, or PSEN) asserted (V10 * tC ) – 30 ns tWTL 31 WAIT hold after bus strobe (RD, WR, or PSEN) asserted (V10 * tC ) – 5 ns NOTES ON PAGE 41.

Philips Semiconductors Preliminary specification XA-S3 XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2C, 2 UARTs, 16 MB address range

2000 Dec 01 39

AC ELECTRICAL CHARACTERISTICS (5 V RANGE) (continued) This set of parameters is referenced to the XA-S3 clock output. SYMBOL FIGURE PARAMETER LIMITS UNITSYMBOL FIGURE PARAMETER MIN MAX UNIT Address Cycle tCHLH 26 CLKOUT rising edge to ALE rising edge – 13 ns tCLLL 26 CLKOUT falling edge to ALE falling edge – 9 ns tCHAV 26 CLKOUT rising edge to address valid – 18 ns tCHAX 26 CLKOUT rising edge to address changing (hold time) 2 – ns Code Read Cycle tCHPL 26 CLKOUT rising edge to PSEN asserted – 14 ns tCHPH 26 CLKOUT rising edge to PSEN de-asserted – 12 ns tIVCH 26 Instruction valid to CLKOUT rising edge (setup time) 20 – ns tCHIX 26 CLKOUT rising edge to instruction changing (hold time) 0 – ns tCHIZ 26 CLKOUT rising edge to Bus 3-State (code read) – tC –8 ns Data Read Cycle tCHRL 28 CLKOUT rising edge to RD asserted – 12 ns tCHRH 28 CLKOUT rising edge to RD de-asserted – 10 ns tDVCH 28 Data valid to CLKOUT rising edge (setup time) 20 – ns tCHDX 28 CLKOUT rising edge to Data changing (hold time) 0 – ns tCHDZ 28 CLKOUT rising edge to Bus 3-State (data read) – tC –8 ns Data Write Cycle tCHWL 30 CLKOUT falling edge to WR asserted – 12 ns tCHWH 30 CLKOUT rising edge to WR de-asserted – 10 ns tQVCH 30 Data valid to CLKOUT rising edge (setup time) 4 – ns tCHQX 30 CLKOUT rising edge to Data changing (hold time) 0 – ns Wait Input tCHWTH 31 WAIT valid prior to CLKOUT rising edge8 21 4 ns NOTES ON PAGE 41.

Philips Semiconductors Preliminary specification XA-S3 XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2C, 2 UARTs, 16 MB address range

2000 Dec 01 40

AC ELECTRICAL CHARACTERISTICS (3 V) VDD = 2.7 V to 4.5 V; Tamb = 0 to +70°C for commercial, Tamb = –40°C to +85°C for industrial. SYMBOL FIGURE PARAMETER LIMITS UNITSYMBOL FIGURE PARAMETER MIN MAX UNIT Address Cycle tLHLL 26, 28, 30 ALE pulse width (programmable) (V1 * tC ) – 10 ns tAVLL 26, 28, 30 Address valid to ALE de-asserted (set-up) (V1 * tC ) – 18 ns tLLAX 26, 28, 30 Address hold after ALE de-asserted (tC /2) – 12 ns Code Read Cycle tPLPH 26 PSEN pulse width (V2 * tC ) – 12 ns tLLPL 26 ALE de-asserted to PSEN asserted (tC /2) – 9 ns tAVIVA 26 Address valid to instruction valid, ALE cycle (access time) (V3 * tC ) – 58 ns tAVIVB 27 Address valid to instruction valid, non-ALE cycle (access time) (V4 * tC ) – 52 ns tPLIV 26 PSEN asserted to instruction valid (enable time) (V2 * tC ) – 52 ns tPHIX 26 Instruction hold after PSEN de-asserted 0 ns tPHIZ 26 Bus 3-State after PSEN de-asserted tC – 8 ns tIXUA 26 Hold time of unlatched part of address after instruction latched0 ns Data Read Cycle tRLRH 28 RD pulse width (V7 * tC ) – 12 ns tLLRL 28 ALE de-asserted to RD asserted (tC /2) – 9 ns tAVDVA 28 Address valid to data input valid, ALE cycle (access time) (V6 * tC ) – 58 ns tAVDVB 29 Address valid to data input valid, non-ALE cycle (access time) (V5 * tC ) – 52 ns tRLDV 28 RD low to valid data in (enable time) (V7 * tC ) – 52 ns tRHDX 28 Data hold time after RD de–asserted 0 ns tRHDZ 28 Bus 3-State after RD de-asserted (disable time) tC – 8 ns tDXUA 28 Hold time of unlatched part of address after data latched 0 ns Data Write Cycle tWLWH 30 WR pulse width (V8 * tC ) – 12 ns tLLWL 30 ALE falling edge to WR asserted (V12 * tC ) – 10 ns tQVWX 30 Data valid before WR asserted (data set-up time) (V13 * tC ) – 28 ns tWHQX 30 Data hold time after WR de-asserted (Note 6) (V11 * tC ) – 8 ns tAVWL 30 Address valid to WR asserted (address set-up time) (Note 5)(V9 * tC ) – 28 ns tUAWH 30 Hold time of unlatched part of address after WR is de-asserted(V11 * tC ) – 10 ns Wait Input tWTH 31 WAIT stable after bus strobe (RD, WR, or PSEN) asserted (V10 * tC ) – 40 ns tWTL 31 WAIT hold after bus strobe (RD, WR, or PSEN) asserted (V10 * tC ) – 5 ns NOTES ON PAGE 41.

Philips Semiconductors Preliminary specification XA-S3 XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2C, 2 UARTs, 16 MB address range

2000 Dec 01 41

AC ELECTRICAL CHARACTERISTICS (3 V RANGE) (continued) This set of parameters is referenced to the XA-S3 clock output. SYMBOL FIGURE PARAMETER LIMITS UNITSYMBOL FIGURE PARAMETER MIN MAX UNIT Address Cycle tCHLH 26 CLKOUT rising edge to ALE rising edge – 15 ns tCLLL 26 CLKOUT falling edge to ALE falling edge – 11 ns tCHAV 26 CLKOUT rising edge to address valid – 29 ns tCHAX 26 CLKOUT rising edge to address changing (hold time) 2 – ns Code Read Cycle tCHPL 26 CLKOUT rising edge to PSEN asserted – 16 ns tCHPH 26 CLKOUT rising edge to PSEN de-asserted – 15 ns tIVCH 26 Instruction valid to CLKOUT rising edge (setup time) 30 – ns tCHIX 26 CLKOUT rising edge to instruction changing (hold time) 0 – ns tCHIZ 26 CLKOUT rising edge to Bus 3-State (code read) – tC –8 ns Data Read Cycle tCHRL 28 CLKOUT rising edge to RD asserted – 20 ns tCHRH 28 CLKOUT rising edge to RD de-asserted – 16 ns tDVCH 28 Data valid to CLKOUT rising edge (setup time) 28 – ns tCHDX 28 CLKOUT rising edge to Data changing (hold time) 0 – ns tCHDZ 28 CLKOUT rising edge to Bus 3-State (data read) – tC –8 ns Data Write Cycle tCHWL 30 CLKOUT falling edge to WR asserted – 19 ns tCHWH 30 CLKOUT rising edge to WR de-asserted – 16 ns tQVCH 30 Data valid to CLKOUT rising edge (setup time) 4 – ns tCHQX 30 CLKOUT rising edge to Data changing (hold time) 0 – ns Wait Input tCHWTH 31 WAIT valid prior to CLKOUT rising edge8 30 4 ns NOTES: 1. Load capacitance for all outputs = 50 pF. 2. Variables V1 through V13 reflect programmable bus timing, which is programmed via the Bus Timing registers (BTRH and BTRL). Refer to the XA User Guide for details of the bus timing settings. V1) This variable represents the programmed width of the ALE pulse as determined by the ALEW bit in the BTRL register. V1 = 0.5 if the ALEW bit = 0, and 1.5 if the ALEW bit = 1. V2) This variable represents the programmed width of the PSEN pulse as determined by the CR1 and CR0 bits or the CRA1, CRA0, and ALEW bits in the BTRL register. – For a bus cycle with no ALE, V2 = 1 if CR1/0 = 00, 2 if CR1/0 = 01, 3 if CR1/0 = 10, and 4 if CR1/0 = 11. Note that during burst mode code fetches, PSEN does not exhibit transitions at the boundaries of bus cycles. V2 still applies for the purpose of determining peripheral timing requirements. – For a bus cycle with an ALE, V2 = the total bus cycle duration (2 if CRA1/0 = 00, 3 if CRA1/0 = 01, 4 if CRA1/0 = 10, and 5 if CRA1/0 = 11) minus the number of clocks used by ALE (V1 + 0.5) = 2. Example: if CRA1/0 = 10 and ALEW = 1, the V2 = 4 – (1.5 + 0.5) = 2. V3) This variable represents the programmed length of an entire code read cycle with ALE. This time is determined by the CRA1 and CRA0 bits in the BTRL register. V3 = the total bus cycle duration (2 if CRA1/0 = 00, 3 if CRA1/0 = 01, 4 if CRA1/0 = 10, and 5 if CRA1/0 = 11). V4) This variable represents the programmed length of an entire code read cycle with no ALE. This time is determined by the CR1 and CR0 bits in the BTRL register. V4 = 1 if CR1/0 = 00, 2 if CR1/0 = 01, 3 if CR1/0 = 10, and 4 if CR1/0 = 11. V5) This variable represents the programmed length of an entire data read cycle with no ALE. This time is determined by the DR1 and DR0 bits in the BTRH register. V5 = 1 if DR1/0 = 00, 2 if DR1/0 = 01, 3 if DR1/0 = 10, and 4 if DR1/0 = 11. V6) This variable represents the programmed length of an entire data read cycle with ALE. The time is determined by the DRA1 and DRA0 bits in the BTRH register. V6 = the total bus cycle duration (2 if DRA1/0 = 00, 3 if DRA1/0 = 01, 4 if DRA1/0 = 10, and 5 if DRA1/0 = 11).

Philips Semiconductors Preliminary specification XA-S3 XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2C, 2 UARTs, 16 MB address range

2000 Dec 01 42

V7) This variable represents the programmed width of the RD pulse as determined by the DR1 and DR0 bits or the DRA1, DRA0 in the BTRH register, and the SLEW bit in the BTRL register. Note that during a 16-bit operation on an 8-bit external bus, RD remains low and does not exhibit a transition between the first and second byte bus cycles. V7 still applies for the purpose of determining peripheral timing requirements. The timing for the first byte is for a bus cycle with ALE, the timing for the second byte is for a bus cycle with no ALE. – For a bus cycle with no ALE, V7 = 1 if DR1/0 = 00, 2 if DR1/0 = 01, 3 if DR1/0 = 10, and 4 if DR1/0 = 11. – For a bus cycle with an ALE, V7 = the total bus cycle duration (2 if DRA1/0 = 00, 3 if DRA1/0 = 01, 4 if DRA1/0 = 10, and 5 if DRA1/0 = 11) minus the number of clocks used by ALE (V1 + 0.5). Example: if DRA1/0 = 00 and ALEW = 0, then V7 = 2 – (0.5 +0.5) = 1. V8) This variable represents the programmed width of the WRL and/or WRH pulse as determined by the WM1 bit in the BTRL register. V8 = 1 if WM1 = 0, and 2 if WM1 = 1. V9) This variable represents the programmed address setup time for a write as determined by the data write cycle duration (defined by DW1 and DW0 or the DWA1 and DWA0 bits in the BTRH register), the WM0 bit in the BTRL register, and the value of V8. – For a bus cycle with an ALE, V9 = the total bus write cycle duration (2 if DWA1/0 = 00, 3 if DWA1/0 = 01, 4 if DWA1/0 = 10, and 5 if DWA1/0 = 11) minus the number of clocks used by the WRL and/or WRH pulse (V8) minus the number of clocks used by data hold time (0 if WM0 = 0 and 1 if WM0 = 1). Example: If DWA1/0 = 10, WM0 = 1, and WM1 = 1, then V9 = 4 – 1 – 2 = 1. – For a bus cycle with no ALE, V9 = the total bus cycle duration (2 if DW1/0 = 00, 3 if DW1/0 = 01, 4 if DW1/0 = 10, and 5 if DW1/0 = 11) minus the number of clocks used by the WRL and/or WRH pulse (V8), minus the number of clocks used by data hold time (0 if WMo = 0 and 1 if WM0 = 1). Example: If DW1/0 = 11, WM0 = 1, and WM1 = 0, then V9 = 5 – 1 – 1 = 3. V10) This variable represents the length of a bus strobe for calculation of WAIT set-up and hold times. The strobe may be RD (for data read cycles), WRL and/or WRH (for data write cycles), or PSEN (for code read cycles), depending on the type of bus cycle being widened by WAIT. V10 = 2 for WAIT associated with a code read cycle using PSEN. V10 = V8 for a data write cycle using WRL and/or WRH. V10 = V7 – 1 for a data read cycle using RD. This means that a single clock data read cycle cannot be stretched using WAIT. If WAIT is used to vary the duration of data read cycles, the RD strobe width must be set to be at least two clocks in duration. Also see Note 4. V11) This variable represents the programmed write hold time as determined by the WM0 bit in the BTRL register. V11 0 if the WM0 bit = 0, and 1 if the WM0 bit = 1. V12) this variable represents the programmed period between the end of the ALE pulse and the beginning of the WRL and/or WRH pulse as determined by the data write cycle duration (defined by the DWA1 and DWA0 bits in the BTRH register), the WM0 bit in the BTRL register, and the values of V1 and V8. V12 = the total bus cycle duration (2 if DWA1/0 = 00, 3 if DWA1/0 = 01, 4 if DWA1/0 = 10, and 5 if DWA1/0 = 11) minus the number of clocks used by the WRL and/or WRH pulse (V8), minus the number of clocks used by data hold time (0 if WM0 = 0 and 1 if WM0 = 1), minus the width of the ALE pulse (V1). Example: If SWA1/0 = 11, WM0 = 1, WM1 = 0, and ALEW = 1, then V12 = 5 – 1 – 1 – 1.5 = 1.5. V13) This variable represents the programmed data setup time for a write as determined by the data write cycle duration (defined by DW1 and DW0 or the DWA1 and DWA0 bits in the BTRH register), the WM0 bit in the BTRL register, and the values of V1 and V8. – For a bus cycle with an ALE, V13 = the total bus cycle duration (2 if DWA1/0 = 00, 3 if DWA1/0 = 01, 4 if DWA1/0 = 10, and 5 if DWA1/0 = 11) minus the number of clocks used by the WRL and/or WRH pulse (V8), minus the number of clocks used by data hold time (0 if WM0 = 0 and 1 if WM0 = 1), minus the number of clocks used by ALE (V1 + 0.5). Example: If DWA1/0 = 11, WM0 = 1, WM1 = 1, and ALEW = 0, then V13 = 5 – 1 – 2 – 1 = 1. – For a bus cycle with no ALE, V13 = the total bus cycle duration (2 if DW1/0 = 00, 3 if DW1/0 = 01, 4 if DW1/0 = 10, and 5 if DW1/0 = 11) minus the number of clocks used by the WRL and/or WRH pulse (V8), minus the number of clocks used by data hold time (0 if WM0 = 0 and 1 if WM0 = 1). Example: If DW1/0 = 01, WM0 = 1, and WM1 = 0, then V13 = 3 – 1 – 1 = 1. 3. Not all combinations of bus timing configuration values result in valid bus cycles. Please refer to the XA User Guide section on the External Bus for details. 4. When code is being fetched for execution on the external bus, a burst mode fetch is used that dows not have PSEN edges in every fetch cycle. This would be A3–A0 for an 8-bit bus, and A3–A1 for a 16-bit bus. Also, a 16-bit read operation conducted on an 8-bit wide bus similarly does not include two separate RD strobes. So, a rising edge on the low order address line (A0) must be used to trigger a WAIT in the second half of such a cycle. 5. This parameter is provided for peripherals that have the data clocked in on the falling edge of the WR strobe. This is not usually the case and in most applications this parameter is not used. 6. Please note that the XA-S3 requires that extended data bus hold time (WM0 = 1) to be used with external bus write cycles. 7. Applies only to an external clock source, not when a crystal is connected to the XTAL1 and XTAL2 pins. 8. WAIT should not change between these times.

2000 Dec 01 43

Figure 26. External Program Memory Read Cycle (ALE Cycle) Figure 27. External Program Memory Read Cycle (Non-ALE Cycle)

2000 Dec 01 44

Figure 28. External Data Memory Read Cycle (ALE Cycle) Figure 29. External Data Memory Read Cycle (Non-ALE Cycle)

2000 Dec 01 45

*DATA OUT is either D0–D7 or D0–D15, depending on the bus width (8 or 16 bits). Figure 30. External Data Memory Write Cycle Figure 31. WAIT Signal Timing

2000 Dec 01 46

Figure 32. External Clock Drive AC inputs during testing are driven at VDD –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’. Timing measurements are made at the 50% point of transitions. Figure 33. AC Testing Input/Output and begins to float when a 100mV change from the loaded VOH /VOL level occurs. IOH /IOL ≥ ±20mA. Figure 34. Float Waveform Figure 35. IDD Test Condition, Active Mode Figure 36. IDD Test Condition, Idle Mode

2000 Dec 01 47

Figure 37. IDD vs. Frequency Valid only within frequency specification of the device under test. Figure 38. Clock Signal Waveform for IDD Tests in Active and Idle Modes Figure 39. IDD Test Condition, Power Down Mode

2000 Dec 01 48

different pins are used for many programming functions. Table 6. Program Security Bits 1 U U U No Program Security features enabled.

2 P U U MOVC instructions executed from external program memory are disabled from fetching code bytes

from internal memory and further programming of the EPROM is disabled. 3 P P U Same as 2, also verify is disabled. 4 P P P Same as 3, external execution is disabled. Internal data RAM is not accessible.

1. P – programmed. U – unprogrammed.
2. Any other combination of the security bits is not defined.

 Trademark phrase of Intel Corporation.

Philips Semiconductors Preliminary specification XA-S3 XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2C, 2 UARTs, 16 MB address range

2000 Dec 01 49

PLCC68: plastic leaded chip carrier; 68 leads; pedestal SOT188-3

Philips Semiconductors Preliminary specification XA-S3 XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2C, 2 UARTs, 16 MB address range

2000 Dec 01 50

LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm SOT315-1

Philips Semiconductors Preliminary specification XA-S3 XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2C, 2 UARTs, 16 MB address range

2000 Dec 01 51

Philips Semiconductors Preliminary specification XA-S3 XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2C, 2 UARTs, 16 MB address range

2000 Dec 01 52

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors

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P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381  Copyright Philips Electronics North America Corporation 2000 All rights reserved. Printed in U.S.A. Date of release: 12-00 Document order number: 9397 750 07816 /C0080 /C0115 /C0111/C0110/C0111 /C0115 Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Production Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Data sheet status [1] Please consult the most recently issued datasheet before initiating or completing a design.