PXAH30KFBE

XA-H3 PHILIPS | Alldatasheet

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/C0080 /C0115 /C0111/C0110/C0111 /C0115 XA-H3 CMOS 16-bit highly integrated microcontroller Preliminary specification IC28 Data Handbook

1999 Sep 24

Philips Semiconductors Preliminary specification XA-H3CMOS 16-bit highly integrated microcontroller

21999 Sep 24

DESCRIPTION

The powerful 16-bit XA CPU core and rich feature set make the XA-H3 and XA-H4 devices ideal for high-performance real-time applications such as industrial control and networking. By supporting of up to 32 MB of external memory, these devices provide a low-cost solution to embedded applications of any complexity. Features like DMA, memory controller and four advanced UARTs help solve I/O intensive tasks with a minimum of CPU load. The XA-H3 feature set is a subset of the XA-H4 (see Table 1). The XA-H3/H4 devices are members of the Philips XA (eXtended Architecture) family of high performance 16-bit microcontrollers. The XA-H3 and XA-H4 are designed to significantly minimize the need for external components.

FEATURES

• Large Memory Support (up to 6 MB external)
• De-multiplexed Address/Data Bus
• Six Programmable Chip Selects – Support for Unified Memory – allows easy user modification of all code – External ISP Flash support for easy code download
• Dynamic Bus Sizing – each of 6 Chip Selects can be programmed for 8-bit or 16-bit bus.
• Dynamic Bus Timing – each of 6 chip selects has individual programmable bus timing.
• 32 Programmable General Purpose I/O Pins
• Four UARTs with 230.4 kbps capability
• Eight DMA Channels

Table 1. XA-H3 and XA-H4 features comparison

6 MB 32 MB

4 High Priority SW

13 Hardware Event

7 Standard SW

1. Can be used as additional counters if not needed as BRGs.

Philips Semiconductors Preliminary specification XA-H3CMOS 16-bit highly integrated microcontroller

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ORDERING INFORMATION

ROMless Only Temperature range °C and Package Freq (MHz) Package Drawing Number H3 = PXAH30KFBE –40 to +85°C, 100-Pin Low Profile Quad Flat Package (LQFP)30 SOT407-1 NOTE K=30 MHz, F = (–40 to +85), BE = LQFP PIN CONFIGURATION XA-H3 Top View 100 Pin LQFP Part Number: PXAH30KFBE K = 30 MHz, F = –40 to +85°C, BE = LQFP pkg 100 1VSS VDD A10 A11 A12 A13 A14 A15 VSS VDD A16 A17 A18 A19 WE CS0 CS1 CS2 CS3 ClkOut VSS VDD D15 D14 D13 D12 D11 D10 VDD VSS VSS VDD CD1_Int2 Int0 P2.0_RxD3 P2.1_TxD3 P2.2_RTClk3 P2.3_ComClk_TRClk3 P2.4_CD3 P2.5_CTS3 P2.6_RTS3 P2.7_BRG3 VSS VDD P0.0_BRG0 P0.1_RTS0 P0.2_CTS0 P0.3_CD0 P0.4_TRClk0 P0.5_RTClk0 TxD0 RxD0 GPOut P0.6 P0.7 P1.7_BRG2 P1.6_RTS2 P1.5_CTS2 P1.4_CD2 P1.3_TRClk2 P1.2_RTClk2 P1.1_TxD2 P1.0_RxD2 P3.7_Int1_TRClk1 P3.6_TxD1 P3.5_RxD1 P3.4_CTS1 P3.3_Timer1_BRG1 VDD XTALOUT XTALIN VSS P3.2_Timer0_ResetOut P3.1_CS5_RTS1 P3.0_CS4_RTClk1 Reset_In BLE BHE WAIT_Size16 OE SU01234 MOLD MARK MOLD MARK

Philips Semiconductors Preliminary specification XA-H3CMOS 16-bit highly integrated microcontroller

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D15 – D0 A19 – A0 0.7 0.0 0.1 0.2 0.3 0.4 0.5 0.6 3.0 3.7 TxD0 RxD0 3.1 3.2 3.3 3.4 3.5 3.6 1.0 1.7 1.1 1.2 1.3 1.4 1.5 1.6 UART2 2.0 2.7 2.1 2.2 2.3 2.4 2.5 2.6 MISC. UART1 PORT3 PORT1 PORT0UART0 VDD VSS RxD3 TxD3 RTClk3 ComClk , TRClk3 CD3 CTS3 RTS3 BRG3 RxD2 TxD2 RTClk2 TRClk2 CD2 CTS2 RTS2 BRG2 BRG0 RTS0 CTS0 CD0 TRClk0 RTClk0 UART3 Int2 CS4 CS5 ResetOut, Timer0 Timer1 Int1 CD1 RTClk1 RTS1 BRG1 CTS1 RxD1 TRClk1 TxD1 Wait, Size16 WE OE BLE BHE ClkOut CS0 CS1 CS2 CS3 Int0 PORT2 GPOut

Philips Semiconductors Preliminary specification XA-H3CMOS 16-bit highly integrated microcontroller

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256 Bytes Data

6 Chip Selects

Philips Semiconductors Preliminary specification XA-H3CMOS 16-bit highly integrated microcontroller

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(von Neuman architecture) Harvard Architecture

6 MB *

*In either memory architecture, the XA-H3 can support a maximum of 6 MB because each of six Chip Selects is capable of 1 MB each. In Unified architecture, Code and Data can share the same physical Memory Chip and address space. Code Space + Data Space = 6 MB Maximum Total with 1 MB per Chip Select. Each CS (and thus, 1 MB space) can support either Code or Data in Harvard architecture. Dedicated Code Space Dedicated Data Space

Philips Semiconductors Preliminary specification XA-H3CMOS 16-bit highly integrated microcontroller

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Pin No. Type Name and Function See Note VSS 1, 19, 28, 44, 59, 76, 88 I Ground: 0 V reference. VDD 2, 20, 29, 43, 62, 77, 89 I Power Supply: This is the power supply voltage for normal, idle, and power down operation. ResetIn 55 I Reset: A low on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor to begin execution at the address contained in the reset vector. WAIT/ Size16 52 I Wait/Size16: During Reset, this input determines bus size for boot device (“1” = 16-bit boot device; “0” = 8-bit.) During normal operation this is the Wait input (“1” = Wait; “0” = Proceed.) XTALIn 60 I Crystal 1: Input to the inverting amplifier used in the oscillator circuit and input to the internal clock generator circuits. XTALOut 61 I Crystal 2: Output from the oscillator amplifier. CS0 49 O Chip Select 0: This output provides the active low chip select to the boot device (usually ROM or Flash.) From reset, it is enabled and mapped to an address range based at 000000h. It can be remapped by software to a higher base in the address map (see the “Memory Interface” chapter in the XA-H3 User Manual.) CS1 48 O Chip Select 1*: Chip Selects 1 through 5 come out of reset disabled. They function as normal chip selects on the H3. CS1 can be “swapped” with CS0 (see the SWAP operation in the “Memory Controller” chapter of the XA-H3 User Manual.) CS1 is usually mapped to be based at 000000h after the swap, but is capable of being based anywhere in the 16 MB address space. CS2 47 O Chip Select 2 *: Active low Chip Selects CS1 through CS5 come out of reset disabled. They can be programmed to function as normal chip selects. CS2 through CS5 are not used with the “SWAP” operation (only /CS0 and CS1 can be swapped; see “Memory Controller” chapter in the XA-H3 User Manual.) They are mappable to any region of the 16 MB address space. CS3 46 O Chip Select 3 *: See Chip Select 2 for description. See Pins 56, 57 for 2 additional Chip Selects WE 50 O Write Enable: Goes active low during all bus write cycles only. OE 51 O Output Enable: Goes active low during all bus read cycles only. BLE 54 O Byte Low Enable: Goes active low during all bus cycles that access data bus lines D7 – D0, read or write. BHE 53 O Byte High Enable: Goes active low during all bus cycles that access data bus lines D15 – D8, read or write. Never goes active on an 8-bit bus; always goes active on Reads or Fetches on a 16-bit bus, even if the processor does not need these bits. In other words, all Reads (byte or word) on a 16-bit bus, assert BHE ClkOut 45 O Clock Output: This pin outputs a buffered version of the internal CPU clock. The clock output may be used in conjunction with the external bus to synchronize WAIT state generators, etc. The clock output may be disabled by software. WARNING: The capacitive loading on this output must not exceed 40 pf. A19 – A0 24 – 21, 18 – 3 O Address[19:0]: These address lines output A19 – A0 during all external bus cycles. D15 – D0 42 – 30, 27 – 25 I/O Data[15:0]: Bi-directional data bus, D15 – D0; for those bus cycles that are programmed to occur on an “8-bit bus”, D15 – D8 are unused. P0.0 90 I/O P0.0_BRG0 *: Port 0 Bit 0, or UART0 BRG output, or UART0 TxClk output 1 P0.1 91 I/O P0.1_RTS0 : Port 0 Bit 1 , or UART0 RTS (Request To Send) output. 1 P0.2 92 I/O P0.2_CTS0 : Port 0 Bit 2, or UART0 CTS (Clear To Send) input. 1 P0.3 93 I/O P0.3_CD0 : Port 0 Bit 3, or UART0 Carrier Detect input. 1 P0.4 94 I/O P0.4_TRClk0: Port 0 Bit 4, or UART0 TR clock input. 1, 2 P0.5 95 I/O P0.5_RTClk0: Port 0 Bit 5, or UART0 RT clock input. 1, 2 P0.6 99 I/O P0.6: Port 0 Bit 6 1 P0.7 100 I/O P0.7: Port 0 Bit 7 1 TxD0 96 O TxD0: Transmit data for UART0.

Philips Semiconductors Preliminary specification XA-H3CMOS 16-bit highly integrated microcontroller

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NoteName and FunctionTypeLqfp Pin No. RxD0 97 I RxD0: Receive data for UART0 GPOut 98 O GPOut – General Purpose Output Bar: Similar to GPIO, but Push/Pull and inverted output only. WARNING: This output is inverted. The polarity of the pin is the opposite of the bit that drives it (GPOut[7]) P1.0 68 I/O P1.0_RxD2: Port 1 Bit 0, or UART2 RxD input P1.1 69 I/O P1.1_TxD2: Port 1 Bit 1, or UART2 TxD output P1.2 70 I/O P1.2_RTClk2: Port 1 Bit 2, or UART2 RT Clock input 2 P1.3 71 I/O P1.3_TRClk2: Port 1 Bit 3, or UART2 TR Clock input 2 P1.4 72 I/O P1.4_CD2 : Port 1 Bit 4, or UART2 Carrier Detect input P1.5 73 I/O P1.5_CTS2 : Port 1 Bit 5, or UART2 Clear To Send input P1.6 74 I/O P1.6_RTS2 : Port 1 Bit 6, or UART2 Request To Send output P1.7 75 I/O P1.7_BRG2 : Port 1 Bit 7, or BRG output, or TxClk output (see UART clk diagrams in the XA-H3 User Manual.) P2.0 80 I/O P2.0_RxD3: Port 2 Bit 0, or UART3 Rx Data input P2.1 81 I/O P2.1_TxD3: Port 2 Bit 1, or UART3 Tx Data output P2.2 82 I/O P2.2_RTClk3: Port 2 Bit 2, or UART3 RT Clock input 2 P2.3 83 I/O P2.3_ComClk _TRClk3: Port 2 Bit 3, or UART3 TR Clock input 2 P2.4 84 I/O P2.4_CD3 : Port 2 Bit 4, or UART3 Carrier Detect input P2.5 85 I/O P2.5_CTS3 : Port 2 Bit 5, or UART3 Clear To Send input P2.6 86 I/O P2.6_RTS3 : Port 2 Bit 6, or UART3 Request To Send output P2.7 87 I/O P2.7_BRG3 : Port 2 Bit 7, or BRG output, or TxClk output (see UART clock diagrams in the XA-H3 User Manual.) P3.0 56 I/O P3.0_CS4_RTClk1: Port 3 Bit 0, or CS4 output, or UART1 RT Clock input Active low chip selects CS1 through CS5 come out of reset disabled. CS2 through CS5 are not used with the “SWAP” operation (see “Memory Controller” chapter in the XA-H3 User Manual.) They are mappable to any region of the 16 MB address space. P3.1 57 I/O P3.1_CS5_RTS1 : Port 3 Bit 1, or CS5 output, or UART1 Request To Send output Active low chip selects CS1 through CS5 come out of reset disabled. CS2 through CS5 are not used with the “SWAP” operation (see “Memory Controller” chapter in the XA-H3 User Manual.) They are mappable to any region of the 16 MB address space. P3.2 58 I/O P3.2_Timer0_ResetOut: Port 3 Bit 2, or Timer0 input or output, or ResetOut output. ResetOut: If the ResetOut function is selected, this pin outputs a low whenever the XA-H3 processor is reset by an internal source (Watchdog Reset or the RESET instruction.) WARNING: Unlike the other 31 GPIO pins, during power up reset, this pin can output a strongly driven low pulse. The duration of this low pulse ranges from 0 ns to 258 system clocks, starting at the time that VCC is valid. The state of the ResetIn pin does not affect this pulse; in other words ResetIn is not passed to ResetOut. When used as GPIO, this pin can also be driven low by software without resetting the XA-H3. P3.3 63 I/O P3.3_Timer1_BRG1 : Port 3 Bit 3, or Timer1 input or output, or UART1 BRG output. P3.4 64 I/O P3.4_CTS1 : Port 3 Bit 4, or UART1 Clear To Send input P3.5 65 I/O P3.5_RxD1: Port 3 Bit 5, or UART1 Receive Data input P3.6 66 I/O P3.6_TxD1: Port 3 Bit 6, or UART1 Transmit Data output P3.7 67 I/O P3.7_Int1_TRClk1: Port 3 Bit 7, or External Interrupt 1 input, or UART1 TR Clock input 2 CD1 _Int2 78 I/O CD1 _Int2: UART1 Carrier Detect, or External Interrupt 2 Int0 79 I/O External Interrupt 0 NOTES: 1. See XA-H3 User Guide, “Pins Chapter,” for how to program selection of pin functions. 2. RTClk input is usually used for Rx Clock if an external clock is needed, but can be used for either Rx or Tx or both. TRClk is usually used for Tx Clock, but can be used for Rx or Tx or both.

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WARNINGs about BCR, BRTH, and BRTL in Table 2. (MMR Base Low and High) registers. Table 2. Special Function Registers (SFR) the only legal value. This is not the same as for some other XA derivatives.

Philips Semiconductors Preliminary specification XA-H3CMOS 16-bit highly integrated microcontroller

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Bit Functions and Addresses MSB LSB SFR AddressDescription P0CFGA Port 0 Configuration A 470h 5 P1CFGA Port 1 Configuration A 471h 5 P2CFGA Port 2 Configuration A 472h 5 P3CFGA Port 3 Configuration A 473h 5 P0CFGB Port 0 Configuration B 4F0h 5 P1CFGB Port 1 Configuration B 4F1h 5 P2CFGB Port 2 Configuration B 4F2h 5 P3CFGB Port 3 Configuration B 4F3h 5 227 226 225 224 223 222 221 220 PCON* Power Control Reg 404h – – – – – – PD IDL 00h 20F 20E 20D 20C 20B 20A 209 208 PSWH* Program Status Word High401h SM TM RS1 RS0 IM3 IM2 IM1 IM0 2 207 206 205 204 203 202 201 200 PSWL* Program Status Word Low400h C AC – – – V N Z 2 217 216 215 214 213 212 211 210 PSW51* 80C51 Compatible PSW 402h C AC F0 RS1 RS0 V F1 P 3 RSTSRC Reset Source Reg 463h ROEN – – – – R_WD R_CMD R_EXT 7 RTH0 Timer 0 Reload High 455h 00h RTH1 Timer 1 Reload High 457h 00h RTL0 Timer 0 Reload Low 454h 00h RTL1 Timer 1 Reload Low 456h 00h SCR System Configuration Reg440h – – – – PT1 PT0 CM PZ 00h 21F 21E 21D 21C 21B 21A 219 218 SSEL* Segment Selection Reg 403h ESWEN R6SEG R5SEG R4SEG R3SEG R2SEG R1SEG R0SEG 00h SWE Software Interrupt Enable47Ah – SWE7 SWE6 SWE5 SWE4 SWE3 SWE2 SWE1 00h 357 356 355 354 353 352 351 350 SWR* 42Ah – SWR7 SWR6 SWR5 SWR4 SWR3 SWR2 SWR1 00h 287 286 285 284 283 282 281 280 TCON* Timer 0/1 Control 410h TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00h TH0 Timer 0 High 451h 00h TH1 Timer 1 High 453h 00h TL0 Timer 0 Low 450h 00h TL1 Timer 1 Low 452h 00h TMOD Timer 0/1 Mode 45Ch GATE C/T M1 M0 GATE C/T M1 M0 00h

Philips Semiconductors Preliminary specification XA-H3CMOS 16-bit highly integrated microcontroller

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Bit Functions and Addresses MSB LSB SFR AddressDescription 28F 28E 28D 28C 28B 28A 289 288 TSTAT* Timer 0/1 Extended Status411h – – – – – T1OE – T0OE 00h 2FF 2FE 2FD 2FC 2FB 2FA 2F9 2F8 WDCON* Watchdog Control 41Fh PRE2 PRE1 PRE0 – – WDRUN WDTOF – 6 WDL Watchdog Timer Reload 45Fh 00h WFEED1 Watchdog Feed 1 45Dh x WFEED2 Watchdog Feed 2 45Eh x NOTES: * SFRs marked with an asterisk (*) are bit addressable. # SFRs marked with a pound sign (#) are additional SFR registers specific to the XA-H3 and XA-H4. 1. The XA-H3 implements an 8-bit SFR bus, as stated in Chapter 8 of the IC25 Data Handbook XA User Guide. All SFR accesses must be 8-bit operations. Attempts to write 16 bits to an SFR will actually write only the lower 8 bits. 16-bit SFR reads will return undefined data in the upper byte. 2. SFR is loaded from the reset vector. 3. F1, F0, and P reset to “0”. All other bits are loaded from the reset vector. 4. Unimplemented bits in SFRs are “X” (unknown) at all times. “1”s should not be written to these bits since they may be used for other purposes in future XA derivatives. The reset value shown for these bits is “0”. 5. Port configurations default to quasi-bidirectional when the XA begins execution after reset. Thus all PnCFGA registers will contain FFh and PnCFGB register will contain 00h. See warning in XA-H3 User Manual about P3.2_Timer0_ResetOut pin during first 258 clocks after power up. Basically, during this period, this pin may output a strongly-driven low pulse. If the pulse does occur, it will terminate in a transition to high at a time no later than the 259th system clock after valid VCC power up. 6. The WDCON reset value is E6 for a Watchdog reset; E4 for all other reset causes. 7. The RSTSRC register reflects the cause of the last XA reset. One bit will be set to “1”, the others will be “0”. RSTSRC[7] enables the ResetOut function; “1” = Enabled, “0” = Disabled. See XA-H3 User Manual for details; RSTSRC[7] differs in function from most other XA derivatives. 8. The XA guards writes to certain bits (typically interrupt flags) that may be written by a peripheral function. This prevents loss of an interrupt or other status if a bit was written directly by a peripheral action between the read and write of an instruction that performs a read-modify-write operation. XA-H3 SFR bits that are guarded in this manner are: TF1, TF0, IE1, and IE0 (in TCON), and WDTOF (in WDCON).

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Table 3. Memory Mapped Registers (MMR)

Philips Semiconductors Preliminary specification XA-H3CMOS 16-bit highly integrated microcontroller

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UART1 Write Register 14 R/W 8 85Ch Miscellaneous Control bits xx UART1 Write Register 15 R/W 8 85Eh External / Status interrupt control f8h Reserved – do not write 8 868h Reserved – do not write 00h Reserved – do not write 8 86Ah Reserved – do not write 00h UART1 Read Register 0 RO 8 860h Tx/Rx buffer and external status UART1 Read Register 1 RO 8 862h Receive condition status Reserved – do not write 864h UART1 Read Register 3 RO 8 866 Interrupt Pending Bits Reserved – do not write 8 86Ch Reserved – do not write Reserved – do not write 8 86Eh Reserved – do not write UART1 Read Register 8 RO 8 870h Receive Buffer Reserved – do not write 872h UART1 Read Register 10 RO 8 874h Clock status Reserved – do not write 876-87Eh UART2 Registers UART2 Write Register 0 R/W 8 880h Command register 00h UART2 Write Register 1 R/W 8 882h Tx/Rx Interrupt & data transfer mode xx UART2 Write Register 2 R/W 8 884h Extended Features Control xx UART2 Write Register 3 R/W 8 886h Receive Parameter and Control 00h UART2 Write Register 4 R/W 8 888h Tx/Rx miscellaneous parameters & mode 00h UART2 Write Register 5 R/W 8 88Ah Tx. parameter and control 00h Reserved – do not write 8 88Ch Reserved – do not write 00h Reserved – do not write 8 88Eh Reserved – do not write xx UART2 Write Register 8 R/W 8 890h Transmit Data Buffer xx UART2 Write Register 9 R/W 8 892h Master Interrupt control xx UART2 Write Register 10 R/W 8 894h Miscellaneous Tx/Rx control register 00h UART2 Write Register 11 R/W 8 896h Clock Mode Control xx UART2 Write Register 12 R/W 8 898h Lower Byte of Baud rate time constant 00h UART2 Write Register 13 R/W 8 89Ah Upper Byte of Baud rate time constant 00h UART2 Write Register 14 R/W 8 89Ch Miscellaneous Control bits xx UART2 Write Register 15 R/W 8 89Eh External / Status interrupt control f8h Reserved – do not write 8 8A8h Reserved – do not write 00h Reserved – do not write 8 8AAh Reserved – do not write 00h UART2 Read Register 0 RO 8 8A0h Tx/Rx buffer and external status UART2 Read Register 1 RO 8 8A2h Receive condition status Reserved – do not write 8A4h UART2 Read Register 3 RO 8 8A6h Interrupt Pending Bits Reserved – do not write 8 8ACh Reserved – do not write Reserved – do not write 8 8AEh Reserved – do not write UART2 Read Register 8 RO 8 8B0h Receive Buffer Reserved – do not write 8B2h UART2 Read Register 10 RO 8 8B4h Clock status Reserved – do not write 8B6-8BEh

Philips Semiconductors Preliminary specification XA-H3CMOS 16-bit highly integrated microcontroller

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UART3 Write Register 0 R/W 8 8C0h Command register 00h UART3 Write Register 1 R/W 8 8C2h Tx/Rx Interrupt & data transfer mode xx UART3 Write Register 2 R/W 8 8C4h Extended Features Control xx UART3 Write Register 3 R/W 8 8C6h Receive Parameter and Control 00h UART3 Write Register 4 R/W 8 8C8h Tx/Rx miscellaneous parameters & mode 00h UART3 Write Register 5 R/W 8 8CAh Tx. parameter and control 00h Reserved – do not write 8 8CCh Reserved – do not write 00h Reserved – do not write 8 8CEh Reserved – do not write xx UART3 Write Register 8 R/W 8 8D0h Transmit Data Buffer xx UART3 Write Register 9 R/W 8 8D2h Master Interrupt control xx UART3 Write Register 10 R/W 8 8D4h Miscellaneous Tx/Rx control register 00h UART3 Write Register 11 R/W 8 8D6h Clock Mode Control xx UART3 Write Register 12 R/W 8 8D8h Lower Byte of Baud rate time constant 00h UART3 Write Register 13 R/W 8 8DAh Upper Byte of Baud rate time constant 00h UART3 Write Register 14 R/W 8 8DCh Miscellaneous Control bits xx UART3 Write Register 15 R/W 8 8DEh External / Status interrupt control f8h Reserved – do not write 8 8E8h Reserved – do not write 00h Reserved – do not write 8 8EAh Reserved – do not write 00h UART3 Read Register 0 RO 8 8E0h Tx/Rx buffer and external status UART3 Read Register 1 RO 8 8E2h Receive condition status Reserved – do not write 8E4h UART3 Read Register 3 RO 8 8E6h Interrupt Pending Bits Reserved – do not write 8 8ECh Reserved – do not write Reserved – do not write 8 8EEh Reserved – do not write UART3 Read Register 8 RO 8 8F0h Receive Buffer Reserved – do not write 8F2h – UART3 Read Register 10 RO 8 8F4h Clock status Reserved – do not write 8F6-8FEh Rx DMA Registers DMA Control Register Ch.0 Rx R/W 8 100h Control Register 00h FIFO Control & Status Reg Ch.0 Rx R/W 8 101h Control & Status Register 00h Segment Register Ch.0 Rx R/W 8 102h Points to 64 k data segment 00h Buffer Base Register Ch.0 Rx R/W 8 104h Wrap Reload Value for A15 – A8, A7 – A0 reloaded to zero by hardware 00h Buffer Bound Register Ch.0 Rx R/W 16 106h Upper Bound (plus 1) on A15 – A0 0000h Address Pointer Reg Ch.0 Rx R/W 16 108h Current Address pointer A15 – A0 0000h Byte Count Register Ch.0 Rx R/W 16 10Ah Corresponds to A15 – A0 Byte Count, generates interrupt if enabled and byte count exceeded. 0000h Data FIFO Register Ch.0 Lo Rx R/W 16 10Ch 10Ch = Byte 0 = older, 10Dh = Byte 1 = younger 00h 00h Data FIFO Register Ch.0 Hi Rx R/W 16 10Eh 10Eh = Byte 2 = older, 10Fh = Byte 3 = younger 00h 00h DMA Control Register Ch.1 Rx R/W 8 110h Control Register 00h FIFO Control & Status Register Ch.1 Rx R/W 8 111h Control & Status Register 00h Segment Register Ch. 1 Rx R/W 8 112h Points to 64 k data segment 00h

Philips Semiconductors Preliminary specification XA-H3CMOS 16-bit highly integrated microcontroller

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Buffer Base Register Ch. 1 Rx R/W 8 114h Wrap Reload Value for A15 – A8, A7 – A0 reloaded to zero by hardware 00h Buffer Bound Register Ch.1 Rx R/W 16 116h Upper Bound (plus 1) on A15 – A0 0000h Address Pointer Reg Ch.1 Rx R/W 16 118h Current Address pointer A15 – A0 0000h Byte Count Register Ch.1 Rx R/W 16 11Ah Corresponds to A15 – A0 Byte Count, generates interrupt if enabled and byte count exceeded. 0000h Data FIFO Register Ch.1 Lo Rx R/W 16 11Ch 11Ch = Byte 0 = older, 11Dh = Byte 1 = younger 00h 00h Data FIFO Register Ch.1 Hi Rx R/W 16 11Eh 11Eh = Byte 2 = older, 11Fh = Byte 3 = younger 00h 00h DMA Control Register Ch.2 Rx R/W 8 120h Control Register 00h FIFO Control & Status Register Ch.2 Rx R/W 8 121h Control & Status Register 00h Segment Register Ch. 2 Rx R/W 8 122h Points to 64 k data segment 00h Buffer Base Register Ch. 2 Rx R/W 8 124h Wrap Reload Value for A15 – A8, A7 – A0 reloaded to zero by hardware 00h Buffer Bound Register Ch.2 Rx R/W 16 126h Upper Bound (plus 1) on A15 – A0 0000h Address Pointer Reg Ch.2 Rx R/W 16 128h Current Address pointer A15 – A0 0000h Byte Count Register Ch.2 Rx R/W 16 12Ah Corresponds to A15 – A0 Byte Count, generates interrupt if enabled and byte count exceeded. 0000h Data FIFO Register Ch.2 Lo Rx R/W 16 12Ch 12Ch = Byte 0 = older, 12Dh = Byte 1 = younger 00h 00h Data FIFO Register Ch.2 Hi Rx R/W 16 12Eh 12Eh = Byte 2 = older, 12Fh = Byte 3 = younger 00h 00h DMA Control Register Ch.3 Rx R/W 8 130h Control Register 00h FIFO Control & Status Register Ch.3 Rx R/W 8 131h Control & Status Register 00h Segment Register Ch. 3 Rx R/W 8 132h Points to 64 k data segment 00h Buffer Base Register Ch. 3 Rx R/W 8 134h Wrap Reload Value for A15 – A8, A7 – A0 reloaded to zero by hardware 00h Buffer Bound Register Ch.3 Rx R/W 16 136h Upper Bound (plus 1) on A15 – A0 0000h Address Pointer Reg Ch.3 Rx R/W 16 138h Current Address pointer A15 – A0 0000h Byte Count Register Ch.3 Rx R/W 16 13Ah Corresponds to A15 – A0 Byte Count, generates interrupt if enabled and byte count exceeded. 0000h Data FIFO Register Ch.3 Lo Rx R/W 16 13Ch 13Ch = Byte 0 = older, 13Dh = Byte 1 = younger 00h 00h Data FIFO Register Ch.3 Hi Rx R/W 16 13Eh 13Eh = Byte 2 = older, 13Fh = Byte 3 = younger 00h 00h Tx DMA Registers DMA Control Register Ch.0 Tx R/W 8 140h Control Register 00h FIFO Control & Status Register Ch.0 Tx R/W 8 141h Control & Status Register 00h Segment Register Ch. 0 Tx R/W 8 142h Points to 64 k data segment 00h Buffer Base Register Ch. 0 Tx R/W 8 144h Wrap Reload Value for A15 – A8, A7 – A0 reloaded to zero by hardware 00h Buffer Bound Register Ch.0 Tx R/W 16 146h Upper Bound (plus 1) on A15 – A0 0000h Address Pointer Reg Ch.0 Tx R/W 16 148h Current Address pointer A15 – A0 0000h Byte Count Register Ch.0 Tx R/W 16 14Ah Corresponds to A15 – A0 Byte Count, generates interrupt if enabled and byte count exceeded. 0000h Data FIFO Register Ch.0 Tx R/W 16 14Ch 14C = Byte0 = older 14D = Byte 1 = younger 0000h

Philips Semiconductors Preliminary specification XA-H3CMOS 16-bit highly integrated microcontroller

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Data FIFO Register Ch.0 Tx R/W 16 14Eh 14E = Byte2 = older 14F = Byte3 = younger 0000h DMA Control Register Ch.1 Tx R/W 8 150h Control Register 00h FIFO Control & Status Register Ch.1 Tx R/W 8 151h Control & Status Register 00h Segment Register Ch.1 Tx R/W 8 152h Points to 64 k data segment 00h Buffer Base Register Ch.1 Tx R/W 8 154h Wrap Reload Value for A15 – A8, A7 – A0 reloaded to zero by hardware 00h Buffer Bound Register Ch.1 Tx R/W 16 156h Upper Bound (plus 1) on A15 – A0 0000h Address Pointer Reg Ch.1 Tx R/W 16 158h Current Address pointer A15 – A0 0000h Byte Count Register Ch.1 Tx R/W 16 15Ah Corresponds to A15 – A0 Byte Count, generates interrupt if enabled and byte count exceeded. 0000h Data FIFO Register Ch.1 Lo Tx R/W 16 15Ch Byte0 & 1 0000h Data FIFO Register Ch.1 Hi Tx R/W 16 15Eh Byte2 & 3 0000h DMA Control Register Ch.2 Tx R/W 8 160h Control Register 00h FIFO Control & Status Register Ch.2 Tx R/W 8 161h Control & Status Register 00h Segment Register Ch.2 Tx R/W 8 162h Points to 64 k data segment 00h Buffer Base Register Ch.2 Tx R/W 8 164h Wrap Reload Value for A15 – A8, A7 – A0 reloaded to zero by hardware 00h Buffer Bound Register Ch.2 Tx R/W 16 166h Upper Bound (plus 1) on A15 – A0 0000h Address Pointer Reg Ch.2 Tx R/W 16 168h Current Address pointer A15 – A0 0000h Byte Count Register Ch.2 Tx R/W 16 16Ah Corresponds to A15 – A0 Byte Count, generates interrupt if enabled and byte count exceeded. 0000h Data FIFO Register Ch.2 Lo Tx R/W 16 16Ch Byte0 & 1 0000h Data FIFO Register Ch.2 Hi Tx R/W 16 16Eh Byte2 & 3 0000h DMA Control Register Ch.3 Tx R/W 8 170h Control Register 00h FIFO Control & Status Register Ch.3 Tx R/W 8 171h Control & Status Register 00h Segment Register Ch. 3 Tx R/W 8 172h Points to 64 k data segment 00h Buffer Base Register Ch. 3 Tx R/W 8 174h Wrap Reload Value for A15 – A8, A7 – A0 reloaded to zero by hardware 00h Buffer Bound Register Ch.3 Tx R/W 16 176h Upper Bound (plus 1) on A15 – A0 0000h Address Pointer Reg Ch.3 Tx R/W 16 178h Current Address pointer A15 – A0 0000h Byte Count Register Ch.3 Tx R/W 16 17Ah Corresponds to A15 – A0 Byte Count, generates interrupt if enabled and byte count exceeded. 0000h Data FIFO Register Ch.3Lo Tx R/W 16 17Ch Byte0 & 1 0000h Data FIFO Register Ch.3 Hi Tx R/W 16 17Eh Byte2 & 3 0000h R/W 180-1FEh RESERVED for future DMA – Miscellaneous DMA Registers Rx Character Time Out Register Ch.0 R/W 8 200h 0 value disables counter interrupt. 00h Rx Character Time Out Register Ch.1 R/W 8 202h Same as above, for Rx1 00h Rx Character Time Out Register Ch.2 R/W 8 204h Same as above, for Rx2 00h Rx Character Time Out Register Ch.3 R/W 8 206h Same as above, for Rx3 00h Global DMA Interrupt Register R/W 16 210h DMA Interrupt Flags 0000h GPOut R/W 8 260h GPOut[7] drives pin 98 (GPOut) through an inverter. GPOut[6-0] are unused, and must be written with zeroes. 8xh

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The XA-H3 functions are described in the following sections. The CPU is a 30 MHz implementation of the standard XA CPU core. connects the CPU to Memory Controller. initialized to 07h, which is the only value that will work. Figure 1. XA CPU Core BIU (Bus Interface Unit)

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to provide other functions on the XA-H3. pin, see “ResetOut” in the XA-H3 User Manual. P3.2_Timer0_ResetOut output can be configured as ResetOut. a full discussion of the reset functions. XA-H3 User Manual for details on reset. other devices in the system that the XA-H3 has been internally reset. activated, the duration of the ResetOut pulse is 256 system clocks. independently of whether ResetIn is active or not. RSTSRC[7] differs in function from most other XA derivatives. RSTSRC.6 – Reserved for future use. Should not be set to 1 by user programs. RSTSRC.5 – Reserved for future use. Should not be set to 1 by user programs. RSTSRC.4 – Reserved for future use. Should not be set to 1 by user programs. RSTSRC.3 – Reserved for future use. Should not be set to 1 by user programs. Figure 2. RSTSRC Reset Source Register designed to service SRAMs, Flash, EEPROM, peripheral chips, etc. accommodate slow or fast devices, with various bus protocols.

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style and 68000 bus style SRAMs and peripherals. Figure 3. Memory Bus Interface Signal Pins For the following discussion, see Figure 3. strobe sequence, and bus width. as two consecutive 8-bit reads even though the CPU instruction specified a byte read. expensive) solution is to operate these 8-bit devices on a 16-bit bus, and access them in software on all odd byte (or all even byte) boundaries. (tri-state disabled) by software via the MICFG MMR.

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Byte Reads, both BLE and BHE will go active. Figure 4. Typical System Bus Configuration

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Table 4. Memory interface control registers using this SFR to relocate the MMRs. Contains the CLKOUT Enable bit. Contains the bits for locking and unlocking the BiCFG Registers. Contains the size, type, bus width, and enable bits for Memory Bank i. Contains the base address bits for Memory Bank i. Contains the timing control bits for Memory Bank i. traditional linear data buffers. Table 5. Tx DMA modes summary XA-H3 User Manual for details. number of bytes, generates maskable interrupt, and stops. rolls over, a new maskable interrupt is generated. and use, see the XA-H3 User Manual.

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Table 6. Rx DMA modes summary generated once every n received bytes. from the DMA address pointer. from the DMA address pointer. Figure 5. Rx and Tx DMA Registers space. These registers are summarized below.

• Global DMA Interrupt Register (not shown in figure): All DMA interrupt flags are in this register .
• DMA Control Register: Contains the master mode select and interrupt enable bits for the channel.

Philips Semiconductors Preliminary specification XA-H3CMOS 16-bit highly integrated microcontroller

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• Segment Register: Holds A23–A16 (the current segment) of the 24-bit data buffer address.
• Buffer Base Register: Holds a pointer (A15–A8) to the lowest byte in the memory buffer.
• Buffer Bound Register: Points to the first out-of-bounds address above a circular buffer.
• Address Pointer Register: Points to a single byte or word in the data buffer in memory. The 24-bit DMA address is formed by concatenating the contents of the Segment Register [A23–A16] with the contents of the Address Pointer Register [A15–A0].
• Byte Count Register: Holds the initial number of bytes to be transferred. In Tx Chaining mode, this register is not used because the byte count is brought into the byte counter from buffer headers in memory.
• FIFO Control & Status Register: Holds the queuing order and full/empty status for the Data FIFO Registers.
• Data FIFO Registers: A four-byte data FIFO buffer internal to the DMA channel.
• Rx Char Time Out Register (RxCTOR, Rx DMA channels only): Holds the initial value for an 8-bit character timeout countdown timer which can generate an interrupt. Four UARTS
• Asynchronous transfers up to 230.4 kbps
• 5, 6, 7, or 8 data bits per character
• 1, 1.5, or 2 Stop bits per character
• Even or Odd parity generate and check
• Parity, Rx Overrun, and Framing Error detection
• Break detection
• Programmable Baud Rate Generator
• Auto Echo and Loopback Modes I/O Port Output Configuration Port input/output configurations are the same as standard XA ports: open drain, quasi-bidirectional, push-pull, and off (off means tri-state Hi-Z, and allows the pin to be used as an input. WARNING: At power on time, from the time that power coming up is valid, the P3.2_Timer0_ResetOut pin may be driven low for any period from zero nanoseconds up to 258 system clocks. This is true independently of whether ResetIn is active or not. Power Reduction Modes The XA-H3 supports Idle and Power Down modes of power reduction. The idle mode leaves most peripherals running in order to allow them to activate the processor when an interrupt is generated. The power down mode stops the oscillator in order to absolutely minimize power. The processor can be made to exit power down mode via a reset or one of the external interrupt inputs (INT0 or INT1). This will occur if the interrupt is enabled and its priority is higher than that defined by IM3 through IM0. In power down mode, the power supply voltage may be reduced to the RAM keep-alive voltage VRAM. This retains the RAM, register, and SFR contents at the point where power down mode was entered. WARNING: V DD must be raised to within the operating range before power down mode is exited. Interrupts In the XA architecture, all exceptions, including Reset, are handled in the same general exception structure. The highest priority exception is of course Reset, and it is non-maskable. All exceptions are vectored through the Exception Vector Table in low memory. Coming out of Reset, these vectors must be stored in non-volatile memory based at location 000000. Later in the boot sequence, SRAM or other memory can be mapped into this address space if desired. There is a feature in the XA-H3 Memory Controller called “Bank Swap” that supports replacing the ROM vector table and other low memory with RAM. See the XA-H3 User Manual for details. The XA-H3 has a standard XA CPU Interrupt Controller, implemented with 15 Maskable Event Interrupts. Event Interrupts are defined as maskable interrupts usually generated by hardware events. However, in the XA-H3, 4 of the 15 Event Interrupts are generated by software writing directly to the interrupt flag bit. These 4 interrupts are referred to as High Priority Software Interrupts. See the IC25 XA Data Handbook for a full explanation of the exception structure, including event interrupts, of the XA CPU. Because the High Priority Software Interrupts are specific to the XA-H3, they are explained in the XA-H3 User Manual.

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Figure 6. XA-H3 Interrupt Structure Overview

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Table 7. UART0 Interrupts (Interrupt structure is the same except for bit locations for all 4 UARTs)

Philips Semiconductors Preliminary specification XA-H3CMOS 16-bit highly integrated microcontroller

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Interrupt Source Flag Bit Interrupt Vector Address Enable Bit (SFR) Priority Register Bit Field (SFR) Arb. Rank High Priority Software Interrupt 3 HSWR3 MMR 2D0[15] 00BF–00BC EHSWR3 427[7] 33F PHSWR3 4A7[6:4] High Priority Software Interrupt 2 HSWR2 MMR 2D0[14] 00BB–00B8 EHSWR2 427[6] 33E PHSWR2 4A7[2:0] High Priority Software Interrupt 1 HSWR1 MMR 2D0[13] 00B7–00B4 EHSWR1 427[5] 33D PHSWR1 4A6[6:4] High Priority Software Interrupt 0 HSWR0 MMR 2D0[12] 00B3–00B0 EHSWR0 427[4] 33C PHSWR0 4A6[2:0] UART “UART2/3” Interrupt multiple OR from UART2 & UART3 00A7–00A4 ESC23 427[1] 339 PSC23 4A4[6:4] UART “UART0/1” Interrupt multiple OR from UART0 & UART1 00A3–00A0 ESC01 427[0] 338 PSC01 4A4[2:0] DMA “DMAH” Interrupt multiple OR from DMA 009B–0098 EDMAH 426[6] 336 PDMAH 4A3[2:0] DMA “DMAL” Interrupt multiple OR from DMA 0097–0094 EDMAL 426[5] 335 PDMAL 4A2[6:4] External Interrupt 2 (INT2 IE2 MMR 2D2[0] 0093–0090 EX2 426[4] 334 PX2 4A2[2:0] Timer 1 TF1 SFR 410[7] 287 008F–008C ET1 426[3] 333 PT1 4A1[6:4] External Interrupt 1 (INT1 IE1 SFR 410[3] 283 008B–0088 EX1 426[2] 332 PX1 4A1[2:0] Timer 0 TF0 SFR 410[5] 285 0087–0084 ET0 426[1] 331 PT0 4A0[6:4] External Interrupt 0 (INT0 IE0 SFR 410[1] 0083–0080 EX0 426[0] 330 PX0 4A0[2:0] 2 SOFTWARE INTERRUPTS Description Flag Bit Vector Address Enable Bit Interrupt Priority Software Interrupt 1 SWR1 0100–0103 SWE1 (fixed at 1) Software Interrupt 2 SWR2 0104–0107 SWE2 (fixed at 2) Software Interrupt 3 SWR3 0108–010B SWE3 (fixed at 3) Software Interrupt 4 SWR4 010C–010F SWE4 (fixed at 4) Software Interrupt 5 SWR5 0110–0113 SWE5 (fixed at 5) Software Interrupt 6 SWR6 0114–0117 SWE6 (fixed at 6) Software Interrupt 7 SWR7 0118–011B SWE7 (fixed at 7)

Philips Semiconductors Preliminary specification XA-H3CMOS 16-bit highly integrated microcontroller

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Operating temperature under bias –55 to +125 °C Storage temperature range –65 to +150 °C Voltage on any other pin to VSS –0.5 to VDD +0.5 V v Maximum IOL per I/O pin 15 mA Power dissipation (based on package heat transfer, not device power consumption) 1.5 W PRELIMINARY DC ELECTRICAL CHARACTERISTICS VDD = 5.0 V +/– 10% or 3.3 V +/– 10% unless otherwise specified; Tamb = –40°C to +85°C for industrial, unless otherwise specified. Symbol Parameter Test Conditions Limits UnitSymbol Parameter Test Conditions Min Typ Max Unit IDD Power supply current, operating 5.0 V, 30 MHz 64 80 mA

3.3 V, 30 MHz 55 70 mA

IID Power supply current, Idle mode 5.0 V, 30 MHz 50 70 mA

3.3 V, 30 MHz 44 60 mA

IPDI Power supply current, Power Down mode1 5.0 V, 3.0 V 500 µA VRAM RAM keep-alive voltage 1.5 V VIL Input low voltage –0.5 0.22 VDD V VIH Input high voltage, except Xtal1, RST 2.2 V VIH1 Input high voltage to Xtal1, RST For both 3.0 & 5.0 V 0.7 VDD V VOL Output low voltage all ports8 IOL = 3.2 mA, VDD = 4.5 V 0.5 V IOL = 1.0 mA, VDD = 3.0 V 0.4 V VOH1 Output high voltage, all ports IOH = –100 µA, VDD = 4.5 V 2.4 V IOH = –30 µA, VDD = 3.0 V 2.0 V VOH2 Output high voltage, all ports IOH = 3.2 mA, VDD = 4.5 V 2.4 V IOH = 1.0 mA, VDD = 3.0 V 2.2 V C IO Input/Output pin capacitance 15 pF IIL Logical 0 input current, all ports7 VIN = 0.45 V –50 µA ILI Input leakage current, all ports6 VIN = VIL or VIH ±10 µA ITL Logical 1 to 0 transition current, all ports5 At VDD = 5.5 V –650 µA At VDD = 3.6 V –250 µA NOTE: 1. VDD must be raised to within the operating range before power down mode is exited. 2. Ports in quasi-bidirectional mode with weak pullup. 3. Ports in PUSH-PULL mode, both pullup and pulldown assumed to be the same strength. 4. In all output modes. 5. Port pins source a transition current when used in quasi-bidirectional mode and externally driven from 1 to 0. This current is highest when V IN is approximately 2 V. 6. Measured with port in high impedance mode. 7. Measured with port in quasi-bidirectional mode. 8. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum I OL per port pin: 15 mA (NOTE: This is +85 °C specification for VDD = 5 V) Maximum IOL per 8-bit port: 26 mA Maximum total IOL for all outputs: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.

Philips Semiconductors Preliminary specification XA-H3CMOS 16-bit highly integrated microcontroller

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PRELIMINARY AC ELECTRICAL CHARACTERISTICS (5.0 V +/–10%) Symbol Fig re Parameter Limits UnitSymbol Figure Parameter Min Max Unit All Cycles FC System Clock Frequency 0 30 MHz tC 13 System Clock Period = 1/FC 33.33 – ns tCHCX 13 XTALIN High Time tC * 0.5 – ns tCLCX 13 XTALIN Low Time tC * 0.4 – ns tCLCH 13 XTALIN Rise Time – 5 ns tCHCL 13 XTALIN Fall Time – 5 ns tAVSL All Address Valid to Strobe low tC – 21 – ns tCHAH All Address hold after CLKOUT rising edge 7 1 – ns tCHAV All Delay from CLKOUT rising edge to address valid – 25 ns tCHSH All Delay from CLKOUT rising edge to Strobe High7 1 21 ns tCHSL All Delay from CLKOUT rising edge to Strobe Low7 1 19 ns tCODH 14 ClkOut Duty Cycle High (into 40 pF max.) tCHCX –7 tCHCX +3 ns Data Read Only tAHDR 10 Address hold (A19 – A1 only, not A0) after CS, BLE, BHE rise at end of Data Read Cycle (not code fetch) tC – 12 – ns Data Read and Instruction Fetch Cycles tDIS 7, 8, 10, 11 Data In Valid setup to ClkOut rising edge 25 – ns tDIH 7, 8, 10, 11 Data In Valid hold after ClkOut rising edge 2 0 – ns tOHDE 10 OE high to XA Data Bus Driver Enable tC – 14 – ns Write Cycles tCHDV 9 Clock High to Data Valid – 25 ns tDVSL 12 Data Valid prior to Strobe Low tC – 23 – ns tSHAH 9, 12 Minimum Address Hold Time after strobe goes inactive tC – 25 – ns tSHDH 9, 12 Data hold after strobes (CS and BHE/BLE) high tC – 25 – ns Wait Input tWS 15 WAIT setup (stable high or low) to CLKOUT rising edge 20 – ns tWH 15 WAIT hold (stable high or low) after CLKOUT rising edge 0 – ns NOTE: 1. On a 16-bit bus, if only one byte is being written, then only one of BLE or BHE will go active. On an 8-bit bus, BLE goes active for all (odd or even address) accesses. BHE will not go active during any accesses on an 8 bit bus. 2. The bus timing is designed to make meeting hold time very straightforward without glue logic. On all reads and fetches, in order to meet hold time, the slave should hold data valid on the bus until the earliest of CS, BHE/BLE, OE, goes high (inactive), or until the address changes. 3. To avoid 3-State fights during read cycles and fetch cycles, do not drive data bus until OE goes active 4. WARNING: ClkOut is specified at 40 pF max. More than 40 pf on ClkOut may significantly degrade the ClkOut waveform. Load capacitance for all outputs (except ClkOut) = 80 pF. 5. Not all combinations of bus timing configuration values result in valid bus cycles. Please refer to the XA-H3 User Manual for details. 6. When code is being fetched on the external bus, a burst mode fetch is used. This burst can be from 2 to 16 bytes long. On a 16-bit bus, A3 – A1 are incremented for each new word of the burst. On an 8-bit bus, A3 – A0 are incremented for each new byte of the burst code fetch. 7. The MIN value for this parameter is guaranteed by design and is not tested in production to the specified limit. In those cases where a maximum value is specified in the table for this parameter, it is tested.

Philips Semiconductors Preliminary specification XA-H3CMOS 16-bit highly integrated microcontroller

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AC ELECTRICAL CHARACTERISTICS (3.3 V +/–10%) Vdd = 3.3 V +/– 10%; Tamb = –40°C to +85°C ( industrial ) Symbol Fig re Parameter Limits UnitSymbol Figure Parameter Min Max Unit All Cycles FC System Clock (internally called CClk) Frequency 0 30 MHz tC 13 System Clock Period = 1/FC 33.33 – ns tCHCX 13 XTALIN High Time tC * 0.5 – ns tCLCX 13 XTALIN Low Time tC * 0.4 – ns tCLCH 13 XTALIN Rise Time – 5 ns tCHCL 13 XTALIN Fall Time – 5 ns tAVSL All Address Valid to Strobe low tC – 21 – ns tCHAH All Address hold after CLKOUT rising edge 7 1 – ns tCHAV All Delay from CLKOUT rising edge to address valid – 30 ns tCHSH All Delay from CLKOUT rising edge to Strobe High 7 1 28 ns tCHSL All Delay from CLKOUT rising edge to Strobe Low 7 1 25 ns tCODH 14 ClkOut Duty Cycle High (into 40 pF max.) tCHCX –7 tCHCX +3 ns Data Read Only tAHDR 10 Address hold (A19 – A1 only, not A0) after CS, BLE, BHE rise at end of Data Read Cycle (not code fetch) tC – 12 – ns Data Read and Instruction Fetch Cycles tDIS 7, 8, 10, 11 Data In Valid setup to ClkOut rising edge 32 – ns tDIH 7, 8, 10, 11 Data In Valid hold after ClkOut rising edge 2 0 – ns tOHDE 10 OE high to XA Data Bus Driver Enable tC – 19 – ns Write Cycles tCHDV 9 Clock High to Data Valid – 30 ns tDVSL 12 Data Valid prior to Strobe Low tC – 23 – ns tSHAH 9, 12 Minimum Address Hold Time after strobe goes inactive tC – 25 – ns tSHDH 9, 12 Data hold after strobes (CS and BHE/BLE) high tC – 25 – ns Wait Input tWS 15 WAIT setup (stable high or low)prior to CLKOUT rising edge 25 – ns tWH 15 WAIT hold (stable high or low) after CLKOUT rising edge 0 – ns NOTE: 1. On a 16-bit bus, if only one byte is being written, then only one of BLE or BHE will go active. On an 8-bit bus, BLE goes active for all (odd or even address) accesses. BHE will not go active during any accesses on an 8-bit bus. 2. The bus timing is designed to make meeting hold time very straightforward without glue logic. On all reads and fetches, in order to meet hold time, the slave should hold data valid on the bus until the earliest of CS, BHE/BLE, OE, goes high (inactive), or until the address changes. 3. To avoid 3-State fights during read cycles and fetch cycles, do not drive data bus until OE goes active 4. WARNING: ClkOut is specified at 40 pF max. More than 40 pf on ClkOut may significantly degrade the ClkOut waveform. Load capacitance for all outputs (except ClkOut) = 80 pF. 5. Not all combinations of bus timing configuration values result in valid bus cycles. Please refer to the XA-H3 User Manual for details. 6. When code is being fetched on the external bus, a burst mode fetch is used. This burst can be from 2 to 16 bytes long. On a 16-bit bus, A3 – A1 are incremented for each new word of the burst. On an 8-bit bus, A3 – A0 are incremented for each new byte of the burst code fetch. 7. The MIN value for this parameter is guaranteed by design and is not tested in production to the specified limit. In those cases where a maximum value is specified in the table for this parameter, it is tested.

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should not be used on some peripheral devices. Figure 7. Read on 16-Bit Bus Note: The processor can prefetch from one to eight words. Figure 8. Burst Code Fetch on 16-Bit Bus

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Figure 9. Write ( byte write on 8-bit bus, or all writes on 16-bit bus ) though the CPU will only use one of the two bytes. nique is that byte reads are faster than on an 8-bit bus, because only 1 word is fetched (a single read) instead of 2 consecutive bytes. Figure 10. Read (16-Bit or 8-Bit) on 8 Bit Bus

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from 1 to 8 words (1 word = 2 bytes), a 2 word fetch is shown here. Figure 11. Burst Code Fetch on 8-bit bus Note. OE is inactive during all writes. Figure 12. 16-Bit Write on 8-Bit Bus

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0.7 VDD

Figure 13. External Clock Input Drive WARNING: ClkOut is specified into 40 pF max, do not overload. Figure 14. ClkOut Duty Cycle tWS – Setup time of WAIT to rising edge of ClkOut. tWH – Hold time of WAIT after ClkOut High. Figure 15. External WAIT Pin Timing

Philips Semiconductors Preliminary specification XA-H3CMOS 16-bit highly integrated microcontroller

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LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1

Philips Semiconductors Preliminary specification XA-H3CMOS 16-bit highly integrated microcontroller

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Philips Semiconductors Preliminary specification XA-H3CMOS 16-bit highly integrated microcontroller

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Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors

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P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381  Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Date of release: 09-99 Document order number: 9397 750 06431 /C0080 /C0115 /C0111/C0110/C0111 /C0115 Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Production Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Data sheet status [1] Please consult the most recently issued datasheet before initiating or completing a design.