Microcontroller

PXAC37

NXP Semiconductors

XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce 2000 Jan 25

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/C0080 /C0115 /C0111/C0110/C0111 /C0115 XA-C3 XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-processor Preliminary specification Supersedes data of 1999 Dec 20

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Philips Semiconductors Preliminary specification XA-C3 XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor

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The XA–C3 is a member of the Philips XA (eXtended Architecture) family of high–performance 16–bit single–chip microcontrollers. The XA–C3 combines an array of standard peripherals together with a PeliCAN CAN 2.0B engine and unique ”Message Management” hardware to provide integrated support for most CAN Transport Layer (CTL) protocols such as DeviceNet, CANopen and OSEK. For additional details, refer to the XA-C3 Overview on page 35. The XA architecture supports: /C0068Easy 16-bit migration from the 80C51 architecture. /C006816–bit fully static CPU with 24–bit addressed PROGRAM and DATA spaces. /C0068Twenty–one 16–bit CPU core registers capable of all arithmetic and logic operations while serving as memory pointers. /C0068An enhanced orthogonal instruction set tailored for high–level support of the C language. /C0068Multi–tasking and direct real–time executive support. /C0068Low–power operation intrinsic to the XA architecture includes Power–Down and Idle modes. FEATURES IN COMMON WITH XA-G3 /C0068Pin–compatibility (CAN RxD and CAN TxD use the XA-G3 NC pins). /C006832K bytes of on–chip EPROM PROGRAM memory (see Table 1). /C006844–pin PLCC (Figure 1 and Table 2) and 44–pin LQFP (Figure 2 and Table 3) packages. /C0068Commercial (0 to 70oC) and Industrial (–40 to 85oC) ranges. /C0068Supports off–chip addressing of PROGRAM and DATA memory up to 1 megabyte each (20 address lines). /C0068Three standard counter/timers (T0, T1, and T2) with enhancements such as Auto Reload for PWM outputs. /C0068UART–0 with enhancements such as separate Rx and Tx interrupts, Break Detection, and Automatic Address Recognition. /C0068Watchdog with a secure WFEED1 / WFEED2 sequence. /C0068Four 8–bit I/O ports with 4 programmable output configurations per pin. XA-C3 SPECIFIC FEATURES /C006832 MHz operating frequency at 4.5 to 5.5V operation. /C0068One Serial Port Interface (SPI) /C00681024 bytes of on–chip DATA RAM. /C006842 vectored interrupts. These include 13 maskable Events, 7 Software interrupts, 6 Exceptions, 16 software Traps, segmented DATA memory, multiple User stacks, and banked registers to support rapid context switching. /C0068External interfacing via a 16–bit DATA bus width. XA-C3 CAN AND CTL FEATURES /C0068A PeliCAN CAN 2.0B engine from the SJA1000 Stand–alone CAN controller which supports 11– and 29–bit IDentifiers and the maximum CAN data rate (1 Mbps) and CAN Diagnostics. /C0068Hardware “Message Management” support for all major CTL protocols: DeviceNet, CANopen, OSEK. /C0068Automatic (hardware) assembly of Fragmented Messages via a Transport Layer Co-Processor. Concurrent assembly of up to 32 separate interleaved Fragmented Messages /C006832 CAN Transport Layer (CTL) Message Objects are modelled as a FullCAN Object Superset. /C006832 separate filters/screeners (one per Message Object), each allowing a 30–bit ID Match and full 29–bit Mask (i.e., each filter/screener represents a unique Group address). /C0068Each Message Object can be configured as Receive or Transmit. /C0068A separate message buffer is associated with each CTL Message Object. 32 message buffers are located in XRAM and managed by 32 DMA channels. Message buffer size for each Message Object is independently configurable in length (from 2 to 256 bytes). /C0068For single–chip systems there is a 512–byte (on–chip) XRAM message buffer, independent of the 1K on–chip DATA RAM, which is extendable (off–chip) to 8K bytes (i.e., 32 Message Objects that can be up to 256 bytes each). LOGIC SYMBOL AND BLOCK DIAGRAM Refer to Figure 3 for the logic symbol for the XA-C3 and to Figure 4 for a simplified block diagram representation. UPGRADING XA-G3 DESIGNS TO CAN /C0068XA-G3 NC pins are XA-C3 CAN RxD and CAN TxD pins. /C0068XA-G3 UART–1 is replaced by a Serial Port Interface (SPI) /C0068XA-C3 software must never write to the BCR register /C0068XA-C3 software must initialize BTRH and BTRL with 00h

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ORDERING INFORMATION

Table 1. Ordering Information

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Figure 1. 44-pin PLCC package Table 2. 44-pin PLCC package pin functions

1 VSS 23 VDD

10 RST / 32 PSEN /

12 CAN RxD 34 CAN TxD

22 VSS 44 VDD

All active–low signals are indicated by a “/” symbol

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Figure 2. 44-pin PLCC package Table 3. 44-pin LQFP package pin functions

4 RST / 26 PSEN /

6 CAN RxD 28 CAN TxD

16 VSS 38 VDD

17 VDD 39 VSS

All active–low signals are indicated by a “/” symbol

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32 DMA CHANNELS

32 CAL MESSAGE

Figure 3. Logic Symbol

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1024 BYTES

512 BYTES XRAM

32 CTL DMA

32 OBJECT PTRS

32 ID FILTERS

Figure 4. XA-C3 Simplified Block Diagram

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Table 4. Pin Descriptions VSS 1, 22 16, 39 I Ground: 0V Reference. lected. Each Port pin is configured independently. configuration and DC Electrical Characteristics for details.

When the External PROGRAM/DATA bus is used, Port 0 becomes the multiplexed

low DATA/Instruction Byte and Address lines 4 through 11. lected. Each Port pin is configured independently. configuration and DC Electrical Characteristics for details. P1.1 3 41 O A1: Address bit 1 of the External Address bus. P1.2 4 42 O A2: Address bit 2 of the External Address bus. P1.3 5 43 O A3: Address bit 3 of the External Address bus. P1.4 6 44 I SPIRx: Receiver serial input of SPI. P1.5 7 1 O SPITx: Transmitter serial output of SPI. output, or SPI Clock output.

SPICLK must be configured to idle in the logic ‘1’ state in order to use either the T2
The default state from Reset of the SPICLK polarity is “inverted” which yields an

SPICLK idle state of logic ‘1’.

If the SPI Clock polarity is changed by the user during SPI Port usage, it must be

P1.7 9 3 O T2EX: Timer/counter 2 reload/capture/direction control. lected. Each Port pin is configured independently.

When the External 16–bit PROGRAM/DATA bus is used, Port 2 is MUXed between

High (DATA/Instruction) Byte and Address lines 12 through 19. I/O Port 3: Port 3 is an 8–bit I/O Port with user–configurable pins.

Port 3 latches have 1’s written to them and are configured in the Quasi–Bidirectional
The operation of Port 3 pins as inputs or outputs depends upon the Port
Each Port pin is configured independently.

P3.0 11 5 I RxD0: Receiver serial input of UART 0. P3.1 13 7 O TxD0: Transmitter serial output of UART 0. P3.2 14 8 I INT0/: External interrupt 0 input. P3.3 15 9 I INT1/: External interrupt 1 input.

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MNEMONIC NAME AND FUNCTION TYPEPIN NUMBERS LQFPPLCC P3.4 16 10 I/O T0: Timer 0 External count input or Timer 0 Overflow output. P3.5 17 11 I/O T1 : Timer 1 External count input or Timer 1 Overflow output. P3.6 18 12 O WRL /: External DATA memory Low Byte Write Strobe. P3.7 19 13 O RD /: External DATA memory Read Strobe. RST / 10 4 I RESET /: NOTE: 10. A low on this pin resets the XA–C3, causing I/O Ports and peripherals to take on their default states, and the processor to begin execution at the Address contained in the Reset Vector. Refer to the Reset section for details. ALE ; PROG/ 33 27 I/O Address Latch Enable ; Program Pulse/: NOTES: 11. A high output on the ALE pin signals External circuitry to latch the address portion of the multiplexed Address/DATA bus. 12. A pulse on ALE occurs only when needed to process an External bus cycle. During EPROM programming, this pin is used as the Program pulse input. PSEN / 32 26 O Program Store Enable/: This is the Read Strobe for External PROGRAM memory. NOTES: 13. When the microcontroller accesses External PROGRAM memory, PSEN/ is driven low in order to enable memory devices. 14. PSEN/ is only active when External code accesses are performed. EA / ; WAIT ; VPP 35 29 I External Access/ ; WAIT ; Programming Supply Voltage: NOTES: 15. The EA/ input determines whether the internal PROGRAM memory of the XA–C3 is used for code execution. 16. The EA/ pin is latched as the (External) Reset input is released and its value applied during later execution. When latched as a 0, External PROGRAM memory is used exclusively. When latched as a 1, internal PROGRAM memory will be used up to its limit, and External PROGRAM memory is used above that point. 17. After Reset is released, this pin takes on the function of a Bus WAIT input. If WAIT is asserted High during any External bus access, that cycle will be extended until WAIT is released. 18. During EPROM programming, this pin is also the programming supply voltage input. CAN RxD 12 6 I CAN Receive Data input: CAN serial receiver input to the SJA1000 PeliCAN core. CAN TxD 34 28 O CAN Transmit Data output: CAN serial transmitter output from the SJA1000 PeliCAN core. XTAL1 21 15 I Crystal 1: Input to the inverting amplifier used in the oscillator circuit and input to the internal clock generator circuits. XTAL2 20 14 O Crystal 2: Output from the oscillator amplifier. NOTE: 1. All active–low signals are indicated by a “/” symbol.

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Table 5. Special Function Registers

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NAME RESETBIT FUNCTIONS AND BIT ADDRESSESSFRDESCRIPTION VALUE01234567ADDRESS 30F 30E 30D 30C 30B 30A 309 308 S0STAT* Serial port 0 extended status 421h – – – – FE0 BR0 OE0 STINT0 00h S0BUF Serial port 0 buffer register 460h xxh S0ADDR Serial port 0 address register461h 00h S0ADEN Serial port 0 address enable register 462h 00h SCR System configuration register 440h – – – – PT1 PT0 CM PZ 00h 21F 21E 21D 21C 21B 21A 219 218 SSEL* Segment selection register 403h ESWEN R6SEG R5SEG R4SEG R3SEG R2SEG R1SEG R0SEG 00h SWE Software Interrupt Enable 47Ah – SWE7 SWE6 SWE5 SWE4 SWE3 SWE2 SWE1 00h 357 356 355 354 353 352 351 350 SWR* Software Interrupt Request 42Ah – SWR7 SWR6 SWR5 SWR4 SWR3 SWR2 SWR1 00h 2C7 2C6 2C5 2C4 2C3 2C2 2C1 2C0 T2CON* Timer 2 control register 418h TF2 EXF2 RCLK0 TCLK0 EXEN2 TR2 C2 or T2/ CP or RL2 / 00h 2CF 2CE 2CD 2CC 2CB 2CA 2C9 2C8 T2MOD* Timer 2 mode control 419h – – – – – – T2OE DCEN 00h TH2 Timer 2 high byte 459h 00h TL2 Timer 2 low byte 458h 00h T2CAPH Timer 2 capture register, high byte 45Bh 00h T2CAPL Timer 2 capture register, low byte 45Ah 00h 287 286 285 284 283 282 281 280 TCON* Timer 0 and 1 control register410h TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00h TH0 Timer 0 high byte 451h 00h TH1 Timer 1 high byte 453h 00h TL0 Timer 0 low byte 450h 00h TL1 Timer 1 low byte 452h 00h TMOD Timer 0 and 1 mode control 45Ch GATE1 C1 or T1/ M1 M0 GATE0 C0 or T0/ M1 M0 00h 28F 28E 28D 28C 28B 28A 289 288 TSTAT* Timer 0 and 1 extended status 411h – – – – – T1OE – T0OE 00h 2FF 2FE 2FD 2FC 2FB 2FA 2F9 2F8 WDCON* Watchdog control register 41Fh PRE2 PRE1 PRE0 – – WDRUN WDTOF – Note 6 WDL Watchdog timer reload 45Fh 00h WFEED1 Watchdog feed 1 45Dh xxh WFEED2 Watchdog feed 2 45Eh xxh NOTES: 1. Users should never write to the BCR register. 2. Users must ALWAYS INITIALIZE (Write) 00h to this register. 3. Port configurations default to Quasi–Bidirectional when the XA begins execution from Internal code memory after Reset, based on the condition found on the EA / pin. Thus, all PnCFGA registers will contain FFh and PnCFGB registers will contain 00h. When the XA begins execution using External code memory, the default configuration for pins that are associated with the External bus will be Push–Pull. The PnCFGA and PnCFGB register contents will reflect this difference. 4. SFR is loaded from the Reset vector. 5. All bits except F1, F0, and P are loaded from the Reset vector. Those bits are all 0. 6. The WDCON Reset value is E6h for a Watchdog Reset, E4h for all other Reset causes. The Watchdog is always turned ON as one consequence of RST/. Therefore, the user should turn OFF the Watchdog if immediate Watchdog operation is not desired: See the Watchdog Timer section in this Data Sheet for a recommended code example. GENERAL NOTES: – SFRs marked with an asterisk (*) are bit–addressable. – The XA–C3 implements an 8–bit SFR bus, as stated in Chapter 8 of the XA User Guide. All SFR accesses must be 8–bit operations. Attempts to write 16 bits to an SFR will actually write only the lower 8 bits. Sixteen–bit SFR reads will return undefined data in the upper byte. – Unimplemented bits in SFRs (indicated by ”–”} are unknown at all times. Ones should not be written to these bits since they may be used for other purposes in future XA derivatives. In general, the Reset value shown for these unimplemented bits is 00h. – The XA guards writes to all SFR bits that can be modified by hardware, including all SFR resident interrupt flags, as well as the WDTOF bit in WDCON. This mechanism, called Read–Modify–Write Lockout, prevents loss of an interrupt (or other status) flag if a bit is written to directly by hardware between the read and write of an instruction that performs a read–modify–write operation.

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Table 6. Memory-Mapped Registers

SLPEN (Sleep Enable), CANCMR[3], is writable only when the CAN Core is in Normal mode.

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count up unless otherwise stated. timer functions, including baud rate generation and Timer 2 capture. Note: This single SCR rate setting applies to all timers. guaranteed to be “seen” by the timer logic. larger range when used as time bases. and speeds up execution but limits memory access to 64k. Figure 5. System Configuration Register (SCR) “TRn” control bit is set. When cleared Timer “n” is enabled whenever “TRn” control bit is set. Set for Counter operation (input from “Tn” input pin). Figure 6. Timer/Counter Mode Control (TMOD) Register

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and RTH registers respectively. 8–bit auto–reload mode (Mode 2) instead of TH. where N = the TCLK prescaler value: 4 (default), 16, or 64. Mode 1 is the 16–bit non–auto reload mode. reloads TLn with the contents of RTLn, which is preset by software. The reload leaves THn unchanged. Mode 2 operation is the same for Timer/Counter 0. where N = the TCLK prescaler value: 4, 16, or 64. Mode 3 is provided for applications requiring an extra 8–bit timer. TCON.7 TF1 Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. This flag will not be set if T1OE (TSTAT.2) is set. Cleared by hardware when processor vectors to interrupt routine, or by clearing the bit in software. TCON.6 TR1 Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter 1 on/off. TCON.5 TF0 Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. This flag will not be set if T0OE (TSTAT.0) is set. Cleared by hardware when processor vectors to interrupt routine, or by clearing the bit in software. TCON.4 TR0 Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter 0 on/off. TCON.3 IE1 Interrupt 1 Edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. TCON.1 IE0 Interrupt 0 Edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. triggered external interrupts. Figure 7. Timer/Counter Control (TCON) Register

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T2CON.7 TF2 Timer 2 overflow flag. Set by hardware on Timer/Counter overflow. Must be cleared by software. TF2 will not be set when RCLK0, RCLK1, TCLK0, TCLK1 or T2OE=1. T2CON.5 RCLK0 Receive Clock Flag. T2CON.3 EXEN2 Timer 2 external enable bit allows a capture or reload to occur due to a negative transition on T2EX. T2CON.2 TR2 Start=1/Stop=0 control for Timer 2. T2CON.1 C2 or T2/ Timer or counter select. T2CON.0 CP or RL2/ Capture/Reload flag. If CP/RL2 & EXEN2=1 captures will occur on negative transitions of T2EX. If CP/RL2=0, EXEN2=1 auto reloads occur with either Timer 2 overflows or negative transitions at T2EX. If RCLK or TCLK=1 the timer is set to auto reload on Timer 2 overflow, this bit has no effect. Figure 8. Timer/Counter 2 Control (T2CON) Register cycle PWM outputs (changing the auto–reload register values). UART via SFRs T2CON and T2MOD – see Figure 10. These modes are shown in Table 7. interrupt is enabled. The capture mode is illustrated in Figure 11. 16–bit value in T2CAPH and T2CAPL when the count overflows. T2EX. The auto–reload mode is shown in Figure 12. T2EX is low, the count is in the down direction. bit or EXF2 bit can generate the Timer 2 interrupt.

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TF2 flag, which can generate an interrupt if enabled. mode. As the baud rate generator, timer T2 is incremented by TCLK. A 50% duty cycle clock can be programmed to come out on P1.6. Timer/Counter 2 or to output a 50% duty cycle clock. set. Bit TR2 (T2CON[2]) also must be set to start the timer. interrupt. This is similar to when it is used as a baud–rate generator. 1/8 of the Clock–Out frequency. Table 7. Timer 2 Operating Modes

0 X X X Timer off (stopped)

1 X 1 X Baud rate generator

TSTAT.2 T1OE When 0, this bit allows the T1 pin to clock Timer 1 when in the counter mode. When 1, T1 acts as an output and toggles at every Timer 1 overflow. TSTAT.0 T0OE When 0, this bit allows the T0 pin to clock Timer 0 when in the counter mode. When 1, T0 acts as an output and toggles at every Timer 0 overflow. Figure 9. Timer 0 and 1 Extended Status (TSTAT) T2MOD.5 RCLK1 Receive Clock Flag. for UART1 instead of Timer T1. T2MOD.1 T2OE When 0, this bit allows the T2 pin to clock Timer 2 when in the counter mode. When 1, T2 acts as an output and toggles at every Timer 2 overflow. T2MOD.0 DCEN Controls count direction for Timer 2 in autoreload mode. DCEN=1 counter set to count up or down, depending on T2EX (see text). Figure 10. Timer 2 Mode Control (T2MOD)

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Figure 11. Timer 2 in Capture Mode Figure 12. Timer 2 in Auto-Reload Mode (DCEN = 0)

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Figure 13. Timer 2 Auto Reload Mode (DCEN = 1)

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8–bits of the prescaler as shown in Figure 14. permissible since the prescaler is cleared upon autoload). tD is the design time–out value. value to be loaded into the main timer is held in an autoload register. operation is referred to as feeding the watchdog timer. clr ea ; disable global interrupts. setb ea ; re–enable global interrupts. Table 8. Prescalar Select Values in WDCON /C0068Watchdog run control bit set to ON (1). /C0068Autoload register WDL set to 00 (min. count). /C0068Watchdog time–out flag cleared. /C0068Prescaler tap set to the highest divide.

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Figure 14. Watchdog Timer in XA-C3 /C0068Watchdog run bit unchanged. /C0068Autoload (WDL) register unchanged. /C0068Prescaler tap unchanged. /C0068All other device action same as External Reset. loaded from the Reset vector as in the case of an internal Reset. flag bit can be cleared by software. between bytes and less critical interrupt service routine timing. status bit that the User program may use to test BR0 (S0STAT[2]). characters in the received data stream. overflow rate (in UART–0 Modes 1 and 3). to 1/32 of the oscillator frequency.

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Reception is initiated in Mode 1, 2, or 3 by the incoming start bit if

Receive Interrupt flag RI_0 (S0CON[0]) . setting the EA bit (IEL[7]). clock rate is determined by the overflow rates of either T1 or T2. however, it is fixed rate at fosc/32. Table 9. TCLK Frequencies fosc/4 (since the minimum pre–scalar value N is equal to 4). overflow) divided by 16, i.e., fosc/64. where N = the TCLK prescaler value (4, 16, or 64). and Timer_Range = 256 for Timer 1 in Mode 2.

The maximum baud rate for UART–0 in Mode 1 or 3 is fosc/64.
The lowest possible baud rate (for a given oscillator frequency

and N value) may be found by using a timer reload value of 0.

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The timer reload value may never be larger than the timer range.
If a timer reload value calculation gives a negative or fractional

oscillator frequency and N value. receiver by setting TCLK0 and/or RCLK0 in T2CON (see Table 10). (SCR[3]) and PTO (SCR[2]). See Table 11). “INT2/” whenever Timer T2 is used as a baud rate generator. Table 10. T2CON Settings Table 11. Prescaler Select for Timer Clock S0STAT.3 FE0 Framing Error flag is set when the receiver fails to see a valid STOP bit at the end of the frame. a user program may poll. Cleared by software. received while RI_0 in S0CON is still set. Cleared by software. S0STAT.0 STINT0 This flag must be set to enable any of the above status flags to generate a receive interrupt (RI_0). The only way it can be cleared is by a software write to this register. Figure 15. Serial Port Extended Status (S0STAT) Register Note: See also Figure 17 regarding Framing Error flag. receive functions (see Table 12 below). Table 12. Vector Locations for UART in XA address to work like an 8051 interrupt scheme. one goes into bit RB_8 (S0CON[2]). Then comes a stop bit. received, the serial port interrupt will be activated only if RB_8 = 1. unless a valid stop bit is received. UART–0 has the four error flags as described in Figure 15. address recognition is shown in Figure 16.

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necessary to make bit 2 = 1 to exclude slave 2. the broadcast address will be FF hexadecimal. UART drivers which do not make use of this feature. activated if a valid stop bit was not received. In Mode 0, SM2_0 should be 0. S0CON.4 REN_0 Enables serial reception. Set by software to enable reception. Clear by software to disable reception. not double buffered. See text for details. received. In Mode 0, RB8_0 is not used. S0CON.1 TI_0 Transmit interrupt flag. Set when another byte may be written to the UART transmitter. See text for details. Must be cleared by software. in the other modes (except see SM2_0). Must be cleared by software. Figure 16. Serial Port Control (S0CON) Register

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Figure 17. UART Framing Error Detection – WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2_0 TO WAIT FOR NEXT ADDRESS. Figure 18. UART Multiprocessor Communication, Automatic Address Recognition Reset, the default configuration is Quasi–Bidirectional. controlled by setting bit 3 (P1CFGA[3] and P1CFGB[3]). Table 13. Port Configuration Register Settings Note: Mode changes may cause glitches to occur during transitions. Refer to Figure 19 for a recommended Reset circuit example. Figure 19. Recommended Reset Circuit

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The EA/ pin is sampled on the rising edge of the Reset (RST/) pulse. begin execution from internal or External PROGRAM memory. Specifically, if EA/ is pulled high, the XA starts in Single–Chip mode. bus WAIT signal for External bus transactions. weak pull up assures the PXAC3 will set–up a 16 bit External bus. put a LOW on P3.5 during RESET. guarantee that the desired EA/ value is latched correctly. signals is shown in Figure 20. Figure 20. EA/ Timing Diagram Power–Down mode stops the oscillator in order to minimize power. Power–Down mode was entered. permitting lower priority Event Interrupts to run. RTOS, via non–maskable interrupts.

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Reset, Stack Overflow, and Divide–by–zero. Four tables provide details of the XA-C3 Interrupt structure. serviced, the higher priority Event takes over. priority Event is serviced first. Table 14. Interrupt Priority Levels

15 Event Interrupt

14 Event Interrupt

13 Event Interrupt

12 Event Interrupt

11 Event Interrupt

10 Event Interrupt

9 Event Interrupt

7 Software Interrupt

6 Software Interrupt

5 Software Interrupt

4 Software Interrupt

3 Software Interrupt

2 Software Interrupt

1 Software Interrupt

0 Interrupt Disable

Details of the priority scheme may be found in the XA User

Table 15. Exception and Trap Interrupt Vectors

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Table 16. Event Interrupt Vectors

When Timer 2 is used as a baud rate generator, pin T2EX [P1.7] acts as an additional External interrupt.

Table 17. Software Interrupt Vectors Table 18. Absolute Maximum Ratings

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Table 19. DC Electrical Characteristics Tambient = 0 to +70°C for commercial, –40°C to +85°C for industrial, unless otherwise specified.

Ports in Quasi–Bidirectional mode with weak pull–up (applies to ALE, PSEN/ only during Reset operations).
Ports in Push–Pull mode, both pull–up and pull–down are assumed to be of the same strength
Port pins source a transition current when used in Quasi–Bidirectional mode and externally driven from 1 to 0. This current is highest when
Measured with port in high–impedance output mode.
Measured with port in Quasi–Bidirectional output mode.
Load capacitance for all outputs=80pF.
Under steady state (non–transient) conditions, IOL must be externally limited as follows:
See Figures 29, 30, 32, and 33 for IDD test conditions, and Figure 31 for ICC vs. Frequency.

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Table 20. AC Electrical Characteristics VDD = 4.5V to 5.5V; Tamb = 0 to +70°C for commercial, –40°C to +85°C for industrial.

Load capacitance for all outputs = 80pF.
Variables V1 through V13 reflect programmable bus timing, which is

programmed via the Bus Timing registers (BTRH and BTRL). Refer to the XA User Guide for details of the bus timing settings. as determined by the ALEW bit in the BTRL register. V1 = 0.5 if the ALEW bit = 0, and 1.5 if the ALEW bit = 1. ALEW bits in the BTRL register. determining peripheral timing requirements.

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V4) This variable represents the programmed length of an entire code read cycle with no ALE. This time is determined by the CR1 and CR0 bits in the BTRL register. V4 = 1 if CR1/0 = 00, 2 if CR1/0 = 01, 3 if CR1/0 = 10, and 4 if CR1/0 = 11. V5) This variable represents the programmed length of an entire data read cycle with no ALE. this time is determined by the DR1 and DR0 bits in the BTRH register. V5 = 1 if DR1/0 = 00, 2 if DR1/0 = 01, 3 if DR1/0 = 10, and 4 if DR1/0 = 11. V6) This variable represents the programmed length of an entire data read cycle with ALE. The time is determined by the DRA1 and DRA0 bits in the BTRH register. V6 = the total bus cycle duration (2 if DRA1/0 = 00, 3 if DRA1/0 = 01, 4 if DRA1/0 = 10, and 5 if DRA1/0 = 11). V7) This variable represents the programmed width of the RD/ pulse as determined by the DR1 and DR0 bits or the DRA1, DRA0 in the BTRH register, and the ALEW bit in the BTRL register. – For a bus cycle with no ALE, V7 = 1 if DR1/0 = 00, 2 if DR1/0 = 01, 3 if DR1/0 = 10, and 4 if DR1/0 = 11. – For a bus cycle with an ALE, V7 = the total bus cycle duration (2 if DRA1/0 = 00, 3 if DRA1/0 = 01, 4 if DRA1/0 = 10, and 5 if DRA1/0 = 11) minus the number of clocks used by ALE (V1 + 0.5). Example: If DRA1/0 = 00 and ALEW = 0, then V7 = 2 – (0.5 + 0.5) = 1. V8) This variable represents the programmed width of the WRL/ and/or WRH / pulse as determined by the WM1 bit in the BTRL register. V8 1 if WM1 = 0, and 2 if WM1 = 1. V9) This variable represents the programmed address setup time for a write as determined by the data write cycle duration (defined by DW1 and DW0 or the DWA1 and DWA0 bits in the BTRH register), the WM0 bit in the BTRL register, and the value of V8. – For a bus cycle with an ALE, V9 = the total bus write cycle duration (2 if DWA1/0 = 00, 3 if DWA1/0 = 01, 4 if DWA1/0 = 10, and 5 if DWA1/0 = 11) minus the number of clocks used by the WRL / and/or WRH/ pulse (V8), minus the number of clocks used by data hold time (0 if WM0 = 0 and 1 if WM0 = 1). Example: If DWA1/0 = 10, WM0 = 1, and WM1 = 1, then V9 = 4 – 1 – 2 = 1. – For a bus cycle with no ALE, V9 = the total bus cycle duration (2 if DW1/0 = 00, 3 if DW1/0 = 01, 4 if DW1/0 = 10, and 5 if DW1/0 = 11) minus the number of clocks used by the WRL/ and/or WRH/ pulse (V8), minus the number of clocks used by data hold time (0 if WM0 = 0 and 1 if WM0 = 1). Example: If DW1/0 = 11, WM0 = 1, and WM1 = 0, then V9 = 5 – 1 – 1 = 3. V10) This variable represents the length of a bus strobe for calculation of WAIT setup and hold times. The strobe may be RD/ (for data read cycles), WRL/ and/or WRH/ (for data write cycles), or PSEN/ (for code read cycles), depending on the type of bus cycle being widened by WAIT. V10 = V2 for WAIT associated with a code read cycle using PSEN/. V10 = V8 for a data write cycle using WRL/ and/or WRH/. V10 = V7–1 for a data read cycle using RD/. This means that a single clock data read cycle cannot be stretched using WAIT. If WAIT is used to vary the duration of data read cycles, the RD/ strobe width must be set to be at least two clocks in duration. Also see Note 4. V11) This variable represents the programmed write hold time as determined by the WM0 bit in the BTRL register. V11 = 0 if the WM0 bit = 0, and 1 if the WM0 bit = 1. V12) This variable represents the programmed period between the end of the ALE pulse and the beginning of the WRL/ and/or WRH/ pulse as determined by the data write cycle duration (defined by the DWA1 and DWA0 bits in the BTRH register), the WM0 bit in the BTRL register, and the values of V1 and V8. V12 = the total bus cycle duration (2 if DWA1/0 = 00, 3 if DWA1/0 = 01, 4 if DWA1/0 = 10, and 5 if DWA1/0 = 11) minus the number of clocks used by the WRL/ and/or WRH/ pulse (V8), minus the number of clocks used by data hold time (0 if WM0 = 0 and 1 if WM0 = 1), minus the width of the ALE pulse (V1). Example: If DWA1/0 = 11, WM0 = 1, WM1 = 0, and ALEW = 1, then V12 = 5 – 1 – 1 – 1.5 = 1.5. V13) This variable represents the programmed data setup time for a write as determined by the data write cycle duration (defined by DW1 and DW0 or the DWA1 and DWA0 bits in the BTRH register), the WM0 bit in the BTRL register, and the values of V1 and V8. – For a bus cycle with an ALE, V13 = the total bus cycle duration (2 if DWA1/0 = 00, 3 if DWA1/0 = 01, 4 if DWA1/0 = 10, and 5 if DWA1/0 = 11) minus the number of clocks used by the WRL/ and/or WRH/ pulse (V8), minus the number of clocks used by data hold time (0 if WM0 = 0 and 1 if WM0 = 1), minus the number of clocks used by ALE (V1 + 0.5). Example: If DWA1/0 = 11, WM0 = 1, WM1 = 1, and ALEW = 0, then V13 = 5 – 1 – 2 – 1 = 1. – For a bus cycle with no ALE, V13 = the total bus cycle duration (2 if DW1/0 = 00, 3 if DW1/0 = 01, 4 if DW1/0 = 10, and 5 if DW1/0 = 11) minus the number of clocks used by the WRL/ and/or WRH/ pulse (V8), minus the number of clocks used by data hold time (0 if WM0 = 0 and 1 if WM0 = 1). Example: If DW1/0 = 01, WM0 = 1, and WM1 = 0, then V13 = 3 – 1 – 1 = 1. 3. Not all combinations of bus timing configuration values result in valid bus cycles. Refer to the XA User Guide section on the External Bus for details. 4. When code is being fetched for execution on the External bus, a burst–mode fetch is used that does not have PSEN/ edges in every fetch cycle. Thus, if WAIT is used to delay code fetch cycles, a change in the low–order address lines must be detected to locate the beginning of a cycle. This would be A3 A1 while using an External 16 bit bus. 5. This parameter is provided for peripherals that have the data clocked in on the falling edge of the WR/ strobe. This is not usually the case, and in most applications this parameter is not used. 6. Please note that the XA–C3 requires that extended data bus hold time (WM0 = 1) to be used with External bus write cycles.

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Figure 21. External PROGRAM Memory Read Cycle (ALE Cycle) Figure 22. External PROGRAM Memory Read Cycle (Non-ALE Cycle)

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Figure 23. External DATA Memory Read Cycle (ALE Cycle) Figure 24. External DATA Memory Write Cycle

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Figure 25. WAIT Signal Timing Figure 26. External Clock Drive AC inputs during testing are driven at VDD –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’. Timing measurements are made at the 50% point of transitions. Figure 27. AC Testing Input/Output and begins to float when a 100mV change from the loaded VOH /VOL level occurs. IOH /IOL ≥ ±20mA. Figure 28. Float Waveform

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Figure 29. IDD Test Condition, Active Mode Figure 30. IDD Test Condition, Idle Mode Figure 31. IDD vs. Frequency at VDD = 5.0V Figure 32. Clock Signal Waveform for IDD Tests in Active and Idle Modes

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Figure 33. IDD Test Condition, Power-Down Mode the same as that used by the later 80C51 family EPROM parts. However, different pins are used for many programming functions. the internet at www.philipsmcu.com/ftp.html. PROGRAM memory execution is disabled. (See Table 21). Table 21. PROGRAM Security Bits 1 U U U No PROGRAM Security features enabled.

2 P U U MOVC instructions executed from External PROGRAM memory are disabled from fetching code

bytes from internal memory and further programming of the EPROM is disabled. 3 P P U Same as 2, also verify is disabled. 4 P P P Same as 3, External execution is disabled. Internal DATA RAM is not accessible.

P – programmed. U – unprogrammed.
Any other combination of the security bits is not defined.

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family of high performance 16–bit single–chip microcontrollers. support for most CAN T ransport Layer (CTL) protocols. existing CAN product, including the SJA 1000 itself. long Messages distributed over many CAN Frames (see Figure 34). can be used independently of CTL . Figure 34. Interleaved CAN Data Frames accepted, to store that frame in a pre–assigned Message Object. necessary data to transmit a complete CAN Data Frame. Arbitration ID and the IDE bit, and can include up to 2 Data Bytes. Object, are programmed by the User in designated MMR s. Objects is an important new CTL feature.

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associated Receive Message Object. is accessed as Data memory by the XA processor. Figure 35. CAN Frame Formats Objects that store single CAN frames. processing from 80% to as low as 10%. as–well–as 29 bits of Mask … per object. where some (or all) of the 32 (Rx/Tx) message buffers may reside. can accommodate up to thirty–two, 256–byte message buffers.

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independent of arbitration ID. The XA-C3 supports Remote CAN Frames.

512 Bytes

Figure 36. MMRs and XRAM mapped into Segment 00h. 008000h. The code memory address space extends to 0FFFFFh. Figure 37. External Code Memory starts at 008000h. BRP.0 are bits in the MMR CAN B us Timing R egister (CANBTR). number of CAN System Clocks.

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The location of the sample point within a bit period is determined according to the following: one bit period tSYNC– SEG tSEG1 tSEG2 Sample point SU01339 /C0068tSYNCSEG = tSCL /C0068tSEG1 = tSCL ∗ (8 ∗ tSEG1.3 + 4 ∗ tSEG1.2 + 2 ∗ tSEG1.1 + tSEG1.0 + 1) /C0068tSEG2 = tSCL ∗ (4 ∗ tSEG2.2 + 2 ∗ tSEG2.1 + tSEG2.0 + 1) where tSEG1.3 – tSEG1.0 and tSEG2.2 – tSEG2.0 are bits in CANBTR. Synchronization Jump Width To compensate for phase shifts between clock oscillators of different bus controllers, any bus controller must re–synchronize on any relevant signal edge of the current transmission. The Synchronization Jump Width defines the maximum number of CAN System Clock cycles that a bit period may be shortened or lengthened by one re–synchronization, and is given by the following expression: /C0068tSJW = tSCL ∗ (2 ∗ SJW.1 + SJW.0 + 1) where SJW.1 and SJW.0 are bits in CANBTR. CANBTR: CAN Bus Timing Register /C0068Address: MMR base + 272h /C0068Access: Read, Write during reset mode only. Word access only. /C0068Reset value: 0000h CANBTR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CAN Command and Status Registers Two Modes in CAN Core Operation The CCB has two different modes of operation: Reset mode, and Operation mode. On hardware reset, the CAN core is in Reset mode, and the RR bit of CANCMR (CAN C om mand R egister) will be set. The User application would usually set up registers, etc., then put the CCB into Operation mode by clearing the RR bit. While in Operation mode, the following conditions will cause the RR bit to be set, putting the CCB back into Reset mode: /C0068Tx Buffer Underflow (TBUF) /C0068Bus Off /C0068Hardware reset /C0068Test mode (Refer to XA-C3 User Guide, Sections 2.2.2.1 and 2.7.1.2) CANCMR: CAN Command Register /C0068Address: MMR base + 270h /C0068Access: Read/Write, no R/M/W, Byte or Word Access. Hardware can set bit 0. /C0068Reset value: 01h CANCMR 7 6 5 4 3 2 1 0 RXP ST LO Reserved SLPEN OC1 Reserved RR RXP Rx Polarity, writable during reset mode only. 0 = non–inverted, 1 = inverted. ST Self test, disable TxACK LO Listen only Reserved Reserved bit. SLPEN CTL will go back to idle if no interrupt is generated. OC1 Output control for Tx pad. 0 = Push–Pull, 1 = Open Drain Reserved Reserved bit RR Reset Request. CANSTR: CAN Status Register /C0068Address: MMR base + 271h /C0068Access: Read only, no write, no R/M/W. Byte access OK. Hardware can set or clear bits 7 – 2. /C0068Reset value: 00h CANSTR 7 6 5 4 3 2 1 0 BS EP EW TS RS SLPOK – – BS Bus status EP Error passive EW Error warning TS Transmit status RS Receive status SLPOK CAN status: no CAN bus activity and no pending core interrupts

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IDs which share certain ID bit fields. and base address of an object’s message buffer is programmable.

MnMIDH – Message n Match ID High
MnMIDL – Message n Match ID Low
MnMSKH – Message n Mask High
MnMSKL – Message n Mask Low
MnCTL – Message n Control
MnBLR – Message n Buffer Location Register
MnBSZ – Message n Buffer Size
MnFCR – Message n Fragment Count Register

Object involves configuring some or all of its eight MMRs. objects. Details can be found in the sections that follow. Table 22. Message Object Register Functions for Tx and Rx benefit of the User application. position(s) in the appropriate MnMSKH or MnMSKL register. the one with the lowest object number. Standard and Extended CAN Frames. fields of all enabled receive Message Objects. always yields a Match with the Screener ID). to have matched the one with the lowest object number. compared to the Match ID and Mask fields of Object n.

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OBJECT N MATCH ID FIELD (MNMIDH AND MNMIDL) Mid28 – Mid18 Mid17 – Mid10 Mid9 – Mid2 Mid1 Mid0 MIDE OBJECT N MASK FIELD (MNMSKH AND MNMSKL) Msk28 – Msk18 Msk17 – Msk10 Msk9 – Msk2 Msk1 Msk0 SCREENER ID FIELD (ASSEMBLED FROM INCOMING BIT–STREAM) CAN ID.28 – CAN ID.18 Data Byte 1 [7:0] Data Byte 2 [7: 0] x x IDE NOTE: 1. For a Standard CAN Frame Message Object, only 27 bits plus IDE (11 bits of CAN ID + 2x8 bits + IDE ) from the incoming message are routed to the acceptance filter. The User is therefore required to set the Msk1 and Msk0 bits in the Mask field for that object (i.e., “don’t care”). The IDE bit is not Maskable. In many applications based on Standard CAN frames, either Data Byte 1, Data Byte 2, or both do not participate in Acceptance Filtering. Therefore, the User is required to Mask out the unused Data Byte(s). Screener ID Field for Extended CAN Frame The following table shows how the Screener ID field is assembled from the incoming bits of an Extended CAN Frame, and how it is compared to the Match ID and Mask fields of Object n. Note: The IDE bit is not Maskable. OBJECT N MATCH ID FIELD (MNMIDH AND MNMIDL) Mid28 – Mid18 Mid17 – Mid10 Mid9 – Mid2 Mid1 Mid0 MIDE OBJECT N MASK FIELD (MNMSKH AND MNMSKL) Msk28 – Msk18 Msk17 – Msk10 Msk9 – Msk2 Msk1 Msk0 SCREENER ID FIELD (ASSEMBLED FROM INCOMING BIT–STREAM) CAN ID.28 – CAN ID.0 IDE MnMIDH: Message n Match ID High Word /C0068Address: MMR base + n0h /C0068Access: Read, write. Word access only. /C0068Reset value: xxxxh MNMIDH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mid28 Mid27 Mid26 Mid25 Mid24 Mid23 Mid22 Mid21 Mid20 Mid19 Mid18 Mid17 Mid16 Mid15 Mid14 Mid13 MnMIDL: Message n Match ID Low Word /C0068Address: MMR base + n2h /C0068Access: Read, write. Word access only. /C0068Reset value: xxxxxxxxxxxxxx00b (unused bits are always read as ‘0’) MNMIDL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mid12 Mid11 Mid10 Mid9 Mid8 Mid7 Mid6 Mid5 Mid4 Mid3 Mid2 Mid1 Mid0 MIDE – – MnMSKH: Message n Mask High Word /C0068Address: MMR base + n4h /C0068Access: Read, write. Word access only. /C0068Reset value: xxxxh MNMSKH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Msk28 Msk27 Msk26 Msk25 Msk24 Msk23 Msk22 Msk21 Msk20 Msk19 Msk18 Msk17 Msk16 Msk15 Msk14 Msk13 NOTE: 1. Note: For transmit objects, the frame information is programmed in this register. MnMSKL: Message n Mask Low Word /C0068Address: MMR base + n6h /C0068Access: Read, write. Word access only. /C0068Reset value: xxxxxxxxxxxxx000b (unused bits are always read as ‘0’)

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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Msk12 Msk11 Msk10 Msk9 Msk8 Msk7 Msk6 Msk5 Msk4 Msk3 Msk2 Msk1 Msk0 – – – MnCTL: Message n Control Register /C0068Address: MMR base + n8h /C0068Access: Read, write. Byte or word access. /C0068Reset value: 00000xxxb (unused bits are always read as ‘0’) MNCTL 7 6 5 4 3 2 1 0 – – – OBJ_EN INT_EN Tx/Rx FRAG RTR_EN OBJ_EN Object Enable. Enables the Message Object for receive or transmit. 0 = disabled, 1 = enabled. INT_EN Message–Complete Interrupt Enable. Specifies whether or not a Tx or Rx Message–Complete for this object will cause the object’s Message–Complete Interrupt to be generated. 0 = disabled, 1 = enabled. Tx/Rx Transmit or Receive. Specifies whether this is a transmit or receive Message Object. 0 = transmit object, 1 = receive object. FRAG Fragmented Message Enable. Only relevant for receive Message Objects. Enables automatic assembly of Fragmented Rx messages. If disabled, messages received by this object are assumed to be single–frame, or will be assembled by User software. 0 = disabled, 1 = enabled. Note: Masking of the CAN Identifier field by User software, for the purpose of Message Object grouping, is disallowed for objects using hardware Fragmentation assembly. However, Masking of unused bit positions in the “screener”, such is mandatory in all cases. RTR_EN Enable Request To Transmit. 0 = the object is not enabled for RTR handling, 1 = the object is enabled for RTR handling. See section entitled RTR Handling, page 46. Message Storage When an incoming message frame has passed acceptance filtering, it will be automatically stored in data memory via DMA. Each message will be stored in its corresponding buffer area. On setup, the User is responsible for assigning a unique buffer location for each Message Object. This is specified in the object’s MnBLR register. The User is also required to set up the size of each buffer in the MnBSZ register. The XA-C3 provides a total of 512 bytes of on–chip message buffer RAM (XRAM) which may contain part or all of the CAN/CTL (transmit & receive) message buffer space. See Section entitled On-Chip Message Buffer RAM (XRAM) on page 55 for details. Note: The following discussion concerning message buffer registers applies to transmit message retrieval as well as receive message storage. MBXSR (applies to all objects) /C0068Address: MMR base + 291h /C0068Access: Read, write, byte or word /C0068Reset value: FFh MBXSR 7 6 5 4 3 2 1 0 a23 – a16 of all message buffer (and XRAM) base addresses All 32 message buffers must reside within the same 64K memory page. This page is specified by the contents of the MBXSR (Message Buffer and XRAM Segment Register) register. Also, the 512 byte on–chip message buffer RAM (XRAM) is always positioned within that same 64K page pointed to by MBXSR. Note: The XA-C3 brings out only 20 address lines to package pins. It can, therefore, only address 1MByte of off–chip data memory (a maximum of sixteen 64K segments). As a result, for the XA-C3, the four most significant bits of the MBSXR register must be set to ‘0000’ if External RAM is to be used for any portion of the message buffer space. MnBSZ: Message n Buffer Size Register /C0068Address: MMR base + nCh /C0068Access: Read–modify–write, byte or word access. /C0068Reset value: 00000xxxb MNBSZ 7 6 5 4 3 2 1 0 – – – – – BSZ.2 BSZ.1 BSZ.0 The size of an object’s message buffer is specified with the 3–bit field MnBSZ[2:0] as shown in Table 23.

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Table 23. Allowable Message Buffer Sizes /C0068Access: Read, write. Word access only. Objects must reside within the same 64Kbyte segment. Messages in CANopen on page 44. the message was non–Fragmented (single frame) or Fragmented. MnMIDL can change every time an incoming frame is accepted. accepted incoming frame (see Figure 38). Figure 38. Memory Image for Non–Fragmented Messages

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Figure 39. Retrieving the Screener ID for an Extended CAN Frame appropriate MnMIDH and MnMIDL registers. message has been received and stored. second data byte (Data Byte 2) and proceed to the end of the frame. Figure 40. Memory Image for Fragmented CTL Messages buffer, not offset ‘0’, and there will be no Byte Count written. Figure 41. Memory Image for CAN Frame Buffering (FRAG = 1 generating addresses starting from the bottom of the buffer again. action to prevent data loss. Fragmentation information contained in Data Byte 1 of each frame. the object’s MnCTL register.

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DMA, and then interrupt the CPU that a complete message has been received. Since Data Byte 1 of each frame contains the Fragmentation information, it will never be stored in the CTL message buffer, thus each frame will have up to seven bytes of data stored. After the entire message is received, the message buffer will contain all of the actual informational data bytes received (exclusive of Fragmentation information bytes) plus the Byte Count at location 00 which will contain the total number of informational data bytes stored. Fragmentation Error By looking at the Fragmentation information, the message handler can determine the first frame , the middle frames, the end frame of the message, and each sequence number. In the case of CANopen, there is no sequence number but rather a one bit field that toggles each frame. If a Fragmentation error occurs, the message handler will reset the byte count, address pointer, and generate an interrupt to the CPU. At this point the CTL message buffer is determined to be invalid. Fragmentation checking is disabled for all objects when CAN is the system protocol (Prtcl[1:0] = 00). Fragmentation error occurs only one way: 1. When the message handler receives a frame where the sequence number is NOT one greater than that of the previous frame. Or in the case of CANopen, the toggle bit has not toggled. Fragmented Messages in OSEK There are several important items that must be kept in mind with regard to hardware assembly of Fragmented OSEK messages. For a complete discussion, please see the XA-C3 User Manual. These items are summarized below: /C0068The OSEK FirstFrame cannot be treated as part of the Fragmented message, but must be handled as a completely separate, single–frame, non–Fragmented message. However, the FirstFrame may contain the first several bytes of User–data. /C0068For the object receiving the forthcoming message Fragments, the MnFCR register must be initialized by the User to point at an address other than the buffer base location. This can be byte offset ‘1’ or some other, more strategically chosen location. Since there will be no FirstFrame received for this object, there will be no write of 00h to the buffer base location, by DMA, at the beginning of the message. /C0068The Fragment Count Register (MnFCR) of the object receiving the message Fragments must be initialized by the User before enabling the object for receive. The initial value written to MnFCR must be identical to the SequenceNumber of the first ConsecutiveFrame that arrives (typically 0h). /C0068There is no “Last Frame” encoding for OSEK. Therefore, there will be neither an Rx Message Complete Status Flag, nor an interrupt, nor a Byte Count write associated with Rx Message Complete, at the conclusion of a Fragmented message. However, by carefully choosing the initial value for the MnBLR register, the User can arrange to get an Rx Buffer Full interrupt, and the associated Rx Buffer Full Byte Count write, instead. Fragmented Messages in CANopen In a CANopen system, the software will need to write to the object‘s Fragment Count Register (MnFCR) to initialize the toggle bit prior to receiving the first frame of any new message which requires hardware Fragmentation assembly. This bit will have to be initialized to the same state that will be received in the 1 st packet (typically 0). This bit will need to be initialized each time a new channel is established, even if none of the other parameters change (e.g., Match, Mask, buffer location, buffer size, etc.). Since the hardware cannot detect a message start, there can be no semaphore write to the bottom of the buffer space at the start of a new Fragmented message (for a discussion of the semaphore, see the section entitled Using the Semaphore Bits, SEM1 and SEM0 on page 46. This location must still be left free for the hardware to write the byte count into at the end of the message. This means that for CANopen Fragmented messages (only Fragmented) the software must initialize the address pointer to location ‘1’ of the designated receive buffer, not location ‘0’ as it does in DeviceNet. It also implies, of course, that the software loses the ability to check the semaphore to determine if message reconstruction is currently in progress. Essentially, the hardware will treat the first frame of a multi–frame CANopen message exactly the same as intermediate frames. Auto–Acknowledge in CANopen A Fragmented (Segmented) CANopen message may need to be acknowledged on a frame by frame basis. The XA-C3 provides hardware support for this process, with no CPU intervention. Of course the User may elect not to auto–acknowledge, or to implement the acknowledge function in software. Suppose Message Object n ( n = 0… 31) is enabled for receive, with the FRAG bit set. If the high level protocol is CANopen, as selected in the GCTL register, then the following steps must be taken to ensure that CANopen frames are automatically acknowledged: /C0068Set the AUTO_ACK bit in GCTL. /C0068Set up a transmit object sequential to the CANopen receive object, i.e., the object number set to be n+1. Set the FRAG bit for this object. /C0068It is important NOT to set the OBJ_EN bit for the transmit message. With the above setup, the XA-C3 will automatically generate a transmit frame upon successful reception of a CANopen frame. The User must setup the screener ID for the Tx frame in the M n+1MIDH and Mn+1MIDL registers, the RTR bit in Mn+1CNTL[0], and the DLC in Mn+1MSKH[3:0]. The User must also store the proper “Acknowledge Byte”, as defined by the protocol specification, in byte offset 0 of the Tx object’s message buffer. Bit position [4] is a don’t care, because the XA-C3 will automatically insert the toggle bit value from the incoming frame into the toggle bit position of the outgoing auto–acknowledge frame. The format for storing the Acknowledge Byte is shown below in Table 24 (subject to change without notice by the CiA).

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Table 24. Format for storing the CANopen Acknowledge byte /C0068Access: Read, write. Byte or word access. OSEK systems, the User must initialize this register. Auto_Ack Enables automatic acknowledge for CANopen. Pre–arbitration based on object number only. [Prtcl1 Prtcl0] Indicates CTL protocol of the system (if any). participate in the pre–arbitration process. setting or clearing the Pre_Arb bit in the GCTL register. Pre–Arbitration process gets reset and begins again. will be selected regardless of the pre–arbitration policy. This mode is selected by writing ‘0’ to the Pre_Arb bit in GCTL[2]. will compete for access with other transmitting nodes. to the Pre_Arb bit in GCTL[2].

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and transferring the data to the CAN core block for transmission. Message Storage on page 41 for a complete description. bus, reading from memory and writing to the CCB. MnMSKH register is shown in Figure 42. Figure 42. Format for Storing the Tx Frame Info in MnMSKH queued–up and enabled, and will be transmitted in order.

The software must setup an Rx object with the RTR bit in
An RTR frame is received when the CAN ID Matches that of the

enabled receive object whose RTR bit set to ‘1’.

If interrupt is enabled for that Message Object, an interrupt will

be generated upon the RTR message reception.

The software would usually have a transmit object available with
The software must setup a Tx object with the RTR bit in
The software sets the object enable bit (OBJ_EN) which will

enable the object to participate in pre–arbitration.

After the object wins pre–arbitration, an RTR frame will be sent

out with a ‘1’ in the RTR bit position.

At the end of a successful RTR transmission, the OBJ_EN bit will

be cleared. An interrupt could be generated if it is enabled.

It is possible for an incoming message, with CAN ID Matching

to read from and write to the buffer. detect and abandon the data read.

Being accessed by DMA (therefore not ready for CPU read)

the first byte of the receive buffer.

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At the start of a non–Fragmented message, prior to writing any data bytes, the DMA will begin by writing 01h into the first byte of the buffer (byte 0). Once the complete frame has been stored, the DMA will write the frame information into byte 0, with bits [5] and [4] always set to ‘1’. When the application wants to read from the object’s buffer, it can read byte 0 to determine if the DMA is currently updating the buffer. If byte 0 contains 01h, then the buffer is currently being updated. The application should not continue to read from the buffer. When the application starts to read from the buffer, it should set the semaphore to 10b. After reading is finished, the application should check the semaphore again. If it is still 10b, everything is OK. If, however, the semaphore becomes 01b or 11b after the CPU access is finished, it means that either the buffer is currently being accessed by DMA or has been accessed by DMA during the time the CPU was performing reads. In either case, the CPU should wait until the semaphore bits become 11b again, and reread. Use of the semaphore bits is not mandatory. However, their use may help to maintain data consistency. There are no dedicated semaphore bits for use with Fragmented messages. In the case of a Fragmented message (in DeviceNet only), the DMA will write a 00h in byte 0 of the object’s buffer. After the completion of a CTL message, the byte count (1 to 255) will be written to byte 0. Avoiding Data Corruption for Transmit Message Objects To avoid data corruption when transmitting messages, there are three possible approaches: 1. If the Message Complete interrupt is enabled for the transmit message, the User application would write to the transmit buffer after seeing the interrupt. Once the interrupt flag is set, it is known for sure that the pending message has already been transmitted. 2. Wait until OBJ_EN clears before writing to the buffer. This can be done by polling the OBJ_EN bit. 3. Clear OBJ_EN, while the object is still in pre–arbitration. In the first two cases, the pending message will be transmitted completely before the next message gets sent. For the third case, the message will not be transmitted. Instead, a message with new content will enter pre–arbitration. There is an additional mechanism that prevents corruption of a message that is being transmitted. If a transmission is ongoing for a Message Object, the XA-C3 hardware will prevent the User from clearing the OBJ_EN bit in the object’s MnCTL register. OSEK, DEVICENET, AND CANOPEN FRAMES OF INTEREST OSEK ConsecutiveFrame Data Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2 – DLC User Data 1 0 0 1 0 SN DeviceNet I/O Message Data Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2 – DLC User Data

1 Fragment Type Fragment Count

Fragment Type = 00 /C0068Fragment Count = 0 ... This is the First Fragment /C0068Fragment Count = 3F ... This is both the First and Last Fragment Fragment Type = 01 ... Middle Fragment Fragment Type = 10 ... Last Fragment CANopen Download Domain Segment Request Data Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2 – DLC User Data 1 ccs (User specified) t n (User specified) c CANopen Auto–Acknowledge Tx Response to Download Domain Segment Data Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2 – 8 reserved 1 scs (User specified) t not used, always 0000 CAN/CTL RELATED INTERRUPTS The CAN/CTL module will generate five different Event interrupts to the XA core: /C0068Rx Message Complete /C0068Tx Message Complete /C0068Rx Buffer Full /C0068Message Error /C0068Frame Error Rx and Tx Message Complete Interrupts In the following discussion (and elsewhere in the document) the term “message” applies to a complete transfer of information. For single–frame messages, the “message complete” condition occurs at the end of the frame. For multi–frame (Fragmented) messages, message complete occurs after the last frame is received and stored. Since the hardware doesn’t recognize or handle Fragmentation for transmit messages, the Tx message complete

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condition will always be generated at the end of each successfully transmitted frame. There is a control bit associated with each Message Object indicating whether a message complete condition should generate an interrupt, or just set a “message complete status flag” (for polling) without generating an interrupt. This is the INT_EN bit in the object’s MnCTL register, MnCTL[3]. There are two 16–bit MMRs, MCPLH and MCPLL, which contain the message complete status flags for all 32 objects. When a message complete (Tx or Rx) condition is detected for a particular Message Object, the corresponding bit in the MCPLH or MCPLL register will be set. This will occur regardless of whether the INT_EN bit is set for that object (in MnCTL[3]), or whether message complete status flags have already been set for any other objects. In addition to these 32 message complete status flags, there is a Tx Message Complete Interrupt Flag and an Rx Message Complete Interrupt Flag (CANINTFLG[1] and CANINTFLG[0] respectively), which will generate the actual Event interrupt requests to the XA core. When an end of message occurs, at the same moment that the message complete status flag is set, the appropriate Tx or Rx Message Complete Interrupt flip–flop will also be set provided that INT_EN = 1 for the object, and the interrupt is not already set and pending. The message complete interrupt flags should always be cleared using the 2–step process outlined below: 1. Message Complete Status Flags for all interrupt enabled objects of that type (Tx or Rx) should first be cleared by writing ‘1’ to their bit positions. 2. The Message Complete Interrupt Flag itself can now be cleared by writing ‘1’ to its bit position. Warning: Message Complete Interrupt Flags may be cleared before all Message Complete Status Flags for interrupt enabled objects of that type (Rx or Tx) are removed. However, the interrupt flag will not be reset to ‘1’ by hardware, unless a new message complete condition occurs for some other interrupt enabled object. Therefore, it is strongly recommended that Message Complete Interrupt Flags be cleared only after removing all Message Complete Status Flags for interrupt enabled objects of the same type, and at the end of the interrupt service routine. The newest addition is the M essage C omplete Info R egister (MCIR). MCIR[4:0] will encode the lowest object number of all objects whose INT_EN bits are set AND who currently have a message complete condition (objects whose message complete status flags are set). A ‘1’ in bit 5 means that one or more objects whose INT_EN bits are set have a message complete condition. A ‘0’ in bit 5 means that no objects whose INT_EN bits are set have a message complete condition. Bits 6 and 7 are unused. Rx Buffer Full Interrupt As successive frames of a Fragmented message are transferred by DMA into an object’s message buffer, it is possible to reach the end of the designated buffer space before the complete message has been received. When this occurs, it is necessary for the processor to intervene in order that the remainder of the message be stored without any loss of data. If the system protocol is DeviceNet, CANopen, or OSEK, then a message buffer is considered full when the number of bytes remaining in the buffer space, at the end of a complete frame, is less than seven. If the system protocol is CAN, i.e., [Prtcl1 Prtcl0] = 00, then Rx Buffer Full is defined as “less than 9 bytes remaining” after storage of a complete CAN frame. When the DMA pointer wraps around, it will be reset to offset ‘1’ in the buffer, not offset ‘0’, and there will be no Byte Count written. This condition could occur if the application has underestimated the message size, or deliberately established a small buffer to conserve memory. The condition will always occur with messages containing more than 255 data bytes (excluding Fragmentation information bytes), since the maximum message buffer size is 256 bytes. The following discussion only applies to frames which are not the last frame of a message (which also, necessarily, excludes non–Fragmented, single–frame messages). After DMA of the last data byte of the frame is completed, a check will be performed to determine if the current byte count is less than 7 bytes from the end of the assigned message buffer. If it is, then there is the potential for the next frame to overrun the buffer. We will consider this “less–than–seven–bytes–remaining” situation to be a buffer–full condition. When this condition is detected, the following will occur: /C0068The current byte count will be written into buffer location ‘0’ except in CAN systems. If [Prtcl1 Prtcl0] = 00, no byte count will be written. /C0068The address pointer will be initialized to location ‘1’ /C0068The Rx Buffer Full interrupt will be generated As subsequent frames are received, the data bytes will be stored, beginning at location ‘1’. The semaphore byte will not be written to again, since message assembly is still in progress. Once the end–of–message is finally received, the DMP will respond as usual, writing the byte–count to location ‘0’ and setting the Rx Message Complete Interrupt Flag. Note that the byte count will now reflect the number of bytes received since the buffer wrapped around, not the total number of bytes in the message. Software will have to calculate the difference. The software has two choices as to how to respond to this Rx Buffer Full interrupt: 1. Read the contents of the buffer, thereby freeing up space in the buffer for any remaining frames. 2. Reposition the buffer by modifying the address pointer. Note: The least significant bit of the address pointer will already be set to ‘1’, and must remain so. The bottom location must be reserved for the byte–count which will be written at the end of the message. If option 1 is selected, the software will retrieve the current byte count from the bottom of the buffer. It will then retrieve the designated number of data bytes from the buffer. Subsequent data received will be loaded into the buffer, beginning at location ‘1’. When the end–of–message occurs, the byte–count stored in location ‘0’ will indicate how many new bytes have been received which must now be retrieved. For option 2, subsequent bytes will actually be written into a different buffer space, elsewhere in memory. The processor can wait until the entire message is received before retrieving any data. At that time, the ‘0’ location of the 1 st buffer will indicate how many bytes are stored there, and likewise for the second buffer (or third or so on). Note that option 2 is far more efficient and can be implemented with very few instructions.

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bits wide, and for CANopen it is merely a single, toggling bit. no interrupt or error flag of any kind will be generated.

The six individual Frame Error Status Flags in the FESTR

be found in the following sections.

The FERIF bit can then be cleared by writing ‘1’ to the flag’s bit

Table 25. Error Codes for the Error Code Capture

00 Bit Error

01 Form Error

10 Stuff Error

11 Other Error

0 Tx Error, error occurred during

1 Rx Error, error occurred during

00011 Start of Frame

00010 ID28 … ID21

00110 ID20 … ID18

00100 SRR Bit

00101 IDE Bit

00111 ID17 … ID13

01111 ID12 … ID5

01110 ID4 … ID0

01100 RTR Bit

01101 Reserved Bit 1

01001 Reserved Bit 0

01011 Data Length Code

01010 Data Field

01000 CRC Sequence

11000 CRC Delimiter

11001 Acknowledge slot

11011 Acknowledge Delimiter

11010 End Of Frame

10010 Intermission (go buy popcorn)

10001 Active Error Flag

10110 Passive Error Flag

10011 Tolerate DOM bits

10111 Error Delimiter

11100 Overload Flag

ample time for the previous frame to be written to memory by DMA. pre–buffer bytes are full, subsequent incoming bits will be ignored.

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FESTR[5] will be set, generating a Frame Error interrupt, if enabled. The PBO status flag is cleared by writing ‘1’ to the flag’s bit position. executing a read of the Arbitration Lost Capture Register. ALCR[4:0]. ALCR[7:5] are reserved, and are always read as zeros. Table 26. Arbitration Lost Codes

0 Arbitration lost in ID28

1 Arbitration lost in ID27

2 Arbitration lost in ID26

10 Arbitration lost in ID18

11 Arbitration lost in SRR bit

12 Arbitration lost in IDE bit

13 Arbitration lost in ID17 (Extended Frame only)

30 Arbitration lost in ID0 (Extended Frame only)

31 Arbitration lost in RTR bit (Extended Frame only)

flag is cleared by writing ‘1’ to the flag’s bit position. until it is returned to Normal mode by clearing the RR bit. above, exactly as if it had been caused by bus errors. Frame Error interrupts if enabled.

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MERIF Message Error Interrupt Flag (cleared by writing ‘1’) RBFIF Rx Buffer Full Interrupt Flag (cleared by writing ‘1’) TMCIF Transmit Message Complete Interrupt Flag (should be cleared using the 2–step process described in the section entitled Rx and Tx Message Complete Interrupts on page 47). RMCIF Receive Message Complete Interrupt Flag (should be cleared using the 2–step process described in the section entitled Rx and Tx Message Complete Interrupts on page 47 FESTR (Frame Error Status Register) /C0068Address: MMR base + 22Ch /C0068Access: Read, byte or word /C0068Reset Value: 00h FESTR 7 6 5 4 3 2 1 0 – – PBO ARBLST BERR BOFF ERRW ERRP PBO Frame Error sub–type is Pre–Buffer Overflow (cleared by writing ‘1’) ARBLST Frame Error sub–type is Arbitration Lost (cleared by reading the ALCR register) BERR Frame Error sub–type is Bus Error (cleared by reading the ECCR register) BOFF Frame Error sub–type is Bus Off (cleared by writing ‘1’) ERRW Frame Error sub–type is Error Warning (cleared by writing ‘1’) ERRP Frame Error sub–type is Error Passive (cleared by writing ‘1’) FEENR (Frame Error Enable Register) /C0068Address: MMR base + 22Eh /C0068Access: Read, byte or word /C0068Reset Value: 00h FEENR 7 6 5 4 3 2 1 0 – – PBOE ARBLSTE BERRE BOFFE ERRWE ERRPE PBOE Pre–Buffer Overflow Enable (0 = disabled, 1 = enabled) ARBLSTE Arbitration Lost Enable (0 = disabled, 1 = enabled) BERRE Bus Error Enable (0 = disabled, 1 = enabled) BOFFE Bus Off Enable (0 = disabled, 1 = enabled) ERRWE Error Warning Enable (0 = disabled, 1 = enabled) ERRPE Error Passive Enable (0 = disabled, 1 = enabled) MCIR (Message Complete Info Register) /C0068Address: MMR base + 229h /C0068Access: Read, byte or word /C0068Reset Value: 00h MCIR 7 6 5 4 3 2 1 0 – – 1 or More Object Number 1orMore 0 = No objects whose INT_EN bits are set currently have a message complete condition. 1 = One or more objects whose INT_EN bits are set currently have a message complete condition. Object Number These 5 bits encode the lowest object number (0 – 31) of all objects whose INT_EN bits are set AND who currently have a message complete condition. If there are no such objects (1orMore = 0), these bits will be 00000b. MEIR (Message Error Info Register) /C0068Address: MMR base + 22Ah /C0068Access: Read, byte or word /C0068Reset Value: 00h MEIR 7 6 5 4 3 2 1 0 TBU FRAG RBF Object Number [TBU FRAG RBF] 001 = Most recent is Rx Buffer Full interrupt. 010 = Most recent is Fragmentation Error interrupt. 100 = Most recent is Tx Buffer Underflow interrupt. Object Number These 5 bits encode the object number (0 – 31) of the Message Object experiencing the most recent Message Error (Tx Buffer Underflow, Fragmentation Error, or Rx Buffer Full) condition. If more than one object are encountering Message Errors, only the most recent object number will be available. MCPLH (Message Complete Status Flags High) /C0068Address: MMR base + 226h /C0068Access: Read/Clear, byte or word /C0068Reset Value: 0000h

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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Obj31 Obj30 Obj29 Obj28 Obj27 Obj26 Obj25 Obj24 Obj23 Obj22 Obj21 Obj20 Obj19 Obj18 Obj17 Obj16 MCPLL (Message Complete Status Flags Low) /C0068Address: MMR base + 224h /C0068Access: Read/Clear, byte or word /C0068Reset Value: 0000h MCPLL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Obj15 Obj14 Obj13 Obj12 Obj11 Obj10 Obj9 Obj8 Obj7 Obj6 Obj5 Obj4 Obj3 Obj2 Obj1 Obj0 TxERC (Tx Error Counter) /C0068Address: MMR base + 274h /C0068Access: Read, write, R/M/W, byte or word /C0068Reset Value: 00h TXERC 7 6 5 4 3 2 1 0 TC 7 TC 6 TC 5 TC 4 TC 3 TC 2 TC 1 TC 0 The Tx Error Counter can only be written to when the CAN Core is in Reset mode. Hardware will preset the register to 128 when a Bus–Off condition occurs. See the section entitled Bus Off on page 50 for details. RxERC (Rx Error Counter) /C0068Address: MMR base + 275h /C0068Access: Read, write, R/M/W, byte or word /C0068Reset Value: 00h RXERC 7 6 5 4 3 2 1 0 RC 7 RC 6 RC 5 RC 4 RC 3 RC 2 RC 1 RC 0 The Rx Error Counter can only be written to when the CAN Core is in Reset mode. When a Bus–Off condition occurs, this register is cleared to 00h. EWLR (Error Warning Limit Register) /C0068Address: MMR base + 276h /C0068Access: Read, write, R/M/W, byte or word /C0068Reset Value: 96h EWLR 7 6 5 4 3 2 1 0 EWL 7 EWL 6 EWL 5 EWL 4 EWL 3 EWL 2 EWL 1 EWL 0 ECCR (Error Code Capture Register) /C0068Address: MMR base + 278h /C0068Access: Read, write, R/M/W, byte or word /C0068Reset Value: 00h ECCR 7 6 5 4 3 2 1 0 EC1 EC0 State The Error Code Capture Register contains detailed information about the most recent Bus Error. See Table 25 for details. The register must be read in order to be re–enabled for capturing the next error code, as well as to clear the BERR status flag. This register should be read before enabling the Bus Error interrupt. ALCR (Arbitration Lost Capture Register) /C0068Address: MMR base + 27Ah /C0068Access: Read, write, R/M/W, byte or word /C0068Reset Value: 00h ALCR 7 6 5 4 3 2 1 0 – – – Bit Number The ALCR latches the bit number in the CAN Identifier where the most recent Arbitration Lost occurred. See Table 26 for details. The register must be read in order to be reenabled for capturing the next arbitration lost code, as well as to clear the ARBLST status flag. This register should be read before enabling the Arbitration Lost interrupt.

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Table 27. SFR Interrupt Enable/Priority Bit Positions EMER Message Error interrupt enable. ECER Frame Error interrupt enable. ESPI SPI Port Interrupt enable. EBUFF Rx Buffer Full interrupt enable. External interrupt enable bits. PSPI SPI Port interrupt priority field. PCER Frame Error interrupt priority field. oscillator clocks (enough for several CAN frames to be transmitted). reduces power consumption by approximately 30 mA @ 32MHz. CAN/CTL blocks (including the CMI) at the top level. the termination of the Power–Down mode is actually complete.

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everything discussed in this section will be in the CCB. and the on–chip message buffer RAM (XRAM). /C0068Supports generic memory including SRAM, flash, and EPROM. /C0068Static 16-bit bus sizing. /C0068Arbitrates between CPU and DMA access. CAN/CTL related configuration and data. memory space for memory mapped registers (MMRs). always start at a 4K boundary. be automatically routed to the on–chip MMR bus. Figure 43. Formation of the MMR Base Address

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512 Bytes Object Registers

Figure 44. Detail of MMR space showing block of Message Object Registers reset, MRBE is cleared to 0. programmed by software, and must start at a 512–Byte boundary. Memory Mapped Registers MBXSR and XRAMB as shown in and . MBXSR[7:0]XRAMB[7:1] will be automatically routed to the XRAM. On reset, the XRAM is disabled. which must be below the 1M byte address limit.

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Figure 45. Formation of the XRAM base address, with object n message buffer mapped to off–chip data memory. Figure 46. Object n Message Buffer mapped into the on–chip XRAM.

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a15 – a9 of XRAM Base Address XRE XRE XRAM Enable bit, resets to ‘0’. 0 = XRAM disabled 1 = XRAM enabled MIF Control and Configuration Registers MIFCNTL (SFR) /C0068Address: SFR 495h MIFCNTL 7 6 5 4 3 2 1 0 WAITD Wait Disable 0 = Wail enabled 1 = Wait disabled BUSD External Access Disable 0 = enable 1 = disable MIFBTRL (Memory Interface Bus Timing Register Low, MMR) /C0068Address: MMR base + 292h /C0068Access: Read, write, byte or word /C0068Reset value: EFh MIFBTRL 7 6 5 4 3 2 1 0 WM1 WM0 ALEW – CR1 CR0 CRA1 CRA0 MIFBTRH (Memory Interface Bus Timing Register High, MMR) /C0068Address: MMR base + 294h /C0068Access: Read, write, byte or word /C0068Reset value: FFh MIFBTRH 7 6 5 4 3 2 1 0 DW1 DW0 DWA1 DWA0 DR1 DR0 DRA1 DRA0 Note: The two MMRs MIFBTRL and MIFBTRH are not to be confused with the two SFRs BTRL and BTRH, which control the operation of the BIU, not the MIF. In order for the MIF to function properly, the contents of BTRL and BTRH have to be set at a fixed configuration on reset, by User application software, similar to the treatment for the XA-SCC MIF. Bus Arbitration Bus arbitration is done on an “alternate” policy. After a DMA bus access, the CPU will get the bus if requested. After a CPU bus access, the DMA will get the bus if requested. A burst access from the CPU cannot be interrupted by a DMA bus access. SPI Port The on–chip SPI Port uses the following Memory Mapped Registers: SPICFG (MMR) /C0068Address: MMR base + 260h /C0068Access: Read, write, byte or word /C0068Reset value: 00h SPICFG 7 6 5 4 3 2 1 0 SPCP Rsvd Rsvd Rsvd SPC3 SPC2 SPC1 SPC0 SPCP SPICLK Polarity 0 = inverted SPICLK 1 = normal SPICLK Rsvd Reserved bits, only write zeros. SPC3 – SPC0 SPICLK timing SPICLK = (CClk) / 4 (SPICFG[3:0] + 1) SPIDATA (MMR) /C0068Address: MMR base + 262h /C0068Access: Read, write, byte or word /C0068Reset value: 00h SPIDATA 7 6 5 4 3 2 1 0 Data SPICS (MMR) /C0068Address: MMR base + 263h /C0068Access: Read, write, byte or word /C0068Reset value: 00h

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SPSTT SPB2 SPB1 SPB0 SPFG Rsvd Rsvd SPIDL SPSTT SPI Start 0 = Cycle finished, cleared by hardware and on reset 1 = Start SPB2 – SPB0 Number of SPI bits transceived = SPICFG[6:4] + 1 Rsvd Reserved bits, write only zeros SPIDL SPI TxD idle state 0 = idle low 1 = idle high

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LQFP44: plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm SOT389-1

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PLCC44: plastic leaded chip carrier; 44 leads SOT187-2

2000 Jan 25 61

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors

811 East Arques Avenue

P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381  Copyright Philips Electronics North America Corporation 2000 All rights reserved. Printed in U.S.A. Date of release: 01-00 Document order number: 9397 750 06805 /C0080 /C0115 /C0111/C0110/C0111 /C0115 Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Production Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Data sheet status [1] Please consult the most recently issued datasheet before initiating or completing a design.

Product Information

PXAC37 specifications and overview.

Summary

XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce 2000 Jan 25

Description

XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce 2000 Jan 25

Source title PXAC37 Datasheet(PDF) - NXP Semiconductors

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