PX3511A INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Dual MOSFET Drives for Sy nchronous Rectified Bridge
  • Adjustable Gate Voltage (5V to 12V) for Optimal Efficiency
  • 36V Internal Bootstrap Schottky Diode
  • Bootstrap Capacitor Ov ercharging Prevention
  • Supports High Switching Frequency (up to 2MHz) - 3A Sinking Current Capability - Fast Rise/Fall Times and Low Propagation Delays
  • Three-State PWM Input for Output Stage Shutdown
  • Three-State PWM Input Hysteresis for Applications With Power Sequencing Requirement
  • Pre-POR Overvoltage Protection
  • VCC Undervoltage Protection
  • Expandable Bottom Copper Pad for Enhanced Heat Sinking
  • Dual Flat No-Lead (DFN) Package - Near Chip-Scale Package Footprint; Improves PCB Efficiency and Thinner in Profile
  • Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

  • Core Regulators for Intel® and AMD® Microprocessors
  • High Current DC/DC Converters
  • High Frequency and High Efficiency VRM and VRD Related Literature
  • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)”
  • Technical Brief TB417 for Power Train Design, Layout Guidelines, and Feedback Compensation Design Data Sheet February 26, 2007 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

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Ordering Information

PART NUMBER PART MARKING TEMP . RANGE (°C) PACKAGE PKG. DWG. # PX3511ADAG (Note) PX3511 ADAG 0 to +85 8 Ld SOIC (Pb-free) M8.15 PX3511ADAG-R3 (Note) PX3511 ADAG 0 to +85 8 Ld SOIC (Pb-free) Tape and Reel M8.15 PX3511ADDG 11AD 0 to +85 10 Ld 3x3 DFN L10.3x3 PX3511ADDG-RA 11AD 0 to +85 10 Ld 3x3 DFN Tape and Reel L10.3x3 PX3511BDAG (Note) PX351 BDAG 0 to +85 8 Ld SOIC (Pb-free) M8.15 PX3511BDAG-R3 (Note) PX3511 BDAG 0 to +85 8 Ld SOIC (Pb-free) Tape and Reel M8.15 PX3511BDDG 11BD 0 to +85 10 Ld 3x3 DFN L10.3x3 PX3511BDDG-RA 11BD 0 to +85 10 Ld 3x3 DFN Tape and Reel L10.3x3 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Pinouts PX3511ACB, PX3511BCB (8 LD SOIC) TOP VIEW PX3511ACR, PX3511BCR (10 LD 3x3 DFN) TOP VIEW UGATE BOOT PWM GND PHASE PVCC VCC LGATE USB PPR CHG NTC or OVP USBP IUSB ICDL GND BAT or EN CRDLUGATE BOOT N/C GND PHASE PWM PVCC N/C VCC LGATE Block Diagram PX3511A AND PX3511B PVCC VCC PWM +5V 10K BOOT UGATE PHASE LGATE GND FOR DFN -DEVICES, THE PAD ON THE BOTTOM SIDE OFPAD THE PACKAGE MUST BE SOLDERED TO THE CIRCUIT’S GROUND. UVCC = VCC FOR PX3511A CONTROL LOGIC POR/ SHOOT- THROUGH PROTECTION Pre-POR OVP (LVCC) UVCC = PVCC FOR PX3511B UVCC PX3511A, PX3511B

3 FN6462.0 February 26, 2007 Typical Application - 4 Channel Converter Using ISL6595 and PX3511A Gate Drivers +12V +5V RTHERM +3.3V FROM µP I2C I/F BUS TO µP FAULT OUTPUTS PX3511 PX3511 PX3511 PX3511 Vout RTN ISL6595 V12_SEN GND OUT1 OUT2 ISEN1 OUT3 OUT4 ISEN2 OUT5 OUT6 ISEN3 OUT7 OUT8 ISEN4 OUT9 OUT10 ISEN5 OUT11 OUT12 ISEN6 TEMP_SEN CAL_CUR_EN CAL_CUR_SEN VSENP VSENN VDD VID4 VID3 VID2 VID1 VID0 VID5 LL0 LL1 OUTEN VCC_PWRGD RESET_N FAULT1 FAULT2 SDA SCL SADDR ISEN5 UGATE BOOT PWM GND PHASE PVCC VCC LGATE UGATE BOOT PWM GND PHASE PVCC VCC LGATE UGATE BOOT PWM GND PHASE PVCC VCC LGATE UGATE BOOT PWM GND PHASE PVCC VCC LGATE PX3511A, PX3511B

4 FN6462.0 February 26, 2007 Absolute Maximum Ratings Thermal Information VPHASE - 3.5V (<100ns Pulse Width, 2µJ) to VBOOT + 0.3V GND - 5V (<100ns Pulse Width, 2µJ) to VPVCC + 0.3V GND - 8V (<400ns, 20µJ) to 30V (<200ns, VBOOT-GND<36V) ESD Rating Recommended Operating Conditions Thermal Resistance θ JA (°C/W) θJC (°C/W) (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. 2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 3. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS VCC SUPPLY CURRENT Bias Supply Current I VCC PX3511A, fPWM = 300kHz, VVCC = 12V - 8 - mA PX3511B, fPWM = 300kHz, VVCC = 12V - 4.5 - mA IVCC PX3511A, fPWM = 1MHz, VVCC = 12V - 10.5 - mA PX3511B, fPWM = 1MHz, VVCC = 12V - 5 - mA Gate Drive Bias Current I PVCC PX3511A, fPWM = 300kHz, VPVCC = 12V - 4 - mA PX3511B, fPWM = 300kHz, VPVCC = 12V - 7.5 - mA IPVCC (Note 4) PX3511A, fPWM = 1MHz, VPVCC = 12V - 5 - mA PX3511B, fPWM = 1MHz, VPVCC = 12V - 8.5 - mA POWER-ON RESET AND ENABLE VCC Rising Threshold 9.35 9.8 10.0 V VCC Falling Threshold 7.35 7.6 8.0 V PWM INPUT (See Timing Diagram on Page 6) Input Current I PWM VPWM = 3.3V - 505 - µA VPWM = 0V - -460 - µA PWM Rising Threshold (Note 4) VCC = 12V - 1.70 - V PWM Falling Threshold (Note 4) VCC = 12V - 1.30 - V Typical Three-State Shutdown Window VCC = 12V 1.23 - 1.82 V Three-State Lower Gate Falling Threshold VCC = 12V - 1.18 - V Three-State Lower Gate Rising Threshold VCC = 12V - 0.76 - V Three-State Upper Gate Rising Threshold VCC = 12V - 2.36 - V PX3511A, PX3511B

5 FN6462.0 February 26, 2007 Three-State Upper Gate Falling Threshold VCC = 12V - 1.96 - V Shutdown Holdoff Time t TSSHD - 245 - ns UGATE Rise Time t RU VPVCC = 12V, 3nF Load, 10% to 90% - 26 - ns LGATE Rise Time t RL VPVCC = 12V, 3nF Load, 10% to 90% - 18 - ns UGATE Fall Time (Note 4) t FU VPVCC = 12V, 3nF Load, 90% to 10% - 18 - ns LGATE Fall Time (Note 4) t FL VPVCC = 12V, 3nF Load, 90% to 10% - 12 - ns UGATE Turn-On Propagation Delay (Note 4) t PDHU VPVCC = 12V, 3nF Load, Adaptive - 10 - ns LGATE Turn-On Propagation Delay (Note 4) t PDHL VPVCC = 12V, 3nF Load, Adaptive - 10 - ns UGATE Turn-Off Propagation Delay (Note 4) t PDLU VPVCC = 12V, 3nF Load - 10 - ns LGATE Turn-Off Propagation Delay (Note 4) t PDLL VPVCC = 12V, 3nF Load - 10 - ns LG/UG Three-State Propagation Delay (Note 4) t PDTS VPVCC = 12V, 3nF Load - 10 - ns OUTPUT Upper Drive Source Current (Note 4) I U_SOURCE VPVCC = 12V, 3nF Load - 1.25 - A Upper Drive Source Impedance R U_SOURCE 150mA Source Current 1.4 2.0 3.0 Ω Upper Drive Sink Current (Note 4) I U_SINK VPVCC = 12V, 3nF Load - 2 - A Upper Drive Sink Impedance R U_SINK 150mA Sink Current 0.9 1.65 3.0 Ω Lower Drive Source Current (Note 4) I L_SOURCE VPVCC = 12V, 3nF Load - 2 - A Lower Drive Source Impedance R L_SOURCE 150mA Source Current 0.85 1.3 2.2 Ω Lower Drive Sink Current (Note 4) I L_SINK VPVCC = 12V, 3nF Load - 3 - A Lower Drive Sink Impedance R L_SINK 150mA Sink Current 0.60 0.94 1.35 Ω NOTE: 4. Guaranteed by design. Not 100% tested in production. Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Functional Pin Description PACKAGE PIN # PIN SYMBOL FUNCTIONSOIC DFN 1 1 UGATE Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET. 2 2 BOOT Floating bootstrap supply pin for the upper gate driv e. Connect the bootstrap capacitor between this pin and the PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Internal Bootstrap Device section under DESCRIPTION for guidance in choosing the capacitor value. - 3,8 N/C No Connection. 3 4 PWM The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see the three-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM output of the controller. 4 5 GND Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver. 5 6 LGATE Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET. 6 7 VCC Connect this pin to a +12V bias supply. Place a high quality low ESR ceramic capacitor from this pin to GND. 7 9 PVCC This pin supplies power to both upper and lower gate drives in PX3511B; only the lower gate drive in PX3511A. Its operating range is +5V to 12V. Place a high quality low ESR ceramic capacitor from this pin to GND. 8 10 PHASE Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides a return path for the upper gate drive. 9 11 PAD Connect this pad to the power ground plane (GND) via thermally enhanced connection. PX3511A, PX3511B

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Description

Designed for versatility and speed, the PX3511A and PX3511B MOSFET drivers control both high-side and low- side N-Channel FETs of a half-bridge power train from one externally provided PWM signal. Prior to VCC exceeding its POR level, the Pre-POR overvoltage protection function is activated during initial startup; the upper gate (UGATE) is held low and the lower gate (LGATE), controlled by the Pre-POR overvoltage protection circuits, is connected to the PHASE. Once the VCC voltage surpasses the VCC Rising Threshold (See Electrical Specifications), the PWM signal takes control of gate transitions. A rising edge on PWM initiates the turn-off of the lower MOSFET (see Timing Diagram). After a short propagation delay [t PDLL], the lower gate begins to fall. Typical fall times [tFL] are provided in the Electrical Specifications section. Adaptive shoot-through circuitry monitors the LGATE voltage and determines the upper gate delay time [t PDHU]. This prevents both the lower and upper MOSFETs from conducting simultaneously. Once this delay period is complete, the upper gate drive begins to rise [t RU] and the upper MOSFET turns on. A falling transition on PWM results in the turn-off of the upper MOSFET and the turn-on of the lower MOSFET. A short propagation delay [t PDLU] is encountered before the upper gate begins to fall [tFU]. Again, the adaptive shoot-through circuitry determines the lower gate delay time, tPDHL. The PHASE voltage and the UGATE voltage are monitored, and the lower gate is allowed to rise after PHASE drops below a level or the voltage of UGATE to PHASE reaches a level depending upon the current direction (See next section for details). The lower gate then rises [t RL], turning on the lower MOSFET. Adaptive Zero Shoot-Through Deadtime Control These drivers incorporate an adaptive deadtime control technique to minimize deadtime, resulting in high efficiency from the reduced freewheeling time of the lower MOSFETs’ body-diode conduction, and to prevent the upper and lower MOSFETs from conducting simultaneously. This is accomplished by ensuring either rising gate turns on its MOSFET with minimum and sufficient delay after the other has turned off. During turn-off of the lower MOSFET, the LGATE voltage is monitored until it drops below 1.75V, at which time the UGATE is released to rise after 20ns of propagation delay. Once the PHASE is high, the adaptive shoot-through circuitry monitors the PHASE and UGATE voltages during a PWM falling edge and the subsequent UGATE turn-off. If either the UGATE falls to less than 1.75V above the PHASE or the PHASE falls to less than +0.8V, the LGATE is released to turn on. Three-State PWM Input A unique feature of these drivers and other Intersil drivers is the addition of a shutdown window to the PWM input. If the PWM signal enters and remains within the shutdown window for a set holdoff time, the driver outputs are disabled and both MOSFET gates are pulled and held low. The shutdown state is removed when the PWM signal moves outside the shutdown window. Otherwise, the PWM rising and falling thresholds outlined in the ELECTRICAL SPECIFICATIONS determine when the lower and upper gates are enabled. This feature helps prevent a negative transient on the output voltage when the output is shut down, eliminating the Schottky diode that is used in some systems for protecting the load from reversed output voltage events. In addition, more than 400mV hysteresis also incorporates into the three-state shutdown window to eliminate PWM PWM UGATE LGATE tFL tPDHU tPDLL tRL tTSSHD tPDTS tPDTS 1.18V<PWM<2.36V 0.76V<PWM<1.96V tFUtRU tPDLU tPDHL tTSSHD FIGURE 1. TIMING DIAGRAM

bias supplies of the driver and PWM controller are required. During initial startup, the VCC voltage rise is monitored. Both drivers feature an internal bootstrap schottky diode. stress on the boot to phase pins. allowable droop in the rail of the upper gate drive. that a bootstrap capacitance of at least 0.267μF is required. choosing the gate drive voltage for efficiency optimization. PX3511B ties the upper and lower drive rails together. both gate drive rail voltages simultaneously. FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE

9 FN6462.0 February 26, 2007 PX3511A, PX3511B Dual Flat No-Lead Plastic Package (DFN) D E A B 0.10 MC e 0.415 C SECTION "C-C" NX (b) (A1) C0.15 0.15 B NX L REF. (Nd-1)Xe A C (DATUM B) D2/2 E2/2 TOP VIEW BOTTOM VIEW INDEX AREA AB NX k INDEX AREA (DATUM A) N-1N NX b NX b NX L0.200 C A SEATING PLANE 0.08 C A3SIDE VIEW 0.10 C L10.3x3

10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE

A 0.80 0.90 1.00 - A1 - - 0.05 - A3 0.20 REF - b 0.18 0.23 0.28 5,8 D 3.00 BSC - D2 1.95 2.00 2.05 7,8 E 3.00 BSC - E2 1.55 1.60 1.65 7,8 e 0.50 BSC - k0 . 2 5 - - - L0 . 3 0 0.35 0.40 8 N1 0 2 Nd 5 3 Rev. 3 6/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd refers to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are prov ided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. FOR ODD TERMINAL/SIDE CL e TERMINAL TIP L CC

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6462.0 February 26, 2007 PX3511A, PX3511B Small Outline Plastic Packages (SOIC) INDEX AREA E D N 123 -B- 0.25(0.010) C AM BS e -A- L B M -C- A SEATING PLANE 0.10(0.004) h x 45° C H 0.25(0.010) BM M α NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETE R. Converted inch dimensions are not necessarily exact. M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 e 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N8 8 7 α 0° 8° 0° 8° - Rev. 1 6/05