PWD13F60 STMICROELECTRONICS | Alldatasheet

Document overview

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  • PDF pages: 26

Technical content

Datasheet sections

  • 1 Block diagram
  • 2 Pin connection diagram and d escription
  • 3 Electrical data
  • 3.1 Absolute maximum ratings
  • 3.2 Recommended operating conditions
  • 3.3 Thermal data
  • 4 Electrical characteristics
  • 4.1 Driver
  • 4.2 Power MOSFET
  • 5 Device characterization values
  • 6 Functional description
  • 6.1 Logic inputs
  • 6.2 Bootstrap structure
  • 6.3 V CC supply pins and UVLO function
  • 7 Typical application diagram
  • 8 Package information
  • 9 Suggested footprint
  • 10 Ordering information
  • 11 Revision history

Features

 Power system-in-package integrating gate drivers and high-voltage power MOSFETs – Low R DS(on) = 320 mΩ –B V DSS = 600 V  Suitable for operating as – Full bridge – Dual independent half bridges  Wide driver supply voltage down to 6.5 V  UVLO protection on supply voltage  3.3 V to 15 V compatible inputs with hysteresis and pull-down  Interlocking function to prevent cross conduction  Internal bootstrap diode  Outputs in phase with inputs  Very compact and simplified layout  Flexible, easy and fast design

Applications

 Motor drivers for industrial and home appliances  Factory automation  Fans and pumps  HID, ballasts  Power supply units  DC-DC and DC-AC converters

Description

The PWD13F60 is a high-density power driver integrating gate drivers and four N-channel power MOSFETs in dual half bridge configuration. The integrated power MOSFETs have low R DS(on) of 320 mΩ and 600 V drain-source breakdown voltage, while the embedded gate drivers high side can be easily supplied by the integrated bootstrap diode. The high integration of the device allows to efficiently drive loads in a tiny space. The PWD13F60 device accepts a supply voltage CC) extending over a wide range and is protected by means of low-voltage UVLO detection on the supply voltage. The input pins extended range allows an easy interfacing with microcontrollers, DSP units or Hall effect sensors. The device is available in a compact VFQFPN package. VFQFPN 10 x 13 x 1.0 mm

1 Block diagram

Figure 1. Block diagram

2 Pin connection diagram and description

Figure 2. Pin connection (top view)

Table 1. Pin description

5 BOOT1 Power supply Gate driver 1 high side supply voltage

19 BOOT2 Power supply Gate driver 2 high side supply voltage

9 VCC1 Power supply Gate driver 1 supply voltage

23 VCC2 Power supply Gate driver 2 supply voltage

6 LIN1 Logic input Logic input of low side MOSFET 1

8 HIN1 Logic input Logic input of high side MOSFET 1

21 LIN2 Logic input Logic input of low side MOSFET 2

22 HIN2 Logic input Logic input of high side MOSFET 2

3 Electrical data

3.1 Absolute maximum ratings

Table 2. Absolute maximum ratings

  1. T CB is temperature of case bottom pad.
  2. Characterized, not tested in production.
  3. The value specified by the design factor, pulse duration limited by max. junction temperature and SOA.
  4. Value calculated basing on thermal resistance, power uniformly distributed over the four power MOSFETs,
  5. The device mounted on a FR4 2s2p board as JESD51-5/7.
  6. Actual applicative board max. diss ipation could be higher or lower depending on the layout and cooling

3.2 Recommended operating conditions

3.3 Thermal data

Table 3. Recommended operating conditions

  1. The integrated gate driver can work with V CC as low as VCC_thON. Higher supply voltage allows decreasing

Table 4. Thermal data

  1. The junction to ambient thermal resistance is obtained simulating the device mounted on a FR4 2s2p

board as the JESD51-5/7 with power dissipation uniformly distributed over the four power MOSFETs.

4 Electrical characteristics

4.1 Driver

VCCx = 15 V; TJ = 25 °C, unless otherwise specified. Table 5. Driver section electrical characteristics

  1. R BD(on) is tested in the following way:

Where: Ia is the BOOT pin current when VBOOT = VBOOTa; Ib is the BOOT pin current when VBOOT = VBOOTb.

4.2 Power MOSFET

VCCx = 15 V; TJ = 25 °C, unless otherwise specified. Table 6. Power MOSFET electrical characteristics

  1. Tested at the wafer level before packaging.

5 Device characterization values

in this section represent typical values based on characterization and simulation results. Table 7. Power MOSFET Table 8. Inductive load switching characteristics

  1. t (on) and t(off) include the propagation delay time of the internal driver.
  2. t C(on) and tC(off) are the switching times of the MOSFET itself under the internally given gate driving conditions.

Figure 3. Switching time and losses definition

Figure 12. Static source-drain diode forward characteristics

6 Functional description

6.1 Logic inputs

LS MOSFETs within the same channel (see Table 9). low level and the corresponding MOSFETs are turned off. Table 9. Truth table

6.2 Bootstrap structure

normally accomplished by a high-voltage fast recovery diode (see Figure 13 a). the best performance when the low side driver is on. integrated structure is possible. Figure 13. Bootstrap structure

6.3 V CC supply pins and UVLO function

MOSFETs flow through these pins. connected together at the power supply in the final application. CC_thON voltage. A VCC_hys hysteresis is provided for the noise rejection purpose. occurs on a single rail, only the related half bridge MOSFETs are turned off.

7 Typical application diagram

Figure 14. Typical application

8 Package information

specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. The package outline CAD file is available upon request. Figure 15. VFQFPN 10 x 13 x 1.0 mm package outline (drawing top and side view)

Figure 16. VFQFPN 10 x 13 x 1.0 mm package outline (bottom view drawing)

Table 10. VFQFPN 10 x 13 x 1.0 mm package mechanical data

  1. N is the total number of terminals.

Note: Dimensioning and tolerances conform to the ASME Y14.5-1994. All dimensions are in millimeters. identifier for the correct orientation. A variable pitch is applied on leads. Please refer to Figure 17 for the detailed lead position. The leads size is comprehensive of the thickness of the leads finishing material. Dimensions do not include the mold protrusion, not to exceed 0.15 mm. Package outline exclusive of metal burr dimensions. Figure 17. VFQFPN 10 x 13 x 1.0 mm package dimensions - pin position drawing

Figure 18. VFQFPN 10 x 13 x 1.0 mm package dimensions – large pads details

9 Suggested footprint

for the largest variety of PCBs. layout example is available with the PWD13F60 evaluation board. As for the package outline, also the suggested footprint CAD file is available upon request. Figure 19. Suggested footprint (top view drawing)

Figure 20. Suggested footprint detailed dimensions (top view drawing)

Table 11. Device summary Table 12. Document revision history 20-Jul-2017 1 Initial release. page 7, Table 5 on page 8, and Table 6 on page 9. Minor modifications throughout document.