ULN2002A_V02 TI | Alldatasheet
Document overview
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Technical content
ULN200x, ULQ200x High-Voltage, High-Current Darlington Transistor Arrays
1 Features
- 500mA-rated collector current (single output)
- High-voltage outputs: 50V
- Output clamp diodes
- Inputs compatible with various types of logic
- Relay-driver applications
2 Applications
- Relay Drivers
- Stepper and DC Brushed Motor Drivers
- Lamp Drivers
- Display Drivers (LED and Gas Discharge)
- Line Drivers
- Logic Buffers
3 Description
The ULx200xA devices are high-voltage, high-current Darlington transistor arrays. Each consists of seven NPN Darlington pairs that feature high-voltage outputs with common-cathode clamp diodes for switching inductive loads. The collector-current rating of a single Darlington pair is 500mA. The Darlington pairs can be paralleled for higher current capability. Applications include relay drivers, hammer drivers, lamp drivers, display drivers (LED and gas discharge), line drivers, and logic buffers. For 100V (otherwise interchangeable) versions of the ULx2003A devices, see the SLRS023 data sheet for the SN75468 and SN75469 devices. The ULN2002A device is designed specifically for use with 14V to 25V PMOS devices. Each input of this device has a Zener diode and resistor in series to control the input current to a safe limit. The ULx2003A devices have a 2.7k Ω series base resistor for each Darlington pair for operation directly with TTL or 5V CMOS devices. The ULx2004A devices have a 10.5k Ω series base resistor to allow operation directly from CMOS devices that use supply voltages of 6V to 15V. The required input current of the ULx2004A device is below that of the ULx2003A devices, and the required voltage is less than that required by the ULN2002A device.
Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2) ULN200xAD SOIC (16) 9.90mm × 3.91mm ULN200xAN PDIP (16) 19.30mm × 6.35mm ULN200xANS SOP (16) 10.30mm × 5.30mm ULN200xAPW TSSOP (16) 5.00mm × 4.40mm ULN2003ADYY SOT (16) 4.20mm × 2.00mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) The package size (length × width) is a nominal value and includes pins, where applicable. COM Simplified Block Diagram ULN2002A, ULN2003A, ULN2003AI ULQ2003A, ULN2004A, ULQ2004A SLRS027S – DECEMBER 1976 – REVISED JUNE 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
5.6 Electrical Characteristics: ULN2003A and
5.9 Electrical Characteristics: ULQ2003A and
5.10 Switching Characteristics: ULN2002A,
5.13 Switching Characteristics: ULQ2003A,
11 Mechanical, Packaging, and Orderable
ULN2002A, ULN2003A, ULN2003AI ULQ2003A, ULN2004A, ULQ2004A SLRS027S – DECEMBER 1976 – REVISED JUNE 2024 www.ti.com
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4 Pin Configuration and Functions
Figure 4-1. D, N, NS, and PW Package 16-Pin SOIC, PDIP, SO, and TSSOP Top View Table 4-1. Pin Functions PIN I/O(1) DESCRIPTION NAME NO. 1B 1 I Channel 1 through 7 Darlington base input 2B 2 3B 3 4B 4 5B 5 6B 6 7B 7 1C 16 O Channel 1 through 7 Darlington collector output 2C 15 3C 14 4C 13 5C 12 6C 11 7C 10 COM 9 — Common cathode node for flyback diodes (required for inductive loads) E 8 — Common emitter shared by all channels (typically tied to ground) (1) I = Input, O = Output www.ti.com ULN2002A, ULN2003A, ULN2003AI ULQ2003A, ULN2004A, ULQ2004A SLRS027S – DECEMBER 1976 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: ULN2002A ULN2003A ULN2003AI ULQ2003A ULN2004A ULQ2004A
5 Specifications
5.1 Absolute Maximum Ratings
at 25°C free-air temperature (unless otherwise noted)(1) MIN MAX UNIT VCC Collector-emitter voltage 50 V Clamp diode reverse voltage(2) 50 V VI Input voltage(2) 30 V Peak collector current, See Figure 5-4 and Figure 5-5 500 mA IOK Output clamp current 500 mA Total emitter-terminal current –2.5 A TA Operating free-air temperature range ULN200xA –40 70 ULN200xAI –40 105 ULQ200xA –40 85 ULQ200xAT –40 105 TJ Operating virtual junction temperature 150 °C Lead temperature for 1.6 mm (1/16 inch) from case for 10 seconds 260 °C Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to the emitter/substrate terminal E, unless otherwise noted.
5.2 ESD Ratings
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
5.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Collector-emitter voltage (non-V devices) 0 50 V TJ Junction temperature –40 125 °C
5.4 Thermal Information
THERMAL METRIC(1) ULx200x UNITD (SOIC) N (PDIP) NS (SO) PW (TSSOP) DYY (SOT)
16 PINS 16 PINS 16 PINS 16 PINS 16 PINS
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. ULN2002A, ULN2003A, ULN2003AI ULQ2003A, ULN2004A, ULQ2004A SLRS027S – DECEMBER 1976 – REVISED JUNE 2024 www.ti.com
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5.5 Electrical Characteristics: ULN2002A
TA = 25°C PARAMETER TEST FIGURE TEST CONDITIONS ULN2002A UNIT MIN TYP MAX VI(on) ON-state input voltage Figure 6-6 VCE = 2 V, IC = 300 mA 13 V VOH High-level output voltage after switching Figure 6-10 VS = 50 V, IO = 300 mA VS – 20 mV VCE(sat) Collector-emitter saturation voltage Figure 6-4 II = 250 μA, IC = 100 mA 0.9 1.1 VII = 350 μA, IC = 200 mA 1 1.3 II = 500 μA, IC = 350 mA 1.2 1.6 VF Clamp forward voltage Figure 6-7 IF = 350 mA 1.7 2 V ICEX Collector cutoff current Figure 6-1 VCE = 50 V, II = 0 50 μA Figure 6-2 VCE = 50 V, TA = 70°C II = 0 100 VI = 6 V 500 II(off) OFF-state input current Figure 6-2 VCE = 50 V, IC = 500 μA 50 65 μA II Input current Figure 6-3 VI = 17 V 0.82 1.25 mA IR Clamp reverse current Figure 6-6 VR = 50 V TA = 70°C 100 μA VR = 50 V 50 Ci Input capacitance VI = 0, f = 1 MHz 25 pF
5.6 Electrical Characteristics: ULN2003A and ULN2004A
TA = 25°C PARAMETER TEST FIGURE TEST CONDITIONS ULN2003A ULN2004A UNIT MIN TYP MAX MIN TYP MAX VI(on) ON-state input voltage Figure 6-6 VCE = 2 V IC = 125 mA 5 V IC = 200 mA 2.4 6 IC = 250 mA 2.7 IC = 275 mA 7 IC = 300 mA 3 IC = 350 mA 8 VOH High-level output voltage after switching Figure 6-10 VS = 50 V, IO = 300 mA VS – 20 VS – 20 mV VCE(sat) Collector-emitter saturation voltage Figure 6-5 II = 250 μA, IC = 100 mA 0.9 1.1 0.9 1.1 VII = 350 μA, IC = 200 mA 1 1.3 1 1.3 II = 500 μA, IC = 350 mA 1.2 1.6 1.2 1.6 ICEX Collector cutoff current Figure 6-1 VCE = 50 V, II = 0 50 50 μA Figure 6-2 VCE = 50 V, TA = 70°C II = 0 100 100 VI = 6 V 500 VF Clamp forward voltage Figure 6-8 IF = 350 mA 1.7 2 1.7 2 V II(off) Off-state input current Figure 6-3 VCE = 50 V, TA = 70°C, IC = 500 μA 50 65 50 65 μA II Input current Figure 6-4 VI = 3.85 V 0.93 1.35 mAVI = 5 V 0.35 0.5 VI = 12 V 1 1.45 IR Clamp reverse current Figure 6-7 VR = 50 V 50 50 μA VR = 50 V TA = 70°C 100 100 www.ti.com ULN2002A, ULN2003A, ULN2003AI ULQ2003A, ULN2004A, ULQ2004A SLRS027S – DECEMBER 1976 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: ULN2002A ULN2003A ULN2003AI ULQ2003A ULN2004A ULQ2004A
5.6 Electrical Characteristics: ULN2003A and ULN2004A (continued)
TA = 25°C PARAMETER TEST FIGURE TEST CONDITIONS ULN2003A ULN2004A UNIT MIN TYP MAX MIN TYP MAX Ci Input capacitance VI = 0, f = 1 MHz 15 25 15 25 pF
5.7 Electrical Characteristics: ULN2003AI
TA = 25°C PARAMETER TEST FIGURE TEST CONDITIONS ULN2003AI UNIT MIN TYP MAX VI(on) ON-state input voltage Figure 6-6 VCE = 2 V IC = 200 mA 2.4 VIC = 250 mA 2.7 IC = 300 mA 3 VOH High-level output voltage after switching Figure 6-10 VS = 50 V, IO = 300 mA VS – 50 mV VCE(sat) Collector-emitter saturation voltage Figure 6-5 II = 250 μA, IC = 100 mA 0.9 1.1 VII = 350 μA, IC = 200 mA 1 1.3 II = 500 μA, IC = 350 mA 1.2 1.6 ICEX Collector cutoff current Figure 6-1 VCE = 50 V, II = 0 50 μA VF Clamp forward voltage Figure 6-8 IF = 350 mA 1.7 2 V II(off) OFF-state input current Figure 6-3 VCE = 50 V, IC = 500 μA 50 65 μA II Input current Figure 6-4 VI = 3.85 V 0.93 1.35 mA IR Clamp reverse current Figure 6-7 VR = 50 V 50 μA Ci Input capacitance VI = 0, f = 1 MHz 15 25 pF
5.8 Electrical Characteristics: ULN2003AI
TA = –40°C to 105°C PARAMETER TEST FIGURE TEST CONDITIONS ULN2003AI UNIT MIN TYP MAX VI(on) ON-state input voltage Figure 6-6 VCE = 2 V IC = 200 mA 2.7 VIC = 250 mA 2.9 IC = 300 mA 3 VOH High-level output voltage after switching Figure 6-10 VS = 50 V, IO = 300 mA VS – 50 mV VCE(sat) Collector-emitter saturation voltage Figure 6-5 II = 250 μA, IC = 100 mA 0.9 1.2 VII = 350 μA, IC = 200 mA 1 1.4 II = 500 μA, IC = 350 mA 1.2 1.7 ICEX Collector cutoff current Figure 6-1 VCE = 50 V, II = 0 100 μA VF Clamp forward voltage Figure 6-8 IF = 350 mA 1.7 2.2 V II(off) OFF-state input current Figure 6-3 VCE = 50 V, IC = 500 μA 30 65 μA II Input current Figure 6-4 VI = 3.85 V 0.93 1.35 mA IR Clamp reverse current Figure 6-7 VR = 50 V 100 μA Ci Input capacitance VI = 0, f = 1 MHz 15 25 pF ULN2002A, ULN2003A, ULN2003AI ULQ2003A, ULN2004A, ULQ2004A SLRS027S – DECEMBER 1976 – REVISED JUNE 2024 www.ti.com
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5.9 Electrical Characteristics: ULQ2003A and ULQ2004A
over recommended operating conditions (unless otherwise noted) PARAMETER TEST FIGURE TEST CONDITIONS ULQ2003A ULQ2004A UNIT MIN TYP MAX MIN TYP MAX VI(on) ON-state input voltage Figure 6-6 VCE = 2 V IC = 125 mA 5 V IC = 200 mA 2.7 6 IC = 250 mA 2.9 IC = 275 mA 7 IC = 300 mA 3 IC = 350 mA 8 VOH High-level output voltage after switching Figure 6-10 VS = 50 V, IO = 300 mA VS – 50 VS – 50 mV VCE(sat) Collector-emitter saturation voltage Figure 6-5 II = 250 μA, IC = 100 mA 0.9 1.2 0.9 1.1 VII = 350 μA, IC = 200 mA 1 1.4 1 1.3 II = 500 μA, IC = 350 mA 1.2 1.7 1.2 1.6 ICEX Collector cutoff current Figure 6-1 VCE = 50 V, II = 0 100 50 μA Figure 6-2 VCE = 50 V, TA = 70°C II = 0 100 VI = 6 V 500 VF Clamp forward voltage Figure 6-8 IF = 350 mA 1.7 2.3 1.7 2 V II(off) OFF-state input current Figure 6-3 VCE = 50 V, TA = 70°C, IC = 500 μA 65 50 65 μA II Input current Figure 6-4 VI = 3.85 V 0.93 1.35 mAVI = 5 V 0.35 0.5 VI = 12 V 1 1.45 IR Clamp reverse current Figure 6-7 VR = 50 V TA = 25°C 100 50 μA VR = 50 V 100 100 Ci Input capacitance VI = 0, f = 1 MHz 15 25 15 25 pF
5.10 Switching Characteristics: ULN2002A, ULN2003A, ULN2004A
TA = 25°C PARAMETER TEST CONDITIONS ULN2002A, ULN2003A, ULN2004A UNIT MIN TYP MAX tPLH Propagation delay time, low- to high-level output See Figure 6-9 0.25 1 μs tPHL Propagation delay time, high- to low-level output See Figure 6-9 0.25 1 μs
5.11 Switching Characteristics: ULN2003AI
TA = 25°C PARAMETER TEST CONDITIONS ULN2003AI UNIT MIN TYP MAX tPLH Propagation delay time, low- to high-level output See Figure 6-9 0.25 1 μs tPHL Propagation delay time, high- to low-level output See Figure 6-9 0.25 1 μs www.ti.com ULN2002A, ULN2003A, ULN2003AI ULQ2003A, ULN2004A, ULQ2004A SLRS027S – DECEMBER 1976 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: ULN2002A ULN2003A ULN2003AI ULQ2003A ULN2004A ULQ2004A
5.12 Switching Characteristics: ULN2003AI
TA = –40°C to 105°C PARAMETER TEST CONDITIONS ULN2003AI UNIT MIN TYP MAX tPLH Propagation delay time, low- to high-level output See Figure 6-9 1 10 μs tPHL Propagation delay time, high- to low-level output See Figure 6-9 1 10 μs
5.13 Switching Characteristics: ULQ2003A, ULQ2004A
over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS ULQ2003A, ULQ2004A UNIT MIN TYP MAX tPLH Propagation delay time, low- to high-level output See Figure 6-9 1 10 μs tPHL Propagation delay time, high- to low-level output See Figure 6-9 1 10 μs ULN2002A, ULN2003A, ULN2003AI ULQ2003A, ULN2004A, ULQ2004A SLRS027S – DECEMBER 1976 – REVISED JUNE 2024 www.ti.com
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5.14 Typical Characteristics
0 50 100 150 200 250 300 350 400 450 500 I C - Collector Current - mA V CE(sat) - Collector-Emitter Saturation Voltage - V I I = 250μA I I = 350μA I I = 500μA Figure 5-1. Collector-Emitter Saturation Voltage vs Collector Current (One Darlington) 0 100 200 300 400 500 600 700 800 I C(tot) - Total Collector Current - mA 0.4 0.6 0.8 1.2 1.4 1.6 1.8 V CE(sat) - Collector-Emitter Saturation Voltage - V I I = 250μA I I = 350μA I I = 500μA Figure 5-2. Collector-Emitter Saturation Voltage vs Total Collector Current (Two Darlingtons in Parallel) 90 100 110 120 130 140 150 I I - Input Current - μA 120 160 200 240 280 320 360 400 440 I C - Collector Current - mA V S =8V V S =10V Figure 5-3. Collector Current vs Input Current 0 10 20 30 40 50 60 70 80 90 100 Duty Cycle - % 0.1 0.2 0.3 0.4 0.5 0.6 I C - Maximum Collector Current - A N = 1 N = 2 N = 3 N = 4 N = 5 N = 6 N = 7 Figure 5-4. D Package Maximum Collector Current vs Duty Cycle (TA = 70°C) 0 20 40 60 80 100 Duty Cycle - % 0.1 0.2 0.3 0.4 0.5 0.6 I C - Maximum Collector Current - A N = 1 N = 2 N = 3 N = 4 N = 5 N = 6 N = 7 Figure 5-5. DYY Package Maximum Collector Current vs Duty Cycle (TA = 70°C) Input Voltage - V 200 400 600 800 1000 1200 1400 Input Current - μA − 40°C 25°C 105°C Figure 5-6. Maximum and Typical Input Current vs Input Voltage www.ti.com ULN2002A, ULN2003A, ULN2003AI ULQ2003A, ULN2004A, ULQ2004A SLRS027S – DECEMBER 1976 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: ULN2002A ULN2003A ULN2003AI ULQ2003A ULN2004A ULQ2004A
5.14 Typical Characteristics (continued)
0.4 0.6 0.8 1.2 1.4 1.6 1.8 Maximum V CE(sat) Voltage - V − 40°C 25°C 105°C Figure 5-7. Maximum and Typical Saturated VCE vs Output Current 250 300 350 400 450 500 550 600 650 Input Current - µA 340 360 380 400 420 440 460 480 500 520 Output Current - mA − 40°C 25°C 105°C Figure 5-8. Minimum Output Current vs Input Current ULN2002A, ULN2003A, ULN2003AI ULQ2003A, ULN2004A, ULQ2004A SLRS027S – DECEMBER 1976 – REVISED JUNE 2024 www.ti.com
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6 Parameter Measurement Information
Figure 6-1. ICEX Test Circuit Open VCE VI ICEX Figure 6-2. ICEX Test Circuit Open VCE ICII(off) Figure 6-3. II(off) Test Circuit Open Open II(on) VI Figure 6-4. II Test Circuit Open VCE ICII hFE = IC II II is fixed for measuring VCE(sat), variable for measuring hFE. Figure 6-5. hFE, VCE(sat) Test Circuit Open VCE ICVI(on) Figure 6-6. VI(on) Test Circuit VR Open IR Figure 6-7. IR Test Circuit IFVF Open Figure 6-8. VF Test Circuit www.ti.com ULN2002A, ULN2003A, ULN2003AI ULQ2003A, ULN2004A, ULQ2004A SLRS027S – DECEMBER 1976 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: ULN2002A ULN2003A ULN2003AI ULQ2003A ULN2004A ULQ2004A
Figure 6-9. Propagation Delay-Time Waveforms 90% 90% 1.5 V 1.5 V 10% 10% 40 µs ≤ 10 ns≤ 5 ns VIH (see Note C) 0 V VOH VOL Input Output VOL T AGE WAVEFORMS 200 /c87 The pulse generator has the following characteristics: PRR = 12.5 kHz, ZO = 50 Ω. CL includes probe and jig capacitance. For testing the ULN2003A device, ULN2003AI device, and ULQ2003A devices, VIH = 3 V; for the ULN2002A device, VIH = 13 V; for the ULN2004A and the ULQ2004A devices, VIH = 8 V. Figure 6-10. Latch-Up Test Circuit and Voltage Waveforms ULN2002A, ULN2003A, ULN2003AI ULQ2003A, ULN2004A, ULQ2004A SLRS027S – DECEMBER 1976 – REVISED JUNE 2024 www.ti.com
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7 Detailed Description
7.1 Overview
This standard device has proven ubiquity and versatility across a wide range of applications. This is due to integration of 7 Darlington transistors of the device that are capable of sinking up to 500 mA and wide GPIO range capability. The ULN2003A device comprises seven high-voltage, high-current NPN Darlington transistor pairs. All units feature a common emitter and open collector outputs. To maximize their effectiveness, these units contain suppression diodes for inductive loads. The ULN2003A device has a series base resistor to each Darlington pair, thus allowing operation directly with TTL or CMOS operating at supply voltages of 5 V or 3.3 V. The ULN2003A device offers solutions to a great many interface needs, including solenoids, relays, lamps, small motors, and LEDs. Applications requiring sink currents beyond the capability of a single output may be accommodated by paralleling the outputs. This device can operate over a wide temperature range (–40°C to 105°C).
7.2 Functional Block Diagrams
All resistor values shown are nominal. The collector-emitter diode is a parasitic structure and should not be used to conduct current. If the collectors go below GND, an external Schottky diode should be added to clamp negative undershoots. COM Output C E Input B 10.5 N
7.2 N 3 N
Figure 7-1. ULN2002A Block Diagram COM Output C E Input B RB 2.7 N Figure 7-2. ULN2003A, ULQ2003A and ULN2003AI Block Diagram COM Output C E Input B RB 10.5 N Figure 7-3. ULN2004A and LQ2004A Block Diagram www.ti.com ULN2002A, ULN2003A, ULN2003AI ULQ2003A, ULN2004A, ULQ2004A SLRS027S – DECEMBER 1976 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: ULN2002A ULN2003A ULN2003AI ULQ2003A ULN2004A ULQ2004A
7.3 Feature Description
Each channel of the ULN2003A device consists of Darlington connected NPN transistors. This connection creates the effect of a single transistor with a very high-current gain ( β2). This can be as high as 10,000 A/A at certain currents. The very high β allows for high-output current drive with a very low input current, essentially equating to operation with low GPIO voltages. The GPIO voltage is converted to base current through the 2.7-k Ω resistor connected between the input and base of the predriver Darlington NPN. The 7.2-kΩ and 3-kΩ resistors connected between the base and emitter of each respective NPN act as pulldowns and suppress the amount of leakage that may occur from the input. The diodes connected between the output and COM pin is used to suppress the kick-back voltage from an inductive load that is excited when the NPN drivers are turned off (stop sinking) and the stored energy in the coils causes a reverse current to flow into the coil supply through the kick-back diode. In normal operation the diodes on base and collector pins to emitter will be reversed biased. If these diodes are forward biased, internal parasitic NPN transistors will draw (a nearly equal) current from other (nearby) device pins.
7.4 Device Functional Modes
7.4.1 Inductive Load Drive
When the COM pin is tied to the coil supply voltage, ULN2003A device is able to drive inductive loads and suppress the kick-back voltage through the internal free-wheeling diodes.
7.4.2 Resistive Load Drive
When driving a resistive load, a pullup resistor is needed in order for ULN2003A device to sink current and for there to be a logic high level. The COM pin can be left floating for these applications. ULN2002A, ULN2003A, ULN2003AI ULQ2003A, ULN2004A, ULQ2004A SLRS027S – DECEMBER 1976 – REVISED JUNE 2024 www.ti.com
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8 Application and Implementation
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.
8.1 Application Information
Typically, the ULN2003A device drives a high-voltage or high-current (or both) peripheral from an MCU or logic device that cannot tolerate these conditions. This design is a common application of ULN2003A device, driving inductive loads. This includes motors, solenoids and relays. Figure 8-1 shows a model for each load type.
8.2 Typical Application
3.3-V Logic 3.3-V Logic 3.3-V Logic VSUP VSUP Figure 8-1. ULN2003A Device as Inductive Load Driver
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 8-1 as the input parameters. Table 8-1. Design Parameters DESIGN PARAMETER EXAMPLE VALUE GPIO voltage 3.3 V or 5 V Coil supply voltage 12 V to 48 V Number of channels 7 Output current (RCOIL) 20 mA to 300 mA per channel Duty cycle 100% www.ti.com ULN2002A, ULN2003A, ULN2003AI ULQ2003A, ULN2004A, ULQ2004A SLRS027S – DECEMBER 1976 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: ULN2002A ULN2003A ULN2003AI ULQ2003A ULN2004A ULQ2004A
8.2.2 Detailed Design Procedure
When using ULN2003A device in a coil driving application, determine the following:
- Input voltage range
- Temperature range
- Output and drive current
- Power dissipation
8.2.2.1 Drive Current
The coil voltage (VSUP), coil resistance (RCOIL), and low-level output voltage (V CE(SAT) or VOL) determine the coil current. ICOIL = (VSUP – VCE(SAT)) / RCOIL (1)
8.2.2.2 Low-Level Output Voltage
The low-level output voltage (V OL) is the same as V CE(SAT) and can be determined by, Figure 5-1, Figure 5-2, or Figure 5-7.
8.2.2.3 Power Dissipation and Temperature
The number of coils driven is dependent on the coil current and on-chip power dissipation. The number of coils driven can be determined by Figure 5-4 or Figure 5-5. For a more accurate determination of number of coils possible, use the below equation to calculate ULN2003A device on-chip power dissipation PD: N D OLi Li i 1 P V I /c61 /c61 /c180/c229 (2) where
- N is the number of channels active together
- VOLi is the OUTi pin voltage for the load current ILi. This is the same as VCE(SAT) To ensure reliability of ULN2003A device and the system, the on-chip power dissipation must be lower that or equal to the maximum allowable power dissipation (PD(MAX)) dictated by below equation Equation 3. AJ MAX MAX JA T T PD T (3) where
- TJ(max) is the target maximum junction temperature
- TA is the operating ambient temperature
- RθJA is the package junction to ambient thermal resistance Limit the die junction temperature of the ULN2003A device to less than 125°C. The IC junction temperature is directly proportional to the on-chip power dissipation. ULN2002A, ULN2003A, ULN2003AI ULQ2003A, ULN2004A, ULQ2004A SLRS027S – DECEMBER 1976 – REVISED JUNE 2024 www.ti.com
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8.2.3 Application Curves
The characterization data shown in Figure 8-2 and Figure 8-3 were generated using the ULN2003A device driving an OMRON G5NB relay and under the following conditions: VIN = 5 V, VSUP= 12 V, and RCOIL= 2.8 kΩ. Time (s) Output voltage - V D001 Figure 8-2. Output Response With Activation of Coil (Turnon) Time (s) Output voltage - V D001 Figure 8-3. Output Response With De-activation of Coil (Turnoff) www.ti.com ULN2002A, ULN2003A, ULN2003AI ULQ2003A, ULN2004A, ULQ2004A SLRS027S – DECEMBER 1976 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: ULN2002A ULN2003A ULN2003AI ULQ2003A ULN2004A ULQ2004A
8.3 System Examples
Figure 8-4. P-MOS to Load ULQ2003A Lam T estTTL Output VCC V Figure 8-5. TTL to Load VDD V ULN2004A ULQ2004A CMOS Output Figure 8-6. Buffer for Higher Current Loads VCC V RP ULQ2003A TTL Output 7 Figure 8-7. Use of Pullup Resistors to Increase Drive Current
8.4 Power Supply Recommendations
This device does not need a power supply. However, the COM pin is typically tied to the system power supply. When this is the case, it is very important to ensure that the output voltage does not heavily exceed the COM pin voltage. This discrepancy heavily forward biases the fly-back diodes and causes a large current to flow into COM, potentially damaging the on-chip metal or over-heating the device.
8.5 Layout
8.5.1 Layout Guidelines
Thin traces can be used on the input due to the low-current logic that is typically used to drive ULN2003A device. Take care to separate the input channels as much as possible, as to eliminate crosstalk. TI recommends thick traces for the output to drive whatever high currents that may be needed. Wire thickness can be determined by the current density of the trace material and desired drive current. ULN2002A, ULN2003A, ULN2003AI ULQ2003A, ULN2004A, ULQ2004A SLRS027S – DECEMBER 1976 – REVISED JUNE 2024 www.ti.com
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Product Folder Links: ULN2002A ULN2003A ULN2003AI ULQ2003A ULN2004A ULQ2004A
Because all of the channels currents return to a common emitter, it is best to size that trace width to be very wide. Some applications require up to 2.5 A.
8.5.2 Layout Example
E GND Figure 8-8. Package Layout www.ti.com ULN2002A, ULN2003A, ULN2003AI ULQ2003A, ULN2004A, ULQ2004A SLRS027S – DECEMBER 1976 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: ULN2002A ULN2003A ULN2003AI ULQ2003A ULN2004A ULQ2004A
9 Device and Documentation Support
9.1 Documentation Support
9.1.1 Related Documentation
For related documentation, see the following: SN7546x Darlington Transistor Arrays, SLRS023
9.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 9-1. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY ULN2002A Click here Click here Click here Click here Click here ULN2003A Click here Click here Click here Click here Click here ULN2003AI Click here Click here Click here Click here Click here ULN2004A Click here Click here Click here Click here Click here ULQ2003A Click here Click here Click here Click here Click here ULQ2004A Click here Click here Click here Click here Click here
9.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
9.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
9.5 Trademarks
TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.
9.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
9.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. ULN2002A, ULN2003A, ULN2003AI ULQ2003A, ULN2004A, ULQ2004A SLRS027S – DECEMBER 1976 – REVISED JUNE 2024 www.ti.com
20 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated
Product Folder Links: ULN2002A ULN2003A ULN2003AI ULQ2003A ULN2004A ULQ2004A
Changes from Revision R (February 2024) to Revision S (June 2024) Page Changes from Revision Q (July 2022) to Revision R (February 2024) Page
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser based versions of this data sheet, refer to the left hand navigation. www.ti.com ULN2002A, ULN2003A, ULN2003AI ULQ2003A, ULN2004A, ULQ2004A SLRS027S – DECEMBER 1976 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: ULN2002A ULN2003A ULN2003AI ULQ2003A ULN2004A ULQ2004A
www.ti.com 4-Jul-2024 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PULN2003ADYYR ACTIVE SOT-23-THIN DYY 16 2500 TBD Call TI Call TI -40 to 70 Samples ULN2002AN ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -20 to 70 ULN2002AN Samples ULN2002ANE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -20 to 70 ULN2002AN Samples ULN2003ADR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 70 ULN2003A Samples ULN2003AIDR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 105 ULN2003AI Samples ULN2003AINSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 ULN2003AI Samples ULN2003AIPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 105 UN2003AI Samples ULN2003AN ACTIVE PDIP N 16 25 RoHS & Green NIPDAU | SN N / A for Pkg Type -40 to 70 ULN2003AN Samples ULN2003ANSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 70 ULN2003A Samples ULN2003ANSRE4 ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 70 ULN2003A Samples ULN2003ANSRG4 ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 70 ULN2003A Samples ULN2003APWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 70 UN2003A Samples ULN2004ADR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -20 to 70 ULN2004A Samples ULN2004AN ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -20 to 70 ULN2004AN Samples ULN2004ANE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -20 to 70 ULN2004AN Samples ULN2004ANSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -20 to 70 ULN2004A Samples ULQ2003AN ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 ULQ2003A Samples ULQ2004AD ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ULQ2004A Samples ULQ2004ADG4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM ULQ2004A Samples ULQ2004ADR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ULQ2004A Samples Addendum-Page 1
www.ti.com 4-Jul-2024 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples ULQ2004ADRG4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM ULQ2004A Samples ULQ2004AN ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 ULQ2004AN Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF ULQ2003A, ULQ2004A : Addendum-Page 2
www.ti.com 4-Jul-2024
- Automotive : ULQ2003A-Q1 , ULQ2004A-Q1 NOTE: Qualified Version Definitions:
- Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 3
PACKAGE MATERIALS INFORMATION www.ti.com 5-Jun-2024 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 5-Jun-2024 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ULN2003ADR SOIC D 16 2500 340.5 336.1 32.0 ULN2003ADR SOIC D 16 2500 356.0 356.0 35.0 ULN2003AIDR SOIC D 16 2500 364.0 364.0 27.0 ULN2003AIDR SOIC D 16 2500 340.5 336.1 32.0 ULN2003AINSR SO NS 16 2000 356.0 356.0 35.0 ULN2003AIPWR TSSOP PW 16 2000 356.0 356.0 35.0 ULN2003ANSR SO NS 16 2000 356.0 356.0 35.0 ULN2003APWR TSSOP PW 16 2000 356.0 356.0 35.0 ULN2004ADR SOIC D 16 2500 340.5 336.1 32.0 ULN2004ADR SOIC D 16 2500 356.0 356.0 35.0 ULN2004ANSR SO NS 16 2000 356.0 356.0 35.0 Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 5-Jun-2024 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) ULN2002AN N PDIP 16 25 506 13.97 11230 4.32 ULN2002ANE4 N PDIP 16 25 506 13.97 11230 4.32 ULN2003AN N PDIP 16 25 506 13.97 11230 4.32 ULN2003AN N PDIP 16 25 506.1 9 600 5.4 ULN2003AN N PDIP 16 25 506 13.97 11230 4.32 ULN2004AN N PDIP 16 25 506 13.97 11230 4.32 ULN2004AN N PDIP 16 25 506 13.97 11230 4.32 ULN2004ANE4 N PDIP 16 25 506 13.97 11230 4.32 ULN2004ANE4 N PDIP 16 25 506 13.97 11230 4.32 ULQ2003AN N PDIP 16 25 506 13.97 11230 4.32 ULQ2003AN N PDIP 16 25 506 13.97 11230 4.32 ULQ2004AD D SOIC 16 40 507 8 3940 4.32 ULQ2004ADG4 D SOIC 16 40 507 8 3940 4.32 ULQ2004AN N PDIP 16 25 506 13.97 11230 4.32 Pack Materials-Page 3
www.ti.com PACKAGE OUTLINE C 14X 0.65 4.55 16X 0.30 0.19 TYP6.6 6.2
1.2 MAX
0.15 0.05 0.25 GAGE PLANE -80 B NOTE 4 4.5 4.3 A NOTE 3 5.1 4.9 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/A 02/2017
0.1 C A B
0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500
www.ti.com EXAMPLE BOARD LAYOUT
0.05 MAX
0.05 MIN
16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 8 9 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN 16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 8 9
NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.50 per side. 5. Reference JEDEC Registration MO-345, Variation AA PACKAGE OUTLINE 4224642/C 04/2024 www.ti.com SOT-23-THIN - 1.1 mm max height PLASTIC SMALL OUTLINE DYY0016A A 0.1 C B PIN 1 INDEX AREA 4.3 4.1 NOTE 3 2.1 1.9 3.36 3.16 14X 0.5 3.5 16X 0.3 0.11
1.1 MAX
C SEATING PLANE 0.2
0.08 TYP
0.1 0.0 0.25 GAUGE PLANE 0°- 8° 0.63 0.33 DETAIL A TYP ALTERNATIVE PACKAGE SINGULATION VIEW
NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. EXAMPLE BOARD LAYOUT 4224642/C 04/2024 www.ti.com SOT-23-THIN - 1.1 mm max heightDYY0016A PLASTIC SMALL OUTLINE SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X 16X (0.3) 16X (1.05) (3) 14X (0.5) (R0.05) TYP 8 9 METAL SOLDER MASK OPENING SOLDER MASK OPENING METAL UNDER SOLDER MASK NON- SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS
NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. EXAMPLE STENCIL DESIGN 4224642/C 04/2024 www.ti.com SOT-23-THIN - 1.1 mm max heightDYY0016A PLASTIC SMALL OUTLINE SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 20X SYMM SYMM 16X (0.3) 16X (1.05) (3) 14X (0.5) (R0.05) TYP 8 9
www.ti.com PACKAGE OUTLINE C 8.2
7.4 TYP
14X 1.27 16X 0.51 0.35 8.89
0.15 TYP
0.3 0.1
2.00 MAX
(1.25) 0.25 GAGE PLANE 1.05 0.55 A 10.4 10.0 NOTE 3 B 5.4 5.2 NOTE 4 4220735/A 12/2021 SOP - 2.00 mm max heightNS0016A SOP NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side. 1 16
0.25 C A B
0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.500
www.ti.com EXAMPLE BOARD LAYOUT
0.07 MAX
0.07 MIN
14X (1.27) (R0.05) TYP (7) 16X (1.85) 16X (0.6) 4220735/A 12/2021 SOP - 2.00 mm max heightNS0016A SOP NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS OPENING SOLDER MASK METAL SOLDER MASK DEFINED LAND PATTERN EXAMPLE SCALE:7X SYMM 8 9 SEE DETAILS SYMM
www.ti.com EXAMPLE STENCIL DESIGN (7)(R0.05) TYP 16X (1.85) 16X (0.6) 14X (1.27) 4220735/A 12/2021 SOP - 2.00 mm max heightNS0016A SOP NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:7X SYMM SYMM 8 9
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