UCC57108-Q1_V01 TI | Alldatasheet

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UCC5710x-Q1 High-Speed, Low-Side Gate Driver With DESAT Protection For Automotive Applications

1 Features

  • Qualified for automotive applications
  • AEC-Q100 qualified – Device temperature grade 1
  • Typical 3A sink 3A source output currents
  • DESAT protection with programmable delay
  • Soft turn-off when fault happens
  • Absolute maximum VDD voltage: 30V
  • Input and enable pins capable of withstanding up to –5V
  • Tight UVLO thresholds for bias flexibility
  • Typical 25ns propagation delay
  • Self-protect driver with thermal shutsown function
  • Wide bias voltage range
  • Available in 5mm x 4mm SOIC8 package
  • Operating junction temperature range of –40°C to 150°C

2 Applications

  • HEV/EV PTC heaters
  • Traction inverters
  • Residential EV chargers
  • Motor drives
  • HVAC compressors

3 Description

The UCC5710x-Q1 is a single channel, high- performance low-side IGBT/SiC gate driver for high power automotive application such as PTC heaters, traction inverter active discharge circuit and other auxiliary subsystems.It offers protection features including Under-voltage-lock-out (UVLO), Desaturation protection (DESAT), FAULT report , and Thermal shutdown protection. UCC5710x-Q1 has a typical peak drive strength of 3A. and it can handle –5V on its inputs, which improves robustness in systems with moderate ground bouncing. The inputs are independent of supply voltage and can be connected to most controller outputs for maximum control flexibility. Depending on the different pin configuration, the wide voltage range of bias supply is provided in UCC5710xB-Q1 accommodates bipolar voltage. Also, the seperate high and low driver outputs ( UCC5710xC-Q1) and enable funtion ( UCC5710xW-Q1) are provided. An accurate 5V output is available with UCC5710xB-Q1 and UCC5710xC-Q1.

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE (NOM) UCC57108B-Q1 D (SOIC 8) 4.9mm × 6.0mm 4.90mm × 3.91mm UCC57102-Q1 D (SOIC 8) 4.9mm × 6.0mm 4.90mm × 3.91mm UCC5710xC-Q1(3) D (SOIC 8) 4.9mm × 6.0mm 4.90mm × 3.91mm UCC5710xW-Q1(3) D (SOIC 8) 4.9mm × 6.0mm 4.90mm × 3.91mm (1) For all available packages, see Section 12. (2) The package size (length × width) is a nominal value and includes pins, where applicable. (3) Product Preview OUTH OUTL GND VDD IN GND VREF GND DESAT MCU FLT GND VDD PTC Heater Vbat Simplified Application Diagram ADVANCE INFORMATION UCC57108-Q1, UCC57102-Q1 SLUSF94B – DECEMBER 2023 – REVISED JUNE 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains ADVANCE INFORMATION for pre-production products; subject to change without notice.

12 Mechanical, Packaging, and Orderable

UCC57108-Q1, UCC57102-Q1 SLUSF94B – DECEMBER 2023 – REVISED JUNE 2024 www.ti.com

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4 Pin Configuration and Functions

Figure 4-1. UCC5710xB-Q1 D Package SOIC-8 Top View IN VREF DESAT GND OUTL OUTH VDD 6FLT Figure 4-2. UCC5710xC-Q1 D Package SOIC-8 Top View IN NC DESAT GND EN OUT VDD 6FLT Figure 4-3. UCC5710xW-Q1 D Package SOIC-8 Top View Table 4-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME UCC5710xB- UCC5710x C-Q1 UCC5710x W-Q1 IN 1 1 1 I Non-inverting PWM input VREF 2 2 NA O 5V Reference generated within the driver NC NA NA 2 Not Connected FLTb 3 3 3 O Active low fault reporting DEAST 4 4 4 I Input for detecting the desatuation fault VDD 5 5 5 P Driver bias supply OUT 6 NA 6 O Output of the driver OUTH NA 6 NA O Driver high output EN NA NA 6 I Enable or disable control pin. OUTL NA 7 NA O Driver low output GND 7 8 8 G Driver ground VEE 8 NA NA P Driver negtive bias supply with respect to GND (1) I/O = Digital input/output, IA = Analog input, AO= Analog output, P = Power connection www.ti.com UCC57108-Q1, UCC57102-Q1 SLUSF94B – DECEMBER 2023 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: UCC57108-Q1 UCC57102-Q1 ADVANCE INFORMATION

5 Specifications

5.1 Absolute Maximum Ratings

All the voltages are with respect to GND. Over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VDD-GND Positive power supply –0.3 30 V VDD-VEE Differential Power Supply -0.3 30 V VEE-GND Negative Power Supply -18 0.3 V OUT Output signal DC voltage GND/VEE–0.3 VDD+0.3 V Output signal transient voltage for 200-ns GND/VEE–2 VDD+3 V VDESAT Desat voltage –0.3 VDD+0.3 V VIN IN signal DC voltage –5 30 V VEN EN signal DC voltage (W Version) –5 30 V IFLT FLT current sink 20 mA VFLT External pull-up -0.3 VDD+0.3 V TJ Junction temperature –40 150 ℃ Tstg Storage temperature –65 150 ℃ (1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/ JEDEC JS-001(1) All pins except VREF ±2000 V VREF (UCC5710xB-Q1, UCC5710xC-Q1) ±1500 Charged device model (CDM), per JEDEC specification JESD22-C101(2) All pins ±1000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Thermal Information

THERMAL METRIC(1) UCC5710x-Q1 UNITD (SOIC)

8 PINS

RθJA Junction-to-ambient thermal resistance 126.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 67.0 °C/W RθJB Junction-to-board thermal resistance 69.9 °C/W ΨJT Junction-to-top characterization parameter 19.2 °C/W ΨJB Junction-to-board characterization parameter 69.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. UCC57108-Q1, UCC57102-Q1 SLUSF94B – DECEMBER 2023 – REVISED JUNE 2024 www.ti.com

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5.4 Recommended Operating Conditions

All voltages are with reference to GND. Over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD-GND Positive Power Supply UVLO 26 V VDD-VEE Differential Power Supply 26 V VEE-GND Negative Power Supply -15 0 V VOUT Output Voltage GND/VEE VDD V VIN IN signal DC voltage -2 26 V VEN EN signal DC voltage (W Version) -2 26 V TJ Junction temperature –40 150 ℃

5.5 Electrical Characteristics

VDD = 15 V, VEE = 0 V, 1-µF capacitor from VDD to GND, 1-µF capacitor from VEE to GND, TJ = –40°C to +150°C, CL = 0 pF, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENTS IVDDQ VDD quiescent supply current VIN = 3.3V, EN = 5V, VDD = 6.5V 1.4 mA IVDD VDD static supply current VIN = 3.3 V, EN = 5V 1.1 1.5 mA IVEEQ VEE static supply current VIN = 0 V, EN = 5V, VEE = -10V 1.1 mA IVDD VDD static supply current VIN = 0 V, EN = 5V 0.8 1.2 mA IVDDO VDD dynamic operating current fSW = 1000 kHz, EN = 5V, VDD=15 V, CL=1800pF 35 mA IDIS VDD disable current VINx = 3.3 V, EN = 0 V 0.8 1.1 mA VDD UNDERVOLTAGE THRESHOLDS AND DELAY VVDD_ON VDD UVLO Rising Threshold 8.5-V UVLO Option 7.6 8 8.4 V VVDD_OFF VDD UVLO Falling Threshold 8.5-V UVLO Option 6.65 7 7.35 V VVDD_HYS VDD UVLO Threshold Hysteresis 8.5-V UVLO Option 1 V tUVLO2FLT Propagation delay from UVLO shutdown to FLT 8.4 us VVDD_ON VDD UVLO Rising Threshold 12.5-V UVLO Option 12.8 13.5 14.2 V VVDD_OFF VDD UVLO Falling Threshold 11.8 12.5 13.2 V VVDD_HYS VDD UVLO Threshold Hysteresis 1.0 V VREF VREF Voltage Reference IREF=10mA 5 V IREF Reference output current 20 mA IN, EN VINH Input High Threshold Voltage Output goes high when threshold is reached 1.8 2.2 2.6 V VINL Input Low Threshold Voltage Output goes low when threshold reached 0.8 1.2 1.6 V VIN_HYS Input-threshold Hysteresis Calculate as VINH - VINL 1.0 V RIND IN Pin Pull Down Resistance IN, DIS = 3.3V 120 kΩ VENH Enable High Threshold Voltage Output goes HIGH when threshold reached 1.8 2.2 2.6 V VENL Enable Low Threshold Voltage Output goes LOW when threshold reached 0.8 1.2 1.6 V VEN_HYS Enable Threshold Hysteresis Calculate as VENH - VENL 1 V RENU EN Pin Pull Up Resistance EN = 0V 400 kΩ VFLTth FLT threshold voltage IFLT-sink = 15mA 0.43 1 V DESAT DETECTION www.ti.com UCC57108-Q1, UCC57102-Q1 SLUSF94B – DECEMBER 2023 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: UCC57108-Q1 UCC57102-Q1 ADVANCE INFORMATION

5.5 Electrical Characteristics (continued)

VDD = 15 V, VEE = 0 V, 1-µF capacitor from VDD to GND, 1-µF capacitor from VEE to GND, TJ = –40°C to +150°C, CL = 0 pF, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ICHG Blanking capacitor charge current (250µA variant) VDESAT = 3.25V 200 250 316 µA IDCHG DESAT pin discharge current VDESAT = 8V -20 mA VDESATTH DESAT Detection Threshold FLT goes low when threshold is reached 6.0 6.5 7.0 V VDESLO DESAT voltage when OUT=L, referenced to GND 100 mV tDESLEB Leading edge blanking time 150 ns tDESFIL DESAT deglitch filter 100 150 ns tDES2OUT DESAT propagation delay to 90% of OUT VDESAT>VDESATTH 140 250 ns tDES2FLT DESAT propagation delay to FLT low VDESATTH to 90% of FLT, Cl=10pF 135 250 ns SOFT TURN OFF RSTO Internal Soft turn-off Pulldown Resistance DESAT triggered, VOUT=5V 35 Ω OVERTEMPERATURE PROTECTION TSD Overtemperature threshold 180 C THYS Overtemperature protection hysteresis 30 C tOTP2FLT Propagation delay from overtemperature shutdown to FLT Over temperature shutdow to 90% of FLT, Cl=10pF 8 us OUTPUT DRIVER STAGE ISRCPK Peak Output Source Current CVDD = 10 µF, CL = 0.1 µF, f = 1 kHz -3 A ISNKPK Peak Output Sink Current CVDD = 10 µF, CL = 0.1 µF, f = 1 kHz 2.8 A ROH Pull up resistance IOUT = –500mA 5 Ω ROL Pull down resistance IOUT = 500mA 1 Ω

5.6 Switching Characteristics

VDD = 15 V, VEE = 0 V, 1-µF capacitor from VDD to GND, 1-µF capacitor from VEE to GND, TJ = –40°C to +150°C, CL = 0 pF, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tRA, tRB Output Rise Time CL=1.8nF, 10% to 90%, Vin = 0 to 3.3V 8 18 ns tFA, tFB Output Fall Time CL=1.8nF, 90% to 10%, Vin = 0 to 3.3V 14 32 ns tD2 Propagation Delay – Input falling to output falling CL=1.8nF, from 1V falling on Vin to 90% of output fall, Vin=0 - 3.3V, Fsw=500kHz, 50% duty cycle 28 50 ns tD1 Propagation Delay – Input rising to output rising CL=1.8nF, from 2V rising on Vin to 10% of output rise, Vin=0 - 3.3V, Fsw=500kHz, 50% duty cycle 26 50 ns tPD_EN EN Response Delay (W Version) CL=1.8nF, from 2V rising on EN to 10% of output rise, EN=0 - 3.3V, Fsw=500kHz, 50% duty cycle 26 40 ns tPD_DIS DIS Response Delay (W Version) CL=1.8nF, from 1V falling on EN to 90% of output fall, EN=0 - 3.3V, Fsw=500kHz, 50% duty cycle 27 45 ns tPWmin Minimum Input Pulse Width That Passes to Output CL=1.8nF, Vin=0 - 3.3V, Fsw=500kHz, Vo >2V 9 15 ns UCC57108-Q1, UCC57102-Q1 SLUSF94B – DECEMBER 2023 – REVISED JUNE 2024 www.ti.com

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5.6 Switching Characteristics (continued)

VDD = 15 V, VEE = 0 V, 1-µF capacitor from VDD to GND, 1-µF capacitor from VEE to GND, TJ = –40°C to +150°C, CL = 0 pF, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPWD Pulse Width Distortion Input Pulse Width = 100ns, 500kHz tD2_1 – tD1_1 ,CL=1.8nF -10 10 ns

6 Detailed Description

6.1 Overview

The UCC5710x-Q1 deviceis a single-channel, high-speed, gate drivers capable of effectively driving MOSFET, SiC MOSFET, and IGBT power switches with 3-A source and 3-A sink (symmetrical drive) peak current. The driver has a good transient handling capability on its output due to reverse currents, as well as rail-to-rail drive capability and small propagation delay, typically 26ns. The device has the state-of-art DESAT detection time, and fault reporting function to the low voltage side DSP/MCU. Soft turn off is triggered when the DESAT fault is detected, minimizing the short circuit energy while reducing the overshoot voltage on the switch. The input threshold of UCC5710x-Q1 is compatible to TTL low-voltage logic, which is fixed and independent of VDD supply voltage. The driver can also work with CMOS based controllers as long as the threshold requirement is met. The 1-V typical hysteresis offers excellent noise immunity. In the UCC5710xW-Q1, the driver has an EN pin with fixed TTL compatible threshold. EN is internally pulled up.Pulling EN low disables the driver, while leaving EN open provides normal operation. In the UCC5710xB-Q1 and UCC5710xC-Q1 offer an additional 5V output (VREF) that source up to 20mA function.

6.2 Functional Block Diagram

Figure 6-1. UCC5710xB-Q1 Simplified Functional Block Diagram www.ti.com UCC57108-Q1, UCC57102-Q1 SLUSF94B – DECEMBER 2023 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: UCC57108-Q1 UCC57102-Q1 ADVANCE INFORMATION

Figure 6-2. UCC5710xC-Q1 Simplified Functional Block Diagram EN IN DRIVER STAGE 3FLT GND OUT VDD DESAT NC UVLO VDD DESATLATCH TSD 2Mohm Figure 6-3. UCC5710xW-Q1 Simplified Functional Block Diagram UCC57108-Q1, UCC57102-Q1 SLUSF94B – DECEMBER 2023 – REVISED JUNE 2024 www.ti.com

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6.3 Feature Description

6.3.1 Input Stage

The inputs of the UCC5710x-Q1 device are compatible with TTL based threshold logic andthe inputs are independent of the VDD supply voltage. With typical high threshold of 2.2 V and typical low threshold of 1.2 V, the logic level thresholds can be conveniently driven with PWM control signals derived from 3.3-V or 5-V logic. Wider hysteresis (typically 1 V) offers enhanced noise immunity compared to traditional TTL logic implementations, where the hysteresis is typically less than 0.5 V. This device also features tight control of the input pin threshold voltage levels which eases system design considerations and ensures stable operation across temperature. The very low input capacitance, typically less than 8 pF, on these pins reduces loading and increases switching speed. The device features an important protection function wherein, whenever the input pin is in a floating condition, the output is held in the low state. This is achieved with internal pullup or pulldown resistors on the input pins as shown in the simplified functional block diagrams. In some applications, due to difference in bias supply sequencing, different ICs power-up at different times. This may cause output of the controller to be in tri-state. This output of the controller gets connected to the input of the driver IC. If the driver IC does not have a pulldown resistor then the output of the driver may go high erroneously and damage the switching power device. The input stage of the driver should preferably be driven by a signal with a short rise or fall time. Caution must be exercised whenever the driver is used with slowly varying input signals, especially in situations where the device is located in a separate daughter board or PCB layout has long input connection traces:

  • High dI/dt current from the driver output coupled with board layout parasitics can cause ground bounce. Because the device features just one GND pin which may be referenced to the power ground, this may interfere with the differential voltage between Input pins and GND and trigger an unintended change of output state. Because of fast 26-ns propagation delay, this can ultimately result in high-frequency oscillations, which increases power dissipation and poses risk of damage.
  • 1-V Input threshold hysteresis boosts noise immunity compared to most other industry standard drivers. An external resistance is highly recommended between the output of the driver and the power device instead of adding delays on the input signal. This also limits the rise or fall times to the power device which reduces the EMI. The external resistor has the additional benefit of reducing part of the gate charge related power dissipation in the gate driver device package and transferring it into the external resistor itself. Finally, because of the unique input structure that allows negative voltage capability on the Input and Enable pins, caution must be used in the following applications:
  • Input or Enable pins are switched to amplitude > 15 V.
  • Input or Enable pins are switched at dV/dt > 2 V/ns. If both of these conditions occur, add a series 150- Ω resistor for the pin(s) being switched to limit the current through the input structure.

6.3.2 Enable Function

The Enable (EN) pin of the UCC5710xW-Q1 device also has TTL compatible input thresholds with wide hysteresis. The typical turnon threshold is 2.2V and the typical turn-off threshold is 1.2V with typical hysteresis of 1V. The Enable (EN) pin of the UCC5710xW-Q1 has an internal pullup resistor to an internal reference voltage. Thus, leaving the Enable pin floating turns on the driver and allows it to send output signals properly. If desired, the Enable can also be driven by low-voltage logic to enable and disable the driver. There is minimum delay from the enable block to the output for fast system response time. Similar to the input pins, the enable pin can also handle significant negative voltage and therefore provides system robustness. The enable pin can withstand wide range of slew rate such as 1V/ns to 1V/ms. The enable signal is independent of VDD voltage and stable across the full operating temperature range.

6.3.3 Driver Stage

The device has ±3-A peak drive strength and is suitable for driving IGBT/SiC. The driver features an important safety function wherein, when the input pins are in floating condition, the output is held in LOW state. The www.ti.com UCC57108-Q1, UCC57102-Q1 SLUSF94B – DECEMBER 2023 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: UCC57108-Q1 UCC57102-Q1 ADVANCE INFORMATION

driver has rail-to-rail output by implementing an NMOS pull-up with intrinsic bootstrap gate drive. Under DC conditions, a PMOS is used to keep OUT tied to VDD as shown in the figure. The low pullup impedance of the NMOS results in strong drive strength during the turn-on transient, which shortens the charging time of the input capacitance of the power semiconductor and reduces the turn on switching loss. VDD VEE COM OUT3A FET 3A FET Driver PWM CONTROLLER Figure 6-4. Gate Driver Output Stage

6.3.4 Desaturation (DESAT) Protection

The UCC5710x-Q1 implements a fast overcurrent and short circuit protection feature to protect the MOSFET/ IGBT from catastrophic breakdown during fault. The DESAT pin has a typical 6.5 V threshold with respect to COM, the source or emitter of the power semiconductor. When the input is in a floating condition or the output is held in low state, the DESAT pin is pulled down by an internal MOSFET and held in the LOW state, which prevents the overcurrent and short circuit fault from false triggering. The internal current source of the DESAT pin is activated only during the driver ON state, which means the overcurrent and short circuit protection feature only works when the power semiconductor is in the ON state. The internal pulldown MOSFET helps to discharge the voltage of the DESAT pin when the power semiconductor is turned off. The features a 150-ns internal leading edge blanking time after the OUT switches to high state. The UCC5710x-Q1 internal current source is activated to charge the external blanking capacitor after the internal leading edge blanking time. The typical value of the internal current source is 250 µA. UCC57108-Q1, UCC57102-Q1 SLUSF94B – DECEMBER 2023 – REVISED JUNE 2024 www.ti.com

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Figure 6-5. DESAT Protection

6.3.5 Fault (FLT)

The FLT pin of UCC5710x-Q1 can report a fault signal to the DSP/MCU when the fault is detected through the DESAT pin, internal TSD or the UVLO. The FLT pin is pulled down to GND after the fault is detected, and is held low until the fault is clear.

6.4 Device Functional Modes

The UCC5710x-Q1 devices operate in normal mode and UVLO mode (see Section 7.2.2.1 for information on UVLO operation). In normal mode, the output state is dependent on the states of the device, and the input pins. The UCC5710xW-Q1 features a single, non-inverting input, but also contains enable and disable functionality through the EN pin. Setting the EN pin to logic HIGH will enable the non-inverting input to output on the IN pin. Table 6-1. UCC5710xB-Q1, UCC5710xC-Q1 Truth Table IN DESAT INTERNAL TSD FLT OUT H L L Open drain H L L L Open drain L H H L L L X X H L L Table 6-2. UCC5710xW-Q1 Truth Table IN EN DESAT INTERNAL TSD FLT OUT L H L L Open drain L H H L L Open drain H X L X X X L H H H L L L X H X H L L www.ti.com UCC57108-Q1, UCC57102-Q1 SLUSF94B – DECEMBER 2023 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: UCC57108-Q1 UCC57102-Q1 ADVANCE INFORMATION

7 Applications and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

7.1 Application Information

High-current gate driver devices are required in switching power applications for a variety of reasons. To enable fast switching of power devices and reduce associated switching power losses, a powerful gate driver can be employed between the PWM output of controllers or signal isolation devices and the gates of the power semiconductor devices. Further, gate drivers are indispensable when sometimes it is just not feasible to have the PWM controller directly drive the gates of the switching devices. The situation will be often encountered because the PWM signal from a digital controller or signal isolation device is often a 3.3-V or 5-V logic signal which is not capable of effectively turning on a power switch. A level-shifting circuitry is needed to boost the logic-level signal to the gate-drive voltage in order to fully turn on the power device and minimize conduction losses. Traditional buffer drive circuits based on NPN/PNP bipolar, (or P- N-channel MOSFET), transistors in totem-pole arrangement, being emitter follower configurations, prove inadequate for this because they lack level-shifting capability and low-drive voltage protection. Gate drivers effectively combine both the level-shifting, buffer drive and UVLO functions. Gate drivers also find other needs such as minimizing the effect of switching noise by locating the high-current driver physically close to the power switch, driving gate-drive transformers and controlling floating power device gates, reducing power dissipation and thermal stress in controllers by moving gate charge power losses into itself. The UCC5710x-Q1 is very flexible in this role with a strong drive current capability and wide recommended supply voltage range of UVLO to 26 V. This allows the driver to be used in 5-V bias logic level very high frequency MOSFET applications, 12-V MOSFET applications, 20-V and -5-V (relative to Source) SiC FET applications, 15-V and -8-V (relative to Emitter) IGBT applications and many others. These requirements, coupled with the need for low propagation delays and availability in compact, and low-inductance packages with good thermal capability, make gate driver devices such as the UCC5710x-Q1 extremely important components in switching power combining benefits of high-performance, low cost, low component count, board space reduction and simplified system design. UCC57108-Q1, UCC57102-Q1 SLUSF94B – DECEMBER 2023 – REVISED JUNE 2024 www.ti.com

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7.2 Typical Application

Figure 7-1. UCC57108C-Q1 Used in a PTC Heater Application

7.2.1 Design Requirements

When selecting the gate driver device for an end application, some design considerations must be evaluated in order to make the most appropriate selection. Following are some of the design parameters that should be used when selecting the gate driver device for an end application: input-to-output configuration, the input threshold type, bias supply voltage levels, peak source and sink currents, availability of independent enable and disable functions, propagation delay, power dissipation, and package type. See the example design parameters and requirements in Table 7-1. Table 7-1. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input to output logic Non-inverting Input threshold type TTL Bias supply voltage levels +18 V Negative output low voltage N/A dVDS/dt(1) 100 V/ns Enable function Yes Disable function N/A Propagation delay <30 ns Power dissipation <1 W (1) dVDS/dt is a typical requirement for a given design. This value can be used to find the peak source/sink currents needed as shown in .

7.2.2 Detailed Design Procedure

7.2.2.1 VDD Undervoltage Lockout

The UCC57108-Q1 device offers an undervoltage lockout threshold of 8 V and UCC57102 provide under voltage lockout threshold of 12V. The device's hysteresis range helps to avoid any chattering due to the presence of noise on the bias supply. 1V of typical UVLO hysteresis is expected. There is no significant driver output turnon www.ti.com UCC57108-Q1, UCC57102-Q1 SLUSF94B – DECEMBER 2023 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: UCC57108-Q1 UCC57102-Q1 ADVANCE INFORMATION

delay due to the UVLO feature, and 4 μs of UVLO delay is expected. The UVLO turn-off delay is also minimized as much as possible. The UVLO delay is designed to minimize chattering that may occur due to very fast transients that may appear on VDD. When the bias supply is below UVLO thresholds, the outputs are held actively low irrespective of the state of input pins and enable pin. The device accepts a wide range of slew rates on its VDD pin, and VDD noise within the hysteresis range does not affect the output state of the driver (neither ON nor OFF). OUT IN VDD VDD Threshold Figure 7-2. Power Up UCC57108-Q1, UCC57102-Q1 SLUSF94B – DECEMBER 2023 – REVISED JUNE 2024 www.ti.com

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7.2.3 Application Curves

The figures below show the typical switching characteristics of the UCC57108-Q1 device with a 1nF capacitor load. Figure 7-3. UCC57108-Q1 Rising (Turn-On) Propagation Delay Figure 7-4. UCC57108-Q1 Falling (Turn-Off) Propagation Delay www.ti.com UCC57108-Q1, UCC57102-Q1 SLUSF94B – DECEMBER 2023 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: UCC57108-Q1 UCC57102-Q1 ADVANCE INFORMATION

8 Power Supply Recommendations

The bias supply voltage range for which the UCC5710x-Q1 devices are recommended to operate is from UVLO to 26 V. The lower end of this range is governed by the internal UVLO protection feature on the VDD pin supply circuit blocks. Whenever the driver is in UVLO condition when the VDD pin voltage is below the V (ON) supply start threshold, this feature holds the output low, regardless of the status of the inputs. The upper end of this range is driven by the 26-V recommended maximum voltage rating of the VDD pin of the device. The absolute maximum voltage for the VDD pin is 30 V. The UVLO protection feature also involves a hysteresis function. This means that when the VDD pin bias voltage has exceeded the threshold voltage and device begins to operate, and if the voltage drops, then the device continues to deliver normal functionality unless the voltage drop exceeds the hysteresis specification. Therefore, ensuring that, while operating at or near the UVLOrange, the voltage ripple on the auxiliary power supply output is smaller than the hysteresis specification of the device is important to avoid triggering device shutdown. During system shutdown, the device operation continues until the VDD pin voltage has dropped below the VDD UVLO falling threshold which must be accounted for while evaluating system shutdown timing design requirements. Likewise, at system start-up, the device does not begin operation until the VDD pin voltage has exceeded above the VDD UVLO rising threshold. The quiescent current consumed by the internal circuit blocks of the device is supplied through the VDD pin. Although this fact is well known, recognizing that the charge for source current pulses delivered by the OUT pin is also supplied through the same VDD pin is important. As a result, every time a current is sourced out of the output pin (OUT), a corresponding current pulse is delivered into the device through the VDD pin. Thus ensuring that local bypass capacitors are provided between the VDD and GND pins and located as close to the device as possible for the purpose of decoupling is important. A low-ESR, ceramic surface-mount capacitor is needed. TI recommends having two capacitors; a 100-nF ceramic surface-mount capacitorplaced less than 1mm from the VDD pin of the device and another ceramic surface-mount capacitor of few microfarads added in parallel. UCC5710x-Q1 is a high current gate driver. If the gate driver is placed far from the switching power device such as MOSFET then that may create large inductive loop. Large inductive loop may cause excessive ringing on any and all pins of the gate driver. This may result in stress exceeding device recommended rating. Therefore, it is recommended to place the gate driver as close to the switching power device as possible. It is also advisable to use an external gate resistor to damp any ringing due to the high switching currents and board parasitic elements. UCC57108-Q1, UCC57102-Q1 SLUSF94B – DECEMBER 2023 – REVISED JUNE 2024 www.ti.com

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9 Layout

9.1 Layout Guidelines

Proper PCB layout is extremely important in a high-current, fast-switching circuit to provide appropriate device operation and design robustness. The UCC5710x-Q1 gate driver incorporates short propagation delays and powerful output stages capable of delivering large current peaks with very fast rise and fall times at the gate of power switch to facilitate voltage transitions very quickly. Very high di/dt can cause unacceptable ringing if the trace lengths and impedances are not well controlled. The following circuit layout guidelines are recommended when designing with these high-speed drivers.

  • Place the driver device as close as possible to power device to minimize the length of high-current traces between the driver output pins and the gate of the power switch device.
  • Place the bypass capacitors between VDD pin and the GND pin as close to the driver pins as possible to minimize trace length for improved noise filtering. TI recommends having two capacitors; a 100-nF ceramic surface-mount capacitor placed less than 1mm from the VDD pin of the device and another ceramic surface- mount capacitor of few microfarads added in parallel. These capacitors support high peak current being drawn from VDD during turnon of power switch. The use of low inductance surface-mount components such as chip capacitors is highly recommended.
  • The turnon and turn-off current loop paths (driver device, power switch and VDD bypass capacitor) should be minimized as much as possible in order to keep the stray inductance to a minimum. High di/dt is established in these loops at two instances – during turnon and turn-off transients, which induces significant voltage transients on the output pins of the driver device and gate of the power switch.
  • Wherever possible, parallel the source and return traces of a current loop, taking advantage of flux cancellation
  • Separate power traces and signal traces, such as output and input signals.
  • To minimize switch node transients and ringing, adding some gate resistance and/or snubbers on the power devices may be necessary. These measures may also reduce EMI.
  • Star-point grounding is a good way to minimize noise coupling from one current loop to another. The GND of the driver should be connected to the other circuit nodes such as source of power switch, ground of PWM controller, and so forth, at a single point. The connected paths should be as short as possible to reduce inductance and be as wide as possible to reduce resistance.
  • Use a ground plane to provide noise shielding. Fast rise and fall times at OUT pin may corrupt the input signals during transitions. The ground plane must not be a conduction path for any current loop. Instead the ground plane should be connected to the star-point with one trace to establish the ground potential. In addition to noise shielding, the ground plane can help in power dissipation as well.

9.2 Layout Example

Figure 9-1. Layout Example: UCC5710xB-Q1 www.ti.com UCC57108-Q1, UCC57102-Q1 SLUSF94B – DECEMBER 2023 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: UCC57108-Q1 UCC57102-Q1 ADVANCE INFORMATION

10 Device and Documentation Support

10.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

10.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

10.3 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

10.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

10.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (March 2024) to Revision B (June 2024) Page Changes from Revision * (December 2023) to Revision A (March 2024) Page

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. UCC57108-Q1, UCC57102-Q1 SLUSF94B – DECEMBER 2023 – REVISED JUNE 2024 www.ti.com

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www.ti.com 14-Jun-2024 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PUCC57102BQDRQ1 ACTIVE SOIC D 8 3000 TBD Call TI Call TI -40 to 125 Samples PUCC57102CQDRQ1 ACTIVE SOIC D 8 3000 TBD Call TI Call TI -40 to 125 Samples PUCC57102WQDRQ1 ACTIVE SOIC D 8 3000 TBD Call TI Call TI -40 to 125 Samples PUCC57108BQDRQ1 ACTIVE SOIC D 8 3000 TBD Call TI Call TI -40 to 125 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

www.ti.com 14-Jun-2024 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

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