PUCC5304DWV

UCC5304 TI1 | Alldatasheet

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ADVANCE□INFORMATION text VDD UVLO, Level Shift and Control Logic VCC2 IN VCCI GND ISOLATION BARRIER UVLO and Input Logic Rest of Circuit Copyright © 2019, Texas Instruments Incorporated OUT VSS Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. UCC5304 SLUSDV5A –OCTOBER 2019–REVISED FEBRUARY 2020 UCC53044-ASource,6-ASinkSingle-ChannelReinforcedIsolationGateDriver WithHighNoiseImmunity

1 Features

1• Reinforced isolation

• Single channel in DWV Package with 8.5mm creepage distance
• CMTI greater than 100-V/ns
• 4-A peak source, 6-A peak sink output
• Switching parameters: – 40-ns maximum propagation delay – 5-ns maximum delay matching – 5.5-ns maximum pulse-width distortion – 35-µs maximum VDD power-up delay
• Up to 18-V VDD output drive supply – 5-V VDD UVLO
• Operating temp. range (TA) –40°C to 125°C
• Rejects input pulses shorter than 5-ns
• TTL and CMOS compatible inputs
• Safety-related certifications: – 7000-VPK reinforced isolation per DIN V VDE V 0884-11:2017-01 (planned) – 5000-VRMS isolation for 1 minute per UL 1577 (Planned) – CQC certification per GB4943.1-2011 (planned)

2 Applications

• AC-DC and DC-DC converters
• Motor drives
• Industrial transportation and robotics

3 Description

The UCC5304 device is an isolated single-channel gate driver with 4-A peak-source and 6-A peak-sink current. It is designed to drive power MOSFETs and GaNFETs in PFC, Isolated AC/DC, DC/DC, and synchronous rectification applications, with fast switching performance and robust ground bounce protection through greater than 100-V/ns common- mode transient immunity (CMTI). The UCC5304 is available in a 8.5 mm SOIC-8 (DWV) package and can support isolation voltage up to 5-kVRMS. Compared to an optocoupler, the UCC5304 family has lower part-to-part skew, lower propagation delay, higher operating temperature, and higher CMTI. Protection features include: IN pin rejects input transient shorter than 5-ns; both input and output can withstand –2-V spikes for 200-ns, both supplies have undervoltage lockout (UVLO), and active pull down protection clamps the output below 2.1-V when unpowered or floated. With these features, this device enables high efficiency, high power density, and robustness in a wide variety of power applications. Device Information(1) PART NUMBER PACKAGE UVLO UCC5304 DWV-8 (SOIC) 5-V (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application

ADVANCE□INFORMATION UCC5304 SLUSDV5A –OCTOBER 2019–REVISED FEBRUARY 2020 www.ti.com Product Folder Links: UCC5304 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Table of Contents

12 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (October 2019) to Revision A Page

ADVANCE□INFORMATION 1IN 8 VDD 2VCCI 7 OUT 3VCCI 6 VSS 4GND 5 VSS Not to scale ISOLATION UCC5304 www.ti.com SLUSDV5A –OCTOBER 2019–REVISED FEBRUARY 2020 Product Folder Links: UCC5304 Submit Documentation FeedbackCopyright © 2019–2020, Texas Instruments Incorporated (1) P = power, G = ground, I = input, O = output

5 Pin Configuration and Functions

PIN I/O(1) DESCRIPTION GND 4 P Primary-side ground reference. All signals in the primary side are referenced to this ground. IN 1 I Input signal. IN input has a TTL/CMOS compatible input threshold. This pin is pulled low internally if left open. It is recommended to tie this pin to ground if not used to achieve better noise immunity. OUT 7 O Output of driver. Connect to the gate of the FET or IGBT. VCCI 2, 3 P Primary-side supply voltage. Locally decoupled to GND using a low ESR/ESL capacitor located as close to the device as possible. VDD 8 P Secondary-side power for driver. Locally decoupled to VSS using a low ESR/ESL capacitor located as close to the device as possible. VSS 5, 6 P Ground for secondary-side driver.

ADVANCE□INFORMATION UCC5304 SLUSDV5A –OCTOBER 2019–REVISED FEBRUARY 2020 www.ti.com Product Folder Links: UCC5304 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Values are verified by characterization and are not production tested. (3) To maintain the recommended operating conditions for TJ, see the Thermal Information .

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Input bias pin supply voltage VCCI to GND –0.5 6 V Driver bias supply VDD-VSS –0.5 20 V Output signal voltage OUT to VSS –0.5 VVDD+0.5 V OUT to VSS, Transient for 200 ns(2) –2 VVDD+0.5 V Input signal voltage IN to GND –0.5 VVCCI+0.5 V IN Transient to GND for 200ns(2) –2 VVCCI+0.5 V Junction temperature, TJ (3) –40 150 °C Storage temperature, Tstg –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 VCharged-device model (CDM), per JEDEC specification JESD22- C101(2) ±1500

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCCI VCCI Input supply voltage 3 5.5 V VDD Driver output bias supply 6.0 18 V TJ Junction Temperature –40 130 °C TA Ambient Temperature –40 125 °C

ADVANCE□INFORMATION UCC5304 www.ti.com SLUSDV5A –OCTOBER 2019–REVISED FEBRUARY 2020 Product Folder Links: UCC5304 Submit Documentation FeedbackCopyright © 2019–2020, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.4 Thermal Information

THERMAL METRIC(1) DWV (SOIC) UNIT

8 PINS

RθJA Junction-to-ambient thermal resistance 108.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 52.0 °C/W RθJB Junction-to-board thermal resistance 58.6 °C/W ψJT Junction-to-top characterization parameter 32.7 °C/W ψJB Junction-to-board characterization parameter 56.6 °C/W

6.5 Power Ratings

PD Power dissipation VCCI= 5.0 V; VDD = 12 V; IN = 3.3-V, 2.36- MHz 50% duty cycle square wave; 1.0-nF load on OUT 0.700 W PDI Power dissipation by transmitter side 0.015 W PDO Power dissipation by driver side 0.685 W

ADVANCE□INFORMATION UCC5304 SLUSDV5A –OCTOBER 2019–REVISED FEBRUARY 2020 www.ti.com Product Folder Links: UCC5304 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated (1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications. (2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits. (3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier. (4) Apparent charge is electrical discharge caused by a partial discharge (pd). (5) All pins on each side of the barrier tied together creating a two-pin device.

6.6 Insulation Specifications

PARAMETER TEST CONDITIONS VALUE UNIT CLR External clearance(1) Shortest pin-to-pin distance through air > 8.5 mm CPG External creepage(1) Shortest pin-to-pin distance across the package surface > 8.5 mm DTI Distance through the insulation Minimum internal gap (internal clearance) > 17 µm CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 > 600 V Material group According to IEC 60664-1 I Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 600 VRMS I-IV Rated mains voltage ≤ 1000 VRMS I-III DIN V VDE V 0884-11:2017-01(2) VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 1500 VPK VIOWM Maximum working isolation voltage AC voltage (sine wave); time dependent dielectric breakdown (TDDB) test; 1060 VRMS DC Voltage 1500 VDC VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60 s (qualification); VTEST = 1.2 × VIOTM, t = 1 s (100% production) 7000 VPK VIOSM Maximum surge isolation voltage(3) Test method per IEC 62368-1, 1.2/50 μs waveform, VTEST = 1.6 × VIOSM (qualification) 8000 VPK qpd Apparent charge(4) Method a, After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM, tm = 10 s ≤ 5 pC Method a, After environmental tests subgroup 1, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM = 2400 VPK, tm = 10 s ≤ 5 Method b1; At routine test (100% production) and preconditioning (type test) Vini = 1.2 × VIOTM; tini = 1 s; Vpd(m) = 1.875 × VIORM = 2813 VPK, tm = 1 s ≤ 5 CIO Barrier capacitance, input to output(5) VIO = 0.4 sin (2πft), f =1 MHz 0.5 pF RIO Isolation resistance, input to output(5) VIO = 500 V at TA = 25°C > 1012 ΩVIO = 500 V at 100°C ≤ TA ≤ 125°C > 1011 VIO = 500 V at TS =150°C > 109 Pollution degree 2 Climatic category 40/125/21 UL 1577 VISO Withstand isolation voltage VTEST = VISO = 5700 VRMS, t = 60 s. (qualification), VTEST = 1.2 × VISO = 6840 VRMS, t = 1 s (100% production) 5000 VRMS

ADVANCE□INFORMATION UCC5304 www.ti.com SLUSDV5A –OCTOBER 2019–REVISED FEBRUARY 2020 Product Folder Links: UCC5304 Submit Documentation FeedbackCopyright © 2019–2020, Texas Instruments Incorporated

6.7 Safety-Related Certifications

Plan to certify according to DIN V VDE V 0884-11:2017-01 Plan to be recognized under UL 1577 Component Recognition Program Plan to certify according to GB 4943.1-2011 (1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be exceeded. These limits vary with the ambient temperature, TA. The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages. Use these equations to calculate the value for each parameter: TJ = TA + RθJA × P, where P is the power dissipated in the device. TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature. PS = IS × VI, where VI is the maximum input voltage.

6.8 Safety-Limiting Values

Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. PARAMETER TEST CONDITIONS SIDE MIN TYP MAX UNIT IS Safety output supply current RθJA = 108.5ºC/W, VVDD = 12 V, TJ = 150°C, TA = 25°C See DRIVER side 96 mA PS Safety supply power RθJA = 108.5ºC/W, VVCCI = 5.5 V, TJ = 150°C, TA = 25°C See INPUT side 0.015 WDRIVER side 1.135 TOTAL 1.150 TS Safety temperature(1) 150 °C

ADVANCE□INFORMATION UCC5304 SLUSDV5A –OCTOBER 2019–REVISED FEBRUARY 2020 www.ti.com Product Folder Links: UCC5304 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated (1) Current direction in the testing conditions are defined to be positive into the pin and negative out of the specified terminal (unless otherwise noted). (2) Parameters that has only typical values, are not production tested and guaranteed by design.

6.9 Electrical Characteristics

VVCCI = 3.3 V or 5.0 V, 0.1-µF capacitor from VCCI to GND and 1uF capacitor from VDD to VSS, VVDD = 12 V, 1-µF capacitor from VDD to VSS, TA = –40°C to +125°C, unless otherwise noted(1)(2). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENTS IVCCI VCCI quiescent current VIN = 0 V 1.5 2.0 mA IVDD VDD quiescent current VIN = 0 V, 1.0 1.8 mA IVCCI VCCI operating current (f = 500 kHz) current per channel 2.5 mA IVDD VDD operating current (f = 500 kHz) current per channel, COUT = 100 pF, VVDD = 12 V 2.5 mA VCC SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS VVCCI_ON UVLO Rising threshold 2.55 2.7 2.85 V VVCCI_OFF UVLO Falling threshold 2.35 2.5 2.65 V VVCCI_HYS UVLO Threshold hysteresis 0.2 V VDD SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS VVDD UVLO Rising threshold 5.0 5.5 5.9 V VVDD_OFF UVLO Falling threshold 4.7 5.2 5.6 V VVDD_HYS UVLO Threshold hysteresis 0.3 V IN VINH Input high threshold voltage 1.6 1.8 2 V VINL Input low threshold voltage 0.8 1 1.25 V VIN_HYS Input threshold hysteresis 0.8 V OUTPUT IO+ Peak output source current CVDD = 10 µF, CLOAD = 0.18 µF, f = 1 kHz, bench measurement 4 A IO- Peak output sink current CVDD = 10 µF, CLOAD = 0.18 µF, f = 1 kHz, bench measurement 6 A ROH Output resistance at high state IOUT = –10 mA, ROHA, ROHB do not represent drive pull-up performance. See tRISE in Switching Characteristics and Output Stage for more details. 5 Ω ROL Output resistance at low state IOUT = 10 mA 0.55 Ω VOH Output voltage at high state VVDD = 12 V, IOUT = –10 mA 11.95 V VOL Output voltage at low state VVDD = 12 V, IOUT = 10 mA 5.5 mV VOAPD Driver output (VOUT) active pull down VVDD, IOUT = 200 mA 1.75 2.1 V

ADVANCE□INFORMATION UCC5304 www.ti.com SLUSDV5A –OCTOBER 2019–REVISED FEBRUARY 2020 Product Folder Links: UCC5304 Submit Documentation FeedbackCopyright © 2019–2020, Texas Instruments Incorporated (1) Parameters that has only typical values, are not production tested and guaranteed by design.

6.10 Switching Characteristics

VVCCI = 3.3 V or 5.5 V, 0.1-µF capacitor from VCCI to GND, VVDD = 12 V, 1-µF capacitor from VDD and VSS, load capacitance COUT = 0 pF, TJ = –40°C to +125°C, unless otherwise noted(1). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tRISE Output rise time, see Figure 17 CVDD = 10 µF, COUT = 1.8 nF, VVDD = 12 V, f = 1 kHz 5 16 ns tFALL Output fall time, see Figure 17 CVDD = 10 µF, COUT = 1.8 nF , VVDD = 12 V, f = 1 kHz 6 12 ns tPWmin Minimum input pulse width that passes to output, see and Output does not change the state if input signal less than tPWmin 10 20 ns tPDHL Propagation delay at falling edge, see INx high threshold, VINH, to 10% of the output 28 40 ns tPDLH Propagation delay at rising edge, see INx low threshold, VINL, to 90% of the output 28 40 ns tPWD Pulse width distortion in each channel, see |tPDLH – tPDHL| 5.5 ns tVCCI+ to OUT VCCI Power-up Delay Time: UVLO Rise to OUT, See Figure 18 IN tied to VCCI 40 59 µs tVDD+ to OUT VDD Power-up Delay Time: UVLO Rise to OUT See Figure 19 INtied to VCCI 22 35 |CMH| High-level common-mode transient immunity (See ) Slew rate of GND vs. VSS, IN is tied to GND or VCCI; VCM=1000 V; 100 V/ns |CML| Low-level common-mode transient immunity (See ) Slew rate of GND vs. VSS, IN is tied to GND or VCCI; VCM=1000 V; 100

6.11 Typical Characteristics

VDD = 12 V, VCCI = 3.3 V or 5.0 V, TA = 25°C, CL=0pF unless otherwise noted. Figure 1. VCCI Quiescent Current Figure 2. VCCI Operating Current - IVCCI Figure 3. VCCI Operating Current vs. Frequency Figure 4. VDD Quiescent Current (IVDD) Figure 5. VDD Channel Operating Current (IVDD) Figure 6. Per Channel Operating Current (IVDD) vs.

7 Parameter Measurement Information

7.1 Rising and Falling Time

Figure 17. Rising and Falling Time Criteria

7.2 Power-up UVLO Delay to OUTPUT

UVLO delay timing diagram for VCCI and VDD. ensure safe operation during VCCI or VDD brownouts. Figure 18. VCCI Power-up UVLO Delay Figure 19. VDD Power-up UVLO Delay

ADVANCE□INFORMATION 200 k: UVLO VCCI 7 5,6 Driver VDD OUT VSS UVLO DEMODMOD GND IN VCCI Deglitch Filter BarrierIsolation 2,3 UCC5304 SLUSDV5A –OCTOBER 2019–REVISED FEBRUARY 2020 www.ti.com Product Folder Links: UCC5304 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

In order to switch power transistors rapidly and reduce switching power losses, high-current gate drivers are often placed between the output of control devices and the gates of power transistors. There are several instances where controllers are not capable of delivering sufficient current to drive the gates of power transistors. This is especially the case with digital controllers, since the input signal from the digital controller is often a 3.3-V logic signal capable of only delivering a few mA. The UCC5304 is a flexible gate driver that can be configured to fit a variety of power supply and motor drive topologies, as well as drive several types of transistors. UCC5304 has many features that allow it to integrate well with control circuitry and protect the gates it drives such as under voltage lock-out (UVLO) for both input and output voltages. The UCC5304 holds its output low when the input is left open or when the input pulse is not wide enough. The driver input pin is CMOS and TTL compatible for interfacing with digital and analog power controllers alike.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)

upper PMOS is resistively held off by RHi-Z while the lower NMOS gate is tied to the driver output through RCLAMP. typically around 1.5V, when no bias power is available. Figure 20. Simplified Representation of Active Pull Down Feature bound to happen when the device starts switching and operating current consumption increases suddenly. Table 1. VCCI UVLO Feature Logic

Table 2. VDD UVLO Feature Logic

8.3.2 Input Stage

pin low. This resistance is typically 200 kΩ (see Functional Block Diagram). MOSFET/IGBT gate. That said, the amplitude of any signal applied to IN must not exceed VCCI.

8.3.3 Output Stage

of this N-channel MOSFET (RNMOS) is approximately 1.47 Ω when activated. Figure 21. Output Stage

8.4 Device Functional Modes

UVLO operation modes. Table 3 lists the UCC5304's functional modes. Table 3. INPUT/OUTPUT Logic Table

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

more robust designs for enterprise, telecom, automotive, and industrial applications with a faster time to market.

9.2 Typical Application

synchronous boost, half-bridge/full bridge isolated topologies, and 3-phase motor drive applications. Figure 22. Typical Application Schematic

9.2.1 Design Requirements

Table 4 lists reference design parameters for an example application: UCC5304 driving a 650-V MOSFET. Table 4. UCC5304 Design Requirements

9.2.2 Detailed Design Procedure

9.2.2.1 Designing IN pin Input Filter

non-ideal layout or long PCB traces. example, an RIN = 51 Ω and a CIN = 33 pF are selected, with a corner frequency of approximately 100 MHz.

9.2.2.2 Estimating Junction Temperature

• TC is the UCC5304 case-top temperature measured with a thermocouple or some other instrument, ψJT is the junction-to-top characterization parameter from the Thermal Information table. Importantly, ψJT is developed based on JEDEC standard PCB board and it is subject to change when the PCB board layout is different. For more information, please visit application report - semiconductor and IC package thermal metrics. (1) Using the junction-to-top characterization parameter (ΨJT) instead of the junction-to-case thermal resistance (RΘJC) can greatly improve the accuracy of the junction temperature estimation. The majority of the thermal energy of most ICs is released into the PCB through the package leads, whereas only a small percentage of the total energy is released through the top of the case (where thermocouple measurements are usually conducted). RΘJC can only be used effectively when most of the thermal energy is released through the case, such as with metal packages or when a heatsink is applied to an IC package. In all other cases, use of RΘJC will inaccurately estimate the true junction temperature. ΨJT is experimentally derived by assuming that the amount of energy leaving through the top of the IC will be similar in both the testing environment and the application environment. As long as the recommended layout guidelines are observed, junction temperature estimates can be made accurately to within a few degrees Celsius. For more information, see the Layout Guidelines and Semiconductor and IC Package Thermal Metrics application report.

9.2.2.3 Selecting VCCI and VDD Capacitors

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9.2.2.3.1 Selecting a VCCI Capacitor

A bypass capacitor connected to VCCI supports the transient current needed for the primary logic and the total current consumption, which is only a few mA. Therefore, a 25-V MLCC with over 100 nF is recommended for this application. If the bias power supply output is a relatively long distance from the VCCI pin, a tantalum or electrolytic capacitor, with a value over 1 µF, should be placed in parallel with the MLCC.

9.2.2.3.2 Selecting a VDD Capacitor

A 50-V, 10-µF MLCC and a 50-V, 220-nF MLCC are chosen for CVDD. If the bias power supply output is a relatively long distance from the VDD pin, a tantalum or electrolytic capacitor with a value over 10 µF, should be used in parallel with CVDD.

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10 Power Supply Recommendations

The recommended input supply voltage (VCCI) for UCC5304 is between 3 V and 5.5 V. The output bias supply voltage (VDD) range from 9.2V to 18V. The lower end of this bias supply range is governed by the internal under voltage lockout (UVLO) protection feature of each device. One mustn’t let VDD or VCCI fall below their respective UVLO thresholds (For more information on UVLO see VDD, VCCI, and Under Voltage Lock Out (UVLO)). The upper end of the VDD range depends on the maximum gate voltage of the power device being driven by UCC5304. The UCC5304 has a recommended maximum VDD of 18 V. A local bypass capacitor should be placed between the VDD and VSS pins. This capacitor should be positioned as close to the device as possible. A low ESR, ceramic surface mount capacitor is recommended. It is further suggested that one place two such capacitors: one with a value of ≈10-µF for device biasing, and an additional ≤100-nF capacitor in parallel for high frequency filtering.. Similarly, a bypass capacitor should also be placed between the VCCI and GND pins. Given the small amount of current drawn by the logic circuitry within the input side of UCC5304, this bypass capacitor has a minimum recommended value of 100 nF.

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11 Layout

11.1 Layout Guidelines

Consider these PCB layout guidelines for in order to achieve optimum performance for the UCC5304.

11.1.1 Component Placement Considerations

• Low-ESR and low-ESL capacitors must be connected close to the device between the VCCI and GND pins and between the VDD and VSS pins to support high peak currents when turning on the external power transistor.
• To avoid large negative transients on the switch node VSS pin in a half-bridge application, the parasitic inductances between the source of the top transistor and the source of the bottom transistor must be minimized.

11.1.2 Grounding Considerations

• It is essential to confine the high peak currents that charge and discharge the transistor gates to a minimal physical area. This will decrease the loop inductance and minimize noise on the gate terminals of the transistors. The gate driver must be placed as close as possible to the transistors.

11.1.3 High-Voltage Considerations

• To ensure isolation performance between the primary and secondary side, one should avoid placing any PCB traces or copper below the driver device. A PCB cutout is recommended in order to prevent contamination that may compromise the UCC5304 isolation performance.
• For half-bridge, or high-side/low-side configurations, one should try to increase the clearance distance of the PCB layout between the high and low-side PCB traces.

11.1.4 Thermal Considerations

• A large amount of power may be dissipated by the UCC5304 if the driving voltage is high, the load is heavy, or the switching frequency is high (Refer to for more details). Proper PCB layout can help dissipate heat from the device to the PCB and minimize junction to board thermal impedance (θJB).
• Increasing the PCB copper connecting to VDD and VSS pins is recommended, with priority on maximizing the connection to VSS (See and ). However, high voltage PCB considerations mentioned above must be maintained.
• If there are multiple layers in the system, it is also recommended to connect the VDD and VSS pins to internal ground or power planes through multiple vias of adequate size. Ensure that no traces or coppers from different high-voltage planes overlap.

11.2 Layout Example

Figure 23 shows a 2-layer PCB layout example. Figure 23. Layout Example

12 Mechanical, Packaging, and Orderable Information

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com PACKAGE OUTLINE C TYP 11.5 0.25

2.8 MAX

TYP0.33 0.13 6X 1.27 8X 0.51 0.31 3.81 0.46 0.36 1.0 0.5 0.25 GAGE PLANE A NOTE 3 5.95 5.75 B NOTE 4 7.6 7.4 (2.286) (2) 4218796/A 09/2013 SOIC - 2.8 mm max heightDWV0008A SOIC NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side. 1 8

0.25 C A B

0.1 C SEE DETAIL A TYPICAL DETAIL A SCALE 2.000 ADVANCE□INFORMATION UCC5304 www.ti.com SLUSDV5A –OCTOBER 2019–REVISED FEBRUARY 2020 Product Folder Links: UCC5304 Submit Documentation FeedbackCopyright © 2019–2020, Texas Instruments Incorporated

www.ti.com EXAMPLE BOARD LAYOUT (10.9)

0.07 MAX

0.07 MIN

8X (1.8) 8X (0.6) 6X (1.27) 4218796/A 09/2013 SYMM SOIC - 2.8 mm max heightDWV0008A SOIC SYMM SEE DETAILS 9.1 mm NOMINAL CLEARANCE/CREEPAGE LAND PATTERN EXAMPLE SCALE:6X NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED OPENING SOLDER MASK DETAILS SOLDER MASK METAL SOLDER MASK DEFINED ADVANCE□INFORMATION UCC5304 SLUSDV5A –OCTOBER 2019–REVISED FEBRUARY 2020 www.ti.com Product Folder Links: UCC5304 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated

www.ti.com EXAMPLE STENCIL DESIGN 8X (1.8) 8X (0.6) 6X (1.27) (10.9) 4218796/A 09/2013 SOIC - 2.8 mm max heightDWV0008A SOIC NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X SYMM SYMM ADVANCE□INFORMATION UCC5304 www.ti.com SLUSDV5A –OCTOBER 2019–REVISED FEBRUARY 2020 Product Folder Links: UCC5304 Submit Documentation FeedbackCopyright © 2019–2020, Texas Instruments Incorporated

www.ti.com 12-Mar-2020 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PUCC5304DWV ACTIVE SOIC DWV 8 64 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com PACKAGE OUTLINE C TYP 11.5 0.25 TYP0.33 0.13 0 -8 6X 1.27 8X 0.51 0.31 3.81 0.46 0.36 1.0 0.5 0.25 GAGE PLANE A NOTE 3 5.95 5.75 B NOTE 4 7.6 7.4 (2.286) (2) 4218796/A 09/2013 SOIC - 2.8 mm max heightDWV0008A SOIC NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side. 1 8 0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 2.000

www.ti.com EXAMPLE BOARD LAYOUT (10.9) 8X (1.8) 8X (0.6) 6X (1.27) 4218796/A 09/2013 SOIC - 2.8 mm max heightDWV0008A SOIC SYMM SYMM SEE DETAILS LAND PATTERN EXAMPLE 9.1 mm NOMINAL CLEARANCE/CREEPAGE SCALE:6X NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS OPENING SOLDER MASK METAL SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 8X (1.8) 8X (0.6) 6X (1.27) (10.9) 4218796/A 09/2013 SOIC - 2.8 mm max heightDWV0008A SOIC NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X SYMM SYMM

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