PUCC34141

Texas Instruments

UCC34141-Q1 Automotive 1.5W, 12V VIN, 25V VOUT, High-Density, > 5kVRMS, Isolated DC/DC Module REVISED AUGUST 2025

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UCC34141-Q1 Automotive 1.5W, 12V VIN, 25V VOUT, High-Density, > 5kVRMS, Isolated DC/DC Module

1 Features

Fully integrated high-density isolated DC/DC module with isolation planar transformer
Wide input range: 5.5V to 28V (with 22V OVLO) – ≥ 0.6W typical output for 6V ≤ VVIN ≤ 7V, and ≥ 0.5W for VVIN = 5.5V, at TA ≤ 85°C – ≥ 1.3W typical output for 8V ≤ VVIN ≤ 18V, 18V ≤ VVDD-COM ≤ 20V, at TA ≤ 85°C – ≥ 1.5W typical output for 11V ≤ VVIN ≤ 13V, 18V ≤ VVDD-COM ≤ 20V, at TA ≤ 85°C – ≥1.2W typical output for 11V ≤ VVIN ≤ 13V, 15V ≤ VVDD-COM < 18V, at TA ≤ 85°C
Programmable (VDD – COM) output voltage – 15V to 20V, ≤ ±1.5% total regulation accuracy
Programmable (VEE – COM) output voltage – -2V to -8V, ≤ ±5% total regulation accuracy
Adaptive spread spectrum modulation (SSM)
Strong magnetic and radiated field immunities
Reduced inrush current soft-start
ENA pin for logic enable and programming input UVLO
Open-drain PG for fault indicator, power good
Integrated protections: UVLO, OVLO, short-circuit, OVP, UVP, and thermal shutdown.
< 3pF isolation capacitance
Static and dynamic CMTI > ±250kV/µs
AEC-Q100 qualified for automotive applications – Temperature grade 1:–40°C ≤ TA ≤ 125°C
Safety-related certifications (Planned): – Reinforced isolation per DIN EN IEC 60747-17 (VDE 0884-17) – UL 1577 / CSA component recognition program
16-pin, wide body SOIC package

2 Applications

Hybrid, electric and power train system (EV/HEV) – Inverter and motor control – On-board (OBC) and wireless charger – DC/DC converter
Grid infrastructure – EV charging station power module – DC charging (pile) station – String inverter
Industrial transport – Off-highway vehicle electric drive
Power Delivery – Rack and Server Power

3 Description

The UCC34141-Q1 is an automotive qualified high isolation voltage DC/DC power module designed to provide power to SiC and IGBT isolated gate drivers. Its proprietary integrated transformer, flip-chip package, and advanced control architectures achieve high power density, low noise, and lowest system BOM. This device is capable of delivering 1.5W typical output power at 85 oC ambient temperature. The highly accurate dual-output voltages, easily set by resistor dividers, enable low on-resistance, fast and reliable switching for SiC/IGBT. The low-latency feedback control reduces the output capacitance for fast load transient and supports dynamic voltage programming. The wide input voltage and adjustable VIN UVLO supports both wide battery voltage of electric vehicles and regulated input rails. It is operational from 5.5V to 20V VIN, and can withstand VIN overvoltage transient up to 28V. The integrated protection features, fault-report PG pin, and enable function increase system robustness and save external components. The SOIC package with 8.2mm creepage and clearance distance ensures high isolation capability. Device Information ORDERABLE PART NUMBER PACKAGE(1) BODY SIZE (NOM) PUCC34141 QDHARQ1 DHA (SSOP, 16) 5.85mm × 7.50mm (1) For all available packages, see Section 11. ENA GNDP VDD BSW FBVDD FBVEE COM ENA VIN COM VDD Isolation barrier PG CIN VIN VEE R2L CVDD CVDD_GD CVEE_GD VEE Source/ Emitter PG CVEE Simplified Application Typical Power-up Sequence ADVANCE INFORMATION UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.

11 Mechanical, Packaging, and Orderable

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4 Device Comparison

Table 4-1. Device Comparison Table DEVICE NAME VVIN RANGE OUTPUT (VDD-COM) ADJUSTABLE RANGE OUTPUT (VEE-COM) ADJUSTABLE RANGE TYPICAL POWER POWER GOOD (PG) ACTIVE POLARITY FAULT RESPONSE UCC34141-Q1 8V to 20V 18V to 20V -2V to -8V 1.5W LOW LATCH-OFF15V to 18V -2V to -8V ≥1W 5.5V to 8V 15V to 20V -2V to -8V ≥0.3W www.ti.com UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: UCC34141-Q1 ADVANCE INFORMATION

5 Pin Configuration and Functions

Figure 5-1. DHA Package, 16-Pin SSOP (Top View) Table 5-1. Pin Functions PIN TYPE (1) DESCRIPTION NAME NO. ENA 1 I Enable pin. Forcing ENA LOW disables the device. Pull HIGH to enable normal device functionality. 5.5V recommended maximum. Can be used to program input UVLO with a resistor divider from VIN. PG 2 O Active low power-good open-drain output pin. PG remains low when VVIN_UVLOP ≤ VVIN ≤ VVIN_OVLOP; VVDD_UVP ≤ VFBVDD ≤ VVDD_OVP; VVEE_UVP ≤ VFBVEE ≤ VVEE_OVP; TJ_Primary ≤ TSHUT_P_R; and TJ_secondary ≤ TSHUT_S_R. Connect a decoupling capacitor in 0402 body size for by-passing the high frequency noise. It must be next to the power-good pin on the same side of the PCB as the IC. VIN 3, 4 P Primary input voltage. Connect a 10µF and a parallel 0.1µF ceramic capacitor from VIN to GNDP. The 0.1µF ceramic capacitor in 0402 body size is for by-passing the high frequency noise and must be next to the VIN and GNDP pins on the same side of the PCB as the IC. GNDP 5, 6, 7, 8 G Primary-side ground connection for VIN. Place several vias to copper pours for thermal relief. See the "Layout" section for more details. COMA 9 G Secondary-side analog sense reference connection for the noise sensitive analog feedback input FBVDD, and FBVEE. Connect the low-side FBVDD feedback resistor and high frequency decoupling filter capacitors close to the COMA pin and respective feedback pin FBVDD. Connect to secondary-side gate drive voltage reference, COM. Use a single point connection and place the high frequency decoupling ceramic capacitor close to the COMA pin. COM 10, 11 G Secondary ground. Connect to Source of power switch. VDD 12 P Secondary-side isolated output voltage from transformer. Connect a 10µF and a parallel 0.1µF ceramic capacitor from VDD to COM. The 0.1µF ceramic capacitor in 0402 body size is for bypassing high frequency noise and must be next to the VDD and COM pins. BSW 13 P Internal buck-boost converter switch pin. Connect an inductor from this pin to COM. Recommend a 3.3µH to 10µH chip inductor. VEE 14 P Secondary-side isolated output voltage for negative rail. Connect a 2.2µF ceramic capacitor from VEE to COM for bypassing high frequency noise. FBVDD 15 I Feedback (VDD – COM) output voltage sense pin and to adjust the output (VDD – COM) voltage. Connect a resistor divider from VDD to COMA so that the midpoint is connected to FBVDD. The equivalent FBVDD voltage is regulated at 2.5V with the internal hysteresis control across isolation. Adding a 220pF ceramic capacitor for high frequency decoupling in parallel with the low-side feedback resistor is needed. The 220pF ceramic capacitor for high frequency bypass must be next to the FBVDD and COMA pins on top layer or back layer connected with vias. UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 www.ti.com

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Table 5-1. Pin Functions (continued) PIN TYPE (1) DESCRIPTION NAME NO. FBVEE 16 I Feedback (COM – VEE) output voltage sense pin used to adjust the output (COM – VEE) voltage. Connect one feedback resistor, 40kΩ to 160kΩ, to VEE to program the (COM – VEE) voltage from 2V to 8V. The equivalent FBVEE voltage is regulated close to 0V with the internal hysteresis control. Connect a 10pF ceramic capacitor from FBVEE to COMA for bypassing high frequency noise. The 10pF ceramic capacitor must be next to the FBVEE pin on top layer or back layer connected with vias. (1) P = power, G = ground, I = input, O = output www.ti.com UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: UCC34141-Q1 ADVANCE INFORMATION

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN TYP MAX UNIT VVIN VIN to GNDP –0.3 30 V VENA, VPG ENA, PG to GNDP –0.3 7 V VBSW-COM, VFBVEE-COM BSW, FBVEE to COM -10 25.5 V VBSW-VEE BSW to VEE -0.7 32 V VBSW-VEE_tran BSW to VEE (0.24ns transient) -2.1 33.4 V VCOM-VEE COM to VEE -0.3 10 V VVDD-COM, VFBVDD-COM VDD, FBVDD to COM –0.3 25.5 V VVDD-VEE VDD to VEE –0.3 32 V POUT_VDD_MAX Total output power at TA=25°C 3 W TJ Operating junction temperature range –40 150 °C Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 V Charged-device model (CDM), per AEC Q100-011 Section 7.2 ±750 V (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN TYP MAX UNIT VVIN Primary-side input voltage to GNDP during continuous operation 5.5(1) 12 20 V VVIN Primary-side input voltage to GNDP during overvoltage transient 28 V VENA Enable to GNDP 0 5.5 V VPG Powergood to GNDP 0 5.5 V VVDD-COM VDD to COM 15 18 20 V VVDD-VEE VDD to VEE 15 22 25 V VCOM-VEE COM to VEE 2 4 8 V TA Ambient temperature –40 125 °C TJ (2) Junction temperature –40 150 °C (1) See the VVIN_UVLO_R and VVIN_ UVLO_F electrical characteristics for the miminum operational VVIN. (2) See the (VDD-COM) and (COM-VEE) Load Recommended Operating Area section for maximum rated values across temperature and VVIN conditions for different (VDD-COM) and (COM-VEE) output voltage settings. UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 www.ti.com

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6.4 Thermal Information

THERMAL METRIC(1) UNITDHA (SOIC)

16 PINS

RθJA Junction-to-ambient thermal resistance 63.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 32.3 °C/W RθJB Junction-to-board thermal resistance 20.1 °C/W ΨJA Junction-to-ambient characterization parameter 47.8 °C/W ΨJB Junction-to-board characterization parameter 20.5 °C/W ΨJT Junction-to-top characterization parameter 3 °C/W (1) The thermal resistances (R) are based on JEDEC board, and the characterization parameters (Ψ) are based on the EVM described in the Layout section. For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Insulation Specifications

PARAMETER TEST CONDITIONS VALUE UNIT General CLR External clearance (1) Shortest terminal-to-terminal distance through air > 8.2 mm CPG External creepage (1) Shortest terminal-to-terminal distance across the package surface > 8.2 mm DTI Distance through the insulation Minimum internal gap (internal clearance – transformer power isolation) > 70 µm CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 > 600 V Material group According to IEC 60664-1 I Overvoltage category Rated mains voltage ≤ 300VRMS I-IV Rated mains voltage ≤ 600VRMS I-IV Rated mains voltage ≤ 1000VRMS I-III DIN EN IEC 60747-17 (VDE 0884-17) (Planned Certification Targets) (2) VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 1700 VPK VIOWM Maximum working isolation voltage AC voltage (sine wave) Time dependent dielectric breakdown (TDDB) test 1202 VRMS DC voltage 1700 VDC VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60s (qualification); VTEST = 1.2 × VIOTM, t = 1s (100% production) 7071 VPK VIMP Maximum impulse voltage (3) Tested in air, 1.2/50μs waveform per IEC 62368-1 8000 VPK VIOSM Maximum surge isolation voltage (3) VIOSM ≥ 1.3 × VIMP; Tested in oil (qualification test), 1.2/50µs waveform per IEC 62368-1 10400 VPK qpd Apparent charge (4) Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60s; Vpd(m) = 1.2 × VIORM, tm = 10s ≤ 5 pC Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60s; Vpd(m) = 1.6 × VIORM, tm = 10s ≤ 5 pC Method b1: At routine test (100% production), Vini = 1.2 × VIOTM, tini = 1s; Vpd(m) = 1.875 × VIORM, tm = 1s ≤ 5 pC CIO Barrier capacitance, input to output (5) VIO = 0.4 sin (2πft), f = 1MHz < 3 pF RIO Isolation resistance, input to output (5) VIO = 500V, TA = 25°C > 1012 Ω VIO = 500V, 100°C ≤ TA ≤ 125°C > 1011 Ω VIO = 500V at TS = 150°C > 109 Ω Pollution degree 2 www.ti.com UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: UCC34141-Q1 ADVANCE INFORMATION

6.5 Insulation Specifications (continued)

PARAMETER TEST CONDITIONS VALUE UNIT Climatic category 40/125/21 UL 1577 (Planned Certification Target) VISO Withstand isolation voltage VTEST = VISO = 5000VRMS, t = 60s (qualification); VTEST = 1.2 × VISO = 6000VRMS, t = 1s (100% production)

5000 VRMS

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed-circuit board are used to help increase these specifications. (2) This coupler is suitable for safe electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits. (3) Testing is carried out in air to determine the surge immunity of the package. Testing is carried out in oil to determine the intrinsic surge immunity of the isolation barrier. (4) Apparent charge is electrical discharge caused by a partial discharge (pd). (5) All pins on each side of the barrier tied together creating a two-terminal device.

6.6 Electrical Characteristics

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6.6 Electrical Characteristics (continued)

Over operating temperature range (TJ = –40°C to 150°C), unless otherwise noted. All typical values at TA = 25°C and VVIN = 12V. External BOM components are listed in the pin description table. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ENA INPUT PIN (Primary-side. All voltages with respect to GNDP) VENA_R Enable pin rising threshold Rising edge 1.425 1.5 1.575 V VENA_F Enable pin falling threshold Falling edge 1.282 1.35 1.418 V IENA Enable Pin Input Current VENA = 5.0V 5 10 µA tENA_LO_RST Minimum period for EN = Low to reset latch off 400 µs tENA_LO_DLY Minimum period required before EN = Low to reset latch off 200 µs PG OPEN-DRAIN OUTPUT PIN (Primary-side. All voltages with respect to GNDP) VPG_L PG output-low saturation voltage Sink Current = 5mA 0.5 V IPG_H PG Leakage current VPG = 5.5V 5 µA PRIMARY-SIDE SOFT START tPG_Delay Deglitch time during soft start between VDD reaches regulation and power good signal (PG) is issued. 2.7 3 3.3 ms Primary-side Control (All voltages with respect to GNDP) fSW Switching frequency VVIN = 12V; VENA = 5V; (VDD- COM)=18V, (COM-VEE)=4V 16.5 MHz tSSTO Primary-side soft-start time-out Timer begins when VIN > UVLOP and ENA = High and reset when Powergood pin indicates Good 32 ms (VDD-COM) OUTPUT VOLTAGE (Secondary-side) VVDD (VDD – COM) output voltage range 15 18 20 V VVDD_REG (VDD – COM) output voltage DC regulation accuracy Secondary-side (VDD – COM) output voltage accuracy at FBVDD, over load, line and temperature range, externally adjust with external resistor divider, within SOA range. -1.45 1.45 % (VDD-COM) REGULATION HYSTERETIC COMPARATOR (Secondary-side) VFBVDD_REF Feedback regulation reference voltage for (VDD – COM) 2.467 2.505 2.533 V VFBVDD_HYST (VDD-COM) hysteresis comparator hysteresis settings. Hysteresis at the FBVDD pin. The value represents peak-to-peak magnitude. Hysteresis Setting 18 20 22 mV (COM-VEE) REGULATION HYSTERETIC COMPARATOR (Secondary-side) VFBVEE_HYST (COM-VEE) hysteresis comparator settings. Hysteresis at the FBVEE pin. The value represents peak-to-peak magnitude. Hysteresis Setting 50 60 70 mV (VDD-COM) UVLOs COMPARATOR (Secondary-side) VVDD_UVLOS_R (VDD – COM) undervoltage lockout rising threshold Voltage from VDD to COM, rising 3.2 3.45 3.7 V VVDD_UVLOS_F (VDD – COM) undervoltage lockout falling threshold Voltage from VDD to COM, falling 3 3.25 3.5 V (VDD-COM) OVLOs COMPARATOR (Secondary-side) VVDD_OVLOS_R (VDD – COM) over-voltage lockout rising threshold Voltage from VDD to COM, rising 22.5 23 23.5 V www.ti.com UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: UCC34141-Q1 ADVANCE INFORMATION

Over operating temperature range (TJ = –40°C to 150°C), unless otherwise noted. All typical values at TA = 25°C and VVIN = 12V. External BOM components are listed in the pin description table. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VVDD_OVLOS_F (VDD – COM) over-voltage lockout falling threshold Voltage from VDD to COM, falling 21.7 22.2 22.7 V (VDD-COM) UVP, UNDER -VOLTAGE PROTECTION COMPARATOR (Secondary-side) VVDD_UVP_R (VDD – COM) under-voltage protection rising threshold, VUVP = VREF × 90% At FBVDD 2.175 2.25 2.35 V VVDD_UVP_HYST (VDD – COM) under-voltage protection hysteresis At FBVDD 22 mV (VDD-COM) OVP, OVER-VOLTAGE PROTECTION COMPARATOR (Secondary-side) VVDD_OVP_R (VDD – COM) over-voltage protection rising threshold, VOVP = VREF ×110% At FBVDD 2.7 2.75 2.825 V VVDD_OVP_HYST (VDD – COM) over-voltage protection hysteresis At FBVDD 23 mV (COM-VEE) Buck-Boost Converter (Secondary Side) VVEE_REG (COM-VEE) regulation accuracy COM-VEE=2V, with 1% feedback resistance accuracy 7.5 % COM-VEE=3V, 4V, 5V, with 1% feedback resistance accuracy 4.5 % COM-VEE=6V, 7V, 8V, with 1% feedback resistance accuracy 6.5 % VVEE_OVLOS_R (COM-VEE) over-voltage lockout rising threshold Voltage from COM to VEE, rising 8.8 9 9.2 V VVEE_OVLOS_F (COM-VEE) over-voltage lockout falling threshold Voltage from COM to VEE, falling 8.4 8.6 8.8 V fSW_VEE Switching frequency of VEE converter VDD-COM=18V, COM-VEE=4V, 3.3uH external inductor 3.2 MHz ILIM Buck boost inductor current limit, out of BSW pin Max current limit without VDD feedforward 0.235 0.261 0.287 A ILIM Buck boost inductor current limit, out of BSW pin VDD-COM=18V 0.127 0.141 0.155 A tVEE_SSTO Timeout threshold to determine if the VEE soft start is succesful 1.3 1.6 2 ms (COM-VEE) UVP, UNDER -VOLTAGE PROTECTION COMPARATOR (Secondary-side) VVEE_UVP_F (COM – VEE) under-voltage protection falling threshold COM-VEE=2V 83 % COM-VEE=5V 90 % COM-VEE=8V 92 % VVEE_UVP_HYST (COM – VEE) under-voltage protection hysteresis COM-VEE=5V 85 mV (COM-VEE) OVP, OVER-VOLTAGE PROTECTION COMPARATOR (Secondary-side) VVEE_OVP_R (COM – VEE) over-voltage protection rising threshold COM-VEE=2V 117 % COM-VEE=5V 110 % COM-VEE=8V 108 % VVEE_OVP_HYST (COM – VEE) over-voltage protection hysteresis COM-VEE=5V 84 mV TSHUTS THERMAL SHUTDOWN COMPARATOR (Secondary-side) TSHUT_S_R Secondary -side over-temperature shutdown rising threshold 150 165 °C TSHUT_S_HYST Secondary-side over-temperature shutdown hysteresis 15 20 °C UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 www.ti.com

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Over operating temperature range (TJ = –40°C to 150°C), unless otherwise noted. All typical values at TA = 25°C and VVIN = 12V. External BOM components are listed in the pin description table. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CMTI (Common Mode Transient Immunity) CMTI Common Mode Transient Immunity Positive COM with respect to GNDP 250 V/ns Negative COM with respect to GNDP -250 V/ns INTEGRATED TRANSFORMER N Transformer effective turns ratio Secondary side to primary side 2.43 (1) See the VVIN_UVLO_R and VVIN_ UVLO_F electrical characteristics for the miminum operational VVIN.

6.7 Safety-Related Certifications

Plan to certify according to DIN EN IEC 60747-17 (VDE 0884-17) Plan to certify under UL 1577 / CSA Component Recognition Program Certificate planned Certificate planned www.ti.com UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: UCC34141-Q1 ADVANCE INFORMATION

6.8 Typical Characteristics

As shown in Figure 6-4, Figure 6-5, Figure 6-6, and Figure 6-7, the VDD-COM maximum recommended average power safe operating area (SOA) at each VIN is determined by the lower value of the 3W limit (dotted line) and the corresponding thermal derating curve (solid line) at that input voltage. It is not recommended to operate at an ambient temperatures higher than 125oC. As shown in the Electrical Characteristics table, the typical TSHUT value is 165oC, and minimal TSHUT value is 150oC. The SOA derating curves with TSHUT = 150oC are provided below. The thermal derating power is acquired with the EVM shown in the "Layout" section. The total power requirement in the application can be calculated by the last row of "design requirements"section of the Excel calculator tool, as another design supporting doucment besides this datasheet. VIN = 12V VVDD-COM = 18V VCOM-VEE = 5V No Load on VCOM-VEE Figure 6-1. Efficiency vs. Load on VVDD-COM VIN = 15V VVDD-COM = 18V VCOM-VEE = 5V No Load on VCOM-VEE Figure 6-2. Efficiency vs. Load on VVDD-COM VIN = 17V VVDD-COM = 18V VCOM-VEE = 5V No Load on VCOM-VEE Figure 6-3. Efficiency vs. Load on VVDD-COM A m b i e n t T e m p e r a t u r e (  C ) Maximum Output Power (W) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 0 . 5 1 . 5 2 . 5 3 . 5 8 V 1 2 V + / - 1 V 1 5 V + / - 1 V 1 7 V + / - 1 V 2 0 V VVDD-COM = 20V VCOM-VEE = 5V No Load on VCOM-VEE Figure 6-4. SOA Derating Curves for Pre-regulated Input Voltages UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 www.ti.com

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6.8 Typical Characteristics (continued)

As shown in Figure 6-4, Figure 6-5, Figure 6-6, and Figure 6-7, the VDD-COM maximum recommended average power safe operating area (SOA) at each VIN is determined by the lower value of the 3W limit (dotted line) and the corresponding thermal derating curve (solid line) at that input voltage. It is not recommended to operate at an ambient temperatures higher than 125oC. As shown in the Electrical Characteristics table, the typical TSHUT value is 165oC, and minimal TSHUT value is 150oC. The SOA derating curves with TSHUT = 150oC are provided below. The thermal derating power is acquired with the EVM shown in the "Layout" section. The total power requirement in the application can be calculated by the last row of "design requirements"section of the Excel calculator tool, as another design supporting doucment besides this datasheet. A m b i e n t T e m p e r a t u r e (  C ) Maximum Output Power (W) - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 0 . 5 1 . 5 2 . 5 3 . 5 8 V 1 2 V + / - 1 V 1 5 V + / - 1 V 1 7 V + / - 1 V 2 0 V VVDD-COM = 18V VCOM-VEE = 5V No Load on VCOM-VEE Figure 6-5. SOA Derating Curves for Pre-regulated Input Voltages A m b i e n t T e m p e r a t u r e (  C ) Maximum Output Power (W) - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 0 . 5 1 . 5 2 . 5 8 V 1 2 V + / - 1 V 1 5 V + / - 1 V 1 7 V + / - 1 V 2 0 V VVDD-COM = 15V VCOM-VEE = 4V No Load on VCOM-VEE Figure 6-6. SOA Derating Curves for Pre-regulated Input Voltages A m b i e n t T e m p e r a t u r e (  C ) Maximum Output Power (W) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 0 . 3 0 . 6 0 . 9 1 . 2 1 . 5 1 . 8 2 . 1 2 . 4 2 . 7 8 V 1 2 V + / - 1 V 1 5 V + / - 1 V 1 7 V + / - 1 V 2 0 V VVDD-COM = 15V VCOM-VEE = 7V No Load on VCOM-VEE Figure 6-7. SOA Derating Curves for Pre-regulated Input Voltages VVDD-COM = 18V VCOM-VEE = 5V No Load on VCOM-VEE Figure 6-8. SOA Derating Curves with Wide Input Voltage for Direct Battery Connection www.ti.com UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: UCC34141-Q1 ADVANCE INFORMATION

7 Detailed Description

7.1 Overview

UCC34141-Q1 device is suitable for applications that have limited board space and require more integration. It is also suitable for very-high voltage applications, where power transformers meeting the required isolation specifications are bulky and expensive. The low-profile, low-center of gravity, and low weight provides a higher vibration tolerance than systems using large bulky transformers. The device is easy-to-use and provides flexibility to adjust both positive and negative output voltages as needed when optimizing the gate voltage for maximum efficiency while also protecting gate oxide from over-stress with its tight voltage regulation accuracy. The device integrates a high-efficiency, low-emissions, isolated DC/DC converter for powering the gate drive of SiC or IGBT power devices in traction inverter motor drives, on-board-charger (OBC), server telecom rectifiers, industrial motor drives, or other high voltage DC/DC converters. This DC/DC converter can provide greater than 1.5W of power. The integrated DC/DC converter uses switched mode operation and proprietary circuit techniques to reduce power losses and boost efficiency. Specialized control mechanisms, clocking schemes, and the use of an on- chip transformer provide high efficiency and low radiated emissions. The integrated transformer provides power delivery throughout a wide temperature range while maintaining a 5000V RMS isolation, and an 1202V RMS continuous working voltage. The low isolation capacitance of the transformer provides high CMTI allowing fast dv/dt switching and higher switching frequencies, while emitting less noise. The VIN supply is provided to the primary-side power controller that switches the input stage connected to the integrated transformer. Power is transferred to the secondary-side output stage, and regulated to a level set by the resistor divider connected between the VDD pin and the FBVDD pin with respect to the COMA pin. The output voltage is adjustable with external resistor divider allowing a wide (VDD – COM) range. For optimal performance ensure to maintain the V VIN input voltage within the recommended operating voltage range. Do not exceed the absolute maximum voltage rating to avoid over-stressing the input pins. A fast hysteretic feedback burst control loop monitors (VDD – COM) and ensures the output voltage is kept within the hysteresis with low overshoot and undershoot during load and line transients. The burst control loop enables efficient operation across full load and allows a wide output voltage adjustability throughout the whole VVIN range. The undervoltage lockout (UVLO) protection monitors the input voltage pin, VIN, with hysteresis and input filter ensuring robust system performance under noisy conditions. The overvoltage lockout (OVLO) protection monitors the input voltage pin, VIN, to protect against over-voltage stress by disabling switching and reducing the internal peak voltage. Controlled soft-start timing, provided throughout the full power-up time, limits the peak input inrush current while charging the output capacitor and load. The UCC34141-Q1 can also provide a second output rail, (COM – VEE), that is used as a negative bias for the gate drivers allowing quicker turn-off switching for the IGBTs and also to protect from unwanted turn-on during fast switching of SiC devices. (COM – VEE) has a simple yet fast and efficient bias controller to ensure the positive and negative rails are regulated during the PWM switching. In this case, COM pin is used as the common reference point. The COM pin connects to the source of SiC device or emitter of an IGBT device. A fault protection and powergood status pin provides a mechanism for the host controller to monitor the status of the DC/DC converter and provide proper sequencing of power and PWM control signals to the gate driver. Fault protection includes undervoltage, overvoltage, over-temperature shutdown, and isolated channel communication interface watchdog timer. A typical soft-start ramp-up time is lower than t SSTO, and varies based on input voltage, output voltage, output capacitance, and load. If either output is shorted or over-loaded, the device will not be able to power-up within the tSSTO soft-start time, so the device will shut down and latches off for protection. The latch can be reset by toggling the ENA pin or resetting VVIN. The output load must be kept low until start-up is complete and PG pin becomes low. For succesful soft-start, do not apply a heavy load to (VDD – COM) or (COM – VEE) outputs until the PG pin has indicated power is good. UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 www.ti.com

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TI recommends to use the PG status indicator as a trigger point to start the PWM signal into the gate driver. PG output removes any ambiguity as to when the outputs are ready by providing a robust closed loop indication of when both (VDD –COM) and (COM – VEE) outputs have reached their regulation threshold within ±10%. Do not allow the host to begin PWM to gate driver until PG goes low. This action typically occurs less than t SSTO after VVIN > VVIN_UVLOP and ENA goes high. The PG status output indicates the power is good after soft-start of (VDD – COM) and (COM – VEE) and are within ±10% of regulation. If the host is not monitoring PG , it is recommended that the host disables PWM to gate driver until 50 ms after VVIN > VVIN_UVLOP and ENA goes high in order to allow enough time for power to be good after soft-start of VDD and VEE. Pre-production sample limitation on operating and optimization range for input and output voltages (production devices will have the limitation removed): For VVDD-COM=15V, the input voltage operating range of the pre-production samples is 11V≤VVIN≤20V. The production devices will extend this range to 8V≤VVIN≤20V. The pre-production samples are optimized for 15V ≤VVDD-COM≤18V. More optimizatin for output power capablity will be implemented for 18V<VVDD-COM≤20V in the production devices.

7.2 Functional Block Diagram

2.5V ref VEE BSW FBVEE Buck-boost controller 4.5V ref 90k Ω www.ti.com UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: UCC34141-Q1 ADVANCE INFORMATION

7.3 Feature Description

7.3.1 Power Stage Operation

The UCC34141-Q1 module uses a soft-switching full-bridge converter on the primary-side and a passive full- bridge rectifier on the secondary-side. The small integrated transformer operates with a high switching frequency to reduce the size for integrating into the 16-pin SSOP package. The power stage switching frequency is within 16.5MHz to 27MHz. The power stage switching frequency is determined by input voltage with a feed-forward control as illustrated by the figure below. Adapative spread spectrum modulation, ASSM, is used to reduce emissions. ZVS operation is maintained to reduce switching power losses. The UCC34141-Q1 module creates two regulated outputs. It can be configured as a single output converter, VDD to COM only, or a dual-output converter, VDD to COM and COM to VEE. These two outputs are controlled independently through hysteretic control. Furthermore, the VDD to COM is the main output, and COM to VEE uses the main output as its input to create a second regulated output voltage. Figure 7-1. VDD-COM Switching Frequency with Respect to Input Voltage

7.3.1.1 VDD-COM Voltage Regulation

The VDD output is the main output of the module. The power stage operation is determined by the sensed VDD voltage on FBVDD pin using hysteresis control. The internal reference voltage V FBVDD_REF = 2.5V. The VDD voltage is sensed through a voltage divider R FBVDD_TOP and RFBVDD_BOT. When FBVDD voltage stays below the turn-off threshold, the power stage operates in burst on state, delivers power to the secondary side and makes the VDD output voltage rise. After FBVDD reaches the turn-off threshold, the power stage turns off. VDD Output voltage drops because of the load current. After FBVDD voltage drops below the turn-on threshold, the power stage is turned on again. With the accurate voltage reference and hysteresis control, the VDD output voltage can be regulated with ≤1.5% accuracy. To improve the noise immunity, a small capacitor C FBVDD of 220pF should be added between FBVDD and COMA pins. In an environment with high EM noise, higher feedback decoupling capacitance C FBVDD, and lower feedback resistance RFBVDD_TOP and RFBVDD_BOT values can be selected to further improve the noise immunity of the VDD feedback loop. UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 www.ti.com

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7.3.1.2 COM-VEE Voltage Regulation

An internal buck-boost converter generates the regulated negative VEE voltage. The buck-boost converter operation is determined by the sensed VEE voltage on FBVEE pin. With an internal 90k resistor and a 4.5V reference voltage, VEE voltage can be programed and regulated between -2V to -8V. The buck-boost converter is controlled by an integrated hysteresis voltage feedback loop for COM-to-VEE voltage regulation and an integrated current control loop for cycle-to-cycle current limit. When FBVEE voltage stays below the turn-off threshold, the buck-boost converter operates with peak current mode control. The inductor current increases at the beginning of a switching cycle until it reaches the peak current limit, then returns to zero. In normal operation, the converter operates in boundary conduction mode, but can enter continuous conduction mode during start-up. As the peak current of the buck-boost is limited to less than ILIM, the chosen inductor must have a saturation current above I LIM. As shown in the Electrical Characteristics table, the peak current limit, I LIM, is implemented with a feedforward control based on VDD voltage, so that the maximum inductor current will not exceed I LIM, considering the overshoot due to the control loop delay at different VDD voltages. A higher VDD voltage leads to a bigger overshoot, and thus results in a lower I LIM value for compensation. The recommended inductor selection is between 3.0μH and 10.0μH. The typical switching frequency is fSW_VEE under the conditions listed in the Electrical Characteristics. After the FBVEE voltage reaches the turn-off threshold, the buck-boost converter turns off. After the FBVEE voltage drops below the turn-on threshold due to the load current, the buck-boost converter is turned on again. With the accurate voltage reference and hysteresis control, the VEE output voltage can be regulated with ≤5% accuracy. VDD COM VEE BSW FBVEE Buck-boost controller 4.5V ref 90k Ω VIN GNDP Power stage R FBVEE L BB C VEE COMA C FBVEE Figure 7-4. COM-VEE Voltage Regulation Functional Block Diagram UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 www.ti.com

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V V E E -C O M /L B BV V D D -C O M /L B B ILIM Power stage duty cycle Burst-on Bur s t -off Figure 7-5. Concept of COM-VEE Regulation Scheme www.ti.com UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: UCC34141-Q1 ADVANCE INFORMATION

7.3.1.3 COM-VEE Output Capability

The maximum output current and output power capability of the VEE buck-boost converter at different VDD- COM and COM-VEE voltages are shown in Figure 7-6 and Figure 7-7. It can also be calculated in the Excel calculator tool, as another design supporting doucment besides this datasheet. The power module has two independent output power capablilities: one is of VDD-COM output as shown by the SOA curves in the Typical Characteristics section, and the other one is of COM-VEE output as shown in this section. Excessive output power requirement out of either of the two output power capablity can cause an output undervoltage protection and shutdown of the device. Figure 7-6. Output Current Capablity of VEE buck-boost converter at Different VDD-COM and VEE-COM Voltages Figure 7-7. Output Power Capablity of VEE buck-boost converter at Different VDD-COM and VEE-COM Voltages UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 www.ti.com

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7.3.2 Output Voltage Soft Start

UCC34141-Q1 has soft-start mechanism that ensures a smooth and fast soft-start operation with minimum input inrush current. The output voltage soft-start diagram is shown in the figure below. After input voltage is higher than the VIN_UVLO threshold, and the ENA signal is pulled high, the soft-start sequence starts with a primary duty cycle open loop control. The power stage operates with a fixed burst frequency with an incremental increasing duty cycle starting at 6.5%. The rate of change of the duty cycle is pre-programmed in the part to reduce the input inrush current while building the output voltage VDD. The primary side limits the maximum duty cycle to 62.5% during this phase till the secondary side VDD voltage passes VDD_UVLO before releasing this duty cycle limit. This limit will ensure minimum input current in case the device starts on a short circuit and the VDD is not building up. Once the VDD reaches the regulation range, the duty cycle is no longer determined from the primary side controller but instead VDD hysteretic control is active to tightly regulate the output voltage within the defined hysteresis band. When VDD passes V VDD_UVLO, a FBVEE status check will be performed, and then a single inductor current pulse is generated for BSW pin fault detection. When VDD reaches regulation, the VEE soft start occurs with low peak current. In this way, the charge current of isolated converter can dedicatedly supply VDD cap first before the VEE soft start. The soft start process of VEE voltage has two phases. In phase 1, limited VEE soft start peak current at the beginning reduces the power loss before the soft-start timeout expires, especially when VEE pin is shorted to COM. When V COM-VEE is higher than V VEE_SS (0.5V Typ.), the VEE soft start enters phase 2, and the inductor peak current is increased to a higher value so that the startup time of charging VEE capacitor will show faster ramp rate. For the power good signal generation, when VDD voltage reaches regulation, two timers of t VEE_SSTO and tPG_Delay are started. If VEE does not pass VEE_UVP threshold within t VEE_SSTO period, a fault will be triggered to shut down the part and flag a failed soft start. If no fault is detected up within t PG_Delay period, PG signal will be pulled low to indicate a power good state. If VDD voltage does not reach regulation within tSSTO peroid, a fault will be triggered to shut down the part and flag a failed soft start. To ensure VEE reaches VEE_UVP threshold within t VEE_SSTO period, the sum of the COM-to-VEE output capacitance at gate driver side (C VEE_GD) and at isolated-converter bias side (C VEE_BIAS) should not exceed a maximum allowed value. The maximum allowed value at gate driver side (C VEE_GD) is available in a calculation tool, as another design supporting document besides this datasheet. The equation to determine the maximum allowed capacitor value is shown as below, and is implemented in the calculation tool. In the equation, ILOAD_SS_VEE represents the quiescent current of output load during VEE soft start. C V EE _ G D ≤ t VE E _ SS OT _ mi n V VE E _ SS I VE E _ P ℎ as e 1 − I L O AD _ SS _ V EE + V VE E − V V EE _ SS I V EE _ P ℎ as e 2 − I LO AD _ S S _ VE E − C VE E _ BI AS (1) www.ti.com UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: UCC34141-Q1 ADVANCE INFORMATION

/PG VDD OVP UVP COM-VEE IL V EE_SS =0.5V OVP UVP tPG_Delay tS S _ ti m e _ o u t tVEE_SS_timeout ENA Duty Cycle Limit Duty Cycle V IN V VIN_UVLO V VDD_UVLO Incremental Duty Cycle Control VDD Regulation Control Figure 7-8. Output Voltage Soft-Start Diagram Figure 7-9. VDD-COM Rising Slope Change During Soft Start of the Pre-production Sample Pre-production sample limitation on soft start (production devices will have the limitation removed): For pre-production samples, as shown in Figure 7-9 , a rising slope change during soft start may be observed on the VDD-COM waveform, when the part is enabled by toggling the ENA signal from low to high. This limitation shows no impact to the successful completion of start-up and reaching desired regulation setpoint, as long as the soft-start duration is below the soft-start timeout (t SSTO) and the UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 www.ti.com

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VDD-COM load could be applied after PG signal goes low. Production devices will have the limitation removed. www.ti.com UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: UCC34141-Q1 ADVANCE INFORMATION

7.3.3 ENA and PG

The ENA input pin and PG output pin on the primary-side support both TTL and CMOS logic levels in 5V or 3.3V domain. The active-high enable input (ENA) pin is used to turn-on the isolated DC/DC converter. Either 3.3V or 5V logic rail can be used. The recommended maximum ENA-pin voltage is 5.5V. After ENA pin voltage rises above the enable threshold VENA_R, the power module starts switching, goes through the soft-start process and delivers power to the secondary side. After ENA pin voltage falls below the disable threshold V ENA_F, UCC34141-Q1 is disabled, and the internal power stage stops switching. The ENA pin can also be used to reset the device after it enters the protection safe-state mode. After a detected fault, the protection logic will latch off and place the device into a safe state. To reset the part, the user is required to wait for t EN_LO_DLY after fault, then toggle the ENA-pin voltage below V ENA_F for longer than tEN_LO_RST, then toggle back up to 3.3V or 5V. The device will then exit the latch-off mode and a soft-start sequence will be reinitiated. The ENA pin can also be used to implement a programmable input UVLO by using an external resistor divider between VIN and ENA pins. For the device and application with relatively low input UVLO and relatively high VIN, when there is a slow V IN ramp during start-up, the relatively low transformer turns-ratio will not be able to generate enough power to charge up the output capacitor and will thus fail the start-up. This issue can be solved by adding a resistor divider between VIN, ENA, and GNDP pins to program the ENA signal time and override the internal input UVLO. The V ENA_R rising threshold is set at 1.5V and the V ENA_F falling threshold is set at 1.35V. The programmable input UVLO feature can also be used to sequentially start-up multiple integrated DC/DC modules, by adding delay capacitors between ENA and GNDP pins to program the delay time between each power module. Specifically, the ENA1 signal can enable one module or one grouped modules, while the delayed ENA2 signal from ENA1 can sequentially enable another module or another grouped modules. For the appliation where ENA1 and ENA2 are too far away for the R ENA2 routing, the RC circuitry for ENA1 can be duplicated at the ENA pin of each module to enable sequential startup. If the sequential power up is not needed, multiple modules can share the same resistor divider to program input UVLO threshold. To facilitate the implementation, the recommended resistor and capacitor values are available in a calculation tool, as another design supporting document besides this datasheet. If a single fault event on the resistor divider needs to be considered, e.g. the single bottom resistor is failed open, the risk of exceeding the 7V absolute maximum of ENA pin needs to be mitigated in application level. Two approaches can be applied: one option is adding an external Zener diode on ENA pin; another option is to split the bottom resistance into two resistor components. Figure 7-10. Input UVLO Programming Circuit and Operation Principle UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 www.ti.com

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The active-low power-good ( PG ) pin is an open-drain output that indicates (short) when the module has no fault and the output voltages are within ±10% of the output voltage regulation setpoints. To account for the maximum current sinking capability of the internal pull-down MOSFET < 5mA, a pull-up resistor (> 1k Ω) from PG pin to either a 5V or 3.3V logic rail is recommended. Higher resistance will reduce the quiescent current in normal logic state of PG pin. It is essential to maintain the PG pin voltage below 5.5V without exceeding its recommended operating voltage. There is a voltage drop in the PG signal during start up, due to the parasitic capacitance between the adjacent VIN pin and PG pin. This capacitive coupling generates a pulling currect into the PG pin and therefore leads to a volage drop across the pull-up resistor and thus a voltage drop on PG signal during start up. A 10k Ω pull-up resistor, and a 1 μF decoupling capacitor connecting PG pin and ground are recommended to diminish the voltage drop during start up. Alternatively, available in another device in the device family, the active-high PG-pin polarity setting allows the power-good signal to be grounded during the start up, so a small decoupling capacitor in the range of 0.1μF-1μF can be selected.

7.3.4 Protection Functions

UCC34141-Q1 is equipped with a full feature of protection functions, including input undervoltage lockout, overvoltage lockout, output undervoltage, overvoltage, and over-temperature. The input undervoltage and overvoltage lockout protections have an auto recovery response. All other protections have a latch-off response. After the latch-off-response protections are triggered, the converter enters a latch-off state, and stops switching. The latch is reset by either toggling the ENA pin Off then On, or by lowering the V VIN voltage below the VVIN_UVLO_F threshold, and then above the VVIN_UVLO_R threshold.

7.3.4.1 Input Undervoltage Lockout

The UCC34141-Q1 enters input undervoltage lockout when V VIN voltage becomes lower than the UVLO threshold V VIN_UVLO_F. In UVLO mode, the converter stops switching. After VIN pin voltage falls lower than the VVIN_UVLO_F, UCC34141-Q1 resets all the protections. And then, after the VVIN voltage rises above the UVLO threshold V VIN_UVLO_R, the converter is enabled. Depending on the ENA pin voltage, the converter can start switching, go through the soft-start process, or in the disable mode, waiting for ENA pin voltage becomes high.

7.3.4.2 Input Overvoltage Lockout

The input overvoltage lockout protection is used to protect the UCC34141-Q1 from overvoltage damage. The UCC34141-Q1 also has an auto-recovery response. When the V VIN pin voltage becomes higher than the input overvoltage lockout threshold V VIN_OVLO_R, switching stops and the converter stops sending energy to the secondary side. Once VVIN pin voltage drops below the recovery threshold V VIN_OVLO_F following an overvoltage lockout, depending on the ENA pin voltage status, the converter can either resuming operation, go through the full soft-start process, or in the disabled mode, wait for ENA pin to go high. The input overvoltage lockout does not reset other latch-off protections.

7.3.4.3 Output Undervoltage Protection

The output voltage under voltage protection is based on the FBVDD and FBVEE pin voltages. When the FBVDD pin voltage falls below the UVP threshold V VDD_UVP_F, or the FBVEE pin voltage falls below the UVP threshold VVEE_UVP_F, the undervoltage protection is activated. The UCC34141-Q1 stops switching, and the PG pin becomes high. During soft start, the output voltages rise from zero volts, thus, both FBVDD and FBVEE pin voltages are below the UVP thresholds. The UVP is disabled during the soft start. If the pin voltage cannot reach the UVP recovery thresholds (V VDD_UVP_R, V VEE_UVP_R) after the soft start completes, undervoltage protection is activated, the UCC34141-Q1 stops switching, and the PG pin becomes high. The output undervoltage protection has a latched-off response. After activation, the latch-off state can be cleared by recycling V VIN. Toggling ENA pin can also reset the latch-off state. Refer to ENA and PG section for more details.

7.3.4.4 Output Overvoltage Protection

The UCC34141-Q1 senses the output voltage through FBVDD and FBVEE pins to control the output voltage. To prevent the output voltage from getting too high, damaging the load or UCC34141-Q1 device, the UCC34141-Q1 www.ti.com UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: UCC34141-Q1 ADVANCE INFORMATION

is equipped with the output overvoltage protection. There are two levels of overvoltage protection based on the feedback pin voltage, and the output voltage. During the normal operation, because of load transient, the output voltages can exceed the regulation level. Based on the pin voltages on FBVDD and FBVEE, after the voltage exceeds the threshold, V VDD_OVP_R, or VVEE_OVP_R, the converter stops switching immediately. In rare cases, the voltage divider can malfunction resulting in the wrong output voltage information. In turn, the control loop will regulate the output voltages at a wrong voltage level. For instances like this, the UCC34141-Q1 is also equipped with a fail-safe overvoltage protection. After the VDD-COM or COM-VEE voltage exceeds the overvoltage protection threshold V VDD_OVLOS_R or V VEE_OVLOS_R, the converter shuts down immediately. This fail-safe protection level is meant to protect UCC34141-Q1 rather than the load. The design must specify the voltage feedback divider normal operation at all conditions. The output overvoltage protections have the latch-off response.

7.3.4.5 Over-Temperature Protection

UCC34141-Q1 integrates the primary-side, secondary-side power stages, as well as the isolation transformer. The power loss caused by the power conversion causes the module temperature higher than the ambient temperature. For the safe operation of the power module, the UCC34141-Q1 is equipped with over-temperature protection. Both the primary-side power stage, and the secondary-side power stage temperatures are sensed and compared with the over-temperature protection threshold. If the primary-side power stage temperature becomes higher than T SHUT_P_R, or the secondary-side power stage temperature becomes higher than TSHUT_S_R, the module enters over-temperature protection mode. The module stops switching and the PG pin becomes high. The over-temperature protection has a latched-off response. When the power stage temperature drops below the over-temperature recovery threshold, recycling V VIN, or toggling ENA pin voltage brings the module out of latch-off mode. Depending on ENA pin voltage, the module either resumes switching delivering power to the secondary side, or in the standby mode waiting for ENA pin voltage to go high.

7.3.4.6 BSW Pin Faults Protection

UCC34141-Q1 has protection mechanism against BSW Pin faults during the soft-start period for the COM-VEE buck-boost converter. In the case of BSW pin-open, when VDD voltage passes V VDD_UVLOS_R threshold, the part detects the first inductor current pulse width, which is the current ramp-up period until it hits the peak current limit. If the first inductor current pulse width is higher than the normal pulse width using largest inductance (>2.9 μs), the BSW fault protection will be triggered to disable the buck-boost switching. Then, the device will stop switching after VDD soft start completion. In the case of BSW pin-short to COM or VEE pin, the part detects the inductor current at the end of leading- edge-blank period. If the current is higher than the inductor peak current limit during soft-start, the BSW fault protection will be triggered to disable the buck-boost switching. Then the device will stop switching after VDD soft start completion. The BSW pin faults protections have the latch-off response. UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 www.ti.com

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7.4 Device Functional Modes

Depending on the input and output conditions, ENA pin voltage, as well as the device temperature, the UCC34141-Q1 operates in one of the below operation modes. 1. Disable mode. In this mode, the module is off, waiting for ENA pin to go high to begin operation. 2. Soft-start mode. In this mode, the module starts to deliver power to the secondary side. The primary-side operation duty cycle is raised gradually to reduce the stress to the module. 3. Normal operation mode. In this mode, the module operates normally, delivering power to the secondary side. 4. Protection mode, auto-recovery. In this mode the module is off due to the input UVLO or OVLO protection. After the input voltage fault is cleared, depending on the ENA pin voltage condition, it either becomes disabled mode if the ENA pin voltage is low, or it goes through soft-start mode to the normal operation mode. 5. Protection mode, latched-off. In this mode the part is off due to other protections. The module remains off even the fault causing the protection is cleared. Recycling VVIN operation must ensure the input voltage goes below the analog UVLO falling threshold (VVIN_UVLO_F) first to reset the latch-off state, or the ENA pin is toggled Low (OFF) then High (ON). Table 7-1 lists the supply functional modes for this device. The ENA pin has an internal weak pull-down resistance to ground, but TI does not recommend leaving this pin open. Table 7-1. Device Functional Modes INPUT OUTPUTS OPERATION MODE VVIN ENA FAULT V(VDD – COM) Isolated Output1 V(COM – VEE) Isolated Output2 PG Open Drain VVIN < VVIN_UVLO_R X X OFF OFF HIGH Protection mode, auto- recovery VVIN_UVLO_R < VVIN < VVIN_OVLO_R LOW X OFF OFF HIGH Disable mode VVIN_UVLO_R < VVIN < VVIN_OVLO_R HIGH NO FAULT Regulating at Setpoint Regulating at Setpoint LOW Normal operation VVIN_UVLO_R < VVIN < VVIN_OVLO_R HIGH YES FAULT OFF OFF HIGH Protection mode, latched-off VVIN > VVIN_OVLO_R X X OFF OFF HIGH Protection mode, auto- recovery www.ti.com UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: UCC34141-Q1 ADVANCE INFORMATION

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The UCC34141-Q1 is suitable for applications that have limited board space and desire more integration. This device is also suitable for very high voltage applications, where power transformers meeting the required isolation specifications are bulky and expensive.

8.2 Typical Application

The following figures show the typical application schematics for the UCC34141-Q1 device configurations supplying an isolated load. CVDD_GD CVEE_GD Isolation Barrier ENA VIN VIN GNDP GNDP GNDP GNDP FBVDD FBVEE VEE BSW VDD COM COM COMA PG VIN CIN CVDD RFBVEE VEE LBB VDD COM CFBVDD RFBVDD_BOT RFBVDD_TOP 3.3V Vbias CVEE RPGRENA CENA CFBVEE CPG Figure 8-1. Dual Adjustable Output Configuration UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 www.ti.com

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CFBVDD RFBVDD_BOT RFBVDD_TOP VIN CIN 3.3V Vbias RPGRENA CENA CPG Figure 8-2. Single Adjustable Output Configuration

8.2.1 Design Requirements

Designing with the UCC34141-Q1 is simple. First, choose single output or dual output. Determine the voltage for each output and then set the regulation through feedback resistors. The gate charge of the power device determines the amount of output decoupling capacitance needed at the gate driver input. For dual adjustable output configuration an internal inverting buck-boost converter generates a regulated negative rail for the turn-off supply (VEE). The buck-boost converter is controlled by a peak current mode, hysteretic controller. In normal operation, the converter remains in discontinuous-conduction mode, but can enter continuous-conduction mode during start-up. The converter is controlled internally and requires only a single surface-mount inductor (L BB) and output bypass capacitor (C VDD). Typically, the converter is designed to use a 3.3μH inductor and a 2.2μF output capacitor. A summary table for the recommended values of BOM components is available in a calculation tool, as another design supporting document besides this datasheet.

8.2.2 Detailed Design Procedure

Place ceramic decoupling capacitors as close as possible to the device pins. For the input supply, place the capacitors between pin 4 (VIN) and pin 5 (GNDP). For the isolated output supply, (VDD – COM), place the C VDD capacitor between pin 12 (VDD) and pin 11 (COM). For the negative votage supply, (COM – VEE), place the CVEE capacitor between pin 14 (VEE) and pin 11 (COM). These locations are of particular importance to all the decoupling capacitors because the capacitors supply the transient current associated with the fast switching waveforms of the power drive circuits. Ensure the capacitor dielectric material is compatible with the target application temperature. www.ti.com UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: UCC34141-Q1 ADVANCE INFORMATION

8.2.2.1 VDD-COM Voltage Regulation

The UCC34141-Q1 creates an isolated output VDD-COM as its main output. The power stage operation is determined by sensing the VDD voltage on FBVDD pin using hysteresis control. The internal reference voltage VFBVDD_REF = 2.5V. To determine the values for RFBVDD_TOP with a chosen RFBVDD_BOT, please use the equation R F BV DD _ TO P = V V DD * R F BV DD _ B OT

2.5 V − R F BVD D _ BOT (2)

As an example, to set a VDD value of 20V, a 10k Ω resistor can be chosen as R FBVDD_BOT, and the R FBVDD_TOP can be calculated as R F BV DD _ TO P = 20 V *10 k Ω

2.5 V − 10 kΩ = 70 k Ω (3)

To improve the noise immunity, a small capacitor C FBVDD of 220pF should be added between FBVDD and COMA pins.

8.2.2.2 COM-VEE Voltage Regulation and Single Output Configuration

UCC34141-Q1 can be configured either as a dual output or a single output converter, using the VEE feedback resistor RFBVEE. The table below summarizes the programmable range with different R FBVEE value. The VDD single output mode can be programmed by a R FBVEE value between 300k Ω and 600k Ω. A R FBVEE lower than 300kΩ could trigger VDD & VEE dual output mode, and a R FBVEE higher than 600k Ω could trigger FBVEE pin-open fault. The typical application schematic of single output configuration is shown in Figure 8-2 Table 8-1. RFBVEE Programming RFBVEE 0 - 7kΩ 40kΩ - 160kΩ 300kΩ - 600kΩ >1000kΩ Operation Mode Trigger FBVEE pin-short fault SMD resistor with ±5% tolerance is enough VEE in regulation, VDD & VEE dual output Recommend SMD resistor with ≤ ±1% tolerance for best regulation accuracy. VDD single output Recommend 330 kΩ SMD resistor with ≤±5% tolerance. Trigger FBVEE pin-open fault An internal buck-boost converter generates the regulated negative VEE voltage. The buck-boost converter operation is determined by sensing the VEE voltage on FBVEE pin. With an internal 90k resistor and a 4.5V reference voltage, VEE voltage can be programed and regulated between -2V to -8V. The transfer function between COM-VEE and RFBVEE in dual output mode is R F BVE E = − V VE E *90 kΩ

4.5 V (4)

An example equation to set a VEE regulation value at -5V R F BVE E = − − 5 V *90 k Ω

4.5 V = 100 kΩ (5)

Pre-production sample limitation on RFBVEE (production devices will have the limitation removed): An 110% correction factor needs to be applied to compensate the VEE regulation offset in the pre- production sample, uisng the relationship of RFBVEE_Pre-Production = RFBVEE_Production / 1.1. Taking the above example , to set a VEE regulation value at -5V, the VEE feedback resistor value for the pre-production sample should be 100kΩ/1.1=90.9kΩ. UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 www.ti.com

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8.3 System Examples

The UCC34141-Q1 module is designed to allow a microcontroller host to enable it with the ENA pin for proper system sequencing. The PG output also allows the host to monitor the status of the module. The PG pin goes low when there are no faults. The output voltage is meant to power a gate driver for either IGBT or SiC FET power device. The microcontroller can start sending PWM control to the gate driver after the PG pin goes low to ensure proper sequencing. The system diagrams for the dual-output configuration and single-output configuration are shown below. ISOLATION BARRIOR VEE VDD VIN GNDP CIN VIN ENA PG VDD 400- 800V From Battery 5V/3.3V PG EN VCC Open-Drain To Motor Buck EMITTER/ SOURCE VEE EMITTER/ SOURCE CVDD CVEE PWM Control Microcontroller ISOLATION BARRIOR VCC VDD GNDP VEE GATEPWM Similar Isolated DC - DC + Isolated Gate Driver Block as Above VCC PG_BIAS ON_BIAS 5V/3.3V COMCOM BSW LBB Figure 8-3. Dual Output System Configuration ISOLATION BARRIOR VEE VDD VIN GNDP CIN VIN ENA PG VDD 400- 800V From Battery 5V/3.3V PG EN VCC Open - Drain To Motor Buck EMITTER/ SOURCE EMITTER/ SOURCE CVDD PWM Control Microcontroller ISOLATION BARRIOR VCC VDD GNDP VEE GATEPWM Similar Isolated DC - DC + Isolated Gate Driver Block as Above VCC PG_BIAS ON_BIAS 5V/3.3V COMCOM BSW Figure 8-4. Single Output System Configuration www.ti.com UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: UCC34141-Q1 ADVANCE INFORMATION

8.4 Power Supply Recommendations

The recommended input supply voltage (V VIN) for UCC34141-Q1 is between 5.5V and 20V. To help ensure reliable operation, adequate decoupling capacitors must be located as close to supply pins as possible. Local bypass capacitors must be placed between the VIN and GNDP pins at the input; between VDD and COM, and between COM and VEE at the output. TI recommends low ESR, ceramic surface mount capacitors to provide the recommended capacitance for high frequency decoupling. The input supply must have an appropriate current rating to support output load required by the end application.

8.5 Layout

8.5.1 Layout Guidelines

The UCC34141-Q1 integrated isolated power solution simplifies system design and reduces board area usage. Follow these guidelines for proper PCB layout to achieve optimum performance. A minimum of 4-layer PCB layer stack using 2 ounce copper on external layers is recommended to accomplish a good thermal PCB design. 1. Input capacitors between VIN pin and GNDP pin: a. Place the 0.1µF high frequency bypass capacitor (C3) as close as possible to pins 3, 4 (VIN) and pins 5–8 (GNDP) and on the same side of the PCB as the IC. 0402 ceramic SMD or smaller is a desired size for optimal placement. The self-resonant frequency in a range between 10MHz to 30MHz is most ideal to offer low impedance decoupling for the switching frequency noise of the internal isolated convertor. Do not place any vias between the bypass capacitor and the IC pins so as to force the high frequency current through the capacitor. b. Place the bulk VIN capacitor(s) (C2) as close as possible and parallel to the 0.1µF high frequency bypass capacitor (C3) and on the same side of the PCB as the IC. 2. Output capacitors between VDD pin and COM pin: a. Place the 0.1µF high frequency bypass capacitor (C5) as close as possible to pin 12 (VDD) and pins 10, 11 (COM) and on the same side of the PCB as the IC. 0402 ceramic SMD or smaller is a desired size for optimal placement. The self-resonant frequency in a range between 10MHz to 30MHz is most ideal to offer low impedance decoupling for the switching frequency noise of the internal isolated convertor. Do not place any vias between the bypass capacitor and the IC pins so as to force the high frequency current through the capacitor. b. Place the bulk VDD-COM capacitor (C8) as close as possible and parallel to the 0.1µF high frequency bypass capacitor (C5) and on the same side of the PCB as the IC. 3. Output capacitors between VEE pin and COM pin: a. Place the 2.2µF high frequency bypass capacitor as close as possible to VEE and COM pins. The self-resonant frequency in 3MHz to 4MHz is most ideal to offer low impedance decoupling for the switching frequency noise of the buck-boost converter with the 3.3uH inductor selection. It is possible to put the capacitor on the different side of PCB and use via to connect, in order to reduce the switching loop between the internal low-side MOSFET and the capacitor. In addition, putting the capacitor on different side will also simplify the decoupling capacitor placement of VDD pin and COM pin. 4. Gate driver output capacitors: CVDD_GD and CVEE_GD are reference designators referred to in the Excel calculator tool. CVDD_GD is the capacitor(s) between VDD-COM and CVEE_GD is the capacitor(s) between COM-VEE. CVDD_GD and CVEE_GD are capacitors required by the gate driver IC. a. CVDD_GD and CVEE_GD should be placed next to the gate driver IC for best decoupling and gate driver switching performance. 5. Feedback: a. COMA should be isolated through all PCB layers, from the COM plane. Use one via to make a direct connection to the low-side resistor and filter capacitor from FBVDD pin, same as the low-side filter capacitor from FBVEE pin. b. Place the RFBVDD feedback resistors (R6 and R7) and the decoupling ceramic capacitor (C6) close to the IC . UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 www.ti.com

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c. The top-side feedback resistor should be placed next to the low-side resistor with a short, direct connection between both resistors and single connection to FBVDD pin. The top connection to sense the regulated rail (VDD-COM) should be routed and connected at the VDD bias capacitor remote location near the gate driver pins for best accuracy and best transient response. d. The VEE feedback resistor (R5) should be placed with the decoupling ceramic capacitor (C4) next to FBVEE (pin 15); while the connection to sense the regulated rail (COM-VEE) should be routed and connected at the COM bias capacitor remote location near the gate driver pins for best accuracy and best transient response. e. When using the dual output mode, the buck-boost inductor and a 2.2uF decoupling ceramic capacitor must be populated. They can be place on the opposite side of the IC or on the same layer as IC. f. A layout example is shown in Figure 8-6. Please refer to the user's guide for more details. 6. Thermal Vias: The UCC34141-Q1 internal transformer makes a direct connection to the lead frame. It is therefore critical to provide adequate space and proper heatsinking designed into the PCB as outlined in the steps below. a. TI recommends to connect the VIN, GNDP, VDD, and COM pins to internal ground or power planes through multiple vias. Alternatively, make the polygons connected to these pins as wide as possible. b. Use multiple thermal vias connecting PCB top side GNDP copper to bottom side GNDP copper. If possible, it is recommended to use 2 ounce copper on external top and bottom PCB layers. c. Use multiple thermal vias connecting PCB top side VEE copper to bottom side VEE copper. If possible, it is recommended to use 2 ounce copper on external top and bottom PCB layers. d. Thermal vias connecting top and bottom copper can also connect to internal copper layers for further improved heat extraction. e. Thermal vias should be similar to pattern shown below but apply as many as the copper area will allow. TI recommends to use thermal via with 30mil diameter, 12mil hole size. f. A layout example is shown in Figure 8-7. g. As seen in the thermal Image, there is a point of diminishing return, regarding the number of vias and size of the thermal via array. The thermal image below shows an example with 1.5W in VDD-COM output power, at VVIN = 12V, VVDD-COM = 20V, VCOM-VEE = 4V, and no load on VCOM-VEE. Figure 8-5. Thermal Image 7. Creepage clearance: Avoid routing copper under the UCC34141-Q1 , to maintain the full creepage, clearance and voltage isolation ratings specified in the data sheet. Maintain the clearance width highlighted in red, throughout the entire defined isolation barrier. Keep-out clearance for basic isolation can be 50% www.ti.com UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: UCC34141-Q1 ADVANCE INFORMATION

less than the reinforced isolation requirement (8.2mm). Using 8.2mm provides additional margin. A layout example is shown in Figure 8-8. 8. Gate driver capacitors and feedback routing: a. VDD-COM and VEE-COM gate driver capacitors need to be placed as close to the associated gate driver pins as possible. b. For optimal voltage regulation, the feedback trace from VEE (VEE FB) and VDD (VDD FB) should be as direct as possible so that the voltage feedback is being sensed directly at the VDD and VEE capacitors near the gate driver IC. UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 www.ti.com

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8.5.2 Layout Example

The layout example shown in the following figures is based on the Figure 8-1 design. Figure 8-6. Layout Example of Components Locations Figure 8-7. Layout Example of Thermal Vias www.ti.com UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: UCC34141-Q1 ADVANCE INFORMATION

Figure 8-8. Layout Example of Keep Out Clearance Figure 8-9. UCC34141-Q1 EVM, PCB Top Layer, Assembly UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 www.ti.com

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9 Device and Documentation Support

9.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

9.2 Documentation Support

9.2.1 Related Documentation

For related documentation, see the following:

Texas Instruments, Isolation Glossary

9.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.5 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

9.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (April 2025) to Revision A (August 2025) Page www.ti.com UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: UCC34141-Q1 ADVANCE INFORMATION

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. TI recommends to install the device with JEDEC standard J-STD-020 reflow process. The peak solder temperature should not exceed 260 oC. If manual installation is needed durning testing process, TI recommends to limit the peak temperature not exceeding 260oC. UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 www.ti.com

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11.1 Packaging Information

Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead finish/ Ball material(6) MSL Peak Temp(3) Op Temp (°C) Device Marking(4) (5) PUCC34141QD HARQ1 PREVIEW SSOP DHA 16 -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. www.ti.com UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 ADVANCE INFORMATION Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: UCC34141-Q1

11.2 Tape and Reel Information

Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PUCC34141QDHARQ1 SSOP DHA 16 UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 www.ti.com

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TAPE AND REEL BOX DIMENSIONS Width (mm) W L H Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PUCC34141QDHARQ1 SSOP DHA 16 www.ti.com UCC34141-Q1 SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: UCC34141-Q1 ADVANCE INFORMATION

11.3 Mechanical Data

SLUSFP1A – APRIL 2025 – REVISED AUGUST 2025 www.ti.com

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IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2025, Texas Instruments Incorporated

Product Information

PUCC34141 specifications and overview.

Summary

UCC34141-Q1 Automotive 1.5W, 12V VIN, 25V VOUT, High-Density, > 5kVRMS, Isolated DC/DC Module REVISED AUGUST 2025

Description

UCC34141-Q1 Automotive 1.5W, 12V VIN, 25V VOUT, High-Density, > 5kVRMS, Isolated DC/DC Module REVISED AUGUST 2025

Source title PUCC34141 Datasheet(PDF) - Texas Instruments

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UCC34141-Q1 TI | Alldatasheet

Document overview

Technical content

1 Features

2 Applications

3 Description

11 Mechanical, Packaging, and Orderable

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4 Device Comparison

5 Pin Configuration and Functions

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6 Specifications

6.1 Absolute Maximum Ratings

6.2 ESD Ratings

6.3 Recommended Operating Conditions

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6.4 Thermal Information

16 PINS

6.5 Insulation Specifications

6.5 Insulation Specifications (continued)

5000 VRMS

6.6 Electrical Characteristics

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6.6 Electrical Characteristics (continued)

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6.7 Safety-Related Certifications

6.8 Typical Characteristics

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6.8 Typical Characteristics (continued)

7 Detailed Description

7.1 Overview

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7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Power Stage Operation

7.3.1.1 VDD-COM Voltage Regulation

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7.3.1.2 COM-VEE Voltage Regulation

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7.3.1.3 COM-VEE Output Capability

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7.3.2 Output Voltage Soft Start

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7.3.3 ENA and PG

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7.3.4 Protection Functions

7.3.4.1 Input Undervoltage Lockout

7.3.4.2 Input Overvoltage Lockout

7.3.4.3 Output Undervoltage Protection

7.3.4.4 Output Overvoltage Protection

7.3.4.5 Over-Temperature Protection

7.3.4.6 BSW Pin Faults Protection

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7.4 Device Functional Modes

8 Application and Implementation

8.1 Application Information

8.2 Typical Application

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8.2.1 Design Requirements

8.2.2 Detailed Design Procedure

8.2.2.1 VDD-COM Voltage Regulation

2.5 V − R F BVD D _ BOT (2)

2.5 V − 10 kΩ = 70 k Ω (3)

8.2.2.2 COM-VEE Voltage Regulation and Single Output Configuration

4.5 V (4)

4.5 V = 100 kΩ (5)

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8.3 System Examples

8.4 Power Supply Recommendations

8.5 Layout

8.5.1 Layout Guidelines

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8.5.2 Layout Example

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9 Device and Documentation Support

9.1 Third-Party Products Disclaimer

9.2 Documentation Support