PUCC33410QRAQRQ1

UCC33410-Q1 TI | Alldatasheet

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Technical content

UCC33410-Q1 Ultra-Small, 1.0W, 3.3V, 3kVRMS Isolation, Automotive DC/DC Module

1 Features

• 1.0W Maximum output power
• 4.5V to 5.5V input voltage operation range
• 3.3V, 3.7V regulated selectable output voltage – 3.3V: 300mA available load current
• 0.5% typical load regulation
• 2mV/V typical line regulation
• Robust isolation barrier: – Isolation rating: 3kVRMS – Surge capability: 6.5kVPK – Working voltage: 1159VPK – 200V/ns common mode transient immunity
• Power dense isolated DC/DC module with integrated transformer technology
• Adaptive spread spectrum modulation (SSM)
• Meets CISPR32 Class B emission
• Strong magnetic fields immunity
• Overload and short circuit protection
• Thermal shutdown
• Low inrush current soft-start
• Enable pin with fault reporting mechanism
• Functional Safety-Capable
• Planned Safety-related certifications: – Basic isolation per DIN EN IEC 60747-17 (VDE 0884-17) – 3kVRMS isolation for 1 minute per UL 1577 – UL certification per IEC 62368-1, and IEC 60601-1 end equipment standards – CQC approval per GB4943.1-2022
• AEC-Q100 qualified with the following results: – Device temperature Grade 1: –40°C to 125°C ambient operating temperature
• VSON-12 (4.0mm × 5.00mm) package

2 Applications

• Battery-Management Systems (BMS)
• HEV/EV OBC and DC/DC converter
• Isolated bias for isolated voltage and current sensors
• Isolated bias for digital isolators,
• Isolated bias for isolated RS-485, RS-422 and CAN transceivers

3 Description

UCC33410-Q1 is an automotive qualified DC/DC power module with integrated transformer technology designed to provide 1.0W of isolated output power. It can support an input voltage operation range of 4.5V to 5.5V and regulate 3.3V output voltage with a selectable headroom of 3.7V. UCC33410-Q1 features a proprietary transformer architecture that achieves a 3kVRMS isolation rating, while simultaneously supporting low EMI and excellent load regulation. The UCC33410-Q1 integrates protection features for increased system robustness such as enable pin with fault reporting mechanism, short circuit protection and thermal shutdown. The UCC33410-Q1 comes in a miniaturized, low- profile solution VSON (4.0mm × 5.00mm ) package with 1.00mm height and > 4.1mm creepage and clearance Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) UCC33410-Q1 VSON-FCRLF (12) 4.0mm × 5.00mm (1) For all available packages, see the orderable addendum at the end of the data sheet. EN/FLT GNDP VINP VCC GNDS SEL Isolation Barrier REN/FLT FLT VINP VCC EN CIN1 COUT1 COUT2CIN2 Simplified Application ADVANCE INFORMATION UCC33410-Q1 SLUSFK2 – JUNE 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.

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4 Pin Configuration and Functions

Figure 4-1. VSON-FCRLF12-pin Package (Top View) Table 4-1. Pin Functions PIN TYPE (1) DESCRIPTION NAME NO. EN/FLT 1 I/O Multi-function Enable input pin and fault output pin. Connect to microcontroller through an 18kΩ or greater pull-up resistor. Enable input pin: Forcing EN low disables the device. Pull high to enable normal device functionality. Fault output pin: This pin is pulled low for 200μs to alert that power converter is shutdown due to fault condition VINP 2 P Primary side input supply voltage pin. 2.2nF (CIN1) and 22μF (CIN2) ceramic bypass capacitors placed close to device pins are required between VINP and GNDP pins GNDP G Power ground return connection for VINP. SEL 7 I VCC selection pin. VCC setpoint is 3.3V when SEL is connected to VCC, and 3.7V when SEL is shorted to GNDS VCC 8 P Isolated supply output voltage pin. 2.2nF (COUT1) and 22μF (COUT2) ceramic bypass capacitors placed close to device pins are required between VCC and GNDS pins GNDS G Power ground return connection for VCC. (1) P = Power, G = Ground, I = Input, O = Output www.ti.com UCC33410-Q1 SLUSFK2 – JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: UCC33410-Q1 ADVANCE INFORMATION

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) PIN MIN TYP MAX UNIT VINP to GNDP(3) –0.3 6 V EN/FLT to GNDP –0.3 6 V VCC to GNDS (3) –0.3 6 V SEL to GNDS (3) –0.3 6 V Total VCC output power at TA=25°C, POUT_VCC_MAX (2) 1.1 W Operating junction temperature range, TJ –40 150 °C Storage temperature, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) See the VCC Load Recommended Operating Area section for maximum rated values across temperature and VINP conditions for different VCC output voltage settings. (3) Less than 1ms. Extended time at this voltage can affect lifetime reliability.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002 (1) ±2000 V Charged-device model (CDM), per AEC Q100-011 Section 7.2 ±500 V (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification UCC33410-Q1 SLUSFK2 – JUNE 2024 www.ti.com

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5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) PIN MIN TYP MAX UNIT VVINP Primary-side input voltage to GNDP 4.5 5.5 V VEN/FLT EN/FLT pin voltage to GNDP 0 5.5 V VVCC Secondary-side Isolated output voltage to GNDS 0 3.9 V VSEL SEL pin input voltage to GNDS 0 3.9 V PVCC VCC output power at VINP=5.0V±10%, VCC = 3.3V, TA=25°C - 85°C (1) 1 W PVCC VCC output power at VINP=5.0V±10%, VCC = 3.3V, TA=105°C (1) 0.7 W PVCC VCC output power at VINP=5.0V±10%, VCC = 3.3V, TA=125°C (1) 0.4 W Static CMTI Static Common mode transient immunity rating (dV/dt rate across the isolation barrier) 200 V/ns Dynamic CMTI Dynamic Common mode transient immunity rating (dV/dt rate across the isolation barrier) 200 V/ns TA Ambient temperature –40 125 ℃ TJ Junction temperature –40 150 ℃ (1) See the VCC Load Recommended Operating Area section for maximum rated values across temperature and VINP conditions for different VCC output voltage settings.

5.4 Thermal Information

THERMAL METRIC(1) UNITVSON-FCRLF

12 PINS

RθJA Junction-to-ambient thermal resistance 59.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 7.35 °C/W RθJB Junction-to-board thermal resistance 25.6 °C/W ΨJA Junction-to-ambient characterization parameter 59.6 °C/W ΨJT Junction-to-top characterization parameter 9.3 °C/W ΨJB Junction-to-board characterization parameter 29.2 °C/W (1) The thermal resistances (R) are based on JEDEC board, and the characterization parameters (Ψ) are based on the EVM described in the Layout section. For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. www.ti.com UCC33410-Q1 SLUSFK2 – JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: UCC33410-Q1 ADVANCE INFORMATION

5.5 Insulation Specifications

PARAMETER TEST CONDITIONS VALUE UNIT CLR External clearance (1) Shortest terminal-to-terminal distance through air > 4.1 mm CPG External creepage (1) Shortest terminal-to-terminal distance across the package surface > 4.1 mm DTI Distance through the insulation Minimum internal gap (internal clearance) > 50 µm CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 > 600 V Material group According to IEC 60664-1 I Overvoltage category Rated mains voltage ≤ 300VRMS I-IV Rated mains voltage ≤ 600VRMS I-IV Rated mains voltage ≤ 1000VRMS I-III DIN EN IEC60747-17 (VDE 0884-17) (2) VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 1159 VPK VIOWM Maximum working isolation voltage AC voltage (sine wave) Time dependent dielectric breakdown (TDDB) test 820 VRMS DC voltage 1159 VDC VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60s (qualification) 4243 VPK VTEST = 1.2 × VIOTM , t = 1s (100%) production 5091 VPK VIMP Impulse Voltage (3) Tested in air, 1.2/50µs waveform per IEC 62368-1 5000 VPK VIOSM Maximum surge isolation voltage (4) Tested in oil (qualification test), 1.2/50µs waveform per IEC 62368-1. 6500 VPK qpd Apparent charge (5) Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60s; Vpd(m) = 1.2 × VIORM, tm = 10s ≤ 5 pC Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60s; Vpd(m) = 1.3 × VIORM, tm = 10s ≤ 5 pC Method b1: At routine test (100% production) and preconditioning (type test), Vini = 1.2 x VIOTM, tini = 1s; Vpd(m) = 1.5 × VIORM, tm = 1s ≤ 5 pC CIO Barrier capacitance, input to output (6) VIO = 0.4 sin (2πft), f = 1MHz < 3 pF RIO Isolation resistance, input to output (6) VIO = 500V, TA = 25°C > 1012 Ω VIO = 500V, 100°C ≤ TA ≤ 125°C > 1011 Ω VIO = 500V at TS = 150°C > 109 Ω Pollution degree 2 Climatic category 40/125/21 UL 1577 VISO Withstand isolation voltage Withstand isolation voltage VTEST = VISO , t = 60s (qualification) VTEST = 1.2 × VISO , t=1s (100% production)

3000 VRMS

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed-circuit board are used to help increase these specifications. (2) This coupler is suitable for basic electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits. (3) Testing is carried out in air to determine the surge immunity of the package. (4) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier (5) Apparent charge is electrical discharge caused by a partial discharge (pd). (6) All pins on each side of the barrier tied together creating a two-terminal device UCC33410-Q1 SLUSFK2 – JUNE 2024 www.ti.com

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5.6 Safety-Related Certifications

Plan to certify according to DIN EN IEC 60747-17 (VDE 0884-17) Plan to certify under UL 1577 Component Recognition program Plan to certify according to IEC 62368-1 Plan to certify according to IEC 60601-1 Plan to certify according to GB4943.1-2022 Basic insulation Maximum transient isolation voltage, 4242VPK; Maximum repetitive peak isolation voltage, 1159VPK; Maximum surge isolation voltage, 6500VPK Single protection, 3000VRMS Basic insulation per UL 62368-1- 14 and IEC 62368-1 2nd Ed., 820VRMS maximum working voltage (pollution degree 2, material group I) Basic insulation per UL 60601- 1:14 and IEC 60601-1 d.3+A1,AAMI ES 60601- 1:2005/(R)2012 and A1:2012, C1:2009/(R)2012 and A2:2010/(R)2012 CSA C22.2 No. 60601-1:2014 IEC 60601-1:2012, 250VRMS maximum working voltage,

1 MOPP (Means of patient

protection) Basic insulation , Altitude ≤ 5000m, Tropical Climate, 574VRMS maximum working voltage Certificate number: (planned) Certificate number: (planned) File number: (planned) Certificate number: (planned) Certificate number: (planned)

5.7 Electrical Characteristics

Over operating temperature range (TJ = –40°C to 150°C), VINP = 5.0V, CIN1 = COUT1 = 2.2nF, CIN2 = 10µF, COUT2 = 22µF, SEL connected to VCC, EN/FLT = 5.0V unless otherwise noted. All typical values at VINP=5.0V, TA = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SUPPLY (Primary-side. All voltages with respect to GNDP) IVINP_Q VIN quiescent current,disabled EN/FLT=Low, VINP=5.0V, no load 180 µA IVINP_NL VIN operating current, no load EN/FLT=High; VINP=4.5V-5.5V; VCC=3.3V no load 7 15 mA EN/FLT=High; VINP=4.5V-5.5V; VCC=3.7V no load 7 15 mA IVINP_FL VIN operating current, full load EN/FLT=High; VINP=5.0V; VCC=3.3V, Iout=300mA, TA=25°C 400 mA UVLOP COMPARATOR (Primary-side. All voltages with respect to GNDP) VVINP_U VLO_R VINP under-voltage lockout rising threshold 2.8 2.9 V VVINP_U VLO_F VINP under-voltage lockout falling threshold 2.6 2.7 V VUVLO_H VINP under-voltage lockout hysteresis 0.1 V OVLO COMPARATOR (Primary-side. All voltages with respect to GNDP) VVINP_O VLO_R VINP over-voltage lockout rising threshold 5.77 5.9 V VVINP_O VLO_F VINP over-voltage lockout falling threshold 5.55 5.72 V VVINP_H VINP over-voltage lockout hysteresis 0.05 V Switching Charactarestics fSw DC-DC Converter switching frequency 76 MHz PRIMARY SIDE THERMAL SHUTDOWN TSDP_R Primary-side over-temperature shutdown rising threshold 150 165 ºC TSDP_F Primary-side over-temperature shutdown falling threshold 130 ºC TSDP_H Primary-side over-temperature shutdown hysteresis 20 ºC www.ti.com UCC33410-Q1 SLUSFK2 – JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: UCC33410-Q1 ADVANCE INFORMATION

Over operating temperature range (TJ = –40°C to 150°C), VINP = 5.0V, CIN1 = COUT1 = 2.2nF, CIN2 = 10µF, COUT2 = 22µF, SEL connected to VCC, EN/FLT = 5.0V unless otherwise noted. All typical values at VINP=5.0V, TA = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT EN/FLT PIN VEN_R Enable voltage rising threshold EN/FLT = 0V to 5.0V 2.1 V VEN_F Enable voltage falling threshold EN/FLT = 5.0V to 0V 0.8 V IEN Enable pin input Current EN/FLT = 5.0V 10 µA VFLT EN/FLT pin voltage when faults occur With a minimum 18kohm (10% tolerance) resistor connected to EN/FLT pin 0.5 V tFault EN/FLT pull down interval when faults occur EN/FLT > 0.5V , Fault occur 200 µs VCC OUTPUT VOLTAGE (Secondary-side. All voltages with respect to GNDS) VCC Isolated supply regulated output voltage Isolated supply regulated output voltage accuracy VINP = 4.5V - 5.5V; VCC = 3.3V / 3.7V -4 4 % VCC_Line Vcc DC line regulation VINP = 4.5V - 5.5V; VCC = 3.3V, Iout = 150mA 2 mV/V VINP = 4.5V - 5.5V; VCC = 3.7V, Iout = 150mA 2 mV/V VCC_Loa d Vcc DC load regulation VINP = 5.0V; VCC = 3.3V, Iout = 0 - 303mA 0.5% VINP = 5.0V; VCC = 3.7V, Iout = 0 - 270mA 0.5% VCC_Ripp le Voltage ripple on isolated supply output 20-MHz bandwidth, VINP = 5.0V , VCC = 3.3V, Iout = 300mA, TA=25°C 50 75 mV EFF Efficiency PVCC to PVINP VINP = 5.0V, VCC = 3.3V, Iout = 300mA, TA = 25°C 50 % VCC_Rise VCC rise time from 10% - 90% VINP = 5.0V, VCC = 3.3V, Iout = 70mA 500 µs VINP = 5.0V, VCC = 3.7V, Iout = 70mA 500 µs VCC UVP UNDER -VOLTAGE PROTECTION (Secondary-side. All voltages with respect to GNDS) KVCC_UV P VCC under-voltage protection threshold ratio VUVP = VCC * 90% 90 % VUVP_H VCC under-voltage protection hysteresis VCC =3.3V 52 66 80 mV VUVP_H VCC under-voltage protection hysteresis VCC =3.7V 73 93 112 mV VCC OVP OVER -VOLTAGE PROTECTION (Secondary-side. All voltages with respect to GNDS) VVCC_OV P_R VCC over-voltage protection rising threshold VCC = 3.3V 3.75 3.8 V VVCC_OV P_H VCC over-voltage protection hysterisis VCC = 3.3V 0.1 V VVCC_OV P_R VCC over-voltage protection rising threshold VCC = 3.7V 4.2 4.25 V VVCC_OV P_H VCC over-voltage protection hysterisis VCC = 3.7V 0.1 V SECONDARY SIDE THERMAL SHUTDOWN TSDS_R Secondary-side over-temperature shutdown rising threshold 150 165 ºC TSDS_F Secondary-side over-temperature shutdown falling threshold 130 ºC TSDS_H Secondary-side over-temperature shutdown hysteresis 20 ºC UCC33410-Q1 SLUSFK2 – JUNE 2024 www.ti.com

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5.8 External BOM Components

Over recommended conditions COMPONENT NOTES MIN TYP MAX UNIT CIN1 VINP first decoupling capacitor 2.2 nF CIN2 VINP second decouling capacitor 10 22 µF COUT1 VCC first decoupling capacitor 2.2 nF COUT2 VCC second decoupling capacitor 10 22 µF www.ti.com UCC33410-Q1 SLUSFK2 – JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: UCC33410-Q1 ADVANCE INFORMATION

6 Detailed Description

6.1 Overview

The UCC33410-Q1 device integrates a high-efficiency, low-emissions isolated DC/DC converter. Requiring minimum passive componenets to form a completely functional DC/DC power module, the device can deliver a maxiumum power of 1.0W across a 3kVRMS basic isolation barrier over a wide range of operating temperatures in a low profile , high power density VSON - 12-pin package. The easy-to-use feature, low profile and high power density promotes this device for size limited, cost sensitive systems with a minimum design effort replacing bulky and expensive transformer based designs. The integrated DC/DC converter uses switched mode operation and proprietary circuit techniques to reduce power losses and boost efficiency across all loading conditions. Specialized control mechanisms, clocking schemes, and the use of an on-chip transformer provide high efficiency and low radiated emissions. The VINP supply is provided to the primary power controller that switches the power stage connected to the integrated transformer. Power is transferred to the secondary side, rectified, and regulated using a fast hysteritic burst mode control scheme that monitors VCC and ensures it is kept within the hysterisis band under normal and transient loading events while maintaining efficient operation across all loading conditions. The VCC is regulated to 3.3V or 3.7V by SEL pin connection to have enough headrome for a post regulator LDO for tighter regulation or lower output ripple requirement applications . The device has an enable pin to turn the device on or off depending on the system requirement. Pulling enable pin low will reduce the quiscent current significantly if the system wants to operate in a low power conumption mode. The enable pin can also be used as a fault reporting pin, when connected to 18kΩ, the pin will be pulled low for 200μs for any fault shutdown of the device. The device has a soft-start mechanism for a smooth and fast VCC ramp up with minimum input inrush current to avoid oversizing front-end power supplies powering the device's input.

6.2 Functional Block Diagram

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6.3 Feature Description

6.3.1 Enable and Disable

Forcing EN/FLT pin low disables the device, which greatly reduces the VINP power consumption. Pull the EN/FLT pin high to enable normal device functionality. The EN/FLT pin has a weak internal pull-down resistor so it is not recommended to leave this pin floating in noisy systems.

6.3.2 Output Voltage Soft-Start and Steady-State Regulation

The UCC33410-Q1 has soft-start mechanism that ensures a smooth and fast soft-start operation with minimum input inrush current. The output voltage Soft-Start diagram is shown in Figure 6-1. After VINP > V VINP_UVLO_R and EN/FLT is pulled high, the soft-start sequence starts with a primary duty cycle open loop control. The power stage operates with a fixed burst frequency with an incremental increasing duty cycle starting at 6.5% . The rate of change of the duty cycle is pre-programmed in the part to reduce the input inrush current while building the output voltage VCC. The primary side limits the maximum duty cycle during this phase till the secondary side VCC voltage passes a certain threshold before releasing this duty cycle limit. This limit will ensure minimum input current in case the device starts on a short circuit and the VCC is not building up. Once the VCC reaches the regulation range, the duty cycle is no longer determined from the primary side controller but instead VCC hysteritic control is active to tightly regulate the output voltage within the defined hysterisis bands to reduce the output voltage ripple. The soft-start time will vary depending on the output capacitors and loading conditions. During VCC regulation state, the burst frequency will change according to the output capacitors and loading conditions. The burst frequency will be highest at higher loading conditions and lowest at light loading conditions by which light load efficiency improvments can be achieved. VCC VCC Regulation Control EN/FLT Duty Cycle VINP D = 6.5% D = 12.5% Incremental Duty Cycle Control VINP_UVLO D = 87.5% Duty Cycle Limit Figure 6-1. Output Voltage Soft-Start Diagram www.ti.com UCC33410-Q1 SLUSFK2 – JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: UCC33410-Q1 ADVANCE INFORMATION

6.3.3 Protection Features

The UCC33410-Q1 is equipped with full feature of protection functions including input under-voltage lockout, input over-voltage lockout, output under-voltage protection and over-temperature protection. In addition, the device has a fault reporting mechanism that can be utilized on the system level to report faulty conditions of the device that caused a shutdown. Under certain faulty conditions the device will shutdown and attempt an auto-restart after defined duration.

6.3.3.1 Input Under-voltage and Over-Voltage Lockout

The UCC33410-Q1 can operate at input voltage range from 4.5V to 5.5V. If the VINP < V VINP_UVLO_F or VINP > VVINP_OVLO_R conditions occured, the converter will stop switching and part will shutdown. Once the VINP gets back in normal operation range , VINP > V VINP_UVLO_R or VINP < V VINP_OVLO_F. The part will resume switching immediately without waiting for the auto-restart timer.

6.3.3.2 Output Under-Voltage Protection

The UCC33410-Q1 has under voltage protection feature to protect the part when overload condition occurs . If an overload or a short circuit occurs at VCC such that VCC < 0.9 ×VCC condition occurs, the converter will go into the duty cycle limit mode as in the soft-start operation then will shutdown after a certain deglitch time. The deglitch time is added to accommodate for any instantaneous overloading or short circuit conditions that might be removed quickly and normal operation can resume. Once the part shuts down, the part will attempt an auto-restart after 160ms. If the fault condition remains, the part will shutdown again and attempt another auto-restart.

6.3.3.3 Output Over-Voltage Protection

The UCC33410-Q1 has over voltage protection feature to protect the load against over-voltage conditions . If an over-voltage , the converter will go into the duty cycle limit mode as in the soft-start operation then will shutdown after a certain deglitch time. Once the part shuts down, the part will attempt an auto-restart after 160ms. If the fault condition remains, the part will shutdown again and attempt another auto-restart. UCC33410-Q1 SLUSFK2 – JUNE 2024 www.ti.com

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6.3.3.4 Over-Temperature Protection

The UCC33410-Q1 integrates the primary-side, secondary-side power stages, as well as the isolation transformer. The power loss caused by the power conversion causes the module temperature higher than the ambient temperature. To ensure the safe operation of the power module, the device is equipped with over- temperature protection. Both the primary-side power stage, and the secondary-side power stage temperatures are sensed and compared with the over-temperature protection threshold. If the primary-side power stage temperature becomes higher TSD P_R, or the secondary-side power stage temperature becomes higher than TSDS_R , the module enters over-temperature protection mode. The module stops switching after a defined deglitch time, report the fault and attempt an auto-restart after 160ms.

6.3.3.5 Fault Reporting and Auto-Restart

The UCC33410-Q1 has a fault reporting mechanism that can alert a system level MCU or monitoring circuitry of faulty onditions on the device that resulted in a shutdown. If an input over-voltage , over-temperature or output under voltage protection faults occur. The primary-side controller and fault monitoring system will enable a current source that will sink I Fault current for t Fault duration. If a resistor > 18kΩ is connected between the MCU and the EN/FLT pin, the VFLT will be pulled low for the same tFault duration whenever one of the abovementioned faults occur that resulted in a shutdown of the device as shown in Figure 6-2. If the fault reporting mechanism is not required on the system, the EN/FLT pin can be connected directly to the enable source voltage without the 18kΩ resistor. The device has a auto-restart feature that occur after the device is shutdown only due to when output under- voltage or over-temperature faults occur. After the t Fault time expires, a 160ms timer will start and the part will attemp a new soft-start sequence as shown in Figure 6-3. If the fault has been removed, the VCC will soft-start to regulation successfully. If the fault remains , the part will shutdown again and report the fault. The device can continuously operate safely in hiccup mode as long as the fault occurs. EN/FLT IFault Out-Pin In-Pin MCU VFLT Primary-side controller and fault monitoring Enable/Disable Part VFLT tFault > 18 Kohm Figure 6-2. Fault Reporting Mechanism EN/FLT Operation Status Auto-Restart Fault Normal Regulation Fault Report / Shut Down 200uS 160mS Figure 6-3. Auto-restart operation www.ti.com UCC33410-Q1 SLUSFK2 – JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: UCC33410-Q1 ADVANCE INFORMATION

6.3.4 VCC Output Voltage Selection

The UCC33410-Q1 can program the VCC voltage accoring to the SEL pin connection. The SEL pin voltage is monitored during soft-start sequence. The output voltage is then programmed to 3.3V with SEL = VCC or 3.7V with SEL = GNDS. Note that after this initial monitoring, the SEL pin no longer affects the VCC output level. In order to change the output mode selection, either the EN/FLT pin must be toggled or the VINP power supply must be cycled off and back on.

6.3.5 VCC Load Recommended Operating Area

Figure 6-4 depicts the device VCC regulation behavior across the output load range, including when the output is overloaded. For proper device operation, ensure that the device VCC output load does not exceed the maximum output current I OUT_MAX. The value for I OUT_MAX over different temperature and V INP conditions are shown from "TBD". If the UCC33410-Q1 is loaded beyond the recommended operating area, the VCC will drop and once it goes below the VCC_UVP threshold, the part enters a power limiting mode to avoid stressing the device till power stage stop switching and shutdown. VCC_SET VCC Recommended Operating Area IOUT_MAX IOUT Power Limit VCC_UVP Figure 6-4. VCC Load Recommended Operating Area Description

6.3.6 Electromagnetic Compatibility (EMC) Considerations

UCC33410-Q1 devices use spread spectrum modulation algorithm for the internal oscillator and advanced internal layout scheme to minimize radiated emissions at the system level. Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge (ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances are regulated by international standards such as IEC 61000-4-x , CISPR 32 and CISPR-25. Although system- level performance and reliability depends, to a large extent, on the application board design and layout, the device incorporates many chip-level design improvements for overall system robustness. UCC33410-Q1 SLUSFK2 – JUNE 2024 www.ti.com

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6.4 Device Functional Modes

Table 6-1 lists the supply functional modes for this device. Table 6-1. Device Functional Modes INPUTS Isolated Supply Output Voltage (VCC) Setpoint EN/FLT SEL HIGH Shorted to VCC 3.3V HIGH Shorted to GNDS 3.7V Low x 0V OPEN(1) OPEN(1) UNSUPPORTED (1) The SEL and EN/FLT pins has an internal weak pull-down resistance to ground, but leaving this pin open is not recommended.

6.5 Pre-Production Samples Operating Limits

UCC33410-Q1 pre-production samples have the following operating limits. Production devices will have these limitations removed. 1. For ambient operating temperature < 0°C, the following sequence is required to allow the device reach regulation point during start-up. EN/FLT pin required to be high (VEN/FLT > VEN_R ) before applying input voltage VINP to the device. This can be achieved by connecting EN/FLT pin after the 18kΩ resistor directly to the VINP pin and applying VINP with rise time > 6ms on the device. 2. For ambient operating temperature < 0°C, the following protection features; short-circuit, UVP and OVP protections of VCC output are disabled. Fault reporting and auto-restart features due to these faults will be disabled as well. If the part shuts down as a result of fault condition, the part will require to follow the same condition in step 1 above to restart and reach regulation. This require to recycle VINP by falling below VVINP_UVLO_F and then rising above VVINP_UVLO_R with the same > 6ms rise time. www.ti.com UCC33410-Q1 SLUSFK2 – JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: UCC33410-Q1 ADVANCE INFORMATION

7 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

7.1 Application Information

The UCC33410-Q1 device is suitable for applications that have limited board space and desire more integration. This device is also suitable for very high voltage applications, where power transformers meeting the required isolation specifications are bulky and expensive.

7.2 Typical Application

Typical Application shows the schematic for the UCC33410-Q1 device supplying an isolated load. GNDP VINP SEL Isolation Barrier 18 K EN FLT EN/FLT 2.2nF 22 F GNDP GNDP GNDP GNDS GNDS GNDS GNDS VCC 2.2nF 22 F 3.3V Figure 7-1. Typical Application

7.2.1 Design Requirements

To design using UCC33410-Q1, a few simple design considerations must be evaluated. Table 7-1 shows some recommended values for a typical application. See Section 7.3 and Section 7.4 sections to review other key design considerations for the UCC33410-Q1. Table 7-1. Design Parameters PARAMETER RECOMMENDED VALUE Input supply voltage, VINP 4.5V to 5.5V First Decoupling capacitance between VINP and GNDP 2.2nF, 16V, ± 10%, X7R Second Decoupling capacitance between VINP and GNDP 22µF, 16V, ± 10%, X7R First Decoupling capacitance between VCC and GNDS 2.2nF, 16V, ± 10%, X7R Second Decoupling capacitance between VCC and GNDS 22µF, 16V, ± 10%, X7R EN/FLT pin resistor for fault reporting 18kΩ UCC33410-Q1 SLUSFK2 – JUNE 2024 www.ti.com

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7.2.2 Detailed Design Procedure

The UCC33410-Q1 design procedure is very simple, the device requires two decoupling capacitors connected between VINP and GNDP pins for the input supply, and two decoupling capacitors for the isolated output supply placed between VCC and GNDS pins to form a completely functinoal DC/DC converter. A low ESR, ESL ceramic capacitors are recommended to be connected close to the device pins. It should be noted that the effective burst frequency would be impacted by the selected VCC output capacitor

7.3 Power Supply Recommendations

The recommended input supply voltage (VINP) for the UCC33410-Q1 is between 4.5V and 5.5V. To help ensure reliable operation, adequate decoupling capacitors must be located as close to supply pins as possible. Place local bypass capacitors between the VINP and GNDP pins at the input, and between VCC and GNDS at the isolated output supply. The input supply must have an appropriate current rating to support output load required by the end application.

7.4 Layout

7.4.1 Layout Guidelines

The UCC33410-Q1 integrated isolated power solution simplifies system design and reduces board area usage. Proper PCB layout is important in order to achieve optimum performance. Here is a list of recommendations:

• Place decoupling capacitors as close as possible to the device pins. For the input supply, place 0402 and 0805 ceramic capacitor between pin 2 (VINP) and pins 3, 4, 5 and 6 (GNDP). For the isolated output supply, place 0402 and 0805 ceramaic capacitora between pin 8 (VCC) and pins 9, 10, 11 and 12 (GNDS). This location is of particular importance to the input decoupling capacitor, because this capacitor supplies the transient current associated with the fast switching waveforms of the power drive circuits.
• Because the device does not have a thermal pad for heat-sinking, the device dissipates heat through the respective GND pins. Ensure that enough copper (preferably a connection to the ground plane) is present on all GNDP and GNDS pins for best heat-sinking. Placing vias close to the device pins and away from the high frequency path between the ceramic capacitors and the device pins is essential for better thermal performance.
• If space and layer count allow, it is also recommended to connect the VINP, GNDP, VCC and GNDS pins to internal ground or power planes through multiple vias of adequate size. Alternatively, make traces for these nets as wide as possible to minimize losses.
• Pay close attention to the spacing between primary ground plane (GNDP) and secondary ground plane (GNDS) on the PCB outer layers. The effective creepage and or clearance of the system reduces if the two ground planes have a lower spacing than that of the device package.
• To ensure isolation performance between the primary and secondary side, avoid placing any PCB traces or copper below the UCC33410-Q1 device on the outer copper layers. www.ti.com UCC33410-Q1 SLUSFK2 – JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: UCC33410-Q1 ADVANCE INFORMATION

7.4.2 Layout Example

Figure 7-2. Layout Example UCC33410-Q1 SLUSFK2 – JUNE 2024 www.ti.com

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8 Device and Documentation Support

8.1 Device Support

8.2 Documentation Support

8.2.1 Related Documentation

For related documentation see the following:

• Isolation Glossary

8.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

8.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

8.5 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

8.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

8.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

9 Revision History

June 2024 * Advance Information Release www.ti.com UCC33410-Q1 SLUSFK2 – JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: UCC33410-Q1 ADVANCE INFORMATION

10 Mechanical and Packaging Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. UCC33410-Q1 SLUSFK2 – JUNE 2024 www.ti.com

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www.ti.com PACKAGE OUTLINE C 5.14.94.13.9 1.050.95 2X 1.651.55 12X (0.23) 2X (0.3) VSON-FCRLF - 1.05 mm max heightRAQ0012CPLASTIC SMALL OUTLINE - NO LEAD 4230399/A 01/2024 0.08 C PIN 1 INDEX AREA SEATING PLANEPKGPKG1 6 7 120.1CAB0.05CPIN 1 ID(45X 0.13) 0.1CAB0.05C SCALE 2.500 AB www.ti.com UCC33410-Q1 SLUSFK2 – JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: UCC33410-Q1 ADVANCE INFORMATION

www.ti.com EXAMPLE BOARD LAYOUT 10X (0.65) (R0.05) TYP 0.07 MAXALL AROUND0.07 MINALL AROUND 12X (0.6)6X (0.3) (4.8) VSON-FCRLF - 1.05 mm max heightRAQ0012CPLASTIC SMALL OUTLINE - NO LEAD PKG PKG LAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE: 15X SEE SOLDER MASKDETAIL1 6 7 METAL EDGESOLDER MASKOPENINGEXPOSED METALMETAL UNDERSOLDER MASKSOLDER MASKOPENINGEXPOSEDMETALNON SOLDER MASKDEFINED(PREFERRED)SOLDER MASK DEFINEDSOLDER MASK DETAILS UCC33410-Q1 SLUSFK2 – JUNE 2024 www.ti.com

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www.ti.com EXAMPLE STENCIL DESIGN (4.8)(R0.05) TYP VSON-FCRLF - 1.05 mm max heightRAQ0012CPLASTIC SMALL OUTLINE - NO LEAD 4230399/A 01/2024NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLEBASED ON 0.125 MM THICK STENCILSCALE: 15X PKG PKG1 6 7 www.ti.com UCC33410-Q1 SLUSFK2 – JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: UCC33410-Q1 ADVANCE INFORMATION

www.ti.com 1-Jul-2024 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PUCC33410QRAQRQ1 ACTIVE 3000 TBD Call TI Call TI -40 to 125 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF UCC33410-Q1 : Addendum-Page 1

www.ti.com 1-Jul-2024

• Catalog : UCC33410 NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product Addendum-Page 2

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